diff options
| author | Trilok Soni <tsoni@codeaurora.org> | 2016-01-27 12:43:31 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:21:30 -0700 |
| commit | f028b6979e7896e4b327e16827527ce2fc476514 (patch) | |
| tree | be0e2dcee5f23e763dc05e2f70fe3eb514bbed32 /drivers | |
| parent | 1c851f4668e67637a8c45c47b04a1b654c94d627 (diff) | |
edac: cortex: Add EDAC L1 and L2 error reporting for Kryo2xx Silver CPUs
Kryo2xx Silver CPUs support L1 and L2 cache error reporting. Add
support for the same.
CRs-Fixed: 969563
Change-Id: Ia2c860803169843a227eacebc9869e11673ffc7a
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/edac/cortex_arm64_edac.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/edac/cortex_arm64_edac.c b/drivers/edac/cortex_arm64_edac.c index a07ed5630b37..d134e8822c9d 100644 --- a/drivers/edac/cortex_arm64_edac.c +++ b/drivers/edac/cortex_arm64_edac.c @@ -497,6 +497,7 @@ static void arm64_erp_local_handler(void *info) switch (partnum) { case ARM_CPU_PART_CORTEX_A53: + case ARM_CPU_PART_KRYO2XX_SILVER: ca53_parse_cpumerrsr(errdata); ca53_parse_l2merrsr(errdata); break; @@ -664,6 +665,7 @@ static void check_sbe_event(struct erp_drvdata *drv) spin_lock_irqsave(&local_handler_lock, flags); switch (partnum) { case ARM_CPU_PART_CORTEX_A53: + case ARM_CPU_PART_KRYO2XX_SILVER: ca53_parse_cpumerrsr(&errdata); ca53_parse_l2merrsr(&errdata); break; |