diff options
| author | Feng Tang <feng.tang@intel.com> | 2013-03-12 11:56:45 +0800 |
|---|---|---|
| committer | John Stultz <john.stultz@linaro.org> | 2013-03-15 16:50:26 -0700 |
| commit | c54fdbb2823d96b842d00c548e14dbc0dd37831d (patch) | |
| tree | 1193dec6db8b75b990c0375ac8a55bfd2ffc034c /firmware/WHENCE | |
| parent | 3195ef59cb42cda3aeeb24a7fd2ba1b900c4a3cc (diff) | |
x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3
On some new Intel Atom processors (Penwell and Cloverview), there is
a feature that the TSC won't stop in S3 state, say the TSC value
won't be reset to 0 after resume. This feature makes TSC a more reliable
clocksource and could benefit the timekeeping code during system
suspend/resume cycle, so add a flag for it.
Signed-off-by: Feng Tang <feng.tang@intel.com>
[jstultz: Fix checkpatch warning]
Signed-off-by: John Stultz <john.stultz@linaro.org>
Diffstat (limited to 'firmware/WHENCE')
0 files changed, 0 insertions, 0 deletions