diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2006-06-18 23:06:41 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-18 23:06:41 +0100 |
| commit | 96ce2385dd2817da549910001a69ac0a2762a1b9 (patch) | |
| tree | 18ec36e9e1e8a6b7c19aacb53c256fdb941c4ecd /include/asm-arm/arch-s3c2410 | |
| parent | 66a9b49a370baac75d90b7da9a2445997a8a9438 (diff) | |
[ARM] 3559/1: S3C2442: core and serial port
Patch from Ben Dooks
Core support for the Samsung S3C2442, and the
serial port driver update to allow the serial
port blocks to be used.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-s3c2410')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-clock.h | 6 | ||||
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-gpio.h | 5 | ||||
| -rw-r--r-- | include/asm-arm/arch-s3c2410/uncompress.h | 5 |
3 files changed, 12 insertions, 4 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index 34360706e016..6c92faffe985 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h @@ -114,7 +114,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) #endif /* __ASSEMBLY__ */ -#ifdef CONFIG_CPU_S3C2440 +#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) /* extra registers */ #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) @@ -136,7 +136,9 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) #define S3C2440_CAMDIVN_DVSEN (1<<12) -#endif /* CONFIG_CPU_S3C2440 */ +#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) + +#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ #endif /* __ASM_ARM_REGS_CLOCK */ diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index d2574084697f..5f10334f06bf 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h @@ -450,12 +450,14 @@ #define S3C2410_GPD0_OUTP (0x01 << 0) #define S3C2410_GPD0_VD8 (0x02 << 0) #define S3C2400_GPD0_VFRAME (0x02 << 0) +#define S3C2442_GPD0_nSPICS1 (0x03 << 0) #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) #define S3C2410_GPD1_INP (0x00 << 2) #define S3C2410_GPD1_OUTP (0x01 << 2) #define S3C2410_GPD1_VD9 (0x02 << 2) #define S3C2400_GPD1_VM (0x02 << 2) +#define S3C2442_GPD1_SPICLK1 (0x03 << 2) #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) #define S3C2410_GPD2_INP (0x00 << 4) @@ -858,6 +860,7 @@ #define S3C2410_GPG12_OUTP (0x01 << 24) #define S3C2410_GPG12_EINT20 (0x02 << 24) #define S3C2410_GPG12_XMON (0x03 << 24) +#define S3C2442_GPG12_nSPICS0 (0x03 << 24) #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) #define S3C2410_GPG13_INP (0x00 << 26) @@ -943,6 +946,7 @@ #define S3C2410_GPH9_INP (0x00 << 18) #define S3C2410_GPH9_OUTP (0x01 << 18) #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) +#define S3C2442_GPH9_nSPICS0 (0x03 << 18) #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) #define S3C2410_GPH10_INP (0x00 << 20) @@ -1051,6 +1055,7 @@ #define S3C2410_GSTATUS1_IDMASK (0xffff0000) #define S3C2410_GSTATUS1_2410 (0x32410000) #define S3C2410_GSTATUS1_2440 (0x32440000) +#define S3C2410_GSTATUS1_2442 (0x32440aaa) #define S3C2410_GSTATUS2_WTRESET (1<<2) #define S3C2410_GSTATUS2_OFFRESET (1<<1) diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h index a6f6a0e44afa..bbd9ee1ff75a 100644 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ b/include/asm-arm/arch-s3c2410/uncompress.h @@ -82,7 +82,8 @@ static void putc(int ch) while (1) { level = uart_rd(S3C2410_UFSTAT); - if (cpuid == S3C2410_GSTATUS1_2440) { + if (cpuid == S3C2410_GSTATUS1_2440 || + cpuid == S3C2410_GSTATUS1_2442) { level &= S3C2440_UFSTAT_TXMASK; level >>= S3C2440_UFSTAT_TXSHIFT; } else { @@ -130,7 +131,7 @@ static void arch_decomp_wdog_start(void) { __raw_writel(WDOG_COUNT, S3C2410_WTDAT); __raw_writel(WDOG_COUNT, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); + __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); } #else |