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authorBruce Losure <blosure@americas.sgi.com>2005-09-02 15:16:35 -0500
committerTony Luck <tony.luck@intel.com>2005-09-06 14:16:01 -0700
commit25732ad493b22b7d9f0d250c5a9ad17219f96a47 (patch)
tree6d2c753c248977fdca4b5d423b65d7fbf2f70186 /include/asm-ia64/sn/l1.h
parent4706df3d3c42af802597d82c8b1542c3d52eab23 (diff)
[IA64] Altix patch for fpga reset
1) workaround a h/w reset issue 2) to improve the determination of FPGA-based h/w in the arch/ia64/sn/kernel/tiocx code. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/sn/l1.h')
-rw-r--r--include/asm-ia64/sn/l1.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index 2e5f0aa38889..e3b819110d47 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -35,4 +35,16 @@
#define L1_BRICKTYPE_ATHENA 0x2b /* + */
#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
+/* board type response codes */
+#define L1_BOARDTYPE_IP69 0x0100 /* CA */
+#define L1_BOARDTYPE_IP63 0x0200 /* CB */
+#define L1_BOARDTYPE_BASEIO 0x0300 /* IB */
+#define L1_BOARDTYPE_PCIE2SLOT 0x0400 /* IC */
+#define L1_BOARDTYPE_PCIX3SLOT 0x0500 /* ID */
+#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600 /* IE */
+#define L1_BOARDTYPE_ABACUS 0x0700 /* AB */
+#define L1_BOARDTYPE_DAYTONA 0x0800 /* AD */
+#define L1_BOARDTYPE_INVAL (-1) /* invalid brick type */
+
+
#endif /* _ASM_IA64_SN_L1_H */