diff options
| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-13 09:49:04 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-13 09:49:04 -0700 |
| commit | dcf397f037f52add9945eced57ca300ab6a4413c (patch) | |
| tree | e78767d164589e9097a54bf564b072fb01f80820 /include/asm-sh | |
| parent | 6faf035cf9fdd8283c2b2b2c34b76b5445ec6fc4 (diff) | |
| parent | 68ee0f9c98a42e36f9eab29155b2bb0e7e409ac6 (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (124 commits)
sh: allow building for both r2d boards in same binary.
sh: fix r2d board detection
sh: Discard .exit.text/.exit.data at runtime.
sh: Fix up some section alignments in linker script.
sh: Fix SH-4 DMAC CHCR masking.
sh: Rip out left-over nommu cond syscall cruft.
sh: Make kgdb i-cache flushing less inept.
sh: kgdb section mismatches and tidying.
sh: cleanup struct irqaction initializers.
sh: early_printk tidying.
video: pvr2fb: Add TV (RGB) support to Dreamcast PVR driver.
sh: Conditionalize gUSA support.
sh: Follow gUSA preempt changes in __switch_to().
sh: Tidy up gUSA preempt handling.
sh: __copy_user() optimizations for small copies.
sh: clkfwk: Support multi-level clock propagation.
sh: Fix URAM start address on SH7785.
sh: Use boot_cpu_data for CPU probe.
sh: Support extended mode TLB on SH-X3.
sh: Bump MAX_ACTIVE_REGIONS for SH7785.
...
Diffstat (limited to 'include/asm-sh')
33 files changed, 705 insertions, 270 deletions
diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h index 07f62ec9ff0c..aa558da08471 100644 --- a/include/asm-sh/cacheflush.h +++ b/include/asm-sh/cacheflush.h @@ -1,16 +1,47 @@ #ifndef __ASM_SH_CACHEFLUSH_H #define __ASM_SH_CACHEFLUSH_H + #ifdef __KERNEL__ -#include <linux/mm.h> +#ifdef CONFIG_CACHE_OFF +/* + * Nothing to do when the cache is disabled, initial flush and explicit + * disabling is handled at CPU init time. + * + * See arch/sh/kernel/cpu/init.c:cache_init(). + */ +#define p3_cache_init() do { } while (0) +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_dup_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) +#define flush_dcache_page(page) do { } while (0) +#define flush_icache_range(start, end) do { } while (0) +#define flush_icache_page(vma,pg) do { } while (0) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +#define flush_cache_sigtramp(vaddr) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) +#define __flush_wback_region(start, size) do { (void)(start); } while (0) +#define __flush_purge_region(start, size) do { (void)(start); } while (0) +#define __flush_invalidate_region(start, size) do { (void)(start); } while (0) +#else #include <asm/cpu/cacheflush.h> +/* + * Consistent DMA requires that the __flush_xxx() primitives must be set + * for any of the enabled non-coherent caches (most of the UP CPUs), + * regardless of PIPT or VIPT cache configurations. + */ + /* Flush (write-back only) a region (smaller than a page) */ extern void __flush_wback_region(void *start, int size); /* Flush (write-back & invalidate) a region (smaller than a page) */ extern void __flush_purge_region(void *start, int size); /* Flush (invalidate only) a region (smaller than a page) */ extern void __flush_invalidate_region(void *start, int size); +#endif #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h index ffe08d2813f9..255016fc91f0 100644 --- a/include/asm-sh/cpu-sh3/cache.h +++ b/include/asm-sh/cpu-sh3/cache.h @@ -26,7 +26,9 @@ #define CCR_CACHE_ENABLE CCR_CACHE_CE #define CCR_CACHE_INVALIDATE CCR_CACHE_CF -#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710) +#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7710) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) #define CCR3 0xa40000b4 #define CCR_CACHE_16KB 0x00010000 #define CCR_CACHE_32KB 0x00020000 diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h index 3a66dc458023..54bfece328c2 100644 --- a/include/asm-sh/cpu-sh3/dma.h +++ b/include/asm-sh/cpu-sh3/dma.h @@ -1,7 +1,20 @@ #ifndef __ASM_CPU_SH3_DMA_H #define __ASM_CPU_SH3_DMA_H + +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709) +#define SH_DMAC_BASE 0xa4010020 + +#define DMTE0_IRQ 48 +#define DMTE1_IRQ 49 +#define DMTE2_IRQ 50 +#define DMTE3_IRQ 51 +#define DMTE4_IRQ 76 +#define DMTE5_IRQ 77 + +#else #define SH_DMAC_BASE 0xa4000020 +#endif /* Definitions for the SuperH DMAC */ #define TM_BURST 0x00000020 diff --git a/include/asm-sh/cpu-sh3/gpio.h b/include/asm-sh/cpu-sh3/gpio.h new file mode 100644 index 000000000000..48770c1c7bdf --- /dev/null +++ b/include/asm-sh/cpu-sh3/gpio.h @@ -0,0 +1,66 @@ +/* + * include/asm-sh/cpu-sh3/gpio.h + * + * Copyright (C) 2007 Markus Brunner, Mark Jonas + * + * Addresses for the Pin Function Controller + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef _CPU_SH3_GPIO_H +#define _CPU_SH3_GPIO_H + +#if defined(CONFIG_CPU_SUBTYPE_SH7720) + +/* Control registers */ +#define PORT_PACR 0xA4050100UL +#define PORT_PBCR 0xA4050102UL +#define PORT_PCCR 0xA4050104UL +#define PORT_PDCR 0xA4050106UL +#define PORT_PECR 0xA4050108UL +#define PORT_PFCR 0xA405010AUL +#define PORT_PGCR 0xA405010CUL +#define PORT_PHCR 0xA405010EUL +#define PORT_PJCR 0xA4050110UL +#define PORT_PKCR 0xA4050112UL +#define PORT_PLCR 0xA4050114UL +#define PORT_PMCR 0xA4050116UL +#define PORT_PPCR 0xA4050118UL +#define PORT_PRCR 0xA405011AUL +#define PORT_PSCR 0xA405011CUL +#define PORT_PTCR 0xA405011EUL +#define PORT_PUCR 0xA4050120UL +#define PORT_PVCR 0xA4050122UL + +/* Data registers */ +#define PORT_PADR 0xA4050140UL +/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */ +#define PORT_PBDR 0xA4050142UL +#define PORT_PCDR 0xA4050144UL +#define PORT_PDDR 0xA4050146UL +#define PORT_PEDR 0xA4050148UL +#define PORT_PFDR 0xA405014AUL +#define PORT_PGDR 0xA405014CUL +#define PORT_PHDR 0xA405014EUL +#define PORT_PJDR 0xA4050150UL +#define PORT_PKDR 0xA4050152UL +#define PORT_PLDR 0xA4050154UL +#define PORT_PMDR 0xA4050156UL +#define PORT_PPDR 0xA4050158UL +#define PORT_PRDR 0xA405015AUL +#define PORT_PSDR 0xA405015CUL +#define PORT_PTDR 0xA405015EUL +#define PORT_PUDR 0xA4050160UL +#define PORT_PVDR 0xA4050162UL + +/* Pin Select Registers */ +#define PORT_PSELA 0xA4050124UL +#define PORT_PSELB 0xA4050126UL +#define PORT_PSELC 0xA4050128UL +#define PORT_PSELD 0xA405012AUL + +#endif + +#endif diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h index b20786d42d09..16c2d63b7e39 100644 --- a/include/asm-sh/cpu-sh3/mmu_context.h +++ b/include/asm-sh/cpu-sh3/mmu_context.h @@ -27,12 +27,13 @@ #define TRA 0xffffffd0 #define EXPEVT 0xffffffd4 -#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ - defined(CONFIG_CPU_SUBTYPE_SH7709) || \ +#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7706) || \ - defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7707) || \ + defined(CONFIG_CPU_SUBTYPE_SH7709) || \ + defined(CONFIG_CPU_SUBTYPE_SH7710) || \ defined(CONFIG_CPU_SUBTYPE_SH7712) || \ - defined(CONFIG_CPU_SUBTYPE_SH7710) + defined(CONFIG_CPU_SUBTYPE_SH7720) #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ #else #define INTEVT 0xffffffd8 diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h index b6c2020a2ad3..3880ce047fe0 100644 --- a/include/asm-sh/cpu-sh3/timer.h +++ b/include/asm-sh/cpu-sh3/timer.h @@ -23,11 +23,13 @@ * --------------------------------------------------------------------------- */ -#if !defined(CONFIG_CPU_SUBTYPE_SH7727) +#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ + !defined(CONFIG_CPU_SUBTYPE_SH7727) #define TMU_TOCR 0xfffffe90 /* Byte access */ #endif -#if defined(CONFIG_CPU_SUBTYPE_SH7710) +#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) #define TMU_012_TSTR 0xa412fe92 /* Byte access */ #define TMU0_TCOR 0xa412fe94 /* Long access */ @@ -56,7 +58,8 @@ #define TMU2_TCOR 0xfffffeac /* Long access */ #define TMU2_TCNT 0xfffffeb0 /* Long access */ #define TMU2_TCR 0xfffffeb4 /* Word access */ -#if !defined(CONFIG_CPU_SUBTYPE_SH7727) +#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ + !defined(CONFIG_CPU_SUBTYPE_SH7727) #define TMU2_TCPR2 0xfffffeb8 /* Long access */ #endif #endif diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h index 9d308cbe9b29..18467c574534 100644 --- a/include/asm-sh/cpu-sh3/ubc.h +++ b/include/asm-sh/cpu-sh3/ubc.h @@ -11,7 +11,8 @@ #ifndef __ASM_CPU_SH3_UBC_H #define __ASM_CPU_SH3_UBC_H -#if defined(CONFIG_CPU_SUBTYPE_SH7710) +#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) #define UBC_BARA 0xa4ffffb0 #define UBC_BAMRA 0xa4ffffb4 #define UBC_BBRA 0xa4ffffb8 diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h index 36e26a964765..aaf71b018c28 100644 --- a/include/asm-sh/cpu-sh4/dma.h +++ b/include/asm-sh/cpu-sh4/dma.h @@ -31,7 +31,7 @@ #define TS_32 0x00000030 #define TS_64 0x00000000 -#define CHCR_TS_MASK 0x30 +#define CHCR_TS_MASK 0x70 #define CHCR_TS_SHIFT 4 #define DMAOR_COD 0x00000008 diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h index ff4c5fbbfaf0..979acddc0f8e 100644 --- a/include/asm-sh/cpu-sh4/mmu_context.h +++ b/include/asm-sh/cpu-sh4/mmu_context.h @@ -22,13 +22,21 @@ #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 #define MMU_PAGE_ASSOC_BIT 0x80 -#define MMU_NTLB_ENTRIES 64 /* for 7750 */ +#ifdef CONFIG_X2TLB +#define MMUCR_ME (1 << 7) +#else +#define MMUCR_ME (0) +#endif + #ifdef CONFIG_SH_STORE_QUEUES -#define MMU_CONTROL_INIT 0x05 /* SQMD=0, SV=0, TI=1, AT=1 */ +#define MMUCR_SQMD (1 << 9) #else -#define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */ +#define MMUCR_SQMD (0) #endif +#define MMU_NTLB_ENTRIES 64 +#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME) + #define MMU_ITLB_DATA_ARRAY 0xF3000000 #define MMU_UTLB_DATA_ARRAY 0xF7000000 diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h index 4c75b70b6414..a65b02fd186e 100644 --- a/include/asm-sh/dma.h +++ b/include/asm-sh/dma.h @@ -152,14 +152,9 @@ extern struct dma_info *get_dma_info_by_name(const char *dmac_name); extern int dma_extend(unsigned int chan, unsigned long op, void *param); extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist); -#ifdef CONFIG_SYSFS /* arch/sh/drivers/dma/dma-sysfs.c */ extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *); extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *); -#else -#define dma_create_sysfs_file(channel, info) do { } while (0) -#define dma_remove_sysfs_file(channel, info) do { } while (0) -#endif #ifdef CONFIG_PCI extern int isa_dma_bridge_buggy; diff --git a/include/asm-sh/dreamcast/maple.h b/include/asm-sh/dreamcast/maple.h new file mode 100644 index 000000000000..51f6a87f1f11 --- /dev/null +++ b/include/asm-sh/dreamcast/maple.h @@ -0,0 +1,37 @@ +#ifndef __ASM_MAPLE_H +#define __ASM_MAPLE_H + +#define MAPLE_PORTS 4 +#define MAPLE_PNP_INTERVAL HZ +#define MAPLE_MAXPACKETS 8 +#define MAPLE_DMA_ORDER 14 +#define MAPLE_DMA_SIZE (1 << MAPLE_DMA_ORDER) +#define MAPLE_DMA_PAGES ((MAPLE_DMA_ORDER > PAGE_SHIFT) ? \ + MAPLE_DMA_ORDER - PAGE_SHIFT : 0) + +/* Maple Bus registers */ +#define MAPLE_BASE 0xa05f6c00 +#define MAPLE_DMAADDR (MAPLE_BASE+0x04) +#define MAPLE_TRIGTYPE (MAPLE_BASE+0x10) +#define MAPLE_ENABLE (MAPLE_BASE+0x14) +#define MAPLE_STATE (MAPLE_BASE+0x18) +#define MAPLE_SPEED (MAPLE_BASE+0x80) +#define MAPLE_RESET (MAPLE_BASE+0x8c) + +#define MAPLE_MAGIC 0x6155404f +#define MAPLE_2MBPS 0 +#define MAPLE_TIMEOUT(n) ((n)<<15) + +/* Function codes */ +#define MAPLE_FUNC_CONTROLLER 0x001 +#define MAPLE_FUNC_MEMCARD 0x002 +#define MAPLE_FUNC_LCD 0x004 +#define MAPLE_FUNC_CLOCK 0x008 +#define MAPLE_FUNC_MICROPHONE 0x010 +#define MAPLE_FUNC_ARGUN 0x020 +#define MAPLE_FUNC_KEYBOARD 0x040 +#define MAPLE_FUNC_LIGHTGUN 0x080 +#define MAPLE_FUNC_PURUPURU 0x100 +#define MAPLE_FUNC_MOUSE 0x200 + +#endif /* __ASM_MAPLE_H */ diff --git a/include/asm-sh/gpio.h b/include/asm-sh/gpio.h new file mode 100644 index 000000000000..9bb27e0f11a4 --- /dev/null +++ b/include/asm-sh/gpio.h @@ -0,0 +1,19 @@ +/* + * include/asm-sh/gpio.h + * + * Copyright (C) 2007 Markus Brunner, Mark Jonas + * + * Addresses for the Pin Function Controller + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_SH_GPIO_H +#define __ASM_SH_GPIO_H + +#if defined(CONFIG_CPU_SH3) +#include <asm/cpu/gpio.h> +#endif + +#endif /* __ASM_SH_GPIO_H */ diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h index 4dd8592ca014..342ca55a266a 100644 --- a/include/asm-sh/hd64461.h +++ b/include/asm-sh/hd64461.h @@ -226,6 +226,7 @@ #define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) #define HD64461_IRQBASE OFFCHIP_IRQ_BASE +#define OFFCHIP_IRQ_BASE 64 #define HD64461_IRQ_NUM 16 #define HD64461_IRQ_UART (HD64461_IRQBASE+5) diff --git a/include/asm-sh/heartbeat.h b/include/asm-sh/heartbeat.h new file mode 100644 index 000000000000..724a43ed245e --- /dev/null +++ b/include/asm-sh/heartbeat.h @@ -0,0 +1,17 @@ +#ifndef __ASM_SH_HEARTBEAT_H +#define __ASM_SH_HEARTBEAT_H + +#include <linux/timer.h> + +#define HEARTBEAT_INVERTED (1 << 0) + +struct heartbeat_data { + void __iomem *base; + unsigned char *bit_pos; + unsigned int nr_bits; + struct timer_list timer; + unsigned int regsize; + unsigned long flags; +}; + +#endif /* __ASM_SH_HEARTBEAT_H */ diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 20d42959f52a..cb0b6c9f7020 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h @@ -6,24 +6,6 @@ extern atomic_t irq_err_count; -struct intc2_data { - unsigned short irq; - unsigned char ipr_offset, ipr_shift; - unsigned char msk_offset, msk_shift; - unsigned char priority; -}; - -struct intc2_desc { - unsigned long prio_base; - unsigned long msk_base; - unsigned long mskclr_base; - struct intc2_data *intc2_data; - unsigned int nr_irqs; - struct irq_chip chip; -}; - -void register_intc2_controller(struct intc2_desc *); - struct ipr_data { unsigned char irq; unsigned char ipr_idx; /* Index for the IPR registered */ @@ -41,11 +23,6 @@ struct ipr_desc { void register_ipr_controller(struct ipr_desc *); -/* - * Enable individual interrupt mode for external IPR IRQs. - */ -void __init ipr_irq_enable_irlm(void); - typedef unsigned char intc_enum; struct intc_vect { @@ -54,6 +31,7 @@ struct intc_vect { }; #define INTC_VECT(enum_id, vect) { enum_id, vect } +#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq)) struct intc_prio { intc_enum enum_id; @@ -64,19 +42,25 @@ struct intc_prio { struct intc_group { intc_enum enum_id; - intc_enum *enum_ids; + intc_enum enum_ids[32]; }; -#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } } +#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } } struct intc_mask_reg { unsigned long set_reg, clr_reg, reg_width; intc_enum enum_ids[32]; +#ifdef CONFIG_SMP + unsigned long smp; +#endif }; struct intc_prio_reg { - unsigned long reg, reg_width, field_width; + unsigned long set_reg, clr_reg, reg_width, field_width; intc_enum enum_ids[16]; +#ifdef CONFIG_SMP + unsigned long smp; +#endif }; struct intc_sense_reg { @@ -84,6 +68,12 @@ struct intc_sense_reg { intc_enum enum_ids[16]; }; +#ifdef CONFIG_SMP +#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8) +#else +#define INTC_SMP(stride, nr) +#endif + struct intc_desc { struct intc_vect *vectors; unsigned int nr_vectors; @@ -97,25 +87,28 @@ struct intc_desc { unsigned int nr_prio_regs; struct intc_sense_reg *sense_regs; unsigned int nr_sense_regs; - struct irq_chip chip; + char *name; }; #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ priorities, mask_regs, prio_regs, sense_regs) \ -struct intc_desc symbol = { \ +struct intc_desc symbol __initdata = { \ _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ _INTC_ARRAY(priorities), \ _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ _INTC_ARRAY(sense_regs), \ - .chip.name = chipname, \ + chipname, \ } void __init register_intc_controller(struct intc_desc *desc); +int intc_set_priority(unsigned int irq, unsigned int prio); void __init plat_irq_setup(void); -enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; +enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210, + IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK, + IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; void __init plat_irq_setup_pins(int mode); #endif /* __ASM_SH_HW_IRQ_H */ diff --git a/include/asm-sh/ilsel.h b/include/asm-sh/ilsel.h new file mode 100644 index 000000000000..e3d304b280f6 --- /dev/null +++ b/include/asm-sh/ilsel.h @@ -0,0 +1,45 @@ +#ifndef __ASM_SH_ILSEL_H +#define __ASM_SH_ILSEL_H + +typedef enum { + ILSEL_NONE, + ILSEL_LAN, + ILSEL_USBH_I, + ILSEL_USBH_S, + ILSEL_USBH_V, + ILSEL_RTC, + ILSEL_USBP_I, + ILSEL_USBP_S, + ILSEL_USBP_V, + ILSEL_KEY, + + /* + * ILSEL Aliases - corner cases for interleaved level tables. + * + * Someone thought this was a good idea and less hassle than + * demuxing a shared vector, really. + */ + + /* ILSEL0 and 2 */ + ILSEL_FPGA0, + ILSEL_FPGA1, + ILSEL_EX1, + ILSEL_EX2, + ILSEL_EX3, + ILSEL_EX4, + + /* ILSEL1 and 3 */ + ILSEL_FPGA2 = ILSEL_FPGA0, + ILSEL_FPGA3 = ILSEL_FPGA1, + ILSEL_EX5 = ILSEL_EX1, + ILSEL_EX6 = ILSEL_EX2, + ILSEL_EX7 = ILSEL_EX3, + ILSEL_EX8 = ILSEL_EX4, +} ilsel_source_t; + +/* arch/sh/boards/renesas/x3proto/ilsel.c */ +int ilsel_enable(ilsel_source_t set); +int ilsel_enable_fixed(ilsel_source_t set, unsigned int level); +void ilsel_disable(unsigned int irq); + +#endif /* __ASM_SH_ILSEL_H */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index e6a1877dcb20..1a336cdc75fe 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -135,6 +135,32 @@ void __raw_readsl(unsigned long addr, void *data, int longlen); # define writel(v,a) ({ __raw_writel((v),(a)); mb(); }) #endif +#define __BUILD_MEMORY_STRING(bwlq, type) \ + \ +static inline void writes##bwlq(volatile void __iomem *mem, \ + const void *addr, unsigned int count) \ +{ \ + const volatile type *__addr = addr; \ + \ + while (count--) { \ + __raw_write##bwlq(*__addr, mem); \ + __addr++; \ + } \ +} \ + \ +static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ + unsigned int count) \ +{ \ + volatile type *__addr = addr; \ + \ + while (count--) { \ + *__addr = __raw_read##bwlq(mem); \ + __addr++; \ + } \ +} + +__BUILD_MEMORY_STRING(b, u8) +__BUILD_MEMORY_STRING(w, u16) #define writesl __raw_writesl #define readsl __raw_readsl diff --git a/include/asm-sh/kgdb.h b/include/asm-sh/kgdb.h index 74bd0953e5ce..4bc8cb187d11 100644 --- a/include/asm-sh/kgdb.h +++ b/include/asm-sh/kgdb.h @@ -17,9 +17,6 @@ #define __KGDB_H #include <asm/ptrace.h> -#include <asm/cacheflush.h> - -struct console; /* Same as pt_regs but has vbr in place of syscall_nr */ struct kgdb_regs { @@ -35,10 +32,7 @@ struct kgdb_regs { /* State info */ extern char kgdb_in_gdb_mode; -extern int kgdb_done_init; -extern int kgdb_enabled; extern int kgdb_nofault; /* Ignore bus errors (in gdb mem access) */ -extern int kgdb_halt; /* Execute initial breakpoint at startup */ extern char in_nmi; /* Debounce flag to prevent NMI reentry*/ /* SCI */ @@ -59,6 +53,7 @@ extern kgdb_debug_hook_t *kgdb_debug_hook; extern kgdb_bus_error_hook_t *kgdb_bus_err_hook; /* Console */ +struct console; void kgdb_console_write(struct console *co, const char *s, unsigned count); extern int kgdb_console_setup(struct console *, char *); @@ -69,22 +64,7 @@ extern void longjmp(jmp_buf __jmpb, int __retval); extern int setjmp(jmp_buf __jmpb); /* Forced breakpoint */ -#define breakpoint() \ -do { \ - if (kgdb_enabled) \ - __asm__ __volatile__("trapa #0x3c"); \ -} while (0) - -/* KGDB should be able to flush all kernel text space */ -#if defined(CONFIG_CPU_SH4) -#define kgdb_flush_icache_range(start, end) \ -{ \ - __flush_purge_region((void*)(start), (int)(end) - (int)(start));\ - flush_icache_range((start), (end)); \ -} -#else -#define kgdb_flush_icache_range(start, end) do { } while (0) -#endif +#define breakpoint() __asm__ __volatile__("trapa #0x3c") /* Taken from sh-stub.c of GDB 4.18 */ static const char hexchars[] = "0123456789abcdef"; diff --git a/include/asm-sh/magicpanelr2.h b/include/asm-sh/magicpanelr2.h new file mode 100644 index 000000000000..c644a77ee357 --- /dev/null +++ b/include/asm-sh/magicpanelr2.h @@ -0,0 +1,67 @@ +/* + * include/asm-sh/magicpanelr2.h + * + * Copyright (C) 2007 Markus Brunner, Mark Jonas + * + * I/O addresses and bitmasks for Magic Panel Release 2 board + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_SH_MAGICPANELR2_H +#define __ASM_SH_MAGICPANELR2_H + +#include <asm/gpio.h> + +#define __IO_PREFIX mpr2 +#include <asm/io_generic.h> + + +#define SETBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) | mask, reg) +#define SETBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) | mask, reg) +#define SETBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) | mask, reg) +#define CLRBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) & ~mask, reg) +#define CLRBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) & ~mask, reg) +#define CLRBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) & ~mask, reg) + + +#define PA_LED PORT_PADR /* LED */ + + +/* BSC */ +#define CMNCR 0xA4FD0000UL +#define CS0BCR 0xA4FD0004UL +#define CS2BCR 0xA4FD0008UL +#define CS3BCR 0xA4FD000CUL +#define CS4BCR 0xA4FD0010UL +#define CS5ABCR 0xA4FD0014UL +#define CS5BBCR 0xA4FD0018UL +#define CS6ABCR 0xA4FD001CUL +#define CS6BBCR 0xA4FD0020UL +#define CS0WCR 0xA4FD0024UL +#define CS2WCR 0xA4FD0028UL +#define CS3WCR 0xA4FD002CUL +#define CS4WCR 0xA4FD0030UL +#define CS5AWCR 0xA4FD0034UL +#define CS5BWCR 0xA4FD0038UL +#define CS6AWCR 0xA4FD003CUL +#define CS6BWCR 0xA4FD0040UL + + +/* usb */ + +#define PORT_UTRCTL 0xA405012CUL +#define PORT_UCLKCR_W 0xA40A0008UL + +#define INTC_ICR0 0xA414FEE0UL +#define INTC_ICR1 0xA4140010UL +#define INTC_ICR2 0xA4140012UL + +/* MTD */ + +#define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL +#define MPR2_MTD_KERNEL_SIZE 0x00200000UL + +#endif /* __ASM_SH_MAGICPANELR2_H */ diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h index 6bc9bba10105..cb3d46c59eab 100644 --- a/include/asm-sh/page.h +++ b/include/asm-sh/page.h @@ -70,14 +70,14 @@ extern void clear_page_nommu(void *to); extern void copy_page_nommu(void *to, void *from); #endif -#if defined(CONFIG_MMU) && (defined(CONFIG_CPU_SH4) || \ - defined(CONFIG_SH7705_CACHE_32KB)) +#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \ + (defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)) struct page; extern void clear_user_page(void *to, unsigned long address, struct page *pg); extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg); extern void __clear_user_page(void *to, void *orig_to); extern void __copy_user_page(void *to, void *from, void *orig_to); -#elif defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH3) || !defined(CONFIG_MMU) +#else #define clear_user_page(page, vaddr, pg) clear_page(page) #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) #endif @@ -88,6 +88,7 @@ extern void __copy_user_page(void *to, void *from, void *orig_to); #ifdef CONFIG_X2TLB typedef struct { unsigned long pte_low, pte_high; } pte_t; typedef struct { unsigned long long pgprot; } pgprot_t; +typedef struct { unsigned long long pgd; } pgd_t; #define pte_val(x) \ ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) #define __pte(x) \ @@ -95,12 +96,11 @@ typedef struct { unsigned long long pgprot; } pgprot_t; #else typedef struct { unsigned long pte_low; } pte_t; typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct { unsigned long pgd; } pgd_t; #define pte_val(x) ((x).pte_low) #define __pte(x) ((pte_t) { (x) } ) #endif -typedef struct { unsigned long pgd; } pgd_t; - #define pgd_val(x) ((x).pgd) #define pgprot_val(x) ((x).pgprot) diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h index e3fae12c0e49..cf0dd2b648c2 100644 --- a/include/asm-sh/pgtable.h +++ b/include/asm-sh/pgtable.h @@ -42,13 +42,12 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; /* PGD bits */ #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS) -#define PGDIR_BITS (32 - PGDIR_SHIFT) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* Entries per level */ #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE)) -#define PTRS_PER_PGD (PAGE_SIZE / 4) +#define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) #define FIRST_USER_ADDRESS 0 @@ -100,17 +99,18 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; #define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */ #define _PAGE_DIRTY 0x004 /* D-bit : page changed */ #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */ -#ifndef CONFIG_X2TLB -# define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */ -# define _PAGE_RW 0x020 /* PR0-bit : write access allowed */ -# define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/ -# define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */ -#endif +#define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */ +#define _PAGE_RW 0x020 /* PR0-bit : write access allowed */ +#define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/ +#define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */ #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */ #define _PAGE_PROTNONE 0x200 /* software: if not present */ #define _PAGE_ACCESSED 0x400 /* software: page referenced */ #define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */ +#define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1) +#define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER) + /* Extended mode bits */ #define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */ #define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */ @@ -126,11 +126,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; #define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */ /* Wrapper for extended mode pgprot twiddling */ -#ifdef CONFIG_X2TLB -# define _PAGE_EXT(x) ((unsigned long long)(x) << 32) -#else -# define _PAGE_EXT(x) (0) -#endif +#define _PAGE_EXT(x) ((unsigned long long)(x) << 32) /* software: moves to PTEA.TC (Timing Control) */ #define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */ @@ -146,10 +142,14 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */ /* Mask which drops unused bits from the PTEL value */ -#ifdef CONFIG_CPU_SH3 +#if defined(CONFIG_CPU_SH3) #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \ _PAGE_FILE | _PAGE_SZ1 | \ _PAGE_HW_SHARED) +#elif defined(CONFIG_X2TLB) +/* Get rid of the legacy PR/SZ bits when using extended mode */ +#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | \ + _PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK) #else #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE) #endif @@ -212,27 +212,36 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ - _PAGE_EXT(_PAGE_EXT_USER_READ | \ + _PAGE_EXT(_PAGE_EXT_KERN_READ | \ + _PAGE_EXT_KERN_WRITE | \ + _PAGE_EXT_USER_READ | \ _PAGE_EXT_USER_WRITE)) #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ - _PAGE_EXT(_PAGE_EXT_USER_EXEC | \ + _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \ + _PAGE_EXT_KERN_READ | \ + _PAGE_EXT_USER_EXEC | \ _PAGE_EXT_USER_READ)) #define PAGE_COPY PAGE_EXECREAD #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ - _PAGE_EXT(_PAGE_EXT_USER_READ)) + _PAGE_EXT(_PAGE_EXT_KERN_READ | \ + _PAGE_EXT_USER_READ)) #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ - _PAGE_EXT(_PAGE_EXT_USER_WRITE)) + _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \ + _PAGE_EXT_USER_WRITE)) #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ - _PAGE_EXT(_PAGE_EXT_USER_WRITE | \ + _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \ + _PAGE_EXT_KERN_READ | \ + _PAGE_EXT_KERN_EXEC | \ + _PAGE_EXT_USER_WRITE | \ _PAGE_EXT_USER_READ | \ _PAGE_EXT_USER_EXEC)) @@ -373,11 +382,15 @@ static inline void set_pte(pte_t *ptep, pte_t pte) #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) #define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT))) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) -#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) -#define pte_none(x) (!pte_val(x)) -#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE)) +#define pfn_pte(pfn, prot) \ + __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pfn_pmd(pfn, prot) \ + __pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) + +#define pte_none(x) (!pte_val(x)) +#define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE)) + #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) #define pmd_none(x) (!pmd_val(x)) @@ -392,15 +405,15 @@ static inline void set_pte(pte_t *ptep, pte_t pte) * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -#define pte_not_present(pte) (!(pte_val(pte) & _PAGE_PRESENT)) -#define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY) -#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED) -#define pte_file(pte) (pte_val(pte) & _PAGE_FILE) +#define pte_not_present(pte) (!((pte).pte_low & _PAGE_PRESENT)) +#define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY) +#define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED) +#define pte_file(pte) ((pte).pte_low & _PAGE_FILE) #ifdef CONFIG_X2TLB #define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE) #else -#define pte_write(pte) (pte_val(pte) & _PAGE_RW) +#define pte_write(pte) ((pte).pte_low & _PAGE_RW) #endif #define PTE_BIT_FUNC(h,fn,op) \ @@ -429,17 +442,10 @@ PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED); /* * Macro and implementation to make a page protection as uncachable. */ -#define pgprot_noncached pgprot_noncached +#define pgprot_writecombine(prot) \ + __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE) -static inline pgprot_t pgprot_noncached(pgprot_t _prot) -{ - unsigned long prot = pgprot_val(_prot); - - prot &= ~_PAGE_CACHABLE; - return __pgprot(prot); -} - -#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE) +#define pgprot_noncached pgprot_writecombine /* * Conversion functions: convert a page and protection to a page entry, @@ -451,28 +457,33 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { - set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | - pgprot_val(newprot))); + pte.pte_low &= _PAGE_CHG_MASK; + pte.pte_low |= pgprot_val(newprot); + +#ifdef CONFIG_X2TLB + pte.pte_high |= pgprot_val(newprot) >> 32; +#endif + return pte; } -#define pmd_page_vaddr(pmd) pmd_val(pmd) +#define pmd_page_vaddr(pmd) ((unsigned long)pmd_val(pmd)) #define pmd_page(pmd) (virt_to_page(pmd_val(pmd))) /* to find an entry in a page-table-directory. */ -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) -#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) +#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) /* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) +#define pgd_offset_k(address) pgd_offset(&init_mm, address) /* Find an entry in the third-level page table.. */ -#define pte_index(address) \ - ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) #define pte_offset_kernel(dir, address) \ ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address)) -#define pte_offset_map(dir, address) pte_offset_kernel(dir, address) -#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address) +#define pte_offset_map(dir, address) pte_offset_kernel(dir, address) +#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address) + #define pte_unmap(pte) do { } while (0) #define pte_unmap_nested(pte) do { } while (0) @@ -480,13 +491,14 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) #define pte_ERROR(e) \ printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \ &(e), (e).pte_high, (e).pte_low) +#define pgd_ERROR(e) \ + printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) #else #define pte_ERROR(e) \ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) -#endif - #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) +#endif struct vm_area_struct; extern void update_mmu_cache(struct vm_area_struct * vma, @@ -563,7 +575,8 @@ struct mm_struct; extern unsigned int kobjsize(const void *objp); #endif /* !CONFIG_MMU */ -#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) +#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \ + defined(CONFIG_SH7705_CACHE_32KB)) #define __HAVE_ARCH_PTEP_GET_AND_CLEAR extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); #endif diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index 26d52174f4b4..4f2922a1979c 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -45,7 +45,7 @@ enum cpu_type { CPU_SH7705, CPU_SH7706, CPU_SH7707, CPU_SH7708, CPU_SH7708S, CPU_SH7708R, CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, - CPU_SH7729, + CPU_SH7720, CPU_SH7729, /* SH-4 types */ CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, @@ -73,15 +73,10 @@ struct sh_cpuinfo { unsigned long flags; } __attribute__ ((aligned(SMP_CACHE_BYTES))); -extern struct sh_cpuinfo boot_cpu_data; - -#ifdef CONFIG_SMP extern struct sh_cpuinfo cpu_data[]; +#define boot_cpu_data cpu_data[0] #define current_cpu_data cpu_data[smp_processor_id()] -#else -#define cpu_data (&boot_cpu_data) -#define current_cpu_data boot_cpu_data -#endif +#define raw_current_cpu_data cpu_data[raw_smp_processor_id()] /* * User space process size: 2GB. diff --git a/include/asm-sh/r7780rp.h b/include/asm-sh/r7780rp.h index 4083b5949928..de37f933aa42 100644 --- a/include/asm-sh/r7780rp.h +++ b/include/asm-sh/r7780rp.h @@ -65,24 +65,6 @@ #define PA_PMR (PA_BCR+0x0900) /* */ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ - -#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */ -#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */ -#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */ -#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */ -#define IRQ_TP 2 /* Touch Panel IRQ */ -#define IRQ_SCI1 3 /* SCI1 IRQ */ -#define IRQ_SCI0 4 /* SCI0 IRQ */ -#define IRQ_2SERIAL 5 /* Serial IRQ */ -#define IRQ_RTC 6 /* RTC A / B IRQ */ -#define IRQ_EXTENTION6 7 /* EXT6n IRQ */ -#define IRQ_EXTENTION5 8 /* EXT5n IRQ */ -#define IRQ_EXTENTION4 9 /* EXT4n IRQ */ -#define IRQ_EXTENTION2 10 /* EXT2n IRQ */ -#define IRQ_EXTENTION1 11 /* EXT1n IRQ */ -#define IRQ_ONETH 13 /* On board Ethernet IRQ */ -#define IRQ_PSW 14 /* Push Switch IRQ */ - #define IVDR_CK_ON 8 /* iVDR Clock ON */ #elif defined(CONFIG_SH_R7780RP) @@ -203,11 +185,24 @@ #define PA_MMSR (PA_BCR+0x0400) #define IVDR_CK_ON 4 /* iVDR Clock ON */ +#endif +#define HL_FPGA_IRQ_BASE 200 +#define HL_NR_IRL 15 + +#define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0) +#define IRQ_CF (HL_FPGA_IRQ_BASE + 1) +#ifndef IRQ_PSW +#define IRQ_PSW (HL_FPGA_IRQ_BASE + 2) #endif +#define IRQ_EXT1 (HL_FPGA_IRQ_BASE + 3) +#define IRQ_EXT4 (HL_FPGA_IRQ_BASE + 4) void make_r7780rp_irq(unsigned int irq); -void highlander_init_irq(void); + +unsigned char *highlander_init_irq_r7780mp(void); +unsigned char *highlander_init_irq_r7780rp(void); +unsigned char *highlander_init_irq_r7785rp(void); #define __IO_PREFIX r7780rp #include <asm/io_generic.h> diff --git a/include/asm-sh/rtc.h b/include/asm-sh/rtc.h index 91aacc96151b..858da99d37e0 100644 --- a/include/asm-sh/rtc.h +++ b/include/asm-sh/rtc.h @@ -5,4 +5,10 @@ extern void (*board_time_init)(void); extern void (*rtc_sh_get_time)(struct timespec *); extern int (*rtc_sh_set_time)(const time_t); +#define RTC_CAP_4_DIGIT_YEAR (1 << 0) + +struct sh_rtc_platform_info { + unsigned long capabilities; +}; + #endif /* _ASM_RTC_H */ diff --git a/include/asm-sh/rts7751r2d.h b/include/asm-sh/rts7751r2d.h index 5d7800aa31b5..83b9c111f171 100644 --- a/include/asm-sh/rts7751r2d.h +++ b/include/asm-sh/rts7751r2d.h @@ -9,7 +9,7 @@ * Renesas Technology Sales RTS7751R2D support */ -/* Box specific addresses. */ +/* Board specific addresses. */ #define PA_BCR 0xa4000000 /* FPGA */ #define PA_IRLMON 0xa4000002 /* Interrupt Status control */ @@ -20,19 +20,19 @@ #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */ #define PA_PCICD 0xa400000e /* PCI Extention detect control */ #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */ -#if defined(CONFIG_RTS7751R2D_REV11) -#define PA_AXRST 0xa4000022 /* AX_LAN Reset control */ -#define PA_CFRST 0xa4000024 /* CF Reset control */ -#define PA_ADMRTS 0xa4000026 /* SD Reset control */ -#define PA_EXTRST 0xa4000028 /* Extention Reset control */ -#define PA_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */ -#else -#define PA_CFRST 0xa4000022 /* CF Reset control */ -#define PA_ADMRTS 0xa4000024 /* SD Reset control */ -#define PA_EXTRST 0xa4000026 /* Extention Reset control */ -#define PA_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */ -#define PA_KEYCTLCLR 0xa400002a /* Key Interrupt clear */ -#endif + +#define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */ +#define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */ +#define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */ +#define PA_R2D1_EXTRST 0xa4000028 /* Extention Reset control */ +#define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */ + +#define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */ +#define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */ +#define PA_R2DPLUS_EXTRST 0xa4000026 /* Extention Reset control */ +#define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */ +#define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */ + #define PA_POWOFF 0xa4000030 /* Board Power OFF control */ #define PA_VERREG 0xa4000032 /* FPGA Version Register */ #define PA_INPORT 0xa4000034 /* KEY Input Port control */ @@ -46,27 +46,22 @@ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ -#if defined(CONFIG_RTS7751R2D_REV11) -#define IRQ_PCIETH 0 /* PCI Ethernet IRQ */ -#define IRQ_CFCARD 1 /* CF Card IRQ */ -#define IRQ_CFINST 2 /* CF Card Insert IRQ */ -#define IRQ_PCMCIA 3 /* PCMCIA IRQ */ -#define IRQ_VOYAGER 4 /* VOYAGER IRQ */ -#define IRQ_ONETH 5 /* On board Ethernet IRQ */ -#else -#define IRQ_KEYIN 0 /* Key Input IRQ */ -#define IRQ_PCIETH 1 /* PCI Ethernet IRQ */ -#define IRQ_CFCARD 2 /* CF Card IRQ */ -#define IRQ_CFINST 3 /* CF Card Insert IRQ */ -#define IRQ_PCMCIA 4 /* PCMCIA IRQ */ -#define IRQ_VOYAGER 5 /* VOYAGER IRQ */ -#endif -#define IRQ_RTCALM 6 /* RTC Alarm IRQ */ -#define IRQ_RTCTIME 7 /* RTC Timer IRQ */ -#define IRQ_SDCARD 8 /* SD Card IRQ */ -#define IRQ_PCISLOT1 9 /* PCI Slot #1 IRQ */ -#define IRQ_PCISLOT2 10 /* PCI Slot #2 IRQ */ -#define IRQ_EXTENTION 11 /* EXTn IRQ */ +#define R2D_FPGA_IRQ_BASE 100 + +#define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0) +#define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1) +#define IRQ_TP (R2D_FPGA_IRQ_BASE + 2) +#define IRQ_RTC_T (R2D_FPGA_IRQ_BASE + 3) +#define IRQ_RTC_A (R2D_FPGA_IRQ_BASE + 4) +#define IRQ_SDCARD (R2D_FPGA_IRQ_BASE + 5) +#define IRQ_CF_CD (R2D_FPGA_IRQ_BASE + 6) +#define IRQ_CF_IDE (R2D_FPGA_IRQ_BASE + 7) +#define IRQ_AX88796 (R2D_FPGA_IRQ_BASE + 8) +#define IRQ_KEY (R2D_FPGA_IRQ_BASE + 9) +#define IRQ_PCI_INTA (R2D_FPGA_IRQ_BASE + 10) +#define IRQ_PCI_INTB (R2D_FPGA_IRQ_BASE + 11) +#define IRQ_PCI_INTC (R2D_FPGA_IRQ_BASE + 12) +#define IRQ_PCI_INTD (R2D_FPGA_IRQ_BASE + 13) /* arch/sh/boards/renesas/rts7751r2d/irq.c */ void init_rts7751r2d_IRQ(void); diff --git a/include/asm-sh/sections.h b/include/asm-sh/sections.h index 2a696b8ee4f5..bd9cbc967c2a 100644 --- a/include/asm-sh/sections.h +++ b/include/asm-sh/sections.h @@ -4,6 +4,7 @@ #include <asm-generic/sections.h> extern long __machvec_start, __machvec_end; +extern char _ebss[]; #endif /* __ASM_SH_SECTIONS_H */ diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h index 4ff1eb900301..c39c785bba94 100644 --- a/include/asm-sh/sh03/io.h +++ b/include/asm-sh/sh03/io.h @@ -11,22 +11,13 @@ #include <linux/time.h> -#define INTC_IPRD 0xffd00010UL - #define IRL0_IRQ 2 -#define IRL0_IPR_POS 3 #define IRL0_PRIORITY 13 - #define IRL1_IRQ 5 -#define IRL1_IPR_POS 2 #define IRL1_PRIORITY 10 - #define IRL2_IRQ 8 -#define IRL2_IPR_POS 1 #define IRL2_PRIORITY 7 - #define IRL3_IRQ 11 -#define IRL3_IPR_POS 0 #define IRL3_PRIORITY 4 void heartbeat_sh03(void); diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h index b99ca786c0c1..9c8d34b07ebf 100644 --- a/include/asm-sh/smp.h +++ b/include/asm-sh/smp.h @@ -1,12 +1,3 @@ -/* - * include/asm-sh/smp.h - * - * Copyright (C) 2002, 2003 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive for - * more details. - */ #ifndef __ASM_SH_SMP_H #define __ASM_SH_SMP_H @@ -20,6 +11,15 @@ #include <asm/current.h> #define raw_smp_processor_id() (current_thread_info()->cpu) +#define hard_smp_processor_id() plat_smp_processor_id() + +/* Map from cpu id to sequential logical cpu number. */ +extern int __cpu_number_map[NR_CPUS]; +#define cpu_number_map(cpu) __cpu_number_map[cpu] + +/* The reverse map from sequential logical cpu number to cpu id. */ +extern int __cpu_logical_map[NR_CPUS]; +#define cpu_logical_map(cpu) __cpu_logical_map[cpu] /* I've no idea what the real meaning of this is */ #define PROC_CHANGE_PENALTY 20 @@ -35,10 +35,22 @@ struct smp_fn_call_struct { extern struct smp_fn_call_struct smp_fn_call; -#define SMP_MSG_RESCHEDULE 0x0001 +#define SMP_MSG_FUNCTION 0 +#define SMP_MSG_RESCHEDULE 1 +#define SMP_MSG_NR 2 -#endif /* CONFIG_SMP */ +void plat_smp_setup(void); +void plat_prepare_cpus(unsigned int max_cpus); +int plat_smp_processor_id(void); +void plat_start_cpu(unsigned int cpu, unsigned long entry_point); +void plat_send_ipi(unsigned int cpu, unsigned int message); +int plat_register_ipi_handler(unsigned int message, + void (*handler)(void *), void *arg); + +#else #define hard_smp_processor_id() (0) +#endif /* CONFIG_SMP */ + #endif /* __ASM_SH_SMP_H */ diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h index 3554e3a74e99..042d95f51c4d 100644 --- a/include/asm-sh/snapgear.h +++ b/include/asm-sh/snapgear.h @@ -19,20 +19,16 @@ * is the interrupt :-) */ -#define IRL0_IRQ 2 -#define IRL0_IPR_POS 3 +#define IRL0_IRQ 2 #define IRL0_PRIORITY 13 -#define IRL1_IRQ 5 -#define IRL1_IPR_POS 2 +#define IRL1_IRQ 5 #define IRL1_PRIORITY 10 -#define IRL2_IRQ 8 -#define IRL2_IPR_POS 1 +#define IRL2_IRQ 8 #define IRL2_PRIORITY 7 -#define IRL3_IRQ 11 -#define IRL3_IPR_POS 0 +#define IRL3_IRQ 11 #define IRL3_PRIORITY 4 #endif diff --git a/include/asm-sh/spinlock.h b/include/asm-sh/spinlock.h index 92f6e2008b2e..e793181d64da 100644 --- a/include/asm-sh/spinlock.h +++ b/include/asm-sh/spinlock.h @@ -2,6 +2,7 @@ * include/asm-sh/spinlock.h * * Copyright (C) 2002, 2003 Paul Mundt + * Copyright (C) 2006, 2007 Akio Idehara * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -10,17 +11,22 @@ #ifndef __ASM_SH_SPINLOCK_H #define __ASM_SH_SPINLOCK_H -#include <asm/atomic.h> -#include <asm/spinlock_types.h> +/* + * The only locking implemented here uses SH-4A opcodes. For others, + * split this out as per atomic-*.h. + */ +#ifndef CONFIG_CPU_SH4A +#error "Need movli.l/movco.l for spinlocks" +#endif /* * Your basic SMP spinlocks, allowing only a single CPU anywhere */ -#define __raw_spin_is_locked(x) ((x)->lock != 0) +#define __raw_spin_is_locked(x) ((x)->lock <= 0) #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) #define __raw_spin_unlock_wait(x) \ - do { cpu_relax(); } while (__raw_spin_is_locked(x)) + do { cpu_relax(); } while ((x)->lock) /* * Simple spin lock operations. There are two variants, one clears IRQ's @@ -30,12 +36,19 @@ */ static inline void __raw_spin_lock(raw_spinlock_t *lock) { + unsigned long tmp; + unsigned long oldval; + __asm__ __volatile__ ( - "1:\n\t" - "tas.b @%0\n\t" - "bf/s 1b\n\t" - "nop\n\t" - : "=r" (lock->lock) + "1: \n\t" + "movli.l @%2, %0 ! __raw_spin_lock \n\t" + "mov %0, %1 \n\t" + "mov #0, %0 \n\t" + "movco.l %0, @%2 \n\t" + "bf 1b \n\t" + "cmp/pl %1 \n\t" + "bf 1b \n\t" + : "=&z" (tmp), "=&r" (oldval) : "r" (&lock->lock) : "t", "memory" ); @@ -43,12 +56,36 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) static inline void __raw_spin_unlock(raw_spinlock_t *lock) { - //assert_spin_locked(lock); + unsigned long tmp; - lock->lock = 0; + __asm__ __volatile__ ( + "mov #1, %0 ! __raw_spin_unlock \n\t" + "mov.l %0, @%1 \n\t" + : "=&z" (tmp) + : "r" (&lock->lock) + : "t", "memory" + ); } -#define __raw_spin_trylock(x) (!test_and_set_bit(0, &(x)->lock)) +static inline int __raw_spin_trylock(raw_spinlock_t *lock) +{ + unsigned long tmp, oldval; + + __asm__ __volatile__ ( + "1: \n\t" + "movli.l @%2, %0 ! __raw_spin_trylock \n\t" + "mov %0, %1 \n\t" + "mov #0, %0 \n\t" + "movco.l %0, @%2 \n\t" + "bf 1b \n\t" + "synco \n\t" + : "=&z" (tmp), "=&r" (oldval) + : "r" (&lock->lock) + : "t", "memory" + ); + + return oldval; +} /* * Read-write spinlocks, allowing multiple readers but only one writer. @@ -59,58 +96,124 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) * read-locks. */ +/** + * read_can_lock - would read_trylock() succeed? + * @lock: the rwlock in question. + */ +#define __raw_read_can_lock(x) ((x)->lock > 0) + +/** + * write_can_lock - would write_trylock() succeed? + * @lock: the rwlock in question. + */ +#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS) + static inline void __raw_read_lock(raw_rwlock_t *rw) { - __raw_spin_lock(&rw->lock); - - atomic_inc(&rw->counter); + unsigned long tmp; - __raw_spin_unlock(&rw->lock); + __asm__ __volatile__ ( + "1: \n\t" + "movli.l @%1, %0 ! __raw_read_lock \n\t" + "cmp/pl %0 \n\t" + "bf 1b \n\t" + "add #-1, %0 \n\t" + "movco.l %0, @%1 \n\t" + "bf 1b \n\t" + : "=&z" (tmp) + : "r" (&rw->lock) + : "t", "memory" + ); } static inline void __raw_read_unlock(raw_rwlock_t *rw) { - __raw_spin_lock(&rw->lock); - - atomic_dec(&rw->counter); + unsigned long tmp; - __raw_spin_unlock(&rw->lock); + __asm__ __volatile__ ( + "1: \n\t" + "movli.l @%1, %0 ! __raw_read_unlock \n\t" + "add #1, %0 \n\t" + "movco.l %0, @%1 \n\t" + "bf 1b \n\t" + : "=&z" (tmp) + : "r" (&rw->lock) + : "t", "memory" + ); } static inline void __raw_write_lock(raw_rwlock_t *rw) { - __raw_spin_lock(&rw->lock); - atomic_set(&rw->counter, -1); + unsigned long tmp; + + __asm__ __volatile__ ( + "1: \n\t" + "movli.l @%1, %0 ! __raw_write_lock \n\t" + "cmp/hs %2, %0 \n\t" + "bf 1b \n\t" + "sub %2, %0 \n\t" + "movco.l %0, @%1 \n\t" + "bf 1b \n\t" + : "=&z" (tmp) + : "r" (&rw->lock), "r" (RW_LOCK_BIAS) + : "t", "memory" + ); } static inline void __raw_write_unlock(raw_rwlock_t *rw) { - atomic_set(&rw->counter, 0); - __raw_spin_unlock(&rw->lock); + __asm__ __volatile__ ( + "mov.l %1, @%0 ! __raw_write_unlock \n\t" + : + : "r" (&rw->lock), "r" (RW_LOCK_BIAS) + : "t", "memory" + ); } -static inline int __raw_write_can_lock(raw_rwlock_t *rw) +static inline int __raw_read_trylock(raw_rwlock_t *rw) { - return (atomic_read(&rw->counter) == RW_LOCK_BIAS); -} + unsigned long tmp, oldval; -static inline int __raw_read_trylock(raw_rwlock_t *lock) -{ - atomic_t *count = (atomic_t*)lock; - if (atomic_dec_return(count) >= 0) - return 1; - atomic_inc(count); - return 0; + __asm__ __volatile__ ( + "1: \n\t" + "movli.l @%2, %0 ! __raw_read_trylock \n\t" + "mov %0, %1 \n\t" + "cmp/pl %0 \n\t" + "bf 2f \n\t" + "add #-1, %0 \n\t" + "movco.l %0, @%2 \n\t" + "bf 1b \n\t" + "2: \n\t" + "synco \n\t" + : "=&z" (tmp), "=&r" (oldval) + : "r" (&rw->lock) + : "t", "memory" + ); + + return (oldval > 0); } static inline int __raw_write_trylock(raw_rwlock_t *rw) { - if (atomic_sub_and_test(RW_LOCK_BIAS, &rw->counter)) - return 1; - - atomic_add(RW_LOCK_BIAS, &rw->counter); + unsigned long tmp, oldval; + + __asm__ __volatile__ ( + "1: \n\t" + "movli.l @%2, %0 ! __raw_write_trylock \n\t" + "mov %0, %1 \n\t" + "cmp/hs %3, %0 \n\t" + "bf 2f \n\t" + "sub %3, %0 \n\t" + "2: \n\t" + "movco.l %0, @%2 \n\t" + "bf 1b \n\t" + "synco \n\t" + : "=&z" (tmp), "=&r" (oldval) + : "r" (&rw->lock), "r" (RW_LOCK_BIAS) + : "t", "memory" + ); - return 0; + return (oldval > (RW_LOCK_BIAS - 1)); } #define _raw_spin_relax(lock) cpu_relax() diff --git a/include/asm-sh/spinlock_types.h b/include/asm-sh/spinlock_types.h index 5c58134f2c4e..b4d244e7b60c 100644 --- a/include/asm-sh/spinlock_types.h +++ b/include/asm-sh/spinlock_types.h @@ -6,19 +6,16 @@ #endif typedef struct { - volatile unsigned long lock; + volatile unsigned int lock; } raw_spinlock_t; -#define __RAW_SPIN_LOCK_UNLOCKED { 1 } - -#include <asm/atomic.h> +#define __RAW_SPIN_LOCK_UNLOCKED { 1 } typedef struct { - raw_spinlock_t lock; - atomic_t counter; + volatile unsigned int lock; } raw_rwlock_t; #define RW_LOCK_BIAS 0x01000000 -#define __RAW_RW_LOCK_UNLOCKED { { 0 }, { RW_LOCK_BIAS } } +#define __RAW_RW_LOCK_UNLOCKED { RW_LOCK_BIAS } #endif diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h index 245042537205..9d849e6df268 100644 --- a/include/asm-sh/system.h +++ b/include/asm-sh/system.h @@ -266,6 +266,7 @@ void disable_hlt(void); void enable_hlt(void); void default_idle(void); +void per_cpu_trap_init(void); asmlinkage void break_point_trap(void); asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5, diff --git a/include/asm-sh/voyagergx.h b/include/asm-sh/voyagergx.h index 64c936b22715..d825596562df 100644 --- a/include/asm-sh/voyagergx.h +++ b/include/asm-sh/voyagergx.h @@ -27,13 +27,35 @@ #define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE) #define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE) -#define VOYAGER_IRQ_NUM 32 -#define VOYAGER_IRQ_BASE 50 -#define VOYAGER_USBH_IRQ VOYAGER_IRQ_BASE + 6 -#define VOYAGER_8051_IRQ VOYAGER_IRQ_BASE + 10 -#define VOYAGER_UART0_IRQ VOYAGER_IRQ_BASE + 12 -#define VOYAGER_UART1_IRQ VOYAGER_IRQ_BASE + 13 -#define VOYAGER_AC97_IRQ VOYAGER_IRQ_BASE + 17 +#define VOYAGER_IRQ_NUM 26 +#define VOYAGER_IRQ_BASE 200 + +#define IRQ_SM501_UP (VOYAGER_IRQ_BASE + 0) +#define IRQ_SM501_G54 (VOYAGER_IRQ_BASE + 1) +#define IRQ_SM501_G53 (VOYAGER_IRQ_BASE + 2) +#define IRQ_SM501_G52 (VOYAGER_IRQ_BASE + 3) +#define IRQ_SM501_G51 (VOYAGER_IRQ_BASE + 4) +#define IRQ_SM501_G50 (VOYAGER_IRQ_BASE + 5) +#define IRQ_SM501_G49 (VOYAGER_IRQ_BASE + 6) +#define IRQ_SM501_G48 (VOYAGER_IRQ_BASE + 7) +#define IRQ_SM501_I2C (VOYAGER_IRQ_BASE + 8) +#define IRQ_SM501_PW (VOYAGER_IRQ_BASE + 9) +#define IRQ_SM501_DMA (VOYAGER_IRQ_BASE + 10) +#define IRQ_SM501_PCI (VOYAGER_IRQ_BASE + 11) +#define IRQ_SM501_I2S (VOYAGER_IRQ_BASE + 12) +#define IRQ_SM501_AC (VOYAGER_IRQ_BASE + 13) +#define IRQ_SM501_US (VOYAGER_IRQ_BASE + 14) +#define IRQ_SM501_U1 (VOYAGER_IRQ_BASE + 15) +#define IRQ_SM501_U0 (VOYAGER_IRQ_BASE + 16) +#define IRQ_SM501_CV (VOYAGER_IRQ_BASE + 17) +#define IRQ_SM501_MC (VOYAGER_IRQ_BASE + 18) +#define IRQ_SM501_S1 (VOYAGER_IRQ_BASE + 19) +#define IRQ_SM501_S0 (VOYAGER_IRQ_BASE + 20) +#define IRQ_SM501_UH (VOYAGER_IRQ_BASE + 21) +#define IRQ_SM501_2D (VOYAGER_IRQ_BASE + 22) +#define IRQ_SM501_ZD (VOYAGER_IRQ_BASE + 23) +#define IRQ_SM501_PV (VOYAGER_IRQ_BASE + 24) +#define IRQ_SM501_CI (VOYAGER_IRQ_BASE + 25) /* ----- MISC controle register ------------------------------ */ #define MISC_CTRL (0x000004 + VOYAGER_BASE) @@ -313,4 +335,7 @@ void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t); int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t); +/* arch/sh/cchips/voyagergx/irq.c */ +void setup_voyagergx_irq(void); + #endif /* _VOYAGER_GX_REG_H */ |