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authorAndi Kleen <ak@suse.de>2006-01-11 22:45:24 +0100
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-11 19:04:58 -0800
commitc818a18146997d1356a4840b0c01f1168c16c8a4 (patch)
tree8d7e049742e87666bf3089fe46e04828b6417fd7 /include/asm-x86_64/cpufeature.h
parent7f6c5b046978d68e69bdc73433ead41612a2a1c9 (diff)
[PATCH] x86_64: On Intel CPUs don't do an additional CPU sync before RDTSC
RDTSC serialization using cpuid is not needed for Intel platforms. This increases gettimeofday performance. Cc: vojtech@suse.cz Cc: rohit.seth@intel.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-x86_64/cpufeature.h')
-rw-r--r--include/asm-x86_64/cpufeature.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h
index aea308c65709..72b39f514798 100644
--- a/include/asm-x86_64/cpufeature.h
+++ b/include/asm-x86_64/cpufeature.h
@@ -63,6 +63,7 @@
#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
#define X86_FEATURE_K8_C (3*32+ 4) /* C stepping K8 */
#define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */
+#define X86_FEATURE_SYNC_RDTSC (3*32+6) /* RDTSC syncs CPU core */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */