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authorAlim Akhtar <alim.akhtar@samsung.com>2015-09-10 14:14:35 +0530
committerSylwester Nawrocki <s.nawrocki@samsung.com>2015-09-15 11:16:10 +0200
commit753195a749a6c849dbd05cb82a2deb4190a06257 (patch)
tree29ed14b94aa2776759085f4ab6f0f47748928396 /include/dt-bindings/clock
parenta259a61be1d0d01aa2dd4778722e4d161780c813 (diff)
clk: samsung: exynos7: Correct CMU_FSYS1 clocks names
This patch renames CMU_FSYS1 clocks names to match with user manual. And also adds missing gate clock for aclk_fsys1_200. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 667faed474ce..acdf2e5e1ac0 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -63,7 +63,8 @@
#define CLK_SCLK_MMC1 7
#define CLK_SCLK_MMC0 8
#define CLK_ACLK_FSYS0_200 9
-#define TOP1_NR_CLK 10
+#define CLK_ACLK_FSYS1_200 10
+#define TOP1_NR_CLK 11
/* CCORE */
#define PCLK_RTC 1