diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-06-02 12:06:05 -0700 |
|---|---|---|
| committer | Kyle Yan <kyan@codeaurora.org> | 2016-06-20 15:06:16 -0700 |
| commit | 3091a5c5f772b5087ae0000a108b06e0ed385b21 (patch) | |
| tree | 03bc2c2ea60336f1cd877534e5c503efdf3b8bc7 /include/dt-bindings | |
| parent | d7a02e724c03c53b23af6ade1e11e885a1b08d47 (diff) | |
clk: msm: clock: Add support for programming MDP_LUT_CBCR register
Add support for the mdss_mdp_lut_clk clock on MSMCOBALT.
In addition, remove toggling the memory retention bits for the
mdp core clock during gdsc_enable/disable. The display driver
will use the set_flags API to set the core clock memory retention.
CRs-Fixed: 1025605
Change-Id: If812473a67a7900c8f7b8b97f32fbf003f0e80a4
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-cobalt.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-hwio-cobalt.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h index c4c8f271e944..d3cfc622b323 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-cobalt.h @@ -412,6 +412,7 @@ #define clk_mmss_mdss_hdmi_clk 0x28460a6d #define clk_mmss_mdss_hdmi_dp_ahb_clk 0x5448519f #define clk_mmss_mdss_mdp_clk 0x43539b0e +#define clk_mmss_mdss_mdp_lut_clk 0x00627b2b #define clk_mmss_mdss_pclk0_clk 0xcc0e909d #define clk_mmss_mdss_pclk1_clk 0x850d9146 #define clk_mmss_mdss_rot_clk 0xbb7e71c4 diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h index 4175d3be68a3..af26f826e18c 100644 --- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h @@ -380,6 +380,7 @@ #define MMSS_MDSS_HDMI_CBCR 0x02338 #define MMSS_MDSS_HDMI_DP_AHB_CBCR 0x0230C #define MMSS_MDSS_MDP_CBCR 0x0231C +#define MMSS_MDSS_MDP_LUT_CBCR 0x02320 #define MMSS_MDSS_PCLK0_CBCR 0x02314 #define MMSS_MDSS_PCLK1_CBCR 0x02318 #define MMSS_MDSS_ROT_CBCR 0x02350 |