diff options
| author | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-02-22 16:43:23 -0800 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-09 18:35:23 -0700 |
| commit | 3ee6103a8dcace1b8f6aa20fc3c5844ca51dd829 (patch) | |
| tree | 466d6f3af405d067461c4d750ff8c034394cf86a /include/dt-bindings | |
| parent | a240321fd68894659859861b96a618af8370efbb (diff) | |
clk: qcom: mdss: add Display-port pll clock driver support
Add support for new Display-port PLL clock driver to handle
different DP panel resolutions in msmcobalt. Add separate files
to support this new PHY PLL block.
CRs-Fixed: 1009740
Change-Id: Ic282c7e14fc6e23f4d044cb6a58249bdb4c8c2d8
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-cobalt.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h index 6899733515c3..eb4251cf5e06 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-cobalt.h @@ -451,6 +451,13 @@ #define clk_dsi1pll_bitclk_src 0x13ab045b #define clk_dsi1pll_vco_clk 0x99797b50 +#define clk_dp_vco_clk 0xfcaaeec7 +#define clk_hsclk_divsel_clk_src 0x0a325543 +#define clk_dp_link_2x_clk_divsel_five 0xcfe3f5dd +#define clk_dp_link_2x_clk_divsel_ten 0xfeb9924d +#define clk_dp_link_2x_clk_mux 0xce4c4fc6 +#define clk_vco_divided_clk_src 0x3da6cb51 + /* clock_gpu controlled clocks*/ #define clk_gpucc_xo 0xc4e1a890 #define clk_gpucc_gpll0 0x0db0e37f |