diff options
| author | Rajkumar Subbiah <rsubbia@codeaurora.org> | 2017-03-03 17:21:43 -0500 |
|---|---|---|
| committer | Rajkumar Subbiah <rsubbia@codeaurora.org> | 2017-05-15 11:45:00 -0400 |
| commit | 6d8fa6f1ccf8ec205e34e1333bffc39b920fe171 (patch) | |
| tree | 98558bd8485d834e4b684682c4d10575a58fb8d3 /include/dt-bindings | |
| parent | c6d1c1699e7dcc7ec170baae48be94814061d0b7 (diff) | |
clk: msm: Fix dsi clock divider configuration
The MND values and the PLL output divider configuration does
not match the recommended values. When setting DSI pixel clock
rate the MND array is ordered in a way that the requested
rate goes from highest to lowest. Since the recommendation is
to divide the clocks as close to VCO as possible, the request
should be from lowest to highest. So reversing the fraction
array to match the recommendation. The VCO min max rates are
currently forced after pll output divider which is also fixed.
Change-Id: I3cb5163f9c8dd3723cdc58bd7e7980719e683f1b
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-8998.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/msm-clocks-8998.h b/include/dt-bindings/clock/msm-clocks-8998.h index cd36374a04a7..67e47c46e09a 100644 --- a/include/dt-bindings/clock/msm-clocks-8998.h +++ b/include/dt-bindings/clock/msm-clocks-8998.h @@ -443,6 +443,11 @@ #define clk_dsi0pll_pclk_src 0x5efd85d4 #define clk_dsi0pll_pclk_src_mux 0x84b14663 #define clk_dsi0pll_post_bit_div 0xf46dcf27 +#define clk_dsi0pll_pll_out_div1 0xeda5b7fe +#define clk_dsi0pll_pll_out_div2 0x97fa476d +#define clk_dsi0pll_pll_out_div4 0x90a98ce0 +#define clk_dsi0pll_pll_out_div8 0x9d9d85cf +#define clk_dsi0pll_pll_out_mux 0x179c27ca #define clk_dsi0pll_post_vco_mux 0xfaf9bd1f #define clk_dsi0pll_post_vco_div1 0xabb50b2a #define clk_dsi0pll_post_vco_div4 0xbe51c091 @@ -455,6 +460,11 @@ #define clk_dsi1pll_pclk_src 0xeddcd80e #define clk_dsi1pll_pclk_src_mux 0x3651feb3 #define clk_dsi1pll_post_bit_div 0x712f0260 +#define clk_dsi1pll_pll_out_div8 0x87628ddb +#define clk_dsi1pll_pll_out_div4 0x0d9a384b +#define clk_dsi1pll_pll_out_div2 0x0c9b5748 +#define clk_dsi1pll_pll_out_div1 0x3193164e +#define clk_dsi1pll_pll_out_mux 0x171bf8fd #define clk_dsi1pll_post_vco_mux 0xc6a90d20 #define clk_dsi1pll_post_vco_div1 0x6f47ca7d #define clk_dsi1pll_post_vco_div4 0x90628974 |