diff options
| author | Sahitya Tummala <stummala@codeaurora.org> | 2015-05-28 16:54:19 +0530 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-31 15:26:40 -0700 |
| commit | 83ed2ae95e1dc8e07faa82f570cb7cbbc58754ff (patch) | |
| tree | 7c4cee5cba969e5842e845de191b45f0319bc04f /include/linux/mmc | |
| parent | c3475c87343ca5e78e1033612c604489d2fd6566 (diff) | |
mmc: block: Add cache barrier support
eMMC cache barrier provides a way to perform delayed
and in-order flushing of cached data. Host can use this
to avoid flushing delays but still maintain the order
between the data requests in cache.
In case the device gets more barrier requests than it
supports, then a barrier request is treated as a normal flush
request in the device.
If the eMMC cache flushing policy is set to 1, then the device
inherently flushes all the cached requests in FIFO order. For such
devices, as per spec, it is redundant to send any barrier requests
to the device. This may add unnecessary overhead to both host and
the device. So make sure to not send barrier requests in such cases.
Change-Id: Ia7af316800a6895942d3cabcd64600d56fab25a6
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Diffstat (limited to 'include/linux/mmc')
| -rw-r--r-- | include/linux/mmc/card.h | 3 | ||||
| -rw-r--r-- | include/linux/mmc/core.h | 1 | ||||
| -rw-r--r-- | include/linux/mmc/mmc.h | 3 |
3 files changed, 7 insertions, 0 deletions
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 609a792e9e5c..0f4e22db31ab 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -119,10 +119,13 @@ struct mmc_ext_csd { u8 raw_pwr_cl_ddr_52_195; /* 238 */ u8 raw_pwr_cl_ddr_52_360; /* 239 */ u8 raw_pwr_cl_ddr_200_360; /* 253 */ + u8 cache_flush_policy; /* 240 */ u8 raw_bkops_status; /* 246 */ u8 raw_sectors[4]; /* 212 - 4 bytes */ u8 cmdq_depth; /* 307 */ u8 cmdq_support; /* 308 */ + u8 barrier_support; /* 486 */ + u8 barrier_en; unsigned int feature_support; #define MMC_DISCARD_FEATURE BIT(0) /* CMD38 feature */ diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index fcad0aa31b2e..22c610609a25 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -185,6 +185,7 @@ extern void mmc_put_card(struct mmc_card *card); extern void mmc_set_ios(struct mmc_host *host); extern int mmc_flush_cache(struct mmc_card *); +extern int mmc_cache_barrier(struct mmc_card *); extern int mmc_detect_card_removed(struct mmc_host *host); diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index 07b04c6e5c64..5612781ef522 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h @@ -221,6 +221,7 @@ struct _mmc_csd { */ #define EXT_CSD_CMDQ 15 /* R/W */ +#define EXT_CSD_BARRIER_CTRL 31 /* R/W */ #define EXT_CSD_FLUSH_CACHE 32 /* W */ #define EXT_CSD_CACHE_CTRL 33 /* R/W */ #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ @@ -273,6 +274,7 @@ struct _mmc_csd { #define EXT_CSD_PWR_CL_200_360 237 /* RO */ #define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ #define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ +#define EXT_CSD_CACHE_FLUSH_POLICY 240 /* RO */ #define EXT_CSD_BKOPS_STATUS 246 /* RO */ #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ @@ -281,6 +283,7 @@ struct _mmc_csd { #define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */ #define EXT_CSD_CMDQ_DEPTH 307 /* RO */ #define EXT_CSD_CMDQ_SUPPORT 308 /* RO */ +#define EXT_CSD_BARRIER_SUPPORT 486 /* RO */ #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ #define EXT_CSD_SUPPORTED_MODE 493 /* RO */ #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ |