diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2012-07-10 08:36:09 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-07-10 08:36:09 -0600 |
| commit | 6ee53f4c38e70ba34777ad38807a50c1812ff36f (patch) | |
| tree | 8a4eeef5923d28c2e4ab14f4559e686cc1fce455 /include/linux | |
| parent | d68e70c6e59ad08feca291c2790164d3231c425e (diff) | |
| parent | 1c975931128c1128892981095a64fb8eabf240eb (diff) | |
Merge branch 'pci/bjorn-p2p-bridge-windows' into next
* pci/bjorn-p2p-bridge-windows:
sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases()
PCI: support sizing P2P bridge I/O windows with 1K granularity
PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)
PCI: allow P2P bridge windows starting at PCI bus address zero
Conflicts:
drivers/pci/probe.c
include/linux/pci.h
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/pci.h | 1 | ||||
| -rw-r--r-- | include/linux/pci_regs.h | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index 85cffb823b4e..5faa8310eec9 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -333,6 +333,7 @@ struct pci_dev { unsigned int __aer_firmware_first_valid:1; unsigned int __aer_firmware_first:1; unsigned int broken_intx_masking:1; + unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ pci_dev_flags_t dev_flags; atomic_t enable_cnt; /* pci_enable_device has been called */ diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 80e8605b5f93..53274bff5773 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -126,7 +126,8 @@ #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ #define PCI_IO_RANGE_TYPE_16 0x00 #define PCI_IO_RANGE_TYPE_32 0x01 -#define PCI_IO_RANGE_MASK (~0x0fUL) +#define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */ +#define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */ #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ #define PCI_MEMORY_LIMIT 0x22 |