diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-05-10 16:29:54 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-15 22:41:21 -0700 |
| commit | 8cc9b35f9afa15b9aa45c7fc35ddcd958d3207cb (patch) | |
| tree | a30290d771b59d24c37ca56a0e8db68886955ea5 /include/net/llc_pdu.h | |
| parent | 4622a2f4260b7d6a523909a4d86fa66000f36324 (diff) | |
clk: msm: clock-gcc-cobalt: Add reset capability to PCIE pipe clock
Instead of having a separate reset clock for PCIE 0 reset, tag the
BCR register with the gcc_pcie_0_pipe_clk directly.
CRs-Fixed: 1014989
Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'include/net/llc_pdu.h')
0 files changed, 0 insertions, 0 deletions