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authorRafał Miłecki <zajec5@gmail.com>2015-01-26 18:05:22 +0100
committerBjorn Helgaas <bhelgaas@google.com>2015-01-27 08:14:26 -0600
commit5929b8a38ce02b7769e8b79605a8690f442a2933 (patch)
treeac41c369249dc996102b5f03a29f83a02613587d /include/uapi
parent94a90312e4ef1b03469086d41fedfa55e67a1532 (diff)
PCI: Add defines for PCIe Max_Read_Request_Size
There are a few drivers using magic numbers when operating with PCIe capabilities and PCI_EXP_DEVCTL_READRQ. Define known values to allow cleaning their code a bit. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/uapi')
-rw-r--r--include/uapi/linux/pci_regs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 4a1d0cc38ff2..efe3443572ba 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -451,6 +451,10 @@
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */
+#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
#define PCI_EXP_DEVSTA 10 /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */