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authorKumar Gala <galak@kernel.crashing.org>2007-07-19 16:07:35 -0500
committerKumar Gala <galak@kernel.crashing.org>2007-07-23 22:29:09 -0500
commit2e56ff206b7c6c28b847ccdbe46ad69b3263ac32 (patch)
tree636f8d31a2b6c19fe21b12c61f47dcd96d393871 /include
parentd5269966e57484548bc5d38e117f161bf2f56ce9 (diff)
[POWERPC] Make endianess of cfg_addr for indirect pci ops runtime
Make it so we do a runtime check to know if we need to write cfg_addr as big or little endian. This is needed if we want to allow 86xx support to co-exist in the same kernel as other 6xx PPCs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/pci-bridge.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index 13cb0a973478..9ce8f2991acf 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -49,11 +49,13 @@ struct pci_controller {
* hanging if we don't have link and try to do config cycles to
* anything but the PHB. Only allow talking to the PHB if this is
* set.
+ * BIG_ENDIAN - cfg_addr is a big endian register
*/
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
+#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
u32 indirect_type;
/* Currently, we limit ourselves to 1 IO range and 3 mem
@@ -88,7 +90,7 @@ extern int early_find_capability(struct pci_controller *hose, int bus,
int dev_fn, int cap);
extern void setup_indirect_pci(struct pci_controller* hose,
- u32 cfg_addr, u32 cfg_data);
+ u32 cfg_addr, u32 cfg_data, u32 flags);
extern void setup_grackle(struct pci_controller *hose);
#else