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authorHans Rosenfeld <hans.rosenfeld@amd.com>2010-10-29 17:14:32 +0200
committerBorislav Petkov <borislav.petkov@amd.com>2010-11-18 15:53:06 +0100
commitf658bcfb2607bf0808966a69cf74135ce98e5c2d (patch)
treea01f768fb6b49acd701f912f426e1fd6ee4f0f56 /init
parent9653a5c76c8677b05b45b3b999d3b39988d2a064 (diff)
x86, cacheinfo: Cleanup L3 cache index disable support
Adaptions to the changes of the AMD northbridge caching code: instead of a bool in each l3 struct, use a flag in amd_northbridges.flags to indicate L3 cache index disable support; use a pointer to the whole northbridge instead of the misc device in the l3 struct; simplify the initialisation; dynamically generate sysfs attribute array. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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