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authorDeng-Cheng Zhu <dengcheng.zhu@imgtec.com>2013-10-08 16:17:48 +0100
committerRalf Baechle <ralf@linux-mips.org>2013-10-29 21:18:23 +0100
commit7f081f175502373673c015a4d0fa1d5cc264758a (patch)
treebd53f2a1470b37b79d7e5f5f6e0fe7bcfbc452d4 /mm/debug-pagealloc.c
parent959f58544b7f20c92d5eb43d1232c96c15c01bfb (diff)
MIPS: Perf: Fix 74K cache map
According to Software User's Manual, the event of last-level-cache read/write misses is mapped to even counters. Odd counters of that event number count miss cycles. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6036/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'mm/debug-pagealloc.c')
0 files changed, 0 insertions, 0 deletions