diff options
| author | Jarkko Nikula <jhnikula@gmail.com> | 2009-08-23 12:24:26 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-08-25 10:20:48 +0100 |
| commit | 32080af7a612e8c56131d6bdcd268cd9e8b0add1 (patch) | |
| tree | 8022b8c7cdd0e2efc9f73e5f913cdd913078bd27 /sound/soc | |
| parent | 9b30050908fad96968497e73b88626056ea33c96 (diff) | |
ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI
Commit ca6e2ce08679c094878d7f39a0349a7db1d13675 is setting up few XCCR and
RCCR bits for I2S and DPS_A formats. Part of the bits are already set
for all formats and I believe that XDISABLE and RDISABLE bits are
format independent.
As XCCR and RCCR are found only from OMAP2430 and OMAP34xx, I move setup
of XDISABLE and RDISABLE to where those cpu's are tested and remove format
dependent part for simplicity.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc')
| -rw-r--r-- | sound/soc/omap/omap-mcbsp.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index f5387d962f5d..89e8bce114af 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -379,8 +379,8 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, regs->xcr2 |= XFIG; } if (cpu_is_omap2430() || cpu_is_omap34xx()) { - regs->xccr = DXENDLY(1) | XDMAEN; - regs->rccr = RFULL_CYCLE | RDMAEN; + regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; + regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; } switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -388,15 +388,11 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, /* 1-bit data delay */ regs->rcr2 |= RDATDLY(1); regs->xcr2 |= XDATDLY(1); - regs->rccr |= RFULL_CYCLE | RDMAEN | RDISABLE; - regs->xccr |= (DXENDLY(1) | XDMAEN | XDISABLE); break; case SND_SOC_DAIFMT_DSP_A: /* 1-bit data delay */ regs->rcr2 |= RDATDLY(1); regs->xcr2 |= XDATDLY(1); - regs->rccr |= RFULL_CYCLE | RDMAEN | RDISABLE; - regs->xccr |= (DXENDLY(1) | XDMAEN | XDISABLE); /* Invert FS polarity configuration */ temp_fmt ^= SND_SOC_DAIFMT_NB_IF; break; |