diff options
| author | Soumya Managoli <smanag@codeaurora.org> | 2018-05-03 13:41:41 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2018-06-18 22:29:38 -0700 |
| commit | 586a6ad358404b2f9d68b92aa81510ada4556e8a (patch) | |
| tree | 04611472b60060a5a8a785933a8f251ed58dfefd /sound | |
| parent | 2763b994a1a1145eb8d538b35e7bab5156e1e351 (diff) | |
asoc: codecs: sdm660_cdc: Fix LPASS register access during SSR
When AFE returns failure in setting the digital codec
core clock during SSR, it leads to LPASS register access
which results in NOC error and AHB timeout. Put the regmap
in cache only mode when clock enable fails to fix this.
Also fix watchdog bite failure during stability run
by returning from digclock control if cacheonly mode
is set. This is seen while SSR is in progress and teardown
of session happens, it will request for afe clock enable
continuously at digital clock control.
Change-Id: I952b667a5cffcb667154378102609b23ab0cee3d
Signed-off-by: Soumya Managoli <smanag@codeaurora.org>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c index 43f00dcff7af..f4546f4fdcc2 100644 --- a/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c +++ b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -86,6 +86,8 @@ static int msm_digcdc_clock_control(bool flag) if (flag) { mutex_lock(&pdata->cdc_int_mclk0_mutex); if (atomic_read(&pdata->int_mclk0_enabled) == false) { + if (msm_dig_cdc->regmap->cache_only == true) + return ret; if (pdata->native_clk_set) pdata->digital_cdc_core_clk.clk_freq_in_hz = NATIVE_MCLK_RATE; @@ -103,8 +105,7 @@ static int msm_digcdc_clock_control(bool flag) * Avoid access to lpass register * as clock enable failed during SSR. */ - if (ret == -ENODEV) - msm_dig_cdc->regmap->cache_only = true; + msm_dig_cdc->regmap->cache_only = true; return ret; } pr_debug("enabled digital codec core clk\n"); |