diff options
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 2 | ||||
| -rw-r--r-- | drivers/clk/msm/clock-gcc-cobalt.c | 22 | ||||
| -rw-r--r-- | drivers/clk/msm/clock-mmss-cobalt.c | 9 | ||||
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-cobalt.h | 19 |
4 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index d49a4faa22f0..c9ddfd1d024b 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -737,6 +737,7 @@ vdd_dig-supply = <&pmcobalt_s1_level>; vdd_dig_ao-supply = <&pmcobalt_s1_level_ao>; #clock-cells = <1>; + #reset-cells = <1>; }; clock_mmss: qcom,mmsscc@c8c0000 { @@ -760,6 +761,7 @@ <&mdss_dp_pll clk_vco_divided_clk_src_mux>, <&mdss_hdmi_pll clk_hdmi_vco_clk>; #clock-cells = <1>; + #reset-cells = <1>; }; clock_gpu: qcom,gpucc@5065000 { diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c index 2049a0bf7dd2..e469c61cc3db 100644 --- a/drivers/clk/msm/clock-gcc-cobalt.c +++ b/drivers/clk/msm/clock-gcc-cobalt.c @@ -32,6 +32,7 @@ #include <dt-bindings/clock/msm-clocks-hwio-cobalt.h> #include "vdd-level-cobalt.h" +#include "reset.h" static void __iomem *virt_base; static void __iomem *virt_dbgbase; @@ -2695,6 +2696,23 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_qspi_ref_clk), }; +static const struct msm_reset_map gcc_cobalt_resets[] = { + [QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [QUSB2PHY_SEC_BCR] = { 0x12004 }, + [BLSP1_BCR] = { 0x17000 }, + [BLSP2_BCR] = { 0x25000 }, + [BOOT_ROM_BCR] = { 0x38000 }, + [PRNG_BCR] = { 0x34000 }, + [UFS_BCR] = { 0x75000 }, + [USB_30_BCR] = { 0x0f000 }, + [USB3_PHY_BCR] = { 0x50020 }, + [USB3PHY_PHY_BCR] = { 0x50024 }, + [PCIE_0_PHY_BCR] = { 0x6c01c }, + [PCIE_PHY_BCR] = { 0x6f000 }, + [PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00C }, + [PCIE_PHY_COM_BCR] = { 0x6f014 }, +}; + static void msm_gcc_cobalt_v1_fixup(void) { gcc_ufs_rx_symbol_1_clk.c.ops = &clk_ops_dummy; @@ -2800,6 +2818,10 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev) clk_set_flags(&gcc_gpu_bimc_gfx_clk.c, CLKFLAG_RETAIN_MEM); + /* Register block resets */ + msm_reset_controller_register(pdev, gcc_cobalt_resets, + ARRAY_SIZE(gcc_cobalt_resets), virt_base); + dev_info(&pdev->dev, "Registered GCC clocks\n"); return 0; } diff --git a/drivers/clk/msm/clock-mmss-cobalt.c b/drivers/clk/msm/clock-mmss-cobalt.c index bbb9af961235..fbd83a02aa02 100644 --- a/drivers/clk/msm/clock-mmss-cobalt.c +++ b/drivers/clk/msm/clock-mmss-cobalt.c @@ -30,6 +30,7 @@ #include <dt-bindings/clock/msm-clocks-hwio-cobalt.h> #include "vdd-level-cobalt.h" +#include "reset.h" static void __iomem *virt_base; @@ -2637,6 +2638,10 @@ static struct clk_lookup msm_clocks_mmss_cobalt[] = { CLK_LIST(mmss_debug_mux), }; +static const struct msm_reset_map mmss_cobalt_resets[] = { + [CAMSS_MICRO_BCR] = { 0x3490 }, +}; + static void msm_mmsscc_hamster_fixup(void) { mmpll3_pll.c.rate = 1066000000; @@ -2838,6 +2843,10 @@ int msm_mmsscc_cobalt_probe(struct platform_device *pdev) if (rc) return rc; + /* Register block resets */ + msm_reset_controller_register(pdev, mmss_cobalt_resets, + ARRAY_SIZE(mmss_cobalt_resets), virt_base); + dev_info(&pdev->dev, "Registered MMSS clocks.\n"); return 0; } diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h index b411a0be4e67..f366d526c138 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-cobalt.h @@ -500,4 +500,23 @@ #define clk_audio_pmi_clk 0xcbfe416d #define clk_audio_ap_clk2 0x454d1e91 +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_30_BCR 7 +#define USB3_PHY_BCR 8 +#define USB3PHY_PHY_BCR 9 +#define PCIE_0_PHY_BCR 10 +#define PCIE_PHY_BCR 11 +#define PCIE_PHY_COM_BCR 12 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 13 + +/* MMSS block resets */ +#define CAMSS_MICRO_BCR 0 + #endif |