diff options
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi | 77 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmtriton.dtsi | 23 |
3 files changed, 101 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index 2623a65a4bc2..572a896ad795 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -1007,7 +1007,7 @@ <0x10b4000 0x800>; reg-names = "dcc-base", "dcc-ram-base"; - clocks = <&clock_rpmcc GCC_DCC_AHB_CLK>; + clocks = <&clock_gcc GCC_DCC_AHB_CLK>; clock-names = "dcc_clk"; }; diff --git a/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi b/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi new file mode 100644 index 000000000000..017483c36866 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi @@ -0,0 +1,77 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msmfalcon-coresight.dtsi" + +&etm0 { + cpu = <&CPU4>; +}; + +&etm1 { + cpu = <&CPU5>; +}; + +&etm2 { + cpu = <&CPU6>; +}; + +&etm3 { + cpu = <&CPU7>; +}; + +&etm4 { + cpu = <&CPU0>; +}; + +&etm5 { + cpu = <&CPU1>; +}; + +&etm6 { + cpu = <&CPU2>; +}; + +&etm7 { + cpu = <&CPU3>; +}; + +&cti_cpu0 { + cpu = <&CPU4>; +}; + +&cti_cpu1 { + cpu = <&CPU5>; +}; + +&cti_cpu2 { + cpu = <&CPU6>; +}; + +&cti_cpu3 { + cpu = <&CPU7>; +}; + +&cti_cpu4 { + cpu = <&CPU0>; +}; + +&cti_cpu5 { + cpu = <&CPU1>; +}; + +&cti_cpu6 { + cpu = <&CPU2>; +}; + +&cti_cpu7 { + cpu = <&CPU3>; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index 2551d7f0f849..dfa592c16643 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -304,6 +304,7 @@ }; #include "msmtriton-smp2p.dtsi" +#include "msmtriton-coresight.dtsi" &soc { #address-cells = <1>; #size-cells = <1>; @@ -448,6 +449,18 @@ qcom,sensors = <12>; }; + wdog: qcom,wdt@17817000 { + status = "disabled"; + compatible = "qcom,msm-watchdog"; + reg = <0x17817000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + uartblsp1dm1: serial@0c170000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xc170000 0x1000>; @@ -603,6 +616,16 @@ qcom,mpu-enabled; }; + dcc: dcc@10b3000 { + compatible = "qcom,dcc"; + reg = <0x10b3000 0x1000>, + <0x10b4000 0x800>; + reg-names = "dcc-base", "dcc-ram-base"; + + clocks = <&clock_gcc GCC_DCC_AHB_CLK>; + clock-names = "dcc_clk"; + }; + qcom,glink-smem-native-xprt-modem@86000000 { compatible = "qcom,glink-smem-native-xprt"; reg = <0x86000000 0x200000>, |