diff options
| -rw-r--r-- | include/dt-bindings/clock/qcom,gcc-msmfalcon.h | 243 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,gpu-msmfalcon.h | 38 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,mmcc-msmfalcon.h | 194 |
3 files changed, 475 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h new file mode 100644 index 000000000000..d0a8419ee54c --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_FALCON_H +#define _DT_BINDINGS_CLK_MSM_GCC_FALCON_H + +/* Clocks */ +#define GPLL0 0 +#define GPLL1 1 +#define GPLL2 2 +#define GPLL3 3 +#define GPLL4 4 +#define GPLL5 5 +#define GPLL6 6 +#define MMSS_QM_CORE_CLK_SRC 7 +#define USB30_MASTER_CLK_SRC 8 +#define USB30_MOCK_UTMI_CLK_SRC 9 +#define USB3_PHY_AUX_CLK_SRC 10 +#define USB20_MASTER_CLK_SRC 11 +#define USB20_MOCK_UTMI_CLK_SRC 12 +#define SDCC2_APPS_CLK_SRC 13 +#define SDCC1_ICE_CORE_CLK_SRC 14 +#define SDCC1_APPS_CLK_SRC 15 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 16 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 17 +#define BLSP1_UART1_APPS_CLK_SRC 18 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 20 +#define BLSP1_UART2_APPS_CLK_SRC 21 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 22 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 23 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 24 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 25 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 26 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 27 +#define BLSP2_UART1_APPS_CLK_SRC 28 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 29 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 30 +#define BLSP2_UART2_APPS_CLK_SRC 31 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 32 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 33 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 34 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 35 +#define PDM2_CLK_SRC 36 +#define HMSS_AHB_CLK_SRC 37 +#define BIMC_HMSS_AXI_CLK_SRC 38 +#define HMSS_RBCPR_CLK_SRC 39 +#define HMSS_GPLL0_CLK_SRC 40 +#define HMSS_GPLL4_CLK_SRC 41 +#define GP1_CLK_SRC 42 +#define GP2_CLK_SRC 43 +#define GP3_CLK_SRC 44 +#define UFS_AXI_CLK_SRC 45 +#define UFS_ICE_CORE_CLK_SRC 46 +#define UFS_UNIPRO_CORE_CLK_SRC 47 +#define UFS_PHY_AUX_CLK_SRC 48 +#define QSPI_SER_CLK_SRC 49 +#define GLM_CLK_SRC 50 +#define GCC_MMSS_SYS_NOC_AXI_CLK 51 +#define GCC_MMSS_NOC_CFG_AHB_CLK 52 +#define GCC_MMSS_QM_CORE_CLK 53 +#define GCC_MMSS_QM_AHB_CLK 54 +#define GCC_USB30_MASTER_CLK 55 +#define GCC_USB30_SLEEP_CLK 56 +#define GCC_USB30_MOCK_UTMI_CLK 57 +#define GCC_USB3_PHY_AUX_CLK 58 +#define GCC_USB3_PHY_PIPE_CLK 59 +#define GCC_USB20_MASTER_CLK 60 +#define GCC_USB20_SLEEP_CLK 61 +#define GCC_USB20_MOCK_UTMI_CLK 62 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 63 +#define GCC_SDCC2_APPS_CLK 64 +#define GCC_SDCC2_AHB_CLK 65 +#define GCC_SDCC1_APPS_CLK 66 +#define GCC_SDCC1_AHB_CLK 67 +#define GCC_SDCC1_ICE_CORE_CLK 68 +#define GCC_BLSP1_AHB_CLK 69 +#define GCC_BLSP1_SLEEP_CLK 70 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 71 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 72 +#define GCC_BLSP1_UART1_APPS_CLK 73 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 74 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 75 +#define GCC_BLSP1_UART2_APPS_CLK 76 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 77 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 78 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 79 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 80 +#define GCC_BLSP2_AHB_CLK 81 +#define GCC_BLSP2_SLEEP_CLK 82 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 83 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 84 +#define GCC_BLSP2_UART1_APPS_CLK 85 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 86 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 87 +#define GCC_BLSP2_UART2_APPS_CLK 88 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 89 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 90 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 91 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 92 +#define GCC_PDM_AHB_CLK 93 +#define GCC_PDM_XO4_CLK 94 +#define GCC_PDM2_CLK 95 +#define GCC_PRNG_AHB_CLK 96 +#define GCC_BIMC_GFX_CLK 97 +#define GCC_MCCC_CFG_AHB_CLK 98 +#define GCC_LPASS_TRIG_CLK 99 +#define GCC_LPASS_AT_CLK 100 +#define GCC_TURING_TRIG_CLK 101 +#define GCC_TURING_AT_CLK 102 +#define GCC_HMSS_AHB_CLK 103 +#define GCC_BIMC_HMSS_AXI_CLK 104 +#define GCC_HMSS_RBCPR_CLK 105 +#define GCC_HMSS_TRIG_CLK 106 +#define GCC_HMSS_AT_CLK 107 +#define GCC_HMSS_DVM_BUS_CLK 108 +#define GCC_GP1_CLK 109 +#define GCC_GP2_CLK 110 +#define GCC_GP3_CLK 111 +#define GCC_UFS_AXI_CLK 112 +#define GCC_UFS_AHB_CLK 113 +#define GCC_UFS_TX_SYMBOL_0_CLK 114 +#define GCC_UFS_RX_SYMBOL_0_CLK 115 +#define GCC_UFS_UNIPRO_CORE_CLK 116 +#define GCC_UFS_ICE_CORE_CLK 117 +#define GCC_UFS_PHY_AUX_CLK 118 +#define GCC_UFS_RX_SYMBOL_1_CLK 119 +#define GCC_AGGRE2_USB3_AXI_CLK 120 +#define GCC_AGGRE2_UFS_AXI_CLK 121 +#define GCC_QSPI_AHB_CLK 122 +#define GCC_QSPI_SER_CLK 123 +#define GCC_GLM_AHB_CLK 124 +#define GCC_GLM_CLK 125 +#define GCC_GLM_XO_CLK 126 +#define GCC_WCSS_AHB_S0_CLK 127 +#define GCC_WCSS_AXI_M_CLK 128 +#define GCC_WCSS_ECAHB_CLK 129 +#define GCC_WCSS_SHDREG_AHB_CLK 130 +#define GCC_GPU_CFG_AHB_CLK 131 +#define GCC_GPU_BIMC_GFX_SRC_CLK 132 +#define GCC_GPU_BIMC_GFX_CLK 133 +#define GCC_GPU_SNOC_DVM_GFX_CLK 134 + +/* Block Resets */ +#define GCC_SYSTEM_NOC_BCR 0 +#define GCC_CONFIG_NOC_BCR 1 +#define GCC_IMEM_BCR 2 +#define GCC_MMSS_BCR 3 +#define GCC_PIMEM_BCR 4 +#define GCC_QDSS_BCR 5 +#define GCC_USB_30_BCR 6 +#define GCC_USB_20_BCR 7 +#define GCC_QUSB2PHY_PRIM_BCR 8 +#define GCC_QUSB2PHY_SEC_BCR 9 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 +#define GCC_SDCC2_BCR 11 +#define GCC_SDCC1_BCR 12 +#define GCC_BLSP1_BCR 13 +#define GCC_BLSP1_QUP1_BCR 14 +#define GCC_BLSP1_UART1_BCR 15 +#define GCC_BLSP1_QUP2_BCR 16 +#define GCC_BLSP1_UART2_BCR 17 +#define GCC_BLSP1_QUP3_BCR 18 +#define GCC_BLSP1_QUP4_BCR 19 +#define GCC_BLSP2_BCR 20 +#define GCC_BLSP2_QUP1_BCR 21 +#define GCC_BLSP2_UART1_BCR 22 +#define GCC_BLSP2_QUP2_BCR 23 +#define GCC_BLSP2_UART2_BCR 24 +#define GCC_BLSP2_QUP3_BCR 25 +#define GCC_BLSP2_QUP4_BCR 26 +#define GCC_PDM_BCR 27 +#define GCC_PRNG_BCR 28 +#define GCC_TCSR_BCR 29 +#define GCC_BOOT_ROM_BCR 30 +#define GCC_MSG_RAM_BCR 31 +#define GCC_TLMM_BCR 32 +#define GCC_MPM_BCR 33 +#define GCC_SEC_CTRL_BCR 34 +#define GCC_SPMI_BCR 35 +#define GCC_SPDM_BCR 36 +#define GCC_CE1_BCR 37 +#define GCC_BIMC_BCR 38 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 40 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 41 +#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 42 +#define GCC_SNOC_BUS_TIMEOUT4_BCR 43 +#define GCC_PNOC_BUS_TIMEOUT0_BCR 44 +#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 45 +#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 46 +#define GCC_CNOC_BUS_TIMEOUT0_BCR 47 +#define GCC_CNOC_BUS_TIMEOUT2_BCR 48 +#define GCC_CNOC_BUS_TIMEOUT3_BCR 49 +#define GCC_CNOC_BUS_TIMEOUT4_BCR 50 +#define GCC_CNOC_BUS_TIMEOUT5_BCR 51 +#define GCC_CNOC_BUS_TIMEOUT6_BCR 52 +#define GCC_CNOC_BUS_TIMEOUT7_BCR 53 +#define GCC_CNOC_BUS_TIMEOUT8_BCR 54 +#define GCC_CNOC_BUS_TIMEOUT9_BCR 55 +#define GCC_CNOC_BUS_TIMEOUT10_BCR 56 +#define GCC_CNOC_BUS_TIMEOUT11_BCR 57 +#define GCC_CNOC_BUS_TIMEOUT12_BCR 58 +#define GCC_CNOC_BUS_TIMEOUT13_BCR 59 +#define GCC_CNOC_BUS_TIMEOUT14_BCR 60 +#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 61 +#define GCC_APB2JTAG_BCR 62 +#define GCC_RBCPR_CX_BCR 63 +#define GCC_RBCPR_MX_BCR 64 +#define GCC_OBT_ODT_BCR 65 +#define GCC_UFS_BCR 66 +#define GCC_VS_BCR 67 +#define GCC_AGGRE2_NOC_BCR 68 +#define GCC_DCC_BCR 69 +#define GCC_QSPI_BCR 70 +#define GCC_IPA_BCR 71 +#define GCC_GLM_BCR 72 +#define GCC_MSMPU_BCR 73 +#define GCC_QREFS_VBG_CAL_BCR 74 +#define GCC_WCSS_BCR 75 +#define GCC_GPU_BCR 76 +#define GCC_AHB2PHY_EAST_BCR 77 +#define GCC_CM_PHY_REFGEN1_BCR 78 +#define GCC_CM_PHY_REFGEN2_BCR 79 +#define GCC_SRAM_SENSOR_BCR 80 + +/* GDSC */ +#define UFS_GDSC 0 +#define USB_30_GDSC 1 +#define DDR_DIM_WRAPPER_GDSC 2 +#define MMSS_GDSC 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h b/include/dt-bindings/clock/qcom,gpu-msmfalcon.h new file mode 100644 index 000000000000..a167716e9cc6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpu-msmfalcon.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GPU_FALCON_H +#define _DT_BINDINGS_CLK_MSM_GPU_FALCON_H + +/* Clocks */ +#define GPU_PLL0_PLL 0 +#define GPU_PLL1_PLL 1 +#define GFX3D_CLK_SRC 2 +#define RBBMTIMER_CLK_SRC 3 +#define RBCPR_CLK_SRC 4 +#define GPUCC_CXO_CLK 5 +#define GPUCC_GFX3D_CLK 6 +#define GPUCC_RBBMTIMER_CLK 7 +#define GPUCC_RBCPR_CLK 8 + +/* Block Reset */ +#define GPU_CC_GPU_GX_BCR 0 +#define GPU_CC_GPU_CX_BCR 1 +#define GPU_CC_RBCPR_BCR 2 +#define GPU_CC_SPDM_BCR 3 + +/* GDSC */ +#define GPU_GX_GDSC 0 +#define GPU_CX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h new file mode 100644 index 000000000000..57aed7c8f43f --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H +#define _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H + +/* Clocks */ +#define MMPLL3_PLL 0 +#define MMPLL4_PLL 1 +#define MMPLL5_PLL 2 +#define MMPLL6_PLL 3 +#define MMPLL7_PLL 4 +#define MMPLL8_PLL 5 +#define AHB_CLK_SRC 6 +#define VIDEO_CORE_CLK_SRC 7 +#define PCLK0_CLK_SRC 8 +#define PCLK1_CLK_SRC 9 +#define MDP_CLK_SRC 10 +#define ROT_CLK_SRC 11 +#define VSYNC_CLK_SRC 12 +#define BYTE0_CLK_SRC 13 +#define BYTE1_CLK_SRC 14 +#define ESC0_CLK_SRC 15 +#define ESC1_CLK_SRC 16 +#define DP_LINK_CLK_SRC 17 +#define DP_CRYPTO_CLK_SRC 18 +#define DP_PIXEL_CLK_SRC 19 +#define DP_AUX_CLK_SRC 20 +#define DP_GTC_CLK_SRC 21 +#define CAMSS_GP0_CLK_SRC 22 +#define CAMSS_GP1_CLK_SRC 23 +#define MCLK0_CLK_SRC 24 +#define MCLK1_CLK_SRC 25 +#define MCLK2_CLK_SRC 26 +#define MCLK3_CLK_SRC 27 +#define CCI_CLK_SRC 28 +#define CSI0PHYTIMER_CLK_SRC 29 +#define CSI1PHYTIMER_CLK_SRC 30 +#define CSI2PHYTIMER_CLK_SRC 31 +#define JPEG0_CLK_SRC 32 +#define VFE0_CLK_SRC 33 +#define VFE1_CLK_SRC 34 +#define CPP_CLK_SRC 35 +#define CSIPHY_CLK_SRC 36 +#define CSI0_CLK_SRC 37 +#define CSI1_CLK_SRC 38 +#define CSI2_CLK_SRC 39 +#define CSI3_CLK_SRC 40 +#define MMSS_CXO_CLK 41 +#define MMSS_SLEEP_CLK 42 +#define MMSS_MNOC_AHB_CLK 43 +#define MMSS_MISC_AHB_CLK 44 +#define MMSS_MISC_CXO_CLK 45 +#define MMSS_BIMC_SMMU_AHB_CLK 46 +#define MMSS_BIMC_SMMU_AXI_CLK 47 +#define MMSS_SNOC_DVM_AXI_CLK 48 +#define MMSS_THROTTLE_CAMSS_CXO_CLK 49 +#define MMSS_THROTTLE_CAMSS_AHB_CLK 50 +#define MMSS_THROTTLE_CAMSS_AXI_CLK 51 +#define MMSS_THROTTLE_MDSS_CXO_CLK 52 +#define MMSS_THROTTLE_MDSS_AHB_CLK 53 +#define MMSS_THROTTLE_MDSS_AXI_CLK 54 +#define MMSS_THROTTLE_VIDEO_CXO_CLK 55 +#define MMSS_THROTTLE_VIDEO_AHB_CLK 56 +#define MMSS_THROTTLE_VIDEO_AXI_CLK 57 +#define MMSS_VIDEO_CORE_CLK 58 +#define MMSS_VIDEO_AXI_CLK 59 +#define MMSS_VIDEO_AHB_CLK 60 +#define MMSS_MDSS_AHB_CLK 61 +#define MMSS_MDSS_HDMI_DP_AHB_CLK 62 +#define MMSS_MDSS_PCLK0_CLK 63 +#define MMSS_MDSS_PCLK1_CLK 64 +#define MMSS_MDSS_VSYNC_CLK 65 +#define MMSS_MDSS_BYTE0_CLK 66 +#define MMSS_MDSS_BYTE0_INTF_CLK 67 +#define MMSS_MDSS_BYTE1_CLK 68 +#define MMSS_MDSS_BYTE1_INTF_CLK 69 +#define MMSS_MDSS_ESC0_CLK 70 +#define MMSS_MDSS_ESC1_CLK 71 +#define MMSS_MDSS_DP_LINK_CLK 72 +#define MMSS_MDSS_DP_LINK_INTF_CLK 73 +#define MMSS_MDSS_DP_CRYPTO_CLK 74 +#define MMSS_MDSS_DP_PIXEL_CLK 75 +#define MMSS_MDSS_DP_AUX_CLK 76 +#define MMSS_MDSS_DP_GTC_CLK 77 +#define MMSS_CAMSS_TOP_AHB_CLK 78 +#define MMSS_CAMSS_AHB_CLK 79 +#define MMSS_CAMSS_GP0_CLK 80 +#define MMSS_CAMSS_GP1_CLK 81 +#define MMSS_CAMSS_MCLK0_CLK 82 +#define MMSS_CAMSS_MCLK1_CLK 83 +#define MMSS_CAMSS_MCLK2_CLK 84 +#define MMSS_CAMSS_MCLK3_CLK 85 +#define MMSS_CAMSS_CCI_CLK 86 +#define MMSS_CAMSS_CCI_AHB_CLK 87 +#define MMSS_CAMSS_CSI0PHYTIMER_CLK 88 +#define MMSS_CAMSS_CSI1PHYTIMER_CLK 89 +#define MMSS_CAMSS_CSI2PHYTIMER_CLK 90 +#define MMSS_CAMSS_JPEG_AHB_CLK 91 +#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 92 +#define MMSS_CAMSS_VFE0_STREAM_CLK 93 +#define MMSS_CAMSS_VFE0_AHB_CLK 94 +#define MMSS_CAMSS_VFE1_STREAM_CLK 95 +#define MMSS_CAMSS_VFE1_AHB_CLK 96 +#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 97 +#define MMSS_CAMSS_CPP_AHB_CLK 98 +#define MMSS_CAMSS_CSIPHY0_CLK 99 +#define MMSS_CAMSS_CSIPHY1_CLK 100 +#define MMSS_CAMSS_CSIPHY2_CLK 101 +#define MMSS_CSIPHY_AHB2CRIF_CLK 102 +#define MMSS_CAMSS_CSI0_CLK 103 +#define MMSS_CAMSS_CPHY_CSID0_CLK 104 +#define MMSS_CAMSS_CSI0_AHB_CLK 105 +#define MMSS_CAMSS_CSI0RDI_CLK 106 +#define MMSS_CAMSS_CSI0PIX_CLK 107 +#define MMSS_CAMSS_CSI1_CLK 108 +#define MMSS_CAMSS_CPHY_CSID1_CLK 109 +#define MMSS_CAMSS_CSI1_AHB_CLK 110 +#define MMSS_CAMSS_CSI1RDI_CLK 111 +#define MMSS_CAMSS_CSI1PIX_CLK 112 +#define MMSS_CAMSS_CSI2_CLK 113 +#define MMSS_CAMSS_CPHY_CSID2_CLK 114 +#define MMSS_CAMSS_CSI2_AHB_CLK 115 +#define MMSS_CAMSS_CSI2RDI_CLK 116 +#define MMSS_CAMSS_CSI2PIX_CLK 117 +#define MMSS_CAMSS_CSI3_CLK 118 +#define MMSS_CAMSS_CPHY_CSID3_CLK 119 +#define MMSS_CAMSS_CSI3_AHB_CLK 120 +#define MMSS_CAMSS_CSI3RDI_CLK 121 +#define MMSS_CAMSS_CSI3PIX_CLK 122 +#define MMSS_CAMSS_ISPIF_AHB_CLK 123 + +/* Block Resets */ +#define MMSS_MNOCAHB_BCR 0 +#define MMSS_MISC_BCR 1 +#define MMSS_BTO_BCR 2 +#define MMSS_MNOCAXI_BCR 3 +#define MMSS_BIMC_SMMU_BCR 4 +#define MMSS_THROTTLE_CAMSS_BCR 5 +#define MMSS_THROTTLE_MDSS_BCR 6 +#define MMSS_THROTTLE_VIDEO_BCR 7 +#define MMSS_VIDEO_TOP_BCR 8 +#define MMSS_MDSS_BCR 9 +#define MMSS_CAMSS_TOP_BCR 10 +#define MMSS_CAMSS_AHB_BCR 11 +#define MMSS_CAMSS_MICRO_BCR 12 +#define MMSS_CAMSS_CCI_BCR 13 +#define MMSS_CAMSS_PHY0_BCR 14 +#define MMSS_CAMSS_PHY1_BCR 15 +#define MMSS_CAMSS_PHY2_BCR 16 +#define MMSS_CAMSS_JPEG_BCR 17 +#define MMSS_CAMSS_VFE_VBIF_BCR 18 +#define MMSS_CAMSS_VFE0_BCR 19 +#define MMSS_CAMSS_VFE1_BCR 20 +#define MMSS_CAMSS_CSI_VFE0_BCR 21 +#define MMSS_CAMSS_CSI_VFE1_BCR 22 +#define MMSS_CAMSS_CPP_TOP_BCR 23 +#define MMSS_CAMSS_CPP_BCR 24 +#define MMSS_CAMSS_CSIPHY_BCR 25 +#define MMSS_CAMSS_CSI0_BCR 26 +#define MMSS_CAMSS_CSI0RDI_BCR 27 +#define MMSS_CAMSS_CSI0PIX_BCR 28 +#define MMSS_CAMSS_CSI1_BCR 29 +#define MMSS_CAMSS_CSI1RDI_BCR 30 +#define MMSS_CAMSS_CSI1PIX_BCR 31 +#define MMSS_CAMSS_CSI2_BCR 32 +#define MMSS_CAMSS_CSI2RDI_BCR 33 +#define MMSS_CAMSS_CSI2PIX_BCR 34 +#define MMSS_CAMSS_CSI3_BCR 35 +#define MMSS_CAMSS_CSI3RDI_BCR 36 +#define MMSS_CAMSS_CSI3PIX_BCR 37 +#define MMSS_CAMSS_ISPIF_BCR 38 + +/* GDSC */ +#define VIDEO_TOP_GDSC 0 +#define VIDEO_SUBCORE0_GDSC 1 +#define CAMSS_VFE0_GDSC 2 +#define BIMC_SMMU_GDSC 3 +#define CAMSS_TOP_GDSC 4 +#define MDSS_GDSC 5 +#define CAMSS_CPP_GDSC 6 +#define CAMSS_VFE1_GDSC 7 + +#endif |