diff options
Diffstat (limited to 'arch/arm/mach-mx2/pcm038.c')
| -rw-r--r-- | arch/arm/mach-mx2/pcm038.c | 82 |
1 files changed, 62 insertions, 20 deletions
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c index 7f55746e2591..dfd4156da7d5 100644 --- a/arch/arm/mach-mx2/pcm038.c +++ b/arch/arm/mach-mx2/pcm038.c @@ -19,6 +19,7 @@ #include <linux/platform_device.h> #include <linux/mtd/physmap.h> +#include <linux/mtd/plat-ram.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/common.h> @@ -27,10 +28,36 @@ #include <asm/mach/time.h> #include <mach/imx-uart.h> #include <mach/board-pcm038.h> +#include <mach/mxc_nand.h> #include "devices.h" /* + * Phytec's PCM038 comes with 2MiB battery buffered SRAM, + * 16 bit width + */ + +static struct platdata_mtd_ram pcm038_sram_data = { + .bankwidth = 2, +}; + +static struct resource pcm038_sram_resource = { + .start = CS1_BASE_ADDR, + .end = CS1_BASE_ADDR + 512 * 1024 - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device pcm038_sram_mtd_device = { + .name = "mtd-ram", + .id = 0, + .dev = { + .platform_data = &pcm038_sram_data, + }, + .num_resources = 1, + .resource = &pcm038_sram_resource, +}; + +/* * Phytec's phyCORE-i.MX27 comes with 32MiB flash, * 16 bit width */ @@ -64,15 +91,14 @@ static int mxc_uart0_pins[] = { static int uart_mxc_port0_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART0"); + ARRAY_SIZE(mxc_uart0_pins), "UART0"); } static int uart_mxc_port0_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART0"); + mxc_gpio_release_multiple_pins(mxc_uart0_pins, + ARRAY_SIZE(mxc_uart0_pins)); + return 0; } static int mxc_uart1_pins[] = { @@ -85,15 +111,14 @@ static int mxc_uart1_pins[] = { static int uart_mxc_port1_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART1"); + ARRAY_SIZE(mxc_uart1_pins), "UART1"); } static int uart_mxc_port1_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART1"); + mxc_gpio_release_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins)); + return 0; } static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS, @@ -104,15 +129,14 @@ static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS, static int uart_mxc_port2_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART2"); + ARRAY_SIZE(mxc_uart2_pins), "UART2"); } static int uart_mxc_port2_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART2"); + mxc_gpio_release_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins)); + return 0; } static struct imxuart_platform_data uart_pdata[] = { @@ -155,29 +179,47 @@ static int mxc_fec_pins[] = { static void gpio_fec_active(void) { mxc_gpio_setup_multiple_pins(mxc_fec_pins, - ARRAY_SIZE(mxc_fec_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "FEC"); + ARRAY_SIZE(mxc_fec_pins), "FEC"); } static void gpio_fec_inactive(void) { - mxc_gpio_setup_multiple_pins(mxc_fec_pins, - ARRAY_SIZE(mxc_fec_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "FEC"); + mxc_gpio_release_multiple_pins(mxc_fec_pins, + ARRAY_SIZE(mxc_fec_pins)); } +static struct mxc_nand_platform_data pcm038_nand_board_info = { + .width = 1, + .hw_ecc = 1, +}; + static struct platform_device *platform_devices[] __initdata = { &pcm038_nor_mtd_device, + &mxc_w1_master_device, + &pcm038_sram_mtd_device, }; +/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and + * setup other stuffs to access the sram. */ +static void __init pcm038_init_sram(void) +{ + __raw_writel(0x0000d843, CSCR_U(1)); + __raw_writel(0x22252521, CSCR_L(1)); + __raw_writel(0x22220a00, CSCR_A(1)); +} + static void __init pcm038_init(void) { gpio_fec_active(); + pcm038_init_sram(); mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); + mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */ + mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); #ifdef CONFIG_MACH_PCM970_BASEBOARD |