diff options
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 8 | ||||
| -rw-r--r-- | arch/mips/kernel/traps.c | 6 |
2 files changed, 6 insertions, 8 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 97c03865c06a..dde2adf1481c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -746,14 +746,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) { decode_configs(c); - /* - * For historical reasons the SB1 comes with it's own variant of - * cache code which eventually will be folded into c-r4k.c. Until - * then we pretend it's got it's own cache architecture. - */ - c->options &= ~MIPS_CPU_4K_CACHE; - c->options |= MIPS_CPU_SB1_CACHE; - switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 3d033e1cd4f0..d96f8218a91e 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1435,6 +1435,9 @@ void __init set_handler (unsigned long offset, void *addr, unsigned long size) flush_icache_range(ebase + offset, ebase + offset + size); } +static char panic_null_cerr[] __initdata = + "Trying to set NULL cache error exception handler"; + /* Install uncached CPU exception handler */ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) { @@ -1445,6 +1448,9 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon unsigned long uncached_ebase = TO_UNCAC(ebase); #endif + if (!addr) + panic(panic_null_cerr); + memcpy((void *)(uncached_ebase + offset), addr, size); } |