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-rw-r--r--arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-cmd.dtsi64
-rw-r--r--arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-video.dtsi60
-rw-r--r--arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi3
-rw-r--r--arch/arm/boot/dts/qcom/msm8996-camera.dtsi4
-rw-r--r--arch/arm/boot/dts/qcom/msm8996.dtsi54
-rw-r--r--arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi2
-rw-r--r--arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi7
-rw-r--r--arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi7
-rw-r--r--arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi7
-rw-r--r--arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi26
-rw-r--r--arch/arm/boot/dts/qcom/msmcobalt.dtsi14
-rw-r--r--arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi1217
-rw-r--r--arch/arm/boot/dts/qcom/msmfalcon.dtsi8
-rw-r--r--arch/arm64/configs/msmcortex-perf_defconfig3
-rw-r--r--arch/arm64/configs/msmcortex_defconfig2
15 files changed, 1385 insertions, 93 deletions
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-cmd.dtsi
index 57c6301f2074..95a8e80ccdbd 100644
--- a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-cmd.dtsi
+++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-cmd.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -53,41 +53,41 @@
qcom,ulps-enabled;
qcom,adjust-timer-wakeup-ms = <1>;
- qcom,mdss-dsi-on-command = [15 01 00 00 0a 00 02 ff 10
- 15 01 00 00 0a 00 02 fb 01
- 15 01 00 00 0a 00 02 ba 03
- 15 01 00 00 0a 00 02 e5 01
- 15 01 00 00 0a 00 02 b0 03
- 15 01 00 00 0a 00 02 ff 28
- 15 01 00 00 0a 00 02 7a 02
- 15 01 00 00 0a 00 02 fb 01
- 15 01 00 00 0a 00 02 ff 10
- 15 01 00 00 0a 00 02 fb 01
- 15 01 00 00 0a 00 02 c0 03
- 15 01 00 00 0a 00 02 bb 10
- 15 01 00 00 0a 00 02 ff e0
- 15 01 00 00 0a 00 02 fb 01
- 15 01 00 00 0a 00 02 6b 3d
- 15 01 00 00 0a 00 02 6c 3d
- 15 01 00 00 0a 00 02 6d 3d
- 15 01 00 00 0a 00 02 6e 3d
- 15 01 00 00 0a 00 02 6f 3d
- 15 01 00 00 0a 00 02 35 02
- 15 01 00 00 0a 00 02 36 72
- 15 01 00 00 0a 00 02 37 10
- 15 01 00 00 0a 00 02 08 c0
- 15 01 00 00 0a 00 02 ff 24
- 15 01 00 00 0a 00 02 fb 01
- 15 01 00 00 0a 00 02 c6 06
- 15 01 00 00 0a 00 02 ff 10
- 05 01 00 00 f0 00 01 11
- 05 01 00 00 f0 00 01 29
+ qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 ba 03
+ 15 01 00 00 00 00 02 e5 01
+ 15 01 00 00 00 00 02 b0 03
+ 15 01 00 00 00 00 02 ff 28
+ 15 01 00 00 00 00 02 7a 02
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 c0 03
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 ff e0
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 6b 3d
+ 15 01 00 00 00 00 02 6c 3d
+ 15 01 00 00 00 00 02 6d 3d
+ 15 01 00 00 00 00 02 6e 3d
+ 15 01 00 00 00 00 02 6f 3d
+ 15 01 00 00 00 00 02 35 02
+ 15 01 00 00 00 00 02 36 72
+ 15 01 00 00 00 00 02 37 10
+ 15 01 00 00 00 00 02 08 c0
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 c6 06
+ 15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 a0 00 01 11
+ 05 01 00 00 00 00 01 29
07 01 00 00 0a 00 02 01 00];
qcom,mdss-dsi-post-panel-on-command = [05 01 00 00 a0 00 01 29];
- qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00
- 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00
+ 05 01 00 00 0a 00 02 10 00];
qcom,compression-mode = "dsc";
qcom,config-select = <&dsi_nt35597_dsc_cmd_config2>;
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-video.dtsi
index 1c515f506e9d..fd11be721dbb 100644
--- a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-video.dtsi
+++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dsc-wqxga-video.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -30,37 +30,37 @@
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
- qcom,mdss-dsi-on-command = [15 01 00 00 0a 00 02 ff 10
- 15 01 00 00 0a 00 02 fb 01
- 15 01 00 00 0a 00 02 ba 03
- 15 01 00 00 0a 00 02 e5 01
- 15 01 00 00 0a 00 02 b0 03
- 39 01 00 00 0a 00 06 3B 03 08 08 2e 64
- 15 01 00 00 0a 00 02 ff 28
- 15 01 00 00 0a 00 02 7a 02
- 15 01 00 00 0a 00 02 fb 01
- 15 01 00 00 0a 00 02 ff 10
- 15 01 00 00 0a 00 02 fb 01
- 15 01 00 00 0a 00 02 c0 03
- 15 01 00 00 0a 00 02 bb 03
- 15 01 00 00 0a 00 02 ff e0
- 15 01 00 00 0a 00 02 fb 01
- 15 01 00 00 0a 00 02 6b 3d
- 15 01 00 00 0a 00 02 6c 3d
- 15 01 00 00 0a 00 02 6d 3d
- 15 01 00 00 0a 00 02 6e 3d
- 15 01 00 00 0a 00 02 6f 3d
- 15 01 00 00 0a 00 02 35 02
- 15 01 00 00 0a 00 02 36 72
- 15 01 00 00 0a 00 02 37 10
- 15 01 00 00 0a 00 02 08 c0
- 15 01 00 00 0a 00 02 ff 10
+ qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 ba 03
+ 15 01 00 00 00 00 02 e5 01
+ 15 01 00 00 00 00 02 b0 03
+ 39 01 00 00 00 00 06 3B 03 08 08 2e 64
+ 15 01 00 00 00 00 02 ff 28
+ 15 01 00 00 00 00 02 7a 02
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 c0 03
+ 15 01 00 00 00 00 02 bb 03
+ 15 01 00 00 00 00 02 ff e0
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 6b 3d
+ 15 01 00 00 00 00 02 6c 3d
+ 15 01 00 00 00 00 02 6d 3d
+ 15 01 00 00 00 00 02 6e 3d
+ 15 01 00 00 00 00 02 6f 3d
+ 15 01 00 00 00 00 02 35 02
+ 15 01 00 00 00 00 02 36 72
+ 15 01 00 00 00 00 02 37 10
+ 15 01 00 00 00 00 02 08 c0
+ 15 01 00 00 00 00 02 ff 10
05 01 00 00 a0 00 01 11
- 05 01 00 00 a0 00 01 29
- 07 01 00 00 a0 00 01 01];
+ 05 01 00 00 00 00 01 29
+ 07 01 00 00 0a 00 01 01];
- qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00
- 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00
+ 05 01 00 00 0a 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
index 5aa4974ded2f..a7861e96d3e2 100644
--- a/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
+++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -16,7 +16,6 @@
"sharp 1080p 120hz dual dsi cmd mode panel";
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
qcom,mdss-dsi-panel-framerate = <120>;
- qcom,mdss-dsi-panel-clockrate = <975000000>;
qcom,mdss-dsi-virtual-channel-id = <0>;
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-panel-width = <540>;
diff --git a/arch/arm/boot/dts/qcom/msm8996-camera.dtsi b/arch/arm/boot/dts/qcom/msm8996-camera.dtsi
index 3422e5e7f500..282e6bcb713b 100644
--- a/arch/arm/boot/dts/qcom/msm8996-camera.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-camera.dtsi
@@ -623,6 +623,10 @@
"camss_cpp_axi_clk", "camss_cpp_clk",
"micro_iface_clk", "camss_ahb_clk",
"smmu_cpp_axi_clk", "cpp_vbif_ahb_clk";
+
+ resets = <&clock_mmss CAMSS_MICRO_BCR>;
+ reset-names = "micro_iface_reset";
+
qcom,clock-rates = <0 0 0 480000000 0 0 480000000 0 0 0 0>;
qcom,min-clock-rate = <200000000>;
qcom,bus-master = <1>;
diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi
index 4b1b9796ebe6..dc1bbcd13c36 100644
--- a/arch/arm/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996.dtsi
@@ -1394,18 +1394,20 @@
<&clock_gcc clk_gcc_pcie_clkref_clk>,
<&clock_gcc clk_gcc_smmu_aggre0_axi_clk>,
<&clock_gcc clk_gcc_pcie_phy_cfg_ahb_clk>,
- <&clock_gcc clk_gcc_pcie_phy_aux_clk>,
- <&clock_gcc clk_gcc_pcie_phy_reset>,
- <&clock_gcc clk_gcc_pcie_phy_com_reset>,
- <&clock_gcc clk_gcc_pcie_phy_nocsr_com_phy_reset>,
- <&clock_gcc clk_gcc_pcie_0_phy_reset>;
+ <&clock_gcc clk_gcc_pcie_phy_aux_clk>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk",
"pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk",
"pcie_0_slv_axi_clk", "pcie_0_ldo", "pcie_0_smmu_clk",
- "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk", "pcie_phy_reset",
- "pcie_phy_com_reset", "pcie_phy_nocsr_com_phy_reset",
- "pcie_0_phy_reset";
+ "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk";
+
+ resets = <&clock_gcc PCIE_PHY_BCR>,
+ <&clock_gcc PCIE_PHY_COM_BCR>,
+ <&clock_gcc PCIE_PHY_NOCSR_COM_PHY_BCR>,
+ <&clock_gcc PCIE_0_PHY_BCR>;
+
+ reset-names = "pcie_phy_reset", "pcie_phy_com_reset",
+ "pcie_phy_nocsr_com_phy_reset","pcie_0_phy_reset";
max-clock-frequency-hz = <0>, <0>, <1010526>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>, <0>;
@@ -1544,18 +1546,20 @@
<&clock_gcc clk_gcc_pcie_clkref_clk>,
<&clock_gcc clk_gcc_smmu_aggre0_axi_clk>,
<&clock_gcc clk_gcc_pcie_phy_cfg_ahb_clk>,
- <&clock_gcc clk_gcc_pcie_phy_aux_clk>,
- <&clock_gcc clk_gcc_pcie_phy_reset>,
- <&clock_gcc clk_gcc_pcie_phy_com_reset>,
- <&clock_gcc clk_gcc_pcie_phy_nocsr_com_phy_reset>,
- <&clock_gcc clk_gcc_pcie_1_phy_reset>;
+ <&clock_gcc clk_gcc_pcie_phy_aux_clk>;
clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", "pcie_1_aux_clk",
"pcie_1_cfg_ahb_clk", "pcie_1_mstr_axi_clk",
"pcie_1_slv_axi_clk", "pcie_1_ldo", "pcie_1_smmu_clk",
- "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk", "pcie_phy_reset",
- "pcie_phy_com_reset", "pcie_phy_nocsr_com_phy_reset",
- "pcie_1_phy_reset";
+ "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk";
+
+ resets = <&clock_gcc PCIE_PHY_BCR>,
+ <&clock_gcc PCIE_PHY_COM_BCR>,
+ <&clock_gcc PCIE_PHY_NOCSR_COM_PHY_BCR>,
+ <&clock_gcc PCIE_1_PHY_BCR>;
+
+ reset-names = "pcie_phy_reset", "pcie_phy_com_reset",
+ "pcie_phy_nocsr_com_phy_reset","pcie_1_phy_reset";
max-clock-frequency-hz = <0>, <0>, <1010526>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>, <0>;
@@ -1698,18 +1702,20 @@
<&clock_gcc clk_gcc_pcie_clkref_clk>,
<&clock_gcc clk_gcc_smmu_aggre0_axi_clk>,
<&clock_gcc clk_gcc_pcie_phy_cfg_ahb_clk>,
- <&clock_gcc clk_gcc_pcie_phy_aux_clk>,
- <&clock_gcc clk_gcc_pcie_phy_reset>,
- <&clock_gcc clk_gcc_pcie_phy_com_reset>,
- <&clock_gcc clk_gcc_pcie_phy_nocsr_com_phy_reset>,
- <&clock_gcc clk_gcc_pcie_2_phy_reset>;
+ <&clock_gcc clk_gcc_pcie_phy_aux_clk>;
clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src", "pcie_2_aux_clk",
"pcie_2_cfg_ahb_clk", "pcie_2_mstr_axi_clk",
"pcie_2_slv_axi_clk", "pcie_2_ldo", "pcie_2_smmu_clk",
- "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk", "pcie_phy_reset",
- "pcie_phy_com_reset", "pcie_phy_nocsr_com_phy_reset",
- "pcie_2_phy_reset";
+ "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk";
+
+ resets = <&clock_gcc PCIE_PHY_BCR>,
+ <&clock_gcc PCIE_PHY_COM_BCR>,
+ <&clock_gcc PCIE_PHY_NOCSR_COM_PHY_BCR>,
+ <&clock_gcc PCIE_2_PHY_BCR>;
+
+ reset-names = "pcie_phy_reset", "pcie_phy_com_reset",
+ "pcie_phy_nocsr_com_phy_reset","pcie_2_phy_reset";
max-clock-frequency-hz = <0>, <0>, <1010526>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>, <0>;
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi
index b4516f381c0c..154bc5b092df 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi
@@ -405,6 +405,8 @@
<106 512 0 0>,
<106 512 0 0>;
qcom,msm-bus-vector-dyn-vote;
+ resets = <&clock_mmss CAMSS_MICRO_BCR>;
+ reset-names = "micro_iface_reset";
qcom,cpp-fw-payload-info {
qcom,stripe-base = <790>;
qcom,plane-base = <715>;
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi
index d44002efea11..f59899fba039 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi
@@ -393,6 +393,13 @@
qcom,5v-boost-gpio = <&tlmm 51 0>;
};
+&dsi_dual_sharp_1080_120hz_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
&mdss_hdmi_tx {
pinctrl-names = "hdmi_hpd_active", "hdmi_ddc_active", "hdmi_cec_active",
"hdmi_active", "hdmi_sleep";
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi
index 3a15fbf6f15c..c9cbfdbb75a1 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi
@@ -24,6 +24,7 @@
#include "dsi-panel-jdi-dualmipi-cmd.dtsi"
#include "dsi-panel-sharp-1080p-cmd.dtsi"
#include "dsi-panel-jdi-1080p-video.dtsi"
+#include "dsi-panel-sharp-dualmipi-1080p-120hz.dtsi"
&soc {
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
@@ -149,3 +150,9 @@
qcom,mdss-dsi-t-clk-post = <0x07>;
qcom,mdss-dsi-t-clk-pre = <0x28>;
};
+
+&dsi_dual_sharp_1080_120hz_cmd {
+ qcom,mdss-dsi-panel-timings = [00 19 05 06 0a 0f 05 06 05 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x7>;
+ qcom,mdss-dsi-t-clk-pre = <0x26>;
+};
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi
index 70755ec1b8f5..8697ba4cb889 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi
@@ -444,6 +444,13 @@
qcom,5v-boost-gpio = <&tlmm 51 0>;
};
+&dsi_dual_sharp_1080_120hz_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
&pmicobalt_haptics {
status = "okay";
};
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi
index c028ea0eeab3..1ae0ab804eac 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include "msmcobalt-pinctrl.dtsi"
+#include "msmcobalt-audio.dtsi"
&blsp1_uart3_hs {
status = "ok";
@@ -99,4 +100,29 @@
debounce-interval = <15>;
};
};
+
+ sound-tavil {
+ qcom,model = "msmcobalt-skuk-tavil-snd-card";
+
+ qcom,audio-routing =
+ "AIF4 VI", "MCLK",
+ "RX_BIAS", "MCLK",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Headset Mic",
+ "DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "DMIC2", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic2",
+ "DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "SpkrLeft IN", "SPK1 OUT";
+
+ qcom,msm-mbhc-hphl-swh = <1>;
+
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft";
+ };
};
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
index 789a322f73bf..7f5f81eff9e5 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
@@ -1579,18 +1579,25 @@
<&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>,
<&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,
<&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,
- <&clock_gcc clk_gcc_pcie_clkref_clk>,
- <&clock_gcc clk_gcc_pcie_phy_reset>;
+ <&clock_gcc clk_gcc_pcie_clkref_clk>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
- "pcie_0_ldo", "pcie_0_phy_reset";
+ "pcie_0_ldo";
max-clock-frequency-hz = <0>, <0>, <19200000>,
<0>, <0>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>,
<0>, <0>;
+
+ resets = <&clock_gcc PCIE_PHY_BCR>,
+ <&clock_gcc PCIE_0_PHY_BCR>,
+ <&clock_gcc PCIE_0_PHY_BCR>;
+
+ reset-names = "pcie_phy_reset",
+ "pcie_0_phy_reset",
+ "pcie_0_phy_pipe_reset";
};
qcom,ipc_router {
@@ -2641,6 +2648,7 @@
qcom,pet-time = <10000>;
qcom,ipi-ping;
qcom,wakeup-enable;
+ qcom,scandump-size = <0x40000>;
};
qcom,spss@1d00000 {
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi
new file mode 100644
index 000000000000..11f602d842bc
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi
@@ -0,0 +1,1217 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ /*Version = 14 */
+ compatible = "qcom,msm-bus-device";
+ reg = <0x1620000 0x20000>,
+ <0x1000000 0x80000>,
+ <0x1500000 0x10000>,
+ <0x1700000 0x20000>,
+ <0x17900000 0xE000>,
+ <0x1740000 0x10000>,
+ <0x1740000 0x10000>;
+
+ reg-names = "snoc-base", "bimc-base", "cnoc-base",
+ "a2noc-base", "gnoc-base", "mmnoc-ahb-base", "mnoc-base";
+
+ /*Buses*/
+
+ fab_a2noc: fab-a2noc {
+ cell-id = <MSM_BUS_FAB_A2_NOC>;
+ label = "fab-a2noc";
+ qcom,fab-dev;
+ qcom,base-name = "a2noc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <16384>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc RPM_AGGRE2_NOC_CLK>,
+ <&clock_gcc RPM_AGGRE2_NOC_A_CLK>;
+ };
+
+ fab_bimc: fab-bimc {
+ cell-id = <MSM_BUS_FAB_BIMC>;
+ label = "fab-bimc";
+ qcom,fab-dev;
+ qcom,base-name = "bimc-base";
+ qcom,bus-type = <2>;
+ qcom,bypass-qos-prg;
+ qcom,util-fact = <153>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc RPM_BIMC_MSMBUS_CLK>,
+ <&clock_gcc RPM_BIMC_MSMBUS_A_CLK>;
+ };
+
+ fab_cnoc: fab-cnoc {
+ cell-id = <MSM_BUS_FAB_CONFIG_NOC>;
+ label = "fab-cnoc";
+ qcom,fab-dev;
+ qcom,base-name = "cnoc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc RPM_CNOC_MSMBUS_CLK>,
+ <&clock_gcc RPM_CNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_gnoc: fab-gnoc {
+ cell-id = <MSM_BUS_FAB_GNOC>;
+ label = "fab-gnoc";
+ qcom,virt-dev;
+ qcom,base-name = "gnoc-base";
+ qcom,bypass-qos-prg;
+ };
+
+ fab_mnoc: fab-mnoc {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC>;
+ label = "fab-mnoc";
+ qcom,fab-dev;
+ qcom,base-name = "mnoc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <20480>;
+ qcom,util-fact = <154>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc RPM_MMSSNOC_AXI_CLK>,
+ <&clock_gcc RPM_MMSSNOC_AXI_A_CLK>;
+ };
+
+ fab_snoc: fab-snoc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-snoc";
+ qcom,fab-dev;
+ qcom,base-name = "snoc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <24576>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_gcc RPM_SNOC_MSMBUS_CLK>,
+ <&clock_gcc RPM_SNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_mnoc_ahb: fab-mnoc-ahb {
+ cell-id = <MSM_BUS_FAB_MMSS_AHB>;
+ label = "fab-mnoc-ahb";
+ qcom,fab-dev;
+ qcom,base-name = "mmnoc-ahb-base";
+ qcom,bypass-qos-prg;
+ qcom,setrate-only-clk;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_mmss AHB_CLK_SRC >,
+ <&clock_mmss AHB_CLK_SRC>;
+ };
+
+ /*Masters*/
+
+ mas_ipa: mas-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_IPA>;
+ };
+
+ mas_cnoc_a2noc: mas-cnoc-a2noc {
+ cell-id = <MSM_BUS_MASTER_CNOC_A2NOC>;
+ label = "mas-cnoc-a2noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CNOC_A2NOC>;
+ qcom,blacklist = <&slv_snoc_cnoc>;
+ };
+
+ mas_sdcc_1: mas-sdcc-1 {
+ cell-id = <MSM_BUS_MASTER_SDCC_1>;
+ label = "mas-sdcc-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>;
+ };
+
+ mas_sdcc_2: mas-sdcc-2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-sdcc-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
+ };
+
+ mas_blsp_1: mas-blsp-1 {
+ cell-id = <MSM_BUS_MASTER_BLSP_1>;
+ label = "mas-blsp-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>;
+ };
+
+ mas_blsp_2: mas-blsp-2 {
+ cell-id = <MSM_BUS_MASTER_BLSP_2>;
+ label = "mas-blsp-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_2>;
+ };
+
+ mas_ufs: mas-ufs {
+ cell-id = <MSM_BUS_MASTER_UFS>;
+ label = "mas-ufs";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_UFS>;
+ };
+
+ mas_usb_hs: mas-usb-hs {
+ cell-id = <MSM_BUS_MASTER_USB_HS>;
+ label = "mas-usb-hs";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB_HS>;
+ };
+
+ mas_usb3: mas-usb3 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-usb3";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB3>;
+ };
+
+ mas_crypto_c0: mas-crypto-c0 {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>;
+ label = "mas-crypto-c0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <11>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO_CORE0>;
+ };
+
+ mas_gnoc_bimc: mas-gnoc-bimc {
+ cell-id = <MSM_BUS_MASTER_GNOC_BIMC>;
+ label = "mas-gnoc-bimc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GNOC_BIMC>;
+ };
+
+ mas_oxili: mas-oxili {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-oxili";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_hmss_l3
+ &slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>;
+ };
+
+ mas_mnoc_bimc: mas-mnoc-bimc {
+ cell-id = <MSM_BUS_MNOC_BIMC_MAS>;
+ label = "mas-mnoc-bimc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_hmss_l3
+ &slv_ebi &slv_bimc_snoc>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MNOC_BIMC>;
+ };
+
+ mas_snoc_bimc: mas-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_MAS>;
+ label = "mas-snoc-bimc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_hmss_l3 &slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC>;
+ };
+
+ mas_snoc_cnoc: mas-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_MAS>;
+ label = "mas-snoc-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_clk_ctl
+ &slv_qdss_cfg &slv_qm_cfg
+ &slv_srvc_cnoc &slv_ufs_cfg
+ &slv_tcsr &slv_a2noc_smmu_cfg
+ &slv_snoc_cfg &slv_tlmm_south
+ &slv_mpm &slv_cnoc_mnoc_mmss_cfg
+ &slv_sdcc_2 &slv_sdcc_1
+ &slv_spdm &slv_pmic_arb
+ &slv_prng &slv_mss_cfg
+ &slv_gpuss_cfg &slv_imem_cfg
+ &slv_usb3_0 &slv_a2noc_cfg
+ &slv_tlmm_north &slv_usb_hs
+ &slv_pdm &slv_tlmm_center
+ &slv_ahb2phy &slv_blsp_2
+ &slv_blsp_1 &slv_pimem_cfg
+ &slv_glm &slv_message_ram
+ &slv_bimc_cfg &slv_cnoc_mnoc_cfg>;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CNOC>;
+ };
+
+ mas_qdss_dap: mas-qdss-dap {
+ cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+ label = "mas-qdss-dap";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_clk_ctl
+ &slv_qdss_cfg &slv_qm_cfg
+ &slv_srvc_cnoc &slv_ufs_cfg
+ &slv_tcsr &slv_a2noc_smmu_cfg
+ &slv_snoc_cfg &slv_tlmm_south
+ &slv_mpm &slv_cnoc_mnoc_mmss_cfg
+ &slv_sdcc_2 &slv_sdcc_1
+ &slv_spdm &slv_pmic_arb
+ &slv_prng &slv_mss_cfg
+ &slv_gpuss_cfg &slv_imem_cfg
+ &slv_usb3_0 &slv_a2noc_cfg
+ &slv_tlmm_north &slv_usb_hs
+ &slv_pdm &slv_tlmm_center
+ &slv_ahb2phy &slv_blsp_2
+ &slv_blsp_1 &slv_pimem_cfg
+ &slv_glm &slv_message_ram
+ &slv_cnoc_a2noc &slv_bimc_cfg
+ &slv_cnoc_mnoc_cfg>;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
+ };
+
+ mas_apps_proc: mas-apps-proc {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-apps-proc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_gnoc_snoc &slv_gnoc_bimc>;
+ qcom,bus-dev = <&fab_gnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
+ };
+
+ mas_cnoc_mnoc_mmss_cfg: mas-cnoc-mnoc-mmss-cfg {
+ cell-id = <MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG>;
+ label = "mas-cnoc-mnoc-mmss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_venus_throttle_cfg
+ &slv_venus_cfg &slv_camera_throttle_cfg
+ &slv_smmu_cfg &slv_camera_cfg &slv_csi_phy_cfg
+ &slv_display_throttle_cfg &slv_display_cfg
+ &slv_mmss_clk_cfg &slv_mnoc_mpu_cfg
+ &slv_misc_cfg &slv_mmss_clk_xpu_cfg>;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CNOC_MNOC_MMSS_CFG>;
+ };
+
+ mas_cnoc_mnoc_cfg: mas-cnoc-mnoc-cfg {
+ cell-id = <MSM_BUS_MASTER_CNOC_MNOC_CFG>;
+ label = "mas-cnoc-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_srvc_mnoc>;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CNOC_MNOC_CFG>;
+ };
+
+ mas_cpp: mas-cpp {
+ cell-id = <MSM_BUS_MASTER_CPP>;
+ label = "mas-cpp";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CPP>;
+ };
+
+ mas_jpeg: mas-jpeg {
+ cell-id = <MSM_BUS_MASTER_JPEG>;
+ label = "mas-jpeg";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <6>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_JPEG>;
+ };
+
+ mas_mdp_p0: mas-mdp-p0 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-mdp-p0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP0>;
+ };
+
+ mas_mdp_p1: mas-mdp-p1 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT1>;
+ label = "mas-mdp-p1";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP1>;
+ };
+
+ mas_venus: mas-venus {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-venus";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VIDEO>;
+ };
+
+ mas_vfe: mas-vfe {
+ cell-id = <MSM_BUS_MASTER_VFE>;
+ label = "mas-vfe";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <5>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VFE>;
+ };
+
+ mas_qdss_etr: mas-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_pimem
+ &slv_imem &slv_snoc_cnoc
+ &slv_snoc_bimc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
+ };
+
+ mas_qdss_bam: mas-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_pimem
+ &slv_imem &slv_snoc_cnoc
+ &slv_snoc_bimc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
+ };
+
+ mas_snoc_cfg: mas-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CFG>;
+ };
+
+ mas_bimc_snoc: mas-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_MAS>;
+ label = "mas-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pimem
+ &slv_ipa &slv_qdss_stm
+ &slv_lpass &slv_hmss
+ &slv_cdsp &slv_snoc_cnoc
+ &slv_wlan &slv_imem>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC>;
+ };
+
+ mas_a2noc_snoc: mas-a2noc-snoc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_MAS>;
+ label = "mas-a2noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pimem
+ &slv_ipa &slv_qdss_stm
+ &slv_lpass &slv_hmss
+ &slv_snoc_bimc &slv_cdsp
+ &slv_snoc_cnoc &slv_wlan
+ &slv_imem>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_A2NOC_SNOC>;
+ };
+ /*Internal nodes*/
+
+ /*Slaves*/
+
+ slv_a2noc_snoc:slv-a2noc-snoc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_SLV>;
+ label = "slv-a2noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,connections = <&mas_a2noc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_SNOC>;
+ };
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
+ };
+
+ slv_hmss_l3:slv-hmss-l3 {
+ cell-id = <MSM_BUS_SLAVE_HMSS_L3>;
+ label = "slv-hmss-l3";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_HMSS_L3>;
+ };
+
+ slv_bimc_snoc:slv-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_SLV>;
+ label = "slv-bimc-snoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,connections = <&mas_bimc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC>;
+ };
+
+ slv_cnoc_a2noc:slv-cnoc-a2noc {
+ cell-id = <MSM_BUS_SLAVE_CNOC_A2NOC>;
+ label = "slv-cnoc-a2noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,connections = <&mas_cnoc_a2noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_A2NOC>;
+ };
+
+ slv_mpm:slv-mpm {
+ cell-id = <MSM_BUS_SLAVE_MPM>;
+ label = "slv-mpm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MPM>;
+ };
+
+ slv_pmic_arb:slv-pmic-arb {
+ cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
+ label = "slv-pmic-arb";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
+ };
+
+ slv_tlmm_north:slv-tlmm-north {
+ cell-id = <MSM_BUS_SLAVE_TLMM_NORTH>;
+ label = "slv-tlmm-north";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_NORTH>;
+ };
+
+ slv_tcsr:slv-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
+ };
+
+ slv_pimem_cfg:slv-pimem-cfg {
+ cell-id = <MSM_BUS_SLAVE_PIMEM_CFG>;
+ label = "slv-pimem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM_CFG>;
+ };
+
+ slv_imem_cfg:slv-imem-cfg {
+ cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+ label = "slv-imem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
+ };
+
+ slv_message_ram:slv-message-ram {
+ cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
+ label = "slv-message-ram";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
+ };
+
+ slv_glm:slv-glm {
+ cell-id = <MSM_BUS_SLAVE_GLM>;
+ label = "slv-glm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GLM>;
+ };
+
+ slv_bimc_cfg:slv-bimc-cfg {
+ cell-id = <MSM_BUS_SLAVE_BIMC_CFG>;
+ label = "slv-bimc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_CFG>;
+ };
+
+ slv_prng:slv-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
+ };
+
+ slv_spdm:slv-spdm {
+ cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>;
+ label = "slv-spdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>;
+ };
+
+ slv_qdss_cfg:slv-qdss-cfg {
+ cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+ label = "slv-qdss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
+ };
+
+ slv_cnoc_mnoc_cfg:slv-cnoc-mnoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_CFG>;
+ label = "slv-cnoc-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,connections = <&mas_cnoc_mnoc_cfg>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MNOC_CFG>;
+ };
+
+ slv_snoc_cfg:slv-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
+ };
+
+ slv_qm_cfg:slv-qm-cfg {
+ cell-id = <MSM_BUS_SLAVE_QM_CFG>;
+ label = "slv-qm-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QM_CFG>;
+ };
+
+ slv_clk_ctl:slv-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
+ };
+
+ slv_mss_cfg:slv-mss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MSS>;
+ label = "slv-mss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MSS>;
+ };
+
+ slv_tlmm_south:slv-tlmm-south {
+ cell-id = <MSM_BUS_SLAVE_TLMM_SOUTH>;
+ label = "slv-tlmm-south";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_SOUTH>;
+ };
+
+ slv_ufs_cfg:slv-ufs-cfg {
+ cell-id = <MSM_BUS_SLAVE_UFS_CFG>;
+ label = "slv-ufs-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_UFS_CFG>;
+ };
+
+ slv_a2noc_cfg:slv-a2noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A2NOC_CFG>;
+ label = "slv-a2noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_CFG>;
+ };
+
+ slv_a2noc_smmu_cfg:slv-a2noc-smmu-cfg {
+ cell-id = <MSM_BUS_SLAVE_A2NOC_SMMU_CFG>;
+ label = "slv-a2noc-smmu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_SMMU_CFG>;
+ };
+
+ slv_gpuss_cfg:slv-gpuss-cfg {
+ cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>;
+ label = "slv-gpuss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GFX3D_CFG>;
+ };
+
+ slv_ahb2phy:slv-ahb2phy {
+ cell-id = <MSM_BUS_SLAVE_PCIE20_AHB2PHY>;
+ label = "slv-ahb2phy";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCIE20_AHB2PHY>;
+ };
+
+ slv_blsp_1:slv-blsp-1 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_1>;
+ label = "slv-blsp-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>;
+ };
+
+ slv_sdcc_1:slv-sdcc-1 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_1>;
+ label = "slv-sdcc-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>;
+ };
+
+ slv_sdcc_2:slv-sdcc-2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-sdcc-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
+ };
+
+ slv_tlmm_center:slv-tlmm-center {
+ cell-id = <MSM_BUS_SLAVE_TLMM_CENTER>;
+ label = "slv-tlmm-center";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_CENTER>;
+ };
+
+ slv_blsp_2:slv-blsp-2 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_2>;
+ label = "slv-blsp-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_2>;
+ };
+
+ slv_pdm:slv-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
+ };
+
+ slv_cnoc_mnoc_mmss_cfg:slv-cnoc-mnoc-mmss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG>;
+ label = "slv-cnoc-mnoc-mmss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,connections = <&mas_cnoc_mnoc_mmss_cfg>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MNOC_MMSS_CFG>;
+ };
+
+ slv_usb_hs:slv-usb-hs {
+ cell-id = <MSM_BUS_SLAVE_USB_HS>;
+ label = "slv-usb-hs";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>;
+ };
+
+ slv_usb3_0:slv-usb3-0 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-usb3-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_USB3_0>;
+ };
+
+ slv_srvc_cnoc:slv-srvc-cnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_CNOC>;
+ label = "slv-srvc-cnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_CNOC>;
+ };
+
+
+ slv_gnoc_bimc:slv-gnoc-bimc {
+ cell-id = <MSM_BUS_SLAVE_GNOC_BIMC>;
+ label = "slv-gnoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_gnoc>;
+ qcom,connections = <&mas_gnoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GNOC_BIMC>;
+ };
+
+ slv_gnoc_snoc:slv-gnoc-snoc {
+ cell-id = <MSM_BUS_SLAVE_GNOC_SNOC>;
+ label = "slv-gnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_gnoc>;
+ qcom,connections = <&mas_gnoc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GNOC_SNOC>;
+ };
+
+ mas_gnoc_snoc: mas-gnoc-snoc {
+ cell-id = <MSM_BUS_MASTER_GNOC_SNOC>;
+ label = "mas-gnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pimem
+ &slv_ipa &slv_qdss_stm
+ &slv_lpass &slv_hmss
+ &slv_cdsp &slv_snoc_cnoc
+ &slv_wlan &slv_imem>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GNOC_SNOC>;
+ };
+
+ slv_camera_cfg:slv-camera-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-camera-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>;
+ };
+
+ slv_camera_throttle_cfg:slv-camera-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG>;
+ label = "slv-camera-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_THROTTLE_CFG>;
+ };
+
+ slv_misc_cfg:slv-misc-cfg {
+ cell-id = <MSM_BUS_SLAVE_MISC_CFG>;
+ label = "slv-misc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MISC_CFG>;
+ };
+
+ slv_venus_throttle_cfg:slv-venus-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_THROTTLE_CFG>;
+ label = "slv-venus-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_THROTTLE_CFG>;
+ };
+
+ slv_venus_cfg:slv-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-venus-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>;
+ };
+
+ slv_mmss_clk_xpu_cfg:slv-mmss-clk-xpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG>;
+ label = "slv-mmss-clk-xpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_CLK_XPU_CFG>;
+ };
+
+ slv_mmss_clk_cfg:slv-mmss-clk-cfg {
+ cell-id = <MSM_BUS_SLAVE_MMSS_CLK_CFG>;
+ label = "slv-mmss-clk-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_CLK_CFG>;
+ };
+
+ slv_mnoc_mpu_cfg:slv-mnoc-mpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MNOC_MPU_CFG>;
+ label = "slv-mnoc-mpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MNOC_MPU_CFG>;
+ };
+
+ slv_display_cfg:slv-display-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-display-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>;
+ };
+
+ slv_csi_phy_cfg:slv-csi-phy-cfg {
+ cell-id = <MSM_BUS_SLAVE_CSI_PHY_CFG>;
+ label = "slv-csi-phy-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CSI_PHY_CFG>;
+ };
+
+ slv_display_throttle_cfg:slv-display-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG>;
+ label = "slv-display-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_THROTTLE_CFG>;
+ };
+
+ slv_smmu_cfg:slv-smmu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MMSS_SMMU_CFG>;
+ label = "slv-smmu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_SMMU_CFG>;
+ };
+
+ slv_mnoc_bimc:slv-mnoc-bimc {
+ cell-id = <MSM_BUS_MNOC_BIMC_SLV>;
+ label = "slv-mnoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,connections = <&mas_mnoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MNOC_BIMC>;
+ };
+
+ slv_srvc_mnoc:slv-srvc-mnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_MNOC>;
+ label = "slv-srvc-mnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_MNOC>;
+ };
+
+ slv_hmss:slv-hmss {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-hmss";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>;
+ };
+
+ slv_lpass:slv-lpass {
+ cell-id = <MSM_BUS_SLAVE_LPASS>;
+ label = "slv-lpass";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>;
+ };
+
+ slv_wlan:slv-wlan {
+ cell-id = <MSM_BUS_SLAVE_WLAN>;
+ label = "slv-wlan";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_WLAN>;
+ };
+
+ slv_cdsp:slv-cdsp {
+ cell-id = <MSM_BUS_SLAVE_CDSP>;
+ label = "slv-cdsp";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CDSP>;
+ };
+
+ slv_ipa:slv-ipa {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-ipa";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IPA_CFG>;
+ };
+
+ slv_snoc_bimc:slv-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_SLV>;
+ label = "slv-snoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC>;
+ };
+
+ slv_snoc_cnoc:slv-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_SLV>;
+ label = "slv-snoc-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CNOC>;
+ };
+
+ slv_imem:slv-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
+ };
+
+ slv_pimem:slv-pimem {
+ cell-id = <MSM_BUS_SLAVE_PIMEM>;
+ label = "slv-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM>;
+ };
+
+ slv_qdss_stm:slv-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_SNOC>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
index 246a6cf5371e..52909eae0e7e 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
@@ -507,6 +507,13 @@
};
};
+ rpm_bus: qcom,rpm-smd {
+ compatible = "qcom,rpm-glink";
+ qcom,glink-edge = "rpm";
+ rpm-channel-name = "rpm_requests";
+ rpm-standalone; /* TODO: remove this after bring up */
+ };
+
qcom,ipc_router {
compatible = "qcom,ipc_router";
qcom,node-id = <1>;
@@ -544,6 +551,7 @@
};
#include "msmfalcon-ion.dtsi"
+#include "msmfalcon-bus.dtsi"
#include "msmfalcon-regulator.dtsi"
#include "msm-gdsc-cobalt.dtsi"
diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig
index c425514ddec5..08288e1b5c25 100644
--- a/arch/arm64/configs/msmcortex-perf_defconfig
+++ b/arch/arm64/configs/msmcortex-perf_defconfig
@@ -317,6 +317,7 @@ CONFIG_MSM_BCL_PERIPHERAL_CTL=y
CONFIG_BATTERY_BCL=y
CONFIG_QPNP_SMB2=y
CONFIG_SMB138X_CHARGER=y
+CONFIG_QPNP_QNOVO=y
CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
CONFIG_LIMITS_MONITOR=y
CONFIG_LIMITS_LITE_HW=y
@@ -484,7 +485,6 @@ CONFIG_ARM_SMMU=y
CONFIG_IOMMU_DEBUG=y
CONFIG_IOMMU_DEBUG_TRACKING=y
CONFIG_IOMMU_TESTS=y
-CONFIG_QCOM_COMMON_LOG=y
CONFIG_MSM_SMEM=y
CONFIG_QPNP_HAPTIC=y
CONFIG_MSM_SMD=y
@@ -550,6 +550,7 @@ CONFIG_PWM_QPNP=y
CONFIG_ARM_GIC_V3_ACL=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_MSM_TZ_LOG=y
CONFIG_SENSORS_SSC=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig
index 27f7ac6663d6..9e2727c4fe1e 100644
--- a/arch/arm64/configs/msmcortex_defconfig
+++ b/arch/arm64/configs/msmcortex_defconfig
@@ -320,6 +320,7 @@ CONFIG_MSM_BCL_PERIPHERAL_CTL=y
CONFIG_BATTERY_BCL=y
CONFIG_QPNP_SMB2=y
CONFIG_SMB138X_CHARGER=y
+CONFIG_QPNP_QNOVO=y
CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
CONFIG_LIMITS_MONITOR=y
CONFIG_LIMITS_LITE_HW=y
@@ -461,7 +462,6 @@ CONFIG_SWITCH=y
CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_CORTEX_ARM64=y
-CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_CE=y
CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_UE=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_QPNP=y
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-19 01:32:46 +0000