diff options
Diffstat (limited to 'arch')
37 files changed, 2056 insertions, 432 deletions
diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi index 8b01f6031211..68dabd2fe41c 100644 --- a/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi +++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,6 +15,7 @@ qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <850000000>; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; qcom,mdss-dsi-panel-width = <1080>; diff --git a/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi index 41b6f50c520b..ba27e3912ee6 100644 --- a/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi +++ b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi @@ -308,6 +308,49 @@ qcom,msm-cpudai-auxpcm-data = <0>, <0>; qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_tert_auxpcm: qcom,msm-tert-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "tertiary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_quat_auxpcm: qcom,msm-quat-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "quaternary"; + qcom,msm-cpudai-afe-clk-ver = <2>; }; hdmi_dba: qcom,msm-hdmi-dba-codec-rx { @@ -327,4 +370,42 @@ compatible = "qcom,adsp-loader"; qcom,adsp-state = <0>; }; + + qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36896>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + pinctrl-names = "default", "sleep"; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36897 >; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + pinctrl-names = "default", "sleep"; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897 >; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi new file mode 100644 index 000000000000..399892f52b6f --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi @@ -0,0 +1,377 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/msm/power-on.h> + +&spmi_bus { + qcom,pm2falcon@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm2falcon_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + qcom,secondary-pon-reset; + qcom,hard-reset-poweroff-type = + <PON_POWER_OFF_SHUTDOWN>; + }; + + pm2falcon_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm2falcon-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + }; + }; + + qcom,pm2falcon@3 { + compatible ="qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm2falcon_pwm_1: pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <1>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <0>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pm2falcon_pwm_2: pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <2>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <1>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pm2falcon_pwm_3: pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <3>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <2>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pm2falcon_pwm_4: pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <4>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <3>; + #pwm-cells = <2>; + status = "disabled"; + }; + + qcom,leds@d000 { + compatible = "qcom,leds-qpnp"; + reg = <0xd000 0x100>; + label = "rgb"; + status = "disabled"; + + red_led: qcom,rgb_0 { + label = "rgb"; + qcom,id = <3>; + qcom,mode = "pwm"; + pwms = <&pm2falcon_pwm_3 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "red"; + linux,default-trigger = + "battery-charging"; + }; + + green_led: qcom,rgb_1 { + label = "rgb"; + qcom,id = <4>; + qcom,mode = "pwm"; + pwms = <&pm2falcon_pwm_2 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "green"; + linux,default-trigger = "battery-full"; + }; + + blue_led: qcom,rgb_2 { + label = "rgb"; + qcom,id = <5>; + qcom,mode = "pwm"; + pwms = <&pm2falcon_pwm_1 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "blue"; + linux,default-trigger = "boot-indication"; + }; + }; + + pm2falcon_wled: qcom,leds@d800 { + compatible = "qcom,qpnp-wled"; + reg = <0xd800 0x100>, + <0xd900 0x100>, + <0xdc00 0x100>, + <0xde00 0x100>; + reg-names = "qpnp-wled-ctrl-base", + "qpnp-wled-sink-base", + "qpnp-wled-ibb-base", + "qpnp-wled-lab-base"; + interrupts = <0x3 0xd8 0x2>; + interrupt-names = "sc-irq"; + linux,name = "wled"; + linux,default-trigger = "bkl-trigger"; + qcom,fdbk-output = "auto"; + qcom,vref-mv = <350>; + qcom,switch-freq-khz = <800>; + qcom,ovp-mv = <29500>; + qcom,ilim-ma = <980>; + qcom,boost-duty-ns = <26>; + qcom,mod-freq-khz = <9600>; + qcom,dim-mode = "hybrid"; + qcom,hyb-thres = <625>; + qcom,sync-dly-us = <800>; + qcom,fs-curr-ua = <25000>; + qcom,cons-sync-write-delay-us = <1000>; + qcom,en-phase-stag; + qcom,led-strings-list = [00 01 02]; + qcom,en-ext-pfet-sc-pro; + status = "ok"; + }; + + flash_led: qcom,leds@d300 { + compatible = "qcom,qpnp-flash-led-v2"; + reg = <0xd300 0x100>; + label = "flash"; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + status = "disabled"; + + pm2falcon_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm2falcon_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm2falcon_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + + pm2falcon_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm2falcon_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm2falcon_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + + pm2falcon_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + reg0 { + regulator-name = "pmfalcon_bob"; + max-voltage-uv = <3600000>; + }; + }; + + pm2falcon_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <4>; + qcom,default-led-trigger = "switch1_trigger"; + reg0 { + regulator-name = "pmfalcon_bob"; + max-voltage-uv = <3600000>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi new file mode 100644 index 000000000000..dec37881249c --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi @@ -0,0 +1,169 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/interrupt-controller/irq.h> + +&spmi_bus { + qcom,pmfalcon@0 { + compatible ="qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pmfalcon_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x4 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", + "resin-bark", "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + }; + + pmfalcon_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pmfalcon-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + status = "disabled"; + }; + }; + + pmfalcon_coincell: qcom,coincell@2800 { + compatible = "qcom,qpnp-coincell"; + reg = <0x2800 0x100>; + }; + + pmfalcon_rtc: qcom,pmfalcon_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pmfalcon_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pmfalcon_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + }; + + qcom,pmfalcon@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi index 3f1ffd497f2c..8a8782f5f8b3 100644 --- a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi @@ -321,6 +321,7 @@ io-channel-names = "rradc_batt_id"; qcom,fg-esr-timer-awake = <64>; qcom,fg-esr-timer-asleep = <256>; + qcom,cycle-counter-en; status = "okay"; qcom,fg-batt-soc@4000 { @@ -329,23 +330,45 @@ interrupts = <0x2 0x40 0x0 IRQ_TYPE_EDGE_BOTH>, <0x2 0x40 0x1 IRQ_TYPE_EDGE_BOTH>, <0x2 0x40 0x2 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x40 0x3 IRQ_TYPE_EDGE_BOTH>; + <0x2 0x40 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x7 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "soc-update", "soc-ready", "bsoc-delta", - "msoc-delta"; + "msoc-delta", + "msoc-low", + "msoc-empty", + "msoc-high", + "msoc-full"; }; qcom,fg-batt-info@4100 { status = "okay"; reg = <0x4100 0x100>; - interrupts = <0x2 0x41 0x3 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "batt-missing"; + interrupts = <0x2 0x41 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "vbatt-pred-delta", + "vbatt-low", + "esr-delta", + "batt-missing", + "batt-temp-delta"; }; qcom,fg-memif@4400 { status = "okay"; reg = <0x4400 0x100>; + interrupts = <0x2 0x44 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x44 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x44 0x2 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ima-rdy", + "mem-xcp", + "dma-grant"; }; }; }; diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi index 4b1b9796ebe6..dc1bbcd13c36 100644 --- a/arch/arm/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996.dtsi @@ -1394,18 +1394,20 @@ <&clock_gcc clk_gcc_pcie_clkref_clk>, <&clock_gcc clk_gcc_smmu_aggre0_axi_clk>, <&clock_gcc clk_gcc_pcie_phy_cfg_ahb_clk>, - <&clock_gcc clk_gcc_pcie_phy_aux_clk>, - <&clock_gcc clk_gcc_pcie_phy_reset>, - <&clock_gcc clk_gcc_pcie_phy_com_reset>, - <&clock_gcc clk_gcc_pcie_phy_nocsr_com_phy_reset>, - <&clock_gcc clk_gcc_pcie_0_phy_reset>; + <&clock_gcc clk_gcc_pcie_phy_aux_clk>; clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", "pcie_0_ldo", "pcie_0_smmu_clk", - "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk", "pcie_phy_reset", - "pcie_phy_com_reset", "pcie_phy_nocsr_com_phy_reset", - "pcie_0_phy_reset"; + "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk"; + + resets = <&clock_gcc PCIE_PHY_BCR>, + <&clock_gcc PCIE_PHY_COM_BCR>, + <&clock_gcc PCIE_PHY_NOCSR_COM_PHY_BCR>, + <&clock_gcc PCIE_0_PHY_BCR>; + + reset-names = "pcie_phy_reset", "pcie_phy_com_reset", + "pcie_phy_nocsr_com_phy_reset","pcie_0_phy_reset"; max-clock-frequency-hz = <0>, <0>, <1010526>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; @@ -1544,18 +1546,20 @@ <&clock_gcc clk_gcc_pcie_clkref_clk>, <&clock_gcc clk_gcc_smmu_aggre0_axi_clk>, <&clock_gcc clk_gcc_pcie_phy_cfg_ahb_clk>, - <&clock_gcc clk_gcc_pcie_phy_aux_clk>, - <&clock_gcc clk_gcc_pcie_phy_reset>, - <&clock_gcc clk_gcc_pcie_phy_com_reset>, - <&clock_gcc clk_gcc_pcie_phy_nocsr_com_phy_reset>, - <&clock_gcc clk_gcc_pcie_1_phy_reset>; + <&clock_gcc clk_gcc_pcie_phy_aux_clk>; clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", "pcie_1_ldo", "pcie_1_smmu_clk", - "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk", "pcie_phy_reset", - "pcie_phy_com_reset", "pcie_phy_nocsr_com_phy_reset", - "pcie_1_phy_reset"; + "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk"; + + resets = <&clock_gcc PCIE_PHY_BCR>, + <&clock_gcc PCIE_PHY_COM_BCR>, + <&clock_gcc PCIE_PHY_NOCSR_COM_PHY_BCR>, + <&clock_gcc PCIE_1_PHY_BCR>; + + reset-names = "pcie_phy_reset", "pcie_phy_com_reset", + "pcie_phy_nocsr_com_phy_reset","pcie_1_phy_reset"; max-clock-frequency-hz = <0>, <0>, <1010526>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; @@ -1698,18 +1702,20 @@ <&clock_gcc clk_gcc_pcie_clkref_clk>, <&clock_gcc clk_gcc_smmu_aggre0_axi_clk>, <&clock_gcc clk_gcc_pcie_phy_cfg_ahb_clk>, - <&clock_gcc clk_gcc_pcie_phy_aux_clk>, - <&clock_gcc clk_gcc_pcie_phy_reset>, - <&clock_gcc clk_gcc_pcie_phy_com_reset>, - <&clock_gcc clk_gcc_pcie_phy_nocsr_com_phy_reset>, - <&clock_gcc clk_gcc_pcie_2_phy_reset>; + <&clock_gcc clk_gcc_pcie_phy_aux_clk>; clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src", "pcie_2_aux_clk", "pcie_2_cfg_ahb_clk", "pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk", "pcie_2_ldo", "pcie_2_smmu_clk", - "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk", "pcie_phy_reset", - "pcie_phy_com_reset", "pcie_phy_nocsr_com_phy_reset", - "pcie_2_phy_reset"; + "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk"; + + resets = <&clock_gcc PCIE_PHY_BCR>, + <&clock_gcc PCIE_PHY_COM_BCR>, + <&clock_gcc PCIE_PHY_NOCSR_COM_PHY_BCR>, + <&clock_gcc PCIE_2_PHY_BCR>; + + reset-names = "pcie_phy_reset", "pcie_phy_com_reset", + "pcie_phy_nocsr_com_phy_reset","pcie_2_phy_reset"; max-clock-frequency-hz = <0>, <0>, <1010526>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi index 9b50bb96750a..445f32df8aa4 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi @@ -35,6 +35,19 @@ compatible = "qcom,msmcobalt-asoc-snd-tasha"; qcom,model = "msmcobalt-tasha-snd-card"; qcom,ext-disp-audio-rx; + qcom,wcn-btfm; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; qcom,audio-routing = "AIF4 VI", "MCLK", @@ -81,6 +94,10 @@ "msm-pcm-routing", "msm-cpe-lsm", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, @@ -89,8 +106,13 @@ <&incall_record_tx>, <&incall_music_rx>, <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, - <&usb_audio_rx>, <&usb_audio_tx>; + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", @@ -103,7 +125,8 @@ "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673"; + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897"; asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; @@ -118,6 +141,19 @@ compatible = "qcom,msmcobalt-asoc-snd-tavil"; qcom,model = "msmcobalt-tavil-snd-card"; qcom,ext-disp-audio-rx; + qcom,wcn-btfm; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; qcom,audio-routing = "RX_BIAS", "MCLK", @@ -162,15 +198,25 @@ "msm-pcm-routing", "msm-cpe-lsm", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, <&afe_proxy_tx>, <&incall_record_rx>, <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, <&sb_5_rx>, - <&usb_audio_rx>, <&usb_audio_tx>, <&sb_6_rx>; + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", @@ -181,8 +227,10 @@ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-dev.16396"; + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897"; asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi index bbf1f783236b..190feb5000fc 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi @@ -28,7 +28,10 @@ reg-names = "csiphy"; interrupts = <0 78 0>; interrupt-names = "csiphy"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -42,7 +45,7 @@ <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_csiphy_clk_src>, <&clock_mmss clk_mmss_camss_csiphy0_clk>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", @@ -60,7 +63,10 @@ reg-names = "csiphy"; interrupts = <0 79 0>; interrupt-names = "csiphy"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -74,7 +80,7 @@ <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_csiphy_clk_src>, <&clock_mmss clk_mmss_camss_csiphy1_clk>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", @@ -92,7 +98,10 @@ reg-names = "csiphy"; interrupts = <0 80 0>; interrupt-names = "csiphy"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -106,7 +115,7 @@ <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_csiphy_clk_src>, <&clock_mmss clk_mmss_camss_csiphy2_clk>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", @@ -128,8 +137,9 @@ qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pmcobalt_l1>; - qcom,cam-vreg-name = "vdd_sec", "gdscr"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -144,7 +154,7 @@ <&clock_mmss clk_mmss_camss_csi0pix_clk>, <&clock_mmss clk_mmss_camss_cphy_csid0_clk>, <&clock_mmss clk_csiphy_clk_src>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", @@ -166,8 +176,9 @@ qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pmcobalt_l1>; - qcom,cam-vreg-name = "vdd_sec", "gdscr"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -182,7 +193,7 @@ <&clock_mmss clk_mmss_camss_csi1pix_clk>, <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, <&clock_mmss clk_csiphy_clk_src>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", @@ -204,8 +215,9 @@ qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pmcobalt_l1>; - qcom,cam-vreg-name = "vdd_sec", "gdscr"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -220,7 +232,7 @@ <&clock_mmss clk_mmss_camss_csi2pix_clk>, <&clock_mmss clk_mmss_camss_cphy_csid2_clk>, <&clock_mmss clk_csiphy_clk_src>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", @@ -242,8 +254,9 @@ qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pmcobalt_l1>; - qcom,cam-vreg-name = "vdd_sec", "gdscr"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -257,7 +270,7 @@ <&clock_mmss clk_mmss_camss_csi3pix_clk>, <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, <&clock_mmss clk_csiphy_clk_src>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", diff --git a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi index f59899fba039..ad293d9827d1 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi @@ -31,9 +31,9 @@ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ }; }; @@ -425,7 +425,7 @@ }; &pmicobalt_charger { - qcom,suspend-input; + qcom,batteryless-platform; }; &pmicobalt_haptics { @@ -539,10 +539,6 @@ }; &soc { - sound-9335 { - qcom,wcn-btfm; - }; - gpio_keys { compatible = "gpio-keys"; input-name = "gpio-keys"; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi index c9cbfdbb75a1..a4ba9a61cded 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi @@ -78,17 +78,17 @@ }; &dsi_dual_nt35597_video { - qcom,mdss-dsi-panel-timings = [00 19 05 06 0a 0f 05 06 05 03 04 00]; - qcom,mdss-dsi-t-clk-post = <0x07>; - qcom,mdss-dsi-t-clk-pre = <0x26>; + qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07 05 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "bta_check"; }; &dsi_dual_nt35597_cmd { - qcom,mdss-dsi-panel-timings = [00 19 05 06 0a 0f 05 06 05 03 04 00]; - qcom,mdss-dsi-t-clk-post = <0x07>; - qcom,mdss-dsi-t-clk-pre = <0x26>; + qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07 05 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; }; &dsi_dual_nt35597_truly_video { diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi index fd930d3d1644..4fe694069011 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi @@ -21,9 +21,6 @@ interrupt-controller; #interrupt-cells = <1>; vdd-supply = <&gdsc_mdss>; - vdd-cx-supply = <&pmcobalt_s1_level>; - vdd-cx-min-uV = <RPM_SMD_REGULATOR_LEVEL_LOW_SVS>; - vdd-cx-max-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; /* Bus Scale Settings */ qcom,msm-bus,name = "mdss_mdp"; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi index 8697ba4cb889..99402e3033ed 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi @@ -32,9 +32,9 @@ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ }; }; @@ -562,10 +562,6 @@ }; &soc { - sound-9335 { - qcom,wcn-btfm; - }; - gpio_keys { compatible = "gpio-keys"; input-name = "gpio-keys"; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi index f4f47bc461fc..3975bc5d16f5 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi @@ -1779,6 +1779,66 @@ }; }; + tsif0_signals_active: tsif0_signals_active { + tsif1_clk { + pins = "gpio89"; /* TSIF0 CLK */ + function = "tsif1_clk"; + }; + tsif1_en { + pins = "gpio90"; /* TSIF0 Enable */ + function = "tsif1_en"; + }; + tsif1_data { + pins = "gpio91"; /* TSIF0 DATA */ + function = "tsif1_data"; + }; + signals_cfg { + pins = "gpio89", "gpio90", "gpio91"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif0_sync_active: tsif0_sync_active { + tsif1_sync { + pins = "gpio9"; /* TSIF0 SYNC */ + function = "tsif1_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_signals_active: tsif1_signals_active { + tsif2_clk { + pins = "gpio93"; /* TSIF1 CLK */ + function = "tsif2_clk"; + }; + tsif2_en { + pins = "gpio94"; /* TSIF1 Enable */ + function = "tsif2_en"; + }; + tsif2_data { + pins = "gpio95"; /* TSIF1 DATA */ + function = "tsif2_data"; + }; + signals_cfg { + pins = "gpio93", "gpio94", "gpio95"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif1_sync_active: tsif1_sync_active { + tsif2_sync { + pins = "gpio96"; /* TSIF1 SYNC */ + function = "tsif2_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + pri_aux_pcm_clk { pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { mux { diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi index c028ea0eeab3..1ae0ab804eac 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include "msmcobalt-pinctrl.dtsi" +#include "msmcobalt-audio.dtsi" &blsp1_uart3_hs { status = "ok"; @@ -99,4 +100,29 @@ debounce-interval = <15>; }; }; + + sound-tavil { + qcom,model = "msmcobalt-skuk-tavil-snd-card"; + + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "SpkrLeft IN", "SPK1 OUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft"; + }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi index 86bc048adeb5..c2d45ec3ef07 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi @@ -533,7 +533,7 @@ regulator-name = "pm8005_s1"; status = "okay"; regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1032000>; + regulator-max-microvolt = <1100000>; qcom,enable-time = <500>; }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi index db50038b297e..25fd35c1bd10 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi @@ -28,88 +28,89 @@ compatible = "qcom,cpu-clock-osm-msmcobalt-v2"; /delete-property/ qcom,llm-sw-overr; qcom,pwrcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 364800000 0x05040013 0x01200020 0x1 >, - < 441600000 0x05040017 0x02200020 0x1 >, - < 518400000 0x0504001b 0x02200020 0x1 >, - < 595200000 0x0504001f 0x02200020 0x1 >, - < 672000000 0x05040023 0x03200020 0x1 >, - < 748800000 0x05040027 0x03200020 0x1 >, - < 825600000 0x0404002b 0x03220022 0x1 >, - < 883200000 0x0404002e 0x04250025 0x1 >, - < 960000000 0x04040032 0x04280028 0x1 >, - < 1036800000 0x04040036 0x042b002b 0x1 >, - < 1094400000 0x04040039 0x052e002e 0x2 >, - < 1171200000 0x0404003d 0x05310031 0x2 >, - < 1248000000 0x04040041 0x05340034 0x2 >, - < 1324800000 0x04040045 0x06370037 0x2 >, - < 1401600000 0x04040049 0x063a003a 0x2 >, - < 1478400000 0x0404004d 0x073e003e 0x2 >, - < 1555200000 0x04040051 0x07410041 0x2 >, - < 1670400000 0x04040057 0x08460046 0x2 >, - < 1747200000 0x0404005b 0x08490049 0x2 >, - < 1824000000 0x0404005f 0x084c004c 0x3 >, - < 1900800000 0x04040063 0x094f004f 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 364800000 0x05040013 0x01200020 0x1 2 >, + < 441600000 0x05040017 0x02200020 0x1 3 >, + < 518400000 0x0504001b 0x02200020 0x1 4 >, + < 595200000 0x0504001f 0x02200020 0x1 5 >, + < 672000000 0x05040023 0x03200020 0x1 6 >, + < 748800000 0x05040027 0x03200020 0x1 7 >, + < 825600000 0x0404002b 0x03220022 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x04280028 0x1 10 >, + < 1036800000 0x04040036 0x042b002b 0x1 11 >, + < 1094400000 0x04040039 0x052e002e 0x2 12 >, + < 1171200000 0x0404003d 0x05310031 0x2 13 >, + < 1248000000 0x04040041 0x05340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x063a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1555200000 0x04040051 0x07410041 0x2 18 >, + < 1670400000 0x04040057 0x08460046 0x2 19 >, + < 1747200000 0x0404005b 0x08490049 0x2 20 >, + < 1824000000 0x0404005f 0x084c004c 0x3 21 >, + < 1900800000 0x04040063 0x094f004f 0x3 22 >; qcom,perfcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 345600000 0x05040012 0x01200020 0x1 >, - < 422400000 0x05040016 0x02200020 0x1 >, - < 499200000 0x0504001a 0x02200020 0x1 >, - < 576000000 0x0504001e 0x02200020 0x1 >, - < 652800000 0x05040022 0x03200020 0x1 >, - < 729600000 0x05040026 0x03200020 0x1 >, - < 806400000 0x0504002a 0x03220022 0x1 >, - < 902400000 0x0404002f 0x04260026 0x1 >, - < 979200000 0x04040033 0x04290029 0x1 >, - < 1056000000 0x04040037 0x052c002c 0x1 >, - < 1132800000 0x0404003b 0x052f002f 0x1 >, - < 1190400000 0x0404003e 0x05320032 0x2 >, - < 1267200000 0x04040042 0x06350035 0x2 >, - < 1344000000 0x04040046 0x06380038 0x2 >, - < 1420800000 0x0404004a 0x063b003b 0x2 >, - < 1497600000 0x0404004e 0x073e003e 0x2 >, - < 1574400000 0x04040052 0x07420042 0x2 >, - < 1651200000 0x04040056 0x07450045 0x2 >, - < 1728000000 0x0404005a 0x08480048 0x2 >, - < 1804800000 0x0404005e 0x084b004b 0x2 >, - < 1881600000 0x04040062 0x094e004e 0x2 >, - < 1958400000 0x04040066 0x09520052 0x2 >, - < 2035200000 0x0404006a 0x09550055 0x3 >, - < 2112000000 0x0404006e 0x0a580058 0x3 >, - < 2188800000 0x04040072 0x0a5b005b 0x3 >, - < 2265600000 0x04040076 0x0a5e005e 0x3 >, - < 2342400000 0x0404007a 0x0a620062 0x3 >, - < 2419200000 0x0404007e 0x0a650065 0x3 >, - < 2496000000 0x04040082 0x0a680068 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2188800000 0x04040072 0x0a5b005b 0x3 26 >, + < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, + < 2342400000 0x0404007a 0x0a620062 0x3 28 >, + < 2419200000 0x0404007e 0x0a650065 0x3 29 >, + < 2496000000 0x04040082 0x0a680068 0x3 30 >; qcom,perfcl-speedbin1-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 345600000 0x05040012 0x01200020 0x1 >, - < 422400000 0x05040016 0x02200020 0x1 >, - < 499200000 0x0504001a 0x02200020 0x1 >, - < 576000000 0x0504001e 0x02200020 0x1 >, - < 652800000 0x05040022 0x03200020 0x1 >, - < 729600000 0x05040026 0x03200020 0x1 >, - < 806400000 0x0504002a 0x03220022 0x1 >, - < 902400000 0x0404002f 0x04260026 0x1 >, - < 979200000 0x04040033 0x04290029 0x1 >, - < 1056000000 0x04040037 0x052c002c 0x1 >, - < 1132800000 0x0404003b 0x052f002f 0x1 >, - < 1190400000 0x0404003e 0x05320032 0x2 >, - < 1267200000 0x04040042 0x06350035 0x2 >, - < 1344000000 0x04040046 0x06380038 0x2 >, - < 1420800000 0x0404004a 0x063b003b 0x2 >, - < 1497600000 0x0404004e 0x073e003e 0x2 >, - < 1574400000 0x04040052 0x07420042 0x2 >, - < 1651200000 0x04040056 0x07450045 0x2 >, - < 1728000000 0x0404005a 0x08480048 0x2 >, - < 1804800000 0x0404005e 0x084b004b 0x2 >, - < 1881600000 0x04040062 0x094e004e 0x2 >, - < 1958400000 0x04040066 0x09520052 0x2 >, - < 2035200000 0x0404006a 0x09550055 0x3 >, - < 2112000000 0x0404006e 0x0a580058 0x3 >, - < 2208000000 0x04040073 0x0a5c005c 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2304000000 0x04010078 0x0a5c005c 0x3 26 >; }; &msm_cpufreq { @@ -202,8 +203,7 @@ < 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >; + < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >; qcom,gfxfreq-mx-speedbin0 = < 0 0 >, < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, @@ -212,8 +212,7 @@ < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; }; &mdss_mdp { @@ -250,14 +249,14 @@ /* Speed bin 0 */ <828000 828000 828000 828000 828000 828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 - 828000 828000 828000 952000 952000 + 828000 900000 900000 900000 900000 + 900000 900000 900000 952000 952000 1056000 1056000>, /* Speed bin 1 */ <828000 828000 828000 828000 828000 828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 - 828000 828000 828000 952000 952000 + 828000 900000 900000 900000 900000 + 900000 900000 900000 952000 952000 1056000 1056000>; qcom,cpr-voltage-floor = @@ -326,43 +325,43 @@ qcom,cpr-open-loop-voltage-fuse-adjustment = /* Speed bin 0 */ - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, /* Speed bin 1 */ - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>, - <40000 24000 0 0>; + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>; qcom,cpr-closed-loop-voltage-fuse-adjustment = /* Speed bin 0 */ - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, /* Speed bin 1 */ - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>, - <20000 26000 0 0>; + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>; qcom,allow-voltage-interpolation; qcom,allow-quotient-interpolation; @@ -396,15 +395,15 @@ /* Speed bin 0 */ <828000 828000 828000 828000 828000 828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 952000 952000 952000 1056000 1056000 1056000 1056000 1056000 1056000 1056000>, /* Speed bin 1 */ <828000 828000 828000 828000 828000 828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 952000 952000 952000 1056000 1056000 1056000>; @@ -525,6 +524,11 @@ qcom,cpr-scaled-open-loop-voltage-as-ceiling; }; +&pm8005_s1 { + regulator-min-microvolt = <516000>; + regulator-max-microvolt = <1088000>; +}; + &gfx_cpr { compatible = "qcom,cpr4-msmcobalt-v2-mmss-regulator"; }; @@ -540,12 +544,17 @@ qcom,cpr-corner-fmax-map = <1 3 5 8>; qcom,cpr-voltage-ceiling = - <656000 716000 772000 880000 908000 - 948000 1016000 1088000>; + <656000 716000 772000 880000 908000 948000 1016000 1088000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>; qcom,cpr-voltage-floor = - <516000 516000 532000 584000 632000 - 672000 712000 756000>; + <516000 516000 532000 584000 632000 672000 712000 756000>; qcom,mem-acc-voltage = <1 1 1 2 2 2 2 2>; @@ -590,11 +599,11 @@ 0 0 3487 0 3280 1896 1874 0>; qcom,cpr-open-loop-voltage-fuse-adjustment = - < 72000 0 0 0>; + < 100000 0 0 0>; qcom,cpr-closed-loop-voltage-adjustment = - < 65000 26000 8000 0 - 0 0 0 0>; + < 96000 18000 4000 0 + 0 13000 9000 0>; qcom,cpr-floor-to-ceiling-max-range = <50000 50000 50000 50000 50000 50000 70000 70000>; @@ -655,18 +664,18 @@ /* SVS2 */ qcom,imem-ab-tbl = - <200000000 1752000>, - <269330000 1752000>, - <355200000 2500000>, - <444000000 6000000>, - <533000000 6000000>; + <200000000 1560000>,/* imem @ svs2 freq 75 Mhz */ + <269330000 3570000>,/* imem @ svs freq 171 Mhz */ + <355200000 3570000>,/* imem @ svs freq 171 Mhz */ + <444000000 6750000>,/* imem @ nom freq 323 Mhz */ + <533000000 8490000>;/* imem @ turbo freq 406 Mhz */ }; /* GPU overrides */ &msm_gpu { /* Updated chip ID */ qcom,chipid = <0x05040001>; - qcom,initial-pwrlevel = <6>; + qcom,initial-pwrlevel = <5>; qcom,gpu-pwrlevels { #address-cells = <1>; @@ -676,69 +685,61 @@ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <710000000>; - qcom,bus-freq = <12>; - qcom,bus-min = <12>; - qcom,bus-max = <12>; - }; - - qcom,gpu-pwrlevel@1 { - reg = <1>; qcom,gpu-freq = <670000000>; qcom,bus-freq = <12>; qcom,bus-min = <11>; qcom,bus-max = <12>; }; - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <596000000>; qcom,bus-freq = <11>; qcom,bus-min = <9>; qcom,bus-max = <12>; }; - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <515000000>; qcom,bus-freq = <11>; qcom,bus-min = <9>; qcom,bus-max = <12>; }; - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <414000000>; qcom,bus-freq = <9>; qcom,bus-min = <8>; qcom,bus-max = <11>; }; - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <342000000>; qcom,bus-freq = <8>; qcom,bus-min = <5>; qcom,bus-max = <9>; }; - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <257000000>; qcom,bus-freq = <5>; qcom,bus-min = <3>; qcom,bus-max = <8>; }; - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <180000000>; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <5>; }; - qcom,gpu-pwrlevel@8 { - reg = <8>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <27000000>; qcom,bus-freq = <0>; qcom,bus-min = <0>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi index c44e8f976710..f17be7570742 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi @@ -66,10 +66,10 @@ * corresponding video core frequency. */ qcom,imem-ab-tbl = - <100000000 1752000>, /* imem @ svs2 freq 75 Mhz */ - <186000000 1752000>, /* imem @ svs2 freq 75 Mhz */ - <360000000 2500000>, /* imem @ svs freq 171 Mhz */ - <465000000 6000000>; /* imem @ noimal freq 320 Mhz */ + <100000000 1560000>, /* imem @ svs2 freq 75 Mhz */ + <186000000 3570000>, /* imem @ svs freq 171 Mhz */ + <360000000 6750000>, /* imem @ nom freq 323 Mhz */ + <465000000 8490000>; /* imem @ turbo freq 406 Mhz */ /* Regulators */ smmu-vdd-supply = <&gdsc_bimc_smmu>; @@ -124,7 +124,7 @@ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0_OCMEM>; qcom,bus-slave = <MSM_BUS_SLAVE_VMEM>; qcom,bus-governor = "msm-vidc-vmem+"; - qcom,bus-range-kbps = <1000 6776000>; + qcom,bus-range-kbps = <1000 8490000>; }; arm9_bus_ddr { diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index a16894dd4765..27f9e2ace106 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -823,55 +823,55 @@ interrupt-names = "pwrcl-irq", "perfcl-irq"; qcom,pwrcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 345600000 0x05040012 0x02200020 0x1 >, - < 422400000 0x05040016 0x02200020 0x1 >, - < 499200000 0x0504001a 0x02200020 0x1 >, - < 576000000 0x0504001e 0x03200020 0x1 >, - < 633600000 0x05040021 0x03200020 0x1 >, - < 710400000 0x05040025 0x03200020 0x1 >, - < 806400000 0x0504002a 0x04200020 0x1 >, - < 883200000 0x0404002e 0x04250025 0x1 >, - < 960000000 0x04040032 0x05280028 0x1 >, - < 1036800000 0x04040036 0x052b002b 0x2 >, - < 1113600000 0x0404003a 0x052e002e 0x2 >, - < 1190400000 0x0404003e 0x06320032 0x2 >, - < 1248000000 0x04040041 0x06340034 0x2 >, - < 1324800000 0x04040045 0x06370037 0x2 >, - < 1401600000 0x04040049 0x073a003a 0x2 >, - < 1478400000 0x0404004d 0x073e003e 0x2 >, - < 1574400000 0x04040052 0x08420042 0x2 >, - < 1651200000 0x04040056 0x08450045 0x2 >, - < 1728000000 0x0404005a 0x08480048 0x2 >, - < 1804800000 0x0404005e 0x094b004b 0x3 >, - < 1881600000 0x04040062 0x094e004e 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x04200020 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x05280028 0x1 10 >, + < 1036800000 0x04040036 0x052b002b 0x2 11 >, + < 1113600000 0x0404003a 0x052e002e 0x2 12 >, + < 1190400000 0x0404003e 0x06320032 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x08420042 0x2 18 >, + < 1651200000 0x04040056 0x08450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x094b004b 0x3 21 >, + < 1881600000 0x04040062 0x094e004e 0x3 22 >; qcom,perfcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 345600000 0x05040012 0x02200020 0x1 >, - < 422400000 0x05040016 0x02200020 0x1 >, - < 480000000 0x05040019 0x02200020 0x1 >, - < 556800000 0x0504001d 0x03200020 0x1 >, - < 633600000 0x05040021 0x03200020 0x1 >, - < 710400000 0x05040025 0x03200020 0x1 >, - < 787200000 0x05040029 0x04200020 0x1 >, - < 844800000 0x0404002c 0x04230023 0x1 >, - < 902400000 0x0404002f 0x04260026 0x1 >, - < 979200000 0x04040033 0x05290029 0x1 >, - < 1056000000 0x04040037 0x052c002c 0x1 >, - < 1171200000 0x0404003d 0x06310031 0x2 >, - < 1248000000 0x04040041 0x06340034 0x2 >, - < 1324800000 0x04040045 0x06370037 0x2 >, - < 1401600000 0x04040049 0x073a003a 0x2 >, - < 1478400000 0x0404004d 0x073e003e 0x2 >, - < 1536000000 0x04040050 0x07400040 0x2 >, - < 1632000000 0x04040055 0x08440044 0x2 >, - < 1708800000 0x04040059 0x08470047 0x2 >, - < 1785600000 0x0404005d 0x094a004a 0x2 >, - < 1862400000 0x04040061 0x094e004e 0x2 >, - < 1939200000 0x04040065 0x09510051 0x3 >, - < 2016000000 0x04040069 0x0a540054 0x3 >, - < 2092800000 0x0404006d 0x0a570057 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 480000000 0x05040019 0x02200020 0x1 4 >, + < 556800000 0x0504001d 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 787200000 0x05040029 0x04200020 0x1 8 >, + < 844800000 0x0404002c 0x04230023 0x1 9 >, + < 902400000 0x0404002f 0x04260026 0x1 10 >, + < 979200000 0x04040033 0x05290029 0x1 11 >, + < 1056000000 0x04040037 0x052c002c 0x1 12 >, + < 1171200000 0x0404003d 0x06310031 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1536000000 0x04040050 0x07400040 0x2 18 >, + < 1632000000 0x04040055 0x08440044 0x2 19 >, + < 1708800000 0x04040059 0x08470047 0x2 20 >, + < 1785600000 0x0404005d 0x094a004a 0x2 21 >, + < 1862400000 0x04040061 0x094e004e 0x2 22 >, + < 1939200000 0x04040065 0x09510051 0x3 23 >, + < 2016000000 0x04040069 0x0a540054 0x3 24 >, + < 2092800000 0x0404006d 0x0a570057 0x3 25 >; qcom,up-timer = <1000 1000>; @@ -1579,18 +1579,25 @@ <&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>, <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>, <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>, - <&clock_gcc clk_gcc_pcie_clkref_clk>, - <&clock_gcc clk_gcc_pcie_phy_reset>; + <&clock_gcc clk_gcc_pcie_clkref_clk>; clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", - "pcie_0_ldo", "pcie_0_phy_reset"; + "pcie_0_ldo"; max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; + + resets = <&clock_gcc PCIE_PHY_BCR>, + <&clock_gcc PCIE_0_PHY_BCR>, + <&clock_gcc PCIE_0_PHY_BCR>; + + reset-names = "pcie_phy_reset", + "pcie_0_phy_reset", + "pcie_0_phy_pipe_reset"; }; qcom,ipc_router { @@ -2184,7 +2191,9 @@ reg-names = "tsens_physical"; interrupts = <0 458 0>, <0 445 0>; interrupt-names = "tsens-upper-lower", "tsens-critical"; - qcom,sensors = <14>; + qcom,client-id = <0 1 2 3 4 7 8 9 10 11 12 13>; + qcom,sensor-id = <0 1 2 3 4 7 8 9 10 11 12 13>; + qcom,sensors = <12>; }; tsens1: tsens@10ad000 { @@ -2225,16 +2234,6 @@ qcom,sensor-name = "tsens_tz_sensor4"; qcom,scaling-factor = <10>; }; - sensor_information5: qcom,sensor-information-5 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor5"; - qcom,scaling-factor = <10>; - }; - sensor_information6: qcom,sensor-information-6 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor6"; - qcom,scaling-factor = <10>; - }; sensor_information7: qcom,sensor-information-7 { qcom,sensor-type = "tsens"; qcom,sensor-name = "tsens_tz_sensor7"; @@ -2621,6 +2620,7 @@ "iface_clk", "noc_axi_clk", "bus_clk", "maxi_clk"; qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = @@ -2886,6 +2886,57 @@ qcom,icnss-adc_tm = <&pmcobalt_adc_tm>; }; + tspp: msm_tspp@0c1e7000 { + compatible = "qcom,msm_tspp"; + reg = <0x0c1e7000 0x200>, /* MSM_TSIF0_PHYS */ + <0x0c1e8000 0x200>, /* MSM_TSIF1_PHYS */ + <0x0c1e9000 0x1000>, /* MSM_TSPP_PHYS */ + <0x0c1c4000 0x23000>; /* MSM_TSPP_BAM_PHYS */ + reg-names = "MSM_TSIF0_PHYS", + "MSM_TSIF1_PHYS", + "MSM_TSPP_PHYS", + "MSM_TSPP_BAM_PHYS"; + interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */ + <0 119 0>, /* TSIF0_IRQ */ + <0 120 0>, /* TSIF1_IRQ */ + <0 122 0>; /* TSIF_BAM_IRQ */ + interrupt-names = "TSIF_TSPP_IRQ", + "TSIF0_IRQ", + "TSIF1_IRQ", + "TSIF_BAM_IRQ"; + + clock-names = "iface_clk", "ref_clk"; + clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>, + <&clock_gcc clk_gcc_tsif_ref_clk>; + + qcom,msm-bus,name = "tsif"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <82 512 0 0>, /* No vote */ + <82 512 12288 24576>; + /* Max. bandwidth, 2xTSIF, each max of 96Mbps */ + + pinctrl-names = "disabled", + "tsif0-mode1", "tsif0-mode2", + "tsif1-mode1", "tsif1-mode2", + "dual-tsif-mode1", "dual-tsif-mode2"; + + pinctrl-0 = <>; /* disabled */ + pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */ + pinctrl-2 = <&tsif0_signals_active + &tsif0_sync_active>; /* tsif0-mode2 */ + pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */ + pinctrl-4 = <&tsif1_signals_active + &tsif1_sync_active>; /* tsif1-mode2 */ + pinctrl-5 = <&tsif0_signals_active + &tsif1_signals_active>; /* dual-tsif-mode1 */ + pinctrl-6 = <&tsif0_signals_active + &tsif0_sync_active + &tsif1_signals_active + &tsif1_sync_active>; /* dual-tsif-mode2 */ + }; + wil6210: qcom,wil6210 { compatible = "qcom,wil6210"; qcom,pcie-parent = <&pcie0>; @@ -2933,16 +2984,10 @@ }; &gdsc_usb30 { - clock-names = "core_clk"; - clocks = <&clock_gcc clk_gcc_usb30_master_clk>; status = "ok"; }; &gdsc_pcie_0 { - clock-names = "master_bus_clk", "slave_bus_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>, - <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>, - <&clock_gcc clk_gcc_pcie_0_pipe_clk>; status = "ok"; }; @@ -3000,19 +3045,14 @@ }; &gdsc_mdss { - clock-names = "bus_clk", "rot_clk"; - clocks = <&clock_mmss clk_mmss_mdss_axi_clk>, - <&clock_mmss clk_mmss_mdss_rot_clk>; proxy-supply = <&gdsc_mdss>; qcom,proxy-consumer-enable; status = "ok"; }; &gdsc_gpu_gx { - clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; - clocks = <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>, - <&clock_gfx clk_gpucc_gfx3d_clk>, - <&clock_gfx clk_gfx3d_clk_src>; + clock-names = "core_root_clk"; + clocks = <&clock_gfx clk_gfx3d_clk_src>; qcom,force-enable-root-clk; parent-supply = <&gfx_vreg>; status = "ok"; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi index 352856965373..b60d4013dad8 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi @@ -26,6 +26,8 @@ arm,buffer-size = <0x400000>; arm,sg-enable; + coresight-ctis = <&cti0 &cti8>; + coresight-name = "coresight-tmc-etr"; clocks = <&clock_gcc RPM_QDSS_CLK>, @@ -76,6 +78,8 @@ coresight-name = "coresight-tmc-etf"; + coresight-ctis = <&cti0 &cti8>; + clocks = <&clock_gcc RPM_QDSS_CLK>, <&clock_gcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "core_a_clk"; @@ -161,6 +165,14 @@ <&funnel_merg_in_funnel_in0>; }; }; + port@3 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; port@4 { reg = <7>; funnel_in0_in_stm: endpoint { @@ -191,4 +203,294 @@ }; }; }; + + cti0: cti@6010000 { + compatible = "arm,coresight-cti"; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti1: cti@6011000 { + compatible = "arm,coresight-cti"; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti2: cti@6012000 { + compatible = "arm,coresight-cti"; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti3: cti@6013000 { + compatible = "arm,coresight-cti"; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti4: cti@6014000 { + compatible = "arm,coresight-cti"; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti5: cti@6015000 { + compatible = "arm,coresight-cti"; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti6: cti@6016000 { + compatible = "arm,coresight-cti"; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti7: cti@6017000 { + compatible = "arm,coresight-cti"; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti8: cti@6018000 { + compatible = "arm,coresight-cti"; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti9: cti@6019000 { + compatible = "arm,coresight-cti"; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti10: cti@601a000 { + compatible = "arm,coresight-cti"; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti11: cti@601b000 { + compatible = "arm,coresight-cti"; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti12: cti@601c000 { + compatible = "arm,coresight-cti"; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti13: cti@601d000 { + compatible = "arm,coresight-cti"; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti14: cti@601e000 { + compatible = "arm,coresight-cti"; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti15: cti@601f000 { + compatible = "arm,coresight-cti"; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "qcom,coresight-tpda"; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <7 32>, + <9 32>; + qcom,tc-elem-size = <3 32>, + <6 32>, + <9 32>; + qcom,dsb-elem-size = <7 32>, + <9 32>; + qcom,cmb-elem-size = <3 32>, + <4 32>, + <5 32>, + <9 64>; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + port@2 { + reg = <5>; + tpda_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@7054000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7054000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi index 6a000e4d4fd0..d28d09c2a527 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi @@ -32,5 +32,21 @@ bias-disable; }; }; + + led_enable: led_enable { + mux { + pins = "gpio40"; + drive_strength = <16>; + output-high; + }; + }; + + led_disable: led_disable { + mux { + pins = "gpio40"; + drive_strength = <2>; + output-low; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi index 2c09774c1391..124ab341ba6b 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi @@ -13,341 +13,348 @@ /* Stub regulators */ / { - /* PM660A S1 - VDD_APC0 supply */ - pm660_s1a: regulator-pm660-s1a { + /* PMFALCON S1 - VDD_APC0 supply */ + pmfalcon_s1a: regulator-pmfalcon-s1a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s1a"; + regulator-name = "pmfalcon_s1a"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <565000>; regulator-max-microvolt = <1170000>; }; - /* PM660A S2 + S3 = VDD_APC1 supply */ - pm660_s2a: regulator-pm660-s2a { + /* PMFALCON S2 + S3 = VDD_APC1 supply */ + pmfalcon_s2a: regulator-pmfalcon-s2a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s2a"; + regulator-name = "pmfalcon_s2a"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <565000>; regulator-max-microvolt = <1170000>; }; - pm660_s4a: regulator-pm660-s4a { + pmfalcon_s4a: regulator-pmfalcon-s4a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s4a"; + regulator-name = "pmfalcon_s4a"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <1805000>; regulator-max-microvolt = <2040000>; }; - pm660_s5a: regulator-pm660-s5a { + pmfalcon_s5a: regulator-pmfalcon-s5a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s5a"; + regulator-name = "pmfalcon_s5a"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; }; - pm660_s6a: regulator-pm660-s6a { + pmfalcon_s6a: regulator-pmfalcon-s6a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s6a"; + regulator-name = "pmfalcon_s6a"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <504000>; regulator-max-microvolt = <992000>; }; - pm660_s1b: regulator-pm660-s1b { + pmfalcon_s1b: regulator-pmfalcon-s1b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s1b"; + regulator-name = "pmfalcon_s1b"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <1125000>; regulator-max-microvolt = <1125000>; }; - pm660_s2b: regulator-pm660-s2b { + pmfalcon_s2b: regulator-pmfalcon-s2b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s2b"; + regulator-name = "pmfalcon_s2b"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - /* PM660B S3 + S4 - VDD_CX supply */ - pm660_s3b_level: regulator-pm660-s3b-level { + /* PMFALCON S3 + S4 - VDD_CX supply */ + pmfalcon_s3b_level: regulator-pmfalcon-s3b-level { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s3b_level"; + regulator-name = "pmfalcon_s3b_level"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; - pm660_s3b_floor_level: regulator-pm660-s3b-floor-level { + pmfalcon_s3b_floor_level: regulator-pmfalcon-s3b-floor-level { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s3b_floor_level"; + regulator-name = "pmfalcon_s3b_floor_level"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; - pm660_s3b_level_ao: regulator-pm660-s3b-level-ao { + pmfalcon_s3b_level_ao: regulator-pmfalcon-s3b-level-ao { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s3b_level_ao"; + regulator-name = "pmfalcon_s3b_level_ao"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; - /* PM660B S5 - VDD_MX supply */ - pm660_s5b_level: regulator-pm660-s5b-level { + /* PMFALCON S5 - VDD_MX supply */ + pmfalcon_s5b_level: regulator-pmfalcon-s5b-level { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s5b_level"; + regulator-name = "pmfalcon_s5b_level"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; - pm660_s5b_floor_level: regulator-pm660-s5b-floor-level { + pmfalcon_s5b_floor_level: regulator-pmfalcon-s5b-floor-level { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s5b_floor_level"; + regulator-name = "pmfalcon_s5b_floor_level"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; - pm660_s5b_level_ao: regulator-pm660-s5b-level-ao { + pmfalcon_s5b_level_ao: regulator-pmfalcon-s5b-level-ao { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_s5b_level_ao"; + regulator-name = "pmfalcon_s5b_level_ao"; qcom,hpm-min-load = <100000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; - pm660_l1a: regulator-pm660-l1a { + pmfalcon_l1a: regulator-pmfalcon-l1a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l1a"; + regulator-name = "pmfalcon_l1a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1250000>; }; - pm660_l2a: regulator-pm660-l2a { + pmfalcon_l2a: regulator-pmfalcon-l2a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l2a"; + regulator-name = "pmfalcon_l2a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1010000>; }; - pm660_l3a: regulator-pm660-l3a { + pmfalcon_l3a: regulator-pmfalcon-l3a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l3a"; + regulator-name = "pmfalcon_l3a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1010000>; }; /* TODO: remove if ADRASTEA CX/MX not voted from APPS */ - pm660_l5a: regulator-pm660-l5a { + pmfalcon_l5a: regulator-pmfalcon-l5a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l5a"; + regulator-name = "pmfalcon_l5a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <525000>; regulator-max-microvolt = <950000>; }; - pm660_l6a: regulator-pm660-l6a { + pmfalcon_l6a: regulator-pmfalcon-l6a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l6a"; + regulator-name = "pmfalcon_l6a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1370000>; }; - pm660_l7a: regulator-pm660-l7a { + pmfalcon_l7a: regulator-pmfalcon-l7a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l7a"; + regulator-name = "pmfalcon_l7a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - pm660_l8a: regulator-pm660-l8a { + pmfalcon_l8a: regulator-pmfalcon-l8a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l8a"; + regulator-name = "pmfalcon_l8a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1750000>; regulator-max-microvolt = <1900000>; }; - pm660_l9a: regulator-pm660-l9a { + pmfalcon_l9a: regulator-pmfalcon-l9a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l9a"; + regulator-name = "pmfalcon_l9a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1750000>; regulator-max-microvolt = <1900000>; }; - pm660_l10a: regulator-pm660-l10a { + pmfalcon_l10a: regulator-pmfalcon-l10a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l10a"; + regulator-name = "pmfalcon_l10a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; }; - pm660_l11a: regulator-pm660-l11a { + pmfalcon_l11a: regulator-pmfalcon-l11a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l11a"; + regulator-name = "pmfalcon_l11a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; }; - pm660_l12a: regulator-pm660-l12a { + pmfalcon_l12a: regulator-pmfalcon-l12a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l12a"; + regulator-name = "pmfalcon_l12a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; }; - pm660_l13a: regulator-pm660-l13a { + pmfalcon_l13a: regulator-pmfalcon-l13a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l13a"; + regulator-name = "pmfalcon_l13a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1750000>; regulator-max-microvolt = <1950000>; }; - pm660_l14a: regulator-pm660-l14a { + pmfalcon_l14a: regulator-pmfalcon-l14a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l14a"; + regulator-name = "pmfalcon_l14a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1710000>; regulator-max-microvolt = <1900000>; }; - pm660_l15a: regulator-pm660-l15a { + pmfalcon_l15a: regulator-pmfalcon-l15a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l15a"; + regulator-name = "pmfalcon_l15a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2950000>; }; - pm660_l17a: regulator-pm660-l17a { + pmfalcon_l17a: regulator-pmfalcon-l17a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l17a"; + regulator-name = "pmfalcon_l17a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2950000>; }; - pm660_l19a: regulator-pm660-l19a { + pmfalcon_l19a: regulator-pmfalcon-l19a { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l19a"; + regulator-name = "pmfalcon_l19a"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <3200000>; regulator-max-microvolt = <3400000>; }; - pm660_l1b: regulator-pm660-l1b { + pmfalcon_l1b: regulator-pmfalcon-l1b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l1b"; + regulator-name = "pmfalcon_l1b"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <800000>; regulator-max-microvolt = <925000>; }; - pm660_l2b: regulator-pm660-l2b { + pmfalcon_l2b: regulator-pmfalcon-l2b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l2b"; + regulator-name = "pmfalcon_l2b"; qcom,hpm-min-load = <5000>; regulator-min-microvolt = <350000>; regulator-max-microvolt = <3100000>; }; - pm660_l3b: regulator-pm660-l3b { + pmfalcon_l3b: regulator-pmfalcon-l3b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l3b"; + regulator-name = "pmfalcon_l3b"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1710000>; regulator-max-microvolt = <3600000>; }; - pm660_l4b: regulator-pm660-l4b { + pmfalcon_l4b: regulator-pmfalcon-l4b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l4b"; + regulator-name = "pmfalcon_l4b"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2950000>; }; - pm660_l5b: regulator-pm660-l5b { + pmfalcon_l5b: regulator-pmfalcon-l5b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l5b"; + regulator-name = "pmfalcon_l5b"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <1721000>; regulator-max-microvolt = <3600000>; }; - pm660_l6b: regulator-pm660-l6b { + pmfalcon_l6b: regulator-pmfalcon-l6b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l6b"; + regulator-name = "pmfalcon_l6b"; qcom,hpm-min-load = <5000>; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <3300000>; }; - pm660_l7b: regulator-pm660-l7b { + pmfalcon_l7b: regulator-pmfalcon-l7b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l7b"; + regulator-name = "pmfalcon_l7b"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3125000>; }; - pm660_l8b: regulator-pm660-l8b { + pmfalcon_l8b: regulator-pmfalcon-l8b { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l8b"; + regulator-name = "pmfalcon_l8b"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <3200000>; regulator-max-microvolt = <3400000>; }; - /* PM660B L9 = VDD_SSC_CX supply */ - pm660_l9b_level: regulator-pm660-l9b-level { + /* PMFALCON L9 = VDD_SSC_CX supply */ + pmfalcon_l9b_level: regulator-pmfalcon-l9b-level { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l9b_level"; + regulator-name = "pmfalcon_l9b_level"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; - pm660_l9b_floor_level: regulator-pm660-l9b-floor-level { + pmfalcon_l9b_floor_level: regulator-pmfalcon-l9b-floor-level { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l9b_floor_level"; + regulator-name = "pmfalcon_l9b_floor_level"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; - /* PM660B L10 = VDD_SSC_MX supply */ - pm660_l10b_level: regulator-pm660-l10b-level { + /* PMFALCON L10 = VDD_SSC_MX supply */ + pmfalcon_l10b_level: regulator-pmfalcon-l10b-level { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l10b_level"; + regulator-name = "pmfalcon_l10b_level"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; - pm660_l10b_floor_level: regulator-pm660-l10b-floor-level { + pmfalcon_l10b_floor_level: regulator-pmfalcon-l10b-floor-level { compatible = "qcom,stub-regulator"; - regulator-name = "pm660_l10b_floor_level"; + regulator-name = "pmfalcon_l10b_floor_level"; qcom,hpm-min-load = <10000>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; }; + pmfalcon_bob: regulator-pmfalcon-bob { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_bob"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + /* GFX Supply */ gfx_vreg_corner: regulator-gfx-corner { compatible = "qcom,stub-regulator"; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index bb5dc54d90f6..67748d6683c0 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -151,19 +151,19 @@ modem_fw_mem: modem_fw_region@8ac00000 { compatible = "removed-dma-pool"; no-map; - reg = <0x0 0x8ac00000 0x0 0x7800000>; + reg = <0x0 0x8ac00000 0x0 0x7e00000>; }; - adsp_fw_mem: adsp_fw_region@92400000 { + adsp_fw_mem: adsp_fw_region@92a00000 { compatible = "removed-dma-pool"; no-map; - reg = <0x0 0x92400000 0x0 0x1e00000>; + reg = <0x0 0x92a00000 0x0 0x1e00000>; }; - cdsp_fw_mem: cdsp_fw_region@94200000 { + cdsp_fw_mem: cdsp_fw_region@94800000 { compatible = "removed-dma-pool"; no-map; - reg = <0x0 0x94200000 0x0 0x600000>; + reg = <0x0 0x94800000 0x0 0x600000>; }; venus_fw_mem: venus_fw_region { @@ -231,6 +231,39 @@ clock-frequency = <19200000>; }; + spmi_bus: qcom,spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x800f000 0x1000>, + <0x8400000 0x1000000>, + <0x9400000 0x1000000>, + <0xa400000 0x220000>, + <0x800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + qcom,not-wakeup; /* Needed until Full-boot-chain enabled */ + status = "ok"; + }; + + wdog: qcom,wdt@17817000 { + status = "disabled"; + compatible = "qcom,msm-watchdog"; + reg = <0x17817000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + qcom,sps { compatible = "qcom,msm_sps_4k"; qcom,pipe-attr-ee; @@ -359,6 +392,16 @@ qcom,mpu-enabled; }; + dcc: dcc@10b3000 { + compatible = "qcom,dcc"; + reg = <0x10b3000 0x1000>, + <0x10b4000 0x800>; + reg-names = "dcc-base", "dcc-ram-base"; + + clocks = <&clock_gcc RPM_QDSS_CLK>; + clock-names = "dcc_clk"; + }; + qcom,glink-smem-native-xprt-modem@86000000 { compatible = "qcom,glink-smem-native-xprt"; reg = <0x86000000 0x200000>, @@ -401,7 +444,7 @@ label = "cdsp"; }; - qcom,glink-smem-native-xprt-rpm@68000 { + qcom,glink-smem-native-xprt-rpm@778000 { compatible = "qcom,glink-rpm-native-xprt"; reg = <0x778000 0x7000>, <0x17911008 0x4>; @@ -507,6 +550,13 @@ }; }; + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-glink"; + qcom,glink-edge = "rpm"; + rpm-channel-name = "rpm_requests"; + rpm-standalone; /* TODO: remove this after bring up */ + }; + qcom,ipc_router { compatible = "qcom,ipc_router"; qcom,node-id = <1>; @@ -541,6 +591,35 @@ qcom,xprt-version = <1>; qcom,fragmented-data; }; + + qcom,venus@cce0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xcce0000 0x4000>; + + vdd-supply = <&gdsc_venus>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&clock_mmss MMSS_VIDEO_CORE_CLK>, + <&clock_mmss MMSS_VIDEO_AHB_CLK>, + <&clock_mmss MMSS_VIDEO_AXI_CLK>; + clock-names = "core_clk","iface_clk", + "bus_clk"; + qcom,proxy-clock-names = "core_clk", + "iface_clk","bus_clk"; + + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + + qcom,pas-id = <9>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&venus_fw_mem>; + status = "ok"; + }; }; #include "msmfalcon-ion.dtsi" @@ -620,3 +699,5 @@ &gdsc_gpu_cx { status = "ok"; }; +#include "msm-pmfalcon.dtsi" +#include "msm-pm2falcon.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmtriton-smp2p.dtsi b/arch/arm/boot/dts/qcom/msmtriton-smp2p.dtsi new file mode 100644 index 000000000000..695a4f3b63c7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmtriton-smp2p.dtsi @@ -0,0 +1,136 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 451 1>; + }; + + qcom,smp2p-adsp@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + smp2pgpio_smp2p_15_in: qcom,smp2pgpio-smp2p-15-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_in { + compatible = "qcom,smp2pgpio_test_smp2p_15_in"; + gpios = <&smp2pgpio_smp2p_15_in 0 0>; + }; + + smp2pgpio_smp2p_15_out: qcom,smp2pgpio-smp2p-15-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_out { + compatible = "qcom,smp2pgpio_test_smp2p_15_out"; + gpios = <&smp2pgpio_smp2p_15_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + smp2pgpio_sleepstate_2_out: qcom,smp2pgpio-sleepstate-gpio-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "sleepstate"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio-sleepstate-2-out { + compatible = "qcom,smp2pgpio-sleepstate-out"; + gpios = <&smp2pgpio_sleepstate_2_out 0 0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index 17198e462024..3f0d4cc48696 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -136,8 +136,56 @@ soc: soc { }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + removed_region: removed_region0@85800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85800000 0x0 0x3700000>; + }; + + modem_fw_mem: modem_fw_region@8ac00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8ac00000 0x0 0x7e00000>; + }; + + adsp_fw_mem: adsp_fw_region@92a00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x92a00000 0x0 0x1e00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + secure_display_memory: secure_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x5c00000>; + }; + }; }; +#include "msmtriton-smp2p.dtsi" &soc { #address-cells = <1>; #size-cells = <1>; @@ -172,6 +220,15 @@ qcom,pipe-attr-ee; }; + tsens: tsens@10ad000 { + compatible = "qcom,msmtriton-tsens"; + reg = <0x10ad000 0x2000>; + reg-names = "tsens_physical"; + interrupts = <0 184 0>, <0 430 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + qcom,sensors = <12>; + }; + uartblsp1dm1: serial@0c170000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xc170000 0x1000>; @@ -265,4 +322,172 @@ compatible = "qcom,dummycc"; #clock-cells = <1>; }; + + qcom,ipc-spinlock@1f40000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1f40000 0x8000>; + qcom,num-locks = <8>; + }; + + qcom,smem@86000000 { + compatible = "qcom,smem"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>, + <0x778000 0x7000>, + <0x1fd4000 0x8>; + reg-names = "smem", "irq-reg-base", "aux-mem1", + "smem_targ_info_reg"; + qcom,mpu-enabled; + }; + + qcom,glink-smem-native-xprt-modem@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x8000>; + interrupts = <0 452 1>; + label = "mpss"; + }; + + qcom,glink-smem-native-xprt-adsp@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x200>; + interrupts = <0 157 1>; + label = "lpass"; + qcom,qos-config = <&glink_qos_adsp>; + qcom,ramp-time = <0xaf>; + }; + + glink_qos_adsp: qcom,glink-qos-config-adsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x3c 0x0>, + <0x3c 0x0>, + <0x3c 0x0>, + <0x3c 0x0>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0xa>; + }; + + qcom,glink-smem-native-xprt-rpm@778000 { + compatible = "qcom,glink-rpm-native-xprt"; + reg = <0x778000 0x7000>, + <0x17911008 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = <0 168 1>; + label = "rpm"; + }; + + qcom,glink_pkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-loopback_cntl { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; + }; + + qcom,glinkpkt-loopback_data { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + glink_mpss: qcom,glink-ssr-modem { + compatible = "qcom,glink_ssr"; + label = "modem"; + qcom,edge = "mpss"; + qcom,notify-edges = <&glink_lpass>, <&glink_rpm>; + qcom,xprt = "smem"; + }; + + glink_lpass: qcom,glink-ssr-adsp { + compatible = "qcom,glink_ssr"; + label = "adsp"; + qcom,edge = "lpass"; + qcom,notify-edges = <&glink_mpss>, <&glink_rpm>; + qcom,xprt = "smem"; + }; + + glink_rpm: qcom,glink-ssr-rpm { + compatible = "qcom,glink_ssr"; + label = "rpm"; + qcom,edge = "rpm"; + qcom,notify-edges = <&glink_lpass>, <&glink_mpss>; + qcom,xprt = "smem"; + }; + + qcom,ipc_router { + compatible = "qcom,ipc_router"; + qcom,node-id = <1>; + }; + + qcom,ipc_router_modem_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "mpss"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,ipc_router_q6_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "lpass"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; }; diff --git a/arch/arm/configs/msmcortex_defconfig b/arch/arm/configs/msmcortex_defconfig index 0a20c52bd3b2..d7efed07a31f 100644 --- a/arch/arm/configs/msmcortex_defconfig +++ b/arch/arm/configs/msmcortex_defconfig @@ -261,7 +261,6 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y @@ -459,7 +458,6 @@ CONFIG_TRACER_PKT=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_MSM_MPM_OF=y CONFIG_MSM_EVENT_TIMER=y -CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_QCOM_REMOTEQDSS=y CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MEM_SHARE_QMI_SERVICE=y diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/msmfalcon_defconfig index 0a20c52bd3b2..db50dce9f9a4 100644 --- a/arch/arm/configs/msmfalcon_defconfig +++ b/arch/arm/configs/msmfalcon_defconfig @@ -261,7 +261,6 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y @@ -416,6 +415,9 @@ CONFIG_GPIO_USB_DETECT=y CONFIG_USB_BAM=y CONFIG_REMOTE_SPINLOCK_MSM=y CONFIG_ARM_SMMU=y +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y CONFIG_QCOM_COMMON_LOG=y CONFIG_MSM_SMEM=y CONFIG_QPNP_HAPTIC=y @@ -459,7 +461,6 @@ CONFIG_TRACER_PKT=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_MSM_MPM_OF=y CONFIG_MSM_EVENT_TIMER=y -CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_QCOM_REMOTEQDSS=y CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MEM_SHARE_QMI_SERVICE=y diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 1d45320ee125..f56a831de043 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -37,6 +37,7 @@ #include <linux/kallsyms.h> #include <linux/proc_fs.h> #include <linux/export.h> +#include <linux/cpumask.h> #include <asm/hardware/cache-l2x0.h> #include <asm/hardware/cache-uniphier.h> @@ -127,6 +128,7 @@ static bool migrate_one_irq(struct irq_desc *desc) const struct cpumask *affinity = irq_data_get_affinity_mask(d); struct irq_chip *c; bool ret = false; + struct cpumask available_cpus; /* * If this is a per-CPU interrupt, or the affinity does not @@ -135,8 +137,15 @@ static bool migrate_one_irq(struct irq_desc *desc) if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity)) return false; + cpumask_copy(&available_cpus, affinity); + cpumask_andnot(&available_cpus, &available_cpus, cpu_isolated_mask); + affinity = &available_cpus; + if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { - affinity = cpu_online_mask; + cpumask_andnot(&available_cpus, cpu_online_mask, + cpu_isolated_mask); + if (cpumask_empty(affinity)) + affinity = cpu_online_mask; ret = true; } diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 598323a1842e..e683d147816c 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -190,6 +190,13 @@ static int __init parse_cluster(struct device_node *cluster, int depth) return 0; } +static DEFINE_PER_CPU(unsigned long, cpu_efficiency) = SCHED_CAPACITY_SCALE; + +unsigned long arch_get_cpu_efficiency(int cpu) +{ + return per_cpu(cpu_efficiency, cpu); +} + #ifdef CONFIG_OF struct cpu_efficiency { const char *compatible; @@ -266,6 +273,7 @@ static int __init parse_dt_topology(void) for_each_possible_cpu(cpu) { const u32 *rate; int len; + u32 efficiency; /* too early to use cpu->of_node */ cn = of_get_cpu_node(cpu, NULL); @@ -274,12 +282,26 @@ static int __init parse_dt_topology(void) continue; } - for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++) - if (of_device_is_compatible(cn, cpu_eff->compatible)) - break; + /* + * The CPU efficiency value passed from the device tree + * overrides the value defined in the table_efficiency[] + */ + if (of_property_read_u32(cn, "efficiency", &efficiency) < 0) { + + for (cpu_eff = table_efficiency; + cpu_eff->compatible; cpu_eff++) - if (cpu_eff->compatible == NULL) - continue; + if (of_device_is_compatible(cn, + cpu_eff->compatible)) + break; + + if (cpu_eff->compatible == NULL) + continue; + + efficiency = cpu_eff->efficiency; + } + + per_cpu(cpu_efficiency, cpu) = efficiency; rate = of_get_property(cn, "clock-frequency", &len); if (!rate || len != 4) { @@ -288,7 +310,7 @@ static int __init parse_dt_topology(void) continue; } - capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency; + capacity = ((be32_to_cpup(rate)) >> 20) * efficiency; /* Save min capacity of the system */ if (capacity < min_capacity) diff --git a/arch/arm64/configs/msm-perf_defconfig b/arch/arm64/configs/msm-perf_defconfig index 84bb603c3142..6ba13806cf16 100644 --- a/arch/arm64/configs/msm-perf_defconfig +++ b/arch/arm64/configs/msm-perf_defconfig @@ -282,7 +282,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_ATMEL_MAXTOUCH_TS=y @@ -525,7 +524,6 @@ CONFIG_MSM_PIL_MSS_QDSP6V5=y CONFIG_TRACER_PKT=y CONFIG_MSM_MPM_OF=y CONFIG_MSM_AVTIMER=y -CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y CONFIG_MSM_RPM_LOG=y CONFIG_MSM_RPM_STATS_LOG=y diff --git a/arch/arm64/configs/msm_defconfig b/arch/arm64/configs/msm_defconfig index 6119ff12d46d..bc5fc905188c 100644 --- a/arch/arm64/configs/msm_defconfig +++ b/arch/arm64/configs/msm_defconfig @@ -269,7 +269,6 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_ATMEL_MAXTOUCH_TS=y @@ -527,7 +526,6 @@ CONFIG_TRACER_PKT=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_MSM_MPM_OF=y CONFIG_MSM_AVTIMER=y -CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_QCOM_REMOTEQDSS=y CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index 08288e1b5c25..50c8848bc6f9 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -16,6 +16,7 @@ CONFIG_CGROUP_CPUACCT=y CONFIG_RT_GROUP_SCHED=y CONFIG_SCHED_HMP=y CONFIG_SCHED_HMP_CSTATE_AWARE=y +CONFIG_SCHED_CORE_CTL=y CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set @@ -272,7 +273,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y @@ -525,7 +525,6 @@ CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_MSM_MPM_OF=y CONFIG_MSM_EVENT_TIMER=y CONFIG_MSM_AVTIMER=y -CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_QCOM_REMOTEQDSS=y CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index 9e2727c4fe1e..3d1a01491c0c 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -17,6 +17,7 @@ CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y CONFIG_SCHED_HMP=y CONFIG_SCHED_HMP_CSTATE_AWARE=y +CONFIG_SCHED_CORE_CTL=y CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set @@ -273,7 +274,6 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y @@ -544,7 +544,6 @@ CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_MSM_MPM_OF=y CONFIG_MSM_EVENT_TIMER=y CONFIG_MSM_AVTIMER=y -CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_QCOM_REMOTEQDSS=y CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y diff --git a/arch/arm64/configs/msmfalcon-perf_defconfig b/arch/arm64/configs/msmfalcon-perf_defconfig index 39c2d3f71c5a..79da74733e36 100644 --- a/arch/arm64/configs/msmfalcon-perf_defconfig +++ b/arch/arm64/configs/msmfalcon-perf_defconfig @@ -272,7 +272,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y @@ -522,7 +521,6 @@ CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_MSM_MPM_OF=y CONFIG_MSM_EVENT_TIMER=y CONFIG_MSM_AVTIMER=y -CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_QCOM_REMOTEQDSS=y CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y diff --git a/arch/arm64/configs/msmfalcon_defconfig b/arch/arm64/configs/msmfalcon_defconfig index a277038b3fc3..62e929b998b9 100644 --- a/arch/arm64/configs/msmfalcon_defconfig +++ b/arch/arm64/configs/msmfalcon_defconfig @@ -273,7 +273,6 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y @@ -541,7 +540,6 @@ CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_MSM_MPM_OF=y CONFIG_MSM_EVENT_TIMER=y CONFIG_MSM_AVTIMER=y -CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_QCOM_REMOTEQDSS=y CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 3691553f218e..c3c6557eb083 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -19,6 +19,7 @@ #include <asm/cpu.h> #include <asm/cputype.h> #include <asm/cpufeature.h> +#include <asm/elf.h> #include <linux/bitops.h> #include <linux/bug.h> @@ -107,6 +108,8 @@ static int c_show(struct seq_file *m, void *v) { int i, j; + seq_printf(m, "Processor\t: AArch64 Processor rev %d (%s)\n", + read_cpuid_id() & 15, ELF_PLATFORM); for_each_present_cpu(i) { struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); u32 midr = cpuinfo->reg_midr; diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 10db9cbaf49e..c9df86d68b44 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -683,7 +683,7 @@ int armv8pmu_probe_num_events(struct arm_pmu *arm_pmu) ret = smp_call_function_any(&arm_pmu->supported_cpus, armv8pmu_read_num_pmnc_events, &arm_pmu->num_events, 1); - if (!ret) + if (ret) idle_notifier_unregister(&pmu_idle_nb->perf_cpu_idle_nb); return ret; diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 129fb3f8c322..7c4563cbccf3 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -259,7 +259,7 @@ void __show_regs(struct pt_regs *regs) printk("\n"); } if (!user_mode(regs)) - show_extra_register_data(regs, 256); + show_extra_register_data(regs, 64); printk("\n"); } |