diff options
Diffstat (limited to 'arch')
84 files changed, 2065 insertions, 1768 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 135dff88e882..398a9fbcd427 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -564,6 +564,7 @@ config ARCH_DOVE select PINCTRL_DOVE select PLAT_ORION_LEGACY select USB_ARCH_HAS_EHCI + select MVEBU_MBUS help Support for the Marvell Dove SoC 88AP510 @@ -577,6 +578,7 @@ config ARCH_KIRKWOOD select PINCTRL select PINCTRL_KIRKWOOD select PLAT_ORION_LEGACY + select MVEBU_MBUS help Support for the following Marvell Kirkwood series SoCs: 88F6180, 88F6192 and 88F6281. @@ -588,6 +590,7 @@ config ARCH_MV78XX0 select GENERIC_CLOCKEVENTS select PCI select PLAT_ORION_LEGACY + select MVEBU_MBUS help Support for the following Marvell MV78xx0 series SoCs: MV781x0, MV782x0. @@ -600,6 +603,7 @@ config ARCH_ORION5X select GENERIC_CLOCKEVENTS select PCI select PLAT_ORION_LEGACY + select MVEBU_MBUS help Support for the following Marvell Orion 5x series SoCs: Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index e34b280ce6ec..2353b1f13704 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -30,68 +30,87 @@ }; soc { - serial@d0012000 { - clock-frequency = <200000000>; - status = "okay"; - }; - sata@d00a0000 { - nr-ports = <2>; - status = "okay"; - }; + internal-regs { + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; }; - phy1: ethernet-phy@1 { - reg = <1>; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; }; - }; - ethernet@d0070000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@d0074000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins1>; + pinctrl-names = "default"; + /* + * This device is disabled by default, because + * using the SD card connector requires + * changing the default CON40 connector + * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a + * different connector + * "DB-88F6710_MPP_RGMII_SD_Jumper". + */ + status = "disabled"; + /* No CD or WP GPIOs */ + }; - mvsdio@d00d4000 { - pinctrl-0 = <&sdio_pins1>; - pinctrl-names = "default"; - /* - * This device is disabled by default, because - * using the SD card connector requires - * changing the default CON40 connector - * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a - * different connector - * "DB-88F6710_MPP_RGMII_SD_Jumper". - */ - status = "disabled"; - /* No CD or WP GPIOs */ - }; + usb@50000 { + status = "okay"; + }; - usb@d0050000 { - status = "okay"; - }; + usb@51000 { + status = "okay"; + }; - usb@d0051000 { - status = "okay"; - }; + spi0: spi@10600 { + status = "okay"; - spi0: spi@d0010600 { - status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mx25l25635e"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + }; + }; - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mx25l25635e"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * both standard PCIe slots and mini-PCIe + * slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index dd0c57dd9f30..14e36e19d515 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -25,50 +25,116 @@ }; soc { - serial@d0012000 { - clock-frequency = <200000000>; - status = "okay"; - }; - timer@d0020300 { - clock-frequency = <600000000>; - status = "okay"; - }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; + internal-regs { + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; }; + timer@20300 { + clock-frequency = <600000000>; + status = "okay"; + }; + + pinctrl { + pwr_led_pin: pwr-led-pin { + marvell,pins = "mpp63"; + marvell,function = "gpo"; + }; - phy1: ethernet-phy@1 { - reg = <1>; + stat_led_pins: stat-led-pins { + marvell,pins = "mpp64", "mpp65"; + marvell,function = "gpio"; + }; }; - }; - ethernet@d0070000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@d0074000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - mvsdio@d00d4000 { - pinctrl-0 = <&sdio_pins2>; - pinctrl-names = "default"; - status = "okay"; - /* - * No CD or WP GPIOs: SDIO interface used for - * Wifi/Bluetooth chip - */ - }; + gpio_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_led_pin &stat_led_pins>; - usb@d0050000 { - status = "okay"; - }; + green_pwr_led { + label = "mirabox:green:pwr"; + gpios = <&gpio1 31 1>; + linux,default-trigger = "heartbeat"; + }; + + blue_stat_led { + label = "mirabox:blue:stat"; + gpios = <&gpio2 0 1>; + linux,default-trigger = "cpu0"; + }; + + green_stat_led { + label = "mirabox:green:stat"; + gpios = <&gpio2 1 1>; + default-state = "off"; + }; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins3>; + pinctrl-names = "default"; + status = "okay"; + /* + * No CD or WP GPIOs: SDIO interface used for + * Wifi/Bluetooth chip + */ + }; + + usb@50000 { + status = "okay"; + }; - usb@d0051000 { - status = "okay"; + usb@51000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + pca9505: pca9505@25 { + compatible = "nxp,pca9505"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x25>; + }; + }; + + pcie-controller { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected on the PCB to a USB 3.0 XHCI controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 070bba4f2585..130f8390a7e4 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -28,49 +28,62 @@ }; soc { - serial@d0012000 { - clock-frequency = <200000000>; - status = "okay"; - }; - sata@d00a0000 { - nr-ports = <2>; - status = "okay"; - }; + internal-regs { + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; }; - phy1: ethernet-phy@1 { - reg = <1>; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; }; - }; - ethernet@d0070000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - }; - ethernet@d0074000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins1>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + }; - mvsdio@d00d4000 { - pinctrl-0 = <&sdio_pins1>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - }; + usb@50000 { + status = "okay"; + }; - usb@d0050000 { - status = "okay"; - }; + usb@51000 { + status = "okay"; + }; - usb@d0051000 { - status = "okay"; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + button@1 { + label = "Software Button"; + linux,code = <116>; + gpios = <&gpio0 6 1>; + }; + }; }; }; -}; + }; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 5b708208b607..272bbc65fab0 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -16,7 +16,7 @@ * 370 and Armada XP SoC. */ -/include/ "skeleton.dtsi" +/include/ "skeleton64.dtsi" / { model = "Marvell Armada 370 and XP SoC"; @@ -28,159 +28,203 @@ }; }; - mpic: interrupt-controller@d0020000 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - }; - - coherency-fabric@d0020200 { - compatible = "marvell,coherency-fabric"; - reg = <0xd0020200 0xb0>, - <0xd0021810 0x1c>; - }; - soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&mpic>; - ranges; + ranges = <0 0 0xd0000000 0x100000>; - serial@d0012000 { + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpic: interrupt-controller@20000 { + compatible = "marvell,mpic"; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + }; + + coherency-fabric@20200 { + compatible = "marvell,coherency-fabric"; + reg = <0x20200 0xb0>, <0x21810 0x1c>; + }; + + serial@12000 { compatible = "snps,dw-apb-uart"; - reg = <0xd0012000 0x100>; + reg = <0x12000 0x100>; reg-shift = <2>; interrupts = <41>; reg-io-width = <1>; status = "disabled"; - }; - serial@d0012100 { + }; + serial@12100 { compatible = "snps,dw-apb-uart"; - reg = <0xd0012100 0x100>; + reg = <0x12100 0x100>; reg-shift = <2>; interrupts = <42>; reg-io-width = <1>; status = "disabled"; - }; - - timer@d0020300 { - compatible = "marvell,armada-370-xp-timer"; - reg = <0xd0020300 0x30>, - <0xd0021040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>; - }; - - addr-decoding@d0020000 { - compatible = "marvell,armada-addr-decoding-controller"; - reg = <0xd0020000 0x258>; - }; - - sata@d00a0000 { - compatible = "marvell,orion-sata"; - reg = <0xd00a0000 0x2400>; - interrupts = <55>; - clocks = <&gateclk 15>, <&gateclk 30>; - clock-names = "0", "1"; - status = "disabled"; - }; + }; + + timer@20300 { + compatible = "marvell,armada-370-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts = <37>, <38>, <39>, <40>, <5>, <6>; + clocks = <&coreclk 2>; + }; + + sata@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x2400>; + interrupts = <55>; + clocks = <&gateclk 15>, <&gateclk 30>; + clock-names = "0", "1"; + status = "disabled"; + }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0xd0072004 0x4>; - }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; + }; - ethernet@d0070000 { + ethernet@70000 { compatible = "marvell,armada-370-neta"; - reg = <0xd0070000 0x2500>; + reg = <0x70000 0x2500>; interrupts = <8>; clocks = <&gateclk 4>; status = "disabled"; - }; + }; - ethernet@d0074000 { + ethernet@74000 { compatible = "marvell,armada-370-neta"; - reg = <0xd0074000 0x2500>; + reg = <0x74000 0x2500>; interrupts = <10>; clocks = <&gateclk 3>; status = "disabled"; - }; - - i2c0: i2c@d0011000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0xd0011000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <31>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@d0011100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0xd0011100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0xd0010300 0x20>; - interrupts = <50>; - }; - - mvsdio@d00d4000 { - compatible = "marvell,orion-sdio"; - reg = <0xd00d4000 0x200>; - interrupts = <54>; - clocks = <&gateclk 17>; - status = "disabled"; - }; - - usb@d0050000 { - compatible = "marvell,orion-ehci"; - reg = <0xd0050000 0x500>; - interrupts = <45>; - status = "disabled"; - }; - - usb@d0051000 { - compatible = "marvell,orion-ehci"; - reg = <0xd0051000 0x500>; - interrupts = <46>; - status = "disabled"; - }; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <31>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + rtc@10300 { + compatible = "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <50>; + }; + + mvsdio@d4000 { + compatible = "marvell,orion-sdio"; + reg = <0xd4000 0x200>; + interrupts = <54>; + clocks = <&gateclk 17>; + status = "disabled"; + }; - spi0: spi@d0010600 { - compatible = "marvell,orion-spi"; - reg = <0xd0010600 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <30>; - clocks = <&coreclk 0>; - status = "disabled"; - }; + usb@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x500>; + interrupts = <45>; + status = "disabled"; + }; - spi1: spi@d0010680 { - compatible = "marvell,orion-spi"; - reg = <0xd0010680 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - status = "disabled"; + usb@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x500>; + interrupts = <46>; + status = "disabled"; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + reg = <0x10600 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <30>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,orion-spi"; + reg = <0x10680 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-bootcs@10400 { + compatible = "marvell,mvebu-devbus"; + reg = <0x10400 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs0@10408 { + compatible = "marvell,mvebu-devbus"; + reg = <0x10408 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs1@10410 { + compatible = "marvell,mvebu-devbus"; + reg = <0x10410 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs2@10418 { + compatible = "marvell,mvebu-devbus"; + reg = <0x10418 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs3@10420 { + compatible = "marvell,mvebu-devbus"; + reg = <0x10420 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; }; -}; - + }; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 8188d138020e..b2c1b5af9749 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -16,16 +16,11 @@ */ /include/ "armada-370-xp.dtsi" +/include/ "skeleton.dtsi" / { model = "Marvell Armada 370 family SoC"; compatible = "marvell,armada370", "marvell,armada-370-xp"; - L2: l2-cache { - compatible = "marvell,aurora-outer-cache"; - reg = <0xd0008000 0x1000>; - cache-id-part = <0x100>; - wt-override; - }; aliases { gpio0 = &gpio0; @@ -33,125 +28,198 @@ gpio2 = &gpio2; }; - mpic: interrupt-controller@d0020000 { - reg = <0xd0020a00 0x1d0>, - <0xd0021870 0x58>; - }; - soc { - system-controller@d0018200 { + ranges = <0 0xd0000000 0x100000>; + internal-regs { + system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; - reg = <0xd0018200 0x100>; - }; - - pinctrl { - compatible = "marvell,mv88f6710-pinctrl"; - reg = <0xd0018000 0x38>; + reg = <0x18200 0x100>; + }; - sdio_pins1: sdio-pins1 { - marvell,pins = "mpp9", "mpp11", "mpp12", - "mpp13", "mpp14", "mpp15"; - marvell,function = "sd0"; + L2: l2-cache { + compatible = "marvell,aurora-outer-cache"; + reg = <0xd0008000 0x1000>; + cache-id-part = <0x100>; + wt-override; }; - sdio_pins2: sdio-pins2 { - marvell,pins = "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52"; - marvell,function = "sd0"; + mpic: interrupt-controller@20000 { + reg = <0x20a00 0x1d0>, <0x21870 0x58>; }; - }; - - gpio0: gpio@d0018100 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - }; - gpio1: gpio@d0018140 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018140 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - }; + pinctrl { + compatible = "marvell,mv88f6710-pinctrl"; + reg = <0x18000 0x38>; + + sdio_pins1: sdio-pins1 { + marvell,pins = "mpp9", "mpp11", "mpp12", + "mpp13", "mpp14", "mpp15"; + marvell,function = "sd0"; + }; + + sdio_pins2: sdio-pins2 { + marvell,pins = "mpp47", "mpp48", "mpp49", + "mpp50", "mpp51", "mpp52"; + marvell,function = "sd0"; + }; + + sdio_pins3: sdio-pins3 { + marvell,pins = "mpp48", "mpp49", "mpp50", + "mpp51", "mpp52", "mpp53"; + marvell,function = "sd0"; + }; + }; - gpio2: gpio@d0018180 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018180 0x40>; - ngpios = <2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <91>; - }; + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; - coreclk: mvebu-sar@d0018230 { - compatible = "marvell,armada-370-core-clock"; - reg = <0xd0018230 0x08>; - #clock-cells = <1>; - }; + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + }; - gateclk: clock-gating-control@d0018220 { - compatible = "marvell,armada-370-gating-clock"; - reg = <0xd0018220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; + gpio2: gpio@18180 { + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <91>; + }; - xor@d0060800 { - compatible = "marvell,orion-xor"; - reg = <0xd0060800 0x100 - 0xd0060A00 0x100>; - status = "okay"; + coreclk: mvebu-sar@18230 { + compatible = "marvell,armada-370-core-clock"; + reg = <0x18230 0x08>; + #clock-cells = <1>; + }; - xor00 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-370-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; }; - xor01 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; + + xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60A00 0x100>; + status = "okay"; + + xor00 { + interrupts = <51>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <52>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; }; - }; - xor@d0060900 { - compatible = "marvell,orion-xor"; - reg = <0xd0060900 0x100 - 0xd0060b00 0x100>; - status = "okay"; + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + status = "okay"; + + xor10 { + interrupts = <94>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <95>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; - xor10 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; + usb@50000 { + clocks = <&coreclk 0>; }; - xor11 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; + + usb@51000 { + clocks = <&coreclk 0>; }; - }; - usb@d0050000 { - clocks = <&coreclk 0>; - }; + thermal@18300 { + compatible = "marvell,armada370-thermal"; + reg = <0x18300 0x4 + 0x18304 0x4>; + status = "okay"; + }; - usb@d0051000 { - clocks = <&coreclk 0>; + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + reg = <0x40000 0x2000>, <0x80000 0x2000>; + + reg-names = "pcie0.0", "pcie1.0"; + + ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + }; }; - }; }; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index e83505e4c236..d6cc8bf8272e 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -26,99 +26,134 @@ memory { device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ + reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ }; soc { - serial@d0012000 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012100 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012200 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012300 { - clock-frequency = <250000000>; - status = "okay"; - }; - - sata@d00a0000 { - nr-ports = <2>; - status = "okay"; - }; - - mdio { - phy0: ethernet-phy@0 { - reg = <0>; + internal-regs { + serial@12000 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@12100 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@12200 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@12300 { + clock-frequency = <250000000>; + status = "okay"; }; - phy1: ethernet-phy@1 { - reg = <1>; + sata@a0000 { + nr-ports = <2>; + status = "okay"; }; - phy2: ethernet-phy@2 { - reg = <25>; + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <25>; + }; + + phy3: ethernet-phy@3 { + reg = <27>; + }; }; - phy3: ethernet-phy@3 { - reg = <27>; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; }; - }; - ethernet@d0070000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@d0074000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - ethernet@d0030000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - }; - ethernet@d0034000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; - }; + mvsdio@d4000 { + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + }; - mvsdio@d00d4000 { - pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - }; + usb@50000 { + status = "okay"; + }; - usb@d0050000 { - status = "okay"; - }; + usb@51000 { + status = "okay"; + }; - usb@d0051000 { - status = "okay"; - }; + usb@52000 { + status = "okay"; + }; - usb@d0052000 { - status = "okay"; - }; + spi0: spi@10600 { + status = "okay"; - spi0: spi@d0010600 { - status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p64"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + }; + }; - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; + pcie-controller { + status = "okay"; + + /* + * All 6 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 0, Lane 2 */ + status = "okay"; + }; + pcie@4,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 1c8afe2ffebc..26ad06fc147e 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -26,87 +26,141 @@ memory { device_type = "memory"; - /* - * 4 GB of plug-in RAM modules by default but only 3GB - * are visible, the amount of memory available can be - * changed by the bootloader according the size of the - * module actually plugged + * 8 GB of plug-in RAM modules by default.The amount + * of memory available can be changed by the + * bootloader according the size of the module + * actually plugged. Only 7GB are usable because + * addresses from 0xC0000000 to 0xffffffff are used by + * the internal registers of the SoC. */ - reg = <0x00000000 0xC0000000>; + reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, + <0x00000001 0x00000000 0x00000001 0x00000000>; }; soc { - serial@d0012000 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012100 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012200 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012300 { - clock-frequency = <250000000>; - status = "okay"; - }; - - sata@d00a0000 { - nr-ports = <2>; - status = "okay"; - }; + internal-regs { + serial@12000 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@12100 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@12200 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@12300 { + clock-frequency = <250000000>; + status = "okay"; + }; - mdio { - phy0: ethernet-phy@0 { - reg = <16>; + sata@a0000 { + nr-ports = <2>; + status = "okay"; }; - phy1: ethernet-phy@1 { - reg = <17>; + mdio { + phy0: ethernet-phy@0 { + reg = <16>; + }; + + phy1: ethernet-phy@1 { + reg = <17>; + }; + + phy2: ethernet-phy@2 { + reg = <18>; + }; + + phy3: ethernet-phy@3 { + reg = <19>; + }; }; - phy2: ethernet-phy@2 { - reg = <18>; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "rgmii-id"; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "rgmii-id"; + }; + + spi0: spi@10600 { + status = "okay"; - phy3: ethernet-phy@3 { - reg = <19>; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; }; - }; - ethernet@d0070000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@d0074000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - ethernet@d0030000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "rgmii-id"; - }; - ethernet@d0034000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "rgmii-id"; - }; + devbus-bootcs@10400 { + status = "okay"; + ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; - spi0: spi@d0010600 { - status = "okay"; + pcie-controller { + status = "okay"; - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index f56c40599f5b..f8eaa383e07f 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -25,56 +25,162 @@ }; cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - }; + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + }; }; soc { - pinctrl { - compatible = "marvell,mv78230-pinctrl"; - reg = <0xd0018000 0x38>; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; + internal-regs { + pinctrl { + compatible = "marvell,mv78230-pinctrl"; + reg = <0x18000 0x38>; + + sdio_pins: sdio-pins { + marvell,pins = "mpp30", "mpp31", "mpp32", + "mpp33", "mpp34", "mpp35"; + marvell,function = "sd0"; + }; }; - }; - gpio0: gpio@d0018100 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - }; + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <87>, <88>, <89>; + }; - gpio1: gpio@d0018140 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018140 0x40>; - ngpios = <17>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <87>, <88>, <89>; + /* + * MV78230 has 2 PCIe units Gen2.0: One unit can be + * configured as x4 or quad x1 lanes. One unit is + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + +#address-cells = <3>; +#size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index f8f2b787d2b0..f4029f015aff 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -26,75 +26,199 @@ }; cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - }; + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + }; }; soc { - pinctrl { - compatible = "marvell,mv78260-pinctrl"; - reg = <0xd0018000 0x38>; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; + internal-regs { + pinctrl { + compatible = "marvell,mv78260-pinctrl"; + reg = <0x18000 0x38>; + + sdio_pins: sdio-pins { + marvell,pins = "mpp30", "mpp31", "mpp32", + "mpp33", "mpp34", "mpp35"; + marvell,function = "sd0"; + }; }; - }; - gpio0: gpio@d0018100 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - }; + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; - gpio1: gpio@d0018140 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018140 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - }; + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + }; - gpio2: gpio@d0018180 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <91>; - }; + gpio2: gpio@18180 { + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <91>; + }; - ethernet@d0034000 { + ethernet@34000 { compatible = "marvell,armada-370-neta"; - reg = <0xd0034000 0x2500>; + reg = <0x34000 0x2500>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; + }; + + /* + * MV78260 has 3 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. One unit is + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + pcie@10,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 936c25dc32b0..6ab56bd35de9 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -27,89 +27,279 @@ cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <2>; - clocks = <&cpuclk 2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <3>; - clocks = <&cpuclk 3>; - }; - }; + #address-cells = <1>; + #size-cells = <0>; - soc { - pinctrl { - compatible = "marvell,mv78460-pinctrl"; - reg = <0xd0018000 0x38>; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; }; - gpio0: gpio@d0018100 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; }; - gpio1: gpio@d0018140 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018140 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; + cpu@2 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <2>; + clocks = <&cpuclk 2>; }; - gpio2: gpio@d0018180 { - compatible = "marvell,orion-gpio"; - reg = <0xd0018180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupts-cells = <2>; - interrupts = <91>; + cpu@3 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <3>; + clocks = <&cpuclk 3>; }; + }; + + soc { + internal-regs { + pinctrl { + compatible = "marvell,mv78460-pinctrl"; + reg = <0x18000 0x38>; + + sdio_pins: sdio-pins { + marvell,pins = "mpp30", "mpp31", "mpp32", + "mpp33", "mpp34", "mpp35"; + marvell,function = "sd0"; + }; + }; - ethernet@d0034000 { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + }; + + gpio2: gpio@18180 { + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <91>; + }; + + ethernet@34000 { compatible = "marvell,armada-370-neta"; - reg = <0xd0034000 0x2500>; + reg = <0x34000 0x2500>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; + }; + + /* + * MV78460 has 4 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. Two units are + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; + }; + + pcie@7,0 { + device_type = "pci"; + assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 64>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + pcie@8,0 { + device_type = "pci"; + assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 65>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; + }; + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + pcie@10,0 { + device_type = "pci"; + assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + }; + }; }; }; - }; +}; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 3818a82176a2..f14d36c46159 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -23,121 +23,161 @@ memory { device_type = "memory"; - reg = <0x00000000 0xC0000000>; /* 3 GB */ + reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */ }; soc { - serial@d0012000 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@d0012100 { - clock-frequency = <250000000>; - status = "okay"; - }; - pinctrl { - led_pins: led-pins-0 { - marvell,pins = "mpp49", "mpp51", "mpp53"; - marvell,function = "gpio"; + internal-regs { + serial@12000 { + clock-frequency = <250000000>; + status = "okay"; }; - }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - red_led { - label = "red_led"; - gpios = <&gpio1 17 1>; - default-state = "off"; + serial@12100 { + clock-frequency = <250000000>; + status = "okay"; }; - - yellow_led { - label = "yellow_led"; - gpios = <&gpio1 19 1>; - default-state = "off"; + pinctrl { + led_pins: led-pins-0 { + marvell,pins = "mpp49", "mpp51", "mpp53"; + marvell,function = "gpio"; + }; }; - - green_led { - label = "green_led"; - gpios = <&gpio1 21 1>; - default-state = "off"; - linux,default-trigger = "heartbeat"; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + red_led { + label = "red_led"; + gpios = <&gpio1 17 1>; + default-state = "off"; + }; + + yellow_led { + label = "yellow_led"; + gpios = <&gpio1 19 1>; + default-state = "off"; + }; + + green_led { + label = "green_led"; + gpios = <&gpio1 21 1>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; }; - }; - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; - button@1 { - label = "Init Button"; - linux,code = <116>; - gpios = <&gpio1 28 0>; + button@1 { + label = "Init Button"; + linux,code = <116>; + gpios = <&gpio1 28 0>; + }; }; - }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; - phy1: ethernet-phy@1 { - reg = <1>; - }; + phy1: ethernet-phy@1 { + reg = <1>; + }; - phy2: ethernet-phy@2 { - reg = <2>; + phy2: ethernet-phy@2 { + reg = <2>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; }; - phy3: ethernet-phy@3 { - reg = <3>; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; + }; + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + }; + i2c@11100 { + status = "okay"; + clock-frequency = <400000>; + + s35390a: s35390a@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + usb@50000 { + status = "okay"; + }; + usb@51000 { + status = "okay"; }; - }; - ethernet@d0070000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - }; - ethernet@d0074000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - }; - ethernet@d0030000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - }; - ethernet@d0034000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; - }; - i2c@d0011000 { - status = "okay"; - clock-frequency = <400000>; - }; - i2c@d0011100 { - status = "okay"; - clock-frequency = <400000>; + devbus-bootcs@10400 { + status = "okay"; + ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 128 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x8000000>; + bank-width = <2>; + }; + }; - s35390a: s35390a@30 { - compatible = "s35390a"; - reg = <0x30>; + pcie-controller { + status = "okay"; + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; }; }; - sata@d00a0000 { - nr-ports = <2>; - status = "okay"; - }; - usb@d0050000 { - status = "okay"; - }; - usb@d0051000 { - status = "okay"; - }; }; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index ca00d8326c87..bacab11c10dc 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -22,134 +22,140 @@ model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; - L2: l2-cache { - compatible = "marvell,aurora-system-cache"; - reg = <0xd0008000 0x1000>; - cache-id-part = <0x100>; - wt-override; - }; + soc { + internal-regs { + L2: l2-cache { + compatible = "marvell,aurora-system-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; + wt-override; + }; - mpic: interrupt-controller@d0020000 { - reg = <0xd0020a00 0x2d0>, - <0xd0021070 0x58>; - }; + mpic: interrupt-controller@20000 { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + }; - armada-370-xp-pmsu@d0022000 { - compatible = "marvell,armada-370-xp-pmsu"; - reg = <0xd0022100 0x430>, - <0xd0020800 0x20>; - }; + armada-370-xp-pmsu@22000 { + compatible = "marvell,armada-370-xp-pmsu"; + reg = <0x22100 0x430>, <0x20800 0x20>; + }; - soc { - serial@d0012200 { + serial@12200 { compatible = "snps,dw-apb-uart"; - reg = <0xd0012200 0x100>; + reg = <0x12200 0x100>; reg-shift = <2>; interrupts = <43>; reg-io-width = <1>; status = "disabled"; - }; - serial@d0012300 { + }; + serial@12300 { compatible = "snps,dw-apb-uart"; - reg = <0xd0012300 0x100>; + reg = <0x12300 0x100>; reg-shift = <2>; interrupts = <44>; reg-io-width = <1>; status = "disabled"; - }; + }; - timer@d0020300 { + timer@20300 { marvell,timer-25Mhz; - }; + }; - coreclk: mvebu-sar@d0018230 { - compatible = "marvell,armada-xp-core-clock"; - reg = <0xd0018230 0x08>; - #clock-cells = <1>; - }; + coreclk: mvebu-sar@18230 { + compatible = "marvell,armada-xp-core-clock"; + reg = <0x18230 0x08>; + #clock-cells = <1>; + }; - cpuclk: clock-complex@d0018700 { - #clock-cells = <1>; - compatible = "marvell,armada-xp-cpu-clock"; - reg = <0xd0018700 0xA0>; - clocks = <&coreclk 1>; - }; + cpuclk: clock-complex@18700 { + #clock-cells = <1>; + compatible = "marvell,armada-xp-cpu-clock"; + reg = <0x18700 0xA0>; + clocks = <&coreclk 1>; + }; - gateclk: clock-gating-control@d0018220 { - compatible = "marvell,armada-xp-gating-clock"; - reg = <0xd0018220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-xp-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; - system-controller@d0018200 { + system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; - reg = <0xd0018200 0x500>; - }; + reg = <0x18200 0x500>; + }; - ethernet@d0030000 { + ethernet@30000 { compatible = "marvell,armada-370-neta"; - reg = <0xd0030000 0x2500>; + reg = <0x30000 0x2500>; interrupts = <12>; clocks = <&gateclk 2>; status = "disabled"; - }; - - xor@d0060900 { - compatible = "marvell,orion-xor"; - reg = <0xd0060900 0x100 - 0xd0060b00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor10 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; }; - }; - xor@d00f0900 { - compatible = "marvell,orion-xor"; - reg = <0xd00F0900 0x100 - 0xd00F0B00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor10 { + interrupts = <51>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <52>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; - xor00 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; + xor@f0900 { + compatible = "marvell,orion-xor"; + reg = <0xF0900 0x100 + 0xF0B00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor00 { + interrupts = <94>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <95>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; }; - xor01 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; + + usb@50000 { + clocks = <&gateclk 18>; }; - }; - usb@d0050000 { - clocks = <&gateclk 18>; - }; + usb@51000 { + clocks = <&gateclk 19>; + }; - usb@d0051000 { - clocks = <&gateclk 19>; - }; + usb@52000 { + compatible = "marvell,orion-ehci"; + reg = <0x52000 0x500>; + interrupts = <47>; + clocks = <&gateclk 20>; + status = "disabled"; + }; - usb@d0052000 { - compatible = "marvell,orion-ehci"; - reg = <0xd0052000 0x500>; - interrupts = <47>; - clocks = <&gateclk 20>; - status = "disabled"; + thermal@182b0 { + compatible = "marvell,armadaxp-thermal"; + reg = <0x182b0 0x4 + 0x184d0 0x4>; + status = "okay"; + }; }; - }; }; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index f7509cafc377..6cab46849cdb 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -50,6 +50,11 @@ #clock-cells = <1>; }; + thermal: thermal@d001c { + compatible = "marvell,dove-thermal"; + reg = <0xd001c 0x0c>, <0xd005c 0x08>; + }; + uart0: serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 192cf76fbf93..23991e45bc55 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -49,6 +49,12 @@ }; }; + thermal@10078 { + compatible = "marvell,kirkwood-thermal"; + reg = <0x10078 0x4>; + status = "okay"; + }; + i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11100 0x20>; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index bd83b8fc7c83..c3573be7b92c 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -77,6 +77,7 @@ }; nand@3000000 { + chip-delay = <40>; status = "okay"; partition@0 { diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 9555a86297c2..44fd97dfc1f3 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -69,6 +69,10 @@ status = "okay"; nr-ports = <1>; }; + + mvsdio@90000 { + status = "okay"; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 93c3afbef9ee..3694e94f6e99 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -96,11 +96,11 @@ marvell,function = "gpio"; }; pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { - marvell,pins = "mpp44"; + marvell,pins = "mpp46"; marvell,function = "gpio"; }; pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { - marvell,pins = "mpp45"; + marvell,pins = "mpp47"; marvell,function = "gpio"; }; @@ -157,14 +157,14 @@ gpios = <&gpio0 16 0>; linux,default-trigger = "default-on"; }; - health_led1 { + rebuild_led { + label = "status:white:rebuild_led"; + gpios = <&gpio1 4 0>; + }; + health_led { label = "status:red:health_led"; gpios = <&gpio1 5 0>; }; - health_led2 { - label = "status:white:health_led"; - gpios = <&gpio1 4 0>; - }; backup_led { label = "status:blue:backup_led"; gpios = <&gpio0 15 0>; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 8aad00f81ed9..892c64e3f1e1 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -13,6 +13,9 @@ compatible = "marvell,orion5x"; interrupt-parent = <&intc>; + aliases { + gpio0 = &gpio0; + }; intc: interrupt-controller { compatible = "marvell,orion-intc", "marvell,intc"; interrupt-controller; @@ -32,7 +35,9 @@ #gpio-cells = <2>; gpio-controller; reg = <0x10100 0x40>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; interrupts = <6>, <7>, <8>, <9>; }; @@ -69,6 +74,20 @@ status = "okay"; }; + ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <17>; + status = "disabled"; + }; + + ehci@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0xa0000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; + sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; @@ -86,12 +105,31 @@ status = "disabled"; }; + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + status = "okay"; + + xor00 { + interrupts = <30>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <31>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + crypto@90000 { compatible = "marvell,orion-crypto"; reg = <0x90000 0x10000>, <0xf2200000 0x800>; reg-names = "regs", "sram"; - interrupts = <22>; + interrupts = <28>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi new file mode 100644 index 000000000000..15994158a998 --- /dev/null +++ b/arch/arm/boot/dts/skeleton64.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree in the 64 bits version; the bare minimum + * needed to boot; just include and add a compatible value. The + * bootloader will typically populate the memory node. + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0>; }; +}; diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 3fe8dae8d32d..4364eff5b01e 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -75,6 +75,8 @@ CONFIG_I2C_MV64XXX=y CONFIG_SPI=y CONFIG_SPI_ORION=y # CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_DOVE_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 13482ea58b09..8f0065bb6f39 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -119,6 +119,8 @@ CONFIG_SPI=y CONFIG_SPI_ORION=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_KIRKWOOD_THERMAL=y CONFIG_WATCHDOG=y CONFIG_ORION_WATCHDOG=y CONFIG_HID_DRAGONRISE=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 2ec8119cff73..f3e8ae001ff1 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -46,9 +46,16 @@ CONFIG_I2C_MV64XXX=y CONFIG_MTD=y CONFIG_MTD_CHAR=y CONFIG_MTD_M25P80=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y CONFIG_SERIAL_8250_DW=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y +CONFIG_THERMAL=y +CONFIG_ARMADA_THERMAL=y CONFIG_USB_SUPPORT=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -65,6 +72,8 @@ CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_MV=y CONFIG_DMADEVICES=y CONFIG_MV_XOR=y +CONFIG_MEMORY=y +CONFIG_MVEBU_DEVBUS=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S index 865c6d02b332..df191afa3be1 100644 --- a/arch/arm/include/debug/mvebu.S +++ b/arch/arm/include/debug/mvebu.S @@ -12,7 +12,7 @@ */ #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 -#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000 +#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000 .macro addruart, rp, rv, tmp ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index 3f0a858fb597..4d9d2ffc4535 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o irq.o +obj-y += common.o irq.o obj-$(CONFIG_DOVE_LEGACY) += mpp.o obj-$(CONFIG_PCI) += pcie.o obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c deleted file mode 100644 index 2a06c0163418..000000000000 --- a/arch/arm/mach-dove/addr-map.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * arch/arm/mach-dove/addr-map.c - * - * Address map functions for Marvell Dove 88AP510 SoC - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <asm/mach/arch.h> -#include <asm/setup.h> -#include <mach/dove.h> -#include <plat/addr-map.h> -#include "common.h" - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DDR 0x0 -#define TARGET_BOOTROM 0x1 -#define TARGET_CESA 0x3 -#define TARGET_PCIE0 0x4 -#define TARGET_PCIE1 0x8 -#define TARGET_SCRATCHPAD 0xd - -#define ATTR_CESA 0x01 -#define ATTR_BOOTROM 0xfd -#define ATTR_DEV_SPI0_ROM 0xfe -#define ATTR_DEV_SPI1_ROM 0xfb -#define ATTR_PCIE_IO 0xe0 -#define ATTR_PCIE_MEM 0xe8 -#define ATTR_SCRATCHPAD 0x0 - -static inline void __iomem *ddr_map_sc(int i) -{ - return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); -} - -/* - * Description of the windows needed by the platform code - */ -static struct __initdata orion_addr_map_cfg addr_map_cfg = { - .num_wins = 8, - .remappable_wins = 4, - .bridge_virt_base = BRIDGE_VIRT_BASE, -}; - -static const struct __initdata orion_addr_map_info addr_map_info[] = { - /* - * Windows for PCIe IO+MEM space. - */ - { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, - TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE - }, - { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, - TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE - }, - { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, - TARGET_PCIE0, ATTR_PCIE_MEM, -1 - }, - { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, - TARGET_PCIE1, ATTR_PCIE_MEM, -1 - }, - /* - * Window for CESA engine. - */ - { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, - TARGET_CESA, ATTR_CESA, -1 - }, - /* - * Window to the BootROM for Standby and Sleep Resume - */ - { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, - TARGET_BOOTROM, ATTR_BOOTROM, -1 - }, - /* - * Window to the PMU Scratch Pad space - */ - { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, - TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1 - }, - /* End marker */ - { -1, 0, 0, 0, 0, 0 } -}; - -void __init dove_setup_cpu_mbus(void) -{ - int i; - int cs; - - /* - * Disable, clear and configure windows. - */ - orion_config_wins(&addr_map_cfg, addr_map_info); - - /* - * Setup MBUS dram target info. - */ - orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - for (i = 0, cs = 0; i < 2; i++) { - u32 map = readl(ddr_map_sc(i)); - - /* - * Chip select enabled? - */ - if (map & 1) { - struct mbus_dram_window *w; - - w = &orion_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0; /* CS address decoding done inside */ - /* the DDR controller, no need to */ - /* provide attributes */ - w->base = map & 0xff800000; - w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); - } - } - orion_mbus_dram_info.num_cs = cs; -} diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c index fbde1dd67113..0b142803b2e1 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-dove/board-dt.c @@ -64,7 +64,7 @@ static void __init dove_dt_init(void) #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(0); #endif - dove_setup_cpu_mbus(); + dove_setup_cpu_wins(); /* Setup root of clk tree */ dove_of_clk_init(); diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index c6b3b2bb50e7..e2b5da031f96 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -224,6 +224,9 @@ void __init dove_i2c_init(void) void __init dove_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); + mvebu_mbus_init("marvell,dove-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); } static int __init dove_find_tclk(void) @@ -326,6 +329,40 @@ void __init dove_sdio1_init(void) platform_device_register(&dove_sdio1); } +void __init dove_setup_cpu_wins(void) +{ + /* + * The PCIe windows will no longer be statically allocated + * here once Dove is migrated to the pci-mvebu driver. + */ + mvebu_mbus_add_window_remap_flags("pcie0.0", + DOVE_PCIE0_IO_PHYS_BASE, + DOVE_PCIE0_IO_SIZE, + DOVE_PCIE0_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie1.0", + DOVE_PCIE1_IO_PHYS_BASE, + DOVE_PCIE1_IO_SIZE, + DOVE_PCIE1_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie0.0", + DOVE_PCIE0_MEM_PHYS_BASE, + DOVE_PCIE0_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window_remap_flags("pcie1.0", + DOVE_PCIE1_MEM_PHYS_BASE, + DOVE_PCIE1_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE, + DOVE_CESA_SIZE); + mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE, + DOVE_BOOTROM_SIZE); + mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE, + DOVE_SCRATCHPAD_SIZE); +} + void __init dove_init(void) { pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", @@ -334,7 +371,7 @@ void __init dove_init(void) #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(0); #endif - dove_setup_cpu_mbus(); + dove_setup_cpu_wins(); /* Setup root of clk tree */ dove_clk_init(); diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h index ee59fba4c6d1..e86347928b67 100644 --- a/arch/arm/mach-dove/common.h +++ b/arch/arm/mach-dove/common.h @@ -23,7 +23,7 @@ void dove_map_io(void); void dove_init(void); void dove_init_early(void); void dove_init_irq(void); -void dove_setup_cpu_mbus(void); +void dove_setup_cpu_wins(void); void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); void dove_sata_init(struct mv_sata_platform_data *sata_data); #ifdef CONFIG_PCI diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index 661725e3115a..0c4b35f4ee5b 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -77,6 +77,8 @@ /* North-South Bridge */ #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) #define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) +#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) +#define BRIDGE_WINS_SZ (0x80) /* Cryptographic Engine */ #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) @@ -168,6 +170,9 @@ #define DOVE_SSP_CLOCK_ENABLE (1 << 1) #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) /* Memory Controller */ +#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000) +#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100) +#define DOVE_MC_WINS_SZ (0x8) #define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) /* LCD Controller */ diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 4cc4bee4d0cf..d805f8078fa3 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o irq.o pcie.o mpp.o +obj-y += common.o irq.o pcie.o mpp.o obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c deleted file mode 100644 index 8f0d162a1e1d..000000000000 --- a/arch/arm/mach-kirkwood/addr-map.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * arch/arm/mach-kirkwood/addr-map.c - * - * Address map functions for Marvell Kirkwood SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <plat/addr-map.h> -#include "common.h" - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DEV_BUS 1 -#define TARGET_SRAM 3 -#define TARGET_PCIE 4 -#define ATTR_DEV_SPI_ROM 0x1e -#define ATTR_DEV_BOOT 0x1d -#define ATTR_DEV_NAND 0x2f -#define ATTR_DEV_CS3 0x37 -#define ATTR_DEV_CS2 0x3b -#define ATTR_DEV_CS1 0x3d -#define ATTR_DEV_CS0 0x3e -#define ATTR_PCIE_IO 0xe0 -#define ATTR_PCIE_MEM 0xe8 -#define ATTR_PCIE1_IO 0xd0 -#define ATTR_PCIE1_MEM 0xd8 -#define ATTR_SRAM 0x01 - -/* - * Description of the windows needed by the platform code - */ -static struct __initdata orion_addr_map_cfg addr_map_cfg = { - .num_wins = 8, - .remappable_wins = 4, - .bridge_virt_base = BRIDGE_VIRT_BASE, -}; - -static const struct __initdata orion_addr_map_info addr_map_info[] = { - /* - * Windows for PCIe IO+MEM space. - */ - { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE - }, - { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE - }, - { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, - TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE - }, - { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE - }, - /* - * Window for NAND controller. - */ - { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, - TARGET_DEV_BUS, ATTR_DEV_NAND, -1 - }, - /* - * Window for SRAM. - */ - { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, - TARGET_SRAM, ATTR_SRAM, -1 - }, - /* End marker */ - { -1, 0, 0, 0, 0, 0 } -}; - -void __init kirkwood_setup_cpu_mbus(void) -{ - /* - * Disable, clear and configure windows. - */ - orion_config_wins(&addr_map_cfg, addr_map_info); - - /* - * Setup MBUS dram target info. - */ - orion_setup_cpu_mbus_target(&addr_map_cfg, - (void __iomem *) DDR_WINDOW_CPU_BASE); -} diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index d367aa6b47bb..f5437c27dc2a 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -93,7 +93,7 @@ static void __init kirkwood_dt_init(void) */ writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); - kirkwood_setup_cpu_mbus(); + kirkwood_setup_wins(); kirkwood_l2_init(); diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c index 0a0df4554d8b..a857163954a5 100644 --- a/arch/arm/mach-kirkwood/board-guruplug.c +++ b/arch/arm/mach-kirkwood/board-guruplug.c @@ -13,7 +13,6 @@ #include <linux/init.h> #include <linux/mv643xx_eth.h> #include <linux/gpio.h> -#include <linux/platform_data/mmc-mvsdio.h> #include "common.h" static struct mv643xx_eth_platform_data guruplug_ge00_data = { @@ -24,10 +23,6 @@ static struct mv643xx_eth_platform_data guruplug_ge01_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(1), }; -static struct mvsdio_platform_data guruplug_mvsdio_data = { - /* unfortunately the CD signal has not been connected */ -}; - void __init guruplug_dt_init(void) { /* @@ -35,5 +30,4 @@ void __init guruplug_dt_init(void) */ kirkwood_ge00_init(&guruplug_ge00_data); kirkwood_ge01_init(&guruplug_ge01_data); - kirkwood_sdio_init(&guruplug_mvsdio_data); } diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c index f655b2637b0e..e5f70415905a 100644 --- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c @@ -20,10 +20,15 @@ static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = { .duplex = DUPLEX_FULL, }; +static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(11), +}; + void __init iomega_ix2_200_init(void) { /* * Basic setup. Needs to be called early. */ - kirkwood_ge01_init(&iomega_ix2_200_ge00_data); + kirkwood_ge00_init(&iomega_ix2_200_ge00_data); + kirkwood_ge01_init(&iomega_ix2_200_ge01_data); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 49792a0cd2d3..c2cae69e6d2b 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -33,7 +33,6 @@ #include <linux/platform_data/usb-ehci-orion.h> #include <plat/common.h> #include <plat/time.h> -#include <plat/addr-map.h> #include <linux/platform_data/dma-mv_xor.h> #include "common.h" @@ -535,6 +534,9 @@ void __init kirkwood_init_early(void) * the allocations won't fail. */ init_dma_coherent_pool_size(SZ_1M); + mvebu_mbus_init("marvell,kirkwood-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); } int kirkwood_tclk; @@ -650,6 +652,38 @@ char * __init kirkwood_id(void) } } +void __init kirkwood_setup_wins(void) +{ + /* + * The PCIe windows will no longer be statically allocated + * here once Kirkwood is migrated to the pci-mvebu driver. + */ + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_IO_PHYS_BASE, + KIRKWOOD_PCIE_IO_SIZE, + KIRKWOOD_PCIE_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_MEM_PHYS_BASE, + KIRKWOOD_PCIE_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_IO_PHYS_BASE, + KIRKWOOD_PCIE1_IO_SIZE, + KIRKWOOD_PCIE1_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_MEM_PHYS_BASE, + KIRKWOOD_PCIE1_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, + KIRKWOOD_NAND_MEM_SIZE); + mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, + KIRKWOOD_SRAM_SIZE); +} + void __init kirkwood_l2_init(void) { #ifdef CONFIG_CACHE_FEROCEON_L2 @@ -675,7 +709,7 @@ void __init kirkwood_init(void) */ writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); - kirkwood_setup_cpu_mbus(); + kirkwood_setup_wins(); kirkwood_l2_init(); diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 5ed70565c843..e24f74305b34 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -30,7 +30,7 @@ void kirkwood_init(void); void kirkwood_init_early(void); void kirkwood_init_irq(void); -void kirkwood_setup_cpu_mbus(void); +void kirkwood_setup_wins(void); void kirkwood_enable_pcie(void); void kirkwood_pcie_id(u32 *dev, u32 *rev); diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c index 1c6e736cbbf8..08dd739aa709 100644 --- a/arch/arm/mach-kirkwood/guruplug-setup.c +++ b/arch/arm/mach-kirkwood/guruplug-setup.c @@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = { static struct mvsdio_platform_data guruplug_mvsdio_data = { /* unfortunately the CD signal has not been connected */ + .gpio_card_detect = -1, + .gpio_write_protect = -1, }; static struct gpio_led guruplug_led_pins[] = { diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index a05563a31c95..92976cef3910 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -60,8 +60,9 @@ * Register Map */ #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) -#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) -#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500) +#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) +#define DDR_WINDOW_CPU_BASE (DDR_PHYS_BASE + 0x1500) +#define DDR_WINDOW_CPU_SZ (0x20) #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) @@ -80,6 +81,8 @@ #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) +#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) +#define BRIDGE_WINS_SZ (0x80) #define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c index 8ddd69fdc937..6a6eb548307d 100644 --- a/arch/arm/mach-kirkwood/openrd-setup.c +++ b/arch/arm/mach-kirkwood/openrd-setup.c @@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = { static struct mvsdio_platform_data openrd_mvsdio_data = { .gpio_card_detect = 29, /* MPP29 used as SD card detect */ + .gpio_write_protect = -1, }; static unsigned int openrd_mpp_config[] __initdata = { diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index d96ad4c09972..7f43e6c2f8c0 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -17,7 +17,6 @@ #include <asm/mach/pci.h> #include <plat/pcie.h> #include <mach/bridge-regs.h> -#include <plat/addr-map.h> #include "common.h" static void kirkwood_enable_pcie_clk(const char *port) diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index c7d93b48926b..d24223166e06 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = { static struct mvsdio_platform_data rd88f6281_mvsdio_data = { .gpio_card_detect = 28, + .gpio_write_protect = -1, }; static unsigned int rd88f6281_mpp_config[] __initdata = { diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index 67a13f9bfe64..7cd04634d302 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o mpp.o irq.o pcie.o +obj-y += common.o mpp.o irq.o pcie.o obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c deleted file mode 100644 index 26e9876b50e9..000000000000 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/addr-map.c - * - * Address map functions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <plat/addr-map.h> -#include <mach/mv78xx0.h> -#include "common.h" - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DEV_BUS 1 -#define TARGET_PCIE0 4 -#define TARGET_PCIE1 8 -#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0) -#define ATTR_DEV_SPI_ROM 0x1f -#define ATTR_DEV_BOOT 0x2f -#define ATTR_DEV_CS3 0x37 -#define ATTR_DEV_CS2 0x3b -#define ATTR_DEV_CS1 0x3d -#define ATTR_DEV_CS0 0x3e -#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l))) -#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) - -/* - * CPU Address Decode Windows registers - */ -#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) -#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) - -static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) -{ - /* - * Find the control register base address for this window. - * - * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's) - * MBUS bridge depending on which CPU core we're running on, - * so we don't need to take that into account here. - */ - - return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win); -} - -/* - * Description of the windows needed by the platform code - */ -static struct orion_addr_map_cfg addr_map_cfg __initdata = { - .num_wins = 14, - .remappable_wins = 8, - .win_cfg_base = win_cfg_base, -}; - -void __init mv78xx0_setup_cpu_mbus(void) -{ - /* - * Disable, clear and configure windows. - */ - orion_config_wins(&addr_map_cfg, NULL); - - /* - * Setup MBUS dram target info. - */ - if (mv78xx0_core_index() == 0) - orion_setup_cpu_mbus_target(&addr_map_cfg, - (void __iomem *) DDR_WINDOW_CPU0_BASE); - else - orion_setup_cpu_mbus_target(&addr_map_cfg, - (void __iomem *) DDR_WINDOW_CPU1_BASE); -} - -void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, - int maj, int min) -{ - orion_setup_cpu_win(&addr_map_cfg, window, base, size, - TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0); -} - -void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, - int maj, int min) -{ - orion_setup_cpu_win(&addr_map_cfg, window, base, size, - TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1); -} diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 0efa14498ebc..749a7f8c4992 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -334,6 +334,14 @@ void __init mv78xx0_uart3_init(void) void __init mv78xx0_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); + if (mv78xx0_core_index() == 0) + mvebu_mbus_init("marvell,mv78xx0-mbus", + BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ); + else + mvebu_mbus_init("marvell,mv78xx0-mbus", + BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ); } void __init_refok mv78xx0_timer_init(void) @@ -397,8 +405,6 @@ void __init mv78xx0_init(void) printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); - mv78xx0_setup_cpu_mbus(); - #ifdef CONFIG_CACHE_FEROCEON_L2 feroceon_l2_init(is_l2_writethrough()); #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index 46200a183cf2..723748d8ba7d 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -60,13 +60,18 @@ */ #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) #define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) +#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE) +#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE) +#define BRIDGE_WINS_SZ (0xA000) /* * Register Map */ #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) -#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570) +#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000) +#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500) +#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570) +#define DDR_WINDOW_CPU_SZ (0x20) #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index ee8c0b51df2c..dc26a654c496 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -10,11 +10,11 @@ #include <linux/kernel.h> #include <linux/pci.h> +#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> -#include <plat/addr-map.h> #include <mach/mv78xx0.h> #include "common.h" @@ -54,7 +54,6 @@ static void __init mv78xx0_pcie_preinit(void) int i; u32 size_each; u32 start; - int win = 0; pcie_io_space.name = "PCIe I/O Space"; pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); @@ -72,6 +71,7 @@ static void __init mv78xx0_pcie_preinit(void) start = MV78XX0_PCIE_MEM_PHYS_BASE; for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; + char winname[MVEBU_MBUS_MAX_WINNAME_SZ]; snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d.%d MEM", pp->maj, pp->min); @@ -85,12 +85,17 @@ static void __init mv78xx0_pcie_preinit(void) if (request_resource(&iomem_resource, &pp->res)) panic("can't allocate PCIe MEM sub-space"); - mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start, - resource_size(&pp->res), - pp->maj, pp->min); - - mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K, - pp->maj, pp->min); + snprintf(winname, sizeof(winname), "pcie%d.%d", + pp->maj, pp->min); + + mvebu_mbus_add_window_remap_flags(winname, + pp->res.start, + resource_size(&pp->res), + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window_remap_flags(winname, + i * SZ_64K, SZ_64K, + 0, MVEBU_MBUS_PCI_IO); } } diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 440b13ef1fed..e11acbb0a46d 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -13,6 +13,8 @@ config ARCH_MVEBU select MVEBU_CLK_CORE select MVEBU_CLK_CPU select MVEBU_CLK_GATING + select MVEBU_MBUS + select ZONE_DMA if ARM_LPAE if ARCH_MVEBU diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index da93bcbc74c1..ba769e082ad4 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -5,6 +5,6 @@ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a obj-y += system-controller.o obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o -obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o +obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c deleted file mode 100644 index ab9b3bd4fef5..000000000000 --- a/arch/arm/mach-mvebu/addr-map.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Address map functions for Marvell 370 / XP SoCs - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <plat/addr-map.h> - -/* - * Generic Address Decode Windows bit settings - */ -#define ARMADA_XP_TARGET_DEV_BUS 1 -#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D -#define ARMADA_XP_TARGET_ETH1 3 -#define ARMADA_XP_TARGET_PCIE_0_2 4 -#define ARMADA_XP_TARGET_ETH0 7 -#define ARMADA_XP_TARGET_PCIE_1_3 8 - -#define ARMADA_370_TARGET_DEV_BUS 1 -#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D -#define ARMADA_370_TARGET_PCIE_0 4 -#define ARMADA_370_TARGET_PCIE_1 8 - -#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90 -#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180 - -static const struct __initdata orion_addr_map_info -armada_xp_addr_map_info[] = { - /* - * Window for the BootROM, needed for SMP on Armada XP - */ - { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS, - ARMADA_XP_ATTR_DEV_BOOTROM, -1 }, - /* End marker */ - { -1, 0, 0, 0, 0, 0 }, -}; - -static const struct __initdata orion_addr_map_info -armada_370_addr_map_info[] = { - /* End marker */ - { -1, 0, 0, 0, 0, 0 }, -}; - -static struct of_device_id of_addr_decoding_controller_table[] = { - { .compatible = "marvell,armada-addr-decoding-controller" }, - { /* end of list */ }, -}; - -static void __iomem * -armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win) -{ - unsigned int offset; - - /* The register layout is a bit annoying and the below code - * tries to cope with it. - * - At offset 0x0, there are the registers for the first 8 - * windows, with 4 registers of 32 bits per window (ctrl, - * base, remap low, remap high) - * - Then at offset 0x80, there is a hole of 0x10 bytes for - * the internal registers base address and internal units - * sync barrier register. - * - Then at offset 0x90, there the registers for 12 - * windows, with only 2 registers of 32 bits per window - * (ctrl, base). - */ - if (win < 8) - offset = (win << 4); - else - offset = ARMADA_WINDOW_8_PLUS_OFFSET + ((win - 8) << 3); - - return cfg->bridge_virt_base + offset; -} - -static struct __initdata orion_addr_map_cfg addr_map_cfg = { - .num_wins = 20, - .remappable_wins = 8, - .win_cfg_base = armada_cfg_base, -}; - -static int __init armada_setup_cpu_mbus(void) -{ - struct device_node *np; - void __iomem *mbus_unit_addr_decoding_base; - void __iomem *sdram_addr_decoding_base; - - np = of_find_matching_node(NULL, of_addr_decoding_controller_table); - if (!np) - return -ENODEV; - - mbus_unit_addr_decoding_base = of_iomap(np, 0); - BUG_ON(!mbus_unit_addr_decoding_base); - - sdram_addr_decoding_base = - mbus_unit_addr_decoding_base + - ARMADA_SDRAM_ADDR_DECODING_OFFSET; - - addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base; - - if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric")) - addr_map_cfg.hw_io_coherency = 1; - - /* - * Disable, clear and configure windows. - */ - if (of_machine_is_compatible("marvell,armadaxp")) - orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info); - else if (of_machine_is_compatible("marvell,armada370")) - orion_config_wins(&addr_map_cfg, armada_370_addr_map_info); - else { - pr_err("Unsupported SoC\n"); - return -EINVAL; - } - - /* - * Setup MBUS dram target info. - */ - orion_setup_cpu_mbus_target(&addr_map_cfg, - sdram_addr_decoding_base); - return 0; -} - -/* Using a early_initcall is needed so that this initialization gets - * done before the SMP initialization, which requires the BootROM to - * be remapped. */ -early_initcall(armada_setup_cpu_mbus); diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index a5ea616d6d12..12d3655830d1 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -19,6 +19,7 @@ #include <linux/time-armada-370-xp.h> #include <linux/clk/mvebu.h> #include <linux/dma-mapping.h> +#include <linux/mbus.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -48,12 +49,29 @@ void __init armada_370_xp_timer_and_clk_init(void) void __init armada_370_xp_init_early(void) { + char *mbus_soc_name; + /* * Some Armada 370/XP devices allocate their coherent buffers * from atomic context. Increase size of atomic coherent pool * to make sure such the allocations won't fail. */ init_dma_coherent_pool_size(SZ_1M); + + /* + * This initialization will be replaced by a DT-based + * initialization once the mvebu-mbus driver gains DT support. + */ + if (of_machine_is_compatible("marvell,armada370")) + mbus_soc_name = "marvell,armada370-mbus"; + else + mbus_soc_name = "marvell,armadaxp-mbus"; + + mvebu_mbus_init(mbus_soc_name, + ARMADA_370_XP_MBUS_WINS_BASE, + ARMADA_370_XP_MBUS_WINS_SIZE, + ARMADA_370_XP_SDRAM_WINS_BASE, + ARMADA_370_XP_SDRAM_WINS_SIZE); } static void __init armada_370_xp_dt_init(void) diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h index c6a7d74fddfe..2070e1b4f342 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.h +++ b/arch/arm/mach-mvebu/armada-370-xp.h @@ -16,9 +16,15 @@ #define __MACH_ARMADA_370_XP_H #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 -#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000) +#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfec00000) #define ARMADA_370_XP_REGS_SIZE SZ_1M +/* These defines can go away once mvebu-mbus has a DT binding */ +#define ARMADA_370_XP_MBUS_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000) +#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100 +#define ARMADA_370_XP_SDRAM_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180) +#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20 + #ifdef CONFIG_SMP #include <linux/cpumask.h> diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c index 274ff58271de..d5970f5a1e8d 100644 --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -44,6 +44,8 @@ #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) +#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5) + #define ACTIVE_DOORBELLS (8) static DEFINE_RAW_SPINLOCK(irq_controller_lock); @@ -59,36 +61,26 @@ static struct irq_domain *armada_370_xp_mpic_domain; */ static void armada_370_xp_irq_mask(struct irq_data *d) { -#ifdef CONFIG_SMP irq_hw_number_t hwirq = irqd_to_hwirq(d); - if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) + if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); else writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); -#else - writel(irqd_to_hwirq(d), - per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); -#endif } static void armada_370_xp_irq_unmask(struct irq_data *d) { -#ifdef CONFIG_SMP irq_hw_number_t hwirq = irqd_to_hwirq(d); - if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) + if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); else writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); -#else - writel(irqd_to_hwirq(d), - per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); -#endif } #ifdef CONFIG_SMP @@ -144,10 +136,14 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { armada_370_xp_irq_mask(irq_get_irq_data(virq)); - writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); + if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) + writel(hw, per_cpu_int_base + + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); + else + writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); irq_set_status_flags(virq, IRQ_LEVEL); - if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { + if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) { irq_set_percpu_devid(virq); irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, handle_percpu_devid_irq); diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index fe16aaf7c19c..875ea748391c 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -21,6 +21,7 @@ #include <linux/smp.h> #include <linux/clk.h> #include <linux/of.h> +#include <linux/mbus.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> #include "common.h" @@ -109,6 +110,7 @@ void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) set_secondary_cpus_clock(); flush_cache_all(); set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); + mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M); } struct smp_operations armada_xp_smp_ops __initdata = { diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 9e809a7c05c0..45da805fb236 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o pci.o irq.o mpp.o +obj-y += common.o pci.o irq.o mpp.o obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c deleted file mode 100644 index b5efc0fd31cb..000000000000 --- a/arch/arm/mach-orion5x/addr-map.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * arch/arm/mach-orion5x/addr-map.c - * - * Address map functions for Marvell Orion 5x SoCs - * - * Maintainer: Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <plat/addr-map.h> -#include "common.h" - -/* - * The Orion has fully programmable address map. There's a separate address - * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB, - * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own - * address decode windows that allow it to access any of the Orion resources. - * - * CPU address decoding -- - * Linux assumes that it is the boot loader that already setup the access to - * DDR and internal registers. - * Setup access to PCI and PCIe IO/MEM space is issued by this file. - * Setup access to various devices located on the device bus interface (e.g. - * flashes, RTC, etc) should be issued by machine-setup.c according to - * specific board population (by using orion5x_setup_*_win()). - * - * Non-CPU Masters address decoding -- - * Unlike the CPU, we setup the access from Orion's master interfaces to DDR - * banks only (the typical use case). - * Setup access for each master to DDR is issued by platform device setup. - */ - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DEV_BUS 1 -#define TARGET_PCI 3 -#define TARGET_PCIE 4 -#define TARGET_SRAM 9 -#define ATTR_PCIE_MEM 0x59 -#define ATTR_PCIE_IO 0x51 -#define ATTR_PCIE_WA 0x79 -#define ATTR_PCI_MEM 0x59 -#define ATTR_PCI_IO 0x51 -#define ATTR_DEV_CS0 0x1e -#define ATTR_DEV_CS1 0x1d -#define ATTR_DEV_CS2 0x1b -#define ATTR_DEV_BOOT 0xf -#define ATTR_SRAM 0x0 - -static int __initdata win_alloc_count; - -static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, - const int win) -{ - u32 dev, rev; - - orion5x_pcie_id(&dev, &rev); - if ((dev == MV88F5281_DEV_ID && win < 4) - || (dev == MV88F5182_DEV_ID && win < 2) - || (dev == MV88F5181_DEV_ID && win < 2) - || (dev == MV88F6183_DEV_ID && win < 4)) - return 1; - - return 0; -} - -/* - * Description of the windows needed by the platform code - */ -static struct orion_addr_map_cfg addr_map_cfg __initdata = { - .num_wins = 8, - .cpu_win_can_remap = cpu_win_can_remap, - .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, -}; - -static const struct __initdata orion_addr_map_info addr_map_info[] = { - /* - * Setup windows for PCI+PCIe IO+MEM space. - */ - { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE - }, - { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, - TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE - }, - { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, -1 - }, - { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, - TARGET_PCI, ATTR_PCI_MEM, -1 - }, - /* End marker */ - { -1, 0, 0, 0, 0, 0 } -}; - -void __init orion5x_setup_cpu_mbus_bridge(void) -{ - /* - * Disable, clear and configure windows. - */ - orion_config_wins(&addr_map_cfg, addr_map_info); - win_alloc_count = 4; - - /* - * Setup MBUS dram target info. - */ - orion_setup_cpu_mbus_target(&addr_map_cfg, - (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE); -} - -void __init orion5x_setup_dev_boot_win(u32 base, u32 size) -{ - orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); -} - -void __init orion5x_setup_dev0_win(u32 base, u32 size) -{ - orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS0, -1); -} - -void __init orion5x_setup_dev1_win(u32 base, u32 size) -{ - orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS1, -1); -} - -void __init orion5x_setup_dev2_win(u32 base, u32 size) -{ - orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS2, -1); -} - -void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) -{ - orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, - TARGET_PCIE, ATTR_PCIE_WA, -1); -} - -void __init orion5x_setup_sram_win(void) -{ - orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, - ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE, - TARGET_SRAM, ATTR_SRAM, -1); -} diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 35a8014529ca..6bbc8786c1e3 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -41,7 +41,7 @@ static void __init orion5x_dt_init(void) /* * Setup Orion address map */ - orion5x_setup_cpu_mbus_bridge(); + orion5x_setup_wins(); /* Setup root of clk tree */ clk_init(); diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index d068f1431c40..8e468e3a6015 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -34,7 +34,6 @@ #include <linux/platform_data/usb-ehci-orion.h> #include <plat/time.h> #include <plat/common.h> -#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -174,7 +173,8 @@ void __init orion5x_xor_init(void) ****************************************************************************/ static void __init orion5x_crypto_init(void) { - orion5x_setup_sram_win(); + mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE, + ORION5X_SRAM_SIZE); orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, SZ_8K, IRQ_ORION5X_CESA); } @@ -193,6 +193,9 @@ void __init orion5x_wdt_init(void) ****************************************************************************/ void __init orion5x_init_early(void) { + u32 rev, dev; + const char *mbus_soc_name; + orion_time_set_base(TIMER_VIRT_BASE); /* @@ -201,6 +204,46 @@ void __init orion5x_init_early(void) * the allocations won't fail. */ init_dma_coherent_pool_size(SZ_1M); + + /* Initialize the MBUS driver */ + orion5x_pcie_id(&dev, &rev); + if (dev == MV88F5281_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f5281-mbus"; + else if (dev == MV88F5182_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f5182-mbus"; + else if (dev == MV88F5181_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f5181-mbus"; + else if (dev == MV88F6183_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f6183-mbus"; + else + mbus_soc_name = NULL; + mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE, + ORION5X_BRIDGE_WINS_SZ, + ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ); +} + +void orion5x_setup_wins(void) +{ + /* + * The PCIe windows will no longer be statically allocated + * here once Orion5x is migrated to the pci-mvebu driver. + */ + mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE, + ORION5X_PCIE_IO_SIZE, + ORION5X_PCIE_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE, + ORION5X_PCIE_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE, + ORION5X_PCI_IO_SIZE, + ORION5X_PCI_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE, + ORION5X_PCI_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); } int orion5x_tclk; @@ -282,7 +325,7 @@ void __init orion5x_init(void) /* * Setup Orion address map */ - orion5x_setup_cpu_mbus_bridge(); + orion5x_setup_wins(); /* Setup root of clk tree */ clk_init(); diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index e60345760283..cdaa01f3d186 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -17,18 +17,7 @@ void clk_init(void); extern int orion5x_tclk; extern void orion5x_timer_init(void); -/* - * Enumerations and functions for Orion windows mapping. Used by Orion core - * functions to map its interfaces and by the machine-setup to map its on- - * board devices. Details in /mach-orion/addr-map.c - */ -void orion5x_setup_cpu_mbus_bridge(void); -void orion5x_setup_dev_boot_win(u32 base, u32 size); -void orion5x_setup_dev0_win(u32 base, u32 size); -void orion5x_setup_dev1_win(u32 base, u32 size); -void orion5x_setup_dev2_win(u32 base, u32 size); -void orion5x_setup_pcie_wa_win(u32 base, u32 size); -void orion5x_setup_sram_win(void); +void orion5x_setup_wins(void); void orion5x_ehci0_init(void); void orion5x_ehci1_init(void); diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index 57d0af74874d..16c88bbabc98 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c @@ -317,8 +317,8 @@ static void __init d2net_init(void) d2net_sata_power_init(); orion5x_sata_init(&d2net_sata_data); - orion5x_setup_dev_boot_win(D2NET_NOR_BOOT_BASE, - D2NET_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE, + D2NET_NOR_BOOT_SIZE); platform_device_register(&d2net_nor_flash); platform_device_register(&d2net_gpio_buttons); diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 76665640087b..4e1263da38bb 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -340,16 +340,19 @@ static void __init db88f5281_init(void) orion5x_uart0_init(); orion5x_uart1_init(); - orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE, + DB88F5281_NOR_BOOT_SIZE); platform_device_register(&db88f5281_boot_flash); - orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); + mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE, + DB88F5281_7SEG_SIZE); - orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); + mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE, + DB88F5281_NOR_SIZE); platform_device_register(&db88f5281_nor_flash); - orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); + mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE, + DB88F5281_NAND_SIZE); platform_device_register(&db88f5281_nand_flash); i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 6eb1732757fd..9e6baf581ed3 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -611,7 +611,8 @@ static void __init dns323_init(void) /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 */ - orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE, + DNS323_NOR_BOOT_SIZE); platform_device_register(&dns323_nor_flash); /* Sort out LEDs, Buttons and i2c devices */ diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index d675e727803d..147615510dd0 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c @@ -154,8 +154,8 @@ void __init edmini_v2_init(void) orion5x_ehci0_init(); orion5x_eth_init(&edmini_v2_eth_data); - orion5x_setup_dev_boot_win(EDMINI_V2_NOR_BOOT_BASE, - EDMINI_V2_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE, + EDMINI_V2_NOR_BOOT_SIZE); platform_device_register(&edmini_v2_nor_flash); pr_notice("edmini_v2: USB device port, flash write and power-off " diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index d265f5484a8e..b78ff3248868 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -66,8 +66,10 @@ * Orion Registers Map ******************************************************************************/ +#define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000) +#define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500) +#define ORION5X_DDR_WINS_SZ (0x10) #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) -#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500) #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) @@ -81,6 +83,8 @@ #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) #define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) +#define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE) +#define ORION5X_BRIDGE_WINS_SZ (0x80) #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index b98403526218..aae10e4a917c 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -359,13 +359,13 @@ static void __init kurobox_pro_init(void) orion5x_uart1_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, - KUROBOX_PRO_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE, + KUROBOX_PRO_NOR_BOOT_SIZE); platform_device_register(&kurobox_pro_nor_flash); if (machine_is_kurobox_pro()) { - orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, - KUROBOX_PRO_NAND_SIZE); + mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE, + KUROBOX_PRO_NAND_SIZE); platform_device_register(&kurobox_pro_nand_flash); } diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index 044da5b6a6ae..24f4e14e5893 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c @@ -294,8 +294,8 @@ static void __init lschl_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE, - LSCHL_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE, + LSCHL_NOR_BOOT_SIZE); platform_device_register(&lschl_nor_flash); platform_device_register(&lschl_leds); diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index d49f93423f52..fc653bb41e78 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -243,8 +243,8 @@ static void __init ls_hgl_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(LS_HGL_NOR_BOOT_BASE, - LS_HGL_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE, + LS_HGL_NOR_BOOT_SIZE); platform_device_register(&ls_hgl_nor_flash); platform_device_register(&ls_hgl_button_device); diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index 8e3965c6c0fe..18e66e617dc2 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c @@ -244,8 +244,8 @@ static void __init lsmini_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(LSMINI_NOR_BOOT_BASE, - LSMINI_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE, + LSMINI_NOR_BOOT_SIZE); platform_device_register(&lsmini_nor_flash); platform_device_register(&lsmini_button_device); diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 0ec94a1f2b16..827acbafc9dc 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -241,7 +241,8 @@ static void __init mss2_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE, + MSS2_NOR_BOOT_SIZE); platform_device_register(&mss2_nor_flash); platform_device_register(&mss2_button_device); diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index 18143f2a9093..92600ae2b4b6 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -204,7 +204,8 @@ static void __init mv2120_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE, + MV2120_NOR_BOOT_SIZE); platform_device_register(&mv2120_nor_flash); platform_device_register(&mv2120_button_device); diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index 282e503b003e..dd0641a0d074 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -397,8 +397,8 @@ static void __init net2big_init(void) net2big_sata_power_init(); orion5x_sata_init(&net2big_sata_data); - orion5x_setup_dev_boot_win(NET2BIG_NOR_BOOT_BASE, - NET2BIG_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE, + NET2BIG_NOR_BOOT_SIZE); platform_device_register(&net2big_nor_flash); platform_device_register(&net2big_gpio_buttons); diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index d9c7c3bf0d9c..503368023bb1 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -157,8 +157,11 @@ static int __init pcie_setup(struct pci_sys_data *sys) if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " "read transaction workaround\n"); - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); + mvebu_mbus_add_window_remap_flags("pcie0.0", + ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_WA); pcie_ops.read = pcie_rd_conf_wa; } @@ -402,8 +405,9 @@ static void __init orion5x_pci_master_slave_enable(void) orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); } -static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) +static void __init orion5x_setup_pci_wins(void) { + const struct mbus_dram_target_info *dram = mv_mbus_dram_info(); u32 win_enable; int bus; int i; @@ -420,7 +424,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) bus = orion5x_pci_local_bus_nr(); for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; + const struct mbus_dram_window *cs = dram->cs + i; u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); u32 reg; u32 val; @@ -467,7 +471,7 @@ static int __init pci_setup(struct pci_sys_data *sys) /* * Point PCI unit MBUS decode windows to DRAM space. */ - orion5x_setup_pci_wins(&orion_mbus_dram_info); + orion5x_setup_pci_wins(); /* * Master + Slave enable diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index d6e72f672afb..1c4498bf650a 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -123,8 +123,8 @@ static void __init rd88f5181l_fxo_init(void) orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); orion5x_uart0_init(); - orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE, - RD88F5181L_FXO_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE, + RD88F5181L_FXO_NOR_BOOT_SIZE); platform_device_register(&rd88f5181l_fxo_nor_boot_flash); } diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index c8b7913310e5..adabe34c4fc6 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -130,8 +130,8 @@ static void __init rd88f5181l_ge_init(void) orion5x_i2c_init(); orion5x_uart0_init(); - orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE, - RD88F5181L_GE_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE, + RD88F5181L_GE_NOR_BOOT_SIZE); platform_device_register(&rd88f5181l_ge_nor_boot_flash); i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index f9e156725d7c..66e77ec91532 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -264,10 +264,11 @@ static void __init rd88f5182_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE, + RD88F5182_NOR_BOOT_SIZE); - orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); + mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE, + RD88F5182_NOR_SIZE); platform_device_register(&rd88f5182_nor_flash); platform_device_register(&rd88f5182_gpio_leds); diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index acc0877ec1c9..a0bfa53e7556 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -329,8 +329,8 @@ static void __init tsp2_init(void) /* * Configure peripherals. */ - orion5x_setup_dev_boot_win(TSP2_NOR_BOOT_BASE, - TSP2_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE, + TSP2_NOR_BOOT_SIZE); platform_device_register(&tsp2_nor_flash); orion5x_ehci0_init(); diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 9c17f0c2b488..80174f0f168e 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -286,8 +286,8 @@ static void __init qnap_ts209_init(void) /* * Configure peripherals. */ - orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, - QNAP_TS209_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE); platform_device_register(&qnap_ts209_nor_flash); orion5x_ehci0_init(); diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 8cc5ab6c503e..92592790d6da 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -277,8 +277,8 @@ static void __init qnap_ts409_init(void) /* * Configure peripherals. */ - orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE, - QNAP_TS409_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE, + QNAP_TS409_NOR_BOOT_SIZE); platform_device_register(&qnap_ts409_nor_flash); orion5x_ehci0_init(); diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 66552ca7e05d..6b84863c018d 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -127,8 +127,8 @@ static void __init wnr854t_init(void) orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); orion5x_uart0_init(); - orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE, - WNR854T_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE, + WNR854T_NOR_BOOT_SIZE); platform_device_register(&wnr854t_nor_flash); } diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index 2c5408e2e689..fae684bc54f2 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -213,8 +213,8 @@ static void __init wrt350n_v2_init(void) orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ); orion5x_uart0_init(); - orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE, - WRT350N_V2_NOR_BOOT_SIZE); + mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE, + WRT350N_V2_NOR_BOOT_SIZE); platform_device_register(&wrt350n_v2_nor_flash); platform_device_register(&wrt350n_v2_leds); platform_device_register(&wrt350n_v2_button_device); diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index a82cecb84948..2eca54b65906 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -3,8 +3,6 @@ # ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include -obj-y += addr-map.o - orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y) diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c deleted file mode 100644 index 807ac8e5cbc0..000000000000 --- a/arch/arm/plat-orion/addr-map.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * arch/arm/plat-orion/addr-map.c - * - * Address map functions for Marvell Orion based SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <plat/addr-map.h> - -struct mbus_dram_target_info orion_mbus_dram_info; - -const struct mbus_dram_target_info *mv_mbus_dram_info(void) -{ - return &orion_mbus_dram_info; -} -EXPORT_SYMBOL_GPL(mv_mbus_dram_info); - -/* - * DDR target is the same on all Orion platforms. - */ -#define TARGET_DDR 0 - -/* - * Helpers to get DDR bank info - */ -#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) - -/* - * CPU Address Decode Windows registers - */ -#define WIN_CTRL_OFF 0x0000 -#define WIN_BASE_OFF 0x0004 -#define WIN_REMAP_LO_OFF 0x0008 -#define WIN_REMAP_HI_OFF 0x000c - -#define ATTR_HW_COHERENCY (0x1 << 4) - -/* - * Default implementation - */ -static void __init __iomem * -orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) -{ - return cfg->bridge_virt_base + (win << 4); -} - -/* - * Default implementation - */ -static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, - const int win) -{ - if (win < cfg->remappable_wins) - return 1; - - return 0; -} - -void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, - const int win, const u32 base, - const u32 size, const u8 target, - const u8 attr, const int remap) -{ - void __iomem *addr = cfg->win_cfg_base(cfg, win); - u32 ctrl, base_high, remap_addr; - - if (win >= cfg->num_wins) { - printk(KERN_ERR "setup_cpu_win: trying to allocate window " - "%d when only %d allowed\n", win, cfg->num_wins); - } - - base_high = base & 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base_high, addr + WIN_BASE_OFF); - writel(ctrl, addr + WIN_CTRL_OFF); - if (cfg->cpu_win_can_remap(cfg, win)) { - if (remap < 0) - remap_addr = base; - else - remap_addr = remap; - writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } -} - -/* - * Configure a number of windows. - */ -static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg, - const struct orion_addr_map_info *info) -{ - while (info->win != -1) { - orion_setup_cpu_win(cfg, info->win, info->base, info->size, - info->target, info->attr, info->remap); - info++; - } -} - -static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg) -{ - void __iomem *addr; - int i; - - for (i = 0; i < cfg->num_wins; i++) { - addr = cfg->win_cfg_base(cfg, i); - - writel(0, addr + WIN_BASE_OFF); - writel(0, addr + WIN_CTRL_OFF); - if (cfg->cpu_win_can_remap(cfg, i)) { - writel(0, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } - } -} - -/* - * Disable, clear and configure windows. - */ -void __init orion_config_wins(struct orion_addr_map_cfg * cfg, - const struct orion_addr_map_info *info) -{ - if (!cfg->cpu_win_can_remap) - cfg->cpu_win_can_remap = orion_cpu_win_can_remap; - - if (!cfg->win_cfg_base) - cfg->win_cfg_base = orion_win_cfg_base; - - orion_disable_wins(cfg); - - if (info) - orion_setup_cpu_wins(cfg, info); -} - -/* - * Setup MBUS dram target info. - */ -void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, - const void __iomem *ddr_window_cpu_base) -{ - int i; - int cs; - - orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i)); - u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i)); - - /* - * We only take care of entries for which the chip - * select is enabled, and that don't have high base - * address bits set (devices can only access the first - * 32 bits of the memory). - */ - if ((size & 1) && !(base & 0xF)) { - struct mbus_dram_window *w; - - w = &orion_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - if (cfg->hw_io_coherency) - w->mbus_attr |= ATTR_HW_COHERENCY; - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - orion_mbus_dram_info.num_cs = cs; -} diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index c29ee7ea200b..e39c2ba6e2fb 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -439,6 +439,64 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) } } +#ifdef CONFIG_DEBUG_FS +#include <linux/seq_file.h> + +static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + struct orion_gpio_chip *ochip = + container_of(chip, struct orion_gpio_chip, chip); + u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; + int i; + + out = readl_relaxed(GPIO_OUT(ochip)); + io_conf = readl_relaxed(GPIO_IO_CONF(ochip)); + blink = readl_relaxed(GPIO_BLINK_EN(ochip)); + in_pol = readl_relaxed(GPIO_IN_POL(ochip)); + data_in = readl_relaxed(GPIO_DATA_IN(ochip)); + cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip)); + edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip)); + lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip)); + + for (i = 0; i < chip->ngpio; i++) { + const char *label; + u32 msk; + bool is_out; + + label = gpiochip_is_requested(chip, i); + if (!label) + continue; + + msk = 1 << i; + is_out = !(io_conf & msk); + + seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); + + if (is_out) { + seq_printf(s, " out %s %s\n", + out & msk ? "hi" : "lo", + blink & msk ? "(blink )" : ""); + continue; + } + + seq_printf(s, " in %s (act %s) - IRQ", + (data_in ^ in_pol) & msk ? "hi" : "lo", + in_pol & msk ? "lo" : "hi"); + if (!((edg_msk | lvl_msk) & msk)) { + seq_printf(s, " disabled\n"); + continue; + } + if (edg_msk & msk) + seq_printf(s, " edge "); + if (lvl_msk & msk) + seq_printf(s, " level"); + seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); + } +} +#else +#define orion_gpio_dbg_show NULL +#endif + void __init orion_gpio_init(struct device_node *np, int gpio_base, int ngpio, void __iomem *base, int mask_offset, @@ -471,6 +529,7 @@ void __init orion_gpio_init(struct device_node *np, #ifdef CONFIG_OF ochip->chip.of_node = np; #endif + ochip->chip.dbg_show = orion_gpio_dbg_show; spin_lock_init(&ochip->lock); ochip->base = (void __iomem *)base; diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index f20a321088a2..8b8c06d2e9c4 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base) * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks * WIN[0-3] -> DRAM bank[0-3] */ -static void __init orion_pcie_setup_wins(void __iomem *base, - struct mbus_dram_target_info *dram) +static void __init orion_pcie_setup_wins(void __iomem *base) { + const struct mbus_dram_target_info *dram; u32 size; int i; + dram = mv_mbus_dram_info(); + /* * First, disable and clear BARs and windows. */ @@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, */ size = 0; for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; + const struct mbus_dram_window *cs = dram->cs + i; writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); writel(0, base + PCIE_WIN04_REMAP_OFF(i)); @@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base) /* * Point PCIe unit MBUS decode windows to DRAM space. */ - orion_pcie_setup_wins(base, &orion_mbus_dram_info); + orion_pcie_setup_wins(base); /* * Master + slave enable. |