diff options
Diffstat (limited to 'drivers/tty')
| -rw-r--r-- | drivers/tty/serial/Kconfig | 20 | ||||
| -rw-r--r-- | drivers/tty/serial/Makefile | 2 | ||||
| -rw-r--r-- | drivers/tty/serial/amba-pl011.c | 1 | ||||
| -rw-r--r-- | drivers/tty/serial/arc_uart.c | 1 | ||||
| -rw-r--r-- | drivers/tty/serial/earlycon.c | 10 | ||||
| -rw-r--r-- | drivers/tty/serial/msm_serial.c | 295 | ||||
| -rw-r--r-- | drivers/tty/serial/msm_serial.h | 184 | ||||
| -rw-r--r-- | drivers/tty/serial/msm_serial_hs.c | 3915 | ||||
| -rw-r--r-- | drivers/tty/serial/msm_serial_hs_hwreg.h | 283 | ||||
| -rw-r--r-- | drivers/tty/serial/msm_smd_tty.c | 1045 | ||||
| -rw-r--r-- | drivers/tty/serial/samsung.c | 6 | ||||
| -rw-r--r-- | drivers/tty/serial/sprd_serial.c | 2 | ||||
| -rw-r--r-- | drivers/tty/sysrq.c | 3 | ||||
| -rw-r--r-- | drivers/tty/tty_buffer.c | 28 | ||||
| -rw-r--r-- | drivers/tty/tty_port.c | 10 |
15 files changed, 5554 insertions, 251 deletions
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 5c3c86d4fe71..dcef571299e7 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1055,6 +1055,18 @@ config SERIAL_MSM_CONSOLE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON +config SERIAL_MSM_HS + tristate "MSM UART High Speed: Serial Driver" + depends on ARCH_QCOM + select SERIAL_CORE + help + If you have a machine based on MSM family of SoCs, you + can enable its onboard high speed serial port by enabling + this option. + + Choose M here to compile it as a module. The module will be + called msm_serial_hs. + config SERIAL_VT8500 bool "VIA VT8500 on-chip serial port support" depends on ARCH_VT8500 @@ -1409,6 +1421,14 @@ config SERIAL_PCH_UART_CONSOLE (the system console is the device which receives all kernel messages and warnings and which allows logins in single user mode). +config SERIAL_MSM_SMD + bool "Enable tty device interface for some SMD ports" + default n + depends on MSM_SMD + help + Enables userspace clients to read and write to some streaming SMD + ports via tty device interface for MSM chipset. + config SERIAL_MXS_AUART depends on ARCH_MXS || COMPILE_TEST tristate "MXS AUART support" diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 5ab41119b3dc..666b7c452b12 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o obj-$(CONFIG_SERIAL_MSM) += msm_serial.o +obj-$(CONFIG_SERIAL_MSM_HS) += msm_serial_hs.o obj-$(CONFIG_SERIAL_NETX) += netx-serial.o obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o @@ -79,6 +80,7 @@ obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o +obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 562f2a40e083..cc99a2b6e3eb 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -2227,7 +2227,6 @@ static int __init pl011_early_console_setup(struct earlycon_device *device, device->con->write = pl011_early_write; return 0; } -EARLYCON_DECLARE(pl011, pl011_early_console_setup); OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); #else diff --git a/drivers/tty/serial/arc_uart.c b/drivers/tty/serial/arc_uart.c index 040018d59608..37959c8f42a9 100644 --- a/drivers/tty/serial/arc_uart.c +++ b/drivers/tty/serial/arc_uart.c @@ -576,7 +576,6 @@ static int __init arc_early_console_setup(struct earlycon_device *dev, dev->con->write = arc_early_serial_write; return 0; } -EARLYCON_DECLARE(arc_uart, arc_early_console_setup); OF_EARLYCON_DECLARE(arc_uart, "snps,arc-uart", arc_early_console_setup); #endif /* CONFIG_SERIAL_ARC_CONSOLE */ diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c index b5b2f2be6be7..4d2e3e7a40bb 100644 --- a/drivers/tty/serial/earlycon.c +++ b/drivers/tty/serial/earlycon.c @@ -19,7 +19,6 @@ #include <linux/io.h> #include <linux/serial_core.h> #include <linux/sizes.h> -#include <linux/mod_devicetable.h> #ifdef CONFIG_FIX_EARLYCON_MEM #include <asm/fixmap.h> @@ -37,13 +36,6 @@ static struct earlycon_device early_console_dev = { .con = &early_con, }; -extern struct earlycon_id __earlycon_table[]; -static const struct earlycon_id __earlycon_table_sentinel - __used __section(__earlycon_table_end); - -static const struct of_device_id __earlycon_of_table_sentinel - __used __section(__earlycon_of_table_end); - static void __iomem * __init earlycon_map(unsigned long paddr, size_t size) { void __iomem *base; @@ -159,7 +151,7 @@ int __init setup_earlycon(char *buf) if (early_con.flags & CON_ENABLED) return -EALREADY; - for (match = __earlycon_table; match->name[0]; match++) { + for (match = __earlycon_table; match < __earlycon_table_end; match++) { size_t len = strlen(match->name); if (strncmp(buf, match->name, len)) diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c index 5fbb2d56565d..cfb6ecdbb99f 100644 --- a/drivers/tty/serial/msm_serial.c +++ b/drivers/tty/serial/msm_serial.c @@ -19,33 +19,147 @@ # define SUPPORT_SYSRQ #endif +#include <linux/kernel.h> #include <linux/atomic.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> -#include <linux/hrtimer.h> #include <linux/module.h> #include <linux/io.h> #include <linux/ioport.h> -#include <linux/irq.h> +#include <linux/interrupt.h> #include <linux/init.h> #include <linux/console.h> #include <linux/tty.h> #include <linux/tty_flip.h> #include <linux/serial_core.h> -#include <linux/serial.h> #include <linux/slab.h> #include <linux/clk.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/of.h> #include <linux/of_device.h> - -#include "msm_serial.h" - -#define UARTDM_BURST_SIZE 16 /* in bytes */ -#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */ -#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */ -#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4) +#include <linux/wait.h> + +#define UART_MR1 0x0000 + +#define UART_MR1_AUTO_RFR_LEVEL0 0x3F +#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 +#define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 +#define UART_MR1_RX_RDY_CTL BIT(7) +#define UART_MR1_CTS_CTL BIT(6) + +#define UART_MR2 0x0004 +#define UART_MR2_ERROR_MODE BIT(6) +#define UART_MR2_BITS_PER_CHAR 0x30 +#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) +#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) +#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) +#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) +#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) +#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) +#define UART_MR2_PARITY_MODE_NONE 0x0 +#define UART_MR2_PARITY_MODE_ODD 0x1 +#define UART_MR2_PARITY_MODE_EVEN 0x2 +#define UART_MR2_PARITY_MODE_SPACE 0x3 +#define UART_MR2_PARITY_MODE 0x3 + +#define UART_CSR 0x0008 + +#define UART_TF 0x000C +#define UARTDM_TF 0x0070 + +#define UART_CR 0x0010 +#define UART_CR_CMD_NULL (0 << 4) +#define UART_CR_CMD_RESET_RX (1 << 4) +#define UART_CR_CMD_RESET_TX (2 << 4) +#define UART_CR_CMD_RESET_ERR (3 << 4) +#define UART_CR_CMD_RESET_BREAK_INT (4 << 4) +#define UART_CR_CMD_START_BREAK (5 << 4) +#define UART_CR_CMD_STOP_BREAK (6 << 4) +#define UART_CR_CMD_RESET_CTS (7 << 4) +#define UART_CR_CMD_RESET_STALE_INT (8 << 4) +#define UART_CR_CMD_PACKET_MODE (9 << 4) +#define UART_CR_CMD_MODE_RESET (12 << 4) +#define UART_CR_CMD_SET_RFR (13 << 4) +#define UART_CR_CMD_RESET_RFR (14 << 4) +#define UART_CR_CMD_PROTECTION_EN (16 << 4) +#define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) +#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) +#define UART_CR_CMD_FORCE_STALE (4 << 8) +#define UART_CR_CMD_RESET_TX_READY (3 << 8) +#define UART_CR_TX_DISABLE BIT(3) +#define UART_CR_TX_ENABLE BIT(2) +#define UART_CR_RX_DISABLE BIT(1) +#define UART_CR_RX_ENABLE BIT(0) +#define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) + +#define UART_IMR 0x0014 +#define UART_IMR_TXLEV BIT(0) +#define UART_IMR_RXSTALE BIT(3) +#define UART_IMR_RXLEV BIT(4) +#define UART_IMR_DELTA_CTS BIT(5) +#define UART_IMR_CURRENT_CTS BIT(6) +#define UART_IMR_RXBREAK_START BIT(10) + +#define UART_IPR_RXSTALE_LAST 0x20 +#define UART_IPR_STALE_LSB 0x1F +#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 +#define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 + +#define UART_IPR 0x0018 +#define UART_TFWR 0x001C +#define UART_RFWR 0x0020 +#define UART_HCR 0x0024 + +#define UART_MREG 0x0028 +#define UART_NREG 0x002C +#define UART_DREG 0x0030 +#define UART_MNDREG 0x0034 +#define UART_IRDA 0x0038 +#define UART_MISR_MODE 0x0040 +#define UART_MISR_RESET 0x0044 +#define UART_MISR_EXPORT 0x0048 +#define UART_MISR_VAL 0x004C +#define UART_TEST_CTRL 0x0050 + +#define UART_SR 0x0008 +#define UART_SR_HUNT_CHAR BIT(7) +#define UART_SR_RX_BREAK BIT(6) +#define UART_SR_PAR_FRAME_ERR BIT(5) +#define UART_SR_OVERRUN BIT(4) +#define UART_SR_TX_EMPTY BIT(3) +#define UART_SR_TX_READY BIT(2) +#define UART_SR_RX_FULL BIT(1) +#define UART_SR_RX_READY BIT(0) + +#define UART_RF 0x000C +#define UARTDM_RF 0x0070 +#define UART_MISR 0x0010 +#define UART_ISR 0x0014 +#define UART_ISR_TX_READY BIT(7) + +#define UARTDM_RXFS 0x50 +#define UARTDM_RXFS_BUF_SHIFT 0x7 +#define UARTDM_RXFS_BUF_MASK 0x7 + +#define UARTDM_DMEN 0x3C +#define UARTDM_DMEN_RX_SC_ENABLE BIT(5) +#define UARTDM_DMEN_TX_SC_ENABLE BIT(4) + +#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */ +#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */ + +#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */ +#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */ + +#define UARTDM_DMRX 0x34 +#define UARTDM_NCF_TX 0x40 +#define UARTDM_RX_TOTAL_SNAP 0x38 + +#define UARTDM_BURST_SIZE 16 /* in bytes */ +#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */ +#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */ +#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4) enum { UARTDM_1P1 = 1, @@ -78,10 +192,65 @@ struct msm_port { struct msm_dma rx_dma; }; +#define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart) + +static +void msm_write(struct uart_port *port, unsigned int val, unsigned int off) +{ + writel_relaxed_no_log(val, port->membase + off); +} + +static +unsigned int msm_read(struct uart_port *port, unsigned int off) +{ + return readl_relaxed_no_log(port->membase + off); +} + +/* + * Setup the MND registers to use the TCXO clock. + */ +static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port) +{ + msm_write(port, 0x06, UART_MREG); + msm_write(port, 0xF1, UART_NREG); + msm_write(port, 0x0F, UART_DREG); + msm_write(port, 0x1A, UART_MNDREG); + port->uartclk = 1843200; +} + +/* + * Setup the MND registers to use the TCXO clock divided by 4. + */ +static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port) +{ + msm_write(port, 0x18, UART_MREG); + msm_write(port, 0xF6, UART_NREG); + msm_write(port, 0x0F, UART_DREG); + msm_write(port, 0x0A, UART_MNDREG); + port->uartclk = 1843200; +} + +static void msm_serial_set_mnd_regs(struct uart_port *port) +{ + struct msm_port *msm_port = UART_TO_MSM(port); + + /* + * These registers don't exist so we change the clk input rate + * on uartdm hardware instead + */ + if (msm_port->is_uartdm) + return; + + if (port->uartclk == 19200000) + msm_serial_set_mnd_regs_tcxo(port); + else if (port->uartclk == 4800000) + msm_serial_set_mnd_regs_tcxoby4(port); +} + static void msm_handle_tx(struct uart_port *port); static void msm_start_rx_dma(struct msm_port *msm_port); -void msm_stop_dma(struct uart_port *port, struct msm_dma *dma) +static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma) { struct device *dev = port->dev; unsigned int mapped; @@ -134,15 +303,17 @@ static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base) struct device *dev = msm_port->uart.dev; struct dma_slave_config conf; struct msm_dma *dma; + struct dma_chan *dma_chan; u32 crci = 0; int ret; dma = &msm_port->tx_dma; /* allocate DMA resources, if available */ - dma->chan = dma_request_slave_channel_reason(dev, "tx"); - if (IS_ERR(dma->chan)) + dma_chan = dma_request_slave_channel_reason(dev, "tx"); + if (IS_ERR(dma_chan)) goto no_tx; + dma->chan = dma_chan; of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci); @@ -177,15 +348,17 @@ static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base) struct device *dev = msm_port->uart.dev; struct dma_slave_config conf; struct msm_dma *dma; + struct dma_chan *dma_chan; u32 crci = 0; int ret; dma = &msm_port->rx_dma; /* allocate DMA resources, if available */ - dma->chan = dma_request_slave_channel_reason(dev, "rx"); - if (IS_ERR(dma->chan)) + dma_chan = dma_request_slave_channel_reason(dev, "rx"); + if (IS_ERR(dma_chan)) goto no_rx; + dma->chan = dma_chan; of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci); @@ -392,10 +565,6 @@ static void msm_complete_rx_dma(void *args) val &= ~dma->enable_bit; msm_write(port, val, UARTDM_DMEN); - /* Restore interrupts */ - msm_port->imr |= UART_IMR_RXLEV | UART_IMR_RXSTALE; - msm_write(port, msm_port->imr, UART_IMR); - if (msm_read(port, UART_SR) & UART_SR_OVERRUN) { port->icount.overrun++; tty_insert_flip_char(tport, 0, TTY_OVERRUN); @@ -1003,15 +1172,6 @@ static int msm_set_baud_rate(struct uart_port *port, unsigned int baud, return baud; } -static void msm_init_clock(struct uart_port *port) -{ - struct msm_port *msm_port = UART_TO_MSM(port); - - clk_prepare_enable(msm_port->clk); - clk_prepare_enable(msm_port->pclk); - msm_serial_set_mnd_regs(port); -} - static int msm_startup(struct uart_port *port) { struct msm_port *msm_port = UART_TO_MSM(port); @@ -1021,12 +1181,19 @@ static int msm_startup(struct uart_port *port) snprintf(msm_port->name, sizeof(msm_port->name), "msm_serial%d", port->line); - ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH, - msm_port->name, port); - if (unlikely(ret)) + /* + * UART clk must be kept enabled to + * avoid losing received character + */ + ret = clk_prepare_enable(msm_port->clk); + if (ret) return ret; - msm_init_clock(port); + ret = clk_prepare_enable(msm_port->pclk); + if (ret) + goto err_pclk; + + msm_serial_set_mnd_regs(port); if (likely(port->fifosize > 12)) rfr_level = port->fifosize - 12; @@ -1052,7 +1219,23 @@ static int msm_startup(struct uart_port *port) msm_request_rx_dma(msm_port, msm_port->uart.mapbase); } + ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH, + msm_port->name, port); + if (unlikely(ret)) + goto err_irq; + return 0; + +err_irq: + if (msm_port->is_uartdm) + msm_release_dma(msm_port); + + clk_disable_unprepare(msm_port->pclk); + +err_pclk: + clk_disable_unprepare(msm_port->clk); + + return ret; } static void msm_shutdown(struct uart_port *port) @@ -1065,6 +1248,7 @@ static void msm_shutdown(struct uart_port *port) if (msm_port->is_uartdm) msm_release_dma(msm_port); + clk_disable_unprepare(msm_port->pclk); clk_disable_unprepare(msm_port->clk); free_irq(port->irq, port); @@ -1231,8 +1415,16 @@ static void msm_power(struct uart_port *port, unsigned int state, switch (state) { case 0: - clk_prepare_enable(msm_port->clk); - clk_prepare_enable(msm_port->pclk); + /* + * UART clk must be kept enabled to + * avoid losing received character + */ + if (clk_prepare_enable(msm_port->clk)) + return; + if (clk_prepare_enable(msm_port->pclk)) { + clk_disable_unprepare(msm_port->clk); + return; + } break; case 3: clk_disable_unprepare(msm_port->clk); @@ -1442,6 +1634,7 @@ static void __msm_console_write(struct uart_port *port, const char *s, int j; unsigned int num_chars; char buf[4] = { 0 }; + const u32 *buffer; if (is_uartdm) num_chars = min(count - i, (unsigned int)sizeof(buf)); @@ -1466,7 +1659,8 @@ static void __msm_console_write(struct uart_port *port, const char *s, while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) cpu_relax(); - iowrite32_rep(tf, buf, 1); + buffer = (const u32 *)buf; + writel_relaxed_no_log(*buffer, tf); i += num_chars; } @@ -1504,7 +1698,7 @@ static int __init msm_console_setup(struct console *co, char *options) if (unlikely(!port->membase)) return -ENXIO; - msm_init_clock(port); + msm_serial_set_mnd_regs(port); if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); @@ -1531,7 +1725,6 @@ msm_serial_early_console_setup(struct earlycon_device *device, const char *opt) device->con->write = msm_serial_early_write; return 0; } -EARLYCON_DECLARE(msm_serial, msm_serial_early_console_setup); OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart", msm_serial_early_console_setup); @@ -1553,7 +1746,6 @@ msm_serial_early_console_setup_dm(struct earlycon_device *device, device->con->write = msm_serial_early_write_dm; return 0; } -EARLYCON_DECLARE(msm_serial_dm, msm_serial_early_console_setup_dm); OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm", msm_serial_early_console_setup_dm); @@ -1632,8 +1824,6 @@ static int msm_serial_probe(struct platform_device *pdev) msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); if (IS_ERR(msm_port->pclk)) return PTR_ERR(msm_port->pclk); - - clk_set_rate(msm_port->clk, 1843200); } port->uartclk = clk_get_rate(msm_port->clk); @@ -1670,12 +1860,37 @@ static const struct of_device_id msm_match_table[] = { }; MODULE_DEVICE_TABLE(of, msm_match_table); +#ifdef CONFIG_PM_SLEEP +static int msm_serial_suspend(struct device *dev) +{ + struct uart_port *port = dev_get_drvdata(dev); + + uart_suspend_port(&msm_uart_driver, port); + + return 0; +} + +static int msm_serial_resume(struct device *dev) +{ + struct uart_port *port = dev_get_drvdata(dev); + + uart_resume_port(&msm_uart_driver, port); + + return 0; +} +#endif + +static const struct dev_pm_ops msm_serial_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume) +}; + static struct platform_driver msm_platform_driver = { .remove = msm_serial_remove, .probe = msm_serial_probe, .driver = { .name = "msm_serial", .of_match_table = msm_match_table, + .pm = &msm_serial_pm_ops, }, }; diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h deleted file mode 100644 index 178645826f16..000000000000 --- a/drivers/tty/serial/msm_serial.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (C) 2007 Google, Inc. - * Author: Robert Love <rlove@google.com> - * Copyright (c) 2011, Code Aurora Forum. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DRIVERS_SERIAL_MSM_SERIAL_H -#define __DRIVERS_SERIAL_MSM_SERIAL_H - -#define UART_MR1 0x0000 - -#define UART_MR1_AUTO_RFR_LEVEL0 0x3F -#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 -#define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 -#define UART_MR1_RX_RDY_CTL BIT(7) -#define UART_MR1_CTS_CTL BIT(6) - -#define UART_MR2 0x0004 -#define UART_MR2_ERROR_MODE BIT(6) -#define UART_MR2_BITS_PER_CHAR 0x30 -#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) -#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) -#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) -#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) -#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) -#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) -#define UART_MR2_PARITY_MODE_NONE 0x0 -#define UART_MR2_PARITY_MODE_ODD 0x1 -#define UART_MR2_PARITY_MODE_EVEN 0x2 -#define UART_MR2_PARITY_MODE_SPACE 0x3 -#define UART_MR2_PARITY_MODE 0x3 - -#define UART_CSR 0x0008 - -#define UART_TF 0x000C -#define UARTDM_TF 0x0070 - -#define UART_CR 0x0010 -#define UART_CR_CMD_NULL (0 << 4) -#define UART_CR_CMD_RESET_RX (1 << 4) -#define UART_CR_CMD_RESET_TX (2 << 4) -#define UART_CR_CMD_RESET_ERR (3 << 4) -#define UART_CR_CMD_RESET_BREAK_INT (4 << 4) -#define UART_CR_CMD_START_BREAK (5 << 4) -#define UART_CR_CMD_STOP_BREAK (6 << 4) -#define UART_CR_CMD_RESET_CTS (7 << 4) -#define UART_CR_CMD_RESET_STALE_INT (8 << 4) -#define UART_CR_CMD_PACKET_MODE (9 << 4) -#define UART_CR_CMD_MODE_RESET (12 << 4) -#define UART_CR_CMD_SET_RFR (13 << 4) -#define UART_CR_CMD_RESET_RFR (14 << 4) -#define UART_CR_CMD_PROTECTION_EN (16 << 4) -#define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) -#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) -#define UART_CR_CMD_FORCE_STALE (4 << 8) -#define UART_CR_CMD_RESET_TX_READY (3 << 8) -#define UART_CR_TX_DISABLE BIT(3) -#define UART_CR_TX_ENABLE BIT(2) -#define UART_CR_RX_DISABLE BIT(1) -#define UART_CR_RX_ENABLE BIT(0) -#define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) - -#define UART_IMR 0x0014 -#define UART_IMR_TXLEV BIT(0) -#define UART_IMR_RXSTALE BIT(3) -#define UART_IMR_RXLEV BIT(4) -#define UART_IMR_DELTA_CTS BIT(5) -#define UART_IMR_CURRENT_CTS BIT(6) -#define UART_IMR_RXBREAK_START BIT(10) - -#define UART_IPR_RXSTALE_LAST 0x20 -#define UART_IPR_STALE_LSB 0x1F -#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 -#define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 - -#define UART_IPR 0x0018 -#define UART_TFWR 0x001C -#define UART_RFWR 0x0020 -#define UART_HCR 0x0024 - -#define UART_MREG 0x0028 -#define UART_NREG 0x002C -#define UART_DREG 0x0030 -#define UART_MNDREG 0x0034 -#define UART_IRDA 0x0038 -#define UART_MISR_MODE 0x0040 -#define UART_MISR_RESET 0x0044 -#define UART_MISR_EXPORT 0x0048 -#define UART_MISR_VAL 0x004C -#define UART_TEST_CTRL 0x0050 - -#define UART_SR 0x0008 -#define UART_SR_HUNT_CHAR BIT(7) -#define UART_SR_RX_BREAK BIT(6) -#define UART_SR_PAR_FRAME_ERR BIT(5) -#define UART_SR_OVERRUN BIT(4) -#define UART_SR_TX_EMPTY BIT(3) -#define UART_SR_TX_READY BIT(2) -#define UART_SR_RX_FULL BIT(1) -#define UART_SR_RX_READY BIT(0) - -#define UART_RF 0x000C -#define UARTDM_RF 0x0070 -#define UART_MISR 0x0010 -#define UART_ISR 0x0014 -#define UART_ISR_TX_READY BIT(7) - -#define UARTDM_RXFS 0x50 -#define UARTDM_RXFS_BUF_SHIFT 0x7 -#define UARTDM_RXFS_BUF_MASK 0x7 - -#define UARTDM_DMEN 0x3C -#define UARTDM_DMEN_RX_SC_ENABLE BIT(5) -#define UARTDM_DMEN_TX_SC_ENABLE BIT(4) - -#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */ -#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */ - -#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */ -#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */ - -#define UARTDM_DMRX 0x34 -#define UARTDM_NCF_TX 0x40 -#define UARTDM_RX_TOTAL_SNAP 0x38 - -#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port) - -static inline -void msm_write(struct uart_port *port, unsigned int val, unsigned int off) -{ - writel_relaxed(val, port->membase + off); -} - -static inline -unsigned int msm_read(struct uart_port *port, unsigned int off) -{ - return readl_relaxed(port->membase + off); -} - -/* - * Setup the MND registers to use the TCXO clock. - */ -static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port) -{ - msm_write(port, 0x06, UART_MREG); - msm_write(port, 0xF1, UART_NREG); - msm_write(port, 0x0F, UART_DREG); - msm_write(port, 0x1A, UART_MNDREG); - port->uartclk = 1843200; -} - -/* - * Setup the MND registers to use the TCXO clock divided by 4. - */ -static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port) -{ - msm_write(port, 0x18, UART_MREG); - msm_write(port, 0xF6, UART_NREG); - msm_write(port, 0x0F, UART_DREG); - msm_write(port, 0x0A, UART_MNDREG); - port->uartclk = 1843200; -} - -static inline -void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port) -{ - if (port->uartclk == 19200000) - msm_serial_set_mnd_regs_tcxo(port); - else if (port->uartclk == 4800000) - msm_serial_set_mnd_regs_tcxoby4(port); -} - -#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk - -#endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */ diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c new file mode 100644 index 000000000000..fd191761bfa1 --- /dev/null +++ b/drivers/tty/serial/msm_serial_hs.c @@ -0,0 +1,3915 @@ +/* drivers/serial/msm_serial_hs.c + * + * MSM 7k High speed uart driver + * + * Copyright (c) 2008 Google Inc. + * Copyright (c) 2007-2019, The Linux Foundation. All rights reserved. + * Modified: Nick Pelly <npelly@google.com> + * + * All source code in this file is licensed under the following license + * except where indicated. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * Has optional support for uart power management independent of linux + * suspend/resume: + * + * RX wakeup. + * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the + * UART RX pin). This should only be used if there is not a wakeup + * GPIO on the UART CTS, and the first RX byte is known (for example, with the + * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will + * always be lost. RTS will be asserted even while the UART is off in this mode + * of operation. See msm_serial_hs_platform_data.rx_wakeup_irq. + */ + +#include <linux/module.h> + +#include <linux/serial.h> +#include <linux/serial_core.h> +#include <linux/slab.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/atomic.h> +#include <linux/kernel.h> +#include <linux/timer.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/dma-mapping.h> +#include <linux/tty_flip.h> +#include <linux/wait.h> +#include <linux/sysfs.h> +#include <linux/stat.h> +#include <linux/device.h> +#include <linux/wakelock.h> +#include <linux/debugfs.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_gpio.h> +#include <linux/gpio.h> +#include <linux/ipc_logging.h> +#include <asm/irq.h> +#include <linux/kthread.h> +#include <uapi/linux/sched.h> + +#include <linux/msm-sps.h> +#include <linux/platform_data/msm_serial_hs.h> +#include <linux/msm-bus.h> +#include <soc/qcom/boot_stats.h> + +#include "msm_serial_hs_hwreg.h" +#define UART_SPS_CONS_PERIPHERAL 0 +#define UART_SPS_PROD_PERIPHERAL 1 + +#define IPC_MSM_HS_LOG_STATE_PAGES 2 +#define IPC_MSM_HS_LOG_USER_PAGES 2 +#define IPC_MSM_HS_LOG_DATA_PAGES 3 +#define UART_DMA_DESC_NR 8 +#define BUF_DUMP_SIZE 32 + +/* If the debug_mask gets set to FATAL_LEV, + * a fatal error has happened and further IPC logging + * is disabled so that this problem can be detected + */ +enum { + FATAL_LEV = 0U, + ERR_LEV = 1U, + WARN_LEV = 2U, + INFO_LEV = 3U, + DBG_LEV = 4U, +}; + +#define MSM_HS_DBG(x...) do { \ + if (msm_uport->ipc_debug_mask >= DBG_LEV) { \ + if (msm_uport->ipc_msm_hs_log_ctxt) \ + ipc_log_string(msm_uport->ipc_msm_hs_log_ctxt, x); \ + } \ +} while (0) + +#define MSM_HS_INFO(x...) do { \ + if (msm_uport->ipc_debug_mask >= INFO_LEV) {\ + if (msm_uport->ipc_msm_hs_log_ctxt) \ + ipc_log_string(msm_uport->ipc_msm_hs_log_ctxt, x); \ + } \ +} while (0) + +/* warnings and errors show up on console always */ +#define MSM_HS_WARN(x...) do { \ + pr_warn(x); \ + if (msm_uport->ipc_msm_hs_log_ctxt && \ + msm_uport->ipc_debug_mask >= WARN_LEV) \ + ipc_log_string(msm_uport->ipc_msm_hs_log_ctxt, x); \ +} while (0) + +/* ERROR condition in the driver sets the hs_serial_debug_mask + * to ERR_FATAL level, so that this message can be seen + * in IPC logging. Further errors continue to log on the console + */ +#define MSM_HS_ERR(x...) do { \ + pr_err(x); \ + if (msm_uport->ipc_msm_hs_log_ctxt && \ + msm_uport->ipc_debug_mask >= ERR_LEV) { \ + ipc_log_string(msm_uport->ipc_msm_hs_log_ctxt, x); \ + msm_uport->ipc_debug_mask = FATAL_LEV; \ + } \ +} while (0) + +#define LOG_USR_MSG(ctx, x...) do { \ + if (ctx) \ + ipc_log_string(ctx, x); \ +} while (0) + +/* + * There are 3 different kind of UART Core available on MSM. + * High Speed UART (i.e. Legacy HSUART), GSBI based HSUART + * and BSLP based HSUART. + */ +enum uart_core_type { + LEGACY_HSUART, + GSBI_HSUART, + BLSP_HSUART, +}; + +enum flush_reason { + FLUSH_NONE, + FLUSH_DATA_READY, + FLUSH_DATA_INVALID, /* values after this indicate invalid data */ + FLUSH_IGNORE, + FLUSH_STOP, + FLUSH_SHUTDOWN, +}; + +/* + * SPS data structures to support HSUART with BAM + * @sps_pipe - This struct defines BAM pipe descriptor + * @sps_connect - This struct defines a connection's end point + * @sps_register - This struct defines a event registration parameters + */ +struct msm_hs_sps_ep_conn_data { + struct sps_pipe *pipe_handle; + struct sps_connect config; + struct sps_register_event event; +}; + +struct msm_hs_tx { + bool dma_in_flight; /* tx dma in progress */ + enum flush_reason flush; + wait_queue_head_t wait; + int tx_count; + dma_addr_t dma_base; + struct kthread_work kwork; + struct kthread_worker kworker; + struct task_struct *task; + struct msm_hs_sps_ep_conn_data cons; + struct timer_list tx_timeout_timer; + void *ipc_tx_ctxt; +}; + +struct msm_hs_rx { + enum flush_reason flush; + wait_queue_head_t wait; + dma_addr_t rbuffer; + unsigned char *buffer; + unsigned int buffer_pending; + struct delayed_work flip_insert_work; + struct kthread_work kwork; + struct kthread_worker kworker; + struct task_struct *task; + struct msm_hs_sps_ep_conn_data prod; + unsigned long queued_flag; + unsigned long pending_flag; + int rx_inx; + struct sps_iovec iovec[UART_DMA_DESC_NR]; /* track descriptors */ + void *ipc_rx_ctxt; +}; +enum buffer_states { + NONE_PENDING = 0x0, + FIFO_OVERRUN = 0x1, + PARITY_ERROR = 0x2, + CHARS_NORMAL = 0x4, +}; + +enum msm_hs_pm_state { + MSM_HS_PM_ACTIVE, + MSM_HS_PM_SUSPENDED, + MSM_HS_PM_SYS_SUSPENDED, +}; + +/* optional low power wakeup, typically on a GPIO RX irq */ +struct msm_hs_wakeup { + int irq; /* < 0 indicates low power wakeup disabled */ + unsigned char ignore; /* bool */ + + /* bool: inject char into rx tty on wakeup */ + bool inject_rx; + unsigned char rx_to_inject; + bool enabled; + bool freed; +}; + +struct msm_hs_port { + atomic_t startup_locked; + struct uart_port uport; + unsigned long imr_reg; /* shadow value of UARTDM_IMR */ + struct clk *clk; + struct clk *pclk; + struct msm_hs_tx tx; + struct msm_hs_rx rx; + atomic_t resource_count; + struct msm_hs_wakeup wakeup; + + struct dentry *loopback_dir; + struct work_struct clock_off_w; /* work for actual clock off */ + struct workqueue_struct *hsuart_wq; /* hsuart workqueue */ + struct mutex mtx; /* resource access mutex */ + enum uart_core_type uart_type; + unsigned long bam_handle; + resource_size_t bam_mem; + int bam_irq; + unsigned char __iomem *bam_base; + unsigned int bam_tx_ep_pipe_index; + unsigned int bam_rx_ep_pipe_index; + /* struct sps_event_notify is an argument passed when triggering a + * callback event object registered for an SPS connection end point. + */ + struct sps_event_notify notify; + /* bus client handler */ + u32 bus_perf_client; + /* BLSP UART required BUS Scaling data */ + struct msm_bus_scale_pdata *bus_scale_table; + bool rx_bam_inprogress; + wait_queue_head_t bam_disconnect_wait; + bool use_pinctrl; + struct pinctrl *pinctrl; + struct pinctrl_state *gpio_state_active; + struct pinctrl_state *gpio_state_suspend; + bool flow_control; + enum msm_hs_pm_state pm_state; + atomic_t client_count; + bool obs; /* out of band sleep flag */ + atomic_t client_req_state; + int sys_suspend_noirq_cnt; + void *ipc_msm_hs_log_ctxt; + void *ipc_msm_hs_pwr_ctxt; + int ipc_debug_mask; +}; + +static struct of_device_id msm_hs_match_table[] = { + { .compatible = "qcom,msm-hsuart-v14"}, + {} +}; + + +#define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */ +#define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE +#define UARTDM_RX_BUF_SIZE 512 +#define RETRY_TIMEOUT 5 +#define UARTDM_NR 4 +#define BAM_PIPE_MIN 0 +#define BAM_PIPE_MAX 11 +#define BUS_SCALING 1 +#define BUS_RESET 0 +#define RX_FLUSH_COMPLETE_TIMEOUT 300 /* In jiffies */ +#define BLSP_UART_CLK_FMAX 63160000 + +static struct dentry *debug_base; +static struct platform_driver msm_serial_hs_platform_driver; +static struct uart_driver msm_hs_driver; +static struct uart_ops msm_hs_ops; +static void msm_hs_start_rx_locked(struct uart_port *uport); +static void msm_serial_hs_rx_work(struct kthread_work *work); +static void flip_insert_work(struct work_struct *work); +static void msm_hs_bus_voting(struct msm_hs_port *msm_uport, unsigned int vote); +static struct msm_hs_port *msm_hs_get_hs_port(int port_index); +static void msm_hs_queue_rx_desc(struct msm_hs_port *msm_uport); +static int disconnect_rx_endpoint(struct msm_hs_port *msm_uport); +static int msm_hs_pm_resume(struct device *dev); +static void msm_hs_pm_suspend(struct device *dev); + + +#define UARTDM_TO_MSM(uart_port) \ + container_of((uart_port), struct msm_hs_port, uport) + +static int msm_hs_ioctl(struct uart_port *uport, unsigned int cmd, + unsigned long arg) +{ + int ret = 0, state = 1; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + if (!msm_uport) + return -ENODEV; + + switch (cmd) { + case MSM_ENABLE_UART_CLOCK: { + ret = msm_hs_request_clock_on(&msm_uport->uport); + break; + } + case MSM_DISABLE_UART_CLOCK: { + ret = msm_hs_request_clock_off(&msm_uport->uport); + break; + } + case MSM_GET_UART_CLOCK_STATUS: { + /* Return value 0 - UART CLOCK is OFF + * Return value 1 - UART CLOCK is ON */ + + if (msm_uport->pm_state != MSM_HS_PM_ACTIVE) + state = 0; + ret = state; + MSM_HS_INFO("%s():GET UART CLOCK STATUS: cmd=%d state=%d\n", + __func__, cmd, state); + break; + } + default: { + MSM_HS_INFO("%s():Unknown cmd specified: cmd=%d\n", __func__, + cmd); + ret = -ENOIOCTLCMD; + break; + } + } + + return ret; +} + +/* + * This function is called initially during probe and then + * through the runtime PM framework. The function directly calls + * resource APIs to enable them. + */ + +static int msm_hs_clk_bus_vote(struct msm_hs_port *msm_uport) +{ + int rc = 0; + + msm_hs_bus_voting(msm_uport, BUS_SCALING); + /* Turn on core clk and iface clk */ + if (msm_uport->pclk) { + rc = clk_prepare_enable(msm_uport->pclk); + if (rc) { + dev_err(msm_uport->uport.dev, + "%s: Could not turn on pclk [%d]\n", + __func__, rc); + goto busreset; + } + } + rc = clk_prepare_enable(msm_uport->clk); + if (rc) { + dev_err(msm_uport->uport.dev, + "%s: Could not turn on core clk [%d]\n", + __func__, rc); + goto core_unprepare; + } + MSM_HS_DBG("%s: Clock ON successful\n", __func__); + return rc; +core_unprepare: + clk_disable_unprepare(msm_uport->pclk); +busreset: + msm_hs_bus_voting(msm_uport, BUS_RESET); + return rc; +} + +/* + * This function is called initially during probe and then + * through the runtime PM framework. The function directly calls + * resource apis to disable them. + */ +static void msm_hs_clk_bus_unvote(struct msm_hs_port *msm_uport) +{ + clk_disable_unprepare(msm_uport->clk); + if (msm_uport->pclk) + clk_disable_unprepare(msm_uport->pclk); + msm_hs_bus_voting(msm_uport, BUS_RESET); + MSM_HS_DBG("%s: Clock OFF successful\n", __func__); +} + + /* Remove vote for resources when done */ +static void msm_hs_resource_unvote(struct msm_hs_port *msm_uport) +{ + struct uart_port *uport = &(msm_uport->uport); + int rc = atomic_read(&msm_uport->resource_count); + + MSM_HS_DBG("%s(): power usage count %d", __func__, rc); + if (rc <= 0) { + MSM_HS_WARN("%s(): rc zero, bailing\n", __func__); + WARN_ON(1); + return; + } + atomic_dec(&msm_uport->resource_count); + pm_runtime_mark_last_busy(uport->dev); + pm_runtime_put_autosuspend(uport->dev); +} + + /* Vote for resources before accessing them */ +static void msm_hs_resource_vote(struct msm_hs_port *msm_uport) +{ + int ret; + struct uart_port *uport = &(msm_uport->uport); + ret = pm_runtime_get_sync(uport->dev); + if (ret < 0 || msm_uport->pm_state != MSM_HS_PM_ACTIVE) { + MSM_HS_WARN("%s:%s runtime callback not invoked ret:%d st:%d", + __func__, dev_name(uport->dev), ret, + msm_uport->pm_state); + msm_hs_pm_resume(uport->dev); + } + atomic_inc(&msm_uport->resource_count); +} + +/* Check if the uport line number matches with user id stored in pdata. + * User id information is stored during initialization. This function + * ensues that the same device is selected */ + +static struct msm_hs_port *get_matching_hs_port(struct platform_device *pdev) +{ + struct msm_serial_hs_platform_data *pdata = pdev->dev.platform_data; + struct msm_hs_port *msm_uport = msm_hs_get_hs_port(pdev->id); + + if ((!msm_uport) || (msm_uport->uport.line != pdev->id + && msm_uport->uport.line != pdata->userid)) { + pr_err("uport line number mismatch!"); + WARN_ON(1); + return NULL; + } + + return msm_uport; +} + +static ssize_t show_clock(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int state = 1; + ssize_t ret = 0; + struct platform_device *pdev = container_of(dev, struct + platform_device, dev); + struct msm_hs_port *msm_uport = get_matching_hs_port(pdev); + + /* This check should not fail */ + if (msm_uport) { + if (msm_uport->pm_state != MSM_HS_PM_ACTIVE) + state = 0; + ret = snprintf(buf, PAGE_SIZE, "%d\n", state); + } + return ret; +} + +static ssize_t set_clock(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int state; + ssize_t ret = 0; + struct platform_device *pdev = container_of(dev, struct + platform_device, dev); + struct msm_hs_port *msm_uport = get_matching_hs_port(pdev); + + /* This check should not fail */ + if (msm_uport) { + state = buf[0] - '0'; + switch (state) { + case 0: + MSM_HS_DBG("%s: Request clock OFF\n", __func__); + msm_hs_request_clock_off(&msm_uport->uport); + ret = count; + break; + case 1: + MSM_HS_DBG("%s: Request clock ON\n", __func__); + msm_hs_request_clock_on(&msm_uport->uport); + ret = count; + break; + default: + ret = -EINVAL; + } + } + return ret; +} + +static DEVICE_ATTR(clock, S_IWUSR | S_IRUGO, show_clock, set_clock); + +static ssize_t show_debug_mask(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t ret = 0; + struct platform_device *pdev = container_of(dev, struct + platform_device, dev); + struct msm_hs_port *msm_uport = get_matching_hs_port(pdev); + + /* This check should not fail */ + if (msm_uport) + ret = snprintf(buf, sizeof(int), "%u\n", + msm_uport->ipc_debug_mask); + return ret; +} + +static ssize_t set_debug_mask(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = container_of(dev, struct + platform_device, dev); + struct msm_hs_port *msm_uport = get_matching_hs_port(pdev); + + /* This check should not fail */ + if (msm_uport) { + msm_uport->ipc_debug_mask = buf[0] - '0'; + if (msm_uport->ipc_debug_mask < FATAL_LEV || + msm_uport->ipc_debug_mask > DBG_LEV) { + /* set to default level */ + msm_uport->ipc_debug_mask = INFO_LEV; + MSM_HS_ERR("Range is 0 to 4;Set to default level 3\n"); + return -EINVAL; + } + } + return count; +} + +static DEVICE_ATTR(debug_mask, S_IWUSR | S_IRUGO, show_debug_mask, + set_debug_mask); + +static inline bool is_use_low_power_wakeup(struct msm_hs_port *msm_uport) +{ + return msm_uport->wakeup.irq > 0; +} + +static void msm_hs_bus_voting(struct msm_hs_port *msm_uport, unsigned int vote) +{ + int ret; + + if (msm_uport->bus_perf_client) { + MSM_HS_DBG("Bus voting:%d\n", vote); + ret = msm_bus_scale_client_update_request( + msm_uport->bus_perf_client, vote); + if (ret) + MSM_HS_ERR("%s(): Failed for Bus voting: %d\n", + __func__, vote); + } +} + +static inline unsigned int msm_hs_read(struct uart_port *uport, + unsigned int index) +{ + return readl_relaxed(uport->membase + index); +} + +static inline void msm_hs_write(struct uart_port *uport, unsigned int index, + unsigned int value) +{ + writel_relaxed(value, uport->membase + index); +} + +static int sps_rx_disconnect(struct sps_pipe *sps_pipe_handler) +{ + struct sps_connect config; + int ret; + + ret = sps_get_config(sps_pipe_handler, &config); + if (ret) { + pr_err("%s: sps_get_config() failed ret %d\n", __func__, ret); + return ret; + } + config.options |= SPS_O_POLL; + ret = sps_set_config(sps_pipe_handler, &config); + if (ret) { + pr_err("%s: sps_set_config() failed ret %d\n", __func__, ret); + return ret; + } + return sps_disconnect(sps_pipe_handler); +} + +static void hex_dump_ipc(struct msm_hs_port *msm_uport, void *ipc_ctx, + char *prefix, char *string, u64 addr, int size) + +{ + char buf[(BUF_DUMP_SIZE * 3) + 2]; + int len = 0; + + if (msm_uport->ipc_debug_mask == FATAL_LEV) + return; + len = min(size, BUF_DUMP_SIZE); + /* + * Print upto 32 data bytes, 32 bytes per line, 1 byte at a time and + * don't include the ASCII text at the end of the buffer. + */ + hex_dump_to_buffer(string, len, 32, 1, buf, sizeof(buf), false); + ipc_log_string(ipc_ctx, "%s[0x%.10x:%d] : %s", prefix, + (unsigned int)addr, size, buf); +} + +/* + * This API read and provides UART Core registers information. +*/ +static void dump_uart_hs_registers(struct msm_hs_port *msm_uport) +{ + struct uart_port *uport = &(msm_uport->uport); + + if (msm_uport->pm_state != MSM_HS_PM_ACTIVE) { + MSM_HS_INFO("%s:Failed clocks are off, resource_count %d", + __func__, atomic_read(&msm_uport->resource_count)); + return; + } + + MSM_HS_DBG( + "MR1:%x MR2:%x TFWR:%x RFWR:%x DMEN:%x IMR:%x MISR:%x NCF_TX:%x\n", + msm_hs_read(uport, UART_DM_MR1), + msm_hs_read(uport, UART_DM_MR2), + msm_hs_read(uport, UART_DM_TFWR), + msm_hs_read(uport, UART_DM_RFWR), + msm_hs_read(uport, UART_DM_DMEN), + msm_hs_read(uport, UART_DM_IMR), + msm_hs_read(uport, UART_DM_MISR), + msm_hs_read(uport, UART_DM_NCF_TX)); + MSM_HS_INFO("SR:%x ISR:%x DMRX:%x RX_SNAP:%x TXFS:%x RXFS:%x\n", + msm_hs_read(uport, UART_DM_SR), + msm_hs_read(uport, UART_DM_ISR), + msm_hs_read(uport, UART_DM_DMRX), + msm_hs_read(uport, UART_DM_RX_TOTAL_SNAP), + msm_hs_read(uport, UART_DM_TXFS), + msm_hs_read(uport, UART_DM_RXFS)); + MSM_HS_DBG("rx.flush:%u\n", msm_uport->rx.flush); +} + +static int msm_serial_loopback_enable_set(void *data, u64 val) +{ + struct msm_hs_port *msm_uport = data; + struct uart_port *uport = &(msm_uport->uport); + unsigned long flags; + int ret = 0; + + msm_hs_resource_vote(msm_uport); + + if (val) { + spin_lock_irqsave(&uport->lock, flags); + ret = msm_hs_read(uport, UART_DM_MR2); + ret |= (UARTDM_MR2_LOOP_MODE_BMSK | + UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK); + msm_hs_write(uport, UART_DM_MR2, ret); + spin_unlock_irqrestore(&uport->lock, flags); + } else { + spin_lock_irqsave(&uport->lock, flags); + ret = msm_hs_read(uport, UART_DM_MR2); + ret &= ~(UARTDM_MR2_LOOP_MODE_BMSK | + UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK); + msm_hs_write(uport, UART_DM_MR2, ret); + spin_unlock_irqrestore(&uport->lock, flags); + } + /* Calling CLOCK API. Hence mb() requires here. */ + mb(); + msm_hs_resource_unvote(msm_uport); + return 0; +} + +static int msm_serial_loopback_enable_get(void *data, u64 *val) +{ + struct msm_hs_port *msm_uport = data; + struct uart_port *uport = &(msm_uport->uport); + unsigned long flags; + int ret = 0; + + msm_hs_resource_vote(msm_uport); + + spin_lock_irqsave(&uport->lock, flags); + ret = msm_hs_read(&msm_uport->uport, UART_DM_MR2); + spin_unlock_irqrestore(&uport->lock, flags); + + msm_hs_resource_unvote(msm_uport); + + *val = (ret & UARTDM_MR2_LOOP_MODE_BMSK) ? 1 : 0; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(loopback_enable_fops, msm_serial_loopback_enable_get, + msm_serial_loopback_enable_set, "%llu\n"); + +/* + * msm_serial_hs debugfs node: <debugfs_root>/msm_serial_hs/loopback.<id> + * writing 1 turns on internal loopback mode in HW. Useful for automation + * test scripts. + * writing 0 disables the internal loopback mode. Default is disabled. + */ +static void msm_serial_debugfs_init(struct msm_hs_port *msm_uport, + int id) +{ + char node_name[15]; + snprintf(node_name, sizeof(node_name), "loopback.%d", id); + msm_uport->loopback_dir = debugfs_create_file(node_name, + S_IRUGO | S_IWUSR, + debug_base, + msm_uport, + &loopback_enable_fops); + + if (IS_ERR_OR_NULL(msm_uport->loopback_dir)) + MSM_HS_ERR("%s(): Cannot create loopback.%d debug entry", + __func__, id); +} + +static int msm_hs_remove(struct platform_device *pdev) +{ + + struct msm_hs_port *msm_uport; + struct device *dev; + + if (pdev->id < 0 || pdev->id >= UARTDM_NR) { + pr_err("Invalid plaform device ID = %d\n", pdev->id); + return -EINVAL; + } + + msm_uport = get_matching_hs_port(pdev); + if (!msm_uport) + return -EINVAL; + + dev = msm_uport->uport.dev; + sysfs_remove_file(&pdev->dev.kobj, &dev_attr_clock.attr); + sysfs_remove_file(&pdev->dev.kobj, &dev_attr_debug_mask.attr); + debugfs_remove(msm_uport->loopback_dir); + + dma_free_coherent(msm_uport->uport.dev, + UART_DMA_DESC_NR * UARTDM_RX_BUF_SIZE, + msm_uport->rx.buffer, msm_uport->rx.rbuffer); + + msm_uport->rx.buffer = NULL; + msm_uport->rx.rbuffer = 0; + + destroy_workqueue(msm_uport->hsuart_wq); + mutex_destroy(&msm_uport->mtx); + + uart_remove_one_port(&msm_hs_driver, &msm_uport->uport); + clk_put(msm_uport->clk); + if (msm_uport->pclk) + clk_put(msm_uport->pclk); + + iounmap(msm_uport->uport.membase); + + return 0; +} + + +/* Connect a UART peripheral's SPS endpoint(consumer endpoint) + * + * Also registers a SPS callback function for the consumer + * process with the SPS driver + * + * @uport - Pointer to uart uport structure + * + * @return - 0 if successful else negative value. + * + */ + +static int msm_hs_spsconnect_tx(struct msm_hs_port *msm_uport) +{ + int ret; + struct uart_port *uport = &msm_uport->uport; + struct msm_hs_tx *tx = &msm_uport->tx; + struct sps_pipe *sps_pipe_handle = tx->cons.pipe_handle; + struct sps_connect *sps_config = &tx->cons.config; + struct sps_register_event *sps_event = &tx->cons.event; + unsigned long flags; + unsigned int data; + + if (tx->flush != FLUSH_SHUTDOWN) { + MSM_HS_ERR("%s:Invalid flush state:%d\n", __func__, tx->flush); + return 0; + } + + /* Establish connection between peripheral and memory endpoint */ + ret = sps_connect(sps_pipe_handle, sps_config); + if (ret) { + MSM_HS_ERR("msm_serial_hs: sps_connect() failed for tx!!\n" + "pipe_handle=0x%p ret=%d", sps_pipe_handle, ret); + return ret; + } + /* Register callback event for EOT (End of transfer) event. */ + ret = sps_register_event(sps_pipe_handle, sps_event); + if (ret) { + MSM_HS_ERR("msm_serial_hs: sps_connect() failed for tx!!\n" + "pipe_handle=0x%p ret=%d", sps_pipe_handle, ret); + goto reg_event_err; + } + + spin_lock_irqsave(&(msm_uport->uport.lock), flags); + msm_uport->tx.flush = FLUSH_STOP; + spin_unlock_irqrestore(&(msm_uport->uport.lock), flags); + + data = msm_hs_read(uport, UART_DM_DMEN); + /* Enable UARTDM Tx BAM Interface */ + data |= UARTDM_TX_BAM_ENABLE_BMSK; + msm_hs_write(uport, UART_DM_DMEN, data); + + msm_hs_write(uport, UART_DM_CR, RESET_TX); + msm_hs_write(uport, UART_DM_CR, START_TX_BAM_IFC); + msm_hs_write(uport, UART_DM_CR, UARTDM_CR_TX_EN_BMSK); + + MSM_HS_DBG("%s(): TX Connect", __func__); + return 0; + +reg_event_err: + sps_disconnect(sps_pipe_handle); + return ret; +} + +/* Connect a UART peripheral's SPS endpoint(producer endpoint) + * + * Also registers a SPS callback function for the producer + * process with the SPS driver + * + * @uport - Pointer to uart uport structure + * + * @return - 0 if successful else negative value. + * + */ + +static int msm_hs_spsconnect_rx(struct uart_port *uport) +{ + int ret; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + struct msm_hs_rx *rx = &msm_uport->rx; + struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle; + struct sps_connect *sps_config = &rx->prod.config; + struct sps_register_event *sps_event = &rx->prod.event; + unsigned long flags; + + if (msm_uport->rx.pending_flag) { + MSM_HS_WARN("%s(): Buffers may be pending 0x%lx", + __func__, msm_uport->rx.pending_flag); + } + + /* Establish connection between peripheral and memory endpoint */ + ret = sps_connect(sps_pipe_handle, sps_config); + if (ret) { + MSM_HS_ERR("msm_serial_hs: sps_connect() failed for rx!!\n" + "pipe_handle=0x%p ret=%d", sps_pipe_handle, ret); + return ret; + } + /* Register callback event for DESC_DONE event. */ + ret = sps_register_event(sps_pipe_handle, sps_event); + if (ret) { + MSM_HS_ERR("msm_serial_hs: sps_connect() failed for rx!!\n" + "pipe_handle=0x%p ret=%d", sps_pipe_handle, ret); + goto reg_event_err; + } + spin_lock_irqsave(&uport->lock, flags); + msm_uport->rx.queued_flag = 0; + msm_uport->rx.pending_flag = 0; + msm_uport->rx.rx_inx = 0; + msm_uport->rx.flush = FLUSH_STOP; + spin_unlock_irqrestore(&uport->lock, flags); + MSM_HS_DBG("%s(): RX Connect\n", __func__); + return 0; + +reg_event_err: + sps_disconnect(sps_pipe_handle); + return ret; +} + +/* + * programs the UARTDM_CSR register with correct bit rates + * + * Interrupts should be disabled before we are called, as + * we modify Set Baud rate + * Set receive stale interrupt level, dependant on Bit Rate + * Goal is to have around 8 ms before indicate stale. + * roundup (((Bit Rate * .008) / 10) + 1 + */ +static void msm_hs_set_bps_locked(struct uart_port *uport, + unsigned int bps) +{ + unsigned long rxstale; + unsigned long data; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + switch (bps) { + case 300: + msm_hs_write(uport, UART_DM_CSR, 0x00); + rxstale = 1; + break; + case 600: + msm_hs_write(uport, UART_DM_CSR, 0x11); + rxstale = 1; + break; + case 1200: + msm_hs_write(uport, UART_DM_CSR, 0x22); + rxstale = 1; + break; + case 2400: + msm_hs_write(uport, UART_DM_CSR, 0x33); + rxstale = 1; + break; + case 4800: + msm_hs_write(uport, UART_DM_CSR, 0x44); + rxstale = 1; + break; + case 9600: + msm_hs_write(uport, UART_DM_CSR, 0x55); + rxstale = 2; + break; + case 14400: + msm_hs_write(uport, UART_DM_CSR, 0x66); + rxstale = 3; + break; + case 19200: + msm_hs_write(uport, UART_DM_CSR, 0x77); + rxstale = 4; + break; + case 28800: + msm_hs_write(uport, UART_DM_CSR, 0x88); + rxstale = 6; + break; + case 38400: + msm_hs_write(uport, UART_DM_CSR, 0x99); + rxstale = 8; + break; + case 57600: + msm_hs_write(uport, UART_DM_CSR, 0xaa); + rxstale = 16; + break; + case 76800: + msm_hs_write(uport, UART_DM_CSR, 0xbb); + rxstale = 16; + break; + case 115200: + msm_hs_write(uport, UART_DM_CSR, 0xcc); + rxstale = 31; + break; + case 230400: + msm_hs_write(uport, UART_DM_CSR, 0xee); + rxstale = 31; + break; + case 460800: + msm_hs_write(uport, UART_DM_CSR, 0xff); + rxstale = 31; + break; + case 4000000: + case 3686400: + case 3200000: + case 3500000: + case 3000000: + case 2500000: + case 2000000: + case 1500000: + case 1152000: + case 1000000: + case 921600: + msm_hs_write(uport, UART_DM_CSR, 0xff); + rxstale = 31; + break; + default: + msm_hs_write(uport, UART_DM_CSR, 0xff); + /* default to 9600 */ + bps = 9600; + rxstale = 2; + break; + } + /* + * uart baud rate depends on CSR and MND Values + * we are updating CSR before and then calling + * clk_set_rate which updates MND Values. Hence + * dsb requires here. + */ + mb(); + if (bps > 460800) { + uport->uartclk = bps * 16; + /* BLSP based UART supports maximum clock frequency + * of 63.16 Mhz. With this (63.16 Mhz) clock frequency + * UART can support baud rate of 3.94 Mbps which is + * equivalent to 4 Mbps. + * UART hardware is robust enough to handle this + * deviation to achieve baud rate ~4 Mbps. + */ + if (bps == 4000000) + uport->uartclk = BLSP_UART_CLK_FMAX; + } else { + uport->uartclk = 7372800; + } + + if (clk_set_rate(msm_uport->clk, uport->uartclk)) { + MSM_HS_WARN("Error setting clock rate on UART\n"); + WARN_ON(1); + } + + data = rxstale & UARTDM_IPR_STALE_LSB_BMSK; + data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2); + + msm_hs_write(uport, UART_DM_IPR, data); + /* + * It is suggested to do reset of transmitter and receiver after + * changing any protocol configuration. Here Baud rate and stale + * timeout are getting updated. Hence reset transmitter and receiver. + */ + msm_hs_write(uport, UART_DM_CR, RESET_TX); + msm_hs_write(uport, UART_DM_CR, RESET_RX); +} + + +static void msm_hs_set_std_bps_locked(struct uart_port *uport, + unsigned int bps) +{ + unsigned long rxstale; + unsigned long data; + + switch (bps) { + case 9600: + msm_hs_write(uport, UART_DM_CSR, 0x99); + rxstale = 2; + break; + case 14400: + msm_hs_write(uport, UART_DM_CSR, 0xaa); + rxstale = 3; + break; + case 19200: + msm_hs_write(uport, UART_DM_CSR, 0xbb); + rxstale = 4; + break; + case 28800: + msm_hs_write(uport, UART_DM_CSR, 0xcc); + rxstale = 6; + break; + case 38400: + msm_hs_write(uport, UART_DM_CSR, 0xdd); + rxstale = 8; + break; + case 57600: + msm_hs_write(uport, UART_DM_CSR, 0xee); + rxstale = 16; + break; + case 115200: + msm_hs_write(uport, UART_DM_CSR, 0xff); + rxstale = 31; + break; + default: + msm_hs_write(uport, UART_DM_CSR, 0x99); + /* default to 9600 */ + bps = 9600; + rxstale = 2; + break; + } + + data = rxstale & UARTDM_IPR_STALE_LSB_BMSK; + data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2); + + msm_hs_write(uport, UART_DM_IPR, data); +} + +static void msm_hs_enable_flow_control(struct uart_port *uport, bool override) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + unsigned int data; + + if (msm_uport->flow_control || override) { + /* Enable RFR line */ + msm_hs_write(uport, UART_DM_CR, RFR_LOW); + /* Enable auto RFR */ + data = msm_hs_read(uport, UART_DM_MR1); + data |= UARTDM_MR1_RX_RDY_CTL_BMSK; + msm_hs_write(uport, UART_DM_MR1, data); + /* Ensure register IO completion */ + mb(); + } +} + +static void msm_hs_disable_flow_control(struct uart_port *uport, bool override) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + unsigned int data; + + /* + * Clear the Rx Ready Ctl bit - This ensures that + * flow control lines stop the other side from sending + * data while we change the parameters + */ + + if (msm_uport->flow_control || override) { + data = msm_hs_read(uport, UART_DM_MR1); + /* disable auto ready-for-receiving */ + data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK; + msm_hs_write(uport, UART_DM_MR1, data); + /* Disable RFR line */ + msm_hs_write(uport, UART_DM_CR, RFR_HIGH); + /* Ensure register IO completion */ + mb(); + } +} + +/* + * termios : new ktermios + * oldtermios: old ktermios previous setting + * + * Configure the serial port + */ +static void msm_hs_set_termios(struct uart_port *uport, + struct ktermios *termios, + struct ktermios *oldtermios) +{ + unsigned int bps; + unsigned long data; + unsigned int c_cflag = termios->c_cflag; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + /** + * set_termios can be invoked from the framework when + * the clocks are off and the client has not had a chance + * to turn them on. Make sure that they are on + */ + msm_hs_resource_vote(msm_uport); + mutex_lock(&msm_uport->mtx); + msm_hs_write(uport, UART_DM_IMR, 0); + + msm_hs_disable_flow_control(uport, true); + + /* + * Disable Rx channel of UARTDM + * DMA Rx Stall happens if enqueue and flush of Rx command happens + * concurrently. Hence before changing the baud rate/protocol + * configuration and sending flush command to ADM, disable the Rx + * channel of UARTDM. + * Note: should not reset the receiver here immediately as it is not + * suggested to do disable/reset or reset/disable at the same time. + */ + data = msm_hs_read(uport, UART_DM_DMEN); + /* Disable UARTDM RX BAM Interface */ + data &= ~UARTDM_RX_BAM_ENABLE_BMSK; + msm_hs_write(uport, UART_DM_DMEN, data); + + /* + * Reset RX and TX. + * Resetting the RX enables it, therefore we must reset and disable. + */ + msm_hs_write(uport, UART_DM_CR, RESET_RX); + msm_hs_write(uport, UART_DM_CR, UARTDM_CR_RX_DISABLE_BMSK); + msm_hs_write(uport, UART_DM_CR, RESET_TX); + + /* 300 is the minimum baud support by the driver */ + bps = uart_get_baud_rate(uport, termios, oldtermios, 200, 4000000); + + /* Temporary remapping 200 BAUD to 3.2 mbps */ + if (bps == 200) + bps = 3200000; + + uport->uartclk = clk_get_rate(msm_uport->clk); + if (!uport->uartclk) + msm_hs_set_std_bps_locked(uport, bps); + else + msm_hs_set_bps_locked(uport, bps); + + data = msm_hs_read(uport, UART_DM_MR2); + data &= ~UARTDM_MR2_PARITY_MODE_BMSK; + /* set parity */ + if (c_cflag & PARENB) { + if (c_cflag & PARODD) + data |= ODD_PARITY; + else if (c_cflag & CMSPAR) + data |= SPACE_PARITY; + else + data |= EVEN_PARITY; + } + + /* Set bits per char */ + data &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK; + + switch (c_cflag & CSIZE) { + case CS5: + data |= FIVE_BPC; + break; + case CS6: + data |= SIX_BPC; + break; + case CS7: + data |= SEVEN_BPC; + break; + default: + data |= EIGHT_BPC; + break; + } + uport->status &= ~(UPSTAT_AUTOCTS); + /* stop bits */ + if (c_cflag & CSTOPB) { + data |= STOP_BIT_TWO; + } else { + /* otherwise 1 stop bit */ + data |= STOP_BIT_ONE; + } + data |= UARTDM_MR2_ERROR_MODE_BMSK; + /* write parity/bits per char/stop bit configuration */ + msm_hs_write(uport, UART_DM_MR2, data); + + uport->ignore_status_mask = termios->c_iflag & INPCK; + uport->ignore_status_mask |= termios->c_iflag & IGNPAR; + uport->ignore_status_mask |= termios->c_iflag & IGNBRK; + + uport->read_status_mask = (termios->c_cflag & CREAD); + + /* Set Transmit software time out */ + uart_update_timeout(uport, c_cflag, bps); + + /* Enable UARTDM Rx BAM Interface */ + data = msm_hs_read(uport, UART_DM_DMEN); + data |= UARTDM_RX_BAM_ENABLE_BMSK; + msm_hs_write(uport, UART_DM_DMEN, data); + msm_hs_write(uport, UART_DM_CR, UARTDM_CR_RX_EN_BMSK); + /* Issue TX,RX BAM Start IFC command */ + msm_hs_write(uport, UART_DM_CR, START_TX_BAM_IFC); + msm_hs_write(uport, UART_DM_CR, START_RX_BAM_IFC); + /* Ensure Register Writes Complete */ + mb(); + + /* Configure HW flow control + * UART Core would see status of CTS line when it is sending data + * to remote uart to confirm that it can receive or not. + * UART Core would trigger RFR if it is not having any space with + * RX FIFO. + */ + /* Pulling RFR line high */ + msm_hs_write(uport, UART_DM_CR, RFR_LOW); + data = msm_hs_read(uport, UART_DM_MR1); + data &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK); + if (c_cflag & CRTSCTS) { + data |= UARTDM_MR1_CTS_CTL_BMSK; + data |= UARTDM_MR1_RX_RDY_CTL_BMSK; + uport->status |= UPSTAT_AUTOCTS; + msm_uport->flow_control = true; + } + msm_hs_write(uport, UART_DM_MR1, data); + MSM_HS_INFO("%s: Cflags 0x%x Baud %u\n", __func__, c_cflag, bps); + + mutex_unlock(&msm_uport->mtx); + + msm_hs_resource_unvote(msm_uport); +} + +/* + * Standard API, Transmitter + * Any character in the transmit shift register is sent + */ +unsigned int msm_hs_tx_empty(struct uart_port *uport) +{ + unsigned int data; + unsigned int isr; + unsigned int ret = 0; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + msm_hs_resource_vote(msm_uport); + data = msm_hs_read(uport, UART_DM_SR); + isr = msm_hs_read(uport, UART_DM_ISR); + msm_hs_resource_unvote(msm_uport); + MSM_HS_INFO("%s(): SR:0x%x ISR:0x%x ", __func__, data, isr); + + if (data & UARTDM_SR_TXEMT_BMSK) { + ret = TIOCSER_TEMT; + } else + /* + * Add an extra sleep here because sometimes the framework's + * delay (based on baud rate) isn't good enough. + * Note that this won't happen during every port close, only + * on select occassions when the userspace does back to back + * write() and close(). + */ + usleep_range(5000, 7000); + + return ret; +} +EXPORT_SYMBOL(msm_hs_tx_empty); + +/* + * Standard API, Stop transmitter. + * Any character in the transmit shift register is sent as + * well as the current data mover transfer . + */ +static void msm_hs_stop_tx_locked(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + struct msm_hs_tx *tx = &msm_uport->tx; + + tx->flush = FLUSH_STOP; +} + +static int disconnect_rx_endpoint(struct msm_hs_port *msm_uport) +{ + struct msm_hs_rx *rx = &msm_uport->rx; + struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle; + int ret = 0; + + ret = sps_rx_disconnect(sps_pipe_handle); + if (ret) + MSM_HS_ERR("%s(): sps_disconnect failed\n", __func__); + + if (msm_uport->rx.pending_flag) + MSM_HS_WARN("%s(): Buffers may be pending 0x%lx", + __func__, msm_uport->rx.pending_flag); + MSM_HS_DBG("%s(): clearing desc usage flag", __func__); + msm_uport->rx.queued_flag = 0; + msm_uport->rx.pending_flag = 0; + msm_uport->rx.rx_inx = 0; + + msm_uport->rx.flush = FLUSH_SHUTDOWN; + MSM_HS_DBG("%s: Calling Completion\n", __func__); + wake_up(&msm_uport->bam_disconnect_wait); + MSM_HS_DBG("%s: Done Completion\n", __func__); + wake_up(&msm_uport->rx.wait); + return ret; +} + +static int sps_tx_disconnect(struct msm_hs_port *msm_uport) +{ + struct uart_port *uport = &msm_uport->uport; + struct msm_hs_tx *tx = &msm_uport->tx; + struct sps_pipe *tx_pipe = tx->cons.pipe_handle; + unsigned long flags; + int ret = 0; + + if (msm_uport->tx.flush == FLUSH_SHUTDOWN) { + MSM_HS_DBG("%s(): pipe already disonnected", __func__); + return ret; + } + + ret = sps_disconnect(tx_pipe); + + if (ret) { + MSM_HS_ERR("%s(): sps_disconnect failed %d", __func__, ret); + return ret; + } + + spin_lock_irqsave(&uport->lock, flags); + msm_uport->tx.flush = FLUSH_SHUTDOWN; + spin_unlock_irqrestore(&uport->lock, flags); + + MSM_HS_DBG("%s(): TX Disconnect", __func__); + return ret; +} + +static void msm_hs_disable_rx(struct uart_port *uport) +{ + unsigned int data; + + data = msm_hs_read(uport, UART_DM_DMEN); + data &= ~UARTDM_RX_BAM_ENABLE_BMSK; + msm_hs_write(uport, UART_DM_DMEN, data); +} + +/* + * Standard API, Stop receiver as soon as possible. + * + * Function immediately terminates the operation of the + * channel receiver and any incoming characters are lost. None + * of the receiver status bits are affected by this command and + * characters that are already in the receive FIFO there. + */ +static void msm_hs_stop_rx_locked(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + if (msm_uport->pm_state != MSM_HS_PM_ACTIVE) { + MSM_HS_WARN("%s(): Clocks are off, Rx still active\n", + __func__); + return; + } else + msm_hs_disable_rx(uport); + + if (msm_uport->rx.flush == FLUSH_NONE) + msm_uport->rx.flush = FLUSH_STOP; +} + +static void msm_hs_disconnect_rx(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + struct msm_hs_rx *rx = &msm_uport->rx; + struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle; + u32 prod_empty = 0; + + msm_hs_disable_rx(uport); + /* Disconnect the BAM RX pipe */ + if (msm_uport->rx.flush == FLUSH_NONE) + msm_uport->rx.flush = FLUSH_STOP; + + if (!sps_is_pipe_empty(sps_pipe_handle, &prod_empty)) { + if (prod_empty == false) + MSM_HS_WARN("%s():Pipe Not Empty, prod=%d, flush=%d\n", + __func__, prod_empty, msm_uport->rx.flush); + } + disconnect_rx_endpoint(msm_uport); + MSM_HS_DBG("%s(): rx->flush %d", __func__, msm_uport->rx.flush); +} + +/* Tx timeout callback function */ +void tx_timeout_handler(unsigned long arg) +{ + struct msm_hs_port *msm_uport = (struct msm_hs_port *) arg; + struct uart_port *uport = &msm_uport->uport; + int isr; + + if (msm_uport->pm_state != MSM_HS_PM_ACTIVE) { + MSM_HS_WARN("%s(): clocks are off", __func__); + return; + } + + isr = msm_hs_read(uport, UART_DM_ISR); + if (UARTDM_ISR_CURRENT_CTS_BMSK & isr) + MSM_HS_WARN("%s(): CTS Disabled, ISR 0x%x", __func__, isr); + dump_uart_hs_registers(msm_uport); + /* Stop further logging */ + MSM_HS_ERR("%s(): Stop IPC logging\n", __func__); +} + +/* Transmit the next chunk of data */ +static void msm_hs_submit_tx_locked(struct uart_port *uport) +{ + int left; + int tx_count; + int aligned_tx_count; + dma_addr_t src_addr; + dma_addr_t aligned_src_addr; + u32 flags = SPS_IOVEC_FLAG_EOT | SPS_IOVEC_FLAG_INT; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + struct msm_hs_tx *tx = &msm_uport->tx; + struct circ_buf *tx_buf = &msm_uport->uport.state->xmit; + struct sps_pipe *sps_pipe_handle; + int ret; + + if (uart_circ_empty(tx_buf) || uport->state->port.tty->stopped) { + tx->dma_in_flight = false; + msm_hs_stop_tx_locked(uport); + return; + } + + tx_count = uart_circ_chars_pending(tx_buf); + + if (UARTDM_TX_BUF_SIZE < tx_count) + tx_count = UARTDM_TX_BUF_SIZE; + + left = UART_XMIT_SIZE - tx_buf->tail; + + if (tx_count > left) + tx_count = left; + + src_addr = tx->dma_base + tx_buf->tail; + /* Mask the src_addr to align on a cache + * and add those bytes to tx_count */ + aligned_src_addr = src_addr & ~(dma_get_cache_alignment() - 1); + aligned_tx_count = tx_count + src_addr - aligned_src_addr; + + dma_sync_single_for_device(uport->dev, aligned_src_addr, + aligned_tx_count, DMA_TO_DEVICE); + + tx->tx_count = tx_count; + + hex_dump_ipc(msm_uport, tx->ipc_tx_ctxt, "Tx", + &tx_buf->buf[tx_buf->tail], (u64)src_addr, tx_count); + sps_pipe_handle = tx->cons.pipe_handle; + + /* Set 1 second timeout */ + mod_timer(&tx->tx_timeout_timer, + jiffies + msecs_to_jiffies(MSEC_PER_SEC)); + /* Queue transfer request to SPS */ + ret = sps_transfer_one(sps_pipe_handle, src_addr, tx_count, + msm_uport, flags); + + MSM_HS_DBG("%s:Enqueue Tx Cmd, ret %d\n", __func__, ret); +} + +/* This function queues the rx descriptor for BAM transfer */ +static void msm_hs_post_rx_desc(struct msm_hs_port *msm_uport, int inx) +{ + u32 flags = SPS_IOVEC_FLAG_INT; + struct msm_hs_rx *rx = &msm_uport->rx; + int ret; + + phys_addr_t rbuff_addr = rx->rbuffer + (UARTDM_RX_BUF_SIZE * inx); + u8 *virt_addr = rx->buffer + (UARTDM_RX_BUF_SIZE * inx); + + MSM_HS_DBG("%s: %d:Queue desc %d, 0x%llx, base 0x%llx virtaddr %p", + __func__, msm_uport->uport.line, inx, + (u64)rbuff_addr, (u64)rx->rbuffer, virt_addr); + + rx->iovec[inx].size = 0; + ret = sps_transfer_one(rx->prod.pipe_handle, rbuff_addr, + UARTDM_RX_BUF_SIZE, msm_uport, flags); + + if (ret) + MSM_HS_ERR("Error processing descriptor %d", ret); + return; +} + +/* Update the rx descriptor index to specify the next one to be processed */ +static void msm_hs_mark_next(struct msm_hs_port *msm_uport, int inx) +{ + struct msm_hs_rx *rx = &msm_uport->rx; + int prev; + + inx %= UART_DMA_DESC_NR; + MSM_HS_DBG("%s(): inx %d, pending 0x%lx", __func__, inx, + rx->pending_flag); + + if (!inx) + prev = UART_DMA_DESC_NR - 1; + else + prev = inx - 1; + + if (!test_bit(prev, &rx->pending_flag)) + msm_uport->rx.rx_inx = inx; + MSM_HS_DBG("%s(): prev %d pending flag 0x%lx, next %d", __func__, + prev, rx->pending_flag, msm_uport->rx.rx_inx); + return; +} + +/* + * Queue the rx descriptor that has just been processed or + * all of them if queueing for the first time + */ +static void msm_hs_queue_rx_desc(struct msm_hs_port *msm_uport) +{ + struct msm_hs_rx *rx = &msm_uport->rx; + int i, flag = 0; + + /* At first, queue all, if not, queue only one */ + if (rx->queued_flag || rx->pending_flag) { + if (!test_bit(rx->rx_inx, &rx->queued_flag) && + !test_bit(rx->rx_inx, &rx->pending_flag)) { + msm_hs_post_rx_desc(msm_uport, rx->rx_inx); + set_bit(rx->rx_inx, &rx->queued_flag); + MSM_HS_DBG("%s(): Set Queued Bit %d", + __func__, rx->rx_inx); + } else + MSM_HS_ERR("%s(): rx_inx pending or queued", __func__); + return; + } + + for (i = 0; i < UART_DMA_DESC_NR; i++) { + if (!test_bit(i, &rx->queued_flag) && + !test_bit(i, &rx->pending_flag)) { + MSM_HS_DBG("%s(): Calling post rx %d", __func__, i); + msm_hs_post_rx_desc(msm_uport, i); + set_bit(i, &rx->queued_flag); + flag = 1; + } + } + + if (!flag) + MSM_HS_ERR("%s(): error queueing descriptor", __func__); +} + +/* Start to receive the next chunk of data */ +static void msm_hs_start_rx_locked(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + struct msm_hs_rx *rx = &msm_uport->rx; + unsigned int buffer_pending = msm_uport->rx.buffer_pending; + unsigned int data; + + if (msm_uport->pm_state != MSM_HS_PM_ACTIVE) { + MSM_HS_WARN("%s(): Clocks are off\n", __func__); + return; + } + if (rx->pending_flag) { + MSM_HS_INFO("%s: Rx Cmd got executed, wait for rx_tlet\n", + __func__); + rx->flush = FLUSH_IGNORE; + return; + } + if (buffer_pending) + MSM_HS_ERR("Error: rx started in buffer state =%x", + buffer_pending); + + msm_hs_write(uport, UART_DM_CR, RESET_STALE_INT); + msm_hs_write(uport, UART_DM_DMRX, UARTDM_RX_BUF_SIZE); + msm_hs_write(uport, UART_DM_CR, STALE_EVENT_ENABLE); + /* + * Enable UARTDM Rx Interface as previously it has been + * disable in set_termios before configuring baud rate. + */ + data = msm_hs_read(uport, UART_DM_DMEN); + /* Enable UARTDM Rx BAM Interface */ + data |= UARTDM_RX_BAM_ENABLE_BMSK; + + msm_hs_write(uport, UART_DM_DMEN, data); + msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg); + /* Calling next DMOV API. Hence mb() here. */ + mb(); + + /* + * RX-transfer will be automatically re-activated + * after last data of previous transfer was read. + */ + data = (RX_STALE_AUTO_RE_EN | RX_TRANS_AUTO_RE_ACTIVATE | + RX_DMRX_CYCLIC_EN); + msm_hs_write(uport, UART_DM_RX_TRANS_CTRL, data); + /* Issue RX BAM Start IFC command */ + msm_hs_write(uport, UART_DM_CR, START_RX_BAM_IFC); + /* Ensure register IO completion */ + mb(); + + msm_uport->rx.flush = FLUSH_NONE; + msm_uport->rx_bam_inprogress = true; + msm_hs_queue_rx_desc(msm_uport); + msm_uport->rx_bam_inprogress = false; + wake_up(&msm_uport->rx.wait); + MSM_HS_DBG("%s:Enqueue Rx Cmd\n", __func__); +} + +static void flip_insert_work(struct work_struct *work) +{ + unsigned long flags; + int retval; + struct msm_hs_port *msm_uport = + container_of(work, struct msm_hs_port, + rx.flip_insert_work.work); + struct tty_struct *tty = msm_uport->uport.state->port.tty; + + spin_lock_irqsave(&msm_uport->uport.lock, flags); + if (!tty || msm_uport->rx.flush == FLUSH_SHUTDOWN) { + dev_err(msm_uport->uport.dev, + "%s:Invalid driver state flush %d\n", + __func__, msm_uport->rx.flush); + MSM_HS_ERR("%s:Invalid driver state flush %d\n", + __func__, msm_uport->rx.flush); + spin_unlock_irqrestore(&msm_uport->uport.lock, flags); + return; + } + + if (msm_uport->rx.buffer_pending == NONE_PENDING) { + MSM_HS_ERR("Error: No buffer pending in %s", __func__); + spin_unlock_irqrestore(&msm_uport->uport.lock, flags); + return; + } + if (msm_uport->rx.buffer_pending & FIFO_OVERRUN) { + retval = tty_insert_flip_char(tty->port, 0, TTY_OVERRUN); + if (retval) + msm_uport->rx.buffer_pending &= ~FIFO_OVERRUN; + } + if (msm_uport->rx.buffer_pending & PARITY_ERROR) { + retval = tty_insert_flip_char(tty->port, 0, TTY_PARITY); + if (retval) + msm_uport->rx.buffer_pending &= ~PARITY_ERROR; + } + if (msm_uport->rx.buffer_pending & CHARS_NORMAL) { + int rx_count, rx_offset; + rx_count = (msm_uport->rx.buffer_pending & 0xFFFF0000) >> 16; + rx_offset = (msm_uport->rx.buffer_pending & 0xFFD0) >> 5; + retval = tty_insert_flip_string(tty->port, + msm_uport->rx.buffer + + (msm_uport->rx.rx_inx * UARTDM_RX_BUF_SIZE) + + rx_offset, rx_count); + msm_uport->rx.buffer_pending &= (FIFO_OVERRUN | + PARITY_ERROR); + if (retval != rx_count) + msm_uport->rx.buffer_pending |= CHARS_NORMAL | + retval << 8 | (rx_count - retval) << 16; + } + if (msm_uport->rx.buffer_pending) { + schedule_delayed_work(&msm_uport->rx.flip_insert_work, + msecs_to_jiffies(RETRY_TIMEOUT)); + } else if (msm_uport->rx.flush <= FLUSH_IGNORE) { + MSM_HS_WARN("Pending buffers cleared, restarting"); + clear_bit(msm_uport->rx.rx_inx, + &msm_uport->rx.pending_flag); + msm_hs_start_rx_locked(&msm_uport->uport); + msm_hs_mark_next(msm_uport, msm_uport->rx.rx_inx+1); + } + spin_unlock_irqrestore(&msm_uport->uport.lock, flags); + tty_flip_buffer_push(tty->port); +} + +static void msm_serial_hs_rx_work(struct kthread_work *work) +{ + int retval; + int rx_count = 0; + unsigned long status; + unsigned long flags; + unsigned int error_f = 0; + struct uart_port *uport; + struct msm_hs_port *msm_uport; + unsigned int flush = FLUSH_DATA_INVALID; + struct tty_struct *tty; + struct sps_event_notify *notify; + struct msm_hs_rx *rx; + struct sps_pipe *sps_pipe_handle; + struct platform_device *pdev; + const struct msm_serial_hs_platform_data *pdata; + + msm_uport = container_of((struct kthread_work *) work, + struct msm_hs_port, rx.kwork); + msm_hs_resource_vote(msm_uport); + uport = &msm_uport->uport; + tty = uport->state->port.tty; + notify = &msm_uport->notify; + rx = &msm_uport->rx; + pdev = to_platform_device(uport->dev); + pdata = pdev->dev.platform_data; + + spin_lock_irqsave(&uport->lock, flags); + + if (!tty || rx->flush == FLUSH_SHUTDOWN) { + dev_err(uport->dev, "%s:Invalid driver state flush %d\n", + __func__, rx->flush); + MSM_HS_ERR("%s:Invalid driver state flush %d\n", + __func__, rx->flush); + spin_unlock_irqrestore(&uport->lock, flags); + msm_hs_resource_unvote(msm_uport); + return; + } + + /* + * Process all pending descs or if nothing is + * queued - called from termios + */ + while (!rx->buffer_pending && + (rx->pending_flag || !rx->queued_flag)) { + MSM_HS_DBG("%s(): Loop P 0x%lx Q 0x%lx", __func__, + rx->pending_flag, rx->queued_flag); + + status = msm_hs_read(uport, UART_DM_SR); + + MSM_HS_DBG("In %s\n", __func__); + + /* overflow is not connect to data in a FIFO */ + if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) && + (uport->read_status_mask & CREAD))) { + retval = tty_insert_flip_char(tty->port, + 0, TTY_OVERRUN); + MSM_HS_WARN("%s(): RX Buffer Overrun Detected\n", + __func__); + if (!retval) + msm_uport->rx.buffer_pending |= TTY_OVERRUN; + uport->icount.buf_overrun++; + error_f = 1; + } + + if (!(uport->ignore_status_mask & INPCK)) + status = status & ~(UARTDM_SR_PAR_FRAME_BMSK); + + if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) { + /* Can not tell diff between parity & frame error */ + MSM_HS_WARN("msm_serial_hs: parity error\n"); + uport->icount.parity++; + error_f = 1; + if (!(uport->ignore_status_mask & IGNPAR)) { + retval = tty_insert_flip_char(tty->port, + 0, TTY_PARITY); + if (!retval) + msm_uport->rx.buffer_pending + |= TTY_PARITY; + } + } + + if (unlikely(status & UARTDM_SR_RX_BREAK_BMSK)) { + MSM_HS_DBG("msm_serial_hs: Rx break\n"); + uport->icount.brk++; + error_f = 1; + if (!(uport->ignore_status_mask & IGNBRK)) { + retval = tty_insert_flip_char(tty->port, + 0, TTY_BREAK); + if (!retval) + msm_uport->rx.buffer_pending + |= TTY_BREAK; + } + } + + if (error_f) + msm_hs_write(uport, UART_DM_CR, RESET_ERROR_STATUS); + flush = msm_uport->rx.flush; + if (flush == FLUSH_IGNORE) + if (!msm_uport->rx.buffer_pending) { + MSM_HS_DBG("%s: calling start_rx_locked\n", + __func__); + msm_hs_start_rx_locked(uport); + } + if (flush >= FLUSH_DATA_INVALID) + goto out; + + rx_count = msm_uport->rx.iovec[msm_uport->rx.rx_inx].size; + hex_dump_ipc(msm_uport, rx->ipc_rx_ctxt, "Rx", + (msm_uport->rx.buffer + + (msm_uport->rx.rx_inx * UARTDM_RX_BUF_SIZE)), + msm_uport->rx.iovec[msm_uport->rx.rx_inx].addr, + rx_count); + + /* + * We are in a spin locked context, spin lock taken at + * other places where these flags are updated + */ + if (0 != (uport->read_status_mask & CREAD)) { + if (!test_bit(msm_uport->rx.rx_inx, + &msm_uport->rx.pending_flag) && + !test_bit(msm_uport->rx.rx_inx, + &msm_uport->rx.queued_flag)) + MSM_HS_ERR("%s: RX INX not set", __func__); + else if (test_bit(msm_uport->rx.rx_inx, + &msm_uport->rx.pending_flag) && + !test_bit(msm_uport->rx.rx_inx, + &msm_uport->rx.queued_flag)) { + MSM_HS_DBG("%s(): Clear Pending Bit %d", + __func__, msm_uport->rx.rx_inx); + + retval = tty_insert_flip_string(tty->port, + msm_uport->rx.buffer + + (msm_uport->rx.rx_inx * + UARTDM_RX_BUF_SIZE), + rx_count); + + if (retval != rx_count) { + MSM_HS_INFO("%s(): ret %d rx_count %d", + __func__, retval, rx_count); + msm_uport->rx.buffer_pending |= + CHARS_NORMAL | retval << 5 | + (rx_count - retval) << 16; + } + } else + MSM_HS_ERR("%s: Error in inx %d", __func__, + msm_uport->rx.rx_inx); + } + + if (!msm_uport->rx.buffer_pending) { + msm_uport->rx.flush = FLUSH_NONE; + msm_uport->rx_bam_inprogress = true; + sps_pipe_handle = rx->prod.pipe_handle; + MSM_HS_DBG("Queing bam descriptor\n"); + /* Queue transfer request to SPS */ + clear_bit(msm_uport->rx.rx_inx, + &msm_uport->rx.pending_flag); + msm_hs_queue_rx_desc(msm_uport); + msm_hs_mark_next(msm_uport, msm_uport->rx.rx_inx+1); + msm_hs_write(uport, UART_DM_CR, START_RX_BAM_IFC); + msm_uport->rx_bam_inprogress = false; + wake_up(&msm_uport->rx.wait); + } else + break; + + } +out: + if (msm_uport->rx.buffer_pending) { + MSM_HS_WARN("%s: tty buffer exhausted. Stalling\n", __func__); + schedule_delayed_work(&msm_uport->rx.flip_insert_work + , msecs_to_jiffies(RETRY_TIMEOUT)); + } + /* tty_flip_buffer_push() might call msm_hs_start(), so unlock */ + spin_unlock_irqrestore(&uport->lock, flags); + if (flush < FLUSH_DATA_INVALID) + tty_flip_buffer_push(tty->port); + msm_hs_resource_unvote(msm_uport); +} + +static void msm_hs_start_tx_locked(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + struct msm_hs_tx *tx = &msm_uport->tx; + unsigned int isr; + + /* Bail if transfer in progress */ + if (tx->flush < FLUSH_STOP || tx->dma_in_flight) { + MSM_HS_INFO("%s(): retry, flush %d, dma_in_flight %d\n", + __func__, tx->flush, tx->dma_in_flight); + + if (msm_uport->pm_state == MSM_HS_PM_ACTIVE) { + isr = msm_hs_read(uport, UART_DM_ISR); + if (UARTDM_ISR_CURRENT_CTS_BMSK & isr) { + MSM_HS_DBG("%s():CTS 1: Peer is Busy\n", + __func__); + MSM_HS_DBG("%s():ISR 0x%x\n", + __func__, isr); + } + } else + MSM_HS_WARN("%s(): Clocks are off\n", __func__); + + return; + } + + if (!tx->dma_in_flight) { + tx->dma_in_flight = true; + queue_kthread_work(&msm_uport->tx.kworker, + &msm_uport->tx.kwork); + } +} + +/** + * Callback notification from SPS driver + * + * This callback function gets triggered called from + * SPS driver when requested SPS data transfer is + * completed. + * + */ + +static void msm_hs_sps_tx_callback(struct sps_event_notify *notify) +{ + struct msm_hs_port *msm_uport = + (struct msm_hs_port *) + ((struct sps_event_notify *)notify)->user; + phys_addr_t addr = DESC_FULL_ADDR(notify->data.transfer.iovec.flags, + notify->data.transfer.iovec.addr); + + msm_uport->notify = *notify; + MSM_HS_INFO("tx_cb: addr=0x%pa, size=0x%x, flags=0x%x\n", + &addr, notify->data.transfer.iovec.size, + notify->data.transfer.iovec.flags); + + del_timer(&msm_uport->tx.tx_timeout_timer); + MSM_HS_DBG("%s(): Queue kthread work", __func__); + queue_kthread_work(&msm_uport->tx.kworker, &msm_uport->tx.kwork); +} + +static void msm_serial_hs_tx_work(struct kthread_work *work) +{ + unsigned long flags; + struct msm_hs_port *msm_uport = + container_of((struct kthread_work *)work, + struct msm_hs_port, tx.kwork); + struct uart_port *uport = &msm_uport->uport; + struct circ_buf *tx_buf = &uport->state->xmit; + struct msm_hs_tx *tx = &msm_uport->tx; + + /* + * Do the work buffer related work in BAM + * mode that is equivalent to legacy mode + */ + msm_hs_resource_vote(msm_uport); + if (tx->flush >= FLUSH_STOP) { + spin_lock_irqsave(&(msm_uport->uport.lock), flags); + tx->flush = FLUSH_NONE; + MSM_HS_DBG("%s(): calling submit_tx", __func__); + msm_hs_submit_tx_locked(uport); + spin_unlock_irqrestore(&(msm_uport->uport.lock), flags); + msm_hs_resource_unvote(msm_uport); + return; + } + + spin_lock_irqsave(&(msm_uport->uport.lock), flags); + if (!uart_circ_empty(tx_buf)) + tx_buf->tail = (tx_buf->tail + + tx->tx_count) & ~UART_XMIT_SIZE; + else + MSM_HS_DBG("%s:circ buffer is empty\n", __func__); + + wake_up(&msm_uport->tx.wait); + + uport->icount.tx += tx->tx_count; + + /* + * Calling to send next chunk of data + * If the circ buffer is empty, we stop + * If the clock off was requested, the clock + * off sequence is kicked off + */ + MSM_HS_DBG("%s(): calling submit_tx", __func__); + msm_hs_submit_tx_locked(uport); + + if (uart_circ_chars_pending(tx_buf) < WAKEUP_CHARS) + uart_write_wakeup(uport); + + spin_unlock_irqrestore(&(msm_uport->uport.lock), flags); + msm_hs_resource_unvote(msm_uport); +} + +static void +msm_hs_mark_proc_rx_desc(struct msm_hs_port *msm_uport, + struct sps_event_notify *notify) +{ + struct msm_hs_rx *rx = &msm_uport->rx; + phys_addr_t addr = DESC_FULL_ADDR(notify->data.transfer.iovec.flags, + notify->data.transfer.iovec.addr); + /* divide by UARTDM_RX_BUF_SIZE */ + int inx = (addr - rx->rbuffer) >> 9; + + set_bit(inx, &rx->pending_flag); + clear_bit(inx, &rx->queued_flag); + rx->iovec[inx] = notify->data.transfer.iovec; + MSM_HS_DBG("Clear Q, Set P Bit %d, Q 0x%lx P 0x%lx", + inx, rx->queued_flag, rx->pending_flag); +} + +/** + * Callback notification from SPS driver + * + * This callback function gets triggered called from + * SPS driver when requested SPS data transfer is + * completed. + * + */ + +static void msm_hs_sps_rx_callback(struct sps_event_notify *notify) +{ + + struct msm_hs_port *msm_uport = + (struct msm_hs_port *) + ((struct sps_event_notify *)notify)->user; + struct uart_port *uport; + unsigned long flags; + struct msm_hs_rx *rx = &msm_uport->rx; + phys_addr_t addr = DESC_FULL_ADDR(notify->data.transfer.iovec.flags, + notify->data.transfer.iovec.addr); + /* divide by UARTDM_RX_BUF_SIZE */ + int inx = (addr - rx->rbuffer) >> 9; + + uport = &(msm_uport->uport); + msm_uport->notify = *notify; + MSM_HS_INFO("rx_cb: addr=0x%pa, size=0x%x, flags=0x%x\n", + &addr, notify->data.transfer.iovec.size, + notify->data.transfer.iovec.flags); + + spin_lock_irqsave(&uport->lock, flags); + msm_hs_mark_proc_rx_desc(msm_uport, notify); + spin_unlock_irqrestore(&uport->lock, flags); + + if (msm_uport->rx.flush == FLUSH_NONE) { + /* Test if others are queued */ + if (msm_uport->rx.pending_flag & ~(1 << inx)) { + MSM_HS_DBG("%s(): inx 0x%x, 0x%lx not processed", + __func__, inx, + msm_uport->rx.pending_flag & ~(1<<inx)); + } + queue_kthread_work(&msm_uport->rx.kworker, + &msm_uport->rx.kwork); + MSM_HS_DBG("%s(): Scheduled rx_tlet", __func__); + } +} + +/* + * Standard API, Current states of modem control inputs + * + * Since CTS can be handled entirely by HARDWARE we always + * indicate clear to send and count on the TX FIFO to block when + * it fills up. + * + * - TIOCM_DCD + * - TIOCM_CTS + * - TIOCM_DSR + * - TIOCM_RI + * (Unsupported) DCD and DSR will return them high. RI will return low. + */ +static unsigned int msm_hs_get_mctrl_locked(struct uart_port *uport) +{ + return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS; +} + +/* + * Standard API, Set or clear RFR_signal + * + * Set RFR high, (Indicate we are not ready for data), we disable auto + * ready for receiving and then set RFR_N high. To set RFR to low we just turn + * back auto ready for receiving and it should lower RFR signal + * when hardware is ready + */ +void msm_hs_set_mctrl_locked(struct uart_port *uport, + unsigned int mctrl) +{ + unsigned int set_rts; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + if (msm_uport->pm_state != MSM_HS_PM_ACTIVE) { + MSM_HS_WARN("%s(): Clocks are off\n", __func__); + return; + } + /* RTS is active low */ + set_rts = TIOCM_RTS & mctrl ? 0 : 1; + MSM_HS_INFO("%s: set_rts %d\n", __func__, set_rts); + + if (set_rts) + msm_hs_disable_flow_control(uport, false); + else + msm_hs_enable_flow_control(uport, false); +} + +void msm_hs_set_mctrl(struct uart_port *uport, + unsigned int mctrl) +{ + unsigned long flags; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + msm_hs_resource_vote(msm_uport); + spin_lock_irqsave(&uport->lock, flags); + msm_hs_set_mctrl_locked(uport, mctrl); + spin_unlock_irqrestore(&uport->lock, flags); + msm_hs_resource_unvote(msm_uport); +} +EXPORT_SYMBOL(msm_hs_set_mctrl); + +/* Standard API, Enable modem status (CTS) interrupt */ +static void msm_hs_enable_ms_locked(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + if (msm_uport->pm_state != MSM_HS_PM_ACTIVE) { + MSM_HS_WARN("%s(): Clocks are off\n", __func__); + return; + } + + /* Enable DELTA_CTS Interrupt */ + msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK; + msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg); + /* Ensure register IO completion */ + mb(); + +} + +/* + * Standard API, Break Signal + * + * Control the transmission of a break signal. ctl eq 0 => break + * signal terminate ctl ne 0 => start break signal + */ +static void msm_hs_break_ctl(struct uart_port *uport, int ctl) +{ + unsigned long flags; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + msm_hs_resource_vote(msm_uport); + spin_lock_irqsave(&uport->lock, flags); + msm_hs_write(uport, UART_DM_CR, ctl ? START_BREAK : STOP_BREAK); + /* Ensure register IO completion */ + mb(); + spin_unlock_irqrestore(&uport->lock, flags); + msm_hs_resource_unvote(msm_uport); +} + +static void msm_hs_config_port(struct uart_port *uport, int cfg_flags) +{ + if (cfg_flags & UART_CONFIG_TYPE) + uport->type = PORT_MSM; + +} + +/* Handle CTS changes (Called from interrupt handler) */ +static void msm_hs_handle_delta_cts_locked(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + msm_hs_resource_vote(msm_uport); + /* clear interrupt */ + msm_hs_write(uport, UART_DM_CR, RESET_CTS); + /* Calling CLOCK API. Hence mb() requires here. */ + mb(); + uport->icount.cts++; + + /* clear the IOCTL TIOCMIWAIT if called */ + wake_up_interruptible(&uport->state->port.delta_msr_wait); + msm_hs_resource_unvote(msm_uport); +} + +static irqreturn_t msm_hs_isr(int irq, void *dev) +{ + unsigned long flags; + unsigned int isr_status; + struct msm_hs_port *msm_uport = (struct msm_hs_port *)dev; + struct uart_port *uport = &msm_uport->uport; + struct circ_buf *tx_buf = &uport->state->xmit; + struct msm_hs_tx *tx = &msm_uport->tx; + + spin_lock_irqsave(&uport->lock, flags); + + isr_status = msm_hs_read(uport, UART_DM_MISR); + MSM_HS_INFO("%s: DM_ISR: 0x%x\n", __func__, isr_status); + dump_uart_hs_registers(msm_uport); + + /* Uart RX starting */ + if (isr_status & UARTDM_ISR_RXLEV_BMSK) { + MSM_HS_DBG("%s:UARTDM_ISR_RXLEV_BMSK\n", __func__); + msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK; + msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg); + /* Complete device write for IMR. Hence mb() requires. */ + mb(); + } + /* Stale rx interrupt */ + if (isr_status & UARTDM_ISR_RXSTALE_BMSK) { + msm_hs_write(uport, UART_DM_CR, STALE_EVENT_DISABLE); + msm_hs_write(uport, UART_DM_CR, RESET_STALE_INT); + /* + * Complete device write before calling DMOV API. Hence + * mb() requires here. + */ + mb(); + MSM_HS_DBG("%s:Stal Interrupt\n", __func__); + } + /* tx ready interrupt */ + if (isr_status & UARTDM_ISR_TX_READY_BMSK) { + MSM_HS_DBG("%s: ISR_TX_READY Interrupt\n", __func__); + /* Clear TX Ready */ + msm_hs_write(uport, UART_DM_CR, CLEAR_TX_READY); + + /* + * Complete both writes before starting new TX. + * Hence mb() requires here. + */ + mb(); + /* Complete DMA TX transactions and submit new transactions */ + + /* Do not update tx_buf.tail if uart_flush_buffer already + * called in serial core + */ + if (!uart_circ_empty(tx_buf)) + tx_buf->tail = (tx_buf->tail + + tx->tx_count) & ~UART_XMIT_SIZE; + + tx->dma_in_flight = false; + + uport->icount.tx += tx->tx_count; + + if (uart_circ_chars_pending(tx_buf) < WAKEUP_CHARS) + uart_write_wakeup(uport); + } + if (isr_status & UARTDM_ISR_TXLEV_BMSK) { + /* TX FIFO is empty */ + msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK; + msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg); + MSM_HS_DBG("%s: TXLEV Interrupt\n", __func__); + /* + * Complete device write before starting clock_off request. + * Hence mb() requires here. + */ + mb(); + queue_work(msm_uport->hsuart_wq, &msm_uport->clock_off_w); + } + + /* Change in CTS interrupt */ + if (isr_status & UARTDM_ISR_DELTA_CTS_BMSK) + msm_hs_handle_delta_cts_locked(uport); + + spin_unlock_irqrestore(&uport->lock, flags); + + return IRQ_HANDLED; +} + +/* The following two functions provide interfaces to get the underlying + * port structure (struct uart_port or struct msm_hs_port) given + * the port index. msm_hs_get_uart port is called by clients. + * The function msm_hs_get_hs_port is for internal use + */ + +struct uart_port *msm_hs_get_uart_port(int port_index) +{ + struct uart_state *state = msm_hs_driver.state + port_index; + + /* The uart_driver structure stores the states in an array. + * Thus the corresponding offset from the drv->state returns + * the state for the uart_port that is requested + */ + if (port_index == state->uart_port->line) + return state->uart_port; + + return NULL; +} +EXPORT_SYMBOL(msm_hs_get_uart_port); + +static struct msm_hs_port *msm_hs_get_hs_port(int port_index) +{ + struct uart_port *uport = msm_hs_get_uart_port(port_index); + if (uport) + return UARTDM_TO_MSM(uport); + return NULL; +} + +void enable_wakeup_interrupt(struct msm_hs_port *msm_uport) +{ + unsigned long flags; + struct uart_port *uport = &(msm_uport->uport); + + if (!is_use_low_power_wakeup(msm_uport)) + return; + if (msm_uport->wakeup.freed) + return; + + if (!(msm_uport->wakeup.enabled)) { + spin_lock_irqsave(&uport->lock, flags); + msm_uport->wakeup.ignore = 1; + msm_uport->wakeup.enabled = true; + spin_unlock_irqrestore(&uport->lock, flags); + disable_irq(uport->irq); + enable_irq(msm_uport->wakeup.irq); + } else { + MSM_HS_WARN("%s:Wake up IRQ already enabled", __func__); + } +} + +void disable_wakeup_interrupt(struct msm_hs_port *msm_uport) +{ + unsigned long flags; + struct uart_port *uport = &(msm_uport->uport); + + if (!is_use_low_power_wakeup(msm_uport)) + return; + if (msm_uport->wakeup.freed) + return; + + if (msm_uport->wakeup.enabled) { + disable_irq(msm_uport->wakeup.irq); + enable_irq(uport->irq); + spin_lock_irqsave(&uport->lock, flags); + msm_uport->wakeup.enabled = false; + spin_unlock_irqrestore(&uport->lock, flags); + } else { + MSM_HS_WARN("%s:Wake up IRQ already disabled", __func__); + } +} + +void msm_hs_resource_off(struct msm_hs_port *msm_uport) +{ + struct uart_port *uport = &(msm_uport->uport); + unsigned int data; + int ret = 0; + + MSM_HS_DBG("%s(): begin", __func__); + msm_hs_disable_flow_control(uport, false); + if (msm_uport->rx.flush == FLUSH_NONE) + msm_hs_disconnect_rx(uport); + else if (msm_uport->rx.flush != FLUSH_SHUTDOWN) { + MSM_HS_WARN("%s():Rx Flush=%d Not Expected\n", + __func__, msm_uport->rx.flush); + /* disable and disconnect rx */ + ret = wait_event_timeout(msm_uport->rx.wait, + !msm_uport->rx.pending_flag, 500); + if (!ret) + MSM_HS_WARN("%s(): rx disconnect not complete", + __func__); + msm_hs_disconnect_rx(uport); + } else + MSM_HS_DBG("%s():Rx Flush=%d In Proper State\n", + __func__, msm_uport->rx.flush); + + /* disable dlink */ + if (msm_uport->tx.flush == FLUSH_NONE) { + ret = wait_event_timeout(msm_uport->tx.wait, + msm_uport->tx.flush == FLUSH_STOP, 500); + if (!ret) + MSM_HS_WARN("%s(): tx disconnect not complete", + __func__); + } + + if (msm_uport->tx.flush != FLUSH_SHUTDOWN) { + data = msm_hs_read(uport, UART_DM_DMEN); + data &= ~UARTDM_TX_BAM_ENABLE_BMSK; + msm_hs_write(uport, UART_DM_DMEN, data); + sps_tx_disconnect(msm_uport); + } + if (!atomic_read(&msm_uport->client_req_state)) + msm_hs_enable_flow_control(uport, false); +} + +void msm_hs_resource_on(struct msm_hs_port *msm_uport) +{ + struct uart_port *uport = &(msm_uport->uport); + unsigned int data; + unsigned long flags; + + if (atomic_read(&msm_uport->startup_locked)) { + MSM_HS_DBG("%s(): Port open in progress\n", __func__); + return; + } + msm_hs_disable_flow_control(uport, false); + + if (msm_uport->rx.flush == FLUSH_SHUTDOWN || + msm_uport->rx.flush == FLUSH_STOP) { + msm_hs_write(uport, UART_DM_CR, RESET_RX); + data = msm_hs_read(uport, UART_DM_DMEN); + data |= UARTDM_RX_BAM_ENABLE_BMSK; + msm_hs_write(uport, UART_DM_DMEN, data); + } else + MSM_HS_DBG("%s():rx.flush=%d, Rx is not enabled\n", + __func__, msm_uport->rx.flush); + + if (msm_uport->rx.flush == FLUSH_SHUTDOWN) { + msm_hs_spsconnect_rx(uport); + spin_lock_irqsave(&uport->lock, flags); + msm_hs_start_rx_locked(uport); + spin_unlock_irqrestore(&uport->lock, flags); + } + msm_hs_spsconnect_tx(msm_uport); + + msm_hs_enable_flow_control(uport, false); +} + +/* Request to turn off uart clock once pending TX is flushed */ +int msm_hs_request_clock_off(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + int ret = 0; + int client_count = 0; + + mutex_lock(&msm_uport->mtx); + /* + * If we're in the middle of a system suspend, don't process these + * userspace/kernel API commands. + */ + if (msm_uport->pm_state == MSM_HS_PM_SYS_SUSPENDED) { + MSM_HS_WARN("%s:Can't process clk request during suspend", + __func__); + ret = -EIO; + } + mutex_unlock(&msm_uport->mtx); + if (ret) + goto exit_request_clock_off; + + if (atomic_read(&msm_uport->client_count) <= 0) { + MSM_HS_WARN("%s(): ioctl count -ve, client check voting", + __func__); + ret = -EPERM; + goto exit_request_clock_off; + } + /* Set the flag to disable flow control and wakeup irq */ + if (msm_uport->obs) + atomic_set(&msm_uport->client_req_state, 1); + msm_hs_resource_unvote(msm_uport); + atomic_dec(&msm_uport->client_count); + client_count = atomic_read(&msm_uport->client_count); + LOG_USR_MSG(msm_uport->ipc_msm_hs_pwr_ctxt, + "%s: Client_Count %d\n", __func__, + client_count); +exit_request_clock_off: + return ret; +} +EXPORT_SYMBOL(msm_hs_request_clock_off); + +int msm_hs_request_clock_on(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + int client_count; + int ret = 0; + + mutex_lock(&msm_uport->mtx); + /* + * If we're in the middle of a system suspend, don't process these + * userspace/kernel API commands. + */ + if (msm_uport->pm_state == MSM_HS_PM_SYS_SUSPENDED) { + MSM_HS_WARN("%s:Can't process clk request during suspend", + __func__); + ret = -EIO; + } + mutex_unlock(&msm_uport->mtx); + if (ret) + goto exit_request_clock_on; + + msm_hs_resource_vote(UARTDM_TO_MSM(uport)); + atomic_inc(&msm_uport->client_count); + client_count = atomic_read(&msm_uport->client_count); + LOG_USR_MSG(msm_uport->ipc_msm_hs_pwr_ctxt, + "%s: Client_Count %d\n", __func__, + client_count); + + /* Clear the flag */ + if (msm_uport->obs) + atomic_set(&msm_uport->client_req_state, 0); +exit_request_clock_on: + return ret; +} +EXPORT_SYMBOL(msm_hs_request_clock_on); + +static irqreturn_t msm_hs_wakeup_isr(int irq, void *dev) +{ + unsigned int wakeup = 0; + unsigned long flags; + struct msm_hs_port *msm_uport = (struct msm_hs_port *)dev; + struct uart_port *uport = &msm_uport->uport; + struct tty_struct *tty = NULL; + + spin_lock_irqsave(&uport->lock, flags); + + if (msm_uport->wakeup.ignore) + msm_uport->wakeup.ignore = 0; + else + wakeup = 1; + + if (wakeup) { + /* + * Port was clocked off during rx, wake up and + * optionally inject char into tty rx + */ + if (msm_uport->wakeup.inject_rx) { + tty = uport->state->port.tty; + tty_insert_flip_char(tty->port, + msm_uport->wakeup.rx_to_inject, + TTY_NORMAL); + hex_dump_ipc(msm_uport, msm_uport->rx.ipc_rx_ctxt, + "Rx Inject", + &msm_uport->wakeup.rx_to_inject, 0, 1); + MSM_HS_INFO("Wakeup ISR.Ignore%d\n", + msm_uport->wakeup.ignore); + } + } + + spin_unlock_irqrestore(&uport->lock, flags); + + if (wakeup && msm_uport->wakeup.inject_rx) + tty_flip_buffer_push(tty->port); + return IRQ_HANDLED; +} + +static const char *msm_hs_type(struct uart_port *port) +{ + return "MSM HS UART"; +} + +/** + * msm_hs_unconfig_uart_gpios: Unconfigures UART GPIOs + * @uport: uart port + */ +static void msm_hs_unconfig_uart_gpios(struct uart_port *uport) +{ + struct platform_device *pdev = to_platform_device(uport->dev); + const struct msm_serial_hs_platform_data *pdata = + pdev->dev.platform_data; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + int ret; + + if (msm_uport->use_pinctrl) { + ret = pinctrl_select_state(msm_uport->pinctrl, + msm_uport->gpio_state_suspend); + if (ret) + MSM_HS_ERR("%s():Failed to pinctrl set_state", + __func__); + } else if (pdata) { + if (gpio_is_valid(pdata->uart_tx_gpio)) + gpio_free(pdata->uart_tx_gpio); + if (gpio_is_valid(pdata->uart_rx_gpio)) + gpio_free(pdata->uart_rx_gpio); + if (gpio_is_valid(pdata->uart_cts_gpio)) + gpio_free(pdata->uart_cts_gpio); + if (gpio_is_valid(pdata->uart_rfr_gpio)) + gpio_free(pdata->uart_rfr_gpio); + } else + MSM_HS_ERR("Error:Pdata is NULL.\n"); +} + +/** + * msm_hs_config_uart_gpios - Configures UART GPIOs + * @uport: uart port + */ +static int msm_hs_config_uart_gpios(struct uart_port *uport) +{ + struct platform_device *pdev = to_platform_device(uport->dev); + const struct msm_serial_hs_platform_data *pdata = + pdev->dev.platform_data; + int ret = 0; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + if (!IS_ERR_OR_NULL(msm_uport->pinctrl)) { + MSM_HS_DBG("%s(): Using Pinctrl", __func__); + msm_uport->use_pinctrl = true; + ret = pinctrl_select_state(msm_uport->pinctrl, + msm_uport->gpio_state_active); + if (ret) + MSM_HS_ERR("%s(): Failed to pinctrl set_state", + __func__); + return ret; + } else if (pdata) { + /* Fall back to using gpio lib */ + if (gpio_is_valid(pdata->uart_tx_gpio)) { + ret = gpio_request(pdata->uart_tx_gpio, + "UART_TX_GPIO"); + if (unlikely(ret)) { + MSM_HS_ERR("gpio request failed for:%d\n", + pdata->uart_tx_gpio); + goto exit_uart_config; + } + } + + if (gpio_is_valid(pdata->uart_rx_gpio)) { + ret = gpio_request(pdata->uart_rx_gpio, + "UART_RX_GPIO"); + if (unlikely(ret)) { + MSM_HS_ERR("gpio request failed for:%d\n", + pdata->uart_rx_gpio); + goto uart_tx_unconfig; + } + } + + if (gpio_is_valid(pdata->uart_cts_gpio)) { + ret = gpio_request(pdata->uart_cts_gpio, + "UART_CTS_GPIO"); + if (unlikely(ret)) { + MSM_HS_ERR("gpio request failed for:%d\n", + pdata->uart_cts_gpio); + goto uart_rx_unconfig; + } + } + + if (gpio_is_valid(pdata->uart_rfr_gpio)) { + ret = gpio_request(pdata->uart_rfr_gpio, + "UART_RFR_GPIO"); + if (unlikely(ret)) { + MSM_HS_ERR("gpio request failed for:%d\n", + pdata->uart_rfr_gpio); + goto uart_cts_unconfig; + } + } + } else { + MSM_HS_ERR("Pdata is NULL.\n"); + ret = -EINVAL; + } + return ret; + +uart_cts_unconfig: + if (gpio_is_valid(pdata->uart_cts_gpio)) + gpio_free(pdata->uart_cts_gpio); +uart_rx_unconfig: + if (gpio_is_valid(pdata->uart_rx_gpio)) + gpio_free(pdata->uart_rx_gpio); +uart_tx_unconfig: + if (gpio_is_valid(pdata->uart_tx_gpio)) + gpio_free(pdata->uart_tx_gpio); +exit_uart_config: + return ret; +} + + +static void msm_hs_get_pinctrl_configs(struct uart_port *uport) +{ + struct pinctrl_state *set_state; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + msm_uport->pinctrl = devm_pinctrl_get(uport->dev); + if (IS_ERR_OR_NULL(msm_uport->pinctrl)) { + MSM_HS_DBG("%s(): Pinctrl not defined", __func__); + } else { + MSM_HS_DBG("%s(): Using Pinctrl", __func__); + msm_uport->use_pinctrl = true; + + set_state = pinctrl_lookup_state(msm_uport->pinctrl, + PINCTRL_STATE_DEFAULT); + if (IS_ERR_OR_NULL(set_state)) { + dev_err(uport->dev, + "pinctrl lookup failed for default state"); + goto pinctrl_fail; + } + + MSM_HS_DBG("%s(): Pinctrl state active %p\n", __func__, + set_state); + msm_uport->gpio_state_active = set_state; + + set_state = pinctrl_lookup_state(msm_uport->pinctrl, + PINCTRL_STATE_SLEEP); + if (IS_ERR_OR_NULL(set_state)) { + dev_err(uport->dev, + "pinctrl lookup failed for sleep state"); + goto pinctrl_fail; + } + + MSM_HS_DBG("%s(): Pinctrl state sleep %p\n", __func__, + set_state); + msm_uport->gpio_state_suspend = set_state; + return; + } +pinctrl_fail: + msm_uport->pinctrl = NULL; + return; +} + +/* Called when port is opened */ +static int msm_hs_startup(struct uart_port *uport) +{ + int ret; + int rfr_level; + unsigned long flags; + u32 irq_type; + unsigned int data; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + struct circ_buf *tx_buf = &uport->state->xmit; + struct msm_hs_tx *tx = &msm_uport->tx; + struct msm_hs_rx *rx = &msm_uport->rx; + struct sps_pipe *sps_pipe_handle_tx = tx->cons.pipe_handle; + struct sps_pipe *sps_pipe_handle_rx = rx->prod.pipe_handle; + + atomic_set(&msm_uport->startup_locked, 1); + rfr_level = uport->fifosize; + if (rfr_level > 16) + rfr_level -= 16; + + tx->dma_base = dma_map_single(uport->dev, tx_buf->buf, UART_XMIT_SIZE, + DMA_TO_DEVICE); + + /* turn on uart clk */ + msm_hs_resource_vote(msm_uport); + + if (is_use_low_power_wakeup(msm_uport)) { + irq_type = irq_get_trigger_type(msm_uport->wakeup.irq); + if (irq_type == IRQ_TYPE_NONE) + irq_type = IRQ_TYPE_EDGE_FALLING; + ret = request_irq(msm_uport->wakeup.irq, msm_hs_wakeup_isr, + irq_type | IRQF_ONESHOT, + "msm_hs_wakeup", msm_uport); + if (unlikely(ret)) { + MSM_HS_ERR("%s():Err getting uart wakeup_irq %d\n", + __func__, ret); + goto unvote_exit; + } + + msm_uport->wakeup.freed = false; + disable_irq(msm_uport->wakeup.irq); + msm_uport->wakeup.enabled = false; + + ret = irq_set_irq_wake(msm_uport->wakeup.irq, 1); + if (unlikely(ret)) { + MSM_HS_ERR("%s():Err setting wakeup irq\n", __func__); + goto free_uart_irq; + } + } + + ret = msm_hs_config_uart_gpios(uport); + if (ret) { + MSM_HS_ERR("Uart GPIO request failed\n"); + goto free_uart_irq; + } + + msm_hs_write(uport, UART_DM_DMEN, 0); + + /* Connect TX */ + sps_tx_disconnect(msm_uport); + ret = msm_hs_spsconnect_tx(msm_uport); + if (ret) { + MSM_HS_ERR("msm_serial_hs: SPS connect failed for TX"); + goto unconfig_uart_gpios; + } + + /* Connect RX */ + flush_kthread_worker(&msm_uport->rx.kworker); + if (rx->flush != FLUSH_SHUTDOWN) + disconnect_rx_endpoint(msm_uport); + else + MSM_HS_DBG("%s(): Rx Flush=%d In Proper state\n", + __func__, rx->flush); + ret = msm_hs_spsconnect_rx(uport); + if (ret) { + MSM_HS_ERR("msm_serial_hs: SPS connect failed for RX"); + goto sps_disconnect_tx; + } + + data = (UARTDM_BCR_TX_BREAK_DISABLE | UARTDM_BCR_STALE_IRQ_EMPTY | + UARTDM_BCR_RX_DMRX_LOW_EN | UARTDM_BCR_RX_STAL_IRQ_DMRX_EQL | + UARTDM_BCR_RX_DMRX_1BYTE_RES_EN); + msm_hs_write(uport, UART_DM_BCR, data); + + /* Set auto RFR Level */ + data = msm_hs_read(uport, UART_DM_MR1); + data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK; + data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK; + data |= (UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2)); + data |= (UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level); + msm_hs_write(uport, UART_DM_MR1, data); + + /* Make sure RXSTALE count is non-zero */ + data = msm_hs_read(uport, UART_DM_IPR); + if (!data) { + data |= 0x1f & UARTDM_IPR_STALE_LSB_BMSK; + msm_hs_write(uport, UART_DM_IPR, data); + } + + /* Assume no flow control, unless termios sets it */ + msm_uport->flow_control = false; + msm_hs_disable_flow_control(uport, true); + + + /* Reset TX */ + msm_hs_write(uport, UART_DM_CR, RESET_TX); + msm_hs_write(uport, UART_DM_CR, RESET_RX); + msm_hs_write(uport, UART_DM_CR, RESET_ERROR_STATUS); + msm_hs_write(uport, UART_DM_CR, RESET_BREAK_INT); + msm_hs_write(uport, UART_DM_CR, RESET_STALE_INT); + msm_hs_write(uport, UART_DM_CR, RESET_CTS); + msm_hs_write(uport, UART_DM_CR, RFR_LOW); + /* Turn on Uart Receiver */ + msm_hs_write(uport, UART_DM_CR, UARTDM_CR_RX_EN_BMSK); + + /* Turn on Uart Transmitter */ + msm_hs_write(uport, UART_DM_CR, UARTDM_CR_TX_EN_BMSK); + + tx->dma_in_flight = false; + MSM_HS_DBG("%s():desc usage flag 0x%lx", __func__, rx->queued_flag); + setup_timer(&(tx->tx_timeout_timer), + tx_timeout_handler, + (unsigned long) msm_uport); + + /* Enable reading the current CTS, no harm even if CTS is ignored */ + msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK; + + /* TXLEV on empty TX fifo */ + msm_hs_write(uport, UART_DM_TFWR, 4); + /* + * Complete all device write related configuration before + * queuing RX request. Hence mb() requires here. + */ + mb(); + + ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH, + "msm_hs_uart", msm_uport); + if (unlikely(ret)) { + MSM_HS_ERR("%s():Error %d getting uart irq\n", __func__, ret); + goto sps_disconnect_rx; + } + + + spin_lock_irqsave(&uport->lock, flags); + atomic_set(&msm_uport->client_count, 0); + atomic_set(&msm_uport->client_req_state, 0); + LOG_USR_MSG(msm_uport->ipc_msm_hs_pwr_ctxt, + "%s: Client_Count 0\n", __func__); + atomic_set(&msm_uport->startup_locked, 0); + msm_hs_start_rx_locked(uport); + + spin_unlock_irqrestore(&uport->lock, flags); + + msm_hs_resource_unvote(msm_uport); + return 0; + +sps_disconnect_rx: + sps_disconnect(sps_pipe_handle_rx); +sps_disconnect_tx: + sps_disconnect(sps_pipe_handle_tx); +unconfig_uart_gpios: + msm_hs_unconfig_uart_gpios(uport); +free_uart_irq: + free_irq(uport->irq, msm_uport); +unvote_exit: + atomic_set(&msm_uport->startup_locked, 0); + msm_hs_resource_unvote(msm_uport); + MSM_HS_ERR("%s(): Error return\n", __func__); + return ret; +} + +/* Initialize tx and rx data structures */ +static int uartdm_init_port(struct uart_port *uport) +{ + int ret = 0; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + struct msm_hs_tx *tx = &msm_uport->tx; + struct msm_hs_rx *rx = &msm_uport->rx; + struct sched_param param = { .sched_priority = 1 }; + + init_waitqueue_head(&rx->wait); + init_waitqueue_head(&tx->wait); + init_waitqueue_head(&msm_uport->bam_disconnect_wait); + + /* Init kernel threads for tx and rx */ + + init_kthread_worker(&rx->kworker); + rx->task = kthread_run(kthread_worker_fn, + &rx->kworker, "msm_serial_hs_%d_rx_work", uport->line); + if (IS_ERR(rx->task)) { + MSM_HS_ERR("%s(): error creating task", __func__); + goto exit_lh_init; + } + sched_setscheduler(rx->task, SCHED_FIFO, ¶m); + + init_kthread_work(&rx->kwork, msm_serial_hs_rx_work); + + init_kthread_worker(&tx->kworker); + tx->task = kthread_run(kthread_worker_fn, + &tx->kworker, "msm_serial_hs_%d_tx_work", uport->line); + if (IS_ERR(rx->task)) { + MSM_HS_ERR("%s(): error creating task", __func__); + goto exit_lh_init; + } + sched_setscheduler(tx->task, SCHED_FIFO, ¶m); + + init_kthread_work(&tx->kwork, msm_serial_hs_tx_work); + + rx->buffer = dma_alloc_coherent(uport->dev, + UART_DMA_DESC_NR * UARTDM_RX_BUF_SIZE, + &rx->rbuffer, GFP_KERNEL); + if (!rx->buffer) { + MSM_HS_ERR("%s(): cannot allocate rx->buffer", __func__); + ret = -ENOMEM; + goto exit_lh_init; + } + + /* Set up Uart Receive */ + msm_hs_write(uport, UART_DM_RFWR, 32); + /* Write to BADR explicitly to set up FIFO sizes */ + msm_hs_write(uport, UARTDM_BADR_ADDR, 64); + + INIT_DELAYED_WORK(&rx->flip_insert_work, flip_insert_work); + + return ret; +exit_lh_init: + kthread_stop(rx->task); + rx->task = NULL; + kthread_stop(tx->task); + tx->task = NULL; + return ret; +} + +struct msm_serial_hs_platform_data + *msm_hs_dt_to_pdata(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct msm_serial_hs_platform_data *pdata; + u32 rx_to_inject; + int ret; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + pr_err("unable to allocate memory for platform data\n"); + return ERR_PTR(-ENOMEM); + } + + pdev->id = of_alias_get_id(pdev->dev.of_node, "uart"); + /* UART TX GPIO */ + pdata->uart_tx_gpio = of_get_named_gpio(node, + "qcom,tx-gpio", 0); + if (pdata->uart_tx_gpio < 0) + pr_err("uart_tx_gpio is not available\n"); + + /* UART RX GPIO */ + pdata->uart_rx_gpio = of_get_named_gpio(node, + "qcom,rx-gpio", 0); + if (pdata->uart_rx_gpio < 0) + pr_err("uart_rx_gpio is not available\n"); + + /* UART CTS GPIO */ + pdata->uart_cts_gpio = of_get_named_gpio(node, + "qcom,cts-gpio", 0); + if (pdata->uart_cts_gpio < 0) + pr_err("uart_cts_gpio is not available\n"); + + /* UART RFR GPIO */ + pdata->uart_rfr_gpio = of_get_named_gpio(node, + "qcom,rfr-gpio", 0); + if (pdata->uart_rfr_gpio < 0) + pr_err("uart_rfr_gpio is not available\n"); + + pdata->no_suspend_delay = of_property_read_bool(node, + "qcom,no-suspend-delay"); + + pdata->obs = of_property_read_bool(node, + "qcom,msm-obs"); + if (pdata->obs) + pr_err("%s:Out of Band sleep flag is set\n", __func__); + + pdata->inject_rx_on_wakeup = of_property_read_bool(node, + "qcom,inject-rx-on-wakeup"); + + if (pdata->inject_rx_on_wakeup) { + ret = of_property_read_u32(node, "qcom,rx-char-to-inject", + &rx_to_inject); + if (ret < 0) { + pr_err("Error: Rx_char_to_inject not specified.\n"); + return ERR_PTR(ret); + } + pdata->rx_to_inject = (u8)rx_to_inject; + } + + ret = of_property_read_u32(node, "qcom,bam-tx-ep-pipe-index", + &pdata->bam_tx_ep_pipe_index); + if (ret < 0) { + pr_err("Error: Getting UART BAM TX EP Pipe Index.\n"); + return ERR_PTR(ret); + } + + if (!(pdata->bam_tx_ep_pipe_index >= BAM_PIPE_MIN && + pdata->bam_tx_ep_pipe_index <= BAM_PIPE_MAX)) { + pr_err("Error: Invalid UART BAM TX EP Pipe Index.\n"); + return ERR_PTR(-EINVAL); + } + + ret = of_property_read_u32(node, "qcom,bam-rx-ep-pipe-index", + &pdata->bam_rx_ep_pipe_index); + if (ret < 0) { + pr_err("Error: Getting UART BAM RX EP Pipe Index.\n"); + return ERR_PTR(ret); + } + + if (!(pdata->bam_rx_ep_pipe_index >= BAM_PIPE_MIN && + pdata->bam_rx_ep_pipe_index <= BAM_PIPE_MAX)) { + pr_err("Error: Invalid UART BAM RX EP Pipe Index.\n"); + return ERR_PTR(-EINVAL); + } + + pr_debug("tx_ep_pipe_index:%d rx_ep_pipe_index:%d\n" + "tx_gpio:%d rx_gpio:%d rfr_gpio:%d cts_gpio:%d", + pdata->bam_tx_ep_pipe_index, pdata->bam_rx_ep_pipe_index, + pdata->uart_tx_gpio, pdata->uart_rx_gpio, pdata->uart_cts_gpio, + pdata->uart_rfr_gpio); + + return pdata; +} + + +/** + * Deallocate UART peripheral's SPS endpoint + * @msm_uport - Pointer to msm_hs_port structure + * @ep - Pointer to sps endpoint data structure + */ + +static void msm_hs_exit_ep_conn(struct msm_hs_port *msm_uport, + struct msm_hs_sps_ep_conn_data *ep) +{ + struct sps_pipe *sps_pipe_handle = ep->pipe_handle; + struct sps_connect *sps_config = &ep->config; + + dma_free_coherent(msm_uport->uport.dev, + sps_config->desc.size, + &sps_config->desc.phys_base, + GFP_KERNEL); + sps_free_endpoint(sps_pipe_handle); +} + + +/** + * Allocate UART peripheral's SPS endpoint + * + * This function allocates endpoint context + * by calling appropriate SPS driver APIs. + * + * @msm_uport - Pointer to msm_hs_port structure + * @ep - Pointer to sps endpoint data structure + * @is_produce - 1 means Producer endpoint + * - 0 means Consumer endpoint + * + * @return - 0 if successful else negative value + */ + +static int msm_hs_sps_init_ep_conn(struct msm_hs_port *msm_uport, + struct msm_hs_sps_ep_conn_data *ep, + bool is_producer) +{ + int rc = 0; + struct sps_pipe *sps_pipe_handle; + struct sps_connect *sps_config = &ep->config; + struct sps_register_event *sps_event = &ep->event; + + /* Allocate endpoint context */ + sps_pipe_handle = sps_alloc_endpoint(); + if (!sps_pipe_handle) { + MSM_HS_ERR("%s(): sps_alloc_endpoint() failed!!\n" + "is_producer=%d", __func__, is_producer); + rc = -ENOMEM; + goto out; + } + + /* Get default connection configuration for an endpoint */ + rc = sps_get_config(sps_pipe_handle, sps_config); + if (rc) { + MSM_HS_ERR("%s(): failed! pipe_handle=0x%p rc=%d", + __func__, sps_pipe_handle, rc); + goto get_config_err; + } + + /* Modify the default connection configuration */ + if (is_producer) { + /* For UART producer transfer, source is UART peripheral + where as destination is system memory */ + sps_config->source = msm_uport->bam_handle; + sps_config->destination = SPS_DEV_HANDLE_MEM; + sps_config->mode = SPS_MODE_SRC; + sps_config->src_pipe_index = msm_uport->bam_rx_ep_pipe_index; + sps_config->dest_pipe_index = 0; + sps_event->callback = msm_hs_sps_rx_callback; + } else { + /* For UART consumer transfer, source is system memory + where as destination is UART peripheral */ + sps_config->source = SPS_DEV_HANDLE_MEM; + sps_config->destination = msm_uport->bam_handle; + sps_config->mode = SPS_MODE_DEST; + sps_config->src_pipe_index = 0; + sps_config->dest_pipe_index = msm_uport->bam_tx_ep_pipe_index; + sps_event->callback = msm_hs_sps_tx_callback; + } + + sps_config->options = SPS_O_EOT | SPS_O_DESC_DONE | SPS_O_AUTO_ENABLE; + sps_config->event_thresh = 0x10; + + /* Allocate maximum descriptor fifo size */ + sps_config->desc.size = + (1 + UART_DMA_DESC_NR) * sizeof(struct sps_iovec); + sps_config->desc.base = dma_alloc_coherent(msm_uport->uport.dev, + sps_config->desc.size, + &sps_config->desc.phys_base, + GFP_KERNEL); + if (!sps_config->desc.base) { + rc = -ENOMEM; + MSM_HS_ERR("msm_serial_hs: dma_alloc_coherent() failed!!\n"); + goto get_config_err; + } + memset(sps_config->desc.base, 0x00, sps_config->desc.size); + + sps_event->mode = SPS_TRIGGER_CALLBACK; + + sps_event->options = SPS_O_DESC_DONE | SPS_O_EOT; + sps_event->user = (void *)msm_uport; + + /* Now save the sps pipe handle */ + ep->pipe_handle = sps_pipe_handle; + MSM_HS_DBG("msm_serial_hs: success !! %s: pipe_handle=0x%p\n" + "desc_fifo.phys_base=0x%pa\n", + is_producer ? "READ" : "WRITE", + sps_pipe_handle, &sps_config->desc.phys_base); + return 0; + +get_config_err: + sps_free_endpoint(sps_pipe_handle); +out: + return rc; +} + +/** + * Initialize SPS HW connected with UART core + * + * This function register BAM HW resources with + * SPS driver and then initialize 2 SPS endpoints + * + * msm_uport - Pointer to msm_hs_port structure + * + * @return - 0 if successful else negative value + */ + +static int msm_hs_sps_init(struct msm_hs_port *msm_uport) +{ + int rc = 0; + struct sps_bam_props bam = {0}; + unsigned long bam_handle; + + rc = sps_phy2h(msm_uport->bam_mem, &bam_handle); + if (rc || !bam_handle) { + bam.phys_addr = msm_uport->bam_mem; + bam.virt_addr = msm_uport->bam_base; + /* + * This event thresold value is only significant for BAM-to-BAM + * transfer. It's ignored for BAM-to-System mode transfer. + */ + bam.event_threshold = 0x10; /* Pipe event threshold */ + bam.summing_threshold = 1; /* BAM event threshold */ + + /* SPS driver wll handle the UART BAM IRQ */ + bam.irq = (u32)msm_uport->bam_irq; + bam.manage = SPS_BAM_MGR_DEVICE_REMOTE; + + MSM_HS_DBG("msm_serial_hs: bam physical base=0x%pa\n", + &bam.phys_addr); + MSM_HS_DBG("msm_serial_hs: bam virtual base=0x%p\n", + bam.virt_addr); + + /* Register UART Peripheral BAM device to SPS driver */ + rc = sps_register_bam_device(&bam, &bam_handle); + if (rc) { + MSM_HS_ERR("%s: BAM device register failed\n", + __func__); + return rc; + } + MSM_HS_DBG("%s:BAM device registered. bam_handle=0x%lx", + __func__, msm_uport->bam_handle); + } + msm_uport->bam_handle = bam_handle; + + rc = msm_hs_sps_init_ep_conn(msm_uport, &msm_uport->rx.prod, + UART_SPS_PROD_PERIPHERAL); + if (rc) { + MSM_HS_ERR("%s: Failed to Init Producer BAM-pipe", __func__); + goto deregister_bam; + } + + rc = msm_hs_sps_init_ep_conn(msm_uport, &msm_uport->tx.cons, + UART_SPS_CONS_PERIPHERAL); + if (rc) { + MSM_HS_ERR("%s: Failed to Init Consumer BAM-pipe", __func__); + goto deinit_ep_conn_prod; + } + return 0; + +deinit_ep_conn_prod: + msm_hs_exit_ep_conn(msm_uport, &msm_uport->rx.prod); +deregister_bam: + sps_deregister_bam_device(msm_uport->bam_handle); + return rc; +} + + +static bool deviceid[UARTDM_NR] = {0}; +/* + * The mutex synchronizes grabbing next free device number + * both in case of an alias being used or not. When alias is + * used, the msm_hs_dt_to_pdata gets it and the boolean array + * is accordingly updated with device_id_set_used. If no alias + * is used, then device_id_grab_next_free sets that array. + */ +static DEFINE_MUTEX(mutex_next_device_id); + +static int device_id_grab_next_free(void) +{ + int i; + int ret = -ENODEV; + mutex_lock(&mutex_next_device_id); + for (i = 0; i < UARTDM_NR; i++) + if (!deviceid[i]) { + ret = i; + deviceid[i] = true; + break; + } + mutex_unlock(&mutex_next_device_id); + return ret; +} + +static int device_id_set_used(int index) +{ + int ret = 0; + mutex_lock(&mutex_next_device_id); + if (deviceid[index]) + ret = -ENODEV; + else + deviceid[index] = true; + mutex_unlock(&mutex_next_device_id); + return ret; +} + +static void obs_manage_irq(struct msm_hs_port *msm_uport, bool en) +{ + struct uart_port *uport = &(msm_uport->uport); + + if (msm_uport->obs) { + if (en) + enable_irq(uport->irq); + else + disable_irq(uport->irq); + } +} + +static void msm_hs_pm_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_hs_port *msm_uport = get_matching_hs_port(pdev); + int ret; + int client_count = 0; + + if (!msm_uport) + goto err_suspend; + mutex_lock(&msm_uport->mtx); + + client_count = atomic_read(&msm_uport->client_count); + msm_uport->pm_state = MSM_HS_PM_SUSPENDED; + msm_hs_resource_off(msm_uport); + obs_manage_irq(msm_uport, false); + msm_hs_clk_bus_unvote(msm_uport); + + /* For OBS, don't use wakeup interrupt, set gpio to suspended state */ + if (msm_uport->obs) { + ret = pinctrl_select_state(msm_uport->pinctrl, + msm_uport->gpio_state_suspend); + if (ret) + MSM_HS_ERR("%s():Error selecting pinctrl suspend state", + __func__); + } + + if (!atomic_read(&msm_uport->client_req_state)) + enable_wakeup_interrupt(msm_uport); + LOG_USR_MSG(msm_uport->ipc_msm_hs_pwr_ctxt, + "%s: PM State Suspended client_count %d\n", __func__, + client_count); + mutex_unlock(&msm_uport->mtx); + return; +err_suspend: + pr_err("%s(): invalid uport", __func__); + return; +} + +static int msm_hs_pm_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_hs_port *msm_uport = get_matching_hs_port(pdev); + int ret = 0; + int client_count = 0; + + if (!msm_uport) { + dev_err(dev, "%s:Invalid uport\n", __func__); + return -ENODEV; + } + + mutex_lock(&msm_uport->mtx); + client_count = atomic_read(&msm_uport->client_count); + if (msm_uport->pm_state == MSM_HS_PM_ACTIVE) + goto exit_pm_resume; + if (!atomic_read(&msm_uport->client_req_state)) + disable_wakeup_interrupt(msm_uport); + + /* For OBS, don't use wakeup interrupt, set gpio to active state */ + if (msm_uport->obs) { + ret = pinctrl_select_state(msm_uport->pinctrl, + msm_uport->gpio_state_active); + if (ret) + MSM_HS_ERR("%s():Error selecting active state", + __func__); + } + + ret = msm_hs_clk_bus_vote(msm_uport); + if (ret) { + MSM_HS_ERR("%s:Failed clock vote %d\n", __func__, ret); + dev_err(dev, "%s:Failed clock vote %d\n", __func__, ret); + goto exit_pm_resume; + } + obs_manage_irq(msm_uport, true); + msm_uport->pm_state = MSM_HS_PM_ACTIVE; + msm_hs_resource_on(msm_uport); + + LOG_USR_MSG(msm_uport->ipc_msm_hs_pwr_ctxt, + "%s:PM State:Active client_count %d\n", __func__, client_count); +exit_pm_resume: + msm_uport->sys_suspend_noirq_cnt = 0; + mutex_unlock(&msm_uport->mtx); + return ret; +} + +#ifdef CONFIG_PM +static int msm_hs_pm_sys_suspend_noirq(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_hs_port *msm_uport = get_matching_hs_port(pdev); + int clk_cnt, client_count, ret = 0; + + if (IS_ERR_OR_NULL(msm_uport)) + return -ENODEV; + mutex_lock(&msm_uport->mtx); + /* + * If there is an active clk request or an impending userspace request + * fail the suspend callback. + */ + clk_cnt = atomic_read(&msm_uport->resource_count); + client_count = atomic_read(&msm_uport->client_count); + if (msm_uport->pm_state == MSM_HS_PM_ACTIVE) { + if (clk_cnt == 0 && client_count == 0) + msm_uport->sys_suspend_noirq_cnt++; + /*Serve force suspend post autosuspend timer expires + */ + if (msm_uport->sys_suspend_noirq_cnt >= 2) { + msm_uport->pm_state = MSM_HS_PM_SYS_SUSPENDED; + msm_uport->sys_suspend_noirq_cnt = 0; + mutex_unlock(&msm_uport->mtx); + + msm_hs_pm_suspend(dev); + /* + * Synchronize RT-pm and system-pm, RT-PM thinks that + * we are active. The three calls below let the RT-PM + * know that we are suspended already without calling + * suspend callback + */ + pm_runtime_disable(dev); + pm_runtime_set_suspended(dev); + pm_runtime_enable(dev); + + /*To Balance out exit time Mutex unlock */ + mutex_lock(&msm_uport->mtx); + } else { + ret = -EBUSY; + } + } + mutex_unlock(&msm_uport->mtx); + if (ret) + MSM_HS_WARN("%s:Fail Suspend.clk_cnt:%d,clnt_count:%d\n", + __func__, clk_cnt, client_count); + else + LOG_USR_MSG(msm_uport->ipc_msm_hs_pwr_ctxt, + "%s:PM State:Sys-Suspended client_count %d\n", + __func__, client_count); + return ret; +}; + +static int msm_hs_pm_sys_resume_noirq(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_hs_port *msm_uport = get_matching_hs_port(pdev); + + if (IS_ERR_OR_NULL(msm_uport)) + return -ENODEV; + /* + * Note system-pm resume and update the state + * variable. Resource activation will be done + * when transfer is requested. + */ + + mutex_lock(&msm_uport->mtx); + if (msm_uport->pm_state == MSM_HS_PM_SYS_SUSPENDED) + msm_uport->pm_state = MSM_HS_PM_SUSPENDED; + LOG_USR_MSG(msm_uport->ipc_msm_hs_pwr_ctxt, + "%s:PM State: Suspended\n", __func__); + mutex_unlock(&msm_uport->mtx); + return 0; +} +#endif + +#ifdef CONFIG_PM +static void msm_serial_hs_rt_init(struct uart_port *uport) +{ + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + + MSM_HS_INFO("%s(): Enabling runtime pm", __func__); + pm_runtime_set_suspended(uport->dev); + pm_runtime_set_autosuspend_delay(uport->dev, 100); + pm_runtime_use_autosuspend(uport->dev); + mutex_lock(&msm_uport->mtx); + msm_uport->pm_state = MSM_HS_PM_SUSPENDED; + mutex_unlock(&msm_uport->mtx); + pm_runtime_enable(uport->dev); + tty_port_set_policy(&uport->state->port, SCHED_FIFO, 1); +} + +static int msm_hs_runtime_suspend(struct device *dev) +{ + msm_hs_pm_suspend(dev); + return 0; +} + +static int msm_hs_runtime_resume(struct device *dev) +{ + return msm_hs_pm_resume(dev); +} +#else +static void msm_serial_hs_rt_init(struct uart_port *uport) {} +static int msm_hs_runtime_suspend(struct device *dev) {} +static int msm_hs_runtime_resume(struct device *dev) {} +#endif + + +static int msm_hs_probe(struct platform_device *pdev) +{ + int ret = 0; + struct uart_port *uport; + struct msm_hs_port *msm_uport; + struct resource *core_resource; + struct resource *bam_resource; + int core_irqres, bam_irqres, wakeup_irqres; + struct msm_serial_hs_platform_data *pdata = pdev->dev.platform_data; + unsigned long data; + char name[30]; + char boot_marker[40]; + + if (pdev->dev.of_node) { + dev_dbg(&pdev->dev, "device tree enabled\n"); + pdata = msm_hs_dt_to_pdata(pdev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + + if (pdev->id < 0) { + pdev->id = device_id_grab_next_free(); + if (pdev->id < 0) { + dev_err(&pdev->dev, + "Error grabbing next free device id"); + return pdev->id; + } + } else { + ret = device_id_set_used(pdev->id); + if (ret < 0) { + dev_err(&pdev->dev, "%d alias taken", + pdev->id); + return ret; + } + } + pdev->dev.platform_data = pdata; + } + + snprintf(boot_marker, sizeof(boot_marker), + "M - DRIVER MSM HS-UART_%d Init", pdev->id); + place_marker(boot_marker); + + if (pdev->id < 0 || pdev->id >= UARTDM_NR) { + dev_err(&pdev->dev, "Invalid plaform device ID = %d\n", + pdev->id); + return -EINVAL; + } + + msm_uport = devm_kzalloc(&pdev->dev, sizeof(struct msm_hs_port), + GFP_KERNEL); + if (!msm_uport) { + dev_err(&pdev->dev, "Memory allocation failed\n"); + return -ENOMEM; + } + + msm_uport->uport.type = PORT_UNKNOWN; + uport = &msm_uport->uport; + uport->dev = &pdev->dev; + + if (pdev->dev.of_node) + msm_uport->uart_type = BLSP_HSUART; + + msm_hs_get_pinctrl_configs(uport); + /* Get required resources for BAM HSUART */ + core_resource = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "core_mem"); + if (!core_resource) { + dev_err(&pdev->dev, "Invalid core HSUART Resources.\n"); + return -ENXIO; + } + bam_resource = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "bam_mem"); + if (!bam_resource) { + dev_err(&pdev->dev, "Invalid BAM HSUART Resources.\n"); + return -ENXIO; + } + core_irqres = platform_get_irq_byname(pdev, "core_irq"); + if (core_irqres < 0) { + dev_err(&pdev->dev, "Error %d, invalid core irq resources.\n", + core_irqres); + return -ENXIO; + } + bam_irqres = platform_get_irq_byname(pdev, "bam_irq"); + if (bam_irqres < 0) { + dev_err(&pdev->dev, "Error %d, invalid bam irq resources.\n", + bam_irqres); + return -ENXIO; + } + wakeup_irqres = platform_get_irq_byname(pdev, "wakeup_irq"); + if (wakeup_irqres < 0) { + wakeup_irqres = -1; + pr_info("Wakeup irq not specified.\n"); + } + + uport->mapbase = core_resource->start; + + uport->membase = ioremap(uport->mapbase, + resource_size(core_resource)); + if (unlikely(!uport->membase)) { + dev_err(&pdev->dev, "UART Resource ioremap Failed.\n"); + return -ENOMEM; + } + msm_uport->bam_mem = bam_resource->start; + msm_uport->bam_base = ioremap(msm_uport->bam_mem, + resource_size(bam_resource)); + if (unlikely(!msm_uport->bam_base)) { + dev_err(&pdev->dev, "UART BAM Resource ioremap Failed.\n"); + iounmap(uport->membase); + return -ENOMEM; + } + + memset(name, 0, sizeof(name)); + scnprintf(name, sizeof(name), "%s%s", dev_name(msm_uport->uport.dev), + "_state"); + msm_uport->ipc_msm_hs_log_ctxt = + ipc_log_context_create(IPC_MSM_HS_LOG_STATE_PAGES, + name, 0); + if (!msm_uport->ipc_msm_hs_log_ctxt) { + dev_err(&pdev->dev, "%s: error creating logging context", + __func__); + } else { + msm_uport->ipc_debug_mask = INFO_LEV; + ret = sysfs_create_file(&pdev->dev.kobj, + &dev_attr_debug_mask.attr); + if (unlikely(ret)) + MSM_HS_WARN("%s: Failed to create dev. attr", __func__); + } + + uport->irq = core_irqres; + msm_uport->bam_irq = bam_irqres; + pdata->wakeup_irq = wakeup_irqres; + + msm_uport->bus_scale_table = msm_bus_cl_get_pdata(pdev); + if (!msm_uport->bus_scale_table) { + MSM_HS_ERR("BLSP UART: Bus scaling is disabled.\n"); + } else { + msm_uport->bus_perf_client = + msm_bus_scale_register_client + (msm_uport->bus_scale_table); + if (IS_ERR(&msm_uport->bus_perf_client)) { + MSM_HS_ERR("%s():Bus client register failed\n", + __func__); + ret = -EINVAL; + goto unmap_memory; + } + } + + msm_uport->wakeup.irq = pdata->wakeup_irq; + msm_uport->wakeup.ignore = 1; + msm_uport->wakeup.inject_rx = pdata->inject_rx_on_wakeup; + msm_uport->wakeup.rx_to_inject = pdata->rx_to_inject; + msm_uport->obs = pdata->obs; + + msm_uport->bam_tx_ep_pipe_index = + pdata->bam_tx_ep_pipe_index; + msm_uport->bam_rx_ep_pipe_index = + pdata->bam_rx_ep_pipe_index; + msm_uport->wakeup.enabled = true; + + uport->iotype = UPIO_MEM; + uport->fifosize = 64; + uport->ops = &msm_hs_ops; + uport->flags = UPF_BOOT_AUTOCONF; + uport->uartclk = 7372800; + msm_uport->imr_reg = 0x0; + + msm_uport->clk = clk_get(&pdev->dev, "core_clk"); + if (IS_ERR(msm_uport->clk)) { + ret = PTR_ERR(msm_uport->clk); + goto deregister_bus_client; + } + + msm_uport->pclk = clk_get(&pdev->dev, "iface_clk"); + /* + * Some configurations do not require explicit pclk control so + * do not flag error on pclk get failure. + */ + if (IS_ERR(msm_uport->pclk)) + msm_uport->pclk = NULL; + + msm_uport->hsuart_wq = alloc_workqueue("k_hsuart", + WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + if (!msm_uport->hsuart_wq) { + MSM_HS_ERR("%s(): Unable to create workqueue hsuart_wq\n", + __func__); + ret = -ENOMEM; + goto put_clk; + } + + mutex_init(&msm_uport->mtx); + + /* Initialize SPS HW connected with UART core */ + ret = msm_hs_sps_init(msm_uport); + if (unlikely(ret)) { + MSM_HS_ERR("SPS Initialization failed ! err=%d", ret); + goto destroy_mutex; + } + + msm_uport->tx.flush = FLUSH_SHUTDOWN; + msm_uport->rx.flush = FLUSH_SHUTDOWN; + + memset(name, 0, sizeof(name)); + scnprintf(name, sizeof(name), "%s%s", dev_name(msm_uport->uport.dev), + "_tx"); + msm_uport->tx.ipc_tx_ctxt = + ipc_log_context_create(IPC_MSM_HS_LOG_DATA_PAGES, name, 0); + if (!msm_uport->tx.ipc_tx_ctxt) + dev_err(&pdev->dev, "%s: error creating tx logging context", + __func__); + + memset(name, 0, sizeof(name)); + scnprintf(name, sizeof(name), "%s%s", dev_name(msm_uport->uport.dev), + "_rx"); + msm_uport->rx.ipc_rx_ctxt = ipc_log_context_create( + IPC_MSM_HS_LOG_DATA_PAGES, name, 0); + if (!msm_uport->rx.ipc_rx_ctxt) + dev_err(&pdev->dev, "%s: error creating rx logging context", + __func__); + + memset(name, 0, sizeof(name)); + scnprintf(name, sizeof(name), "%s%s", dev_name(msm_uport->uport.dev), + "_pwr"); + msm_uport->ipc_msm_hs_pwr_ctxt = ipc_log_context_create( + IPC_MSM_HS_LOG_USER_PAGES, name, 0); + if (!msm_uport->ipc_msm_hs_pwr_ctxt) + dev_err(&pdev->dev, "%s: error creating usr logging context", + __func__); + + uport->irq = core_irqres; + msm_uport->bam_irq = bam_irqres; + + clk_set_rate(msm_uport->clk, msm_uport->uport.uartclk); + msm_hs_clk_bus_vote(msm_uport); + ret = uartdm_init_port(uport); + if (unlikely(ret)) + goto err_clock; + + /* configure the CR Protection to Enable */ + msm_hs_write(uport, UART_DM_CR, CR_PROTECTION_EN); + + /* + * Enable Command register protection before going ahead as this hw + * configuration makes sure that issued cmd to CR register gets complete + * before next issued cmd start. Hence mb() requires here. + */ + mb(); + + /* + * Set RX_BREAK_ZERO_CHAR_OFF and RX_ERROR_CHAR_OFF + * so any rx_break and character having parity of framing + * error don't enter inside UART RX FIFO. + */ + data = msm_hs_read(uport, UART_DM_MR2); + data |= (UARTDM_MR2_RX_BREAK_ZERO_CHAR_OFF | + UARTDM_MR2_RX_ERROR_CHAR_OFF); + msm_hs_write(uport, UART_DM_MR2, data); + /* Ensure register IO completion */ + mb(); + + ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_clock.attr); + if (unlikely(ret)) { + MSM_HS_ERR("Probe Failed as sysfs failed\n"); + goto err_clock; + } + + msm_serial_debugfs_init(msm_uport, pdev->id); + msm_hs_unconfig_uart_gpios(uport); + + uport->line = pdev->id; + if (pdata->userid && pdata->userid <= UARTDM_NR) + uport->line = pdata->userid; + ret = uart_add_one_port(&msm_hs_driver, uport); + if (!ret) { + msm_hs_clk_bus_unvote(msm_uport); + msm_serial_hs_rt_init(uport); + snprintf(boot_marker, sizeof(boot_marker), + "M - DRIVER MSM HS-UART_%d Ready", pdev->id); + place_marker(boot_marker); + return ret; + } + +err_clock: + msm_hs_clk_bus_unvote(msm_uport); + +destroy_mutex: + mutex_destroy(&msm_uport->mtx); + destroy_workqueue(msm_uport->hsuart_wq); + +put_clk: + if (msm_uport->pclk) + clk_put(msm_uport->pclk); + + if (msm_uport->clk) + clk_put(msm_uport->clk); + +deregister_bus_client: + msm_bus_scale_unregister_client(msm_uport->bus_perf_client); +unmap_memory: + iounmap(uport->membase); + iounmap(msm_uport->bam_base); + + return ret; +} + +static int __init msm_serial_hs_init(void) +{ + int ret; + + ret = uart_register_driver(&msm_hs_driver); + if (unlikely(ret)) { + pr_err("%s failed to load\n", __func__); + return ret; + } + debug_base = debugfs_create_dir("msm_serial_hs", NULL); + if (IS_ERR_OR_NULL(debug_base)) + pr_err("msm_serial_hs: Cannot create debugfs dir\n"); + + ret = platform_driver_register(&msm_serial_hs_platform_driver); + if (ret) { + pr_err("%s failed to load\n", __func__); + debugfs_remove_recursive(debug_base); + uart_unregister_driver(&msm_hs_driver); + return ret; + } + + pr_info("msm_serial_hs module loaded\n"); + return ret; +} + +/* + * Called by the upper layer when port is closed. + * - Disables the port + * - Unhook the ISR + */ +static void msm_hs_shutdown(struct uart_port *uport) +{ + int ret, rc; + struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); + struct circ_buf *tx_buf = &uport->state->xmit; + int data; + unsigned long flags; + + if (is_use_low_power_wakeup(msm_uport)) + irq_set_irq_wake(msm_uport->wakeup.irq, 0); + + if (msm_uport->wakeup.enabled) + disable_irq(msm_uport->wakeup.irq); + else + disable_irq(uport->irq); + + spin_lock_irqsave(&uport->lock, flags); + msm_uport->wakeup.enabled = false; + msm_uport->wakeup.ignore = 1; + spin_unlock_irqrestore(&uport->lock, flags); + + /* Free the interrupt */ + free_irq(uport->irq, msm_uport); + if (is_use_low_power_wakeup(msm_uport)) { + free_irq(msm_uport->wakeup.irq, msm_uport); + MSM_HS_DBG("%s(): wakeup irq freed", __func__); + } + msm_uport->wakeup.freed = true; + + /* make sure tx lh finishes */ + flush_kthread_worker(&msm_uport->tx.kworker); + ret = wait_event_timeout(msm_uport->tx.wait, + uart_circ_empty(tx_buf), 500); + if (!ret) + MSM_HS_WARN("Shutdown called when tx buff not empty"); + + msm_hs_resource_vote(msm_uport); + /* Stop remote side from sending data */ + msm_hs_disable_flow_control(uport, false); + /* make sure rx lh finishes */ + flush_kthread_worker(&msm_uport->rx.kworker); + + if (msm_uport->rx.flush != FLUSH_SHUTDOWN) { + /* disable and disconnect rx */ + ret = wait_event_timeout(msm_uport->rx.wait, + !msm_uport->rx.pending_flag, 500); + if (!ret) + MSM_HS_WARN("%s(): rx disconnect not complete", + __func__); + msm_hs_disconnect_rx(uport); + } else { + MSM_HS_DBG("%s(): Rx Flush is in Proper state=%d\n", + __func__, msm_uport->rx.flush); + } + + if (cancel_delayed_work_sync(&msm_uport->rx.flip_insert_work)) + MSM_HS_DBG("%s(): Work was pending, canceled it\n", + __func__); + flush_workqueue(msm_uport->hsuart_wq); + + /* BAM Disconnect for TX */ + data = msm_hs_read(uport, UART_DM_DMEN); + data &= ~UARTDM_TX_BAM_ENABLE_BMSK; + msm_hs_write(uport, UART_DM_DMEN, data); + ret = sps_tx_disconnect(msm_uport); + if (ret) + MSM_HS_ERR("%s(): sps_disconnect failed\n", + __func__); + msm_uport->tx.flush = FLUSH_SHUTDOWN; + /* Disable the transmitter */ + msm_hs_write(uport, UART_DM_CR, UARTDM_CR_TX_DISABLE_BMSK); + /* Disable the receiver */ + msm_hs_write(uport, UART_DM_CR, UARTDM_CR_RX_DISABLE_BMSK); + + msm_uport->imr_reg = 0; + msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg); + /* + * Complete all device write before actually disabling uartclk. + * Hence mb() requires here. + */ + mb(); + + msm_uport->rx.buffer_pending = NONE_PENDING; + MSM_HS_DBG("%s(): tx, rx events complete", __func__); + + dma_unmap_single(uport->dev, msm_uport->tx.dma_base, + UART_XMIT_SIZE, DMA_TO_DEVICE); + + msm_hs_resource_unvote(msm_uport); + rc = atomic_read(&msm_uport->resource_count); + if (rc) { + atomic_set(&msm_uport->resource_count, 1); + MSM_HS_WARN("%s(): removing extra vote\n", __func__); + msm_hs_resource_unvote(msm_uport); + } + if (atomic_read(&msm_uport->client_req_state)) { + MSM_HS_WARN("%s: Client clock vote imbalance\n", __func__); + atomic_set(&msm_uport->client_req_state, 0); + } + if (atomic_read(&msm_uport->client_count)) { + MSM_HS_WARN("%s: Client vote on, forcing to 0\n", __func__); + atomic_set(&msm_uport->client_count, 0); + } + msm_hs_unconfig_uart_gpios(uport); + LOG_USR_MSG(msm_uport->ipc_msm_hs_pwr_ctxt, + "%s:UART port closed, Client_Count 0\n", __func__); +} + +static void __exit msm_serial_hs_exit(void) +{ + pr_info("msm_serial_hs module removed\n"); + debugfs_remove_recursive(debug_base); + platform_driver_unregister(&msm_serial_hs_platform_driver); + uart_unregister_driver(&msm_hs_driver); +} + +static const struct dev_pm_ops msm_hs_dev_pm_ops = { + .runtime_suspend = msm_hs_runtime_suspend, + .runtime_resume = msm_hs_runtime_resume, + .runtime_idle = NULL, + .suspend_noirq = msm_hs_pm_sys_suspend_noirq, + .resume_noirq = msm_hs_pm_sys_resume_noirq, +}; + +static struct platform_driver msm_serial_hs_platform_driver = { + .probe = msm_hs_probe, + .remove = msm_hs_remove, + .driver = { + .name = "msm_serial_hs", + .pm = &msm_hs_dev_pm_ops, + .of_match_table = msm_hs_match_table, + }, +}; + +static struct uart_driver msm_hs_driver = { + .owner = THIS_MODULE, + .driver_name = "msm_serial_hs", + .dev_name = "ttyHS", + .nr = UARTDM_NR, + .cons = 0, +}; + +static struct uart_ops msm_hs_ops = { + .tx_empty = msm_hs_tx_empty, + .set_mctrl = msm_hs_set_mctrl_locked, + .get_mctrl = msm_hs_get_mctrl_locked, + .stop_tx = msm_hs_stop_tx_locked, + .start_tx = msm_hs_start_tx_locked, + .stop_rx = msm_hs_stop_rx_locked, + .enable_ms = msm_hs_enable_ms_locked, + .break_ctl = msm_hs_break_ctl, + .startup = msm_hs_startup, + .shutdown = msm_hs_shutdown, + .set_termios = msm_hs_set_termios, + .type = msm_hs_type, + .config_port = msm_hs_config_port, + .flush_buffer = NULL, + .ioctl = msm_hs_ioctl, +}; + +module_init(msm_serial_hs_init); +module_exit(msm_serial_hs_exit); +MODULE_DESCRIPTION("High Speed UART Driver for the MSM chipset"); +MODULE_VERSION("1.2"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/tty/serial/msm_serial_hs_hwreg.h b/drivers/tty/serial/msm_serial_hs_hwreg.h new file mode 100644 index 000000000000..046a346cae0c --- /dev/null +++ b/drivers/tty/serial/msm_serial_hs_hwreg.h @@ -0,0 +1,283 @@ +/* drivers/serial/msm_serial_hs_hwreg.h + * + * Copyright (c) 2007-2009, 2012-2014,The Linux Foundation. All rights reserved. + * + * All source code in this file is licensed under the following license + * except where indicated. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, you can find it at http://www.fsf.org + */ + +#ifndef MSM_SERIAL_HS_HWREG_H +#define MSM_SERIAL_HS_HWREG_H + +#define GSBI_CONTROL_ADDR 0x0 +#define GSBI_PROTOCOL_CODE_MASK 0x30 +#define GSBI_PROTOCOL_I2C_UART 0x60 +#define GSBI_PROTOCOL_UART 0x40 +#define GSBI_PROTOCOL_IDLE 0x0 + +#define TCSR_ADM_1_A_CRCI_MUX_SEL 0x78 +#define TCSR_ADM_1_B_CRCI_MUX_SEL 0x7C +#define ADM1_CRCI_GSBI6_RX_SEL 0x800 +#define ADM1_CRCI_GSBI6_TX_SEL 0x400 + +#define MSM_ENABLE_UART_CLOCK TIOCPMGET +#define MSM_DISABLE_UART_CLOCK TIOCPMPUT +#define MSM_GET_UART_CLOCK_STATUS TIOCPMACT + +enum msm_hsl_regs { + UARTDM_MR1, + UARTDM_MR2, + UARTDM_IMR, + UARTDM_SR, + UARTDM_CR, + UARTDM_CSR, + UARTDM_IPR, + UARTDM_ISR, + UARTDM_RX_TOTAL_SNAP, + UARTDM_RFWR, + UARTDM_TFWR, + UARTDM_RF, + UARTDM_TF, + UARTDM_MISR, + UARTDM_DMRX, + UARTDM_NCF_TX, + UARTDM_DMEN, + UARTDM_BCR, + UARTDM_TXFS, + UARTDM_RXFS, + UARTDM_LAST, +}; + +enum msm_hs_regs { + UART_DM_MR1 = 0x0, + UART_DM_MR2 = 0x4, + UART_DM_IMR = 0xb0, + UART_DM_SR = 0xa4, + UART_DM_CR = 0xa8, + UART_DM_CSR = 0xa0, + UART_DM_IPR = 0x18, + UART_DM_ISR = 0xb4, + UART_DM_RX_TOTAL_SNAP = 0xbc, + UART_DM_TFWR = 0x1c, + UART_DM_RFWR = 0x20, + UART_DM_RF = 0x140, + UART_DM_TF = 0x100, + UART_DM_MISR = 0xac, + UART_DM_DMRX = 0x34, + UART_DM_NCF_TX = 0x40, + UART_DM_DMEN = 0x3c, + UART_DM_TXFS = 0x4c, + UART_DM_RXFS = 0x50, + UART_DM_RX_TRANS_CTRL = 0xcc, + UART_DM_BCR = 0xc8, +}; + +#define UARTDM_MR1_ADDR 0x0 +#define UARTDM_MR2_ADDR 0x4 + +/* Backward Compatability Register for UARTDM Core v1.4 */ +#define UARTDM_BCR_ADDR 0xc8 + +/* + * UARTDM Core v1.4 STALE_IRQ_EMPTY bit defination + * Stale interrupt will fire if bit is set when RX-FIFO is empty + */ +#define UARTDM_BCR_TX_BREAK_DISABLE 0x1 +#define UARTDM_BCR_STALE_IRQ_EMPTY 0x2 +#define UARTDM_BCR_RX_DMRX_LOW_EN 0x4 +#define UARTDM_BCR_RX_STAL_IRQ_DMRX_EQL 0x10 +#define UARTDM_BCR_RX_DMRX_1BYTE_RES_EN 0x20 + +/* TRANSFER_CONTROL Register for UARTDM Core v1.4 */ +#define UARTDM_RX_TRANS_CTRL_ADDR 0xcc + +/* TRANSFER_CONTROL Register bits */ +#define RX_STALE_AUTO_RE_EN 0x1 +#define RX_TRANS_AUTO_RE_ACTIVATE 0x2 +#define RX_DMRX_CYCLIC_EN 0x4 + +/* write only register */ +#define UARTDM_CSR_115200 0xFF +#define UARTDM_CSR_57600 0xEE +#define UARTDM_CSR_38400 0xDD +#define UARTDM_CSR_28800 0xCC +#define UARTDM_CSR_19200 0xBB +#define UARTDM_CSR_14400 0xAA +#define UARTDM_CSR_9600 0x99 +#define UARTDM_CSR_7200 0x88 +#define UARTDM_CSR_4800 0x77 +#define UARTDM_CSR_3600 0x66 +#define UARTDM_CSR_2400 0x55 +#define UARTDM_CSR_1200 0x44 +#define UARTDM_CSR_600 0x33 +#define UARTDM_CSR_300 0x22 +#define UARTDM_CSR_150 0x11 +#define UARTDM_CSR_75 0x00 + +/* write only register */ +#define UARTDM_IPR_ADDR 0x18 +#define UARTDM_TFWR_ADDR 0x1c +#define UARTDM_RFWR_ADDR 0x20 +#define UARTDM_HCR_ADDR 0x24 +#define UARTDM_DMRX_ADDR 0x34 +#define UARTDM_DMEN_ADDR 0x3c + +/* UART_DM_NO_CHARS_FOR_TX */ +#define UARTDM_NCF_TX_ADDR 0x40 + +#define UARTDM_BADR_ADDR 0x44 + +#define UARTDM_SIM_CFG_ADDR 0x80 + +/* Read Only register */ +#define UARTDM_TXFS_ADDR 0x4C +#define UARTDM_RXFS_ADDR 0x50 + +/* Register field Mask Mapping */ +#define UARTDM_SR_RX_BREAK_BMSK BIT(6) +#define UARTDM_SR_PAR_FRAME_BMSK BIT(5) +#define UARTDM_SR_OVERRUN_BMSK BIT(4) +#define UARTDM_SR_TXEMT_BMSK BIT(3) +#define UARTDM_SR_TXRDY_BMSK BIT(2) +#define UARTDM_SR_RXRDY_BMSK BIT(0) + +#define UARTDM_CR_TX_DISABLE_BMSK BIT(3) +#define UARTDM_CR_RX_DISABLE_BMSK BIT(1) +#define UARTDM_CR_TX_EN_BMSK BIT(2) +#define UARTDM_CR_RX_EN_BMSK BIT(0) + +/* UARTDM_CR channel_comman bit value (register field is bits 8:4) */ +#define RESET_RX 0x10 +#define RESET_TX 0x20 +#define RESET_ERROR_STATUS 0x30 +#define RESET_BREAK_INT 0x40 +#define START_BREAK 0x50 +#define STOP_BREAK 0x60 +#define RESET_CTS 0x70 +#define RESET_STALE_INT 0x80 +#define RFR_LOW 0xD0 +#define RFR_HIGH 0xE0 +#define CR_PROTECTION_EN 0x100 +#define STALE_EVENT_ENABLE 0x500 +#define STALE_EVENT_DISABLE 0x600 +#define FORCE_STALE_EVENT 0x400 +#define CLEAR_TX_READY 0x300 +#define RESET_TX_ERROR 0x800 +#define RESET_TX_DONE 0x810 + +/* + * UARTDM_CR BAM IFC comman bit value + * for UARTDM Core v1.4 + */ +#define START_RX_BAM_IFC 0x850 +#define START_TX_BAM_IFC 0x860 + +#define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00 +#define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f +#define UARTDM_MR1_CTS_CTL_BMSK 0x40 +#define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80 + +/* + * UARTDM Core v1.4 MR2_RFR_CTS_LOOP bitmask + * Enables internal loopback between RFR_N of + * RX channel and CTS_N of TX channel. + */ +#define UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK 0x400 + +#define UARTDM_MR2_LOOP_MODE_BMSK 0x80 +#define UARTDM_MR2_ERROR_MODE_BMSK 0x40 +#define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30 +#define UARTDM_MR2_RX_ZERO_CHAR_OFF 0x100 +#define UARTDM_MR2_RX_ERROR_CHAR_OFF 0x200 +#define UARTDM_MR2_RX_BREAK_ZERO_CHAR_OFF 0x100 + +#define UARTDM_MR2_BITS_PER_CHAR_8 (0x3 << 4) + +/* bits per character configuration */ +#define FIVE_BPC (0 << 4) +#define SIX_BPC (1 << 4) +#define SEVEN_BPC (2 << 4) +#define EIGHT_BPC (3 << 4) + +#define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc +#define STOP_BIT_ONE (1 << 2) +#define STOP_BIT_TWO (3 << 2) + +#define UARTDM_MR2_PARITY_MODE_BMSK 0x3 + +/* Parity configuration */ +#define NO_PARITY 0x0 +#define EVEN_PARITY 0x2 +#define ODD_PARITY 0x1 +#define SPACE_PARITY 0x3 + +#define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80 +#define UARTDM_IPR_STALE_LSB_BMSK 0x1f + +/* These can be used for both ISR and IMR register */ +#define UARTDM_ISR_TX_READY_BMSK BIT(7) +#define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6) +#define UARTDM_ISR_DELTA_CTS_BMSK BIT(5) +#define UARTDM_ISR_RXLEV_BMSK BIT(4) +#define UARTDM_ISR_RXSTALE_BMSK BIT(3) +#define UARTDM_ISR_RXBREAK_BMSK BIT(2) +#define UARTDM_ISR_RXHUNT_BMSK BIT(1) +#define UARTDM_ISR_TXLEV_BMSK BIT(0) + +/* Field definitions for UART_DM_DMEN*/ +#define UARTDM_TX_DM_EN_BMSK 0x1 +#define UARTDM_RX_DM_EN_BMSK 0x2 + +/* + * UARTDM Core v1.4 bitmask + * Bitmasks for enabling Rx and Tx BAM Interface + */ +#define UARTDM_TX_BAM_ENABLE_BMSK 0x4 +#define UARTDM_RX_BAM_ENABLE_BMSK 0x8 + +/* Register offsets for UART Core v13 */ + +/* write only register */ +#define UARTDM_CSR_ADDR 0x8 + +/* write only register */ +#define UARTDM_TF_ADDR 0x70 +#define UARTDM_TF2_ADDR 0x74 +#define UARTDM_TF3_ADDR 0x78 +#define UARTDM_TF4_ADDR 0x7c + +/* write only register */ +#define UARTDM_CR_ADDR 0x10 +/* write only register */ +#define UARTDM_IMR_ADDR 0x14 +#define UARTDM_IRDA_ADDR 0x38 + +/* Read Only register */ +#define UARTDM_SR_ADDR 0x8 + +/* Read Only register */ +#define UARTDM_RF_ADDR 0x70 +#define UARTDM_RF2_ADDR 0x74 +#define UARTDM_RF3_ADDR 0x78 +#define UARTDM_RF4_ADDR 0x7c + +/* Read Only register */ +#define UARTDM_MISR_ADDR 0x10 + +/* Read Only register */ +#define UARTDM_ISR_ADDR 0x14 +#define UARTDM_RX_TOTAL_SNAP_ADDR 0x38 + +#endif /* MSM_SERIAL_HS_HWREG_H */ diff --git a/drivers/tty/serial/msm_smd_tty.c b/drivers/tty/serial/msm_smd_tty.c new file mode 100644 index 000000000000..0092437faaa2 --- /dev/null +++ b/drivers/tty/serial/msm_smd_tty.c @@ -0,0 +1,1045 @@ +/* Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009-2015, 2020, The Linux Foundation. All rights reserved. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/platform_device.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/ipc_logging.h> +#include <linux/of.h> +#include <linux/suspend.h> + +#include <linux/tty.h> +#include <linux/tty_driver.h> +#include <linux/tty_flip.h> + +#include <soc/qcom/smd.h> +#include <soc/qcom/smsm.h> +#include <soc/qcom/subsystem_restart.h> + +#define MODULE_NAME "msm_smdtty" +#define MAX_SMD_TTYS 37 +#define MAX_TTY_BUF_SIZE 2048 +#define TTY_PUSH_WS_DELAY 500 +#define TTY_PUSH_WS_POST_SUSPEND_DELAY 100 +#define MAX_RA_WAKE_LOCK_NAME_LEN 32 +#define SMD_TTY_LOG_PAGES 2 + +#define SMD_TTY_INFO(buf...) \ +do { \ + if (smd_tty_log_ctx) { \ + ipc_log_string(smd_tty_log_ctx, buf); \ + } \ +} while (0) + +#define SMD_TTY_ERR(buf...) \ +do { \ + if (smd_tty_log_ctx) \ + ipc_log_string(smd_tty_log_ctx, buf); \ + pr_err(buf); \ +} while (0) + +static void *smd_tty_log_ctx; +static bool smd_tty_in_suspend; +static bool smd_tty_read_in_suspend; +static struct wakeup_source read_in_suspend_ws; + +/** + * struct smd_tty_info - context for an individual SMD TTY device + * + * @ch: SMD channel handle + * @port: TTY port context structure + * @device_ptr: TTY device pointer + * @pending_ws: pending-data wakeup source + * @tty_tsklt: read tasklet + * @buf_req_timer: RX buffer retry timer + * @ch_allocated: completion set when SMD channel is allocated + * @pil: Peripheral Image Loader handle + * @edge: SMD edge associated with port + * @ch_name: SMD channel name associated with port + * @dev_name: SMD platform device name associated with port + * + * @open_lock_lha1: open/close lock - used to serialize open/close operations + * @open_wait: Timeout in seconds to wait for SMD port to be created / opened + * + * @reset_lock_lha2: lock for reset and open state + * @in_reset: True if SMD channel is closed / in SSR + * @in_reset_updated: reset state changed + * @is_open: True if SMD port is open + * @ch_opened_wait_queue: SMD port open/close wait queue + * + * @ra_lock_lha3: Read-available lock - used to synchronize reads from SMD + * @ra_wakeup_source_name: Name of the read-available wakeup source + * @ra_wakeup_source: Read-available wakeup source + */ +struct smd_tty_info { + smd_channel_t *ch; + struct tty_port port; + struct device *device_ptr; + struct wakeup_source pending_ws; + struct tasklet_struct tty_tsklt; + struct timer_list buf_req_timer; + struct completion ch_allocated; + void *pil; + uint32_t edge; + char ch_name[SMD_MAX_CH_NAME_LEN]; + char dev_name[SMD_MAX_CH_NAME_LEN]; + + struct mutex open_lock_lha1; + unsigned int open_wait; + + spinlock_t reset_lock_lha2; + int in_reset; + int in_reset_updated; + int is_open; + wait_queue_head_t ch_opened_wait_queue; + + spinlock_t ra_lock_lha3; + char ra_wakeup_source_name[MAX_RA_WAKE_LOCK_NAME_LEN]; + struct wakeup_source ra_wakeup_source; +}; + +/** + * struct smd_tty_pfdriver - SMD tty channel platform driver structure + * + * @list: Adds this structure into smd_tty_platform_driver_list::list. + * @ref_cnt: reference count for this structure. + * @driver: SMD channel platform driver context structure + */ +struct smd_tty_pfdriver { + struct list_head list; + int ref_cnt; + struct platform_driver driver; +}; + +#define LOOPBACK_IDX 36 + +static struct delayed_work loopback_work; +static struct smd_tty_info smd_tty[MAX_SMD_TTYS]; + +static DEFINE_MUTEX(smd_tty_pfdriver_lock_lha1); +static LIST_HEAD(smd_tty_pfdriver_list); + +static int is_in_reset(struct smd_tty_info *info) +{ + return info->in_reset; +} + +static void buf_req_retry(unsigned long param) +{ + struct smd_tty_info *info = (struct smd_tty_info *)param; + unsigned long flags; + + spin_lock_irqsave(&info->reset_lock_lha2, flags); + if (info->is_open) { + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); + tasklet_hi_schedule(&info->tty_tsklt); + return; + } + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); +} + +static ssize_t open_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t n) +{ + unsigned int num_dev; + unsigned long wait; + if (dev == NULL) { + SMD_TTY_INFO("%s: Invalid Device passed", __func__); + return -EINVAL; + } + for (num_dev = 0; num_dev < MAX_SMD_TTYS; num_dev++) { + if (dev == smd_tty[num_dev].device_ptr) + break; + } + if (num_dev >= MAX_SMD_TTYS) { + SMD_TTY_ERR("[%s]: Device Not found", __func__); + return -EINVAL; + } + if (!kstrtoul(buf, 10, &wait)) { + mutex_lock(&smd_tty[num_dev].open_lock_lha1); + smd_tty[num_dev].open_wait = wait; + mutex_unlock(&smd_tty[num_dev].open_lock_lha1); + return n; + } else { + SMD_TTY_INFO("[%s]: Unable to convert %s to an int", + __func__, buf); + return -EINVAL; + } +} + +static ssize_t open_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned int num_dev; + unsigned int open_wait; + + if (dev == NULL) { + SMD_TTY_INFO("%s: Invalid Device passed", __func__); + return -EINVAL; + } + for (num_dev = 0; num_dev < MAX_SMD_TTYS; num_dev++) { + if (dev == smd_tty[num_dev].device_ptr) + break; + } + if (num_dev >= MAX_SMD_TTYS) { + SMD_TTY_ERR("[%s]: Device Not Found", __func__); + return -EINVAL; + } + + mutex_lock(&smd_tty[num_dev].open_lock_lha1); + open_wait = smd_tty[num_dev].open_wait; + mutex_unlock(&smd_tty[num_dev].open_lock_lha1); + + return snprintf(buf, PAGE_SIZE, "%d\n", open_wait); +} + +static DEVICE_ATTR + (open_timeout, 0664, open_timeout_show, open_timeout_store); + +static void smd_tty_read(unsigned long param) +{ + unsigned char *ptr; + int avail; + struct smd_tty_info *info = (struct smd_tty_info *)param; + struct tty_struct *tty = tty_port_tty_get(&info->port); + unsigned long flags; + + if (!tty) + return; + + for (;;) { + if (is_in_reset(info)) { + /* signal TTY clients using TTY_BREAK */ + tty_insert_flip_char(tty->port, 0x00, TTY_BREAK); + tty_flip_buffer_push(tty->port); + break; + } + + if (test_bit(TTY_THROTTLED, &tty->flags)) + break; + spin_lock_irqsave(&info->ra_lock_lha3, flags); + avail = smd_read_avail(info->ch); + if (avail == 0) { + __pm_relax(&info->ra_wakeup_source); + spin_unlock_irqrestore(&info->ra_lock_lha3, flags); + break; + } + spin_unlock_irqrestore(&info->ra_lock_lha3, flags); + + if (avail > MAX_TTY_BUF_SIZE) + avail = MAX_TTY_BUF_SIZE; + + avail = tty_prepare_flip_string(tty->port, &ptr, avail); + if (avail <= 0) { + mod_timer(&info->buf_req_timer, + jiffies + msecs_to_jiffies(30)); + tty_kref_put(tty); + return; + } + + if (smd_read(info->ch, ptr, avail) != avail) { + /* shouldn't be possible since we're in interrupt + ** context here and nobody else could 'steal' our + ** characters. + */ + SMD_TTY_ERR( + "%s - Possible smd_tty_buffer mismatch for %s", + __func__, info->ch_name); + } + + /* + * Keep system awake long enough to allow the TTY + * framework to pass the flip buffer to any waiting + * userspace clients. + */ + __pm_wakeup_event(&info->pending_ws, TTY_PUSH_WS_DELAY); + + if (smd_tty_in_suspend) + smd_tty_read_in_suspend = true; + + tty_flip_buffer_push(tty->port); + } + + /* XXX only when writable and necessary */ + tty_wakeup(tty); + tty_kref_put(tty); +} + +static void smd_tty_notify(void *priv, unsigned event) +{ + struct smd_tty_info *info = priv; + struct tty_struct *tty; + unsigned long flags; + + switch (event) { + case SMD_EVENT_DATA: + spin_lock_irqsave(&info->reset_lock_lha2, flags); + if (!info->is_open) { + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); + break; + } + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); + /* There may be clients (tty framework) that are blocked + * waiting for space to write data, so if a possible read + * interrupt came in wake anyone waiting and disable the + * interrupts + */ + if (smd_write_avail(info->ch)) { + smd_disable_read_intr(info->ch); + tty = tty_port_tty_get(&info->port); + if (tty) + wake_up_interruptible(&tty->write_wait); + tty_kref_put(tty); + } + spin_lock_irqsave(&info->ra_lock_lha3, flags); + if (smd_read_avail(info->ch)) { + __pm_stay_awake(&info->ra_wakeup_source); + tasklet_hi_schedule(&info->tty_tsklt); + } + spin_unlock_irqrestore(&info->ra_lock_lha3, flags); + break; + + case SMD_EVENT_OPEN: + tty = tty_port_tty_get(&info->port); + spin_lock_irqsave(&info->reset_lock_lha2, flags); + if (tty) + clear_bit(TTY_OTHER_CLOSED, &tty->flags); + info->in_reset = 0; + info->in_reset_updated = 1; + info->is_open = 1; + wake_up_interruptible(&info->ch_opened_wait_queue); + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); + tty_kref_put(tty); + break; + + case SMD_EVENT_CLOSE: + spin_lock_irqsave(&info->reset_lock_lha2, flags); + info->in_reset = 1; + info->in_reset_updated = 1; + info->is_open = 0; + wake_up_interruptible(&info->ch_opened_wait_queue); + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); + + tty = tty_port_tty_get(&info->port); + if (tty) { + /* send TTY_BREAK through read tasklet */ + set_bit(TTY_OTHER_CLOSED, &tty->flags); + tasklet_hi_schedule(&info->tty_tsklt); + + if (tty->index == LOOPBACK_IDX) + schedule_delayed_work(&loopback_work, + msecs_to_jiffies(1000)); + } + tty_kref_put(tty); + break; + } +} + +static uint32_t is_modem_smsm_inited(void) +{ + uint32_t modem_state; + uint32_t ready_state = (SMSM_INIT | SMSM_SMDINIT); + + modem_state = smsm_get_state(SMSM_MODEM_STATE); + return (modem_state & ready_state) == ready_state; +} + +static int smd_tty_dummy_probe(struct platform_device *pdev) +{ + int n; + + for (n = 0; n < MAX_SMD_TTYS; ++n) { + if (smd_tty[n].dev_name == NULL) + continue; + + if (pdev->id == smd_tty[n].edge && + !strcmp(pdev->name, smd_tty[n].dev_name)) { + complete_all(&smd_tty[n].ch_allocated); + return 0; + } + } + SMD_TTY_ERR("[ERR]%s: unknown device '%s'\n", __func__, pdev->name); + + return -ENODEV; +} + +/** + * smd_tty_add_driver() - Add platform drivers for smd tty device + * + * @info: context for an individual SMD TTY device + * + * @returns: 0 for success, standard Linux error code otherwise + * + * This function is used to register platform driver once for all + * smd tty devices which have same names and increment the reference + * count for 2nd to nth devices. + */ +static int smd_tty_add_driver(struct smd_tty_info *info) +{ + int r = 0; + struct smd_tty_pfdriver *smd_tty_pfdriverp; + struct smd_tty_pfdriver *item; + + if (!info) { + pr_err("%s on a NULL device structure\n", __func__); + return -EINVAL; + } + + SMD_TTY_INFO("Begin %s on smd_tty[%s]\n", __func__, + info->ch_name); + + mutex_lock(&smd_tty_pfdriver_lock_lha1); + list_for_each_entry(item, &smd_tty_pfdriver_list, list) { + if (!strcmp(item->driver.driver.name, info->dev_name)) { + SMD_TTY_INFO("%s:%s Driver Already reg. cnt:%d\n", + __func__, info->ch_name, item->ref_cnt); + ++item->ref_cnt; + goto exit; + } + } + + smd_tty_pfdriverp = kzalloc(sizeof(*smd_tty_pfdriverp), GFP_KERNEL); + if (IS_ERR_OR_NULL(smd_tty_pfdriverp)) { + pr_err("%s: kzalloc() failed for smd_tty_pfdriver[%s]\n", + __func__, info->ch_name); + r = -ENOMEM; + goto exit; + } + + smd_tty_pfdriverp->driver.probe = smd_tty_dummy_probe; + smd_tty_pfdriverp->driver.driver.name = info->dev_name; + smd_tty_pfdriverp->driver.driver.owner = THIS_MODULE; + r = platform_driver_register(&smd_tty_pfdriverp->driver); + if (r) { + pr_err("%s: %s Platform driver reg. failed\n", + __func__, info->ch_name); + kfree(smd_tty_pfdriverp); + goto exit; + } + ++smd_tty_pfdriverp->ref_cnt; + list_add(&smd_tty_pfdriverp->list, &smd_tty_pfdriver_list); + +exit: + SMD_TTY_INFO("End %s on smd_tty_ch[%s]\n", __func__, info->ch_name); + mutex_unlock(&smd_tty_pfdriver_lock_lha1); + return r; +} + +/** + * smd_tty_remove_driver() - Remove the platform drivers for smd tty device + * + * @info: context for an individual SMD TTY device + * + * This function is used to decrement the reference count on + * platform drivers for smd pkt devices and removes the drivers + * when the reference count becomes zero. + */ +static void smd_tty_remove_driver(struct smd_tty_info *info) +{ + struct smd_tty_pfdriver *smd_tty_pfdriverp; + bool found_item = false; + + if (!info) { + pr_err("%s on a NULL device\n", __func__); + return; + } + + SMD_TTY_INFO("Begin %s on smd_tty_ch[%s]\n", __func__, + info->ch_name); + mutex_lock(&smd_tty_pfdriver_lock_lha1); + list_for_each_entry(smd_tty_pfdriverp, &smd_tty_pfdriver_list, list) { + if (!strcmp(smd_tty_pfdriverp->driver.driver.name, + info->dev_name)) { + found_item = true; + SMD_TTY_INFO("%s:%s Platform driver cnt:%d\n", + __func__, info->ch_name, + smd_tty_pfdriverp->ref_cnt); + if (smd_tty_pfdriverp->ref_cnt > 0) + --smd_tty_pfdriverp->ref_cnt; + else + pr_warn("%s reference count <= 0\n", __func__); + break; + } + } + if (!found_item) + SMD_TTY_ERR("%s:%s No item found in list.\n", + __func__, info->ch_name); + + if (found_item && smd_tty_pfdriverp->ref_cnt == 0) { + platform_driver_unregister(&smd_tty_pfdriverp->driver); + smd_tty_pfdriverp->driver.probe = NULL; + list_del(&smd_tty_pfdriverp->list); + kfree(smd_tty_pfdriverp); + } + mutex_unlock(&smd_tty_pfdriver_lock_lha1); + SMD_TTY_INFO("End %s on smd_tty_ch[%s]\n", __func__, info->ch_name); +} + +static int smd_tty_port_activate(struct tty_port *tport, + struct tty_struct *tty) +{ + int res = 0; + unsigned int n = tty->index; + struct smd_tty_info *info; + const char *peripheral = NULL; + + if (n >= MAX_SMD_TTYS || smd_tty[n].ch_name == NULL) + return -ENODEV; + + info = smd_tty + n; + + mutex_lock(&info->open_lock_lha1); + tty->driver_data = info; + + res = smd_tty_add_driver(info); + if (res) { + SMD_TTY_ERR("%s:%d Idx smd_tty_driver register failed %d\n", + __func__, n, res); + goto out; + } + + peripheral = smd_edge_to_pil_str(smd_tty[n].edge); + if (!IS_ERR_OR_NULL(peripheral)) { + info->pil = subsystem_get(peripheral); + if (IS_ERR(info->pil)) { + SMD_TTY_INFO( + "%s failed on smd_tty device :%s subsystem_get failed for %s", + __func__, info->ch_name, + peripheral); + + /* + * Sleep, inorder to reduce the frequency of + * retry by user-space modules and to avoid + * possible watchdog bite. + */ + msleep((smd_tty[n].open_wait * 1000)); + res = PTR_ERR(info->pil); + goto platform_unregister; + } + } + + /* Wait for the modem SMSM to be inited for the SMD + * Loopback channel to be allocated at the modem. Since + * the wait need to be done atmost once, using msleep + * doesn't degrade the performance. + */ + if (n == LOOPBACK_IDX) { + if (!is_modem_smsm_inited()) + msleep(5000); + smsm_change_state(SMSM_APPS_STATE, + 0, SMSM_SMD_LOOPBACK); + msleep(100); + } + + /* + * Wait for a channel to be allocated so we know + * the modem is ready enough. + */ + if (smd_tty[n].open_wait) { + res = wait_for_completion_interruptible_timeout( + &info->ch_allocated, + msecs_to_jiffies(smd_tty[n].open_wait * + 1000)); + + if (res == 0) { + SMD_TTY_INFO( + "Timed out waiting for SMD channel %s", + info->ch_name); + res = -ETIMEDOUT; + goto release_pil; + } else if (res < 0) { + SMD_TTY_INFO( + "Error waiting for SMD channel %s : %d\n", + info->ch_name, res); + goto release_pil; + } + } + + tasklet_init(&info->tty_tsklt, smd_tty_read, (unsigned long)info); + wakeup_source_init(&info->pending_ws, info->ch_name); + scnprintf(info->ra_wakeup_source_name, MAX_RA_WAKE_LOCK_NAME_LEN, + "SMD_TTY_%s_RA", info->ch_name); + wakeup_source_init(&info->ra_wakeup_source, + info->ra_wakeup_source_name); + + res = smd_named_open_on_edge(info->ch_name, + smd_tty[n].edge, &info->ch, info, + smd_tty_notify); + if (res < 0) { + SMD_TTY_INFO("%s: %s open failed %d\n", + __func__, info->ch_name, res); + goto release_wl_tl; + } + + res = wait_event_interruptible_timeout(info->ch_opened_wait_queue, + info->is_open, (2 * HZ)); + if (res == 0) + res = -ETIMEDOUT; + if (res < 0) { + SMD_TTY_INFO("%s: wait for %s smd_open failed %d\n", + __func__, info->ch_name, res); + goto close_ch; + } + SMD_TTY_INFO("%s with PID %u opened port %s", + current->comm, current->pid, info->ch_name); + smd_disable_read_intr(info->ch); + mutex_unlock(&info->open_lock_lha1); + return 0; + +close_ch: + smd_close(info->ch); + info->ch = NULL; + +release_wl_tl: + tasklet_kill(&info->tty_tsklt); + wakeup_source_trash(&info->pending_ws); + wakeup_source_trash(&info->ra_wakeup_source); + +release_pil: + subsystem_put(info->pil); + +platform_unregister: + smd_tty_remove_driver(info); + +out: + mutex_unlock(&info->open_lock_lha1); + + return res; +} + +static void smd_tty_port_shutdown(struct tty_port *tport) +{ + struct smd_tty_info *info; + struct tty_struct *tty = tty_port_tty_get(tport); + unsigned long flags; + + info = tty->driver_data; + if (info == 0) { + tty_kref_put(tty); + return; + } + + mutex_lock(&info->open_lock_lha1); + + spin_lock_irqsave(&info->reset_lock_lha2, flags); + info->is_open = 0; + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); + + tasklet_kill(&info->tty_tsklt); + wakeup_source_trash(&info->pending_ws); + wakeup_source_trash(&info->ra_wakeup_source); + + SMD_TTY_INFO("%s with PID %u closed port %s", + current->comm, current->pid, + info->ch_name); + tty->driver_data = NULL; + del_timer(&info->buf_req_timer); + + smd_close(info->ch); + info->ch = NULL; + subsystem_put(info->pil); + smd_tty_remove_driver(info); + + mutex_unlock(&info->open_lock_lha1); + tty_kref_put(tty); +} + +static int smd_tty_open(struct tty_struct *tty, struct file *f) +{ + struct smd_tty_info *info = smd_tty + tty->index; + + return tty_port_open(&info->port, tty, f); +} + +static void smd_tty_close(struct tty_struct *tty, struct file *f) +{ + struct smd_tty_info *info = smd_tty + tty->index; + + tty_port_close(&info->port, tty, f); +} + +static int smd_tty_write(struct tty_struct *tty, const unsigned char *buf, + int len) +{ + struct smd_tty_info *info = tty->driver_data; + int avail; + + /* if we're writing to a packet channel we will + ** never be able to write more data than there + ** is currently space for + */ + if (is_in_reset(info)) + return -ENETRESET; + + avail = smd_write_avail(info->ch); + /* if no space, we'll have to setup a notification later to wake up the + * tty framework when space becomes avaliable + */ + if (!avail) { + smd_enable_read_intr(info->ch); + return 0; + } + if (len > avail) + len = avail; + SMD_TTY_INFO("[WRITE]: PID %u -> port %s %x bytes", + current->pid, info->ch_name, len); + + return smd_write(info->ch, buf, len); +} + +static int smd_tty_write_room(struct tty_struct *tty) +{ + struct smd_tty_info *info = tty->driver_data; + return smd_write_avail(info->ch); +} + +static int smd_tty_chars_in_buffer(struct tty_struct *tty) +{ + struct smd_tty_info *info = tty->driver_data; + return smd_read_avail(info->ch); +} + +static void smd_tty_unthrottle(struct tty_struct *tty) +{ + struct smd_tty_info *info = tty->driver_data; + unsigned long flags; + + spin_lock_irqsave(&info->reset_lock_lha2, flags); + if (info->is_open) { + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); + tasklet_hi_schedule(&info->tty_tsklt); + return; + } + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); +} + +/* + * Returns the current TIOCM status bits including: + * SMD Signals (DTR/DSR, CTS/RTS, CD, RI) + * TIOCM_OUT1 - reset state (1=in reset) + * TIOCM_OUT2 - reset state updated (1=updated) + */ +static int smd_tty_tiocmget(struct tty_struct *tty) +{ + struct smd_tty_info *info = tty->driver_data; + unsigned long flags; + int tiocm; + + tiocm = smd_tiocmget(info->ch); + + spin_lock_irqsave(&info->reset_lock_lha2, flags); + tiocm |= (info->in_reset ? TIOCM_OUT1 : 0); + if (info->in_reset_updated) { + tiocm |= TIOCM_OUT2; + info->in_reset_updated = 0; + } + SMD_TTY_INFO("PID %u --> %s TIOCM is %x ", + current->pid, __func__, tiocm); + spin_unlock_irqrestore(&info->reset_lock_lha2, flags); + + return tiocm; +} + +static int smd_tty_tiocmset(struct tty_struct *tty, + unsigned int set, unsigned int clear) +{ + struct smd_tty_info *info = tty->driver_data; + + if (info->in_reset) + return -ENETRESET; + + SMD_TTY_INFO("PID %u --> %s Set: %x Clear: %x", + current->pid, __func__, set, clear); + return smd_tiocmset(info->ch, set, clear); +} + +static void loopback_probe_worker(struct work_struct *work) +{ + /* wait for modem to restart before requesting loopback server */ + if (!is_modem_smsm_inited()) + schedule_delayed_work(&loopback_work, msecs_to_jiffies(1000)); + else + smsm_change_state(SMSM_APPS_STATE, + 0, SMSM_SMD_LOOPBACK); +} + +static const struct tty_port_operations smd_tty_port_ops = { + .shutdown = smd_tty_port_shutdown, + .activate = smd_tty_port_activate, +}; + +static const struct tty_operations smd_tty_ops = { + .open = smd_tty_open, + .close = smd_tty_close, + .write = smd_tty_write, + .write_room = smd_tty_write_room, + .chars_in_buffer = smd_tty_chars_in_buffer, + .unthrottle = smd_tty_unthrottle, + .tiocmget = smd_tty_tiocmget, + .tiocmset = smd_tty_tiocmset, +}; + +static int smd_tty_pm_notifier(struct notifier_block *nb, + unsigned long event, void *unused) +{ + switch (event) { + case PM_SUSPEND_PREPARE: + smd_tty_read_in_suspend = false; + smd_tty_in_suspend = true; + break; + + case PM_POST_SUSPEND: + smd_tty_in_suspend = false; + if (smd_tty_read_in_suspend) { + smd_tty_read_in_suspend = false; + __pm_wakeup_event(&read_in_suspend_ws, + TTY_PUSH_WS_POST_SUSPEND_DELAY); + } + break; + } + return NOTIFY_DONE; +} + +static struct notifier_block smd_tty_pm_nb = { + .notifier_call = smd_tty_pm_notifier, + .priority = 0, +}; + +/** + * smd_tty_log_init()- Init function for IPC logging + * + * Initialize the buffer that is used to provide the log information + * pertaining to the smd_tty module. + */ +static void smd_tty_log_init(void) +{ + smd_tty_log_ctx = ipc_log_context_create(SMD_TTY_LOG_PAGES, + "smd_tty", 0); + if (!smd_tty_log_ctx) + pr_err("%s: Unable to create IPC log", __func__); +} + +static struct tty_driver *smd_tty_driver; + +static int smd_tty_register_driver(void) +{ + int ret; + + smd_tty_driver = alloc_tty_driver(MAX_SMD_TTYS); + if (smd_tty_driver == 0) { + SMD_TTY_ERR("%s - Driver allocation failed", __func__); + return -ENOMEM; + } + + smd_tty_driver->owner = THIS_MODULE; + smd_tty_driver->driver_name = "smd_tty_driver"; + smd_tty_driver->name = "smd"; + smd_tty_driver->major = 0; + smd_tty_driver->minor_start = 0; + smd_tty_driver->type = TTY_DRIVER_TYPE_SERIAL; + smd_tty_driver->subtype = SERIAL_TYPE_NORMAL; + smd_tty_driver->init_termios = tty_std_termios; + smd_tty_driver->init_termios.c_iflag = 0; + smd_tty_driver->init_termios.c_oflag = 0; + smd_tty_driver->init_termios.c_cflag = B38400 | CS8 | CREAD; + smd_tty_driver->init_termios.c_lflag = 0; + smd_tty_driver->flags = TTY_DRIVER_RESET_TERMIOS | + TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; + tty_set_operations(smd_tty_driver, &smd_tty_ops); + + ret = tty_register_driver(smd_tty_driver); + if (ret) { + put_tty_driver(smd_tty_driver); + SMD_TTY_ERR("%s: driver registration failed %d", __func__, ret); + } + + return ret; +} + +static void smd_tty_device_init(int idx) +{ + struct tty_port *port; + + port = &smd_tty[idx].port; + tty_port_init(port); + port->ops = &smd_tty_port_ops; + smd_tty[idx].device_ptr = tty_port_register_device(port, smd_tty_driver, + idx, NULL); + if (IS_ERR_OR_NULL(smd_tty[idx].device_ptr)) { + SMD_TTY_ERR("%s: Unable to register tty port %s reason %d\n", + __func__, + smd_tty[idx].ch_name, + PTR_ERR_OR_ZERO(smd_tty[idx].device_ptr)); + return; + } + init_completion(&smd_tty[idx].ch_allocated); + mutex_init(&smd_tty[idx].open_lock_lha1); + spin_lock_init(&smd_tty[idx].reset_lock_lha2); + spin_lock_init(&smd_tty[idx].ra_lock_lha3); + smd_tty[idx].is_open = 0; + setup_timer(&smd_tty[idx].buf_req_timer, buf_req_retry, + (unsigned long)&smd_tty[idx]); + init_waitqueue_head(&smd_tty[idx].ch_opened_wait_queue); + + if (device_create_file(smd_tty[idx].device_ptr, &dev_attr_open_timeout)) + SMD_TTY_ERR("%s: Unable to create device attributes for %s", + __func__, smd_tty[idx].ch_name); +} + +static int smd_tty_devicetree_init(struct platform_device *pdev) +{ + int ret; + int idx; + int edge; + char *key = NULL; + const char *ch_name; + const char *dev_name; + const char *remote_ss; + struct device_node *node; + + ret = smd_tty_register_driver(); + if (ret) { + SMD_TTY_ERR("%s: driver registration failed %d\n", + __func__, ret); + return ret; + } + + for_each_child_of_node(pdev->dev.of_node, node) { + + ret = of_alias_get_id(node, "smd"); + SMD_TTY_INFO("%s:adding smd%d\n", __func__, ret); + + if (ret < 0 || ret >= MAX_SMD_TTYS) + goto error; + idx = ret; + + key = "qcom,smdtty-remote"; + remote_ss = of_get_property(node, key, NULL); + if (!remote_ss) + goto error; + + edge = smd_remote_ss_to_edge(remote_ss); + if (edge < 0) + goto error; + smd_tty[idx].edge = edge; + + key = "qcom,smdtty-port-name"; + ch_name = of_get_property(node, key, NULL); + if (!ch_name) + goto error; + strlcpy(smd_tty[idx].ch_name, ch_name, + SMD_MAX_CH_NAME_LEN); + + key = "qcom,smdtty-dev-name"; + dev_name = of_get_property(node, key, NULL); + if (!dev_name) { + strlcpy(smd_tty[idx].dev_name, smd_tty[idx].ch_name, + SMD_MAX_CH_NAME_LEN); + } else { + strlcpy(smd_tty[idx].dev_name, dev_name, + SMD_MAX_CH_NAME_LEN); + } + + smd_tty_device_init(idx); + } + INIT_DELAYED_WORK(&loopback_work, loopback_probe_worker); + + ret = register_pm_notifier(&smd_tty_pm_nb); + if (ret) + pr_err("%s: power state notif error %d\n", __func__, ret); + + return 0; + +error: + SMD_TTY_ERR("%s:Initialization error, key[%s]\n", __func__, key); + /* Unregister tty platform devices */ + for_each_child_of_node(pdev->dev.of_node, node) { + + ret = of_alias_get_id(node, "smd"); + SMD_TTY_INFO("%s:Removing smd%d\n", __func__, ret); + + if (ret < 0 || ret >= MAX_SMD_TTYS) + goto out; + idx = ret; + + if (smd_tty[idx].device_ptr) { + device_remove_file(smd_tty[idx].device_ptr, + &dev_attr_open_timeout); + tty_unregister_device(smd_tty_driver, idx); + } + } +out: + tty_unregister_driver(smd_tty_driver); + put_tty_driver(smd_tty_driver); + return ret; +} + +static int msm_smd_tty_probe(struct platform_device *pdev) +{ + int ret; + + if (pdev) { + if (pdev->dev.of_node) { + ret = smd_tty_devicetree_init(pdev); + if (ret) { + SMD_TTY_ERR("%s: device tree init failed\n", + __func__); + return ret; + } + } + } + + return 0; +} + +static struct of_device_id msm_smd_tty_match_table[] = { + { .compatible = "qcom,smdtty" }, + {}, +}; + +static struct platform_driver msm_smd_tty_driver = { + .probe = msm_smd_tty_probe, + .driver = { + .name = MODULE_NAME, + .owner = THIS_MODULE, + .of_match_table = msm_smd_tty_match_table, + }, +}; + + +static int __init smd_tty_init(void) +{ + int rc; + + smd_tty_log_init(); + rc = platform_driver_register(&msm_smd_tty_driver); + if (rc) { + SMD_TTY_ERR("%s: msm_smd_tty_driver register failed %d\n", + __func__, rc); + return rc; + } + + wakeup_source_init(&read_in_suspend_ws, "SMDTTY_READ_IN_SUSPEND"); + return 0; +} + +module_init(smd_tty_init); diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 42aa37515e9b..c0c6b89de598 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -2466,7 +2466,6 @@ static int __init s3c2410_early_console_setup(struct earlycon_device *device, } OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart", s3c2410_early_console_setup); -EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup); /* S3C2412, S3C2440, S3C64xx */ static struct samsung_early_console_data s3c2440_early_console_data = { @@ -2485,9 +2484,6 @@ OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart", s3c2440_early_console_setup); OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", s3c2440_early_console_setup); -EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup); -EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup); -EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup); /* S5PV210, EXYNOS */ static struct samsung_early_console_data s5pv210_early_console_data = { @@ -2504,8 +2500,6 @@ OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", s5pv210_early_console_setup); OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", s5pv210_early_console_setup); -EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup); -EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup); #endif MODULE_ALIAS("platform:samsung-uart"); diff --git a/drivers/tty/serial/sprd_serial.c b/drivers/tty/serial/sprd_serial.c index 82e00ac6f7e3..f8f9927dc0a4 100644 --- a/drivers/tty/serial/sprd_serial.c +++ b/drivers/tty/serial/sprd_serial.c @@ -626,8 +626,6 @@ static int __init sprd_early_console_setup( device->con->write = sprd_early_write; return 0; } - -EARLYCON_DECLARE(sprd_serial, sprd_early_console_setup); OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart", sprd_early_console_setup); diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c index def99f020d82..161128d9c9db 100644 --- a/drivers/tty/sysrq.c +++ b/drivers/tty/sysrq.c @@ -55,10 +55,11 @@ static int __read_mostly sysrq_enabled = CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE; static bool __read_mostly sysrq_always_enabled; -static bool sysrq_on(void) +bool sysrq_on(void) { return sysrq_enabled || sysrq_always_enabled; } +EXPORT_SYMBOL(sysrq_on); /* * A value of 1 means 'all', other nonzero values are an op mask: diff --git a/drivers/tty/tty_buffer.c b/drivers/tty/tty_buffer.c index 4706df20191b..92af201f9030 100644 --- a/drivers/tty/tty_buffer.c +++ b/drivers/tty/tty_buffer.c @@ -71,7 +71,7 @@ void tty_buffer_unlock_exclusive(struct tty_port *port) atomic_dec(&buf->priority); mutex_unlock(&buf->lock); if (restart) - queue_work(system_unbound_wq, &buf->work); + queue_kthread_work(&port->worker, &buf->work); } EXPORT_SYMBOL_GPL(tty_buffer_unlock_exclusive); @@ -132,6 +132,8 @@ void tty_buffer_free_all(struct tty_port *port) buf->tail = &buf->sentinel; atomic_set(&buf->mem_used, 0); + if (!IS_ERR_OR_NULL(port->worker_thread)) + kthread_stop(port->worker_thread); } /** @@ -404,7 +406,7 @@ void tty_schedule_flip(struct tty_port *port) * flush_to_ldisc() sees buffer data. */ smp_store_release(&buf->tail->commit, buf->tail->used); - queue_work(system_unbound_wq, &buf->work); + queue_kthread_work(&port->worker, &buf->work); } EXPORT_SYMBOL(tty_schedule_flip); @@ -472,7 +474,7 @@ receive_buf(struct tty_struct *tty, struct tty_buffer *head, int count) * 'consumer' */ -static void flush_to_ldisc(struct work_struct *work) +static void flush_to_ldisc(struct kthread_work *work) { struct tty_port *port = container_of(work, struct tty_port, buf.work); struct tty_bufhead *buf = &port->buf; @@ -562,8 +564,20 @@ void tty_buffer_init(struct tty_port *port) init_llist_head(&buf->free); atomic_set(&buf->mem_used, 0); atomic_set(&buf->priority, 0); - INIT_WORK(&buf->work, flush_to_ldisc); buf->mem_limit = TTYB_DEFAULT_MEM_LIMIT; + init_kthread_work(&buf->work, flush_to_ldisc); + init_kthread_worker(&port->worker); + port->worker_thread = kthread_run(kthread_worker_fn, &port->worker, + "tty_worker_thread"); + if (IS_ERR(port->worker_thread)) { + /* + * Not good, we can't unwind, this tty is going to be really + * sad... + */ + pr_err("Unable to start tty_worker_thread\n"); + } + + } /** @@ -591,15 +605,15 @@ void tty_buffer_set_lock_subclass(struct tty_port *port) bool tty_buffer_restart_work(struct tty_port *port) { - return queue_work(system_unbound_wq, &port->buf.work); + return queue_kthread_work(&port->worker, &port->buf.work); } bool tty_buffer_cancel_work(struct tty_port *port) { - return cancel_work_sync(&port->buf.work); + return kthread_cancel_work_sync(&port->buf.work); } void tty_buffer_flush_work(struct tty_port *port) { - flush_work(&port->buf.work); + flush_kthread_work(&port->buf.work); } diff --git a/drivers/tty/tty_port.c b/drivers/tty/tty_port.c index 482f33f20043..9f06fc11bc5f 100644 --- a/drivers/tty/tty_port.c +++ b/drivers/tty/tty_port.c @@ -16,6 +16,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/module.h> +#include <uapi/linux/sched.h> void tty_port_init(struct tty_port *port) { @@ -598,3 +599,12 @@ int tty_port_open(struct tty_port *port, struct tty_struct *tty, } EXPORT_SYMBOL(tty_port_open); + +int tty_port_set_policy(struct tty_port *port, int policy, int sched_priority) +{ + struct sched_param param = { .sched_priority = sched_priority }; + + return sched_setscheduler(port->worker_thread, policy, ¶m); +} +EXPORT_SYMBOL_GPL(tty_port_set_policy); + |