diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/qcom,mmcc-msm8996.h | 485 | ||||
| -rw-r--r-- | include/linux/mdss_smmu_ext.h | 4 | ||||
| -rw-r--r-- | include/linux/power_supply.h | 8 | ||||
| -rw-r--r-- | include/linux/qcom_tspp.h | 11 | ||||
| -rw-r--r-- | include/linux/qdsp6v2/rtac.h | 4 | ||||
| -rw-r--r-- | include/soc/qcom/cx_ipeak.h | 46 | ||||
| -rw-r--r-- | include/soc/qcom/icnss.h | 11 | ||||
| -rw-r--r-- | include/soc/qcom/qseecomi.h | 5 | ||||
| -rw-r--r-- | include/soc/qcom/service-notifier.h | 11 | ||||
| -rw-r--r-- | include/sound/apr_audio-v2.h | 185 | ||||
| -rw-r--r-- | include/sound/q6afe-v2.h | 4 | ||||
| -rw-r--r-- | include/sound/q6asm-v2.h | 6 | ||||
| -rw-r--r-- | include/trace/events/power.h | 2 | ||||
| -rw-r--r-- | include/uapi/linux/dvb/dmx.h | 3 | ||||
| -rw-r--r-- | include/uapi/linux/msm_ipa.h | 4 | ||||
| -rw-r--r-- | include/uapi/linux/msm_mdp.h | 1 |
16 files changed, 510 insertions, 280 deletions
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h index f924b92b0188..436badbaad7d 100644 --- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h +++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,213 +14,177 @@ #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H #define _DT_BINDINGS_CLK_MSM_MMCC_8996_H -#define MMPLL0_EARLY 0 -#define MMPLL0_PLL 1 -#define MMPLL1_EARLY 2 -#define MMPLL1_PLL 3 -#define MMPLL2_EARLY 4 -#define MMPLL2_PLL 5 -#define MMPLL3_EARLY 6 -#define MMPLL3_PLL 7 -#define MMPLL4_EARLY 8 -#define MMPLL4_PLL 9 -#define MMPLL5_EARLY 10 -#define MMPLL5_PLL 11 -#define MMPLL8_EARLY 12 -#define MMPLL8_PLL 13 -#define MMPLL9_EARLY 14 -#define MMPLL9_PLL 15 -#define AHB_CLK_SRC 16 -#define AXI_CLK_SRC 17 -#define MAXI_CLK_SRC 18 -#define DSA_CORE_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define RBBMTIMER_CLK_SRC 21 -#define ISENSE_CLK_SRC 22 -#define RBCPR_CLK_SRC 23 -#define VIDEO_CORE_CLK_SRC 24 -#define VIDEO_SUBCORE0_CLK_SRC 25 -#define VIDEO_SUBCORE1_CLK_SRC 26 -#define PCLK0_CLK_SRC 27 -#define PCLK1_CLK_SRC 28 -#define MDP_CLK_SRC 29 -#define EXTPCLK_CLK_SRC 30 -#define VSYNC_CLK_SRC 31 -#define HDMI_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define ESC0_CLK_SRC 35 -#define ESC1_CLK_SRC 36 -#define CAMSS_GP0_CLK_SRC 37 -#define CAMSS_GP1_CLK_SRC 38 -#define MCLK0_CLK_SRC 39 -#define MCLK1_CLK_SRC 40 -#define MCLK2_CLK_SRC 41 -#define MCLK3_CLK_SRC 42 -#define CCI_CLK_SRC 43 -#define CSI0PHYTIMER_CLK_SRC 44 -#define CSI1PHYTIMER_CLK_SRC 45 -#define CSI2PHYTIMER_CLK_SRC 46 -#define CSIPHY0_3P_CLK_SRC 47 -#define CSIPHY1_3P_CLK_SRC 48 -#define CSIPHY2_3P_CLK_SRC 49 -#define JPEG0_CLK_SRC 50 -#define JPEG2_CLK_SRC 51 -#define JPEG_DMA_CLK_SRC 52 -#define VFE0_CLK_SRC 53 -#define VFE1_CLK_SRC 54 -#define CPP_CLK_SRC 55 -#define CSI0_CLK_SRC 56 -#define CSI1_CLK_SRC 57 -#define CSI2_CLK_SRC 58 -#define CSI3_CLK_SRC 59 -#define FD_CORE_CLK_SRC 60 -#define MMSS_CXO_CLK 61 -#define MMSS_SLEEPCLK_CLK 62 -#define MMSS_MMAGIC_AHB_CLK 63 -#define MMSS_MMAGIC_CFG_AHB_CLK 64 -#define MMSS_MISC_AHB_CLK 65 -#define MMSS_MISC_CXO_CLK 66 -#define MMSS_BTO_AHB_CLK 67 -#define MMSS_MMAGIC_AXI_CLK 68 -#define MMSS_S0_AXI_CLK 69 +/* Hardware/Dummy/Voter clocks */ +#define GPLL0_DIV 0 +#define MDSS_MDP_VOTE_CLK 1 +#define MDSS_ROTATOR_VOTE_CLK 2 + +/* RCG and Branches */ +#define MMPLL0_EARLY 10 +#define MMPLL0_PLL 11 +#define MMPLL1_EARLY 12 +#define MMPLL1_PLL 13 +#define MMPLL2_EARLY 14 +#define MMPLL2_PLL 15 +#define MMPLL3_EARLY 16 +#define MMPLL3_PLL 17 +#define MMPLL4_EARLY 18 +#define MMPLL4_PLL 19 +#define MMPLL5_EARLY 20 +#define MMPLL5_PLL 21 +#define MMPLL8_EARLY 22 +#define MMPLL8_PLL 23 +#define MMPLL9_EARLY 24 +#define MMPLL9_PLL 25 +#define AHB_CLK_SRC 26 +#define MAXI_CLK_SRC 27 +#define RBCPR_CLK_SRC 28 +#define VIDEO_CORE_CLK_SRC 29 +#define VIDEO_SUBCORE0_CLK_SRC 30 +#define VIDEO_SUBCORE1_CLK_SRC 31 +#define PCLK0_CLK_SRC 32 +#define PCLK1_CLK_SRC 33 +#define MDP_CLK_SRC 34 +#define EXTPCLK_CLK_SRC 35 +#define VSYNC_CLK_SRC 36 +#define HDMI_CLK_SRC 37 +#define BYTE0_CLK_SRC 38 +#define BYTE1_CLK_SRC 39 +#define ESC0_CLK_SRC 40 +#define ESC1_CLK_SRC 41 +#define CAMSS_GP0_CLK_SRC 42 +#define CAMSS_GP1_CLK_SRC 43 +#define MCLK0_CLK_SRC 44 +#define MCLK1_CLK_SRC 45 +#define MCLK2_CLK_SRC 46 +#define MCLK3_CLK_SRC 47 +#define CCI_CLK_SRC 48 +#define CSI0PHYTIMER_CLK_SRC 49 +#define CSI1PHYTIMER_CLK_SRC 50 +#define CSI2PHYTIMER_CLK_SRC 51 +#define CSIPHY0_3P_CLK_SRC 52 +#define CSIPHY1_3P_CLK_SRC 53 +#define CSIPHY2_3P_CLK_SRC 54 +#define JPEG0_CLK_SRC 55 +#define JPEG2_CLK_SRC 56 +#define JPEG_DMA_CLK_SRC 57 +#define VFE0_CLK_SRC 58 +#define VFE1_CLK_SRC 59 +#define CPP_CLK_SRC 60 +#define CSI0_CLK_SRC 61 +#define CSI1_CLK_SRC 62 +#define CSI2_CLK_SRC 63 +#define CSI3_CLK_SRC 64 +#define FD_CORE_CLK_SRC 65 +#define MMSS_MMAGIC_AHB_CLK 66 +#define MMSS_MMAGIC_CFG_AHB_CLK 67 +#define MMSS_MISC_AHB_CLK 68 +#define MMSS_MISC_CXO_CLK 69 #define MMSS_MMAGIC_MAXI_CLK 70 -#define DSA_CORE_CLK 71 -#define DSA_NOC_CFG_AHB_CLK 72 -#define MMAGIC_CAMSS_AXI_CLK 73 -#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 -#define THROTTLE_CAMSS_CXO_CLK 75 -#define THROTTLE_CAMSS_AHB_CLK 76 -#define THROTTLE_CAMSS_AXI_CLK 77 -#define SMMU_VFE_AHB_CLK 78 -#define SMMU_VFE_AXI_CLK 79 -#define SMMU_CPP_AHB_CLK 80 -#define SMMU_CPP_AXI_CLK 81 -#define SMMU_JPEG_AHB_CLK 82 -#define SMMU_JPEG_AXI_CLK 83 -#define MMAGIC_MDSS_AXI_CLK 84 -#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 -#define THROTTLE_MDSS_CXO_CLK 86 -#define THROTTLE_MDSS_AHB_CLK 87 -#define THROTTLE_MDSS_AXI_CLK 88 -#define SMMU_ROT_AHB_CLK 89 -#define SMMU_ROT_AXI_CLK 90 -#define SMMU_MDP_AHB_CLK 91 -#define SMMU_MDP_AXI_CLK 92 -#define MMAGIC_VIDEO_AXI_CLK 93 -#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 -#define THROTTLE_VIDEO_CXO_CLK 95 -#define THROTTLE_VIDEO_AHB_CLK 96 -#define THROTTLE_VIDEO_AXI_CLK 97 -#define SMMU_VIDEO_AHB_CLK 98 -#define SMMU_VIDEO_AXI_CLK 99 -#define MMAGIC_BIMC_AXI_CLK 100 -#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 -#define GPU_GX_GFX3D_CLK 102 -#define GPU_GX_RBBMTIMER_CLK 103 -#define GPU_AHB_CLK 104 -#define GPU_AON_ISENSE_CLK 105 -#define VMEM_MAXI_CLK 106 -#define VMEM_AHB_CLK 107 -#define MMSS_RBCPR_CLK 108 -#define MMSS_RBCPR_AHB_CLK 109 -#define VIDEO_CORE_CLK 110 -#define VIDEO_AXI_CLK 111 -#define VIDEO_MAXI_CLK 112 -#define VIDEO_AHB_CLK 113 -#define VIDEO_SUBCORE0_CLK 114 -#define VIDEO_SUBCORE1_CLK 115 -#define MDSS_AHB_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_AXI_CLK 118 -#define MDSS_PCLK0_CLK 119 -#define MDSS_PCLK1_CLK 120 -#define MDSS_MDP_CLK 121 -#define MDSS_EXTPCLK_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MDSS_HDMI_CLK 124 -#define MDSS_BYTE0_CLK 125 -#define MDSS_BYTE1_CLK 126 -#define MDSS_ESC0_CLK 127 -#define MDSS_ESC1_CLK 128 -#define CAMSS_TOP_AHB_CLK 129 -#define CAMSS_AHB_CLK 130 -#define CAMSS_MICRO_AHB_CLK 131 -#define CAMSS_GP0_CLK 132 -#define CAMSS_GP1_CLK 133 -#define CAMSS_MCLK0_CLK 134 -#define CAMSS_MCLK1_CLK 135 -#define CAMSS_MCLK2_CLK 136 -#define CAMSS_MCLK3_CLK 137 -#define CAMSS_CCI_CLK 138 -#define CAMSS_CCI_AHB_CLK 139 -#define CAMSS_CSI0PHYTIMER_CLK 140 -#define CAMSS_CSI1PHYTIMER_CLK 141 -#define CAMSS_CSI2PHYTIMER_CLK 142 -#define CAMSS_CSIPHY0_3P_CLK 143 -#define CAMSS_CSIPHY1_3P_CLK 144 -#define CAMSS_CSIPHY2_3P_CLK 145 -#define CAMSS_JPEG0_CLK 146 -#define CAMSS_JPEG2_CLK 147 -#define CAMSS_JPEG_DMA_CLK 148 -#define CAMSS_JPEG_AHB_CLK 149 -#define CAMSS_JPEG_AXI_CLK 150 -#define CAMSS_VFE_AHB_CLK 151 -#define CAMSS_VFE_AXI_CLK 152 -#define CAMSS_VFE0_CLK 153 -#define CAMSS_VFE0_STREAM_CLK 154 -#define CAMSS_VFE0_AHB_CLK 155 -#define CAMSS_VFE1_CLK 156 -#define CAMSS_VFE1_STREAM_CLK 157 -#define CAMSS_VFE1_AHB_CLK 158 -#define CAMSS_CSI_VFE0_CLK 159 -#define CAMSS_CSI_VFE1_CLK 160 -#define CAMSS_CPP_VBIF_AHB_CLK 161 -#define CAMSS_CPP_AXI_CLK 162 -#define CAMSS_CPP_CLK 163 -#define CAMSS_CPP_AHB_CLK 164 -#define CAMSS_CSI0_CLK 165 -#define CAMSS_CSI0_AHB_CLK 166 -#define CAMSS_CSI0PHY_CLK 167 -#define CAMSS_CSI0RDI_CLK 168 -#define CAMSS_CSI0PIX_CLK 169 -#define CAMSS_CSI1_CLK 170 -#define CAMSS_CSI1_AHB_CLK 171 -#define CAMSS_CSI1PHY_CLK 172 -#define CAMSS_CSI1RDI_CLK 173 -#define CAMSS_CSI1PIX_CLK 174 -#define CAMSS_CSI2_CLK 175 -#define CAMSS_CSI2_AHB_CLK 176 -#define CAMSS_CSI2PHY_CLK 177 -#define CAMSS_CSI2RDI_CLK 178 -#define CAMSS_CSI2PIX_CLK 179 -#define CAMSS_CSI3_CLK 180 -#define CAMSS_CSI3_AHB_CLK 181 -#define CAMSS_CSI3PHY_CLK 182 -#define CAMSS_CSI3RDI_CLK 183 -#define CAMSS_CSI3PIX_CLK 184 -#define CAMSS_ISPIF_AHB_CLK 185 -#define FD_CORE_CLK 186 -#define FD_CORE_UAR_CLK 187 -#define FD_AHB_CLK 188 -#define MMSS_SPDM_CSI0_CLK 189 -#define MMSS_SPDM_JPEG_DMA_CLK 190 -#define MMSS_SPDM_CPP_CLK 191 -#define MMSS_SPDM_PCLK0_CLK 192 -#define MMSS_SPDM_AHB_CLK 193 -#define MMSS_SPDM_GFX3D_CLK 194 -#define MMSS_SPDM_PCLK1_CLK 195 -#define MMSS_SPDM_JPEG2_CLK 196 -#define MMSS_SPDM_DEBUG_CLK 197 -#define MMSS_SPDM_VFE1_CLK 198 -#define MMSS_SPDM_VFE0_CLK 199 -#define MMSS_SPDM_VIDEO_CORE_CLK 200 -#define MMSS_SPDM_AXI_CLK 201 -#define MMSS_SPDM_MDP_CLK 202 -#define MMSS_SPDM_JPEG0_CLK 203 -#define MMSS_SPDM_RM_AXI_CLK 204 -#define MMSS_SPDM_RM_MAXI_CLK 205 +#define MMAGIC_CAMSS_AXI_CLK 71 +#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 72 +#define SMMU_VFE_AHB_CLK 73 +#define SMMU_VFE_AXI_CLK 74 +#define SMMU_CPP_AHB_CLK 75 +#define SMMU_CPP_AXI_CLK 76 +#define SMMU_JPEG_AHB_CLK 77 +#define SMMU_JPEG_AXI_CLK 78 +#define MMAGIC_MDSS_AXI_CLK 79 +#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 80 +#define SMMU_ROT_AHB_CLK 81 +#define SMMU_ROT_AXI_CLK 82 +#define SMMU_MDP_AHB_CLK 83 +#define SMMU_MDP_AXI_CLK 84 +#define MMAGIC_VIDEO_AXI_CLK 85 +#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 86 +#define SMMU_VIDEO_AHB_CLK 87 +#define SMMU_VIDEO_AXI_CLK 88 +#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 89 +#define VMEM_MAXI_CLK 90 +#define VMEM_AHB_CLK 91 +#define MMSS_RBCPR_CLK 92 +#define MMSS_RBCPR_AHB_CLK 93 +#define VIDEO_CORE_CLK 94 +#define VIDEO_AXI_CLK 95 +#define VIDEO_MAXI_CLK 96 +#define VIDEO_AHB_CLK 97 +#define VIDEO_SUBCORE0_CLK 98 +#define VIDEO_SUBCORE1_CLK 99 +#define MDSS_AHB_CLK 100 +#define MDSS_HDMI_AHB_CLK 101 +#define MDSS_AXI_CLK 102 +#define MDSS_PCLK0_CLK 103 +#define MDSS_PCLK1_CLK 104 +#define MDSS_MDP_CLK 105 +#define MDSS_EXTPCLK_CLK 106 +#define MDSS_VSYNC_CLK 107 +#define MDSS_HDMI_CLK 108 +#define MDSS_BYTE0_CLK 109 +#define MDSS_BYTE1_CLK 110 +#define MDSS_ESC0_CLK 111 +#define MDSS_ESC1_CLK 112 +#define CAMSS_TOP_AHB_CLK 113 +#define CAMSS_AHB_CLK 114 +#define CAMSS_MICRO_AHB_CLK 115 +#define CAMSS_GP0_CLK 116 +#define CAMSS_GP1_CLK 117 +#define CAMSS_MCLK0_CLK 118 +#define CAMSS_MCLK1_CLK 119 +#define CAMSS_MCLK2_CLK 120 +#define CAMSS_MCLK3_CLK 121 +#define CAMSS_CCI_CLK 122 +#define CAMSS_CCI_AHB_CLK 123 +#define CAMSS_CSI0PHYTIMER_CLK 124 +#define CAMSS_CSI1PHYTIMER_CLK 125 +#define CAMSS_CSI2PHYTIMER_CLK 126 +#define CAMSS_CSIPHY0_3P_CLK 127 +#define CAMSS_CSIPHY1_3P_CLK 128 +#define CAMSS_CSIPHY2_3P_CLK 129 +#define CAMSS_JPEG0_CLK 130 +#define CAMSS_JPEG2_CLK 131 +#define CAMSS_JPEG_DMA_CLK 132 +#define CAMSS_JPEG_AHB_CLK 133 +#define CAMSS_JPEG_AXI_CLK 134 +#define CAMSS_VFE_AHB_CLK 135 +#define CAMSS_VFE_AXI_CLK 136 +#define CAMSS_VFE0_CLK 137 +#define CAMSS_VFE0_STREAM_CLK 138 +#define CAMSS_VFE0_AHB_CLK 139 +#define CAMSS_VFE1_CLK 140 +#define CAMSS_VFE1_STREAM_CLK 141 +#define CAMSS_VFE1_AHB_CLK 142 +#define CAMSS_CSI_VFE0_CLK 143 +#define CAMSS_CSI_VFE1_CLK 144 +#define CAMSS_CPP_VBIF_AHB_CLK 145 +#define CAMSS_CPP_AXI_CLK 146 +#define CAMSS_CPP_CLK 147 +#define CAMSS_CPP_AHB_CLK 148 +#define CAMSS_CSI0_CLK 149 +#define CAMSS_CSI0_AHB_CLK 150 +#define CAMSS_CSI0PHY_CLK 151 +#define CAMSS_CSI0RDI_CLK 152 +#define CAMSS_CSI0PIX_CLK 153 +#define CAMSS_CSI1_CLK 154 +#define CAMSS_CSI1_AHB_CLK 155 +#define CAMSS_CSI1PHY_CLK 156 +#define CAMSS_CSI1RDI_CLK 157 +#define CAMSS_CSI1PIX_CLK 158 +#define CAMSS_CSI2_CLK 159 +#define CAMSS_CSI2_AHB_CLK 160 +#define CAMSS_CSI2PHY_CLK 161 +#define CAMSS_CSI2RDI_CLK 162 +#define CAMSS_CSI2PIX_CLK 163 +#define CAMSS_CSI3_CLK 164 +#define CAMSS_CSI3_AHB_CLK 165 +#define CAMSS_CSI3PHY_CLK 166 +#define CAMSS_CSI3RDI_CLK 167 +#define CAMSS_CSI3PIX_CLK 168 +#define CAMSS_ISPIF_AHB_CLK 169 +#define FD_CORE_CLK 170 +#define FD_CORE_UAR_CLK 171 +#define FD_AHB_CLK 172 +/* Block resets */ #define MMAGICAHB_BCR 0 #define MMAGIC_CFG_BCR 1 #define MISC_BCR 2 @@ -241,63 +205,60 @@ #define THROTTLE_VIDEO_BCR 17 #define SMMU_VIDEO_BCR 18 #define MMAGIC_BIMC_BCR 19 -#define GPU_GX_BCR 20 -#define GPU_BCR 21 -#define GPU_AON_BCR 22 -#define VMEM_BCR 23 -#define MMSS_RBCPR_BCR 24 -#define VIDEO_BCR 25 -#define MDSS_BCR 26 -#define CAMSS_TOP_BCR 27 -#define CAMSS_AHB_BCR 28 -#define CAMSS_MICRO_BCR 29 -#define CAMSS_CCI_BCR 30 -#define CAMSS_PHY0_BCR 31 -#define CAMSS_PHY1_BCR 32 -#define CAMSS_PHY2_BCR 33 -#define CAMSS_CSIPHY0_3P_BCR 34 -#define CAMSS_CSIPHY1_3P_BCR 35 -#define CAMSS_CSIPHY2_3P_BCR 36 -#define CAMSS_JPEG_BCR 37 -#define CAMSS_VFE_BCR 38 -#define CAMSS_VFE0_BCR 39 -#define CAMSS_VFE1_BCR 40 -#define CAMSS_CSI_VFE0_BCR 41 -#define CAMSS_CSI_VFE1_BCR 42 -#define CAMSS_CPP_TOP_BCR 43 -#define CAMSS_CPP_BCR 44 -#define CAMSS_CSI0_BCR 45 -#define CAMSS_CSI0RDI_BCR 46 -#define CAMSS_CSI0PIX_BCR 47 -#define CAMSS_CSI1_BCR 48 -#define CAMSS_CSI1RDI_BCR 49 -#define CAMSS_CSI1PIX_BCR 50 -#define CAMSS_CSI2_BCR 51 -#define CAMSS_CSI2RDI_BCR 52 -#define CAMSS_CSI2PIX_BCR 53 -#define CAMSS_CSI3_BCR 54 -#define CAMSS_CSI3RDI_BCR 55 -#define CAMSS_CSI3PIX_BCR 56 -#define CAMSS_ISPIF_BCR 57 -#define FD_BCR 58 -#define MMSS_SPDM_RM_BCR 59 +#define VMEM_BCR 20 +#define MMSS_RBCPR_BCR 21 +#define VIDEO_BCR 22 +#define MDSS_BCR 23 +#define CAMSS_TOP_BCR 24 +#define CAMSS_AHB_BCR 25 +#define CAMSS_MICRO_BCR 26 +#define CAMSS_CCI_BCR 27 +#define CAMSS_PHY0_BCR 28 +#define CAMSS_PHY1_BCR 29 +#define CAMSS_PHY2_BCR 30 +#define CAMSS_CSIPHY0_3P_BCR 31 +#define CAMSS_CSIPHY1_3P_BCR 32 +#define CAMSS_CSIPHY2_3P_BCR 33 +#define CAMSS_JPEG_BCR 34 +#define CAMSS_VFE_BCR 35 +#define CAMSS_VFE0_BCR 36 +#define CAMSS_VFE1_BCR 37 +#define CAMSS_CSI_VFE0_BCR 38 +#define CAMSS_CSI_VFE1_BCR 39 +#define CAMSS_CPP_TOP_BCR 40 +#define CAMSS_CPP_BCR 41 +#define CAMSS_CSI0_BCR 42 +#define CAMSS_CSI0RDI_BCR 43 +#define CAMSS_CSI0PIX_BCR 44 +#define CAMSS_CSI1_BCR 45 +#define CAMSS_CSI1RDI_BCR 46 +#define CAMSS_CSI1PIX_BCR 47 +#define CAMSS_CSI2_BCR 48 +#define CAMSS_CSI2RDI_BCR 49 +#define CAMSS_CSI2PIX_BCR 50 +#define CAMSS_CSI3_BCR 51 +#define CAMSS_CSI3RDI_BCR 52 +#define CAMSS_CSI3PIX_BCR 53 +#define CAMSS_ISPIF_BCR 54 +#define FD_BCR 55 +#define MMSS_SPDM_RM_BCR 56 /* Indexes for GDSCs */ -#define MMAGIC_VIDEO_GDSC 0 -#define MMAGIC_MDSS_GDSC 1 -#define MMAGIC_CAMSS_GDSC 2 -#define GPU_GDSC 3 -#define VENUS_GDSC 4 -#define VENUS_CORE0_GDSC 5 -#define VENUS_CORE1_GDSC 6 -#define CAMSS_GDSC 7 -#define VFE0_GDSC 8 -#define VFE1_GDSC 9 -#define JPEG_GDSC 10 -#define CPP_GDSC 11 -#define FD_GDSC 12 -#define MDSS_GDSC 13 -#define GPU_GX_GDSC 14 -#define MMAGIC_BIMC_GDSC 15 +#define MMAGIC_VIDEO_GDSC 0 +#define MMAGIC_MDSS_GDSC 1 +#define MMAGIC_CAMSS_GDSC 2 +#define GPU_GDSC 3 +#define VENUS_GDSC 4 +#define VENUS_CORE0_GDSC 5 +#define VENUS_CORE1_GDSC 6 +#define CAMSS_GDSC 7 +#define VFE0_GDSC 8 +#define VFE1_GDSC 9 +#define JPEG_GDSC 10 +#define CPP_GDSC 11 +#define FD_GDSC 12 +#define MDSS_GDSC 13 +#define GPU_GX_GDSC 14 +#define MMAGIC_BIMC_GDSC 15 #endif diff --git a/include/linux/mdss_smmu_ext.h b/include/linux/mdss_smmu_ext.h index 414ab055595a..12ad4305f145 100644 --- a/include/linux/mdss_smmu_ext.h +++ b/include/linux/mdss_smmu_ext.h @@ -22,6 +22,7 @@ * @iommu_ctrl: iommu ctrl function for enable/disable attach. * @secure_session_ctrl: ctrl function for enable/disable session. * @wait_for_transition:function to wait till secure transtion is complete. + * @reg_lock /reg_unlock: Lock to access shared registers. */ struct mdss_smmu_intf { struct device *dev; @@ -30,6 +31,9 @@ struct mdss_smmu_intf { int (*iommu_ctrl)(int); int (*secure_session_ctrl)(int); int (*wait_for_transition)(int state, int request); + void (*reg_lock)(void); + void (*reg_unlock)(void); + bool (*handoff_pending)(void); }; typedef void (*msm_smmu_handler_t) (struct mdss_smmu_intf *smmu); diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 64f5c4ca09d5..457d862cb9a8 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -61,6 +61,7 @@ enum { POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE, POWER_SUPPLY_HEALTH_WARM, POWER_SUPPLY_HEALTH_COOL, + POWER_SUPPLY_HEALTH_HOT, }; enum { @@ -190,6 +191,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_INPUT_CURRENT_MAX, POWER_SUPPLY_PROP_INPUT_CURRENT_TRIM, POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_SETTLED, POWER_SUPPLY_PROP_VCHG_LOOP_DBC_BYPASS, POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW, POWER_SUPPLY_PROP_HI_POWER, @@ -214,6 +216,8 @@ enum power_supply_property { POWER_SUPPLY_PROP_DP_DM, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMITED, POWER_SUPPLY_PROP_INPUT_CURRENT_NOW, + POWER_SUPPLY_PROP_CURRENT_QNOVO, + POWER_SUPPLY_PROP_VOLTAGE_QNOVO, POWER_SUPPLY_PROP_RERUN_AICL, POWER_SUPPLY_PROP_CYCLE_COUNT_ID, POWER_SUPPLY_PROP_SAFETY_TIMER_EXPIRED, @@ -237,7 +241,9 @@ enum power_supply_property { POWER_SUPPLY_PROP_FCC_DELTA, POWER_SUPPLY_PROP_ICL_REDUCTION, POWER_SUPPLY_PROP_PARALLEL_MODE, - POWER_SUPPLY_PROP_CONNECTOR_THERM_ZONE, + POWER_SUPPLY_PROP_DIE_HEALTH, + POWER_SUPPLY_PROP_CONNECTOR_HEALTH, + POWER_SUPPLY_PROP_CTM_CURRENT_MAX, /* Local extensions of type int64_t */ POWER_SUPPLY_PROP_CHARGE_COUNTER_EXT, /* Properties of type `const char *' */ diff --git a/include/linux/qcom_tspp.h b/include/linux/qcom_tspp.h index 28e6695fb057..1b34c389d7f0 100644 --- a/include/linux/qcom_tspp.h +++ b/include/linux/qcom_tspp.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -70,6 +70,11 @@ struct tspp_select_source { int enable_inverse; }; +enum tsif_tts_source { + TSIF_TTS_TCR = 0, /* Time stamps from TCR counter */ + TSIF_TTS_LPASS_TIMER /* Time stamps from AV/Qtimer Timer */ +}; + typedef void (tspp_notifier)(int channel_id, void *user); typedef void* (tspp_allocator)(int channel_id, u32 size, phys_addr_t *phys_base, void *user); @@ -96,4 +101,8 @@ int tspp_allocate_buffers(u32 dev, u32 channel_id, u32 count, u32 size, u32 int_freq, tspp_allocator *alloc, tspp_memfree *memfree, void *user); +int tspp_get_tts_source(u32 dev, int *tts_source); +int tspp_get_lpass_time_counter(u32 dev, enum tspp_source source, + u64 *lpass_time_counter); + #endif /* _MSM_TSPP_H_ */ diff --git a/include/linux/qdsp6v2/rtac.h b/include/linux/qdsp6v2/rtac.h index 3e5433b23a51..eeea0eb0a837 100644 --- a/include/linux/qdsp6v2/rtac.h +++ b/include/linux/qdsp6v2/rtac.h @@ -1,4 +1,5 @@ -/* Copyright (c) 2011, 2013-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2011, 2013-2015, 2017, The Linux Foundation. All rights + * reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -95,4 +96,5 @@ int rtac_clear_mapping(uint32_t cal_type); bool rtac_make_afe_callback(uint32_t *payload, u32 payload_size); void rtac_set_afe_handle(void *handle); void get_rtac_adm_data(struct rtac_adm *adm_data); +void rtac_update_afe_topology(u32 port_id); #endif diff --git a/include/soc/qcom/cx_ipeak.h b/include/soc/qcom/cx_ipeak.h new file mode 100644 index 000000000000..b47e6b4f9b9d --- /dev/null +++ b/include/soc/qcom/cx_ipeak.h @@ -0,0 +1,46 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_COM_CX_IPEAK_H +#define __SOC_COM_CX_IPEAK_H + +struct device_node; +struct cx_ipeak_client; + +#ifndef CONFIG_QCOM_CX_IPEAK + +static inline struct cx_ipeak_client *cx_ipeak_register( + struct device_node *dev_node, + const char *client_name) +{ + return NULL; +} + +static inline void cx_ipeak_unregister(struct cx_ipeak_client *client) +{ +} + +static inline int cx_ipeak_update(struct cx_ipeak_client *ipeak_client, + bool vote) +{ + return 0; +} +#else + +struct cx_ipeak_client *cx_ipeak_register(struct device_node *dev_node, + const char *client_name); +void cx_ipeak_unregister(struct cx_ipeak_client *client); +int cx_ipeak_update(struct cx_ipeak_client *ipeak_client, bool vote); + +#endif + +#endif /*__SOC_COM_CX_IPEAK_H*/ diff --git a/include/soc/qcom/icnss.h b/include/soc/qcom/icnss.h index 6b567d7a08d3..731fa6970b95 100644 --- a/include/soc/qcom/icnss.h +++ b/include/soc/qcom/icnss.h @@ -17,6 +17,16 @@ #define ICNSS_MAX_IRQ_REGISTRATIONS 12 #define ICNSS_MAX_TIMESTAMP_LEN 32 +enum icnss_uevent { + ICNSS_UEVENT_FW_READY, + ICNSS_UEVENT_FW_CRASHED, +}; + +struct icnss_uevent_data { + enum icnss_uevent uevent; + void *data; +}; + struct icnss_driver_ops { char *name; int (*probe)(struct device *dev); @@ -28,6 +38,7 @@ struct icnss_driver_ops { int (*pm_resume)(struct device *dev); int (*suspend_noirq)(struct device *dev); int (*resume_noirq)(struct device *dev); + int (*uevent)(struct device *dev, struct icnss_uevent_data *uevent); }; diff --git a/include/soc/qcom/qseecomi.h b/include/soc/qcom/qseecomi.h index e33fd9fc1841..6497d962e347 100644 --- a/include/soc/qcom/qseecomi.h +++ b/include/soc/qcom/qseecomi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -511,6 +511,9 @@ __packed struct qseecom_continue_blocked_request_ireq { #define TZ_OS_REGISTER_LISTENER_ID \ TZ_SYSCALL_CREATE_SMC_ID(TZ_OWNER_QSEE_OS, TZ_SVC_LISTENER, 0x01) +#define TZ_OS_REGISTER_LISTENER_SMCINVOKE_ID \ + TZ_SYSCALL_CREATE_SMC_ID(TZ_OWNER_QSEE_OS, TZ_SVC_LISTENER, 0x06) + #define TZ_OS_REGISTER_LISTENER_ID_PARAM_ID \ TZ_SYSCALL_CREATE_PARAM_ID_3( \ TZ_SYSCALL_PARAM_TYPE_VAL, TZ_SYSCALL_PARAM_TYPE_BUF_RW, \ diff --git a/include/soc/qcom/service-notifier.h b/include/soc/qcom/service-notifier.h index 0106801fc173..740f7f644a02 100644 --- a/include/soc/qcom/service-notifier.h +++ b/include/soc/qcom/service-notifier.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -25,9 +25,12 @@ enum qmi_servreg_notif_service_state_enum_type_v01 { }; enum pd_subsys_state { - CRASHED, - SHUTDOWN, - UNKNOWN, + ROOT_PD_DOWN, + ROOT_PD_UP, + ROOT_PD_ERR_FATAL, + ROOT_PD_WDOG_BITE, + ROOT_PD_SHUTDOWN, + USER_PD_STATE_CHANGE, }; #if defined(CONFIG_MSM_SERVICE_NOTIFIER) diff --git a/include/sound/apr_audio-v2.h b/include/sound/apr_audio-v2.h index 1f8bba7e9ab7..ddc21d0c1bbb 100644 --- a/include/sound/apr_audio-v2.h +++ b/include/sound/apr_audio-v2.h @@ -1818,11 +1818,14 @@ struct afe_port_data_cmd_rt_proxy_port_read_v2 { #define AFE_PORT_SAMPLE_RATE_16K 16000 #define AFE_PORT_SAMPLE_RATE_48K 48000 #define AFE_PORT_SAMPLE_RATE_96K 96000 +#define AFE_PORT_SAMPLE_RATE_176P4K 176400 #define AFE_PORT_SAMPLE_RATE_192K 192000 +#define AFE_PORT_SAMPLE_RATE_352P8K 352800 #define AFE_LINEAR_PCM_DATA 0x0 #define AFE_NON_LINEAR_DATA 0x1 #define AFE_LINEAR_PCM_DATA_PACKED_60958 0x2 #define AFE_NON_LINEAR_DATA_PACKED_60958 0x3 +#define AFE_GENERIC_COMPRESSED 0x8 /* This param id is used to configure I2S interface */ #define AFE_PARAM_ID_I2S_CONFIG 0x0001020D @@ -2471,6 +2474,13 @@ struct afe_param_id_slimbus_cfg { */ #define AFE_PARAM_ID_USB_AUDIO_DEV_PARAMS 0x000102A5 + +/* ID of the parameter used to set the endianness value for the + * USB audio device. It should be used with + * AFE_MODULE_AUDIO_DEV_INTERFACE + */ +#define AFE_PARAM_ID_USB_AUDIO_DEV_LPCM_FMT 0x000102AA + /* Minor version used for tracking USB audio configuration */ #define AFE_API_MINIOR_VERSION_USB_AUDIO_CONFIG 0x1 @@ -2486,6 +2496,15 @@ struct afe_param_id_usb_audio_dev_params { u32 dev_token; } __packed; +struct afe_param_id_usb_audio_dev_lpcm_fmt { +/* Minor version used for tracking USB audio device parameter. + * Supported values: AFE_API_MINIOR_VERSION_USB_AUDIO_CONFIG + */ + u32 cfg_minor_version; +/* Endianness of actual end USB audio device */ + u32 endian; +} __packed; + /* ID of the parameter used by AFE_PARAM_ID_USB_AUDIO_CONFIG to configure * USB audio interface. It should be used with AFE_MODULE_AUDIO_DEV_INTERFACE */ @@ -2530,13 +2549,18 @@ struct afe_param_id_usb_audio_cfg { u16 reserved; /* device token of actual end USB aduio device */ u32 dev_token; +/* endianness of this interface */ + u32 endian; } __packed; struct afe_usb_audio_dev_param_command { struct apr_hdr hdr; struct afe_port_cmd_set_param_v2 param; struct afe_port_param_data_v2 pdata; - struct afe_param_id_usb_audio_dev_params usb_dev; + union { + struct afe_param_id_usb_audio_dev_params usb_dev; + struct afe_param_id_usb_audio_dev_lpcm_fmt lpcm_fmt; + }; } __packed; /* @@ -2734,25 +2758,31 @@ struct afe_param_id_tdm_cfg { - #AFE_PORT_SAMPLE_RATE_16K - #AFE_PORT_SAMPLE_RATE_24K - #AFE_PORT_SAMPLE_RATE_32K - - #AFE_PORT_SAMPLE_RATE_48K @tablebulletend */ + - #AFE_PORT_SAMPLE_RATE_48K + - #AFE_PORT_SAMPLE_RATE_176P4K + - #AFE_PORT_SAMPLE_RATE_352P8K @tablebulletend + */ u32 bit_width; /**< Bit width of the sample. - @values 16, 24 */ + * @values 16, 24, 32 + */ u16 data_format; - /**< Data format: linear and compressed - + /**< Data format: linear ,compressed, generic compresssed @values - #AFE_LINEAR_PCM_DATA - - #AFE_NON_LINEAR_DATA @tablebulletend */ + - #AFE_NON_LINEAR_DATA + - #AFE_GENERIC_COMPRESSED + */ u16 sync_mode; /**< TDM synchronization setting. @values (short, long, slot) sync mode - #AFE_PORT_TDM_SHORT_SYNC_BIT_MODE - #AFE_PORT_TDM_LONG_SYNC_MODE - - #AFE_PORT_TDM_SHORT_SYNC_SLOT_MODE @tablebulletend */ + - #AFE_PORT_TDM_SHORT_SYNC_SLOT_MODE @tablebulletend + */ u16 sync_src; /**< Synchronization source. @@ -3608,7 +3638,7 @@ struct afe_lpass_core_shared_clk_config_command { #define DEFAULT_COPP_TOPOLOGY 0x00010314 #define DEFAULT_POPP_TOPOLOGY 0x00010BE4 #define COMPRESSED_PASSTHROUGH_DEFAULT_TOPOLOGY 0x0001076B -#define COMPRESS_PASSTHROUGH_NONE_TOPOLOGY 0x00010774 +#define COMPRESSED_PASSTHROUGH_NONE_TOPOLOGY 0x00010774 #define VPM_TX_SM_ECNS_COPP_TOPOLOGY 0x00010F71 #define VPM_TX_DM_FLUENCE_COPP_TOPOLOGY 0x00010F72 #define VPM_TX_QMIC_FLUENCE_COPP_TOPOLOGY 0x00010F75 @@ -3914,6 +3944,8 @@ struct asm_softvolume_params { #define ASM_MEDIA_FMT_EVRCWB_FS 0x00010BF0 +#define ASM_MEDIA_FMT_GENERIC_COMPRESSED 0x00013212 + #define ASM_MAX_EQ_BANDS 12 #define ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2 0x00010D98 @@ -3923,6 +3955,40 @@ u32 fmt_blk_size; /* Media format block size in bytes.*/ } __packed; +struct asm_generic_compressed_fmt_blk_t { + struct apr_hdr hdr; + struct asm_data_cmd_media_fmt_update_v2 fmt_blk; + + /* + * Channel mapping array of bitstream output. + * Channel[i] mapping describes channel i inside the buffer, where + * i < num_channels. All valid used channels must be + * present at the beginning of the array. + */ + uint8_t channel_mapping[8]; + + /* + * Number of channels of the incoming bitstream. + * Supported values: 1,2,3,4,5,6,7,8 + */ + uint16_t num_channels; + + /* + * Nominal bits per sample value of the incoming bitstream. + * Supported values: 16, 32 + */ + uint16_t bits_per_sample; + + /* + * Nominal sampling rate of the incoming bitstream. + * Supported values: 8000, 11025, 16000, 22050, 24000, 32000, + * 44100, 48000, 88200, 96000, 176400, 192000, + * 352800, 384000 + */ + uint32_t sampling_rate; + +} __packed; + struct asm_multi_channel_pcm_fmt_blk_v2 { struct apr_hdr hdr; struct asm_data_cmd_media_fmt_update_v2 fmt_blk; @@ -9971,6 +10037,108 @@ struct afe_port_group_create { union afe_port_group_config data; } __packed; +/* ID of the parameter used by #AFE_MODULE_AUDIO_DEV_INTERFACE to specify + * the timing statistics of the corresponding device interface. + * Client can periodically query for the device time statistics to help adjust + * the PLL based on the drift value. The get param command must be sent to + * AFE port ID corresponding to device interface + + * This parameter ID supports following get param commands: + * #AFE_PORT_CMD_GET_PARAM_V2 and + * #AFE_PORT_CMD_GET_PARAM_V3. + */ +#define AFE_PARAM_ID_DEV_TIMING_STATS 0x000102AD + +/* Version information used to handle future additions to AFE device + * interface timing statistics (for backward compatibility). + */ +#define AFE_API_VERSION_DEV_TIMING_STATS 0x1 + +/* Enumeration for specifying a sink(Rx) device */ +#define AFE_SINK_DEVICE 0x0 + +/* Enumeration for specifying a source(Tx) device */ +#define AFE_SOURCE_DEVICE 0x1 + +/* Enumeration for specifying the drift reference is of type AV Timer */ +#define AFE_REF_TIMER_TYPE_AVTIMER 0x0 + +/* Message payload structure for the + * AFE_PARAM_ID_DEV_TIMING_STATS parameter. + */ +struct afe_param_id_dev_timing_stats { + /* Minor version used to track the version of device interface timing + * statistics. Currently, the supported version is 1. + * @values #AFE_API_VERSION_DEV_TIMING_STATS + */ + u32 minor_version; + + /* Indicates the device interface direction as either + * source (Tx) or sink (Rx). + * @values + * #AFE_SINK_DEVICE + * #AFE_SOURCE_DEVICE + */ + u16 device_direction; + + /* Reference timer for drift accumulation and time stamp information. + * @values + * #AFE_REF_TIMER_TYPE_AVTIMER @tablebulletend + */ + u16 reference_timer; + + /* + * Flag to indicate if resync is required on the client side for + * drift correction. Flag is set to TRUE for the first get_param + * response after device interface starts. This flag value can be + * used by client to identify if device interface restart has + * happened and if any re-sync is required at their end for drift + * correction. + * @values + * 0: FALSE (Resync not required) + * 1: TRUE (Resync required) @tablebulletend + */ + u32 resync_flag; + + /* Accumulated drift value in microseconds. This value is updated + * every 100th ms. + * Positive drift value indicates AV timer is running faster than device + * Negative drift value indicates AV timer is running slower than device + * @values Any valid int32 number + */ + s32 acc_drift_value; + + /* Lower 32 bits of the 64-bit absolute timestamp of reference + * timer in microseconds. + + * This timestamp corresponds to the time when the drift values + * are accumlated for every 100th ms. + * @values Any valid uint32 number + */ + u32 ref_timer_abs_ts_lsw; + + /* Upper 32 bits of the 64-bit absolute timestamp of reference + * timer in microseconds. + * This timestamp corresponds to the time when the drift values + * are accumlated for every 100th ms. + * @values Any valid uint32 number + */ + u32 ref_timer_abs_ts_msw; +} __packed; + +struct afe_av_dev_drift_get_param { + struct apr_hdr hdr; + struct afe_port_cmd_get_param_v2 get_param; + struct afe_port_param_data_v2 pdata; + struct afe_param_id_dev_timing_stats timing_stats; +} __packed; + +struct afe_av_dev_drift_get_param_resp { + uint32_t status; + struct afe_port_param_data_v2 pdata; + struct afe_param_id_dev_timing_stats timing_stats; +} __packed; + /* Command for Matrix or Stream Router */ #define ASM_SESSION_CMD_SET_MTMX_STRTR_PARAMS_V2 0x00010DCE /* Module for AVSYNC */ @@ -10182,6 +10350,7 @@ enum { COMPRESSED_PASSTHROUGH_CONVERT, COMPRESSED_PASSTHROUGH_DSD, LISTEN, + COMPRESSED_PASSTHROUGH_GEN, }; #define AUDPROC_MODULE_ID_COMPRESSED_MUTE 0x00010770 diff --git a/include/sound/q6afe-v2.h b/include/sound/q6afe-v2.h index e4033e712804..b1c3b0baf4b3 100644 --- a/include/sound/q6afe-v2.h +++ b/include/sound/q6afe-v2.h @@ -364,6 +364,8 @@ int afe_send_custom_tdm_header_cfg( struct afe_param_id_custom_tdm_header_cfg *custom_tdm_header_cfg, u16 port_id); int afe_tdm_port_start(u16 port_id, struct afe_tdm_port_config *tdm_port, - u32 rate); + u32 rate, u16 num_groups); void afe_set_routing_callback(routing_cb); +int afe_get_av_dev_drift(struct afe_param_id_dev_timing_stats *timing_stats, + u16 port); #endif /* __Q6AFE_V2_H__ */ diff --git a/include/sound/q6asm-v2.h b/include/sound/q6asm-v2.h index 9a3db9aaa25e..76bb795119c2 100644 --- a/include/sound/q6asm-v2.h +++ b/include/sound/q6asm-v2.h @@ -54,6 +54,7 @@ #define FORMAT_DTS 0x001c #define FORMAT_DSD 0x001d #define FORMAT_APTX 0x001e +#define FORMAT_GEN_COMPR 0x001f #define ENCDEC_SBCBITRATE 0x0001 #define ENCDEC_IMMEDIATE_DECODE 0x0002 @@ -500,6 +501,11 @@ int q6asm_media_format_block_multi_ch_pcm_v2( uint32_t rate, uint32_t channels, bool use_default_chmap, char *channel_map, uint16_t bits_per_sample); +int q6asm_media_format_block_gen_compr( + struct audio_client *ac, + uint32_t rate, uint32_t channels, + bool use_default_chmap, char *channel_map, + uint16_t bits_per_sample); int q6asm_media_format_block_multi_ch_pcm_v3(struct audio_client *ac, uint32_t rate, uint32_t channels, diff --git a/include/trace/events/power.h b/include/trace/events/power.h index 8387688fb71b..19136453a5e2 100644 --- a/include/trace/events/power.h +++ b/include/trace/events/power.h @@ -304,6 +304,7 @@ DEFINE_EVENT(wakeup_source, wakeup_source_deactivate, * The clock events are used for clock enable/disable and for * clock rate change */ +#if defined(CONFIG_COMMON_CLK_MSM) DECLARE_EVENT_CLASS(clock, TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id), @@ -401,6 +402,7 @@ TRACE_EVENT(clock_state, __get_str(name), __entry->prepare_count, __entry->count, __entry->rate, __entry->vdd_level) ); +#endif /* CONFIG_COMMON_CLK_MSM */ /* * The power domain events are used for power domains transitions diff --git a/include/uapi/linux/dvb/dmx.h b/include/uapi/linux/dvb/dmx.h index a768696c90f8..175534a26792 100644 --- a/include/uapi/linux/dvb/dmx.h +++ b/include/uapi/linux/dvb/dmx.h @@ -148,6 +148,9 @@ enum dmx_video_codec { #define DMX_IDX_VC1_FRAME_END 0x02000000 #define DMX_IDX_H264_ACCESS_UNIT_DEL 0x04000000 #define DMX_IDX_H264_SEI 0x08000000 +#define DMX_IDX_H264_IDR_ISLICE_START 0x10000000 +#define DMX_IDX_H264_NON_IDR_PSLICE_START 0x20000000 +#define DMX_IDX_H264_NON_IDR_BSLICE_START 0x40000000 struct dmx_pes_filter_params { diff --git a/include/uapi/linux/msm_ipa.h b/include/uapi/linux/msm_ipa.h index 6aa021e12930..16e4b8e30b07 100644 --- a/include/uapi/linux/msm_ipa.h +++ b/include/uapi/linux/msm_ipa.h @@ -147,7 +147,9 @@ enum ipa_client_type { IPA_CLIENT_A5_WLAN_AMPDU_PROD, IPA_CLIENT_A2_EMBEDDED_PROD, IPA_CLIENT_A2_TETHERED_PROD, - IPA_CLIENT_APPS_LAN_WAN_PROD, + IPA_CLIENT_APPS_LAN_PROD, + IPA_CLIENT_APPS_WAN_PROD, + IPA_CLIENT_APPS_LAN_WAN_PROD = IPA_CLIENT_APPS_WAN_PROD, IPA_CLIENT_APPS_CMD_PROD, IPA_CLIENT_ODU_PROD, IPA_CLIENT_MHI_PROD, diff --git a/include/uapi/linux/msm_mdp.h b/include/uapi/linux/msm_mdp.h index fca2a3c2d494..481814cb8498 100644 --- a/include/uapi/linux/msm_mdp.h +++ b/include/uapi/linux/msm_mdp.h @@ -119,6 +119,7 @@ #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msm8998 */ #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msm8998 v1.0 */ #define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) /* sdm660 */ +#define MDSS_MDP_HW_REV_330 MDSS_MDP_REV(3, 3, 0) /* sdm630 */ enum { NOTIFY_UPDATE_INIT, |