| Age | Commit message (Collapse) | Author |
|---|
|
The request to change the VDD I/O voltage level to high/low will
trigger an IRQ only when -
1. SWITCHABLE_SIGNALING_VOLTAGE bit 29 of SDCC_MCI_GENERICS register
is set.
2. Above condition is true and when there is a state change in VDD
bit 3 of SDHCi Host Control 2 register.
Until now, the MMC core layer issues I/O high request only after
the controller is powered up. The I/O high request is same as the reset
state of host control2 register which will never trigger an IRQ. The
driver already handles this case by ensuring that I/O voltage is set
to high as part of power up itself and thus returns immediately when
I/O high request is issued later. But in 3.10 kernel, this request is
issued even before the controller is powered up. Hence, check for
host->pwr state to avoid waiting for an IRQ that never comes.
Change-Id: I31b6723f53397be1ba151305ead89e739560eb20
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
Some SDHC controllers are unable to handle data end-bit
errors in one bit mode.
This patch adds a quirk to ignore data-end-bit error in
1-bit mode in Qualcomm SDHC controllers.
Change-Id: Ica0f10573d654021449c32197b126e12bb1a3c10
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[venkatg@codeaurora.org: sdhci_clear_set_irqs was removed
from 3.14 kernel, write the registers directly]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict and fixed
the bitmap for the quirk macro]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
Fix following bug -
foo_bar1(int arg1, unsigned long flags) {
spin_unlock_irqrestore(lock, flags); // step 1
<do something>;
spin_lock_irqsave(lock, flags); // step 2
}
foo_bar() {
unsinged long flags;
spin_lock_irqsave(lock, flags); // step 3
foo_bar1(arg1, flags);
spin_unlock_irqrestore(lock, flags); // step 4
}
The "flags" might be changed in step 4 due to irqrestore and irqsave
in foo_bar1().
Change-Id: I42366f7acdde022705f4b3dd06122d54ad817078
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
|
|
Implement dump_vendor_registers host operation to print the
vendor specific registers in addition to standard SDHC
register during error conditions.
Change-Id: I347e8f0373264574a80e460967afba6859607ac9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
Add new host operation dump_vendor_regs to provide a
mechanism through which host drivers can dump vendor
specific registers in addition to SDHC registers
during error conditions.
Change-Id: Ifba3ddcb18c3c0917343d99fe58d5ed04b2da871
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
The auto command error interrupt is not enabled now. Hence,
if there occurs a timeout when auto-cmd is in progress,
no data timeout interrupt would occur and the driver would
only timeout after the software timer expires.
This patch enables the auto command error interrupt and lets the
higher layers know of such an error, if any.
CRs-Fixed: 515513
Change-Id: I69880a72ece7730645dcfe699d58271d60cab33d
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
|
|
This patch adds support to configure regulators only if
it is defined in dts files. However, it doesn't return an
error otherwise.
Change-Id: Iac2284b2df3b3d8af623da0f17697694994b34b8
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
|
|
This flag ensures that the power to the sdio card is not
cut-off. That way this can wake-up the device when required
using asynchronous interrupt mechanism.
Change-Id: Ic91bfdc93e117c5e627360a4d0ef80f661aa1b60
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
|
|
Provide sysfs tunables to defer PM QoS vote of default value so that
back-to-back requests wouldn't suffer from latencies caused by CPU
power collapse transition states.
Change-Id: I7180c68c1f13240faa5f432335d72e7f6b198183
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
PM QoS vote of default value mean that the CPU is allowed to move
into deepest low power mode whenever possible. Currently, if there
are back-to-back MMC requests, with a short delay, the PM QoS vote
to default value is done immediately which cause the immediate
request to have high latency as the CPU might have idle'd and moved
to deepest low power mode. To avoid this defer the PM QoS vote till
a defined timeout (pm_qos_timeout_us), so that back-to-back requests
may not suffer from additional latencies.
In addition, if the load on MMC is low, the additional latency may be
sustainable. Hence, aggressively release the vote in order to achieve
additional power savings.
CRs-Fixed: 501712
Change-Id: I82166b0ce9416eb0d519f7da26e5a96956093cb2
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict and fixed
compilation errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
The specification indicates that the tuning process is normally
shorter than 40 exections of tuning command. Hence, retry the
tuning sequence for at least 3 times before returning the error.
Change-Id: I21724a73af7b997e128b56a2600bdcb12e414996
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
Add support for polling by providing sysfs entry. It can be
enabled/disabled, by writing 1/0 respectively to the sysfs node -
sys/bus/platform/devices/msm_sdcc.<slotno>/polling. The polling
will be available only if hardware based card detection is not
supported.
Change-Id: Ic58c36665e23cb921d76c482494a168289e83b83
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
MMC_CAP_HW_RESET capability was only referring to host driver
capability to toggle eMMC RST_n pin so if the host driver is
unable to toggle this pin, it shouldn't advertise this capability.
CRs-Fixed: 507926
Change-Id: Ia1408d95503d19ae0f7c49c7bb7905b0ddaddbd5
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
The driver currently uses fixed timeout value from capabilities
register (bit 5-0) to calculate the timeout which is advertized
as 50MHz. But the driver uses SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK
and controls the base clock (MCLK) directly. So during card
initialization, the frequency would be 400KHz but still timeout
is calculated at 50MHz which is wrong. This patch fixes this by
using the current base clock frequency to calculate the timeout.
The controller internally multiplies the timeout control register
value by 4 with the assumption that driver always uses fixed
timeout clock value from capabilities register. Add a quirk
SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 to avoid this multiplicaiton in
case base clock is used for timeout calculation.
CRs-fixed: 498159
Change-Id: I503fd16132bf17e590239997d6970b9b730d4202
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
SDIO 3.0 specification has added the support for asynchronous interrupt
period during which card allows the clock to be gated off.
As SDCC driver is capable of handling the asynchronous interrupt,
advertise MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE capability.
Change-Id: Id5a86bc70b7b798b23be3a0fc0d59b2db05e0409
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
SDCC controller provides the PWRSAVE control bit to automatically
disable the clock to card when there is no activity with card.
During the SDCC DLL tuning, PWRSAVE is disabled to make sure that clock
is always running but once the DLL tuning is completed, currently we
enable the PWRSAVE unconditionally irrespective of its previous state.
This change ensures that we always check if the previous state of pwrsave
before really enabling it.
Change-Id: I464ab1e0db41af50550bb5a9ea9b909ee0d27dd9
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
The drivers must do clk_set_rate() before the first
clk_prepare_enable() is invoked. Otherwise, the clock
driver may give a warning for such clocks.
CRs-fixed: 493685
Change-Id: I8342aa2f35d64a4dc7b8396bd9741c0aecaedc5c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
Enable MMC_CAP2_CD_ACTIVE_HIGH capability if the card-detect
gpio polarity is active high.
Change-Id: I80e869dd7ecb6e24e81d1cc73ef8101c44110873
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
|
|
The current driver just enables "iface_clk" before accessing its
registers but MSM bus clocks are also required for register access
without which any register access would result in chip reset.
The MSM bus clocks can be enabled by setting vote to MSM bus bandwidth
driver. Currently, voting is being done in sdhci_enable/disable but these
functions will not be invoked by MMC core layer for some cases such
as mmc_power_up/mmc_power_off, which require peripheral register
access.
To resolve the above mentioned problem, bus voting and de-voting will
now be done as part of clock management within the sdhci MSM driver
i.e., before enabling SDHC clocks and after disabling SDHC clocks.
Change-Id: Iff608fba4c58bf37a6f4ce8eb36876c79969feaf
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
The SDHC driver registers sdhci_led_control() with LED class device
and it gets invoked when the sysfs entry - /sys/class/leds/mmcX::
is updated. This function access SDHC Host control register (0x28)
and hence, check the driver state (runtime suspended/clocks gated)
before accessing it. Otherwise, it may result in unclocked access
resulting in system failure.
CRs-fixed: 480596
Change-Id: Icef51f02abb54316710df30429fec875030d42d9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
SDCC controller reset (SW_RST) during probe may trigger power irq if
previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
enable the power irq interrupt in GIC (by registering the interrupt
handler), we need to ensure that any pending power irq interrupt status
is acknowledged otherwise power irq interrupt handler would be fired
prematurely.
CRs-Fixed: 487962
Change-Id: If4693869210bc8b361dadb2b68a47b6ac8707e0f
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
Wait for SW reset to be complete before proceeding further
in probe. Otherwise, any register writes immediately
after the reset would be ignored/reset.
Change-Id: If1c7f5debfca6f45a0fdb08bc759ad04b96fd86c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
The version register is only 16 bits wide but we use a readl to
read it. Normally this wouldn't be a problem, but the register
offset is 0xfe, something that is not word aligned. This causes
crashes on THUMB2 kernels. Use readw instead to read the register
properly and avoid any alignment issues.
Change-Id: I3b8b14ce2f741631ef7554e3763d1d7f145077a8
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
The MSM SDHCI controller defines the usage of 0xF in data
timeout counter register (0x2E) which is actually a reserved
bit as per specification. This would result in maximum of
5.3 secs timeout value. For some buggy SD cards, the core
layer wants to set the data timeout to 3 secs and on our MSM
SDHCI if we configure data timeout counter value to 0xE,
then we would get only 2.67 secs. Observed data timeout errors
for CMD25 on SDR104 card. Hence program data timeout counter to
0xF, to achieve at least 3 secs timeout value.
CRs-fixed: 470661
Change-Id: Ie1e192eb9c38ca3922bb1f518073a8ff0cb57f0c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
If preset value (bit 15) is enabled in sdhci host control2
register (0x3E), then the preset value registers(0x6F-0x60)
would be used for some of the settings such as clock and
drive strength. These are HW initialized registers and are
not properly initialized by MSM SDHCI controller. This is
resulting in low throughput for some of the modes such as
DDR50/SDR50. Hence, do not enable it for MSM SDHCI.
CRs-fixed: 474518
Change-Id: Iee1241355d14e6bcebc66c3a43abf1ec94d869c3
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
Ignore data timeout error for R1B commands as there will be no
data associated and the busy timeout value for these commands
could be lager than the maximum timeout value that controller
can handle.
CRs-fixed: 473435
Change-Id: I61f7463cf09648ad9fab83437abf5004effc7758
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
This helps check the controller timeout logic in case of data
timeout errors.
Change-Id: Ia30757192e49865698c5f52940e1dc5d97746185
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
The driver is using wrong clock rate to calculate the required
bandwidth and due to this voting is happening for more bandwidth
than it is required. This is ultimately preventing system core
voltage from entering into low power mode.
The sdhci_host clock indicates the clock rate as requested by MMC
core layer and the actual rate that is set is indicated by clk_rate
within struct sdhci_msm_host. As of now, sdhci_host clock is being
used to calculate the bandwidth whereas bus-bw-vectors-bps indicates
only supported bandwidths and hence a mismatch. Fix this by using the
right clock rate which is clk_rate within struct sdhci_msm_host.
Change-Id: If7d81e44a9b479c4c8e9fbaa7e092af2afb9cb9f
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
This patch fixes the following issues in sdhci driver
from msm 3.9 kernel -
1. gpio_get_value_cansleep() is used from atomic context
resulting in warning from gpio driver. Move it to non-atomic
context.
2. Move sdhci_enable_preset_value() in set_ios callback after
clocks are enabled otherwise it would result in access to SDHCI
registers if clocks are disabled due to clock gating or suspend.
Change-Id: I231aa6e5c02669cf1aa3f21764642fa7da9a01ff
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
The SDHC core power control IRQ gets triggered when -
* there is a state change in power control bit (bit 0)
of SDHCI_POWER_CONTROL register.
* there is a state change in 1.8V enable bit (bit 3) of
SDHCI_HOST_CONTROL2 register.
* Bit 1 of SDHCI_SOFTWARE_RESET is set.
This patch addresses the following 2 issues -
The reset state of 1.8V enable bit in SDHCI_HOST_CONTROL2 is 0
which indicates 3.3V IO voltage. So, when MMC core layer tries to
set it to 3.3V before card detection, the IRQ doesn't get
triggered as there is no state change in this bit. Hence, with
the current code, the VDD IO voltage is never getting set to
3.3V. This patch fixes this issue by setting the VDD IO voltage
to 3.3V whenever SDHC gets powered up.
We get different IRQ ACK status for each of these requests -
power on, power off, IO high, IO low. As of now, the driver is
not considering the IRQ ACK for IO high and IO low requests and
is returing prematurely from check_power_status() based on the
previous ACK for power on/off requests. This is resulting voltage
switch errors during voltage switch sequence for SD/eMMC cards.
This issue is fixed by passing the request type to
check_power_status host op so that driver can wait for its
corresponding ACK from power IRQ.
Change-Id: I07707ac5df731a0d3e4abead28076f0bbbf75c0a
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
MSM SDHCI doesn't control power as specified by the Standard
Host Controller 3.0 spec. Writing to power control register/
reset register/voltage bit of host control register would
trigger an IRQ with appropriate status bits set. Hence, use
host op check_power_status after writing to power control
register to check the status and wait until the IRQ is handled.
Change-Id: Ied1a82e385547f7f5d60807fc896ea5a13084657
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: fix trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict
& compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
The SDHCi driver by default specifies a parameter that causes the
core layer to calculate a max discard value which will be set on the
mmc queue. Unfortunately the value calculated because of this would
be very small compared to what comes in by default. As a result of
this, any secure discard kind of operations are very slow.
Instead add quirk so that any SDHCi hosts that would like to use
the default value can do so.
Change-Id: Ifa1343c3e7f14b031da30b06203a8831ba544889
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
[venkatg@codeaurora.org: change max_discard_to was renamed to
max_busy_timeout in 3.14 kernel]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
This patch checks the device state before starting a request.
It also prints out useful information in case of error
conditions.
Change-Id: Iaf87bb069c3ffb13c9b3f174c07c25d612bdcee9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[venkatg@codeaurora.org: remove pm related stuff]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
The BKOPS feature is supported for eMMC cards of version 4.41 and higher.
The BKOPS feature is one time programmable and once it was enabled on
a certain MMC card is cannot be disabled.
LA builds are often being used to verify phones that are targeted for
other HLOSes. Since not all the HLOSes implement the BKOPS features,
enabling this feature by default can cause instability when the phone
will be used by HLOSes other than LA.
Change-Id: I7b9eab0d04a86dfeaf7565dcda8bc9d2035fe02d
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
Add support to disable available SDHC slots at bootup controlled via a
module param with a bit mask of slots to disable. QDSS is one use case
where SDHC slot is disabled for trace output.
Example Usage:
Passing sdhci_msm.disable_slots=1 as kernel command line argument would
disable SDHC slot 1, whereas passing sdhci_msm.disable_slots=3 would
disable both slots 1 and 2.
Change-Id: I97bc517adfe4a1a81a97a2789d77404b0f22b124
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
|
|
Add support for enabling clock scaling feature and indicate
the same to MMC core layer by setting the capability
MMC_CAP2_CLK_SCALE.
Change-Id: I24f144d3f727160c302966888fb439b3a39a0dde
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: sdhci_set_clock is now a library function
thats called from platform clock handler, make changes to address that]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
The MSM SDHCI controller requires SDR104 mode to be set for HS200
cards. To handle this case, implement uhs_set_signaling so that
the mode selection for MSM SDHCI doesn't happen in sdhci driver.
Change-Id: I901dc82312b4299e86a7812dd74d3682650966a2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: Fix fn signature for set_uhs_signaling
that changed as part of 3.14 kernel]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
|
|
Set the dma_mask to 0xffffffff to indicate full 32-bit
address space and thus avoiding unnecessary buffers bouncing
from high to low memory.
Change-Id: Idaffe14d4e54a27b15e5a5d82dad41d843714d57
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
Add support for hardware based card detection for external
SD card slot.
Change-Id: I3e081f2eff54d6932a89f826cc85c201c52ca840
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: Fix arguments for mmc_gpio_request_cd
as the signature had changed in 3.14 kernel]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
|
|
Vote for the MSM bus bandwidth required by SDHC driver
based on the speed and bus width of the card. Otherwise,
the system clocks may run at minimum clock speed and
thus affecting the performance.
Change-Id: Icf0c8710adbe2770f4eae283a50f4a13671f703f
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
Vote for PM QOS by specifying the acceptable CPU to DMA latency
so that system can enter into the possible power states without
affecting the SDHC performance.
Change-Id: I5fcf9aa93da690c6e64ab70ea5b039ca663c80ad
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict and compilation
errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
This reverts commit 40433267331bc6b9d70d5cdd14bfa2c8e3e5f0ec as
MSM platforms still needs ->enable/disable() callbacks.
Conflicts:
drivers/mmc/core/core.c
Change-Id: Ifd986825c10f1475bfcdac37ea1f3b99e5f6daaf
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
Enable config MMC_CLKGATE to enable aggressive clock gating framework that
will disable clocks when the host is not in use for 200ms.
Change-Id: I6bef5dc18b561871689b3d730fd3486323b12520
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[venkatg@codeaurora.org: sdhci_set_clock is now a library function thats
called from platform clock handler, make changes to address that]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
This patch adds a function to configure adma descriptors to
support request size upto 512MB.
Change-Id: Ie2ad32106422bb5bdbf72b08d1ecdd74d9a93c19
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
|
|
Enable MMC_CAP_HW_RESET capability so that MMC block layer
can reset the hardware during error recovery scenarios.
Change-Id: I6100a3c6c34ee4c965595e422f793b195a758a46
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
Implement platform_execute_tuning and toggle_cdr callbacks that are
needed to support HS200 and SDR104 bus speed modes. Also, set
IO_PAD_PWR_SWITCH control bit in vendor specific register if
the IO voltage level is within low voltage range (1.7v - 1.9v).
Change-Id: If41704758d097229ffc0204d581886e137e8b581
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[venkatg@codeaurora.org: Rename tuning ops fn to platform_execute_tuning]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
|
|
MSM SDHCI controller doesn't support tuning as specified by the
Standard Host Controller 3.0 spec. As a result of which,
CMD CRC errors are expected for tuning commands. Hence, add a
new quirk SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING to ignore
those errors for tuning commands.
Change-Id: Id43d300bf8fabea921c80931fbf45cd3782ff3fa
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
Initial version of Qualcomm SDHC has the following two h/w
issues. This patch adds s/w workarounds for the same.
H/W issue: Read Transfer Active/ Write Transfer Active may be not
de-asserted after end of transaction.
S/W workaround: Set Software Reset for DAT line in Software Reset
Register (Bit 2).
Added a quirk SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT to enable this workaround.
H/W issue: Slow interrupt clearance at 400KHz may cause host controller
driver interrupt handler to be called twice.
S/W Workaround: Add 40us delay in interrupt handler when operating at
initialization frequency(400KHz).
Added a quirk SDHCI_QUIRK2_SLOW_INT_CLR to enable this workaround.
Change-Id: I8b4062f101085adadd66560f77b98b04d75cb836
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
|
This patch adds the pad and tlmm configuration to msm-sdhci
driver.
Change-Id: Ic2b9beffdb555598bdc15b4b03c8adb78fbd0c2c
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
|
|
This platform driver adds the support of Secure Digital Host
Controller Interface compliant controller in MSM chipsets.
Change-Id: Ide3a658ad51a3c3d4a05c47c0e8f013f647c9516
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fix trivial merge conflicts and Changed
Qualcomm to Qualcomm Technologies, Inc.]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
|
