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2016-05-31mmc: core: Add sysfs entries for dynamic control of clock scalingSujit Reddy Thumma
Add sysfs attributes to allow dynamic control of clock scaling parameters. These attributes are used to enable/disable clock scaling at runtime and change the up_threshold, down_threshold, and polling_interval values. Complete documentation for these sysfs entries are provided at "Documentation/mmc/mmc-dev-attrs.txt". Change-Id: I4753c75c3b3eeea91e93bceba7af2535b793612e Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org> Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
2016-05-31mmc: block: Add write packing controlTatyana Brokhman
The write packing control will ensure that read requests latency is not increased due to long write packed commands. The trigger for enabling the write packing is managing to pack several write requests. The number of potential packed requests that will trigger the packing can be configured via sysfs by writing the required value to: /sys/block/<block_dev_name>/num_wr_reqs_to_start_packing. The trigger for disabling the write packing is fetching a read request. Change-Id: I22e8ab04cd9aca220678784c39306068a0996790 Signed-off-by: Maya Erez <merez@codeaurora.org> Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org> [merez@codeaurora.org: fixed trivial conflicts] Signed-off-by: Maya Erez <merez@codeaurora.org> [subhashj@codeaurora.org: fixed trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
2016-05-27mmc: host: sdhci: allow definition of pm QoS via dts fileMaya Erez
Add a new dts entry to define the CPU affinity in order to maintain the IRQ pm_qos (Quality of Service) for targets that don't have little cluster and allow setting the pm_qos to the little cluster, to improve its performance. Change-Id: Icf6125066d96331392d98a387974e54c96553306 Signed-off-by: Vince Leung <vincentl@codeaurora.org> Signed-off-by: Maya Erez <merez@codeaurora.org>
2016-05-27mmc: sdhci-msm: add nonhotplug supportGuoping Yu
With some devices like QRD SKUK, SD card could not support hotplug as there is no cd-gpio, and also could not use polling way due to power comsumption. So add nonhotplug to meet such requirement and when SD card lost or removed manually, device will not crash until next reboot process to detect SD card. Change-Id: I318d3db72fc09248c5dada2fb6d69ade1bbf85cb Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
2016-05-27mmc: sdhci: Add support for pinctrl interfacePratibhasagar V
Add support for Linux pin control framework while also supporting the older TLMM configuration for backward compatibility CRs-Fixed: 568232 Change-Id: Ib6b8f41fd6ced9aa62c980d7e4a73469603cbc5b Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
2016-05-27mmc: sdhci-msm: Add HS400 platform supportVenkat Gopalakrishnan
The following msm platform specific changes are added to support HS400. - Enable CDC calibration fixed feedback and sleep clock. - Allow tuning for HS400 mode. - Add capability to parse and configure pull settings for RCLK pin. - Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register. Change-Id: I1304fe0f01df493ead48bf9ff3c7baee5ab040d4 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
2016-05-27mmc: host: add pad and tlmm configurationAsutosh Das
This patch adds the pad and tlmm configuration to msm-sdhci driver. Change-Id: Ic2b9beffdb555598bdc15b4b03c8adb78fbd0c2c Signed-off-by: Asutosh Das <asutoshd@codeaurora.org> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
2016-05-27mmc: host: add SDHCI platform driver for msm chipsetsAsutosh Das
This platform driver adds the support of Secure Digital Host Controller Interface compliant controller in MSM chipsets. Change-Id: Ide3a658ad51a3c3d4a05c47c0e8f013f647c9516 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> [subhashj@codeaurora.org: fix trivial merge conflicts and Changed Qualcomm to Qualcomm Technologies, Inc.] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
2016-05-19Revert "mmc: core: Remove MMC_CLKGATE"Subhash Jadavani
This reverts commit 9eadcc0581a8ccaf4c2378aa1c193fb164304f1d. Clock gating is needed for Qualcomm Platforms hence reverting this upstream patch. Change-Id: I96ac0c1c7627e8e5c2d18782e2fc08608f0a7f91 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
2016-05-18NFC: Add snapshot of NQxxx NFC driverGaurav Singhal
Add the latest version of NQxxx NFC driver from msm-3.18. This change is a combination of following changes: 1) NFC: add NQxxxx driver commit <356203701b7fd61b2d9776fac4fac6427735248b> 2) NFC: change reset and read flow commit <7620346454865b81d7086167d531aea7bb716926> 3) NFC: Enable DMA and CLK_REQ gpio config issue fix commit <150dbf117709b5677f86e5ced86b468731019b8b> 4) NFC: Fix function descriptions commit <c0248d70200c8e09a983758750632b7a75e422d3> 5) nq-nci: enable NFCC hardware check and clock to NQxx commit <2a92c1d6135f2d1e8fe3f2afcd290a2b1311a5a2> 6) nq-nci: XO shut down issue fix commit <8938151d4650fca6d42efdbce138aea9bad7eca0> 7) NFC: Remove sleep from irq handler commit <8ea2c805108cbf59b8e2abf87ee207fbf08fad97> 8) NFC: Remove DMA allocation and stack use in write commit <c1552090e4c46e1eeca756d0a7b4427f94eab0c3> CRs-Fixed: 890678, 892310, 955860, 968399, 993292 Change-Id: Ibb861ebdc63d45699369e23c077589d37e024b5e Signed-off-by: Gaurav Singhal <gsinghal@codeaurora.org>
2016-05-16soc: qcom: dcc: add support for DCC XPU lock/unlock requestShashank Mittal
Add support to request TZ to lock and unlock DCC XPU. DCC XPU is unlocked before accessing DCC and is locked back again after configuring DCC. Change-Id: I8815f65551df0b80f7ecdcaa338a50db8d9b04f5 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-05-16soc: qcom: dcc: add support for DCC driverShashank Mittal
DCC (Data Capture and Compare) is a DMA engine which is used to save configuration data or system memory contents during catastrophic failure or SW trigger. It can also perform CRC over the same configuration or memory space. Change-Id: Ic8a804250ab8b7ac501bd186d2e6f7506bb9b21a Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-05-16Revert "sched: set HMP scheduler's default initial task load to 100%"Joonwoo Park
This reverts commit 28f67e5a50d7c1bfc ("sched: set HMP scheduler's default initial task load to 100%") since 100% of init task load makes too much of power inefficiency on some targets. CRs-fixed: 1006303 Change-Id: I81b4ba8fdc2e2fe1b40f18904964098fa558989b Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
2016-05-16msm: pcie: retrieve PCIe SMMU SID base from DTTony Truong
SMMU SIDs allocated for PCIe varies across chipsets. Thus, add support to retrieve the base SID from PCIe devicetree node so that PCIe bus driver can use it to calculate and assign to each PCI device. Change-Id: I7651f2cbc53587f5b48501855260c87af2a2db01 Signed-off-by: Tony Truong <truong@codeaurora.org>
2016-05-16msm: pcie: add support to get PCIe PHY init sequence from DTTony Truong
PCIe PHY varies between each chipset. Thus, the PHY init sequence on each of these chipsets are also different. Therefore, add the support to read PCIe PHY init sequence from devicetree. Change-Id: I21c2ce2b7d3bf1541a5d3580db4bc40497701095 Signed-off-by: Tony Truong <truong@codeaurora.org>
2016-05-15soc: qcom: Add snapshot of the cpuss driverRunmin Wang
This snapshot is taken as of msm-3.18 commit dacccc6. CRs-Fixed: 1011333 Change-Id: I4ed06b5602220ed4e30bd37a0633ccb3454f7d43 Signed-off-by: Runmin Wang <runminw@codeaurora.org>
2016-05-12power: bcl_peripheral: Support new bcl peripheralRam Chandrasekar
Add support for the new version of bcl peripheral introduced in PMIcobalt. The new support includes, 1. support the new address space 2. set the new Ibat too high threshold 3. set the new vbat low comparator threshold 4. set the new vbat too low comparator threshold 5. enable the LMH DCVSh monitor algorithm, when the thresholds are configured. CRs-Fixed: 1010115 Change-Id: I6dad908bbc673ff1b7f7d3d05fecdfc8f48b5815 Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
2016-05-12power: bcl: snapshot of battery_current_limit driverRam Chandrasekar
This snapshot is taken as of msm-3.18 commit 978d23c. Accommodate the changes in the input arguments for power_supply_register() API and use power_supply_get_property() API to get the SoC information from BMS. CRs-Fixed: 1010115 Change-Id: I1af565ffd3b61e424aca1cbd5ec6cbef8d89f1fa Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
2016-05-11leds: leds-qpnp-flash-v2: create v2 QPNP flash LED driverChun Zhang
There is a new Qualcomm Technology Inc. Plug-n-play(QPNP) PMIC chip, which introduces brand new flash LED hardware. The new hardware comes with up to 3 LEDs support, different register mapping layout, and different torch enablement requirement. Therefore, a new driver is introduced to cover this need. Change-Id: Ic878f1a946955edff3a9228e7fe54b7a525e37b1 Signed-off-by: Chun Zhang <chunz@codeaurora.org> Signed-off-by: Mohan Pallaka <mpallaka@codeaurora.org>
2016-05-11icnss: Add support to configure voltage regulatorHardik Kantilal Patel
Add voltage regulator support to power the WLAN hardware. CRs-Fixed: 982993 Change-Id: Ic36ac920497d05131ef8162a42ee5318600a3473 Signed-off-by: Hardik Kantilal Patel <hkpatel@codeaurora.org>
2016-05-10usb: pd: Add QPNP Power Delivery PHY driverHemant Kumar
The QPNP PD PHY resides in the PMIC and handles USB Power Delivery data transmission and reception over the CC lines. This driver communicates to this device over SPMI or I2C buses. Introduce APIs that upper layers will use to implement the protocol layer and policy engine. Change-Id: I75dec23c297fd5e07d14741e6627b473012b7a01 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org> Signed-off-by: Jack Pham <jackp@codeaurora.org>
2016-05-10qcom-charger: introduce QPNP SMB2 charger driverNicholas Troast
The QPNP SMB2 charger driver supports the charger peripheral present in the PMICOBALT chip. This charger peripheral is common among other chips, therefore the driver uses the smb library to support all common functionality. Register access is provided by the parent device via regmap. Interrupts are controlled by the parent device, and handlers are registered by the QPNP SMB2 charger driver. The power supply framework is used to communicate battery and usb properties to userspace and other driver consumers such as fuel gauge, USB, and USB-PD. VBUS and VCONN regulators are registered for supporting OTG, and powered Type-C cables respectively. CRs-Fixed: 1005389 Change-Id: I160ce3c8caae6999f52590099cf6d1de957dbbaf Signed-off-by: Nicholas Troast <ntroast@codeaurora.org> Signed-off-by: Harry Yang <harryy@codeaurora.org>
2016-05-10regulator: labibb: fix standalone mode configurationSubbaraman Narayanamurthy
Currently, standalone mode is treated as a mode along with other modes, LCD and AMOLED. Rather than keeping it like that, LCD and AMOLED mode configurations should be allowed along with the way LAB and IBB modules are controlled, i.e. standalone or dual. Remove the standalone mode from the list of modes and keep it as a configurable parameter via device tree. This way, LCD and AMOLED modes can be configured along with the way LAB/IBB needs to be controlled (dual or standalone). Add support for parent supply to LABIBB device so that LAB and IBB regulators can vote for MBG when operating in standalone mode. CRs-Fixed: 996961 Change-Id: I56882e3a5a01b017e1ba9cd63ab36933a3d469e7 Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
2016-05-10regulator: qpnp-labibb: Add logic to skip second SWIRE commandAnirudh Ghayal
On newer AMOLED panels the second SWIRE command is expected to control the AVDD voltage. However, the PMI8950/PMI8994 IBB module interprets this command for VDISN and incorrectly reduces its voltage. Add DT properties 'qcom,skip-2nd-swire-cmd' to skip the second SWIRE command and 'qcom,swire-2nd-cmd-delay' to explicitly specify the delay between the first and second SWIRE command. CRs-Fixed: 938038 Change-Id: I617a8490784efd760651b3ec8780cc4fd4b17bae Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org> Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
2016-05-10thermal: qpnp-adc-tm: Support refreshed BTM driverSiddartha Mohanadoss
The BTM (Battery temperature module) peripheral driver on the PMIC (Power management IC) supports threshold monitoring and notifies clients when thresholds are crossed. PMCOBALT supports refreshed BTM peripheral register interface and the driver uses compatible property qpnp-adc-tm-hc to distinguish using the refreshed peripheral. The external client interface with the driver remains the same. Updates include handling the interrupt when the thresholds are crossed,programming the threholds and configuring the hardware based on the refreshed design. BTM peripheral needs the VADC_HC peripheral to compute the gain/offset that are used to reverse compute the threhold values to ADC code. Some of the reverse computation API's such as calculating thermistor thresholds require the gain and offset values before computing the ADC code to be programmed. This requires modification to the existing calibration API in the VADC_HC driver to calculate the reference calibration points and store these values for clients to use in the reverse computation Change-Id: I989cfa4f40e7f1671f04dfa9d4c3fe2ccbbc44ab Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
2016-05-09clk: msm: osm: support programming LMh SW override values in set_rate()Osvaldo Banuelos
To ensure stable operation, it is necessary to place LMh SW override votes when setting the new rate of the power and performance CPU clocks. Add support for parsing these values from Device Tree and programming them in clk_set_rate(). Change-Id: I60d90d546f155edb6c13c46e6c59c75e95848d6c CRs-Fixed: 1009097 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
2016-05-09clk: qcom: mdss: add Display-port pll clock driver supportChandan Uddaraju
Add support for new Display-port PLL clock driver to handle different DP panel resolutions in msmcobalt. Add separate files to support this new PHY PLL block. CRs-Fixed: 1009740 Change-Id: Ic282c7e14fc6e23f4d044cb6a58249bdb4c8c2d8 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
2016-05-06msm: thermal: Remove support for asynchronous clusterRam Chandrasekar
KTM has support for handling cluster with asynchronous cores within a cluster. KTM can get the individual clock plans for the cores and mitigate them separately. This feature is not supported in hardware. So remove the asynchronous cluster support from KTM. CRs-Fixed: 1010111 Change-Id: I13348a16e2e1c11053cf5b99b921fd8ea65c7d89 Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
2016-05-06ASoC: msmcobalt: add BT/FM audio support with WCN3990Banajit Goswami
Add machine driver code to support audio on MSMCOBALT based boards with WCN3990 BT/FM chipset. Change-Id: Ia23572f44775a04c8f8c67e9a61d6b9be8869b82 Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
2016-05-06clk: msm: osm: increase timer resolution programming to nanosecondsOsvaldo Banuelos
OSM clock period is 5 ns. Therefore, the various hysteresis timers used by OSM can be fine tuned with a granularity of 5 ns. Allow specification of timers in units of nanoseconds to prevent losing valid timer setpoints. Change-Id: Ice93347aaf81fe41ea7862752ac0d2d4e82d838c CRs-Fixed: 1009097 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
2016-05-06power: move QTI charger drivers to a new sub-directory againNicholas Troast
The original commit was reverted due to conflicts in the kernel upgrade process. Now that the upgrade is complete we can introduce this commit again. Original commit: commit 8e10bff71301 ("power: move QTI charger drivers to a new sub-directory qcom-charger") QTI charger drivers have outgrown their home in power and deserve their own sub-directory. Move all QTI charger drivers and their dependencies to a new sub-directory of power called qcom-charger. CRs-Fixed: 1001767 Change-Id: I5465a944a79f622ddf69534075b067db0fb10c95 Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
2016-05-06Merge "qseecom: add a new flag commonlib64-loaded-by-uefi" into msm-4.4Linux Build Service Account
2016-05-05qseecom: add a new flag commonlib64-loaded-by-uefiZhen Kong
Add flag commonlib64-loaded-by-uefi to indicate commonlib64 is loaded by uefi already. Change-Id: I9dd3f6bf92e178f1207424b09f39f2e08164df17 Signed-off-by: Zhen Kong <zkong@codeaurora.org>
2016-05-05msm: thermal: Make boot-up mitigation optionalRam Chandrasekar
For the targets with the LMH DCVSh mitigation, HLOS boot-up mitigation is not required. So make the devicetree properties related to boot-up mitigation as optional. CRs-Fixed: 1010111 Change-Id: I7f254f579182effbc1f1a3d49c3c917d3c7af162 Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
2016-05-05workqueue: implement lockup detectorTejun Heo
Workqueue stalls can happen from a variety of usage bugs such as missing WQ_MEM_RECLAIM flag or concurrency managed work item indefinitely staying RUNNING. These stalls can be extremely difficult to hunt down because the usual warning mechanisms can't detect workqueue stalls and the internal state is pretty opaque. To alleviate the situation, this patch implements workqueue lockup detector. It periodically monitors all worker_pools periodically and, if any pool failed to make forward progress longer than the threshold duration, triggers warning and dumps workqueue state as follows. BUG: workqueue lockup - pool cpus=0 node=0 flags=0x0 nice=0 stuck for 31s! Showing busy workqueues and worker pools: workqueue events: flags=0x0 pwq 0: cpus=0 node=0 flags=0x0 nice=0 active=17/256 pending: monkey_wrench_fn, e1000_watchdog, cache_reap, vmstat_shepherd, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, cgroup_release_agent workqueue events_power_efficient: flags=0x80 pwq 0: cpus=0 node=0 flags=0x0 nice=0 active=2/256 pending: check_lifetime, neigh_periodic_work workqueue cgroup_pidlist_destroy: flags=0x0 pwq 0: cpus=0 node=0 flags=0x0 nice=0 active=1/1 pending: cgroup_pidlist_destroy_work_fn ... The detection mechanism is controller through kernel parameter workqueue.watchdog_thresh and can be updated at runtime through the sysfs module parameter file. v2: Decoupled from softlockup control knobs. CRs-Fixed: 1007459 Change-Id: Id7dfbbd2701128a942b1bcac2299e07a66db8657 Signed-off-by: Tejun Heo <tj@kernel.org> Acked-by: Don Zickus <dzickus@redhat.com> Cc: Ulrich Obergfell <uobergfe@redhat.com> Cc: Michal Hocko <mhocko@suse.com> Cc: Chris Mason <clm@fb.com> Cc: Andrew Morton <akpm@linux-foundation.org> Git-commit: 82607adcf9cdf40fb7b5331269780c8f70ec6e35 Git-repo: git://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
2016-05-05regulator: cprh-kbss-regulator: update corner switch delay time docOsvaldo Banuelos
The qcom,cpr-corner-switch-delay-time property is used to specify voltage settling delay per 1 mV of voltage change. Update the documentation to reflect this. Change-Id: I6af5a0bd5ddb5fdb22585f9da34524475f49233f CRs-Fixed: 1009142 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
2016-05-05msm: jpeg: Expose JPEG DMA max downscale to user spaceGautham Mayyuri
This change will retrieve JPEG DMA max downscale factor from dtsi and expose it to user space. CRs-Fixed: 1009871 Change-Id: I57496aeb47d907f540a25c854ef7b35c6b5ab399 Signed-off-by: Gautham Mayyuri <gmayyuri@codeaurora.org>
2016-05-03iommu/iommu-debug: Add dummy driver for standalone testingMitchel Humpherys
The IOMMU test framework relies on the `iommus' property, and we currently rely on these methods for making that happen: (1) Clients enabling their DT nodes. (2) We put an `iommus' property in our IOMMU DT nodes themselves. The problem with (1) is that clients aren't always ready during early chip validation. The problem with (2) is that it results in us recursively mapping into the SMMU when we try to do cache maintenance on our page table memory. Fix these problems by introducing a dummy driver with associated device tree bindings that will do absolutely nothing other than wait for the SMMU driver and IOMMU test framework to slurp it up. CRs-Fixed: 1003233 Change-Id: I6a5802aff5bab99d29c6ed9d953a203cbd8015bb Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
2016-05-03icnss: Add SMMU supportYue Ma
Add SMMU support for WLAN. Config it as stage-1 enable by default. Change-Id: I70db6555d236857c5a8d62a337afdc9fec22c97f CRs-fixed: 1009865 Signed-off-by: Yue Ma <yuem@codeaurora.org>
2016-04-29bluetooth: Add slimbus driver for WCN3990Sungjun Park
For WCN3990, it supports slimbus slave interface to receive/send audio data such as FM audio, bluetooth SCO, bluetooth A2DP data, etc. Change-Id: I6c64debd0c9b43ea5ebf55a58f1f4b06cdc9bd4e Signed-off-by: Sungjun Park <sjpark@codeaurora.org>
2016-04-29clk: msm: clock: Support graphics clocks on MSMHAMSTERDeepak Katragadda
Add support for controlling the graphics clocks on MSMHAMSTER. CRs-Fixed: 1004885 Change-Id: If96d8e7e0cd97cf45c48c6c39236d42659e25ea2 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-04-29clk: msm: clock: Support multimedia clocks on MSMHAMSTERDeepak Katragadda
Add support for controlling the multimedia clocks on MSM HAMSTER. CRs-Fixed: 1004885 Change-Id: Ic995c37ae819ce16668374cecf28fa98e6cf3180 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-04-29clk: msm: clock: Support peripheral clocks on MSMHAMSTERDeepak Katragadda
Add support for controlling the peripheral clocks on MSM HAMSTER. CRs-Fixed: 1004885 Change-Id: If77ad3d662fbba145374abe38ea14a1a6e540fee Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-04-29ARM: dts: msm: Add initial device tree files for MSMHAMSTERRunmin Wang
Add the device tree files necessary to support the MSMHAMSTER SoC. CRs-Fixed: 1009230 Change-Id: I4370d561af7a34494accf00b4098ffa13c60410b Signed-off-by: Runmin Wang <runminw@codeaurora.org>
2016-04-28msm: mdss: parse and populate PPB offsets separatelyJeykumar Sankaran
This change parses and populates PPB control and config register offsets separately. Its not necessary every ping pong blocks to have both control and config registers. Change-Id: I4be0dcaa9fabbd81e4875255d808707bf1e97e8e Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2016-04-28msm: mdss: add scr rev support for dscDhaval Patel
Panels can support different dsc revisions based on the scr. Add scr revision support for dsc based on updated spec. Change-Id: Icbd93ed592a7d79dcd7f72b52d73572ced384759 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2016-04-28msm: mdss: register smmu context fault handlerDhaval Patel
Smmu context fault handler provides the fault iova information but does not provide any information about xin client. This patch registers the context fault handler in MDSS software to get the vmid/xin client information. It also dumps the registers for source associated with respective vmid client Change-Id: I2a833a4b5e81e36f4d7af23a3968c9755424b7a7 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2016-04-27clk: msm: osm: model LMh RCG to ensure OSM clock runs at 200 MHzOsvaldo Banuelos
The OSM clock is sourced from the LMh RCG. Model this RCG so that it can be configured properly to provide the OSM a 200 MHz clock source. Change-Id: Ib799e8c082977ac226d6bd31ffad8ca63597c0fc CRs-Fixed: 1007896 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
2016-04-27ARM: perf: Set ARMv7 SDER SUNIDEN bitMartin Fuzzey
ARMv7 counters other than the CPU cycle counter only work if the Secure Debug Enable Register (SDER) SUNIDEN bit is set. Since access to the SDER is only possible in secure state, it will only be done if the device tree property "secure-reg-access" is set. Without this: Performance counter stats for 'sleep 1': 14606094 cycles # 0.000 GHz 0 instructions # 0.00 insns per cycle After applying: Performance counter stats for 'sleep 1': 5843809 cycles 2566484 instructions # 0.44 insns per cycle 1.020144000 seconds time elapsed Some platforms (eg i.MX53) may also need additional platform specific setup. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com> Signed-off-by: George G. Davis <george_davis@mentor.com> [will: add warning if property is found on arm64] Signed-off-by: Will Deacon <will.deacon@arm.com> Git-commit: 8d1a0ae724ad74ef7946a45e3b2d3e01f39df02b Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git CRs-Fixed: 1008368 Change-Id: Ic946deff2433ada458eb8040ddf40615a0a80959 Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
2016-04-27input: touchscreen: synaptics_dsx: Set power specificationsAlex Sarraf
Set voltage and current specifications for LDOs. Change-Id: I6e666390ddbdd8128b6ebff8e2deb8c85cf35b21 Signed-off-by: Alex Sarraf <asarraf@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-20 01:33:57 +0000