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For the targets with the LMH DCVSh mitigation, HLOS boot-up
mitigation is not required. So make the devicetree properties
related to boot-up mitigation as optional.
CRs-Fixed: 1010111
Change-Id: I7f254f579182effbc1f1a3d49c3c917d3c7af162
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
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Workqueue stalls can happen from a variety of usage bugs such as
missing WQ_MEM_RECLAIM flag or concurrency managed work item
indefinitely staying RUNNING. These stalls can be extremely difficult
to hunt down because the usual warning mechanisms can't detect
workqueue stalls and the internal state is pretty opaque.
To alleviate the situation, this patch implements workqueue lockup
detector. It periodically monitors all worker_pools periodically and,
if any pool failed to make forward progress longer than the threshold
duration, triggers warning and dumps workqueue state as follows.
BUG: workqueue lockup - pool cpus=0 node=0 flags=0x0 nice=0 stuck for 31s!
Showing busy workqueues and worker pools:
workqueue events: flags=0x0
pwq 0: cpus=0 node=0 flags=0x0 nice=0 active=17/256
pending: monkey_wrench_fn, e1000_watchdog, cache_reap, vmstat_shepherd, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, release_one_tty, cgroup_release_agent
workqueue events_power_efficient: flags=0x80
pwq 0: cpus=0 node=0 flags=0x0 nice=0 active=2/256
pending: check_lifetime, neigh_periodic_work
workqueue cgroup_pidlist_destroy: flags=0x0
pwq 0: cpus=0 node=0 flags=0x0 nice=0 active=1/1
pending: cgroup_pidlist_destroy_work_fn
...
The detection mechanism is controller through kernel parameter
workqueue.watchdog_thresh and can be updated at runtime through the
sysfs module parameter file.
v2: Decoupled from softlockup control knobs.
CRs-Fixed: 1007459
Change-Id: Id7dfbbd2701128a942b1bcac2299e07a66db8657
Signed-off-by: Tejun Heo <tj@kernel.org>
Acked-by: Don Zickus <dzickus@redhat.com>
Cc: Ulrich Obergfell <uobergfe@redhat.com>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Chris Mason <clm@fb.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Git-commit: 82607adcf9cdf40fb7b5331269780c8f70ec6e35
Git-repo: git://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
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The qcom,cpr-corner-switch-delay-time property is used to specify
voltage settling delay per 1 mV of voltage change. Update the
documentation to reflect this.
Change-Id: I6af5a0bd5ddb5fdb22585f9da34524475f49233f
CRs-Fixed: 1009142
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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This change will retrieve JPEG DMA max downscale factor
from dtsi and expose it to user space.
CRs-Fixed: 1009871
Change-Id: I57496aeb47d907f540a25c854ef7b35c6b5ab399
Signed-off-by: Gautham Mayyuri <gmayyuri@codeaurora.org>
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The IOMMU test framework relies on the `iommus' property, and we
currently rely on these methods for making that happen:
(1) Clients enabling their DT nodes.
(2) We put an `iommus' property in our IOMMU DT nodes themselves.
The problem with (1) is that clients aren't always ready during early
chip validation. The problem with (2) is that it results in us
recursively mapping into the SMMU when we try to do cache maintenance on
our page table memory.
Fix these problems by introducing a dummy driver with associated device
tree bindings that will do absolutely nothing other than wait for the
SMMU driver and IOMMU test framework to slurp it up.
CRs-Fixed: 1003233
Change-Id: I6a5802aff5bab99d29c6ed9d953a203cbd8015bb
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
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Add SMMU support for WLAN. Config it as stage-1 enable by default.
Change-Id: I70db6555d236857c5a8d62a337afdc9fec22c97f
CRs-fixed: 1009865
Signed-off-by: Yue Ma <yuem@codeaurora.org>
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For WCN3990, it supports slimbus slave interface
to receive/send audio data such as FM audio, bluetooth
SCO, bluetooth A2DP data, etc.
Change-Id: I6c64debd0c9b43ea5ebf55a58f1f4b06cdc9bd4e
Signed-off-by: Sungjun Park <sjpark@codeaurora.org>
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Add support for controlling the graphics clocks on
MSMHAMSTER.
CRs-Fixed: 1004885
Change-Id: If96d8e7e0cd97cf45c48c6c39236d42659e25ea2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add support for controlling the multimedia clocks on
MSM HAMSTER.
CRs-Fixed: 1004885
Change-Id: Ic995c37ae819ce16668374cecf28fa98e6cf3180
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add support for controlling the peripheral clocks on
MSM HAMSTER.
CRs-Fixed: 1004885
Change-Id: If77ad3d662fbba145374abe38ea14a1a6e540fee
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add the device tree files necessary to support the MSMHAMSTER SoC.
CRs-Fixed: 1009230
Change-Id: I4370d561af7a34494accf00b4098ffa13c60410b
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
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This change parses and populates PPB control and config register
offsets separately. Its not necessary every ping pong blocks
to have both control and config registers.
Change-Id: I4be0dcaa9fabbd81e4875255d808707bf1e97e8e
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
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Panels can support different dsc revisions based on the scr.
Add scr revision support for dsc based on updated spec.
Change-Id: Icbd93ed592a7d79dcd7f72b52d73572ced384759
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
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Smmu context fault handler provides the fault iova
information but does not provide any information about
xin client. This patch registers the context fault
handler in MDSS software to get the vmid/xin client
information. It also dumps the registers for source
associated with respective vmid client
Change-Id: I2a833a4b5e81e36f4d7af23a3968c9755424b7a7
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
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The OSM clock is sourced from the LMh RCG. Model this RCG so
that it can be configured properly to provide the OSM a 200 MHz
clock source.
Change-Id: Ib799e8c082977ac226d6bd31ffad8ca63597c0fc
CRs-Fixed: 1007896
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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ARMv7 counters other than the CPU cycle counter only work if the Secure
Debug Enable Register (SDER) SUNIDEN bit is set.
Since access to the SDER is only possible in secure state, it will
only be done if the device tree property "secure-reg-access" is set.
Without this:
Performance counter stats for 'sleep 1':
14606094 cycles # 0.000 GHz
0 instructions # 0.00 insns per cycle
After applying:
Performance counter stats for 'sleep 1':
5843809 cycles
2566484 instructions # 0.44 insns per cycle
1.020144000 seconds time elapsed
Some platforms (eg i.MX53) may also need additional platform specific
setup.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>
Signed-off-by: George G. Davis <george_davis@mentor.com>
[will: add warning if property is found on arm64]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: 8d1a0ae724ad74ef7946a45e3b2d3e01f39df02b
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
CRs-Fixed: 1008368
Change-Id: Ic946deff2433ada458eb8040ddf40615a0a80959
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
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Set voltage and current specifications for LDOs.
Change-Id: I6e666390ddbdd8128b6ebff8e2deb8c85cf35b21
Signed-off-by: Alex Sarraf <asarraf@codeaurora.org>
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Add device tree binding doc for the qpnp-haptic driver.
Change-Id: I866eb6915717ce54c52061a22e29c1dfc88c1c7b
Signed-off-by: Jing Lin <jinglin@codeaurora.org>
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Add Synaptics, Inc. to the vendor prefix list.
Change-Id: Ie0ee0c0c5bc841c86ac0f45eec3ec71fb657098c
Signed-off-by: Jing Lin <jinglin@codeaurora.org>
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Some panel don't require backlight to be updated during
unblank and only require update upon first commit. Add
support to update the backlight based on panel specific
property.
Change-Id: I43f33505be5151640ad7dc2ee1a14df8a55a6dfe
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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On SoCs that have OSM hardware, use the hardware to setup the CPU
mitigation limits. Having the OSM control CPU frequencies offloads
mitigation from the CPU, resulting in faster thermal mitigation
response.
The LMH DCVS aggregation does not do a max of the min frequency limits.
Therefore to avoid cpufreq voting any lesser than what KTM decides based
on vdd min restrictions, we update cpufreq as well, only if the min freq
has changed.
Change-Id: I2912eaf418d5e7ea4d62a9a55702e02b744a785b
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
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The Limits Management Hardware (LMH-DCVS) is a hardware block for
monitoring thermal profiles and taking immediate action to control
temperature without software intervention. The h/w block can only be
configured under secure mode.
The LMH-DCVS block reads CPU temperatures of a cluster by sensing
information from the TSENS hardware and determines the course of action.
When enabled, the h/w triggers when the high threshold is hit for any
CPU in the cluster. The mitigative action is frequency and voltage
control that is provided to the OSM hardware.
The driver registers a virtual thermal zone device for each hardware
instance. The thermal zone device is used to set the thresholds for the
hardware to work on. Once the thresholds are setup and the trip type is
enabled, the hardware functions autonomously. Mitigative action is
completely controlled in the h/w.
Writing to the actual hardware is done through the SCM call.
Change-Id: I70d4bc387717491256fec1ef6bd8cd6a28ea641b
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
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Add support to program the DSI PLL on msmcobalt which is needed to drive
the DSI byte and pixel clocks.
CRs-Fixed: 1000576
Change-Id: Ic11a3747a0e008e1f71df91a1a79d33242d2a2a4
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Add additional event buffers for GSI based hardware accelerated
endpoints and its related configuration.
CRs-Fixed: 1003784
Change-Id: Ibedf73690040b8bd872f5621835680a66c22e265
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
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For certain board configurations, the enable port on display
connector card needs to be controlled via LCD mode selection
GPIO. For example, for DSC/single DSI mode, the GPIO needs to
be driven high and for non-DSC/split DSI mode, the GPIO
needs to be driven low. Add support for this.
CRs-Fixed: 1000724
Change-Id: I3546fc2b5dacd77e9d2cd2ea843481dc34bfef54
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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WCD and WSA codecs uses MSM gpios that are accessed through pinctrl
mechanism. Codec reset gpios need to be configured before master
controller is initialized otherwise codec cannot be enumerated
on the bus. Add a new platform device driver to update reset gpio
configuration to valid state before bus initialization.
Change-Id: I1e36f4a85334704652c6b50950f50b90224a472e
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
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On few devices QPDI's LDOs are configured by some other component.
This change adds support to skip LDO configuration on such devices.
Change-Id: I84c8b4a5a0d6155a39e43e0503961f76e2d8a615
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
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Add HW event driver in upstream implementation of Coresight driver.
This change copies coresight-hwevent.c file from drivers/coresight
(commit f9b3004b242c ("msm: pcie: enable/disable PCIe AER from
debugfs"))
to driver/hwtracing/coresight directory.
Change-Id: I2d75108bae975107ee5c13fa5dfb5846185fbd3d
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
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Add qpdi driver in upstream implementation of Coresight driver.
This change copies coresight-qpdi.c file from drivers/coresight
(commit f9b3004b242c ("msm: pcie: enable/disable PCIe AER from
debugfs"))
to driver/hwtracing/coresight directory.
Change-Id: I8f29f386a31aec1a10a1398e0753a3b4355b3449
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
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Add support to set default sink at probe time.
Change-Id: I62abe39a5cb5e7f8b1bb1198cecd3b529b124de8
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
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Add remote etm driver in upstream implementation of Coresight
driver.
This change copies coresight-remote-etm.c file from drivers/coresight
(commit c1fe9ac38d93 ("input: touchscreen: correct function and variable
names in ITE tech driver"))
to driver/hwtracing/coresight directory.
Change-Id: I77a1aaf10aaf3f3010ab19d5878bb53dcc504c29
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
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Add FE(front end) and BE(Back end) DAI(Digital Audio Interface)
links needed to support audio functionality on msmcobalt
simulation platform.
Change-Id: I87feebf29fb4b3e3e8db52d9d85c902c384d061f
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
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Add support to configure the CPR interrupt affinity via a CPR3
controller device tree node. This can be used to avoid servicing
CPR interrupts triggered by a CPU enterring power collapse on the
CPU that just power collapsed.
Change-Id: I4c04a2c255a6bd249c888c0dd0dbda19b8436be2
CRs-Fixed: 949650
Signed-off-by: David Collins <collinsd@codeaurora.org>
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In order to set SMMU to S1 bypass configuration
IPA driver needs to set DOMAIN_ATTR_S1_BYPASS before
attaching to SMMU. The actual SMMU setting is controlled
via device tree.
CRs-Fixed: 998074
Change-Id: I3e63d9e6c511dd692b299543881e7266799108af
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
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Commit be231853070770fd7e7c6fd5ca2414e26e7534a7 ("Merge branch
'mdss-final-replay' into msm-4.4") resulted in the driver changes related
to writeback sub node being merged without the documentation for the
bindings associated with that device node. Add the missing binding
documentation.
Change-Id: Id2affddf055a6bbf0038958bcdb7abd6d7930509
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Add support for gladiator cache inter connect error detection
and reporting for msmcobalt
CRs-Fixed: 1000642
Change-Id: I68c5ce09cc77a19eb334a1d8ccce8d577f964316
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
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Newer versions of the DSI phy do not require any programming of the lane
regulator settings. Make this binding an optional property for the DSI
device node.
CRs-Fixed: 1000724
Change-Id: I696aab348cdb04db4068b2b62bcd049c839cbc33
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Fixed issues in jpeg DMA v4l2 driver, related to
incorrect clock index, incorrect buffer offset,
incorrect dtsi node names for VBIF, QOS and
mmu prefetch.
CRs-Fixed: 1001324
Change-Id: Ice15afd63e006401a469376277b50a129ef177b4
Signed-off-by: Ashwini Rao <ashwinik@codeaurora.org>
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The Modem Host Interface (MHI) device driver supports
clients to send control and data packets such as
IP data packets, control messages and Diagnostic
data between the Host and the device. It follows the
MHI specification to transfer data.
The driver interfaces with the IPA driver for Hardware
accelerated channels and PCIe End point driver
to communicate between the Host and the device.
The driver exposes to both userspace and kernel space
generic IO read/write/open/close system calls and
kernel APIs to communicate and transfer data between
Host and the device.
Change-Id: I64990a972cbf7c2022d638c35f7517071de67f19
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
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FastRPC migration to use GLINK from existing SMD driver for inter-
process communication. Updated FastRPC context bank details for
msmcobalt. Added "qcom,enable-glink" option in dtsi file for
using glink, uses smd if this flag is not defined.
Change-Id: I4a933c9b3355b0aa1b653719ec1ec7ded1f368dd
Acked-by: Viswanatham Paduchuri <vpaduchu@qti.qualcomm.com>
Signed-off-by: Sathish Ambley <sathishambley@codeaurora.org>
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Add a library for a kernel client to register and be notified of
any state changes regarding a local or remote service which runs
on a remote processor on the SoC.
CRs-Fixed: 999530
Change-Id: Idd56140e11f4fdc48fd999a1e808f3263024f34d
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
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On newer platform USB QMP PHY needs different voltage supply as core
voltage. This change adds required support for the same.
CRs-Fixed: 1001463
Change-Id: If100d36bade241dedf28e3cea9e07be192bdfdc2
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
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Adjust floor voltages based upon a configurable APM hysteresis voltage.
This reduces the number of corners whose floor voltages must be raised
to ensure stable operation with manual APM switching. In particular,
for corners with ceiling voltage greater than or equal to the APM
threshold voltage and floor voltage less than APM threshold voltage
set an adjusted floor of max(floor, APM threshold - APM hysteresis).
Change-Id: I65bebcfd8f4785bce9f65243987c05444aab14ee
CRs-Fixed: 1001346
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Add new version 5.0 to CSIPHY and CSID documentation
Change-Id: I7295aa6f23b01304c65ff8de08ac115dc53b9803
Signed-off-by: Sureshnaidu Laveti <lsuresh@codeaurora.org>
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Add documentation file for camera drivers into the 4.4 kernel
tree.
CRs-Fixed: 1001183
Change-Id: I6fe3301673eaba9b8b6fa6c4ad8706fa5e979dd0
Signed-off-by: Seemanta Dutta <seemanta@codeaurora.org>
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On platforms where the power supply for 11AD is external
the wil6210 device can control the rfclk3 clock using a GPIO.
wil6210 driver has to enable the clock during device reset
to guarantee the rfclk3 is on for bootloader activity.
After the wil6210 device is up, the wil6210 driver needs to
leave only the pin clock enabled, to allow the device to
toggle it.
Change-Id: I0f6181d18268f7a2f615155525fbed0f0fe7572a
CRs-Fixed: 986130
Signed-off-by: Maya Erez <merez@codeaurora.org>
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Add support for the fuse layout and hardware constraints of the
msmcobalt CPR4 controller which is used to manage the GPU supply
regulator. Also update the cpr3-regulator core driver in order
to support CPR register writing for this device.
Change-Id: I408854a93e820c168551bcfec7d4f87cdbe5d638
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
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This is a snapshot of the mem-acc-regulator device tree bindings
documentation file present in the msm-3.18 branch as of
commit 9d555a2ec04c ("regulator: mem-acc: Add support for multi
register configuration").
Change-Id: Iad561ef5bab93f1e82879364639b4a5472e65902
CRs-Fixed: 986619
Signed-off-by: David Collins <collinsd@codeaurora.org>
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The CPR driver on MSMCOBALT needs the gpucc_rbcpr_clk clock in
order to probe and register the gfx_vreg regulator which the
graphics clock driver in-turn is dependent on for registering
the gfx3d clocks.
To break this circular dependency, register the non-gfx clocks
first, let the CPR driver probe, and then register the GPU PLLs
and gfx3d clocks. Also, correct the gfx CRC sequence.
CRs-Fixed: 986619
Change-Id: Id16ad7940e96cc9d5a3127551c8a92b05cfbb181
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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This merge brings all display changes from msm-3.18 kernel
* (58 commits)
msm: mdss: add support for additional DMA pipes
msm: mdss: refactor device tree pipe parsing logic
msm: mdss: refactor mixer configuration code
msm: mdss: add support for secure display on msm8953.
msm: mdss: disable ECG feature on 28nm PHY platform
msm: mdss: send DSI command using TPG when in secure session
msm: mdss: Update histogram and PA LUT in mdss V3
msm: mdss: validate layer count before copying userdata
msm: mdss: Fix potential NULL pointer dereferences
Revert "msm: mdss: Remove redundant handoff pending check"
msm: mdss: hdmi: Do not treat intermediate ddc error as failure
msm: mdss: revisit igc pipe enumeration logic
msm: mdss: Add PA support for mdss V3
msm: mdss: Add support for mdss v3 ops
msm: mdss: Update the postprocessing ops using mdss revision
msm: mdss: update the caching payload based on mdss version
msm: clk: hdmi: add support for atomic update
msm: sde: Add v4l2 rotator driver to enable multi-context usecase
msm: mdss: refactor pipe type checks
msm: mdss: add proper layer zorder validation
msm: mdss: stub bus scaling functions if driver is disabled
msm: mdss: avoid failure if primary panel pref is not enabled
msm: adv7533: add support for clients to read audio block
msm: mdss: add lineptr interrupt support for command mode panels
msm: mdss: update rotator frame rate in the pipe configuration
mdss: msm: Avoid excessive failure logs in igc config
msm: mdss: delay dma commands for split-dsi cmd mode panels
msm: mdss: enable GDSC before enabling clocks in MDP3 probe
mdss: dsi: turn off phy power supply during static screen
mdss: dsi: read dsi and phy revision during dsi ctrl probe
msm: mdss: Fix memory leak in MDP3 driver
msm: mdss: delay overlay start until first update for external
msm: mdss: free splash memory for MSM8909w after splash done
msm: mdss: hdmi: separate audio from transmitter core
msm: mdss: disable dsi burst mode when idle is enabled
msm: mdss: remove invalid csc initialization during hw init
msm: mdss: dsi: increase dsi error count only for valid errors
msm: mdss: remove HIST LUT programming in mdss_hw_init
msm: mdss: dsi: ignore error interrupt when mask not set
msm: mdss: add support to configure bus scale vectors from dt
msm: mdss: unstage the pipe if there is z_order mismatch
msm: mdss: squash MDP3 driver changes and SMMU change
msm: mdss: Read the bridge chip name and instance id from DTSI
msm: mdss: Enable continuous splash on bridge chip
msm: mdss: Fix multiple bridge chip usecase
msm: mdss: Enable export of mdss interrupt to external driver
msm: mdss: rotator: turn off rotator clock in wq release
msm: mdss: fix ulps during suspend feature logic
clk: msm: mdss: program correct divider for PLL configuration
msm: mdss: fix DSI PHY timing configuration logic
msm: mdss: hdmi: add support for hdmi simulation
msm: mdss: handle race condition in pingpong done counter
clk: qcom: mdss: calculate pixel clock for HDMI during handoff
msm: mdss: ensure proper dynamic refresh programming for dual DSI
msm: mdss: Add fps flag and update blit request version
msm: mdss: initialize fb split values during fb probe
mdss: mdp: fix rotator compat layer copy
msm: mdss: handle DSI ctrl/PHY regulator control properly
CRs-Fixed: 1000197
Change-Id: I521519c8abe8eed6924e2fbe3e1a026126582b77
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
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