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2016-03-22defconfig: arm64: msm: Enable Data featuresSubash Abhinov Kasiviswanathan
Enable configurations needed for data functionality Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
2016-03-22Revert "net, lib: kill arch_fast_hash library bits"Rohit Vaswani
This reverts commit 0cb6c969ed9de43687abdfc63714b6fe4385d2fc.
2016-03-22defconfig: msm: enable PCIe bus driver in defconfig for 4.4 kernelTony Truong
Enable defconfig for PCIe bus driver on 4.4 kernel. Signed-off-by: Tony Truong <truong@codeaurora.org>
2016-03-22msm: pcie: add PCIe bus driver snapshotTony Truong
This PCIe bus driver snapshot is taken as of msm-3.10 commit: 803998b (Merge "ASoC: wcd: don't set autozeroing for conga") This change adds the PCIe bus driver and its dependecies from msm-3.10 to msm-3.14. All the files are as is from msm-3.10. No additional changes were made. Change-Id: Ia1a2d0eea0cc87c16357c95bfcc4df72e910cd34 Signed-off-by: Tony Truong <truong@codeaurora.org>
2016-03-22Enable CONFIG_RTC_DRV_QPNPMao Jinlong
Enable CONFIG_RTC_DRV_QPNP as power_on_alarm_init is added by change : I781389c658fb00ba7f0ce089d706c10f202a7dc6 Change-Id: I48bc69e2215e45e0c5c7bc8aa2c489fca995c201 Signed-off-by: Mao Jinlong <c_jmao@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable sensors SSC driverSatya Durga Srinivasu Prabhala
Enable sensors SSC driver. Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2016-03-22drivers: GICv3: Add mb() after the read of the IAR1_EL1 and other registersAbhimanyu Kapur
As per the GICv3 architecture spec section "Observability of GIC Register Accsses", architecture execution of the "DSB" gurantees that last interrupt identifier read from ICC_IAR{0,1}_EL1 is observable by the top-level Distributor and by accesses from any processor to the top-level Distributor. Same comment goes for the ICC_PMR_EL1 and ICC_SGI1R_EL1 too. CRs-Fixed: 960754 Change-Id: I9c7bcdee51f71d369e2a6f04faf7a22c3c1381bc Signed-off-by: Trilok Soni <tsoni@codeaurora.org> [abhimany: relocate mb()'s to header files] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
2016-03-22arm: traps: emulate a MRCC instruction reading CNTPCT registerSe Wang (Patrick) Oh
A user space application is planned to support feature for synchronized timestamp among debug packets across peripherals. As part of the feature, it is responsible for providing physical timer count value to user space. If memory mapped timer is used in ARM arch, Usersapce can't read the physical timer count directly with a MRCC ASM instruction. So Kernel traps the instruction and returns the physical timer count. Change-Id: Ia3f0d9c8c06ca9e2204187890c0c57c8640e4f7e Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org> [abhimany: minor merge conflict resolution] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
2016-03-22defconfig: arm64: enable boot stats reporting on msmcortexAbhimanyu Kapur
Enable boot stats reporting on the debug and perf msmcortex configs. Change-Id: I3baa866f93a484acdde5789dbd3ac02a03bc561a Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable smd_ttyKarthikeyan Ramasubramanian
Enable userspace access to SMD channels via a streaming interface. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable glink_pktKarthikeyan Ramasubramanian
The glink_pkt driver provides packet access to G-Link channels for userspace clients. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
2016-03-22defconfig: msmcortex: enable core hang detectionAbhimanyu Kapur
Enable core hang detection debug feature on msmcortex defconfig. Change-Id: I4cbf8811f190d88e6a0efddc23ee19f80b5a74df Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
2016-03-22defconfig: msmcortex: enable gladiator hang detectionAbhimanyu Kapur
Enable gladiator hang detection debug feature on the msmcortex defconfig. Change-Id: Ie33697d94cf9bd964b6a832ce7aeebf960e00e2a Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
2016-03-22defconfig: msm: enable SPS/BAM driverYan He
Enable SPS/BAM driver on 4.4 kernel. Change-Id: Ib7a7bce4564f0a817fd93612fcc0d8824bd1c9cf Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22arm64: dts: msm: Temporarily disable WiPower chargingJack Pham
WiPower charging depends on VADC which is not yet ported. Disable it for now in order to allow pmi8994 charger to work for other use cases, such as USB charging and detection. Signed-off-by: Jack Pham <jackp@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable USB Gadget ConfigFS driversJack Pham
Enable USB_GADGET, USB_CONFIGFS and several of the most used function drivers to allow device mode operation. These drivers provide functionality previously provided by the Android gadget driver. Signed-off-by: Jack Pham <jackp@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable USB DWC3 and PHY drivers (v2)Jack Pham
Enable DWC3, QUSB and QMP PHY drivers to support the USB controller hardware. Also enable XHCI_HCD for USB host mode. This is the second take, after fixing compilation errors in dwc3-msm.c. Signed-off-by: Jack Pham <jackp@codeaurora.org>
2016-03-22defconfig: arm: msm: Enable memshare config flagMohit Aggarwal
Memshare driver is required to provide memory from HLOS to clients present on Modem. Signed-off-by: Mohit Aggarwal <maggarwa@codeaurora.org>
2016-03-22defconfig: msm: Enable CONFIG_UIO and CONFIG_MSM_SHAREDMEMRohit Vaswani
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable kernel QMI InterfaceKarthikeyan Ramasubramanian
The kernel QMI interface permits QMI communication to/from kernel drivers. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable IPC Router G-Link TransportKarthikeyan Ramasubramanian
The IPC Router G-Link Transport permits IPC Router communication over G-Link to the other processors in the SoC. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable IPC Router, IPC Router SecurityKarthikeyan Ramasubramanian
IPC Router is a peer-to-peer, message oriented router that supports name service and limited multihop routing for interprocessor messages in the SoC. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable IPC LoggingKarthikeyan Ramasubramanian
IPC Logging is a low latency and minimal overhead logging framework used by many interprocessor communication drivers such as GLink. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable SMEM logKarthikeyan Ramasubramanian
The SMEM log allows certain log events to be synchronized between multiple processors in the SoC. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
2016-03-22defconfig: msm-perf: Bring it up-to-date with missing features during upgradeRohit Vaswani
Also run savedefconfig to remove any diff on both defconfigs. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
2016-03-22defconfig: Enable CONFIG_SYNC for AndroidRohit Vaswani
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
2016-03-22defconfig: arm64: Add msmcortex defconfigsAbhimanyu Kapur
Add defconfig for supporting msmcobalt debug, perf and other similar targets. Change-Id: I3a55fea53cbfe65131fc4ccd505bc684cda9b2fa Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
2016-03-22arm64: Split out MSM8996 from generic ARCH_QCOM platform KconfigAbhimanyu Kapur
Add support for CONFIG_MSM89986 and split it out from generic ARCH_QCOM platform. Change-Id: Ibc287ffb76e5599ba63449534b264e4f31c98ec6 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
2016-03-22ARM: dts: qcom: Snapshot all device tree files for MSMCOBALTAbhimanyu Kapur
Snapshot all device tree files from msm-3.18@b6a638f8795ee77ca ("Merge "msm: mdss: add support to send dcs cmds by left port only in video mode") Change-Id: I631047dffa019c6d2ee731ead328d332f1c7f3b8 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
2016-03-22Revert "defconfig: arm64: msm: Enable USB DWC3 and PHY drivers"Rohit Vaswani
This reverts commit 52bfd76cadb4bcc4371ea83429d9de0dab981eb7.
2016-03-22defconfig: enable subsystem restart, MSM_PIL_GENERIC and PIL_MSS_QDSP6V5David Keitel
Enable subsystem restart and relevant PIL drivers to allow secure peripheral image loading and QDSP6V5 loading to work. Change-Id: I899382d04e6a348cde2d46e9e0e6f3faadab2c5d Signed-off-by: David Keitel <dkeitel@codeaurora.org>
2016-03-22defconfig: disable EFIDavid Keitel
Change-Id: I26d6398478a8cbdcc56c93f501b70b9f9f2924e8 Signed-off-by: David Keitel <dkeitel@codeaurora.org>
2016-03-22dma-mapping: fix merge conflict mistakeDavid Keitel
As part of the 4.4 upgrade an incorrect merge conflict resolution in dma-mapping caused the function __dma_alloc_coherent to not work correctly. Fix this by changing correctly resolving the merge conflict resolution. Change-Id: I5b2411187768f2e3c4292a7c28cd742f5eb2dc54 Signed-off-by: David Keitel <dkeitel@codeaurora.org>
2016-03-22defconfig: enable MSM_PM for msm-perf defconfigMahesh Sivasubramanian
Enable sleep driver for QCOM chipsets Change-Id: I67244ff55690c164634e9233e2d0cec3388c5be8 Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
2016-03-22defconfig: Enable MPM for msm-perf defconfigMahesh Sivasubramanian
Change-Id: I09313d7809ec939a9d0440d0ab30a5992f512b96
2016-03-22arm64: psci: Support for OS initiated schemeMahesh Sivasubramanian
Existing PSCI implementation supports platform coordinated means of low power modes where cluster low power modes are aggregated at the platform level. Adding support for OS initiated scheme, where is OS is responsible for selecting cluster low power modes based on last man determination. With OS initiated scheme, the OS can make better cluster decisions based on wakeup times of CPUs within a cluster. To this effect, in OS initiated schemes, the composite state ID is computed by the idle driver before calling into the cpu_suspend API. The PSCI driver is modified to use the composite ID to distinguish between retention and non-retention states. Change-Id: Iee5533676a28a8f6beb7942dcb908f2fa3518d78 Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org> Conflicts: arch/arm64/kernel/psci.c
2016-03-22ARM64: smp: Prevent cluster LPM modes when pending IPIs on cluster CPUsMahesh Sivasubramanian
LPM modes can fail if there is a pending IPI interrupt at GIC CPU interface. On some usecases frequent failure of LPM modes can cause power and performance degradation. Hence, prevent cluster low power modes when there is a pending IPI on cluster CPUs. Change-Id: Id8a0ac24e4867ef824e0a6f11d989f1e1a2b0e93 Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org> Conflicts: arch/arm/kernel/smp.c arch/arm64/kernel/smp.c
2016-03-22cpu_pm: Add level to the cluster pm notificationMurali Nalajala
Cluster pm notifications without level information increases difficulty and complexity for the registered drivers to figure out when the last coherency level is going into power collapse. Send notifications with level information that allows the registered drivers to easily determine the cluster level that is going in/out of power collapse. There is an issue with this implementation. GIC driver saves and restores the distributed registers as part of cluster notifications. On newer platforms there are multiple cluster levels are defined (e.g l2, cci etc). These cluster level notofications can happen independently. On MSM platforms GIC is still active while the cluster sleeps in idle, causing the GIC state to be overwritten with an incorrect previous state of the interrupts. This leads to a system hang. Do not save and restore on any L2 and higher cache coherency level sleep entry and exit. Change-Id: I31918d6383f19e80fe3b064cfaf0b55e16b97eb6 Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org> Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org> Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
2016-03-22qcom: kconfig: Enable MSM_PM to enable QCOM sleep driversMahesh Sivasubramanian
Enable sleep driver for QCOM chipsets Change-Id: I67244ff55690c164634e9233e2d0cec3388c5be8 Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
2016-03-22defconfg: Enable MPM for msm defconfigMahesh Sivasubramanian
Change-Id: I09313d7809ec939a9d0440d0ab30a5992f512b96
2016-03-22defconfig: arm64: msm: Enable USB DWC3 and PHY driversJack Pham
Enable DWC3, QUSB and QMP PHY drivers to support the USB controller hardware. Also enable XHCI_HCD for USB host mode. Signed-off-by: Jack Pham <jackp@codeaurora.org>
2016-03-22ARM: dts: msm: Use correct HS PHY IRQ for msm8996 secondary USBJack Pham
The driver change in commit 96f92e28e035 ("usb: dwc3-msm: Use hs phy and ss phy irq as wake up source") favored using hs_phy_irq over pwr_event_irq to wake up USB out of suspend. This change revealed the wrong IRQ was used for the secondary USB2s instance on msm8996. Use the correct HS PHY IRQ number which maps to QUSB. Map this IRQ to the corresponding MPM wakeup pin as well. Change-Id: Ibd56c10c3c96f88d964f7f5f8a0fe9b590c522c5 Signed-off-by: Jack Pham <jackp@codeaurora.org>
2016-03-22ARM: dts: msm: Add ss_phy_irq as SS USB wakeup sourceHemant Kumar
For mdmcalifornium in case of super speed suspend, power event irq is not generated upon bus resume. Hence explicitly register for lfps_rxterm irq as a wake up source to initiate resume sequence for controller in super speed mode. To have the same solution across all platforms, update 8996 dtsi. Also for 8996 update the correct hs_phy_irq interrupt number as that of QUSB PHY IRQ. Change-Id: Ie0e67f202513b2c4bf069c10f2b2538a08c8c80c Signed-off-by: Hemant Kumar <hemantk@codeaurora.org> Signed-off-by: Azhar Shaikh <azhars@codeaurora.org>
2016-03-22ARM: dts: msm: Remove unused ref_clk from USBJack Pham
As of commit b44b9c5ae647 ("usb: dwc3-msm: Remove voting for ref_clk") the USB device no longer references the ref_clk. Remove the unused entries from msm8996, mdm9640 and mdmcalifornium. Change-Id: I3979e56293c8729cf89b32677bb23216ce68f120 Signed-off-by: Jack Pham <jackp@codeaurora.org>
2016-03-22ARM: dts: msm: Add ref_clk_src to QUSB PHYs on msm8996Jack Pham
The QUSB PHY instances each require a ref clk sourced by PMIC ln_bb_clk in order to function properly. Since this clock is shared among other peripherals, make sure the PHYs also can enable it independently when needed. Change-Id: Id5837532a2c9249b7babb720483c94734d80b717 Signed-off-by: Jack Pham <jackp@codeaurora.org>
2016-03-22defconfig: arm64: msm: Enable RmNet Data featureSubash Abhinov Kasiviswanathan
Enabled RmNet data on msm based platforms in order to support MAP data feature as required for data connectivity. Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
2016-03-22ARM64: Enable APPENDED_DTB in Makefile and defconfigRohit Vaswani
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
2016-03-22defconfig: msm_defconfig: Enable ION and IOMMU defconfigs. Also cleanup the ↵Rohit Vaswani
defconfigs Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
2016-03-22arm64: dma: Bring back set_dma_ops for other internal uses like dma-removed.cRohit Vaswani
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
2016-03-22mm: Update is_vmalloc_addr to account for vmalloc savingsSusheel Khiani
is_vmalloc_addr currently assumes that all vmalloc addresses exist between VMALLOC_START and VMALLOC_END. This may not be the case when interleaving vmalloc and lowmem. Update the is_vmalloc_addr to properly check for this. Correspondingly we need to ensure that VMALLOC_TOTAL accounts for all the vmalloc regions when CONFIG_ENABLE_VMALLOC_SAVING is enabled. Change-Id: I5def3d6ae1a4de59ea36f095b8c73649a37b1f36 Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-19 02:27:21 +0000