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Add SVS2 frequencies to the ufs_axi_clk_src and
ufs_ice_core_clk_src clock sources on MSMCOBALT.
CRs-Fixed: 1010329
Change-Id: I01210f48d32d7d6cb32f4977e52fb46acd33b1ba
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add the BCR register for the gcc_ufs_axi_clk and
gcc_blsp1/2_ahb_clk clocks.
CRs-Fixed: 1005036
Change-Id: I8cd2403bed66141c99ccf8b9c57e59b936c1d90e
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add support for controlling the graphics clocks on
MSMHAMSTER.
CRs-Fixed: 1004885
Change-Id: If96d8e7e0cd97cf45c48c6c39236d42659e25ea2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add support for controlling the multimedia clocks on
MSM HAMSTER.
CRs-Fixed: 1004885
Change-Id: Ic995c37ae819ce16668374cecf28fa98e6cf3180
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add support for controlling the peripheral clocks on
MSM HAMSTER.
CRs-Fixed: 1004885
Change-Id: If77ad3d662fbba145374abe38ea14a1a6e540fee
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Update the FMAXes for some camera clocks to align with
their supported frequencies.
CRs-Fixed: 1007250
Change-Id: I5691c34376f54845cbd288bb824d67fb1b8e4bbc
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The OSM clock is sourced from the LMh RCG. Model this RCG so
that it can be configured properly to provide the OSM a 200 MHz
clock source.
Change-Id: Ib799e8c082977ac226d6bd31ffad8ca63597c0fc
CRs-Fixed: 1007896
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Add support to program the DSI PLL on msmcobalt which is needed to drive
the DSI byte and pixel clocks.
CRs-Fixed: 1000576
Change-Id: Ic11a3747a0e008e1f71df91a1a79d33242d2a2a4
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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The hmss_gpll0_clk_src is being sourced off the gpll0 which
uses the cxo_clk_src RPM resource. This causes XO shutdown
to fail. Use the gpll0_ao source instead.
The hmss_ahb_clk_src RCG frequency table is also updated to
use the cxo_clk_src_ao to generate XO frequency.
CRs-Fixed: 1001330
Change-Id: Ic5cba530ea22cd19a20a21f0c33433c5e023debc
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The glm clocks are controlled by TZ, so remove support for
these clocks from the clock-gcc-cobalt driver.
Change-Id: Ibfb8f211ca8c29617aca4ff0ee885366f95aac00
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
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Change the log about the clocks being enabled even without a
SW vote to pr_warn instead of WARN. The stack trace isn't very
helpful in this case and cause a lot of logging.
Also, add the check_enable_bit property to some SMMU clocks
which are votable.
CRs-Fixed: 1006841
Change-Id: Icb15b038b170590e69073ca628b3d610e14893da
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The throttle clocks are managed by XBL and HLOS does not need to
control them. Remove support for these clocks from the clock
driver.
CRs-Fixed: 1006824
Change-Id: I1a33b3dbde6d5526be1073874e28b12350adad5e
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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clk_get_sys was updated to return EPROBE_DEFER because on the
older kernel returning ENOENT was causing drivers that probed
before the clock provider to fail instead of deferring. The new
kernel version fixes this by returning EPROBE_DEFER in
__of_clk_get_from_provider. Thus, clk_get_sys failing means that
the clock provider exists, but the requested clock is not defined
in the provider, in which case ENOENT is a more appropriate error
code to return.
Change-Id: I67d60bf5c0d2dfb71a189e351bc5b4c535d280bb
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
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Add HW clock measurement support for the gcc_gpu_cfg_ahb_clk,
gcc_gpu_bimc_gfx_src_clk and gcc_gpu_bimc_gfx_clk clocks.
CRs-Fixed: 1003179
Change-Id: Id403238f612a277973cd06f7d1d6f656a1812bba
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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There is a configurable divider between the byte_clk_src RCGs
and the mmss_mdss_byte_intf_clk clocks. Add support to program
it.
CRs-Fixed: 1003173
Change-Id: I976c2b9e9739b603f6cfb10d11c7b1d64cb577c5
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The CPR driver on MSMCOBALT needs the gpucc_rbcpr_clk clock in
order to probe and register the gfx_vreg regulator which the
graphics clock driver in-turn is dependent on for registering
the gfx3d clocks.
To break this circular dependency, register the non-gfx clocks
first, let the CPR driver probe, and then register the GPU PLLs
and gfx3d clocks. Also, correct the gfx CRC sequence.
CRs-Fixed: 986619
Change-Id: Id16ad7940e96cc9d5a3127551c8a92b05cfbb181
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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This merge brings all display changes from msm-3.18 kernel
* (58 commits)
msm: mdss: add support for additional DMA pipes
msm: mdss: refactor device tree pipe parsing logic
msm: mdss: refactor mixer configuration code
msm: mdss: add support for secure display on msm8953.
msm: mdss: disable ECG feature on 28nm PHY platform
msm: mdss: send DSI command using TPG when in secure session
msm: mdss: Update histogram and PA LUT in mdss V3
msm: mdss: validate layer count before copying userdata
msm: mdss: Fix potential NULL pointer dereferences
Revert "msm: mdss: Remove redundant handoff pending check"
msm: mdss: hdmi: Do not treat intermediate ddc error as failure
msm: mdss: revisit igc pipe enumeration logic
msm: mdss: Add PA support for mdss V3
msm: mdss: Add support for mdss v3 ops
msm: mdss: Update the postprocessing ops using mdss revision
msm: mdss: update the caching payload based on mdss version
msm: clk: hdmi: add support for atomic update
msm: sde: Add v4l2 rotator driver to enable multi-context usecase
msm: mdss: refactor pipe type checks
msm: mdss: add proper layer zorder validation
msm: mdss: stub bus scaling functions if driver is disabled
msm: mdss: avoid failure if primary panel pref is not enabled
msm: adv7533: add support for clients to read audio block
msm: mdss: add lineptr interrupt support for command mode panels
msm: mdss: update rotator frame rate in the pipe configuration
mdss: msm: Avoid excessive failure logs in igc config
msm: mdss: delay dma commands for split-dsi cmd mode panels
msm: mdss: enable GDSC before enabling clocks in MDP3 probe
mdss: dsi: turn off phy power supply during static screen
mdss: dsi: read dsi and phy revision during dsi ctrl probe
msm: mdss: Fix memory leak in MDP3 driver
msm: mdss: delay overlay start until first update for external
msm: mdss: free splash memory for MSM8909w after splash done
msm: mdss: hdmi: separate audio from transmitter core
msm: mdss: disable dsi burst mode when idle is enabled
msm: mdss: remove invalid csc initialization during hw init
msm: mdss: dsi: increase dsi error count only for valid errors
msm: mdss: remove HIST LUT programming in mdss_hw_init
msm: mdss: dsi: ignore error interrupt when mask not set
msm: mdss: add support to configure bus scale vectors from dt
msm: mdss: unstage the pipe if there is z_order mismatch
msm: mdss: squash MDP3 driver changes and SMMU change
msm: mdss: Read the bridge chip name and instance id from DTSI
msm: mdss: Enable continuous splash on bridge chip
msm: mdss: Fix multiple bridge chip usecase
msm: mdss: Enable export of mdss interrupt to external driver
msm: mdss: rotator: turn off rotator clock in wq release
msm: mdss: fix ulps during suspend feature logic
clk: msm: mdss: program correct divider for PLL configuration
msm: mdss: fix DSI PHY timing configuration logic
msm: mdss: hdmi: add support for hdmi simulation
msm: mdss: handle race condition in pingpong done counter
clk: qcom: mdss: calculate pixel clock for HDMI during handoff
msm: mdss: ensure proper dynamic refresh programming for dual DSI
msm: mdss: Add fps flag and update blit request version
msm: mdss: initialize fb split values during fb probe
mdss: mdp: fix rotator compat layer copy
msm: mdss: handle DSI ctrl/PHY regulator control properly
CRs-Fixed: 1000197
Change-Id: I521519c8abe8eed6924e2fbe3e1a026126582b77
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
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Currently, there is an assumption that the Fmax differs
from the minimum frequency. This is not necessarily true
if the Clock CPU device defines a single frequency. Fix
this by only adding a maximum frequency/voltage pair to
the OPP table if the maximum frequency differs from the
minimum supported frequency.
Change-Id: I6224ecb800bcbca821f42abec43bc57ee701ce80
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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The hmss clocks in the GCC domain should be left enabled
as they are required to be on as long as the CPUs are
active.
Change-Id: If3cc9573debc65018b896f64b1fc85d6a8682168
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Allow child devices to be defined and populated once the OSM
clock device probes. This enables parent and child relationships
across the OSM clock device and any dependent devices.
Change-Id: I0193663d72e05d8227f9814268ec293cfb94bbe3
CRs-Fixed: 994175
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Use secure IO write calls to program the APM crossover corner
and registers 47 and 48 of OSM sequencer architectural space.
Values for these registers reside in the HLOS, but must be
programmed from a secure domain.
Change-Id: I961bde48822adcbfbbb28130f2872104de5c11ce
CRs-Fixed: 992982
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Add a debugfs interface to enable and configure OSM debug trace
packet generation. There are four different supported OSM packet
IDs and two tracing modes. The supported sysfs files and their
corresponding values are:
trace_enable [0, 1]
trace_method [xor, periodic]
trace_packet_id [0, 1, 2, 3]
trace_periodic_timer [1 - 20000000] (us)
Unless otherwised modified through trace_periodic_timer, the
default periodic timer is set to 1 millisecond.
Change-Id: I82b7f78bac7379e9a647b5c8e68c356cd1d5c863
CRs-Fixed: 987787
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Refactor the enablement and parameter initialization of the
supported OSM FSMs. This initialization can be performed
by the clock-osm driver in absence of secure-world
initialization.
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
CRs-Fixed: 992982
Change-Id: Ie2a78394b388b0357459f1778bb7b2d821abde1c
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Support an additional column in the OSM look up hardware table
which establishes a mapping between frequency and mem-acc level.
The OSM uses this mapping to program ACC settings which vary
depending upon the performance level. In addition, update the
OSM sequencer and branch instructions to support ACC programming
as part of the clock scaling scheme and define the mem-acc level
associated with each row of the OSM look up tables.
Change-Id: I03e6f189ab0ab6af406a338bd667fb40240d89b3
CRs-Fixed: 981231
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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There have been some updates to the multimedia clock frequency
plan on MSMCOBALT. Reflect these in the linux clock driver as
well.
CRs-Fixed: 994012
Change-Id: If787e92dbd59b9147d44a53fa3d35d3b3bcfc3d9
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Update the alpha_pll_set_rate function to support dynamically
updating the pll frequency if the dynamic_update flag is defined
for the pll. Also set the HW_UPDATE_BYPASS_LOGIC bit for these
plls during handoff.
CRs-Fixed: 988270
Change-Id: I7f3527ef45cf68c3f5c41e04bfdd3ede55bbaa4d
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
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XO shutdown should not happen when there's still a sleep
vote on DDR. Making CXO as bimc_clk parent takes care of
this.
CRs-Fixed: 992753
Change-Id: I49ac2aefb645a4463cb1873072cd3a1f9a136dad
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add the dynamic_update flag and define the update_mask to enable
MMPLL9 to be able to dynamically update its frequency.
CRs-Fixed: 988270
Change-Id: I48a40f879b07469a954065d568c12e4a75925292
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
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The register offsets for the CPU PLLs might vary with
the standard offsets used for other PLLs. Remove having
the print capability for these clocks.
CRs-Fixed: 941434
Change-Id: Id67a70117b0621d98ac010f712552ecaaf92641f
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The default settings of the gcc_hmss_gpll0_clk_src make it
run at 600 MHz. Call set rate on the clock so that its
divider settings can be programmed.
CRs-Fixed: 989118
Change-Id: I49aee860dd3f0f4f7ecb024228f182d126424906
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The gcc_mmss_qm_ahb_ahb_clk is controlled by XBL on MSMCOBALT.
There is no need to control it separately from the linux clock
driver. Remove support for it.
CRs-Fixed: 988972
Change-Id: I23b4114096758342403e07058ef4df9b18f6622c
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add 300 MHz and 320 MHz as supportable frequencies for the VFE
clock sources on MSMCOBALT.
Change-Id: Id5eac307313bbf2a32d0ae8e4f3ae34e73d376a1
CRs-Fixed: 987721
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The gcc_dcc_ahb_clk needs to be controlled by the HLOS clock
driver on MSMCOBALT since its use is restricted to the HLOS
debug driver.
CRs-Fixed: 988930
Change-Id: I1abef9f1268080dbe5dba1e91f4b84fab03ce66c
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Update the PLL_LPF_CAP values to latest recommended settings.
This fixes any PLL locking issues.
Change-Id: I206c9cc343ac435161393445714de2e03a64aaae
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
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Updated characterization has shown the need to modify
certain calibration settings for hardware blocks within
the CPU subsystem. Modify these values.
CRs-Fixed: 930377
Change-Id: I601802746224e2abb43fd0b3aedb09e049062adf
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
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The video subcore RCGs should be force enabled during rate
scaling to workaround video firmware potentially disabling
the branch clock at the same time on msm8996.
CRs-Fixed: 971305
Change-Id: Ib0223ee33040c365d8a00bb796c44395102754f5
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Firmware running on HW blocks could be powering down the branch
clock or the RCG whilst software is doing frequency changes. If
this happens, the RCG behavior is undefined and may cause issues
with its functioning.
To work around this, use the RCG root_en bit and force turn it on
while scaling the rate. In addition, make the polling timeouts
configurable.
CRs-Fixed: 971305
Change-Id: If2db14c70614c47d673fc735f5f4bac276d4a3d9
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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On MSMCOBALT, while enabling the gpu_gx_gdsc, the DEMET cells
need to be explicitly reset by using the domain_addr register.
Add support in the gdsc driver to do this.
CRs-Fixed: 922984
Change-Id: I145a581a50719427b7303720a48cd421e2e1ef45
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The root clock for all GPUCC clocks, gpucc_cxo_clk is currently
being sourced off the cxo_clk_src clock. This will not allow XO
shutdown to happen. Use the cxo_clk_src_ao instead.
CRs-Fixed: 983874
Change-Id: I7f8dd9ea28114d3d06fec3397064356b4deb6e7e
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Use the cxo_clk_src_ao resource to source the HMSS CPR RCG. In
addition, remove it's vote on the CX rail since CX is guaranteed
to be at least SVS2 as long as even one CPU is online.
CRs-Fixed: 983870
Change-Id: I5a4d37310e56235a590e8a93dc8a33d6c3e46e4d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The mmss_mdss_byte0/1_intf_clk clocks are needed by the display
driver. Add support to program them in the clock driver.
CRs-Fixed: 981902
Change-Id: I17b1ecaec9c98261faa49c6f088c4802a716ecf7
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Update the number of frame rates supported for dynamic refresh
feature from 10 to 20. This is needed to support all the fps
values requested by display HAL between minimum fps and maxiumum
fps based on the requirement.
Change-Id: Ib7487ad17261ac8c4d6929787899161061e71078
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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As part of dynamic refresh sequence, we program PLL_UPPER_ADDR2 register to
0x003FFE00 instead of 0x001FFE00. This causes a register write to
DSIPHY_PLL_KVCO_COUNT1 to 0x1 during the dynamic refresh operation whereas
the register write is supposed to happen for DSIPHY_CMN_PLL_CNTRL register.
Update the write value to DYNAMIC_REFRESH_PLL_UPPER_ADDR2 to take care
of this.
Change-Id: I991920d5a45e79670a4a033c8a83bef6c7f3136b
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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Rename the vdd-level header file included from vdd-level-californium
to vdd-level-cobalt, which is the correct name. Also update the
header file to include the FMAX mappings needed for the cobalt
GPUCC driver.
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
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Modify the round_rate() callback function so that it selects
the nearest configured fmax frequency instead of the closest
possible supported frequency of the parent clock. This ensures
that clk_round_rate() always returns power efficient frequencies
for 8996 CPU clocks.
Change-Id: Icc27ba64b9c8af74ee0f81443fea37c4564b9f94
CRs-Fixed: 981475
Signed-off-by: David Collins <collinsd@codeaurora.org>
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To open up the frequency range from 150 to 300MHz, change
the fixed CBF PLL post divider from 2 to 4. That way, to
generate frequencies less than 300MHz, the VCO can be run
at 4x with the CBF mux set to use the main output.
While we're here, add the cbf_pll_main clock to the lookup
table.
CRs-Fixed: 980903
Change-Id: I9f70f18e01199c41e1940857afb7bdd477c1c04c
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
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Configure the RECAL_VCTL/CPR_DLY registers to enable and set the
voltage delay time for hardware based droop detector recalibration.
Only needed on MSM8996 Pro.
CRs-Fixed: 980641
Change-Id: I217e4510b020b7708665394c42f46773bd8b225d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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The Operating State Manager is a hardware block which deals with
performing voltage and frequency change operations in the CPUSS. Two
instances exist, one for each cluster, in the msmcobalt chip.
Introduce the OSM clock driver to perform the required OSM hardware
block initialization and support DCVS scale requests.
Change-Id: I3e155db5cd580e371ca1791815e4942f442a3d20
CRs-Fixed: 967319
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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In the current implementation, the DSI PLL codes are copied from
a CMA memory which has a no-map attribute. Update the logic by
reading the pre-calibrated DSI PLL codes from physical memory
which is re-mapped to virtual memory allocated in kernel using
ioremap_page_range. Once the DSI PLL codes are stored, free the
reserved CMA memory back to kernel.
Change-Id: Iaa0bbd600dd1a18497cd4dfd7830a9bf88ab0ead
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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Update the clock framework to support the setting of post_div for
debug mux so as to divide the clock by post_div.
CRs-Fixed: 977413
Change-Id: I7299bdb0953dcf65fbf2a38b7578e2e54446c0d7
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
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