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2016-03-22soc: qcom: pil-q6v5: Add support to read acc register value and override itAvaneesh Kumar Dwivedi
Update the reset sequence to read and override acc register based on msm specific value provided in device tree. Change-Id: I8ed290f5ab5e48e94ef5c8c91fd1d8f8414e86f7 Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
2016-03-22soc: qcom: Add generic irq handler for secure processorPuja Gupta
This patch adds the code to handle watchdog, err_ready and other interrupts from secure processor subsystem to the PIL driver. CRs-Fixed: 972423 Change-Id: I65455229ee14bd4da357358ac3977f2137f3c07e Signed-off-by: Puja Gupta <pujag@codeaurora.org>
2016-03-22msm: ep_pcie: update the regulator API call on 4.4 kernelYan He
Update the regulator API used in PCIe endpoint driver for 4.4 kernel upgrade. Change-Id: Iacca851bfbd7f5a5544b97ac82630d9a2dc5ebfc Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: add the support of PCIe EP mode for mdmcaliforniumYan He
Add the support of PCIe Endpoint (EP) mode for mdmcalifornium. Change-Id: I55c85813e674810d865b444b7e19ce4157cea479 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: Update MSI configurationSiddartha Mohanadoss
Update check for valid MSI enable and setting using MSI_ENABLE bit instead of address and data. Host can set address and data to 0 therefore check if MSI_ENABLE is set. Change-Id: I686c3ed155b8c5c843d12a49218f4720655dcc18 Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
2016-03-22msm: ep_pcie: update PCIe PHY configurationYan He
Update the configuration of PCIe PHY based on the version of PHY. Change-Id: I1faf65c2cc1215cd6ad679d0c4558a17f43db3fc Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: support multiple link training optionsYan He
Add the support to trigger link training based on PCIe PHY version. Change-Id: I4c765797d8e8adf5c15effae95da350a0d8ec0c3 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: add the phy reset clockYan He
Add the phy reset clock for PCIe endpoint mode and add the support of this optional clock. Change-Id: Id92e2fd589d0e97e8a3db2e1eeb1d6c99a464777 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: fix the bug in debugfs testingYan He
PCIe device ID can't be got from register when the power of the core is off. Thus, use the saved device ID so that we can turn on link in the debugfs testing. Change-Id: I28ec17b4fdf84b130cd32267d097b1c0d7c32aed Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: fix the bug of power statusYan He
Fix the bug of the power status of PCIe core and update the power status as soon as power is turned on. Change-Id: Ib5b550c78a630d36049296daf1291065a1a44cd5 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: update retry counters and intervalsYan He
Update retry counters and intervals for PCIe PHY init and PCIe link training to accommodate various hosts. Change-Id: I767de1f08580137559e974c0ef90273ccf5f4b76 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: update lpeak values of PCIe LDOsYan He
Update the lpeak values of PCIe LDOs based on the updated HW requirement. Change-Id: I2f8b63edf3f8571ea960abdebde982324f7f6d74 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: add L1ss supportYan He
Enable L1ss support in L1ss capability register. Change-Id: I51e6e1bbd8073e7bb88c7e041199d862db020ae7 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: disable debouncersYan He
Disable debouncers for PCIe endpoint mode. Change-Id: I504418193920861296d995bd898f01307e6dc518 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: update read-only registers for compliance testingYan He
Update some read-only PCIe registers with non-arbitrary values which are required by PCIe compliance testing. Change-Id: I10fd448f38d874ba582d1a46a98a76d29e0d9cb4 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: fix duplicated counter incrementYan He
The logging macro has multiple outputs. If we increase the counter as a parameter to the logging macro, the counter will be increased for multiple times. The change here fixes this bug. Change-Id: I321e281b506e35770e222def86f5b04ae0bfdce2 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: correct PME configurationYan He
Correct the PME configuration for PCIe endpoint to support D0, D3 hot and D3 cold. Change-Id: Ib906fbafc490be75e5f178176e33882c392d074e Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: allow wake assertion during D3hotYan He
PCIe client may need to wake up the host when PCIe link is still on. Add the support to assert wake to host side when PCIe is in D3hot. Change-Id: I15ffd5f03183054c7ef5d143757b923f32de0adc Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22msm: ep_pcie: add PCIe endpoint driverYan He
The MSM PCIe endpoint driver enables the PCIe core in endpoint mode and handles the control signaling with PCIe root complex on host side. Change-Id: Ifc2735e061820762c6040eda44089a2dc26fc065 Signed-off-by: Yan He <yanhe@codeaurora.org>
2016-03-22spmi: pmic_arb: use handle_fasteoi_irq handlerAbhijeet Dharmapurikar
The interrupt controller uses level handler for all its interrupt. The hardware irq controller confirms to the fasteoi handler type in that it rearms itself when acknowledged. There is no need to additionally mask the interrupt while being handled. Use fasteoi handler type for pmic interrupts. Since fasteoi needs an irq_eoi callback, use the same function used for irq_ack. Change-Id: I9a941d8b56ad5698da38e16b2afcf87ef920ebfd Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
2016-03-22spmi: pmic_arb: don't synchronize accesses to interrupt regionAbhijeet Dharmapurikar
The current driver ensures that no read/write transaction is in progress while it makes changes to the interrupt regions. This is not necessary because read/writes over spmi and arbiter interrupt control are independent operations. Change-Id: Id6a93eed0aabe55a4b655a2050c31b48327dffe4 Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
2016-03-22spmi: pmic_arb: remove disabling of ACC bitAbhijeet Dharmapurikar
The interrupt controller code in the arbiter disables the peripheral accumulated interrupt (ACC) bit when none of the interrupts in the peripheral is enabled. This is not required since the controller disables the interrupt at the pmic. So leave the ACC bit enabled while masking an interrupt. Also ensure that the ACC bit is enabled while unmasking an interrupt. There is no issues with enabling ACC bit if it were already enabled. Change-Id: Idbea562157e65a4dfe0c51b7a25eed5ce000068d Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
2016-03-22msm: kgsl: Increase GPMU timeoutsJordan Crouse
The existing timeout values for the various GPMU interactions seems to have been a tad optimistic for all conditions. Increase them to cover measured worse case scenarios. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2016-03-22msm: kgsl: Conditionally use bwmon governor if it existsJordan Crouse
Wrap the code to use the bwmon governor or not depending if it exists. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2016-03-22msm: kgsl: Update various exernal APIs for the 4.4 kernelJordan Crouse
Make several changes to build the GPU driver for 4.4: - Rename CONFIG_MSM to CONFIG_QCOM where applicable - Add msm_kgsl.h to the Kbuild exports - Remove linux/coresight_of.h (as it has been merged into coresight.h) and remove the .owner member of the coresight_desc struct. - Use the new location for the sync.h file (in staging) - Remove an unused sync function - Move oneshot_sync.h inside of #ifdef wrappers Signed-off-by: Jordan Crouse <jcrouse@codeauorora.org>
2016-03-22devfreq: Add Qualcomm GPU devfreq governorsJordan Crouse
Snapshot of the Qualcomm GPU devfreq governors and support as of msm-3.18 commit e70ad0cd5efd ("Promotion of kernel.lnx.3.18-151201."). Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2016-03-22PM / devfreq: allow governors to use devfreq_get_freq_levelJeremy Gebben
Level based governors may need to perform this lookup to interpret the current frequency of the device. Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org> Signed-off-by: Vladimir Razgulin <vrazguli@codeaurora.org>
2016-03-22msm: kgsl: Add Qualcomm GPU driverJordan Crouse
Snapshot of the Qualcom Adreno GPU driver (KGSL) as of msm-3.18 commit commit e70ad0cd5efd ("Promotion of kernel.lnx.3.18-151201."). Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2016-03-22iommu/arm-smmu: Add iommu_dev for dynamic attach casePatrick Daly
A new struct element was added during the kernel 4.4 upgrade. Ensure that it is set during dynamic attach. Change-Id: I0150aebe4a67728945890be2b547a6cbb9bd5306 Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
2016-03-22Coresight: add support for device namesShashank Mittal
Add support to read device names from device tree entries. This allows using same names for CoreSight devices across different targets. Change-Id: Ide3da74533051db38e9a6c5904a7cab42b3be6c1 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-03-22Coresight: change attribute names for sources and sinksShashank Mittal
Use 'enable' instead of 'enable_source' and 'curr_sink' instead of 'enable_sink attributes to align it with MSM implementation. This change ensures same device node interface for host tools between MSM and upstream Coresight driver implementation. Change-Id: I5267d2ad92e76607e0ac1bd0e9ef63c0a89cfe7f Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-03-22coresight: add CSR driver support in upstream implementationShashank Mittal
Add CSR driver in upstream implementation of coresight driver. This change copies drivers/coresight/coresight-csr.c (commit : 90095b2a) to driver/hwtracing/coresight directory. Change-Id: Ib5408ccce868bb36230a26a8d32f463a80a4a6a5 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-03-22coresight: tmc: add scatter-gather support for ETR deviceShashank Mittal
Add support to configure ETR device in scatter-gather mode. In scatter-gather mode trace buffer can be configured to use bigger buffer size without need of bigger contiguous memory. Change-Id: I3ce654392d2b75d24f7982638e53c2aab27d4a0e Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-03-22coresight: tmc: add support to configure etr mem sizeShashank Mittal
Add support to expose a node for user to configure memory buffer size for an ETR device. Change-Id: Ide175ca8eeb5b9c2d7213dfff4c81b5314ce61f6 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-03-22coresight: stm: change to amba device driverShashank Mittal
Current STM device registers itself as a platform device. Change it to an amba device driver to align it with upstream implementation of coresight devices. Change-Id: I7ff9300e3606d5ffc9a54098f7f5d4d03212fec0 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-03-22coresight: add STM driver support in upstream implementationShashank Mittal
Add STM driver in upstream implementation of Coresight driver. This change copies drivers/coresight/coresight-stm.c (commit : 90095b2ae1d987882f67c6d4a512baa98eecd6cb) to driver/hwtracing/coresight directory. Change-Id: Id023bf85df0345205ca8baa6a97ff340d5808aeb Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-03-22iommu: Apply necessary initcall orderingPatrick Daly
Iommus do not currently support probe deferral. Ensure that they probe after gdscs. Change-Id: I693ce5ba74090a76f0442a3057fe45ff849c3fe1 Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
2016-03-22iommu-debug: Add proper header file for module_init()Patrick Daly
Fix compilation on 4.4 kernel. Change-Id: I760e9adb94c15263e4bf653aec2e3c63e368c2bc Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
2016-03-22iommu/io-pgtable-arm: Fix IOMMU_IO_PGTABLE_LPAE_SELFTEST compilationPatrick Daly
Use the proper number of arguments to map_sg() Change-Id: I8f1d038334b0145436e7df86283482482ebca209 Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
2016-03-22iommu/arm-smmu: Restore __arm_smmu_get_pci_sid()Patrick Daly
This function is used upstream. Restore it. Change-Id: If828a4e3504a27b866daea9caa6d9238b362bb16 Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
2016-03-22arm-smmu: Remove PCIE header file dependencyPatrick Daly
Until the msm pcie driver has been upgraded, remove references to its header file to allow compilation. Change-Id: I6413abfd2279a20a4c062cb04d9e0e1f1b10ce9d Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
2016-03-22iommu/io-pgtable: Add module.h include filePatrick Daly
This is needed for the module_init/exit() macros. Change-Id: Ibbb757685b285c28fc8fae8cb27555dccebd9c86 Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
2016-03-22Revert "scatterlist: use sg_phys()"Dan Williams
commit db0fa0cb0157 "scatterlist: use sg_phys()" did replacements of the form: phys_addr_t phys = page_to_phys(sg_page(s)); phys_addr_t phys = sg_phys(s) & PAGE_MASK; However, this breaks platforms where sizeof(phys_addr_t) > sizeof(unsigned long). Revert for 4.3 and 4.4 to make room for a combined helper in 4.5. Cc: <stable@vger.kernel.org> Cc: Jens Axboe <axboe@fb.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Andrew Morton <akpm@linux-foundation.org> Fixes: db0fa0cb0157 ("scatterlist: use sg_phys()") Suggested-by: Joerg Roedel <joro@8bytes.org> Reported-by: Vitaly Lavrov <vel21ripn@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2016-03-22iommu: Move default domain allocation to iommu_group_get_for_dev()Joerg Roedel
Now that the iommu core support for iommu groups is not pci-centric anymore, we can move default domain allocation to the bus independent iommu_group_get_for_dev() function. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-03-22iommu: Remove is_pci_dev() fall-back from iommu_group_get_for_devJoerg Roedel
All callers of iommu_group_get_for_dev() provide a device_group call-back now, so this fall-back is no longer needed. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-03-22iommu/arm-smmu: Switch to device_group call-backJoerg Roedel
This converts the ARM SMMU and the SMMUv3 driver to use the new device_group call-back. Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-03-22iommu: Add generic_device_group() functionJoerg Roedel
This function can be used as a device_group call-back and just allocates one iommu-group per device. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-03-22iommu: Export and rename iommu_group_get_for_pci_dev()Joerg Roedel
Rename that function to pci_device_group() and export it, so that IOMMU drivers can use it as their device_group call-back. Change-Id: Ic54268d9854dd2eeba53ca9f9635d0287bfc7f0f Signed-off-by: Joerg Roedel <jroedel@suse.de> [pdaly@codeaurora.org Resolve minor conflicts]
2016-03-22iommu: Revive device_group iommu-ops call-backJoerg Roedel
That call-back is currently unused, change it into a call-back function for finding the right IOMMU group for a device. This is a first step to remove the hard-coded PCI dependency in the iommu-group code. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-03-22iommu/arm-smmu: Remove redundant calculation of gr0 base addressWill Deacon
Since commit 1463fe44fd0f ("iommu/arm-smmu: Don't use VMIDs for stage-1 translations"), we don't need the GR0 base address when initialising a context bank, so remove the useless local variable and its init code. Signed-off-by: Will Deacon <will.deacon@arm.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-20 09:17:58 +0000