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2016-06-24msm: mdss: fix multi-rect validation propertiesAbhijit Kulkarni
Fix issues with multi-rect to allow the multi-rects on the same z-order. In multi-rect use cases the rect 0 of the pipes have higher priority than rect 1. The change checks the priority of rect on the right mixer with the priority of rect on the pipe staged on left mixer. CRs-Fixed: 1023723 Change-Id: Ifd1df8ee04238db0338a7dd70eb5097af2d0eb62 Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2016-06-24msm: mdss: Add dereference check for xlog vbif dumpAlan Kwong
Bypass vbif dump for ununsed vbif by checking for null pointer dereference of io base. Change-Id: Ic7204921fc82d5aea31c58fcbb668b296794b1c1 CRs-Fixed: 1030443 Signed-off-by: Alan Kwong <akwong@codeaurora.org>
2016-06-24scsi: ufs-debugfs: add error stateSubhash Jadavani
This change adds support to allow user space query if low level UFS driver has encountered any error or not, this state can be read/cleared via debugfs. Change-Id: I867a4621315108aff17be852cfaadcfa945566a7 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
2016-06-24regulator: cpr3-util: init panic notifier for CPRh controllersOsvaldo Banuelos
Call cpr3_panic_notifier_init() when cpr3_parse_common_ctrl_data() is called for CPRh controllers. This allows dumping registers during a kernel panic when CPRh controller devices specify panic register configuration. CRs-Fixed: 1033060 Change-Id: I437fe28725d5c1ed06fe8b9735b04bbd84e92db1 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
2016-06-24regulator: cpr3: Add panic handler to dump register contentsTirupathi Reddy
Add panic handler to dump a few critical CPR registers when device crashes due to kernel panic errors. CRs-Fixed: 1004533 Change-Id: Id01b4f959c134af48c509ade61c7ec46401b4e70 Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
2016-06-23clk: msm: Set the GMEM GX clamp before disabling the GPU_GX GDSCDeepak Katragadda
The GMEM GX clamp should be set to the active state before turning off the gdsc_gpu_gx. CRs-Fixed: 1027772 Change-Id: I5bb97734a2402e763836250c3ce6f7fc308c20a6 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-06-23clk: qcom: alpha-pll: Add support for hwfsm opsRajendra Nayak
Add support to enable/disable the alpha pll using hwfsm Also add support for initial configuration (needs to be split) Change-Id: Ifc2fe0539b943e850681143da76da27274203ed2 Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23clk: qcom: Add Alpha PLL supportStephen Boyd
Add support for configuring rates of, enabling, and disabling Alpha PLLs. This is sufficient for the types of PLLs found in the global and multimedia clock controllers. Change-Id: I0d26e8f6d225cc3669f3a9e3c37b45e49e139879 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23fixup rpm clks on 8996Srini Kandagatla
Change-Id: Ia19aa0ebc209322955da1d22f5eb73c9cd7af908 (cherry picked from commit 6c72267db866b9841312defdf81b100db77a0e71) Git-commit: 6c72267db866b9841312defdf81b100db77a0e71 Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Srini Kandagatla <srinivas.kandagatla@hackbox.linaro.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23clk: qcom: rpmcc: Add rpm clock data for msm8996Rajendra Nayak
Add all RPM clock data for msm8996 family of devices ToDo: Adapt to changes needed for RPM over GLINK against RPM over SMD that the driver currently supports Change-Id: Ib095af601a4f03d866cf94c8e277d04630abb42b Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23clk: qcom: Add support for RPM ClocksGeorgi Djakov
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Change-Id: I1a73355bc9117c34589a25cf58446cad13ceb6e3 (cherry picked from commit 06d998a24c68be94685af38e8becfda3c8bf757b) Git-commit: 06d998a24c68be94685af38e8becfda3c8bf757b Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23clk: qcom: Add support for SMD-RPM ClocksGeorgi Djakov
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c Change-Id: I8d2882de9410a992a8045caedc7ab71e3c3e45b2 (cherry picked from commit 69edeaf51c07c24e06b433762b3ada7b3d786315) Git-commit: 69edeaf51c07c24e06b433762b3ada7b3d786315 Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23clk: qcom: Add A53 clock driverGeorgi Djakov
Add a driver for the A53 subsystem PLL, so that we can provide higher frequency clocks for use by the system. Change-Id: I69b4c363c8b656bcd9481b6310a972b8140311a9 (cherry picked from commit 60e4f862c16dfc995a71ec0f50524e020dbfde2f) Git-commit: 60e4f862c16dfc995a71ec0f50524e020dbfde2f Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23clk: qcom: Add Krait clock controller driverStephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary mux for each CPU and the L2, controlled via cp15 accessors. For Kraits within KPSSv1 each secondary mux accepts a different aux source, but on KPSSv2 each secondary mux accepts the same aux source. Change-Id: I871de8d291f5c1b848b215766c61b8bd0ed98f77 Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23msm: misc: hdcp: support tz hdcp2p2 app interface changeShivaprasad Hongal
TZ hdcp2p2 app interface has changed to include device, session commands and version control. Update hdcp driver to align. CRs-Fixed: 1027108 Change-Id: I4acdad2f243ea32f6ce10b6c0064ef2a5262fab2 Signed-off-by: Shivaprasad Hongal <shongal@codeaurora.org>
2016-06-23coresight-tpdm: fix dsb edge ctrl mask interfaceShashank Mittal
Fix edge ctrl mask interface for DSB subunit to accept DSB event ranges in both hexadecimal and decimal format. Change-Id: Ibe650067fc30a65defa2c0e76ef5526235980f72 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-23coresight-tmc: configure ETR_DBAHI registerShashank Mittal
On an ARM64 arch this register is used by ETR to find correct location of buffer in memory. Change-Id: Ie0aa7932e46f63969ba85cb0dc4855b3b267f2d6 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-23coresight-tmc: avoid reading TMC buffer before enablingShashank Mittal
Add stricky enable flag to avoid reading TMC buffer before enabling TMC at least once. Change-Id: Iccb6338ef4fce25830f27541f5f22cfcad7264ae Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-23coresight-tmc: fix read_count for tmc_openShashank Mittal
'read_count' is used to reference count simultaneous TMC read requests. This count should reset to zero in case tmc_read_preapare fails. Change-Id: Iaded781ee76ec3b079ac9cd9d551bdfb42834fd9 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-23clk: msm: clock-gcc-cobalt: Enable support to scale the aggre clocksDeepak Katragadda
The aggre NoC clocks are controlled by RPM and until now, HLOS has only had to enable/disable the resource when required. Due to a new requirement, enable support to scale these resources as well. Change-Id: I3b141d62f6c3b479d8d61ae7829e9f5ca72a3886 CRs-Fixed: 1030966 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-06-23coresight-tmc: add support to save TMC registersShashank Mittal
On some devices TMC registers are not preserved across reset. Add support to save TMC registers to read TMC buffer after a crash. Change-Id: I5fb7e870ddece35159d1fe465d4b70d2a4c1ec35 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-22msm: ipa: fix delete dependency race conditionSkylar Chang
IPA RM dependencies are added both by kernel drivers and by userspace application (IPACM), depending on the use case. On rare condition, a race is possible between adding the dependency and deleting it, which results in a bad state of the dependency graph. This change makes sure that dependency is deleted only if it was added by the same entity. CRs-Fixed: 1027773 Change-Id: I9253469887b8913f6f2c513a6c7043ed60400b8a Acked-by Ady Abraham <adya@qti.qualcomm.com> Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
2016-06-22qcom-cpufreq: Use cpufreq_table_validate_and_show to fill freq_tableJunjie Wu
cpufreq_table_validate_and_show() is created as a standard way to initialize frequency for a policy and assign freq_table. Use this new API to assign freq_table. CRs-Fixed: 1024229 Change-Id: Iac3a9394790e140492c5c0c0ad6d068840bfffa4 Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
2016-06-22hwmon: qpnp-adc-voltage: Update VADC settings maskSiddartha Mohanadoss
Update the mask to use default settings to enable fast average for channel configuration. Setting this allows low latency for multiple averaged conversions. Also update the field mask for hardware settling delay. Change-Id: If50943f86a6d3f54039a0b4ed4f8a71c8aaaa1fa Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
2016-06-22msm: isp: Reducing logs in error caseAbhishek Kondaveeti
Reducing logs in error case by making pr_err as pr_err_limited. Change-Id: I2ff998fcec7ace9a94ca67a797f008389dc510f2 Signed-off-by: Abhishek Kondaveeti <akondave@codeaurora.org> Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
2016-06-22msm: isp: Avoid unaligned register accessAbhishek Kondaveeti
Unaligned register access will reslut in device crash. Avoid them by checking the register address before accessing them. Change-Id: Ib58efa2a68115ec9929b9270c123c904737196ee Signed-off-by: Abhishek Kondaveeti <akondave@codeaurora.org> Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
2016-06-22msm: camera: isp: Fix framedrop reportingJing Zhou
This change fixed the framedrop reporting that causes the CTS test failure. The failure is due to the wrong frame id is used to report the framedrop. This change will change the framedrop report logic so that the correct frame id is used. Change-Id: I5b219ed570b81a7fd6a97be46977cafd3e452492 Signed-off-by: Jing Zhou <jzhou70@codeaurora.org> Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
2016-06-22qcom-charger: introduce parallel charging supportHarry Yang
Parallel charging increases charging capacity and efficiency by distributing the current between two charging chips. PMI8998 feeds the parallel charger via its MID input, and handles input current limiting in its front-porch FET. As master charger, PMI8998 is responsible for enabling/disabling the parallel charger, and the FCC distribution. To enable parallel charging in software, the following conditions must be met: - Strong USBIN input - Battery present - In fast or taper charging state - Attached UFP source While the enabling/disabling is always under the control of software the disabling can also be done by hardware in case of fault. Battery current is usually fixed to the battery rating. The FCC distribution is simple, a split of 50/50 by default, which can be changed in runtime. When taper irq kicks in, the algorithm reduces parallel FCC by 25%. This puts the charging back in constant current phase until the next one happens where again the algorithm reduces the FCC by 25%. This continues until the parallel FCC drops to 500mA. At that time parallel charging is disabled and master continues charging the rest of constant voltage phase. CRs-Fixed: 1023703 1030934 Change-Id: Ied7c31d5913df94a288d36ecf06d081d32e07396 Signed-off-by: Harry Yang <harryy@codeaurora.org> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
2016-06-21coresight-tmc: add support to configure flush and reset CTIsShashank Mittal
Add support to map/unmap TMC flush and reset CTIs as part of TMC enable/disable. Change-Id: I5aae2ce3d2e0dec252139db571d4598d49f3a371 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-21coresight-etm4x: enable default include address range comparatorShashank Mittal
ETM driver sets the address comparator in TRCACVR0 and TRCACVR1. Enable default inclusive range selected by these registers. Change-Id: I08d798d6fb24571856929f84db572bbd3651cd6c Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-21coresight: change CoreSight device probe orderShashank Mittal
Change to make sure that CTIs get probed before CoreSight sources and sinks. Change-Id: I7e83fe663c32a6d75470bb0cb546b42c9fe04ab1 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-21coresight: add support to read cti dataShashank Mittal
Add support to read cti data from OF nodes. Devices can use this data to configure CTIs as part of their configurations. Change-Id: I55b0534ab4d81b9ce02378b513e6ae9bc3b6cd1e Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-21coresight-etm4x: add code to allocate memory for dump tableShashank Mittal
Add code to allocate and register memory dump entry for dumping etm registers. Change-Id: I0487e1c0d4e0fffc5df1456d53567762d7b18d51 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
2016-06-21msm: camera: isp: Implement new ioctlShubhraprakash Das
Implement a new ioctl that sets the ahb clock vote. This can be used from user space to make register programming quicker. CRs-Fixed: 1001335 Change-Id: I1bc0253ada50040d55b57f0ed07ba66b5535106a Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
2016-06-21usb: gadget: Use mult as 3 for GSI related USB IN endpoint alwaysMayank Rana
Interfaces like MBIM or ECM is having multiple data interfaces. In this case, SET_CONFIG() happens before set_alt with data interface 1. Due to this, TXFIFO of GSI IN endpoint is not resized causing low throughput in DL direction. Fix this issue by using mult as 3 for GSI related USB IN endpoint irrespective of super-speed or high-speed mode. CRs-Fixed: 1025031 Change-Id: I10de98ae57284699af3abcd90bafac63ba03844e Signed-off-by: Mayank Rana <mrana@codeaurora.org>
2016-06-21Revert "usb: dwc3: core: only setting the dma_mask when needed"Hemant Kumar
commit 19bacdc925055f020a ("usb: dwc3: core: only setting the dma_mask when needed") does not allow to modify dma mask if it is already set. Since the platform device has default 32-bit dma mask set change prevents to update the dma mask to 64-bit. This leads to kernel panic due to out of SW-IOMMU space when a function driver tries to map more than 32-bit wide address. Change-Id: I38b178f38277f9a2fa40735f4e15385638403ae6 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2016-06-21mmc: host: sdhci-msm: fix NULL pointer dereferenceSubhash Jadavani
We are seeing the kernel panic due to NULL pointer dereference with following call trace: sdhci_msm_set_clock+0x59c/0xa28 sdhci_do_set_ios+0xf4/0x740 sdhci_set_ios+0x28/0x3c mmc_set_ios+0xac/0x1ec __mmc_set_clock+0x2c/0x3c mmc_ungate_clock+0x20/0x28 mmc_host_clk_hold+0x54/0xc4 mmc_power_off+0x1c/0x70 mmc_rescan+0x250/0x27c process_one_work+0x240/0x420 worker_thread+0x268/0x390 kthread+0xf8/0x100 This is happending when eMMC initialization is failing in HS400 mode. sdhci_msm_set_clock() might be accessing the card pointer after it was deallocated, this change adds the safety checks to avoid NULL dereference. Change-Id: I895b8b33cce4173100d58acf690e57b5f4e69081 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
2016-06-21tty: serial: msm: replace iowrite32_rep with writel_relaxed_no_logSatya Durga Srinivasu Prabhala
RTB logs gets flooded during console write operation due to logged variant of API. This commit replaces logged variant API with no log variant to suppress logs. CRs-Fixed: 1030352 Change-Id: I79f943cbc13553b3dbdce68f5c1143fa54f6eafa Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2016-06-21clk: msm: osm: remove rtb logging for cycle counter readsOsvaldo Banuelos
The cycle counters are read often by the scheduler to perform CPU clock frequency estimation. Remove logging the counter reads to prevent unnecessary logging to the RTBs. Change-Id: I15e26e4d46d5ee663923d5678fa75878636e6940 CRs-Fixed: 1023437 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
2016-06-21drivers: clocksource: arch_timer: enable user access to virt timersKyle Yan
Allow virtual timers i.e. CNTV_TVAL_EL0 to be accessed by userspace. CRs-Fixed: 1018301 Change-Id: I724ddbf4e7c02ee25622c6712210aee948d037f6 Signed-off-by: Kyle Yan <kyan@codeaurora.org>
2016-06-21lowmemorykiller:fix arguments to zone_watermark_ok_safeSrinivas Ramana
The alloc_flags argument of zone_watermark_ok_safe() is no more available. Fix the usage. Change-Id: I99b832418b914765a4941682929dd7183d274e1c Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
2016-06-21msm: ipa3: support use for 64bit DMA maskSkylar Chang
add 64bit dma mask support on ipa3 to resolve the dma pool exhausted issue. Change-Id: I629e2ae15574ab779c43dd40d40cf169fe19bb8e Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
2016-06-21spcom: add spcom_is_sp_subsystem_link_upAmir Samuelov
Add implementation of spcom_is_sp_subsystem_link_up() kernel API. Remove Load App API declaration, as it is not supported for kernel drivers. Change-Id: I76a43a04d454d1f25a640831f43b51dbb7e75943 Signed-off-by: Amir Samuelov <amirs@codeaurora.org>
2016-06-21staging: android: Change %p to %pK in debug messagesDivya Ponnusamy
The format specifier %p can leak kernel addresses while not valuing the kptr_restrict system settings. Use %pK instead of %p, which also evaluates whether kptr_restrict is set. Change-Id: Ib1adf14e9620ad7b1bd3e962001c852610210d46 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
2016-06-21msm: ipa3: Move IPA FnR building to IPAHALGhanim Fodi
IPA Filtering and Routing rules and tables building is a logic related to IPA H/W. As such, migrating this logic to IPAHAL (H/W abstraction layer) of IPA driver and adapt the core driver code to use it. New internal S/W API is added to access IPAHAL for Filtering and Routing rules and tables building and clearing. CRs-Fixed: 1006485 Change-Id: I23a95be86412987f72287138817235d3f1f9bc61 Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
2016-06-20base: sync: Increase char buffer size to get accurate fence nameDivya Ponnusamy
Increase the char buffer size for the sync fence name from 32 to 64. This makes it possible for drivers to use a longer, more descriptive name for sync_fence, which improves the readability of the sync dump in debugfs. Change-Id: I8a54ec1c7b95764fe3a39f00ce392fddcfd261f1 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
2016-06-20msm: camera: Changes to support MIPI C-Phy modeViswanadha Raju Thotakura
Changes to support MIPI Cphy mode on CSID version 5.0. CRs-Fixed: 1030317 Change-Id: I6e0835811a47820714eddcf851ea15ece729c2bb Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
2016-06-20clk: msm: clock: Add support for programming MDP_LUT_CBCR registerDeepak Katragadda
Add support for the mdss_mdp_lut_clk clock on MSMCOBALT. In addition, remove toggling the memory retention bits for the mdp core clock during gdsc_enable/disable. The display driver will use the set_flags API to set the core clock memory retention. CRs-Fixed: 1025605 Change-Id: If812473a67a7900c8f7b8b97f32fbf003f0e80a4 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-06-20msm: mdss: dsi: configure data lane swap for newer hw revisionsAravind Venkateswaran
Starting with DSI PHY hardware revisions 3.0 and above, data lane swap configurations need to be programmed via the DSI PHY interface. In other cases, a new register interface has been introduced to program the lane swap configuration for DSI controller revision 2.0 and above. Refactor the existing implementation to account for these hardware changes. Change-Id: I3772c614bfee0ed13f30a38535bb814158d23226 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
2016-06-20coresight-tmc: allocate memory for register and buffer dumpShashank Mittal
Add code to allocate memory for dumping TMC register and buffer data. These memory locations can be used to store TMC registers and buffer information after a crash. Change-Id: I8e98178110efa8e455a329e358c471757e87f2d1 Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
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