Age | Commit message (Expand) | Author |
---|---|---|
2007-07-24 | Blackfin arch: setup aliases for some core Core A MMRs | Mike Frysinger |
2007-07-12 | Blackfin arch: clean up some coding style issues | Bryan Wu |
2007-07-12 | Blackfin arch: Add Support for Peripheral PortMux and resouce allocation | Michael Hennerich |
2007-06-21 | Blackfin arch: add missing implementations SIC_IWR crosses several registers | Michael Hennerich |
2007-07-12 | Blackfin arch: initial supporting for BF548-EZKIT | Roy Huang |
2007-06-21 | Blackfin arch: add missing braces around array bfin serial init | Mike Frysinger |
2007-05-21 | Blackfin arch: update blackfin header files to latest one in VDSP. | Bryan Wu |
2007-05-21 | Blackfin arch: Move write to VR_CTL closer to IDLE | Michael Hennerich |
2007-05-07 | blackfin architecture | Bryan Wu |