From ca84bcaf9cedb83f9f5b67bb0023790a6e865d3a Mon Sep 17 00:00:00 2001
From: Abhijit Kulkarni <kabhijit@codeaurora.org>
Date: Tue, 29 Sep 2015 10:16:51 -0700
Subject: drm/msm/sde: add driver for sde support

Initial DRM/KMS driver to support snapdragon display engine.

Change-Id: I2f93d7cd24acf77359682f90b6b9647017ed62ba
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt        | 55 ++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/msm/sde.txt

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
new file mode 100644
index 000000000000..8ec9f78346d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -0,0 +1,55 @@
+Qualcomm Technologies, Inc. SDE KMS
+
+Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user
+interface to different panel interfaces. SDE driver is the core of
+display subsystem which manage all data paths to different panel interfaces.
+
+Required properties
+- compatible: Must be "qcom,sde-kms"
+- reg: Offset and length of the register set for the device.
+- reg-names : Names to refer to register sets related to this device
+- clocks: List of Phandles for clock device nodes
+    needed by the device.
+- clock-names: List of clock names needed by the device.
+- mmagic-supply: Phandle for mmagic mdss supply regulator device node.
+- vdd-supply: Phandle for vdd regulator device node.
+- interrupt-parent: Must be core interrupt controller.
+- interrupts: Interrupt associated with MDSS.
+- interrupt-controller: Mark the device node as an interrupt controller.
+- #interrupt-cells: Should be one. The first cell is interrupt number.
+- iommus: Specifies the SID's used by this context bank.
+
+Please refer to ../../interrupt-controller/interrupts.txt for a general
+description of interrupt bindings.
+
+Example:
+  mdss_mdp: qcom,mdss_mdp@900000 {
+    compatible = "qcom,sde-kms";
+    reg = <0x00900000 0x90000>,
+          <0x009b0000 0x1040>,
+          <0x009b8000 0x1040>;
+    reg-names = "mdp_phys",
+      "vbif_phys",
+      "vbif_nrt_phys";
+    clocks = <&clock_mmss clk_mdss_ahb_clk>,
+      <&clock_mmss clk_mdss_axi_clk>,
+      <&clock_mmss clk_mdp_clk_src>,
+      <&clock_mmss clk_mdss_mdp_vote_clk>,
+      <&clock_mmss clk_smmu_mdp_axi_clk>,
+      <&clock_mmss clk_mmagic_mdss_axi_clk>,
+      <&clock_mmss clk_mdss_vsync_clk>;
+    clock-names = "iface_clk",
+      "bus_clk",
+      "core_clk_src",
+      "core_clk",
+      "iommu_clk",
+      "mmagic_clk",
+      "vsync_clk";
+    mmagic-supply = <&gdsc_mmagic_mdss>;
+    vdd-supply = <&gdsc_mdss>;
+    interrupt-parent = <&intc>;
+    interrupts = <0 83 0>;
+    interrupt-controller;
+    #interrupt-cells = <1>;
+    iommus = <&mdp_smmu 0>;
+  };
-- 
cgit v1.2.3


From 989b6c672e98c8c9c217bcc88ac291f7c6c7f2b0 Mon Sep 17 00:00:00 2001
From: Ajay Singh Parmar <aparmar@codeaurora.org>
Date: Wed, 22 Jun 2016 17:31:21 -0700
Subject: drm/msm/dsi-staging: add dsi controller driver

Add dsi controller driver. Initialize and implement hw modules,
memory map, interrupt handling, check and set states, dsi message
send and receive, low power mode and driver initialization.

Change-Id: I9905e775ed73ba8dc8b57c717d32c4383b51d361
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
---
 .../devicetree/bindings/drm/msm/sde-dsi.txt        |   63 +
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c         | 2170 ++++++++++++++++++++
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h         |  471 +++++
 3 files changed, 2704 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
new file mode 100644
index 000000000000..e435df862d26
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
@@ -0,0 +1,63 @@
+Qualcomm Technologies, Inc.
+
+mdss-dsi is the master DSI device which supports multiple DSI host controllers
+that are compatible with MIPI display serial interface specification.
+
+DSI Controller:
+Required properties:
+- compatible:           Should be "qcom,dsi-ctrl-hw-v<version>". Supported
+			versions include 1.4 and 2.0.
+			eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0
+- reg:                  Base address and length of DSI controller's memory
+			mapped regions.
+- reg-names:            A list of strings that name the list of regs.
+			"dsi_ctrl" - DSI controller memory region.
+			"mmss_misc" - MMSS misc memory region.
+- cell-index:           Specifies the controller instance.
+- clocks:               Clocks required for DSI controller operation.
+- clock-names:          Names of the clocks corresponding to handles. Following
+			clocks are required:
+			"mdp_core_clk"
+			"iface_clk"
+			"core_mmss_clk"
+			"bus_clk"
+			"byte_clk"
+			"pixel_clk"
+			"core_clk"
+			"byte_clk_rcg"
+			"pixel_clk_rcg"
+- gdsc-supply:		phandle to gdsc regulator node.
+- vdda-supply:		phandle to vdda regulator node.
+- vcca-supply:		phandle to vcca regulator node.
+- interrupt-parent	phandle to the interrupt parent device node.
+- interrupts:		The interrupt signal from the DSI block.
+
+Bus Scaling Data:
+- qcom,msm-bus,name:		String property describing MDSS client.
+- qcom,msm-bus,num-cases:	This is the number of bus scaling use cases
+				defined in the vectors property. This must be
+				set to <2> for MDSS DSI driver where use-case 0
+				is used to remove BW votes from the system. Use
+				case 1 is used to generate bandwidth requestes
+				when sending command packets.
+- qcom,msm-bus,num-paths:	This represents number of paths in each bus
+				scaling usecase. This value depends on number of
+				AXI master ports dedicated to MDSS for
+				particular chipset.
+- qcom,msm-bus,vectors-KBps:	A series of 4 cell properties, with a format
+				of (src, dst, ab, ib) which is defined at
+				Documentation/devicetree/bindings/arm/msm/msm_bus.txt.
+				DSI driver should always set average bandwidth
+				(ab) to 0 and always use instantaneous
+				bandwidth(ib) values.
+
+Optional properties:
+- label:                  String to describe controller.
+- qcom,platform-te-gpio:  Specifies the gpio used for TE.
+- qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the
+					a particular "type" of DSI module. The module "types"
+					can be "core", "ctrl", and "phy". Within the same type,
+					there can be more than one instance of this binding,
+					in which case the entry would be appended with the
+					supply entry index.
+
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
new file mode 100644
index 000000000000..a282fce38354
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -0,0 +1,2170 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"dsi-ctrl:[%s] " fmt, __func__
+
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#include <linux/msm-bus.h>
+#include <linux/of_irq.h>
+#include <video/mipi_display.h>
+
+#include "msm_drv.h"
+#include "msm_kms.h"
+#include "msm_gpu.h"
+#include "dsi_ctrl.h"
+#include "dsi_ctrl_hw.h"
+#include "dsi_clk_pwr.h"
+#include "dsi_catalog.h"
+
+#define DSI_CTRL_DEFAULT_LABEL "MDSS DSI CTRL"
+
+#define DSI_CTRL_TX_TO_MS     200
+
+/**
+ * enum dsi_ctrl_driver_ops - controller driver ops
+ */
+enum dsi_ctrl_driver_ops {
+	DSI_CTRL_OP_POWER_STATE_CHANGE,
+	DSI_CTRL_OP_CMD_ENGINE,
+	DSI_CTRL_OP_VID_ENGINE,
+	DSI_CTRL_OP_HOST_ENGINE,
+	DSI_CTRL_OP_CMD_TX,
+	DSI_CTRL_OP_ULPS_TOGGLE,
+	DSI_CTRL_OP_CLAMP_TOGGLE,
+	DSI_CTRL_OP_SET_CLK_SOURCE,
+	DSI_CTRL_OP_HOST_INIT,
+	DSI_CTRL_OP_TPG,
+	DSI_CTRL_OP_PHY_SW_RESET,
+	DSI_CTRL_OP_MAX
+};
+
+struct dsi_ctrl_list_item {
+	struct dsi_ctrl *ctrl;
+	struct list_head list;
+};
+
+static LIST_HEAD(dsi_ctrl_list);
+static DEFINE_MUTEX(dsi_ctrl_list_lock);
+
+static const enum dsi_ctrl_version dsi_ctrl_v1_4 = DSI_CTRL_VERSION_1_4;
+static const enum dsi_ctrl_version dsi_ctrl_v2_0 = DSI_CTRL_VERSION_2_0;
+
+static const struct of_device_id msm_dsi_of_match[] = {
+	{
+		.compatible = "qcom,dsi-ctrl-hw-v1.4",
+		.data = &dsi_ctrl_v1_4,
+	},
+	{
+		.compatible = "qcom,dsi-ctrl-hw-v2.0",
+		.data = &dsi_ctrl_v2_0,
+	},
+	{}
+};
+
+static int dsi_ctrl_check_state(struct dsi_ctrl *dsi_ctrl,
+				enum dsi_ctrl_driver_ops op,
+				u32 op_state)
+{
+	int rc = 0;
+	struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
+
+	switch (op) {
+	case DSI_CTRL_OP_POWER_STATE_CHANGE:
+		if (state->power_state == op_state) {
+			pr_debug("[%d] No change in state, pwr_state=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if (state->power_state == DSI_CTRL_POWER_LINK_CLK_ON) {
+			if ((state->cmd_engine_state == DSI_CTRL_ENGINE_ON) ||
+			    (state->vid_engine_state == DSI_CTRL_ENGINE_ON) ||
+			    (state->controller_state == DSI_CTRL_ENGINE_ON)) {
+				pr_debug("[%d]State error: op=%d: %d, %d, %d\n",
+				       dsi_ctrl->index,
+				       op_state,
+				       state->cmd_engine_state,
+				       state->vid_engine_state,
+				       state->controller_state);
+				rc = -EINVAL;
+			}
+		}
+		break;
+	case DSI_CTRL_OP_CMD_ENGINE:
+		if (state->cmd_engine_state == op_state) {
+			pr_debug("[%d] No change in state, cmd_state=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_VID_ENGINE:
+		if (state->vid_engine_state == op_state) {
+			pr_debug("[%d] No change in state, cmd_state=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_HOST_ENGINE:
+		if (state->controller_state == op_state) {
+			pr_debug("[%d] No change in state, ctrl_state=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if (state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) {
+			pr_debug("[%d]State error (link is off): op=%d:, %d\n",
+			       dsi_ctrl->index,
+			       op_state,
+			       state->power_state);
+			rc = -EINVAL;
+		} else if ((op_state == DSI_CTRL_ENGINE_OFF) &&
+			   ((state->cmd_engine_state != DSI_CTRL_ENGINE_OFF) ||
+			    (state->vid_engine_state != DSI_CTRL_ENGINE_OFF))) {
+			pr_debug("[%d]State error (eng on): op=%d: %d, %d\n",
+				  dsi_ctrl->index,
+				  op_state,
+				  state->cmd_engine_state,
+				  state->vid_engine_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_CMD_TX:
+		if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+		    (state->host_initialized != true) ||
+		    (state->cmd_engine_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->host_initialized,
+			       state->cmd_engine_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_HOST_INIT:
+		if (state->host_initialized == op_state) {
+			pr_debug("[%d] No change in state, host_init=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if (state->power_state != DSI_CTRL_POWER_CORE_CLK_ON) {
+			pr_debug("[%d]State error: op=%d: %d\n",
+			       dsi_ctrl->index, op, state->power_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_ULPS_TOGGLE:
+		if (state->ulps_enabled == op_state) {
+			pr_debug("[%d] No change in state, ulps_enabled=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_CLAMP_TOGGLE:
+		if (state->clamp_enabled == op_state) {
+			pr_debug("[%d] No change in state, clamp_enabled=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_SET_CLK_SOURCE:
+		if (state->power_state == DSI_CTRL_POWER_LINK_CLK_ON) {
+			pr_debug("[%d] State error: op=%d: %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_TPG:
+		if (state->tpg_enabled == op_state) {
+			pr_debug("[%d] No change in state, tpg_enabled=%d\n",
+			       dsi_ctrl->index, op_state);
+			rc = -EINVAL;
+		} else if ((state->power_state != DSI_CTRL_POWER_LINK_CLK_ON) ||
+			   (state->controller_state != DSI_CTRL_ENGINE_ON)) {
+			pr_debug("[%d]State error: op=%d: %d, %d\n",
+			       dsi_ctrl->index,
+			       op,
+			       state->power_state,
+			       state->controller_state);
+			rc = -EINVAL;
+		}
+		break;
+	case DSI_CTRL_OP_PHY_SW_RESET:
+		if (state->power_state != DSI_CTRL_POWER_CORE_CLK_ON) {
+			pr_debug("[%d]State error: op=%d: %d\n",
+			       dsi_ctrl->index, op, state->power_state);
+			rc = -EINVAL;
+		}
+		break;
+	default:
+		rc = -ENOTSUPP;
+		break;
+	}
+
+	return rc;
+}
+
+static void dsi_ctrl_update_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_ctrl_driver_ops op,
+				  u32 op_state)
+{
+	struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
+
+	switch (op) {
+	case DSI_CTRL_OP_POWER_STATE_CHANGE:
+		state->power_state = op_state;
+		if (op_state == DSI_CTRL_POWER_OFF) {
+			state->pwr_enabled = false;
+			state->core_clk_enabled = false;
+			state->link_clk_enabled = false;
+		} else if (op_state == DSI_CTRL_POWER_VREG_ON) {
+			state->pwr_enabled = true;
+			state->core_clk_enabled = false;
+			state->link_clk_enabled = false;
+		} else if (op_state == DSI_CTRL_POWER_CORE_CLK_ON) {
+			state->pwr_enabled = true;
+			state->core_clk_enabled = true;
+			state->link_clk_enabled = false;
+		} else if (op_state == DSI_CTRL_POWER_LINK_CLK_ON) {
+			state->pwr_enabled = true;
+			state->core_clk_enabled = true;
+			state->link_clk_enabled = true;
+		}
+		break;
+	case DSI_CTRL_OP_CMD_ENGINE:
+		state->cmd_engine_state = op_state;
+		break;
+	case DSI_CTRL_OP_VID_ENGINE:
+		state->vid_engine_state = op_state;
+		break;
+	case DSI_CTRL_OP_HOST_ENGINE:
+		state->controller_state = op_state;
+		break;
+	case DSI_CTRL_OP_ULPS_TOGGLE:
+		state->ulps_enabled = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_CLAMP_TOGGLE:
+		state->clamp_enabled = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_SET_CLK_SOURCE:
+		state->clk_source_set = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_HOST_INIT:
+		state->host_initialized = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_TPG:
+		state->tpg_enabled = (op_state == 1) ? true : false;
+		break;
+	case DSI_CTRL_OP_CMD_TX:
+	case DSI_CTRL_OP_PHY_SW_RESET:
+	default:
+		break;
+	}
+}
+
+static int dsi_ctrl_init_regmap(struct platform_device *pdev,
+				struct dsi_ctrl *ctrl)
+{
+	int rc = 0;
+	void __iomem *ptr;
+
+	ptr = msm_ioremap(pdev, "dsi_ctrl", ctrl->name);
+	if (IS_ERR(ptr)) {
+		rc = PTR_ERR(ptr);
+		return rc;
+	}
+
+	ctrl->hw.base = ptr;
+	pr_debug("[%s] map dsi_ctrl registers to %p\n", ctrl->name,
+		 ctrl->hw.base);
+
+	ptr = msm_ioremap(pdev, "mmss_misc", ctrl->name);
+	if (IS_ERR(ptr)) {
+		rc = PTR_ERR(ptr);
+		return rc;
+	}
+
+	ctrl->hw.mmss_misc_base = ptr;
+	pr_debug("[%s] map mmss_misc registers to %p\n", ctrl->name,
+		 ctrl->hw.mmss_misc_base);
+	return rc;
+}
+
+static irqreturn_t dsi_ctrl_isr(int irq, void *ptr)
+{
+	struct dsi_ctrl *dsi_ctrl = ptr;
+	u32 interrupt_status = 0;
+	u64 error_status = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dsi_ctrl->int_info.intr_lock, flags);
+	interrupt_status = dsi_ctrl->hw.ops.get_interrupt_status(&dsi_ctrl->hw);
+	error_status = dsi_ctrl->hw.ops.get_error_status(&dsi_ctrl->hw);
+
+	dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw,
+						interrupt_status);
+	dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw, error_status);
+
+	dsi_ctrl->int_info.interrupt_status = interrupt_status;
+	dsi_ctrl->int_info.error_status = error_status;
+
+	spin_unlock_irqrestore(&dsi_ctrl->int_info.intr_lock, flags);
+
+	if (interrupt_status & DSI_CMD_MODE_DMA_DONE)
+		complete(&dsi_ctrl->int_info.cmd_dma_done);
+
+	if (interrupt_status & DSI_VIDEO_MODE_FRAME_DONE)
+		complete(&dsi_ctrl->int_info.vid_frame_done);
+
+	if (interrupt_status & DSI_CMD_FRAME_DONE)
+		complete(&dsi_ctrl->int_info.cmd_frame_done);
+
+	return IRQ_HANDLED;
+}
+
+static int dsi_ctrl_clocks_deinit(struct dsi_ctrl *ctrl)
+{
+	struct dsi_core_clk_info *core = &ctrl->clk_info.core_clks;
+	struct dsi_link_clk_info *link = &ctrl->clk_info.link_clks;
+	struct dsi_clk_link_set *rcg = &ctrl->clk_info.rcg_clks;
+
+	if (core->mdp_core_clk)
+		devm_clk_put(&ctrl->pdev->dev, core->mdp_core_clk);
+	if (core->iface_clk)
+		devm_clk_put(&ctrl->pdev->dev, core->iface_clk);
+	if (core->core_mmss_clk)
+		devm_clk_put(&ctrl->pdev->dev, core->core_mmss_clk);
+	if (core->bus_clk)
+		devm_clk_put(&ctrl->pdev->dev, core->bus_clk);
+
+	memset(core, 0x0, sizeof(*core));
+
+	if (link->byte_clk)
+		devm_clk_put(&ctrl->pdev->dev, link->byte_clk);
+	if (link->pixel_clk)
+		devm_clk_put(&ctrl->pdev->dev, link->pixel_clk);
+	if (link->esc_clk)
+		devm_clk_put(&ctrl->pdev->dev, link->esc_clk);
+
+	memset(link, 0x0, sizeof(*link));
+
+	if (rcg->byte_clk)
+		devm_clk_put(&ctrl->pdev->dev, rcg->byte_clk);
+	if (rcg->pixel_clk)
+		devm_clk_put(&ctrl->pdev->dev, rcg->pixel_clk);
+
+	memset(rcg, 0x0, sizeof(*rcg));
+
+	return 0;
+}
+
+static int dsi_ctrl_clocks_init(struct platform_device *pdev,
+				struct dsi_ctrl *ctrl)
+{
+	int rc = 0;
+	struct dsi_core_clk_info *core = &ctrl->clk_info.core_clks;
+	struct dsi_link_clk_info *link = &ctrl->clk_info.link_clks;
+	struct dsi_clk_link_set *rcg = &ctrl->clk_info.rcg_clks;
+
+	core->mdp_core_clk = devm_clk_get(&pdev->dev, "mdp_core_clk");
+	if (IS_ERR(core->mdp_core_clk)) {
+		rc = PTR_ERR(core->mdp_core_clk);
+		pr_err("failed to get mdp_core_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->iface_clk = devm_clk_get(&pdev->dev, "iface_clk");
+	if (IS_ERR(core->iface_clk)) {
+		rc = PTR_ERR(core->iface_clk);
+		pr_err("failed to get iface_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->core_mmss_clk = devm_clk_get(&pdev->dev, "core_mmss_clk");
+	if (IS_ERR(core->core_mmss_clk)) {
+		rc = PTR_ERR(core->core_mmss_clk);
+		pr_err("failed to get core_mmss_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
+	if (IS_ERR(core->bus_clk)) {
+		rc = PTR_ERR(core->bus_clk);
+		pr_err("failed to get bus_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	link->byte_clk = devm_clk_get(&pdev->dev, "byte_clk");
+	if (IS_ERR(link->byte_clk)) {
+		rc = PTR_ERR(link->byte_clk);
+		pr_err("failed to get byte_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	link->pixel_clk = devm_clk_get(&pdev->dev, "pixel_clk");
+	if (IS_ERR(link->pixel_clk)) {
+		rc = PTR_ERR(link->pixel_clk);
+		pr_err("failed to get pixel_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	link->esc_clk = devm_clk_get(&pdev->dev, "core_clk");
+	if (IS_ERR(link->esc_clk)) {
+		rc = PTR_ERR(link->esc_clk);
+		pr_err("failed to get esc_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	rcg->byte_clk = devm_clk_get(&pdev->dev, "byte_clk_rcg");
+	if (IS_ERR(rcg->byte_clk)) {
+		rc = PTR_ERR(rcg->byte_clk);
+		pr_err("failed to get byte_clk_rcg, rc=%d\n", rc);
+		goto fail;
+	}
+
+	rcg->pixel_clk = devm_clk_get(&pdev->dev, "pixel_clk_rcg");
+	if (IS_ERR(rcg->pixel_clk)) {
+		rc = PTR_ERR(rcg->pixel_clk);
+		pr_err("failed to get pixel_clk_rcg, rc=%d\n", rc);
+		goto fail;
+	}
+
+	return 0;
+fail:
+	dsi_ctrl_clocks_deinit(ctrl);
+	return rc;
+}
+
+static int dsi_ctrl_supplies_deinit(struct dsi_ctrl *ctrl)
+{
+	int i = 0;
+	int rc = 0;
+	struct dsi_regulator_info *regs;
+
+	regs = &ctrl->pwr_info.digital;
+	for (i = 0; i < regs->count; i++) {
+		if (!regs->vregs[i].vreg)
+			pr_err("vreg is NULL, should not reach here\n");
+		else
+			devm_regulator_put(regs->vregs[i].vreg);
+	}
+
+	regs = &ctrl->pwr_info.host_pwr;
+	for (i = 0; i < regs->count; i++) {
+		if (!regs->vregs[i].vreg)
+			pr_err("vreg is NULL, should not reach here\n");
+		else
+			devm_regulator_put(regs->vregs[i].vreg);
+	}
+
+	if (!ctrl->pwr_info.host_pwr.vregs) {
+		devm_kfree(&ctrl->pdev->dev, ctrl->pwr_info.host_pwr.vregs);
+		ctrl->pwr_info.host_pwr.vregs = NULL;
+		ctrl->pwr_info.host_pwr.count = 0;
+	}
+
+	if (!ctrl->pwr_info.digital.vregs) {
+		devm_kfree(&ctrl->pdev->dev, ctrl->pwr_info.digital.vregs);
+		ctrl->pwr_info.digital.vregs = NULL;
+		ctrl->pwr_info.digital.count = 0;
+	}
+
+	return rc;
+}
+
+static int dsi_ctrl_supplies_init(struct platform_device *pdev,
+				  struct dsi_ctrl *ctrl)
+{
+	int rc = 0;
+	int i = 0;
+	struct dsi_regulator_info *regs;
+	struct regulator *vreg = NULL;
+
+	rc = dsi_clk_pwr_get_dt_vreg_data(&pdev->dev,
+					  &ctrl->pwr_info.digital,
+					  "qcom,core-supply-entries");
+	if (rc) {
+		pr_err("failed to get digital supply, rc = %d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_clk_pwr_get_dt_vreg_data(&pdev->dev,
+					  &ctrl->pwr_info.host_pwr,
+					  "qcom,ctrl-supply-entries");
+	if (rc) {
+		pr_err("failed to get host power supplies, rc = %d\n", rc);
+		goto error_digital;
+	}
+
+	regs = &ctrl->pwr_info.digital;
+	for (i = 0; i < regs->count; i++) {
+		vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
+		if (IS_ERR(vreg)) {
+			pr_err("failed to get %s regulator\n",
+			       regs->vregs[i].vreg_name);
+			rc = PTR_ERR(vreg);
+			goto error_host_pwr;
+		}
+		regs->vregs[i].vreg = vreg;
+	}
+
+	regs = &ctrl->pwr_info.host_pwr;
+	for (i = 0; i < regs->count; i++) {
+		vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
+		if (IS_ERR(vreg)) {
+			pr_err("failed to get %s regulator\n",
+			       regs->vregs[i].vreg_name);
+			for (--i; i >= 0; i--)
+				devm_regulator_put(regs->vregs[i].vreg);
+			rc = PTR_ERR(vreg);
+			goto error_digital_put;
+		}
+		regs->vregs[i].vreg = vreg;
+	}
+
+	return rc;
+
+error_digital_put:
+	regs = &ctrl->pwr_info.digital;
+	for (i = 0; i < regs->count; i++)
+		devm_regulator_put(regs->vregs[i].vreg);
+error_host_pwr:
+	devm_kfree(&pdev->dev, ctrl->pwr_info.host_pwr.vregs);
+	ctrl->pwr_info.host_pwr.vregs = NULL;
+	ctrl->pwr_info.host_pwr.count = 0;
+error_digital:
+	devm_kfree(&pdev->dev, ctrl->pwr_info.digital.vregs);
+	ctrl->pwr_info.digital.vregs = NULL;
+	ctrl->pwr_info.digital.count = 0;
+error:
+	return rc;
+}
+
+static int dsi_ctrl_axi_bus_client_init(struct platform_device *pdev,
+					struct dsi_ctrl *ctrl)
+{
+	int rc = 0;
+	struct dsi_ctrl_bus_scale_info *bus = &ctrl->axi_bus_info;
+
+	bus->bus_scale_table = msm_bus_cl_get_pdata(pdev);
+	if (IS_ERR_OR_NULL(bus->bus_scale_table)) {
+		rc = PTR_ERR(bus->bus_scale_table);
+		pr_err("msm_bus_cl_get_pdata() failed, rc = %d\n", rc);
+		bus->bus_scale_table = NULL;
+		return rc;
+	}
+
+	bus->bus_handle = msm_bus_scale_register_client(bus->bus_scale_table);
+	if (!bus->bus_handle) {
+		rc = -EINVAL;
+		pr_err("failed to register axi bus client\n");
+	}
+
+	return rc;
+}
+
+static int dsi_ctrl_axi_bus_client_deinit(struct dsi_ctrl *ctrl)
+{
+	struct dsi_ctrl_bus_scale_info *bus = &ctrl->axi_bus_info;
+
+	if (bus->bus_handle) {
+		msm_bus_scale_unregister_client(bus->bus_handle);
+
+		bus->bus_handle = 0;
+	}
+
+	return 0;
+}
+
+static int dsi_ctrl_validate_panel_info(struct dsi_ctrl *dsi_ctrl,
+					struct dsi_host_config *config)
+{
+	int rc = 0;
+	struct dsi_host_common_cfg *host_cfg = &config->common_config;
+
+	if (config->panel_mode >= DSI_OP_MODE_MAX) {
+		pr_err("Invalid dsi operation mode (%d)\n", config->panel_mode);
+		rc = -EINVAL;
+		goto err;
+	}
+
+	if ((host_cfg->data_lanes & (DSI_CLOCK_LANE - 1)) == 0) {
+		pr_err("No data lanes are enabled\n");
+		rc = -EINVAL;
+		goto err;
+	}
+err:
+	return rc;
+}
+
+static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
+				      struct dsi_host_config *config)
+{
+	int rc = 0;
+	u32 num_of_lanes = 0;
+	u32 bpp = 3;
+	u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,
+	    byte_clk_rate;
+	struct dsi_host_common_cfg *host_cfg = &config->common_config;
+	struct dsi_mode_info *timing = &config->video_timing;
+
+	if (host_cfg->data_lanes & DSI_DATA_LANE_0)
+		num_of_lanes++;
+	if (host_cfg->data_lanes & DSI_DATA_LANE_1)
+		num_of_lanes++;
+	if (host_cfg->data_lanes & DSI_DATA_LANE_2)
+		num_of_lanes++;
+	if (host_cfg->data_lanes & DSI_DATA_LANE_3)
+		num_of_lanes++;
+
+	h_period = DSI_H_TOTAL(timing);
+	v_period = DSI_V_TOTAL(timing);
+
+	bit_rate = h_period * v_period * timing->refresh_rate * bpp * 8;
+	bit_rate_per_lane = bit_rate;
+	do_div(bit_rate_per_lane, num_of_lanes);
+	pclk_rate = bit_rate;
+	do_div(pclk_rate, (8 * bpp));
+	byte_clk_rate = bit_rate_per_lane;
+	do_div(byte_clk_rate, 8);
+	pr_debug("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
+		 bit_rate, bit_rate_per_lane);
+	pr_debug("byte_clk_rate = %llu, pclk_rate = %llu\n",
+		  byte_clk_rate, pclk_rate);
+
+	rc = dsi_clk_set_link_frequencies(&dsi_ctrl->clk_info.link_clks,
+					  pclk_rate,
+					  byte_clk_rate,
+					  config->esc_clk_rate_hz);
+	if (rc)
+		pr_err("Failed to update link frequencies\n");
+
+	return rc;
+}
+
+static int dsi_ctrl_enable_supplies(struct dsi_ctrl *dsi_ctrl, bool enable)
+{
+	int rc = 0;
+
+	if (enable) {
+		rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.host_pwr,
+					      true);
+		if (rc) {
+			pr_err("failed to enable host power regs, rc=%d\n", rc);
+			goto error;
+		}
+
+		rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.digital,
+					      true);
+		if (rc) {
+			pr_err("failed to enable gdsc, rc=%d\n", rc);
+			(void)dsi_pwr_enable_regulator(
+						&dsi_ctrl->pwr_info.host_pwr,
+						false
+						);
+			goto error;
+		}
+	} else {
+		rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.digital,
+					      false);
+		if (rc) {
+			pr_err("failed to disable gdsc, rc=%d\n", rc);
+			goto error;
+		}
+
+		rc = dsi_pwr_enable_regulator(&dsi_ctrl->pwr_info.host_pwr,
+					      false);
+		if (rc) {
+			pr_err("failed to disable host power regs, rc=%d\n",
+			       rc);
+			goto error;
+		}
+	}
+error:
+	return rc;
+}
+
+static int dsi_ctrl_vote_for_bandwidth(struct dsi_ctrl *dsi_ctrl, bool on)
+{
+	int rc = 0;
+	bool changed = false;
+	struct dsi_ctrl_bus_scale_info *axi_bus = &dsi_ctrl->axi_bus_info;
+
+	if (on) {
+		if (axi_bus->refcount == 0)
+			changed = true;
+
+		axi_bus->refcount++;
+	} else {
+		if (axi_bus->refcount != 0) {
+			axi_bus->refcount--;
+
+			if (axi_bus->refcount == 0)
+				changed = true;
+		} else {
+			pr_err("bus bw votes are not balanced\n");
+		}
+	}
+
+	if (changed) {
+		rc = msm_bus_scale_client_update_request(axi_bus->bus_handle,
+							 on ? 1 : 0);
+		if (rc)
+			pr_err("bus scale client update failed, rc=%d\n", rc);
+	}
+
+	return rc;
+}
+
+static int dsi_ctrl_copy_and_pad_cmd(struct dsi_ctrl *dsi_ctrl,
+				     const struct mipi_dsi_packet *packet,
+				     u8 **buffer,
+				     u32 *size)
+{
+	int rc = 0;
+	u8 *buf = NULL;
+	u32 len, i;
+
+	len = packet->size;
+	len += 0x3; len &= ~0x03; /* Align to 32 bits */
+
+	buf = devm_kzalloc(&dsi_ctrl->pdev->dev, len * sizeof(u8), GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	for (i = 0; i < len; i++) {
+		if (i >= packet->size)
+			buf[i] = 0xFF;
+		else if (i < sizeof(packet->header))
+			buf[i] = packet->header[i];
+		else
+			buf[i] = packet->payload[i - sizeof(packet->header)];
+	}
+
+	if (packet->payload_length > 0)
+		buf[3] |= BIT(6);
+
+	buf[3] |= BIT(7);
+	*buffer = buf;
+	*size = len;
+
+	return rc;
+}
+
+static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl,
+			  const struct mipi_dsi_msg *msg,
+			  u32 flags)
+{
+	int rc = 0;
+	struct mipi_dsi_packet packet;
+	struct dsi_ctrl_cmd_dma_fifo_info cmd;
+	u32 hw_flags = 0;
+	u32 length = 0;
+	u8 *buffer = NULL;
+
+	if (!(flags & DSI_CTRL_CMD_FIFO_STORE)) {
+		pr_err("Memory DMA is not supported, use FIFO\n");
+		goto error;
+	}
+
+	rc = mipi_dsi_create_packet(&packet, msg);
+	if (rc) {
+		pr_err("Failed to create message packet, rc=%d\n", rc);
+		goto error;
+	}
+
+	if (flags & DSI_CTRL_CMD_FIFO_STORE) {
+		rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl,
+					       &packet,
+					       &buffer,
+					       &length);
+		if (rc) {
+			pr_err("[%s] failed to copy message, rc=%d\n",
+			       dsi_ctrl->name, rc);
+			goto error;
+		}
+		cmd.command =  (u32 *)buffer;
+		cmd.size = length;
+		cmd.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ?
+				     true : false;
+		cmd.is_master = (flags & DSI_CTRL_CMD_BROADCAST_MASTER) ?
+				  true : false;
+		cmd.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
+				  true : false;
+	}
+
+	hw_flags |= (flags & DSI_CTRL_CMD_DEFER_TRIGGER) ?
+			DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER : 0;
+
+	if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER))
+		reinit_completion(&dsi_ctrl->int_info.cmd_dma_done);
+
+	if (flags & DSI_CTRL_CMD_FIFO_STORE)
+		dsi_ctrl->hw.ops.kickoff_fifo_command(&dsi_ctrl->hw,
+						      &cmd,
+						      hw_flags);
+
+	if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER)) {
+		u32 retry = 10;
+		u32 status = 0;
+		u64 error = 0;
+		u32 mask = (DSI_CMD_MODE_DMA_DONE);
+
+		while ((status == 0) && (retry > 0)) {
+			udelay(1000);
+			status = dsi_ctrl->hw.ops.get_interrupt_status(
+								&dsi_ctrl->hw);
+			error = dsi_ctrl->hw.ops.get_error_status(
+								&dsi_ctrl->hw);
+			status &= mask;
+			retry--;
+			dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw,
+								status);
+			dsi_ctrl->hw.ops.clear_error_status(&dsi_ctrl->hw,
+							    error);
+		}
+		pr_debug("INT STATUS = %x, retry = %d\n", status, retry);
+		if (retry == 0)
+			pr_err("[DSI_%d]Command transfer failed\n",
+			       dsi_ctrl->index);
+
+		dsi_ctrl->hw.ops.reset_cmd_fifo(&dsi_ctrl->hw);
+		rc = wait_for_completion_timeout(
+			&dsi_ctrl->int_info.cmd_dma_done,
+			msecs_to_jiffies(DSI_CTRL_TX_TO_MS));
+		if (rc == 0) {
+			pr_err("[%s] timedout waiting for cmd tx\n",
+				dsi_ctrl->name);
+			rc = -ETIMEDOUT;
+			goto error;
+		} else {
+			rc = 0;
+		}
+	}
+error:
+	if (buffer)
+		devm_kfree(&dsi_ctrl->pdev->dev, buffer);
+	return rc;
+}
+
+static int dsi_set_max_return_size(struct dsi_ctrl *dsi_ctrl,
+				   const struct mipi_dsi_msg *rx_msg,
+				   u32 size)
+{
+	int rc = 0;
+	u8 tx[2] = { (u8)(size & 0xFF), (u8)(size >> 8) };
+	struct mipi_dsi_msg msg = {
+		.channel = rx_msg->channel,
+		.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
+		.tx_len = 2,
+		.tx_buf = tx,
+	};
+
+	rc = dsi_message_tx(dsi_ctrl, &msg, 0x0);
+	if (rc)
+		pr_err("failed to send max return size packet, rc=%d\n", rc);
+
+	return rc;
+}
+
+static int dsi_message_rx(struct dsi_ctrl *dsi_ctrl,
+			  const struct mipi_dsi_msg *msg,
+			  u32 flags)
+{
+	int rc = 0;
+	u32 rd_pkt_size;
+	u32 total_read_len;
+	u32 bytes_read = 0, tot_bytes_read = 0;
+	u32 current_read_len;
+	bool short_resp = false;
+	bool read_done = false;
+
+	if (msg->rx_len <= 2) {
+		short_resp = true;
+		rd_pkt_size = msg->rx_len;
+		total_read_len = 4;
+	} else {
+		short_resp = false;
+		current_read_len = 10;
+		if (msg->rx_len < current_read_len)
+			rd_pkt_size = msg->rx_len;
+		else
+			rd_pkt_size = current_read_len;
+
+		total_read_len = current_read_len + 6;
+	}
+
+	while (!read_done) {
+		rc = dsi_set_max_return_size(dsi_ctrl, msg, rd_pkt_size);
+		if (rc) {
+			pr_err("Failed to set max return packet size, rc=%d\n",
+			       rc);
+			goto error;
+		}
+
+		rc = dsi_message_tx(dsi_ctrl, msg, flags);
+		if (rc) {
+			pr_err("Message transmission failed, rc=%d\n", rc);
+			goto error;
+		}
+
+
+		tot_bytes_read += bytes_read;
+		if (short_resp)
+			read_done = true;
+		else if (msg->rx_len <= tot_bytes_read)
+			read_done = true;
+	}
+error:
+	return rc;
+}
+
+
+static int dsi_enable_ulps(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+	u32 lanes;
+	u32 ulps_lanes;
+
+	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)
+		lanes = dsi_ctrl->host_config.common_config.data_lanes;
+
+	lanes |= DSI_CLOCK_LANE;
+	dsi_ctrl->hw.ops.ulps_request(&dsi_ctrl->hw, lanes);
+
+	ulps_lanes = dsi_ctrl->hw.ops.get_lanes_in_ulps(&dsi_ctrl->hw);
+
+	if ((lanes & ulps_lanes) != lanes) {
+		pr_err("Failed to enter ULPS, request=0x%x, actual=0x%x\n",
+		       lanes, ulps_lanes);
+		rc = -EIO;
+	}
+
+	return rc;
+}
+
+static int dsi_disable_ulps(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+	u32 ulps_lanes, lanes = 0;
+
+	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)
+		lanes = dsi_ctrl->host_config.common_config.data_lanes;
+
+	lanes |= DSI_CLOCK_LANE;
+	ulps_lanes = dsi_ctrl->hw.ops.get_lanes_in_ulps(&dsi_ctrl->hw);
+
+	if ((lanes & ulps_lanes) != lanes)
+		pr_err("Mismatch between lanes in ULPS\n");
+
+	lanes &= ulps_lanes;
+
+	dsi_ctrl->hw.ops.ulps_exit(&dsi_ctrl->hw, lanes);
+
+	/* 1 ms delay is recommended by specification */
+	udelay(1000);
+
+	dsi_ctrl->hw.ops.clear_ulps_request(&dsi_ctrl->hw, lanes);
+
+	ulps_lanes = dsi_ctrl->hw.ops.get_lanes_in_ulps(&dsi_ctrl->hw);
+	if (ulps_lanes & lanes) {
+		pr_err("Lanes (0x%x) stuck in ULPS\n", ulps_lanes);
+		rc = -EIO;
+	}
+
+	return rc;
+}
+
+static int dsi_ctrl_drv_state_init(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+	bool splash_enabled = false;
+	struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
+
+	if (!splash_enabled) {
+		state->power_state = DSI_CTRL_POWER_OFF;
+		state->cmd_engine_state = DSI_CTRL_ENGINE_OFF;
+		state->vid_engine_state = DSI_CTRL_ENGINE_OFF;
+		state->pwr_enabled = false;
+		state->core_clk_enabled = false;
+		state->link_clk_enabled = false;
+		state->ulps_enabled = false;
+		state->clamp_enabled = false;
+		state->clk_source_set = false;
+	}
+
+	return rc;
+}
+
+static int dsi_ctrl_intr_deinit(struct dsi_ctrl *dsi_ctrl)
+{
+	struct dsi_ctrl_interrupts *ints = &dsi_ctrl->int_info;
+
+	devm_free_irq(&dsi_ctrl->pdev->dev, ints->irq, dsi_ctrl);
+
+	return 0;
+}
+
+static int dsi_ctrl_intr_init(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+	struct dsi_ctrl_interrupts *ints = &dsi_ctrl->int_info;
+
+	ints->irq = irq_of_parse_and_map(dsi_ctrl->pdev->dev.of_node, 0);
+	if ((int)ints->irq < 0) {
+		rc = -EINVAL;
+		pr_err("failed to parse and map irq, rc=%d\n", rc);
+		dsi_ctrl->int_info.irq = 0;
+		goto end;
+	}
+
+	spin_lock_init(&ints->intr_lock);
+
+	init_completion(&ints->cmd_dma_done);
+	init_completion(&ints->vid_frame_done);
+	init_completion(&ints->cmd_frame_done);
+
+	rc = devm_request_threaded_irq(&dsi_ctrl->pdev->dev,
+				       ints->irq,
+				       NULL,
+				       dsi_ctrl_isr,
+				       IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+				       dsi_ctrl->name,
+				       dsi_ctrl);
+	if (rc)
+		pr_err("IRQ request failed, rc=%d\n", rc);
+end:
+	return rc;
+}
+
+static int dsi_ctrl_buffer_deinit(struct dsi_ctrl *dsi_ctrl)
+{
+	if (dsi_ctrl->tx_cmd_buf) {
+		msm_gem_put_iova(dsi_ctrl->tx_cmd_buf, 0);
+
+		msm_gem_free_object(dsi_ctrl->tx_cmd_buf);
+		dsi_ctrl->tx_cmd_buf = NULL;
+	}
+
+	return 0;
+}
+
+int dsi_ctrl_buffer_init(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+	u32 iova = 0;
+
+	dsi_ctrl->tx_cmd_buf = msm_gem_new(dsi_ctrl->drm_dev,
+					   SZ_4K,
+					   MSM_BO_UNCACHED);
+
+	if (IS_ERR(dsi_ctrl->tx_cmd_buf)) {
+		rc = PTR_ERR(dsi_ctrl->tx_cmd_buf);
+		pr_err("failed to allocate gem, rc=%d\n", rc);
+		dsi_ctrl->tx_cmd_buf = NULL;
+		goto error;
+	}
+
+	dsi_ctrl->cmd_buffer_size = SZ_4K;
+
+	rc = msm_gem_get_iova(dsi_ctrl->tx_cmd_buf, 0, &iova);
+	if (rc) {
+		pr_err("failed to get iova, rc=%d\n", rc);
+		(void)dsi_ctrl_buffer_deinit(dsi_ctrl);
+		goto error;
+	}
+
+	if (iova & 0x07) {
+		pr_err("Tx command buffer is not 8 byte aligned\n");
+		rc = -ENOTSUPP;
+		(void)dsi_ctrl_buffer_deinit(dsi_ctrl);
+		goto error;
+	}
+error:
+	return rc;
+}
+
+static int dsi_enable_io_clamp(struct dsi_ctrl *dsi_ctrl, bool enable)
+{
+	bool en_ulps = dsi_ctrl->current_state.ulps_enabled;
+	u32 lanes = 0;
+
+	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)
+		lanes = dsi_ctrl->host_config.common_config.data_lanes;
+
+	lanes |= DSI_CLOCK_LANE;
+
+	if (enable)
+		dsi_ctrl->hw.ops.clamp_enable(&dsi_ctrl->hw, lanes, en_ulps);
+	else
+		dsi_ctrl->hw.ops.clamp_disable(&dsi_ctrl->hw, lanes, en_ulps);
+
+	return 0;
+}
+
+static int dsi_ctrl_dev_probe(struct platform_device *pdev)
+{
+	struct dsi_ctrl *dsi_ctrl;
+	struct dsi_ctrl_list_item *item;
+	const struct of_device_id *id;
+	enum dsi_ctrl_version version;
+	u32 index = 0;
+	int rc = 0;
+
+	id = of_match_node(msm_dsi_of_match, pdev->dev.of_node);
+	if (!id)
+		return -ENODEV;
+
+	version = *(enum dsi_ctrl_version *)id->data;
+
+	item = devm_kzalloc(&pdev->dev, sizeof(*item), GFP_KERNEL);
+	if (!item)
+		return -ENOMEM;
+
+	dsi_ctrl = devm_kzalloc(&pdev->dev, sizeof(*dsi_ctrl), GFP_KERNEL);
+	if (!dsi_ctrl)
+		return -ENOMEM;
+
+	rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &index);
+	if (rc) {
+		pr_debug("cell index not set, default to 0\n");
+		index = 0;
+	}
+
+	dsi_ctrl->index = index;
+
+	dsi_ctrl->name = of_get_property(pdev->dev.of_node, "label", NULL);
+	if (!dsi_ctrl->name)
+		dsi_ctrl->name = DSI_CTRL_DEFAULT_LABEL;
+
+	rc = dsi_ctrl_init_regmap(pdev, dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to parse register information, rc = %d\n", rc);
+		goto fail;
+	}
+
+	rc = dsi_ctrl_clocks_init(pdev, dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to parse clock information, rc = %d\n", rc);
+		goto fail;
+	}
+
+	rc = dsi_ctrl_supplies_init(pdev, dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to parse voltage supplies, rc = %d\n", rc);
+		goto fail_clks;
+	}
+
+	dsi_ctrl->version = version;
+	rc = dsi_catalog_ctrl_setup(&dsi_ctrl->hw, dsi_ctrl->version,
+				    dsi_ctrl->index);
+	if (rc) {
+		pr_err("Catalog does not support version (%d)\n",
+		       dsi_ctrl->version);
+		goto fail_supplies;
+	}
+
+	rc = dsi_ctrl_axi_bus_client_init(pdev, dsi_ctrl);
+	if (rc)
+		pr_err("failed to init axi bus client, rc = %d\n", rc);
+
+	item->ctrl = dsi_ctrl;
+
+	mutex_lock(&dsi_ctrl_list_lock);
+	list_add(&item->list, &dsi_ctrl_list);
+	mutex_unlock(&dsi_ctrl_list_lock);
+
+	mutex_init(&dsi_ctrl->ctrl_lock);
+
+	dsi_ctrl->pdev = pdev;
+	platform_set_drvdata(pdev, dsi_ctrl);
+
+	pr_debug("Probe successful for %s\n", dsi_ctrl->name);
+
+	return 0;
+
+fail_supplies:
+	(void)dsi_ctrl_supplies_deinit(dsi_ctrl);
+fail_clks:
+	(void)dsi_ctrl_clocks_deinit(dsi_ctrl);
+fail:
+	return rc;
+}
+
+static int dsi_ctrl_dev_remove(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct dsi_ctrl *dsi_ctrl;
+	struct list_head *pos, *tmp;
+
+	dsi_ctrl = platform_get_drvdata(pdev);
+
+	mutex_lock(&dsi_ctrl_list_lock);
+	list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
+		struct dsi_ctrl_list_item *n = list_entry(pos,
+						  struct dsi_ctrl_list_item,
+						  list);
+		if (n->ctrl == dsi_ctrl) {
+			list_del(&n->list);
+			break;
+		}
+	}
+	mutex_unlock(&dsi_ctrl_list_lock);
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	rc = dsi_ctrl_axi_bus_client_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("failed to deinitialize axi bus client, rc = %d\n", rc);
+
+	rc = dsi_ctrl_supplies_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("failed to deinitialize voltage supplies, rc=%d\n", rc);
+
+	rc = dsi_ctrl_clocks_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("failed to deinitialize clocks, rc=%d\n", rc);
+
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+
+	mutex_destroy(&dsi_ctrl->ctrl_lock);
+	devm_kfree(&pdev->dev, dsi_ctrl);
+
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+static struct platform_driver dsi_ctrl_driver = {
+	.probe = dsi_ctrl_dev_probe,
+	.remove = dsi_ctrl_dev_remove,
+	.driver = {
+		.name = "mdss_dsi_ctrl",
+		.of_match_table = msm_dsi_of_match,
+	},
+};
+
+/**
+ * dsi_ctrl_get() - get a dsi_ctrl handle from an of_node
+ * @of_node:    of_node of the DSI controller.
+ *
+ * Gets the DSI controller handle for the corresponding of_node. The ref count
+ * is incremented to one and all subsequent gets will fail until the original
+ * clients calls a put.
+ *
+ * Return: DSI Controller handle.
+ */
+struct dsi_ctrl *dsi_ctrl_get(struct device_node *of_node)
+{
+	struct list_head *pos, *tmp;
+	struct dsi_ctrl *ctrl = NULL;
+
+	mutex_lock(&dsi_ctrl_list_lock);
+	list_for_each_safe(pos, tmp, &dsi_ctrl_list) {
+		struct dsi_ctrl_list_item *n;
+
+		n = list_entry(pos, struct dsi_ctrl_list_item, list);
+		if (n->ctrl->pdev->dev.of_node == of_node) {
+			ctrl = n->ctrl;
+			break;
+		}
+	}
+	mutex_unlock(&dsi_ctrl_list_lock);
+
+	if (!ctrl) {
+		pr_err("Device with of node not found\n");
+		ctrl = ERR_PTR(-EPROBE_DEFER);
+		return ctrl;
+	}
+
+	mutex_lock(&ctrl->ctrl_lock);
+	if (ctrl->refcount == 1) {
+		pr_err("[%s] Device in use\n", ctrl->name);
+		ctrl = ERR_PTR(-EBUSY);
+	} else {
+		ctrl->refcount++;
+	}
+	mutex_unlock(&ctrl->ctrl_lock);
+	return ctrl;
+}
+
+/**
+ * dsi_ctrl_put() - releases a dsi controller handle.
+ * @dsi_ctrl:       DSI controller handle.
+ *
+ * Releases the DSI controller. Driver will clean up all resources and puts back
+ * the DSI controller into reset state.
+ */
+void dsi_ctrl_put(struct dsi_ctrl *dsi_ctrl)
+{
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	if (dsi_ctrl->refcount == 0)
+		pr_err("Unbalanced dsi_ctrl_put call\n");
+	else
+		dsi_ctrl->refcount--;
+
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+}
+
+/**
+ * dsi_ctrl_drv_init() - initialize dsi controller driver.
+ * @dsi_ctrl:      DSI controller handle.
+ *
+ * Initializes DSI controller driver. Driver should be initialized after
+ * dsi_ctrl_get() succeeds.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_drv_init(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	rc = dsi_ctrl_drv_state_init(dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to initialize driver state, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_ctrl_intr_init(dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to initialize interrupt deps, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_ctrl_buffer_init(dsi_ctrl);
+	if (rc) {
+		pr_err("Failed to initialize tx buffer, rc=%d\n", rc);
+		goto error;
+	}
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_drv_deinit() - de-initializes dsi controller driver
+ * @dsi_ctrl:      DSI controller handle.
+ *
+ * Releases all resources acquired by dsi_ctrl_drv_init().
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_drv_deinit(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	rc = dsi_ctrl_buffer_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("Failed to free cmd buffers, rc=%d\n", rc);
+
+	rc = dsi_ctrl_intr_deinit(dsi_ctrl);
+	if (rc)
+		pr_err("Failed to free interrupt deps, rc=%d\n", rc);
+
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_phy_sw_reset() - perform a PHY software reset
+ * @dsi_ctrl:         DSI controller handle.
+ *
+ * Performs a PHY software reset on the DSI controller. Reset should be done
+ * when the controller power state is DSI_CTRL_POWER_CORE_CLK_ON and the PHY is
+ * not enabled.
+ *
+ * This function will fail if driver is in any other state.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_PHY_SW_RESET, 0x0);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	dsi_ctrl->hw.ops.phy_sw_reset(&dsi_ctrl->hw);
+
+	pr_debug("[DSI_%d] PHY soft reset done\n", dsi_ctrl->index);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_PHY_SW_RESET, 0x0);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_host_init() - Initialize DSI host hardware.
+ * @dsi_ctrl:        DSI controller handle.
+ *
+ * Initializes DSI controller hardware with host configuration provided by
+ * dsi_ctrl_update_host_config(). Initialization can be performed only during
+ * DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been
+ * performed.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw,
+					  &dsi_ctrl->host_config.video_timing);
+
+	dsi_ctrl->hw.ops.setup_lane_map(&dsi_ctrl->hw,
+					&dsi_ctrl->host_config.lane_map);
+
+	dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
+				    &dsi_ctrl->host_config.common_config);
+
+	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)
+		dsi_ctrl->hw.ops.cmd_engine_setup(&dsi_ctrl->hw,
+					&dsi_ctrl->host_config.common_config,
+					&dsi_ctrl->host_config.u.cmd_engine);
+	else
+		dsi_ctrl->hw.ops.video_engine_setup(&dsi_ctrl->hw,
+					&dsi_ctrl->host_config.common_config,
+					&dsi_ctrl->host_config.u.video_engine);
+
+
+	dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
+	dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw, 0x0);
+
+	/* Perform a soft reset before enabling dsi controller */
+	dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
+	pr_debug("[DSI_%d]Host initialization complete\n", dsi_ctrl->index);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_host_deinit() - De-Initialize DSI host hardware.
+ * @dsi_ctrl:        DSI controller handle.
+ *
+ * De-initializes DSI controller hardware. It can be performed only during
+ * DSI_CTRL_POWER_CORE_CLK_ON state after LINK clocks have been turned off.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_host_deinit(struct dsi_ctrl *dsi_ctrl)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x0);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		pr_err("driver state check failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	pr_debug("[DSI_%d] Host deinitization complete\n", dsi_ctrl->index);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x0);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_update_host_config() - update dsi host configuration
+ * @dsi_ctrl:          DSI controller handle.
+ * @config:            DSI host configuration.
+ *
+ * Updates driver with new Host configuration to use for host initialization.
+ * This function call will only update the software context. The stored
+ * configuration information will be used when the host is initialized.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl,
+				struct dsi_host_config *config)
+{
+	int rc = 0;
+
+	if (!ctrl || !config) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_validate_panel_info(ctrl, config);
+	if (rc) {
+		pr_err("panel validation failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_ctrl_update_link_freqs(ctrl, config);
+	if (rc) {
+		pr_err("[%s] failed to update link frequencies, rc=%d\n",
+		       ctrl->name, rc);
+		goto error;
+	}
+
+	pr_debug("[DSI_%d]Host config updated\n", ctrl->index);
+	memcpy(&ctrl->host_config, config, sizeof(ctrl->host_config));
+error:
+	mutex_unlock(&ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_validate_timing() - validate a video timing configuration
+ * @dsi_ctrl:       DSI controller handle.
+ * @timing:         Pointer to timing data.
+ *
+ * Driver will validate if the timing configuration is supported on the
+ * controller hardware.
+ *
+ * Return: error code if timing is not supported.
+ */
+int dsi_ctrl_validate_timing(struct dsi_ctrl *dsi_ctrl,
+			     struct dsi_mode_info *mode)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl || !mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+
+	return rc;
+}
+
+/**
+ * dsi_ctrl_cmd_transfer() - Transfer commands on DSI link
+ * @dsi_ctrl:             DSI controller handle.
+ * @msg:                  Message to transfer on DSI link.
+ * @flags:                Modifiers for message transfer.
+ *
+ * Command transfer can be done only when command engine is enabled. The
+ * transfer API will block until either the command transfer finishes or
+ * the timeout value is reached. If the trigger is deferred, it will return
+ * without triggering the transfer. Command parameters are programmed to
+ * hardware.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl,
+			  const struct mipi_dsi_msg *msg,
+			  u32 flags)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl || !msg) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_CMD_TX, 0x0);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	rc = dsi_ctrl_vote_for_bandwidth(dsi_ctrl, true);
+	if (rc) {
+		pr_err("bandwidth request failed, rc=%d\n", rc);
+		goto error;
+	}
+
+	if (flags & DSI_CTRL_CMD_READ) {
+		rc = dsi_message_rx(dsi_ctrl, msg, flags);
+		if (rc)
+			pr_err("read message failed, rc=%d\n", rc);
+	} else {
+		rc = dsi_message_tx(dsi_ctrl, msg, flags);
+		if (rc)
+			pr_err("command msg transfer failed, rc = %d\n", rc);
+	}
+
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CMD_TX, 0x0);
+error_disable_bw_vote:
+	(void)dsi_ctrl_vote_for_bandwidth(dsi_ctrl, false);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command.
+ * @dsi_ctrl:              DSI controller handle.
+ * @flags:                 Modifiers.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags)
+{
+	int rc = 0;
+	u32 status = 0;
+	u32 mask = (DSI_CMD_MODE_DMA_DONE);
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	reinit_completion(&dsi_ctrl->int_info.cmd_dma_done);
+
+	dsi_ctrl->hw.ops.trigger_command_dma(&dsi_ctrl->hw);
+
+	if ((flags & DSI_CTRL_CMD_BROADCAST) &&
+	    (flags & DSI_CTRL_CMD_BROADCAST_MASTER)) {
+		u32 retry = 10;
+
+		while ((status == 0) && (retry > 0)) {
+			udelay(1000);
+			status = dsi_ctrl->hw.ops.get_interrupt_status(
+								&dsi_ctrl->hw);
+			status &= mask;
+			retry--;
+			dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw,
+								status);
+		}
+		pr_debug("INT STATUS = %x, retry = %d\n", status, retry);
+		if (retry == 0)
+			pr_err("[DSI_%d]Command transfer failed\n",
+			       dsi_ctrl->index);
+	}
+
+	rc = wait_for_completion_timeout(&dsi_ctrl->int_info.cmd_dma_done,
+					 msecs_to_jiffies(DSI_CTRL_TX_TO_MS));
+	if (rc == 0) {
+		pr_err("[%s] timedout waiting for cmd tx\n", dsi_ctrl->name);
+		rc = -ETIMEDOUT;
+	} else {
+		rc = 0;
+	}
+
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_power_state() - set power state for dsi controller
+ * @dsi_ctrl:          DSI controller handle.
+ * @state:             Power state.
+ *
+ * Set power state for DSI controller. Power state can be changed only when
+ * Controller, Video and Command engines are turned off.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl,
+			     enum dsi_power_state state)
+{
+	int rc = 0;
+	bool core_clk_enable = false;
+	bool link_clk_enable = false;
+	bool reg_enable = false;
+	struct dsi_ctrl_state_info *drv_state;
+
+	if (!dsi_ctrl || (state >= DSI_CTRL_POWER_MAX)) {
+		pr_err("Invalid Params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE,
+				  state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (state == DSI_CTRL_POWER_LINK_CLK_ON)
+		reg_enable = core_clk_enable = link_clk_enable = true;
+	else if (state == DSI_CTRL_POWER_CORE_CLK_ON)
+		reg_enable = core_clk_enable = true;
+	else if (state == DSI_CTRL_POWER_VREG_ON)
+		reg_enable = true;
+
+	drv_state = &dsi_ctrl->current_state;
+
+	if ((reg_enable) && (reg_enable != drv_state->pwr_enabled)) {
+		rc = dsi_ctrl_enable_supplies(dsi_ctrl, true);
+		if (rc) {
+			pr_err("[%d]failed to enable voltage supplies, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	if ((core_clk_enable) &&
+	    (core_clk_enable != drv_state->core_clk_enabled)) {
+		rc = dsi_clk_enable_core_clks(&dsi_ctrl->clk_info.core_clks,
+					      true);
+		if (rc) {
+			pr_err("[%d] failed to enable core clocks, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	if (link_clk_enable != drv_state->link_clk_enabled) {
+		rc = dsi_clk_enable_link_clks(&dsi_ctrl->clk_info.link_clks,
+					      link_clk_enable);
+		if (rc) {
+			pr_err("[%d] failed to enable link clocks, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	if ((!core_clk_enable) &&
+	    (core_clk_enable != drv_state->core_clk_enabled)) {
+		rc = dsi_clk_enable_core_clks(&dsi_ctrl->clk_info.core_clks,
+					      false);
+		if (rc) {
+			pr_err("[%d] failed to disable core clocks, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	if ((!reg_enable) && (reg_enable != drv_state->pwr_enabled)) {
+		rc = dsi_ctrl_enable_supplies(dsi_ctrl, true);
+		if (rc) {
+			pr_err("[%d]failed to disable vreg supplies, rc=%d\n",
+			       dsi_ctrl->index, rc);
+			goto error;
+		}
+	}
+
+	pr_debug("[DSI_%d] Power state updated to %d\n", dsi_ctrl->index,
+		 state);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE, state);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller
+ * @dsi_ctrl:          DSI controller handle.
+ * @on:                enable/disable test pattern.
+ *
+ * Test pattern can be enabled only after Video engine (for video mode panels)
+ * or command engine (for cmd mode panels) is enabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_tpg_state(struct dsi_ctrl *dsi_ctrl, bool on)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_TPG, on);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (on) {
+		if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) {
+			dsi_ctrl->hw.ops.video_test_pattern_setup(&dsi_ctrl->hw,
+							  DSI_TEST_PATTERN_INC,
+							  0xFFFF);
+		} else {
+			dsi_ctrl->hw.ops.cmd_test_pattern_setup(
+							&dsi_ctrl->hw,
+							DSI_TEST_PATTERN_INC,
+							0xFFFF,
+							0x0);
+		}
+	}
+	dsi_ctrl->hw.ops.test_pattern_enable(&dsi_ctrl->hw, on);
+
+	pr_debug("[DSI_%d]Set test pattern state=%d\n", dsi_ctrl->index, on);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_TPG, on);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_host_engine_state() - set host engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Host engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON and cmd, video engines are disabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_host_engine_state(struct dsi_ctrl *dsi_ctrl,
+				   enum dsi_engine_state state)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_ENGINE, state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (state == DSI_CTRL_ENGINE_ON)
+		dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, true);
+	else
+		dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, false);
+
+	pr_debug("[DSI_%d] Set host engine state = %d\n", dsi_ctrl->index,
+		 state);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_ENGINE, state);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_cmd_engine_state() - set command engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Command engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_cmd_engine_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_engine_state state)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_CMD_ENGINE, state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (state == DSI_CTRL_ENGINE_ON)
+		dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, true);
+	else
+		dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, false);
+
+	pr_debug("[DSI_%d] Set cmd engine state = %d\n", dsi_ctrl->index,
+		 state);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CMD_ENGINE, state);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_vid_engine_state() - set video engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Video engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_engine_state state)
+{
+	int rc = 0;
+	bool on;
+
+	if (!dsi_ctrl || (state >= DSI_CTRL_ENGINE_MAX)) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_VID_ENGINE, state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	on = (state == DSI_CTRL_ENGINE_ON) ? true : false;
+	dsi_ctrl->hw.ops.video_engine_en(&dsi_ctrl->hw, on);
+
+	/* perform a reset when turning off video engine */
+	if (!on)
+		dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
+
+	pr_debug("[DSI_%d] Set video engine state = %d\n", dsi_ctrl->index,
+		 state);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_VID_ENGINE, state);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_ulps() - set ULPS state for DSI lanes.
+ * @dsi_ctrl:         DSI controller handle.
+ * @enable:           enable/disable ULPS.
+ *
+ * ULPS can be enabled/disabled after DSI host engine is turned on.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_ULPS_TOGGLE, enable);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	if (enable)
+		rc = dsi_enable_ulps(dsi_ctrl);
+	else
+		rc = dsi_disable_ulps(dsi_ctrl);
+
+	if (rc) {
+		pr_err("[DSI_%d] Ulps state change(%d) failed, rc=%d\n",
+		       dsi_ctrl->index, enable, rc);
+		goto error;
+	}
+
+	pr_debug("[DSI_%d] ULPS state = %d\n", dsi_ctrl->index, enable);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_ULPS_TOGGLE, enable);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_clamp_state() - set clamp state for DSI phy
+ * @dsi_ctrl:             DSI controller handle.
+ * @enable:               enable/disable clamping.
+ *
+ * Clamps can be enabled/disabled while DSI contoller is still turned on.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_clamp_state(struct dsi_ctrl *dsi_ctrl, bool enable)
+{
+	int rc = 0;
+
+	if (!dsi_ctrl) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_CLAMP_TOGGLE, enable);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	rc = dsi_enable_io_clamp(dsi_ctrl, enable);
+	if (rc) {
+		pr_err("[DSI_%d] Failed to enable IO clamp\n", dsi_ctrl->index);
+		goto error;
+	}
+
+	pr_debug("[DSI_%d] Clamp state = %d\n", dsi_ctrl->index, enable);
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CLAMP_TOGGLE, enable);
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_set_clock_source() - set clock source fpr dsi link clocks
+ * @dsi_ctrl:        DSI controller handle.
+ * @source_clks:     Source clocks for DSI link clocks.
+ *
+ * Clock source should be changed while link clocks are disabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_clock_source(struct dsi_ctrl *dsi_ctrl,
+			      struct dsi_clk_link_set *source_clks)
+{
+	int rc = 0;
+	u32 op_state = 0;
+
+	if (!dsi_ctrl || !source_clks) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_ctrl->ctrl_lock);
+
+	if (source_clks->pixel_clk && source_clks->byte_clk)
+		op_state = 1;
+
+	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_SET_CLK_SOURCE,
+				 op_state);
+	if (rc) {
+		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		goto error;
+	}
+
+	rc = dsi_clk_update_parent(source_clks, &dsi_ctrl->clk_info.rcg_clks);
+	if (rc) {
+		pr_err("[DSI_%d]Failed to update link clk parent, rc=%d\n",
+		       dsi_ctrl->index, rc);
+		(void)dsi_clk_update_parent(&dsi_ctrl->clk_info.pll_op_clks,
+					    &dsi_ctrl->clk_info.rcg_clks);
+		goto error;
+	}
+
+	dsi_ctrl->clk_info.pll_op_clks.byte_clk = source_clks->byte_clk;
+	dsi_ctrl->clk_info.pll_op_clks.pixel_clk = source_clks->pixel_clk;
+
+	pr_debug("[DSI_%d] Source clocks are updated\n", dsi_ctrl->index);
+
+	dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_SET_CLK_SOURCE, op_state);
+
+error:
+	mutex_unlock(&dsi_ctrl->ctrl_lock);
+	return rc;
+}
+
+/**
+ * dsi_ctrl_drv_register() - register platform driver for dsi controller
+ */
+void __init dsi_ctrl_drv_register(void)
+{
+	platform_driver_register(&dsi_ctrl_driver);
+}
+
+/**
+ * dsi_ctrl_drv_unregister() - unregister platform driver
+ */
+void __exit dsi_ctrl_drv_unregister(void)
+{
+	platform_driver_unregister(&dsi_ctrl_driver);
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
new file mode 100644
index 000000000000..407ce517b803
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
@@ -0,0 +1,471 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_CTRL_H_
+#define _DSI_CTRL_H_
+
+#include "dsi_defs.h"
+#include "dsi_ctrl_hw.h"
+#include "dsi_clk_pwr.h"
+#include "drm_mipi_dsi.h"
+
+/*
+ * DSI Command transfer modifiers
+ * @DSI_CTRL_CMD_READ:             The current transfer involves reading data.
+ * @DSI_CTRL_CMD_BROADCAST:        The current transfer needs to be done in
+ *				   broadcast mode to multiple slaves.
+ * @DSI_CTRL_CMD_BROADCAST_MASTER: This controller is the master and the slaves
+ *				   sync to this trigger.
+ * @DSI_CTRL_CMD_DEFER_TRIGGER:    Defer the command trigger to later.
+ * @DSI_CTRL_CMD_FIFO_STORE:       Use FIFO for command transfer in place of
+ *				   reading data from memory.
+ */
+#define DSI_CTRL_CMD_READ             0x1
+#define DSI_CTRL_CMD_BROADCAST        0x2
+#define DSI_CTRL_CMD_BROADCAST_MASTER 0x4
+#define DSI_CTRL_CMD_DEFER_TRIGGER    0x8
+#define DSI_CTRL_CMD_FIFO_STORE       0x10
+
+/**
+ * enum dsi_power_state - defines power states for dsi controller.
+ * @DSI_CTRL_POWER_OFF:         DSI controller is powered down.
+ * @DSI_CTRL_POWER_VREG_ON:     Digital and analog supplies for DSI controller
+ *				are powered on.
+ * @DSI_CTRL_POWER_CORE_CLK_ON: DSI core clocks for register access are enabled.
+ * @DSI_CTRL_POWER_LINK_CLK_ON: DSI link clocks for link transfer are enabled.
+ * @DSI_CTRL_POWER_MAX:         Maximum value.
+ */
+enum dsi_power_state {
+	DSI_CTRL_POWER_OFF = 0,
+	DSI_CTRL_POWER_VREG_ON,
+	DSI_CTRL_POWER_CORE_CLK_ON,
+	DSI_CTRL_POWER_LINK_CLK_ON,
+	DSI_CTRL_POWER_MAX,
+};
+
+/**
+ * enum dsi_engine_state - define engine status for dsi controller.
+ * @DSI_CTRL_ENGINE_OFF:  Engine is turned off.
+ * @DSI_CTRL_ENGINE_ON:   Engine is turned on.
+ * @DSI_CTRL_ENGINE_MAX:  Maximum value.
+ */
+enum dsi_engine_state {
+	DSI_CTRL_ENGINE_OFF = 0,
+	DSI_CTRL_ENGINE_ON,
+	DSI_CTRL_ENGINE_MAX,
+};
+
+/**
+ * struct dsi_ctrl_power_info - digital and analog power supplies for dsi host
+ * @digital:  Digital power supply required to turn on DSI controller hardware.
+ * @host_pwr: Analog power supplies required to turn on DSI controller hardware.
+ *            Even though DSI controller it self does not require an analog
+ *            power supply, supplies required for PLL can be defined here to
+ *            allow proper control over these supplies.
+ */
+struct dsi_ctrl_power_info {
+	struct dsi_regulator_info digital;
+	struct dsi_regulator_info host_pwr;
+};
+
+/**
+ * struct dsi_ctrl_clk_info - clock information for DSI controller
+ * @core_clks:          Core clocks needed to access DSI controller registers.
+ * @link_clks:          Link clocks required to transmit data over DSI link.
+ * @rcg_clks:           Root clock generation clocks generated in MMSS_CC. The
+ *			output of the PLL is set as parent for these root
+ *			clocks. These clocks are specific to controller
+ *			instance.
+ * @mux_clks:           Mux clocks used for Dynamic refresh feature.
+ * @ext_clks:           External byte/pixel clocks from the MMSS block. These
+ *			clocks are set as parent to rcg clocks.
+ * @pll_op_clks:        TODO:
+ * @shadow_clks:        TODO:
+ */
+struct dsi_ctrl_clk_info {
+	/* Clocks parsed from DT */
+	struct dsi_core_clk_info core_clks;
+	struct dsi_link_clk_info link_clks;
+	struct dsi_clk_link_set rcg_clks;
+
+	/* Clocks set by DSI Manager */
+	struct dsi_clk_link_set mux_clks;
+	struct dsi_clk_link_set ext_clks;
+	struct dsi_clk_link_set pll_op_clks;
+	struct dsi_clk_link_set shadow_clks;
+};
+
+/**
+ * struct dsi_ctrl_bus_scale_info - Bus scale info for msm-bus bandwidth voting
+ * @bus_scale_table:        Bus scale voting usecases.
+ * @bus_handle:             Handle used for voting bandwidth.
+ * @refcount:               reference count.
+ */
+struct dsi_ctrl_bus_scale_info {
+	struct msm_bus_scale_pdata *bus_scale_table;
+	u32 bus_handle;
+	u32 refcount;
+};
+
+/**
+ * struct dsi_ctrl_state_info - current driver state information
+ * @power_state:        Controller power state.
+ * @cmd_engine_state:   Status of DSI command engine.
+ * @vid_engine_state:   Status of DSI video engine.
+ * @controller_state:   Status of DSI Controller engine.
+ * @pwr_enabled:        Set to true, if voltage supplies are enabled.
+ * @core_clk_enabled:   Set to true, if core clocks are enabled.
+ * @lin_clk_enabled:    Set to true, if link clocks are enabled.
+ * @ulps_enabled:       Set to true, if lanes are in ULPS state.
+ * @clamp_enabled:      Set to true, if PHY output is clamped.
+ * @clk_source_set:     Set to true, if parent is set for DSI link clocks.
+ */
+struct dsi_ctrl_state_info {
+	enum dsi_power_state power_state;
+	enum dsi_engine_state cmd_engine_state;
+	enum dsi_engine_state vid_engine_state;
+	enum dsi_engine_state controller_state;
+	bool pwr_enabled;
+	bool core_clk_enabled;
+	bool link_clk_enabled;
+	bool ulps_enabled;
+	bool clamp_enabled;
+	bool clk_source_set;
+	bool host_initialized;
+	bool tpg_enabled;
+};
+
+/**
+ * struct dsi_ctrl_interrupts - define interrupt information
+ * @irq:                   IRQ id for the DSI controller.
+ * @intr_lock:             Spinlock to protect access to interrupt registers.
+ * @interrupt_status:      Status interrupts which need to be serviced.
+ * @error_status:          Error interurpts which need to be serviced.
+ * @interrupts_enabled:    Status interrupts which are enabled.
+ * @errors_enabled:        Error interrupts which are enabled.
+ * @cmd_dma_done:          Completion signal for DSI_CMD_MODE_DMA_DONE interrupt
+ * @vid_frame_done:        Completion signal for DSI_VIDEO_MODE_FRAME_DONE int.
+ * @cmd_frame_done:        Completion signal for DSI_CMD_FRAME_DONE interrupt.
+ * @interrupt_done_work:   Work item for servicing status interrupts.
+ * @error_status_work:     Work item for servicing error interrupts.
+ */
+struct dsi_ctrl_interrupts {
+	u32 irq;
+	spinlock_t intr_lock; /* protects access to interrupt registers */
+	u32 interrupt_status;
+	u64 error_status;
+
+	u32 interrupts_enabled;
+	u64 errors_enabled;
+
+	struct completion cmd_dma_done;
+	struct completion vid_frame_done;
+	struct completion cmd_frame_done;
+
+	struct work_struct interrupt_done_work;
+	struct work_struct error_status_work;
+};
+
+/**
+ * struct dsi_ctrl - DSI controller object
+ * @pdev:                Pointer to platform device.
+ * @index:               Instance id.
+ * @name:                Name of the controller instance.
+ * @refcount:            ref counter.
+ * @ctrl_lock:           Mutex for hardware and object access.
+ * @drm_dev:             Pointer to DRM device.
+ * @version:             DSI controller version.
+ * @hw:                  DSI controller hardware object.
+ * @current_state;       Current driver and hardware state.
+ * @int_info:            Interrupt information.
+ * @clk_info:            Clock information.
+ * @pwr_info:            Power information.
+ * @axi_bus_info:        AXI bus information.
+ * @host_config:         Current host configuration.
+ * @tx_cmd_buf:          Tx command buffer.
+ * @cmd_buffer_size:     Size of command buffer.
+ * @debugfs_root:        Root for debugfs entries.
+ */
+struct dsi_ctrl {
+	struct platform_device *pdev;
+	u32 index;
+	const char *name;
+	u32 refcount;
+	struct mutex ctrl_lock;
+	struct drm_device *drm_dev;
+
+	enum dsi_ctrl_version version;
+	struct dsi_ctrl_hw hw;
+
+	/* Current state */
+	struct dsi_ctrl_state_info current_state;
+
+	struct dsi_ctrl_interrupts int_info;
+	/* Clock and power states */
+	struct dsi_ctrl_clk_info clk_info;
+	struct dsi_ctrl_power_info pwr_info;
+	struct dsi_ctrl_bus_scale_info axi_bus_info;
+
+	struct dsi_host_config host_config;
+	/* Command tx and rx */
+	struct drm_gem_object *tx_cmd_buf;
+	u32 cmd_buffer_size;
+
+	/* Debug Information */
+	struct dentry *debugfs_root;
+
+};
+
+/**
+ * dsi_ctrl_get() - get a dsi_ctrl handle from an of_node
+ * @of_node:    of_node of the DSI controller.
+ *
+ * Gets the DSI controller handle for the corresponding of_node. The ref count
+ * is incremented to one and all subsequent gets will fail until the original
+ * clients calls a put.
+ *
+ * Return: DSI Controller handle.
+ */
+struct dsi_ctrl *dsi_ctrl_get(struct device_node *of_node);
+
+/**
+ * dsi_ctrl_put() - releases a dsi controller handle.
+ * @dsi_ctrl:       DSI controller handle.
+ *
+ * Releases the DSI controller. Driver will clean up all resources and puts back
+ * the DSI controller into reset state.
+ */
+void dsi_ctrl_put(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_drv_init() - initialize dsi controller driver.
+ * @dsi_ctrl:      DSI controller handle.
+ *
+ * Initializes DSI controller driver. Driver should be initialized after
+ * dsi_ctrl_get() succeeds.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_drv_init(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_drv_deinit() - de-initializes dsi controller driver
+ * @dsi_ctrl:      DSI controller handle.
+ *
+ * Releases all resources acquired by dsi_ctrl_drv_init().
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_drv_deinit(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_validate_timing() - validate a video timing configuration
+ * @dsi_ctrl:       DSI controller handle.
+ * @timing:         Pointer to timing data.
+ *
+ * Driver will validate if the timing configuration is supported on the
+ * controller hardware.
+ *
+ * Return: error code if timing is not supported.
+ */
+int dsi_ctrl_validate_timing(struct dsi_ctrl *dsi_ctrl,
+			     struct dsi_mode_info *timing);
+
+/**
+ * dsi_ctrl_update_host_config() - update dsi host configuration
+ * @dsi_ctrl:          DSI controller handle.
+ * @config:            DSI host configuration.
+ *
+ * Updates driver with new Host configuration to use for host initialization.
+ * This function call will only update the software context. The stored
+ * configuration information will be used when the host is initialized.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_update_host_config(struct dsi_ctrl *dsi_ctrl,
+				struct dsi_host_config *config);
+
+/**
+ * dsi_ctrl_phy_sw_reset() - perform a PHY software reset
+ * @dsi_ctrl:         DSI controller handle.
+ *
+ * Performs a PHY software reset on the DSI controller. Reset should be done
+ * when the controller power state is DSI_CTRL_POWER_CORE_CLK_ON and the PHY is
+ * not enabled.
+ *
+ * This function will fail if driver is in any other state.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_host_init() - Initialize DSI host hardware.
+ * @dsi_ctrl:        DSI controller handle.
+ *
+ * Initializes DSI controller hardware with host configuration provided by
+ * dsi_ctrl_update_host_config(). Initialization can be performed only during
+ * DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been
+ * performed.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_host_deinit() - De-Initialize DSI host hardware.
+ * @dsi_ctrl:        DSI controller handle.
+ *
+ * De-initializes DSI controller hardware. It can be performed only during
+ * DSI_CTRL_POWER_CORE_CLK_ON state after LINK clocks have been turned off.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_host_deinit(struct dsi_ctrl *dsi_ctrl);
+
+/**
+ * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller
+ * @dsi_ctrl:          DSI controller handle.
+ * @on:                enable/disable test pattern.
+ *
+ * Test pattern can be enabled only after Video engine (for video mode panels)
+ * or command engine (for cmd mode panels) is enabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_tpg_state(struct dsi_ctrl *dsi_ctrl, bool on);
+
+/**
+ * dsi_ctrl_cmd_transfer() - Transfer commands on DSI link
+ * @dsi_ctrl:             DSI controller handle.
+ * @msg:                  Message to transfer on DSI link.
+ * @flags:                Modifiers for message transfer.
+ *
+ * Command transfer can be done only when command engine is enabled. The
+ * transfer API will until either the command transfer finishes or the timeout
+ * value is reached. If the trigger is deferred, it will return without
+ * triggering the transfer. Command parameters are programmed to hardware.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl,
+			  const struct mipi_dsi_msg *msg,
+			  u32 flags);
+
+/**
+ * dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command.
+ * @dsi_ctrl:              DSI controller handle.
+ * @flags:                 Modifiers.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags);
+
+/**
+ * dsi_ctrl_set_power_state() - set power state for dsi controller
+ * @dsi_ctrl:          DSI controller handle.
+ * @state:             Power state.
+ *
+ * Set power state for DSI controller. Power state can be changed only when
+ * Controller, Video and Command engines are turned off.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl,
+			     enum dsi_power_state state);
+
+/**
+ * dsi_ctrl_set_cmd_engine_state() - set command engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Command engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_cmd_engine_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_engine_state state);
+
+/**
+ * dsi_ctrl_set_vid_engine_state() - set video engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Video engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl,
+				  enum dsi_engine_state state);
+
+/**
+ * dsi_ctrl_set_host_engine_state() - set host engine state
+ * @dsi_ctrl:            DSI Controller handle.
+ * @state:               Engine state.
+ *
+ * Host engine state can be modified only when DSI controller power state is
+ * set to DSI_CTRL_POWER_LINK_CLK_ON and cmd, video engines are disabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_host_engine_state(struct dsi_ctrl *dsi_ctrl,
+				   enum dsi_engine_state state);
+
+/**
+ * dsi_ctrl_set_ulps() - set ULPS state for DSI lanes.
+ * @dsi_ctrl:         DSI controller handle.
+ * @enable:           enable/disable ULPS.
+ *
+ * ULPS can be enabled/disabled after DSI host engine is turned on.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable);
+
+/**
+ * dsi_ctrl_set_clamp_state() - set clamp state for DSI phy
+ * @dsi_ctrl:             DSI controller handle.
+ * @enable:               enable/disable clamping.
+ *
+ * Clamps can be enabled/disabled while DSI contoller is still turned on.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_clamp_state(struct dsi_ctrl *dsi_Ctrl, bool enable);
+
+/**
+ * dsi_ctrl_set_clock_source() - set clock source fpr dsi link clocks
+ * @dsi_ctrl:        DSI controller handle.
+ * @source_clks:     Source clocks for DSI link clocks.
+ *
+ * Clock source should be changed while link clocks are disabled.
+ *
+ * Return: error code.
+ */
+int dsi_ctrl_set_clock_source(struct dsi_ctrl *dsi_ctrl,
+			      struct dsi_clk_link_set *source_clks);
+
+/**
+ * dsi_ctrl_drv_register() - register platform driver for dsi controller
+ */
+void dsi_ctrl_drv_register(void);
+
+/**
+ * dsi_ctrl_drv_unregister() - unregister platform driver
+ */
+void dsi_ctrl_drv_unregister(void);
+
+#endif /* _DSI_CTRL_H_ */
-- 
cgit v1.2.3


From a8872e7407238eebd1a69cbe087c4ce5e4000660 Mon Sep 17 00:00:00 2001
From: Ajay Singh Parmar <aparmar@codeaurora.org>
Date: Wed, 22 Jun 2016 17:31:46 -0700
Subject: drm/msm/dsi-staging: add clock and power utilities

Add clock and power utilities for DSI driver components.
Read the clocks, regulators, gpios etc from device tree
and make them available for use.

Change-Id: Id3b08bac976da6834e636cbd79d05b3ba4b91557
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
---
 .../devicetree/bindings/drm/msm/sde-dsi.txt        |  11 +-
 drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.c      | 673 +++++++++++++++++++++
 drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.h      | 214 +++++++
 3 files changed, 897 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.c
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
index e435df862d26..6c1763622123 100644
--- a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
@@ -60,4 +60,13 @@ Optional properties:
 					there can be more than one instance of this binding,
 					in which case the entry would be appended with the
 					supply entry index.
-
+					e.g. qcom,ctrl-supply-entry@0
+					-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
+					-- qcom,supply-min-voltage: minimum voltage level (uV)
+					-- qcom,supply-max-voltage: maximum voltage level (uV)
+					-- qcom,supply-enable-load: load drawn (uA) from enabled supply
+					-- qcom,supply-disable-load: load drawn (uA) from disabled supply
+					-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
+					-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
+					-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
+					-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.c b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.c
new file mode 100644
index 000000000000..b10c80286a97
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.c
@@ -0,0 +1,673 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk/msm-clk.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "dsi_clk_pwr.h"
+
+#define INC_REFCOUNT(s, start_func) \
+	({ \
+		int rc = 0; \
+		if ((s)->refcount == 0) { \
+			rc = start_func(s); \
+			if (rc) \
+				pr_err("failed to enable, rc = %d\n", rc); \
+		} \
+		(s)->refcount++; \
+		rc; \
+	})
+
+#define DEC_REFCOUNT(s, stop_func) \
+	({ \
+		int rc = 0; \
+		if ((s)->refcount == 0) { \
+			pr_err("unbalanced refcount\n"); \
+		} else { \
+			(s)->refcount--; \
+			if ((s)->refcount == 0) { \
+				rc = stop_func(s); \
+				if (rc) \
+					pr_err("disable failed, rc=%d\n", rc); \
+			} \
+		} \
+		rc; \
+	})
+
+static int dsi_core_clk_start(struct dsi_core_clk_info *clks)
+{
+	int rc = 0;
+
+	rc = clk_prepare_enable(clks->mdp_core_clk);
+	if (rc) {
+		pr_err("failed to enable mdp_core_clk, rc=%d\n", rc);
+		goto error;
+	}
+
+	rc = clk_prepare_enable(clks->iface_clk);
+	if (rc) {
+		pr_err("failed to enable iface_clk, rc=%d\n", rc);
+		goto error_disable_core_clk;
+	}
+
+	rc = clk_prepare_enable(clks->bus_clk);
+	if (rc) {
+		pr_err("failed to enable bus_clk, rc=%d\n", rc);
+		goto error_disable_iface_clk;
+	}
+
+	rc = clk_prepare_enable(clks->core_mmss_clk);
+	if (rc) {
+		pr_err("failed to enable core_mmss_clk, rc=%d\n", rc);
+		goto error_disable_bus_clk;
+	}
+
+	return rc;
+
+error_disable_bus_clk:
+	clk_disable_unprepare(clks->bus_clk);
+error_disable_iface_clk:
+	clk_disable_unprepare(clks->iface_clk);
+error_disable_core_clk:
+	clk_disable_unprepare(clks->mdp_core_clk);
+error:
+	return rc;
+}
+
+static int dsi_core_clk_stop(struct dsi_core_clk_info *clks)
+{
+	clk_disable_unprepare(clks->core_mmss_clk);
+	clk_disable_unprepare(clks->bus_clk);
+	clk_disable_unprepare(clks->iface_clk);
+	clk_disable_unprepare(clks->mdp_core_clk);
+
+	return 0;
+}
+
+static int dsi_link_clk_set_rate(struct dsi_link_clk_info *l_clks)
+{
+	int rc = 0;
+
+	rc = clk_set_rate(l_clks->esc_clk, l_clks->esc_clk_rate);
+	if (rc) {
+		pr_err("clk_set_rate failed for esc_clk rc = %d\n", rc);
+		goto error;
+	}
+
+	rc = clk_set_rate(l_clks->byte_clk, l_clks->byte_clk_rate);
+	if (rc) {
+		pr_err("clk_set_rate failed for byte_clk rc = %d\n", rc);
+		goto error;
+	}
+
+	rc = clk_set_rate(l_clks->pixel_clk, l_clks->pixel_clk_rate);
+	if (rc) {
+		pr_err("clk_set_rate failed for pixel_clk rc = %d\n", rc);
+		goto error;
+	}
+error:
+	return rc;
+}
+
+static int dsi_link_clk_prepare(struct dsi_link_clk_info *l_clks)
+{
+	int rc = 0;
+
+	rc = clk_prepare(l_clks->esc_clk);
+	if (rc) {
+		pr_err("Failed to prepare dsi esc clk, rc=%d\n", rc);
+		goto esc_clk_err;
+	}
+
+	rc = clk_prepare(l_clks->byte_clk);
+	if (rc) {
+		pr_err("Failed to prepare dsi byte clk, rc=%d\n", rc);
+		goto byte_clk_err;
+	}
+
+	rc = clk_prepare(l_clks->pixel_clk);
+	if (rc) {
+		pr_err("Failed to prepare dsi pixel clk, rc=%d\n", rc);
+		goto pixel_clk_err;
+	}
+
+	return rc;
+
+pixel_clk_err:
+	clk_unprepare(l_clks->byte_clk);
+byte_clk_err:
+	clk_unprepare(l_clks->esc_clk);
+esc_clk_err:
+	return rc;
+}
+
+static void dsi_link_clk_unprepare(struct dsi_link_clk_info *l_clks)
+{
+	clk_unprepare(l_clks->pixel_clk);
+	clk_unprepare(l_clks->byte_clk);
+	clk_unprepare(l_clks->esc_clk);
+}
+
+static int dsi_link_clk_enable(struct dsi_link_clk_info *l_clks)
+{
+	int rc = 0;
+
+	rc = clk_enable(l_clks->esc_clk);
+	if (rc) {
+		pr_err("Failed to enable dsi esc clk, rc=%d\n", rc);
+		goto esc_clk_err;
+	}
+
+	rc = clk_enable(l_clks->byte_clk);
+	if (rc) {
+		pr_err("Failed to enable dsi byte clk, rc=%d\n", rc);
+		goto byte_clk_err;
+	}
+
+	rc = clk_enable(l_clks->pixel_clk);
+	if (rc) {
+		pr_err("Failed to enable dsi pixel clk, rc=%d\n", rc);
+		goto pixel_clk_err;
+	}
+
+	return rc;
+
+pixel_clk_err:
+	clk_disable(l_clks->byte_clk);
+byte_clk_err:
+	clk_disable(l_clks->esc_clk);
+esc_clk_err:
+	return rc;
+}
+
+static void dsi_link_clk_disable(struct dsi_link_clk_info *l_clks)
+{
+	clk_disable(l_clks->esc_clk);
+	clk_disable(l_clks->pixel_clk);
+	clk_disable(l_clks->byte_clk);
+}
+
+/**
+ * dsi_link_clk_start() - enable dsi link clocks
+ */
+static int dsi_link_clk_start(struct dsi_link_clk_info *clks)
+{
+	int rc = 0;
+
+	if (clks->set_new_rate) {
+		rc = dsi_link_clk_set_rate(clks);
+		if (rc) {
+			pr_err("failed to set clk rates, rc = %d\n", rc);
+			goto error;
+		} else {
+			clks->set_new_rate = false;
+		}
+	}
+
+	rc = dsi_link_clk_prepare(clks);
+	if (rc) {
+		pr_err("failed to prepare link clks, rc = %d\n", rc);
+		goto error;
+	}
+
+	rc = dsi_link_clk_enable(clks);
+	if (rc) {
+		pr_err("failed to enable link clks, rc = %d\n", rc);
+		goto error_unprepare;
+	}
+
+	pr_debug("Link clocks are enabled\n");
+	return rc;
+error_unprepare:
+	dsi_link_clk_unprepare(clks);
+error:
+	return rc;
+}
+
+/**
+ * dsi_link_clk_stop() - Stop DSI link clocks.
+ */
+static int dsi_link_clk_stop(struct dsi_link_clk_info *clks)
+{
+	dsi_link_clk_disable(clks);
+	dsi_link_clk_unprepare(clks);
+
+	pr_debug("Link clocks disabled\n");
+
+	return 0;
+}
+
+/*
+ * dsi_pwr_parse_supply_node() - parse power supply node from root device node
+ */
+static int dsi_pwr_parse_supply_node(struct device_node *root,
+				     struct dsi_regulator_info *regs)
+{
+	int rc = 0;
+	int i = 0;
+	u32 tmp = 0;
+	struct device_node *node = NULL;
+
+	for_each_child_of_node(root, node) {
+		const char *st = NULL;
+
+		rc = of_property_read_string(node, "qcom,supply-name", &st);
+		if (rc) {
+			pr_err("failed to read name, rc = %d\n", rc);
+			goto error;
+		}
+
+		snprintf(regs->vregs[i].vreg_name,
+			 strlen(regs->vregs[i].vreg_name),
+			 "%s", st);
+
+		rc = of_property_read_u32(node, "qcom,supply-min-voltage",
+					  &tmp);
+		if (rc) {
+			pr_err("failed to read min voltage, rc = %d\n", rc);
+			goto error;
+		}
+		regs->vregs[i].min_voltage = tmp;
+
+		rc = of_property_read_u32(node, "qcom,supply-max-voltage",
+					  &tmp);
+		if (rc) {
+			pr_err("failed to read max voltage, rc = %d\n", rc);
+			goto error;
+		}
+		regs->vregs[i].max_voltage = tmp;
+
+		rc = of_property_read_u32(node, "qcom,supply-enable-load",
+					  &tmp);
+		if (rc) {
+			pr_err("failed to read enable load, rc = %d\n", rc);
+			goto error;
+		}
+		regs->vregs[i].enable_load = tmp;
+
+		rc = of_property_read_u32(node, "qcom,supply-disable-load",
+					  &tmp);
+		if (rc) {
+			pr_err("failed to read disable load, rc = %d\n", rc);
+			goto error;
+		}
+		regs->vregs[i].disable_load = tmp;
+
+		/* Optional values */
+		rc = of_property_read_u32(node, "qcom,supply-pre-on-sleep",
+					  &tmp);
+		if (rc) {
+			pr_debug("pre-on-sleep not specified\n");
+			rc = 0;
+		} else {
+			regs->vregs[i].pre_on_sleep = tmp;
+		}
+
+		rc = of_property_read_u32(node, "qcom,supply-pre-off-sleep",
+					  &tmp);
+		if (rc) {
+			pr_debug("pre-off-sleep not specified\n");
+			rc = 0;
+		} else {
+			regs->vregs[i].pre_off_sleep = tmp;
+		}
+
+		rc = of_property_read_u32(node, "qcom,supply-post-on-sleep",
+					  &tmp);
+		if (rc) {
+			pr_debug("post-on-sleep not specified\n");
+			rc = 0;
+		} else {
+			regs->vregs[i].post_on_sleep = tmp;
+		}
+
+		rc = of_property_read_u32(node, "qcom,supply-post-off-sleep",
+					  &tmp);
+		if (rc) {
+			pr_debug("post-off-sleep not specified\n");
+			rc = 0;
+		} else {
+			regs->vregs[i].post_off_sleep = tmp;
+		}
+
+		++i;
+		pr_debug("[%s] minv=%d maxv=%d, en_load=%d, dis_load=%d\n",
+			 regs->vregs[i].vreg_name,
+			 regs->vregs[i].min_voltage,
+			 regs->vregs[i].max_voltage,
+			 regs->vregs[i].enable_load,
+			 regs->vregs[i].disable_load);
+	}
+
+error:
+	return rc;
+}
+
+/**
+ * dsi_pwr_enable_vregs() - enable/disable regulators
+ */
+static int dsi_pwr_enable_vregs(struct dsi_regulator_info *regs, bool enable)
+{
+	int rc = 0, i = 0;
+	struct dsi_vreg *vreg;
+	int num_of_v = 0;
+
+	if (enable) {
+		for (i = 0; i < regs->count; i++) {
+			vreg = &regs->vregs[i];
+			if (vreg->pre_on_sleep)
+				msleep(vreg->pre_on_sleep);
+
+			rc = regulator_set_load(vreg->vreg,
+						vreg->enable_load);
+			if (rc < 0) {
+				pr_err("Setting optimum mode failed for %s\n",
+				       vreg->vreg_name);
+				goto error;
+			}
+			num_of_v = regulator_count_voltages(vreg->vreg);
+			if (num_of_v > 0) {
+				rc = regulator_set_voltage(vreg->vreg,
+							   vreg->min_voltage,
+							   vreg->max_voltage);
+				if (rc) {
+					pr_err("Set voltage(%s) fail, rc=%d\n",
+						 vreg->vreg_name, rc);
+					goto error_disable_opt_mode;
+				}
+			}
+
+			rc = regulator_enable(vreg->vreg);
+			if (rc) {
+				pr_err("enable failed for %s, rc=%d\n",
+				       vreg->vreg_name, rc);
+				goto error_disable_voltage;
+			}
+
+			if (vreg->post_on_sleep)
+				msleep(vreg->post_on_sleep);
+		}
+	} else {
+		for (i = (regs->count - 1); i >= 0; i--) {
+			if (regs->vregs[i].pre_off_sleep)
+				msleep(regs->vregs[i].pre_off_sleep);
+
+			(void)regulator_set_load(regs->vregs[i].vreg,
+						regs->vregs[i].disable_load);
+			(void)regulator_disable(regs->vregs[i].vreg);
+
+			if (regs->vregs[i].post_off_sleep)
+				msleep(regs->vregs[i].post_off_sleep);
+		}
+	}
+
+	return 0;
+error_disable_opt_mode:
+	(void)regulator_set_load(regs->vregs[i].vreg,
+				 regs->vregs[i].disable_load);
+
+error_disable_voltage:
+	if (num_of_v > 0)
+		(void)regulator_set_voltage(regs->vregs[i].vreg,
+					    0, regs->vregs[i].max_voltage);
+error:
+	for (i--; i >= 0; i--) {
+		if (regs->vregs[i].pre_off_sleep)
+			msleep(regs->vregs[i].pre_off_sleep);
+
+		(void)regulator_set_load(regs->vregs[i].vreg,
+					 regs->vregs[i].disable_load);
+
+		num_of_v = regulator_count_voltages(regs->vregs[i].vreg);
+		if (num_of_v > 0)
+			(void)regulator_set_voltage(regs->vregs[i].vreg,
+					    0, regs->vregs[i].max_voltage);
+
+		(void)regulator_disable(regs->vregs[i].vreg);
+
+		if (regs->vregs[i].post_off_sleep)
+			msleep(regs->vregs[i].post_off_sleep);
+	}
+
+	return rc;
+}
+
+/**
+ * dsi_clk_pwr_get_dt_vreg_data - parse regulator supply information
+ * @dev:            Device whose of_node needs to be parsed.
+ * @regs:           Pointer where regulator information will be copied to.
+ * @supply_name:    Name of the supply node.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_pwr_get_dt_vreg_data(struct device *dev,
+				 struct dsi_regulator_info *regs,
+				 char *supply_name)
+{
+	int rc = 0;
+	struct device_node *of_node = NULL;
+	struct device_node *supply_node = NULL;
+	struct device_node *supply_root_node = NULL;
+
+	if (!dev || !regs) {
+		pr_err("Bad params\n");
+		return -EINVAL;
+	}
+
+	of_node = dev->of_node;
+	regs->count = 0;
+	supply_root_node = of_get_child_by_name(of_node, supply_name);
+	if (!supply_root_node) {
+		supply_root_node = of_parse_phandle(of_node, supply_name, 0);
+		if (!supply_root_node) {
+			pr_err("No supply entry present for %s\n", supply_name);
+			return -EINVAL;
+		}
+	}
+
+	for_each_child_of_node(supply_root_node, supply_node)
+		regs->count++;
+
+	if (regs->count == 0) {
+		pr_err("No vregs defined for %s\n", supply_name);
+		return -EINVAL;
+	}
+
+	regs->vregs = devm_kcalloc(dev, regs->count, sizeof(*regs->vregs),
+				   GFP_KERNEL);
+	if (!regs->vregs) {
+		regs->count = 0;
+		return -ENOMEM;
+	}
+
+	rc = dsi_pwr_parse_supply_node(supply_root_node, regs);
+	if (rc) {
+		pr_err("failed to parse supply node for %s, rc = %d\n",
+		       supply_name, rc);
+		devm_kfree(dev, regs->vregs);
+		regs->vregs = NULL;
+		regs->count = 0;
+	}
+
+	return rc;
+}
+
+/**
+ * dsi_pwr_enable_regulator() - enable a set of regulators
+ * @regs:       Pointer to set of regulators to enable or disable.
+ * @enable:     Enable/Disable regulators.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_pwr_enable_regulator(struct dsi_regulator_info *regs, bool enable)
+{
+	int rc = 0;
+
+	if (enable) {
+		if (regs->refcount == 0) {
+			rc = dsi_pwr_enable_vregs(regs, true);
+			if (rc)
+				pr_err("failed to enable regulators\n");
+		}
+		regs->refcount++;
+	} else {
+		if (regs->refcount == 0) {
+			pr_err("Unbalanced regulator off\n");
+		} else {
+			regs->refcount--;
+			if (regs->refcount == 0) {
+				rc = dsi_pwr_enable_vregs(regs, false);
+				if (rc)
+					pr_err("failed to disable vregs\n");
+			}
+		}
+	}
+
+	return rc;
+}
+
+/**
+ * dsi_clk_enable_core_clks() - enable DSI core clocks
+ * @clks:      DSI core clock information.
+ * @enable:    enable/disable DSI core clocks.
+ *
+ * A ref count is maintained, so caller should make sure disable and enable
+ * calls are balanced.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_enable_core_clks(struct dsi_core_clk_info *clks, bool enable)
+{
+	int rc = 0;
+
+	if (enable)
+		rc = INC_REFCOUNT(clks, dsi_core_clk_start);
+	else
+		rc = DEC_REFCOUNT(clks, dsi_core_clk_stop);
+
+	return rc;
+}
+
+/**
+ * dsi_clk_enable_link_clks() - enable DSI link clocks
+ * @clks:      DSI link clock information.
+ * @enable:    enable/disable DSI link clocks.
+ *
+ * A ref count is maintained, so caller should make sure disable and enable
+ * calls are balanced.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_enable_link_clks(struct dsi_link_clk_info *clks, bool enable)
+{
+	int rc = 0;
+
+	if (enable)
+		rc = INC_REFCOUNT(clks, dsi_link_clk_start);
+	else
+		rc = DEC_REFCOUNT(clks, dsi_link_clk_stop);
+
+	return rc;
+}
+
+/**
+ * dsi_clk_set_link_frequencies() - set frequencies for link clks
+ * @clks:         Link clock information
+ * @pixel_clk:    pixel clock frequency in KHz.
+ * @byte_clk:     Byte clock frequency in KHz.
+ * @esc_clk:      Escape clock frequency in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_link_frequencies(struct dsi_link_clk_info *clks,
+				 u64 pixel_clk,
+				 u64 byte_clk,
+				 u64 esc_clk)
+{
+	int rc = 0;
+
+	clks->pixel_clk_rate = pixel_clk;
+	clks->byte_clk_rate = byte_clk;
+	clks->esc_clk_rate = esc_clk;
+	clks->set_new_rate = true;
+
+	return rc;
+}
+
+/**
+ * dsi_clk_set_pixel_clk_rate() - set frequency for pixel clock
+ * @clks:      DSI link clock information.
+ * @pixel_clk: Pixel clock rate in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_pixel_clk_rate(struct dsi_link_clk_info *clks, u64 pixel_clk)
+{
+	int rc = 0;
+
+	rc = clk_set_rate(clks->pixel_clk, pixel_clk);
+	if (rc)
+		pr_err("failed to set clk rate for pixel clk, rc=%d\n", rc);
+	else
+		clks->pixel_clk_rate = pixel_clk;
+
+	return rc;
+}
+
+/**
+ * dsi_clk_set_byte_clk_rate() - set frequency for byte clock
+ * @clks:      DSI link clock information.
+ * @byte_clk: Byte clock rate in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_byte_clk_rate(struct dsi_link_clk_info *clks, u64 byte_clk)
+{
+	int rc = 0;
+
+	rc = clk_set_rate(clks->byte_clk, byte_clk);
+	if (rc)
+		pr_err("failed to set clk rate for byte clk, rc=%d\n", rc);
+	else
+		clks->byte_clk_rate = byte_clk;
+
+	return rc;
+}
+
+/**
+ * dsi_clk_update_parent() - update parent clocks for specified clock
+ * @parent:       link clock pair which are set as parent.
+ * @child:        link clock pair whose parent has to be set.
+ */
+int dsi_clk_update_parent(struct dsi_clk_link_set *parent,
+			  struct dsi_clk_link_set *child)
+{
+	int rc = 0;
+
+	rc = clk_set_parent(child->byte_clk, parent->byte_clk);
+	if (rc) {
+		pr_err("failed to set byte clk parent\n");
+		goto error;
+	}
+
+	rc = clk_set_parent(child->pixel_clk, parent->pixel_clk);
+	if (rc) {
+		pr_err("failed to set pixel clk parent\n");
+		goto error;
+	}
+error:
+	return rc;
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.h b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.h
new file mode 100644
index 000000000000..223ca4ec4290
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_pwr.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_CLK_PWR_H_
+#define _DSI_CLK_PWR_H_
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+
+/**
+ * struct dsi_vreg - regulator information for DSI regulators
+ * @vreg:            Handle to the regulator.
+ * @vreg_name:       Regulator name.
+ * @min_voltage:     Minimum voltage in uV.
+ * @max_voltage:     Maximum voltage in uV.
+ * @enable_load:     Load, in uA, when enabled.
+ * @disable_load:    Load, in uA, when disabled.
+ * @pre_on_sleep:    Sleep, in ms, before enabling the regulator.
+ * @post_on_sleep:   Sleep, in ms, after enabling the regulator.
+ * @pre_off_sleep:   Sleep, in ms, before disabling the regulator.
+ * @post_off_sleep:  Sleep, in ms, after disabling the regulator.
+ */
+struct dsi_vreg {
+	struct regulator *vreg;
+	char vreg_name[32];
+	u32 min_voltage;
+	u32 max_voltage;
+	u32 enable_load;
+	u32 disable_load;
+	u32 pre_on_sleep;
+	u32 post_on_sleep;
+	u32 pre_off_sleep;
+	u32 post_off_sleep;
+};
+
+/**
+ * struct dsi_regulator_info - set of vregs that are turned on/off together.
+ * @vregs:       Array of dsi_vreg structures.
+ * @count:       Number of vregs.
+ * @refcount:    Reference counting for enabling.
+ */
+struct dsi_regulator_info {
+	struct dsi_vreg *vregs;
+	u32 count;
+	u32 refcount;
+};
+
+/**
+ * struct dsi_core_clk_info - Core clock information for DSI hardware
+ * @mdp_core_clk:        Handle to MDP core clock.
+ * @iface_clk:           Handle to MDP interface clock.
+ * @core_mmss_clk:       Handle to MMSS core clock.
+ * @bus_clk:             Handle to bus clock.
+ * @refcount:            Reference count for core clocks.
+ * @clk_state:           Current clock state.
+ */
+struct dsi_core_clk_info {
+	struct clk *mdp_core_clk;
+	struct clk *iface_clk;
+	struct clk *core_mmss_clk;
+	struct clk *bus_clk;
+
+	u32 refcount;
+	u32 clk_state;
+};
+
+/**
+ * struct dsi_link_clk_info - Link clock information for DSI hardware.
+ * @byte_clk:        Handle to DSI byte clock.
+ * @byte_clk_rate:   Frequency of DSI byte clock in KHz.
+ * @pixel_clk:       Handle to DSI pixel clock.
+ * @pixel_clk_rate:  Frequency of DSI pixel clock in KHz.
+ * @esc_clk:         Handle to DSI escape clock.
+ * @esc_clk_rate:    Frequency of DSI escape clock in KHz.
+ * @refcount:        Reference count for link clocks.
+ * @clk_state:       Current clock state.
+ * @set_new_rate:    private flag used by clock utility.
+ */
+struct dsi_link_clk_info {
+	struct clk *byte_clk;
+	u64 byte_clk_rate;
+
+	struct clk *pixel_clk;
+	u64 pixel_clk_rate;
+
+	struct clk *esc_clk;
+	u64 esc_clk_rate;
+
+	u32 refcount;
+	u32 clk_state;
+	bool set_new_rate;
+};
+
+/**
+ * struct dsi_clk_link_set - Pair of clock handles to describe link clocks
+ * @byte_clk:     Handle to DSi byte clock.
+ * @pixel_clk:    Handle to DSI pixel clock.
+ */
+struct dsi_clk_link_set {
+	struct clk *byte_clk;
+	struct clk *pixel_clk;
+};
+
+/**
+ * dsi_clk_pwr_of_get_vreg_data - parse regulator supply information
+ * @of_node:        Device of node to parse for supply information.
+ * @regs:           Pointer where regulator information will be copied to.
+ * @supply_name:    Name of the supply node.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_pwr_of_get_vreg_data(struct device_node *of_node,
+				 struct dsi_regulator_info *regs,
+				 char *supply_name);
+
+/**
+ * dsi_clk_pwr_get_dt_vreg_data - parse regulator supply information
+ * @dev:            Device whose of_node needs to be parsed.
+ * @regs:           Pointer where regulator information will be copied to.
+ * @supply_name:    Name of the supply node.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_pwr_get_dt_vreg_data(struct device *dev,
+				 struct dsi_regulator_info *regs,
+				 char *supply_name);
+
+/**
+ * dsi_pwr_enable_regulator() - enable a set of regulators
+ * @regs:       Pointer to set of regulators to enable or disable.
+ * @enable:     Enable/Disable regulators.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_pwr_enable_regulator(struct dsi_regulator_info *regs, bool enable);
+
+/**
+ * dsi_clk_enable_core_clks() - enable DSI core clocks
+ * @clks:      DSI core clock information.
+ * @enable:    enable/disable DSI core clocks.
+ *
+ * A ref count is maintained, so caller should make sure disable and enable
+ * calls are balanced.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_enable_core_clks(struct dsi_core_clk_info *clks, bool enable);
+
+/**
+ * dsi_clk_enable_link_clks() - enable DSI link clocks
+ * @clks:      DSI link clock information.
+ * @enable:    enable/disable DSI link clocks.
+ *
+ * A ref count is maintained, so caller should make sure disable and enable
+ * calls are balanced.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_enable_link_clks(struct dsi_link_clk_info *clks, bool enable);
+
+/**
+ * dsi_clk_set_link_frequencies() - set frequencies for link clks
+ * @clks:         Link clock information
+ * @pixel_clk:    pixel clock frequency in KHz.
+ * @byte_clk:     Byte clock frequency in KHz.
+ * @esc_clk:      Escape clock frequency in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_link_frequencies(struct dsi_link_clk_info *clks,
+				 u64 pixel_clk,
+				 u64 byte_clk,
+				 u64 esc_clk);
+
+/**
+ * dsi_clk_set_pixel_clk_rate() - set frequency for pixel clock
+ * @clks:      DSI link clock information.
+ * @pixel_clk: Pixel clock rate in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_pixel_clk_rate(struct dsi_link_clk_info *clks, u64 pixel_clk);
+
+/**
+ * dsi_clk_set_byte_clk_rate() - set frequency for byte clock
+ * @clks:      DSI link clock information.
+ * @byte_clk: Byte clock rate in KHz.
+ *
+ * return: error code in case of failure or 0 for success.
+ */
+int dsi_clk_set_byte_clk_rate(struct dsi_link_clk_info *clks, u64 byte_clk);
+
+/**
+ * dsi_clk_update_parent() - update parent clocks for specified clock
+ * @parent:       link clock pair which are set as parent.
+ * @child:        link clock pair whose parent has to be set.
+ */
+int dsi_clk_update_parent(struct dsi_clk_link_set *parent,
+			  struct dsi_clk_link_set *child);
+#endif /* _DSI_CLK_PWR_H_ */
-- 
cgit v1.2.3


From 5edb750561e25d4241639e735aba3b2691afcead Mon Sep 17 00:00:00 2001
From: Ajay Singh Parmar <aparmar@codeaurora.org>
Date: Wed, 22 Jun 2016 17:37:56 -0700
Subject: drm/msm/dsi-staging: add dsi phy driver

Add dsi phy driver. Configure clocks, regulators, gpios, lanes,
and other dsi phy related hardware.

Change-Id: Ic06c17f57496b22bcf820ea5c6929e334fa99a09
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
---
 .../devicetree/bindings/drm/msm/sde-dsi.txt        |   3 +
 drivers/gpu/drm/msm/dsi-staging/dsi_phy.c          | 859 +++++++++++++++++++++
 drivers/gpu/drm/msm/dsi-staging/dsi_phy.h          | 196 +++++
 3 files changed, 1058 insertions(+)
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
index 6c1763622123..cdeb37be498d 100644
--- a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
@@ -8,6 +8,9 @@ Required properties:
 - compatible:           Should be "qcom,dsi-ctrl-hw-v<version>". Supported
 			versions include 1.4 and 2.0.
 			eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0
+			And for dsi phy driver:
+			qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, qcom,dsi-phy-v3.0,
+			qcom,dsi-phy-v4.0
 - reg:                  Base address and length of DSI controller's memory
 			mapped regions.
 - reg-names:            A list of strings that name the list of regs.
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
new file mode 100644
index 000000000000..d53ef1140f99
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
@@ -0,0 +1,859 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"msm-dsi-phy:[%s] " fmt, __func__
+
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#include <linux/msm-bus.h>
+#include <linux/list.h>
+
+#include "msm_drv.h"
+#include "msm_kms.h"
+#include "msm_gpu.h"
+#include "dsi_phy.h"
+#include "dsi_phy_hw.h"
+#include "dsi_clk_pwr.h"
+#include "dsi_catalog.h"
+
+#define DSI_PHY_DEFAULT_LABEL "MDSS PHY CTRL"
+
+struct dsi_phy_list_item {
+	struct msm_dsi_phy *phy;
+	struct list_head list;
+};
+
+static LIST_HEAD(dsi_phy_list);
+static DEFINE_MUTEX(dsi_phy_list_lock);
+
+static const struct dsi_ver_spec_info dsi_phy_v1_0 = {
+	.version = DSI_PHY_VERSION_1_0,
+	.lane_cfg_count = 4,
+	.strength_cfg_count = 2,
+	.regulator_cfg_count = 1,
+	.timing_cfg_count = 8,
+};
+static const struct dsi_ver_spec_info dsi_phy_v2_0 = {
+	.version = DSI_PHY_VERSION_2_0,
+	.lane_cfg_count = 4,
+	.strength_cfg_count = 2,
+	.regulator_cfg_count = 1,
+	.timing_cfg_count = 8,
+};
+static const struct dsi_ver_spec_info dsi_phy_v3_0 = {
+	.version = DSI_PHY_VERSION_3_0,
+	.lane_cfg_count = 4,
+	.strength_cfg_count = 2,
+	.regulator_cfg_count = 1,
+	.timing_cfg_count = 8,
+};
+static const struct dsi_ver_spec_info dsi_phy_v4_0 = {
+	.version = DSI_PHY_VERSION_4_0,
+	.lane_cfg_count = 4,
+	.strength_cfg_count = 2,
+	.regulator_cfg_count = 1,
+	.timing_cfg_count = 8,
+};
+
+static const struct of_device_id msm_dsi_phy_of_match[] = {
+	{ .compatible = "qcom,dsi-phy-v1.0",
+	  .data = &dsi_phy_v1_0,},
+	{ .compatible = "qcom,dsi-phy-v2.0",
+	  .data = &dsi_phy_v2_0,},
+	{ .compatible = "qcom,dsi-phy-v3.0",
+	  .data = &dsi_phy_v3_0,},
+	{ .compatible = "qcom,dsi-phy-v4.0",
+	  .data = &dsi_phy_v4_0,},
+	{}
+};
+
+static int dsi_phy_regmap_init(struct platform_device *pdev,
+			       struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	void __iomem *ptr;
+
+	ptr = msm_ioremap(pdev, "dsi_phy", phy->name);
+	if (IS_ERR(ptr)) {
+		rc = PTR_ERR(ptr);
+		return rc;
+	}
+
+	phy->hw.base = ptr;
+
+	pr_debug("[%s] map dsi_phy registers to %p\n", phy->name, phy->hw.base);
+
+	return rc;
+}
+
+static int dsi_phy_regmap_deinit(struct msm_dsi_phy *phy)
+{
+	pr_debug("[%s] unmap registers\n", phy->name);
+	return 0;
+}
+
+static int dsi_phy_clocks_deinit(struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	struct dsi_core_clk_info *core = &phy->clks.core_clks;
+
+	if (core->mdp_core_clk)
+		devm_clk_put(&phy->pdev->dev, core->mdp_core_clk);
+	if (core->iface_clk)
+		devm_clk_put(&phy->pdev->dev, core->iface_clk);
+	if (core->core_mmss_clk)
+		devm_clk_put(&phy->pdev->dev, core->core_mmss_clk);
+	if (core->bus_clk)
+		devm_clk_put(&phy->pdev->dev, core->bus_clk);
+
+	memset(core, 0x0, sizeof(*core));
+
+	return rc;
+}
+
+static int dsi_phy_clocks_init(struct platform_device *pdev,
+			       struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	struct dsi_core_clk_info *core = &phy->clks.core_clks;
+
+	core->mdp_core_clk = devm_clk_get(&pdev->dev, "mdp_core_clk");
+	if (IS_ERR(core->mdp_core_clk)) {
+		rc = PTR_ERR(core->mdp_core_clk);
+		pr_err("failed to get mdp_core_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->iface_clk = devm_clk_get(&pdev->dev, "iface_clk");
+	if (IS_ERR(core->iface_clk)) {
+		rc = PTR_ERR(core->iface_clk);
+		pr_err("failed to get iface_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->core_mmss_clk = devm_clk_get(&pdev->dev, "core_mmss_clk");
+	if (IS_ERR(core->core_mmss_clk)) {
+		rc = PTR_ERR(core->core_mmss_clk);
+		pr_err("failed to get core_mmss_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	core->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
+	if (IS_ERR(core->bus_clk)) {
+		rc = PTR_ERR(core->bus_clk);
+		pr_err("failed to get bus_clk, rc=%d\n", rc);
+		goto fail;
+	}
+
+	return rc;
+fail:
+	dsi_phy_clocks_deinit(phy);
+	return rc;
+}
+
+static int dsi_phy_supplies_init(struct platform_device *pdev,
+				 struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	int i = 0;
+	struct dsi_regulator_info *regs;
+	struct regulator *vreg = NULL;
+
+	regs = &phy->pwr_info.digital;
+	regs->vregs = devm_kzalloc(&pdev->dev, sizeof(struct dsi_vreg),
+				   GFP_KERNEL);
+	if (!regs->vregs)
+		goto error;
+
+	regs->count = 1;
+	snprintf(regs->vregs->vreg_name,
+		 ARRAY_SIZE(regs->vregs[i].vreg_name),
+		 "%s", "gdsc");
+
+	rc = dsi_clk_pwr_get_dt_vreg_data(&pdev->dev,
+					  &phy->pwr_info.phy_pwr,
+					  "qcom,phy-supply-entries");
+	if (rc) {
+		pr_err("failed to get host power supplies, rc = %d\n", rc);
+		goto error_digital;
+	}
+
+	regs = &phy->pwr_info.digital;
+	for (i = 0; i < regs->count; i++) {
+		vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
+		rc = PTR_RET(vreg);
+		if (rc) {
+			pr_err("failed to get %s regulator\n",
+			       regs->vregs[i].vreg_name);
+			goto error_host_pwr;
+		}
+		regs->vregs[i].vreg = vreg;
+	}
+
+	regs = &phy->pwr_info.phy_pwr;
+	for (i = 0; i < regs->count; i++) {
+		vreg = devm_regulator_get(&pdev->dev, regs->vregs[i].vreg_name);
+		rc = PTR_RET(vreg);
+		if (rc) {
+			pr_err("failed to get %s regulator\n",
+			       regs->vregs[i].vreg_name);
+			for (--i; i >= 0; i--)
+				devm_regulator_put(regs->vregs[i].vreg);
+			goto error_digital_put;
+		}
+		regs->vregs[i].vreg = vreg;
+	}
+
+	return rc;
+
+error_digital_put:
+	regs = &phy->pwr_info.digital;
+	for (i = 0; i < regs->count; i++)
+		devm_regulator_put(regs->vregs[i].vreg);
+error_host_pwr:
+	devm_kfree(&pdev->dev, phy->pwr_info.phy_pwr.vregs);
+	phy->pwr_info.phy_pwr.vregs = NULL;
+	phy->pwr_info.phy_pwr.count = 0;
+error_digital:
+	devm_kfree(&pdev->dev, phy->pwr_info.digital.vregs);
+	phy->pwr_info.digital.vregs = NULL;
+	phy->pwr_info.digital.count = 0;
+error:
+	return rc;
+}
+
+static int dsi_phy_supplies_deinit(struct msm_dsi_phy *phy)
+{
+	int i = 0;
+	int rc = 0;
+	struct dsi_regulator_info *regs;
+
+	regs = &phy->pwr_info.digital;
+	for (i = 0; i < regs->count; i++) {
+		if (!regs->vregs[i].vreg)
+			pr_err("vreg is NULL, should not reach here\n");
+		else
+			devm_regulator_put(regs->vregs[i].vreg);
+	}
+
+	regs = &phy->pwr_info.phy_pwr;
+	for (i = 0; i < regs->count; i++) {
+		if (!regs->vregs[i].vreg)
+			pr_err("vreg is NULL, should not reach here\n");
+		else
+			devm_regulator_put(regs->vregs[i].vreg);
+	}
+
+	if (phy->pwr_info.phy_pwr.vregs) {
+		devm_kfree(&phy->pdev->dev, phy->pwr_info.phy_pwr.vregs);
+		phy->pwr_info.phy_pwr.vregs = NULL;
+		phy->pwr_info.phy_pwr.count = 0;
+	}
+	if (phy->pwr_info.digital.vregs) {
+		devm_kfree(&phy->pdev->dev, phy->pwr_info.digital.vregs);
+		phy->pwr_info.digital.vregs = NULL;
+		phy->pwr_info.digital.count = 0;
+	}
+
+	return rc;
+}
+
+static int dsi_phy_parse_dt_per_lane_cfgs(struct platform_device *pdev,
+					  struct dsi_phy_per_lane_cfgs *cfg,
+					  char *property)
+{
+	int rc = 0, i = 0, j = 0;
+	const u8 *data;
+	u32 len = 0;
+
+	data = of_get_property(pdev->dev.of_node, property, &len);
+	if (!data) {
+		pr_err("Unable to read Phy %s settings\n", property);
+		return -EINVAL;
+	}
+
+	if (len != DSI_LANE_MAX * cfg->count_per_lane) {
+		pr_err("incorrect phy %s settings, exp=%d, act=%d\n",
+		       property, (DSI_LANE_MAX * cfg->count_per_lane), len);
+		return -EINVAL;
+	}
+
+	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
+		for (j = 0; j < cfg->count_per_lane; j++) {
+			cfg->lane[i][j] = *data;
+			data++;
+		}
+	}
+
+	return rc;
+}
+
+static int dsi_phy_settings_init(struct platform_device *pdev,
+				 struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+	struct dsi_phy_per_lane_cfgs *lane = &phy->cfg.lanecfg;
+	struct dsi_phy_per_lane_cfgs *strength = &phy->cfg.strength;
+	struct dsi_phy_per_lane_cfgs *timing = &phy->cfg.timing;
+	struct dsi_phy_per_lane_cfgs *regs = &phy->cfg.regulators;
+
+	lane->count_per_lane = phy->ver_info->lane_cfg_count;
+	rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, lane,
+					    "qcom,platform-lane-config");
+	if (rc) {
+		pr_err("failed to parse lane cfgs, rc=%d\n", rc);
+		goto err;
+	}
+
+	strength->count_per_lane = phy->ver_info->strength_cfg_count;
+	rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, strength,
+					    "qcom,platform-strength-ctrl");
+	if (rc) {
+		pr_err("failed to parse lane cfgs, rc=%d\n", rc);
+		goto err;
+	}
+
+	regs->count_per_lane = phy->ver_info->regulator_cfg_count;
+	rc = dsi_phy_parse_dt_per_lane_cfgs(pdev, regs,
+					    "qcom,platform-regulator-settings");
+	if (rc) {
+		pr_err("failed to parse lane cfgs, rc=%d\n", rc);
+		goto err;
+	}
+
+	/* Actual timing values are dependent on panel */
+	timing->count_per_lane = phy->ver_info->timing_cfg_count;
+
+err:
+	lane->count_per_lane = 0;
+	strength->count_per_lane = 0;
+	regs->count_per_lane = 0;
+	timing->count_per_lane = 0;
+	return rc;
+}
+
+static int dsi_phy_settings_deinit(struct msm_dsi_phy *phy)
+{
+	memset(&phy->cfg.lanecfg, 0x0, sizeof(phy->cfg.lanecfg));
+	memset(&phy->cfg.strength, 0x0, sizeof(phy->cfg.strength));
+	memset(&phy->cfg.timing, 0x0, sizeof(phy->cfg.timing));
+	memset(&phy->cfg.regulators, 0x0, sizeof(phy->cfg.regulators));
+	return 0;
+}
+
+static int dsi_phy_driver_probe(struct platform_device *pdev)
+{
+	struct msm_dsi_phy *dsi_phy;
+	struct dsi_phy_list_item *item;
+	const struct of_device_id *id;
+	const struct dsi_ver_spec_info *ver_info;
+	int rc = 0;
+	u32 index = 0;
+
+	if (!pdev || !pdev->dev.of_node) {
+		pr_err("pdev not found\n");
+		return -ENODEV;
+	}
+
+	id = of_match_node(msm_dsi_phy_of_match, pdev->dev.of_node);
+	if (!id)
+		return -ENODEV;
+
+	ver_info = id->data;
+
+	item = devm_kzalloc(&pdev->dev, sizeof(*item), GFP_KERNEL);
+	if (!item)
+		return -ENOMEM;
+
+
+	dsi_phy = devm_kzalloc(&pdev->dev, sizeof(*dsi_phy), GFP_KERNEL);
+	if (!dsi_phy) {
+		devm_kfree(&pdev->dev, item);
+		return -ENOMEM;
+	}
+
+	rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &index);
+	if (rc) {
+		pr_debug("cell index not set, default to 0\n");
+		index = 0;
+	}
+
+	dsi_phy->index = index;
+
+	dsi_phy->name = of_get_property(pdev->dev.of_node, "label", NULL);
+	if (!dsi_phy->name)
+		dsi_phy->name = DSI_PHY_DEFAULT_LABEL;
+
+	pr_debug("Probing %s device\n", dsi_phy->name);
+
+	rc = dsi_phy_regmap_init(pdev, dsi_phy);
+	if (rc) {
+		pr_err("Failed to parse register information, rc=%d\n", rc);
+		goto fail;
+	}
+
+	rc = dsi_phy_clocks_init(pdev, dsi_phy);
+	if (rc) {
+		pr_err("failed to parse clock information, rc = %d\n", rc);
+		goto fail_regmap;
+	}
+
+	rc = dsi_phy_supplies_init(pdev, dsi_phy);
+	if (rc) {
+		pr_err("failed to parse voltage supplies, rc = %d\n", rc);
+		goto fail_clks;
+	}
+
+	rc = dsi_catalog_phy_setup(&dsi_phy->hw, ver_info->version,
+				   dsi_phy->index);
+	if (rc) {
+		pr_err("Catalog does not support version (%d)\n",
+		       ver_info->version);
+		goto fail_supplies;
+	}
+
+	dsi_phy->ver_info = ver_info;
+	rc = dsi_phy_settings_init(pdev, dsi_phy);
+	if (rc) {
+		pr_err("Failed to parse phy setting, rc=%d\n", rc);
+		goto fail_supplies;
+	}
+
+	item->phy = dsi_phy;
+
+	mutex_lock(&dsi_phy_list_lock);
+	list_add(&item->list, &dsi_phy_list);
+	mutex_unlock(&dsi_phy_list_lock);
+
+	mutex_init(&dsi_phy->phy_lock);
+	/** TODO: initialize debugfs */
+	dsi_phy->pdev = pdev;
+	platform_set_drvdata(pdev, dsi_phy);
+	pr_debug("Probe successful for %s\n", dsi_phy->name);
+	return 0;
+
+fail_supplies:
+	(void)dsi_phy_supplies_deinit(dsi_phy);
+fail_clks:
+	(void)dsi_phy_clocks_deinit(dsi_phy);
+fail_regmap:
+	(void)dsi_phy_regmap_deinit(dsi_phy);
+fail:
+	devm_kfree(&pdev->dev, dsi_phy);
+	devm_kfree(&pdev->dev, item);
+	return rc;
+}
+
+static int dsi_phy_driver_remove(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
+	struct list_head *pos, *tmp;
+
+	if (!pdev || !phy) {
+		pr_err("Invalid device\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_phy_list_lock);
+	list_for_each_safe(pos, tmp, &dsi_phy_list) {
+		struct dsi_phy_list_item *n;
+
+		n = list_entry(pos, struct dsi_phy_list_item, list);
+		if (n->phy == phy) {
+			list_del(&n->list);
+			devm_kfree(&pdev->dev, n);
+			break;
+		}
+	}
+	mutex_unlock(&dsi_phy_list_lock);
+
+	mutex_lock(&phy->phy_lock);
+	rc = dsi_phy_settings_deinit(phy);
+	if (rc)
+		pr_err("failed to deinitialize phy settings, rc=%d\n", rc);
+
+	rc = dsi_phy_supplies_deinit(phy);
+	if (rc)
+		pr_err("failed to deinitialize voltage supplies, rc=%d\n", rc);
+
+	rc = dsi_phy_clocks_deinit(phy);
+	if (rc)
+		pr_err("failed to deinitialize clocks, rc=%d\n", rc);
+
+	rc = dsi_phy_regmap_deinit(phy);
+	if (rc)
+		pr_err("failed to deinitialize regmap, rc=%d\n", rc);
+	mutex_unlock(&phy->phy_lock);
+
+	mutex_destroy(&phy->phy_lock);
+	devm_kfree(&pdev->dev, phy);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver dsi_phy_platform_driver = {
+	.probe      = dsi_phy_driver_probe,
+	.remove     = dsi_phy_driver_remove,
+	.driver     = {
+		.name   = "msm_dsi_phy",
+		.of_match_table = msm_dsi_phy_of_match,
+	},
+};
+
+static void dsi_phy_enable_hw(struct msm_dsi_phy *phy)
+{
+	if (phy->hw.ops.regulator_enable)
+		phy->hw.ops.regulator_enable(&phy->hw, &phy->cfg.regulators);
+
+	if (phy->hw.ops.enable)
+		phy->hw.ops.enable(&phy->hw, &phy->cfg);
+}
+
+static void dsi_phy_disable_hw(struct msm_dsi_phy *phy)
+{
+	if (phy->hw.ops.disable)
+		phy->hw.ops.disable(&phy->hw);
+
+	if (phy->hw.ops.regulator_disable)
+		phy->hw.ops.regulator_disable(&phy->hw);
+}
+
+/**
+ * dsi_phy_get() - get a dsi phy handle from device node
+ * @of_node:           device node for dsi phy controller
+ *
+ * Gets the DSI PHY handle for the corresponding of_node. The ref count is
+ * incremented to one all subsequents get will fail until the original client
+ * calls a put.
+ *
+ * Return: DSI PHY handle or an error code.
+ */
+struct msm_dsi_phy *dsi_phy_get(struct device_node *of_node)
+{
+	struct list_head *pos, *tmp;
+	struct msm_dsi_phy *phy = NULL;
+
+	mutex_lock(&dsi_phy_list_lock);
+	list_for_each_safe(pos, tmp, &dsi_phy_list) {
+		struct dsi_phy_list_item *n;
+
+		n = list_entry(pos, struct dsi_phy_list_item, list);
+		if (n->phy->pdev->dev.of_node == of_node) {
+			phy = n->phy;
+			break;
+		}
+	}
+	mutex_unlock(&dsi_phy_list_lock);
+
+	if (!phy) {
+		pr_err("Device with of node not found\n");
+		phy = ERR_PTR(-EPROBE_DEFER);
+		return phy;
+	}
+
+	mutex_lock(&phy->phy_lock);
+	if (phy->refcount > 0) {
+		pr_err("[PHY_%d] Device under use\n", phy->index);
+		phy = ERR_PTR(-EINVAL);
+	} else {
+		phy->refcount++;
+	}
+	mutex_unlock(&phy->phy_lock);
+	return phy;
+}
+
+/**
+ * dsi_phy_put() - release dsi phy handle
+ * @dsi_phy:              DSI PHY handle.
+ *
+ * Release the DSI PHY hardware. Driver will clean up all resources and puts
+ * back the DSI PHY into reset state.
+ */
+void dsi_phy_put(struct msm_dsi_phy *dsi_phy)
+{
+	mutex_lock(&dsi_phy->phy_lock);
+
+	if (dsi_phy->refcount == 0)
+		pr_err("Unbalanced dsi_phy_put call\n");
+	else
+		dsi_phy->refcount--;
+
+	mutex_unlock(&dsi_phy->phy_lock);
+}
+
+/**
+ * dsi_phy_drv_init() - initialize dsi phy driver
+ * @dsi_phy:         DSI PHY handle.
+ *
+ * Initializes DSI PHY driver. Should be called after dsi_phy_get().
+ *
+ * Return: error code.
+ */
+int dsi_phy_drv_init(struct msm_dsi_phy *dsi_phy)
+{
+	return 0;
+}
+
+/**
+ * dsi_phy_drv_deinit() - de-initialize dsi phy driver
+ * @dsi_phy:          DSI PHY handle.
+ *
+ * Release all resources acquired by dsi_phy_drv_init().
+ *
+ * Return: error code.
+ */
+int dsi_phy_drv_deinit(struct msm_dsi_phy *dsi_phy)
+{
+	return 0;
+}
+
+/**
+ * dsi_phy_validate_mode() - validate a display mode
+ * @dsi_phy:            DSI PHY handle.
+ * @mode:               Mode information.
+ *
+ * Validation will fail if the mode cannot be supported by the PHY driver or
+ * hardware.
+ *
+ * Return: error code.
+ */
+int dsi_phy_validate_mode(struct msm_dsi_phy *dsi_phy,
+			  struct dsi_mode_info *mode)
+{
+	int rc = 0;
+
+	if (!dsi_phy || !mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_phy->phy_lock);
+
+	pr_debug("[PHY_%d] Skipping validation\n", dsi_phy->index);
+
+	mutex_unlock(&dsi_phy->phy_lock);
+	return rc;
+}
+
+/**
+ * dsi_phy_set_power_state() - enable/disable dsi phy power supplies
+ * @dsi_phy:               DSI PHY handle.
+ * @enable:                Boolean flag to enable/disable.
+ *
+ * Return: error code.
+ */
+int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable)
+{
+	int rc = 0;
+
+	if (!dsi_phy) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&dsi_phy->phy_lock);
+
+	if (enable == dsi_phy->power_state) {
+		pr_err("[PHY_%d] No state change\n", dsi_phy->index);
+		goto error;
+	}
+
+	if (enable) {
+		rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.digital, true);
+		if (rc) {
+			pr_err("failed to enable digital regulator\n");
+			goto error;
+		}
+		rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.phy_pwr, true);
+		if (rc) {
+			pr_err("failed to enable phy power\n");
+			(void)dsi_pwr_enable_regulator(
+						&dsi_phy->pwr_info.digital,
+						false
+						);
+			goto error;
+		}
+	} else {
+		rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.phy_pwr,
+					      false);
+		if (rc) {
+			pr_err("failed to enable digital regulator\n");
+			goto error;
+		}
+		rc = dsi_pwr_enable_regulator(&dsi_phy->pwr_info.digital,
+					      false);
+		if (rc) {
+			pr_err("failed to enable phy power\n");
+			goto error;
+		}
+	}
+
+	dsi_phy->power_state = enable;
+error:
+	mutex_unlock(&dsi_phy->phy_lock);
+	return rc;
+}
+
+/**
+ * dsi_phy_enable() - enable DSI PHY hardware
+ * @dsi_phy:            DSI PHY handle.
+ * @config:             DSI host configuration.
+ * @pll_source:         Source PLL for PHY clock.
+ * @skip_validation:    Validation will not be performed on parameters.
+ *
+ * Validates and enables DSI PHY.
+ *
+ * Return: error code.
+ */
+int dsi_phy_enable(struct msm_dsi_phy *phy,
+		   struct dsi_host_config *config,
+		   enum dsi_phy_pll_source pll_source,
+		   bool skip_validation)
+{
+	int rc = 0;
+
+	if (!phy || !config) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&phy->phy_lock);
+
+	if (!skip_validation)
+		pr_debug("[PHY_%d] TODO: perform validation\n", phy->index);
+
+	rc = dsi_clk_enable_core_clks(&phy->clks.core_clks, true);
+	if (rc) {
+		pr_err("failed to enable core clocks, rc=%d\n", rc);
+		goto error;
+	}
+
+	memcpy(&phy->mode, &config->video_timing, sizeof(phy->mode));
+	phy->data_lanes = config->common_config.data_lanes;
+	phy->dst_format = config->common_config.dst_format;
+	phy->lane_map = config->lane_map;
+	phy->cfg.pll_source = pll_source;
+
+	rc = phy->hw.ops.calculate_timing_params(&phy->hw,
+						 &phy->mode,
+						 &config->common_config,
+						 &phy->cfg.timing);
+	if (rc) {
+		pr_err("[%s] failed to set timing, rc=%d\n", phy->name, rc);
+		goto error_disable_clks;
+	}
+
+	dsi_phy_enable_hw(phy);
+
+error_disable_clks:
+	rc = dsi_clk_enable_core_clks(&phy->clks.core_clks, false);
+	if (rc) {
+		pr_err("failed to disable clocks, skip phy disable\n");
+		goto error;
+	}
+error:
+	mutex_unlock(&phy->phy_lock);
+	return rc;
+}
+
+/**
+ * dsi_phy_disable() - disable DSI PHY hardware.
+ * @phy:        DSI PHY handle.
+ *
+ * Return: error code.
+ */
+int dsi_phy_disable(struct msm_dsi_phy *phy)
+{
+	int rc = 0;
+
+	if (!phy) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&phy->phy_lock);
+
+	rc = dsi_clk_enable_core_clks(&phy->clks.core_clks, true);
+	if (rc) {
+		pr_err("failed to enable core clocks, rc=%d\n", rc);
+		goto error;
+	}
+
+	dsi_phy_disable_hw(phy);
+
+	rc = dsi_clk_enable_core_clks(&phy->clks.core_clks, false);
+	if (rc) {
+		pr_err("failed to disable core clocks, rc=%d\n", rc);
+		goto error;
+	}
+
+error:
+	mutex_unlock(&phy->phy_lock);
+	return rc;
+}
+
+/**
+ * dsi_phy_set_timing_params() - timing parameters for the panel
+ * @phy:          DSI PHY handle
+ * @timing:       array holding timing params.
+ * @size:         size of the array.
+ *
+ * When PHY timing calculator is not implemented, this array will be used to
+ * pass PHY timing information.
+ *
+ * Return: error code.
+ */
+int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
+			      u8 *timing, u32 size)
+{
+	int rc = 0;
+	int i, j;
+	struct dsi_phy_per_lane_cfgs *timing_cfg;
+
+	if (!phy || !timing || !size) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&phy->phy_lock);
+
+	if (size != (DSI_LANE_MAX * phy->cfg.timing.count_per_lane)) {
+		pr_err("Unexpected timing array size %d\n", size);
+		rc = -EINVAL;
+	} else {
+		timing_cfg = &phy->cfg.timing;
+		for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
+			for (j = 0; j < timing_cfg->count_per_lane; j++) {
+				timing_cfg->lane[i][j] = *timing;
+				timing++;
+			}
+		}
+	}
+	mutex_unlock(&phy->phy_lock);
+	return rc;
+}
+
+void __init dsi_phy_drv_register(void)
+{
+	platform_driver_register(&dsi_phy_platform_driver);
+}
+
+void __exit dsi_phy_drv_unregister(void)
+{
+	platform_driver_unregister(&dsi_phy_platform_driver);
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h
new file mode 100644
index 000000000000..6c31bfa3ea00
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DSI_PHY_H_
+#define _DSI_PHY_H_
+
+#include "dsi_defs.h"
+#include "dsi_clk_pwr.h"
+#include "dsi_phy_hw.h"
+
+struct dsi_ver_spec_info {
+	enum dsi_phy_version version;
+	u32 lane_cfg_count;
+	u32 strength_cfg_count;
+	u32 regulator_cfg_count;
+	u32 timing_cfg_count;
+};
+
+/**
+ * struct dsi_phy_clk_info - clock information for DSI controller
+ * @core_clks:         Core clocks needed to access PHY registers.
+ */
+struct dsi_phy_clk_info {
+	struct dsi_core_clk_info core_clks;
+};
+
+/**
+ * struct dsi_phy_power_info - digital and analog power supplies for DSI PHY
+ * @digital:       Digital power supply for DSI PHY.
+ * @phy_pwr:       Analog power supplies for DSI PHY to work.
+ */
+struct dsi_phy_power_info {
+	struct dsi_regulator_info digital;
+	struct dsi_regulator_info phy_pwr;
+};
+
+/**
+ * struct msm_dsi_phy - DSI PHY object
+ * @pdev:              Pointer to platform device.
+ * @index:             Instance id.
+ * @name:              Name of the PHY instance.
+ * @refcount:          Reference count.
+ * @phy_lock:          Mutex for hardware and object access.
+ * @ver_info:          Version specific phy parameters.
+ * @hw:                DSI PHY hardware object.
+ * @cfg:               DSI phy configuration.
+ * @power_state:       True if PHY is powered on.
+ * @mode:              Current mode.
+ * @data_lanes:        Number of data lanes used.
+ * @dst_format:        Destination format.
+ * @lane_map:          Map between logical and physical lanes.
+ */
+struct msm_dsi_phy {
+	struct platform_device *pdev;
+	int index;
+	const char *name;
+	u32 refcount;
+	struct mutex phy_lock;
+
+	const struct dsi_ver_spec_info *ver_info;
+	struct dsi_phy_hw hw;
+
+	struct dsi_phy_clk_info clks;
+	struct dsi_phy_power_info pwr_info;
+
+	struct dsi_phy_cfg cfg;
+
+	bool power_state;
+	struct dsi_mode_info mode;
+	enum dsi_data_lanes data_lanes;
+	enum dsi_pixel_format dst_format;
+	struct dsi_lane_mapping lane_map;
+};
+
+/**
+ * dsi_phy_get() - get a dsi phy handle from device node
+ * @of_node:           device node for dsi phy controller
+ *
+ * Gets the DSI PHY handle for the corresponding of_node. The ref count is
+ * incremented to one all subsequents get will fail until the original client
+ * calls a put.
+ *
+ * Return: DSI PHY handle or an error code.
+ */
+struct msm_dsi_phy *dsi_phy_get(struct device_node *of_node);
+
+/**
+ * dsi_phy_put() - release dsi phy handle
+ * @dsi_phy:              DSI PHY handle.
+ *
+ * Release the DSI PHY hardware. Driver will clean up all resources and puts
+ * back the DSI PHY into reset state.
+ */
+void dsi_phy_put(struct msm_dsi_phy *dsi_phy);
+
+/**
+ * dsi_phy_drv_init() - initialize dsi phy driver
+ * @dsi_phy:         DSI PHY handle.
+ *
+ * Initializes DSI PHY driver. Should be called after dsi_phy_get().
+ *
+ * Return: error code.
+ */
+int dsi_phy_drv_init(struct msm_dsi_phy *dsi_phy);
+
+/**
+ * dsi_phy_drv_deinit() - de-initialize dsi phy driver
+ * @dsi_phy:          DSI PHY handle.
+ *
+ * Release all resources acquired by dsi_phy_drv_init().
+ *
+ * Return: error code.
+ */
+int dsi_phy_drv_deinit(struct msm_dsi_phy *dsi_phy);
+
+/**
+ * dsi_phy_validate_mode() - validate a display mode
+ * @dsi_phy:            DSI PHY handle.
+ * @mode:               Mode information.
+ *
+ * Validation will fail if the mode cannot be supported by the PHY driver or
+ * hardware.
+ *
+ * Return: error code.
+ */
+int dsi_phy_validate_mode(struct msm_dsi_phy *dsi_phy,
+			  struct dsi_mode_info *mode);
+
+/**
+ * dsi_phy_set_power_state() - enable/disable dsi phy power supplies
+ * @dsi_phy:               DSI PHY handle.
+ * @enable:                Boolean flag to enable/disable.
+ *
+ * Return: error code.
+ */
+int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable);
+
+/**
+ * dsi_phy_enable() - enable DSI PHY hardware
+ * @dsi_phy:            DSI PHY handle.
+ * @config:             DSI host configuration.
+ * @pll_source:         Source PLL for PHY clock.
+ * @skip_validation:    Validation will not be performed on parameters.
+ *
+ * Validates and enables DSI PHY.
+ *
+ * Return: error code.
+ */
+int dsi_phy_enable(struct msm_dsi_phy *dsi_phy,
+		   struct dsi_host_config *config,
+		   enum dsi_phy_pll_source pll_source,
+		   bool skip_validation);
+
+/**
+ * dsi_phy_disable() - disable DSI PHY hardware.
+ * @phy:        DSI PHY handle.
+ *
+ * Return: error code.
+ */
+int dsi_phy_disable(struct msm_dsi_phy *phy);
+
+/**
+ * dsi_phy_set_timing_params() - timing parameters for the panel
+ * @phy:          DSI PHY handle
+ * @timing:       array holding timing params.
+ * @size:         size of the array.
+ *
+ * When PHY timing calculator is not implemented, this array will be used to
+ * pass PHY timing information.
+ *
+ * Return: error code.
+ */
+int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
+			      u8 *timing, u32 size);
+
+/**
+ * dsi_phy_drv_register() - register platform driver for dsi phy
+ */
+void dsi_phy_drv_register(void);
+
+/**
+ * dsi_phy_drv_unregister() - unregister platform driver
+ */
+void dsi_phy_drv_unregister(void);
+
+#endif /* _DSI_PHY_H_ */
-- 
cgit v1.2.3


From 7b778d492026b62b96dbfc145a70b8af50dfab41 Mon Sep 17 00:00:00 2001
From: Ajay Singh Parmar <aparmar@codeaurora.org>
Date: Mon, 16 May 2016 17:55:52 -0700
Subject: drm/msm/dsi-staging: add dsi display driver

Add dsi display driver. Configure all internal DSI modules.
Manage power sequence for internal modules like controller
and phy. Configure lanes, modes etc.

Change-Id: I8edc918c4858f16d32af9373fc4626066b20d2e5
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
---
 .../devicetree/bindings/drm/msm/sde-dsi.txt        |    3 +
 drivers/gpu/drm/msm/dsi-staging/dsi_display.c      | 1989 ++++++++++++++++++++
 drivers/gpu/drm/msm/dsi-staging/dsi_display.h      |  407 ++++
 3 files changed, 2399 insertions(+)
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_display.c
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_display.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
index cdeb37be498d..52482a198088 100644
--- a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
@@ -57,6 +57,9 @@ Bus Scaling Data:
 Optional properties:
 - label:                  String to describe controller.
 - qcom,platform-te-gpio:  Specifies the gpio used for TE.
+- qcom,dsi-display-active: Current active display
+- qcom,dsi-ctrl: handle to dsi controller device
+- qcom,dsi-phy: handle to dsi phy device
 - qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the
 					a particular "type" of DSI module. The module "types"
 					can be "core", "ctrl", and "phy". Within the same type,
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
new file mode 100644
index 000000000000..68e3b52c8605
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -0,0 +1,1989 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"msm-dsi-display:[%s] " fmt, __func__
+
+#include <linux/list.h>
+#include <linux/of.h>
+
+#include "msm_drv.h"
+#include "dsi_display.h"
+#include "dsi_panel.h"
+#include "dsi_ctrl.h"
+#include "dsi_ctrl_hw.h"
+#include "dsi_drm.h"
+
+#define to_dsi_display(x) container_of(x, struct dsi_display, host)
+
+static DEFINE_MUTEX(dsi_display_list_lock);
+static LIST_HEAD(dsi_display_list);
+
+static struct dsi_display *main_display;
+
+static int dsi_display_ctrl_power_on(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/* Sequence does not matter for split dsi usecases */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl)
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_VREG_ON);
+		if (rc) {
+			pr_err("[%s] Failed to set power state, rc=%d\n",
+			       ctrl->ctrl->name, rc);
+			goto error;
+		}
+	}
+
+	return rc;
+error:
+	for (i = i - 1; i >= 0; i--) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl)
+			continue;
+		(void)dsi_ctrl_set_power_state(ctrl->ctrl, DSI_CTRL_POWER_OFF);
+	}
+	return rc;
+}
+
+static int dsi_display_ctrl_power_off(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/* Sequence does not matter for split dsi usecases */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl)
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl, DSI_CTRL_POWER_OFF);
+		if (rc) {
+			pr_err("[%s] Failed to power off, rc=%d\n",
+			       ctrl->ctrl->name, rc);
+			goto error;
+		}
+	}
+error:
+	return rc;
+}
+
+static int dsi_display_phy_power_on(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/* Sequence does not matter for split dsi usecases */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl)
+			continue;
+
+		rc = dsi_phy_set_power_state(ctrl->phy, true);
+		if (rc) {
+			pr_err("[%s] Failed to set power state, rc=%d\n",
+			       ctrl->phy->name, rc);
+			goto error;
+		}
+	}
+
+	return rc;
+error:
+	for (i = i - 1; i >= 0; i--) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->phy)
+			continue;
+		(void)dsi_phy_set_power_state(ctrl->phy, false);
+	}
+	return rc;
+}
+
+static int dsi_display_phy_power_off(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/* Sequence does not matter for split dsi usecases */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->phy)
+			continue;
+
+		rc = dsi_phy_set_power_state(ctrl->phy, false);
+		if (rc) {
+			pr_err("[%s] Failed to power off, rc=%d\n",
+			       ctrl->ctrl->name, rc);
+			goto error;
+		}
+	}
+error:
+	return rc;
+}
+
+static int dsi_display_ctrl_core_clk_on(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	/*
+	 * In case of split DSI usecases, the clock for master controller should
+	 * be enabled before the other controller. Master controller in the
+	 * clock context refers to the controller that sources the clock.
+	 */
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_CORE_CLK_ON);
+	if (rc) {
+		pr_err("[%s] failed to turn on clocks, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	/* Turn on rest of the controllers */
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_CORE_CLK_ON);
+		if (rc) {
+			pr_err("[%s] failed to turn on clock, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_VREG_ON);
+error:
+	return rc;
+}
+
+static int dsi_display_ctrl_link_clk_on(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	/*
+	 * In case of split DSI usecases, the clock for master controller should
+	 * be enabled before the other controller. Master controller in the
+	 * clock context refers to the controller that sources the clock.
+	 */
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,
+				       &display->clock_info.src_clks);
+	if (rc) {
+		pr_err("[%s] failed to set source clocks for master, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_LINK_CLK_ON);
+	if (rc) {
+		pr_err("[%s] failed to turn on clocks, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	/* Turn on rest of the controllers */
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_clock_source(ctrl->ctrl,
+					       &display->clock_info.src_clks);
+		if (rc) {
+			pr_err("[%s] failed to set source clocks, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_LINK_CLK_ON);
+		if (rc) {
+			pr_err("[%s] failed to turn on clock, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_power_state(m_ctrl->ctrl,
+				       DSI_CTRL_POWER_CORE_CLK_ON);
+error:
+	return rc;
+}
+
+static int dsi_display_ctrl_core_clk_off(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	/*
+	 * In case of split DSI usecases, clock for slave DSI controllers should
+	 * be disabled first before disabling clock for master controller. Slave
+	 * controllers in the clock context refer to controller which source
+	 * clock from another controller.
+	 */
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_VREG_ON);
+		if (rc) {
+			pr_err("[%s] failed to turn off clock, rc=%d\n",
+			       display->name, rc);
+		}
+	}
+
+	rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_VREG_ON);
+	if (rc)
+		pr_err("[%s] failed to turn off clocks, rc=%d\n",
+		       display->name, rc);
+
+	return rc;
+}
+
+static int dsi_display_ctrl_link_clk_off(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	/*
+	 * In case of split DSI usecases, clock for slave DSI controllers should
+	 * be disabled first before disabling clock for master controller. Slave
+	 * controllers in the clock context refer to controller which source
+	 * clock from another controller.
+	 */
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_power_state(ctrl->ctrl,
+					      DSI_CTRL_POWER_CORE_CLK_ON);
+		if (rc) {
+			pr_err("[%s] failed to turn off clock, rc=%d\n",
+			       display->name, rc);
+		}
+	}
+	rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_CORE_CLK_ON);
+	if (rc)
+		pr_err("[%s] failed to turn off clocks, rc=%d\n",
+		       display->name, rc);
+	return rc;
+}
+
+static int dsi_display_ctrl_init(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	for (i = 0 ; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_host_init(ctrl->ctrl);
+		if (rc) {
+			pr_err("[%s] failed to init host_%d, rc=%d\n",
+			       display->name, i, rc);
+			goto error_host_deinit;
+		}
+	}
+
+	return 0;
+error_host_deinit:
+	for (i = i - 1; i >= 0; i--) {
+		ctrl = &display->ctrl[i];
+		(void)dsi_ctrl_host_deinit(ctrl->ctrl);
+	}
+	return rc;
+}
+
+static int dsi_display_ctrl_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	for (i = 0 ; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_host_deinit(ctrl->ctrl);
+		if (rc) {
+			pr_err("[%s] failed to deinit host_%d, rc=%d\n",
+			       display->name, i, rc);
+		}
+	}
+
+	return rc;
+}
+
+static int dsi_display_cmd_engine_enable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+
+	rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
+	if (rc) {
+		pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
+						   DSI_CTRL_ENGINE_ON);
+		if (rc) {
+			pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+error:
+	return rc;
+}
+
+static int dsi_display_cmd_engine_disable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
+						   DSI_CTRL_ENGINE_OFF);
+		if (rc)
+			pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+			       display->name, rc);
+	}
+
+	rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+	if (rc) {
+		pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_display_ctrl_host_enable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+
+	rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
+	if (rc) {
+		pr_err("[%s] failed to enable host engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
+						    DSI_CTRL_ENGINE_ON);
+		if (rc) {
+			pr_err("[%s] failed to enable sl host engine, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+error:
+	return rc;
+}
+
+static int dsi_display_ctrl_host_disable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
+						    DSI_CTRL_ENGINE_OFF);
+		if (rc)
+			pr_err("[%s] failed to disable host engine, rc=%d\n",
+			       display->name, rc);
+	}
+
+	rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+	if (rc) {
+		pr_err("[%s] failed to disable host engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_display_vid_engine_enable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->video_master_idx];
+
+	rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_ON);
+	if (rc) {
+		pr_err("[%s] failed to enable vid engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
+						   DSI_CTRL_ENGINE_ON);
+		if (rc) {
+			pr_err("[%s] failed to enable vid engine, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+
+	return rc;
+error_disable_master:
+	(void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+error:
+	return rc;
+}
+
+static int dsi_display_vid_engine_disable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->video_master_idx];
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
+						   DSI_CTRL_ENGINE_OFF);
+		if (rc)
+			pr_err("[%s] failed to disable vid engine, rc=%d\n",
+			       display->name, rc);
+	}
+
+	rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl, DSI_CTRL_ENGINE_OFF);
+	if (rc)
+		pr_err("[%s] failed to disable mvid engine, rc=%d\n",
+		       display->name, rc);
+
+	return rc;
+}
+
+static int dsi_display_phy_enable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+	enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+	if (display->ctrl_count > 1)
+		m_src = DSI_PLL_SOURCE_NATIVE;
+
+	rc = dsi_phy_enable(m_ctrl->phy,
+			    &display->config,
+			    m_src,
+			    true);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI PHY, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_phy_enable(ctrl->phy,
+				    &display->config,
+				    DSI_PLL_SOURCE_NON_NATIVE,
+				    true);
+		if (rc) {
+			pr_err("[%s] failed to enable DSI PHY, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_master;
+		}
+	}
+
+	return rc;
+
+error_disable_master:
+	(void)dsi_phy_disable(m_ctrl->phy);
+error:
+	return rc;
+}
+
+static int dsi_display_phy_disable(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->clk_master_idx];
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_phy_disable(ctrl->phy);
+		if (rc)
+			pr_err("[%s] failed to disable DSI PHY, rc=%d\n",
+			       display->name, rc);
+	}
+
+	rc = dsi_phy_disable(m_ctrl->phy);
+	if (rc)
+		pr_err("[%s] failed to disable DSI PHY, rc=%d\n",
+		       display->name, rc);
+
+	return rc;
+}
+
+static int dsi_display_wake_up(struct dsi_display *display)
+{
+	return 0;
+}
+
+static int dsi_display_broadcast_cmd(struct dsi_display *display,
+				     const struct mipi_dsi_msg *msg)
+{
+	int rc = 0;
+	u32 flags, m_flags;
+	struct dsi_display_ctrl *ctrl, *m_ctrl;
+	int i;
+
+	m_flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_BROADCAST_MASTER |
+		   DSI_CTRL_CMD_DEFER_TRIGGER | DSI_CTRL_CMD_FIFO_STORE);
+	flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER |
+		 DSI_CTRL_CMD_FIFO_STORE);
+
+	/*
+	 * 1. Setup commands in FIFO
+	 * 2. Trigger commands
+	 */
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+	rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, msg, m_flags);
+	if (rc) {
+		pr_err("[%s] cmd transfer failed on master,rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (ctrl == m_ctrl)
+			continue;
+
+		rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, msg, flags);
+		if (rc) {
+			pr_err("[%s] cmd transfer failed, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+
+		rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl,
+			DSI_CTRL_CMD_BROADCAST);
+		if (rc) {
+			pr_err("[%s] cmd trigger failed, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+	}
+
+	rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl,
+				(DSI_CTRL_CMD_BROADCAST_MASTER |
+				 DSI_CTRL_CMD_BROADCAST));
+	if (rc) {
+		pr_err("[%s] cmd trigger failed for master, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_display_phy_sw_reset(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *m_ctrl, *ctrl;
+
+	m_ctrl = &display->ctrl[display->cmd_master_idx];
+
+	rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
+	if (rc) {
+		pr_err("[%s] failed to reset phy, rc=%d\n", display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if (!ctrl->ctrl || (ctrl == m_ctrl))
+			continue;
+
+		rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
+		if (rc) {
+			pr_err("[%s] failed to reset phy, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_host_attach(struct mipi_dsi_host *host,
+			   struct mipi_dsi_device *dsi)
+{
+	return 0;
+}
+
+static int dsi_host_detach(struct mipi_dsi_host *host,
+			   struct mipi_dsi_device *dsi)
+{
+	return 0;
+}
+
+static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
+				 const struct mipi_dsi_msg *msg)
+{
+	struct dsi_display *display = to_dsi_display(host);
+
+	int rc = 0;
+
+	if (!host || !msg) {
+		pr_err("Invalid params\n");
+		return 0;
+	}
+
+	rc = dsi_display_wake_up(display);
+	if (rc) {
+		pr_err("[%s] failed to wake up display, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	rc = dsi_display_cmd_engine_enable(display);
+	if (rc) {
+		pr_err("[%s] failed to enable cmd engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	if (display->ctrl_count > 1) {
+		rc = dsi_display_broadcast_cmd(display, msg);
+		if (rc) {
+			pr_err("[%s] cmd broadcast failed, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_cmd_engine;
+		}
+	} else {
+		rc = dsi_ctrl_cmd_transfer(display->ctrl[0].ctrl, msg,
+					  DSI_CTRL_CMD_FIFO_STORE);
+		if (rc) {
+			pr_err("[%s] cmd transfer failed, rc=%d\n",
+			       display->name, rc);
+			goto error_disable_cmd_engine;
+		}
+	}
+error_disable_cmd_engine:
+	(void)dsi_display_cmd_engine_disable(display);
+error:
+	return rc;
+}
+
+
+static struct mipi_dsi_host_ops dsi_host_ops = {
+	.attach = dsi_host_attach,
+	.detach = dsi_host_detach,
+	.transfer = dsi_host_transfer,
+};
+
+static int dsi_display_mipi_host_init(struct dsi_display *display)
+{
+	int rc = 0;
+	struct mipi_dsi_host *host = &display->host;
+
+	host->dev = &display->pdev->dev;
+	host->ops = &dsi_host_ops;
+
+	rc = mipi_dsi_host_register(host);
+	if (rc) {
+		pr_err("[%s] failed to register mipi dsi host, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+error:
+	return rc;
+}
+static int dsi_display_mipi_host_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+	struct mipi_dsi_host *host = &display->host;
+
+	mipi_dsi_host_unregister(host);
+
+	host->dev = NULL;
+	host->ops = NULL;
+
+	return rc;
+}
+
+static int dsi_display_clocks_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+	struct dsi_clk_link_set *src = &display->clock_info.src_clks;
+	struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
+	struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
+
+	if (src->byte_clk) {
+		devm_clk_put(&display->pdev->dev, src->byte_clk);
+		src->byte_clk = NULL;
+	}
+
+	if (src->pixel_clk) {
+		devm_clk_put(&display->pdev->dev, src->pixel_clk);
+		src->pixel_clk = NULL;
+	}
+
+	if (mux->byte_clk) {
+		devm_clk_put(&display->pdev->dev, mux->byte_clk);
+		mux->byte_clk = NULL;
+	}
+
+	if (mux->pixel_clk) {
+		devm_clk_put(&display->pdev->dev, mux->pixel_clk);
+		mux->pixel_clk = NULL;
+	}
+
+	if (shadow->byte_clk) {
+		devm_clk_put(&display->pdev->dev, shadow->byte_clk);
+		shadow->byte_clk = NULL;
+	}
+
+	if (shadow->pixel_clk) {
+		devm_clk_put(&display->pdev->dev, shadow->pixel_clk);
+		shadow->pixel_clk = NULL;
+	}
+
+	return rc;
+}
+
+static int dsi_display_clocks_init(struct dsi_display *display)
+{
+	int rc = 0;
+	struct dsi_clk_link_set *src = &display->clock_info.src_clks;
+	struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
+	struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
+
+	src->byte_clk = devm_clk_get(&display->pdev->dev, "src_byte_clk");
+	if (IS_ERR_OR_NULL(src->byte_clk)) {
+		rc = PTR_ERR(src->byte_clk);
+		pr_err("failed to get src_byte_clk, rc=%d\n", rc);
+		goto error;
+	}
+
+	src->pixel_clk = devm_clk_get(&display->pdev->dev, "src_pixel_clk");
+	if (IS_ERR_OR_NULL(src->pixel_clk)) {
+		rc = PTR_ERR(src->pixel_clk);
+		pr_err("failed to get src_pixel_clk, rc=%d\n", rc);
+		goto error;
+	}
+
+	mux->byte_clk = devm_clk_get(&display->pdev->dev, "mux_byte_clk");
+	if (IS_ERR_OR_NULL(mux->byte_clk)) {
+		rc = PTR_ERR(mux->byte_clk);
+		pr_err("failed to get mux_byte_clk, rc=%d\n", rc);
+		/*
+		 * Skip getting rest of clocks since one failed. This is a
+		 * non-critical failure since these clocks are requied only for
+		 * dynamic refresh use cases.
+		 */
+		rc = 0;
+		goto done;
+	};
+
+	mux->pixel_clk = devm_clk_get(&display->pdev->dev, "mux_pixel_clk");
+	if (IS_ERR_OR_NULL(mux->pixel_clk)) {
+		rc = PTR_ERR(mux->pixel_clk);
+		pr_err("failed to get mux_pixel_clk, rc=%d\n", rc);
+		/*
+		 * Skip getting rest of clocks since one failed. This is a
+		 * non-critical failure since these clocks are requied only for
+		 * dynamic refresh use cases.
+		 */
+		rc = 0;
+		goto done;
+	};
+
+	shadow->byte_clk = devm_clk_get(&display->pdev->dev, "shadow_byte_clk");
+	if (IS_ERR_OR_NULL(shadow->byte_clk)) {
+		rc = PTR_ERR(shadow->byte_clk);
+		pr_err("failed to get shadow_byte_clk, rc=%d\n", rc);
+		/*
+		 * Skip getting rest of clocks since one failed. This is a
+		 * non-critical failure since these clocks are requied only for
+		 * dynamic refresh use cases.
+		 */
+		rc = 0;
+		goto done;
+	};
+
+	shadow->pixel_clk = devm_clk_get(&display->pdev->dev,
+					 "shadow_pixel_clk");
+	if (IS_ERR_OR_NULL(shadow->pixel_clk)) {
+		rc = PTR_ERR(shadow->pixel_clk);
+		pr_err("failed to get shadow_pixel_clk, rc=%d\n", rc);
+		/*
+		 * Skip getting rest of clocks since one failed. This is a
+		 * non-critical failure since these clocks are requied only for
+		 * dynamic refresh use cases.
+		 */
+		rc = 0;
+		goto done;
+	};
+
+done:
+	return 0;
+error:
+	(void)dsi_display_clocks_deinit(display);
+	return rc;
+}
+
+static int dsi_display_parse_lane_map(struct dsi_display *display)
+{
+	int rc = 0;
+
+	display->lane_map.physical_lane0 = DSI_LOGICAL_LANE_0;
+	display->lane_map.physical_lane1 = DSI_LOGICAL_LANE_1;
+	display->lane_map.physical_lane2 = DSI_LOGICAL_LANE_2;
+	display->lane_map.physical_lane3 = DSI_LOGICAL_LANE_3;
+	return rc;
+}
+
+static int dsi_display_parse_dt(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	u32 phy_count = 0;
+	struct device_node *of_node;
+
+	/* Parse controllers */
+	for (i = 0; i < MAX_DSI_CTRLS_PER_DISPLAY; i++) {
+		of_node = of_parse_phandle(display->pdev->dev.of_node,
+					   "qcom,dsi-ctrl", i);
+		if (!of_node) {
+			if (!i) {
+				pr_err("No controllers present\n");
+				return -ENODEV;
+			}
+			break;
+		}
+
+		display->ctrl[i].ctrl_of_node = of_node;
+		display->ctrl_count++;
+	}
+
+	/* Parse Phys */
+	for (i = 0; i < MAX_DSI_CTRLS_PER_DISPLAY; i++) {
+		of_node = of_parse_phandle(display->pdev->dev.of_node,
+					   "qcom,dsi-phy", i);
+		if (!of_node) {
+			if (!i) {
+				pr_err("No PHY devices present\n");
+				rc = -ENODEV;
+				goto error;
+			}
+			break;
+		}
+
+		display->ctrl[i].phy_of_node = of_node;
+		phy_count++;
+	}
+
+	if (phy_count != display->ctrl_count) {
+		pr_err("Number of controllers does not match PHYs\n");
+		rc = -ENODEV;
+		goto error;
+	}
+
+	of_node = of_parse_phandle(display->pdev->dev.of_node,
+				   "qcom,dsi-panel", 0);
+	if (!of_node) {
+		pr_err("No Panel device present\n");
+		rc = -ENODEV;
+		goto error;
+	} else {
+		display->panel_of = of_node;
+	}
+
+	rc = dsi_display_parse_lane_map(display);
+	if (rc) {
+		pr_err("Lane map not found, rc=%d\n", rc);
+		goto error;
+	}
+error:
+	return rc;
+}
+
+static int dsi_display_res_init(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
+		if (IS_ERR_OR_NULL(ctrl->ctrl)) {
+			rc = PTR_ERR(ctrl->ctrl);
+			pr_err("failed to get dsi controller, rc=%d\n", rc);
+			ctrl->ctrl = NULL;
+			goto error_ctrl_put;
+		}
+
+		ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
+		if (IS_ERR_OR_NULL(ctrl->phy)) {
+			rc = PTR_ERR(ctrl->phy);
+			pr_err("failed to get phy controller, rc=%d\n", rc);
+			dsi_ctrl_put(ctrl->ctrl);
+			ctrl->phy = NULL;
+			goto error_ctrl_put;
+		}
+	}
+
+	display->panel = dsi_panel_get(&display->pdev->dev, display->panel_of);
+	if (IS_ERR_OR_NULL(display->panel)) {
+		rc = PTR_ERR(display->panel);
+		pr_err("failed to get panel, rc=%d\n", rc);
+		display->panel = NULL;
+		goto error_ctrl_put;
+	}
+
+	rc = dsi_display_clocks_init(display);
+	if (rc) {
+		pr_err("Failed to parse clock data, rc=%d\n", rc);
+		goto error_ctrl_put;
+	}
+
+	return 0;
+error_ctrl_put:
+	for (i = i - 1; i >= 0; i--) {
+		ctrl = &display->ctrl[i];
+		dsi_ctrl_put(ctrl->ctrl);
+		dsi_phy_put(ctrl->phy);
+	}
+	return rc;
+}
+
+static int dsi_display_res_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	rc = dsi_display_clocks_deinit(display);
+	if (rc)
+		pr_err("clocks deinit failed, rc=%d\n", rc);
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		dsi_phy_put(ctrl->phy);
+		dsi_ctrl_put(ctrl->ctrl);
+	}
+
+	return rc;
+}
+
+static int dsi_display_validate_mode_set(struct dsi_display *display,
+					 struct dsi_display_mode *mode,
+					 u32 flags)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	/*
+	 * To set a mode:
+	 * 1. Controllers should be turned off.
+	 * 2. Link clocks should be off.
+	 * 3. Phy should be disabled.
+	 */
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
+		    (ctrl->phy_enabled)) {
+			rc = -EINVAL;
+			goto error;
+		}
+	}
+
+error:
+	return rc;
+}
+
+static int dsi_display_set_mode_sub(struct dsi_display *display,
+				    struct dsi_display_mode *mode,
+				    u32 flags)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	rc = dsi_panel_get_host_cfg_for_mode(display->panel,
+					     mode,
+					     &display->config);
+	if (rc) {
+		pr_err("[%s] failed to get host config for mode, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	memcpy(&display->config.lane_map, &display->lane_map,
+	       sizeof(display->lane_map));
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config);
+		if (rc) {
+			pr_err("[%s] failed to update ctrl config, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+
+	}
+error:
+	return rc;
+}
+
+int dsi_display_dev_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct dsi_display *display;
+
+	if (!pdev || !pdev->dev.of_node) {
+		pr_err("pdev not found\n");
+		return -ENODEV;
+	}
+
+	display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
+	if (!display)
+		return -ENOMEM;
+
+	display->name = of_get_property(pdev->dev.of_node, "label", NULL);
+
+	display->is_active = of_property_read_bool(pdev->dev.of_node,
+						"qcom,dsi-display-active");
+
+	display->display_type = of_get_property(pdev->dev.of_node,
+						"qcom,display-type", NULL);
+	if (!display->display_type)
+		display->display_type = "unknown";
+
+	mutex_init(&display->display_lock);
+
+	display->pdev = pdev;
+	platform_set_drvdata(pdev, display);
+	mutex_lock(&dsi_display_list_lock);
+	list_add(&display->list, &dsi_display_list);
+	mutex_unlock(&dsi_display_list_lock);
+	if (display->is_active)
+		main_display = display;
+	return rc;
+}
+
+int dsi_display_dev_remove(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct dsi_display *display;
+	struct dsi_display *pos, *tmp;
+
+	if (!pdev) {
+		pr_err("Invalid device\n");
+		return -EINVAL;
+	}
+
+	display = platform_get_drvdata(pdev);
+
+	mutex_lock(&dsi_display_list_lock);
+	list_for_each_entry_safe(pos, tmp, &dsi_display_list, list) {
+		if (pos == display) {
+			list_del(&display->list);
+			break;
+		}
+	}
+	mutex_unlock(&dsi_display_list_lock);
+
+	platform_set_drvdata(pdev, NULL);
+	devm_kfree(&pdev->dev, display);
+	return rc;
+}
+
+u32 dsi_display_get_num_of_displays(void)
+{
+	u32 count = 0;
+	struct dsi_display *display;
+
+	mutex_lock(&dsi_display_list_lock);
+
+	list_for_each_entry(display, &dsi_display_list, list) {
+		count++;
+	}
+
+	mutex_unlock(&dsi_display_list_lock);
+	return count;
+}
+
+struct dsi_display *dsi_display_get_display_by_index(u32 index)
+{
+	struct dsi_display *display = NULL;
+	struct dsi_display *pos;
+	int i = 0;
+
+	mutex_lock(&dsi_display_list_lock);
+
+	list_for_each_entry(pos, &dsi_display_list, list) {
+		if (i == index) {
+			display = pos;
+			break;
+		}
+		i++;
+	}
+
+	mutex_unlock(&dsi_display_list_lock);
+	return display;
+}
+
+struct dsi_display *dsi_display_get_display_by_name(const char *name)
+{
+	struct dsi_display *display = NULL, *pos;
+
+	mutex_lock(&dsi_display_list_lock);
+
+	list_for_each_entry(pos, &dsi_display_list, list) {
+		if (!strcmp(name, pos->name))
+			display = pos;
+	}
+
+	mutex_unlock(&dsi_display_list_lock);
+
+	return display;
+}
+
+void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
+{
+	mutex_lock(&display->display_lock);
+	display->is_active = is_active;
+	mutex_unlock(&display->display_lock);
+}
+
+bool dsi_display_is_active(struct dsi_display *display)
+{
+	bool is_active;
+
+	mutex_lock(&display->display_lock);
+	is_active = display->is_active;
+	mutex_unlock(&display->display_lock);
+
+	return is_active;
+}
+
+int dsi_display_dev_init(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_display_parse_dt(display);
+	if (rc) {
+		pr_err("[%s] failed to parse dt, rc=%d\n", display->name, rc);
+		goto error;
+	}
+
+	rc = dsi_display_res_init(display);
+	if (rc) {
+		pr_err("[%s] failed to initialize resources, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_dev_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_display_res_deinit(display);
+	if (rc)
+		pr_err("[%s] failed to deinitialize resource, rc=%d\n",
+		       display->name, rc);
+
+	mutex_unlock(&display->display_lock);
+
+	return rc;
+}
+
+int dsi_display_bind(struct dsi_display *display, struct drm_device *dev)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *display_ctrl;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		display_ctrl = &display->ctrl[i];
+
+		rc = dsi_ctrl_drv_init(display_ctrl->ctrl);
+		if (rc) {
+			pr_err("[%s] Failed to initialize ctrl[%d], rc=%d\n",
+			       display->name, i, rc);
+			goto error_ctrl_deinit;
+		}
+
+		rc = dsi_phy_drv_init(display_ctrl->phy);
+		if (rc) {
+			pr_err("[%s] Failed to initialize phy[%d], rc=%d\n",
+				display->name, i, rc);
+			(void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
+			goto error_ctrl_deinit;
+		}
+	}
+
+	rc = dsi_display_mipi_host_init(display);
+	if (rc) {
+		pr_err("[%s] Failed to initialize mipi host, rc=%d\n",
+		       display->name, rc);
+		goto error_ctrl_deinit;
+	}
+
+	rc = dsi_panel_drv_init(display->panel, &display->host);
+	if (rc) {
+		pr_err("[%s] Failed to initialize panel driver, rc=%d\n",
+		       display->name, rc);
+		goto error_host_deinit;
+	}
+
+	rc = dsi_panel_get_mode_count(display->panel, &display->num_of_modes);
+	if (rc) {
+		pr_err("[%s] Failed to get mode count, rc=%d\n",
+		       display->name, rc);
+		goto error_panel_deinit;
+	}
+
+	display->drm_dev = dev;
+	goto error;
+
+error_panel_deinit:
+	(void)dsi_panel_drv_deinit(display->panel);
+error_host_deinit:
+	(void)dsi_display_mipi_host_deinit(display);
+error_ctrl_deinit:
+	for (i = i - 1; i >= 0; i--) {
+		display_ctrl = &display->ctrl[i];
+		(void)dsi_phy_drv_deinit(display_ctrl->phy);
+		(void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
+	}
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_unbind(struct dsi_display *display)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *display_ctrl;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_drv_deinit(display->panel);
+	if (rc)
+		pr_err("[%s] failed to deinit panel driver, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_mipi_host_deinit(display);
+	if (rc)
+		pr_err("[%s] failed to deinit mipi hosts, rc=%d\n",
+		       display->name,
+		       rc);
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		display_ctrl = &display->ctrl[i];
+
+		rc = dsi_phy_drv_deinit(display_ctrl->phy);
+		if (rc)
+			pr_err("[%s] failed to deinit phy%d driver, rc=%d\n",
+			       display->name, i, rc);
+
+		rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
+		if (rc)
+			pr_err("[%s] failed to deinit ctrl%d driver, rc=%d\n",
+			       display->name, i, rc);
+	}
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_drm_init(struct dsi_display *display, struct drm_encoder *enc)
+{
+	int rc = 0;
+	struct dsi_bridge *bridge;
+	struct dsi_connector *connector;
+	struct msm_drm_private *priv = NULL;
+
+	if (!display || !enc) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+	priv = display->drm_dev->dev_private;
+
+	if (!priv) {
+		pr_err("Private data is not present\n");
+		rc = -EINVAL;
+		goto error;
+	}
+
+	if (display->connector || display->bridge) {
+		pr_err("display is already initialize\n");
+		goto error;
+	}
+
+	bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
+	if (IS_ERR_OR_NULL(bridge)) {
+		rc = PTR_ERR(bridge);
+		pr_err("[%s] brige init failed, rc=%d\n", display->name, rc);
+		goto error;
+	}
+
+	connector = dsi_drm_connector_init(display, display->drm_dev, bridge);
+	if (IS_ERR_OR_NULL(connector)) {
+		rc = PTR_ERR(connector);
+		pr_err("[%s] connector init failed, rc=%d\n", display->name,
+		       rc);
+		goto error_bridge_deinit;
+	}
+
+	display->connector = connector;
+	priv->connectors[priv->num_connectors++] = &connector->base;
+	display->bridge = bridge;
+	priv->bridges[priv->num_bridges++] = &bridge->base;
+
+	goto error;
+error_bridge_deinit:
+	dsi_drm_bridge_cleanup(bridge);
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_drm_deinit(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	dsi_drm_connector_cleanup(display->connector);
+	dsi_drm_bridge_cleanup(display->bridge);
+	display->connector = NULL;
+	display->bridge = NULL;
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_get_info(struct dsi_display *display,
+			 struct dsi_display_info *info)
+{
+	int rc = 0;
+	int i;
+	struct dsi_panel_phy_props phy_props;
+
+	if (!display || !info) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+	rc = dsi_panel_get_phy_props(display->panel, &phy_props);
+	if (rc) {
+		pr_err("[%s] failed to get panel phy props, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	info->type = display->type;
+
+	/* TODO: do not access dsi_ctrl structure */
+	info->num_of_h_tiles = display->ctrl_count;
+	for (i = 0; i < info->num_of_h_tiles; i++)
+		info->h_tile_ids[i] = display->ctrl[i].ctrl->index;
+
+	info->is_hot_pluggable = false;
+	info->is_edid_supported = false;
+
+	info->width_mm = phy_props.panel_width_mm;
+	info->height_mm = phy_props.panel_height_mm;
+	strlcpy(info->display_type, display->display_type,
+		sizeof(display->display_type));
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_get_modes(struct dsi_display *display,
+			  struct dsi_display_mode *modes,
+			  u32 *count)
+{
+	int rc = 0;
+	int i;
+
+	if (!display || !count) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	if (!modes) {
+		*count = display->num_of_modes;
+		goto error;
+	}
+
+	for (i = 0; i < *count; i++) {
+		rc = dsi_panel_get_mode(display->panel, i, modes);
+		if (rc) {
+			pr_err("[%s] failed to get mode from panel\n",
+			       display->name);
+			goto error;
+		}
+		if (display->ctrl_count > 1) {
+			modes->timing.h_active *= display->ctrl_count;
+			modes->timing.h_front_porch *= display->ctrl_count;
+			modes->timing.h_sync_width *= display->ctrl_count;
+			modes->timing.h_back_porch *= display->ctrl_count;
+			modes->timing.h_skew *= display->ctrl_count;
+			modes->pixel_clk_khz *= display->ctrl_count;
+		}
+
+		modes++;
+	}
+
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_validate_mode(struct dsi_display *display,
+			      struct dsi_display_mode *mode)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+	struct dsi_display_mode adj_mode;
+
+	if (!display || !mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	adj_mode = *mode;
+	if (display->ctrl_count > 1) {
+		adj_mode.timing.h_active /= display->ctrl_count;
+		adj_mode.timing.h_front_porch /= display->ctrl_count;
+		adj_mode.timing.h_sync_width /= display->ctrl_count;
+		adj_mode.timing.h_back_porch /= display->ctrl_count;
+		adj_mode.timing.h_skew /= display->ctrl_count;
+		adj_mode.pixel_clk_khz /= display->ctrl_count;
+	}
+
+	rc = dsi_panel_validate_mode(display->panel, &adj_mode);
+	if (rc) {
+		pr_err("[%s] panel mode validation failed, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
+		if (rc) {
+			pr_err("[%s] ctrl mode validation failed, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+
+		rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
+		if (rc) {
+			pr_err("[%s] phy mode validation failed, rc=%d\n",
+			       display->name, rc);
+			goto error;
+		}
+	}
+
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_set_mode(struct dsi_display *display,
+			 struct dsi_display_mode *mode,
+			 u32 flags)
+{
+	int rc = 0;
+	struct dsi_display_mode adj_mode;
+
+	if (!display || !mode) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	adj_mode = *mode;
+	if (display->ctrl_count > 1) {
+		adj_mode.timing.h_active /= display->ctrl_count;
+		adj_mode.timing.h_front_porch /= display->ctrl_count;
+		adj_mode.timing.h_sync_width /= display->ctrl_count;
+		adj_mode.timing.h_back_porch /= display->ctrl_count;
+		adj_mode.timing.h_skew /= display->ctrl_count;
+		adj_mode.pixel_clk_khz /= display->ctrl_count;
+	}
+
+	rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
+	if (rc) {
+		pr_err("[%s] mode cannot be set\n", display->name);
+		goto error;
+	}
+
+	rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
+	if (rc) {
+		pr_err("[%s] failed to set mode\n", display->name);
+		goto error;
+	}
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
+{
+	int rc = 0;
+	int i;
+	struct dsi_display_ctrl *ctrl;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < display->ctrl_count; i++) {
+		ctrl = &display->ctrl[i];
+		rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
+		if (rc) {
+			pr_err("[%s] failed to set tpg state for host_%d\n",
+			       display->name, i);
+			goto error;
+		}
+	}
+
+	display->is_tpg_enabled = enable;
+error:
+	return rc;
+}
+
+int dsi_display_prepare(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_pre_prepare(display->panel);
+	if (rc) {
+		pr_err("[%s] panel pre-prepare failed, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	rc = dsi_display_ctrl_power_on(display);
+	if (rc) {
+		pr_err("[%s] failed to power on dsi controllers, rc=%d\n",
+		       display->name, rc);
+		goto error_panel_post_unprep;
+	}
+
+	rc = dsi_display_phy_power_on(display);
+	if (rc) {
+		pr_err("[%s] failed to power on dsi phy, rc = %d\n",
+		       display->name, rc);
+		goto error_ctrl_pwr_off;
+	}
+
+	rc = dsi_display_ctrl_core_clk_on(display);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI core clocks, rc=%d\n",
+		       display->name, rc);
+		goto error_phy_pwr_off;
+	}
+
+	rc = dsi_display_phy_sw_reset(display);
+	if (rc) {
+		pr_err("[%s] failed to reset phy, rc=%d\n", display->name, rc);
+		goto error_ctrl_clk_off;
+	}
+
+	rc = dsi_display_phy_enable(display);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI PHY, rc=%d\n",
+		       display->name, rc);
+		goto error_ctrl_clk_off;
+	}
+
+	rc = dsi_display_ctrl_init(display);
+	if (rc) {
+		pr_err("[%s] failed to setup DSI controller, rc=%d\n",
+		       display->name, rc);
+		goto error_phy_disable;
+	}
+
+	rc = dsi_display_ctrl_link_clk_on(display);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI link clocks, rc=%d\n",
+		       display->name, rc);
+		goto error_ctrl_deinit;
+	}
+
+	rc = dsi_display_ctrl_host_enable(display);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI host, rc=%d\n",
+		       display->name, rc);
+		goto error_ctrl_link_off;
+	}
+
+	rc = dsi_panel_prepare(display->panel);
+	if (rc) {
+		pr_err("[%s] panel prepare failed, rc=%d\n", display->name, rc);
+		goto error_host_engine_off;
+	}
+
+	goto error;
+
+error_host_engine_off:
+	(void)dsi_display_ctrl_host_disable(display);
+error_ctrl_link_off:
+	(void)dsi_display_ctrl_link_clk_off(display);
+error_ctrl_deinit:
+	(void)dsi_display_ctrl_deinit(display);
+error_phy_disable:
+	(void)dsi_display_phy_disable(display);
+error_ctrl_clk_off:
+	(void)dsi_display_ctrl_core_clk_off(display);
+error_phy_pwr_off:
+	(void)dsi_display_phy_power_off(display);
+error_ctrl_pwr_off:
+	(void)dsi_display_ctrl_power_off(display);
+error_panel_post_unprep:
+	(void)dsi_panel_post_unprepare(display->panel);
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_enable(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_enable(display->panel);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI panel, rc=%d\n",
+		       display->name, rc);
+		goto error_disable_vid_engine;
+	}
+
+	rc = dsi_display_vid_engine_enable(display);
+	if (rc) {
+		pr_err("[%s] failed to enable DSI video engine, rc=%d\n",
+		       display->name, rc);
+		goto error;
+	}
+
+	goto error;
+
+error_disable_vid_engine:
+	(void)dsi_display_vid_engine_disable(display);
+error:
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_post_enable(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_post_enable(display->panel);
+	if (rc)
+		pr_err("[%s] panel post-enable failed, rc=%d\n",
+		       display->name, rc);
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_pre_disable(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_panel_pre_disable(display->panel);
+	if (rc)
+		pr_err("[%s] panel pre-disable failed, rc=%d\n",
+		       display->name, rc);
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_disable(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_display_wake_up(display);
+	if (rc)
+		pr_err("[%s] display wake up failed, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_panel_disable(display->panel);
+	if (rc)
+		pr_err("[%s] failed to disable DSI panel, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_vid_engine_disable(display);
+	if (rc)
+		pr_err("[%s] failed to disable video engine, rc=%d\n",
+		       display->name, rc);
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
+
+int dsi_display_unprepare(struct dsi_display *display)
+{
+	int rc = 0;
+
+	if (!display) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&display->display_lock);
+
+	rc = dsi_display_wake_up(display);
+	if (rc)
+		pr_err("[%s] display wake up failed, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_panel_unprepare(display->panel);
+	if (rc)
+		pr_err("[%s] panel unprepare failed, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_host_disable(display);
+	if (rc)
+		pr_err("[%s] failed to disable DSI host, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_link_clk_off(display);
+	if (rc)
+		pr_err("[%s] failed to disable Link clocks, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_deinit(display);
+	if (rc)
+		pr_err("[%s] failed to deinit controller, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_phy_disable(display);
+	if (rc)
+		pr_err("[%s] failed to disable DSI PHY, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_core_clk_off(display);
+	if (rc)
+		pr_err("[%s] failed to disable DSI clocks, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_phy_power_off(display);
+	if (rc)
+		pr_err("[%s] failed to power off PHY, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_display_ctrl_power_off(display);
+	if (rc)
+		pr_err("[%s] failed to power DSI vregs, rc=%d\n",
+		       display->name, rc);
+
+	rc = dsi_panel_post_unprepare(display->panel);
+	if (rc)
+		pr_err("[%s] panel post-unprepare failed, rc=%d\n",
+		       display->name, rc);
+
+	mutex_unlock(&display->display_lock);
+	return rc;
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
new file mode 100644
index 000000000000..df15bb84270f
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
@@ -0,0 +1,407 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DSI_DISPLAY_H_
+#define _DSI_DISPLAY_H_
+
+#include <linux/types.h>
+#include <linux/bitops.h>
+#include <linux/of_device.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+
+#include "dsi_defs.h"
+#include "dsi_ctrl.h"
+#include "dsi_phy.h"
+#include "dsi_panel.h"
+
+#define MAX_DSI_CTRLS_PER_DISPLAY             2
+
+/**
+ * enum dsi_display_type - enumerates DSI display types
+ * @DSI_DISPLAY_SINGLE:       A panel connected on a single DSI interface.
+ * @DSI_DISPLAY_EXT_BRIDGE:   A bridge is connected between panel and DSI host.
+ *			      It utilizes a single DSI interface.
+ * @DSI_DISPLAY_SPLIT:        A panel that utilizes more than one DSI
+ *			      interfaces.
+ * @DSI_DISPLAY_SPLIT_EXT_BRIDGE: A bridge is present between panel and DSI
+ *				  host. It utilizes more than one DSI interface.
+ */
+enum dsi_display_type {
+	DSI_DISPLAY_SINGLE = 0,
+	DSI_DISPLAY_EXT_BRIDGE,
+	DSI_DISPLAY_SPLIT,
+	DSI_DISPLAY_SPLIT_EXT_BRIDGE,
+	DSI_DISPLAY_MAX,
+};
+
+/**
+ * struct dsi_display_info - defines dsi display properties
+ * @display_type:      Display type as defined by device tree.
+ * @type:              Type of panel connected to DSI interface.
+ * @num_of_h_tiles:    In case of split panels, number of h tiles indicates the
+ *		       number of dsi interfaces used. For single DSI panels this
+ *		       is set to 1. This will be set for horizontally split
+ *		       panels.
+ * @h_tile_ids:        The DSI instance ID for each tile.
+ * @is_hot_pluggable:  Can panel be hot plugged.
+ * @is_connected:      Is panel connected.
+ * @is_edid_supported: Does panel support reading EDID information.
+ * @width_mm:          Physical width of panel in millimeters.
+ * @height_mm:         Physical height of panel in millimeters.
+ */
+struct dsi_display_info {
+	char display_type[20];
+	enum dsi_display_type type;
+
+	/* Split DSI properties */
+	bool h_tiled;
+	u32 num_of_h_tiles;
+	u32 h_tile_ids[MAX_DSI_CTRLS_PER_DISPLAY];
+
+	/* HPD */
+	bool is_hot_pluggable;
+	bool is_connected;
+	bool is_edid_supported;
+
+	/* Physical properties */
+	u32 width_mm;
+	u32 height_mm;
+};
+
+/**
+ * struct dsi_display_ctrl - dsi ctrl/phy information for the display
+ * @ctrl:           Handle to the DSI controller device.
+ * @ctrl_of_node:   pHandle to the DSI controller device.
+ * @dsi_ctrl_idx:   DSI controller instance id.
+ * @power_state:    Current power state of the DSI controller.
+ * @cmd_engine_enabled:   Command engine status.
+ * @video_engine_enabled: Video engine status.
+ * @ulps_enabled:         ULPS status for the controller.
+ * @clamps_enabled:       Clamps status for the controller.
+ * @phy:                  Handle to the DSI PHY device.
+ * @phy_of_node:          pHandle to the DSI PHY device.
+ * @phy_enabled:          PHY power status.
+ */
+struct dsi_display_ctrl {
+	/* controller info */
+	struct dsi_ctrl *ctrl;
+	struct device_node *ctrl_of_node;
+	u32 dsi_ctrl_idx;
+
+	enum dsi_power_state power_state;
+	bool cmd_engine_enabled;
+	bool video_engine_enabled;
+	bool ulps_enabled;
+	bool clamps_enabled;
+
+	/* phy info */
+	struct msm_dsi_phy *phy;
+	struct device_node *phy_of_node;
+
+	bool phy_enabled;
+};
+
+/**
+ * struct dsi_display_clk_info - dsi display clock source information
+ * @src_clks:          Source clocks for DSI display.
+ * @mux_clks:          Mux clocks used for DFPS.
+ * @shadow_clks:       Used for DFPS.
+ */
+struct dsi_display_clk_info {
+	struct dsi_clk_link_set src_clks;
+	struct dsi_clk_link_set mux_clks;
+	struct dsi_clk_link_set shadow_clks;
+};
+
+/**
+ * struct dsi_display - dsi display information
+ * @pdev:             Pointer to platform device.
+ * @drm_dev:          DRM device associated with the display.
+ * @name:             Name of the display.
+ * @display_type:     Display type as defined in device tree.
+ * @list:             List pointer.
+ * @is_active:        Is display active.
+ * @display_lock:     Mutex for dsi_display interface.
+ * @ctrl_count:       Number of DSI interfaces required by panel.
+ * @ctrl:             Controller information for DSI display.
+ * @panel:            Handle to DSI panel.
+ * @panel_of:         pHandle to DSI panel.
+ * @type:             DSI display type.
+ * @clk_master_idx:   The master controller for controlling clocks. This is an
+ *		      index into the ctrl[MAX_DSI_CTRLS_PER_DISPLAY] array.
+ * @cmd_master_idx:   The master controller for sending DSI commands to panel.
+ * @video_master_idx: The master controller for enabling video engine.
+ * @clock_info:       Clock sourcing for DSI display.
+ * @lane_map:         Lane mapping between DSI host and Panel.
+ * @num_of_modes:     Number of modes supported by display.
+ * @is_tpg_enabled:   TPG state.
+ * @host:             DRM MIPI DSI Host.
+ * @connector:        Pointer to DRM connector object.
+ * @bridge:           Pointer to DRM bridge object.
+ */
+struct dsi_display {
+	struct platform_device *pdev;
+	struct drm_device *drm_dev;
+
+	const char *name;
+	const char *display_type;
+	struct list_head list;
+	bool is_active;
+	struct mutex display_lock;
+
+	u32 ctrl_count;
+	struct dsi_display_ctrl ctrl[MAX_DSI_CTRLS_PER_DISPLAY];
+
+	/* panel info */
+	struct dsi_panel *panel;
+	struct device_node *panel_of;
+
+	enum dsi_display_type type;
+	u32 clk_master_idx;
+	u32 cmd_master_idx;
+	u32 video_master_idx;
+
+	struct dsi_display_clk_info clock_info;
+	struct dsi_host_config config;
+	struct dsi_lane_mapping lane_map;
+	u32 num_of_modes;
+	bool is_tpg_enabled;
+
+	struct mipi_dsi_host host;
+	struct dsi_connector *connector;
+	struct dsi_bridge    *bridge;
+};
+
+int dsi_display_dev_probe(struct platform_device *pdev);
+int dsi_display_dev_remove(struct platform_device *pdev);
+
+/**
+ * dsi_display_get_num_of_displays() - returns number of display devices
+ *				       supported.
+ *
+ * Return: number of displays.
+ */
+u32 dsi_display_get_num_of_displays(void);
+
+/**
+ * dsi_display_get_display_by_index()- finds display by index
+ * @index:      index of the display.
+ *
+ * Return: handle to the display or error code.
+ */
+struct dsi_display *dsi_display_get_display_by_index(u32 index);
+
+/**
+ * dsi_display_get_display_by_name()- finds display by name
+ * @index:      name of the display.
+ *
+ * Return: handle to the display or error code.
+ */
+struct dsi_display *dsi_display_get_display_by_name(const char *name);
+
+/**
+ * dsi_display_set_active_state() - sets the state of the display
+ * @display:        Handle to display.
+ * @is_active:      state
+ */
+void dsi_display_set_active_state(struct dsi_display *display, bool is_active);
+
+/**
+ * dsi_display_is_active() - returns the state of the display
+ * @display:        Handle to the display.
+ *
+ * Return: state.
+ */
+bool dsi_display_is_active(struct dsi_display *display);
+
+/**
+ * dsi_display_dev_init() - Initializes the display device
+ * @display:         Handle to the display.
+ *
+ * Initialization will acquire references to the resources required for the
+ * display hardware to function.
+ *
+ * Return: error code.
+ */
+int dsi_display_dev_init(struct dsi_display *display);
+
+/**
+ * dsi_display_dev_deinit() - Desinitializes the display device
+ * @display:        Handle to the display.
+ *
+ * All the resources acquired during device init will be released.
+ *
+ * Return: error code.
+ */
+int dsi_display_dev_deinit(struct dsi_display *display);
+
+/**
+ * dsi_display_bind() - Binds the display device to the DRM device
+ * @display:       Handle to the display.
+ * @dev:           Pointer to the DRM device.
+ *
+ * Return: error code.
+ */
+int dsi_display_bind(struct dsi_display *display, struct drm_device *dev);
+
+/**
+ * dsi_display_unbind() - Unbinds the display device from the DRM device
+ * @display:         Handle to the display.
+ *
+ * Return: error code.
+ */
+int dsi_display_unbind(struct dsi_display *display);
+
+/**
+ * dsi_display_drm_init() - initializes DRM objects for the display device.
+ * @display:            Handle to the display.
+ * @encoder:            Pointer to the encoder object which is connected to the
+ *			display.
+ *
+ * Return: error code.
+ */
+int dsi_display_drm_init(struct dsi_display *display, struct drm_encoder *enc);
+
+/**
+ * dsi_display_drm_deinit() - destroys DRM objects assosciated with the display
+ * @display:        Handle to the display.
+ *
+ * Return: error code.
+ */
+int dsi_display_drm_deinit(struct dsi_display *display);
+
+/**
+ * dsi_display_get_info() - returns the display properties
+ * @display:          Handle to the display.
+ * @info:             Pointer to the structure where info is stored.
+ *
+ * Return: error code.
+ */
+int dsi_display_get_info(struct dsi_display *display,
+			 struct dsi_display_info *info);
+
+/**
+ * dsi_display_get_modes() - get modes supported by display
+ * @display:            Handle to display.
+ * @modes;              Pointer to array of modes. Memory allocated should be
+ *			big enough to store (count * struct dsi_display_mode)
+ *			elements. If modes pointer is NULL, number of modes will
+ *			be stored in the memory pointed to by count.
+ * @count:              If modes is NULL, number of modes will be stored. If
+ *			not, mode information will be copied (number of modes
+ *			copied will be equal to *count).
+ *
+ * Return: error code.
+ */
+int dsi_display_get_modes(struct dsi_display *display,
+			  struct dsi_display_mode *modes,
+			  u32 *count);
+
+/**
+ * dsi_display_validate_mode() - validates if mode is supported by display
+ * @display:             Handle to display.
+ * @mode:                Mode to be validated.
+ *
+ * Return: 0 if supported or error code.
+ */
+int dsi_display_validate_mode(struct dsi_display *display,
+			      struct dsi_display_mode *mode);
+
+/**
+ * dsi_display_set_mode() - Set mode on the display.
+ * @display:           Handle to display.
+ * @mode:              mode to be set.
+ * @flags:             Modifier flags.
+ *
+ * Return: error code.
+ */
+int dsi_display_set_mode(struct dsi_display *display,
+			 struct dsi_display_mode *mode,
+			 u32 flags);
+
+/**
+ * dsi_display_prepare() - prepare display
+ * @display:          Handle to display.
+ *
+ * Prepare will perform power up sequences for the host and panel hardware.
+ * Power and clock resources might be turned on (depending on the panel mode).
+ * The video engine is not enabled.
+ *
+ * Return: error code.
+ */
+int dsi_display_prepare(struct dsi_display *display);
+
+/**
+ * dsi_display_enable() - enable display
+ * @display:            Handle to display.
+ *
+ * Enable will turn on the host engine and the panel. At the end of the enable
+ * function, Host and panel hardware are ready to accept pixel data from
+ * upstream.
+ *
+ * Return: error code.
+ */
+int dsi_display_enable(struct dsi_display *display);
+
+/**
+ * dsi_display_post_enable() - perform post enable operations.
+ * @display:         Handle to display.
+ *
+ * Some panels might require some commands to be sent after pixel data
+ * transmission has started. Such commands are sent as part of the post_enable
+ * function.
+ *
+ * Return: error code.
+ */
+int dsi_display_post_enable(struct dsi_display *display);
+
+/**
+ * dsi_display_pre_disable() - perform pre disable operations.
+ * @display:          Handle to display.
+ *
+ * If a panel requires commands to be sent before pixel data transmission is
+ * stopped, those can be sent as part of pre_disable.
+ *
+ * Return: error code.
+ */
+int dsi_display_pre_disable(struct dsi_display *display);
+
+/**
+ * dsi_display_disable() - disable panel and host hardware.
+ * @display:             Handle to display.
+ *
+ * Disable host and panel hardware and pixel data transmission can not continue.
+ *
+ * Return: error code.
+ */
+int dsi_display_disable(struct dsi_display *display);
+
+/**
+ * dsi_display_unprepare() - power off display hardware.
+ * @display:            Handle to display.
+ *
+ * Host and panel hardware is turned off. Panel will be in reset state at the
+ * end of the function.
+ *
+ * Return: error code.
+ */
+int dsi_display_unprepare(struct dsi_display *display);
+
+int dsi_display_set_tpg_state(struct dsi_display *display, bool enable);
+
+int dsi_display_clock_gate(struct dsi_display *display, bool enable);
+int dsi_dispaly_static_frame(struct dsi_display *display, bool enable);
+
+#endif /* _DSI_DISPLAY_H_ */
-- 
cgit v1.2.3


From 1de12c6e3dde44a9f96f7f405b77427e1a9ddba2 Mon Sep 17 00:00:00 2001
From: Ajay Singh Parmar <aparmar@codeaurora.org>
Date: Fri, 10 Jun 2016 16:44:56 -0700
Subject: drm/msm: common display interface for mdp driver

Display_manager.h provides a commong display interface for
MDP driver to query DSI, HDMI and DP display properties.

This is a replacement for the previous dsi-manager component.

Change-Id: Ifdd213b3341ca3c21ca13aca4e56d9c2404030ff
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
---
 .../devicetree/bindings/drm/msm/sde-dsi.txt        |   5 +
 drivers/gpu/drm/msm/dsi-staging/display_manager.c  | 387 +++++++++++++++++++++
 drivers/gpu/drm/msm/dsi-staging/display_manager.h  | 145 ++++++++
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c         |   4 +-
 drivers/gpu/drm/msm/dsi-staging/dsi_display.c      |  24 ++
 drivers/gpu/drm/msm/dsi-staging/dsi_display.h      |  10 +
 drivers/gpu/drm/msm/dsi-staging/dsi_phy.c          |   6 +-
 drivers/gpu/drm/msm/msm_drv.c                      |   3 +
 drivers/gpu/drm/msm/msm_drv.h                      |   5 +
 9 files changed, 584 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/display_manager.c
 create mode 100644 drivers/gpu/drm/msm/dsi-staging/display_manager.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
index 52482a198088..6be533257bab 100644
--- a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
@@ -60,6 +60,11 @@ Optional properties:
 - qcom,dsi-display-active: Current active display
 - qcom,dsi-ctrl: handle to dsi controller device
 - qcom,dsi-phy: handle to dsi phy device
+- qcom,dsi-manager:       Specifies dsi manager is present
+- qcom,dsi-display:       Specifies dsi display is present
+- qcom,display-manager:   Specifies display manager is present
+- qcom,hdmi-display:      Specifies hdmi is present
+- qcom,dp-display:        Specified dp is present
 - qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the
 					a particular "type" of DSI module. The module "types"
 					can be "core", "ctrl", and "phy". Within the same type,
diff --git a/drivers/gpu/drm/msm/dsi-staging/display_manager.c b/drivers/gpu/drm/msm/dsi-staging/display_manager.c
new file mode 100644
index 000000000000..45d1433dce93
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/display_manager.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#include <linux/msm-bus.h>
+#include <linux/of_irq.h>
+
+#include "msm_drv.h"
+#include "msm_kms.h"
+#include "msm_gpu.h"
+#include "display_manager.h"
+#include "dsi_display.h"
+
+static u32 dm_get_num_of_displays(struct display_manager *disp_m)
+{
+	u32 count = 0;
+
+	count = dsi_display_get_num_of_displays();
+	disp_m->display_count = count;
+	disp_m->dsi_display_count = count;
+
+	/* TODO: get HDMI and DP display count here */
+	return disp_m->display_count;
+}
+
+static int dm_set_active_displays(struct display_manager *disp_m)
+{
+	/* TODO: Make changes from DT config here */
+	return 0;
+}
+
+static int dm_init_active_displays(struct display_manager *disp_m)
+{
+	int rc = 0;
+	int i = 0;
+	struct dsi_display *dsi_display;
+
+	for (i = 0; i < disp_m->dsi_display_count; i++) {
+		dsi_display = dsi_display_get_display_by_index(i);
+		if (!dsi_display || !dsi_display_is_active(dsi_display))
+			continue;
+
+		rc = dsi_display_dev_init(dsi_display);
+		if (rc) {
+			pr_err("failed to init dsi display, rc=%d\n", rc);
+			goto error_deinit_dsi_displays;
+		}
+	}
+
+	/* TODO: INIT HDMI and DP displays here */
+	return rc;
+error_deinit_dsi_displays:
+	for (i = i - 1; i >= 0; i--) {
+		dsi_display = dsi_display_get_display_by_index(i);
+		if (dsi_display && dsi_display_is_active(dsi_display))
+			(void)dsi_display_dev_deinit(dsi_display);
+	}
+
+	return rc;
+}
+
+static int dm_deinit_active_displays(struct display_manager *disp_m)
+{
+	int rc = 0;
+	int i = 0;
+	struct dsi_display *dsi_display;
+
+	for (i = 0; i < disp_m->dsi_display_count; i++) {
+		dsi_display = dsi_display_get_display_by_index(i);
+		if (!dsi_display || !dsi_display_is_active(dsi_display))
+			continue;
+
+		rc = dsi_display_dev_deinit(dsi_display);
+		if (rc)
+			pr_err("failed to deinit dsi display, rc=%d\n", rc);
+	}
+
+	/* TODO: DEINIT HDMI and DP displays here */
+	return rc;
+}
+
+static int disp_manager_comp_ops_bind(struct device *dev,
+				     struct device *master,
+				     void *data)
+{
+	int rc = 0;
+	struct drm_device *drm = dev_get_drvdata(master);
+	struct platform_device *pdev = to_platform_device(dev);
+	struct msm_drm_private *priv = drm->dev_private;
+	struct display_manager *disp_m;
+	struct dsi_display *dsi_display;
+	int i = 0;
+
+	if (!pdev || !drm) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	disp_m = platform_get_drvdata(pdev);
+
+	/* DSI displays */
+	for (i = 0; i < disp_m->dsi_display_count; i++) {
+		dsi_display = dsi_display_get_display_by_index(i);
+		if (!dsi_display) {
+			pr_err("Display does not exist\n");
+			continue;
+		}
+
+		if (!dsi_display_is_active(dsi_display))
+			continue;
+
+		rc = dsi_display_bind(dsi_display, drm);
+		if (rc) {
+			pr_err("Failed to bind dsi display_%d, rc=%d\n", i, rc);
+			goto error_unbind_dsi;
+		}
+	}
+
+	/* TODO: BIND HDMI display here */
+	/* TODO: BIND DP display here */
+
+	priv->dm = disp_m;
+	return rc;
+error_unbind_dsi:
+	for (i = i - 1; i >= 0; i--) {
+		dsi_display = dsi_display_get_display_by_index(i);
+		if (!dsi_display || !dsi_display_is_active(dsi_display))
+			continue;
+		(void)dsi_display_unbind(dsi_display);
+	}
+	return rc;
+}
+
+static void disp_manager_comp_ops_unbind(struct device *dev,
+					struct device *master,
+					void *data)
+{
+	int rc = 0;
+	struct drm_device *drm = dev_get_drvdata(master);
+	struct platform_device *pdev = to_platform_device(dev);
+	struct display_manager *disp_m;
+	struct dsi_display *dsi_display;
+	int i = 0;
+
+	if (!pdev || !drm) {
+		pr_err("Invalid params\n");
+		return;
+	}
+
+	disp_m = platform_get_drvdata(pdev);
+
+	/* DSI displays */
+	for (i = 0; i < disp_m->dsi_display_count; i++) {
+		dsi_display = dsi_display_get_display_by_index(i);
+		if (!dsi_display || !dsi_display_is_active(dsi_display))
+			continue;
+
+		rc = dsi_display_unbind(dsi_display);
+		if (rc)
+			pr_err("failed to unbind dsi display_%d, rc=%d\n",
+			       i, rc);
+	}
+
+	/* TODO: UNBIND HDMI display here */
+	/* TODO: UNBIND DP display here */
+}
+
+static const struct of_device_id displays_dt_match[] = {
+	{.compatible = "qcom,dsi-display"},
+	{.compatible = "qcom,hdmi-display"},
+	{.compatible = "qcom,dp-display"},
+	{}
+};
+
+static const struct component_ops disp_manager_comp_ops = {
+	.bind = disp_manager_comp_ops_bind,
+	.unbind = disp_manager_comp_ops_unbind,
+};
+
+static int disp_manager_dev_probe(struct platform_device *pdev)
+{
+	struct display_manager *disp_m;
+	int rc = 0;
+
+	if (!pdev || !pdev->dev.of_node) {
+		pr_err("pdev not found\n");
+		return -ENODEV;
+	}
+
+	disp_m = devm_kzalloc(&pdev->dev, sizeof(*disp_m), GFP_KERNEL);
+	if (!disp_m)
+		return -ENOMEM;
+
+	disp_m->name = "qcom,display-manager";
+
+	of_platform_populate(pdev->dev.of_node, displays_dt_match,
+			     NULL, &pdev->dev);
+
+	disp_m->display_count = dm_get_num_of_displays(disp_m);
+	if (!disp_m->display_count) {
+		rc = -ENODEV;
+		pr_err("No display found, rc=%d\n", rc);
+		goto error_free_disp_m;
+	}
+
+	rc = dm_set_active_displays(disp_m);
+	if (rc) {
+		pr_err("failed to set active displays, rc=%d\n", rc);
+		goto error_remove_displays;
+	}
+
+	rc = dm_init_active_displays(disp_m);
+	if (rc) {
+		pr_err("failed to initialize displays, rc=%d\n", rc);
+		goto error_remove_displays;
+	}
+
+	rc = component_add(&pdev->dev, &disp_manager_comp_ops);
+	if (rc) {
+		pr_err("failed to add component, rc=%d\n", rc);
+		goto error_deinit_displays;
+	}
+
+	mutex_init(&disp_m->lock);
+	platform_set_drvdata(pdev, disp_m);
+
+	return rc;
+error_deinit_displays:
+	(void)dm_deinit_active_displays(disp_m);
+error_remove_displays:
+	of_platform_depopulate(&pdev->dev);
+error_free_disp_m:
+	devm_kfree(&pdev->dev, disp_m);
+	return rc;
+}
+
+static int disp_manager_dev_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct of_device_id disp_manager_dt_match[] = {
+	{.compatible = "qcom,display-manager"},
+	{}
+};
+
+static struct platform_driver disp_manager_driver = {
+	.probe = disp_manager_dev_probe,
+	.remove = disp_manager_dev_remove,
+	.driver = {
+		.name = "msm-display-manager",
+		.of_match_table = disp_manager_dt_match,
+	},
+};
+
+
+int display_manager_get_count(struct display_manager *disp_m)
+{
+	int count;
+
+	if (!disp_m) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&disp_m->lock);
+
+	count = 1; /* TODO: keep track of active displays */
+
+	mutex_unlock(&disp_m->lock);
+	return count;
+}
+
+int display_manager_get_info_by_index(struct display_manager *disp_m,
+				      u32 display_index,
+				      struct display_info *info)
+{
+	int rc = 0;
+	int i = 0, j = 0;
+	struct dsi_display *display;
+	struct dsi_display_info dsi_info;
+
+	if (!disp_m || !info) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&disp_m->lock);
+
+	for (i = 0; i < disp_m->dsi_display_count; i++) {
+		display = dsi_display_get_display_by_index(i);
+		if (!display || !dsi_display_is_active(display))
+			continue;
+
+		memset(&dsi_info, 0x0, sizeof(dsi_info));
+		rc = dsi_display_get_info(display, &dsi_info);
+		if (rc) {
+			pr_err("failed to get display info, rc=%d\n", rc);
+			goto error;
+		}
+
+		info->intf = DISPLAY_INTF_DSI;
+		info->num_of_h_tiles = dsi_info.num_of_h_tiles;
+
+		for (j = 0; j < info->num_of_h_tiles; j++)
+			info->h_tile_instance[j] = dsi_info.h_tile_ids[j];
+
+		info->is_hot_pluggable = dsi_info.is_hot_pluggable;
+		info->is_connected = dsi_info.is_connected;
+		info->is_edid_supported = dsi_info.is_edid_supported;
+		info->max_width = 1920; /* TODO: */
+		info->max_height = 1080; /* TODO: */
+		info->compression = DISPLAY_COMPRESSION_NONE;
+		break;
+	}
+
+error:
+	mutex_unlock(&disp_m->lock);
+	return rc;
+}
+
+int display_manager_drm_init_by_index(struct display_manager *disp_m,
+				      u32 display_index,
+				      struct drm_encoder *encoder)
+{
+	int rc = 0;
+	int i = 0;
+	struct dsi_display *display;
+
+	if (!disp_m || !encoder) {
+		pr_err("Invalid params\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&disp_m->lock);
+
+	for (i = 0; i < disp_m->dsi_display_count; i++) {
+		display = dsi_display_get_display_by_index(i);
+		if (!display || !dsi_display_is_active(display))
+			continue;
+
+		dsi_display_drm_init(display, encoder);
+		break;
+	}
+
+	mutex_unlock(&disp_m->lock);
+
+	return rc;
+
+}
+
+int display_manager_drm_deinit_by_index(struct display_manager *disp_m,
+					u32 display_index)
+{
+	return 0;
+}
+
+
+void display_manager_register(void)
+{
+	dsi_phy_drv_register();
+	dsi_ctrl_drv_register();
+	dsi_display_register();
+
+	platform_driver_register(&disp_manager_driver);
+}
+void display_manager_unregister(void)
+{
+	platform_driver_unregister(&disp_manager_driver);
+	dsi_display_unregister();
+	dsi_ctrl_drv_register();
+	dsi_phy_drv_unregister();
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/display_manager.h b/drivers/gpu/drm/msm/dsi-staging/display_manager.h
new file mode 100644
index 000000000000..0b7462b7bb53
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi-staging/display_manager.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DISPLAY_MANAGER_H_
+#define _DISPLAY_MANAGER_H_
+
+#define MAX_H_TILES_PER_DISPLAY 2
+
+/**
+ * enum display_interface_type - enumerates display interface types
+ * @DISPLAY_INTF_DSI:        DSI interface
+ * @DISPLAY_INTF_HDMI:       HDMI interface
+ * @DISPLAY_INTF_DP:         Display Port interface
+ */
+enum display_interface_type {
+	DISPLAY_INTF_DSI = 0,
+	DISPLAY_INTF_HDMI,
+	DISPLAY_INTF_DP,
+	DISPLAY_INTF_MAX,
+};
+
+/**
+ * enum display_compression_type - compression method used for pixel stream
+ * @DISPLAY_COMPRESISON_NONE:     Pixel data is not compressed.
+ * @DISPLAY_COMPRESSION_DSC:      DSC compresison is used.
+ * @DISPLAY_COMPRESSION_FBC:      FBC compression is used.
+ */
+enum display_compression_type {
+	DISPLAY_COMPRESSION_NONE = 0,
+	DISPLAY_COMPRESSION_DSC,
+	DISPLAY_COMPRESSION_FBC,
+	DISPLAY_COMPRESISON_MAX
+};
+
+
+/**
+ * struct display_info - defines display properties
+ * @intf:               The interface on which display is connected to SOC.
+ * @num_of_h_tiles:     number of horizontal tiles in case of split interface.
+ * @h_tile_instance:    controller instance used per tile. Number of elements is
+ *			based on num_of_h_tiles.
+ * @is_hot_pluggable:   Set to true if hot plug detection is supported.
+ * @is_connected:       Set to true if display is connected.
+ * @is_edid_supported:  True if display supports EDID.
+ * @max_width:          Max width of display. In case of hot pluggable display,
+ *			this is max width supported by controller.
+ * @max_height:         Max height of display. In case of hot pluggable display,
+ *			this is max height supported by controller.
+ * @compression:        Compression supported by the display.
+ */
+struct display_info {
+	enum display_interface_type intf;
+
+	u32 num_of_h_tiles;
+	u32 h_tile_instance[MAX_H_TILES_PER_DISPLAY];
+
+	bool is_hot_pluggable;
+	bool is_connected;
+	bool is_edid_supported;
+
+	u32 max_width;
+	u32 max_height;
+
+	enum display_compression_type compression;
+};
+
+struct display_manager {
+	struct platform_device *pdev;
+	const char *name;
+
+	struct mutex lock;
+	u32 display_count;
+	u32 dsi_display_count;
+	u32 hdmi_display_count;
+	u32 dp_display_count;
+	/* Debug fs */
+	struct dentry *debugfs_root;
+};
+
+/**
+ * display_manager_get_count() - returns the number of display present
+ * @disp_m:      Handle to Display manager.
+ *
+ * Returns the sum total of DSI, HDMI and DP display present on the board.
+ *
+ * Return: error code (< 0) in case of error or number of display ( >= 0)
+ */
+int display_manager_get_count(struct display_manager *disp_m);
+
+/**
+ * display_manager_get_info_by_index() - returns display information
+ * @disp_m:        Handle to Display manager.
+ * @display_index: display index (valid indices are 0 to (display_count - 1).
+ * @info:          Structure where display info is copied.
+ *
+ * Return: error code.
+ */
+int display_manager_get_info_by_index(struct display_manager *disp_m,
+				      u32 display_index,
+				      struct display_info *info);
+
+/**
+ * display_manager_drm_init_by_index() - initialize drm objects for display
+ * @disp_m:         Handle to Display manager.
+ * @display_index:  display index (valid indices are 0 to (display_count - 1).
+ * @encoder:        Pointer to encoder object to which display is attached.
+ *
+ * Return: error code.
+ */
+int display_manager_drm_init_by_index(struct display_manager *disp_m,
+				      u32 display_index,
+				      struct drm_encoder *encoder);
+
+/**
+ * display_manager_drm_deinit_by_index() - detroys drm objects
+ * @disp_m:         Handle to Display manager.
+ * @display_index:  display index (valid indices are 0 to (display_count - 1).
+ *
+ * Return: error code.
+ */
+int display_manager_drm_deinit_by_index(struct display_manager *disp_m,
+					u32 display_index);
+
+/**
+ * display_manager_register() - register display interface drivers
+ */
+void display_manager_register(void);
+
+/**
+ * display_manager_unregister() - unregisters display interface drivers
+ */
+void display_manager_unregister(void);
+
+#endif /* _DISPLAY_MANAGER_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
index 1fac1b9a4843..04a3a79f2f1d 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -2335,7 +2335,7 @@ error:
 /**
  * dsi_ctrl_drv_register() - register platform driver for dsi controller
  */
-void __init dsi_ctrl_drv_register(void)
+void dsi_ctrl_drv_register(void)
 {
 	platform_driver_register(&dsi_ctrl_driver);
 }
@@ -2343,7 +2343,7 @@ void __init dsi_ctrl_drv_register(void)
 /**
  * dsi_ctrl_drv_unregister() - unregister platform driver
  */
-void __exit dsi_ctrl_drv_unregister(void)
+void dsi_ctrl_drv_unregister(void)
 {
 	platform_driver_unregister(&dsi_ctrl_driver);
 }
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index 87a28dcfcf7d..47fa70823bc3 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -29,6 +29,11 @@
 static DEFINE_MUTEX(dsi_display_list_lock);
 static LIST_HEAD(dsi_display_list);
 
+static const struct of_device_id dsi_display_dt_match[] = {
+	{.compatible = "qcom,dsi-display"},
+	{}
+};
+
 static struct dsi_display *main_display;
 
 static ssize_t debugfs_dump_info_read(struct file *file,
@@ -1259,6 +1264,15 @@ error:
 	return rc;
 }
 
+static struct platform_driver dsi_display_driver = {
+	.probe = dsi_display_dev_probe,
+	.remove = dsi_display_dev_remove,
+	.driver = {
+		.name = "msm-dsi-display",
+		.of_match_table = dsi_display_dt_match,
+	},
+};
+
 int dsi_display_dev_probe(struct platform_device *pdev)
 {
 	int rc = 0;
@@ -2129,3 +2143,13 @@ int dsi_display_unprepare(struct dsi_display *display)
 	mutex_unlock(&display->display_lock);
 	return rc;
 }
+
+void dsi_display_register(void)
+{
+	platform_driver_register(&dsi_display_driver);
+}
+
+void dsi_display_unregister(void)
+{
+	platform_driver_unregister(&dsi_display_driver);
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
index 976baf6b8553..a8c0ebf6d0d6 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
@@ -188,6 +188,16 @@ struct dsi_display {
 int dsi_display_dev_probe(struct platform_device *pdev);
 int dsi_display_dev_remove(struct platform_device *pdev);
 
+/**
+ * dsi_display_register() - register dsi display platform driver
+ */
+void dsi_display_register(void);
+
+/**
+ * dsi_display_unregister() - unregister dsi display platform driver
+ */
+void dsi_display_unregister(void);
+
 /**
  * dsi_display_get_num_of_displays() - returns number of display devices
  *				       supported.
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
index d53ef1140f99..1ccbbe7df573 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
@@ -510,7 +510,7 @@ static struct platform_driver dsi_phy_platform_driver = {
 	.probe      = dsi_phy_driver_probe,
 	.remove     = dsi_phy_driver_remove,
 	.driver     = {
-		.name   = "msm_dsi_phy",
+		.name   = "dsi_phy",
 		.of_match_table = msm_dsi_phy_of_match,
 	},
 };
@@ -848,12 +848,12 @@ int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
 	return rc;
 }
 
-void __init dsi_phy_drv_register(void)
+void dsi_phy_drv_register(void)
 {
 	platform_driver_register(&dsi_phy_platform_driver);
 }
 
-void __exit dsi_phy_drv_unregister(void)
+void dsi_phy_drv_unregister(void)
 {
 	platform_driver_unregister(&dsi_phy_platform_driver);
 }
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 67c4518e22e1..52479155de49 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -18,6 +18,7 @@
 #include "msm_drv.h"
 #include "msm_gpu.h"
 #include "msm_kms.h"
+#include "display_manager.h"
 
 static void msm_fb_output_poll_changed(struct drm_device *dev)
 {
@@ -1169,6 +1170,7 @@ static struct platform_driver msm_platform_driver = {
 static int __init msm_drm_register(void)
 {
 	DBG("init");
+	display_manager_register();
 	msm_dsi_register();
 	msm_edp_register();
 	hdmi_register();
@@ -1184,6 +1186,7 @@ static void __exit msm_drm_unregister(void)
 	adreno_unregister();
 	msm_edp_unregister();
 	msm_dsi_unregister();
+	display_manager_unregister();
 }
 
 module_init(msm_drm_register);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 22d3e11fe821..2efc584ad5d4 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -102,6 +102,8 @@ struct msm_vblank_ctrl {
 	spinlock_t lock;
 };
 
+struct display_manager;
+
 struct msm_drm_private {
 
 	struct msm_kms *kms;
@@ -123,6 +125,9 @@ struct msm_drm_private {
 	/* DSI is shared by mdp4 and mdp5 */
 	struct msm_dsi *dsi[2];
 
+	/* Display manager for SDE driver */
+	struct display_manager *dm;
+
 	/* when we have more than one 'msm_gpu' these need to be an array: */
 	struct msm_gpu *gpu;
 	struct msm_file_private *lastctx;
-- 
cgit v1.2.3


From cc2cbe997040174e69b9b852dc706a54f3090a05 Mon Sep 17 00:00:00 2001
From: Alan Kwong <akwong@codeaurora.org>
Date: Wed, 20 Jul 2016 16:41:25 -0400
Subject: drm/msm/sde: add virtual writeback device and connector

Enable virtual writeback connector by allowing a property on the
connector to specify output frame buffer id, which takes in a
framebuffer object added via ADDFB2 ioctl.  A new writeback
configure ioctl is added to configure connection state and
display modes of writeback connector.

Change-Id: Ifce411a3f0798e3af7dd7f19da27d67cdd849bfb
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Signed-off-by: Clarence Ip <cip@codeaurora.org>
---
 .../devicetree/bindings/drm/msm/sde-wb.txt         |   23 +
 drivers/gpu/drm/msm/Kconfig                        |    8 +
 drivers/gpu/drm/msm/Makefile                       |    3 +
 drivers/gpu/drm/msm/msm_drv.c                      |    2 +
 drivers/gpu/drm/msm/msm_drv.h                      |    5 +-
 drivers/gpu/drm/msm/sde/sde_crtc.c                 |   52 +-
 drivers/gpu/drm/msm/sde/sde_crtc.h                 |    2 +
 drivers/gpu/drm/msm/sde/sde_encoder.c              |  144 ++-
 drivers/gpu/drm/msm/sde/sde_encoder_phys.h         |   95 ++
 drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c      | 1028 ++++++++++++++++++++
 drivers/gpu/drm/msm/sde/sde_formats.c              |   66 ++
 drivers/gpu/drm/msm/sde/sde_formats.h              |   16 +
 drivers/gpu/drm/msm/sde/sde_hw_catalog.h           |    5 +-
 drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c      |  105 +-
 drivers/gpu/drm/msm/sde/sde_hw_mdss.h              |    5 +-
 drivers/gpu/drm/msm/sde/sde_wb.c                   |  692 +++++++++++++
 drivers/gpu/drm/msm/sde/sde_wb.h                   |  376 +++++++
 include/uapi/drm/msm_drm.h                         |    6 +-
 include/uapi/drm/sde_drm.h                         |   20 +
 19 files changed, 2632 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/msm/sde-wb.txt
 create mode 100644 drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
 create mode 100644 drivers/gpu/drm/msm/sde/sde_wb.c
 create mode 100644 drivers/gpu/drm/msm/sde/sde_wb.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/drm/msm/sde-wb.txt b/Documentation/devicetree/bindings/drm/msm/sde-wb.txt
new file mode 100644
index 000000000000..863b334e438a
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/msm/sde-wb.txt
@@ -0,0 +1,23 @@
+QTI Snapdragon Display Engine (SDE) writeback display
+
+Required properties:
+- compatible:		"qcom,wb-display"
+
+Optional properties:
+- cell-index:		Index of writeback device instance.
+			Default to 0 if not specified.
+- label:		String to describe this writeback display.
+			Default to "unknown" if not specified.
+
+Example:
+
+/ {
+	...
+
+	sde_wb: qcom,wb-display {
+		compatible = "qcom,wb-display";
+		cell-index = <2>;
+		label = "wb_display";
+	};
+
+};
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 69ebfd39c2fe..afd94a1e85d3 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -80,3 +80,11 @@ config DRM_MSM_HDCP
 	default n
 	help
 	  Chose this option if HDCP supported is needed in DRM/KMS driver.
+
+config DRM_SDE_WB
+	bool "Enable Writeback support in SDE DRM"
+	depends on DRM_MSM
+	default y
+	help
+	  Choose this option for writeback connector support.
+
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 23d1550c1ffa..89d74cec0ad9 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -119,3 +119,6 @@ obj-$(CONFIG_DRM_MSM) += sde/sde_hw_catalog.o \
 	sde/sde_formats.o
 
 obj-$(CONFIG_DRM_MSM) += display-manager/display_manager.o
+
+obj-$(CONFIG_DRM_SDE_WB) += sde/sde_wb.o \
+	sde/sde_encoder_phys_wb.o
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index fd0b0227d65a..8b9867fffe35 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -19,6 +19,7 @@
 #include "msm_gpu.h"
 #include "msm_kms.h"
 #include "display_manager.h"
+#include "sde_wb.h"
 
 static void msm_fb_output_poll_changed(struct drm_device *dev)
 {
@@ -952,6 +953,7 @@ static const struct drm_ioctl_desc msm_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT,   msm_ioctl_gem_submit,   DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE,   msm_ioctl_wait_fence,   DRM_AUTH|DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(SDE_WB_CONFIG, sde_wb_config, DRM_UNLOCKED|DRM_AUTH),
 };
 
 static const struct vm_operations_struct vm_ops = {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 69e6718339c1..b395ea713db6 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -118,6 +118,10 @@ enum msm_mdp_conn_property {
 	/* range properties */
 	CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
 	CONNECTOR_PROP_RETIRE_FENCE,
+	CONNECTOR_PROP_DST_X,
+	CONNECTOR_PROP_DST_Y,
+	CONNECTOR_PROP_DST_W,
+	CONNECTOR_PROP_DST_H,
 
 	/* enum/bitmask properties */
 
@@ -468,5 +472,4 @@ static inline int align_pitch(int width, int bpp)
 /* for conditionally setting boolean flag(s): */
 #define COND(bool, val) ((bool) ? (val) : 0)
 
-
 #endif /* __MSM_DRV_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 02cd5847c897..ab0c9ad794e4 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -119,6 +119,34 @@ static int sde_crtc_reserve_hw_resources(struct drm_crtc *crtc,
 		}
 	}
 
+	/*
+	 * Get default LMs if specified in platform config,
+	 * otherwise acquire the free LMs.
+	 */
+	for (i = WB_0; i < WB_MAX; i++) {
+		if (enc_hw_res.wbs[i]) {
+			struct sde_crtc_mixer *mixer =
+				&sde_crtc->mixer[sde_crtc->num_mixers];
+			plat_hw_res_map = sde_rm_get_res_map(sde_kms,
+					SDE_NONE, i);
+
+			lm_idx = plat_hw_res_map->lm;
+			if (!lm_idx && unused_lm_count)
+				lm_idx = unused_lm_id[--unused_lm_count];
+
+			DBG("Acquiring LM %d", lm_idx);
+			mixer->hw_lm = sde_rm_acquire_mixer(sde_kms, lm_idx);
+			if (IS_ERR_OR_NULL(mixer->hw_lm)) {
+				DRM_ERROR("Invalid mixer\n");
+				return -EACCES;
+			}
+			/* interface info */
+			mixer->wb_idx = i;
+			mixer->mode = enc_hw_res.wbs[i];
+			sde_crtc->num_mixers++;
+		}
+	}
+
 	DBG("control paths %d, num_mixers %d, lm[0] %d, ctl[0] %d ",
 			sde_crtc->num_ctls, sde_crtc->num_mixers,
 			sde_crtc->mixer[0].hw_lm->idx,
@@ -412,8 +440,23 @@ static u32 _sde_crtc_update_ctl_flush_mask(struct drm_crtc *crtc)
 	for (i = 0; i < sde_crtc->num_ctls; i++) {
 		mixer = &sde_crtc->mixer[i];
 		ctl = mixer->hw_ctl;
-		ctl->ops.get_bitmask_intf(ctl, &mixer->flush_mask,
-				mixer->intf_idx);
+
+		switch (mixer->mode) {
+		case INTF_MODE_CMD:
+		case INTF_MODE_VIDEO:
+			ctl->ops.get_bitmask_intf(ctl, &mixer->flush_mask,
+					mixer->intf_idx);
+			break;
+		case INTF_MODE_WB_LINE:
+			ctl->ops.get_bitmask_wb(ctl, &mixer->flush_mask,
+					mixer->wb_idx);
+			break;
+		default:
+			DBG("Invalid ctl %d interface mode %d", ctl->idx,
+					mixer->mode);
+			return -EINVAL;
+		}
+
 		ctl->ops.update_pending_flush(ctl, mixer->flush_mask);
 		DBG("added CTL_ID %d mask 0x%x to pending flush", ctl->idx,
 						mixer->flush_mask);
@@ -1115,10 +1158,11 @@ static int _sde_debugfs_mixer_read(struct seq_file *s, void *data)
 		} else if (!m->hw_ctl) {
 			seq_printf(s, "Mixer[%d] has no CTL\n", i);
 		} else {
-			seq_printf(s, "LM_%d/CTL_%d -> INTF_%d\n",
+			seq_printf(s, "LM_%d/CTL_%d -> INTF_%d, WB_%d\n",
 					m->hw_lm->idx - LM_0,
 					m->hw_ctl->idx - CTL_0,
-					m->intf_idx - INTF_0);
+					m->intf_idx - INTF_0,
+					m->wb_idx - WB_0);
 		}
 	}
 	seq_printf(s, "Border: %d\n", sde_crtc->stage_cfg.border_enable);
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
index 417e54b3e952..c34be7f40f05 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.h
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -31,6 +31,7 @@
  * @hw_lm       : LM HW Driver context
  * @hw_ctl      : CTL Path HW driver context
  * @intf_idx    : Interface idx
+ * @wb_idx      : Writeback idx
  * @mode        : Interface mode Active/CMD
  * @flush_mask  : Flush mask value for this commit
  */
@@ -39,6 +40,7 @@ struct sde_crtc_mixer {
 	struct sde_hw_mixer *hw_lm;
 	struct sde_hw_ctl   *hw_ctl;
 	enum sde_intf       intf_idx;
+	enum sde_wb         wb_idx;
 	enum sde_intf_mode  mode;
 	u32 flush_mask;
 };
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 5d4d6ceebad3..5194679b53a1 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -256,6 +256,57 @@ static bool sde_encoder_virt_mode_fixup(struct drm_encoder *drm_enc,
 	return ret;
 }
 
+static int sde_encoder_virt_atomic_check(struct drm_encoder *drm_enc,
+		    struct drm_crtc_state *crtc_state,
+		    struct drm_connector_state *conn_state)
+{
+	struct sde_encoder_virt *sde_enc = NULL;
+	const struct drm_display_mode *mode;
+	struct drm_display_mode *adj_mode;
+	int i = 0;
+	int ret = 0;
+
+	DBG("");
+
+	if (!drm_enc || !crtc_state || !conn_state) {
+		DRM_ERROR("Invalid pointer");
+		return -EINVAL;
+	}
+
+	sde_enc = to_sde_encoder_virt(drm_enc);
+	mode = &crtc_state->mode;
+	adj_mode = &crtc_state->adjusted_mode;
+	MSM_EVT(drm_enc->dev, 0, 0);
+
+	/* perform atomic check on the first physical encoder (master) */
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys && phys->ops.atomic_check) {
+			ret = phys->ops.atomic_check(phys, crtc_state,
+					conn_state);
+			if (ret)
+				DRM_ERROR("Mode unsupported, phys_enc %d.%d\n",
+						drm_enc->base.id, i);
+			break;
+		} else if (phys && phys->ops.mode_fixup) {
+			if (!phys->ops.mode_fixup(phys, mode, adj_mode)) {
+				DRM_ERROR("Mode unsupported, phys_enc %d.%d\n",
+						drm_enc->base.id, i);
+				ret = -EINVAL;
+			}
+			break;
+		}
+	}
+
+	/* Call to populate mode->crtc* information required by framework */
+	drm_mode_set_crtcinfo(adj_mode, 0);
+
+	MSM_EVT(drm_enc->dev, adj_mode->flags, adj_mode->private_flags);
+
+	return ret;
+}
+
 static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 				      struct drm_display_mode *mode,
 				      struct drm_display_mode *adj_mode)
@@ -351,6 +402,7 @@ static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
 	.mode_set = sde_encoder_virt_mode_set,
 	.disable = sde_encoder_virt_disable,
 	.enable = sde_encoder_virt_enable,
+	.atomic_check = sde_encoder_virt_atomic_check,
 };
 
 static const struct drm_encoder_funcs sde_encoder_funcs = {
@@ -374,6 +426,15 @@ static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
 	return INTF_MAX;
 }
 
+static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
+		enum sde_intf_type type, u32 controller_id)
+{
+	if (controller_id < catalog->wb_count)
+		return catalog->wb[controller_id].id;
+
+	return WB_MAX;
+}
+
 static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc)
 {
 	struct sde_encoder_virt *sde_enc = NULL;
@@ -567,6 +628,45 @@ static int sde_encoder_virt_add_phys_encs(
 	return 0;
 }
 
+static int sde_encoder_virt_add_phys_enc_wb(
+		struct sde_encoder_virt *sde_enc,
+		struct sde_kms *sde_kms,
+		enum sde_wb wb_idx,
+		enum sde_ctl ctl_idx,
+		enum sde_cdm cdm_idx,
+		enum sde_enc_split_role split_role)
+{
+	struct sde_encoder_phys *enc = NULL;
+	struct sde_encoder_virt_ops parent_ops = {
+		sde_encoder_vblank_callback,
+		sde_encoder_handle_phys_enc_ready_for_kickoff
+	};
+
+	DBG("");
+
+	if (sde_enc->num_phys_encs + 1 >=
+			ARRAY_SIZE(sde_enc->phys_encs)) {
+		DRM_ERROR("Too many physical encoders %d, unable to add\n",
+			  sde_enc->num_phys_encs);
+		return -EINVAL;
+	}
+
+	enc = sde_encoder_phys_wb_init(sde_kms, wb_idx,
+			ctl_idx, cdm_idx, split_role, &sde_enc->base,
+			parent_ops);
+
+	if (IS_ERR_OR_NULL(enc)) {
+		DRM_ERROR("Failed to initialize phys wb enc: %ld\n",
+			PTR_ERR(enc));
+		return enc == 0 ? -EINVAL : PTR_ERR(enc);
+	}
+
+	sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
+	++sde_enc->num_phys_encs;
+
+	return 0;
+}
+
 static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
 				 struct sde_kms *sde_kms,
 				 struct msm_display_info *disp_info,
@@ -584,6 +684,9 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
 	} else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
 		*drm_enc_mode = DRM_MODE_ENCODER_TMDS;
 		intf_type = INTF_HDMI;
+	} else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
+		*drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
+		intf_type = INTF_WB;
 	} else {
 		DRM_ERROR("Unsupported display interface type");
 		return -EINVAL;
@@ -602,7 +705,9 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
 		const struct sde_hw_res_map *hw_res_map = NULL;
 		enum sde_intf intf_idx = INTF_MAX;
 		enum sde_pingpong pp_idx = PINGPONG_MAX;
+		enum sde_wb wb_idx = WB_MAX;
 		enum sde_ctl ctl_idx = CTL_MAX;
+		enum sde_cdm cdm_idx = SDE_NONE;
 		u32 controller_id = disp_info->h_tile_instance[i];
 		enum sde_enc_split_role split_role = ENC_ROLE_SOLO;
 
@@ -616,26 +721,45 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
 		DBG("h_tile_instance %d = %d, split_role %d",
 				i, controller_id, split_role);
 
-		intf_idx = sde_encoder_get_intf(sde_kms->catalog,
-				intf_type, controller_id);
-		if (intf_idx == INTF_MAX) {
-			DRM_ERROR("Error: could not get the interface id\n");
-			ret = -EINVAL;
+		if (intf_type == INTF_WB) {
+			wb_idx = sde_encoder_get_wb(sde_kms->catalog,
+					intf_type, controller_id);
+			if (wb_idx == WB_MAX) {
+				DRM_ERROR(
+					"Error: could not get the writeback id\n");
+				ret = -EINVAL;
+			}
+			intf_idx = SDE_NONE;
+		} else {
+			intf_idx = sde_encoder_get_intf(sde_kms->catalog,
+					intf_type, controller_id);
+			if (intf_idx == INTF_MAX) {
+				DRM_ERROR(
+					"Error: could not get the interface id\n");
+				ret = -EINVAL;
+			}
+			wb_idx = SDE_NONE;
 		}
 
-		hw_res_map = sde_rm_get_res_map(sde_kms, intf_idx, SDE_NONE);
+		hw_res_map = sde_rm_get_res_map(sde_kms, intf_idx, wb_idx);
 		if (IS_ERR_OR_NULL(hw_res_map)) {
 			ret = -EINVAL;
 		} else {
 			pp_idx = hw_res_map->pp;
 			ctl_idx = hw_res_map->ctl;
+			cdm_idx = hw_res_map->cdm;
 		}
 
 		if (!ret) {
-			ret = sde_encoder_virt_add_phys_encs(
-					disp_info->capabilities,
-					sde_enc, sde_kms, intf_idx, pp_idx,
-					ctl_idx, split_role);
+			if (intf_type == INTF_WB)
+				ret = sde_encoder_virt_add_phys_enc_wb(
+						sde_enc, sde_kms, wb_idx,
+						ctl_idx, cdm_idx, split_role);
+			else
+				ret = sde_encoder_virt_add_phys_encs(
+						disp_info->capabilities,
+						sde_enc, sde_kms, intf_idx,
+						pp_idx, ctl_idx, split_role);
 			if (ret)
 				DRM_ERROR("Failed to add phys encs\n");
 		}
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
index cc9fd9f06095..45114d4708b4 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
@@ -20,6 +20,10 @@
 #include "sde_hw_pingpong.h"
 #include "sde_hw_ctl.h"
 #include "sde_hw_top.h"
+#include "sde_hw_wb.h"
+#include "sde_hw_cdm.h"
+
+#define SDE_ENCODER_NAME_MAX	16
 
 /**
  * enum sde_enc_split_role - Role this physical encoder will play in a
@@ -62,6 +66,7 @@ struct sde_encoder_virt_ops {
  *				This likely caches the mode, for use at enable.
  * @enable:			DRM Call. Enable a DRM mode.
  * @disable:			DRM Call. Disable mode.
+ * @atomic_check:		DRM Call. Atomic check new DRM state.
  * @destroy:			DRM Call. Destroy and release resources.
  * @get_hw_resources:		Populate the structure with the hardware
  *				resources that this phys_enc is using.
@@ -86,6 +91,9 @@ struct sde_encoder_phys_ops {
 			struct drm_display_mode *adjusted_mode);
 	void (*enable)(struct sde_encoder_phys *encoder);
 	void (*disable)(struct sde_encoder_phys *encoder);
+	int (*atomic_check)(struct sde_encoder_phys *encoder,
+			    struct drm_crtc_state *crtc_state,
+			    struct drm_connector_state *conn_state);
 	void (*destroy)(struct sde_encoder_phys *encoder);
 	void (*get_hw_resources)(struct sde_encoder_phys *encoder,
 			struct sde_encoder_hw_resources *hw_res);
@@ -118,6 +126,8 @@ enum sde_enc_enable_state {
  * @parent_ops:		Callbacks exposed by the parent to the phys_enc
  * @hw_mdptop:		Hardware interface to the top registers
  * @hw_ctl:		Hardware interface to the ctl registers
+ * @hw_cdm:		Hardware interface to the cdm registers
+ * @cdm_cfg:		Chroma-down hardware configuration
  * @sde_kms:		Pointer to the sde_kms top level
  * @cached_mode:	DRM mode cached at mode_set time, acted on in enable
  * @enabled:		Whether the encoder has enabled and running a mode
@@ -132,6 +142,8 @@ struct sde_encoder_phys {
 	struct sde_encoder_virt_ops parent_ops;
 	struct sde_hw_mdp *hw_mdptop;
 	struct sde_hw_ctl *hw_ctl;
+	struct sde_hw_cdm *hw_cdm;
+	struct sde_hw_cdm_cfg cdm_cfg;
 	struct sde_kms *sde_kms;
 	struct drm_display_mode cached_mode;
 	enum sde_enc_split_role split_role;
@@ -184,6 +196,51 @@ struct sde_encoder_phys_cmd {
 	atomic_t pending_cnt;
 };
 
+/**
+ * struct sde_encoder_phys_wb - sub-class of sde_encoder_phys to handle
+ *	writeback specific operations
+ * @base:		Baseclass physical encoder structure
+ * @hw_wb:		Hardware interface to the wb registers
+ * @irq_idx:		IRQ interface lookup index
+ * @wbdone_timeout:	Timeout value for writeback done in msec
+ * @bypass_irqreg:	Bypass irq register/unregister if non-zero
+ * @wbdone_complete:	for wbdone irq synchronization
+ * @wb_cfg:		Writeback hardware configuration
+ * @intf_cfg:		Interface hardware configuration
+ * @wb_roi:		Writeback region-of-interest
+ * @wb_fmt:		Writeback pixel format
+ * @frame_count:	Counter of completed writeback operations
+ * @kickoff_count:	Counter of issued writeback operations
+ * @mmu_id:		mmu identifier for non-secure/secure domain
+ * @wb_dev:		Pointer to writeback device
+ * @start_time:		Start time of writeback latest request
+ * @end_time:		End time of writeback latest request
+ * @wb_name:		Name of this writeback device
+ * @debugfs_root:	Root entry of writeback debugfs
+ */
+struct sde_encoder_phys_wb {
+	struct sde_encoder_phys base;
+	struct sde_hw_wb *hw_wb;
+	int irq_idx;
+	u32 wbdone_timeout;
+	u32 bypass_irqreg;
+	struct completion wbdone_complete;
+	struct sde_hw_wb_cfg wb_cfg;
+	struct sde_hw_intf_cfg intf_cfg;
+	struct sde_rect wb_roi;
+	const struct sde_format *wb_fmt;
+	u32 frame_count;
+	u32 kickoff_count;
+	int mmu_id[SDE_IOMMU_DOMAIN_MAX];
+	struct sde_wb_device *wb_dev;
+	ktime_t start_time;
+	ktime_t end_time;
+#ifdef CONFIG_DEBUG_FS
+	char wb_name[SDE_ENCODER_NAME_MAX];
+	struct dentry *debugfs_root;
+#endif
+};
+
 /**
  * sde_encoder_phys_vid_init - Construct a new video mode physical encoder
  * @sde_kms:		Pointer to the sde_kms top level
@@ -222,6 +279,44 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init(
 		struct drm_encoder *parent,
 		struct sde_encoder_virt_ops parent_ops);
 
+/**
+ * sde_encoder_phys_wb_init - Construct a new writeback physical encoder
+ * @sde_kms:		Pointer to the sde_kms top level
+ * @wb_idx:		Writeback index this phys_enc will control
+ * @ctl_idx:		Control index this phys_enc requires
+ * @cdm_idx:		Chromadown index this phys_enc requires
+ * @split_role:		Role to play in a split-panel configuration
+ * @parent:		Pointer to the containing virtual encoder
+ * @parent_ops:		Callbacks exposed by the parent to the phys_enc
+ *
+ * Return: Error code or newly allocated encoder
+ */
+#ifdef CONFIG_DRM_SDE_WB
+struct sde_encoder_phys *sde_encoder_phys_wb_init(
+		struct sde_kms *sde_kms,
+		enum sde_wb wb_idx,
+		enum sde_ctl ctl_idx,
+		enum sde_cdm cdm_idx,
+		enum sde_enc_split_role split_role,
+		struct drm_encoder *parent,
+		struct sde_encoder_virt_ops parent_ops);
+#else
+static inline
+struct sde_encoder_phys *sde_encoder_phys_wb_init(
+		struct sde_kms *sde_kms,
+		enum sde_wb wb_idx,
+		enum sde_ctl ctl_idx,
+		enum sde_cdm cdm_idx,
+		enum sde_enc_split_role split_role,
+		struct drm_encoder *parent,
+		struct sde_encoder_virt_ops parent_ops)
+{
+	return NULL;
+}
+#endif
 
+void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
+		struct drm_framebuffer *fb, const struct sde_format *format,
+		struct sde_rect *wb_roi);
 
 #endif /* __sde_encoder_phys_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
new file mode 100644
index 000000000000..5ee57312de8f
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
@@ -0,0 +1,1028 @@
+/*
+ * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"sde-wb:[%s] " fmt, __func__
+
+#include <linux/jiffies.h>
+#include <linux/debugfs.h>
+
+#include "sde_encoder_phys.h"
+#include "sde_formats.h"
+#include "sde_hw_top.h"
+#include "sde_hw_interrupts.h"
+#include "sde_wb.h"
+
+/* wait for at most 2 vsync for lowest refresh rate (24hz) */
+#define WAIT_TIMEOUT_MSEC			84
+
+#define to_sde_encoder_phys_wb(x) \
+	container_of(x, struct sde_encoder_phys_wb, base)
+
+#define DEV(phy_enc) (phy_enc->parent->dev)
+
+/**
+ * sde_encoder_phys_wb_get_intr_type - get interrupt type based on block mode
+ * @hw_wb:	Pointer to h/w writeback driver
+ */
+static enum sde_intr_type sde_encoder_phys_wb_get_intr_type(
+		struct sde_hw_wb *hw_wb)
+{
+	return (hw_wb->caps->features & BIT(SDE_WB_BLOCK_MODE)) ?
+			SDE_IRQ_TYPE_WB_ROT_COMP : SDE_IRQ_TYPE_WB_WFD_COMP;
+}
+
+/**
+ * sde_encoder_phys_wb_set_traffic_shaper - set traffic shaper for writeback
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_set_traffic_shaper(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb_cfg *wb_cfg = &wb_enc->wb_cfg;
+
+	/* traffic shaper is only enabled for rotator */
+	wb_cfg->ts_cfg.en = false;
+}
+
+/**
+ * sde_encoder_phys_setup_cdm - setup chroma down block
+ * @phys_enc:	Pointer to physical encoder
+ * @fb:		Pointer to output framebuffer
+ * @format:	Output format
+ */
+void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc,
+		struct drm_framebuffer *fb, const struct sde_format *format,
+		struct sde_rect *wb_roi)
+{
+	struct sde_hw_cdm *hw_cdm = phys_enc->hw_cdm;
+	struct sde_hw_cdm_cfg *cdm_cfg = &phys_enc->cdm_cfg;
+	int ret;
+
+	if (!SDE_FORMAT_IS_YUV(format)) {
+		SDE_DEBUG("[cdm_disable fmt:%x]\n",
+				format->base.pixel_format);
+
+		if (hw_cdm && hw_cdm->ops.disable)
+			hw_cdm->ops.disable(hw_cdm);
+
+		return;
+	}
+
+	memset(cdm_cfg, 0, sizeof(struct sde_hw_cdm_cfg));
+
+	cdm_cfg->output_width = wb_roi->w;
+	cdm_cfg->output_height = wb_roi->h;
+	cdm_cfg->output_fmt = format;
+	cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB;
+	cdm_cfg->output_bit_depth = CDM_CDWN_OUTPUT_8BIT;
+
+	/* enable 10 bit logic */
+	switch (cdm_cfg->output_fmt->chroma_sample) {
+	case SDE_CHROMA_RGB:
+		cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
+		cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
+		break;
+	case SDE_CHROMA_H2V1:
+		cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
+		cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
+		break;
+	case SDE_CHROMA_420:
+		cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
+		cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
+		break;
+	case SDE_CHROMA_H1V2:
+	default:
+		SDE_ERROR("unsupported chroma sampling type\n");
+		cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
+		cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
+		break;
+	}
+
+	SDE_DEBUG("[cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
+			cdm_cfg->output_width,
+			cdm_cfg->output_height,
+			cdm_cfg->output_fmt->base.pixel_format,
+			cdm_cfg->output_type,
+			cdm_cfg->output_bit_depth,
+			cdm_cfg->h_cdwn_type,
+			cdm_cfg->v_cdwn_type);
+
+	if (hw_cdm && hw_cdm->ops.setup_cdwn) {
+		ret = hw_cdm->ops.setup_cdwn(hw_cdm, cdm_cfg);
+		if (ret < 0) {
+			SDE_ERROR("failed to setup CDM %d\n", ret);
+			return;
+		}
+	}
+
+	if (hw_cdm && hw_cdm->ops.enable) {
+		ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
+		if (ret < 0) {
+			SDE_ERROR("failed to enable CDM %d\n", ret);
+			return;
+		}
+	}
+}
+
+/**
+ * sde_encoder_phys_wb_setup_fb - setup output framebuffer
+ * @phys_enc:	Pointer to physical encoder
+ * @fb:		Pointer to output framebuffer
+ * @wb_roi:	Pointer to output region of interest
+ */
+static void sde_encoder_phys_wb_setup_fb(struct sde_encoder_phys *phys_enc,
+		struct drm_framebuffer *fb, struct sde_rect *wb_roi)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct sde_hw_wb_cfg *wb_cfg = &wb_enc->wb_cfg;
+	const struct msm_format *format;
+	int ret, mmu_id;
+
+	memset(wb_cfg, 0, sizeof(struct sde_hw_wb_cfg));
+
+	wb_cfg->intf_mode = INTF_MODE_WB_LINE;
+	wb_cfg->is_secure = (fb->flags & DRM_MODE_FB_SECURE) ? true : false;
+	mmu_id = (wb_cfg->is_secure) ?
+			wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] :
+			wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE];
+
+	SDE_DEBUG("[fb_secure:%d]\n", wb_cfg->is_secure);
+
+	format = msm_framebuffer_format(fb);
+	wb_cfg->dest.format = sde_get_sde_format_ext(
+			format->pixel_format,
+			fb->modifier,
+			drm_format_num_planes(fb->pixel_format));
+	if (!wb_cfg->dest.format) {
+		/* this error should be detected during atomic_check */
+		SDE_ERROR("failed to get format %x\n", format->pixel_format);
+		return;
+	}
+
+	ret = sde_format_populate_layout_with_roi(mmu_id, fb, wb_roi,
+			&wb_cfg->dest);
+	if (ret) {
+		/* this error should be detected during atomic_check */
+		SDE_DEBUG("failed to populate layout %d\n", ret);
+		return;
+	}
+
+	if ((wb_cfg->dest.format->fetch_planes == SDE_PLANE_PLANAR) &&
+			(wb_cfg->dest.format->element[0] == C1_B_Cb))
+		swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
+
+	SDE_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
+			wb_cfg->dest.plane_addr[0],
+			wb_cfg->dest.plane_addr[1],
+			wb_cfg->dest.plane_addr[2],
+			wb_cfg->dest.plane_addr[3]);
+	SDE_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
+			wb_cfg->dest.plane_pitch[0],
+			wb_cfg->dest.plane_pitch[1],
+			wb_cfg->dest.plane_pitch[2],
+			wb_cfg->dest.plane_pitch[3]);
+
+	if (hw_wb->ops.setup_outformat)
+		hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
+
+	if (hw_wb->ops.setup_outaddress)
+		hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
+}
+
+/**
+ * sde_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_setup_cdp(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct sde_hw_intf_cfg *intf_cfg = &wb_enc->intf_cfg;
+
+	memset(intf_cfg, 0, sizeof(struct sde_hw_intf_cfg));
+
+	intf_cfg->intf = SDE_NONE;
+	intf_cfg->wb = hw_wb->idx;
+
+	if (phys_enc->hw_ctl->ops.setup_intf_cfg)
+		phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl,
+				intf_cfg);
+}
+
+/**
+ * sde_encoder_phys_wb_atomic_check - verify and fixup given atomic states
+ * @phys_enc:	Pointer to physical encoder
+ * @crtc_state:	Pointer to CRTC atomic state
+ * @conn_state:	Pointer to connector atomic state
+ */
+static int sde_encoder_phys_wb_atomic_check(
+		struct sde_encoder_phys *phys_enc,
+		struct drm_crtc_state *crtc_state,
+		struct drm_connector_state *conn_state)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	const struct sde_wb_cfg *wb_cfg = hw_wb->caps;
+	struct drm_framebuffer *fb;
+	const struct sde_format *fmt;
+	struct sde_rect wb_roi;
+	const struct drm_display_mode *mode = &crtc_state->mode;
+	int rc;
+
+	SDE_DEBUG("[atomic_check:%d,%d,\"%s\",%d,%d]\n",
+			hw_wb->idx - WB_0, mode->base.id, mode->name,
+			mode->hdisplay, mode->vdisplay);
+
+	memset(&wb_roi, 0, sizeof(struct sde_rect));
+
+	rc = sde_wb_connector_state_get_output_roi(conn_state, &wb_roi);
+	if (rc) {
+		SDE_ERROR("failed to get roi %d\n", rc);
+		return rc;
+	}
+
+	SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi.x, wb_roi.y,
+			wb_roi.w, wb_roi.h);
+
+	fb = sde_wb_connector_state_get_output_fb(conn_state);
+	if (!fb) {
+		SDE_ERROR("no output framebuffer\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
+			fb->width, fb->height);
+
+	fmt = sde_get_sde_format_ext(fb->pixel_format, fb->modifier,
+			drm_format_num_planes(fb->pixel_format));
+	if (!fmt) {
+		SDE_ERROR("unsupported output pixel format:%d\n",
+				fb->pixel_format);
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->pixel_format,
+			fb->modifier[0]);
+
+	if (SDE_FORMAT_IS_YUV(fmt) &&
+			!(wb_cfg->features & BIT(SDE_WB_YUV_CONFIG))) {
+		SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
+		return -EINVAL;
+	}
+
+	if (SDE_FORMAT_IS_UBWC(fmt) &&
+			!(wb_cfg->features & BIT(SDE_WB_UBWC_1_0))) {
+		SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
+		return -EINVAL;
+	}
+
+	if (wb_roi.w && wb_roi.h) {
+		if (wb_roi.w != mode->hdisplay) {
+			SDE_ERROR("invalid roi w=%d, mode w=%d\n", wb_roi.w,
+					mode->hdisplay);
+			return -EINVAL;
+		} else if (wb_roi.h != mode->vdisplay) {
+			SDE_ERROR("invalid roi h=%d, mode h=%d\n", wb_roi.h,
+					mode->vdisplay);
+			return -EINVAL;
+		} else if (wb_roi.x + wb_roi.w > fb->width) {
+			SDE_ERROR("invalid roi x=%d, w=%d, fb w=%d\n",
+					wb_roi.x, wb_roi.w, fb->width);
+			return -EINVAL;
+		} else if (wb_roi.y + wb_roi.h > fb->height) {
+			SDE_ERROR("invalid roi y=%d, h=%d, fb h=%d\n",
+					wb_roi.y, wb_roi.h, fb->height);
+			return -EINVAL;
+		} else if (wb_roi.w > wb_cfg->sblk->maxlinewidth) {
+			SDE_ERROR("invalid roi w=%d, maxlinewidth=%u\n",
+					wb_roi.w, wb_cfg->sblk->maxlinewidth);
+			return -EINVAL;
+		}
+	} else {
+		if (wb_roi.x || wb_roi.y) {
+			SDE_ERROR("invalid roi x=%d, y=%d\n",
+					wb_roi.x, wb_roi.y);
+			return -EINVAL;
+		} else if (fb->width != mode->hdisplay) {
+			SDE_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
+					mode->hdisplay);
+			return -EINVAL;
+		} else if (fb->height != mode->vdisplay) {
+			SDE_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
+					mode->vdisplay);
+			return -EINVAL;
+		} else if (fb->width > wb_cfg->sblk->maxlinewidth) {
+			SDE_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
+					fb->width, wb_cfg->sblk->maxlinewidth);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * sde_encoder_phys_wb_flush - flush hardware update
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_flush(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct sde_hw_ctl *hw_ctl = phys_enc->hw_ctl;
+	struct sde_hw_cdm *hw_cdm = phys_enc->hw_cdm;
+	u32 flush_mask = 0;
+
+	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
+
+	if (hw_ctl->ops.get_bitmask_wb)
+		hw_ctl->ops.get_bitmask_wb(hw_ctl, &flush_mask, hw_wb->idx);
+
+	if (hw_ctl->ops.get_bitmask_cdm && hw_cdm)
+		hw_ctl->ops.get_bitmask_cdm(hw_ctl, &flush_mask, hw_cdm->idx);
+
+	if (hw_ctl->ops.update_pending_flush)
+		hw_ctl->ops.update_pending_flush(hw_ctl, flush_mask);
+
+	SDE_DEBUG("Flushing CTL_ID %d, flush_mask %x, WB %d\n",
+			hw_ctl->idx - CTL_0, flush_mask, hw_wb->idx - WB_0);
+}
+
+/**
+ * sde_encoder_phys_wb_setup - setup writeback encoder
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_setup(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct drm_display_mode mode = phys_enc->cached_mode;
+	struct drm_framebuffer *fb;
+	struct sde_rect *wb_roi = &wb_enc->wb_roi;
+
+	SDE_DEBUG("[mode_set:%d,%d,\"%s\",%d,%d]\n",
+			hw_wb->idx - WB_0, mode.base.id, mode.name,
+			mode.hdisplay, mode.vdisplay);
+
+	memset(wb_roi, 0, sizeof(struct sde_rect));
+
+	fb = sde_wb_get_output_fb(wb_enc->wb_dev);
+	if (!fb) {
+		SDE_DEBUG("no output framebuffer\n");
+		return;
+	}
+
+	SDE_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
+			fb->width, fb->height);
+
+	sde_wb_get_output_roi(wb_enc->wb_dev, wb_roi);
+	if (wb_roi->w == 0 || wb_roi->h == 0) {
+		wb_roi->x = 0;
+		wb_roi->y = 0;
+		wb_roi->w = fb->width;
+		wb_roi->h = fb->height;
+	}
+
+	SDE_DEBUG("[roi:%u,%u,%u,%u]\n", wb_roi->x, wb_roi->y,
+			wb_roi->w, wb_roi->h);
+
+	wb_enc->wb_fmt = sde_get_sde_format_ext(fb->pixel_format, fb->modifier,
+			drm_format_num_planes(fb->pixel_format));
+	if (!wb_enc->wb_fmt) {
+		SDE_ERROR("unsupported output pixel format: %d\n",
+				fb->pixel_format);
+		return;
+	}
+
+	SDE_DEBUG("[fb_fmt:%x,%llx]\n", fb->pixel_format,
+			fb->modifier[0]);
+
+	sde_encoder_phys_wb_set_traffic_shaper(phys_enc);
+
+	sde_encoder_phys_setup_cdm(phys_enc, fb, wb_enc->wb_fmt, wb_roi);
+
+	sde_encoder_phys_wb_setup_fb(phys_enc, fb, wb_roi);
+
+	sde_encoder_phys_wb_setup_cdp(phys_enc);
+}
+
+/**
+ * sde_encoder_phys_wb_unregister_irq - unregister writeback interrupt handler
+ * @phys_enc:	Pointer to physical encoder
+ */
+static int sde_encoder_phys_wb_unregister_irq(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+
+	if (wb_enc->bypass_irqreg)
+		return 0;
+
+	sde_disable_irq(phys_enc->sde_kms, &wb_enc->irq_idx, 1);
+	sde_register_irq_callback(phys_enc->sde_kms, wb_enc->irq_idx, NULL);
+
+	SDE_DEBUG("un-register IRQ for wb %d, irq_idx=%d\n",
+			hw_wb->idx - WB_0,
+			wb_enc->irq_idx);
+
+	return 0;
+}
+
+/**
+ * sde_encoder_phys_wb_done_irq - writeback interrupt handler
+ * @arg:	Pointer to writeback encoder
+ * @irq_idx:	interrupt index
+ */
+static void sde_encoder_phys_wb_done_irq(void *arg, int irq_idx)
+{
+	struct sde_encoder_phys_wb *wb_enc = arg;
+	struct sde_encoder_phys *phys_enc = &wb_enc->base;
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+
+	SDE_DEBUG("[wb:%d,%u]\n", hw_wb->idx - WB_0,
+			wb_enc->frame_count);
+
+	complete_all(&wb_enc->wbdone_complete);
+
+	phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent);
+}
+
+/**
+ * sde_encoder_phys_wb_register_irq - register writeback interrupt handler
+ * @phys_enc:	Pointer to physical encoder
+ */
+static int sde_encoder_phys_wb_register_irq(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct sde_irq_callback irq_cb;
+	enum sde_intr_type intr_type;
+	int ret = 0;
+
+	if (wb_enc->bypass_irqreg)
+		return 0;
+
+	intr_type = sde_encoder_phys_wb_get_intr_type(hw_wb);
+	wb_enc->irq_idx = sde_irq_idx_lookup(phys_enc->sde_kms,
+			intr_type, hw_wb->idx);
+	if (wb_enc->irq_idx < 0) {
+		SDE_ERROR(
+			"failed to lookup IRQ index for WB_DONE with wb=%d\n",
+			hw_wb->idx - WB_0);
+		return -EINVAL;
+	}
+
+	irq_cb.func = sde_encoder_phys_wb_done_irq;
+	irq_cb.arg = wb_enc;
+	ret = sde_register_irq_callback(phys_enc->sde_kms, wb_enc->irq_idx,
+			&irq_cb);
+	if (ret) {
+		SDE_ERROR("failed to register IRQ callback WB_DONE\n");
+		return ret;
+	}
+
+	ret = sde_enable_irq(phys_enc->sde_kms, &wb_enc->irq_idx, 1);
+	if (ret) {
+		SDE_ERROR(
+			"failed to enable IRQ for WB_DONE, wb %d, irq_idx=%d\n",
+				hw_wb->idx - WB_0,
+				wb_enc->irq_idx);
+		wb_enc->irq_idx = -EINVAL;
+
+		/* Unregister callback on IRQ enable failure */
+		sde_register_irq_callback(phys_enc->sde_kms, wb_enc->irq_idx,
+				NULL);
+		return ret;
+	}
+
+	SDE_DEBUG("registered IRQ for wb %d, irq_idx=%d\n",
+			hw_wb->idx - WB_0,
+			wb_enc->irq_idx);
+
+	return ret;
+}
+
+/**
+ * sde_encoder_phys_wb_mode_set - set display mode
+ * @phys_enc:	Pointer to physical encoder
+ * @mode:	Pointer to requested display mode
+ * @adj_mode:	Pointer to adjusted display mode
+ */
+static void sde_encoder_phys_wb_mode_set(
+		struct sde_encoder_phys *phys_enc,
+		struct drm_display_mode *mode,
+		struct drm_display_mode *adj_mode)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+
+	phys_enc->cached_mode = *adj_mode;
+
+	SDE_DEBUG("[mode_set_cache:%d,%d,\"%s\",%d,%d]\n",
+			hw_wb->idx - WB_0, mode->base.id,
+			mode->name, mode->hdisplay, mode->vdisplay);
+}
+
+/**
+ * sde_encoder_phys_wb_control_vblank_irq - Control vblank interrupt
+ * @phys_enc:	Pointer to physical encoder
+ * @enable:	Enable interrupt
+ */
+static int sde_encoder_phys_wb_control_vblank_irq(
+		struct sde_encoder_phys *phys_enc,
+		bool enable)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	int ret = 0;
+
+	SDE_DEBUG("[wb:%d,%d]\n", hw_wb->idx - WB_0, enable);
+
+	if (enable)
+		ret = sde_encoder_phys_wb_register_irq(phys_enc);
+	else
+		ret = sde_encoder_phys_wb_unregister_irq(phys_enc);
+
+	if (ret)
+		SDE_ERROR("control vblank irq error %d, enable %d\n", ret,
+				enable);
+
+	return ret;
+}
+
+/**
+ * sde_encoder_phys_wb_wait_for_commit_done - wait until request is committed
+ * @phys_enc:	Pointer to physical encoder
+ */
+static int sde_encoder_phys_wb_wait_for_commit_done(
+		struct sde_encoder_phys *phys_enc)
+{
+	unsigned long ret;
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	u32 irq_status;
+	u64 wb_time = 0;
+	int rc = 0;
+
+	/* Return EWOULDBLOCK since we know the wait isn't necessary */
+	if (WARN_ON(phys_enc->enable_state != SDE_ENC_ENABLED))
+		return -EWOULDBLOCK;
+
+	MSM_EVT(DEV(phys_enc), wb_enc->frame_count, 0);
+
+	ret = wait_for_completion_timeout(&wb_enc->wbdone_complete,
+			msecs_to_jiffies(wb_enc->wbdone_timeout));
+
+	if (!ret) {
+		MSM_EVT(DEV(phys_enc), wb_enc->frame_count, 0);
+
+		irq_status = sde_read_irq(phys_enc->sde_kms,
+				wb_enc->irq_idx, true);
+		if (irq_status) {
+			SDE_DEBUG("wb:%d done but irq not triggered\n",
+					wb_enc->wb_dev->wb_idx - WB_0);
+			sde_encoder_phys_wb_done_irq(wb_enc, wb_enc->irq_idx);
+		} else {
+			SDE_ERROR("wb:%d kickoff timed out\n",
+					wb_enc->wb_dev->wb_idx - WB_0);
+			rc = -ETIMEDOUT;
+		}
+	}
+
+	sde_encoder_phys_wb_unregister_irq(phys_enc);
+
+	if (!rc)
+		wb_enc->end_time = ktime_get();
+
+	/* once operation is done, disable traffic shaper */
+	if (wb_enc->wb_cfg.ts_cfg.en && wb_enc->hw_wb &&
+			wb_enc->hw_wb->ops.setup_trafficshaper) {
+		wb_enc->wb_cfg.ts_cfg.en = false;
+		wb_enc->hw_wb->ops.setup_trafficshaper(
+				wb_enc->hw_wb, &wb_enc->wb_cfg);
+	}
+
+	/* remove vote for iommu/clk/bus */
+	wb_enc->frame_count++;
+
+	if (!rc) {
+		wb_time = (u64)ktime_to_us(wb_enc->end_time) -
+				(u64)ktime_to_us(wb_enc->start_time);
+		SDE_DEBUG("wb:%d took %llu us\n",
+			wb_enc->wb_dev->wb_idx - WB_0, wb_time);
+	}
+
+	MSM_EVT(DEV(phys_enc), wb_enc->frame_count, wb_time);
+
+	return rc;
+}
+
+/**
+ * sde_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
+ * @phys_enc:	Pointer to physical encoder
+ * @need_to_wait:	 Wait for next submission
+ */
+static void sde_encoder_phys_wb_prepare_for_kickoff(
+		struct sde_encoder_phys *phys_enc,
+		bool *need_to_wait)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	int ret;
+
+	SDE_DEBUG("[wb:%d,%u]\n", wb_enc->hw_wb->idx - WB_0,
+			wb_enc->kickoff_count);
+
+	*need_to_wait = false;
+
+	reinit_completion(&wb_enc->wbdone_complete);
+
+	ret = sde_encoder_phys_wb_register_irq(phys_enc);
+	if (ret) {
+		SDE_ERROR("failed to register irq %d\n", ret);
+		return;
+	}
+
+	wb_enc->kickoff_count++;
+
+	/* set OT limit & enable traffic shaper */
+	sde_encoder_phys_wb_setup(phys_enc);
+
+	sde_encoder_phys_wb_flush(phys_enc);
+
+	/* vote for iommu/clk/bus */
+	wb_enc->start_time = ktime_get();
+
+	MSM_EVT(DEV(phys_enc), *need_to_wait, wb_enc->kickoff_count);
+}
+
+/**
+ * sde_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_handle_post_kickoff(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+
+	SDE_DEBUG("[wb:%d]\n", wb_enc->hw_wb->idx - WB_0);
+
+	MSM_EVT(DEV(phys_enc), 0, 0);
+}
+
+/**
+ * sde_encoder_phys_wb_enable - enable writeback encoder
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_enable(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	struct drm_connector *connector;
+
+	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
+
+	/* find associated writeback connector */
+	drm_for_each_connector(connector, phys_enc->parent->dev) {
+		if (connector->encoder == phys_enc->parent)
+			break;
+	}
+	if (!connector || connector->encoder != phys_enc->parent) {
+		SDE_ERROR("failed to find writeback connector\n");
+		return;
+	}
+	wb_enc->wb_dev = sde_wb_connector_get_wb(connector);
+
+	phys_enc->enable_state = SDE_ENC_ENABLED;
+}
+
+/**
+ * sde_encoder_phys_wb_disable - disable writeback encoder
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+
+	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
+
+	if (phys_enc->enable_state == SDE_ENC_DISABLED) {
+		SDE_ERROR("encoder is already disabled\n");
+		return;
+	}
+
+	if (wb_enc->frame_count != wb_enc->kickoff_count) {
+		SDE_DEBUG("[wait_for_done: wb:%d, frame:%u, kickoff:%u]\n",
+				hw_wb->idx - WB_0, wb_enc->frame_count,
+				wb_enc->kickoff_count);
+		sde_encoder_phys_wb_wait_for_commit_done(phys_enc);
+	}
+
+	phys_enc->enable_state = SDE_ENC_DISABLED;
+}
+
+/**
+ * sde_encoder_phys_wb_get_hw_resources - get hardware resources
+ * @phys_enc:	Pointer to physical encoder
+ * @hw_res:	Pointer to encoder resources
+ */
+static void sde_encoder_phys_wb_get_hw_resources(
+		struct sde_encoder_phys *phys_enc,
+		struct sde_encoder_hw_resources *hw_res)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+	const struct sde_hw_res_map *hw_res_map;
+
+	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
+
+	hw_res->wbs[hw_wb->idx] = INTF_MODE_WB_LINE;
+
+	/*
+	 * Validate if we want to use the default map
+	 * defaults should not be in use,
+	 * otherwise signal/return failure
+	 */
+	hw_res_map = sde_rm_get_res_map(phys_enc->sde_kms,
+			SDE_NONE, hw_wb->idx);
+	if (IS_ERR_OR_NULL(hw_res_map)) {
+		SDE_ERROR("failed to get hw_res_map: %ld\n",
+				PTR_ERR(hw_res_map));
+		return;
+	}
+
+	/*
+	 * cached ctl_idx at init time, shouldn't we use that?
+	 */
+	hw_res->ctls[hw_res_map->ctl] = true;
+}
+
+#ifdef CONFIG_DEBUG_FS
+/**
+ * sde_encoder_phys_wb_init_debugfs - initialize writeback encoder debugfs
+ * @phys_enc:	Pointer to physical encoder
+ * @sde_kms:	Pointer to SDE KMS object
+ */
+static int sde_encoder_phys_wb_init_debugfs(
+		struct sde_encoder_phys *phys_enc, struct sde_kms *kms)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+
+	if (!phys_enc || !kms || !wb_enc->hw_wb)
+		return -EINVAL;
+
+	snprintf(wb_enc->wb_name, ARRAY_SIZE(wb_enc->wb_name), "encoder_wb%d",
+			wb_enc->hw_wb->idx - WB_0);
+
+	wb_enc->debugfs_root =
+		debugfs_create_dir(wb_enc->wb_name,
+				sde_debugfs_get_root(kms));
+	if (!wb_enc->debugfs_root) {
+		SDE_ERROR("failed to create debugfs\n");
+		return -ENOMEM;
+	}
+
+	if (!debugfs_create_u32("wbdone_timeout", S_IRUGO | S_IWUSR,
+			wb_enc->debugfs_root, &wb_enc->wbdone_timeout)) {
+		SDE_ERROR("failed to create debugfs/wbdone_timeout\n");
+		return -ENOMEM;
+	}
+
+	if (!debugfs_create_u32("bypass_irqreg", S_IRUGO | S_IWUSR,
+			wb_enc->debugfs_root, &wb_enc->bypass_irqreg)) {
+		SDE_ERROR("failed to create debugfs/bypass_irqreg\n");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+/**
+ * sde_encoder_phys_wb_destroy_debugfs - destroy writeback encoder debugfs
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_destroy_debugfs(
+		struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+
+	if (!phys_enc)
+		return;
+
+	debugfs_remove_recursive(wb_enc->debugfs_root);
+}
+#else
+static void sde_encoder_phys_wb_init_debugfs(
+		struct sde_encoder_phys *phys_enc, struct sde_kms *kms)
+{
+}
+static void sde_encoder_phys_wb_destroy_debugfs(
+		struct sde_encoder_phys *phys_enc)
+{
+}
+#endif
+
+/**
+ * sde_encoder_phys_wb_destroy - destroy writeback encoder
+ * @phys_enc:	Pointer to physical encoder
+ */
+static void sde_encoder_phys_wb_destroy(struct sde_encoder_phys *phys_enc)
+{
+	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
+	struct sde_hw_wb *hw_wb = wb_enc->hw_wb;
+
+	SDE_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
+
+	if (!phys_enc)
+		return;
+
+	sde_encoder_phys_wb_destroy_debugfs(phys_enc);
+
+	if (phys_enc->hw_ctl)
+		sde_rm_release_ctl_path(phys_enc->sde_kms,
+				phys_enc->hw_ctl->idx);
+	if (phys_enc->hw_cdm)
+		sde_rm_release_cdm_path(phys_enc->sde_kms,
+				phys_enc->hw_cdm->idx);
+	if (hw_wb)
+		sde_hw_wb_destroy(hw_wb);
+	if (phys_enc->hw_mdptop)
+		sde_hw_mdp_destroy(phys_enc->hw_mdptop);
+
+	kfree(wb_enc);
+}
+
+/**
+ * sde_encoder_phys_wb_init_ops - initialize writeback operations
+ * @ops:	Pointer to encoder operation table
+ */
+static void sde_encoder_phys_wb_init_ops(struct sde_encoder_phys_ops *ops)
+{
+	ops->mode_set = sde_encoder_phys_wb_mode_set;
+	ops->enable = sde_encoder_phys_wb_enable;
+	ops->disable = sde_encoder_phys_wb_disable;
+	ops->destroy = sde_encoder_phys_wb_destroy;
+	ops->atomic_check = sde_encoder_phys_wb_atomic_check;
+	ops->get_hw_resources = sde_encoder_phys_wb_get_hw_resources;
+	ops->control_vblank_irq = sde_encoder_phys_wb_control_vblank_irq;
+	ops->wait_for_commit_done = sde_encoder_phys_wb_wait_for_commit_done;
+	ops->prepare_for_kickoff = sde_encoder_phys_wb_prepare_for_kickoff;
+	ops->handle_post_kickoff = sde_encoder_phys_wb_handle_post_kickoff;
+}
+
+/**
+ * sde_encoder_phys_wb_init - initialize writeback encoder
+ * @sde_kms:	Pointer to SDE KMS object
+ * @wb_idx:	Writeback index
+ * @ctl_idx:	Control index
+ * @cdm_idx:	Chroma down index
+ * @split_role:	Master/slave mode
+ * @parent:	Pointer to virtual encoder
+ * @parent_ops:	Pointer to virtual encoder operations
+ */
+struct sde_encoder_phys *sde_encoder_phys_wb_init(
+		struct sde_kms *sde_kms,
+		enum sde_wb wb_idx,
+		enum sde_ctl ctl_idx,
+		enum sde_cdm cdm_idx,
+		enum sde_enc_split_role split_role,
+		struct drm_encoder *parent,
+		struct sde_encoder_virt_ops parent_ops)
+{
+	struct sde_encoder_phys *phys_enc;
+	struct sde_encoder_phys_wb *wb_enc;
+	struct sde_hw_mdp *hw_mdp;
+	int ret = 0;
+
+	SDE_DEBUG("\n");
+
+	wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);
+	if (!wb_enc) {
+		ret = -ENOMEM;
+		goto fail_alloc;
+	}
+	wb_enc->irq_idx = -EINVAL;
+	wb_enc->wbdone_timeout = WAIT_TIMEOUT_MSEC;
+	init_completion(&wb_enc->wbdone_complete);
+
+	phys_enc = &wb_enc->base;
+
+	if (sde_kms->vbif[VBIF_NRT]) {
+		wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] =
+			sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_UNSECURE];
+		wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] =
+			sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_SECURE];
+	} else {
+		wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] =
+			sde_kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
+		wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] =
+			sde_kms->mmu_id[MSM_SMMU_DOMAIN_SECURE];
+	}
+
+	hw_mdp = sde_hw_mdptop_init(MDP_TOP, sde_kms->mmio, sde_kms->catalog);
+	if (IS_ERR_OR_NULL(hw_mdp)) {
+		ret = PTR_ERR(hw_mdp);
+		SDE_ERROR("failed to init hw_top: %d\n", ret);
+		goto fail_mdp_init;
+	}
+	phys_enc->hw_mdptop = hw_mdp;
+
+	if (wb_idx != SDE_NONE) {
+		struct sde_hw_wb *hw_wb;
+
+		hw_wb = sde_hw_wb_init(wb_idx, sde_kms->mmio,
+				sde_kms->catalog, phys_enc->hw_mdptop);
+		if (IS_ERR_OR_NULL(hw_wb)) {
+			ret = PTR_ERR(hw_wb);
+			SDE_ERROR("failed to init hw_wb%d: %d\n",
+					wb_idx - WB_0, ret);
+			goto fail_wb_init;
+		}
+		wb_enc->hw_wb = hw_wb;
+	} else {
+		ret = -EINVAL;
+		SDE_ERROR("invalid wb_idx\n");
+		goto fail_wb_check;
+	}
+
+	if (cdm_idx != SDE_NONE) {
+		struct sde_hw_cdm *hw_cdm;
+
+		SDE_DEBUG("Acquiring CDM %d\n", cdm_idx - CDM_0);
+		hw_cdm = sde_rm_acquire_cdm_path(sde_kms, cdm_idx,
+				phys_enc->hw_mdptop);
+		if (IS_ERR_OR_NULL(hw_cdm)) {
+			ret = PTR_ERR(hw_cdm);
+			SDE_ERROR("failed to init hw_cdm%d: %d\n",
+					cdm_idx - CDM_0, ret);
+			goto fail_cdm_init;
+		}
+		phys_enc->hw_cdm = hw_cdm;
+	}
+
+	if (ctl_idx != SDE_NONE) {
+		struct sde_hw_ctl *hw_ctl;
+
+		SDE_DEBUG("Acquiring CTL %d\n", ctl_idx - CTL_0);
+		hw_ctl = sde_rm_acquire_ctl_path(sde_kms, ctl_idx);
+		if (IS_ERR_OR_NULL(hw_ctl)) {
+			ret = PTR_ERR(hw_ctl);
+			SDE_ERROR("failed to init hw_ctl%d: %d\n",
+					ctl_idx - CTL_0, ret);
+			goto fail_ctl_init;
+		}
+		phys_enc->hw_ctl = hw_ctl;
+	} else {
+		ret = -EINVAL;
+		SDE_ERROR("invalid ctl_idx\n");
+		goto fail_ctl_check;
+	}
+
+	sde_encoder_phys_wb_init_ops(&phys_enc->ops);
+	phys_enc->parent = parent;
+	phys_enc->parent_ops = parent_ops;
+	phys_enc->sde_kms = sde_kms;
+	phys_enc->split_role = split_role;
+	spin_lock_init(&phys_enc->spin_lock);
+
+	ret = sde_encoder_phys_wb_init_debugfs(phys_enc, sde_kms);
+	if (ret) {
+		SDE_ERROR("failed to init debugfs %d\n", ret);
+		goto fail_debugfs_init;
+	}
+
+	SDE_DEBUG("Created sde_encoder_phys_wb for wb %d\n",
+			wb_enc->hw_wb->idx - WB_0);
+
+	return phys_enc;
+
+fail_debugfs_init:
+	sde_rm_release_ctl_path(sde_kms, ctl_idx);
+fail_ctl_init:
+fail_ctl_check:
+	sde_rm_release_cdm_path(sde_kms, cdm_idx);
+fail_cdm_init:
+	sde_hw_wb_destroy(wb_enc->hw_wb);
+fail_wb_init:
+fail_wb_check:
+	sde_hw_mdp_destroy(phys_enc->hw_mdptop);
+fail_mdp_init:
+	kfree(wb_enc);
+fail_alloc:
+	return ERR_PTR(ret);
+}
+
diff --git a/drivers/gpu/drm/msm/sde/sde_formats.c b/drivers/gpu/drm/msm/sde/sde_formats.c
index 5655a8ae938e..6d9c57402085 100644
--- a/drivers/gpu/drm/msm/sde/sde_formats.c
+++ b/drivers/gpu/drm/msm/sde/sde_formats.c
@@ -363,6 +363,9 @@ static void _sde_get_v_h_subsample_rate(
 	uint32_t *v_sample,
 	uint32_t *h_sample)
 {
+	if (!v_sample || !h_sample)
+		return;
+
 	switch (chroma_sample) {
 	case SDE_CHROMA_H2V1:
 		*v_sample = 1;
@@ -702,6 +705,69 @@ int sde_format_populate_layout(
 	return ret;
 }
 
+static void _sde_format_calc_offset_linear(struct sde_hw_fmt_layout *source,
+		u32 x, u32 y)
+{
+	if ((x == 0) && (y == 0))
+		return;
+
+	source->plane_addr[0] += y * source->plane_pitch[0];
+
+	if (source->num_planes == 1) {
+		source->plane_addr[0] += x * source->format->bpp;
+	} else {
+		uint32_t xoff, yoff;
+		uint32_t v_subsample = 1;
+		uint32_t h_subsample = 1;
+
+		_sde_get_v_h_subsample_rate(source->format->chroma_sample,
+				&v_subsample, &h_subsample);
+
+		xoff = x / h_subsample;
+		yoff = y / v_subsample;
+
+		source->plane_addr[0] += x;
+		source->plane_addr[1] += xoff +
+				(yoff * source->plane_pitch[1]);
+		if (source->num_planes == 2) /* pseudo planar */
+			source->plane_addr[1] += xoff;
+		else /* planar */
+			source->plane_addr[2] += xoff +
+				(yoff * source->plane_pitch[2]);
+	}
+}
+
+int sde_format_populate_layout_with_roi(
+		int mmu_id,
+		struct drm_framebuffer *fb,
+		struct sde_rect *roi,
+		struct sde_hw_fmt_layout *layout)
+{
+	int ret;
+
+	ret = sde_format_populate_layout(mmu_id, fb, layout);
+	if (ret || !roi)
+		return ret;
+
+	if (!roi->w || !roi->h || (roi->x + roi->w > fb->width) ||
+			(roi->y + roi->h > fb->height)) {
+		DRM_ERROR("invalid roi=[%d,%d,%d,%d], fb=[%u,%u]\n",
+				roi->x, roi->y, roi->w, roi->h,
+				fb->width, fb->height);
+		ret = -EINVAL;
+	} else if (SDE_FORMAT_IS_LINEAR(layout->format)) {
+		_sde_format_calc_offset_linear(layout, roi->x, roi->y);
+		layout->width = roi->w;
+		layout->height = roi->h;
+	} else if (roi->x || roi->y || (roi->w != fb->width) ||
+			(roi->h != fb->height)) {
+		DRM_ERROR("non-linear layout with roi not supported\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
 int sde_format_check_modified_format(
 		const struct msm_kms *kms,
 		const struct msm_format *msm_fmt,
diff --git a/drivers/gpu/drm/msm/sde/sde_formats.h b/drivers/gpu/drm/msm/sde/sde_formats.h
index c89048414ff9..db2a4d3d8b26 100644
--- a/drivers/gpu/drm/msm/sde/sde_formats.h
+++ b/drivers/gpu/drm/msm/sde/sde_formats.h
@@ -87,4 +87,20 @@ int sde_format_populate_layout(
 		struct drm_framebuffer *fb,
 		struct sde_hw_fmt_layout *fmtl);
 
+/**
+ * sde_format_populate_layout_with_roi - populate the given format layout
+ *                     based on mmu, fb, roi, and format found in the fb
+ * @mmu_id:            mmu id handle
+ * @fb:                framebuffer pointer
+ * @roi:               region of interest (optional)
+ * @fmtl:              format layout structure to populate
+ *
+ * Return: error code on failure, 0 on success
+ */
+int sde_format_populate_layout_with_roi(
+		int mmu_id,
+		struct drm_framebuffer *fb,
+		struct sde_rect *roi,
+		struct sde_hw_fmt_layout *fmtl);
+
 #endif /*_SDE_FORMATS_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 3ac1af742fe6..e340ca2d56e9 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -408,10 +408,13 @@ struct sde_intf_cfg  {
  * @id                 enum identifying this block
  * @base               register offset of this block
  * @features           bit mask identifying sub-blocks/features
+ * @sblk               sub-block information
+ * @format_list: Pointer to list of supported formats
  */
 struct sde_wb_cfg {
 	SDE_HW_BLK_INFO;
-	struct sde_wb_sub_blocks *sblk;
+	const struct sde_wb_sub_blocks *sblk;
+	const struct sde_format_extended *format_list;
 };
 
 /**
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c
index 2f8bcc00e857..f071437fb176 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c
@@ -140,6 +140,89 @@ static const struct sde_format_extended plane_formats_yuv[] = {
 	{0, 0},
 };
 
+static const struct sde_format_extended wb0_formats[] = {
+	{DRM_FORMAT_RGB565, 0},
+	{DRM_FORMAT_RGB888, 0},
+	{DRM_FORMAT_ARGB8888, 0},
+	{DRM_FORMAT_RGBA8888, 0},
+	{DRM_FORMAT_XRGB8888, 0},
+	{DRM_FORMAT_RGBX8888, 0},
+	{DRM_FORMAT_ARGB1555, 0},
+	{DRM_FORMAT_RGBA5551, 0},
+	{DRM_FORMAT_XRGB1555, 0},
+	{DRM_FORMAT_RGBX5551, 0},
+	{DRM_FORMAT_ARGB4444, 0},
+	{DRM_FORMAT_RGBA4444, 0},
+	{DRM_FORMAT_RGBX4444, 0},
+	{DRM_FORMAT_XRGB4444, 0},
+
+	{DRM_FORMAT_BGR565, 0},
+	{DRM_FORMAT_BGR888, 0},
+	{DRM_FORMAT_ABGR8888, 0},
+	{DRM_FORMAT_BGRA8888, 0},
+	{DRM_FORMAT_BGRX8888, 0},
+	{DRM_FORMAT_ABGR1555, 0},
+	{DRM_FORMAT_BGRA5551, 0},
+	{DRM_FORMAT_XBGR1555, 0},
+	{DRM_FORMAT_BGRX5551, 0},
+	{DRM_FORMAT_ABGR4444, 0},
+	{DRM_FORMAT_BGRA4444, 0},
+	{DRM_FORMAT_BGRX4444, 0},
+	{DRM_FORMAT_XBGR4444, 0},
+
+	{DRM_FORMAT_RGBX8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_RGBA8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_RGB565, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+
+	{DRM_FORMAT_YUV420, 0},
+	{DRM_FORMAT_NV12, 0},
+	{DRM_FORMAT_NV16, 0},
+	{DRM_FORMAT_YUYV, 0},
+
+	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_AYUV, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+
+	{0, 0},
+};
+
+static const struct sde_format_extended wb2_formats[] = {
+	{DRM_FORMAT_RGB565, 0},
+	{DRM_FORMAT_RGB888, 0},
+	{DRM_FORMAT_ARGB8888, 0},
+	{DRM_FORMAT_RGBA8888, 0},
+	{DRM_FORMAT_XRGB8888, 0},
+	{DRM_FORMAT_RGBX8888, 0},
+	{DRM_FORMAT_ARGB1555, 0},
+	{DRM_FORMAT_RGBA5551, 0},
+	{DRM_FORMAT_XRGB1555, 0},
+	{DRM_FORMAT_RGBX5551, 0},
+	{DRM_FORMAT_ARGB4444, 0},
+	{DRM_FORMAT_RGBA4444, 0},
+	{DRM_FORMAT_RGBX4444, 0},
+	{DRM_FORMAT_XRGB4444, 0},
+
+	{DRM_FORMAT_BGR565, 0},
+	{DRM_FORMAT_BGR888, 0},
+	{DRM_FORMAT_ABGR8888, 0},
+	{DRM_FORMAT_BGRA8888, 0},
+	{DRM_FORMAT_BGRX8888, 0},
+	{DRM_FORMAT_ABGR1555, 0},
+	{DRM_FORMAT_BGRA5551, 0},
+	{DRM_FORMAT_XBGR1555, 0},
+	{DRM_FORMAT_BGRX5551, 0},
+	{DRM_FORMAT_ABGR4444, 0},
+	{DRM_FORMAT_BGRA4444, 0},
+	{DRM_FORMAT_BGRX4444, 0},
+	{DRM_FORMAT_XBGR4444, 0},
+
+	{DRM_FORMAT_YUV420, 0},
+	{DRM_FORMAT_NV12, 0},
+	{DRM_FORMAT_NV16, 0},
+	{DRM_FORMAT_YUYV, 0},
+
+	{0, 0},
+};
+
 /**
  * set_cfg_1xx_init(): populate sde sub-blocks reg offsets and instance counts
  */
@@ -257,6 +340,16 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg)
 			.version = 0x1},
 	};
 
+	/* Writeback 0/1 capability */
+	static const struct sde_wb_sub_blocks wb0 = {
+		.maxlinewidth = 2048,
+	};
+
+	/* Writeback 2 capability */
+	static const struct sde_wb_sub_blocks wb2 = {
+		.maxlinewidth = 4096,
+	};
+
 	/* Setup Register maps and defaults */
 	*cfg = (struct sde_mdss_cfg){
 		.mdss_count = 1,
@@ -376,11 +469,17 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg)
 		.wb_count = 3,
 		.wb = {
 			{.id = WB_0, .base = 0x00065000,
-				.features = WB01_17X_MASK},
+				.features = WB01_17X_MASK,
+				.sblk = &wb0,
+				.format_list = wb0_formats},
 			{.id = WB_1, .base = 0x00065800,
-				.features = WB01_17X_MASK},
+				.features = WB01_17X_MASK,
+				.sblk = &wb0,
+				.format_list = wb0_formats},
 			{.id = WB_2, .base = 0x00066000,
-				.features = WB2_17X_MASK},
+				.features = WB2_17X_MASK,
+				.sblk = &wb2,
+				.format_list = wb2_formats},
 		},
 		.ad_count = 2,
 		.ad = {
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
index 73cecbf45d65..a4f5656ad3da 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
@@ -148,7 +148,10 @@ enum sde_intf_type {
 	INTF_HDMI = 0x3,
 	INTF_LCDC = 0x5,
 	INTF_EDP = 0x9,
-	INTF_TYPE_MAX
+	INTF_TYPE_MAX,
+
+	/* virtual interfaces */
+	INTF_WB = 0x100,
 };
 
 enum sde_intf_mode {
diff --git a/drivers/gpu/drm/msm/sde/sde_wb.c b/drivers/gpu/drm/msm/sde/sde_wb.c
new file mode 100644
index 000000000000..2d2f7cf340be
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_wb.c
@@ -0,0 +1,692 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"sde-wb:[%s] " fmt, __func__
+
+#include "msm_kms.h"
+#include "sde_kms.h"
+#include "sde_wb.h"
+#include "sde_formats.h"
+
+/* maximum display mode resolution if not available from catalog */
+#define SDE_WB_MODE_MAX_WIDTH	4096
+#define SDE_WB_MODE_MAX_HEIGHT	4096
+
+/* Serialization lock for sde_wb_list */
+static DEFINE_MUTEX(sde_wb_list_lock);
+
+/* List of all writeback devices installed */
+static LIST_HEAD(sde_wb_list);
+
+/**
+ * sde_wb_is_format_valid - check if given format/modifier is supported
+ * @wb_dev:	Pointer to writeback device
+ * @pixel_format:	Fourcc pixel format
+ * @format_modifier:	Format modifier
+ * Returns:		true if valid; false otherwise
+ */
+static int sde_wb_is_format_valid(struct sde_wb_device *wb_dev,
+		u32 pixel_format, u64 format_modifier)
+{
+	const struct sde_format_extended *fmts = wb_dev->wb_cfg->format_list;
+	int i;
+
+	if (!fmts)
+		return false;
+
+	for (i = 0; fmts[i].fourcc_format; i++)
+		if ((fmts[i].modifier == format_modifier) &&
+				(fmts[i].fourcc_format == pixel_format))
+			return true;
+
+	return false;
+}
+
+enum drm_connector_status
+sde_wb_connector_detect(struct drm_connector *connector,
+		bool force,
+		void *display)
+{
+	enum drm_connector_status rc = connector_status_unknown;
+
+	SDE_DEBUG("\n");
+
+	if (display)
+		rc = ((struct sde_wb_device *)display)->detect_status;
+
+	return rc;
+}
+
+int sde_wb_connector_get_modes(struct drm_connector *connector, void *display)
+{
+	struct sde_wb_device *wb_dev;
+	int num_modes = 0;
+
+	if (!connector || !display)
+		return 0;
+
+	wb_dev = display;
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	if (wb_dev->count_modes && wb_dev->modes) {
+		struct drm_display_mode *mode;
+		int i, ret;
+
+		for (i = 0; i < wb_dev->count_modes; i++) {
+			mode = drm_mode_create(connector->dev);
+			if (!mode) {
+				SDE_ERROR("failed to create mode\n");
+				break;
+			}
+			ret = drm_mode_convert_umode(mode,
+					&wb_dev->modes[i]);
+			if (ret) {
+				SDE_ERROR("failed to convert mode %d\n", ret);
+				break;
+			}
+
+			drm_mode_probed_add(connector, mode);
+			num_modes++;
+		}
+	} else {
+		u32 max_width = (wb_dev->wb_cfg && wb_dev->wb_cfg->sblk) ?
+				wb_dev->wb_cfg->sblk->maxlinewidth :
+				SDE_WB_MODE_MAX_WIDTH;
+
+		num_modes = drm_add_modes_noedid(connector, max_width,
+				SDE_WB_MODE_MAX_HEIGHT);
+	}
+	mutex_unlock(&wb_dev->wb_lock);
+	return num_modes;
+}
+
+struct drm_framebuffer *
+sde_wb_connector_state_get_output_fb(struct drm_connector_state *state)
+{
+	if (!state || !state->connector ||
+		(state->connector->connector_type !=
+				DRM_MODE_CONNECTOR_VIRTUAL)) {
+		SDE_ERROR("invalid params\n");
+		return NULL;
+	}
+
+	SDE_DEBUG("\n");
+
+	return sde_connector_get_out_fb(state);
+}
+
+int sde_wb_connector_state_get_output_roi(struct drm_connector_state *state,
+		struct sde_rect *roi)
+{
+	if (!state || !roi || !state->connector ||
+		(state->connector->connector_type !=
+				DRM_MODE_CONNECTOR_VIRTUAL)) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	roi->x = sde_connector_get_property(state, CONNECTOR_PROP_DST_X);
+	roi->y = sde_connector_get_property(state, CONNECTOR_PROP_DST_Y);
+	roi->w = sde_connector_get_property(state, CONNECTOR_PROP_DST_W);
+	roi->h = sde_connector_get_property(state, CONNECTOR_PROP_DST_H);
+
+	return 0;
+}
+
+/**
+ * sde_wb_connector_set_modes - set writeback modes and connection status
+ * @wb_dev:	Pointer to write back device
+ * @count_modes:	Count of modes
+ * @modes:	Pointer to writeback mode requested
+ * @connected:	Connection status requested
+ * Returns:	0 if success; error code otherwise
+ */
+static
+int sde_wb_connector_set_modes(struct sde_wb_device *wb_dev,
+		u32 count_modes, struct drm_mode_modeinfo __user *modes,
+		bool connected)
+{
+	int ret = 0;
+
+	if (!wb_dev || !wb_dev->connector ||
+			(wb_dev->connector->connector_type !=
+			 DRM_MODE_CONNECTOR_VIRTUAL)) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	if (connected) {
+		SDE_DEBUG("connect\n");
+
+		if (wb_dev->modes) {
+			wb_dev->count_modes = 0;
+
+			kfree(wb_dev->modes);
+			wb_dev->modes = NULL;
+		}
+
+		if (count_modes && modes) {
+			wb_dev->modes = kcalloc(count_modes,
+					sizeof(struct drm_mode_modeinfo),
+					GFP_KERNEL);
+			if (!wb_dev->modes) {
+				SDE_ERROR("invalid params\n");
+				ret = -ENOMEM;
+				goto error;
+			}
+
+			if (copy_from_user(wb_dev->modes, modes,
+					count_modes *
+					sizeof(struct drm_mode_modeinfo))) {
+				SDE_ERROR("failed to copy modes\n");
+				kfree(wb_dev->modes);
+				wb_dev->modes = NULL;
+				ret = -EFAULT;
+				goto error;
+			}
+
+			wb_dev->count_modes = count_modes;
+		}
+
+		wb_dev->detect_status = connector_status_connected;
+	} else {
+		SDE_DEBUG("disconnect\n");
+
+		if (wb_dev->modes) {
+			wb_dev->count_modes = 0;
+
+			kfree(wb_dev->modes);
+			wb_dev->modes = NULL;
+		}
+
+		wb_dev->detect_status = connector_status_disconnected;
+	}
+
+error:
+	return ret;
+}
+
+int sde_wb_connector_set_property(struct drm_connector *connector,
+		struct drm_connector_state *state,
+		int property_index,
+		uint64_t value,
+		void *display)
+{
+	struct sde_wb_device *wb_dev = display;
+	struct drm_framebuffer *out_fb;
+	int rc = 0;
+
+	SDE_DEBUG("\n");
+
+	if (state && (property_index == CONNECTOR_PROP_OUT_FB)) {
+		const struct sde_format *sde_format;
+
+		out_fb = sde_connector_get_out_fb(state);
+		if (!out_fb)
+			goto done;
+
+		sde_format = sde_get_sde_format_ext(out_fb->pixel_format,
+				out_fb->modifier,
+				drm_format_num_planes(out_fb->pixel_format));
+		if (!sde_format) {
+			SDE_ERROR("failed to get sde format\n");
+			rc = -EINVAL;
+			goto done;
+		}
+
+		if (!sde_wb_is_format_valid(wb_dev, out_fb->pixel_format,
+				out_fb->modifier[0])) {
+			SDE_ERROR("unsupported writeback format 0x%x/0x%llx\n",
+					out_fb->pixel_format,
+					out_fb->modifier[0]);
+			rc = -EINVAL;
+			goto done;
+		}
+	}
+
+done:
+	return rc;
+}
+
+int sde_wb_get_info(struct msm_display_info *info, void *display)
+{
+	struct sde_wb_device *wb_dev = display;
+
+	if (!info || !wb_dev) {
+		pr_err("invalid params\n");
+		return -EINVAL;
+	}
+
+	info->intf_type = DRM_MODE_CONNECTOR_VIRTUAL;
+	info->num_of_h_tiles = 1;
+	info->h_tile_instance[0] = sde_wb_get_index(display);
+	info->is_connected = true;
+	info->capabilities = MSM_DISPLAY_CAP_HOT_PLUG | MSM_DISPLAY_CAP_EDID;
+	info->max_width = (wb_dev->wb_cfg && wb_dev->wb_cfg->sblk) ?
+			wb_dev->wb_cfg->sblk->maxlinewidth :
+			SDE_WB_MODE_MAX_WIDTH;
+	info->max_height = SDE_WB_MODE_MAX_HEIGHT;
+	info->compression = MSM_DISPLAY_COMPRESS_NONE;
+	return 0;
+}
+
+int sde_wb_connector_post_init(struct drm_connector *connector,
+		void *info,
+		void *display)
+{
+	struct sde_connector *c_conn;
+	struct sde_wb_device *wb_dev = display;
+	const struct sde_format_extended *format_list;
+
+	if (!connector || !info || !display || !wb_dev->wb_cfg) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	c_conn = to_sde_connector(connector);
+	wb_dev->connector = connector;
+	wb_dev->detect_status = connector_status_connected;
+	format_list = wb_dev->wb_cfg->format_list;
+
+	/*
+	 * Add extra connector properties
+	 */
+	msm_property_install_range(&c_conn->property_info, "FB_ID",
+			0, ~0, ~0, CONNECTOR_PROP_OUT_FB);
+	msm_property_install_range(&c_conn->property_info, "DST_X",
+			0, UINT_MAX, 0, CONNECTOR_PROP_DST_X);
+	msm_property_install_range(&c_conn->property_info, "DST_Y",
+			0, UINT_MAX, 0, CONNECTOR_PROP_DST_Y);
+	msm_property_install_range(&c_conn->property_info, "DST_W",
+			0, UINT_MAX, 0, CONNECTOR_PROP_DST_W);
+	msm_property_install_range(&c_conn->property_info, "DST_H",
+			0, UINT_MAX, 0, CONNECTOR_PROP_DST_H);
+
+	/*
+	 * Populate info buffer
+	 */
+	if (format_list) {
+		sde_kms_info_start(info, "pixel_formats");
+		while (format_list->fourcc_format) {
+			sde_kms_info_append_format(info,
+					format_list->fourcc_format,
+					format_list->modifier);
+			++format_list;
+		}
+		sde_kms_info_stop(info);
+	}
+
+	sde_kms_info_add_keyint(info,
+			"wb_intf_index",
+			wb_dev->wb_idx - WB_0);
+
+	sde_kms_info_add_keyint(info,
+			"maxlinewidth",
+			wb_dev->wb_cfg->sblk->maxlinewidth);
+
+	sde_kms_info_start(info, "features");
+	if (wb_dev->wb_cfg && (wb_dev->wb_cfg->features & SDE_WB_UBWC_1_0))
+		sde_kms_info_append(info, "wb_ubwc");
+	sde_kms_info_stop(info);
+
+	return 0;
+}
+
+struct drm_framebuffer *sde_wb_get_output_fb(struct sde_wb_device *wb_dev)
+{
+	struct drm_framebuffer *fb;
+
+	if (!wb_dev || !wb_dev->connector) {
+		SDE_ERROR("invalid params\n");
+		return NULL;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	fb = sde_wb_connector_state_get_output_fb(wb_dev->connector->state);
+	mutex_unlock(&wb_dev->wb_lock);
+
+	return fb;
+}
+
+int sde_wb_get_output_roi(struct sde_wb_device *wb_dev, struct sde_rect *roi)
+{
+	int rc;
+
+	if (!wb_dev || !wb_dev->connector || !roi) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	rc = sde_wb_connector_state_get_output_roi(
+			wb_dev->connector->state, roi);
+	mutex_unlock(&wb_dev->wb_lock);
+
+	return rc;
+}
+
+u32 sde_wb_get_num_of_displays(void)
+{
+	u32 count = 0;
+	struct sde_wb_device *wb_dev;
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&sde_wb_list_lock);
+	list_for_each_entry(wb_dev, &sde_wb_list, wb_list) {
+		count++;
+	}
+	mutex_unlock(&sde_wb_list_lock);
+
+	return count;
+}
+
+int wb_display_get_displays(void **display_array, u32 max_display_count)
+{
+	struct sde_wb_device *curr;
+	int i = 0;
+
+	SDE_DEBUG("\n");
+
+	if (!display_array || !max_display_count) {
+		if (!display_array)
+			SDE_ERROR("invalid param\n");
+		return 0;
+	}
+
+	mutex_lock(&sde_wb_list_lock);
+	list_for_each_entry(curr, &sde_wb_list, wb_list) {
+		if (i >= max_display_count)
+			break;
+		display_array[i++] = curr;
+	}
+	mutex_unlock(&sde_wb_list_lock);
+
+	return i;
+}
+
+int sde_wb_config(struct drm_device *drm_dev, void *data,
+				struct drm_file *file_priv)
+{
+	struct sde_drm_wb_cfg *config = data;
+	struct msm_drm_private *priv;
+	struct sde_wb_device *wb_dev = NULL;
+	struct sde_wb_device *curr;
+	struct drm_connector *connector;
+	uint32_t flags;
+	uint32_t connector_id;
+	uint32_t count_modes;
+	uint64_t modes;
+	int rc;
+
+	if (!drm_dev || !data) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	flags = config->flags;
+	connector_id = config->connector_id;
+	count_modes = config->count_modes;
+	modes = config->modes;
+
+	priv = drm_dev->dev_private;
+
+	connector = drm_connector_find(drm_dev, connector_id);
+	if (!connector) {
+		SDE_ERROR("failed to find connector\n");
+		rc = -ENOENT;
+		goto fail;
+	}
+
+	mutex_lock(&sde_wb_list_lock);
+	list_for_each_entry(curr, &sde_wb_list, wb_list) {
+		if (curr->connector == connector) {
+			wb_dev = curr;
+			break;
+		}
+	}
+	mutex_unlock(&sde_wb_list_lock);
+
+	if (!wb_dev) {
+		SDE_ERROR("failed to find wb device\n");
+		rc = -ENOENT;
+		goto fail;
+	}
+
+	mutex_lock(&wb_dev->wb_lock);
+
+	rc = sde_wb_connector_set_modes(wb_dev, count_modes,
+		(struct drm_mode_modeinfo __user *) (uintptr_t) modes,
+		(flags & SDE_DRM_WB_CFG_FLAGS_CONNECTED) ? true : false);
+
+	mutex_unlock(&wb_dev->wb_lock);
+	drm_helper_hpd_irq_event(drm_dev);
+fail:
+	return rc;
+}
+
+int sde_wb_dev_init(struct sde_wb_device *wb_dev)
+{
+	int rc = 0;
+
+	if (!wb_dev) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	return rc;
+}
+
+int sde_wb_dev_deinit(struct sde_wb_device *wb_dev)
+{
+	int rc = 0;
+
+	if (!wb_dev) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	return rc;
+}
+
+int sde_wb_bind(struct sde_wb_device *wb_dev, struct drm_device *drm_dev)
+{
+	int rc = 0;
+
+	if (!wb_dev || !drm_dev) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	wb_dev->drm_dev = drm_dev;
+	mutex_unlock(&wb_dev->wb_lock);
+
+	return rc;
+}
+
+int sde_wb_unbind(struct sde_wb_device *wb_dev)
+{
+	int rc = 0;
+
+	if (!wb_dev) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+	wb_dev->drm_dev = NULL;
+	mutex_unlock(&wb_dev->wb_lock);
+
+	return rc;
+}
+
+int sde_wb_drm_init(struct sde_wb_device *wb_dev, struct drm_encoder *encoder)
+{
+	int rc = 0;
+
+	if (!wb_dev || !encoder) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&wb_dev->wb_lock);
+
+	if (wb_dev->drm_dev->dev_private) {
+		struct msm_drm_private *priv = wb_dev->drm_dev->dev_private;
+		struct sde_kms *sde_kms = to_sde_kms(priv->kms);
+
+		if (wb_dev->index < sde_kms->catalog->wb_count) {
+			wb_dev->wb_idx = sde_kms->catalog->wb[wb_dev->index].id;
+			wb_dev->wb_cfg = &sde_kms->catalog->wb[wb_dev->index];
+		}
+	}
+
+	wb_dev->drm_dev = encoder->dev;
+	wb_dev->encoder = encoder;
+	mutex_unlock(&wb_dev->wb_lock);
+	return rc;
+}
+
+int sde_wb_drm_deinit(struct sde_wb_device *wb_dev)
+{
+	int rc = 0;
+
+	if (!wb_dev) {
+		SDE_ERROR("invalid params\n");
+		return -EINVAL;
+	}
+
+	SDE_DEBUG("\n");
+
+	return rc;
+}
+
+/**
+ * sde_wb_probe - load writeback module
+ * @pdev:	Pointer to platform device
+ */
+static int sde_wb_probe(struct platform_device *pdev)
+{
+	struct sde_wb_device *wb_dev;
+	int ret;
+
+	wb_dev = devm_kzalloc(&pdev->dev, sizeof(*wb_dev), GFP_KERNEL);
+	if (!wb_dev)
+		return -ENOMEM;
+
+	SDE_DEBUG("\n");
+
+	ret = of_property_read_u32(pdev->dev.of_node, "cell-index",
+			&wb_dev->index);
+	if (ret) {
+		SDE_DEBUG("cell index not set, default to 0\n");
+		wb_dev->index = 0;
+	}
+
+	wb_dev->name = of_get_property(pdev->dev.of_node, "label", NULL);
+	if (!wb_dev->name) {
+		SDE_DEBUG("label not set, default to unknown\n");
+		wb_dev->name = "unknown";
+	}
+
+	wb_dev->wb_idx = SDE_NONE;
+
+	mutex_init(&wb_dev->wb_lock);
+	platform_set_drvdata(pdev, wb_dev);
+
+	mutex_lock(&sde_wb_list_lock);
+	list_add(&wb_dev->wb_list, &sde_wb_list);
+	mutex_unlock(&sde_wb_list_lock);
+
+	return 0;
+}
+
+/**
+ * sde_wb_remove - unload writeback module
+ * @pdev:	Pointer to platform device
+ */
+static int sde_wb_remove(struct platform_device *pdev)
+{
+	struct sde_wb_device *wb_dev;
+	struct sde_wb_device *curr, *next;
+
+	wb_dev = platform_get_drvdata(pdev);
+	if (!wb_dev)
+		return 0;
+
+	SDE_DEBUG("\n");
+
+	mutex_lock(&sde_wb_list_lock);
+	list_for_each_entry_safe(curr, next, &sde_wb_list, wb_list) {
+		if (curr == wb_dev) {
+			list_del(&wb_dev->wb_list);
+			break;
+		}
+	}
+	mutex_unlock(&sde_wb_list_lock);
+
+	kfree(wb_dev->modes);
+	mutex_destroy(&wb_dev->wb_lock);
+
+	platform_set_drvdata(pdev, NULL);
+	devm_kfree(&pdev->dev, wb_dev);
+
+	return 0;
+}
+
+static const struct of_device_id dt_match[] = {
+	{ .compatible = "qcom,wb-display"},
+	{}
+};
+
+static struct platform_driver sde_wb_driver = {
+	.probe = sde_wb_probe,
+	.remove = sde_wb_remove,
+	.driver = {
+		.name = "sde_wb",
+		.of_match_table = dt_match,
+	},
+};
+
+void sde_wb_register(void)
+{
+	platform_driver_register(&sde_wb_driver);
+}
+
+void sde_wb_unregister(void)
+{
+	platform_driver_unregister(&sde_wb_driver);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_wb.h b/drivers/gpu/drm/msm/sde/sde_wb.h
new file mode 100644
index 000000000000..79056200aa06
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_wb.h
@@ -0,0 +1,376 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SDE_WB_H__
+#define __SDE_WB_H__
+
+#include <linux/platform_device.h>
+
+#include "msm_kms.h"
+#include "sde_kms.h"
+
+/**
+ * struct sde_wb_device - Writeback device context
+ * @drm_dev:		Pointer to controlling DRM device
+ * @index:		Index of hardware instance from device tree
+ * @wb_idx:		Writeback identifier of enum sde_wb
+ * @wb_cfg:		Writeback configuration catalog
+ * @name:		Name of writeback device from device tree
+ * @display_type:	Display type from device tree
+ * @wb_list		List of all writeback devices
+ * @wb_lock		Serialization lock for writeback context structure
+ * @connector:		Connector associated with writeback device
+ * @encoder:		Encoder associated with writeback device
+ * @count_modes:	Length of writeback connector modes array
+ * @modes:		Writeback connector modes array
+ */
+struct sde_wb_device {
+	struct drm_device *drm_dev;
+
+	u32 index;
+	u32 wb_idx;
+	struct sde_wb_cfg *wb_cfg;
+	const char *name;
+
+	struct list_head wb_list;
+	struct mutex wb_lock;
+
+	struct drm_connector *connector;
+	struct drm_encoder *encoder;
+
+	enum drm_connector_status detect_status;
+	u32 count_modes;
+	struct drm_mode_modeinfo *modes;
+};
+
+/**
+ * sde_wb_get_index - get device index of the given writeback device
+ * @wb_dev:	Pointer to writeback device
+ * Returns:	Index of hardware instance
+ */
+static inline
+int sde_wb_get_index(struct sde_wb_device *wb_dev)
+{
+	return wb_dev ? wb_dev->index : -1;
+}
+
+#ifdef CONFIG_DRM_SDE_WB
+/**
+ * sde_wb_get_output_fb - get framebuffer in current atomic state
+ * @wb_dev:	Pointer to writeback device
+ * Returns:	Pointer to framebuffer
+ */
+struct drm_framebuffer *sde_wb_get_output_fb(struct sde_wb_device *wb_dev);
+
+/**
+ * sde_wb_get_output_roi - get region-of-interest in current atomic state
+ * @wb_dev:	Pointer to writeback device
+ * @roi:	Pointer to region of interest
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_get_output_roi(struct sde_wb_device *wb_dev, struct sde_rect *roi);
+
+/**
+ * sde_wb_get_num_of_displays - get total number of writeback devices
+ * Returns:	Number of writeback devices
+ */
+u32 sde_wb_get_num_of_displays(void);
+
+/**
+ * wb_display_get_displays - returns pointers for supported display devices
+ * @display_array: Pointer to display array to be filled
+ * @max_display_count: Size of display_array
+ * @Returns: Number of display entries filled
+ */
+int wb_display_get_displays(void **display_array, u32 max_display_count);
+
+/**
+ * wb_display_get_displays - returns pointers for supported display devices
+ * @display_array: Pointer to display array to be filled
+ * @max_display_count: Size of display_array
+ * @Returns: Number of display entries filled
+ */
+int sde_wb_dev_init(struct sde_wb_device *wb_dev);
+
+/**
+ * sde_wb_dev_deinit - perform device de-initialization
+ * @wb_dev:	Pointer to writeback device
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_dev_deinit(struct sde_wb_device *wb_dev);
+
+/**
+ * sde_wb_bind - bind writeback device with controlling device
+ * @wb_dev:	Pointer to writeback device
+ * @drm_dev:	Pointer to controlling DRM device
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_bind(struct sde_wb_device *wb_dev, struct drm_device *drm_dev);
+
+/**
+ * sde_wb_unbind - unbind writeback from controlling device
+ * @wb_dev:	Pointer to writeback device
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_unbind(struct sde_wb_device *wb_dev);
+
+/**
+ * sde_wb_drm_init - perform DRM initialization
+ * @wb_dev:	Pointer to writeback device
+ * @encoder:	Pointer to associated encoder
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_drm_init(struct sde_wb_device *wb_dev, struct drm_encoder *encoder);
+
+/**
+ * sde_wb_drm_deinit - perform DRM de-initialization
+ * @wb_dev:	Pointer to writeback device
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_drm_deinit(struct sde_wb_device *wb_dev);
+
+/**
+ * sde_wb_register - register writeback module
+ */
+void sde_wb_register(void);
+
+/**
+ * sde_wb_unregister - unregister writeback module
+ */
+void sde_wb_unregister(void);
+
+/**
+ * sde_wb_config - setup connection status and available drm modes of the
+ *			given writeback connector
+ * @drm_dev:	Pointer to DRM device
+ * @data:	Pointer to writeback configuration
+ * @file_priv:	Pointer file private data
+ * Returns:	0 if success; error code otherwise
+ *
+ * This function will initiate hot-plug detection event.
+ */
+int sde_wb_config(struct drm_device *drm_dev, void *data,
+				struct drm_file *file_priv);
+
+/**
+ * sde_wb_connector_post_init - perform writeback specific initialization
+ * @connector: Pointer to drm connector structure
+ * @info: Pointer to connector info
+ * @display: Pointer to private display structure
+ * Returns: Zero on success
+ */
+int sde_wb_connector_post_init(struct drm_connector *connector,
+		void *info,
+		void *display);
+
+/**
+ * sde_wb_connector_detect - perform writeback connection status detection
+ * @connector:	Pointer to connector
+ * @force:	Indicate force detection
+ * @display:	Pointer to writeback device
+ * Returns:	connector status
+ */
+enum drm_connector_status
+sde_wb_connector_detect(struct drm_connector *connector,
+		bool force,
+		void *display);
+
+/**
+ * sde_wb_connector_get_modes - get display modes of connector
+ * @connector:	Pointer to connector
+ * @display:	Pointer to writeback device
+ * Returns:	Number of modes
+ *
+ * If display modes are not specified in writeback configuration IOCTL, this
+ * function will install default EDID modes up to maximum resolution support.
+ */
+int sde_wb_connector_get_modes(struct drm_connector *connector, void *display);
+
+/**
+ * sde_wb_connector_set_property - set atomic connector property
+ * @connector: Pointer to drm connector structure
+ * @state: Pointer to drm connector state structure
+ * @property_index: DRM property index
+ * @value: Incoming property value
+ * @display: Pointer to private display structure
+ * Returns: Zero on success
+ */
+int sde_wb_connector_set_property(struct drm_connector *connector,
+		struct drm_connector_state *state,
+		int property_index,
+		uint64_t value,
+		void *display);
+
+/**
+ * sde_wb_get_info - retrieve writeback 'display' information
+ * @info: Pointer to display info structure
+ * @display: Pointer to private display structure
+ * Returns: Zero on success
+ */
+int sde_wb_get_info(struct msm_display_info *info, void *display);
+
+/**
+ * sde_wb_connector_get_wb - retrieve writeback device of the given connector
+ * @connector: Pointer to drm connector
+ * Returns: Pointer to writeback device on success; NULL otherwise
+ */
+static inline
+struct sde_wb_device *sde_wb_connector_get_wb(struct drm_connector *connector)
+{
+	if (!connector ||
+		(connector->connector_type != DRM_MODE_CONNECTOR_VIRTUAL)) {
+		SDE_ERROR("invalid params\n");
+		return NULL;
+	}
+
+	return sde_connector_get_display(connector);
+}
+
+/**
+ * sde_wb_connector_state_get_output_fb - get framebuffer of given state
+ * @state:	Pointer to connector state
+ * Returns:	Pointer to framebuffer
+ */
+struct drm_framebuffer *
+sde_wb_connector_state_get_output_fb(struct drm_connector_state *state);
+
+/**
+ * sde_wb_connector_state_get_output_roi - get roi from given atomic state
+ * @state:	Pointer to atomic state
+ * @roi:	Pointer to region of interest
+ * Returns:	0 if success; error code otherwise
+ */
+int sde_wb_connector_state_get_output_roi(struct drm_connector_state *state,
+		struct sde_rect *roi);
+
+#else
+static inline
+struct drm_framebuffer *sde_wb_get_output_fb(struct sde_wb_device *wb_dev)
+{
+	return NULL;
+}
+static inline
+int sde_wb_get_output_roi(struct sde_wb_device *wb_dev, struct sde_rect *roi)
+{
+	return 0;
+}
+static inline
+u32 sde_wb_get_num_of_displays(void)
+{
+	return 0;
+}
+static inline
+int wb_display_get_displays(void **display_array, u32 max_display_count)
+{
+	return 0;
+}
+static inline
+int sde_wb_dev_init(struct sde_wb_device *wb_dev)
+{
+	return 0;
+}
+static inline
+int sde_wb_dev_deinit(struct sde_wb_device *wb_dev)
+{
+	return 0;
+}
+static inline
+int sde_wb_bind(struct sde_wb_device *wb_dev, struct drm_device *drm_dev)
+{
+	return 0;
+}
+static inline
+int sde_wb_unbind(struct sde_wb_device *wb_dev)
+{
+	return 0;
+}
+static inline
+int sde_wb_drm_init(struct sde_wb_device *wb_dev, struct drm_encoder *encoder)
+{
+	return 0;
+}
+static inline
+int sde_wb_drm_deinit(struct sde_wb_device *wb_dev)
+{
+	return 0;
+}
+static inline
+void sde_wb_register(void)
+{
+}
+static inline
+void sde_wb_unregister(void)
+{
+}
+static inline
+int sde_wb_config(struct drm_device *drm_dev, void *data,
+				struct drm_file *file_priv)
+{
+	return 0;
+}
+static inline
+int sde_wb_connector_post_init(struct drm_connector *connector,
+		void *info,
+		void *display)
+{
+	return 0;
+}
+static inline
+enum drm_connector_status
+sde_wb_connector_detect(struct drm_connector *connector,
+		bool force,
+		void *display)
+{
+	return connector_status_disconnected;
+}
+static inline
+int sde_wb_connector_get_modes(struct drm_connector *connector, void *display)
+{
+	return -EINVAL;
+}
+static inline
+int sde_wb_connector_set_property(struct drm_connector *connector,
+		struct drm_connector_state *state,
+		int property_index,
+		uint64_t value,
+		void *display)
+{
+	return 0;
+}
+static inline
+int sde_wb_get_info(struct msm_display_info *info, void *display)
+{
+	return 0;
+}
+static inline
+struct sde_wb_device *sde_wb_connector_get_wb(struct drm_connector *connector)
+{
+	return NULL;
+}
+
+static inline
+struct drm_framebuffer *
+sde_wb_connector_state_get_output_fb(struct drm_connector_state *state)
+{
+	return NULL;
+}
+
+static inline
+int sde_wb_connector_state_get_output_roi(struct drm_connector_state *state,
+		struct sde_rect *roi)
+{
+	return 0;
+}
+
+#endif
+#endif /* __SDE_WB_H__ */
+
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 75a232b9a970..9ea8351e843b 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -20,6 +20,7 @@
 
 #include <stddef.h>
 #include <drm/drm.h>
+#include <drm/sde_drm.h>
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints:
@@ -206,7 +207,8 @@ struct drm_msm_wait_fence {
 #define DRM_MSM_GEM_CPU_FINI           0x05
 #define DRM_MSM_GEM_SUBMIT             0x06
 #define DRM_MSM_WAIT_FENCE             0x07
-#define DRM_MSM_NUM_IOCTLS             0x08
+#define DRM_SDE_WB_CONFIG              0x08
+#define DRM_MSM_NUM_IOCTLS             0x09
 
 #define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
 #define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
@@ -215,5 +217,7 @@ struct drm_msm_wait_fence {
 #define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
 #define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
 #define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
+#define DRM_IOCTL_SDE_WB_CONFIG \
+	DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg)
 
 #endif /* __MSM_DRM_H__ */
diff --git a/include/uapi/drm/sde_drm.h b/include/uapi/drm/sde_drm.h
index 668b4c965f5d..bcd64c23eb14 100644
--- a/include/uapi/drm/sde_drm.h
+++ b/include/uapi/drm/sde_drm.h
@@ -220,4 +220,24 @@ struct sde_drm_csc {
 	};
 };
 
+/* Writeback Config version definition */
+#define SDE_DRM_WB_CFG		0x1
+
+/* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */
+#define SDE_DRM_WB_CFG_FLAGS_CONNECTED	(1<<0)
+
+/**
+ * struct sde_drm_wb_cfg - Writeback configuration structure
+ * @flags:		see DRM_MSM_WB_CONFIG_FLAGS
+ * @connector_id:	writeback connector identifier
+ * @count_modes:	Count of modes in modes_ptr
+ * @modes:		Pointer to struct drm_mode_modeinfo
+ */
+struct sde_drm_wb_cfg {
+	uint32_t flags;
+	uint32_t connector_id;
+	uint32_t count_modes;
+	uint64_t modes;
+};
+
 #endif /* _SDE_DRM_H_ */
-- 
cgit v1.2.3


From 238e8cb84564de1509f1bb413b54b9f4c26fb9be Mon Sep 17 00:00:00 2001
From: Dhaval Patel <pdhaval@codeaurora.org>
Date: Wed, 27 Jul 2016 18:36:59 -0700
Subject: drm/msm: add power handle driver for msm

The power handle driver parses the regulator and
clocks present on certain device node and it votes/enables
the clock when client request for it. Multiple clients
can request for enable/disable at the same time. It handles
the reference counting logic to avoid removal vote from
other client. It also supports the register bus driver
voting. Data bus driver support is still missing.

Change-Id: I030f302dce82508e89006cc034d825a071fe9967
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt        |  65 +++
 drivers/gpu/drm/msm/sde_power_handle.c             | 554 +++++++++++++++++++++
 drivers/gpu/drm/msm/sde_power_handle.h             | 139 ++++++
 3 files changed, 758 insertions(+)
 create mode 100644 drivers/gpu/drm/msm/sde_power_handle.c
 create mode 100644 drivers/gpu/drm/msm/sde_power_handle.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 8ec9f78346d8..7739a9cdef66 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -19,6 +19,40 @@ Required properties
 - #interrupt-cells: Should be one. The first cell is interrupt number.
 - iommus: Specifies the SID's used by this context bank.
 
+Optional properties:
+- clock-rate:		List of clock rates in Hz.
+- qcom,platform-supply-entries:	A node that lists the elements of the supply. There
+				can be more than one instance of this binding,
+				in which case the entry would be appended with
+				the supply entry index.
+				e.g. qcom,platform-supply-entry@0
+				-- reg: offset and length of the register set for the device.
+				-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
+				-- qcom,supply-min-voltage: minimum voltage level (uV)
+				-- qcom,supply-max-voltage: maximum voltage level (uV)
+				-- qcom,supply-enable-load: load drawn (uA) from enabled supply
+				-- qcom,supply-disable-load: load drawn (uA) from disabled supply
+				-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
+				-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
+				-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
+				-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
+- qcom,sde-reg-bus:		Property to provide Bus scaling for register access for
+				mdss blocks.
+
+
+Bus Scaling Data:
+- qcom,msm-bus,name:		String property describing client name.
+- qcom,msm-bus,num-cases:	This is the the number of Bus Scaling use cases
+				defined in the vectors property.
+- qcom,msm-bus,num-paths:	This represents the number of paths in each
+				Bus Scaling Usecase.
+- qcom,msm-bus,vectors-KBps:	* A series of 4 cell properties, with a format
+				of (src, dst, ab, ib) which is defined at
+				Documentation/devicetree/bindings/arm/msm/msm_bus.txt
+				* Current values of src & dst are defined at
+				include/linux/msm-bus-board.h
+
+
 Please refer to ../../interrupt-controller/interrupts.txt for a general
 description of interrupt bindings.
 
@@ -45,6 +79,7 @@ Example:
       "iommu_clk",
       "mmagic_clk",
       "vsync_clk";
+    clock-rate = <0>, <0>, <0>;
     mmagic-supply = <&gdsc_mmagic_mdss>;
     vdd-supply = <&gdsc_mdss>;
     interrupt-parent = <&intc>;
@@ -52,4 +87,34 @@ Example:
     interrupt-controller;
     #interrupt-cells = <1>;
     iommus = <&mdp_smmu 0>;
+
+    qcom,platform-supply-entries {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       qcom,platform-supply-entry@0 {
+           reg = <0>;
+           qcom,supply-name = "vdd";
+           qcom,supply-min-voltage = <0>;
+           qcom,supply-max-voltage = <0>;
+           qcom,supply-enable-load = <0>;
+           qcom,supply-disable-load = <0>;
+           qcom,supply-pre-on-sleep = <0>;
+           qcom,supply-post-on-sleep = <0>;
+           qcom,supply-pre-off-sleep = <0>;
+           qcom,supply-post-off-sleep = <0>;
+        };
+    };
+
+    qcom,sde-reg-bus {
+        /* Reg Bus Scale Settings */
+        qcom,msm-bus,name = "mdss_reg";
+        qcom,msm-bus,num-cases = <4>;
+        qcom,msm-bus,num-paths = <1>;
+        qcom,msm-bus,active-only;
+        qcom,msm-bus,vectors-KBps =
+              <1 590 0 0>,
+              <1 590 0 76800>,
+              <1 590 0 160000>,
+              <1 590 0 320000>;
+        };
   };
diff --git a/drivers/gpu/drm/msm/sde_power_handle.c b/drivers/gpu/drm/msm/sde_power_handle.c
new file mode 100644
index 000000000000..28807848d831
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde_power_handle.c
@@ -0,0 +1,554 @@
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d]: " fmt, __func__, __LINE__
+
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/string.h>
+#include <linux/of_address.h>
+#include <linux/clk/msm-clk.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/of_platform.h>
+
+#include <linux/msm-bus.h>
+#include <linux/msm-bus-board.h>
+#include <linux/mdss_io_util.h>
+
+#include "sde_power_handle.h"
+
+struct sde_power_client *sde_power_client_create(
+	struct sde_power_handle *phandle, char *client_name)
+{
+	struct sde_power_client *client;
+	static u32 id;
+
+	if (!client_name || !phandle) {
+		pr_err("client name is null or invalid power data\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	client = kzalloc(sizeof(struct sde_power_client), GFP_KERNEL);
+	if (!client)
+		return ERR_PTR(-ENOMEM);
+
+	mutex_lock(&phandle->phandle_lock);
+	strlcpy(client->name, client_name, MAX_CLIENT_NAME_LEN);
+	client->usecase_ndx = VOTE_INDEX_DISABLE;
+	client->id = id;
+	pr_debug("client %s created:%pK id :%d\n", client_name,
+		client, id);
+	id++;
+	list_add(&client->list, &phandle->power_client_clist);
+	mutex_unlock(&phandle->phandle_lock);
+
+	return client;
+}
+
+void sde_power_client_destroy(struct sde_power_handle *phandle,
+	struct sde_power_client *client)
+{
+	if (!client  || !phandle) {
+		pr_err("reg bus vote: invalid client handle\n");
+	} else {
+		pr_debug("bus vote client %s destroyed:%pK id:%u\n",
+			client->name, client, client->id);
+		mutex_lock(&phandle->phandle_lock);
+		list_del_init(&client->list);
+		mutex_unlock(&phandle->phandle_lock);
+		kfree(client);
+	}
+}
+
+static int sde_power_parse_dt_supply(struct platform_device *pdev,
+				struct dss_module_power *mp)
+{
+	int i = 0, rc = 0;
+	u32 tmp = 0;
+	struct device_node *of_node = NULL, *supply_root_node = NULL;
+	struct device_node *supply_node = NULL;
+
+	if (!pdev || !mp) {
+		pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
+		return -EINVAL;
+	}
+
+	of_node = pdev->dev.of_node;
+
+	mp->num_vreg = 0;
+	supply_root_node = of_get_child_by_name(of_node,
+						"qcom,platform-supply-entries");
+	if (!supply_root_node) {
+		pr_err("no supply entry present\n");
+		return rc;
+	}
+
+	for_each_child_of_node(supply_root_node, supply_node)
+		mp->num_vreg++;
+
+	if (mp->num_vreg == 0) {
+		pr_debug("no vreg\n");
+		return rc;
+	}
+
+	pr_debug("vreg found. count=%d\n", mp->num_vreg);
+	mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) *
+						mp->num_vreg, GFP_KERNEL);
+	if (!mp->vreg_config) {
+		rc = -ENOMEM;
+		return rc;
+	}
+
+	for_each_child_of_node(supply_root_node, supply_node) {
+
+		const char *st = NULL;
+
+		rc = of_property_read_string(supply_node,
+						"qcom,supply-name", &st);
+		if (rc) {
+			pr_err("error reading name. rc=%d\n", rc);
+			goto error;
+		}
+
+		strlcpy(mp->vreg_config[i].vreg_name, st,
+					sizeof(mp->vreg_config[i].vreg_name));
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-min-voltage", &tmp);
+		if (rc) {
+			pr_err("error reading min volt. rc=%d\n", rc);
+			goto error;
+		}
+		mp->vreg_config[i].min_voltage = tmp;
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-max-voltage", &tmp);
+		if (rc) {
+			pr_err("error reading max volt. rc=%d\n", rc);
+			goto error;
+		}
+		mp->vreg_config[i].max_voltage = tmp;
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-enable-load", &tmp);
+		if (rc) {
+			pr_err("error reading enable load. rc=%d\n", rc);
+			goto error;
+		}
+		mp->vreg_config[i].enable_load = tmp;
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-disable-load", &tmp);
+		if (rc) {
+			pr_err("error reading disable load. rc=%d\n", rc);
+			goto error;
+		}
+		mp->vreg_config[i].disable_load = tmp;
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-pre-on-sleep", &tmp);
+		if (rc)
+			pr_debug("error reading supply pre sleep value. rc=%d\n",
+							rc);
+
+		mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0);
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-pre-off-sleep", &tmp);
+		if (rc)
+			pr_debug("error reading supply pre sleep value. rc=%d\n",
+							rc);
+
+		mp->vreg_config[i].pre_off_sleep = (!rc ? tmp : 0);
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-post-on-sleep", &tmp);
+		if (rc)
+			pr_debug("error reading supply post sleep value. rc=%d\n",
+							rc);
+
+		mp->vreg_config[i].post_on_sleep = (!rc ? tmp : 0);
+
+		rc = of_property_read_u32(supply_node,
+					"qcom,supply-post-off-sleep", &tmp);
+		if (rc)
+			pr_debug("error reading supply post sleep value. rc=%d\n",
+							rc);
+
+		mp->vreg_config[i].post_off_sleep = (!rc ? tmp : 0);
+
+		pr_debug("%s min=%d, max=%d, enable=%d, disable=%d, preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d\n",
+					mp->vreg_config[i].vreg_name,
+					mp->vreg_config[i].min_voltage,
+					mp->vreg_config[i].max_voltage,
+					mp->vreg_config[i].enable_load,
+					mp->vreg_config[i].disable_load,
+					mp->vreg_config[i].pre_on_sleep,
+					mp->vreg_config[i].post_on_sleep,
+					mp->vreg_config[i].pre_off_sleep,
+					mp->vreg_config[i].post_off_sleep);
+		++i;
+
+		rc = 0;
+	}
+
+	return rc;
+
+error:
+	if (mp->vreg_config) {
+		devm_kfree(&pdev->dev, mp->vreg_config);
+		mp->vreg_config = NULL;
+		mp->num_vreg = 0;
+	}
+
+	return rc;
+}
+
+static int sde_power_parse_dt_clock(struct platform_device *pdev,
+					struct dss_module_power *mp)
+{
+	u32 i = 0, rc = 0;
+	const char *clock_name;
+	u32 clock_rate;
+
+	if (!pdev || !mp) {
+		pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
+		return -EINVAL;
+	}
+
+	mp->num_clk = of_property_count_strings(pdev->dev.of_node,
+							"clock-names");
+	if (mp->num_clk <= 0) {
+		pr_err("clocks are not defined\n");
+		goto clk_err;
+	}
+
+	mp->clk_config = devm_kzalloc(&pdev->dev,
+			sizeof(struct dss_clk) * mp->num_clk, GFP_KERNEL);
+	if (!mp->clk_config) {
+		rc = -ENOMEM;
+		mp->num_clk = 0;
+		goto clk_err;
+	}
+
+	for (i = 0; i < mp->num_clk; i++) {
+		of_property_read_string_index(pdev->dev.of_node, "clock-names",
+							i, &clock_name);
+		strlcpy(mp->clk_config[i].clk_name, clock_name,
+				sizeof(mp->clk_config[i].clk_name));
+
+		of_property_read_u32_index(pdev->dev.of_node, "clock-rate",
+							i, &clock_rate);
+		mp->clk_config[i].rate = clock_rate;
+
+		if (!clock_rate)
+			mp->clk_config[i].type = DSS_CLK_AHB;
+		else
+			mp->clk_config[i].type = DSS_CLK_PCLK;
+	}
+
+clk_err:
+	return rc;
+}
+
+#ifdef CONFIG_QCOM_BUS_SCALING
+static int sde_power_reg_bus_parse(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	struct device_node *node;
+	struct msm_bus_scale_pdata *bus_scale_table;
+	int rc = 0;
+
+	node = of_get_child_by_name(pdev->dev.of_node, "qcom,sde-reg-bus");
+	if (node) {
+		bus_scale_table = msm_bus_pdata_from_node(pdev, node);
+		if (IS_ERR_OR_NULL(bus_scale_table)) {
+			pr_err("reg bus handle parsing failed\n");
+			rc = PTR_ERR(bus_scale_table);
+			goto end;
+		}
+		phandle->reg_bus_hdl = msm_bus_scale_register_client(
+			      bus_scale_table);
+		if (!phandle->reg_bus_hdl) {
+			pr_err("reg_bus_client register failed\n");
+			rc = -EINVAL;
+			goto end;
+		}
+		pr_debug("register reg_bus_hdl=%x\n", phandle->reg_bus_hdl);
+	}
+
+end:
+	return rc;
+}
+
+static void sde_power_reg_bus_unregister(u32 reg_bus_hdl)
+{
+	if (reg_bus_hdl)
+		msm_bus_scale_unregister_client(reg_bus_hdl);
+}
+
+static int sde_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx)
+{
+	int rc = 0;
+
+	if (reg_bus_hdl)
+		rc = msm_bus_scale_client_update_request(reg_bus_hdl,
+								usecase_ndx);
+	if (rc)
+		pr_err("failed to set reg bus vote rc=%d\n", rc);
+
+	return rc;
+}
+#else
+static int sde_power_reg_bus_parse(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	return 0;
+}
+
+static void sde_power_reg_bus_unregister(u32 reg_bus_hdl)
+{
+}
+
+static int sde_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx)
+{
+	return 0;
+}
+#endif
+
+int sde_power_resource_init(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	int rc = 0;
+	struct dss_module_power *mp;
+
+	if (!phandle || !pdev) {
+		pr_err("invalid input param\n");
+		rc = -EINVAL;
+		goto end;
+	}
+	mp = &phandle->mp;
+
+	rc = sde_power_parse_dt_clock(pdev, mp);
+	if (rc) {
+		pr_err("device clock parsing failed\n");
+		goto end;
+	}
+
+	rc = sde_power_parse_dt_supply(pdev, mp);
+	if (rc) {
+		pr_err("device vreg supply parsing failed\n");
+		goto parse_vreg_err;
+	}
+
+	rc = msm_dss_config_vreg(&pdev->dev,
+				mp->vreg_config, mp->num_vreg, 1);
+	if (rc) {
+		pr_err("vreg config failed rc=%d\n", rc);
+		goto vreg_err;
+	}
+
+	rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
+	if (rc) {
+		pr_err("clock get failed rc=%d\n", rc);
+		goto clk_err;
+	}
+
+	rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
+	if (rc) {
+		pr_err("clock set rate failed rc=%d\n", rc);
+		goto bus_err;
+	}
+
+	rc = sde_power_reg_bus_parse(pdev, phandle);
+	if (rc) {
+		pr_err("register bus parse failed rc=%d\n", rc);
+		goto bus_err;
+	}
+
+	INIT_LIST_HEAD(&phandle->power_client_clist);
+	mutex_init(&phandle->phandle_lock);
+
+	return rc;
+
+bus_err:
+	msm_dss_put_clk(mp->clk_config, mp->num_clk);
+clk_err:
+	msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
+vreg_err:
+	devm_kfree(&pdev->dev, mp->vreg_config);
+	mp->num_vreg = 0;
+parse_vreg_err:
+	devm_kfree(&pdev->dev, mp->clk_config);
+	mp->num_clk = 0;
+end:
+	return rc;
+}
+
+void sde_power_resource_deinit(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	struct dss_module_power *mp;
+
+	if (!phandle) {
+		pr_err("invalid input param\n");
+		return;
+	}
+	mp = &phandle->mp;
+
+	sde_power_reg_bus_unregister(phandle->reg_bus_hdl);
+
+	msm_dss_put_clk(mp->clk_config, mp->num_clk);
+
+	msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
+
+	devm_kfree(&pdev->dev, mp->clk_config);
+	devm_kfree(&pdev->dev, mp->vreg_config);
+	mp->num_vreg = 0;
+	mp->num_clk = 0;
+}
+
+int sde_power_resource_enable(struct sde_power_handle *phandle,
+	struct sde_power_client *pclient, bool enable)
+{
+	int rc = 0;
+	bool changed = false;
+	u32 max_usecase_ndx = VOTE_INDEX_DISABLE, prev_usecase_ndx;
+	struct sde_power_client *client;
+	struct dss_module_power *mp;
+
+	if (!phandle || !pclient) {
+		pr_err("invalid input argument\n");
+		return -EINVAL;
+	}
+
+	mp = &phandle->mp;
+
+	mutex_lock(&phandle->phandle_lock);
+	if (enable)
+		pclient->refcount++;
+	else if (pclient->refcount)
+		pclient->refcount--;
+
+	if (pclient->refcount)
+		pclient->usecase_ndx = VOTE_INDEX_LOW;
+	else
+		pclient->usecase_ndx = VOTE_INDEX_DISABLE;
+
+	list_for_each_entry(client, &phandle->power_client_clist, list) {
+		if (client->usecase_ndx < VOTE_INDEX_MAX &&
+		    client->usecase_ndx > max_usecase_ndx)
+			max_usecase_ndx = client->usecase_ndx;
+	}
+
+	if (phandle->current_usecase_ndx != max_usecase_ndx) {
+		changed = true;
+		prev_usecase_ndx = phandle->current_usecase_ndx;
+		phandle->current_usecase_ndx = max_usecase_ndx;
+	}
+
+	pr_debug("%pS: changed=%d current idx=%d request client %s id:%u enable:%d refcount:%d\n",
+		__builtin_return_address(0), changed, max_usecase_ndx,
+		pclient->name, pclient->id, enable, pclient->refcount);
+
+	if (!changed)
+		goto end;
+
+	if (enable) {
+		rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
+		if (rc) {
+			pr_err("failed to enable vregs rc=%d\n", rc);
+			goto vreg_err;
+		}
+
+		rc = sde_power_reg_bus_update(phandle->reg_bus_hdl,
+							max_usecase_ndx);
+		if (rc) {
+			pr_err("failed to set reg bus vote rc=%d\n", rc);
+			goto reg_bus_hdl_err;
+		}
+
+		rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
+		if (rc) {
+			pr_err("clock enable failed rc:%d\n", rc);
+			goto clk_err;
+		}
+	} else {
+		msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
+
+		sde_power_reg_bus_update(phandle->reg_bus_hdl,
+							max_usecase_ndx);
+
+		msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
+	}
+
+end:
+	mutex_unlock(&phandle->phandle_lock);
+	return rc;
+
+clk_err:
+	sde_power_reg_bus_update(phandle->reg_bus_hdl, prev_usecase_ndx);
+reg_bus_hdl_err:
+	msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0);
+vreg_err:
+	phandle->current_usecase_ndx = prev_usecase_ndx;
+	mutex_unlock(&phandle->phandle_lock);
+	return rc;
+}
+
+int sde_power_clk_set_rate(struct sde_power_handle *phandle, char *clock_name,
+	u64 rate)
+{
+	int i, rc = -EINVAL;
+	struct dss_module_power *mp;
+
+	if (!phandle) {
+		pr_err("invalid input power handle\n");
+		return -EINVAL;
+	}
+	mp = &phandle->mp;
+
+	for (i = 0; i < mp->num_clk; i++) {
+		if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
+			mp->clk_config[i].rate = rate;
+			rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
+			break;
+		}
+	}
+
+	return rc;
+}
+
+u64 sde_power_clk_get_rate(struct sde_power_handle *phandle, char *clock_name)
+{
+	int i;
+	struct dss_module_power *mp;
+	u64 rate = -EINVAL;
+
+	if (!phandle) {
+		pr_err("invalid input power handle\n");
+		return -EINVAL;
+	}
+	mp = &phandle->mp;
+
+	for (i = 0; i < mp->num_clk; i++) {
+		if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
+			rate = clk_get_rate(mp->clk_config[i].clk);
+			break;
+		}
+	}
+
+	return rate;
+}
diff --git a/drivers/gpu/drm/msm/sde_power_handle.h b/drivers/gpu/drm/msm/sde_power_handle.h
new file mode 100644
index 000000000000..214b1d37abda
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde_power_handle.h
@@ -0,0 +1,139 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _SDE_POWER_HANDLE_H_
+#define _SDE_POWER_HANDLE_H_
+
+#define MAX_CLIENT_NAME_LEN 128
+
+/**
+ * mdss_bus_vote_type: register bus vote type
+ * VOTE_INDEX_DISABLE: removes the client vote
+ * VOTE_INDEX_LOW: keeps the lowest vote for register bus
+ * VOTE_INDEX_MAX: invalid
+ */
+enum mdss_bus_vote_type {
+	VOTE_INDEX_DISABLE,
+	VOTE_INDEX_LOW,
+	VOTE_INDEX_MAX,
+};
+
+/**
+ * struct sde_power_client: stores the power client for sde driver
+ * @name:	name of the client
+ * @usecase_ndx: current regs bus vote type
+ * @refcount:	current refcount if multiple modules are using same
+ *              same client for enable/disable. Power module will
+ *              aggregate the refcount and vote accordingly for this
+ *              client.
+ * @id:		assigned during create. helps for debugging.
+ * @list:	list to attach power handle master list
+ */
+struct sde_power_client {
+	char name[MAX_CLIENT_NAME_LEN];
+	short usecase_ndx;
+	short refcount;
+	u32 id;
+	struct list_head list;
+};
+
+/**
+ * struct sde_power_handle: power handle main struct
+ * @mp:		module power for clock and regulator
+ * @client_clist: master list to store all clients
+ * @phandle_lock: lock to synchronize the enable/disable
+ * @usecase_ndx: current usecase index
+ * @reg_bus_hdl: current register bus handle
+ */
+struct sde_power_handle {
+	struct dss_module_power mp;
+	struct list_head power_client_clist;
+	struct mutex phandle_lock;
+	u32 current_usecase_ndx;
+#ifdef CONFIG_QCOM_BUS_SCALING
+	u32 reg_bus_hdl;
+#endif
+};
+
+/**
+ * sde_power_resource_init() - initializes the sde power handle
+ * @pdev:   platform device to search the power resources
+ * @pdata:  power handle to store the power resources
+ *
+ * Return: error code.
+ */
+int sde_power_resource_init(struct platform_device *pdev,
+	struct sde_power_handle *pdata);
+
+/**
+ * sde_power_resource_deinit() - release the sde power handle
+ * @pdev:   platform device for power resources
+ * @pdata:  power handle containing the resources
+ *
+ * Return: error code.
+ */
+void sde_power_resource_deinit(struct platform_device *pdev,
+	struct sde_power_handle *pdata);
+
+/**
+ * sde_power_client_create() - create the client on power handle
+ * @pdata:  power handle containing the resources
+ * @client_name: new client name for registration
+ *
+ * Return: error code.
+ */
+struct sde_power_client *sde_power_client_create(struct sde_power_handle *pdata,
+	char *client_name);
+
+/**
+ * sde_power_client_destroy() - destroy the client on power handle
+ * @pdata:  power handle containing the resources
+ * @client_name: new client name for registration
+ *
+ * Return: none
+ */
+void sde_power_client_destroy(struct sde_power_handle *phandle,
+	struct sde_power_client *client);
+
+/**
+ * sde_power_resource_enable() - enable/disable the power resources
+ * @pdata:  power handle containing the resources
+ * @client: client information to enable/disable its vote
+ * @enable: boolean request for enable/disable
+ *
+ * Return: error code.
+ */
+int sde_power_resource_enable(struct sde_power_handle *pdata,
+	struct sde_power_client *pclient, bool enable);
+
+/**
+ * sde_power_clk_set_rate() - set the clock rate
+ * @pdata:  power handle containing the resources
+ * @clock_name: clock name which needs rate update.
+ * @rate:       Requested rate.
+ *
+ * Return: error code.
+ */
+int sde_power_clk_set_rate(struct sde_power_handle *pdata, char *clock_name,
+	u64 rate);
+
+/**
+ * sde_power_clk_get_rate() - get the clock rate
+ * @pdata:  power handle containing the resources
+ * @clock_name: clock name to get the rate
+ *
+ * Return: current clock rate
+ */
+u64 sde_power_clk_get_rate(struct sde_power_handle *pdata, char *clock_name);
+
+#endif /* _SDE_POWER_HANDLE_H_ */
-- 
cgit v1.2.3


From d18d83c45d51094bd397fd3ac24287a231703162 Mon Sep 17 00:00:00 2001
From: Alan Kwong <akwong@codeaurora.org>
Date: Sat, 17 Sep 2016 20:08:37 -0400
Subject: drm/msm/sde: add max clock property for sde

Add max clock property for sde. This property defines
the maximum allowable clock in Hz.

Change-Id: I4e8f40593345abb970c08b837c76d79f1f8a0581
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
---
 Documentation/devicetree/bindings/display/msm/sde.txt |  2 ++
 drivers/gpu/drm/msm/sde/sde_kms.c                     |  9 ---------
 drivers/gpu/drm/msm/sde_power_handle.c                | 10 ++++++++++
 include/linux/mdss_io_util.h                          |  3 ++-
 4 files changed, 14 insertions(+), 10 deletions(-)

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 7739a9cdef66..aaaf07588cc9 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -21,6 +21,7 @@ Required properties
 
 Optional properties:
 - clock-rate:		List of clock rates in Hz.
+- clock-max-rate:	List of maximum clock rate in Hz that this device supports.
 - qcom,platform-supply-entries:	A node that lists the elements of the supply. There
 				can be more than one instance of this binding,
 				in which case the entry would be appended with
@@ -80,6 +81,7 @@ Example:
       "mmagic_clk",
       "vsync_clk";
     clock-rate = <0>, <0>, <0>;
+    clock-max-rate= <0 320000000 0>;
     mmagic-supply = <&gdsc_mmagic_mdss>;
     vdd-supply = <&gdsc_mdss>;
     interrupt-parent = <&intc>;
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
index a706ef971ee9..9de81768d25f 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -32,8 +32,6 @@ static const char * const iommu_ports[] = {
 		"mdp_0",
 };
 
-#define DEFAULT_MDP_SRC_CLK 300000000
-
 /**
  * Controls size of event log buffer. Specified as a power of 2.
  */
@@ -738,13 +736,6 @@ struct msm_kms *sde_kms_init(struct drm_device *dev)
 		goto kms_destroy;
 	}
 
-	rc = sde_power_clk_set_rate(&priv->phandle, "core_clk",
-		DEFAULT_MDP_SRC_CLK);
-	if (rc) {
-		SDE_ERROR("core clock set rate failed\n");
-		goto clk_rate_err;
-	}
-
 	rc = sde_power_resource_enable(&priv->phandle, sde_kms->core_client,
 		true);
 	if (rc) {
diff --git a/drivers/gpu/drm/msm/sde_power_handle.c b/drivers/gpu/drm/msm/sde_power_handle.c
index 7385086b3005..cd5ee07d0cdc 100644
--- a/drivers/gpu/drm/msm/sde_power_handle.c
+++ b/drivers/gpu/drm/msm/sde_power_handle.c
@@ -221,6 +221,7 @@ static int sde_power_parse_dt_clock(struct platform_device *pdev,
 	u32 i = 0, rc = 0;
 	const char *clock_name;
 	u32 clock_rate;
+	u32 clock_max_rate;
 
 	if (!pdev || !mp) {
 		pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
@@ -256,6 +257,11 @@ static int sde_power_parse_dt_clock(struct platform_device *pdev,
 			mp->clk_config[i].type = DSS_CLK_AHB;
 		else
 			mp->clk_config[i].type = DSS_CLK_PCLK;
+
+		clock_max_rate = 0;
+		of_property_read_u32_index(pdev->dev.of_node, "clock-max-rate",
+							i, &clock_max_rate);
+		mp->clk_config[i].max_rate = clock_max_rate;
 	}
 
 clk_err:
@@ -521,6 +527,10 @@ int sde_power_clk_set_rate(struct sde_power_handle *phandle, char *clock_name,
 
 	for (i = 0; i < mp->num_clk; i++) {
 		if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
+			if (mp->clk_config[i].max_rate &&
+					(rate > mp->clk_config[i].max_rate))
+				rate = mp->clk_config[i].max_rate;
+
 			mp->clk_config[i].rate = rate;
 			rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
 			break;
diff --git a/include/linux/mdss_io_util.h b/include/linux/mdss_io_util.h
index 6ad21e887877..5b2587b28737 100644
--- a/include/linux/mdss_io_util.h
+++ b/include/linux/mdss_io_util.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -77,6 +77,7 @@ struct dss_clk {
 	char clk_name[32];
 	enum dss_clk_type type;
 	unsigned long rate;
+	unsigned long max_rate;
 };
 
 struct dss_module_power {
-- 
cgit v1.2.3


From b97a5e56c535e5dd962c3f9eceb68811469c9dc4 Mon Sep 17 00:00:00 2001
From: Dhaval Patel <pdhaval@codeaurora.org>
Date: Wed, 20 Jul 2016 18:13:24 -0700
Subject: drm/sde: move hardware catalog to dtsi parser

Current SDE DRM driver uses hardcoded structures
for target catalog information. This patch
removes the hardcoding from software and moves
it to dtsi parsing. It helps to remove the target
specific code drm directory and keep it in dtsi.

Change-Id: I2effaf65d7af5e22714c6e61e7f76a7e24ff86d9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt        |  228 +++-
 arch/arm/boot/dts/qcom/msm8996-sde.dtsi            |   78 ++
 drivers/gpu/drm/msm/Makefile                       |    1 -
 drivers/gpu/drm/msm/sde/sde_hw_catalog.c           | 1180 +++++++++++++++++++-
 drivers/gpu/drm/msm/sde/sde_hw_catalog.h           |   39 +-
 drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c      |  669 -----------
 drivers/gpu/drm/msm/sde/sde_hw_catalog_format.h    |  129 +++
 drivers/gpu/drm/msm/sde/sde_hw_mdss.h              |    1 +
 drivers/gpu/drm/msm/sde/sde_kms.c                  |    4 +-
 9 files changed, 1634 insertions(+), 695 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c
 create mode 100644 drivers/gpu/drm/msm/sde/sde_hw_catalog_format.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index aaaf07588cc9..0092c503464b 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -18,6 +18,51 @@ Required properties
 - interrupt-controller: Mark the device node as an interrupt controller.
 - #interrupt-cells: Should be one. The first cell is interrupt number.
 - iommus: Specifies the SID's used by this context bank.
+- qcom,sde-sspp-type:		Array of strings for SDE source surface pipes type information.
+				A source pipe can be "vig", "rgb", "dma" or "cursor" type.
+				Number of xin ids defined should match the number of offsets
+				defined in property: qcom,sde-sspp-off.
+- qcom,sde-sspp-off:		Array of offset for SDE source surface pipes. The offsets
+				are calculated from register "mdp_phys" defined in
+				reg property + "sde-off". The number of offsets defined here should
+				reflect the amount of pipes that can be active in SDE for
+				this configuration.
+- qcom,sde-sspp-xin-id:		Array of VBIF clients ids (xins) corresponding
+				to the respective source pipes. Number of xin ids
+				defined should match the number of offsets
+				defined in property: qcom,sde-sspp-off.
+- qcom,sde-ctl-off:		Array of offset addresses for the available ctl
+				hw blocks within SDE, these offsets are
+				calculated from register "mdp_phys" defined in
+				reg property.  The number of ctl offsets defined
+				here should reflect the number of control paths
+				that can be configured concurrently on SDE for
+				this configuration.
+- qcom,sde-wb-off:		Array of offset addresses for the programmable
+				writeback blocks within SDE.
+- qcom,sde-wb-xin-id:		Array of VBIF clients ids (xins) corresponding
+				to the respective writeback. Number of xin ids
+				defined should match the number of offsets
+				defined in property: qcom,sde-wb-off.
+- qcom,sde-mixer-off:	 	Array of offset addresses for the available
+				mixer blocks that can drive data to panel
+				interfaces. These offsets are be calculated from
+				register "mdp_phys" defined in reg property.
+				The number of offsets defined should reflect the
+				amount of mixers that can drive data to a panel
+				interface.
+- qcom,sde-dspp-off: 		Array of offset addresses for the available dspp
+				blocks. These offsets are calculated from
+				register "mdp_phys" defined in reg property.
+- qcom,sde-pp-off:		Array of offset addresses for the available
+				pingpong blocks. These offsets are calculated
+				from register "mdp_phys" defined in reg property.
+- qcom,sde-intf-off:		Array of offset addresses for the available SDE
+				interface blocks that can drive data to a
+				panel controller. The offsets are calculated
+				from "mdp_phys" defined in reg property. The number
+				of offsets defined should reflect the number of
+				programmable interface blocks available in hardware.
 
 Optional properties:
 - clock-rate:		List of clock rates in Hz.
@@ -39,11 +84,99 @@ Optional properties:
 				-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
 - qcom,sde-reg-bus:		Property to provide Bus scaling for register access for
 				mdss blocks.
-
+- qcom,sde-sspp-src-size:	A u32 value indicates the address range for each sspp.
+- qcom,sde-mixer-size:		A u32 value indicates the address range for each mixer.
+- qcom,sde-ctl-size:		A u32 value indicates the address range for each ctl.
+- qcom,sde-dspp-size:		A u32 value indicates the address range for each dspp.
+- qcom,sde-intf-size:		A u32 value indicates the address range for each intf.
+- qcom,sde-dsc-size:		A u32 value indicates the address range for each dsc.
+- qcom,sde-cdm-size:		A u32 value indicates the address range for each cdm.
+- qcom,sde-pp-size:		A u32 value indicates the address range for each pingpong.
+- qcom,sde-wb-size:		A u32 value indicates the address range for each writeback.
+- qcom,sde-len:			A u32 entry for SDE address range.
+- qcom,sde-intf-max-prefetch-lines:	Array of u32 values for max prefetch lines on
+				each interface.
+- qcom,sde-sspp-linewidth:	A u32 value indicates the max sspp line width.
+- qcom,sde-mixer-linewidth:	A u32 value indicates the max mixer line width.
+- qcom,sde-wb-linewidth:	A u32 value indicates the max writeback line width.
+- qcom,sde-sspp-scale-size:	A u32 value indicates the scaling block size on sspp.
+- qcom,sde-mixer-blendstages:	A u32 value indicates the max mixer blend stages for
+				alpha blending.
+- qcom,sde-qseed-type:		A string entry indiates qseed support on sspp and wb.
+				It supports "qssedv3" and "qseedv2" entries for qseed
+				type. By default "qseedv2" is used if this optional property
+				is not defined.
+- qcom,sde-highest-bank-bit:	A u32 property to indicate GPU/Camera/Video highest memory
+				bank bit used for tile format buffers.
+- qcom,sde-panic-per-pipe:	Boolean property to indicate if panic signal
+				control feature is available on each source pipe.
+- qcom,sde-has-src-split:	Boolean property to indicate if source split
+				feature is available or not.
+- qcom,sde-has-mixer-gc:	Boolean property to indicate if mixer has gamma correction
+				feature available or not.
+- qcom,sde-has-cdp:		Boolean property to indicate if cdp feature is
+				available or not.
+- qcom,sde-sspp-clk-ctrl:	Array of offsets describing clk control
+				offsets for dynamic clock gating. 1st value
+				in the array represents offset of the control
+				register. 2nd value represents bit offset within
+				control register. Number of offsets defined should
+				match the number of offsets defined in
+				property: qcom,sde-sspp-off
+- qcom,sde-sspp-clk-status:	Array of offsets describing clk status
+				offsets for dynamic clock gating. 1st value
+				in the array represents offset of the status
+				register. 2nd value represents bit offset within
+				control register. Number of offsets defined should
+				match the number of offsets defined in
+				property: qcom,sde-sspp-off.
+- qcom,sde-sspp-danger-lut:	Array of u32 values indicating the danger luts on each
+				sspp. Number of offsets defined should
+				match the number of offsets defined in
+				property: qcom,sde-sspp-off.
+- qcom,sde-sspp-safe-lut:	Array of u32 values indicating the safe luts on each
+				sspp. Number of offsets defined should
+				match the number of offsets defined in
+				property: qcom,sde-sspp-off.
+- qcom,sde-sspp-qseed-off:	A u32 offset value indicates the qseed block offset
+				from sspp base. It will install qseed property on
+				vig and rgb sspp pipes.
+- qcom,sde-sspp-csc-off:	A u32 offset value indicates the csc block offset
+				from sspp base. It will be used to install the csc
+				property on vig type pipe.
+- qcom,sde-sspp-max-rects:	Array of u32 values indicating maximum rectangles supported
+				on each sspp. This property is for multirect feature support.
+				Number of offsets defined should match the number of
+				offsets defined in property: qcom,sde-sspp-off.
+- qcom,sde-intf-type:		Array of string provides the interface type information.
+				Possible string values
+					"dsi" - dsi display interface
+					"dp" - Display Port interface
+					"hdmi" - HDMI display interface
+				An interface is considered as "none" if interface type
+				is not defined.
+- qcom,sde-off:			SDE offset from "mdp_phys" defined in reg property.
+- qcom,sde-cdm-off:	 	Array of offset addresses for the available
+				cdm blocks. These offsets will be calculated from
+				register "mdp_phys" defined in reg property.
+- qcom,sde-te-off:		A u32 offset indicates the te block offset on pingpong.
+				This offset is 0x0 by default.
+- qcom,sde-te2-off:		A u32 offset indicates the te2 block offset on pingpong.
+- qcom,sde-te-size:		A u32 value indicates the te block address range.
+- qcom,sde-te2-size:		A u32 value indicates the te2 block address range.
+- qcom,sde-dsc-off:	 	A u32 offset indicates the dsc block offset on pingpong.
+- qcom,sde-dspp-igc-off:	A u32 offset indicates the igc block offset on dssp.
+- qcom,sde-dspp-pcc-off:	A u32 offset indicates the pcc block offset on dssp.
+- qcom,sde-dspp-gc-off:		A u32 offset indicates the gc block offset on dssp.
+- qcom,sde-dspp-pa-off:		A u32 offset indicates the pa block offset on dssp.
+- qcom,sde-dspp-gamut-off:	A u32 offset indicates the gamut block offset on dssp.
+- qcom,sde-dspp-dither-off:	A u32 offset indicates the dither block offset on dssp.
+- qcom,sde-dspp-hist-off:	A u32 offset indicates the hist block offset on dssp.
+- qcom,sde-dspp-ad-off:		A u32 offset indicates the ad block offset on dssp.
 
 Bus Scaling Data:
 - qcom,msm-bus,name:		String property describing client name.
-- qcom,msm-bus,num-cases:	This is the the number of Bus Scaling use cases
+- qcom,msm-bus,num-cases:	This is the number of Bus Scaling use cases
 				defined in the vectors property.
 - qcom,msm-bus,num-paths:	This represents the number of paths in each
 				Bus Scaling Usecase.
@@ -90,6 +223,97 @@ Example:
     #interrupt-cells = <1>;
     iommus = <&mdp_smmu 0>;
 
+    qcom,sde-off = <0x1000>;
+    qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400
+		     0x00002600 0x00002800>;
+    qcom,sde-mixer-off = <0x00045000 0x00046000
+			0x00047000 0x0004a000>;
+    qcom,sde-dspp-off = <0x00055000 0x00057000>;
+    qcom,sde-wb-off = <0x00066000>;
+    qcom,sde-wb-xin-id = <6>;
+    qcom,sde-intf-off = <0x0006b000 0x0006b800
+			0x0006c000 0x0006c800>;
+    qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi";
+    qcom,sde-pp-off = <0x00071000 0x00071800
+			  0x00072000 0x00072800>;
+    qcom,sde-cdm-off = <0x0007a200>;
+    qcom,sde-dsc-off = <0x00081000 0x00081400>;
+    qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;
+
+    qcom,sde-sspp-type = "vig", "vig", "vig",
+			      "vig", "rgb", "rgb",
+			      "rgb", "rgb", "dma",
+			      "dma", "cursor", "cursor";
+
+    qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000
+		      0x0000b000 0x00015000 0x00017000
+		      0x00019000 0x0001b000 0x00025000
+		      0x00027000 0x00035000 0x00037000>;
+
+    qcom,sde-sspp-xin-id = <0 4 8
+			12 1 5
+			9 13 2
+			10 7 7>;
+
+    /* offsets are relative to "mdp_phys + qcom,sde-off */
+    qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
+			  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
+			  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
+			  <0x3b0 16>;
+    qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
+			  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
+			  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
+			  <0x3b0 16>;
+    qcom,sde-mixer-linewidth = <2560>;
+    qcom,sde-sspp-linewidth = <2560>;
+    qcom,sde-mixer-blendstages = <0x7>;
+    qcom,sde-highest-bank-bit = <0x2>;
+    qcom,sde-panic-per-pipe;
+    qcom,sde-has-cdp;
+    qcom,sde-has-src-split;
+    qcom,sde-sspp-src-size = <0x100>;
+    qcom,sde-mixer-size = <0x100>;
+    qcom,sde-ctl-size = <0x100>;
+    qcom,sde-dspp-size = <0x100>;
+    qcom,sde-intf-size = <0x100>;
+    qcom,sde-dsc-size = <0x100>;
+    qcom,sde-cdm-size = <0x100>;
+    qcom,sde-pp-size = <0x100>;
+    qcom,sde-wb-size = <0x100>;
+    qcom,sde-len = <0x100>;
+    qcom,sde-wb-linewidth = <2560>;
+    qcom,sde-sspp-scale-size = <0x100>;
+    qcom,sde-mixer-blendstages = <0x8>;
+    qcom,sde-qseed-type = "qseedv2";
+    qcom,sde-highest-bank-bit = <15>;
+    qcom,sde-has-mixer-gc;
+    qcom,sde-sspp-danger-lut = <0x55 0x55 0x55 0x55
+				0x55 0x55 0x55 0x55
+				0xaa 0xaa
+				0xbb 0xbb>;
+    qcom,sde-sspp-safe-lut = <0x11 0x11 0x11 0x11
+				0x11 0x11 0x11 0x11
+				0xaa 0xaa
+				0xbb 0xbb>;
+    qcom,sde-sspp-max-rects = <1 1 1 1
+				1 1 1 1
+				1 1
+				1 1>;
+    qcom,sde-te-off = <0x100>;
+    qcom,sde-te2-off = <0x100>;
+    qcom,sde-te-size = <0xffff>;
+    qcom,sde-te2-size = <0xffff>;
+    qcom,sde-sspp-qseed-off = <0x100>;
+    qcom,sde-sspp-csc-off = <0x100>;
+    qcom,sde-dspp-igc-off = <0x100>;
+    qcom,sde-dspp-pcc-off = <0x100>;
+    qcom,sde-dspp-gc-off = <0x100>;
+    qcom,sde-dspp-pa-off = <0x100>;
+    qcom,sde-dspp-gamut-off = <0x100>;
+    qcom,sde-dspp-dither-off = <0x100>;
+    qcom,sde-dspp-hist-off = <0x100>;
+    qcom,sde-dspp-ad-off = <0x100>;
+
     qcom,platform-supply-entries {
        #address-cells = <1>;
        #size-cells = <0>;
diff --git a/arch/arm/boot/dts/qcom/msm8996-sde.dtsi b/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
index c00f05b8c699..ea14b16df0af 100644
--- a/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
@@ -19,6 +19,8 @@
 		reg-names = "mdp_phys",
 			"vbif_phys",
 			"vbif_nrt_phys";
+
+		/* clock and supply entries */
 		clocks = <&clock_mmss clk_mdss_ahb_clk>,
 			 <&clock_mmss clk_mdss_axi_clk>,
 			 <&clock_mmss clk_mdp_clk_src>,
@@ -42,12 +44,63 @@
 		clock-rate = <0 0 300000000 300000000 0 0 0 0>;
 		clock-max-rate = <0 0 412500000 412500000 0 0 0 0>;
 
+		/* interrupt config */
 		interrupt-parent = <&intc>;
 		interrupts = <0 83 0>;
 		interrupt-controller;
 		#interrupt-cells = <1>;
 		iommus = <&mdp_smmu 0>;
 
+		/* hw blocks */
+		qcom,sde-off = <0x1000>;
+		qcom,sde-ctl-off = <0x2000 0x2200 0x2400
+				     0x2600 0x2800>;
+		qcom,sde-mixer-off = <0x45000 0x46000 0x47000
+				      0x48000 0x49000 0x4a000>;
+		qcom,sde-dspp-off = <0x55000 0x57000>;
+		qcom,sde-wb-off = <0x65000 0x65800 0x66000>;
+		qcom,sde-wb-xin-id = <3 11 6>;
+		qcom,sde-intf-off = <0x6b000 0x6b800
+					0x6c000 0x6c800>;
+		qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi";
+		qcom,sde-pp-off = <0x71000 0x71800
+					  0x72000 0x72800>;
+		qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>;
+		qcom,sde-cdm-off = <0x7a200>;
+		qcom,sde-dsc-off = <0x10000 0x10000 0x0 0x0>;
+		qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;
+
+		qcom,sde-sspp-type = "vig", "vig", "vig",
+				      "vig", "rgb", "rgb",
+				      "rgb", "rgb", "dma",
+				      "dma", "cursor", "cursor";
+
+		qcom,sde-sspp-off = <0x5000 0x7000 0x9000
+				      0xb000 0x15000 0x17000
+				      0x19000 0x1b000 0x25000
+				      0x27000 0x35000 0x37000>;
+
+		qcom,sde-sspp-xin-id = <0 4 8
+					12 1 5
+					9 13 2
+					10 7 7>;
+
+		/* offsets are relative to "mdp_phys + qcom,sde-off */
+		qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
+				  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
+				  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
+				  <0x3b0 16>;
+		qcom,sde-sspp-csc-off = <0x320>;
+		qcom,sde-qseed-type = "qseedv2";
+		qcom,sde-sspp-qseed-off = <0x200>;
+		qcom,sde-mixer-linewidth = <2560>;
+		qcom,sde-sspp-linewidth = <2560>;
+		qcom,sde-mixer-blendstages = <0x7>;
+		qcom,sde-highest-bank-bit = <0x2>;
+		qcom,sde-panic-per-pipe;
+		qcom,sde-has-cdp;
+		qcom,sde-has-src-split;
+
 		mmagic-supply = <&gdsc_mmagic_mdss>;
 		vdd-supply = <&gdsc_mdss>;
 
@@ -93,6 +146,31 @@
 			compatible = "qcom,smmu_rot_sec";
 			iommus = <&rot_smmu 1>;
 		};
+
+		/* data and reg bus scale settings */
+		mdss-data-bus {
+			qcom,msm-bus,name = "mdss_sde";
+			qcom,msm-bus,num-cases = <3>;
+			qcom,msm-bus,num-paths = <3>;
+			qcom,msm-bus,vectors-KBps =
+				<22 512 0 0>, <23 512 0 0>, <25 512 0 0>,
+				<22 512 0 6400000>, <23 512 0 6400000>,
+					<25 512 0 6400000>,
+				<22 512 0 6400000>, <23 512 0 6400000>,
+					<25 512 0 6400000>;
+		};
+
+		mdss-reg-bus {
+			qcom,msm-bus,name = "mdss_reg";
+			qcom,msm-bus,num-cases = <4>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,active-only;
+			qcom,msm-bus,vectors-KBps =
+				<1 590 0 0>,
+				<1 590 0 76800>,
+				<1 590 0 160000>,
+				<1 590 0 320000>;
+		};
 	};
 
 	mdss_dsi0: qcom,mdss_dsi_ctrl0@994000 {
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 2eb52c4a9581..776120ce9a62 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -108,7 +108,6 @@ msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \
 obj-$(CONFIG_DRM_MSM)	+= msm.o
 
 obj-$(CONFIG_DRM_MSM) += sde/sde_hw_catalog.o \
-	sde/sde_hw_catalog_8996.o \
 	sde/sde_hw_cdm.o \
 	sde/sde_hw_dspp.o \
 	sde/sde_hw_intf.o \
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index 97faec3ed3c2..9b16f26287ed 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -10,28 +10,1178 @@
  * GNU General Public License for more details.
  */
 
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+#include <linux/slab.h>
+#include <linux/of_address.h>
+
+#include "sde_hw_mdss.h"
 #include "sde_hw_catalog.h"
+#include "sde_hw_catalog_format.h"
+#include "sde_kms.h"
 
-struct sde_mdss_hw_cfg_handler cfg_table[] = {
-	{ .major = 1, .minor = 7, .cfg_init = sde_mdss_cfg_170_init},
-};
+/*************************************************************
+ * MACRO DEFINITION
+ *************************************************************/
 
 /**
- * sde_hw_catalog_init: Returns the catalog information for the
- * passed HW version
- * @major:  Major version of the MDSS HW
- * @minor: Minor version
- * @step: step version
+ * Max hardware block in certain hardware. For ex: sspp pipes
+ * can have QSEED, pcc, igc, pa, csc, etc. This count is max
+ * 12 based on software design. It should be increased if any of the
+ * hardware block has more subblocks.
  */
-struct sde_mdss_cfg *sde_hw_catalog_init(u32 major, u32 minor, u32 step)
+#define MAX_SDE_HW_BLK  12
+
+/* each entry will have register address and bit offset in that register */
+#define MAX_BIT_OFFSET 2
+
+/* default line width for sspp */
+#define DEFAULT_SDE_LINE_WIDTH 2048
+
+/* max mixer blend stages */
+#define DEFAULT_SDE_MIXER_BLENDSTAGES 7
+
+/* max bank bit for macro tile and ubwc format */
+#define DEFAULT_SDE_HIGHEST_BANK_BIT 15
+
+/* default hardware block size if dtsi entry is not present */
+#define DEFAULT_SDE_HW_BLOCK_LEN 0x100
+
+/* default rects for multi rect case */
+#define DEFAULT_SDE_SSPP_MAX_RECTS 1
+
+/* total number of intf - dp, dsi, hdmi */
+#define INTF_COUNT			3
+
+#define MAX_SSPP_UPSCALE		20
+#define MAX_SSPP_DOWNSCALE		4
+#define SSPP_UNITY_SCALE		1
+
+#define MAX_HORZ_DECIMATION		4
+#define MAX_VERT_DECIMATION		4
+
+#define MAX_SPLIT_DISPLAY_CTL		2
+#define MAX_PP_SPLIT_DISPLAY_CTL	1
+
+#define MDSS_BASE_OFFSET		0x0
+
+#define ROT_LM_OFFSET			3
+#define LINE_LM_OFFSET			5
+#define LINE_MODE_WB_OFFSET		2
+
+/*************************************************************
+ *  DTSI PROPERTY INDEX
+ *************************************************************/
+enum {
+	HW_OFF,
+	HW_LEN,
+};
+
+enum sde_prop {
+	SDE_OFF,
+	SDE_LEN,
+	SSPP_LINEWIDTH,
+	MIXER_LINEWIDTH,
+	MIXER_BLEND,
+	WB_LINEWIDTH,
+	BANK_BIT,
+	QSEED_TYPE,
+	PANIC_PER_PIPE,
+	CDP,
+};
+
+enum {
+	SSPP_OFF,
+	SSPP_SIZE,
+	SSPP_TYPE,
+	SSPP_XIN,
+	SSPP_CLK_CTRL,
+	SSPP_CLK_STATUS,
+	SSPP_DANGER,
+	SSPP_SAFE,
+	SSPP_MAX_RECTS,
+	SSPP_SCALE_SIZE,
+	SSPP_QSEED_OFF,
+	SSPP_CSC_OFF,
+};
+
+enum {
+	INTF_OFF,
+	INTF_LEN,
+	INTF_PREFETCH,
+	INTF_TYPE,
+};
+
+enum {
+	PP_OFF,
+	PP_LEN,
+	TE_OFF,
+	TE_LEN,
+	TE2_OFF,
+	TE2_LEN,
+	DSC_OFF,
+	DSC_LEN,
+};
+
+enum {
+	DSPP_OFF,
+	DSPP_SIZE,
+	DSPP_IGC,
+	DSPP_PCC,
+	DSPP_GC,
+	DSPP_PA,
+	DSPP_GAMUT,
+	DSPP_DITHER,
+	DSPP_HIST,
+	DSPP_AD,
+};
+
+enum {
+	MIXER_OFF,
+	MIXER_LEN,
+	SRC_SPLIT,
+	MIXER_GC,
+};
+
+enum {
+	WB_OFF,
+	WB_LEN,
+	WB_XIN_ID,
+};
+
+/*************************************************************
+ * dts property definition
+ *************************************************************/
+enum prop_type {
+	PROP_TYPE_BOOL,
+	PROP_TYPE_U32,
+	PROP_TYPE_U32_ARRAY,
+	PROP_TYPE_STRING,
+	PROP_TYPE_STRING_ARRAY,
+	PROP_TYPE_BIT_OFFSET_ARRAY,
+};
+
+struct sde_prop_type {
+	/* use property index from enum property for readability purpose */
+	u8 id;
+	/* it should be property name based on dtsi documentation */
+	char *prop_name;
+	/**
+	 * if property is marked mandatory then it will fail parsing
+	 * when property is not present
+	 */
+	u32  is_mandatory;
+	/* property type based on "enum prop_type"  */
+	enum prop_type type;
+};
+
+/*************************************************************
+ * dts property list
+ *************************************************************/
+static struct sde_prop_type sde_prop[] = {
+	{SDE_OFF, "qcom,sde-off", true, PROP_TYPE_U32},
+	{SDE_LEN, "qcom,sde-len", false, PROP_TYPE_U32},
+	{SSPP_LINEWIDTH, "qcom,sde-sspp-linewidth", false, PROP_TYPE_U32},
+	{MIXER_LINEWIDTH, "qcom,sde-mixer-linewidth", false, PROP_TYPE_U32},
+	{MIXER_BLEND, "qcom,sde-mixer-blendstages", false, PROP_TYPE_U32},
+	{WB_LINEWIDTH, "qcom,sde-wb-linewidth", false, PROP_TYPE_U32},
+	{BANK_BIT, "qcom,sde-highest-bank-bit", false, PROP_TYPE_U32},
+	{QSEED_TYPE, "qcom,sde-qseed-type", false, PROP_TYPE_STRING},
+	{PANIC_PER_PIPE, "qcom,sde-panic-per-pipe", false, PROP_TYPE_BOOL},
+	{CDP, "qcom,sde-has-cdp", false, PROP_TYPE_BOOL},
+};
+
+static struct sde_prop_type sspp_prop[] = {
+	{SSPP_OFF, "qcom,sde-sspp-off", true, PROP_TYPE_U32_ARRAY},
+	{SSPP_SIZE, "qcom,sde-sspp-src-size", false, PROP_TYPE_U32},
+	{SSPP_TYPE, "qcom,sde-sspp-type", true, PROP_TYPE_STRING_ARRAY},
+	{SSPP_XIN, "qcom,sde-sspp-xin-id", true, PROP_TYPE_U32_ARRAY},
+	{SSPP_CLK_CTRL, "qcom,sde-sspp-clk-ctrl", false,
+		PROP_TYPE_BIT_OFFSET_ARRAY},
+	{SSPP_CLK_STATUS, "qcom,sde-sspp-clk-status", false,
+		PROP_TYPE_BIT_OFFSET_ARRAY},
+	{SSPP_DANGER, "qcom,sde-sspp-danger-lut", false, PROP_TYPE_U32_ARRAY},
+	{SSPP_SAFE, "qcom,sde-sspp-safe-lut", false, PROP_TYPE_U32_ARRAY},
+	{SSPP_MAX_RECTS, "qcom,sde-sspp-max-rects", false, PROP_TYPE_U32_ARRAY},
+	{SSPP_SCALE_SIZE, "qcom,sde-sspp-scale-size", false, PROP_TYPE_U32},
+	{SSPP_QSEED_OFF, "qcom,sde-sspp-qseed-off", false, PROP_TYPE_U32},
+	{SSPP_CSC_OFF, "qcom,sde-sspp-csc-off", false, PROP_TYPE_U32},
+};
+
+static struct sde_prop_type ctl_prop[] = {
+	{HW_OFF, "qcom,sde-ctl-off", true, PROP_TYPE_U32_ARRAY},
+	{HW_LEN, "qcom,sde-ctl-size", false, PROP_TYPE_U32},
+};
+
+static struct sde_prop_type mixer_prop[] = {
+	{MIXER_OFF, "qcom,sde-mixer-off", true, PROP_TYPE_U32_ARRAY},
+	{MIXER_LEN, "qcom,sde-mixer-size", false, PROP_TYPE_U32},
+	{SRC_SPLIT, "qcom,sde-has-src-split", false, PROP_TYPE_BOOL},
+	{MIXER_GC, "qcom,sde-has-mixer-gc", false, PROP_TYPE_BOOL},
+};
+
+static struct sde_prop_type dspp_prop[] = {
+	{DSPP_OFF, "qcom,sde-dspp-off", true, PROP_TYPE_U32_ARRAY},
+	{DSPP_SIZE, "qcom,sde-dspp-size", false, PROP_TYPE_U32},
+	{DSPP_IGC, "qcom,sde-dspp-igc-off", false, PROP_TYPE_U32},
+	{DSPP_PCC, "qcom,sde-dspp-pcc-off", false, PROP_TYPE_U32},
+	{DSPP_GC, "qcom,sde-dspp-gc-off", false, PROP_TYPE_U32},
+	{DSPP_PA, "qcom,sde-dspp-pa-off", false, PROP_TYPE_U32},
+	{DSPP_GAMUT, "qcom,sde-dspp-gamut-off", false, PROP_TYPE_U32},
+	{DSPP_DITHER, "qcom,sde-dspp-dither-off", false, PROP_TYPE_U32},
+	{DSPP_HIST, "qcom,sde-dspp-hist-off", false, PROP_TYPE_U32},
+	{DSPP_AD, "qcom,sde-dspp-ad-off", false, PROP_TYPE_U32_ARRAY},
+};
+
+static struct sde_prop_type pp_prop[] = {
+	{PP_OFF, "qcom,sde-pp-off", true, PROP_TYPE_U32_ARRAY},
+	{PP_LEN, "qcom,sde-pp-size", false, PROP_TYPE_U32},
+	{TE_OFF, "qcom,sde-te-off", false, PROP_TYPE_U32_ARRAY},
+	{TE_LEN, "qcom,sde-te-size", false, PROP_TYPE_U32},
+	{TE2_OFF, "qcom,sde-te2-off", false, PROP_TYPE_U32_ARRAY},
+	{TE2_LEN, "qcom,sde-te2-size", false, PROP_TYPE_U32},
+	{DSC_OFF, "qcom,sde-dsc-off", false, PROP_TYPE_U32_ARRAY},
+	{DSC_LEN, "qcom,sde-dsc-size", false, PROP_TYPE_U32},
+};
+
+static struct sde_prop_type cdm_prop[] = {
+	{HW_OFF, "qcom,sde-cdm-off", false, PROP_TYPE_U32_ARRAY},
+	{HW_LEN, "qcom,sde-cdm-size", false, PROP_TYPE_U32},
+};
+
+static struct sde_prop_type intf_prop[] = {
+	{INTF_OFF, "qcom,sde-intf-off", true, PROP_TYPE_U32_ARRAY},
+	{INTF_LEN, "qcom,sde-intf-size", false, PROP_TYPE_U32},
+	{INTF_PREFETCH, "qcom,sde-intf-max-prefetch-lines", false,
+						PROP_TYPE_U32_ARRAY},
+	{INTF_TYPE, "qcom,sde-intf-type", false, PROP_TYPE_STRING_ARRAY},
+};
+
+static struct sde_prop_type wb_prop[] = {
+	{WB_OFF, "qcom,sde-wb-off", true, PROP_TYPE_U32_ARRAY},
+	{WB_LEN, "qcom,sde-wb-size", false, PROP_TYPE_U32},
+	{WB_XIN_ID, "qcom,sde-wb-xin-id", false, PROP_TYPE_U32_ARRAY},
+};
+
+/*************************************************************
+ * static API list
+ *************************************************************/
+static int _parse_dt_u32_handler(struct device_node *np,
+	char *prop_name, u32 *offsets, int len, bool mandatory)
 {
-	int i;
+	int rc = of_property_read_u32_array(np, prop_name, offsets, len);
+
+	if (rc && mandatory)
+		SDE_ERROR("mandatory prop: %s u32 array read len:%d\n",
+				prop_name, len);
+	else if (rc)
+		SDE_DEBUG("optional prop: %s u32 array read len:%d\n",
+				prop_name, len);
+
+	return rc;
+}
+
+static int _parse_dt_bit_offset(struct device_node *np,
+	char *prop_name, u32 prop_value[][MAX_BIT_OFFSET],
+	u32 count, bool mandatory)
+{
+	int rc = 0, len, i, j;
+	const u32 *arr;
+
+	arr = of_get_property(np, prop_name, &len);
+	if (arr) {
+		len /= sizeof(u32);
+		for (i = 0, j = 0; i < len; j++) {
+			prop_value[j][i] = be32_to_cpu(arr[i]);
+			i++;
+			prop_value[j][i] = be32_to_cpu(arr[i]);
+			i++;
+		}
+	} else {
+		if (mandatory) {
+			SDE_ERROR("error mandatory property '%s' not found\n",
+				prop_name);
+			rc = -EINVAL;
+		} else {
+			SDE_DEBUG("error optional property '%s' not found\n",
+				prop_name);
+		}
+	}
+
+	return rc;
+}
+
+static int _validate_dt_entry(struct device_node *np,
+	struct sde_prop_type *sde_prop, u32 prop_size, int *prop_count,
+	int *off_count)
+{
+	int rc = 0, i, val;
+
+	*off_count = of_property_count_u32_elems(np, sde_prop[0].prop_name);
+	if ((*off_count > MAX_BLOCKS) || (*off_count < 0)) {
+		SDE_ERROR("invalid hw offset prop name:%s count:%d\n",
+			sde_prop[0].prop_name, *off_count);
+		*off_count = 0;
+		return sde_prop[0].is_mandatory ? -EINVAL : 0;
+	}
+
+	for (i = 0; i < prop_size && i < MAX_BLOCKS; i++) {
+		switch (sde_prop[i].type) {
+		case PROP_TYPE_U32:
+			rc = of_property_read_u32(np, sde_prop[i].prop_name,
+				&val);
+			break;
+		case PROP_TYPE_U32_ARRAY:
+			prop_count[i] = of_property_count_u32_elems(np,
+				sde_prop[i].prop_name);
+			break;
+		case PROP_TYPE_STRING_ARRAY:
+			prop_count[i] = of_property_count_strings(np,
+				sde_prop[i].prop_name);
+			break;
+		case PROP_TYPE_BIT_OFFSET_ARRAY:
+			of_get_property(np, sde_prop[i].prop_name, &val);
+			prop_count[i] = val / (MAX_BIT_OFFSET * sizeof(u32));
+			break;
+		default:
+			SDE_DEBUG("invalid property type:%d\n",
+							sde_prop[i].type);
+			break;
+		}
+		SDE_DEBUG("prop id:%d prop name:%s prop type:%d \"\
+			prop_count:%d\n", i, sde_prop[i].prop_name,
+			sde_prop[i].type, prop_count[i]);
+
+		if (rc && sde_prop[i].is_mandatory &&
+		   (sde_prop[i].type == PROP_TYPE_U32)) {
+			SDE_ERROR("prop:%s not present\n",
+						sde_prop[i].prop_name);
+			goto end;
+		} else if (sde_prop[i].type == PROP_TYPE_U32 ||
+			sde_prop[i].type == PROP_TYPE_BOOL) {
+			rc = 0;
+			continue;
+		}
+
+		if ((prop_count[i] != *off_count) && sde_prop[i].is_mandatory) {
+			SDE_ERROR("prop:%s count:%d is different compared to \"\
+				offset array:%d\n", sde_prop[i].prop_name,
+				prop_count[i], *off_count);
+			rc = -EINVAL;
+			goto end;
+		} else if (prop_count[i] != *off_count) {
+			SDE_DEBUG("prop:%s count:%d is different compared to \"\
+				offset array:%d\n", sde_prop[i].prop_name,
+				prop_count[i], *off_count);
+			rc = 0;
+			prop_count[i] = 0;
+		}
+	}
+
+end:
+	return rc;
+}
+
+static int _read_dt_entry(struct device_node *np,
+	struct sde_prop_type *sde_prop, u32 prop_size, u32 *prop_count,
+	u32 prop_value[][MAX_SDE_HW_BLK],
+	u32 bit_value[][MAX_SDE_HW_BLK][MAX_BIT_OFFSET])
+{
+	int rc = 0, i, j;
+
+	for (i = 0; i < prop_size && i < MAX_BLOCKS; i++) {
+		switch (sde_prop[i].type) {
+		case PROP_TYPE_U32:
+			of_property_read_u32(np, sde_prop[i].prop_name,
+				&prop_value[i][0]);
+			SDE_DEBUG("prop id:%d prop name:%s prop type:%d \"\
+				 value:0x%x\n", i, sde_prop[i].prop_name,
+				sde_prop[i].type, prop_value[i][0]);
+			break;
+		case PROP_TYPE_BOOL:
+			prop_value[i][0] =  of_property_read_bool(np,
+				sde_prop[i].prop_name);
+			SDE_DEBUG("prop id:%d prop name:%s prop type:%d \"\
+				value:0x%x\n", i, sde_prop[i].prop_name,
+				sde_prop[i].type, prop_value[i][0]);
+			break;
+		case PROP_TYPE_U32_ARRAY:
+			rc = _parse_dt_u32_handler(np, sde_prop[i].prop_name,
+				prop_value[i], prop_count[i],
+				sde_prop[i].is_mandatory);
+			if (rc && sde_prop[i].is_mandatory) {
+				SDE_ERROR("%s prop validation success but \"\
+					read failed\n", sde_prop[i].prop_name);
+				goto end;
+			} else {
+				/* only for debug purpose */
+				SDE_DEBUG("prop id:%d prop name:%s prop \"\
+					type:%d", i, sde_prop[i].prop_name,
+					sde_prop[i].type);
+				for (j = 0; j < prop_count[i]; j++)
+					SDE_DEBUG(" value[%d]:0x%x ", j,
+							prop_value[i][j]);
+				SDE_DEBUG("\n");
+			}
+			break;
+		case PROP_TYPE_BIT_OFFSET_ARRAY:
+			rc = _parse_dt_bit_offset(np, sde_prop[i].prop_name,
+				bit_value[i], prop_count[i],
+				sde_prop[i].is_mandatory);
+			if (rc && sde_prop[i].is_mandatory) {
+				SDE_ERROR("%s prop validation success but \"\
+					read failed\n", sde_prop[i].prop_name);
+				goto end;
+			} else {
+				SDE_DEBUG("prop id:%d prop name:%s prop \"\
+					type:%d", i, sde_prop[i].prop_name,
+					sde_prop[i].type);
+				for (j = 0; j < prop_count[i]; j++)
+					SDE_DEBUG(" count[%d]: bit:0x%x \"\
+					off:0x%x ", j, bit_value[i][j][0],
+					bit_value[i][j][1]);
+				SDE_DEBUG("\n");
+			}
+			break;
+		default:
+			SDE_DEBUG("invalid property type:%d\n",
+							sde_prop[i].type);
+			break;
+		}
+		rc = 0;
+	}
+
+end:
+	return rc;
+}
+
+static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg,
+	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
+	u32 prop_value[][MAX_SDE_HW_BLK], u32 *vig_count)
+{
+	if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) {
+		set_bit(SDE_SSPP_SCALER_QSEED2, &sspp->features);
+		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;
+		sblk->scaler_blk.base = prop_value[SSPP_QSEED_OFF][0];
+	 } else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {
+		set_bit(SDE_SSPP_SCALER_QSEED3, &sspp->features);
+		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;
+		sblk->scaler_blk.base = prop_value[SSPP_QSEED_OFF][0];
+	}
+
+	set_bit(SDE_SSPP_CSC, &sspp->features);
+	sblk->csc_blk.base = prop_value[SSPP_CSC_OFF][0];
+	sblk->csc_blk.id = SDE_SSPP_CSC;
+
+	sblk->maxupscale = MAX_SSPP_UPSCALE;
+	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
+	sspp->id = SSPP_VIG0 + *vig_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
+	sblk->format_list = plane_formats_yuv;
+	(*vig_count)++;
+}
+
+static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg,
+	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
+	u32 prop_value[][MAX_SDE_HW_BLK], u32 *rgb_count)
+{
+	if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) {
+		set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
+		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;
+		sblk->scaler_blk.base = prop_value[SSPP_QSEED_OFF][0];
+	} else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {
+		set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
+		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;
+		sblk->scaler_blk.base = prop_value[SSPP_QSEED_OFF][0];
+	}
+
+	sblk->maxupscale = MAX_SSPP_UPSCALE;
+	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
+	sspp->id = SSPP_RGB0 + *rgb_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
+	sblk->format_list = plane_formats;
+	(*rgb_count)++;
+}
+
+static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg,
+	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
+	u32 prop_value[][MAX_SDE_HW_BLK], u32 *cursor_count)
+{
+	set_bit(SDE_SSPP_CURSOR, &sspp->features);
+	sblk->maxupscale = SSPP_UNITY_SCALE;
+	sblk->maxdwnscale = SSPP_UNITY_SCALE;
+	sspp->id = SSPP_CURSOR0 + *cursor_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
+	sblk->format_list = plane_formats;
+	(*cursor_count)++;
+}
+
+static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg,
+	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
+	u32 prop_value[][MAX_SDE_HW_BLK], u32 *dma_count)
+{
+	sblk->maxupscale = SSPP_UNITY_SCALE;
+	sblk->maxdwnscale = SSPP_UNITY_SCALE;
+	sspp->id = SSPP_DMA0 + *dma_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
+	sblk->format_list = plane_formats;
+	(*dma_count)++;
+}
+
+static int sde_sspp_parse_dt(struct device_node *np,
+	struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MAX_BLOCKS], off_count, i;
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK];
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET];
+	const char *type;
+	struct sde_sspp_cfg *sspp;
+	struct sde_sspp_sub_blks *sblk;
+	u32 vig_count = 0, dma_count = 0, rgb_count = 0, cursor_count = 0;
+
+	rc = _validate_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop),
+		prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	rc = _read_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop), prop_count,
+							prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	sde_cfg->sspp_count = off_count;
+
+	for (i = 0; i < off_count; i++) {
+		sspp = sde_cfg->sspp + i;
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		sspp->sblk = sblk;
+
+		sspp->base = prop_value[SSPP_OFF][i];
+		sblk->maxlinewidth = sde_cfg->max_sspp_linewidth;
+
+		set_bit(SDE_SSPP_SRC, &sspp->features);
+		sblk->src_blk.id = SDE_SSPP_SRC;
+
+		of_property_read_string_index(np,
+				sspp_prop[SSPP_TYPE].prop_name, i, &type);
+		if (!strcmp(type, "vig")) {
+			_sde_sspp_setup_vig(sde_cfg, sspp, sblk, prop_value,
+								&vig_count);
+		} else if (!strcmp(type, "rgb")) {
+			_sde_sspp_setup_rgb(sde_cfg, sspp, sblk, prop_value,
+								&rgb_count);
+		} else if (!strcmp(type, "cursor")) {
+			_sde_sspp_setup_cursor(sde_cfg, sspp, sblk, prop_value,
+								&cursor_count);
+		} else if (!strcmp(type, "dma")) {
+			_sde_sspp_setup_dma(sde_cfg, sspp, sblk, prop_value,
+								&dma_count);
+		} else {
+			SDE_ERROR("invalid sspp type:%s\n", type);
+			rc = -EINVAL;
+			goto end;
+		}
+
+		sblk->maxhdeciexp = MAX_HORZ_DECIMATION;
+		sblk->maxvdeciexp = MAX_VERT_DECIMATION;
+
+		sspp->xin_id = prop_value[SSPP_XIN][i];
+		sblk->danger_lut_linear = prop_value[SSPP_DANGER][i];
+		sblk->safe_lut_linear = prop_value[SSPP_SAFE][i];
+		sblk->src_blk.len = prop_value[SSPP_SIZE][0];
+	}
+
+end:
+	return rc;
+}
+
+static int sde_ctl_parse_dt(struct device_node *np,
+		struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MAX_BLOCKS], i;
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { {0} };
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
+				= { { { 0 } } };
+	struct sde_ctl_cfg *ctl;
+	u32 off_count;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument input param\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, ctl_prop, ARRAY_SIZE(ctl_prop), prop_count,
+		&off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->ctl_count = off_count;
+
+	rc = _read_dt_entry(np, ctl_prop, ARRAY_SIZE(ctl_prop), prop_count,
+		prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		ctl = sde_cfg->ctl + i;
+		ctl->base = prop_value[HW_OFF][i];
+		ctl->id = CTL_0 + i;
+
+		if (i < MAX_SPLIT_DISPLAY_CTL)
+			set_bit(SDE_CTL_SPLIT_DISPLAY, &ctl->features);
+		if (i < MAX_PP_SPLIT_DISPLAY_CTL)
+			set_bit(SDE_CTL_PINGPONG_SPLIT, &ctl->features);
+	}
+
+end:
+	return rc;
+}
+
+static int sde_mixer_parse_dt(struct device_node *np,
+						struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MAX_BLOCKS], i;
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
+				= { { { 0 } } };
+
+	u32 off_count, max_blendstages;
+	u32 blend_reg_base[] = {0x20, 0x50, 0x80, 0xb0, 0x230, 0x260, 0x290};
+	u32 lm_pair_mask[] = {LM_1, LM_0, LM_5, 0x0, 0x0, LM_2};
+	struct sde_lm_cfg *mixer;
+	struct sde_lm_sub_blks *sblk;
+	int pp_count, dspp_count;
+	u32 pp_idx, dspp_idx;
 
-	for (i = 0; i < ARRAY_SIZE(cfg_table); i++) {
-		if ((cfg_table[i].major == major) &&
-		(cfg_table[i].minor == minor))
-			return cfg_table[i].cfg_init(step);
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument input param\n");
+		rc = -EINVAL;
+		goto end;
 	}
+	max_blendstages = sde_cfg->max_mixer_blendstages;
+
+	rc = _validate_dt_entry(np, mixer_prop, ARRAY_SIZE(mixer_prop),
+		prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->mixer_count = off_count;
+
+	rc = _read_dt_entry(np, mixer_prop, ARRAY_SIZE(mixer_prop), prop_count,
+		prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	pp_count = sde_cfg->pingpong_count;
+	dspp_count = sde_cfg->dspp_count;
+
+	for (i = 0, pp_idx = 0, dspp_idx = 0; i < off_count; i++) {
+		mixer = sde_cfg->mixer + i;
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		mixer->sblk = sblk;
+
+		mixer->base = prop_value[HW_OFF][i];
+		mixer->len = prop_value[HW_LEN][0];
+		mixer->id = LM_0 + i;
+		if (!mixer->len)
+			mixer->len = DEFAULT_SDE_HW_BLOCK_LEN;
+
+		if (lm_pair_mask[i])
+			mixer->lm_pair_mask = 1 << lm_pair_mask[i];
+
+		sblk->maxblendstages = max_blendstages;
+		sblk->maxwidth = sde_cfg->max_mixer_width;
+		memcpy(sblk->blendstage_base, blend_reg_base, sizeof(u32) *
+			min_t(u32, MAX_BLOCKS, min_t(u32,
+			ARRAY_SIZE(blend_reg_base), max_blendstages)));
+		if (prop_value[SRC_SPLIT][0])
+			set_bit(SDE_MIXER_SOURCESPLIT, &mixer->features);
+		if (prop_value[MIXER_GC][0])
+			set_bit(SDE_MIXER_GC, &mixer->features);
+
+		if ((i < ROT_LM_OFFSET) || (i >= LINE_LM_OFFSET)) {
+			mixer->pingpong = pp_count > 0 ? pp_idx + PINGPONG_0
+								: PINGPONG_MAX;
+			mixer->dspp = dspp_count > 0 ? dspp_idx + DSPP_0
+								: DSPP_MAX;
+			pp_count--;
+			dspp_count--;
+			pp_idx++;
+			dspp_idx++;
+		} else {
+			mixer->pingpong = PINGPONG_MAX;
+			mixer->dspp = DSPP_MAX;
+		}
+	}
+
+end:
+	return rc;
+}
+
+static int sde_intf_parse_dt(struct device_node *np,
+						struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MAX_BLOCKS], i;
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
+					= { { { 0 } } };
+	u32 off_count;
+	u32 dsi_count = 0, none_count = 0, hdmi_count = 0, dp_count = 0;
+	const char *type;
+	struct sde_intf_cfg *intf;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, intf_prop, ARRAY_SIZE(intf_prop),
+		prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->intf_count = off_count;
+
+	rc = _read_dt_entry(np, intf_prop, ARRAY_SIZE(intf_prop), prop_count,
+		prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		intf = sde_cfg->intf + i;
+		intf->base = prop_value[INTF_OFF][i];
+		intf->len = prop_value[INTF_LEN][0];
+		intf->id = INTF_0 + i;
+		if (!intf->len)
+			intf->len = DEFAULT_SDE_HW_BLOCK_LEN;
+
+		intf->prog_fetch_lines_worst_case =
+					prop_value[INTF_PREFETCH][i];
+
+		of_property_read_string_index(np,
+				intf_prop[INTF_TYPE].prop_name, i, &type);
+		if (!strcmp(type, "dsi")) {
+			intf->type = INTF_DSI;
+			intf->controller_id = dsi_count;
+			dsi_count++;
+		} else if (!strcmp(type, "hdmi")) {
+			intf->type = INTF_HDMI;
+			intf->controller_id = hdmi_count;
+			hdmi_count++;
+		} else if (!strcmp(type, "dp")) {
+			intf->type = INTF_DP;
+			intf->controller_id = dp_count;
+			dp_count++;
+		} else {
+			intf->type = INTF_NONE;
+			intf->controller_id = none_count;
+			none_count++;
+		}
+	}
+
+end:
+	return rc;
+}
+
+static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MAX_BLOCKS], i;
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
+					= { { { 0 } } };
+	u32 off_count;
+	struct sde_wb_cfg *wb;
+	struct sde_wb_sub_blocks *sblk;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, wb_prop, ARRAY_SIZE(wb_prop), prop_count,
+		&off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->wb_count = off_count;
+
+	rc = _read_dt_entry(np, wb_prop, ARRAY_SIZE(wb_prop), prop_count,
+		prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		wb = sde_cfg->wb + i;
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		wb->sblk = sblk;
+
+		wb->base = prop_value[WB_OFF][i];
+		wb->id = WB_0 + i;
+		wb->clk_ctrl = SDE_CLK_CTRL_NONE;
+		wb->xin_id = prop_value[WB_XIN_ID][i];
+		wb->vbif_idx = VBIF_NRT;
+		wb->len = prop_value[WB_LEN][0];
+		wb->format_list = wb2_formats;
+		if (!wb->len)
+			wb->len = DEFAULT_SDE_HW_BLOCK_LEN;
+		sblk->maxlinewidth = sde_cfg->max_wb_linewidth;
+
+		if (i >= LINE_MODE_WB_OFFSET)
+			set_bit(SDE_WB_LINE_MODE, &wb->features);
+		else
+			set_bit(SDE_WB_BLOCK_MODE, &wb->features);
+		set_bit(SDE_WB_TRAFFIC_SHAPER, &wb->features);
+		set_bit(SDE_WB_YUV_CONFIG, &wb->features);
+	}
+
+end:
+	return rc;
+}
+
+static int sde_dspp_parse_dt(struct device_node *np,
+						struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MAX_BLOCKS], i;
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
+				= { { { 0 } } };
+	u32 off_count;
+	struct sde_dspp_cfg *dspp;
+	struct sde_dspp_sub_blks *sblk;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, dspp_prop, ARRAY_SIZE(dspp_prop),
+		prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->dspp_count = off_count;
+
+	rc = _read_dt_entry(np, dspp_prop, ARRAY_SIZE(dspp_prop), prop_count,
+		prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		dspp = sde_cfg->dspp + i;
+		dspp->base = prop_value[DSPP_OFF][i];
+		dspp->id = DSPP_0 + i;
+
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		dspp->sblk = sblk;
+
+		sblk->igc.base = prop_value[DSPP_IGC][0];
+		if (sblk->igc.base)
+			set_bit(SDE_DSPP_IGC, &dspp->features);
+
+		sblk->pcc.base = prop_value[DSPP_PCC][0];
+		if (sblk->pcc.base)
+			set_bit(SDE_DSPP_PCC, &dspp->features);
+
+		sblk->gc.base = prop_value[DSPP_GC][0];
+		if (sblk->gc.base)
+			set_bit(SDE_DSPP_GC, &dspp->features);
+
+		sblk->gamut.base = prop_value[DSPP_GAMUT][0];
+		if (sblk->gamut.base)
+			set_bit(SDE_DSPP_GAMUT, &dspp->features);
+
+		sblk->dither.base = prop_value[DSPP_DITHER][0];
+		if (sblk->dither.base)
+			set_bit(SDE_DSPP_DITHER, &dspp->features);
+
+		sblk->hist.base = prop_value[DSPP_HIST][0];
+		if (sblk->hist.base)
+			set_bit(SDE_DSPP_HIST, &dspp->features);
+
+		sblk->ad.base = prop_value[DSPP_AD][i];
+		if (sblk->ad.base)
+			set_bit(SDE_DSPP_AD, &dspp->features);
+	}
+
+end:
+	return rc;
+}
+
+static int sde_cdm_parse_dt(struct device_node *np,
+				struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MAX_BLOCKS], i;
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
+				= { { { 0 } } };
+	u32 off_count;
+	struct sde_cdm_cfg *cdm;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, cdm_prop, ARRAY_SIZE(cdm_prop), prop_count,
+		&off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->cdm_count = off_count;
+
+	rc = _read_dt_entry(np, cdm_prop, ARRAY_SIZE(cdm_prop), prop_count,
+		prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		cdm = sde_cfg->cdm + i;
+		cdm->base = prop_value[HW_OFF][i];
+		cdm->id = CDM_0 + i;
+		cdm->len = prop_value[HW_LEN][0];
+
+		/* intf3 and wb2 for cdm block */
+		cdm->wb_connect = sde_cfg->wb_count ? BIT(WB_2) : BIT(31);
+		cdm->intf_connect = sde_cfg->intf_count ? BIT(INTF_3) : BIT(31);
+	}
+
+end:
+	return rc;
+}
+
+static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MAX_BLOCKS], i;
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
+				= { { { 0 } } };
+	u32 off_count;
+	struct sde_pingpong_cfg *pp;
+	struct sde_pingpong_sub_blks *sblk;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, pp_prop, ARRAY_SIZE(pp_prop), prop_count,
+		&off_count);
+	if (rc)
+		goto end;
+
+	sde_cfg->pingpong_count = off_count;
+
+	rc = _read_dt_entry(np, pp_prop, ARRAY_SIZE(pp_prop), prop_count,
+		prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	for (i = 0; i < off_count; i++) {
+		pp = sde_cfg->pingpong + i;
+		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
+		if (!sblk) {
+			rc = -ENOMEM;
+			/* catalog deinit will release the allocated blocks */
+			goto end;
+		}
+		pp->sblk = sblk;
+
+		pp->base = prop_value[PP_OFF][i];
+		pp->id = PINGPONG_0 + i;
+		pp->len = prop_value[PP_LEN][0];
+
+		sblk->te.base = prop_value[TE_OFF][i];
+		sblk->te.id = SDE_PINGPONG_TE;
+		set_bit(SDE_PINGPONG_TE, &pp->features);
+
+		sblk->te2.base = prop_value[TE2_OFF][i];
+		if (sblk->te2.base) {
+			sblk->te2.id = SDE_PINGPONG_TE2;
+			set_bit(SDE_PINGPONG_TE2, &pp->features);
+			set_bit(SDE_PINGPONG_SPLIT, &pp->features);
+		}
+
+		sblk->dsc.base = prop_value[DSC_OFF][i];
+		if (sblk->dsc.base) {
+			sblk->dsc.id = SDE_PINGPONG_DSC;
+			set_bit(SDE_PINGPONG_DSC, &pp->features);
+		}
+	}
+
+end:
+	return rc;
+}
+
+static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
+{
+	int rc, len, prop_count[MAX_BLOCKS];
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { {0} };
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
+			= { { { 0 } } };
+	const char *type;
+
+	if (!cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count,
+		&len);
+	if (rc)
+		goto end;
+
+	rc = _read_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count,
+		prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	cfg->mdss_count = 1;
+	cfg->mdss[0].base = MDSS_BASE_OFFSET;
+	cfg->mdss[0].id = MDP_TOP;
+
+	cfg->mdp_count = 1;
+	cfg->mdp[0].id = MDP_TOP;
+	cfg->mdp[0].base = prop_value[SDE_OFF][0];
+	cfg->mdp[0].len = prop_value[SDE_LEN][0];
+	if (!cfg->mdp[0].len)
+		cfg->mdp[0].len = DEFAULT_SDE_HW_BLOCK_LEN;
+
+	cfg->max_sspp_linewidth = prop_value[SSPP_LINEWIDTH][0];
+	if (!cfg->max_sspp_linewidth)
+		cfg->max_sspp_linewidth = DEFAULT_SDE_LINE_WIDTH;
+
+	cfg->max_mixer_width = prop_value[MIXER_LINEWIDTH][0];
+	if (!cfg->max_mixer_width)
+		cfg->max_mixer_width = DEFAULT_SDE_LINE_WIDTH;
+
+	cfg->max_mixer_blendstages = prop_value[MIXER_BLEND][0];
+	if (!cfg->max_mixer_blendstages)
+		cfg->max_mixer_blendstages = DEFAULT_SDE_MIXER_BLENDSTAGES;
+
+	cfg->max_wb_linewidth = prop_value[WB_LINEWIDTH][0];
+	if (!cfg->max_wb_linewidth)
+		cfg->max_wb_linewidth = DEFAULT_SDE_LINE_WIDTH;
+
+	cfg->mdp[0].highest_bank_bit = prop_value[BANK_BIT][0];
+	if (!cfg->mdp[0].highest_bank_bit)
+		cfg->mdp[0].highest_bank_bit = DEFAULT_SDE_HIGHEST_BANK_BIT;
+
+	rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);
+	if (!rc && !strcmp(type, "qseedv3"))
+		cfg->qseed_type = SDE_SSPP_SCALER_QSEED3;
+	else if (!rc && !strcmp(type, "qseedv2"))
+		cfg->qseed_type = SDE_SSPP_SCALER_QSEED2;
+
+end:
+	return rc;
+}
+
+void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg)
+{
+	int i;
+
+	if (!sde_cfg)
+		return;
+
+	for (i = 0; i < sde_cfg->sspp_count; i++)
+		kfree(sde_cfg->sspp[i].sblk);
+
+	for (i = 0; i < sde_cfg->mixer_count; i++)
+		kfree(sde_cfg->mixer[i].sblk);
+
+	for (i = 0; i < sde_cfg->wb_count; i++)
+		kfree(sde_cfg->wb[i].sblk);
+
+	for (i = 0; i < sde_cfg->dspp_count; i++)
+		kfree(sde_cfg->dspp[i].sblk);
+
+	for (i = 0; i < sde_cfg->pingpong_count; i++)
+		kfree(sde_cfg->pingpong[i].sblk);
+}
+
+/*************************************************************
+ * hardware catalog init
+ *************************************************************/
+struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev)
+{
+	int rc;
+	struct sde_mdss_cfg *sde_cfg;
+	struct device_node *np = dev->dev->of_node;
+
+	sde_cfg = kzalloc(sizeof(*sde_cfg), GFP_KERNEL);
+	if (!sde_cfg)
+		return ERR_PTR(-ENOMEM);
+
+	sde_cfg->hwversion = hw_rev;
+
+	rc = sde_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_ctl_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_sspp_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_dspp_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_pp_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	/* mixer parsing should be done after dspp and pp for mapping setup */
+	rc = sde_mixer_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_intf_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	rc = sde_wb_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	/* cdm parsing should be done after intf and wb for mapping setup */
+	rc = sde_cdm_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
+	return sde_cfg;
 
-	return ERR_PTR(-ENODEV);
+end:
+	sde_hw_catalog_deinit(sde_cfg);
+	kfree(sde_cfg);
+	return NULL;
 }
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index a8d4f203461d..de559f1b2579 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -17,9 +17,14 @@
 #include <linux/bug.h>
 #include <linux/bitmap.h>
 #include <linux/err.h>
+#include <drm/drmP.h>
 
-#define MAX_BLOCKS    8
-#define MAX_LAYERS    12
+/**
+ * Max hardware block count: For ex: max 12 SSPP pipes or
+ * 5 ctl paths. In all cases, it can have max 12 hardware blocks
+ * based on current design
+ */
+#define MAX_BLOCKS    12
 
 #define SDE_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28)    |\
 		((MINOR & 0xFFF) << 16)  |\
@@ -225,11 +230,13 @@ enum {
  * MACRO SDE_HW_BLK_INFO - information of HW blocks inside SDE
  * @id:                enum identifying this block
  * @base:              register base offset to mdss
+ * @len:               length of hardware block
  * @features           bit mask identifying sub-blocks/features
  */
 #define SDE_HW_BLK_INFO \
 	u32 id; \
 	u32 base; \
+	u32 len; \
 	unsigned long features; \
 
 /**
@@ -588,10 +595,25 @@ struct sde_vbif_cfg {
  * This is the main catalog data structure representing
  * this HW version. Contains number of instances,
  * register offsets, capabilities of the all MDSS HW sub-blocks.
+ *
+ * @max_sspp_linewidth max source pipe line width support.
+ * @max_mixer_width    max layer mixer line width support.
+ * @max_mixer_blendstages max layer mixer blend stages or
+ *                       supported z order
+ * @max_wb_linewidth   max writeback line width support.
+ * @highest_bank_bit   highest memory bit setting for tile buffers.
+ * @qseed_type         qseed2 or qseed3 support.
  */
 struct sde_mdss_cfg {
 	u32 hwversion;
 
+	u32 max_sspp_linewidth;
+	u32 max_mixer_width;
+	u32 max_mixer_blendstages;
+	u32 max_wb_linewidth;
+	u32 highest_bank_bit;
+	u32 qseed_type;
+
 	u32 mdss_count;
 	struct sde_mdss_base_cfg mdss[MAX_BLOCKS];
 
@@ -602,7 +624,7 @@ struct sde_mdss_cfg {
 	struct sde_ctl_cfg ctl[MAX_BLOCKS];
 
 	u32 sspp_count;
-	struct sde_sspp_cfg sspp[MAX_LAYERS];
+	struct sde_sspp_cfg sspp[MAX_BLOCKS];
 
 	u32 mixer_count;
 	struct sde_lm_cfg mixer[MAX_BLOCKS];
@@ -650,7 +672,14 @@ struct sde_mdss_hw_cfg_handler {
 #define BLK_WB(s) ((s)->wb)
 #define BLK_AD(s) ((s)->ad)
 
-struct sde_mdss_cfg *sde_mdss_cfg_170_init(u32 step);
-struct sde_mdss_cfg *sde_hw_catalog_init(u32 major, u32 minor, u32 step);
+/**
+ * sde_hw_catalog_init() - sde hardware catalog init API parses dtsi property
+ * and stores all parsed offset, hardware capabilities in config structure.
+ * @dev:          drm device node.
+ * @hw_rev:       caller needs provide the hardware revision before parsing.
+ *
+ * Return: parsed sde config structure
+ */
+struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev);
 
 #endif /* _SDE_HW_CATALOG_H */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c
deleted file mode 100644
index d32c280fb073..000000000000
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c
+++ /dev/null
@@ -1,669 +0,0 @@
-/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "sde_hw_catalog.h"
-#include "sde_hw_mdss.h"
-#include "sde_hwio.h"
-
-/* VIG layer capability */
-#define VIG_17X_MASK \
-	(BIT(SDE_SSPP_SRC) | BIT(SDE_SSPP_SCALER_QSEED2) |\
-	BIT(SDE_SSPP_CSC) | BIT(SDE_SSPP_HSIC) |\
-	BIT(SDE_SSPP_PCC) | BIT(SDE_SSPP_IGC) |\
-	BIT(SDE_SSPP_MEMCOLOR) | BIT(SDE_SSPP_QOS))
-
-/* RGB layer capability */
-#define RGB_17X_MASK \
-	(BIT(SDE_SSPP_SRC) | BIT(SDE_SSPP_SCALER_RGB) |\
-	BIT(SDE_SSPP_PCC) | BIT(SDE_SSPP_IGC) | BIT(SDE_SSPP_QOS))
-
-/* DMA layer capability */
-#define DMA_17X_MASK \
-	(BIT(SDE_SSPP_SRC) | BIT(SDE_SSPP_PCC) | BIT(SDE_SSPP_IGC) |\
-	BIT(SDE_SSPP_QOS))
-
-/* Cursor layer capability */
-#define CURSOR_17X_MASK  (BIT(SDE_SSPP_SRC) | BIT(SDE_SSPP_CURSOR))
-
-#define MIXER_17X_MASK (BIT(SDE_MIXER_SOURCESPLIT) |\
-	BIT(SDE_MIXER_GC))
-
-#define DSPP_17X_MASK \
-	(BIT(SDE_DSPP_IGC) | BIT(SDE_DSPP_PCC) |\
-	BIT(SDE_DSPP_GC) | BIT(SDE_DSPP_HSIC) | BIT(SDE_DSPP_GAMUT) |\
-	BIT(SDE_DSPP_DITHER) | BIT(SDE_DSPP_HIST) | BIT(SDE_DSPP_MEMCOLOR) |\
-	BIT(SDE_DSPP_SIXZONE) | BIT(SDE_DSPP_AD) | BIT(SDE_DSPP_VLUT))
-
-#define PINGPONG_17X_MASK \
-	(BIT(SDE_PINGPONG_TE) | BIT(SDE_PINGPONG_DSC))
-
-#define PINGPONG_17X_SPLIT_MASK \
-	(PINGPONG_17X_MASK | BIT(SDE_PINGPONG_SPLIT) |\
-	BIT(SDE_PINGPONG_TE2))
-
-#define WB01_17X_MASK \
-	(BIT(SDE_WB_LINE_MODE) | BIT(SDE_WB_BLOCK_MODE) |\
-	BIT(SDE_WB_CSC) | BIT(SDE_WB_CHROMA_DOWN) | BIT(SDE_WB_DOWNSCALE) |\
-	BIT(SDE_WB_DITHER) | BIT(SDE_WB_TRAFFIC_SHAPER) |\
-	BIT(SDE_WB_UBWC_1_0) | BIT(SDE_WB_YUV_CONFIG))
-
-#define WB2_17X_MASK \
-	(BIT(SDE_WB_LINE_MODE) | BIT(SDE_WB_TRAFFIC_SHAPER) |\
-	BIT(SDE_WB_YUV_CONFIG))
-
-#define DECIMATION_17X_MAX_H	4
-#define DECIMATION_17X_MAX_V	4
-
-#define RES_1080p		((u64)(1088*1920))
-#define RES_UHD			((u64)(3840*2160))
-
-static const struct sde_format_extended plane_formats[] = {
-	{DRM_FORMAT_ARGB8888, 0},
-	{DRM_FORMAT_ABGR8888, 0},
-	{DRM_FORMAT_RGBA8888, 0},
-	{DRM_FORMAT_RGBA8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_BGRA8888, 0},
-	{DRM_FORMAT_XRGB8888, 0},
-	{DRM_FORMAT_RGBX8888, 0},
-	{DRM_FORMAT_RGBX8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_RGB888, 0},
-	{DRM_FORMAT_BGR888, 0},
-	{DRM_FORMAT_RGB565, 0},
-	{DRM_FORMAT_RGB565, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_BGR565, 0},
-	{DRM_FORMAT_ARGB1555, 0},
-	{DRM_FORMAT_ABGR1555, 0},
-	{DRM_FORMAT_RGBA5551, 0},
-	{DRM_FORMAT_BGRA5551, 0},
-	{DRM_FORMAT_XRGB1555, 0},
-	{DRM_FORMAT_XBGR1555, 0},
-	{DRM_FORMAT_RGBX5551, 0},
-	{DRM_FORMAT_BGRX5551, 0},
-	{DRM_FORMAT_ARGB4444, 0},
-	{DRM_FORMAT_ABGR4444, 0},
-	{DRM_FORMAT_RGBA4444, 0},
-	{DRM_FORMAT_BGRA4444, 0},
-	{DRM_FORMAT_XRGB4444, 0},
-	{DRM_FORMAT_XBGR4444, 0},
-	{DRM_FORMAT_RGBX4444, 0},
-	{DRM_FORMAT_BGRX4444, 0},
-	{0, 0},
-};
-
-static const struct sde_format_extended plane_formats_yuv[] = {
-	{DRM_FORMAT_ARGB8888, 0},
-	{DRM_FORMAT_ABGR8888, 0},
-	{DRM_FORMAT_RGBA8888, 0},
-	{DRM_FORMAT_RGBA8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_BGRA8888, 0},
-	{DRM_FORMAT_XRGB8888, 0},
-	{DRM_FORMAT_RGBX8888, 0},
-	{DRM_FORMAT_RGBX8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_RGB888, 0},
-	{DRM_FORMAT_BGR888, 0},
-	{DRM_FORMAT_RGB565, 0},
-	{DRM_FORMAT_RGB565, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_BGR565, 0},
-	{DRM_FORMAT_ARGB1555, 0},
-	{DRM_FORMAT_ABGR1555, 0},
-	{DRM_FORMAT_RGBA5551, 0},
-	{DRM_FORMAT_BGRA5551, 0},
-	{DRM_FORMAT_XRGB1555, 0},
-	{DRM_FORMAT_XBGR1555, 0},
-	{DRM_FORMAT_RGBX5551, 0},
-	{DRM_FORMAT_BGRX5551, 0},
-	{DRM_FORMAT_ARGB4444, 0},
-	{DRM_FORMAT_ABGR4444, 0},
-	{DRM_FORMAT_RGBA4444, 0},
-	{DRM_FORMAT_BGRA4444, 0},
-	{DRM_FORMAT_XRGB4444, 0},
-	{DRM_FORMAT_XBGR4444, 0},
-	{DRM_FORMAT_RGBX4444, 0},
-	{DRM_FORMAT_BGRX4444, 0},
-
-	{DRM_FORMAT_NV12, 0},
-	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_NV21, 0},
-	{DRM_FORMAT_NV16, 0},
-	{DRM_FORMAT_NV61, 0},
-	{DRM_FORMAT_VYUY, 0},
-	{DRM_FORMAT_UYVY, 0},
-	{DRM_FORMAT_YUYV, 0},
-	{DRM_FORMAT_YVYU, 0},
-	{DRM_FORMAT_YUV420, 0},
-	{DRM_FORMAT_YVU420, 0},
-	{0, 0},
-};
-
-static const struct sde_format_extended wb0_formats[] = {
-	{DRM_FORMAT_RGB565, 0},
-	{DRM_FORMAT_RGB888, 0},
-	{DRM_FORMAT_ARGB8888, 0},
-	{DRM_FORMAT_RGBA8888, 0},
-	{DRM_FORMAT_XRGB8888, 0},
-	{DRM_FORMAT_RGBX8888, 0},
-	{DRM_FORMAT_ARGB1555, 0},
-	{DRM_FORMAT_RGBA5551, 0},
-	{DRM_FORMAT_XRGB1555, 0},
-	{DRM_FORMAT_RGBX5551, 0},
-	{DRM_FORMAT_ARGB4444, 0},
-	{DRM_FORMAT_RGBA4444, 0},
-	{DRM_FORMAT_RGBX4444, 0},
-	{DRM_FORMAT_XRGB4444, 0},
-
-	{DRM_FORMAT_BGR565, 0},
-	{DRM_FORMAT_BGR888, 0},
-	{DRM_FORMAT_ABGR8888, 0},
-	{DRM_FORMAT_BGRA8888, 0},
-	{DRM_FORMAT_BGRX8888, 0},
-	{DRM_FORMAT_ABGR1555, 0},
-	{DRM_FORMAT_BGRA5551, 0},
-	{DRM_FORMAT_XBGR1555, 0},
-	{DRM_FORMAT_BGRX5551, 0},
-	{DRM_FORMAT_ABGR4444, 0},
-	{DRM_FORMAT_BGRA4444, 0},
-	{DRM_FORMAT_BGRX4444, 0},
-	{DRM_FORMAT_XBGR4444, 0},
-
-	{DRM_FORMAT_RGBX8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_RGBA8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_RGB565, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-
-	{DRM_FORMAT_YUV420, 0},
-	{DRM_FORMAT_NV12, 0},
-	{DRM_FORMAT_NV16, 0},
-	{DRM_FORMAT_YUYV, 0},
-
-	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-	{DRM_FORMAT_AYUV, DRM_FORMAT_MOD_QCOM_COMPRESSED},
-
-	{0, 0},
-};
-
-static const struct sde_format_extended wb2_formats[] = {
-	{DRM_FORMAT_RGB565, 0},
-	{DRM_FORMAT_RGB888, 0},
-	{DRM_FORMAT_ARGB8888, 0},
-	{DRM_FORMAT_RGBA8888, 0},
-	{DRM_FORMAT_XRGB8888, 0},
-	{DRM_FORMAT_RGBX8888, 0},
-	{DRM_FORMAT_ARGB1555, 0},
-	{DRM_FORMAT_RGBA5551, 0},
-	{DRM_FORMAT_XRGB1555, 0},
-	{DRM_FORMAT_RGBX5551, 0},
-	{DRM_FORMAT_ARGB4444, 0},
-	{DRM_FORMAT_RGBA4444, 0},
-	{DRM_FORMAT_RGBX4444, 0},
-	{DRM_FORMAT_XRGB4444, 0},
-
-	{DRM_FORMAT_BGR565, 0},
-	{DRM_FORMAT_BGR888, 0},
-	{DRM_FORMAT_ABGR8888, 0},
-	{DRM_FORMAT_BGRA8888, 0},
-	{DRM_FORMAT_BGRX8888, 0},
-	{DRM_FORMAT_ABGR1555, 0},
-	{DRM_FORMAT_BGRA5551, 0},
-	{DRM_FORMAT_XBGR1555, 0},
-	{DRM_FORMAT_BGRX5551, 0},
-	{DRM_FORMAT_ABGR4444, 0},
-	{DRM_FORMAT_BGRA4444, 0},
-	{DRM_FORMAT_BGRX4444, 0},
-	{DRM_FORMAT_XBGR4444, 0},
-
-	{DRM_FORMAT_YUV420, 0},
-	{DRM_FORMAT_NV12, 0},
-	{DRM_FORMAT_NV16, 0},
-	{DRM_FORMAT_YUYV, 0},
-
-	{0, 0},
-};
-
-/**
- * set_cfg_1xx_init(): populate sde sub-blocks reg offsets and instance counts
- */
-static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg)
-{
-
-	/* Layer capability */
-	static const struct sde_sspp_sub_blks vig_layer = {
-		.maxlinewidth = 2560,
-		.danger_lut_linear = 0x000f,
-		.safe_lut_linear = 0xfffc,
-		.danger_lut_tile = 0xffff,
-		.safe_lut_tile = 0xff00,
-		.danger_lut_nrt = 0x0,
-		.safe_lut_nrt = 0xffff,
-		.creq_lut_nrt = 0x0,
-		.creq_vblank = 0x2,
-		.danger_vblank = 0,
-		.pixel_ram_size = 50 * 1024,
-		.maxdwnscale = 4, .maxupscale = 20,
-		.maxhdeciexp = DECIMATION_17X_MAX_H,
-		.maxvdeciexp = DECIMATION_17X_MAX_V,
-		.src_blk = {.id = SDE_SSPP_SRC,
-			.base = 0x00, .len = 0x150,},
-		.scaler_blk = {.id = SDE_SSPP_SCALER_QSEED2,
-			.base = 0x200, .len = 0x70,},
-		.csc_blk = {.id = SDE_SSPP_CSC,
-			.base = 0x320, .len = 0x44,},
-		.format_list = plane_formats_yuv,
-		.igc_blk = {.id = SDE_SSPP_IGC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.pcc_blk = {.id = SDE_SSPP_PCC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.hsic = {.id = SDE_SSPP_HSIC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.memcolor = {.id = SDE_SSPP_MEMCOLOR, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-	};
-
-	static const struct sde_sspp_sub_blks layer = {
-		.maxlinewidth = 2560,
-		.danger_lut_linear = 0x000f,
-		.safe_lut_linear = 0xfffc,
-		.danger_lut_tile = 0xffff,
-		.safe_lut_tile = 0xff00,
-		.danger_lut_nrt = 0x0,
-		.safe_lut_nrt = 0xffff,
-		.creq_lut_nrt = 0x0,
-		.creq_vblank = 0x2,
-		.danger_vblank = 0,
-		.pixel_ram_size = 50 * 1024,
-		.maxdwnscale = 4, .maxupscale = 20,
-		.maxhdeciexp = DECIMATION_17X_MAX_H,
-		.maxvdeciexp = DECIMATION_17X_MAX_V,
-		.src_blk = {.id = SDE_SSPP_SRC,
-			.base = 0x00, .len = 0x150,},
-		.scaler_blk = {.id = SDE_SSPP_SCALER_QSEED2,
-			.base = 0x200, .len = 0x70,},
-		.csc_blk = {.id = SDE_SSPP_CSC,
-			.base = 0x320, .len = 0x44,},
-		.format_list = plane_formats,
-		.igc_blk = {.id = SDE_SSPP_IGC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.pcc_blk = {.id = SDE_SSPP_PCC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-	};
-
-	static const struct sde_sspp_sub_blks dma = {
-		.maxlinewidth = 2560,
-		.danger_lut_linear = 0x000f,
-		.safe_lut_linear = 0xfffc,
-		.danger_lut_tile = 0xffff,
-		.safe_lut_tile = 0xff00,
-		.danger_lut_nrt = 0x0,
-		.safe_lut_nrt = 0xffff,
-		.creq_lut_nrt = 0x0,
-		.creq_vblank = 0x2,
-		.danger_vblank = 0,
-		.pixel_ram_size = 50 * 1024,
-		.maxdwnscale = 1, .maxupscale = 1,
-		.maxhdeciexp = DECIMATION_17X_MAX_H,
-		.maxvdeciexp = DECIMATION_17X_MAX_V,
-		.src_blk = {.id = SDE_SSPP_SRC, .base = 0x00, .len = 0x150,},
-		.scaler_blk = {.id = 0, .base = 0x00, .len = 0x0,},
-		.csc_blk = {.id = 0, .base = 0x00, .len = 0x0,},
-		.format_list = plane_formats,
-		.igc_blk = {.id = SDE_SSPP_IGC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.pcc_blk = {.id = SDE_SSPP_PCC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-	};
-
-	static const struct sde_sspp_sub_blks cursor = {
-		.maxlinewidth = 128,
-		.maxdwnscale = 1, .maxupscale = 1,
-		.maxhdeciexp = 0,
-		.maxvdeciexp = 0,
-		.src_blk = {.id = SDE_SSPP_SRC, .base = 0x00, .len = 0x150,},
-		.scaler_blk = {.id = 0, .base = 0x00, .len = 0x0,},
-		.csc_blk = {.id = 0, .base = 0x00, .len = 0x0,},
-		.format_list = plane_formats,
-	};
-
-	/* MIXER capability */
-	static const struct sde_lm_sub_blks lm = {
-		.maxwidth = 2560,
-		.maxblendstages = 7, /* excluding base layer */
-		.blendstage_base = { /* offsets relative to mixer base */
-			0x20, 0x50, 0x80, 0xB0, 0x230, 0x260, 0x290 },
-		.gc = {.id = SDE_DSPP_GC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-	};
-
-	/* DSPP capability */
-	static const struct sde_dspp_sub_blks dspp = {
-		.igc = {.id = SDE_DSPP_IGC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.pcc = {.id = SDE_DSPP_PCC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.gamut = {.id = SDE_DSPP_GAMUT, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.dither = {.id = SDE_DSPP_DITHER, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.hsic = {.id = SDE_DSPP_HSIC, .base = 0x00, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.memcolor = {.id = SDE_DSPP_MEMCOLOR, .base = 0x00, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.sixzone = {.id = SDE_DSPP_SIXZONE, .base = 0x00, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.hist = {.id = SDE_DSPP_HIST, .base = 0x00, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.gc = {.id = SDE_DSPP_GC, .base = 0x0, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-		.ad = {.id = SDE_DSPP_AD, .base = 0x00, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x3, 0x0)},
-		.vlut = {.id = SDE_DSPP_VLUT, .base = 0x1400, .len = 0x0,
-			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},
-	};
-
-	/* PINGPONG capability */
-	static const struct sde_pingpong_sub_blks pingpong = {
-		.te = {.id = SDE_PINGPONG_TE, .base = 0x0000, .len = 0x0,
-			.version = 0x1},
-		.te2 = {.id = SDE_PINGPONG_TE2, .base = 0x2000, .len = 0x0,
-			.version = 0x1},
-		.dsc = {.id = SDE_PINGPONG_DSC, .base = 0x10000, .len = 0x0,
-			.version = 0x1},
-	};
-
-	/* Writeback 0/1 capability */
-	static const struct sde_wb_sub_blocks wb0 = {
-		.maxlinewidth = 2048,
-	};
-
-	/* Writeback 2 capability */
-	static const struct sde_wb_sub_blocks wb2 = {
-		.maxlinewidth = 4096,
-	};
-
-	static const struct sde_vbif_dynamic_ot_cfg dynamic_ot_cfg[] = {
-		{RES_1080p * 30, 2},
-		{RES_1080p * 60, 4},
-		{RES_UHD * 30, 16},
-	};
-
-	/* Setup Register maps and defaults */
-	*cfg = (struct sde_mdss_cfg){
-		.mdss_count = 1,
-		.mdss = {
-			{.id = MDP_TOP, .base = 0x00000000, .features = 0}
-		},
-		.mdp_count = 1,
-		.mdp = {
-			{.id = MDP_TOP, .base = 0x00001000, .features = 0,
-				.highest_bank_bit = 0x2,
-				.clk_ctrls[SDE_CLK_CTRL_VIG0] = {
-					.reg_off = 0x2AC, .bit_off = 0},
-				.clk_ctrls[SDE_CLK_CTRL_VIG1] = {
-					.reg_off = 0x2B4, .bit_off = 0},
-				.clk_ctrls[SDE_CLK_CTRL_VIG2] = {
-					.reg_off = 0x2BC, .bit_off = 0},
-				.clk_ctrls[SDE_CLK_CTRL_VIG3] = {
-					.reg_off = 0x2C4, .bit_off = 0},
-				.clk_ctrls[SDE_CLK_CTRL_RGB0] = {
-					.reg_off = 0x2AC, .bit_off = 4},
-				.clk_ctrls[SDE_CLK_CTRL_RGB1] = {
-					.reg_off = 0x2B4, .bit_off = 4},
-				.clk_ctrls[SDE_CLK_CTRL_RGB2] = {
-					.reg_off = 0x2BC, .bit_off = 4},
-				.clk_ctrls[SDE_CLK_CTRL_RGB3] = {
-					.reg_off = 0x2C4, .bit_off = 4},
-				.clk_ctrls[SDE_CLK_CTRL_DMA0] = {
-					.reg_off = 0x2AC, .bit_off = 8},
-				.clk_ctrls[SDE_CLK_CTRL_DMA1] = {
-					.reg_off = 0x2B4, .bit_off = 8},
-				.clk_ctrls[SDE_CLK_CTRL_CURSOR0] = {
-					.reg_off = 0x3A8, .bit_off = 16},
-				.clk_ctrls[SDE_CLK_CTRL_CURSOR1] = {
-					.reg_off = 0x3B0, .bit_off = 16},
-				.clk_ctrls[SDE_CLK_CTRL_WB0] = {
-					.reg_off = 0x2BC, .bit_off = 8},
-				.clk_ctrls[SDE_CLK_CTRL_WB1] = {
-					.reg_off = 0x2BC, .bit_off = 12},
-				.clk_ctrls[SDE_CLK_CTRL_WB2] = {
-					.reg_off = 0x2BC, .bit_off = 16},
-			},
-		},
-		.ctl_count = 5,
-		.ctl = {
-			{.id = CTL_0,
-				.base = 0x00002000,
-				.features = BIT(SDE_CTL_SPLIT_DISPLAY) |
-					BIT(SDE_CTL_PINGPONG_SPLIT) },
-			{.id = CTL_1,
-				.base = 0x00002200,
-				.features = BIT(SDE_CTL_SPLIT_DISPLAY) },
-			{.id = CTL_2,
-				.base = 0x00002400},
-			{.id = CTL_3,
-				.base = 0x00002600},
-			{.id = CTL_4,
-				.base = 0x00002800},
-		},
-			/* 4 VIG, + 4 RGB + 2 DMA + 2 CURSOR */
-		.sspp_count = 12,
-		.sspp = {
-			{.id = SSPP_VIG0, .base = 0x00005000,
-			.features = VIG_17X_MASK, .sblk = &vig_layer,
-			.xin_id = 0,
-			.clk_ctrl = SDE_CLK_CTRL_VIG0},
-			{.id = SSPP_VIG1, .base = 0x00007000,
-			.features = VIG_17X_MASK, .sblk = &vig_layer,
-			.xin_id = 4,
-			.clk_ctrl = SDE_CLK_CTRL_VIG1},
-			{.id = SSPP_VIG2, .base = 0x00009000,
-			.features = VIG_17X_MASK, .sblk = &vig_layer,
-			.xin_id = 8,
-			.clk_ctrl = SDE_CLK_CTRL_VIG2},
-			{.id = SSPP_VIG3, .base = 0x0000b000,
-			.features = VIG_17X_MASK, .sblk = &vig_layer,
-			.xin_id = 12,
-			.clk_ctrl = SDE_CLK_CTRL_VIG3},
-
-			{.id = SSPP_RGB0, .base = 0x00015000,
-			.features = RGB_17X_MASK, .sblk = &layer,
-			.xin_id = 1,
-			.clk_ctrl = SDE_CLK_CTRL_RGB0},
-			{.id = SSPP_RGB1, .base = 0x00017000,
-			.features = RGB_17X_MASK, .sblk = &layer,
-			.xin_id = 5,
-			.clk_ctrl = SDE_CLK_CTRL_RGB1},
-			{.id = SSPP_RGB2, .base = 0x00019000,
-			.features = RGB_17X_MASK, .sblk = &layer,
-			.xin_id = 9,
-			.clk_ctrl = SDE_CLK_CTRL_RGB2},
-			{.id = SSPP_RGB3, .base = 0x0001B000,
-			.features = RGB_17X_MASK, .sblk = &layer,
-			.xin_id = 13,
-			.clk_ctrl = SDE_CLK_CTRL_RGB3},
-
-			{.id = SSPP_DMA0, .base = 0x00025000,
-			.features = DMA_17X_MASK, .sblk = &dma,
-			.xin_id = 2,
-			.clk_ctrl = SDE_CLK_CTRL_DMA0},
-			{.id = SSPP_DMA1, .base = 0x00027000,
-			.features = DMA_17X_MASK, .sblk = &dma,
-			.xin_id = 10,
-			.clk_ctrl = SDE_CLK_CTRL_DMA1},
-
-			{.id = SSPP_CURSOR0, .base = 0x00035000,
-			.features = CURSOR_17X_MASK, .sblk = &cursor,
-			.xin_id = 7,
-			.clk_ctrl = SDE_CLK_CTRL_CURSOR0},
-			{.id = SSPP_CURSOR1, .base = 0x00037000,
-			.features = CURSOR_17X_MASK, .sblk = &cursor,
-			.xin_id = 7,
-			.clk_ctrl = SDE_CLK_CTRL_CURSOR1},
-		},
-		.mixer_count = 6,
-		.mixer = {
-			{.id = LM_0, .base = 0x00045000,
-				.features = MIXER_17X_MASK,
-				.sblk = &lm,
-				.dspp = DSPP_0,
-				.pingpong = PINGPONG_0,
-				.lm_pair_mask = (1 << LM_1) },
-			{.id = LM_1, .base = 0x00046000,
-				.features = MIXER_17X_MASK,
-				.sblk = &lm,
-				.dspp = DSPP_1,
-				.pingpong = PINGPONG_1,
-				.lm_pair_mask = (1 << LM_0) },
-			{.id = LM_2, .base = 0x00047000,
-				.features = MIXER_17X_MASK,
-				.sblk = &lm,
-				.dspp = DSPP_MAX,
-				.pingpong = PINGPONG_2,
-				.lm_pair_mask = (1 << LM_5) },
-			{.id = LM_3, .base = 0x00048000,
-				.features = MIXER_17X_MASK,
-				.sblk = &lm,
-				.dspp = DSPP_MAX,
-				.pingpong = PINGPONG_MAX},
-			{.id = LM_4, .base = 0x00049000,
-				.features = MIXER_17X_MASK,
-				.sblk = &lm,
-				.dspp = DSPP_MAX,
-				.pingpong = PINGPONG_MAX},
-			{.id = LM_5, .base = 0x0004a000,
-				.features = MIXER_17X_MASK,
-				.sblk = &lm,
-				.dspp = DSPP_MAX,
-				.pingpong = PINGPONG_3,
-				.lm_pair_mask = (1 << LM_2) },
-		},
-		.dspp_count = 2,
-		.dspp = {
-			{.id = DSPP_0, .base = 0x00055000,
-			.features = DSPP_17X_MASK,
-				.sblk = &dspp},
-			{.id = DSPP_1, .base = 0x00057000,
-			.features = DSPP_17X_MASK,
-				.sblk = &dspp},
-		},
-		.pingpong_count = 4,
-		.pingpong = {
-			{.id = PINGPONG_0, .base = 0x00071000,
-				.features = PINGPONG_17X_SPLIT_MASK,
-				.sblk = &pingpong},
-			{.id = PINGPONG_1, .base = 0x00071800,
-				.features = PINGPONG_17X_SPLIT_MASK,
-				.sblk = &pingpong},
-			{.id = PINGPONG_2, .base = 0x00072000,
-				.features = PINGPONG_17X_MASK,
-				.sblk = &pingpong},
-			{.id = PINGPONG_3, .base = 0x00072800,
-				.features = PINGPONG_17X_MASK,
-				.sblk = &pingpong},
-		},
-		.cdm_count = 1,
-		.cdm = {
-			{.id = CDM_0, .base = 0x0007A200, .features = 0,
-				.intf_connect = BIT(INTF_3),
-				.wb_connect = BIT(WB_2),}
-		},
-		.intf_count = 4,
-		.intf = {
-			{.id = INTF_0, .base = 0x0006B000,
-				.type = INTF_NONE, .controller_id = 0,
-				.prog_fetch_lines_worst_case = 21},
-			{.id = INTF_1, .base = 0x0006B800,
-				.type = INTF_DSI, .controller_id = 0,
-				.prog_fetch_lines_worst_case = 21},
-			{.id = INTF_2, .base = 0x0006C000,
-				.type = INTF_DSI, .controller_id = 1,
-				.prog_fetch_lines_worst_case = 21},
-			{.id = INTF_3, .base = 0x0006C800,
-				.type = INTF_HDMI, .controller_id = 0,
-				.prog_fetch_lines_worst_case = 21},
-		},
-		.wb_count = 3,
-		.wb = {
-			{.id = WB_0, .base = 0x00065000,
-				.features = WB01_17X_MASK,
-				.sblk = &wb0,
-				.format_list = wb0_formats,
-				.vbif_idx = VBIF_NRT,
-				.xin_id = 3,
-				.clk_ctrl = SDE_CLK_CTRL_WB0},
-			{.id = WB_1, .base = 0x00065800,
-				.features = WB01_17X_MASK,
-				.sblk = &wb0,
-				.format_list = wb0_formats,
-				.vbif_idx = VBIF_NRT,
-				.xin_id = 11,
-				.clk_ctrl = SDE_CLK_CTRL_WB1},
-			{.id = WB_2, .base = 0x00066000,
-				.features = WB2_17X_MASK,
-				.sblk = &wb2,
-				.format_list = wb2_formats,
-				.vbif_idx = VBIF_NRT,
-				.xin_id = 6,
-				.clk_ctrl = SDE_CLK_CTRL_WB2},
-		},
-		.vbif_count = 2,
-		.vbif = {
-			{.id = VBIF_0,
-				.base = 0, /* 0x000B0000 */
-				.features = BIT(SDE_VBIF_QOS_OTLIM),
-				.default_ot_rd_limit = 32,
-				.default_ot_wr_limit = 16,
-				.xin_halt_timeout = 0x4000,
-				.dynamic_ot_rd_tbl = {
-					.count = ARRAY_SIZE(dynamic_ot_cfg),
-					.cfg = dynamic_ot_cfg},
-				.dynamic_ot_wr_tbl = {
-					.count = ARRAY_SIZE(dynamic_ot_cfg),
-					.cfg = dynamic_ot_cfg},
-			},
-			{.id = VBIF_1,
-				.base = 0, /* 0x000B8000 */
-				.features = BIT(SDE_VBIF_QOS_OTLIM),
-				.default_ot_rd_limit = 32,
-				.default_ot_wr_limit = 16,
-				.xin_halt_timeout = 0x4000,
-				.dynamic_ot_rd_tbl = {
-					.count = ARRAY_SIZE(dynamic_ot_cfg),
-					.cfg = dynamic_ot_cfg},
-				.dynamic_ot_wr_tbl = {
-					.count = ARRAY_SIZE(dynamic_ot_cfg),
-					.cfg = dynamic_ot_cfg},
-			},
-		},
-	};
-	return 0;
-}
-
-/**
- * sde_mdp_cfg_170_init(): Populate the sde sub-blocks catalog information
- */
-struct sde_mdss_cfg *sde_mdss_cfg_170_init(u32 step)
-{
-	struct sde_mdss_cfg *m = NULL;
-
-	/*
-	 * This function, for each sub-block sets,
-	 * instance count, IO regions,
-	 * default capabilities and this version capabilities,
-	 * Additional catalog items
-	 */
-
-	m = kzalloc(sizeof(*m), GFP_KERNEL);
-	if (!m)
-		return NULL;
-
-	set_cfg_1xx_init(m);
-	m->hwversion = SDE_HW_VER(1, 7, step);
-
-	return m;
-}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog_format.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog_format.h
new file mode 100644
index 000000000000..9be1b04b2876
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog_format.h
@@ -0,0 +1,129 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_hw_mdss.h"
+
+static const struct sde_format_extended plane_formats[] = {
+	{DRM_FORMAT_ARGB8888, 0},
+	{DRM_FORMAT_ABGR8888, 0},
+	{DRM_FORMAT_RGBA8888, 0},
+	{DRM_FORMAT_RGBA8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_BGRA8888, 0},
+	{DRM_FORMAT_XRGB8888, 0},
+	{DRM_FORMAT_RGBX8888, 0},
+	{DRM_FORMAT_RGBX8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_RGB888, 0},
+	{DRM_FORMAT_BGR888, 0},
+	{DRM_FORMAT_RGB565, 0},
+	{DRM_FORMAT_RGB565, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_BGR565, 0},
+	{DRM_FORMAT_ARGB1555, 0},
+	{DRM_FORMAT_ABGR1555, 0},
+	{DRM_FORMAT_RGBA5551, 0},
+	{DRM_FORMAT_BGRA5551, 0},
+	{DRM_FORMAT_XRGB1555, 0},
+	{DRM_FORMAT_XBGR1555, 0},
+	{DRM_FORMAT_RGBX5551, 0},
+	{DRM_FORMAT_BGRX5551, 0},
+	{DRM_FORMAT_ARGB4444, 0},
+	{DRM_FORMAT_ABGR4444, 0},
+	{DRM_FORMAT_RGBA4444, 0},
+	{DRM_FORMAT_BGRA4444, 0},
+	{DRM_FORMAT_XRGB4444, 0},
+	{DRM_FORMAT_XBGR4444, 0},
+	{DRM_FORMAT_RGBX4444, 0},
+	{DRM_FORMAT_BGRX4444, 0},
+	{0, 0},
+};
+
+static const struct sde_format_extended plane_formats_yuv[] = {
+	{DRM_FORMAT_ARGB8888, 0},
+	{DRM_FORMAT_ABGR8888, 0},
+	{DRM_FORMAT_RGBA8888, 0},
+	{DRM_FORMAT_RGBA8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_BGRA8888, 0},
+	{DRM_FORMAT_XRGB8888, 0},
+	{DRM_FORMAT_RGBX8888, 0},
+	{DRM_FORMAT_RGBX8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_RGB888, 0},
+	{DRM_FORMAT_BGR888, 0},
+	{DRM_FORMAT_RGB565, 0},
+	{DRM_FORMAT_RGB565, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_BGR565, 0},
+	{DRM_FORMAT_ARGB1555, 0},
+	{DRM_FORMAT_ABGR1555, 0},
+	{DRM_FORMAT_RGBA5551, 0},
+	{DRM_FORMAT_BGRA5551, 0},
+	{DRM_FORMAT_XRGB1555, 0},
+	{DRM_FORMAT_XBGR1555, 0},
+	{DRM_FORMAT_RGBX5551, 0},
+	{DRM_FORMAT_BGRX5551, 0},
+	{DRM_FORMAT_ARGB4444, 0},
+	{DRM_FORMAT_ABGR4444, 0},
+	{DRM_FORMAT_RGBA4444, 0},
+	{DRM_FORMAT_BGRA4444, 0},
+	{DRM_FORMAT_XRGB4444, 0},
+	{DRM_FORMAT_XBGR4444, 0},
+	{DRM_FORMAT_RGBX4444, 0},
+	{DRM_FORMAT_BGRX4444, 0},
+
+	{DRM_FORMAT_NV12, 0},
+	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED},
+	{DRM_FORMAT_NV21, 0},
+	{DRM_FORMAT_NV16, 0},
+	{DRM_FORMAT_NV61, 0},
+	{DRM_FORMAT_VYUY, 0},
+	{DRM_FORMAT_UYVY, 0},
+	{DRM_FORMAT_YUYV, 0},
+	{DRM_FORMAT_YVYU, 0},
+	{DRM_FORMAT_YUV420, 0},
+	{DRM_FORMAT_YVU420, 0},
+	{0, 0},
+};
+
+static const struct sde_format_extended wb2_formats[] = {
+	{DRM_FORMAT_RGB565, 0},
+	{DRM_FORMAT_RGB888, 0},
+	{DRM_FORMAT_ARGB8888, 0},
+	{DRM_FORMAT_RGBA8888, 0},
+	{DRM_FORMAT_XRGB8888, 0},
+	{DRM_FORMAT_RGBX8888, 0},
+	{DRM_FORMAT_ARGB1555, 0},
+	{DRM_FORMAT_RGBA5551, 0},
+	{DRM_FORMAT_XRGB1555, 0},
+	{DRM_FORMAT_RGBX5551, 0},
+	{DRM_FORMAT_ARGB4444, 0},
+	{DRM_FORMAT_RGBA4444, 0},
+	{DRM_FORMAT_RGBX4444, 0},
+	{DRM_FORMAT_XRGB4444, 0},
+
+	{DRM_FORMAT_BGR565, 0},
+	{DRM_FORMAT_BGR888, 0},
+	{DRM_FORMAT_ABGR8888, 0},
+	{DRM_FORMAT_BGRA8888, 0},
+	{DRM_FORMAT_BGRX8888, 0},
+	{DRM_FORMAT_ABGR1555, 0},
+	{DRM_FORMAT_BGRA5551, 0},
+	{DRM_FORMAT_XBGR1555, 0},
+	{DRM_FORMAT_BGRX5551, 0},
+	{DRM_FORMAT_ABGR4444, 0},
+	{DRM_FORMAT_BGRA4444, 0},
+	{DRM_FORMAT_BGRX4444, 0},
+	{DRM_FORMAT_XBGR4444, 0},
+
+	{DRM_FORMAT_YUV420, 0},
+	{DRM_FORMAT_NV12, 0},
+	{DRM_FORMAT_NV16, 0},
+	{DRM_FORMAT_YUYV, 0},
+
+	{0, 0},
+};
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
index f4ed48ee5a61..f89d577990cd 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
@@ -178,6 +178,7 @@ enum sde_intf_type {
 	INTF_HDMI = 0x3,
 	INTF_LCDC = 0x5,
 	INTF_EDP = 0x9,
+	INTF_DP = 0xa,
 	INTF_TYPE_MAX,
 
 	/* virtual interfaces */
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
index 24bae465ef5f..033b23088fb3 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -760,9 +760,7 @@ struct msm_kms *sde_kms_init(struct drm_device *dev)
 
 	core_hw_rev_init(sde_kms);
 
-	sde_kms->catalog = sde_hw_catalog_init(GET_MAJOR_REV(sde_kms->core_rev),
-			GET_MINOR_REV(sde_kms->core_rev),
-			GET_STEP_REV(sde_kms->core_rev));
+	sde_kms->catalog = sde_hw_catalog_init(dev, sde_kms->core_rev);
 	if (IS_ERR_OR_NULL(sde_kms->catalog)) {
 		SDE_ERROR("catalog init failed\n");
 		rc = PTR_ERR(sde_kms->catalog);
-- 
cgit v1.2.3


From 8e3226a2fa93a42eac91227c0f95ff5f55b1cfc3 Mon Sep 17 00:00:00 2001
From: Alan Kwong <akwong@codeaurora.org>
Date: Wed, 12 Oct 2016 16:44:00 -0400
Subject: drm/msm/sde: add writeback id parsing to hardware catalog

Writeback identifier is used to mapped clock control register
for each writeback device. Add writeback identifier parsing to
hardware catalog.

Change-Id: I666072f657dfeb30c6818f3dd25729e891c579ad
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
---
 Documentation/devicetree/bindings/display/msm/sde.txt | 4 ++++
 drivers/gpu/drm/msm/sde/sde_hw_catalog.c              | 8 +++++---
 2 files changed, 9 insertions(+), 3 deletions(-)

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 0092c503464b..141d79222f67 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -174,6 +174,8 @@ Optional properties:
 - qcom,sde-dspp-hist-off:	A u32 offset indicates the hist block offset on dssp.
 - qcom,sde-dspp-ad-off:		A u32 offset indicates the ad block offset on dssp.
 
+- qcom,sde-wb-id:		Array of writeback ids corresponding to the
+				offsets defined in property: qcom,sde-wb-off.
 Bus Scaling Data:
 - qcom,msm-bus,name:		String property describing client name.
 - qcom,msm-bus,num-cases:	This is the number of Bus Scaling use cases
@@ -314,6 +316,8 @@ Example:
     qcom,sde-dspp-hist-off = <0x100>;
     qcom,sde-dspp-ad-off = <0x100>;
 
+    qcom,sde-wb-id = <2>;
+
     qcom,platform-supply-entries {
        #address-cells = <1>;
        #size-cells = <0>;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index fb75c2a59835..ec7c02b2ec6d 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -145,6 +145,7 @@ enum {
 enum {
 	WB_OFF,
 	WB_LEN,
+	WB_ID,
 	WB_XIN_ID,
 };
 
@@ -259,6 +260,7 @@ static struct sde_prop_type intf_prop[] = {
 static struct sde_prop_type wb_prop[] = {
 	{WB_OFF, "qcom,sde-wb-off", true, PROP_TYPE_U32_ARRAY},
 	{WB_LEN, "qcom,sde-wb-size", false, PROP_TYPE_U32},
+	{WB_ID, "qcom,sde-wb-id", true, PROP_TYPE_U32_ARRAY},
 	{WB_XIN_ID, "qcom,sde-wb-xin-id", false, PROP_TYPE_U32_ARRAY},
 };
 
@@ -833,8 +835,8 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 		wb->sblk = sblk;
 
 		wb->base = prop_value[WB_OFF][i];
-		wb->id = WB_0 + i;
-		wb->clk_ctrl = SDE_CLK_CTRL_NONE;
+		wb->id = WB_0 + prop_value[WB_ID][i];
+		wb->clk_ctrl = SDE_CLK_CTRL_WB0 + prop_value[WB_ID][i];
 		wb->xin_id = prop_value[WB_XIN_ID][i];
 		wb->vbif_idx = VBIF_NRT;
 		wb->len = prop_value[WB_LEN][0];
@@ -843,7 +845,7 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 			wb->len = DEFAULT_SDE_HW_BLOCK_LEN;
 		sblk->maxlinewidth = sde_cfg->max_wb_linewidth;
 
-		if (i >= LINE_MODE_WB_OFFSET)
+		if (wb->id >= LINE_MODE_WB_OFFSET)
 			set_bit(SDE_WB_LINE_MODE, &wb->features);
 		else
 			set_bit(SDE_WB_BLOCK_MODE, &wb->features);
-- 
cgit v1.2.3


From 3e418c7ba48ccb1f4be79216ceb7dd009d44ea65 Mon Sep 17 00:00:00 2001
From: Alan Kwong <akwong@codeaurora.org>
Date: Wed, 12 Oct 2016 00:27:07 -0400
Subject: drm/msm/sde: add vbif parsing to hardware catalog

Add vbif parsing to hardware catalog. Default and dynamic
OT limits are defined for each vbif block.

Change-Id: I12336c2f390b5acd2aeec691e1176d814b1cb768
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt        |  26 +++-
 drivers/gpu/drm/msm/sde/sde_hw_catalog.c           | 158 +++++++++++++++++++++
 drivers/gpu/drm/msm/sde/sde_hw_catalog.h           |   2 +-
 3 files changed, 184 insertions(+), 2 deletions(-)

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 141d79222f67..3854f0e1ce5c 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -159,6 +159,10 @@ Optional properties:
 - qcom,sde-cdm-off:	 	Array of offset addresses for the available
 				cdm blocks. These offsets will be calculated from
 				register "mdp_phys" defined in reg property.
+- qcom,sde-vbif-off:		Array of offset addresses for the available
+				vbif blocks. These offsets will be calculated from
+				register "vbif_phys" defined in reg property.
+- qcom,sde-vbif-size:		A u32 value indicates the vbif block address range.
 - qcom,sde-te-off:		A u32 offset indicates the te block offset on pingpong.
 				This offset is 0x0 by default.
 - qcom,sde-te2-off:		A u32 offset indicates the te2 block offset on pingpong.
@@ -173,7 +177,18 @@ Optional properties:
 - qcom,sde-dspp-dither-off:	A u32 offset indicates the dither block offset on dssp.
 - qcom,sde-dspp-hist-off:	A u32 offset indicates the hist block offset on dssp.
 - qcom,sde-dspp-ad-off:		A u32 offset indicates the ad block offset on dssp.
-
+- qcom,sde-vbif-id:		Array of vbif ids corresponding to the
+				offsets defined in property: qcom,sde-vbif-off.
+- qcom,sde-vbif-default-ot-rd-limit:	A u32 value indicates the default read OT limit
+- qcom,sde-vbif-default-ot-wr-limit:	A u32 value indicates the default write OT limit
+- qcom,sde-vbif-dynamic-ot-rd-limit:	A series of 2 cell property, with a format
+				of (pps, OT limit), where pps is pixel per second and
+				OT limit is the read limit to apply if the given
+				pps is not exceeded.
+- qcom,sde-vbif-dynamic-ot-wr-limit:	A series of 2 cell property, with a format
+				of (pps, OT limit), where pps is pixel per second and
+				OT limit is the write limit to apply if the given
+				pps is not exceeded.
 - qcom,sde-wb-id:		Array of writeback ids corresponding to the
 				offsets defined in property: qcom,sde-wb-off.
 Bus Scaling Data:
@@ -318,6 +333,15 @@ Example:
 
     qcom,sde-wb-id = <2>;
 
+    qcom,sde-vbif-off = <0 0>;
+    qcom,sde-vbif-id = <0 1>;
+    qcom,sde-vbif-default-ot-rd-limit = <32>;
+    qcom,sde-vbif-default-ot-wr-limit = <16>;
+    qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>,
+        <124416000 4>, <248832000 16>;
+    qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>,
+        <124416000 4>, <248832000 16>;
+
     qcom,platform-supply-entries {
        #address-cells = <1>;
        #size-cells = <0>;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index ec7c02b2ec6d..f438a2e591df 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -68,6 +68,9 @@
 #define LINE_LM_OFFSET			5
 #define LINE_MODE_WB_OFFSET		2
 
+/* maximum XIN halt timeout in usec */
+#define VBIF_XIN_HALT_TIMEOUT		0x4000
+
 /*************************************************************
  *  DTSI PROPERTY INDEX
  *************************************************************/
@@ -149,6 +152,16 @@ enum {
 	WB_XIN_ID,
 };
 
+enum {
+	VBIF_OFF,
+	VBIF_LEN,
+	VBIF_ID,
+	VBIF_DEFAULT_OT_RD_LIMIT,
+	VBIF_DEFAULT_OT_WR_LIMIT,
+	VBIF_DYNAMIC_OT_RD_LIMIT,
+	VBIF_DYNAMIC_OT_WR_LIMIT,
+};
+
 /*************************************************************
  * dts property definition
  *************************************************************/
@@ -264,6 +277,20 @@ static struct sde_prop_type wb_prop[] = {
 	{WB_XIN_ID, "qcom,sde-wb-xin-id", false, PROP_TYPE_U32_ARRAY},
 };
 
+static struct sde_prop_type vbif_prop[] = {
+	{VBIF_OFF, "qcom,sde-vbif-off", true, PROP_TYPE_U32_ARRAY},
+	{VBIF_LEN, "qcom,sde-vbif-size", false, PROP_TYPE_U32},
+	{VBIF_ID, "qcom,sde-vbif-id", false, PROP_TYPE_U32_ARRAY},
+	{VBIF_DEFAULT_OT_RD_LIMIT, "qcom,sde-vbif-default-ot-rd-limit", false,
+		PROP_TYPE_U32},
+	{VBIF_DEFAULT_OT_WR_LIMIT, "qcom,sde-vbif-default-ot-wr-limit", false,
+		PROP_TYPE_U32},
+	{VBIF_DYNAMIC_OT_RD_LIMIT, "qcom,sde-vbif-dynamic-ot-rd-limit", false,
+		PROP_TYPE_U32_ARRAY},
+	{VBIF_DYNAMIC_OT_WR_LIMIT, "qcom,sde-vbif-dynamic-ot-wr-limit", false,
+		PROP_TYPE_U32_ARRAY},
+};
+
 /*************************************************************
  * static API list
  *************************************************************/
@@ -975,6 +1002,128 @@ end:
 	return rc;
 }
 
+static int sde_vbif_parse_dt(struct device_node *np,
+				struct sde_mdss_cfg *sde_cfg)
+{
+	int rc, prop_count[MAX_BLOCKS], i, j, k;
+	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
+				= { { { 0 } } };
+	u32 off_count, vbif_len, rd_len = 0, wr_len = 0;
+	struct sde_vbif_cfg *vbif;
+
+	if (!sde_cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, vbif_prop, ARRAY_SIZE(vbif_prop),
+			prop_count, &off_count);
+	if (rc)
+		goto end;
+
+	rc = _validate_dt_entry(np, &vbif_prop[VBIF_DYNAMIC_OT_RD_LIMIT], 1,
+			&prop_count[VBIF_DYNAMIC_OT_RD_LIMIT], &rd_len);
+	if (rc)
+		goto end;
+
+	rc = _validate_dt_entry(np, &vbif_prop[VBIF_DYNAMIC_OT_WR_LIMIT], 1,
+			&prop_count[VBIF_DYNAMIC_OT_WR_LIMIT], &wr_len);
+	if (rc)
+		goto end;
+
+	sde_cfg->vbif_count = off_count;
+
+	rc = _read_dt_entry(np, vbif_prop, ARRAY_SIZE(vbif_prop), prop_count,
+		prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	vbif_len = prop_value[VBIF_LEN][0];
+	if (!vbif_len)
+		vbif_len = DEFAULT_SDE_HW_BLOCK_LEN;
+
+	for (i = 0; i < off_count; i++) {
+		vbif = sde_cfg->vbif + i;
+		vbif->base = prop_value[VBIF_OFF][i];
+		vbif->len = vbif_len;
+		vbif->id = VBIF_0 + prop_value[VBIF_ID][i];
+
+		SDE_DEBUG("vbif:%d\n", vbif->id - VBIF_0);
+
+		vbif->xin_halt_timeout = VBIF_XIN_HALT_TIMEOUT;
+
+		vbif->default_ot_rd_limit =
+				prop_value[VBIF_DEFAULT_OT_RD_LIMIT][0];
+		SDE_DEBUG("default_ot_rd_limit=%u\n",
+				vbif->default_ot_rd_limit);
+
+		vbif->default_ot_wr_limit =
+				prop_value[VBIF_DEFAULT_OT_WR_LIMIT][0];
+		SDE_DEBUG("default_ot_wr_limit=%u\n",
+				vbif->default_ot_wr_limit);
+
+		vbif->dynamic_ot_rd_tbl.count =
+				prop_count[VBIF_DYNAMIC_OT_RD_LIMIT] / 2;
+		SDE_DEBUG("dynamic_ot_rd_tbl.count=%u\n",
+				vbif->dynamic_ot_rd_tbl.count);
+		if (vbif->dynamic_ot_rd_tbl.count) {
+			vbif->dynamic_ot_rd_tbl.cfg = kcalloc(
+				vbif->dynamic_ot_rd_tbl.count,
+				sizeof(struct sde_vbif_dynamic_ot_cfg),
+				GFP_KERNEL);
+			if (!vbif->dynamic_ot_rd_tbl.cfg) {
+				rc = -ENOMEM;
+				goto end;
+			}
+		}
+
+		for (j = 0, k = 0; j < vbif->dynamic_ot_rd_tbl.count; j++) {
+			vbif->dynamic_ot_rd_tbl.cfg[j].pps = (u64)
+				prop_value[VBIF_DYNAMIC_OT_RD_LIMIT][k++];
+			vbif->dynamic_ot_rd_tbl.cfg[j].ot_limit =
+				prop_value[VBIF_DYNAMIC_OT_RD_LIMIT][k++];
+			SDE_DEBUG("dynamic_ot_rd_tbl[%d].cfg=<%llu %u>\n", j,
+				vbif->dynamic_ot_rd_tbl.cfg[j].pps,
+				vbif->dynamic_ot_rd_tbl.cfg[j].ot_limit);
+		}
+
+		vbif->dynamic_ot_wr_tbl.count =
+				prop_count[VBIF_DYNAMIC_OT_WR_LIMIT] / 2;
+		SDE_DEBUG("dynamic_ot_wr_tbl.count=%u\n",
+				vbif->dynamic_ot_wr_tbl.count);
+		if (vbif->dynamic_ot_wr_tbl.count) {
+			vbif->dynamic_ot_wr_tbl.cfg = kcalloc(
+				vbif->dynamic_ot_wr_tbl.count,
+				sizeof(struct sde_vbif_dynamic_ot_cfg),
+				GFP_KERNEL);
+			if (!vbif->dynamic_ot_wr_tbl.cfg) {
+				rc = -ENOMEM;
+				goto end;
+			}
+		}
+
+		for (j = 0, k = 0; j < vbif->dynamic_ot_wr_tbl.count; j++) {
+			vbif->dynamic_ot_wr_tbl.cfg[j].pps = (u64)
+				prop_value[VBIF_DYNAMIC_OT_WR_LIMIT][k++];
+			vbif->dynamic_ot_wr_tbl.cfg[j].ot_limit =
+				prop_value[VBIF_DYNAMIC_OT_WR_LIMIT][k++];
+			SDE_DEBUG("dynamic_ot_wr_tbl[%d].cfg=<%llu %u>\n", j,
+				vbif->dynamic_ot_wr_tbl.cfg[j].pps,
+				vbif->dynamic_ot_wr_tbl.cfg[j].ot_limit);
+		}
+
+		if (vbif->default_ot_rd_limit || vbif->default_ot_wr_limit ||
+				vbif->dynamic_ot_rd_tbl.count ||
+				vbif->dynamic_ot_wr_tbl.count)
+			set_bit(SDE_VBIF_QOS_OTLIM, &vbif->features);
+	}
+
+end:
+	return rc;
+}
+
 static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 {
 	int rc, prop_count[MAX_BLOCKS], i;
@@ -1141,6 +1290,11 @@ static void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg)
 
 	for (i = 0; i < sde_cfg->pingpong_count; i++)
 		kfree(sde_cfg->pingpong[i].sblk);
+
+	for (i = 0; i < sde_cfg->vbif_count; i++) {
+		kfree(sde_cfg->vbif[i].dynamic_ot_rd_tbl.cfg);
+		kfree(sde_cfg->vbif[i].dynamic_ot_wr_tbl.cfg);
+	}
 }
 
 /*************************************************************
@@ -1196,6 +1350,10 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev)
 	if (rc)
 		goto end;
 
+	rc = sde_vbif_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
 	sde_hardware_caps(sde_cfg, hw_rev);
 
 	return sde_cfg;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 6e0a52d2bb71..ee09798b5e57 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -567,7 +567,7 @@ struct sde_vbif_dynamic_ot_cfg {
  */
 struct sde_vbif_dynamic_ot_tbl {
 	u32 count;
-	const struct sde_vbif_dynamic_ot_cfg *cfg;
+	struct sde_vbif_dynamic_ot_cfg *cfg;
 };
 
 /**
-- 
cgit v1.2.3


From 488a0a5aaeb6eb1f74538d7b0b241b84d7c3177c Mon Sep 17 00:00:00 2001
From: Alan Kwong <akwong@codeaurora.org>
Date: Wed, 12 Oct 2016 17:10:11 -0400
Subject: drm/msm/sde: add plane QoS parsing to hardware catalog

Add plane QoS parser to retrieve and parse LUTs for
danger, safe and creq QoS settings.

Change-Id: I42dd045c46966a66f43fd9517a16270c83f89aa1
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt        | 23 ++++---------
 drivers/gpu/drm/msm/sde/sde_hw_catalog.c           | 39 ++++++++++++++++++++--
 2 files changed, 44 insertions(+), 18 deletions(-)

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 3854f0e1ce5c..abc1572f17d2 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -130,14 +130,10 @@ Optional properties:
 				control register. Number of offsets defined should
 				match the number of offsets defined in
 				property: qcom,sde-sspp-off.
-- qcom,sde-sspp-danger-lut:	Array of u32 values indicating the danger luts on each
-				sspp. Number of offsets defined should
-				match the number of offsets defined in
-				property: qcom,sde-sspp-off.
-- qcom,sde-sspp-safe-lut:	Array of u32 values indicating the safe luts on each
-				sspp. Number of offsets defined should
-				match the number of offsets defined in
-				property: qcom,sde-sspp-off.
+- qcom,sde-sspp-danger-lut:	A 3 cell property, with a format of <linear, tile, nrt>,
+				indicating the danger luts on sspp.
+- qcom,sde-sspp-safe-lut:	A 3 cell property, with a format of <linear, tile, nrt>,
+				indicating the safe luts on sspp.
 - qcom,sde-sspp-qseed-off:	A u32 offset value indicates the qseed block offset
 				from sspp base. It will install qseed property on
 				vig and rgb sspp pipes.
@@ -304,14 +300,6 @@ Example:
     qcom,sde-qseed-type = "qseedv2";
     qcom,sde-highest-bank-bit = <15>;
     qcom,sde-has-mixer-gc;
-    qcom,sde-sspp-danger-lut = <0x55 0x55 0x55 0x55
-				0x55 0x55 0x55 0x55
-				0xaa 0xaa
-				0xbb 0xbb>;
-    qcom,sde-sspp-safe-lut = <0x11 0x11 0x11 0x11
-				0x11 0x11 0x11 0x11
-				0xaa 0xaa
-				0xbb 0xbb>;
     qcom,sde-sspp-max-rects = <1 1 1 1
 				1 1 1 1
 				1 1
@@ -333,6 +321,9 @@ Example:
 
     qcom,sde-wb-id = <2>;
 
+    qcom,sde-sspp-danger-lut = <0x000f 0xffff 0x0000>;
+    qcom,sde-sspp-safe-lut = <0xfffc 0xff00 0xffff>;
+
     qcom,sde-vbif-off = <0 0>;
     qcom,sde-vbif-id = <0 1>;
     qcom,sde-vbif-default-ot-rd-limit = <32>;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index f438a2e591df..41b55ca09502 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -71,6 +71,9 @@
 /* maximum XIN halt timeout in usec */
 #define VBIF_XIN_HALT_TIMEOUT		0x4000
 
+#define DEFAULT_CREQ_LUT_NRT		0x0
+#define DEFAULT_PIXEL_RAM_SIZE		(50 * 1024)
+
 /*************************************************************
  *  DTSI PROPERTY INDEX
  *************************************************************/
@@ -506,6 +509,7 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg,
 	sspp->id = SSPP_VIG0 + *vig_count;
 	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
 	sblk->format_list = plane_formats_yuv;
+	set_bit(SDE_SSPP_QOS, &sspp->features);
 	(*vig_count)++;
 }
 
@@ -528,6 +532,7 @@ static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg,
 	sspp->id = SSPP_RGB0 + *rgb_count;
 	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
 	sblk->format_list = plane_formats;
+	set_bit(SDE_SSPP_QOS, &sspp->features);
 	(*rgb_count)++;
 }
 
@@ -553,6 +558,7 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg,
 	sspp->id = SSPP_DMA0 + *dma_count;
 	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
 	sblk->format_list = plane_formats;
+	set_bit(SDE_SSPP_QOS, &sspp->features);
 	(*dma_count)++;
 }
 
@@ -566,12 +572,23 @@ static int sde_sspp_parse_dt(struct device_node *np,
 	struct sde_sspp_cfg *sspp;
 	struct sde_sspp_sub_blks *sblk;
 	u32 vig_count = 0, dma_count = 0, rgb_count = 0, cursor_count = 0;
+	u32 danger_count = 0, safe_count = 0;
 
 	rc = _validate_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop),
 		prop_count, &off_count);
 	if (rc)
 		goto end;
 
+	rc = _validate_dt_entry(np, &sspp_prop[SSPP_DANGER], 1,
+			&prop_count[SSPP_DANGER], &danger_count);
+	if (rc)
+		goto end;
+
+	rc = _validate_dt_entry(np, &sspp_prop[SSPP_SAFE], 1,
+			&prop_count[SSPP_SAFE], &safe_count);
+	if (rc)
+		goto end;
+
 	rc = _read_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop), prop_count,
 							prop_value, bit_value);
 	if (rc)
@@ -619,9 +636,27 @@ static int sde_sspp_parse_dt(struct device_node *np,
 		sblk->maxvdeciexp = MAX_VERT_DECIMATION;
 
 		sspp->xin_id = prop_value[SSPP_XIN][i];
-		sblk->danger_lut_linear = prop_value[SSPP_DANGER][i];
-		sblk->safe_lut_linear = prop_value[SSPP_SAFE][i];
+		sblk->danger_lut_linear = prop_value[SSPP_DANGER][0];
+		sblk->danger_lut_tile = prop_value[SSPP_DANGER][1];
+		sblk->danger_lut_nrt = prop_value[SSPP_DANGER][2];
+		sblk->safe_lut_linear = prop_value[SSPP_SAFE][0];
+		sblk->safe_lut_tile = prop_value[SSPP_SAFE][1];
+		sblk->safe_lut_nrt = prop_value[SSPP_SAFE][2];
+		sblk->creq_lut_nrt = DEFAULT_CREQ_LUT_NRT;
+		sblk->pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE;
 		sblk->src_blk.len = prop_value[SSPP_SIZE][0];
+
+		SDE_DEBUG(
+			"xin:%d danger:%x/%x/%x safe:%x/%x/%x creq:%x ram:%d\n",
+			sspp->xin_id,
+			sblk->danger_lut_linear,
+			sblk->danger_lut_tile,
+			sblk->danger_lut_nrt,
+			sblk->safe_lut_linear,
+			sblk->safe_lut_tile,
+			sblk->safe_lut_nrt,
+			sblk->creq_lut_nrt,
+			sblk->pixel_ram_size);
 	}
 
 end:
-- 
cgit v1.2.3


From f2256cebb6a5d11cbb0eb00f41ec8478c62043cf Mon Sep 17 00:00:00 2001
From: Alan Kwong <akwong@codeaurora.org>
Date: Wed, 12 Oct 2016 16:05:17 -0400
Subject: drm/msm/sde: add clock control parsing to hardware catalog

Add parsing logic to setup plane and writeback control clock
register and bit mask.  Clock control registers are used to
change vbif OT settings.

Change-Id: Ie3baee8c25c2899f14c3d0e87e02dc57d73ce582
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt        |  8 ++++
 drivers/gpu/drm/msm/sde/sde_hw_catalog.c           | 46 ++++++++++++++++++----
 2 files changed, 46 insertions(+), 8 deletions(-)

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index abc1572f17d2..fb32a1d0bc6d 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -187,6 +187,13 @@ Optional properties:
 				pps is not exceeded.
 - qcom,sde-wb-id:		Array of writeback ids corresponding to the
 				offsets defined in property: qcom,sde-wb-off.
+- qcom,sde-wb-clk-ctrl:		Array of 2 cell property describing clk control
+				offsets for dynamic clock gating. 1st value
+				in the array represents offset of the control
+				register. 2nd value represents bit offset within
+				control register. Number of offsets defined should
+				match the number of offsets defined in
+				property: qcom,sde-wb-off
 Bus Scaling Data:
 - qcom,msm-bus,name:		String property describing client name.
 - qcom,msm-bus,num-cases:	This is the number of Bus Scaling use cases
@@ -320,6 +327,7 @@ Example:
     qcom,sde-dspp-ad-off = <0x100>;
 
     qcom,sde-wb-id = <2>;
+    qcom,sde-wb-clk-ctrl = <0x2bc 16>;
 
     qcom,sde-sspp-danger-lut = <0x000f 0xffff 0x0000>;
     qcom,sde-sspp-safe-lut = <0xfffc 0xff00 0xffff>;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index 3ac161f86680..b252b5bd2bce 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -153,6 +153,7 @@ enum {
 	WB_LEN,
 	WB_ID,
 	WB_XIN_ID,
+	WB_CLK_CTRL,
 };
 
 enum {
@@ -278,6 +279,8 @@ static struct sde_prop_type wb_prop[] = {
 	{WB_LEN, "qcom,sde-wb-size", false, PROP_TYPE_U32},
 	{WB_ID, "qcom,sde-wb-id", true, PROP_TYPE_U32_ARRAY},
 	{WB_XIN_ID, "qcom,sde-wb-xin-id", false, PROP_TYPE_U32_ARRAY},
+	{WB_CLK_CTRL, "qcom,sde-wb-clk-ctrl", false,
+		PROP_TYPE_BIT_OFFSET_ARRAY},
 };
 
 static struct sde_prop_type vbif_prop[] = {
@@ -507,7 +510,8 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg,
 	sblk->maxupscale = MAX_SSPP_UPSCALE;
 	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
 	sspp->id = SSPP_VIG0 + *vig_count;
-	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
+	sspp->clk_ctrl = SDE_CLK_CTRL_VIG0 + *vig_count;
+
 	sblk->format_list = plane_formats_yuv;
 	set_bit(SDE_SSPP_QOS, &sspp->features);
 	(*vig_count)++;
@@ -530,7 +534,7 @@ static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg,
 	sblk->maxupscale = MAX_SSPP_UPSCALE;
 	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
 	sspp->id = SSPP_RGB0 + *rgb_count;
-	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
+	sspp->clk_ctrl = SDE_CLK_CTRL_RGB0 + *rgb_count;
 	sblk->format_list = plane_formats;
 	set_bit(SDE_SSPP_QOS, &sspp->features);
 	(*rgb_count)++;
@@ -544,7 +548,7 @@ static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg,
 	sblk->maxupscale = SSPP_UNITY_SCALE;
 	sblk->maxdwnscale = SSPP_UNITY_SCALE;
 	sspp->id = SSPP_CURSOR0 + *cursor_count;
-	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
+	sspp->clk_ctrl = SDE_CLK_CTRL_CURSOR0 + *cursor_count;
 	sblk->format_list = plane_formats;
 	(*cursor_count)++;
 }
@@ -556,7 +560,7 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg,
 	sblk->maxupscale = SSPP_UNITY_SCALE;
 	sblk->maxdwnscale = SSPP_UNITY_SCALE;
 	sspp->id = SSPP_DMA0 + *dma_count;
-	sspp->clk_ctrl = SDE_CLK_CTRL_NONE;
+	sspp->clk_ctrl = SDE_CLK_CTRL_DMA0 + *dma_count;
 	sblk->format_list = plane_formats;
 	set_bit(SDE_SSPP_QOS, &sspp->features);
 	(*dma_count)++;
@@ -565,7 +569,7 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg,
 static int sde_sspp_parse_dt(struct device_node *np,
 	struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], off_count, i;
+	int rc, prop_count[MAX_BLOCKS], off_count, i, j;
 	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK];
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET];
 	const char *type;
@@ -646,8 +650,15 @@ static int sde_sspp_parse_dt(struct device_node *np,
 		sblk->pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE;
 		sblk->src_blk.len = prop_value[SSPP_SIZE][0];
 
+		for (j = 0; j < sde_cfg->mdp_count; j++) {
+			sde_cfg->mdp[j].clk_ctrls[sspp->clk_ctrl].reg_off =
+					bit_value[SSPP_CLK_CTRL][i][0];
+			sde_cfg->mdp[j].clk_ctrls[sspp->clk_ctrl].bit_off =
+					bit_value[SSPP_CLK_CTRL][i][1];
+		}
+
 		SDE_DEBUG(
-			"xin:%d danger:%x/%x/%x safe:%x/%x/%x creq:%x ram:%d\n",
+			"xin:%d danger:%x/%x/%x safe:%x/%x/%x creq:%x ram:%d clk%d:%x/%d\n",
 			sspp->xin_id,
 			sblk->danger_lut_linear,
 			sblk->danger_lut_tile,
@@ -656,7 +667,10 @@ static int sde_sspp_parse_dt(struct device_node *np,
 			sblk->safe_lut_tile,
 			sblk->safe_lut_nrt,
 			sblk->creq_lut_nrt,
-			sblk->pixel_ram_size);
+			sblk->pixel_ram_size,
+			sspp->clk_ctrl,
+			sde_cfg->mdp[0].clk_ctrls[sspp->clk_ctrl].reg_off,
+			sde_cfg->mdp[0].clk_ctrls[sspp->clk_ctrl].bit_off);
 	}
 
 end:
@@ -860,7 +874,7 @@ end:
 
 static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], i;
+	int rc, prop_count[MAX_BLOCKS], i, j;
 	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 					= { { { 0 } } };
@@ -913,6 +927,22 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 			set_bit(SDE_WB_BLOCK_MODE, &wb->features);
 		set_bit(SDE_WB_TRAFFIC_SHAPER, &wb->features);
 		set_bit(SDE_WB_YUV_CONFIG, &wb->features);
+
+		for (j = 0; j < sde_cfg->mdp_count; j++) {
+			sde_cfg->mdp[j].clk_ctrls[wb->clk_ctrl].reg_off =
+					bit_value[WB_CLK_CTRL][i][0];
+			sde_cfg->mdp[j].clk_ctrls[wb->clk_ctrl].bit_off =
+					bit_value[WB_CLK_CTRL][i][1];
+		}
+
+		SDE_DEBUG(
+			"wb:%d xin:%d vbif:%d clk%d:%x/%d\n",
+			wb->id - WB_0,
+			wb->xin_id,
+			wb->vbif_idx,
+			wb->clk_ctrl,
+			sde_cfg->mdp[0].clk_ctrls[wb->clk_ctrl].reg_off,
+			sde_cfg->mdp[0].clk_ctrls[wb->clk_ctrl].bit_off);
 	}
 
 end:
-- 
cgit v1.2.3


From 5f3e9e1142df589f4483efe1fabe2d8901231e36 Mon Sep 17 00:00:00 2001
From: Clarence Ip <cip@codeaurora.org>
Date: Mon, 31 Oct 2016 09:59:44 -0400
Subject: drm/msm/sde: remove display manager

Convert dsi and wb into actual drivers, and don't bind them
from within the display manager any more. With this change,
the display manager is no longer necessary, and may be safely
removed.

Change-Id: Ifac790fe31120d72cf78000a1476e22d000db4ae
Signed-off-by: Clarence Ip <cip@codeaurora.org>
---
 .../devicetree/bindings/drm/msm/sde-dsi.txt        |   1 -
 arch/arm/boot/dts/qcom/msm8996-sde-display.dtsi    | 299 +++++-----
 drivers/gpu/drm/msm/Makefile                       |  46 +-
 .../gpu/drm/msm/display-manager/display_manager.c  | 611 ---------------------
 .../gpu/drm/msm/display-manager/display_manager.h  |  98 ----
 drivers/gpu/drm/msm/dsi-staging/dsi_display.c      | 400 ++++++++------
 drivers/gpu/drm/msm/dsi-staging/dsi_display.h      |  50 +-
 drivers/gpu/drm/msm/msm_drv.c                      |   3 -
 drivers/gpu/drm/msm/msm_drv.h                      |   5 -
 drivers/gpu/drm/msm/sde/sde_encoder.c              |  69 +--
 drivers/gpu/drm/msm/sde/sde_kms.c                  | 223 +++++++-
 drivers/gpu/drm/msm/sde/sde_kms.h                  |  21 +-
 drivers/gpu/drm/msm/sde/sde_wb.c                   |  89 ++-
 drivers/gpu/drm/msm/sde/sde_wb.h                   |  66 +--
 14 files changed, 725 insertions(+), 1256 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/display-manager/display_manager.c
 delete mode 100644 drivers/gpu/drm/msm/display-manager/display_manager.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
index 6be533257bab..ea35d1450f0b 100644
--- a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
@@ -62,7 +62,6 @@ Optional properties:
 - qcom,dsi-phy: handle to dsi phy device
 - qcom,dsi-manager:       Specifies dsi manager is present
 - qcom,dsi-display:       Specifies dsi display is present
-- qcom,display-manager:   Specifies display manager is present
 - qcom,hdmi-display:      Specifies hdmi is present
 - qcom,dp-display:        Specified dp is present
 - qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the
diff --git a/arch/arm/boot/dts/qcom/msm8996-sde-display.dtsi b/arch/arm/boot/dts/qcom/msm8996-sde-display.dtsi
index 05be00c7fd97..4b2446c3b8f7 100644
--- a/arch/arm/boot/dts/qcom/msm8996-sde-display.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-sde-display.dtsi
@@ -103,171 +103,168 @@
 		};
 	};
 
-	display_manager: qcom,display-manager {
-		compatible = "qcom,display-manager";
-
-		dsi_dual_sharp_video_1: qcom,dsi-display@0 {
-			compatible = "qcom,dsi-display";
-			label = "dsi_dual_sharp_video";
-			qcom,display-type = "primary";
-
-			qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
-			qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
-			clocks = <&clock_mmss clk_ext_byte0_clk_src>,
-				 <&clock_mmss clk_ext_pclk0_clk_src>;
-			clock-names = "src_byte_clk", "src_pixel_clk";
-
-			pinctrl-names = "panel_active", "panel_suspend";
-			pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
-			pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
-			qcom,platform-te-gpio = <&tlmm 10 0>;
-			qcom,platform-reset-gpio = <&tlmm 8 0>;
-
-			qcom,dsi-panel = <&dsi_dual_sharp_video>;
-			vddio-supply = <&pm8994_l14>;
-			lab-supply = <&lab_regulator>;
-			ibb-supply = <&ibb_regulator>;
-			qcom,dsi-display-active;
-		};
+	dsi_dual_sharp_video_1: qcom,dsi-display@0 {
+		compatible = "qcom,dsi-display";
+		label = "dsi_dual_sharp_video";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+		qcom,platform-reset-gpio = <&tlmm 8 0>;
+
+		qcom,dsi-panel = <&dsi_dual_sharp_video>;
+		vddio-supply = <&pm8994_l14>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
+		qcom,dsi-display-active;
+	};
 
-		single_dsi_sim_vid: qcom,dsi-display@1 {
-			compatible = "qcom,dsi-display";
-			label = "single_dsi_sim";
-			qcom,display-type = "primary";
-
-			qcom,dsi-ctrl = <&mdss_dsi0>;
-			qcom,dsi-phy = <&mdss_dsi_phy0>;
-			clocks = <&clock_mmss clk_ext_byte0_clk_src>,
-				 <&clock_mmss clk_ext_pclk0_clk_src>;
-			clock-names = "src_byte_clk", "src_pixel_clk";
-
-			pinctrl-names = "panel_active", "panel_suspend";
-			pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
-			pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
-			qcom,platform-te-gpio = <&tlmm 10 0>;
-
-			qcom,dsi-panel = <&dsi_sim_vid>;
-			vddio-supply = <&pm8994_l14>;
-			lab-supply = <&lab_regulator>;
-			ibb-supply = <&ibb_regulator>;
-		};
+	single_dsi_sim_vid: qcom,dsi-display@1 {
+		compatible = "qcom,dsi-display";
+		label = "single_dsi_sim";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+
+		qcom,dsi-panel = <&dsi_sim_vid>;
+		vddio-supply = <&pm8994_l14>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
+	};
 
-		dsi_toshiba_720p_vid: qcom,dsi-display@2 {
-			compatible = "qcom,dsi-display";
-			label = "single_dsi_toshiba_720p";
-			qcom,display-type = "primary";
-
-			qcom,dsi-ctrl = <&mdss_dsi0>;
-			qcom,dsi-phy = <&mdss_dsi_phy0>;
-			clocks = <&clock_mmss clk_ext_byte0_clk_src>,
-				 <&clock_mmss clk_ext_pclk0_clk_src>;
-			clock-names = "src_byte_clk", "src_pixel_clk";
-
-			pinctrl-names = "panel_active", "panel_suspend";
-			pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
-			pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
-			qcom,platform-te-gpio = <&tlmm 10 0>;
-
-			qcom,dsi-panel = <&dsi_tosh_720_vid>;
-			vddio-supply = <&pm8994_l14>;
-			vdd-supply = <&pm8994_l19>;
-		};
+	dsi_toshiba_720p_vid: qcom,dsi-display@2 {
+		compatible = "qcom,dsi-display";
+		label = "single_dsi_toshiba_720p";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+
+		qcom,dsi-panel = <&dsi_tosh_720_vid>;
+		vddio-supply = <&pm8994_l14>;
+		vdd-supply = <&pm8994_l19>;
+	};
 
-		dsi_jdi_1080p_vid: qcom,dsi-display@3 {
-			compatible = "qcom,dsi-display";
-			label = "single_dsi_jdi_1080p";
-			qcom,display-type = "primary";
+	dsi_jdi_1080p_vid: qcom,dsi-display@3 {
+		compatible = "qcom,dsi-display";
+		label = "single_dsi_jdi_1080p";
+		qcom,display-type = "primary";
 
-			qcom,dsi-ctrl = <&mdss_dsi0>;
-			qcom,dsi-phy = <&mdss_dsi_phy0>;
-			clocks = <&clock_mmss clk_ext_byte0_clk_src>,
-				 <&clock_mmss clk_ext_pclk0_clk_src>;
-			clock-names = "src_byte_clk", "src_pixel_clk";
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
 
-			pinctrl-names = "panel_active", "panel_suspend";
-			pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
-			pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
 
-			qcom,dsi-panel = <&dsi_jdi_1080p_video>;
-			vddio-supply = <&pm8994_l14>;
-		};
+		qcom,dsi-panel = <&dsi_jdi_1080p_video>;
+		vddio-supply = <&pm8994_l14>;
+	};
 
-		dsi_sharp_fhd_cmd: qcom,dsi-display@4 {
-			compatible = "qcom,dsi-display";
-			label = "single_dsi_sharp_1080p";
-			qcom,display-type = "primary";
-
-			qcom,dsi-ctrl = <&mdss_dsi0>;
-			qcom,dsi-phy = <&mdss_dsi_phy0>;
-			clocks = <&clock_mmss clk_ext_byte0_clk_src>,
-				 <&clock_mmss clk_ext_pclk0_clk_src>;
-			clock-names = "src_byte_clk", "src_pixel_clk";
-
-			pinctrl-names = "panel_active", "panel_suspend";
-			pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
-			pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
-
-			qcom,dsi-panel = <&dsi_sharp_1080_cmd>;
-			vddio-supply = <&pm8994_l14>;
-			vdd-supply = <&pm8994_l19>;
-			lab-supply = <&lab_regulator>;
-			ibb-supply = <&ibb_regulator>;
-		};
+	dsi_sharp_fhd_cmd: qcom,dsi-display@4 {
+		compatible = "qcom,dsi-display";
+		label = "single_dsi_sharp_1080p";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+
+		qcom,dsi-panel = <&dsi_sharp_1080_cmd>;
+		vddio-supply = <&pm8994_l14>;
+		vdd-supply = <&pm8994_l19>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
+	};
 
-		sde_wb: qcom,wb-display@0 {
-			compatible = "qcom,wb-display";
-			cell-index = <0>;
-			label = "wb_display";
-		};
+	sde_wb: qcom,wb-display@0 {
+		compatible = "qcom,wb-display";
+		cell-index = <0>;
+		label = "wb_display";
+	};
 
-		dsi_dual_nt35597_cmd_1: qcom,dsi-display@5 {
-			compatible = "qcom,dsi-display";
-			label = "dsi_dual_nt35597_cmd";
-			qcom,display-type = "primary";
-
-			qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
-			qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
-			clocks = <&clock_mmss clk_ext_byte0_clk_src>,
-				 <&clock_mmss clk_ext_pclk0_clk_src>;
-			clock-names = "src_byte_clk", "src_pixel_clk";
-
-			pinctrl-names = "panel_active", "panel_suspend";
-			pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
-			pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
-			qcom,platform-te-gpio = <&tlmm 10 0>;
-
-			qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
-			vddio-supply = <&pm8994_l14>;
-			lab-supply = <&lab_regulator>;
-			ibb-supply = <&ibb_regulator>;
-		};
+	dsi_dual_nt35597_cmd_1: qcom,dsi-display@5 {
+		compatible = "qcom,dsi-display";
+		label = "dsi_dual_nt35597_cmd";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+
+		qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
+		vddio-supply = <&pm8994_l14>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
+	};
 
-		dsi_dual_nt35597_video_1: qcom,dsi-display@6 {
-			compatible = "qcom,dsi-display";
-			label = "dsi_dual_nt35597_video";
-			qcom,display-type = "primary";
-
-			qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
-			qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
-			clocks = <&clock_mmss clk_ext_byte0_clk_src>,
-				 <&clock_mmss clk_ext_pclk0_clk_src>;
-			clock-names = "src_byte_clk", "src_pixel_clk";
-
-			pinctrl-names = "panel_active", "panel_suspend";
-			pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
-			pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
-			qcom,platform-te-gpio = <&tlmm 10 0>;
-
-			qcom,dsi-panel = <&dsi_dual_nt35597_video>;
-			vddio-supply = <&pm8994_l14>;
-			lab-supply = <&lab_regulator>;
-			ibb-supply = <&ibb_regulator>;
-		};
+	dsi_dual_nt35597_video_1: qcom,dsi-display@6 {
+		compatible = "qcom,dsi-display";
+		label = "dsi_dual_nt35597_video";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+		clocks = <&clock_mmss clk_ext_byte0_clk_src>,
+			 <&clock_mmss clk_ext_pclk0_clk_src>;
+		clock-names = "src_byte_clk", "src_pixel_clk";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+		pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+
+		qcom,dsi-panel = <&dsi_dual_nt35597_video>;
+		vddio-supply = <&pm8994_l14>;
+		lab-supply = <&lab_regulator>;
+		ibb-supply = <&ibb_regulator>;
 	};
 };
 
 &mdss_mdp {
-	connectors = <&display_manager>;
+	connectors = <&dsi_dual_sharp_video_1
+		&sde_wb>;
 };
 
 &dsi_dual_sharp_video {
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 55b5ac96506f..8a534316e240 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -1,5 +1,4 @@
 ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm -Idrivers/gpu/drm/msm/dsi-staging
-ccflags-y += -Idrivers/gpu/drm/msm/display-manager
 ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
 ccflags-$(CONFIG_SYNC) += -Idrivers/staging/android
 ccflags-$(CONFIG_DRM_MSM_DSI_PLL) += -Idrivers/gpu/drm/msm/dsi
@@ -43,22 +42,7 @@ msm_drm-y := \
 	sde/sde_plane.o \
 	sde/sde_connector.o \
 	sde/sde_color_processing.o \
-	sde/sde_vbif.o \
-	msm_atomic.o \
-	msm_drv.o \
-	msm_fb.o \
-	msm_gem.o \
-	msm_gem_prime.o \
-	msm_gem_submit.o \
-	msm_gpu.o \
-	msm_iommu.o \
-	msm_smmu.o \
-	msm_perf.o \
-	msm_rd.o \
-	msm_ringbuffer.o \
-	msm_evtlog.o \
-	sde_power_handle.o \
-	msm_prop.o
+	sde/sde_vbif.o
 
 # use drm gpu driver only if qcom_kgsl driver not available
 ifneq ($(CONFIG_QCOM_KGSL),y)
@@ -106,9 +90,8 @@ msm_drm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \
 msm_drm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \
 				dsi/pll/dsi_pll_28nm.o
 
-obj-$(CONFIG_DRM_MSM)	+= msm_drm.o
-
-obj-$(CONFIG_DRM_MSM) += sde/sde_hw_catalog.o \
+msm_drm-$(CONFIG_DRM_MSM) += \
+	sde/sde_hw_catalog.o \
 	sde/sde_hw_cdm.o \
 	sde/sde_hw_dspp.o \
 	sde/sde_hw_intf.o \
@@ -122,8 +105,25 @@ obj-$(CONFIG_DRM_MSM) += sde/sde_hw_catalog.o \
 	sde/sde_hw_interrupts.o \
 	sde/sde_hw_vbif.o \
 	sde/sde_formats.o \
+	sde_power_handle.o
 
-obj-$(CONFIG_DRM_MSM) += display-manager/display_manager.o
-
-obj-$(CONFIG_DRM_SDE_WB) += sde/sde_wb.o \
+msm_drm-$(CONFIG_DRM_SDE_WB) += sde/sde_wb.o \
 	sde/sde_encoder_phys_wb.o
+
+msm_drm-$(CONFIG_DRM_MSM) += \
+	msm_atomic.o \
+	msm_drv.o \
+	msm_fb.o \
+	msm_gem.o \
+	msm_gem_prime.o \
+	msm_gem_submit.o \
+	msm_gpu.o \
+	msm_iommu.o \
+	msm_smmu.o \
+	msm_perf.o \
+	msm_rd.o \
+	msm_ringbuffer.o \
+	msm_evtlog.o \
+	msm_prop.o
+
+obj-$(CONFIG_DRM_MSM)	+= msm_drm.o
diff --git a/drivers/gpu/drm/msm/display-manager/display_manager.c b/drivers/gpu/drm/msm/display-manager/display_manager.c
deleted file mode 100644
index 0b5d2f9f2ee9..000000000000
--- a/drivers/gpu/drm/msm/display-manager/display_manager.c
+++ /dev/null
@@ -1,611 +0,0 @@
-/*
- * Copyright (c) 2016, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#define pr_fmt(fmt)	"dm-drm:[%s] " fmt, __func__
-#include <linux/of_device.h>
-#include <linux/err.h>
-#include <linux/regulator/consumer.h>
-#include <linux/clk.h>
-#include <linux/msm-bus.h>
-#include <linux/of_irq.h>
-
-#include "msm_drv.h"
-#include "msm_kms.h"
-#include "msm_gpu.h"
-#include "sde_connector.h"
-
-#include "dsi_display.h"
-#include "dsi_drm.h"
-#include "sde_wb.h"
-#include "display_manager.h"
-
-/**
- * _dm_cache_active_displays - determine display type based on index
- * @disp_m: Pointer to display manager structure
- * Returns: Number of active displays in the system
- */
-static u32 _dm_cache_active_displays(struct display_manager *disp_m)
-{
-	u32 count;
-
-	if (!disp_m)
-		return 0;
-
-	disp_m->display_count = 0;
-
-	/* query dsi displays */
-	disp_m->dsi_display_count = dsi_display_get_num_of_displays();
-
-	/* query hdmi displays */
-	disp_m->hdmi_display_count = 0;
-
-	/* query dp displays */
-	disp_m->dp_display_count = 0;
-
-	/* query wb displays */
-	disp_m->wb_display_count = sde_wb_get_num_of_displays();
-	DBG("wb display count=%d", disp_m->wb_display_count);
-
-	count = disp_m->dsi_display_count
-		+ disp_m->hdmi_display_count
-		+ disp_m->dp_display_count
-		+ disp_m->wb_display_count;
-
-	disp_m->displays = kcalloc(count, sizeof(void *), GFP_KERNEL);
-	if (!disp_m->displays) {
-		disp_m->dsi_displays = 0;
-		disp_m->dsi_display_count = 0;
-
-		disp_m->hdmi_displays = 0;
-		disp_m->hdmi_display_count = 0;
-
-		disp_m->dp_displays = 0;
-		disp_m->dp_display_count = 0;
-
-		disp_m->wb_displays = 0;
-		disp_m->wb_display_count = 0;
-	} else {
-		/* get final dsi display list */
-		disp_m->dsi_displays = disp_m->displays;
-		disp_m->dsi_display_count =
-			dsi_display_get_active_displays(disp_m->dsi_displays,
-					disp_m->dsi_display_count);
-
-		/* get final hdmi display list */
-		disp_m->hdmi_displays = disp_m->dsi_displays
-			+ disp_m->dsi_display_count;
-		disp_m->hdmi_display_count = 0;
-
-		/* get final dp display list */
-		disp_m->dp_displays = disp_m->hdmi_displays
-			+ disp_m->hdmi_display_count;
-		disp_m->dp_display_count = 0;
-
-		/* get final wb display list */
-		disp_m->wb_displays = disp_m->dp_displays
-			+ disp_m->dp_display_count;
-		disp_m->wb_display_count =
-			wb_display_get_displays(disp_m->wb_displays,
-					disp_m->wb_display_count);
-	}
-
-	/* set final display count */
-	disp_m->display_count = disp_m->dsi_display_count
-		+ disp_m->hdmi_display_count
-		+ disp_m->dp_display_count
-		+ disp_m->wb_display_count;
-
-	return disp_m->display_count;
-}
-
-/**
- * _dm_get_type_by_index - determine display type based on index
- * @disp_m: Pointer to display manager structure
- * @display_index: Incoming display index
- * Returns: DRM_MODE_CONNECTOR_ definition corresponding to display_index
- */
-static int _dm_get_type_by_index(struct display_manager *disp_m,
-				      u32 display_index)
-{
-	if (disp_m) {
-		if (display_index < disp_m->dsi_display_count)
-			return DRM_MODE_CONNECTOR_DSI;
-		display_index -= disp_m->dsi_display_count;
-
-		if (display_index < disp_m->hdmi_display_count)
-			return DRM_MODE_CONNECTOR_HDMIA;
-		display_index -= disp_m->hdmi_display_count;
-
-		if (display_index < disp_m->dp_display_count)
-			return DRM_MODE_CONNECTOR_DisplayPort;
-		display_index -= disp_m->dp_display_count;
-
-		if (display_index < disp_m->wb_display_count)
-			return DRM_MODE_CONNECTOR_VIRTUAL;
-		display_index -= disp_m->wb_display_count;
-	}
-	return DRM_MODE_CONNECTOR_Unknown;
-}
-
-/**
- * _dm_init_active_displays - initialize active display drivers
- * @disp_m: Pointer to display manager structure
- * Returns: Zero on success
- */
-static int _dm_init_active_displays(struct display_manager *disp_m)
-{
-	void *display;
-	int rc = 0;
-	int dsi_idx, wb_idx;
-
-	for (dsi_idx = 0; dsi_idx < disp_m->dsi_display_count; dsi_idx++) {
-		display = disp_m->dsi_displays[dsi_idx];
-
-		rc = dsi_display_dev_init(display);
-		if (rc) {
-			pr_err("failed to init dsi display, rc=%d\n", rc);
-			goto error_deinit_dsi_displays;
-		}
-	}
-
-	for (wb_idx = 0; wb_idx < disp_m->wb_display_count; wb_idx++) {
-		display = disp_m->wb_displays[wb_idx];
-
-		rc = sde_wb_dev_init(display);
-		if (rc) {
-			pr_err("failed to init wb display, rc=%d\n", rc);
-			goto error_deinit_sde_wb;
-		}
-	}
-
-	/* TODO: INIT HDMI and DP displays here */
-	return rc;
-
-error_deinit_sde_wb:
-	for (wb_idx = wb_idx - 1; wb_idx >= 0; wb_idx--) {
-		display = disp_m->wb_displays[wb_idx];
-		(void)sde_wb_dev_deinit(display);
-	}
-
-error_deinit_dsi_displays:
-	for (dsi_idx = dsi_idx - 1; dsi_idx >= 0; dsi_idx--) {
-		display = disp_m->dsi_displays[dsi_idx];
-		(void)dsi_display_dev_deinit(display);
-	}
-
-	return rc;
-}
-
-/**
- * _dm_deinit_active_displays - deconstruct active display drivers
- * @disp_m: Pointer to display manager structure
- * Returns: Zero on success
- */
-static void _dm_deinit_active_displays(struct display_manager *disp_m)
-{
-	void *display;
-	int rc, i;
-
-	for (i = 0; i < disp_m->wb_display_count; i++) {
-		display = disp_m->wb_displays[i];
-
-		rc = sde_wb_dev_deinit(display);
-		if (rc)
-			pr_err("failed to deinit wb display, rc=%d\n", rc);
-	}
-
-	for (i = 0; i < disp_m->dsi_display_count; i++) {
-		display = disp_m->dsi_displays[i];
-		rc = dsi_display_dev_deinit(display);
-		if (rc)
-			pr_err("failed to deinit dsi display, rc=%d\n", rc);
-	}
-
-	/* TODO: DEINIT HDMI and DP displays here */
-}
-
-static int disp_manager_comp_ops_bind(struct device *dev,
-				     struct device *master,
-				     void *data)
-{
-	struct drm_device *drm;
-	struct msm_drm_private *priv;
-	struct display_manager *disp_m;
-	void *display;
-	int dsi_idx, wb_idx;
-	int rc = -EINVAL;
-
-	if (master && dev) {
-		drm = dev_get_drvdata(master);
-		disp_m = platform_get_drvdata(to_platform_device(dev));
-		if (drm && drm->dev_private && disp_m)
-			rc = 0;
-	}
-
-	if (rc) {
-		pr_err("Invalid params\n");
-		return -EINVAL;
-	}
-
-	priv = drm->dev_private;
-	disp_m->drm_dev = drm;
-
-	/* DSI displays */
-	for (dsi_idx = 0; dsi_idx < disp_m->dsi_display_count; dsi_idx++) {
-		display = disp_m->dsi_displays[dsi_idx];
-
-		rc = dsi_display_bind(display, drm);
-		if (rc) {
-			if (rc != -EPROBE_DEFER)
-				pr_err("Failed to bind dsi display_%d, rc=%d\n",
-					dsi_idx, rc);
-			goto error_unbind_dsi;
-		}
-	}
-
-	/* WB displays */
-	for (wb_idx = 0; wb_idx < disp_m->wb_display_count; wb_idx++) {
-		display = disp_m->wb_displays[wb_idx];
-
-		rc = sde_wb_bind(display, drm);
-		if (rc) {
-			pr_err("Failed to bind wb display_%d, rc=%d\n",
-				wb_idx, rc);
-			goto error_unbind_wb;
-		}
-	}
-
-	/* TODO: BIND HDMI display here */
-	/* TODO: BIND DP display here */
-	priv->dm = disp_m;
-	return rc;
-
-error_unbind_wb:
-	for (wb_idx = wb_idx - 1; wb_idx >= 0; wb_idx--) {
-		display = disp_m->wb_displays[wb_idx];
-		(void)sde_wb_unbind(display);
-	}
-
-error_unbind_dsi:
-	for (dsi_idx = dsi_idx - 1; dsi_idx >= 0; dsi_idx--) {
-		display = disp_m->dsi_displays[dsi_idx];
-		(void)dsi_display_unbind(display);
-	}
-	return rc;
-}
-
-static void disp_manager_comp_ops_unbind(struct device *dev,
-					struct device *master,
-					void *data)
-{
-	int rc = 0;
-	struct platform_device *pdev = to_platform_device(dev);
-	struct display_manager *disp_m;
-	void *display;
-	int i;
-
-	if (!dev) {
-		pr_err("Invalid params\n");
-		return;
-	}
-
-	disp_m = platform_get_drvdata(pdev);
-
-	/* WB displays */
-	for (i = 0; i < disp_m->wb_display_count; i++) {
-		display = disp_m->wb_displays[i];
-
-		rc = sde_wb_unbind(display);
-		if (rc)
-			pr_err("failed to unbind wb display_%d, rc=%d\n",
-			       i, rc);
-	}
-
-	/* DSI displays */
-	for (i = 0; i < disp_m->dsi_display_count; i++) {
-		display = disp_m->dsi_displays[i];
-
-		rc = dsi_display_unbind(display);
-		if (rc)
-			pr_err("failed to unbind dsi display_%d, rc=%d\n",
-			       i, rc);
-	}
-
-	/* TODO: UNBIND HDMI display here */
-	/* TODO: UNBIND DP display here */
-}
-
-static const struct of_device_id displays_dt_match[] = {
-	{.compatible = "qcom,dsi-display"},
-	{.compatible = "qcom,hdmi-display"},
-	{.compatible = "qcom,dp-display"},
-	{.compatible = "qcom,wb-display"},
-	{}
-};
-
-static const struct component_ops disp_manager_comp_ops = {
-	.bind = disp_manager_comp_ops_bind,
-	.unbind = disp_manager_comp_ops_unbind,
-};
-
-static int disp_manager_dev_probe(struct platform_device *pdev)
-{
-	struct display_manager *disp_m;
-	int rc = 0;
-
-	if (!pdev || !pdev->dev.of_node) {
-		pr_err("pdev not found\n");
-		return -ENODEV;
-	}
-
-	disp_m = devm_kzalloc(&pdev->dev, sizeof(*disp_m), GFP_KERNEL);
-	if (!disp_m)
-		return -ENOMEM;
-
-	disp_m->name = "qcom,display-manager";
-
-	of_platform_populate(pdev->dev.of_node, displays_dt_match,
-			     NULL, &pdev->dev);
-
-	disp_m->display_count = _dm_cache_active_displays(disp_m);
-	if (!disp_m->display_count) {
-		rc = -ENODEV;
-		pr_err("no displays found, rc=%d\n", rc);
-		goto error_free_disp_m;
-	}
-
-	rc = _dm_init_active_displays(disp_m);
-	if (rc) {
-		pr_err("failed to initialize displays, rc=%d\n", rc);
-		goto error_remove_displays;
-	}
-
-	rc = component_add(&pdev->dev, &disp_manager_comp_ops);
-	if (rc) {
-		pr_err("failed to add component, rc=%d\n", rc);
-		goto error_deinit_displays;
-	}
-
-	mutex_init(&disp_m->lock);
-	platform_set_drvdata(pdev, disp_m);
-
-	return rc;
-error_deinit_displays:
-	_dm_deinit_active_displays(disp_m);
-error_remove_displays:
-	of_platform_depopulate(&pdev->dev);
-error_free_disp_m:
-	devm_kfree(&pdev->dev, disp_m);
-	return rc;
-}
-
-static int disp_manager_dev_remove(struct platform_device *pdev)
-{
-	struct display_manager *disp_m;
-
-	if (!pdev) {
-		pr_err("invalid pdev argument\n");
-		return -ENODEV;
-	}
-
-	disp_m = platform_get_drvdata(pdev);
-
-	_dm_deinit_active_displays(disp_m);
-	of_platform_depopulate(&pdev->dev);
-	devm_kfree(&pdev->dev, disp_m);
-
-	return 0;
-}
-
-static const struct of_device_id disp_manager_dt_match[] = {
-	{.compatible = "qcom,display-manager"},
-	{}
-};
-
-static struct platform_driver disp_manager_driver = {
-	.probe = disp_manager_dev_probe,
-	.remove = disp_manager_dev_remove,
-	.driver = {
-		.name = "msm-display-manager",
-		.of_match_table = disp_manager_dt_match,
-	},
-};
-
-int display_manager_get_count(struct display_manager *disp_m)
-{
-	int count;
-
-	if (!disp_m) {
-		pr_err("invalid params\n");
-		return 0;
-	}
-
-	mutex_lock(&disp_m->lock);
-
-	count = disp_m->display_count;
-
-	mutex_unlock(&disp_m->lock);
-	return count;
-}
-
-int display_manager_get_info_by_index(struct display_manager *disp_m,
-				      u32 display_index,
-				      struct msm_display_info *info)
-{
-	void *display;
-	int rc = 0;
-
-	if (!disp_m || !info || (display_index >= disp_m->display_count)) {
-		pr_err("Invalid params\n");
-		return -EINVAL;
-	}
-
-	memset(info, 0, sizeof(*info));
-
-	mutex_lock(&disp_m->lock);
-
-	display = disp_m->displays[display_index];
-
-	switch (_dm_get_type_by_index(disp_m, display_index)) {
-	case DRM_MODE_CONNECTOR_DSI:
-		rc = dsi_display_get_info(info, display);
-		if (rc) {
-			pr_err("failed to get dsi info, rc=%d\n", rc);
-			rc = -EINVAL;
-		}
-		break;
-	case DRM_MODE_CONNECTOR_VIRTUAL:
-		rc = sde_wb_get_info(info, display);
-		if (rc) {
-			pr_err("failed to get wb info, rc=%d\n", rc);
-			rc = -EINVAL;
-		}
-		break;
-	default:
-		pr_err("invalid index %d\n", display_index);
-		rc = -EINVAL;
-		break;
-	}
-	mutex_unlock(&disp_m->lock);
-	return rc;
-}
-
-int display_manager_drm_init_by_index(struct display_manager *disp_m,
-				      u32 display_index,
-				      struct drm_encoder *encoder)
-{
-	static const struct sde_connector_ops dsi_ops = {
-		.post_init =  dsi_conn_post_init,
-		.detect =     dsi_conn_detect,
-		.get_modes =  dsi_connector_get_modes,
-		.mode_valid = dsi_conn_mode_valid,
-		.get_info =   dsi_display_get_info,
-	};
-	static const struct sde_connector_ops wb_ops = {
-		.post_init =    sde_wb_connector_post_init,
-		.detect =       sde_wb_connector_detect,
-		.get_modes =    sde_wb_connector_get_modes,
-		.set_property = sde_wb_connector_set_property,
-		.get_info =     sde_wb_get_info,
-	};
-	void *display;
-	int rc = -EINVAL;
-	struct drm_connector *connector;
-
-	if (!disp_m || !encoder || (display_index >= disp_m->display_count)) {
-		pr_err("Invalid params\n");
-		return -EINVAL;
-	}
-
-	mutex_lock(&disp_m->lock);
-
-	display = disp_m->displays[display_index];
-
-	switch (_dm_get_type_by_index(disp_m, display_index)) {
-	case DRM_MODE_CONNECTOR_DSI:
-		rc = dsi_display_drm_bridge_init(display, encoder);
-		if (rc) {
-			pr_err("dsi bridge init failed\n");
-			break;
-		}
-
-		connector = sde_connector_init(disp_m->drm_dev,
-				encoder,
-				0,
-				display,
-				&dsi_ops,
-				DRM_CONNECTOR_POLL_HPD,
-				DRM_MODE_CONNECTOR_DSI);
-		if (!connector)
-			rc = -ENOMEM;
-		else if (IS_ERR(connector))
-			rc = PTR_ERR(connector);
-		break;
-	case DRM_MODE_CONNECTOR_VIRTUAL:
-		rc = sde_wb_drm_init(display, encoder);
-		if (rc) {
-			pr_err("writeback init failed\n");
-			break;
-		}
-
-		connector = sde_connector_init(disp_m->drm_dev,
-				encoder,
-				0,
-				display,
-				&wb_ops,
-				DRM_CONNECTOR_POLL_HPD,
-				DRM_MODE_CONNECTOR_VIRTUAL);
-		if (!connector)
-			rc = -ENOMEM;
-		else if (IS_ERR(connector))
-			rc = PTR_ERR(connector);
-		break;
-	default:
-		pr_err("invalid index %d\n", display_index);
-		break;
-	}
-
-	mutex_unlock(&disp_m->lock);
-
-	return rc;
-}
-
-int display_manager_drm_deinit_by_index(struct display_manager *disp_m,
-					u32 display_index)
-{
-	void *display;
-	int rc = 0;
-
-	if (!disp_m) {
-		pr_err("Invalid params\n");
-		return -EINVAL;
-	}
-
-	mutex_lock(&disp_m->lock);
-
-	if (display_index < disp_m->display_count)
-		display = disp_m->displays[display_index];
-
-	switch (_dm_get_type_by_index(disp_m, display_index)) {
-	case DRM_MODE_CONNECTOR_DSI:
-		dsi_display_drm_bridge_deinit(display);
-		break;
-	default:
-		pr_err("invalid index\n");
-		rc = -EINVAL;
-		break;
-	}
-
-	mutex_unlock(&disp_m->lock);
-
-	return rc;
-}
-
-
-void display_manager_register(void)
-{
-	dsi_phy_drv_register();
-	dsi_ctrl_drv_register();
-	dsi_display_register();
-	sde_wb_register();
-	platform_driver_register(&disp_manager_driver);
-}
-void display_manager_unregister(void)
-{
-	platform_driver_unregister(&disp_manager_driver);
-	sde_wb_unregister();
-	dsi_display_unregister();
-	dsi_ctrl_drv_unregister();
-	dsi_phy_drv_unregister();
-}
diff --git a/drivers/gpu/drm/msm/display-manager/display_manager.h b/drivers/gpu/drm/msm/display-manager/display_manager.h
deleted file mode 100644
index d220fc016a3e..000000000000
--- a/drivers/gpu/drm/msm/display-manager/display_manager.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2016, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DISPLAY_MANAGER_H_
-#define _DISPLAY_MANAGER_H_
-
-struct display_manager {
-	struct drm_device *drm_dev;
-	struct platform_device *pdev;
-	const char *name;
-
-	struct mutex lock;
-
-	u32 display_count;
-	void **displays;
-
-	u32 dsi_display_count;
-	void **dsi_displays;
-
-	u32 hdmi_display_count;
-	void **hdmi_displays;
-
-	u32 dp_display_count;
-	void **dp_displays;
-
-	u32 wb_display_count;
-	void **wb_displays;
-
-	/* Debug fs */
-	struct dentry *debugfs_root;
-};
-
-/**
- * display_manager_get_count() - returns the number of display present
- * @disp_m:      Handle to Display manager.
- *
- * Returns the sum total of DSI, HDMI and DP display present on the board.
- *
- * Return: error code (< 0) in case of error or number of display ( >= 0)
- */
-int display_manager_get_count(struct display_manager *disp_m);
-
-/**
- * display_manager_get_info_by_index() - returns display information
- * @disp_m:        Handle to Display manager.
- * @display_index: display index (valid indices are 0 to (display_count - 1).
- * @info:          Structure where display info is copied.
- *
- * Return: error code.
- */
-int display_manager_get_info_by_index(struct display_manager *disp_m,
-				      u32 display_index,
-				      struct msm_display_info *info);
-
-/**
- * display_manager_drm_init_by_index() - initialize drm objects for display
- * @disp_m:         Handle to Display manager.
- * @display_index:  display index (valid indices are 0 to (display_count - 1).
- * @encoder:        Pointer to encoder object to which display is attached.
- *
- * Return: error code.
- */
-int display_manager_drm_init_by_index(struct display_manager *disp_m,
-				      u32 display_index,
-				      struct drm_encoder *encoder);
-
-/**
- * display_manager_drm_deinit_by_index() - detroys drm objects
- * @disp_m:         Handle to Display manager.
- * @display_index:  display index (valid indices are 0 to (display_count - 1).
- *
- * Return: error code.
- */
-int display_manager_drm_deinit_by_index(struct display_manager *disp_m,
-					u32 display_index);
-
-/**
- * display_manager_register() - register display interface drivers
- */
-void display_manager_register(void);
-
-/**
- * display_manager_unregister() - unregisters display interface drivers
- */
-void display_manager_unregister(void);
-
-#endif /* _DISPLAY_MANAGER_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index 59e9899640bf..825bf2dc3ec1 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -126,7 +126,7 @@ error:
 	return rc;
 }
 
-static int dsi_dipslay_debugfs_deinit(struct dsi_display *display)
+static int dsi_display_debugfs_deinit(struct dsi_display *display)
 {
 	debugfs_remove_recursive(display->root);
 
@@ -1592,148 +1592,19 @@ error:
 	return rc;
 }
 
-static struct platform_driver dsi_display_driver = {
-	.probe = dsi_display_dev_probe,
-	.remove = dsi_display_dev_remove,
-	.driver = {
-		.name = "msm-dsi-display",
-		.of_match_table = dsi_display_dt_match,
-	},
-};
-
-int dsi_display_dev_probe(struct platform_device *pdev)
-{
-	int rc = 0;
-	struct dsi_display *display;
-
-	if (!pdev || !pdev->dev.of_node) {
-		pr_err("pdev not found\n");
-		return -ENODEV;
-	}
-
-	display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
-	if (!display)
-		return -ENOMEM;
-
-	display->name = of_get_property(pdev->dev.of_node, "label", NULL);
-
-	display->is_active = of_property_read_bool(pdev->dev.of_node,
-						"qcom,dsi-display-active");
-
-	display->display_type = of_get_property(pdev->dev.of_node,
-						"qcom,display-type", NULL);
-	if (!display->display_type)
-		display->display_type = "unknown";
-
-	mutex_init(&display->display_lock);
-
-	display->pdev = pdev;
-	platform_set_drvdata(pdev, display);
-	mutex_lock(&dsi_display_list_lock);
-	list_add(&display->list, &dsi_display_list);
-	mutex_unlock(&dsi_display_list_lock);
-	if (display->is_active)
-		main_display = display;
-	return rc;
-}
-
-int dsi_display_dev_remove(struct platform_device *pdev)
-{
-	int rc = 0;
-	struct dsi_display *display;
-	struct dsi_display *pos, *tmp;
-
-	if (!pdev) {
-		pr_err("Invalid device\n");
-		return -EINVAL;
-	}
-
-	display = platform_get_drvdata(pdev);
-
-	mutex_lock(&dsi_display_list_lock);
-	list_for_each_entry_safe(pos, tmp, &dsi_display_list, list) {
-		if (pos == display) {
-			list_del(&display->list);
-			break;
-		}
-	}
-	mutex_unlock(&dsi_display_list_lock);
-
-	platform_set_drvdata(pdev, NULL);
-	devm_kfree(&pdev->dev, display);
-	return rc;
-}
-
-u32 dsi_display_get_num_of_displays(void)
-{
-	u32 count = 0;
-	struct dsi_display *display;
-
-	mutex_lock(&dsi_display_list_lock);
-
-	list_for_each_entry(display, &dsi_display_list, list) {
-		count++;
-	}
-
-	mutex_unlock(&dsi_display_list_lock);
-	return count;
-}
-
-int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
-{
-	struct dsi_display *pos;
-	int i = 0;
-
-	if (!display_array || !max_display_count) {
-		if (!display_array)
-			pr_err("invalid params\n");
-		return 0;
-	}
-
-	mutex_lock(&dsi_display_list_lock);
-
-	list_for_each_entry(pos, &dsi_display_list, list) {
-		if (i >= max_display_count) {
-			pr_err("capping display count to %d\n", i);
-			break;
-		}
-		if (pos->is_active)
-			display_array[i++] = pos;
-	}
-
-	mutex_unlock(&dsi_display_list_lock);
-	return i;
-}
-
-struct dsi_display *dsi_display_get_display_by_name(const char *name)
-{
-	struct dsi_display *display = NULL, *pos;
-
-	mutex_lock(&dsi_display_list_lock);
-
-	list_for_each_entry(pos, &dsi_display_list, list) {
-		if (!strcmp(name, pos->name))
-			display = pos;
-	}
-
-	mutex_unlock(&dsi_display_list_lock);
-
-	return display;
-}
-
-void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
-{
-	mutex_lock(&display->display_lock);
-	display->is_active = is_active;
-	mutex_unlock(&display->display_lock);
-}
-
-int dsi_display_dev_init(struct dsi_display *display)
+/**
+ * _dsi_display_dev_init - initializes the display device
+ * Initialization will acquire references to the resources required for the
+ * display hardware to function.
+ * @display:         Handle to the display
+ * Returns:          Zero on success
+ */
+static int _dsi_display_dev_init(struct dsi_display *display)
 {
 	int rc = 0;
 
 	if (!display) {
-		pr_err("Invalid params\n");
+		pr_err("invalid display\n");
 		return -EINVAL;
 	}
 
@@ -1756,12 +1627,18 @@ error:
 	return rc;
 }
 
-int dsi_display_dev_deinit(struct dsi_display *display)
+/**
+ * _dsi_display_dev_deinit - deinitializes the display device
+ * All the resources acquired during device init will be released.
+ * @display:        Handle to the display
+ * Returns:         Zero on success
+ */
+static int _dsi_display_dev_deinit(struct dsi_display *display)
 {
 	int rc = 0;
 
 	if (!display) {
-		pr_err("Invalid params\n");
+		pr_err("invalid display\n");
 		return -EINVAL;
 	}
 
@@ -1777,14 +1654,34 @@ int dsi_display_dev_deinit(struct dsi_display *display)
 	return rc;
 }
 
-int dsi_display_bind(struct dsi_display *display, struct drm_device *dev)
+/**
+ * dsi_display_bind - bind dsi device with controlling device
+ * @dev:        Pointer to base of platform device
+ * @master:     Pointer to container of drm device
+ * @data:       Pointer to private data
+ * Returns:     Zero on success
+ */
+static int dsi_display_bind(struct device *dev,
+		struct device *master,
+		void *data)
 {
-	int rc = 0;
-	int i;
 	struct dsi_display_ctrl *display_ctrl;
+	struct drm_device *drm;
+	struct dsi_display *display;
+	struct platform_device *pdev = to_platform_device(dev);
+	int i, rc = 0;
 
-	if (!display) {
-		pr_err("Invalid params\n");
+	if (!dev || !pdev || !master) {
+		pr_err("invalid param(s), dev %pK, pdev %pK, master %pK\n",
+				dev, pdev, master);
+		return -EINVAL;
+	}
+
+	drm = dev_get_drvdata(master);
+	display = platform_get_drvdata(pdev);
+	if (!drm || !display) {
+		pr_err("invalid param(s), drm %pK, display %pK\n",
+				drm, display);
 		return -EINVAL;
 	}
 
@@ -1792,7 +1689,7 @@ int dsi_display_bind(struct dsi_display *display, struct drm_device *dev)
 
 	rc = dsi_display_debugfs_init(display);
 	if (rc) {
-		pr_err("[%s]Debugfs init failed, rc=%d\n", display->name, rc);
+		pr_err("[%s] debugfs init failed, rc=%d\n", display->name, rc);
 		goto error;
 	}
 
@@ -1801,7 +1698,7 @@ int dsi_display_bind(struct dsi_display *display, struct drm_device *dev)
 
 		rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
 		if (rc) {
-			pr_err("[%s] Failed to initialize ctrl[%d], rc=%d\n",
+			pr_err("[%s] failed to initialize ctrl[%d], rc=%d\n",
 			       display->name, i, rc);
 			goto error_ctrl_deinit;
 		}
@@ -1817,7 +1714,7 @@ int dsi_display_bind(struct dsi_display *display, struct drm_device *dev)
 
 	rc = dsi_display_mipi_host_init(display);
 	if (rc) {
-		pr_err("[%s] Failed to initialize mipi host, rc=%d\n",
+		pr_err("[%s] failed to initialize mipi host, rc=%d\n",
 		       display->name, rc);
 		goto error_ctrl_deinit;
 	}
@@ -1825,19 +1722,19 @@ int dsi_display_bind(struct dsi_display *display, struct drm_device *dev)
 	rc = dsi_panel_drv_init(display->panel, &display->host);
 	if (rc) {
 		if (rc != -EPROBE_DEFER)
-			pr_err("[%s] Failed to initialize panel driver, rc=%d\n",
+			pr_err("[%s] failed to initialize panel driver, rc=%d\n",
 			       display->name, rc);
 		goto error_host_deinit;
 	}
 
 	rc = dsi_panel_get_mode_count(display->panel, &display->num_of_modes);
 	if (rc) {
-		pr_err("[%s] Failed to get mode count, rc=%d\n",
+		pr_err("[%s] failed to get mode count, rc=%d\n",
 		       display->name, rc);
 		goto error_panel_deinit;
 	}
 
-	display->drm_dev = dev;
+	display->drm_dev = drm;
 	goto error;
 
 error_panel_deinit:
@@ -1850,21 +1747,35 @@ error_ctrl_deinit:
 		(void)dsi_phy_drv_deinit(display_ctrl->phy);
 		(void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
 	}
-	(void)dsi_dipslay_debugfs_deinit(display);
+	(void)dsi_display_debugfs_deinit(display);
 error:
 	mutex_unlock(&display->display_lock);
 	return rc;
 }
 
-int dsi_display_unbind(struct dsi_display *display)
+/**
+ * dsi_display_unbind - unbind dsi from controlling device
+ * @dev:        Pointer to base of platform device
+ * @master:     Pointer to container of drm device
+ * @data:       Pointer to private data
+ */
+static void dsi_display_unbind(struct device *dev,
+		struct device *master, void *data)
 {
-	int rc = 0;
-	int i;
 	struct dsi_display_ctrl *display_ctrl;
+	struct dsi_display *display;
+	struct platform_device *pdev = to_platform_device(dev);
+	int i, rc = 0;
+
+	if (!dev || !pdev) {
+		pr_err("invalid param(s)\n");
+		return;
+	}
 
+	display = platform_get_drvdata(pdev);
 	if (!display) {
-		pr_err("Invalid params\n");
-		return -EINVAL;
+		pr_err("invalid display\n");
+		return;
 	}
 
 	mutex_lock(&display->display_lock);
@@ -1893,13 +1804,165 @@ int dsi_display_unbind(struct dsi_display *display)
 			pr_err("[%s] failed to deinit ctrl%d driver, rc=%d\n",
 			       display->name, i, rc);
 	}
-
-	(void)dsi_dipslay_debugfs_deinit(display);
+	(void)dsi_display_debugfs_deinit(display);
 
 	mutex_unlock(&display->display_lock);
+}
+
+static const struct component_ops dsi_display_comp_ops = {
+	.bind = dsi_display_bind,
+	.unbind = dsi_display_unbind,
+};
+
+static struct platform_driver dsi_display_driver = {
+	.probe = dsi_display_dev_probe,
+	.remove = dsi_display_dev_remove,
+	.driver = {
+		.name = "msm-dsi-display",
+		.of_match_table = dsi_display_dt_match,
+	},
+};
+
+int dsi_display_dev_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct dsi_display *display;
+
+	if (!pdev || !pdev->dev.of_node) {
+		pr_err("pdev not found\n");
+		return -ENODEV;
+	}
+
+	display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
+	if (!display)
+		return -ENOMEM;
+
+	display->name = of_get_property(pdev->dev.of_node, "label", NULL);
+
+	display->is_active = of_property_read_bool(pdev->dev.of_node,
+						"qcom,dsi-display-active");
+
+	display->display_type = of_get_property(pdev->dev.of_node,
+						"qcom,display-type", NULL);
+	if (!display->display_type)
+		display->display_type = "unknown";
+
+	mutex_init(&display->display_lock);
+
+	display->pdev = pdev;
+	platform_set_drvdata(pdev, display);
+	mutex_lock(&dsi_display_list_lock);
+	list_add(&display->list, &dsi_display_list);
+	mutex_unlock(&dsi_display_list_lock);
+
+	if (display->is_active) {
+		main_display = display;
+		rc = _dsi_display_dev_init(display);
+		if (rc) {
+			pr_err("device init failed, rc=%d\n", rc);
+			return rc;
+		}
+
+		rc = component_add(&pdev->dev, &dsi_display_comp_ops);
+		if (rc)
+			pr_err("component add failed, rc=%d\n", rc);
+	}
+	return rc;
+}
+
+int dsi_display_dev_remove(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct dsi_display *display;
+	struct dsi_display *pos, *tmp;
+
+	if (!pdev) {
+		pr_err("Invalid device\n");
+		return -EINVAL;
+	}
+
+	display = platform_get_drvdata(pdev);
+
+	(void)_dsi_display_dev_deinit(display);
+
+	mutex_lock(&dsi_display_list_lock);
+	list_for_each_entry_safe(pos, tmp, &dsi_display_list, list) {
+		if (pos == display) {
+			list_del(&display->list);
+			break;
+		}
+	}
+	mutex_unlock(&dsi_display_list_lock);
+
+	platform_set_drvdata(pdev, NULL);
+	devm_kfree(&pdev->dev, display);
 	return rc;
 }
 
+int dsi_display_get_num_of_displays(void)
+{
+	int count = 0;
+	struct dsi_display *display;
+
+	mutex_lock(&dsi_display_list_lock);
+
+	list_for_each_entry(display, &dsi_display_list, list) {
+		count++;
+	}
+
+	mutex_unlock(&dsi_display_list_lock);
+	return count;
+}
+
+int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
+{
+	struct dsi_display *pos;
+	int i = 0;
+
+	if (!display_array || !max_display_count) {
+		if (!display_array)
+			pr_err("invalid params\n");
+		return 0;
+	}
+
+	mutex_lock(&dsi_display_list_lock);
+
+	list_for_each_entry(pos, &dsi_display_list, list) {
+		if (i >= max_display_count) {
+			pr_err("capping display count to %d\n", i);
+			break;
+		}
+		if (pos->is_active)
+			display_array[i++] = pos;
+	}
+
+	mutex_unlock(&dsi_display_list_lock);
+	return i;
+}
+
+struct dsi_display *dsi_display_get_display_by_name(const char *name)
+{
+	struct dsi_display *display = NULL, *pos;
+
+	mutex_lock(&dsi_display_list_lock);
+
+	list_for_each_entry(pos, &dsi_display_list, list) {
+		if (!strcmp(name, pos->name))
+			display = pos;
+	}
+
+	mutex_unlock(&dsi_display_list_lock);
+
+	return display;
+}
+
+void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
+{
+	mutex_lock(&display->display_lock);
+	display->is_active = is_active;
+	mutex_unlock(&display->display_lock);
+}
+
 int dsi_display_drm_bridge_init(struct dsi_display *display,
 		struct drm_encoder *enc)
 {
@@ -1907,8 +1970,8 @@ int dsi_display_drm_bridge_init(struct dsi_display *display,
 	struct dsi_bridge *bridge;
 	struct msm_drm_private *priv = NULL;
 
-	if (!display || !enc) {
-		pr_err("Invalid params\n");
+	if (!display || !display->drm_dev || !enc) {
+		pr_err("invalid param(s)\n");
 		return -EINVAL;
 	}
 
@@ -2489,12 +2552,19 @@ int dsi_display_unprepare(struct dsi_display *display)
 	return rc;
 }
 
-void dsi_display_register(void)
+static int __init dsi_display_register(void)
 {
-	platform_driver_register(&dsi_display_driver);
+	dsi_phy_drv_register();
+	dsi_ctrl_drv_register();
+	return platform_driver_register(&dsi_display_driver);
 }
 
-void dsi_display_unregister(void)
+static void __exit dsi_display_unregister(void)
 {
 	platform_driver_unregister(&dsi_display_driver);
+	dsi_ctrl_drv_unregister();
+	dsi_phy_drv_unregister();
 }
+
+module_init(dsi_display_register);
+module_exit(dsi_display_unregister);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
index f941cd46feaf..813e7e385076 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
@@ -158,23 +158,13 @@ struct dsi_display {
 int dsi_display_dev_probe(struct platform_device *pdev);
 int dsi_display_dev_remove(struct platform_device *pdev);
 
-/**
- * dsi_display_register() - register dsi display platform driver
- */
-void dsi_display_register(void);
-
-/**
- * dsi_display_unregister() - unregister dsi display platform driver
- */
-void dsi_display_unregister(void);
-
 /**
  * dsi_display_get_num_of_displays() - returns number of display devices
  *				       supported.
  *
  * Return: number of displays.
  */
-u32 dsi_display_get_num_of_displays(void);
+int dsi_display_get_num_of_displays(void);
 
 /**
  * dsi_display_get_active_displays - returns pointers for active display devices
@@ -200,44 +190,6 @@ struct dsi_display *dsi_display_get_display_by_name(const char *name);
  */
 void dsi_display_set_active_state(struct dsi_display *display, bool is_active);
 
-/**
- * dsi_display_dev_init() - Initializes the display device
- * @display:         Handle to the display.
- *
- * Initialization will acquire references to the resources required for the
- * display hardware to function.
- *
- * Return: error code.
- */
-int dsi_display_dev_init(struct dsi_display *display);
-
-/**
- * dsi_display_dev_deinit() - Desinitializes the display device
- * @display:        Handle to the display.
- *
- * All the resources acquired during device init will be released.
- *
- * Return: error code.
- */
-int dsi_display_dev_deinit(struct dsi_display *display);
-
-/**
- * dsi_display_bind() - Binds the display device to the DRM device
- * @display:       Handle to the display.
- * @dev:           Pointer to the DRM device.
- *
- * Return: error code.
- */
-int dsi_display_bind(struct dsi_display *display, struct drm_device *dev);
-
-/**
- * dsi_display_unbind() - Unbinds the display device from the DRM device
- * @display:         Handle to the display.
- *
- * Return: error code.
- */
-int dsi_display_unbind(struct dsi_display *display);
-
 /**
  * dsi_display_drm_bridge_init() - initializes DRM bridge object for DSI
  * @display:            Handle to the display.
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 803bfb35e6ce..46b1f007648e 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -19,7 +19,6 @@
 #include "msm_drv.h"
 #include "msm_gpu.h"
 #include "msm_kms.h"
-#include "display_manager.h"
 #include "sde_wb.h"
 
 #define TEARDOWN_DEADLOCK_RETRY_MAX 5
@@ -1757,7 +1756,6 @@ void __exit adreno_unregister(void)
 static int __init msm_drm_register(void)
 {
 	DBG("init");
-	display_manager_register();
 	msm_dsi_register();
 	msm_edp_register();
 	hdmi_register();
@@ -1773,7 +1771,6 @@ static void __exit msm_drm_unregister(void)
 	adreno_unregister();
 	msm_edp_unregister();
 	msm_dsi_unregister();
-	display_manager_unregister();
 }
 
 module_init(msm_drm_register);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 9164b87877aa..8d5b15b53877 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -210,8 +210,6 @@ struct msm_display_info {
 	enum msm_display_compression compression;
 };
 
-struct display_manager;
-
 /**
  * struct msm_drm_event - defines custom event notification struct
  * @base: base object required for event notification by DRM framework.
@@ -251,9 +249,6 @@ struct msm_drm_private {
 	/* DSI is shared by mdp4 and mdp5 */
 	struct msm_dsi *dsi[2];
 
-	/* Display manager for SDE driver */
-	struct display_manager *dm;
-
 	/* when we have more than one 'msm_gpu' these need to be an array: */
 	struct msm_gpu *gpu;
 	struct msm_file_private *lastctx;
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 0fe1f3401f87..b4757add7dae 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -25,7 +25,6 @@
 #include "sde_hw_ctl.h"
 #include "sde_formats.h"
 #include "sde_encoder_phys.h"
-#include "display_manager.h"
 #include "sde_color_processing.h"
 
 #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
@@ -218,7 +217,7 @@ void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 	}
 }
 
-static void sde_encoder_destroy(struct drm_encoder *drm_enc)
+void sde_encoder_destroy(struct drm_encoder *drm_enc)
 {
 	struct sde_encoder_virt *sde_enc = NULL;
 	int i = 0;
@@ -1051,8 +1050,9 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
 	return ret;
 }
 
-static struct drm_encoder *sde_encoder_virt_init(
-		struct drm_device *dev, struct msm_display_info *disp_info)
+struct drm_encoder *sde_encoder_init(
+		struct drm_device *dev,
+		struct msm_display_info *disp_info)
 {
 	struct msm_drm_private *priv = dev->dev_private;
 	struct sde_kms *sde_kms = to_sde_kms(priv->kms);
@@ -1121,64 +1121,3 @@ int sde_encoder_wait_for_commit_done(struct drm_encoder *drm_enc)
 	return ret;
 }
 
-/* encoders init,
- * initialize encoder based on displays
- */
-void sde_encoders_init(struct drm_device *dev)
-{
-	struct msm_drm_private *priv = NULL;
-	struct display_manager *disp_man = NULL;
-	u32 i = 0;
-	u32 num_displays = 0;
-
-	SDE_DEBUG("\n");
-
-	if (!dev || !dev->dev_private) {
-		SDE_ERROR("invalid device %d\n", dev != 0);
-		return;
-	}
-
-	priv = dev->dev_private;
-	priv->num_encoders = 0;
-	if (!priv->kms || !priv->dm) {
-		SDE_ERROR("invalid priv pointer, kms %d dm %d\n",
-				priv->kms != 0, priv->dm != 0);
-		return;
-	}
-	disp_man = priv->dm;
-
-	num_displays = display_manager_get_count(disp_man);
-	SDE_DEBUG("num_displays %d\n", num_displays);
-
-	if (num_displays > ARRAY_SIZE(priv->encoders)) {
-		num_displays = ARRAY_SIZE(priv->encoders);
-		SDE_ERROR("too many displays found, capping to %d\n",
-				num_displays);
-	}
-
-	for (i = 0; i < num_displays; i++) {
-		struct msm_display_info info = { 0 };
-		struct drm_encoder *enc = NULL;
-		u32 ret = 0;
-
-		ret = display_manager_get_info_by_index(disp_man, i, &info);
-		if (ret) {
-			SDE_ERROR("failed to get display info, %d\n", ret);
-			return;
-		}
-
-		enc = sde_encoder_virt_init(dev, &info);
-		if (IS_ERR_OR_NULL(enc)) {
-			SDE_ERROR("encoder initialization failed\n");
-			return;
-		}
-
-		ret = display_manager_drm_init_by_index(disp_man, i, enc);
-		if (ret) {
-			SDE_ERROR("display drm_init failed, %d\n", ret);
-			return;
-		}
-
-		priv->encoders[priv->num_encoders++] = enc;
-	}
-}
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
index 71cf83671ab5..7462c7b4bd9b 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -17,6 +17,11 @@
 
 #include "msm_drv.h"
 #include "msm_mmu.h"
+
+#include "dsi_display.h"
+#include "dsi_drm.h"
+#include "sde_wb.h"
+
 #include "sde_kms.h"
 #include "sde_core_irq.h"
 #include "sde_formats.h"
@@ -320,6 +325,215 @@ static void sde_kms_prepare_fence(struct msm_kms *kms,
 		sde_connector_prepare_fence(connector);
 }
 
+/**
+ * _sde_kms_get_displays - query for underlying display handles and cache them
+ * @sde_kms:    Pointer to sde kms structure
+ * Returns:     Zero on success
+ */
+static int _sde_kms_get_displays(struct sde_kms *sde_kms)
+{
+	int rc = -ENOMEM;
+
+	if (!sde_kms) {
+		SDE_ERROR("invalid sde kms\n");
+		return -EINVAL;
+	}
+
+	/* dsi */
+	sde_kms->dsi_displays = NULL;
+	sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
+	if (sde_kms->dsi_display_count) {
+		sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
+				sizeof(void *),
+				GFP_KERNEL);
+		if (!sde_kms->dsi_displays) {
+			SDE_ERROR("failed to allocate dsi displays\n");
+			goto exit_deinit_dsi;
+		}
+		sde_kms->dsi_display_count =
+			dsi_display_get_active_displays(sde_kms->dsi_displays,
+					sde_kms->dsi_display_count);
+	}
+
+	/* wb */
+	sde_kms->wb_displays = NULL;
+	sde_kms->wb_display_count = sde_wb_get_num_of_displays();
+	if (sde_kms->wb_display_count) {
+		sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
+				sizeof(void *),
+				GFP_KERNEL);
+		if (!sde_kms->wb_displays) {
+			SDE_ERROR("failed to allocate wb displays\n");
+			goto exit_deinit_wb;
+		}
+		sde_kms->wb_display_count =
+			wb_display_get_displays(sde_kms->wb_displays,
+					sde_kms->wb_display_count);
+	}
+	return 0;
+
+exit_deinit_wb:
+	kfree(sde_kms->wb_displays);
+	sde_kms->wb_display_count = 0;
+	sde_kms->wb_displays = NULL;
+
+exit_deinit_dsi:
+	kfree(sde_kms->dsi_displays);
+	sde_kms->dsi_display_count = 0;
+	sde_kms->dsi_displays = NULL;
+	return rc;
+}
+
+/**
+ * _sde_kms_release_displays - release cache of underlying display handles
+ * @sde_kms:    Pointer to sde kms structure
+ */
+static void _sde_kms_release_displays(struct sde_kms *sde_kms)
+{
+	if (!sde_kms) {
+		SDE_ERROR("invalid sde kms\n");
+		return;
+	}
+
+	kfree(sde_kms->wb_displays);
+	sde_kms->wb_displays = NULL;
+	sde_kms->wb_display_count = 0;
+
+	kfree(sde_kms->dsi_displays);
+	sde_kms->dsi_displays = NULL;
+	sde_kms->dsi_display_count = 0;
+}
+
+/**
+ * _sde_kms_setup_displays - create encoders, bridges and connectors
+ *                           for underlying displays
+ * @dev:        Pointer to drm device structure
+ * @priv:       Pointer to private drm device data
+ * @sde_kms:    Pointer to sde kms structure
+ * Returns:     Zero on success
+ */
+static int _sde_kms_setup_displays(struct drm_device *dev,
+		struct msm_drm_private *priv,
+		struct sde_kms *sde_kms)
+{
+	static const struct sde_connector_ops dsi_ops = {
+		.post_init =  dsi_conn_post_init,
+		.detect =     dsi_conn_detect,
+		.get_modes =  dsi_connector_get_modes,
+		.mode_valid = dsi_conn_mode_valid,
+		.get_info =   dsi_display_get_info,
+	};
+	static const struct sde_connector_ops wb_ops = {
+		.post_init =    sde_wb_connector_post_init,
+		.detect =       sde_wb_connector_detect,
+		.get_modes =    sde_wb_connector_get_modes,
+		.set_property = sde_wb_connector_set_property,
+		.get_info =     sde_wb_get_info,
+	};
+	struct msm_display_info info;
+	struct drm_encoder *encoder;
+	void *display, *connector;
+	int i, max_encoders;
+	int rc = 0;
+
+	if (!dev || !priv || !sde_kms) {
+		SDE_ERROR("invalid argument(s)\n");
+		return -EINVAL;
+	}
+
+	max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count;
+	if (max_encoders > ARRAY_SIZE(priv->encoders)) {
+		max_encoders = ARRAY_SIZE(priv->encoders);
+		SDE_ERROR("capping number of displays to %d", max_encoders);
+	}
+
+	/* dsi */
+	for (i = 0; i < sde_kms->dsi_display_count &&
+		priv->num_encoders < max_encoders; ++i) {
+		display = sde_kms->dsi_displays[i];
+		encoder = NULL;
+
+		memset(&info, 0x0, sizeof(info));
+		rc = dsi_display_get_info(&info, display);
+		if (rc) {
+			SDE_ERROR("dsi get_info %d failed\n", i);
+			continue;
+		}
+
+		encoder = sde_encoder_init(dev, &info);
+		if (IS_ERR_OR_NULL(encoder)) {
+			SDE_ERROR("encoder init failed for dsi %d\n", i);
+			continue;
+		}
+
+		rc = dsi_display_drm_bridge_init(display, encoder);
+		if (rc) {
+			SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
+			sde_encoder_destroy(encoder);
+			continue;
+		}
+
+		connector = sde_connector_init(dev,
+					encoder,
+					0,
+					display,
+					&dsi_ops,
+					DRM_CONNECTOR_POLL_HPD,
+					DRM_MODE_CONNECTOR_DSI);
+		if (connector) {
+			priv->encoders[priv->num_encoders++] = encoder;
+		} else {
+			SDE_ERROR("dsi %d connector init failed\n", i);
+			dsi_display_drm_bridge_deinit(display);
+			sde_encoder_destroy(encoder);
+		}
+	}
+
+	/* wb */
+	for (i = 0; i < sde_kms->wb_display_count &&
+		priv->num_encoders < max_encoders; ++i) {
+		display = sde_kms->wb_displays[i];
+		encoder = NULL;
+
+		memset(&info, 0x0, sizeof(info));
+		rc = sde_wb_get_info(&info, display);
+		if (rc) {
+			SDE_ERROR("wb get_info %d failed\n", i);
+			continue;
+		}
+
+		encoder = sde_encoder_init(dev, &info);
+		if (IS_ERR_OR_NULL(encoder)) {
+			SDE_ERROR("encoder init failed for wb %d\n", i);
+			continue;
+		}
+
+		rc = sde_wb_drm_init(display, encoder);
+		if (rc) {
+			SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
+			sde_encoder_destroy(encoder);
+			continue;
+		}
+
+		connector = sde_connector_init(dev,
+				encoder,
+				0,
+				display,
+				&wb_ops,
+				DRM_CONNECTOR_POLL_HPD,
+				DRM_MODE_CONNECTOR_VIRTUAL);
+		if (connector) {
+			priv->encoders[priv->num_encoders++] = encoder;
+		} else {
+			SDE_ERROR("wb %d connector init failed\n", i);
+			sde_wb_drm_deinit(display);
+			sde_encoder_destroy(encoder);
+		}
+	}
+
+	return 0;
+}
+
 static int modeset_init(struct sde_kms *sde_kms)
 {
 	struct drm_device *dev;
@@ -341,8 +555,12 @@ static int modeset_init(struct sde_kms *sde_kms)
 	priv = dev->dev_private;
 	catalog = sde_kms->catalog;
 
-	/* Enumerate displays supported */
-	sde_encoders_init(dev);
+	/*
+	 * Query for underlying display drivers, and create connectors,
+	 * bridges and encoders for them.
+	 */
+	if (!_sde_kms_get_displays(sde_kms))
+		(void)_sde_kms_setup_displays(dev, priv, sde_kms);
 
 	max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
 	max_plane_count = min_t(u32, catalog->sspp_count, MAX_PLANES);
@@ -440,6 +658,7 @@ static void sde_destroy(struct msm_kms *kms)
 			sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
 	}
 
+	_sde_kms_release_displays(sde_kms);
 	sde_debugfs_destroy(sde_kms);
 	sde_hw_intr_destroy(sde_kms->hw_intr);
 	sde_rm_destroy(&sde_kms->rm);
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.h b/drivers/gpu/drm/msm/sde/sde_kms.h
index 2a2d2f693da1..acdde6d04dd2 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.h
+++ b/drivers/gpu/drm/msm/sde/sde_kms.h
@@ -143,6 +143,10 @@ struct sde_kms {
 
 	struct sde_hw_vbif *hw_vbif[VBIF_MAX];
 	struct sde_hw_mdp *hw_mdp;
+	int dsi_display_count;
+	void **dsi_displays;
+	int wb_display_count;
+	void **wb_displays;
 };
 
 struct vsync_info {
@@ -463,10 +467,19 @@ void sde_encoder_schedule_kickoff(struct drm_encoder *encoder);
 int sde_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder);
 
 /**
- * sde_encoders_init - query platform, create all encoders and bridges,
- *	and register them with the drm_device
- * @dev:	drm device pointer
+ * sde_encoder_init - initialize virtual encoder object
+ * @dev:        Pointer to drm device structure
+ * @disp_info:  Pointer to display information structure
+ * Returns:     Pointer to newly created drm encoder
  */
-void sde_encoders_init(struct drm_device *dev);
+struct drm_encoder *sde_encoder_init(
+		struct drm_device *dev,
+		struct msm_display_info *disp_info);
+
+/**
+ * sde_encoder_destroy - destroy previously initialized virtual encoder
+ * @drm_enc:    Pointer to previously created drm encoder structure
+ */
+void sde_encoder_destroy(struct drm_encoder *drm_enc);
 
 #endif /* __sde_kms_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_wb.c b/drivers/gpu/drm/msm/sde/sde_wb.c
index 1778721cf2a9..647cb5891153 100644
--- a/drivers/gpu/drm/msm/sde/sde_wb.c
+++ b/drivers/gpu/drm/msm/sde/sde_wb.c
@@ -487,7 +487,11 @@ fail:
 	return rc;
 }
 
-int sde_wb_dev_init(struct sde_wb_device *wb_dev)
+/**
+ * _sde_wb_dev_init - perform device initialization
+ * @wb_dev:	Pointer to writeback device
+ */
+static int _sde_wb_dev_init(struct sde_wb_device *wb_dev)
 {
 	int rc = 0;
 
@@ -501,7 +505,11 @@ int sde_wb_dev_init(struct sde_wb_device *wb_dev)
 	return rc;
 }
 
-int sde_wb_dev_deinit(struct sde_wb_device *wb_dev)
+/**
+ * _sde_wb_dev_deinit - perform device de-initialization
+ * @wb_dev:	Pointer to writeback device
+ */
+static int _sde_wb_dev_deinit(struct sde_wb_device *wb_dev)
 {
 	int rc = 0;
 
@@ -515,31 +523,57 @@ int sde_wb_dev_deinit(struct sde_wb_device *wb_dev)
 	return rc;
 }
 
-int sde_wb_bind(struct sde_wb_device *wb_dev, struct drm_device *drm_dev)
+/**
+ * sde_wb_bind - bind writeback device with controlling device
+ * @dev:        Pointer to base of platform device
+ * @master:     Pointer to container of drm device
+ * @data:       Pointer to private data
+ * Returns:     Zero on success
+ */
+static int sde_wb_bind(struct device *dev, struct device *master, void *data)
 {
-	int rc = 0;
+	struct sde_wb_device *wb_dev;
 
-	if (!wb_dev || !drm_dev) {
+	if (!dev || !master) {
 		SDE_ERROR("invalid params\n");
 		return -EINVAL;
 	}
 
+	wb_dev = platform_get_drvdata(to_platform_device(dev));
+	if (!wb_dev) {
+		SDE_ERROR("invalid wb device\n");
+		return -EINVAL;
+	}
+
 	SDE_DEBUG("\n");
 
 	mutex_lock(&wb_dev->wb_lock);
-	wb_dev->drm_dev = drm_dev;
+	wb_dev->drm_dev = dev_get_drvdata(master);
 	mutex_unlock(&wb_dev->wb_lock);
 
-	return rc;
+	return 0;
 }
 
-int sde_wb_unbind(struct sde_wb_device *wb_dev)
+/**
+ * sde_wb_unbind - unbind writeback from controlling device
+ * @dev:        Pointer to base of platform device
+ * @master:     Pointer to container of drm device
+ * @data:       Pointer to private data
+ */
+static void sde_wb_unbind(struct device *dev,
+		struct device *master, void *data)
 {
-	int rc = 0;
+	struct sde_wb_device *wb_dev;
 
-	if (!wb_dev) {
+	if (!dev) {
 		SDE_ERROR("invalid params\n");
-		return -EINVAL;
+		return;
+	}
+
+	wb_dev = platform_get_drvdata(to_platform_device(dev));
+	if (!wb_dev) {
+		SDE_ERROR("invalid wb device\n");
+		return;
 	}
 
 	SDE_DEBUG("\n");
@@ -547,15 +581,23 @@ int sde_wb_unbind(struct sde_wb_device *wb_dev)
 	mutex_lock(&wb_dev->wb_lock);
 	wb_dev->drm_dev = NULL;
 	mutex_unlock(&wb_dev->wb_lock);
-
-	return rc;
 }
 
+static const struct component_ops sde_wb_comp_ops = {
+	.bind = sde_wb_bind,
+	.unbind = sde_wb_unbind,
+};
+
+/**
+ * sde_wb_drm_init - perform DRM initialization
+ * @wb_dev:	Pointer to writeback device
+ * @encoder:	Pointer to associated encoder
+ */
 int sde_wb_drm_init(struct sde_wb_device *wb_dev, struct drm_encoder *encoder)
 {
 	int rc = 0;
 
-	if (!wb_dev || !encoder) {
+	if (!wb_dev || !wb_dev->drm_dev || !encoder) {
 		SDE_ERROR("invalid params\n");
 		return -EINVAL;
 	}
@@ -631,7 +673,13 @@ static int sde_wb_probe(struct platform_device *pdev)
 	list_add(&wb_dev->wb_list, &sde_wb_list);
 	mutex_unlock(&sde_wb_list_lock);
 
-	return 0;
+	if (!_sde_wb_dev_init(wb_dev)) {
+		ret = component_add(&pdev->dev, &sde_wb_comp_ops);
+		if (ret)
+			pr_err("component add failed\n");
+	}
+
+	return ret;
 }
 
 /**
@@ -649,6 +697,8 @@ static int sde_wb_remove(struct platform_device *pdev)
 
 	SDE_DEBUG("\n");
 
+	(void)_sde_wb_dev_deinit(wb_dev);
+
 	mutex_lock(&sde_wb_list_lock);
 	list_for_each_entry_safe(curr, next, &sde_wb_list, wb_list) {
 		if (curr == wb_dev) {
@@ -681,12 +731,15 @@ static struct platform_driver sde_wb_driver = {
 	},
 };
 
-void sde_wb_register(void)
+static int __init sde_wb_register(void)
 {
-	platform_driver_register(&sde_wb_driver);
+	return platform_driver_register(&sde_wb_driver);
 }
 
-void sde_wb_unregister(void)
+static void __exit sde_wb_unregister(void)
 {
 	platform_driver_unregister(&sde_wb_driver);
 }
+
+module_init(sde_wb_register);
+module_exit(sde_wb_unregister);
diff --git a/drivers/gpu/drm/msm/sde/sde_wb.h b/drivers/gpu/drm/msm/sde/sde_wb.h
index 79056200aa06..a2afc1635824 100644
--- a/drivers/gpu/drm/msm/sde/sde_wb.h
+++ b/drivers/gpu/drm/msm/sde/sde_wb.h
@@ -93,35 +93,8 @@ u32 sde_wb_get_num_of_displays(void);
  */
 int wb_display_get_displays(void **display_array, u32 max_display_count);
 
-/**
- * wb_display_get_displays - returns pointers for supported display devices
- * @display_array: Pointer to display array to be filled
- * @max_display_count: Size of display_array
- * @Returns: Number of display entries filled
- */
-int sde_wb_dev_init(struct sde_wb_device *wb_dev);
-
-/**
- * sde_wb_dev_deinit - perform device de-initialization
- * @wb_dev:	Pointer to writeback device
- * Returns:	0 if success; error code otherwise
- */
-int sde_wb_dev_deinit(struct sde_wb_device *wb_dev);
-
-/**
- * sde_wb_bind - bind writeback device with controlling device
- * @wb_dev:	Pointer to writeback device
- * @drm_dev:	Pointer to controlling DRM device
- * Returns:	0 if success; error code otherwise
- */
-int sde_wb_bind(struct sde_wb_device *wb_dev, struct drm_device *drm_dev);
-
-/**
- * sde_wb_unbind - unbind writeback from controlling device
- * @wb_dev:	Pointer to writeback device
- * Returns:	0 if success; error code otherwise
- */
-int sde_wb_unbind(struct sde_wb_device *wb_dev);
+void sde_wb_set_active_state(struct sde_wb_device *wb_dev, bool is_active);
+bool sde_wb_is_active(struct sde_wb_device *wb_dev);
 
 /**
  * sde_wb_drm_init - perform DRM initialization
@@ -138,16 +111,6 @@ int sde_wb_drm_init(struct sde_wb_device *wb_dev, struct drm_encoder *encoder);
  */
 int sde_wb_drm_deinit(struct sde_wb_device *wb_dev);
 
-/**
- * sde_wb_register - register writeback module
- */
-void sde_wb_register(void);
-
-/**
- * sde_wb_unregister - unregister writeback module
- */
-void sde_wb_unregister(void);
-
 /**
  * sde_wb_config - setup connection status and available drm modes of the
  *			given writeback connector
@@ -274,24 +237,13 @@ int wb_display_get_displays(void **display_array, u32 max_display_count)
 	return 0;
 }
 static inline
-int sde_wb_dev_init(struct sde_wb_device *wb_dev)
+void sde_wb_set_active_state(struct sde_wb_device *wb_dev, bool is_active)
 {
-	return 0;
 }
 static inline
-int sde_wb_dev_deinit(struct sde_wb_device *wb_dev)
+bool sde_wb_is_active(struct sde_wb_device *wb_dev)
 {
-	return 0;
-}
-static inline
-int sde_wb_bind(struct sde_wb_device *wb_dev, struct drm_device *drm_dev)
-{
-	return 0;
-}
-static inline
-int sde_wb_unbind(struct sde_wb_device *wb_dev)
-{
-	return 0;
+	return false;
 }
 static inline
 int sde_wb_drm_init(struct sde_wb_device *wb_dev, struct drm_encoder *encoder)
@@ -304,14 +256,6 @@ int sde_wb_drm_deinit(struct sde_wb_device *wb_dev)
 	return 0;
 }
 static inline
-void sde_wb_register(void)
-{
-}
-static inline
-void sde_wb_unregister(void)
-{
-}
-static inline
 int sde_wb_config(struct drm_device *drm_dev, void *data,
 				struct drm_file *file_priv)
 {
-- 
cgit v1.2.3


From 2d488ea7ed4fc104f9a150de13f143dc1776d100 Mon Sep 17 00:00:00 2001
From: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
Date: Mon, 17 Oct 2016 18:45:55 +0530
Subject: drm/msm/sde: Add backlight class support for sde drm driver

Add backlight class support for sde drm driver which provides
sysfs interface to userspace to control display brightness.

Change-Id: I4f777618e8f2ff61e72beddb7a5bd1fa6e9dd5df
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
---
 .../devicetree/bindings/fb/mdss-dsi-panel.txt      |   1 +
 drivers/gpu/drm/msm/Makefile                       |   1 +
 drivers/gpu/drm/msm/dsi-staging/dsi_display.c      |  18 ++++
 drivers/gpu/drm/msm/dsi-staging/dsi_display.h      |   1 +
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.c        |  41 ++++++--
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.h        |   9 +-
 drivers/gpu/drm/msm/sde/sde_backlight.c            | 103 +++++++++++++++++++++
 drivers/gpu/drm/msm/sde/sde_backlight.h            |  18 ++++
 drivers/gpu/drm/msm/sde/sde_connector.c            |   9 ++
 drivers/gpu/drm/msm/sde/sde_connector.h            |   2 +
 drivers/gpu/drm/msm/sde/sde_kms.c                  |   1 +
 11 files changed, 193 insertions(+), 11 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/sde/sde_backlight.c
 create mode 100644 drivers/gpu/drm/msm/sde/sde_backlight.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
index 9fc942cc627d..1fffb617248a 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
@@ -538,6 +538,7 @@ Example:
 		qcom,mdss-dsi-underflow-color = <0xff>;
 		qcom,mdss-dsi-bl-min-level = <1>;
 		qcom,mdss-dsi-bl-max-level = < 15>;
+		qcom,mdss-brightness-max-level = <255>;
 		qcom,mdss-dsi-interleave-mode = <0>;
 		qcom,mdss-dsi-panel-type = "dsi_video_mode";
 		qcom,mdss-dsi-te-check-enable;
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 8a534316e240..f756c0c59ffa 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -41,6 +41,7 @@ msm_drm-y := \
 	sde/sde_kms.o \
 	sde/sde_plane.o \
 	sde/sde_connector.o \
+	sde/sde_backlight.o \
 	sde/sde_color_processing.o \
 	sde/sde_vbif.o
 
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index 825bf2dc3ec1..5a166a4bae93 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -36,6 +36,24 @@ static const struct of_device_id dsi_display_dt_match[] = {
 
 static struct dsi_display *main_display;
 
+int dsi_display_set_backlight(void *display, u32 bl_lvl)
+{
+	struct dsi_display *dsi_display = display;
+	struct dsi_panel *panel;
+	int rc = 0;
+
+	if (dsi_display == NULL)
+		return -EINVAL;
+
+	panel = dsi_display->panel;
+
+	rc = dsi_panel_set_backlight(panel, bl_lvl);
+	if (rc)
+		pr_err("unable to set backlight\n");
+
+	return rc;
+}
+
 static ssize_t debugfs_dump_info_read(struct file *file,
 				      char __user *buff,
 				      size_t count,
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
index 813e7e385076..b77bf268dbd1 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
@@ -332,4 +332,5 @@ int dsi_display_set_tpg_state(struct dsi_display *display, bool enable);
 int dsi_display_clock_gate(struct dsi_display *display, bool enable);
 int dsi_dispaly_static_frame(struct dsi_display *display, bool enable);
 
+int dsi_display_set_backlight(void *display, u32 bl_lvl);
 #endif /* _DSI_DISPLAY_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
index 6e753f08a77e..28cfa1fba6d9 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
@@ -358,6 +358,23 @@ static int dsi_panel_led_bl_register(struct dsi_panel *panel,
 }
 #endif
 
+int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl)
+{
+	int rc = 0;
+	struct dsi_backlight_config *bl = &panel->bl_config;
+
+	switch (bl->type) {
+	case DSI_BACKLIGHT_WLED:
+		led_trigger_event(bl->wled, bl_lvl);
+		break;
+	default:
+		pr_err("Backlight type(%d) not supported\n", bl->type);
+		rc = -ENOTSUPP;
+	}
+
+	return rc;
+}
+
 static int dsi_panel_bl_register(struct dsi_panel *panel)
 {
 	int rc = 0;
@@ -1423,18 +1440,28 @@ static int dsi_panel_parse_bl_config(struct dsi_panel *panel,
 	if (rc) {
 		pr_debug("[%s] bl-min-level unspecified, defaulting to zero\n",
 			 panel->name);
-		panel->bl_config.min_level = 0;
+		panel->bl_config.bl_min_level = 0;
 	} else {
-		panel->bl_config.min_level = val;
+		panel->bl_config.bl_min_level = val;
 	}
 
 	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-bl-max-level", &val);
 	if (rc) {
-		pr_debug("[%s] bl-max-level unspecified, defaulting to 255\n",
+		pr_debug("[%s] bl-max-level unspecified, defaulting to max level\n",
+			 panel->name);
+		panel->bl_config.bl_max_level = MAX_BL_LEVEL;
+	} else {
+		panel->bl_config.bl_max_level = val;
+	}
+
+	rc = of_property_read_u32(of_node, "qcom,mdss-brightness-max-level",
+		&val);
+	if (rc) {
+		pr_debug("[%s] brigheness-max-level unspecified, defaulting to 255\n",
 			 panel->name);
-		panel->bl_config.max_level = 255;
+		panel->bl_config.brightness_max_level = 255;
 	} else {
-		panel->bl_config.max_level = val;
+		panel->bl_config.brightness_max_level = val;
 	}
 
 	if (panel->bl_config.type == DSI_BACKLIGHT_PWM) {
@@ -1834,8 +1861,6 @@ int dsi_panel_enable(struct dsi_panel *panel)
 		pr_err("[%s] failed to send DSI_CMD_SET_ON cmds, rc=%d\n",
 		       panel->name, rc);
 	}
-	/* TODO:  hack to enable backlight; */
-	led_trigger_event(panel->bl_config.wled, panel->bl_config.max_level);
 	mutex_unlock(&panel->panel_lock);
 	return rc;
 }
@@ -1873,8 +1898,6 @@ int dsi_panel_pre_disable(struct dsi_panel *panel)
 
 	mutex_lock(&panel->panel_lock);
 
-	/* TODO:  hack to disable backlight; */
-	led_trigger_event(panel->bl_config.wled, 0x0);
 	rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_PRE_OFF);
 	if (rc) {
 		pr_err("[%s] failed to send DSI_CMD_SET_PRE_OFF cmds, rc=%d\n",
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
index 1009d94f13a1..4d21a4cf6428 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h
@@ -27,6 +27,8 @@
 #include "dsi_ctrl_hw.h"
 #include "dsi_clk_pwr.h"
 
+#define MAX_BL_LEVEL 4096
+
 enum dsi_panel_rotation {
 	DSI_PANEL_ROTATE_NONE = 0,
 	DSI_PANEL_ROTATE_HV_FLIP,
@@ -101,8 +103,9 @@ struct dsi_panel_cmd_set {
 struct dsi_backlight_config {
 	enum dsi_backlight_type type;
 
-	u32 min_level;
-	u32 max_level;
+	u32 bl_min_level;
+	u32 bl_max_level;
+	u32 brightness_max_level;
 
 	int en_gpio;
 	/* PWM params */
@@ -113,6 +116,7 @@ struct dsi_backlight_config {
 
 	/* WLED params */
 	struct led_trigger *wled;
+	struct backlight_device *bd;
 };
 
 struct dsi_reset_seq {
@@ -195,4 +199,5 @@ int dsi_panel_unprepare(struct dsi_panel *panel);
 
 int dsi_panel_post_unprepare(struct dsi_panel *panel);
 
+int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl);
 #endif /* _DSI_PANEL_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_backlight.c b/drivers/gpu/drm/msm/sde/sde_backlight.c
new file mode 100644
index 000000000000..9034eeb944fe
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_backlight.c
@@ -0,0 +1,103 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "sde_connector.h"
+#include <linux/backlight.h>
+#include "dsi_drm.h"
+
+#define SDE_BRIGHT_TO_BL(out, v, bl_max, max_bright) do {\
+	out = (2 * (v) * (bl_max) + max_bright);\
+	do_div(out, 2 * max_bright);\
+} while (0)
+
+static int sde_backlight_device_update_status(struct backlight_device *bd)
+{
+	int brightness;
+	struct drm_connector *connector;
+	struct dsi_display *display;
+	struct sde_connector *c_conn;
+	int bl_lvl;
+
+	brightness = bd->props.brightness;
+
+	if ((bd->props.power != FB_BLANK_UNBLANK) ||
+			(bd->props.state & BL_CORE_FBBLANK) ||
+			(bd->props.state & BL_CORE_SUSPENDED))
+		brightness = 0;
+
+	connector = bl_get_data(bd);
+	c_conn = to_sde_connector(connector);
+	display = (struct dsi_display *) c_conn->display;
+	if (brightness > display->panel->bl_config.bl_max_level)
+		brightness = display->panel->bl_config.bl_max_level;
+
+	/* This maps UI brightness into driver backlight level with
+	 *        rounding
+	 */
+	SDE_BRIGHT_TO_BL(bl_lvl, brightness,
+			display->panel->bl_config.bl_max_level,
+			display->panel->bl_config.brightness_max_level);
+
+	if (!bl_lvl && brightness)
+		bl_lvl = 1;
+
+	if (c_conn->ops.set_backlight)
+		c_conn->ops.set_backlight(c_conn->display, bl_lvl);
+
+	return 0;
+}
+
+static int sde_backlight_device_get_brightness(struct backlight_device *bd)
+{
+	return 0;
+}
+
+static const struct backlight_ops sde_backlight_device_ops = {
+	.update_status = sde_backlight_device_update_status,
+	.get_brightness = sde_backlight_device_get_brightness,
+};
+
+int sde_backlight_setup(struct drm_connector *connector)
+{
+	struct sde_connector *c_conn;
+	struct backlight_device *bd;
+	struct backlight_properties props;
+	struct dsi_display *display;
+	struct dsi_backlight_config *bl_config;
+
+	if (!connector)
+		return -EINVAL;
+
+	c_conn = to_sde_connector(connector);
+	memset(&props, 0, sizeof(props));
+	props.type = BACKLIGHT_RAW;
+	props.power = FB_BLANK_UNBLANK;
+
+	switch (c_conn->connector_type) {
+	case DRM_MODE_CONNECTOR_DSI:
+		display = (struct dsi_display *) c_conn->display;
+		bl_config = &display->panel->bl_config;
+		props.max_brightness = bl_config->brightness_max_level;
+		props.brightness = bl_config->brightness_max_level;
+		bd = backlight_device_register("sde-backlight",
+				connector->kdev,
+				connector,
+				&sde_backlight_device_ops, &props);
+		if (IS_ERR(bd)) {
+			pr_err("Failed to register backlight: %ld\n",
+					    PTR_ERR(bd));
+			return -ENODEV;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_backlight.h b/drivers/gpu/drm/msm/sde/sde_backlight.h
new file mode 100644
index 000000000000..1ea130592302
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_backlight.h
@@ -0,0 +1,18 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SDE_BACKLIGHT_H_
+#define _SDE_BACKLIGHT_H_
+
+int sde_backlight_setup(struct drm_connector *connector);
+
+#endif /* _SDE_BACKLIGHT_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c
index 056cf60004f6..6bc69cb1e578 100644
--- a/drivers/gpu/drm/msm/sde/sde_connector.c
+++ b/drivers/gpu/drm/msm/sde/sde_connector.c
@@ -15,6 +15,7 @@
 
 #include "sde_kms.h"
 #include "sde_connector.h"
+#include "sde_backlight.h"
 
 static const struct drm_prop_enum_list e_topology_name[] = {
 	{SDE_RM_TOPOLOGY_UNKNOWN,	"sde_unknown"},
@@ -536,6 +537,14 @@ struct drm_connector *sde_connector_init(struct drm_device *dev,
 		goto error_unregister_conn;
 	}
 
+	if (c_conn->ops.set_backlight) {
+		rc = sde_backlight_setup(&c_conn->base);
+		if (rc) {
+			pr_err("failed to setup backlight, rc=%d\n", rc);
+			goto error_unregister_conn;
+		}
+	}
+
 	/* create properties */
 	msm_property_init(&c_conn->property_info, &c_conn->base.base, dev,
 			priv->conn_property, c_conn->property_data,
diff --git a/drivers/gpu/drm/msm/sde/sde_connector.h b/drivers/gpu/drm/msm/sde/sde_connector.h
index cca934d52914..9580282291db 100644
--- a/drivers/gpu/drm/msm/sde/sde_connector.h
+++ b/drivers/gpu/drm/msm/sde/sde_connector.h
@@ -111,6 +111,8 @@ struct sde_connector_ops {
 	 * Returns: Zero on success
 	 */
 	int (*get_info)(struct msm_display_info *info, void *display);
+
+	int (*set_backlight)(void *display, u32 bl_lvl);
 };
 
 /**
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
index a7c33adce36d..40a594df7c5b 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -436,6 +436,7 @@ static int _sde_kms_setup_displays(struct drm_device *dev,
 		.get_modes =  dsi_connector_get_modes,
 		.mode_valid = dsi_conn_mode_valid,
 		.get_info =   dsi_display_get_info,
+		.set_backlight = dsi_display_set_backlight
 	};
 	static const struct sde_connector_ops wb_ops = {
 		.post_init =    sde_wb_connector_post_init,
-- 
cgit v1.2.3


From 55bd068e864b5b5ad3a3188960907645da934f9f Mon Sep 17 00:00:00 2001
From: Benet Clark <benetc@codeaurora.org>
Date: Mon, 24 Oct 2016 10:14:00 -0700
Subject: drm/msm/sde: Add device tree subnode parsing capability

This change adds the capability for parsing a device tree subnode
of the SDE. For example, the DSPP's will be enumerated in the SDE
top-level DTSI node. The hardware blocks inside the DSPP will be
enumerated in a subnode in the DTSI.

Change-Id: If0cf37fac2388ab385b0bf416f40436e12d9395b
Signed-off-by: Benet Clark <benetc@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt        |  98 ++-
 arch/arm/boot/dts/qcom/msm8996-sde.dtsi            |  34 +-
 drivers/gpu/drm/msm/sde/sde_hw_catalog.c           | 871 ++++++++++++++++-----
 drivers/gpu/drm/msm/sde/sde_hw_catalog.h           |   4 +-
 drivers/gpu/drm/msm/sde/sde_hw_dspp.c              |   6 +-
 drivers/gpu/drm/msm/sde/sde_hw_sspp.c              |   4 +-
 6 files changed, 790 insertions(+), 227 deletions(-)

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index fb32a1d0bc6d..4c46e485f7bb 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -134,12 +134,6 @@ Optional properties:
 				indicating the danger luts on sspp.
 - qcom,sde-sspp-safe-lut:	A 3 cell property, with a format of <linear, tile, nrt>,
 				indicating the safe luts on sspp.
-- qcom,sde-sspp-qseed-off:	A u32 offset value indicates the qseed block offset
-				from sspp base. It will install qseed property on
-				vig and rgb sspp pipes.
-- qcom,sde-sspp-csc-off:	A u32 offset value indicates the csc block offset
-				from sspp base. It will be used to install the csc
-				property on vig type pipe.
 - qcom,sde-sspp-max-rects:	Array of u32 values indicating maximum rectangles supported
 				on each sspp. This property is for multirect feature support.
 				Number of offsets defined should match the number of
@@ -165,14 +159,48 @@ Optional properties:
 - qcom,sde-te-size:		A u32 value indicates the te block address range.
 - qcom,sde-te2-size:		A u32 value indicates the te2 block address range.
 - qcom,sde-dsc-off:	 	A u32 offset indicates the dsc block offset on pingpong.
-- qcom,sde-dspp-igc-off:	A u32 offset indicates the igc block offset on dssp.
-- qcom,sde-dspp-pcc-off:	A u32 offset indicates the pcc block offset on dssp.
-- qcom,sde-dspp-gc-off:		A u32 offset indicates the gc block offset on dssp.
-- qcom,sde-dspp-pa-off:		A u32 offset indicates the pa block offset on dssp.
-- qcom,sde-dspp-gamut-off:	A u32 offset indicates the gamut block offset on dssp.
-- qcom,sde-dspp-dither-off:	A u32 offset indicates the dither block offset on dssp.
-- qcom,sde-dspp-hist-off:	A u32 offset indicates the hist block offset on dssp.
-- qcom,sde-dspp-ad-off:		A u32 offset indicates the ad block offset on dssp.
+- qcom,sde-sspp-vig-blocks:	A node that lists the blocks inside the VIG hardware. The
+				block entries will contain the offset and version (if needed)
+				of each feature block. The presence of a block entry
+				indicates that the SSPP VIG contains that feature hardware.
+				e.g. qcom,sde-sspp-vig-blocks
+				-- qcom,sde-vig-csc-off: offset of CSC hardware
+				-- qcom,sde-vig-qseed-off: offset of QSEED hardware
+				-- qcom,sde-vig-pcc: offset and version of PCC hardware
+				-- qcom,sde-vig-hsic: offset and version of global PA adjustment
+				-- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware
+- qcom,sde-sspp-rgb-blocks:	A node that lists the blocks inside the RGB hardware. The
+				block entries will contain the offset and version (if needed)
+				of each feature block. The presence of a block entry
+				indicates that the SSPP RGB contains that feature hardware.
+				e.g. qcom,sde-sspp-vig-blocks
+				-- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware
+				-- qcom,sde-rgb-pcc: offset and version of PCC hardware
+- qcom,sde-dspp-blocks:		A node that lists the blocks inside the DSPP hardware. The
+				block entries will contain the offset and version of each
+				feature block. The presence of a block entry indicates that
+				the DSPP contains that feature hardware.
+				e.g. qcom,sde-dspp-blocks
+				-- qcom,sde-dspp-pcc: offset and version of PCC hardware
+				-- qcom,sde-dspp-gc: offset and version of GC hardware
+				-- qcom,sde-dspp-hsic: offset and version of global PA adjustment
+				-- qcom,sde-dspp-memcolor: offset and version of PA memcolor hardware
+				-- qcom,sde-dspp-sixzone: offset and version of PA sixzone hardware
+				-- qcom,sde-dspp-gamut: offset and version of Gamut mapping hardware
+				-- qcom,sde-dspp-dither: offset and version of dither hardware
+				-- qcom,sde-dspp-hist: offset and version of histogram hardware
+				-- qcom,sde-dspp-vlut: offset and version of PA vLUT hardware
+- qcom,sde-mixer-blocks:	A node that lists the blocks inside the layer mixer hardware. The
+				block entries will contain the offset and version (if needed)
+				of each feature block. The presence of a block entry
+				indicates that the layer mixer contains that feature hardware.
+				e.g. qcom,sde-mixer-blocks
+				-- qcom,sde-mixer-gc: offset and version of mixer GC hardware
+- qcom,sde-dspp-ad-off:		Array of u32 offsets indicate the ad block offset from the
+				DSPP offset. Since AD hardware is represented as part of
+				DSPP block, the AD offsets must be offset from the
+				corresponding DSPP base.
+- qcom,sde-dspp-ad-version	A u32 value indicating the version of the AD hardware
 - qcom,sde-vbif-id:		Array of vbif ids corresponding to the
 				offsets defined in property: qcom,sde-vbif-off.
 - qcom,sde-vbif-default-ot-rd-limit:	A u32 value indicates the default read OT limit
@@ -249,6 +277,8 @@ Example:
     qcom,sde-mixer-off = <0x00045000 0x00046000
 			0x00047000 0x0004a000>;
     qcom,sde-dspp-off = <0x00055000 0x00057000>;
+    qcom,sde-dspp-ad-off = <0x24000 0x22800>;
+    qcom,sde-dspp-ad-version = <0x00030000>;
     qcom,sde-wb-off = <0x00066000>;
     qcom,sde-wb-xin-id = <6>;
     qcom,sde-intf-off = <0x0006b000 0x0006b800
@@ -315,16 +345,6 @@ Example:
     qcom,sde-te2-off = <0x100>;
     qcom,sde-te-size = <0xffff>;
     qcom,sde-te2-size = <0xffff>;
-    qcom,sde-sspp-qseed-off = <0x100>;
-    qcom,sde-sspp-csc-off = <0x100>;
-    qcom,sde-dspp-igc-off = <0x100>;
-    qcom,sde-dspp-pcc-off = <0x100>;
-    qcom,sde-dspp-gc-off = <0x100>;
-    qcom,sde-dspp-pa-off = <0x100>;
-    qcom,sde-dspp-gamut-off = <0x100>;
-    qcom,sde-dspp-dither-off = <0x100>;
-    qcom,sde-dspp-hist-off = <0x100>;
-    qcom,sde-dspp-ad-off = <0x100>;
 
     qcom,sde-wb-id = <2>;
     qcom,sde-wb-clk-ctrl = <0x2bc 16>;
@@ -341,6 +361,36 @@ Example:
     qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>,
         <124416000 4>, <248832000 16>;
 
+    qcom,sde-sspp-vig-blocks {
+        qcom,sde-vig-csc-off = <0x320>;
+        qcom,sde-vig-qseed-off = <0x200>;
+        /* Offset from vig top, version of HSIC */
+        qcom,sde-vig-hsic = <0x200 0x00010000>;
+        qcom,sde-vig-memcolor = <0x200 0x00010000>;
+        qcom,sde-vig-pcc = <0x1780 0x00010000>;
+    };
+
+    qcom,sde-sspp-rgb-blocks {
+        qcom,sde-rgb-scaler-off = <0x200>;
+        qcom,sde-rgb-pcc = <0x380 0x00010000>;
+    };
+
+    qcom,sde-dspp-blocks {
+        qcom,sde-dspp-pcc = <0x1700 0x00010000>;
+        qcom,sde-dspp-gc = <0x17c0 0x00010000>;
+        qcom,sde-dspp-hsic = <0x0 0x00010000>;
+        qcom,sde-dspp-memcolor = <0x0 0x00010000>;
+        qcom,sde-dspp-sixzone = <0x0 0x00010000>;
+        qcom,sde-dspp-gamut = <0x1600 0x00010000>;
+        qcom,sde-dspp-dither = <0x0 0x00010000>;
+        qcom,sde-dspp-hist = <0x0 0x00010000>;
+        qcom,sde-dspp-vlut = <0x0 0x00010000>;
+    };
+
+    qcom,sde-mixer-blocks {
+        qcom,sde-mixer-gc = <0x3c0 0x00010000>;
+    };
+
     qcom,platform-supply-entries {
        #address-cells = <1>;
        #size-cells = <0>;
diff --git a/arch/arm/boot/dts/qcom/msm8996-sde.dtsi b/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
index 513788af9b09..de61b0269f6d 100644
--- a/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
@@ -58,6 +58,8 @@
 		qcom,sde-mixer-off = <0x45000 0x46000 0x47000
 				      0x48000 0x49000 0x4a000>;
 		qcom,sde-dspp-off = <0x55000 0x57000>;
+		qcom,sde-dspp-ad-off = <0x24000 0x22800>;
+		qcom,sde-dspp-ad-version = <0x00030000>;
 		qcom,sde-wb-off = <0x66000>;
 		qcom,sde-wb-id = <2>;
 		qcom,sde-wb-xin-id = <6>;
@@ -92,9 +94,7 @@
 				  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
 				  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
 				  <0x3b0 16>;
-		qcom,sde-sspp-csc-off = <0x320>;
 		qcom,sde-qseed-type = "qseedv2";
-		qcom,sde-sspp-qseed-off = <0x200>;
 		qcom,sde-mixer-linewidth = <2560>;
 		qcom,sde-sspp-linewidth = <2560>;
 		qcom,sde-mixer-blendstages = <0x7>;
@@ -119,6 +119,36 @@
 		mmagic-supply = <&gdsc_mmagic_mdss>;
 		vdd-supply = <&gdsc_mdss>;
 
+		qcom,sde-sspp-vig-blocks {
+			qcom,sde-vig-csc-off = <0x320>;
+			qcom,sde-vig-qseed-off = <0x200>;
+			/* Offset from vig top, version of HSIC */
+			qcom,sde-vig-hsic = <0x200 0x00010007>;
+			qcom,sde-vig-memcolor = <0x200 0x00010007>;
+			qcom,sde-vig-pcc = <0x1780 0x00010007>;
+		};
+
+		qcom,sde-sspp-rgb-blocks {
+			qcom,sde-rgb-scaler-off = <0x200>;
+			qcom,sde-rgb-pcc = <0x380 0x00010007>;
+		};
+
+		qcom,sde-dspp-blocks {
+			qcom,sde-dspp-pcc = <0x1700 0x00010007>;
+			qcom,sde-dspp-gc = <0x17c0 0x00010007>;
+			qcom,sde-dspp-hsic = <0x0 0x00010007>;
+			qcom,sde-dspp-memcolor = <0x0 0x00010007>;
+			qcom,sde-dspp-sixzone = <0x0 0x00010007>;
+			qcom,sde-dspp-gamut = <0x1600 0x00010007>;
+			qcom,sde-dspp-dither = <0x0 0x00010007>;
+			qcom,sde-dspp-hist = <0x0 0x00010007>;
+			qcom,sde-dspp-vlut = <0x0 0x00010007>;
+		};
+
+		qcom,sde-mixer-blocks {
+			qcom,sde-mixer-gc = <0x3c0 0x00010007>;
+		};
+
 		qcom,platform-supply-entries {
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index 5460aa32a37e..f8c753d2a8dd 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -74,12 +74,16 @@
 #define DEFAULT_CREQ_LUT_NRT		0x0
 #define DEFAULT_PIXEL_RAM_SIZE		(50 * 1024)
 
+/* Access 2D array element in a 1D array memory allocation */
+#define PROP_VALUE_ACCESS(p, i, j)	(*(p + i * MAX_SDE_HW_BLK + j))
+
 /*************************************************************
  *  DTSI PROPERTY INDEX
  *************************************************************/
 enum {
 	HW_OFF,
 	HW_LEN,
+	HW_PROP_MAX,
 };
 
 enum sde_prop {
@@ -94,6 +98,7 @@ enum sde_prop {
 	PANIC_PER_PIPE,
 	CDP,
 	SRC_SPLIT,
+	SDE_PROP_MAX,
 };
 
 enum {
@@ -107,8 +112,24 @@ enum {
 	SSPP_SAFE,
 	SSPP_MAX_RECTS,
 	SSPP_SCALE_SIZE,
-	SSPP_QSEED_OFF,
-	SSPP_CSC_OFF,
+	SSPP_VIG_BLOCKS,
+	SSPP_RGB_BLOCKS,
+	SSPP_PROP_MAX,
+};
+
+enum {
+	VIG_QSEED_OFF,
+	VIG_CSC_OFF,
+	VIG_HSIC_PROP,
+	VIG_MEMCOLOR_PROP,
+	VIG_PCC_PROP,
+	VIG_PROP_MAX,
+};
+
+enum {
+	RGB_SCALER_OFF,
+	RGB_PCC_PROP,
+	RGB_PROP_MAX,
 };
 
 enum {
@@ -116,6 +137,7 @@ enum {
 	INTF_LEN,
 	INTF_PREFETCH,
 	INTF_TYPE,
+	INTF_PROP_MAX,
 };
 
 enum {
@@ -127,25 +149,46 @@ enum {
 	TE2_LEN,
 	DSC_OFF,
 	DSC_LEN,
+	PP_PROP_MAX,
 };
 
 enum {
 	DSPP_OFF,
 	DSPP_SIZE,
-	DSPP_IGC,
-	DSPP_PCC,
-	DSPP_GC,
-	DSPP_PA,
-	DSPP_GAMUT,
-	DSPP_DITHER,
-	DSPP_HIST,
-	DSPP_AD,
+	DSPP_BLOCKS,
+	DSPP_PROP_MAX,
+};
+
+enum {
+	DSPP_IGC_PROP,
+	DSPP_PCC_PROP,
+	DSPP_GC_PROP,
+	DSPP_HSIC_PROP,
+	DSPP_MEMCOLOR_PROP,
+	DSPP_SIXZONE_PROP,
+	DSPP_GAMUT_PROP,
+	DSPP_DITHER_PROP,
+	DSPP_HIST_PROP,
+	DSPP_VLUT_PROP,
+	DSPP_BLOCKS_PROP_MAX,
+};
+
+enum {
+	AD_OFF,
+	AD_VERSION,
+	AD_PROP_MAX,
 };
 
 enum {
 	MIXER_OFF,
 	MIXER_LEN,
-	MIXER_GC,
+	MIXER_BLOCKS,
+	MIXER_PROP_MAX,
+};
+
+enum {
+	MIXER_GC_PROP,
+	MIXER_BLOCKS_PROP_MAX,
 };
 
 enum {
@@ -154,6 +197,7 @@ enum {
 	WB_ID,
 	WB_XIN_ID,
 	WB_CLK_CTRL,
+	WB_PROP_MAX,
 };
 
 enum {
@@ -164,6 +208,7 @@ enum {
 	VBIF_DEFAULT_OT_WR_LIMIT,
 	VBIF_DYNAMIC_OT_RD_LIMIT,
 	VBIF_DYNAMIC_OT_WR_LIMIT,
+	VBIF_PROP_MAX,
 };
 
 /*************************************************************
@@ -176,6 +221,7 @@ enum prop_type {
 	PROP_TYPE_STRING,
 	PROP_TYPE_STRING_ARRAY,
 	PROP_TYPE_BIT_OFFSET_ARRAY,
+	PROP_TYPE_NODE,
 };
 
 struct sde_prop_type {
@@ -222,8 +268,22 @@ static struct sde_prop_type sspp_prop[] = {
 	{SSPP_SAFE, "qcom,sde-sspp-safe-lut", false, PROP_TYPE_U32_ARRAY},
 	{SSPP_MAX_RECTS, "qcom,sde-sspp-max-rects", false, PROP_TYPE_U32_ARRAY},
 	{SSPP_SCALE_SIZE, "qcom,sde-sspp-scale-size", false, PROP_TYPE_U32},
-	{SSPP_QSEED_OFF, "qcom,sde-sspp-qseed-off", false, PROP_TYPE_U32},
-	{SSPP_CSC_OFF, "qcom,sde-sspp-csc-off", false, PROP_TYPE_U32},
+	{SSPP_VIG_BLOCKS, "qcom,sde-sspp-vig-blocks", false, PROP_TYPE_NODE},
+	{SSPP_RGB_BLOCKS, "qcom,sde-sspp-rgb-blocks", false, PROP_TYPE_NODE},
+};
+
+static struct sde_prop_type vig_prop[] = {
+	{VIG_QSEED_OFF, "qcom,sde-vig-qseed-off", false, PROP_TYPE_U32},
+	{VIG_CSC_OFF, "qcom,sde-vig-csc-off", false, PROP_TYPE_U32},
+	{VIG_HSIC_PROP, "qcom,sde-vig-hsic", false, PROP_TYPE_U32_ARRAY},
+	{VIG_MEMCOLOR_PROP, "qcom,sde-vig-memcolor", false,
+		PROP_TYPE_U32_ARRAY},
+	{VIG_PCC_PROP, "qcom,sde-vig-pcc", false, PROP_TYPE_U32_ARRAY},
+};
+
+static struct sde_prop_type rgb_prop[] = {
+	{RGB_SCALER_OFF, "qcom,sde-rgb-scaler-off", false, PROP_TYPE_U32},
+	{RGB_PCC_PROP, "qcom,sde-rgb-pcc", false, PROP_TYPE_U32_ARRAY},
 };
 
 static struct sde_prop_type ctl_prop[] = {
@@ -234,20 +294,37 @@ static struct sde_prop_type ctl_prop[] = {
 static struct sde_prop_type mixer_prop[] = {
 	{MIXER_OFF, "qcom,sde-mixer-off", true, PROP_TYPE_U32_ARRAY},
 	{MIXER_LEN, "qcom,sde-mixer-size", false, PROP_TYPE_U32},
-	{MIXER_GC, "qcom,sde-has-mixer-gc", false, PROP_TYPE_BOOL},
+	{MIXER_BLOCKS, "qcom,sde-mixer-blocks", false, PROP_TYPE_NODE},
+};
+
+static struct sde_prop_type mixer_blocks_prop[] = {
+	{MIXER_GC_PROP, "qcom,sde-mixer-gc", false, PROP_TYPE_U32_ARRAY},
 };
 
 static struct sde_prop_type dspp_prop[] = {
 	{DSPP_OFF, "qcom,sde-dspp-off", true, PROP_TYPE_U32_ARRAY},
 	{DSPP_SIZE, "qcom,sde-dspp-size", false, PROP_TYPE_U32},
-	{DSPP_IGC, "qcom,sde-dspp-igc-off", false, PROP_TYPE_U32},
-	{DSPP_PCC, "qcom,sde-dspp-pcc-off", false, PROP_TYPE_U32},
-	{DSPP_GC, "qcom,sde-dspp-gc-off", false, PROP_TYPE_U32},
-	{DSPP_PA, "qcom,sde-dspp-pa-off", false, PROP_TYPE_U32},
-	{DSPP_GAMUT, "qcom,sde-dspp-gamut-off", false, PROP_TYPE_U32},
-	{DSPP_DITHER, "qcom,sde-dspp-dither-off", false, PROP_TYPE_U32},
-	{DSPP_HIST, "qcom,sde-dspp-hist-off", false, PROP_TYPE_U32},
-	{DSPP_AD, "qcom,sde-dspp-ad-off", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_BLOCKS, "qcom,sde-dspp-blocks", false, PROP_TYPE_NODE},
+};
+
+static struct sde_prop_type dspp_blocks_prop[] = {
+	{DSPP_IGC_PROP, "qcom,sde-dspp-igc", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_PCC_PROP, "qcom,sde-dspp-pcc", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_GC_PROP, "qcom,sde-dspp-gc", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_HSIC_PROP, "qcom,sde-dspp-hsic", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_MEMCOLOR_PROP, "qcom,sde-dspp-memcolor", false,
+		PROP_TYPE_U32_ARRAY},
+	{DSPP_SIXZONE_PROP, "qcom,sde-dspp-sixzone", false,
+		PROP_TYPE_U32_ARRAY},
+	{DSPP_GAMUT_PROP, "qcom,sde-dspp-gamut", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_DITHER_PROP, "qcom,sde-dspp-dither", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_HIST_PROP, "qcom,sde-dspp-hist", false, PROP_TYPE_U32_ARRAY},
+	{DSPP_VLUT_PROP, "qcom,sde-dspp-vlut", false, PROP_TYPE_U32_ARRAY},
+};
+
+static struct sde_prop_type ad_prop[] = {
+	{AD_OFF, "qcom,sde-dspp-ad-off", false, PROP_TYPE_U32_ARRAY},
+	{AD_VERSION, "qcom,sde-dspp-ad-version", false, PROP_TYPE_U32},
 };
 
 static struct sde_prop_type pp_prop[] = {
@@ -350,18 +427,21 @@ static int _validate_dt_entry(struct device_node *np,
 	int *off_count)
 {
 	int rc = 0, i, val;
-
-	*off_count = of_property_count_u32_elems(np, sde_prop[0].prop_name);
-	if ((*off_count > MAX_BLOCKS) || (*off_count < 0)) {
-		*off_count = 0;
-
-		if (sde_prop[0].is_mandatory) {
-			SDE_ERROR("invalid hw offset prop name:%s count:%d\n",
+	struct device_node *snp = NULL;
+
+	if (off_count) {
+		*off_count = of_property_count_u32_elems(np,
+				sde_prop[0].prop_name);
+		if ((*off_count > MAX_BLOCKS) || (*off_count < 0)) {
+			if (sde_prop[0].is_mandatory) {
+				SDE_ERROR("invalid hw offset prop name:%s\"\
+					  count: %d\n",
 					sde_prop[0].prop_name, *off_count);
-			rc = -EINVAL;
+				rc = -EINVAL;
+			}
+			*off_count = 0;
+			return rc;
 		}
-
-		return rc;
 	}
 
 	for (i = 0; i < prop_size && i < MAX_BLOCKS; i++) {
@@ -373,15 +453,25 @@ static int _validate_dt_entry(struct device_node *np,
 		case PROP_TYPE_U32_ARRAY:
 			prop_count[i] = of_property_count_u32_elems(np,
 				sde_prop[i].prop_name);
+			if (prop_count[i] < 0)
+				rc = prop_count[i];
 			break;
 		case PROP_TYPE_STRING_ARRAY:
 			prop_count[i] = of_property_count_strings(np,
 				sde_prop[i].prop_name);
+			if (prop_count[i] < 0)
+				rc = prop_count[i];
 			break;
 		case PROP_TYPE_BIT_OFFSET_ARRAY:
 			of_get_property(np, sde_prop[i].prop_name, &val);
 			prop_count[i] = val / (MAX_BIT_OFFSET * sizeof(u32));
 			break;
+		case PROP_TYPE_NODE:
+			snp = of_get_child_by_name(np,
+					sde_prop[i].prop_name);
+			if (!snp)
+				rc = -EINVAL;
+			break;
 		default:
 			SDE_DEBUG("invalid property type:%d\n",
 							sde_prop[i].type);
@@ -392,29 +482,44 @@ static int _validate_dt_entry(struct device_node *np,
 			sde_prop[i].type, prop_count[i]);
 
 		if (rc && sde_prop[i].is_mandatory &&
-		   (sde_prop[i].type == PROP_TYPE_U32)) {
+		   ((sde_prop[i].type == PROP_TYPE_U32) ||
+		    (sde_prop[i].type == PROP_TYPE_NODE))) {
 			SDE_ERROR("prop:%s not present\n",
 						sde_prop[i].prop_name);
 			goto end;
 		} else if (sde_prop[i].type == PROP_TYPE_U32 ||
-			sde_prop[i].type == PROP_TYPE_BOOL) {
+			sde_prop[i].type == PROP_TYPE_BOOL ||
+			sde_prop[i].type == PROP_TYPE_NODE) {
 			rc = 0;
 			continue;
 		}
 
-		if ((prop_count[i] != *off_count) && sde_prop[i].is_mandatory) {
+		if (off_count && (prop_count[i] != *off_count) &&
+				sde_prop[i].is_mandatory) {
 			SDE_ERROR("prop:%s count:%d is different compared to \"\
 				offset array:%d\n", sde_prop[i].prop_name,
 				prop_count[i], *off_count);
 			rc = -EINVAL;
 			goto end;
-		} else if (prop_count[i] != *off_count) {
+		} else if (off_count && prop_count[i] != *off_count) {
 			SDE_DEBUG("prop:%s count:%d is different compared to \"\
 				offset array:%d\n", sde_prop[i].prop_name,
 				prop_count[i], *off_count);
 			rc = 0;
 			prop_count[i] = 0;
 		}
+		if (!off_count && prop_count[i] < 0) {
+			prop_count[i] = 0;
+			if (sde_prop[i].is_mandatory) {
+				SDE_ERROR("prop:%s count:%d is negative\n",
+					sde_prop[i].prop_name, prop_count[i]);
+				rc = -EINVAL;
+			} else {
+				rc = 0;
+				SDE_DEBUG("prop:%s count:%d is negative\n",
+					sde_prop[i].prop_name, prop_count[i]);
+			}
+		}
 	}
 
 end:
@@ -422,44 +527,55 @@ end:
 }
 
 static int _read_dt_entry(struct device_node *np,
-	struct sde_prop_type *sde_prop, u32 prop_size, u32 *prop_count,
-	u32 prop_value[][MAX_SDE_HW_BLK],
+	struct sde_prop_type *sde_prop, u32 prop_size, int *prop_count,
+	bool *prop_exists,
+	u32 *prop_value,
 	u32 bit_value[][MAX_SDE_HW_BLK][MAX_BIT_OFFSET])
 {
 	int rc = 0, i, j;
 
 	for (i = 0; i < prop_size && i < MAX_BLOCKS; i++) {
+		prop_exists[i] = true;
 		switch (sde_prop[i].type) {
 		case PROP_TYPE_U32:
-			of_property_read_u32(np, sde_prop[i].prop_name,
-				&prop_value[i][0]);
+			rc = of_property_read_u32(np, sde_prop[i].prop_name,
+				&PROP_VALUE_ACCESS(prop_value, i, 0));
 			SDE_DEBUG("prop id:%d prop name:%s prop type:%d \"\
 				 value:0x%x\n", i, sde_prop[i].prop_name,
-				sde_prop[i].type, prop_value[i][0]);
+				sde_prop[i].type,
+				PROP_VALUE_ACCESS(prop_value, i, 0));
+			if (rc)
+				prop_exists[i] = false;
 			break;
 		case PROP_TYPE_BOOL:
-			prop_value[i][0] =  of_property_read_bool(np,
-				sde_prop[i].prop_name);
+			PROP_VALUE_ACCESS(prop_value, i, 0) =
+				of_property_read_bool(np,
+					sde_prop[i].prop_name);
 			SDE_DEBUG("prop id:%d prop name:%s prop type:%d \"\
 				value:0x%x\n", i, sde_prop[i].prop_name,
-				sde_prop[i].type, prop_value[i][0]);
+				sde_prop[i].type,
+				PROP_VALUE_ACCESS(prop_value, i, 0));
 			break;
 		case PROP_TYPE_U32_ARRAY:
 			rc = _parse_dt_u32_handler(np, sde_prop[i].prop_name,
-				prop_value[i], prop_count[i],
-				sde_prop[i].is_mandatory);
+				&PROP_VALUE_ACCESS(prop_value, i, 0),
+				prop_count[i], sde_prop[i].is_mandatory);
 			if (rc && sde_prop[i].is_mandatory) {
 				SDE_ERROR("%s prop validation success but \"\
 					read failed\n", sde_prop[i].prop_name);
+				prop_exists[i] = false;
 				goto end;
 			} else {
+				if (rc)
+					prop_exists[i] = false;
 				/* only for debug purpose */
 				SDE_DEBUG("prop id:%d prop name:%s prop \"\
 					type:%d", i, sde_prop[i].prop_name,
 					sde_prop[i].type);
 				for (j = 0; j < prop_count[i]; j++)
 					SDE_DEBUG(" value[%d]:0x%x ", j,
-							prop_value[i][j]);
+						PROP_VALUE_ACCESS(prop_value, i,
+								j));
 				SDE_DEBUG("\n");
 			}
 			break;
@@ -470,8 +586,11 @@ static int _read_dt_entry(struct device_node *np,
 			if (rc && sde_prop[i].is_mandatory) {
 				SDE_ERROR("%s prop validation success but \"\
 					read failed\n", sde_prop[i].prop_name);
+				prop_exists[i] = false;
 				goto end;
 			} else {
+				if (rc)
+					prop_exists[i] = false;
 				SDE_DEBUG("prop id:%d prop name:%s prop \"\
 					type:%d", i, sde_prop[i].prop_name,
 					sde_prop[i].type);
@@ -482,6 +601,10 @@ static int _read_dt_entry(struct device_node *np,
 				SDE_DEBUG("\n");
 			}
 			break;
+		case PROP_TYPE_NODE:
+			/* Node will be parsed in calling function */
+			rc = 0;
+			break;
 		default:
 			SDE_DEBUG("invalid property type:%d\n",
 							sde_prop[i].type);
@@ -496,58 +619,107 @@ end:
 
 static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg,
 	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
-	u32 prop_value[][MAX_SDE_HW_BLK], u32 *vig_count)
+	bool *prop_exists, u32 *prop_value, u32 *vig_count)
 {
+	sblk->maxupscale = MAX_SSPP_UPSCALE;
+	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
+	sspp->id = SSPP_VIG0 + *vig_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_VIG0 + *vig_count;
+	sblk->format_list = plane_formats_yuv;
+	set_bit(SDE_SSPP_QOS, &sspp->features);
+	(*vig_count)++;
+
+	if (!prop_value)
+		return;
+
 	if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) {
 		set_bit(SDE_SSPP_SCALER_QSEED2, &sspp->features);
 		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;
-		sblk->scaler_blk.base = prop_value[SSPP_QSEED_OFF][0];
+		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_QSEED_OFF, 0);
 	 } else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {
 		set_bit(SDE_SSPP_SCALER_QSEED3, &sspp->features);
 		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;
-		sblk->scaler_blk.base = prop_value[SSPP_QSEED_OFF][0];
+		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_QSEED_OFF, 0);
 	}
 
-	set_bit(SDE_SSPP_CSC, &sspp->features);
-	sblk->csc_blk.base = prop_value[SSPP_CSC_OFF][0];
 	sblk->csc_blk.id = SDE_SSPP_CSC;
+	set_bit(SDE_SSPP_CSC, &sspp->features);
+	sblk->csc_blk.base = PROP_VALUE_ACCESS(prop_value, VIG_CSC_OFF, 0);
+
+	sblk->hsic_blk.id = SDE_SSPP_HSIC;
+	if (prop_exists[VIG_HSIC_PROP]) {
+		sblk->hsic_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_HSIC_PROP, 0);
+		sblk->hsic_blk.version = PROP_VALUE_ACCESS(prop_value,
+			VIG_HSIC_PROP, 1);
+		sblk->hsic_blk.len = 0;
+		set_bit(SDE_SSPP_HSIC, &sspp->features);
+	}
 
-	sblk->maxupscale = MAX_SSPP_UPSCALE;
-	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
-	sspp->id = SSPP_VIG0 + *vig_count;
-	sspp->clk_ctrl = SDE_CLK_CTRL_VIG0 + *vig_count;
+	sblk->memcolor_blk.id = SDE_SSPP_MEMCOLOR;
+	if (prop_exists[VIG_MEMCOLOR_PROP]) {
+		sblk->memcolor_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_MEMCOLOR_PROP, 0);
+		sblk->memcolor_blk.version = PROP_VALUE_ACCESS(prop_value,
+			VIG_MEMCOLOR_PROP, 1);
+		sblk->memcolor_blk.len = 0;
+		set_bit(SDE_SSPP_MEMCOLOR, &sspp->features);
+	}
 
-	sblk->format_list = plane_formats_yuv;
-	set_bit(SDE_SSPP_QOS, &sspp->features);
-	(*vig_count)++;
+	sblk->pcc_blk.id = SDE_SSPP_PCC;
+	if (prop_exists[VIG_PCC_PROP]) {
+		sblk->pcc_blk.base = PROP_VALUE_ACCESS(prop_value,
+			VIG_PCC_PROP, 0);
+		sblk->pcc_blk.version = PROP_VALUE_ACCESS(prop_value,
+			VIG_PCC_PROP, 1);
+		sblk->pcc_blk.len = 0;
+		set_bit(SDE_SSPP_PCC, &sspp->features);
+	}
 }
 
 static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg,
 	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
-	u32 prop_value[][MAX_SDE_HW_BLK], u32 *rgb_count)
+	bool *prop_exists, u32 *prop_value, u32 *rgb_count)
 {
+	sblk->maxupscale = MAX_SSPP_UPSCALE;
+	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
+	sspp->id = SSPP_RGB0 + *rgb_count;
+	sspp->clk_ctrl = SDE_CLK_CTRL_RGB0 + *rgb_count;
+	sblk->format_list = plane_formats;
+	set_bit(SDE_SSPP_QOS, &sspp->features);
+	(*rgb_count)++;
+
+	if (!prop_value)
+		return;
+
 	if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) {
 		set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
 		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;
-		sblk->scaler_blk.base = prop_value[SSPP_QSEED_OFF][0];
+		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
+			RGB_SCALER_OFF, 0);
 	} else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {
 		set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
 		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;
-		sblk->scaler_blk.base = prop_value[SSPP_QSEED_OFF][0];
+		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,
+			RGB_SCALER_OFF, 0);
 	}
 
-	sblk->maxupscale = MAX_SSPP_UPSCALE;
-	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;
-	sspp->id = SSPP_RGB0 + *rgb_count;
-	sspp->clk_ctrl = SDE_CLK_CTRL_RGB0 + *rgb_count;
-	sblk->format_list = plane_formats;
-	set_bit(SDE_SSPP_QOS, &sspp->features);
-	(*rgb_count)++;
+	sblk->pcc_blk.id = SDE_SSPP_PCC;
+	if (prop_exists[RGB_PCC_PROP]) {
+		sblk->pcc_blk.base = PROP_VALUE_ACCESS(prop_value,
+			RGB_PCC_PROP, 0);
+		sblk->pcc_blk.version = PROP_VALUE_ACCESS(prop_value,
+			RGB_PCC_PROP, 1);
+		sblk->pcc_blk.len = 0;
+		set_bit(SDE_SSPP_PCC, &sspp->features);
+	}
 }
 
 static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg,
 	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
-	u32 prop_value[][MAX_SDE_HW_BLK], u32 *cursor_count)
+	u32 *prop_value, u32 *cursor_count)
 {
 	set_bit(SDE_SSPP_CURSOR, &sspp->features);
 	sblk->maxupscale = SSPP_UNITY_SCALE;
@@ -560,7 +732,7 @@ static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg,
 
 static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg,
 	struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
-	u32 prop_value[][MAX_SDE_HW_BLK], u32 *dma_count)
+	u32 *prop_value, u32 *dma_count)
 {
 	sblk->maxupscale = SSPP_UNITY_SCALE;
 	sblk->maxdwnscale = SSPP_UNITY_SCALE;
@@ -574,14 +746,25 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg,
 static int sde_sspp_parse_dt(struct device_node *np,
 	struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], off_count, i, j;
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK];
+	int rc, prop_count[SSPP_PROP_MAX], off_count, i, j;
+	int vig_prop_count[VIG_PROP_MAX], rgb_prop_count[RGB_PROP_MAX];
+	bool prop_exists[SSPP_PROP_MAX], vig_prop_exists[VIG_PROP_MAX];
+	bool rgb_prop_exists[RGB_PROP_MAX];
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET];
+	u32 *prop_value = NULL, *vig_prop_value = NULL, *rgb_prop_value = NULL;
 	const char *type;
 	struct sde_sspp_cfg *sspp;
 	struct sde_sspp_sub_blks *sblk;
 	u32 vig_count = 0, dma_count = 0, rgb_count = 0, cursor_count = 0;
 	u32 danger_count = 0, safe_count = 0;
+	struct device_node *snp = NULL;
+
+	prop_value = kzalloc(SSPP_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
 
 	rc = _validate_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop),
 		prop_count, &off_count);
@@ -599,12 +782,48 @@ static int sde_sspp_parse_dt(struct device_node *np,
 		goto end;
 
 	rc = _read_dt_entry(np, sspp_prop, ARRAY_SIZE(sspp_prop), prop_count,
-							prop_value, bit_value);
+					prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
 	sde_cfg->sspp_count = off_count;
 
+	/* get vig feature dt properties if they exist */
+	snp = of_get_child_by_name(np, sspp_prop[SSPP_VIG_BLOCKS].prop_name);
+	if (snp) {
+		vig_prop_value = kzalloc(VIG_PROP_MAX * MAX_SDE_HW_BLK *
+			sizeof(u32), GFP_KERNEL);
+		if (!vig_prop_value) {
+			rc = -ENOMEM;
+			goto end;
+		}
+		rc = _validate_dt_entry(snp, vig_prop, ARRAY_SIZE(vig_prop),
+			vig_prop_count, NULL);
+		if (rc)
+			goto end;
+		rc = _read_dt_entry(snp, vig_prop, ARRAY_SIZE(vig_prop),
+				vig_prop_count, vig_prop_exists, vig_prop_value,
+				NULL);
+	}
+
+	/* get rgb feature dt properties if they exist */
+	snp = of_get_child_by_name(np, sspp_prop[SSPP_RGB_BLOCKS].prop_name);
+	if (snp) {
+		rgb_prop_value = kzalloc(RGB_PROP_MAX * MAX_SDE_HW_BLK *
+					sizeof(u32), GFP_KERNEL);
+		if (!rgb_prop_value) {
+			rc = -ENOMEM;
+			goto end;
+		}
+		rc = _validate_dt_entry(snp, rgb_prop, ARRAY_SIZE(rgb_prop),
+			rgb_prop_count, NULL);
+		if (rc)
+			goto end;
+		rc = _read_dt_entry(snp, rgb_prop, ARRAY_SIZE(rgb_prop),
+				rgb_prop_count, rgb_prop_exists, rgb_prop_value,
+				NULL);
+	}
+
 	for (i = 0; i < off_count; i++) {
 		sspp = sde_cfg->sspp + i;
 		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
@@ -615,7 +834,7 @@ static int sde_sspp_parse_dt(struct device_node *np,
 		}
 		sspp->sblk = sblk;
 
-		sspp->base = prop_value[SSPP_OFF][i];
+		sspp->base = PROP_VALUE_ACCESS(prop_value, SSPP_OFF, i);
 		sblk->maxlinewidth = sde_cfg->max_sspp_linewidth;
 
 		set_bit(SDE_SSPP_SRC, &sspp->features);
@@ -624,16 +843,18 @@ static int sde_sspp_parse_dt(struct device_node *np,
 		of_property_read_string_index(np,
 				sspp_prop[SSPP_TYPE].prop_name, i, &type);
 		if (!strcmp(type, "vig")) {
-			_sde_sspp_setup_vig(sde_cfg, sspp, sblk, prop_value,
-								&vig_count);
+			_sde_sspp_setup_vig(sde_cfg, sspp, sblk,
+				vig_prop_exists, vig_prop_value, &vig_count);
 		} else if (!strcmp(type, "rgb")) {
-			_sde_sspp_setup_rgb(sde_cfg, sspp, sblk, prop_value,
-								&rgb_count);
+			_sde_sspp_setup_rgb(sde_cfg, sspp, sblk,
+				rgb_prop_exists, rgb_prop_value, &rgb_count);
 		} else if (!strcmp(type, "cursor")) {
-			_sde_sspp_setup_cursor(sde_cfg, sspp, sblk, prop_value,
+			/* No prop values for cursor pipes */
+			_sde_sspp_setup_cursor(sde_cfg, sspp, sblk, NULL,
 								&cursor_count);
 		} else if (!strcmp(type, "dma")) {
-			_sde_sspp_setup_dma(sde_cfg, sspp, sblk, prop_value,
+			/* No prop values for DMA pipes */
+			_sde_sspp_setup_dma(sde_cfg, sspp, sblk, NULL,
 								&dma_count);
 		} else {
 			SDE_ERROR("invalid sspp type:%s\n", type);
@@ -644,16 +865,22 @@ static int sde_sspp_parse_dt(struct device_node *np,
 		sblk->maxhdeciexp = MAX_HORZ_DECIMATION;
 		sblk->maxvdeciexp = MAX_VERT_DECIMATION;
 
-		sspp->xin_id = prop_value[SSPP_XIN][i];
-		sblk->danger_lut_linear = prop_value[SSPP_DANGER][0];
-		sblk->danger_lut_tile = prop_value[SSPP_DANGER][1];
-		sblk->danger_lut_nrt = prop_value[SSPP_DANGER][2];
-		sblk->safe_lut_linear = prop_value[SSPP_SAFE][0];
-		sblk->safe_lut_tile = prop_value[SSPP_SAFE][1];
-		sblk->safe_lut_nrt = prop_value[SSPP_SAFE][2];
+		sspp->xin_id = PROP_VALUE_ACCESS(prop_value, SSPP_XIN, i);
+		sblk->danger_lut_linear =
+			PROP_VALUE_ACCESS(prop_value, SSPP_DANGER, 0);
+		sblk->danger_lut_tile =
+			PROP_VALUE_ACCESS(prop_value, SSPP_DANGER, 1);
+		sblk->danger_lut_nrt =
+			PROP_VALUE_ACCESS(prop_value, SSPP_DANGER, 2);
+		sblk->safe_lut_linear =
+			PROP_VALUE_ACCESS(prop_value, SSPP_SAFE, 0);
+		sblk->safe_lut_tile =
+			PROP_VALUE_ACCESS(prop_value, SSPP_SAFE, 1);
+		sblk->safe_lut_nrt =
+			PROP_VALUE_ACCESS(prop_value, SSPP_SAFE, 2);
 		sblk->creq_lut_nrt = DEFAULT_CREQ_LUT_NRT;
 		sblk->pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE;
-		sblk->src_blk.len = prop_value[SSPP_SIZE][0];
+		sblk->src_blk.len = PROP_VALUE_ACCESS(prop_value, SSPP_SIZE, 0);
 
 		for (j = 0; j < sde_cfg->mdp_count; j++) {
 			sde_cfg->mdp[j].clk_ctrls[sspp->clk_ctrl].reg_off =
@@ -679,14 +906,18 @@ static int sde_sspp_parse_dt(struct device_node *np,
 	}
 
 end:
+	kfree(prop_value);
+	kfree(vig_prop_value);
+	kfree(rgb_prop_value);
 	return rc;
 }
 
 static int sde_ctl_parse_dt(struct device_node *np,
 		struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], i;
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { {0} };
+	int rc, prop_count[HW_PROP_MAX], i;
+	bool prop_exists[HW_PROP_MAX];
+	u32 *prop_value = NULL;
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 				= { { { 0 } } };
 	struct sde_ctl_cfg *ctl;
@@ -698,6 +929,13 @@ static int sde_ctl_parse_dt(struct device_node *np,
 		goto end;
 	}
 
+	prop_value = kzalloc(HW_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
 	rc = _validate_dt_entry(np, ctl_prop, ARRAY_SIZE(ctl_prop), prop_count,
 		&off_count);
 	if (rc)
@@ -706,13 +944,13 @@ static int sde_ctl_parse_dt(struct device_node *np,
 	sde_cfg->ctl_count = off_count;
 
 	rc = _read_dt_entry(np, ctl_prop, ARRAY_SIZE(ctl_prop), prop_count,
-		prop_value, bit_value);
+		prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
 	for (i = 0; i < off_count; i++) {
 		ctl = sde_cfg->ctl + i;
-		ctl->base = prop_value[HW_OFF][i];
+		ctl->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);
 		ctl->id = CTL_0 + i;
 
 		if (i < MAX_SPLIT_DISPLAY_CTL)
@@ -722,17 +960,20 @@ static int sde_ctl_parse_dt(struct device_node *np,
 	}
 
 end:
+	kfree(prop_value);
 	return rc;
 }
 
 static int sde_mixer_parse_dt(struct device_node *np,
 						struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], i;
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	int rc, prop_count[MIXER_PROP_MAX], i;
+	int blocks_prop_count[MIXER_BLOCKS_PROP_MAX];
+	bool prop_exists[MIXER_PROP_MAX];
+	bool blocks_prop_exists[MIXER_BLOCKS_PROP_MAX];
+	u32 *prop_value = NULL, *blocks_prop_value = NULL;
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 				= { { { 0 } } };
-
 	u32 off_count, max_blendstages;
 	u32 blend_reg_base[] = {0x20, 0x50, 0x80, 0xb0, 0x230, 0x260, 0x290};
 	u32 lm_pair_mask[] = {LM_1, LM_0, LM_5, 0x0, 0x0, LM_2};
@@ -740,6 +981,7 @@ static int sde_mixer_parse_dt(struct device_node *np,
 	struct sde_lm_sub_blks *sblk;
 	int pp_count, dspp_count;
 	u32 pp_idx, dspp_idx;
+	struct device_node *snp = NULL;
 
 	if (!sde_cfg) {
 		SDE_ERROR("invalid argument input param\n");
@@ -748,6 +990,13 @@ static int sde_mixer_parse_dt(struct device_node *np,
 	}
 	max_blendstages = sde_cfg->max_mixer_blendstages;
 
+	prop_value = kzalloc(MIXER_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
 	rc = _validate_dt_entry(np, mixer_prop, ARRAY_SIZE(mixer_prop),
 		prop_count, &off_count);
 	if (rc)
@@ -756,13 +1005,32 @@ static int sde_mixer_parse_dt(struct device_node *np,
 	sde_cfg->mixer_count = off_count;
 
 	rc = _read_dt_entry(np, mixer_prop, ARRAY_SIZE(mixer_prop), prop_count,
-		prop_value, bit_value);
+		prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
 	pp_count = sde_cfg->pingpong_count;
 	dspp_count = sde_cfg->dspp_count;
 
+	/* get mixer feature dt properties if they exist */
+	snp = of_get_child_by_name(np, mixer_prop[MIXER_BLOCKS].prop_name);
+	if (snp) {
+		blocks_prop_value = kzalloc(MIXER_BLOCKS_PROP_MAX *
+				MAX_SDE_HW_BLK * sizeof(u32), GFP_KERNEL);
+		if (!blocks_prop_value) {
+			rc = -ENOMEM;
+			goto end;
+		}
+		rc = _validate_dt_entry(snp, mixer_blocks_prop,
+			ARRAY_SIZE(mixer_blocks_prop), blocks_prop_count, NULL);
+		if (rc)
+			goto end;
+		rc = _read_dt_entry(snp, mixer_blocks_prop,
+				ARRAY_SIZE(mixer_blocks_prop),
+				blocks_prop_count, blocks_prop_exists,
+				blocks_prop_value, NULL);
+	}
+
 	for (i = 0, pp_idx = 0, dspp_idx = 0; i < off_count; i++) {
 		mixer = sde_cfg->mixer + i;
 		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
@@ -773,10 +1041,10 @@ static int sde_mixer_parse_dt(struct device_node *np,
 		}
 		mixer->sblk = sblk;
 
-		mixer->base = prop_value[HW_OFF][i];
-		mixer->len = prop_value[HW_LEN][0];
+		mixer->base = PROP_VALUE_ACCESS(prop_value, MIXER_OFF, i);
+		mixer->len = PROP_VALUE_ACCESS(prop_value, MIXER_LEN, 0);
 		mixer->id = LM_0 + i;
-		if (!mixer->len)
+		if (!prop_exists[MIXER_LEN])
 			mixer->len = DEFAULT_SDE_HW_BLOCK_LEN;
 
 		if (lm_pair_mask[i])
@@ -789,8 +1057,6 @@ static int sde_mixer_parse_dt(struct device_node *np,
 			ARRAY_SIZE(blend_reg_base), max_blendstages)));
 		if (sde_cfg->has_src_split)
 			set_bit(SDE_MIXER_SOURCESPLIT, &mixer->features);
-		if (prop_value[MIXER_GC][0])
-			set_bit(SDE_MIXER_GC, &mixer->features);
 
 		if ((i < ROT_LM_OFFSET) || (i >= LINE_LM_OFFSET)) {
 			mixer->pingpong = pp_count > 0 ? pp_idx + PINGPONG_0
@@ -805,17 +1071,30 @@ static int sde_mixer_parse_dt(struct device_node *np,
 			mixer->pingpong = PINGPONG_MAX;
 			mixer->dspp = DSPP_MAX;
 		}
+
+		sblk->gc.id = SDE_MIXER_GC;
+		if (blocks_prop_value && blocks_prop_exists[MIXER_GC_PROP]) {
+			sblk->gc.base = PROP_VALUE_ACCESS(blocks_prop_value,
+					MIXER_GC_PROP, 0);
+			sblk->gc.version = PROP_VALUE_ACCESS(blocks_prop_value,
+					MIXER_GC_PROP, 1);
+			sblk->gc.len = 0;
+			set_bit(SDE_MIXER_GC, &mixer->features);
+		}
 	}
 
 end:
+	kfree(prop_value);
+	kfree(blocks_prop_value);
 	return rc;
 }
 
 static int sde_intf_parse_dt(struct device_node *np,
 						struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], i;
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	int rc, prop_count[INTF_PROP_MAX], i;
+	u32 *prop_value = NULL;
+	bool prop_exists[INTF_PROP_MAX];
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 					= { { { 0 } } };
 	u32 off_count;
@@ -829,6 +1108,13 @@ static int sde_intf_parse_dt(struct device_node *np,
 		goto end;
 	}
 
+	prop_value = kzalloc(INTF_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
 	rc = _validate_dt_entry(np, intf_prop, ARRAY_SIZE(intf_prop),
 		prop_count, &off_count);
 	if (rc)
@@ -837,20 +1123,20 @@ static int sde_intf_parse_dt(struct device_node *np,
 	sde_cfg->intf_count = off_count;
 
 	rc = _read_dt_entry(np, intf_prop, ARRAY_SIZE(intf_prop), prop_count,
-		prop_value, bit_value);
+		prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
 	for (i = 0; i < off_count; i++) {
 		intf = sde_cfg->intf + i;
-		intf->base = prop_value[INTF_OFF][i];
-		intf->len = prop_value[INTF_LEN][0];
+		intf->base = PROP_VALUE_ACCESS(prop_value, INTF_OFF, i);
+		intf->len = PROP_VALUE_ACCESS(prop_value, INTF_LEN, 0);
 		intf->id = INTF_0 + i;
-		if (!intf->len)
+		if (!prop_exists[INTF_LEN])
 			intf->len = DEFAULT_SDE_HW_BLOCK_LEN;
 
 		intf->prog_fetch_lines_worst_case =
-					prop_value[INTF_PREFETCH][i];
+				PROP_VALUE_ACCESS(prop_value, INTF_PREFETCH, i);
 
 		of_property_read_string_index(np,
 				intf_prop[INTF_TYPE].prop_name, i, &type);
@@ -874,13 +1160,15 @@ static int sde_intf_parse_dt(struct device_node *np,
 	}
 
 end:
+	kfree(prop_value);
 	return rc;
 }
 
 static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], i, j;
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	int rc, prop_count[WB_PROP_MAX], i, j;
+	u32 *prop_value = NULL;
+	bool prop_exists[WB_PROP_MAX];
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 					= { { { 0 } } };
 	u32 off_count;
@@ -893,6 +1181,13 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 		goto end;
 	}
 
+	prop_value = kzalloc(WB_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
 	rc = _validate_dt_entry(np, wb_prop, ARRAY_SIZE(wb_prop), prop_count,
 		&off_count);
 	if (rc)
@@ -901,7 +1196,7 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 	sde_cfg->wb_count = off_count;
 
 	rc = _read_dt_entry(np, wb_prop, ARRAY_SIZE(wb_prop), prop_count,
-		prop_value, bit_value);
+		prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
@@ -915,14 +1210,15 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 		}
 		wb->sblk = sblk;
 
-		wb->base = prop_value[WB_OFF][i];
-		wb->id = WB_0 + prop_value[WB_ID][i];
-		wb->clk_ctrl = SDE_CLK_CTRL_WB0 + prop_value[WB_ID][i];
-		wb->xin_id = prop_value[WB_XIN_ID][i];
+		wb->base = PROP_VALUE_ACCESS(prop_value, WB_OFF, i);
+		wb->id = WB_0 + PROP_VALUE_ACCESS(prop_value, WB_ID, i);
+		wb->clk_ctrl = SDE_CLK_CTRL_WB0 +
+			PROP_VALUE_ACCESS(prop_value, WB_ID, i);
+		wb->xin_id = PROP_VALUE_ACCESS(prop_value, WB_XIN_ID, i);
 		wb->vbif_idx = VBIF_NRT;
-		wb->len = prop_value[WB_LEN][0];
+		wb->len = PROP_VALUE_ACCESS(prop_value, WB_LEN, 0);
 		wb->format_list = wb2_formats;
-		if (!wb->len)
+		if (!prop_exists[WB_LEN])
 			wb->len = DEFAULT_SDE_HW_BLOCK_LEN;
 		sblk->maxlinewidth = sde_cfg->max_wb_linewidth;
 
@@ -951,19 +1247,130 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 	}
 
 end:
+	kfree(prop_value);
 	return rc;
 }
 
+static void _sde_dspp_setup_blocks(struct sde_mdss_cfg *sde_cfg,
+	struct sde_dspp_cfg *dspp, struct sde_dspp_sub_blks *sblk,
+	bool *prop_exists, u32 *prop_value)
+{
+	sblk->igc.id = SDE_DSPP_IGC;
+	if (prop_exists[DSPP_IGC_PROP]) {
+		sblk->igc.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_IGC_PROP, 0);
+		sblk->igc.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_IGC_PROP, 1);
+		sblk->igc.len = 0;
+		set_bit(SDE_DSPP_IGC, &dspp->features);
+	}
+
+	sblk->pcc.id = SDE_DSPP_PCC;
+	if (prop_exists[DSPP_PCC_PROP]) {
+		sblk->pcc.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_PCC_PROP, 0);
+		sblk->pcc.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_PCC_PROP, 1);
+		sblk->pcc.len = 0;
+		set_bit(SDE_DSPP_PCC, &dspp->features);
+	}
+
+	sblk->gc.id = SDE_DSPP_GC;
+	if (prop_exists[DSPP_GC_PROP]) {
+		sblk->gc.base = PROP_VALUE_ACCESS(prop_value, DSPP_GC_PROP, 0);
+		sblk->gc.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_GC_PROP, 1);
+		sblk->gc.len = 0;
+		set_bit(SDE_DSPP_GC, &dspp->features);
+	}
+
+	sblk->gamut.id = SDE_DSPP_GAMUT;
+	if (prop_exists[DSPP_GAMUT_PROP]) {
+		sblk->gamut.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_GAMUT_PROP, 0);
+		sblk->gamut.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_GAMUT_PROP, 1);
+		sblk->gamut.len = 0;
+		set_bit(SDE_DSPP_GAMUT, &dspp->features);
+	}
+
+	sblk->dither.id = SDE_DSPP_DITHER;
+	if (prop_exists[DSPP_DITHER_PROP]) {
+		sblk->dither.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_DITHER_PROP, 0);
+		sblk->dither.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_DITHER_PROP, 1);
+		sblk->dither.len = 0;
+		set_bit(SDE_DSPP_DITHER, &dspp->features);
+	}
+
+	sblk->hist.id = SDE_DSPP_HIST;
+	if (prop_exists[DSPP_HIST_PROP]) {
+		sblk->hist.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_HIST_PROP, 0);
+		sblk->hist.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_HIST_PROP, 1);
+		sblk->hist.len = 0;
+		set_bit(SDE_DSPP_HIST, &dspp->features);
+	}
+
+	sblk->hsic.id = SDE_DSPP_HSIC;
+	if (prop_exists[DSPP_HSIC_PROP]) {
+		sblk->hsic.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_HSIC_PROP, 0);
+		sblk->hsic.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_HSIC_PROP, 1);
+		sblk->hsic.len = 0;
+		set_bit(SDE_DSPP_HSIC, &dspp->features);
+	}
+
+	sblk->memcolor.id = SDE_DSPP_MEMCOLOR;
+	if (prop_exists[DSPP_MEMCOLOR_PROP]) {
+		sblk->memcolor.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_MEMCOLOR_PROP, 0);
+		sblk->memcolor.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_MEMCOLOR_PROP, 1);
+		sblk->memcolor.len = 0;
+		set_bit(SDE_DSPP_MEMCOLOR, &dspp->features);
+	}
+
+	sblk->sixzone.id = SDE_DSPP_SIXZONE;
+	if (prop_exists[DSPP_SIXZONE_PROP]) {
+		sblk->sixzone.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_SIXZONE_PROP, 0);
+		sblk->sixzone.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_SIXZONE_PROP, 1);
+		sblk->sixzone.len = 0;
+		set_bit(SDE_DSPP_SIXZONE, &dspp->features);
+	}
+
+	sblk->vlut.id = SDE_DSPP_VLUT;
+	if (prop_exists[DSPP_VLUT_PROP]) {
+		sblk->vlut.base = PROP_VALUE_ACCESS(prop_value,
+			DSPP_VLUT_PROP, 0);
+		sblk->vlut.version = PROP_VALUE_ACCESS(prop_value,
+			DSPP_VLUT_PROP, 1);
+		sblk->sixzone.len = 0;
+		set_bit(SDE_DSPP_VLUT, &dspp->features);
+	}
+}
+
 static int sde_dspp_parse_dt(struct device_node *np,
 						struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], i;
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	int rc, prop_count[DSPP_PROP_MAX], i;
+	int ad_prop_count[AD_PROP_MAX];
+	bool prop_exists[DSPP_PROP_MAX], ad_prop_exists[AD_PROP_MAX];
+	bool blocks_prop_exists[DSPP_BLOCKS_PROP_MAX];
+	u32 *ad_prop_value = NULL;
+	int blocks_prop_count[DSPP_BLOCKS_PROP_MAX];
+	u32 *prop_value = NULL, *blocks_prop_value = NULL;
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 				= { { { 0 } } };
-	u32 off_count;
+	u32 off_count, ad_off_count;
 	struct sde_dspp_cfg *dspp;
 	struct sde_dspp_sub_blks *sblk;
+	struct device_node *snp = NULL;
 
 	if (!sde_cfg) {
 		SDE_ERROR("invalid argument\n");
@@ -971,6 +1378,13 @@ static int sde_dspp_parse_dt(struct device_node *np,
 		goto end;
 	}
 
+	prop_value = kzalloc(DSPP_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
 	rc = _validate_dt_entry(np, dspp_prop, ARRAY_SIZE(dspp_prop),
 		prop_count, &off_count);
 	if (rc)
@@ -979,13 +1393,49 @@ static int sde_dspp_parse_dt(struct device_node *np,
 	sde_cfg->dspp_count = off_count;
 
 	rc = _read_dt_entry(np, dspp_prop, ARRAY_SIZE(dspp_prop), prop_count,
-		prop_value, bit_value);
+		prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
+	/* Parse AD dtsi entries */
+	ad_prop_value = kzalloc(AD_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!ad_prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+	rc = _validate_dt_entry(np, ad_prop, ARRAY_SIZE(ad_prop),
+		ad_prop_count, &ad_off_count);
+	if (rc)
+		goto end;
+	rc = _read_dt_entry(np, ad_prop, ARRAY_SIZE(ad_prop), ad_prop_count,
+		ad_prop_exists, ad_prop_value, bit_value);
+	if (rc)
+		goto end;
+
+	/* get DSPP feature dt properties if they exist */
+	snp = of_get_child_by_name(np, dspp_prop[DSPP_BLOCKS].prop_name);
+	if (snp) {
+		blocks_prop_value = kzalloc(DSPP_BLOCKS_PROP_MAX *
+				MAX_SDE_HW_BLK * sizeof(u32), GFP_KERNEL);
+		if (!blocks_prop_value) {
+			rc = -ENOMEM;
+			goto end;
+		}
+		rc = _validate_dt_entry(snp, dspp_blocks_prop,
+			ARRAY_SIZE(dspp_blocks_prop), blocks_prop_count, NULL);
+		if (rc)
+			goto end;
+		rc = _read_dt_entry(snp, dspp_blocks_prop,
+			ARRAY_SIZE(dspp_blocks_prop), blocks_prop_count,
+			blocks_prop_exists, blocks_prop_value, NULL);
+		if (rc)
+			goto end;
+	}
+
 	for (i = 0; i < off_count; i++) {
 		dspp = sde_cfg->dspp + i;
-		dspp->base = prop_value[DSPP_OFF][i];
+		dspp->base = PROP_VALUE_ACCESS(prop_value, DSPP_OFF, i);
 		dspp->id = DSPP_0 + i;
 
 		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
@@ -996,44 +1446,34 @@ static int sde_dspp_parse_dt(struct device_node *np,
 		}
 		dspp->sblk = sblk;
 
-		sblk->igc.base = prop_value[DSPP_IGC][0];
-		if (sblk->igc.base)
-			set_bit(SDE_DSPP_IGC, &dspp->features);
-
-		sblk->pcc.base = prop_value[DSPP_PCC][0];
-		if (sblk->pcc.base)
-			set_bit(SDE_DSPP_PCC, &dspp->features);
-
-		sblk->gc.base = prop_value[DSPP_GC][0];
-		if (sblk->gc.base)
-			set_bit(SDE_DSPP_GC, &dspp->features);
-
-		sblk->gamut.base = prop_value[DSPP_GAMUT][0];
-		if (sblk->gamut.base)
-			set_bit(SDE_DSPP_GAMUT, &dspp->features);
-
-		sblk->dither.base = prop_value[DSPP_DITHER][0];
-		if (sblk->dither.base)
-			set_bit(SDE_DSPP_DITHER, &dspp->features);
-
-		sblk->hist.base = prop_value[DSPP_HIST][0];
-		if (sblk->hist.base)
-			set_bit(SDE_DSPP_HIST, &dspp->features);
-
-		sblk->ad.base = prop_value[DSPP_AD][i];
-		if (sblk->ad.base)
+		if (blocks_prop_value)
+			_sde_dspp_setup_blocks(sde_cfg, dspp, sblk,
+					blocks_prop_exists, blocks_prop_value);
+
+		sblk->ad.id = SDE_DSPP_AD;
+		if (ad_prop_value && (i < ad_off_count) &&
+		    ad_prop_exists[AD_OFF]) {
+			sblk->ad.base = PROP_VALUE_ACCESS(ad_prop_value,
+				AD_OFF, i);
+			sblk->ad.version = PROP_VALUE_ACCESS(ad_prop_value,
+				AD_VERSION, 0);
 			set_bit(SDE_DSPP_AD, &dspp->features);
+		}
 	}
 
 end:
+	kfree(prop_value);
+	kfree(ad_prop_value);
+	kfree(blocks_prop_value);
 	return rc;
 }
 
 static int sde_cdm_parse_dt(struct device_node *np,
 				struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], i;
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	int rc, prop_count[HW_PROP_MAX], i;
+	u32 *prop_value = NULL;
+	bool prop_exists[HW_PROP_MAX];
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 				= { { { 0 } } };
 	u32 off_count;
@@ -1045,6 +1485,13 @@ static int sde_cdm_parse_dt(struct device_node *np,
 		goto end;
 	}
 
+	prop_value = kzalloc(HW_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
 	rc = _validate_dt_entry(np, cdm_prop, ARRAY_SIZE(cdm_prop), prop_count,
 		&off_count);
 	if (rc)
@@ -1053,15 +1500,15 @@ static int sde_cdm_parse_dt(struct device_node *np,
 	sde_cfg->cdm_count = off_count;
 
 	rc = _read_dt_entry(np, cdm_prop, ARRAY_SIZE(cdm_prop), prop_count,
-		prop_value, bit_value);
+		prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
 	for (i = 0; i < off_count; i++) {
 		cdm = sde_cfg->cdm + i;
-		cdm->base = prop_value[HW_OFF][i];
+		cdm->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);
 		cdm->id = CDM_0 + i;
-		cdm->len = prop_value[HW_LEN][0];
+		cdm->len = PROP_VALUE_ACCESS(prop_value, HW_LEN, 0);
 
 		/* intf3 and wb2 for cdm block */
 		cdm->wb_connect = sde_cfg->wb_count ? BIT(WB_2) : BIT(31);
@@ -1069,14 +1516,16 @@ static int sde_cdm_parse_dt(struct device_node *np,
 	}
 
 end:
+	kfree(prop_value);
 	return rc;
 }
 
 static int sde_vbif_parse_dt(struct device_node *np,
 				struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], i, j, k;
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	int rc, prop_count[VBIF_PROP_MAX], i, j, k;
+	u32 *prop_value = NULL;
+	bool prop_exists[VBIF_PROP_MAX];
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 				= { { { 0 } } };
 	u32 off_count, vbif_len, rd_len = 0, wr_len = 0;
@@ -1088,6 +1537,13 @@ static int sde_vbif_parse_dt(struct device_node *np,
 		goto end;
 	}
 
+	prop_value = kzalloc(VBIF_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
 	rc = _validate_dt_entry(np, vbif_prop, ARRAY_SIZE(vbif_prop),
 			prop_count, &off_count);
 	if (rc)
@@ -1106,31 +1562,31 @@ static int sde_vbif_parse_dt(struct device_node *np,
 	sde_cfg->vbif_count = off_count;
 
 	rc = _read_dt_entry(np, vbif_prop, ARRAY_SIZE(vbif_prop), prop_count,
-		prop_value, bit_value);
+		prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
-	vbif_len = prop_value[VBIF_LEN][0];
-	if (!vbif_len)
+	vbif_len = PROP_VALUE_ACCESS(prop_value, VBIF_LEN, 0);
+	if (!prop_exists[VBIF_LEN])
 		vbif_len = DEFAULT_SDE_HW_BLOCK_LEN;
 
 	for (i = 0; i < off_count; i++) {
 		vbif = sde_cfg->vbif + i;
-		vbif->base = prop_value[VBIF_OFF][i];
+		vbif->base = PROP_VALUE_ACCESS(prop_value, VBIF_OFF, i);
 		vbif->len = vbif_len;
-		vbif->id = VBIF_0 + prop_value[VBIF_ID][i];
+		vbif->id = VBIF_0 + PROP_VALUE_ACCESS(prop_value, VBIF_ID, i);
 
 		SDE_DEBUG("vbif:%d\n", vbif->id - VBIF_0);
 
 		vbif->xin_halt_timeout = VBIF_XIN_HALT_TIMEOUT;
 
-		vbif->default_ot_rd_limit =
-				prop_value[VBIF_DEFAULT_OT_RD_LIMIT][0];
+		vbif->default_ot_rd_limit = PROP_VALUE_ACCESS(prop_value,
+				VBIF_DEFAULT_OT_RD_LIMIT, 0);
 		SDE_DEBUG("default_ot_rd_limit=%u\n",
 				vbif->default_ot_rd_limit);
 
-		vbif->default_ot_wr_limit =
-				prop_value[VBIF_DEFAULT_OT_WR_LIMIT][0];
+		vbif->default_ot_wr_limit = PROP_VALUE_ACCESS(prop_value,
+				VBIF_DEFAULT_OT_WR_LIMIT, 0);
 		SDE_DEBUG("default_ot_wr_limit=%u\n",
 				vbif->default_ot_wr_limit);
 
@@ -1151,9 +1607,11 @@ static int sde_vbif_parse_dt(struct device_node *np,
 
 		for (j = 0, k = 0; j < vbif->dynamic_ot_rd_tbl.count; j++) {
 			vbif->dynamic_ot_rd_tbl.cfg[j].pps = (u64)
-				prop_value[VBIF_DYNAMIC_OT_RD_LIMIT][k++];
+				PROP_VALUE_ACCESS(prop_value,
+				VBIF_DYNAMIC_OT_RD_LIMIT, k++);
 			vbif->dynamic_ot_rd_tbl.cfg[j].ot_limit =
-				prop_value[VBIF_DYNAMIC_OT_RD_LIMIT][k++];
+				PROP_VALUE_ACCESS(prop_value,
+				VBIF_DYNAMIC_OT_RD_LIMIT, k++);
 			SDE_DEBUG("dynamic_ot_rd_tbl[%d].cfg=<%llu %u>\n", j,
 				vbif->dynamic_ot_rd_tbl.cfg[j].pps,
 				vbif->dynamic_ot_rd_tbl.cfg[j].ot_limit);
@@ -1176,9 +1634,11 @@ static int sde_vbif_parse_dt(struct device_node *np,
 
 		for (j = 0, k = 0; j < vbif->dynamic_ot_wr_tbl.count; j++) {
 			vbif->dynamic_ot_wr_tbl.cfg[j].pps = (u64)
-				prop_value[VBIF_DYNAMIC_OT_WR_LIMIT][k++];
+				PROP_VALUE_ACCESS(prop_value,
+				VBIF_DYNAMIC_OT_WR_LIMIT, k++);
 			vbif->dynamic_ot_wr_tbl.cfg[j].ot_limit =
-				prop_value[VBIF_DYNAMIC_OT_WR_LIMIT][k++];
+				PROP_VALUE_ACCESS(prop_value,
+				VBIF_DYNAMIC_OT_WR_LIMIT, k++);
 			SDE_DEBUG("dynamic_ot_wr_tbl[%d].cfg=<%llu %u>\n", j,
 				vbif->dynamic_ot_wr_tbl.cfg[j].pps,
 				vbif->dynamic_ot_wr_tbl.cfg[j].ot_limit);
@@ -1191,13 +1651,15 @@ static int sde_vbif_parse_dt(struct device_node *np,
 	}
 
 end:
+	kfree(prop_value);
 	return rc;
 }
 
 static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 {
-	int rc, prop_count[MAX_BLOCKS], i;
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { { 0 } };
+	int rc, prop_count[PP_PROP_MAX], i;
+	u32 *prop_value = NULL;
+	bool prop_exists[PP_PROP_MAX];
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 				= { { { 0 } } };
 	u32 off_count;
@@ -1210,6 +1672,13 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 		goto end;
 	}
 
+	prop_value = kzalloc(PP_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
 	rc = _validate_dt_entry(np, pp_prop, ARRAY_SIZE(pp_prop), prop_count,
 		&off_count);
 	if (rc)
@@ -1218,7 +1687,7 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 	sde_cfg->pingpong_count = off_count;
 
 	rc = _read_dt_entry(np, pp_prop, ARRAY_SIZE(pp_prop), prop_count,
-		prop_value, bit_value);
+		prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
@@ -1232,22 +1701,22 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 		}
 		pp->sblk = sblk;
 
-		pp->base = prop_value[PP_OFF][i];
+		pp->base = PROP_VALUE_ACCESS(prop_value, PP_OFF, i);
 		pp->id = PINGPONG_0 + i;
-		pp->len = prop_value[PP_LEN][0];
+		pp->len = PROP_VALUE_ACCESS(prop_value, PP_LEN, 0);
 
-		sblk->te.base = prop_value[TE_OFF][i];
+		sblk->te.base = PROP_VALUE_ACCESS(prop_value, TE_OFF, i);
 		sblk->te.id = SDE_PINGPONG_TE;
 		set_bit(SDE_PINGPONG_TE, &pp->features);
 
-		sblk->te2.base = prop_value[TE2_OFF][i];
+		sblk->te2.base = PROP_VALUE_ACCESS(prop_value, TE2_OFF, i);
 		if (sblk->te2.base) {
 			sblk->te2.id = SDE_PINGPONG_TE2;
 			set_bit(SDE_PINGPONG_TE2, &pp->features);
 			set_bit(SDE_PINGPONG_SPLIT, &pp->features);
 		}
 
-		sblk->dsc.base = prop_value[DSC_OFF][i];
+		sblk->dsc.base = PROP_VALUE_ACCESS(prop_value, DSC_OFF, i);
 		if (sblk->dsc.base) {
 			sblk->dsc.id = SDE_PINGPONG_DSC;
 			set_bit(SDE_PINGPONG_DSC, &pp->features);
@@ -1255,13 +1724,15 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 	}
 
 end:
+	kfree(prop_value);
 	return rc;
 }
 
 static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
 {
-	int rc, len, prop_count[MAX_BLOCKS];
-	u32 prop_value[MAX_BLOCKS][MAX_SDE_HW_BLK] = { {0} };
+	int rc, len, prop_count[SDE_PROP_MAX];
+	u32 *prop_value = NULL;
+	bool prop_exists[SDE_PROP_MAX];
 	u32 bit_value[MAX_BLOCKS][MAX_SDE_HW_BLK][MAX_BIT_OFFSET]
 			= { { { 0 } } };
 	const char *type;
@@ -1272,13 +1743,20 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
 		goto end;
 	}
 
+	prop_value = kzalloc(SDE_PROP_MAX * MAX_SDE_HW_BLK * sizeof(u32),
+			GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
 	rc = _validate_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count,
 		&len);
 	if (rc)
 		goto end;
 
 	rc = _read_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count,
-		prop_value, bit_value);
+		prop_exists, prop_value, bit_value);
 	if (rc)
 		goto end;
 
@@ -1288,29 +1766,33 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
 
 	cfg->mdp_count = 1;
 	cfg->mdp[0].id = MDP_TOP;
-	cfg->mdp[0].base = prop_value[SDE_OFF][0];
-	cfg->mdp[0].len = prop_value[SDE_LEN][0];
-	if (!cfg->mdp[0].len)
+	cfg->mdp[0].base = PROP_VALUE_ACCESS(prop_value, SDE_OFF, 0);
+	cfg->mdp[0].len = PROP_VALUE_ACCESS(prop_value, SDE_LEN, 0);
+	if (!prop_exists[SDE_LEN])
 		cfg->mdp[0].len = DEFAULT_SDE_HW_BLOCK_LEN;
 
-	cfg->max_sspp_linewidth = prop_value[SSPP_LINEWIDTH][0];
-	if (!cfg->max_sspp_linewidth)
+	cfg->max_sspp_linewidth = PROP_VALUE_ACCESS(prop_value,
+			SSPP_LINEWIDTH, 0);
+	if (!prop_exists[SSPP_LINEWIDTH])
 		cfg->max_sspp_linewidth = DEFAULT_SDE_LINE_WIDTH;
 
-	cfg->max_mixer_width = prop_value[MIXER_LINEWIDTH][0];
-	if (!cfg->max_mixer_width)
+	cfg->max_mixer_width = PROP_VALUE_ACCESS(prop_value,
+			MIXER_LINEWIDTH, 0);
+	if (!prop_exists[MIXER_LINEWIDTH])
 		cfg->max_mixer_width = DEFAULT_SDE_LINE_WIDTH;
 
-	cfg->max_mixer_blendstages = prop_value[MIXER_BLEND][0];
-	if (!cfg->max_mixer_blendstages)
+	cfg->max_mixer_blendstages = PROP_VALUE_ACCESS(prop_value,
+			MIXER_BLEND, 0);
+	if (!prop_exists[MIXER_BLEND])
 		cfg->max_mixer_blendstages = DEFAULT_SDE_MIXER_BLENDSTAGES;
 
-	cfg->max_wb_linewidth = prop_value[WB_LINEWIDTH][0];
-	if (!cfg->max_wb_linewidth)
+	cfg->max_wb_linewidth = PROP_VALUE_ACCESS(prop_value, WB_LINEWIDTH, 0);
+	if (!prop_exists[WB_LINEWIDTH])
 		cfg->max_wb_linewidth = DEFAULT_SDE_LINE_WIDTH;
 
-	cfg->mdp[0].highest_bank_bit = prop_value[BANK_BIT][0];
-	if (!cfg->mdp[0].highest_bank_bit)
+	cfg->mdp[0].highest_bank_bit = PROP_VALUE_ACCESS(prop_value,
+			BANK_BIT, 0);
+	if (!prop_exists[BANK_BIT])
 		cfg->mdp[0].highest_bank_bit = DEFAULT_SDE_HIGHEST_BANK_BIT;
 
 	rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);
@@ -1319,8 +1801,9 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
 	else if (!rc && !strcmp(type, "qseedv2"))
 		cfg->qseed_type = SDE_SSPP_SCALER_QSEED2;
 
-	cfg->has_src_split = prop_value[SRC_SPLIT][0];
+	cfg->has_src_split = PROP_VALUE_ACCESS(prop_value, SRC_SPLIT, 0);
 end:
+	kfree(prop_value);
 	return rc;
 }
 
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 6c705558a4d8..5ca297a46b26 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -339,8 +339,8 @@ struct sde_sspp_sub_blks {
 	struct sde_src_blk src_blk;
 	struct sde_scaler_blk scaler_blk;
 	struct sde_pp_blk csc_blk;
-	struct sde_pp_blk hsic;
-	struct sde_pp_blk memcolor;
+	struct sde_pp_blk hsic_blk;
+	struct sde_pp_blk memcolor_blk;
 	struct sde_pp_blk pcc_blk;
 	struct sde_pp_blk igc_blk;
 
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
index 21bab265b860..aa7d37b100af 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
@@ -251,17 +251,17 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features)
 		switch (i) {
 		case SDE_DSPP_PCC:
 			if (c->cap->sblk->pcc.version ==
-				(SDE_COLOR_PROCESS_VER(0x1, 0x0)))
+				(SDE_COLOR_PROCESS_VER(0x1, 0x7)))
 				c->ops.setup_pcc = sde_dspp_setup_pcc;
 			break;
 		case SDE_DSPP_HSIC:
 			if (c->cap->sblk->hsic.version ==
-				(SDE_COLOR_PROCESS_VER(0x1, 0x0)))
+				(SDE_COLOR_PROCESS_VER(0x1, 0x7)))
 				c->ops.setup_hue = sde_dspp_setup_hue;
 			break;
 		case SDE_DSPP_VLUT:
 			if (c->cap->sblk->vlut.version ==
-				(SDE_COLOR_PROCESS_VER(0x1, 0x0))) {
+				(SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
 				c->ops.setup_vlut = sde_dspp_setup_vlut;
 			}
 		default:
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
index cfcdda407a2e..6020e46f9d8d 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
@@ -186,13 +186,13 @@ static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx,
 		*idx = sblk->csc_blk.base;
 		break;
 	case SDE_SSPP_HSIC:
-		*idx = sblk->hsic.base;
+		*idx = sblk->hsic_blk.base;
 		break;
 	case SDE_SSPP_PCC:
 		*idx = sblk->pcc_blk.base;
 		break;
 	case SDE_SSPP_MEMCOLOR:
-		*idx = sblk->memcolor.base;
+		*idx = sblk->memcolor_blk.base;
 		break;
 	default:
 		rc = -EINVAL;
-- 
cgit v1.2.3


From ed93daaea77966c21d6b3807a8e3f94bcd07f11b Mon Sep 17 00:00:00 2001
From: Clarence Ip <cip@codeaurora.org>
Date: Fri, 9 Dec 2016 09:43:57 -0500
Subject: drm/msm/sde: enable ping pong split support

Add support for using a single layer mixer to drive two video
or command mode interfaces. This configuration frees up one of
the layer mixer paths for other use cases/displays.

Change-Id: I3a0ca07e37f121bf56ea8984c0cca25af7bc647e
Signed-off-by: Clarence Ip <cip@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt        |   3 +
 drivers/gpu/drm/msm/sde/sde_crtc.c                 |  11 +-
 drivers/gpu/drm/msm/sde/sde_encoder.c              |  65 ++++++++++--
 drivers/gpu/drm/msm/sde/sde_encoder_phys.h         |  15 ++-
 drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c     | 117 +++++++++++----------
 drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c     |  46 ++------
 drivers/gpu/drm/msm/sde/sde_hw_catalog.c           |   5 +
 drivers/gpu/drm/msm/sde/sde_hw_catalog.h           |   2 +
 drivers/gpu/drm/msm/sde/sde_hw_top.c               |  39 ++++++-
 drivers/gpu/drm/msm/sde/sde_hw_top.h               |  14 ++-
 drivers/gpu/drm/msm/sde/sde_rm.c                   |  24 ++++-
 11 files changed, 230 insertions(+), 111 deletions(-)

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 4c46e485f7bb..a1f0fc53f250 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -57,6 +57,8 @@ Required properties
 - qcom,sde-pp-off:		Array of offset addresses for the available
 				pingpong blocks. These offsets are calculated
 				from register "mdp_phys" defined in reg property.
+- qcom,sde-pp-slave:		Array of flags indicating whether each ping pong
+				block may be configured as a pp slave.
 - qcom,sde-intf-off:		Array of offset addresses for the available SDE
 				interface blocks that can drive data to a
 				panel controller. The offsets are calculated
@@ -286,6 +288,7 @@ Example:
     qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi";
     qcom,sde-pp-off = <0x00071000 0x00071800
 			  0x00072000 0x00072800>;
+    qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>;
     qcom,sde-cdm-off = <0x0007a200>;
     qcom,sde-dsc-off = <0x00081000 0x00081400>;
     qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 875c3c99f337..535a033435d2 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -290,8 +290,11 @@ static void _sde_crtc_blend_setup(struct drm_crtc *crtc)
 		/* stage config flush mask */
 		ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
 
-		SDE_DEBUG("lm %d ctl %d add mask 0x%x to pending flush\n",
-			mixer[i].hw_lm->idx, ctl->idx, mixer[i].flush_mask);
+		SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
+			mixer[i].hw_lm->idx - LM_0,
+			mixer[i].mixer_op_mode,
+			ctl->idx - CTL_0,
+			mixer[i].flush_mask);
 
 		ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
 			&sde_crtc->stage_cfg, i);
@@ -492,7 +495,7 @@ static void _sde_crtc_setup_mixer_for_encoder(
 		/* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
 		if (!sde_rm_get_hw(rm, &ctl_iter)) {
 			SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
-					mixer->hw_lm->idx);
+					mixer->hw_lm->idx - LM_0);
 			mixer->hw_ctl = last_valid_ctl;
 		} else {
 			mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
@@ -502,7 +505,7 @@ static void _sde_crtc_setup_mixer_for_encoder(
 		/* Shouldn't happen, mixers are always >= ctls */
 		if (!mixer->hw_ctl) {
 			SDE_ERROR("no valid ctls found for lm %d\n",
-					mixer->hw_lm->idx);
+					mixer->hw_lm->idx - LM_0);
 			return;
 		}
 
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 7481c2a63d7d..545dfa7c4f16 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -244,6 +244,57 @@ void sde_encoder_destroy(struct drm_encoder *drm_enc)
 	kfree(sde_enc);
 }
 
+void sde_encoder_helper_split_config(
+		struct sde_encoder_phys *phys_enc,
+		enum sde_intf interface)
+{
+	struct sde_encoder_virt *sde_enc;
+	struct split_pipe_cfg cfg = { 0 };
+	struct sde_hw_mdp *hw_mdptop;
+	enum sde_rm_topology_name topology;
+
+	if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
+		SDE_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
+		return;
+	}
+
+	sde_enc = to_sde_encoder_virt(phys_enc->parent);
+	hw_mdptop = phys_enc->hw_mdptop;
+	cfg.en = phys_enc->split_role != ENC_ROLE_SOLO;
+	cfg.mode = phys_enc->intf_mode;
+	cfg.intf = interface;
+
+	if (cfg.en && phys_enc->ops.needs_single_flush &&
+			phys_enc->ops.needs_single_flush(phys_enc))
+		cfg.split_flush_en = true;
+
+	topology = sde_connector_get_topology_name(phys_enc->connector);
+	if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
+		cfg.pp_split_slave = cfg.intf;
+	else
+		cfg.pp_split_slave = INTF_MAX;
+
+	if (phys_enc->split_role != ENC_ROLE_SLAVE) {
+		/* master/solo encoder */
+		SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg.en);
+
+		if (hw_mdptop->ops.setup_split_pipe)
+			hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
+	} else {
+		/*
+		 * slave encoder
+		 * - determine split index from master index,
+		 *   assume master is first pp
+		 */
+		cfg.pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
+		SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
+				cfg.pp_split_index);
+
+		if (hw_mdptop->ops.setup_pp_split)
+			hw_mdptop->ops.setup_pp_split(hw_mdptop, &cfg);
+	}
+}
+
 static int sde_encoder_virt_atomic_check(
 		struct drm_encoder *drm_enc,
 		struct drm_crtc_state *crtc_state,
@@ -581,6 +632,7 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
 		struct sde_encoder_phys *phys, uint32_t extra_flush_bits)
 {
 	struct sde_hw_ctl *ctl;
+	int pending_kickoff_cnt;
 
 	if (!drm_enc || !phys) {
 		SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
@@ -594,6 +646,10 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
 		return;
 	}
 
+	pending_kickoff_cnt = sde_encoder_phys_inc_pending(phys);
+	SDE_EVT32(DRMID(&to_sde_encoder_virt(drm_enc)->base),
+			phys->intf_idx, pending_kickoff_cnt);
+
 	if (extra_flush_bits && ctl->ops.update_pending_flush)
 		ctl->ops.update_pending_flush(ctl, extra_flush_bits);
 
@@ -674,7 +730,6 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
 	struct sde_hw_ctl *ctl;
 	uint32_t i, pending_flush;
 	unsigned long lock_flags;
-	int pending_kickoff_cnt;
 
 	if (!sde_enc) {
 		SDE_ERROR("invalid encoder\n");
@@ -689,18 +744,16 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
 	/* don't perform flush/start operations for slave encoders */
 	for (i = 0; i < sde_enc->num_phys_encs; i++) {
 		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
 		if (!phys || phys->enable_state == SDE_ENC_DISABLED)
 			continue;
 
-		pending_kickoff_cnt = sde_encoder_phys_inc_pending(phys);
-		SDE_EVT32(DRMID(&sde_enc->base), i, pending_kickoff_cnt);
-
 		ctl = phys->hw_ctl;
 		if (!ctl)
 			continue;
 
-		if (!phys->ops.needs_split_flush ||
-				!phys->ops.needs_split_flush(phys))
+		if (!phys->ops.needs_single_flush ||
+				!phys->ops.needs_single_flush(phys))
 			_sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
 		else if (ctl->ops.get_pending_flush)
 			pending_flush |= ctl->ops.get_pending_flush(ctl);
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
index 21a52acdbde7..355bd7e7fc11 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
@@ -87,7 +87,7 @@ struct sde_encoder_virt_ops {
  *				For CMD encoder, may wait for previous tx done
  * @handle_post_kickoff:	Do any work necessary post-kickoff work
  * @trigger_start:		Process start event on physical encoder
- * @needs_split_flush:		Whether encoder type needs split flush
+ * @needs_single_flush:		Whether encoder slaves need to be flushed
  * @setup_misr:		Sets up MISR, enable and disables based on sysfs
  * @collect_misr:		Collects MISR data on frame update
  */
@@ -114,7 +114,7 @@ struct sde_encoder_phys_ops {
 	void (*prepare_for_kickoff)(struct sde_encoder_phys *phys_enc);
 	void (*handle_post_kickoff)(struct sde_encoder_phys *phys_enc);
 	void (*trigger_start)(struct sde_encoder_phys *phys_enc);
-	bool (*needs_split_flush)(struct sde_encoder_phys *phys_enc);
+	bool (*needs_single_flush)(struct sde_encoder_phys *phys_enc);
 
 	void (*setup_misr)(struct sde_encoder_phys *phys_encs,
 			struct sde_misr_params *misr_map);
@@ -388,4 +388,15 @@ static inline enum sde_3d_blend_mode sde_encoder_helper_get_3d_blend_mode(
 	return BLEND_3D_NONE;
 }
 
+/**
+ * sde_encoder_helper_split_config - split display configuration helper function
+ *	This helper function may be used by physical encoders to configure
+ *	the split display related registers.
+ * @phys_enc: Pointer to physical encoder structure
+ * @interface: enum sde_intf setting
+ */
+void sde_encoder_helper_split_config(
+		struct sde_encoder_phys *phys_enc,
+		enum sde_intf interface);
+
 #endif /* __sde_encoder_phys_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
index bd18281c73ae..17ed73dc5155 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
@@ -80,9 +80,8 @@ static void sde_encoder_phys_cmd_mode_set(
 	/* Retrieve previously allocated HW Resources. Shouldn't fail */
 	sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
 	for (i = 0; i <= instance; i++) {
-		sde_rm_get_hw(rm, &iter);
-		if (i == instance)
-			phys_enc->hw_ctl = (struct sde_hw_ctl *) iter.hw;
+		if (sde_rm_get_hw(rm, &iter))
+			phys_enc->hw_ctl = (struct sde_hw_ctl *)iter.hw;
 	}
 
 	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
@@ -129,6 +128,22 @@ static void sde_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx)
 			phys_enc);
 }
 
+static bool _sde_encoder_phys_is_ppsplit_slave(
+		struct sde_encoder_phys *phys_enc)
+{
+	enum sde_rm_topology_name topology;
+
+	if (!phys_enc)
+		return false;
+
+	topology = sde_connector_get_topology_name(phys_enc->connector);
+	if (topology == SDE_RM_TOPOLOGY_PPSPLIT &&
+			phys_enc->split_role == ENC_ROLE_SLAVE)
+		return true;
+
+	return false;
+}
+
 static int _sde_encoder_phys_cmd_wait_for_idle(
 		struct sde_encoder_phys *phys_enc)
 {
@@ -137,6 +152,15 @@ static int _sde_encoder_phys_cmd_wait_for_idle(
 	u32 irq_status;
 	int ret;
 
+	if (!phys_enc) {
+		SDE_ERROR("invalid encoder\n");
+		return -EINVAL;
+	}
+
+	/* slave encoder doesn't enable for ppsplit */
+	if (_sde_encoder_phys_is_ppsplit_slave(phys_enc))
+		return 0;
+
 	/* return EWOULDBLOCK since we know the wait isn't necessary */
 	if (phys_enc->enable_state == SDE_ENC_DISABLED) {
 		SDE_ERROR_CMDENC(cmd_enc, "encoder is disabled\n");
@@ -374,34 +398,16 @@ static void sde_encoder_phys_cmd_pingpong_config(
 	sde_encoder_phys_cmd_tearcheck_config(phys_enc);
 }
 
-static bool sde_encoder_phys_cmd_needs_split_flush(
+static bool sde_encoder_phys_cmd_needs_single_flush(
 		struct sde_encoder_phys *phys_enc)
 {
-	return false;
-}
+	enum sde_rm_topology_name topology;
 
-static void sde_encoder_phys_cmd_split_config(
-		struct sde_encoder_phys *phys_enc, bool enable)
-{
-	struct sde_encoder_phys_cmd *cmd_enc =
-		to_sde_encoder_phys_cmd(phys_enc);
-	struct sde_hw_mdp *hw_mdptop = phys_enc->hw_mdptop;
-	struct split_pipe_cfg cfg = { 0 };
+	if (!phys_enc)
+		return false;
 
-	if (!phys_enc) {
-		SDE_ERROR("invalid encoder\n");
-		return;
-	}
-	SDE_DEBUG_CMDENC(cmd_enc, "enable %d\n", enable);
-
-	cfg.en = enable;
-	cfg.mode = INTF_MODE_CMD;
-	cfg.intf = cmd_enc->intf_idx;
-	cfg.split_flush_en = enable &&
-		sde_encoder_phys_cmd_needs_split_flush(phys_enc);
-
-	if (hw_mdptop && hw_mdptop->ops.setup_split_pipe)
-		hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
+	topology = sde_connector_get_topology_name(phys_enc->connector);
+	return topology == SDE_RM_TOPOLOGY_PPSPLIT;
 }
 
 static int sde_encoder_phys_cmd_control_vblank_irq(
@@ -453,28 +459,26 @@ static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc)
 		to_sde_encoder_phys_cmd(phys_enc);
 	struct sde_hw_ctl *ctl;
 	u32 flush_mask;
-	int ret = 0;
+	int ret;
 
-	if (!phys_enc) {
-		SDE_ERROR("invalid encoder\n");
+	if (!phys_enc || !phys_enc->hw_ctl) {
+		SDE_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
 		return;
 	}
 	SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
 
-	if (WARN_ON(phys_enc->enable_state == SDE_ENC_ENABLED))
+	if (phys_enc->enable_state == SDE_ENC_ENABLED) {
+		SDE_ERROR("already enabled\n");
 		return;
+	}
 
-	/*
-	 * Only master configures master/slave configuration, so no slave check
-	 * In solo configuration, solo encoder needs to program no-split
-	 */
-	if (phys_enc->split_role == ENC_ROLE_MASTER)
-		sde_encoder_phys_cmd_split_config(phys_enc, true);
-	else if (phys_enc->split_role == ENC_ROLE_SOLO)
-		sde_encoder_phys_cmd_split_config(phys_enc, false);
+	sde_encoder_helper_split_config(phys_enc, cmd_enc->intf_idx);
 
 	sde_encoder_phys_cmd_pingpong_config(phys_enc);
 
+	if (_sde_encoder_phys_is_ppsplit_slave(phys_enc))
+		goto update_flush;
+
 	/* Both master and slave need to register for pp_tx_done */
 	ret = sde_encoder_phys_cmd_register_irq(phys_enc,
 			SDE_IRQ_TYPE_PING_PONG_COMP,
@@ -503,6 +507,7 @@ static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc)
 		return;
 	}
 
+update_flush:
 	ctl = phys_enc->hw_ctl;
 	ctl->ops.get_bitmask_intf(ctl, &flush_mask, cmd_enc->intf_idx);
 	ctl->ops.update_pending_flush(ctl, flush_mask);
@@ -524,24 +529,30 @@ static void sde_encoder_phys_cmd_disable(struct sde_encoder_phys *phys_enc)
 	}
 	SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
 
-	if (WARN_ON(phys_enc->enable_state == SDE_ENC_DISABLED))
+	if (phys_enc->enable_state == SDE_ENC_DISABLED) {
+		SDE_ERROR_CMDENC(cmd_enc, "already disabled\n");
 		return;
+	}
 
 	SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0);
 
-	ret = _sde_encoder_phys_cmd_wait_for_idle(phys_enc);
-	if (ret) {
-		atomic_set(&phys_enc->pending_kickoff_cnt, 0);
-		SDE_ERROR_CMDENC(cmd_enc,
-				"pp %d failed wait for idle at disable: %d\n",
-				phys_enc->hw_pp->idx - PINGPONG_0, ret);
-		SDE_EVT32(DRMID(phys_enc->parent),
-				phys_enc->hw_pp->idx - PINGPONG_0, ret);
-	}
+	if (!_sde_encoder_phys_is_ppsplit_slave(phys_enc)) {
+		ret = _sde_encoder_phys_cmd_wait_for_idle(phys_enc);
+		if (ret) {
+			atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+			SDE_ERROR_CMDENC(cmd_enc,
+					"pp %d failed wait for idle, %d\n",
+					phys_enc->hw_pp->idx - PINGPONG_0, ret);
+			SDE_EVT32(DRMID(phys_enc->parent),
+					phys_enc->hw_pp->idx - PINGPONG_0, ret);
+		}
 
-	sde_encoder_phys_cmd_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
-	sde_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
-	sde_encoder_phys_cmd_unregister_irq(phys_enc, INTR_IDX_PINGPONG);
+		sde_encoder_phys_cmd_unregister_irq(
+				phys_enc, INTR_IDX_UNDERRUN);
+		sde_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
+		sde_encoder_phys_cmd_unregister_irq(
+				phys_enc, INTR_IDX_PINGPONG);
+	}
 
 	phys_enc->enable_state = SDE_ENC_DISABLED;
 
@@ -634,7 +645,7 @@ static void sde_encoder_phys_cmd_init_ops(
 	ops->wait_for_commit_done = sde_encoder_phys_cmd_wait_for_commit_done;
 	ops->prepare_for_kickoff = sde_encoder_phys_cmd_prepare_for_kickoff;
 	ops->trigger_start = sde_encoder_helper_trigger_start;
-	ops->needs_split_flush = sde_encoder_phys_cmd_needs_split_flush;
+	ops->needs_single_flush = sde_encoder_phys_cmd_needs_single_flush;
 }
 
 struct sde_encoder_phys *sde_encoder_phys_cmd_init(
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
index 683868eaec1e..eddb28a86b52 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
@@ -319,38 +319,12 @@ static void sde_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
 			phys_enc);
 }
 
-static bool sde_encoder_phys_vid_needs_split_flush(
+static bool sde_encoder_phys_vid_needs_single_flush(
 		struct sde_encoder_phys *phys_enc)
 {
 	return phys_enc && phys_enc->split_role != ENC_ROLE_SOLO;
 }
 
-static void _sde_encoder_phys_vid_split_config(
-		struct sde_encoder_phys *phys_enc, bool enable)
-{
-	struct sde_encoder_phys_vid *vid_enc =
-		to_sde_encoder_phys_vid(phys_enc);
-	struct sde_hw_mdp *hw_mdptop = phys_enc->hw_mdptop;
-	struct split_pipe_cfg cfg = { 0 };
-
-	SDE_DEBUG_VIDENC(vid_enc, "enable %d\n", enable);
-
-	cfg.en = enable;
-	cfg.mode = INTF_MODE_VIDEO;
-	cfg.intf = vid_enc->hw_intf->idx;
-	cfg.split_flush_en = enable &&
-		sde_encoder_phys_vid_needs_split_flush(phys_enc);
-
-	/* Configure split pipe control to handle master/slave triggering */
-	if (hw_mdptop && hw_mdptop->ops.setup_split_pipe) {
-		unsigned long lock_flags;
-
-		spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
-		hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
-		spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
-	}
-}
-
 static int sde_encoder_phys_vid_register_irq(struct sde_encoder_phys *phys_enc,
 	enum sde_intr_type intr_type, int idx,
 	void (*irq_func)(void *, int), const char *irq_name)
@@ -429,16 +403,17 @@ static void sde_encoder_phys_vid_mode_set(
 		struct drm_display_mode *mode,
 		struct drm_display_mode *adj_mode)
 {
-	struct sde_rm *rm = &phys_enc->sde_kms->rm;
+	struct sde_rm *rm;
 	struct sde_rm_hw_iter iter;
 	int i, instance;
 	struct sde_encoder_phys_vid *vid_enc;
 
-	if (!phys_enc) {
+	if (!phys_enc || !phys_enc->sde_kms) {
 		SDE_ERROR("invalid encoder\n");
 		return;
 	}
 
+	rm = &phys_enc->sde_kms->rm;
 	vid_enc = to_sde_encoder_phys_vid(phys_enc);
 	phys_enc->cached_mode = *adj_mode;
 	SDE_DEBUG_VIDENC(vid_enc, "caching mode:\n");
@@ -449,11 +424,9 @@ static void sde_encoder_phys_vid_mode_set(
 	/* Retrieve previously allocated HW Resources. Shouldn't fail */
 	sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
 	for (i = 0; i <= instance; i++) {
-		sde_rm_get_hw(rm, &iter);
-		if (i == instance)
-			phys_enc->hw_ctl = (struct sde_hw_ctl *) iter.hw;
+		if (sde_rm_get_hw(rm, &iter))
+			phys_enc->hw_ctl = (struct sde_hw_ctl *)iter.hw;
 	}
-
 	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
 		SDE_ERROR_VIDENC(vid_enc, "failed to init ctl, %ld\n",
 				PTR_ERR(phys_enc->hw_ctl));
@@ -531,10 +504,7 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc)
 	if (WARN_ON(!vid_enc->hw_intf->ops.enable_timing))
 		return;
 
-	if (phys_enc->split_role == ENC_ROLE_MASTER)
-		_sde_encoder_phys_vid_split_config(phys_enc, true);
-	else if (phys_enc->split_role == ENC_ROLE_SOLO)
-		_sde_encoder_phys_vid_split_config(phys_enc, false);
+	sde_encoder_helper_split_config(phys_enc, vid_enc->hw_intf->idx);
 
 	sde_encoder_phys_vid_setup_timing_engine(phys_enc);
 	ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true);
@@ -772,7 +742,7 @@ static void sde_encoder_phys_vid_init_ops(struct sde_encoder_phys_ops *ops)
 	ops->control_vblank_irq = sde_encoder_phys_vid_control_vblank_irq;
 	ops->wait_for_commit_done = sde_encoder_phys_vid_wait_for_commit_done;
 	ops->handle_post_kickoff = sde_encoder_phys_vid_handle_post_kickoff;
-	ops->needs_split_flush = sde_encoder_phys_vid_needs_split_flush;
+	ops->needs_single_flush = sde_encoder_phys_vid_needs_single_flush;
 	ops->setup_misr = sde_encoder_phys_vid_setup_misr;
 	ops->collect_misr = sde_encoder_phys_vid_collect_misr;
 }
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index 6783c232e868..72c0b5cfd094 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -155,6 +155,7 @@ enum {
 	TE2_LEN,
 	DSC_OFF,
 	DSC_LEN,
+	PP_SLAVE,
 	PP_PROP_MAX,
 };
 
@@ -347,6 +348,7 @@ static struct sde_prop_type pp_prop[] = {
 	{TE2_LEN, "qcom,sde-te2-size", false, PROP_TYPE_U32},
 	{DSC_OFF, "qcom,sde-dsc-off", false, PROP_TYPE_U32_ARRAY},
 	{DSC_LEN, "qcom,sde-dsc-size", false, PROP_TYPE_U32},
+	{PP_SLAVE, "qcom,sde-pp-slave", false, PROP_TYPE_U32_ARRAY},
 };
 
 static struct sde_prop_type cdm_prop[] = {
@@ -1723,6 +1725,9 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 			set_bit(SDE_PINGPONG_SPLIT, &pp->features);
 		}
 
+		if (PROP_VALUE_ACCESS(prop_value, PP_SLAVE, i))
+			set_bit(SDE_PINGPONG_SLAVE, &pp->features);
+
 		sblk->dsc.base = PROP_VALUE_ACCESS(prop_value, DSC_OFF, i);
 		if (sblk->dsc.base) {
 			sblk->dsc.id = SDE_PINGPONG_DSC;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 26bb832b5fa3..b9a1bd97c015 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -159,6 +159,7 @@ enum {
  * @SDE_PINGPONG_TE         Tear check block
  * @SDE_PINGPONG_TE2        Additional tear check block for split pipes
  * @SDE_PINGPONG_SPLIT      PP block supports split fifo
+ * @SDE_PINGPONG_SLAVE      PP block is a suitable slave for split fifo
  * @SDE_PINGPONG_DSC,       Display stream compression blocks
  * @SDE_PINGPONG_MAX
  */
@@ -166,6 +167,7 @@ enum {
 	SDE_PINGPONG_TE = 0x1,
 	SDE_PINGPONG_TE2,
 	SDE_PINGPONG_SPLIT,
+	SDE_PINGPONG_SLAVE,
 	SDE_PINGPONG_DSC,
 	SDE_PINGPONG_MAX
 };
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.c b/drivers/gpu/drm/msm/sde/sde_hw_top.c
index 10d39177345d..045d4c24bb29 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_top.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.c
@@ -29,13 +29,16 @@
 #define TRAFFIC_SHAPER_WR_CLIENT(num)     (0x060 + (num * 4))
 #define TRAFFIC_SHAPER_FIXPOINT_FACTOR    4
 
-static void sde_hw_setup_split_pipe_control(struct sde_hw_mdp *mdp,
+static void sde_hw_setup_split_pipe(struct sde_hw_mdp *mdp,
 		struct split_pipe_cfg *cfg)
 {
 	struct sde_hw_blk_reg_map *c = &mdp->hw;
 	u32 upper_pipe = 0;
 	u32 lower_pipe = 0;
 
+	if (!mdp || !cfg)
+		return;
+
 	if (cfg->en) {
 		if (cfg->mode == INTF_MODE_CMD) {
 			lower_pipe = FLD_SPLIT_DISPLAY_CMD;
@@ -46,7 +49,7 @@ static void sde_hw_setup_split_pipe_control(struct sde_hw_mdp *mdp,
 				lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
 
 			/* free run */
-			if (cfg->pp_split)
+			if (cfg->pp_split_slave != INTF_MAX)
 				lower_pipe = FLD_SMART_PANEL_FREE_RUN;
 
 			upper_pipe = lower_pipe;
@@ -61,12 +64,39 @@ static void sde_hw_setup_split_pipe_control(struct sde_hw_mdp *mdp,
 		}
 	}
 
-	SDE_REG_WRITE(c, SSPP_SPARE, (cfg->split_flush_en) ? 0x1 : 0x0);
+	SDE_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0);
 	SDE_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);
 	SDE_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);
 	SDE_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
 }
 
+static void sde_hw_setup_pp_split(struct sde_hw_mdp *mdp,
+		struct split_pipe_cfg *cfg)
+{
+	u32 ppb_config = 0x0;
+	u32 ppb_control = 0x0;
+
+	if (!mdp || !cfg)
+		return;
+
+	if (cfg->en && cfg->pp_split_slave != INTF_MAX) {
+		ppb_config |= (cfg->pp_split_slave - INTF_0 + 1) << 20;
+		ppb_config |= BIT(16); /* split enable */
+		ppb_control = BIT(5); /* horz split*/
+	}
+	if (cfg->pp_split_index) {
+		SDE_REG_WRITE(&mdp->hw, PPB0_CONFIG, 0x0);
+		SDE_REG_WRITE(&mdp->hw, PPB0_CNTL, 0x0);
+		SDE_REG_WRITE(&mdp->hw, PPB1_CONFIG, ppb_config);
+		SDE_REG_WRITE(&mdp->hw, PPB1_CNTL, ppb_control);
+	} else {
+		SDE_REG_WRITE(&mdp->hw, PPB0_CONFIG, ppb_config);
+		SDE_REG_WRITE(&mdp->hw, PPB0_CNTL, ppb_control);
+		SDE_REG_WRITE(&mdp->hw, PPB1_CONFIG, 0x0);
+		SDE_REG_WRITE(&mdp->hw, PPB1_CNTL, 0x0);
+	}
+}
+
 static void sde_hw_setup_cdm_output(struct sde_hw_mdp *mdp,
 		struct cdm_output_cfg *cfg)
 {
@@ -112,7 +142,8 @@ static bool sde_hw_setup_clk_force_ctrl(struct sde_hw_mdp *mdp,
 static void _setup_mdp_ops(struct sde_hw_mdp_ops *ops,
 		unsigned long cap)
 {
-	ops->setup_split_pipe = sde_hw_setup_split_pipe_control;
+	ops->setup_split_pipe = sde_hw_setup_split_pipe;
+	ops->setup_pp_split = sde_hw_setup_pp_split;
 	ops->setup_cdm_output = sde_hw_setup_cdm_output;
 	ops->setup_clk_force_ctrl = sde_hw_setup_clk_force_ctrl;
 }
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.h b/drivers/gpu/drm/msm/sde/sde_hw_top.h
index 7359a77bc954..eb8ff8685908 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_top.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.h
@@ -40,7 +40,8 @@ struct traffic_shaper_cfg {
  * @en        : Enable/disable dual pipe confguration
  * @mode      : Panel interface mode
  * @intf      : Interface id for main control path
- * @pp_split  : Ping pong split is enabled or disabled
+ * @pp_split_slave: Slave interface for ping pong split, INTF_MAX to disable
+ * @pp_split_idx:   Ping pong index for ping pong split
  * @split_flush_en: Allows both the paths to be flushed when master path is
  *              flushed
  */
@@ -48,7 +49,8 @@ struct split_pipe_cfg {
 	bool en;
 	enum sde_intf_mode mode;
 	enum sde_intf intf;
-	bool pp_split;
+	enum sde_intf pp_split_slave;
+	u32 pp_split_index;
 	bool split_flush_en;
 };
 
@@ -66,6 +68,7 @@ struct cdm_output_cfg {
  * struct sde_hw_mdp_ops - interface to the MDP TOP Hw driver functions
  * Assumption is these functions will be called after clocks are enabled.
  * @setup_split_pipe : Programs the pipe control registers
+ * @setup_pp_split : Programs the pp split control registers
  * @setup_cdm_output : programs cdm control
  * @setup_traffic_shaper : programs traffic shaper control
  */
@@ -78,6 +81,13 @@ struct sde_hw_mdp_ops {
 	void (*setup_split_pipe)(struct sde_hw_mdp *mdp,
 			struct split_pipe_cfg *p);
 
+	/** setup_pp_split() : Configure pp split related registers
+	 * @mdp  : mdp top context driver
+	 * @cfg  : upper and lower part of pipe configuration
+	 */
+	void (*setup_pp_split)(struct sde_hw_mdp *mdp,
+			struct split_pipe_cfg *cfg);
+
 	/**
 	 * setup_cdm_output() : Setup selection control of the cdm data path
 	 * @mdp  : mdp top context driver
diff --git a/drivers/gpu/drm/msm/sde/sde_rm.c b/drivers/gpu/drm/msm/sde/sde_rm.c
index 075e9d69af8f..1d27b27d265c 100644
--- a/drivers/gpu/drm/msm/sde/sde_rm.c
+++ b/drivers/gpu/drm/msm/sde/sde_rm.c
@@ -592,7 +592,7 @@ static int _sde_rm_reserve_lms(
 	struct sde_rm_hw_blk *pp[MAX_BLOCKS];
 	struct sde_rm_hw_iter iter_i, iter_j;
 	int lm_count = 0;
-	int i;
+	int i, rc = 0;
 
 	if (!reqs->num_lm) {
 		SDE_ERROR("invalid number of lm: %d\n", reqs->num_lm);
@@ -651,7 +651,27 @@ static int _sde_rm_reserve_lms(
 				dspp[i] ? dspp[i]->id : 0);
 	}
 
-	return 0;
+	if (reqs->top_name == SDE_RM_TOPOLOGY_PPSPLIT) {
+		/* reserve a free PINGPONG_SLAVE block */
+		rc = -ENAVAIL;
+		sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_PINGPONG);
+		while (sde_rm_get_hw(rm, &iter_i)) {
+			struct sde_pingpong_cfg *pp_cfg =
+				(struct sde_pingpong_cfg *)
+				(iter_i.blk->catalog);
+
+			if (!(test_bit(SDE_PINGPONG_SLAVE, &pp_cfg->features)))
+				continue;
+			if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
+				continue;
+
+			iter_i.blk->rsvp_nxt = rsvp;
+			rc = 0;
+			break;
+		}
+	}
+
+	return rc;
 }
 
 static int _sde_rm_reserve_ctls(
-- 
cgit v1.2.3


From 94386a395b25a55f92eaae1c8a927642820cda6d Mon Sep 17 00:00:00 2001
From: Alan Kwong <akwong@codeaurora.org>
Date: Tue, 1 Nov 2016 23:16:53 -0400
Subject: drm/msm/sde: add bus bandwidth control for crtc

Add bus bandwidth control (on/off) for crtc around atomic
commit and frame done event. To support video mode interface,
also add bandwidth control around encoder enable/disable.

Change-Id: I90ef372aad4a20040602a468393e8a5cd8f08201
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt        |  32 +-
 drivers/gpu/drm/msm/Makefile                       |   1 +
 drivers/gpu/drm/msm/sde/sde_core_perf.c            | 140 +++++++++
 drivers/gpu/drm/msm/sde/sde_core_perf.h            |  73 +++++
 drivers/gpu/drm/msm/sde/sde_crtc.c                 |  59 ++++
 drivers/gpu/drm/msm/sde/sde_crtc.h                 |   2 +
 drivers/gpu/drm/msm/sde/sde_encoder.c              | 115 ++-----
 drivers/gpu/drm/msm/sde/sde_encoder.h              |   8 +-
 drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c     |  20 +-
 drivers/gpu/drm/msm/sde/sde_hw_catalog.h           |   1 +
 drivers/gpu/drm/msm/sde/sde_kms.c                  |  14 +-
 drivers/gpu/drm/msm/sde/sde_kms.h                  |   3 +
 drivers/gpu/drm/msm/sde/sde_trace.h                |  20 ++
 drivers/gpu/drm/msm/sde_power_handle.c             | 348 +++++++++++++++++++++
 drivers/gpu/drm/msm/sde_power_handle.h             |  92 ++++++
 15 files changed, 828 insertions(+), 100 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/sde/sde_core_perf.c
 create mode 100644 drivers/gpu/drm/msm/sde/sde_core_perf.h

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index a1f0fc53f250..395c051476a4 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -84,8 +84,6 @@ Optional properties:
 				-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
 				-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
 				-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
-- qcom,sde-reg-bus:		Property to provide Bus scaling for register access for
-				mdss blocks.
 - qcom,sde-sspp-src-size:	A u32 value indicates the address range for each sspp.
 - qcom,sde-mixer-size:		A u32 value indicates the address range for each mixer.
 - qcom,sde-ctl-size:		A u32 value indicates the address range for each ctl.
@@ -224,6 +222,21 @@ Optional properties:
 				control register. Number of offsets defined should
 				match the number of offsets defined in
 				property: qcom,sde-wb-off
+- qcom,sde-dram-channels:	This represents the number of channels in the
+				Bus memory controller.
+- qcom,sde-num-nrt-paths:	Integer property represents the number of non-realtime
+				paths in each Bus Scaling Usecase. This value depends on
+				number of AXI ports that are dedicated to non-realtime VBIF
+				for particular chipset.
+				These paths must be defined after rt-paths in
+				"qcom,msm-bus,vectors-KBps" vector request.
+
+Bus Scaling Subnodes:
+- qcom,sde-reg-bus:		Property to provide Bus scaling for register access for
+				mdss blocks.
+- qcom,sde-data-bus:		Property to provide Bus scaling for data bus access for
+				mdss blocks.
+
 Bus Scaling Data:
 - qcom,msm-bus,name:		String property describing client name.
 - qcom,msm-bus,num-cases:	This is the number of Bus Scaling use cases
@@ -364,6 +377,9 @@ Example:
     qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>,
         <124416000 4>, <248832000 16>;
 
+    qcom,sde-dram-channels = <2>;
+    qcom,sde-num-nrt-paths = <1>;
+
     qcom,sde-sspp-vig-blocks {
         qcom,sde-vig-csc-off = <0x320>;
         qcom,sde-vig-qseed-off = <0x200>;
@@ -411,6 +427,18 @@ Example:
         };
     };
 
+    qcom,sde-data-bus {
+        qcom,msm-bus,name = "mdss_sde";
+        qcom,msm-bus,num-cases = <3>;
+        qcom,msm-bus,num-paths = <3>;
+        qcom,msm-bus,vectors-KBps =
+            <22 512 0 0>, <23 512 0 0>, <25 512 0 0>,
+            <22 512 0 6400000>, <23 512 0 6400000>,
+                <25 512 0 6400000>,
+            <22 512 0 6400000>, <23 512 0 6400000>,
+                <25 512 0 6400000>;
+    };
+
     qcom,sde-reg-bus {
         /* Reg Bus Scale Settings */
         qcom,msm-bus,name = "mdss_reg";
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 1bc2044d3fc7..4ca16fc01e1c 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -36,6 +36,7 @@ msm_drm-y := \
 	sde/sde_encoder_phys_cmd.o \
 	sde/sde_irq.o \
 	sde/sde_core_irq.o \
+	sde/sde_core_perf.o \
 	sde/sde_rm.o \
 	sde/sde_kms_utils.o \
 	sde/sde_kms.o \
diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.c b/drivers/gpu/drm/msm/sde/sde_core_perf.c
new file mode 100644
index 000000000000..3479cf8dbc20
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.c
@@ -0,0 +1,140 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include <linux/debugfs.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/sort.h>
+#include <linux/clk.h>
+#include <linux/bitmap.h>
+
+#include "msm_prop.h"
+
+#include "sde_kms.h"
+#include "sde_fence.h"
+#include "sde_formats.h"
+#include "sde_hw_sspp.h"
+#include "sde_trace.h"
+#include "sde_crtc.h"
+#include "sde_plane.h"
+#include "sde_encoder.h"
+#include "sde_wb.h"
+#include "sde_core_perf.h"
+#include "sde_trace.h"
+
+#ifdef CONFIG_DEBUG_FS
+
+static void sde_debugfs_core_perf_destroy(struct sde_core_perf *perf)
+{
+	debugfs_remove_recursive(perf->debugfs_root);
+	perf->debugfs_root = NULL;
+}
+
+static int sde_debugfs_core_perf_init(struct sde_core_perf *perf,
+		struct dentry *parent)
+{
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
+
+	priv = perf->dev->dev_private;
+	if (!priv || !priv->kms) {
+		SDE_ERROR("invalid KMS reference\n");
+		return -EINVAL;
+	}
+
+	sde_kms = to_sde_kms(priv->kms);
+
+	perf->debugfs_root = debugfs_create_dir("core_perf", parent);
+	if (!perf->debugfs_root) {
+		SDE_ERROR("failed to create core perf debugfs\n");
+		return -EINVAL;
+	}
+
+	debugfs_create_u64("max_core_clk_rate", 0644, perf->debugfs_root,
+			&perf->max_core_clk_rate);
+	debugfs_create_u32("core_clk_rate", 0644, perf->debugfs_root,
+			&perf->core_clk_rate);
+
+	return 0;
+}
+#else
+static void sde_debugfs_core_perf_destroy(struct sde_core_perf *perf)
+{
+}
+
+static int sde_debugfs_core_perf_init(struct sde_core_perf *perf,
+		struct dentry *parent)
+{
+	return 0;
+}
+#endif
+
+void sde_core_perf_destroy(struct sde_core_perf *perf)
+{
+	if (!perf) {
+		SDE_ERROR("invalid parameters\n");
+		return;
+	}
+
+	sde_debugfs_core_perf_destroy(perf);
+	perf->max_core_clk_rate = 0;
+	perf->core_clk = NULL;
+	mutex_destroy(&perf->perf_lock);
+	perf->clk_name = NULL;
+	perf->phandle = NULL;
+	perf->catalog = NULL;
+	perf->dev = NULL;
+}
+
+int sde_core_perf_init(struct sde_core_perf *perf,
+		struct drm_device *dev,
+		struct sde_mdss_cfg *catalog,
+		struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		char *clk_name,
+		struct dentry *debugfs_parent)
+{
+	if (!perf || !catalog || !phandle || !pclient ||
+			!clk_name || !debugfs_parent) {
+		SDE_ERROR("invalid parameters\n");
+		return -EINVAL;
+	}
+
+	perf->dev = dev;
+	perf->catalog = catalog;
+	perf->phandle = phandle;
+	perf->pclient = pclient;
+	perf->clk_name = clk_name;
+	mutex_init(&perf->perf_lock);
+
+	perf->core_clk = sde_power_clk_get_clk(phandle, clk_name);
+	if (!perf->core_clk) {
+		SDE_ERROR("invalid core clk\n");
+		goto err;
+	}
+
+	perf->max_core_clk_rate = sde_power_clk_get_max_rate(phandle, clk_name);
+	if (!perf->max_core_clk_rate) {
+		SDE_ERROR("invalid max core clk rate\n");
+		goto err;
+	}
+
+	sde_debugfs_core_perf_init(perf, debugfs_parent);
+
+	return 0;
+
+err:
+	sde_core_perf_destroy(perf);
+	return -ENODEV;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.h b/drivers/gpu/drm/msm/sde/sde_core_perf.h
new file mode 100644
index 000000000000..172deb5f3208
--- /dev/null
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.h
@@ -0,0 +1,73 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SDE_CORE_PERF_H__
+#define __SDE_CORE_PERF_H__
+
+#include <linux/types.h>
+#include <linux/dcache.h>
+#include <linux/mutex.h>
+
+#include "sde_hw_catalog.h"
+#include "sde_power_handle.h"
+
+/**
+ * struct sde_core_perf - definition of core performance context
+ * @dev: Pointer to drm device
+ * @debugfs_root: top level debug folder
+ * @perf_lock: serialization lock for this context
+ * @catalog: Pointer to catalog configuration
+ * @phandle: Pointer to power handler
+ * @pclient: Pointer to power client
+ * @clk_name: core clock name
+ * @core_clk: Pointer to core clock structure
+ * @core_clk_rate: current core clock rate
+ * @max_core_clk_rate: maximum allowable core clock rate
+ */
+struct sde_core_perf {
+	struct drm_device *dev;
+	struct dentry *debugfs_root;
+	struct mutex perf_lock;
+	struct sde_mdss_cfg *catalog;
+	struct sde_power_handle *phandle;
+	struct sde_power_client *pclient;
+	char *clk_name;
+	struct clk *core_clk;
+	u32 core_clk_rate;
+	u64 max_core_clk_rate;
+};
+
+/**
+ * sde_core_perf_destroy - destroy the given core performance context
+ * @perf: Pointer to core performance context
+ */
+void sde_core_perf_destroy(struct sde_core_perf *perf);
+
+/**
+ * sde_core_perf_init - initialize the given core performance context
+ * @perf: Pointer to core performance context
+ * @dev: Pointer to drm device
+ * @catalog: Pointer to catalog
+ * @phandle: Pointer to power handle
+ * @pclient: Pointer to power client
+ * @clk_name: core clock name
+ * @debugfs_parent: Pointer to parent debugfs
+ */
+int sde_core_perf_init(struct sde_core_perf *perf,
+		struct drm_device *dev,
+		struct sde_mdss_cfg *catalog,
+		struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		char *clk_name,
+		struct dentry *debugfs_parent);
+
+#endif /* __SDE_CORE_PERF_H__ */
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 4a6aedada52b..6d12c0402240 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -28,6 +28,7 @@
 #include "sde_color_processing.h"
 #include "sde_encoder.h"
 #include "sde_connector.h"
+#include "sde_power_handle.h"
 
 /* default input fence timeout, in ms */
 #define SDE_CRTC_INPUT_FENCE_TIMEOUT    2000
@@ -331,6 +332,12 @@ void sde_crtc_prepare_commit(struct drm_crtc *crtc,
 				cstate->is_rt = true;
 		}
 
+	if (cstate->num_connectors > 0 && cstate->connectors[0]->encoder)
+		cstate->intf_mode = sde_encoder_get_intf_mode(
+				cstate->connectors[0]->encoder);
+	else
+		cstate->intf_mode = INTF_MODE_NONE;
+
 	/* prepare main output fence */
 	sde_fence_prepare(&sde_crtc->output_fence);
 }
@@ -389,6 +396,7 @@ static void sde_crtc_vblank_cb(void *data)
 
 static void sde_crtc_frame_event_work(struct kthread_work *work)
 {
+	struct msm_drm_private *priv;
 	struct sde_crtc_frame_event *fevent;
 	struct drm_crtc *crtc;
 	struct sde_crtc *sde_crtc;
@@ -414,6 +422,7 @@ static void sde_crtc_frame_event_work(struct kthread_work *work)
 		SDE_ERROR("invalid kms handle\n");
 		return;
 	}
+	priv = sde_kms->dev->dev_private;
 
 	SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
 			ktime_to_ns(fevent->ts));
@@ -434,6 +443,8 @@ static void sde_crtc_frame_event_work(struct kthread_work *work)
 					crtc->base.id,
 					ktime_to_ns(fevent->ts));
 			SDE_EVT32(DRMID(crtc), fevent->event, 1);
+			sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+					sde_kms->core_client, false);
 		} else {
 			SDE_EVT32(DRMID(crtc), fevent->event, 2);
 		}
@@ -798,6 +809,8 @@ void sde_crtc_commit_kickoff(struct drm_crtc *crtc)
 	struct drm_encoder *encoder;
 	struct drm_device *dev;
 	struct sde_crtc *sde_crtc;
+	struct msm_drm_private *priv;
+	struct sde_kms *sde_kms;
 
 	if (!crtc) {
 		SDE_ERROR("invalid argument\n");
@@ -805,6 +818,8 @@ void sde_crtc_commit_kickoff(struct drm_crtc *crtc)
 	}
 	dev = crtc->dev;
 	sde_crtc = to_sde_crtc(crtc);
+	sde_kms = _sde_crtc_get_kms(crtc);
+	priv = sde_kms->dev->dev_private;
 
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc != crtc)
@@ -827,6 +842,8 @@ void sde_crtc_commit_kickoff(struct drm_crtc *crtc)
 		/* acquire bandwidth and other resources */
 		SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
 		SDE_EVT32(DRMID(crtc), 1);
+		sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+				sde_kms->core_client, true);
 	} else {
 		SDE_DEBUG("crtc%d commit\n", crtc->base.id);
 		SDE_EVT32(DRMID(crtc), 2);
@@ -915,14 +932,18 @@ static void sde_crtc_reset(struct drm_crtc *crtc)
 
 static void sde_crtc_disable(struct drm_crtc *crtc)
 {
+	struct msm_drm_private *priv;
 	struct sde_crtc *sde_crtc;
 	struct drm_encoder *encoder;
+	struct sde_kms *sde_kms;
 
 	if (!crtc) {
 		SDE_ERROR("invalid crtc\n");
 		return;
 	}
 	sde_crtc = to_sde_crtc(crtc);
+	sde_kms = _sde_crtc_get_kms(crtc);
+	priv = sde_kms->dev->dev_private;
 
 	SDE_DEBUG("crtc%d\n", crtc->base.id);
 
@@ -947,6 +968,8 @@ static void sde_crtc_disable(struct drm_crtc *crtc)
 		SDE_ERROR("crtc%d invalid frame pending\n",
 				crtc->base.id);
 		SDE_EVT32(DRMID(crtc));
+		sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+				sde_kms->core_client, false);
 		atomic_set(&sde_crtc->frame_pending, 0);
 	}
 
@@ -1347,6 +1370,7 @@ static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
 	return ret;
 }
 
+#ifdef CONFIG_DEBUG_FS
 static int _sde_debugfs_status_show(struct seq_file *s, void *data)
 {
 	struct sde_crtc *sde_crtc;
@@ -1464,6 +1488,7 @@ static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, _sde_debugfs_status_show, inode->i_private);
 }
+#endif
 
 static void sde_crtc_suspend(struct drm_crtc *crtc)
 {
@@ -1498,6 +1523,33 @@ static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
 	.atomic_flush = sde_crtc_atomic_flush,
 };
 
+#ifdef CONFIG_DEBUG_FS
+#define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix)				\
+static int __prefix ## _open(struct inode *inode, struct file *file)	\
+{									\
+	return single_open(file, __prefix ## _show, inode->i_private);	\
+}									\
+static const struct file_operations __prefix ## _fops = {		\
+	.owner = THIS_MODULE,						\
+	.open = __prefix ## _open,					\
+	.release = single_release,					\
+	.read = seq_read,						\
+	.llseek = seq_lseek,						\
+}
+
+static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
+{
+	struct drm_crtc *crtc = (struct drm_crtc *) s->private;
+	struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
+
+	seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
+	seq_printf(s, "is_rt: %d\n", cstate->is_rt);
+	seq_printf(s, "intf_mode: %d\n", cstate->intf_mode);
+
+	return 0;
+}
+DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
+
 static void _sde_crtc_init_debugfs(struct sde_crtc *sde_crtc,
 		struct sde_kms *sde_kms)
 {
@@ -1507,6 +1559,7 @@ static void _sde_crtc_init_debugfs(struct sde_crtc *sde_crtc,
 		.llseek =	seq_lseek,
 		.release =	single_release,
 	};
+
 	if (sde_crtc && sde_kms) {
 		sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
 				sde_debugfs_get_root(sde_kms));
@@ -1518,6 +1571,12 @@ static void _sde_crtc_init_debugfs(struct sde_crtc *sde_crtc,
 		}
 	}
 }
+#else
+static void _sde_crtc_init_debugfs(struct sde_crtc *sde_crtc,
+		struct sde_kms *sde_kms)
+{
+}
+#endif
 
 /* initialize crtc */
 struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
index 9902c9364939..dc5998a9124c 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.h
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -130,6 +130,7 @@ struct sde_crtc {
  * @connectors    : Currently associated drm connectors
  * @num_connectors: Number of associated drm connectors
  * @is_rt         : Whether or not the current commit contains RT connectors
+ * @intf_mode     : Interface mode of the primary connector
  * @property_values: Current crtc property values
  * @input_fence_timeout_ns : Cached input fence timeout, in ns
  * @property_blobs: Reference pointers for blob properties
@@ -140,6 +141,7 @@ struct sde_crtc_state {
 	struct drm_connector *connectors[MAX_CONNECTORS];
 	int num_connectors;
 	bool is_rt;
+	enum sde_intf_mode intf_mode;
 
 	uint64_t property_values[CRTC_PROP_COUNT];
 	uint64_t input_fence_timeout_ns;
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 4fc2d7e5b35d..27218eefc2b5 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -109,93 +109,6 @@ struct sde_encoder_virt {
 
 #define to_sde_encoder_virt(x) container_of(x, struct sde_encoder_virt, base)
 
-#ifdef CONFIG_QCOM_BUS_SCALING
-#include <linux/msm-bus.h>
-#include <linux/msm-bus-board.h>
-#define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val)		\
-	{						\
-		.src = MSM_BUS_MASTER_MDP_PORT0,	\
-		.dst = MSM_BUS_SLAVE_EBI_CH0,		\
-		.ab = (ab_val),				\
-		.ib = (ib_val),				\
-	}
-
-static struct msm_bus_vectors mdp_bus_vectors[] = {
-	MDP_BUS_VECTOR_ENTRY(0, 0),
-	MDP_BUS_VECTOR_ENTRY(8000000000, 8000000000),
-};
-
-static struct msm_bus_paths mdp_bus_usecases[] = { {
-						    .num_paths = 1,
-						    .vectors =
-						    &mdp_bus_vectors[0],
-						    }, {
-							.num_paths = 1,
-							.vectors =
-							&mdp_bus_vectors[1],
-							}
-};
-
-static struct msm_bus_scale_pdata mdp_bus_scale_table = {
-	.usecase = mdp_bus_usecases,
-	.num_usecases = ARRAY_SIZE(mdp_bus_usecases),
-	.name = "mdss_mdp",
-};
-
-static void bs_init(struct sde_encoder_virt *sde_enc)
-{
-	if (!sde_enc) {
-		SDE_ERROR("invalid encoder\n");
-		return;
-	}
-
-	sde_enc->bus_scaling_client =
-	    msm_bus_scale_register_client(&mdp_bus_scale_table);
-	SDE_DEBUG_ENC(sde_enc, "bus scale client %08x\n",
-			sde_enc->bus_scaling_client);
-}
-
-static void bs_fini(struct sde_encoder_virt *sde_enc)
-{
-	if (!sde_enc) {
-		SDE_ERROR("invalid encoder\n");
-		return;
-	}
-
-	if (sde_enc->bus_scaling_client) {
-		msm_bus_scale_unregister_client(sde_enc->bus_scaling_client);
-		sde_enc->bus_scaling_client = 0;
-	}
-}
-
-static void bs_set(struct sde_encoder_virt *sde_enc, int idx)
-{
-	if (!sde_enc) {
-		SDE_ERROR("invalid encoder\n");
-		return;
-	}
-
-	if (sde_enc->bus_scaling_client) {
-		SDE_DEBUG_ENC(sde_enc, "set bus scaling to %d\n", idx);
-		idx = 1;
-		msm_bus_scale_client_update_request(sde_enc->bus_scaling_client,
-						    idx);
-	}
-}
-#else
-static void bs_init(struct sde_encoder_virt *sde_enc)
-{
-}
-
-static void bs_fini(struct sde_encoder_virt *sde_enc)
-{
-}
-
-static void bs_set(struct sde_encoder_virt *sde_enc, int idx)
-{
-}
-#endif
-
 void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 		struct sde_encoder_hw_resources *hw_res,
 		struct drm_connector_state *conn_state)
@@ -256,7 +169,6 @@ void sde_encoder_destroy(struct drm_encoder *drm_enc)
 
 	drm_encoder_cleanup(drm_enc);
 	debugfs_remove_recursive(sde_enc->debugfs_root);
-	bs_fini(sde_enc);
 	mutex_destroy(&sde_enc->enc_lock);
 
 	kfree(sde_enc);
@@ -471,8 +383,6 @@ static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
 
 	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, true);
 
-	bs_set(sde_enc, 1);
-
 	sde_enc->cur_master = NULL;
 	for (i = 0; i < sde_enc->num_phys_encs; i++) {
 		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
@@ -546,7 +456,6 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
 	sde_enc->cur_master = NULL;
 	SDE_DEBUG_ENC(sde_enc, "cleared master\n");
 
-	bs_set(sde_enc, 0);
 	sde_rm_release(&sde_kms->rm, drm_enc);
 
 	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
@@ -1345,7 +1254,6 @@ struct drm_encoder *sde_encoder_init(
 	drm_enc = &sde_enc->base;
 	drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode);
 	drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
-	bs_init(sde_enc);
 
 	atomic_set(&sde_enc->frame_done_timeout, 0);
 	setup_timer(&sde_enc->frame_done_timer, sde_encoder_frame_done_timeout,
@@ -1394,3 +1302,26 @@ int sde_encoder_wait_for_commit_done(struct drm_encoder *drm_enc)
 	return ret;
 }
 
+enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
+{
+	struct sde_encoder_virt *sde_enc = NULL;
+	int i;
+
+	if (!encoder) {
+		SDE_ERROR("invalid encoder\n");
+		return INTF_MODE_NONE;
+	}
+	sde_enc = to_sde_encoder_virt(encoder);
+
+	if (sde_enc->cur_master)
+		return sde_enc->cur_master->intf_mode;
+
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (phys)
+			return phys->intf_mode;
+	}
+
+	return INTF_MODE_NONE;
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.h b/drivers/gpu/drm/msm/sde/sde_encoder.h
index 81f63e00d8b5..7da871f8eec5 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.h
@@ -79,7 +79,7 @@ void sde_encoder_prepare_for_kickoff(struct drm_encoder *encoder);
  *	(i.e. ctl flush and start) immediately.
  * @encoder:	encoder pointer
  */
-void sde_encoder_kickoff(struct drm_encoder *drm_enc);
+void sde_encoder_kickoff(struct drm_encoder *encoder);
 
 /**
  * sde_encoder_wait_nxt_committed - Wait for hardware to have flushed the
@@ -91,6 +91,12 @@ void sde_encoder_kickoff(struct drm_encoder *drm_enc);
  */
 int sde_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder);
 
+/*
+ * sde_encoder_get_intf_mode - get interface mode of the given encoder
+ * @encoder: Pointer to drm encoder object
+ */
+enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder);
+
 /**
  * sde_encoder_init - initialize virtual encoder object
  * @dev:        Pointer to drm device structure
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
index 3127e2003a16..e61ff97d2ca4 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
@@ -479,16 +479,19 @@ static int sde_encoder_phys_vid_control_vblank_irq(
 
 static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc)
 {
+	struct msm_drm_private *priv;
 	struct sde_encoder_phys_vid *vid_enc;
 	struct sde_hw_intf *intf;
 	struct sde_hw_ctl *ctl;
 	u32 flush_mask = 0;
 	int ret;
 
-	if (!phys_enc) {
-		SDE_ERROR("invalid encoder\n");
+	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
+			!phys_enc->parent->dev->dev_private) {
+		SDE_ERROR("invalid encoder/device\n");
 		return;
 	}
+	priv = phys_enc->parent->dev->dev_private;
 
 	vid_enc = to_sde_encoder_phys_vid(phys_enc);
 	intf = vid_enc->hw_intf;
@@ -504,6 +507,9 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc)
 	if (WARN_ON(!vid_enc->hw_intf->ops.enable_timing))
 		return;
 
+	sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+			phys_enc->sde_kms->core_client, true);
+
 	sde_encoder_helper_split_config(phys_enc, vid_enc->hw_intf->idx);
 
 	sde_encoder_phys_vid_setup_timing_engine(phys_enc);
@@ -650,14 +656,17 @@ static int sde_encoder_phys_vid_wait_for_commit_done(
 
 static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc)
 {
+	struct msm_drm_private *priv;
 	struct sde_encoder_phys_vid *vid_enc;
 	unsigned long lock_flags;
 	int ret;
 
-	if (!phys_enc) {
-		SDE_ERROR("invalid encoder\n");
+	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
+			!phys_enc->parent->dev->dev_private) {
+		SDE_ERROR("invalid encoder/device\n");
 		return;
 	}
+	priv = phys_enc->parent->dev->dev_private;
 
 	vid_enc = to_sde_encoder_phys_vid(phys_enc);
 	if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
@@ -703,6 +712,9 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc)
 		sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);
 	}
 
+	sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
+			phys_enc->sde_kms->core_client, false);
+
 	if (atomic_read(&phys_enc->vblank_refcount))
 		SDE_ERROR_VIDENC(vid_enc, "invalid vblank refcount %d\n",
 				atomic_read(&phys_enc->vblank_refcount));
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index b9a1bd97c015..2625d3ea15ab 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -17,6 +17,7 @@
 #include <linux/bug.h>
 #include <linux/bitmap.h>
 #include <linux/err.h>
+#include <linux/msm-bus.h>
 #include <drm/drmP.h>
 
 /**
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
index 75170f3599e3..5b5245d73273 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -834,6 +834,7 @@ static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
 	/* safe to call these more than once during shutdown */
 	_sde_debugfs_destroy(sde_kms);
 	_sde_kms_mmu_destroy(sde_kms);
+	sde_core_perf_destroy(&sde_kms->perf);
 
 	for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
 		u32 vbif_idx = sde_kms->catalog->vbif[i].id;
@@ -1116,6 +1117,14 @@ static int sde_kms_hw_init(struct msm_kms *kms)
 		goto power_error;
 	}
 
+	rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
+			&priv->phandle, priv->pclient, "core_clk_src",
+			sde_kms->debugfs_debug);
+	if (rc) {
+		SDE_ERROR("failed to init perf %d\n", rc);
+		goto perf_err;
+	}
+
 	/*
 	 * _sde_kms_drm_obj_init should create the DRM related objects
 	 * i.e. CRTCs, planes, encoders, connectors and so forth
@@ -1123,7 +1132,7 @@ static int sde_kms_hw_init(struct msm_kms *kms)
 	rc = _sde_kms_drm_obj_init(sde_kms);
 	if (rc) {
 		SDE_ERROR("modeset init failed: %d\n", rc);
-		goto power_error;
+		goto drm_obj_init_err;
 	}
 
 	dev->mode_config.min_width = 0;
@@ -1154,6 +1163,9 @@ static int sde_kms_hw_init(struct msm_kms *kms)
 
 hw_intr_init_err:
 	_sde_kms_drm_obj_destroy(sde_kms);
+drm_obj_init_err:
+	sde_core_perf_destroy(&sde_kms->perf);
+perf_err:
 power_error:
 	sde_power_resource_enable(&priv->phandle, sde_kms->core_client, false);
 error:
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.h b/drivers/gpu/drm/msm/sde/sde_kms.h
index f3c165e1bfc7..5fe849a43711 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.h
+++ b/drivers/gpu/drm/msm/sde/sde_kms.h
@@ -26,6 +26,7 @@
 #include "sde_rm.h"
 #include "sde_power_handle.h"
 #include "sde_irq.h"
+#include "sde_core_perf.h"
 
 #define DRMID(x) ((x) ? (x)->base.id : -1)
 
@@ -136,6 +137,8 @@ struct sde_kms {
 	struct sde_hw_intr *hw_intr;
 	struct sde_irq irq_obj;
 
+	struct sde_core_perf perf;
+
 	struct sde_rm rm;
 	bool rm_init;
 
diff --git a/drivers/gpu/drm/msm/sde/sde_trace.h b/drivers/gpu/drm/msm/sde/sde_trace.h
index 862b5c990b81..26e3afa50a3e 100644
--- a/drivers/gpu/drm/msm/sde/sde_trace.h
+++ b/drivers/gpu/drm/msm/sde/sde_trace.h
@@ -92,6 +92,26 @@ TRACE_EVENT(sde_perf_set_ot,
 			__entry->vbif_idx)
 )
 
+TRACE_EVENT(sde_perf_update_bus,
+	TP_PROTO(int client, unsigned long long ab_quota,
+	unsigned long long ib_quota),
+	TP_ARGS(client, ab_quota, ib_quota),
+	TP_STRUCT__entry(
+			__field(int, client)
+			__field(u64, ab_quota)
+			__field(u64, ib_quota)
+	),
+	TP_fast_assign(
+			__entry->client = client;
+			__entry->ab_quota = ab_quota;
+			__entry->ib_quota = ib_quota;
+	),
+	TP_printk("Request client:%d ab=%llu ib=%llu",
+			__entry->client,
+			__entry->ab_quota,
+			__entry->ib_quota)
+)
+
 
 TRACE_EVENT(sde_mark_write,
 	TP_PROTO(int pid, const char *name, bool trace_begin),
diff --git a/drivers/gpu/drm/msm/sde_power_handle.c b/drivers/gpu/drm/msm/sde_power_handle.c
index 2f9d3575177e..6e002b464432 100644
--- a/drivers/gpu/drm/msm/sde_power_handle.c
+++ b/drivers/gpu/drm/msm/sde_power_handle.c
@@ -27,6 +27,7 @@
 #include <linux/mdss_io_util.h>
 
 #include "sde_power_handle.h"
+#include "sde_trace.h"
 
 struct sde_power_client *sde_power_client_create(
 	struct sde_power_handle *phandle, char *client_name)
@@ -272,6 +273,228 @@ clk_err:
 }
 
 #ifdef CONFIG_QCOM_BUS_SCALING
+
+#define MAX_AXI_PORT_COUNT 3
+
+static int _sde_power_data_bus_set_quota(
+		struct sde_power_data_bus_handle *pdbus,
+		u64 ab_quota_rt, u64 ab_quota_nrt,
+		u64 ib_quota_rt, u64 ib_quota_nrt)
+{
+	int new_uc_idx;
+	u64 ab_quota[MAX_AXI_PORT_COUNT] = {0, 0};
+	u64 ib_quota[MAX_AXI_PORT_COUNT] = {0, 0};
+	int rc;
+
+	if (pdbus->data_bus_hdl < 1) {
+		pr_err("invalid bus handle %d\n", pdbus->data_bus_hdl);
+		return -EINVAL;
+	}
+
+	if (!ab_quota_rt && !ab_quota_nrt && !ib_quota_rt && !ib_quota_nrt)  {
+		new_uc_idx = 0;
+	} else {
+		int i;
+		struct msm_bus_vectors *vect = NULL;
+		struct msm_bus_scale_pdata *bw_table =
+			pdbus->data_bus_scale_table;
+		u32 nrt_axi_port_cnt = pdbus->nrt_axi_port_cnt;
+		u32 total_axi_port_cnt = pdbus->axi_port_cnt;
+		u32 rt_axi_port_cnt = total_axi_port_cnt - nrt_axi_port_cnt;
+		int match_cnt = 0;
+
+		if (!bw_table || !total_axi_port_cnt ||
+		    total_axi_port_cnt > MAX_AXI_PORT_COUNT) {
+			pr_err("invalid input\n");
+			return -EINVAL;
+		}
+
+		if (pdbus->bus_channels) {
+			ib_quota_rt = div_u64(ib_quota_rt,
+						pdbus->bus_channels);
+			ib_quota_nrt = div_u64(ib_quota_nrt,
+						pdbus->bus_channels);
+		}
+
+		if (nrt_axi_port_cnt) {
+
+			ab_quota_rt = div_u64(ab_quota_rt, rt_axi_port_cnt);
+			ab_quota_nrt = div_u64(ab_quota_nrt, nrt_axi_port_cnt);
+
+			for (i = 0; i < total_axi_port_cnt; i++) {
+				if (i < rt_axi_port_cnt) {
+					ab_quota[i] = ab_quota_rt;
+					ib_quota[i] = ib_quota_rt;
+				} else {
+					ab_quota[i] = ab_quota_nrt;
+					ib_quota[i] = ib_quota_nrt;
+				}
+			}
+		} else {
+			ab_quota[0] = div_u64(ab_quota_rt + ab_quota_nrt,
+					total_axi_port_cnt);
+			ib_quota[0] = ib_quota_rt + ib_quota_nrt;
+
+			for (i = 1; i < total_axi_port_cnt; i++) {
+				ab_quota[i] = ab_quota[0];
+				ib_quota[i] = ib_quota[0];
+			}
+		}
+
+		for (i = 0; i < total_axi_port_cnt; i++) {
+			vect = &bw_table->usecase
+				[pdbus->curr_bw_uc_idx].vectors[i];
+			/* avoid performing updates for small changes */
+			if ((ab_quota[i] == vect->ab) &&
+				(ib_quota[i] == vect->ib))
+				match_cnt++;
+		}
+
+		if (match_cnt == total_axi_port_cnt) {
+			pr_debug("skip BW vote\n");
+			return 0;
+		}
+
+		new_uc_idx = (pdbus->curr_bw_uc_idx %
+			(bw_table->num_usecases - 1)) + 1;
+
+		for (i = 0; i < total_axi_port_cnt; i++) {
+			vect = &bw_table->usecase[new_uc_idx].vectors[i];
+			vect->ab = ab_quota[i];
+			vect->ib = ib_quota[i];
+
+			pr_debug("uc_idx=%d %s path idx=%d ab=%llu ib=%llu\n",
+				new_uc_idx, (i < rt_axi_port_cnt) ? "rt" : "nrt"
+				, i, vect->ab, vect->ib);
+		}
+	}
+	pdbus->curr_bw_uc_idx = new_uc_idx;
+	pdbus->ao_bw_uc_idx = new_uc_idx;
+
+	if ((pdbus->bus_ref_cnt == 0) && pdbus->curr_bw_uc_idx) {
+		rc = 0;
+	} else { /* vote BW if bus_bw_cnt > 0 or uc_idx is zero */
+		SDE_ATRACE_BEGIN("msm_bus_scale_req");
+		rc = msm_bus_scale_client_update_request(pdbus->data_bus_hdl,
+			new_uc_idx);
+		SDE_ATRACE_END("msm_bus_scale_req");
+	}
+	return rc;
+}
+
+int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		int bus_client, u64 ab_quota, u64 ib_quota)
+{
+	int rc = 0;
+	int i;
+	u64 total_ab_rt = 0, total_ib_rt = 0;
+	u64 total_ab_nrt = 0, total_ib_nrt = 0;
+	struct sde_power_client *client;
+
+	if (!phandle || !pclient ||
+			bus_client >= SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX) {
+		pr_err("invalid parameters\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&phandle->phandle_lock);
+
+	pclient->ab[bus_client] = ab_quota;
+	pclient->ib[bus_client] = ib_quota;
+	trace_sde_perf_update_bus(bus_client, ab_quota, ib_quota);
+
+	list_for_each_entry(client, &phandle->power_client_clist, list) {
+		for (i = 0; i < SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX; i++) {
+			if (i == SDE_POWER_HANDLE_DATA_BUS_CLIENT_NRT) {
+				total_ab_nrt += client->ab[i];
+				total_ib_nrt += client->ib[i];
+			} else {
+				total_ab_rt += client->ab[i];
+				total_ib_rt = max(total_ib_rt, client->ib[i]);
+			}
+		}
+	}
+
+	rc = _sde_power_data_bus_set_quota(&phandle->data_bus_handle,
+			total_ab_rt, total_ab_nrt,
+			total_ib_rt, total_ib_nrt);
+
+	mutex_unlock(&phandle->phandle_lock);
+
+	return rc;
+}
+
+static void sde_power_data_bus_unregister(
+		struct sde_power_data_bus_handle *pdbus)
+{
+	if (pdbus->data_bus_hdl) {
+		msm_bus_scale_unregister_client(pdbus->data_bus_hdl);
+		pdbus->data_bus_hdl = 0;
+	}
+}
+
+static int sde_power_data_bus_parse(struct platform_device *pdev,
+	struct sde_power_data_bus_handle *pdbus)
+{
+	struct device_node *node;
+	int rc = 0;
+	int paths;
+
+	pdbus->bus_channels = 1;
+	rc = of_property_read_u32(pdev->dev.of_node,
+		"qcom,sde-dram-channels", &pdbus->bus_channels);
+	if (rc)
+		pr_debug("number of channels property not specified\n");
+
+	pdbus->nrt_axi_port_cnt = 0;
+	rc = of_property_read_u32(pdev->dev.of_node,
+			"qcom,sde-num-nrt-paths",
+			&pdbus->nrt_axi_port_cnt);
+
+	node = of_get_child_by_name(pdev->dev.of_node, "qcom,sde-data-bus");
+	if (node) {
+		rc = of_property_read_u32(node,
+				"qcom,msm-bus,num-paths", &paths);
+		if (rc) {
+			pr_err("Error. qcom,msm-bus,num-paths not found\n");
+			return rc;
+		}
+		pdbus->axi_port_cnt = paths;
+
+		pdbus->data_bus_scale_table =
+				msm_bus_pdata_from_node(pdev, node);
+		if (IS_ERR_OR_NULL(pdbus->data_bus_scale_table)) {
+			pr_err("reg bus handle parsing failed\n");
+			rc = PTR_ERR(pdbus->data_bus_scale_table);
+			goto end;
+		}
+		pdbus->data_bus_hdl = msm_bus_scale_register_client(
+				pdbus->data_bus_scale_table);
+		if (!pdbus->data_bus_hdl) {
+			pr_err("data_bus_client register failed\n");
+			rc = -EINVAL;
+			goto end;
+		}
+		pr_debug("register data_bus_hdl=%x\n", pdbus->data_bus_hdl);
+
+		/*
+		 * Following call will not result in actual vote rather update
+		 * the current index and ab/ib value. When continuous splash
+		 * is enabled, actual vote will happen when splash handoff is
+		 * done.
+		 */
+		return _sde_power_data_bus_set_quota(pdbus,
+				SDE_POWER_HANDLE_DATA_BUS_AB_QUOTA,
+				SDE_POWER_HANDLE_DATA_BUS_AB_QUOTA,
+				SDE_POWER_HANDLE_DATA_BUS_IB_QUOTA,
+				SDE_POWER_HANDLE_DATA_BUS_IB_QUOTA);
+	}
+
+end:
+	return rc;
+}
+
 static int sde_power_reg_bus_parse(struct platform_device *pdev,
 	struct sde_power_handle *phandle)
 {
@@ -320,6 +543,23 @@ static int sde_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx)
 	return rc;
 }
 #else
+static int sde_power_data_bus_parse(struct platform_device *pdev,
+	struct sde_power_handle *phandle)
+{
+	return 0;
+}
+
+static void sde_power_data_bus_unregister(u32 reg_bus_hdl)
+{
+}
+
+int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		int bus_client, u64 ab_quota, u64 ib_quota)
+{
+	return 0;
+}
+
 static int sde_power_reg_bus_parse(struct platform_device *pdev,
 	struct sde_power_handle *phandle)
 {
@@ -336,6 +576,57 @@ static int sde_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx)
 }
 #endif
 
+void sde_power_data_bus_bandwidth_ctrl(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient, int enable)
+{
+	struct sde_power_data_bus_handle *pdbus;
+	int changed = 0;
+
+	if (!phandle || !pclient) {
+		pr_err("invalid power/client handle\n");
+		return;
+	}
+
+	pdbus = &phandle->data_bus_handle;
+
+	mutex_lock(&phandle->phandle_lock);
+	if (enable) {
+		if (pdbus->bus_ref_cnt == 0)
+			changed++;
+		pdbus->bus_ref_cnt++;
+	} else {
+		if (pdbus->bus_ref_cnt) {
+			pdbus->bus_ref_cnt--;
+			if (pdbus->bus_ref_cnt == 0)
+				changed++;
+		} else {
+			pr_debug("Can not be turned off\n");
+		}
+	}
+
+	pr_debug("%pS: task:%s bw_cnt=%d changed=%d enable=%d\n",
+		__builtin_return_address(0), current->group_leader->comm,
+		pdbus->bus_ref_cnt, changed, enable);
+
+	if (changed) {
+		SDE_ATRACE_INT("data_bus_ctrl", enable);
+
+		if (!enable) {
+			if (!pdbus->handoff_pending) {
+				msm_bus_scale_client_update_request(
+						pdbus->data_bus_hdl, 0);
+				pdbus->ao_bw_uc_idx = 0;
+			}
+		} else {
+			msm_bus_scale_client_update_request(
+					pdbus->data_bus_hdl,
+					pdbus->curr_bw_uc_idx);
+		}
+	}
+
+	mutex_unlock(&phandle->phandle_lock);
+}
+
 int sde_power_resource_init(struct platform_device *pdev,
 	struct sde_power_handle *phandle)
 {
@@ -348,6 +639,7 @@ int sde_power_resource_init(struct platform_device *pdev,
 		goto end;
 	}
 	mp = &phandle->mp;
+	phandle->dev = &pdev->dev;
 
 	rc = sde_power_parse_dt_clock(pdev, mp);
 	if (rc) {
@@ -386,11 +678,19 @@ int sde_power_resource_init(struct platform_device *pdev,
 		goto bus_err;
 	}
 
+	rc = sde_power_data_bus_parse(pdev, &phandle->data_bus_handle);
+	if (rc) {
+		pr_err("register data bus parse failed rc=%d\n", rc);
+		goto data_bus_err;
+	}
+
 	INIT_LIST_HEAD(&phandle->power_client_clist);
 	mutex_init(&phandle->phandle_lock);
 
 	return rc;
 
+data_bus_err:
+	sde_power_reg_bus_unregister(phandle->reg_bus_hdl);
 bus_err:
 	msm_dss_put_clk(mp->clk_config, mp->num_clk);
 clk_err:
@@ -416,6 +716,8 @@ void sde_power_resource_deinit(struct platform_device *pdev,
 	}
 	mp = &phandle->mp;
 
+	sde_power_data_bus_unregister(&phandle->data_bus_handle);
+
 	sde_power_reg_bus_unregister(phandle->reg_bus_hdl);
 
 	msm_dss_put_clk(mp->clk_config, mp->num_clk);
@@ -568,3 +870,49 @@ u64 sde_power_clk_get_rate(struct sde_power_handle *phandle, char *clock_name)
 
 	return rate;
 }
+
+u64 sde_power_clk_get_max_rate(struct sde_power_handle *phandle,
+		char *clock_name)
+{
+	int i;
+	struct dss_module_power *mp;
+	u64 rate = 0;
+
+	if (!phandle) {
+		pr_err("invalid input power handle\n");
+		return 0;
+	}
+	mp = &phandle->mp;
+
+	for (i = 0; i < mp->num_clk; i++) {
+		if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
+			rate = mp->clk_config[i].max_rate;
+			break;
+		}
+	}
+
+	return rate;
+}
+
+struct clk *sde_power_clk_get_clk(struct sde_power_handle *phandle,
+		char *clock_name)
+{
+	int i;
+	struct dss_module_power *mp;
+	struct clk *clk = NULL;
+
+	if (!phandle) {
+		pr_err("invalid input power handle\n");
+		return 0;
+	}
+	mp = &phandle->mp;
+
+	for (i = 0; i < mp->num_clk; i++) {
+		if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
+			clk = mp->clk_config[i].clk;
+			break;
+		}
+	}
+
+	return clk;
+}
diff --git a/drivers/gpu/drm/msm/sde_power_handle.h b/drivers/gpu/drm/msm/sde_power_handle.h
index 3e43d80d4f8e..b982d1704312 100644
--- a/drivers/gpu/drm/msm/sde_power_handle.h
+++ b/drivers/gpu/drm/msm/sde_power_handle.h
@@ -16,6 +16,9 @@
 
 #define MAX_CLIENT_NAME_LEN 128
 
+#define SDE_POWER_HANDLE_DATA_BUS_IB_QUOTA 2000000000
+#define SDE_POWER_HANDLE_DATA_BUS_AB_QUOTA 2000000000
+
 /**
  * mdss_bus_vote_type: register bus vote type
  * VOTE_INDEX_DISABLE: removes the client vote
@@ -28,6 +31,18 @@ enum mdss_bus_vote_type {
 	VOTE_INDEX_MAX,
 };
 
+/**
+ * enum sde_power_handle_data_bus_client - type of axi bus clients
+ * @SDE_POWER_HANDLE_DATA_BUS_CLIENT_RT: core real-time bus client
+ * @SDE_POWER_HANDLE_DATA_BUS_CLIENT_NRT: core non-real-time bus client
+ * @SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX: maximum number of bus client type
+ */
+enum sde_power_handle_data_bus_client {
+	SDE_POWER_HANDLE_DATA_BUS_CLIENT_RT,
+	SDE_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
+	SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX
+};
+
 /**
  * struct sde_power_client: stores the power client for sde driver
  * @name:	name of the client
@@ -38,6 +53,8 @@ enum mdss_bus_vote_type {
  *              client.
  * @id:		assigned during create. helps for debugging.
  * @list:	list to attach power handle master list
+ * @ab:         arbitrated bandwidth for each bus client
+ * @ib:         instantaneous bandwidth for each bus client
  */
 struct sde_power_client {
 	char name[MAX_CLIENT_NAME_LEN];
@@ -45,6 +62,32 @@ struct sde_power_client {
 	short refcount;
 	u32 id;
 	struct list_head list;
+	u64 ab[SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX];
+	u64 ib[SDE_POWER_HANDLE_DATA_BUS_CLIENT_MAX];
+};
+
+/**
+ * struct sde_power_data_handle: power handle struct for data bus
+ * @data_bus_scale_table: pointer to bus scaling table
+ * @data_bus_hdl: current data bus handle
+ * @axi_port_cnt: number of rt axi ports
+ * @nrt_axi_port_cnt: number of nrt axi ports
+ * @bus_channels: number of memory bus channels
+ * @curr_bw_uc_idx: current use case index of data bus
+ * @ao_bw_uc_idx: active only use case index of data bus
+ * @bus_ref_cnt: reference count of data bus enable request
+ * @handoff_pending: True to indicate if bootloader hand-over is pending
+ */
+struct sde_power_data_bus_handle {
+	struct msm_bus_scale_pdata *data_bus_scale_table;
+	u32 data_bus_hdl;
+	u32 axi_port_cnt;
+	u32 nrt_axi_port_cnt;
+	u32 bus_channels;
+	u32 curr_bw_uc_idx;
+	u32 ao_bw_uc_idx;
+	u32 bus_ref_cnt;
+	int handoff_pending;
 };
 
 /**
@@ -52,15 +95,19 @@ struct sde_power_client {
  * @mp:		module power for clock and regulator
  * @client_clist: master list to store all clients
  * @phandle_lock: lock to synchronize the enable/disable
+ * @dev: pointer to device structure
  * @usecase_ndx: current usecase index
  * @reg_bus_hdl: current register bus handle
+ * @data_bus_handle: context structure for data bus control
  */
 struct sde_power_handle {
 	struct dss_module_power mp;
 	struct list_head power_client_clist;
 	struct mutex phandle_lock;
+	struct device *dev;
 	u32 current_usecase_ndx;
 	u32 reg_bus_hdl;
+	struct sde_power_data_bus_handle data_bus_handle;
 };
 
 /**
@@ -134,4 +181,49 @@ int sde_power_clk_set_rate(struct sde_power_handle *pdata, char *clock_name,
  */
 u64 sde_power_clk_get_rate(struct sde_power_handle *pdata, char *clock_name);
 
+/**
+ * sde_power_clk_get_max_rate() - get the maximum clock rate
+ * @pdata:  power handle containing the resources
+ * @clock_name: clock name to get the max rate.
+ *
+ * Return: maximum clock rate or 0 if not found.
+ */
+u64 sde_power_clk_get_max_rate(struct sde_power_handle *pdata,
+		char *clock_name);
+
+/**
+ * sde_power_clk_get_clk() - get the clock
+ * @pdata:  power handle containing the resources
+ * @clock_name: clock name to get the clk pointer.
+ *
+ * Return: Pointer to clock
+ */
+struct clk *sde_power_clk_get_clk(struct sde_power_handle *phandle,
+		char *clock_name);
+
+/**
+ * sde_power_data_bus_set_quota() - set data bus quota for power client
+ * @phandle:  power handle containing the resources
+ * @client: client information to set quota
+ * @bus_client: real-time or non-real-time bus client
+ * @ab_quota: arbitrated bus bandwidth
+ * @ib_quota: instantaneous bus bandwidth
+ *
+ * Return: zero if success, or error code otherwise
+ */
+int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient,
+		int bus_client, u64 ab_quota, u64 ib_quota);
+
+/**
+ * sde_power_data_bus_bandwidth_ctrl() - control data bus bandwidth enable
+ * @phandle:  power handle containing the resources
+ * @client: client information to bandwidth control
+ * @enable: true to enable bandwidth for data base
+ *
+ * Return: none
+ */
+void sde_power_data_bus_bandwidth_ctrl(struct sde_power_handle *phandle,
+		struct sde_power_client *pclient, int enable);
+
 #endif /* _SDE_POWER_HANDLE_H_ */
-- 
cgit v1.2.3


From 306d4ef12f8b9befd6293b0850a5411c7a19eb4c Mon Sep 17 00:00:00 2001
From: Alan Kwong <akwong@codeaurora.org>
Date: Sun, 6 Nov 2016 21:17:12 -0500
Subject: drm/msm/sde: add dynamic clock and bandwidth commit support

Current crtc supports static clock and bandwidth defined in
device tree.  Add support for dynamic clock and bandwidth
control using new atomic crtc properties. User mode
can adjust core clock rate, instantaneous and arbitrated
bandwidth per crtc commit.

Change-Id: I753a141bbc023d89f1532943f48252875883d684
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
---
 .../devicetree/bindings/display/msm/dsi.txt        |  16 +
 .../devicetree/bindings/display/msm/sde.txt        |  15 +
 .../devicetree/bindings/drm/msm/sde-dsi.txt        |  14 +
 drivers/gpu/drm/msm/dsi-staging/dsi_defs.h         |   3 +
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c          |   2 +
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.c        |  10 +
 drivers/gpu/drm/msm/msm_drv.h                      |   3 +
 drivers/gpu/drm/msm/sde/sde_core_perf.c            | 470 +++++++++++++++++++++
 drivers/gpu/drm/msm/sde/sde_core_perf.h            |  51 +++
 drivers/gpu/drm/msm/sde/sde_crtc.c                 |  38 ++
 drivers/gpu/drm/msm/sde/sde_crtc.h                 |  46 ++
 drivers/gpu/drm/msm/sde/sde_hw_catalog.c           |  55 +++
 drivers/gpu/drm/msm/sde/sde_hw_catalog.h           |  12 +
 drivers/gpu/drm/msm/sde/sde_trace.h                |  12 +
 14 files changed, 747 insertions(+)

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index f344b9e49198..ae2278fb3d1c 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -69,6 +69,20 @@ Required properties:
 Optional properties:
 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
   regulator is wanted.
+- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode
+					panels in microseconds. Driver uses this number to adjust
+					the clock rate according to the expected transfer time.
+					Increasing this value would slow down the mdp processing
+					and can result in slower performance.
+					Decreasing this value can speed up the mdp processing,
+					but this can also impact power consumption.
+					As a rule this time should not be higher than the time
+					that would be expected with the processing at the
+					dsi link rate since anyways this would be the maximum
+					transfer time that could be achieved.
+					If ping pong split is enabled, this time should not be higher
+					than two times the dsi link rate time.
+					If the property is not specified, then the default value is 14000 us.
 
 Example:
 	mdss_dsi0: qcom,mdss_dsi@fd922800 {
@@ -105,6 +119,8 @@ Example:
 		qcom,master-dsi;
 		qcom,sync-dual-dsi;
 
+		qcom,mdss-mdp-transfer-time-us = <12000>;
+
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&mdss_dsi_active>;
 		pinctrl-1 = <&mdss_dsi_suspend>;
diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 395c051476a4..7e96a05440e9 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -230,6 +230,18 @@ Optional properties:
 				for particular chipset.
 				These paths must be defined after rt-paths in
 				"qcom,msm-bus,vectors-KBps" vector request.
+- qcom,sde-max-bw-low-kbps:	This value indicates the max bandwidth in Kbps
+				that can be supported without underflow.
+				This is a low bandwidth threshold which should
+				be applied in most scenarios to be safe from
+				underflows when unable to satisfy bandwidth
+				requirements.
+- qcom,sde-max-bw-high-kbps:	This value indicates the max bandwidth in Kbps
+				that can be supported without underflow.
+				This is a high bandwidth threshold which can be
+				applied in scenarios where panel interface can
+				be more tolerant to memory latency such as
+				command mode panels.
 
 Bus Scaling Subnodes:
 - qcom,sde-reg-bus:		Property to provide Bus scaling for register access for
@@ -380,6 +392,9 @@ Example:
     qcom,sde-dram-channels = <2>;
     qcom,sde-num-nrt-paths = <1>;
 
+    qcom,sde-max-bw-high-kbps = <9000000>;
+    qcom,sde-max-bw-low-kbps = <9000000>;
+
     qcom,sde-sspp-vig-blocks {
         qcom,sde-vig-csc-off = <0x320>;
         qcom,sde-vig-qseed-off = <0x200>;
diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
index ea35d1450f0b..48a2c6c78297 100644
--- a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt
@@ -80,3 +80,17 @@ Optional properties:
 					-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
 					-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
 					-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
+- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode
+					panels in microseconds. Driver uses this number to adjust
+					the clock rate according to the expected transfer time.
+					Increasing this value would slow down the mdp processing
+					and can result in slower performance.
+					Decreasing this value can speed up the mdp processing,
+					but this can also impact power consumption.
+					As a rule this time should not be higher than the time
+					that would be expected with the processing at the
+					dsi link rate since anyways this would be the maximum
+					transfer time that could be achieved.
+					If ping pong split enabled, this time should not be higher
+					than two times the dsi link rate time.
+					If the property is not specified, then the default value is 14000 us.
\ No newline at end of file
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
index 50a07334682d..2caa32ea8f0c 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
@@ -318,12 +318,15 @@ struct dsi_video_engine_cfg {
  * @wr_mem_continue:               DCS command for write_memory_continue.
  * @insert_dcs_command:            Insert DCS command as first byte of payload
  *                                 of the pixel data.
+ * @mdp_transfer_time_us   Specifies the mdp transfer time for command mode
+ *                         panels in microseconds
  */
 struct dsi_cmd_engine_cfg {
 	u32 max_cmd_packets_interleave;
 	u32 wr_mem_start;
 	u32 wr_mem_continue;
 	bool insert_dcs_command;
+	u32 mdp_transfer_time_us;
 };
 
 /**
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
index bf50ebba1580..a1adecf81cc0 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
@@ -313,6 +313,8 @@ int dsi_conn_post_init(struct drm_connector *connector,
 		break;
 	case DSI_OP_CMD_MODE:
 		sde_kms_info_add_keystr(info, "panel mode", "command");
+		sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
+				panel->cmd_config.mdp_transfer_time_us);
 		break;
 	default:
 		pr_debug("invalid panel type:%d\n", panel->mode.panel_mode);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
index 28cfa1fba6d9..a7a39e685d4d 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
@@ -22,6 +22,8 @@
 
 #define DSI_PANEL_DEFAULT_LABEL  "Default dsi panel"
 
+#define DEFAULT_MDP_TRANSFER_TIME 14000
+
 static int dsi_panel_vreg_get(struct dsi_panel *panel)
 {
 	int rc = 0;
@@ -954,6 +956,14 @@ static int dsi_panel_parse_cmd_host_config(struct dsi_cmd_engine_cfg *cfg,
 		goto error;
 	}
 
+	if (of_property_read_u32(of_node, "qcom,mdss-mdp-transfer-time-us",
+				&val)) {
+		pr_debug("[%s] Fallback to default transfer-time-us\n", name);
+		cfg->mdp_transfer_time_us = DEFAULT_MDP_TRANSFER_TIME;
+	} else {
+		cfg->mdp_transfer_time_us = val;
+	}
+
 error:
 	return rc;
 }
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 7ee0788a05c0..304a2a33cf04 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -125,6 +125,9 @@ enum msm_mdp_crtc_property {
 	CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT,
 	CRTC_PROP_OUTPUT_FENCE,
 	CRTC_PROP_OUTPUT_FENCE_OFFSET,
+	CRTC_PROP_CORE_CLK,
+	CRTC_PROP_CORE_AB,
+	CRTC_PROP_CORE_IB,
 
 	/* total # of properties */
 	CRTC_PROP_COUNT
diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.c b/drivers/gpu/drm/msm/sde/sde_core_perf.c
index 3479cf8dbc20..0ba644d5519d 100644
--- a/drivers/gpu/drm/msm/sde/sde_core_perf.c
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.c
@@ -33,8 +33,469 @@
 #include "sde_core_perf.h"
 #include "sde_trace.h"
 
+static struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
+{
+	struct msm_drm_private *priv;
+
+	if (!crtc->dev || !crtc->dev->dev_private) {
+		SDE_ERROR("invalid device\n");
+		return NULL;
+	}
+
+	priv = crtc->dev->dev_private;
+	if (!priv || !priv->kms) {
+		SDE_ERROR("invalid kms\n");
+		return NULL;
+	}
+
+	return to_sde_kms(priv->kms);
+}
+
+static bool _sde_core_perf_crtc_is_power_on(struct drm_crtc *crtc)
+{
+	return sde_crtc_is_enabled(crtc);
+}
+
+static bool _sde_core_video_mode_intf_connected(struct drm_crtc *crtc)
+{
+	struct drm_crtc *tmp_crtc;
+
+	if (!crtc)
+		return 0;
+
+	drm_for_each_crtc(tmp_crtc, crtc->dev) {
+		if ((sde_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO) &&
+				_sde_core_perf_crtc_is_power_on(tmp_crtc)) {
+			SDE_DEBUG("video interface connected crtc:%d\n",
+				tmp_crtc->base.id);
+			return true;
+		}
+	}
+
+	return false;
+}
+
+int sde_core_perf_crtc_check(struct drm_crtc *crtc,
+		struct drm_crtc_state *state)
+{
+	u32 bw, threshold;
+	u64 bw_sum_of_intfs = 0;
+	bool is_video_mode;
+	struct sde_crtc_state *sde_cstate;
+	struct drm_crtc *tmp_crtc;
+	struct sde_kms *kms;
+
+	if (!crtc || !state) {
+		SDE_ERROR("invalid crtc\n");
+		return -EINVAL;
+	}
+
+	kms = _sde_crtc_get_kms(crtc);
+	if (!kms || !kms->catalog) {
+		SDE_ERROR("invalid parameters\n");
+		return 0;
+	}
+
+	/* we only need bandwidth check on real-time clients (interfaces) */
+	if (sde_crtc_is_wb(crtc))
+		return 0;
+
+	sde_cstate = to_sde_crtc_state(state);
+
+	bw_sum_of_intfs = sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_AB);
+
+	drm_for_each_crtc(tmp_crtc, crtc->dev) {
+		if (_sde_core_perf_crtc_is_power_on(tmp_crtc) &&
+				sde_crtc_is_rt(tmp_crtc) && tmp_crtc != crtc) {
+			struct sde_crtc_state *tmp_cstate =
+					to_sde_crtc_state(tmp_crtc->state);
+
+			bw_sum_of_intfs += tmp_cstate->cur_perf.bw_ctl;
+		}
+	}
+
+	/* convert bandwidth to kb */
+	bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
+	SDE_DEBUG("calculated bandwidth=%uk\n", bw);
+
+	is_video_mode = sde_crtc_get_intf_mode(crtc) == INTF_MODE_VIDEO;
+	threshold = (is_video_mode ||
+		_sde_core_video_mode_intf_connected(crtc)) ?
+		kms->catalog->perf.max_bw_low : kms->catalog->perf.max_bw_high;
+
+	SDE_DEBUG("final threshold bw limit = %d\n", threshold);
+
+	if (!threshold) {
+		sde_cstate->cur_perf.bw_ctl = 0;
+		SDE_ERROR("no bandwidth limits specified\n");
+		return -E2BIG;
+	} else if (bw > threshold) {
+		sde_cstate->cur_perf.bw_ctl = 0;
+		SDE_DEBUG("exceeds bandwidth: %ukb > %ukb\n", bw, threshold);
+		return -E2BIG;
+	}
+
+	return 0;
+}
+
+static void _sde_core_perf_calc_crtc(struct sde_kms *kms,
+		struct drm_crtc *crtc,
+		struct sde_core_perf_params *perf)
+{
+	struct sde_crtc_state *sde_cstate;
+
+	sde_cstate = to_sde_crtc_state(crtc->state);
+	memset(perf, 0, sizeof(struct sde_core_perf_params));
+
+	perf->bw_ctl = sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_AB);
+	perf->max_per_pipe_ib =
+			sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_IB);
+	perf->core_clk_rate =
+			sde_crtc_get_property(sde_cstate, CRTC_PROP_CORE_CLK);
+
+	SDE_DEBUG("crtc=%d clk_rate=%u ib=%llu ab=%llu\n",
+			crtc->base.id, perf->core_clk_rate,
+			perf->max_per_pipe_ib, perf->bw_ctl);
+}
+
+static u64 _sde_core_perf_crtc_calc_client_vote(struct sde_kms *kms,
+		struct drm_crtc *crtc, struct sde_core_perf_params *perf,
+		bool nrt_client, u32 core_clk)
+{
+	u64 bw_sum_of_intfs = 0;
+	struct drm_crtc *tmp_crtc;
+
+	drm_for_each_crtc(tmp_crtc, crtc->dev) {
+		if (_sde_core_perf_crtc_is_power_on(crtc) &&
+		    /* RealTime clients */
+		    ((!nrt_client) ||
+		    /* Non-RealTime clients */
+		    (nrt_client && sde_crtc_is_nrt(tmp_crtc)))) {
+			struct sde_crtc_state *sde_cstate =
+					to_sde_crtc_state(tmp_crtc->state);
+
+			perf->max_per_pipe_ib = max(perf->max_per_pipe_ib,
+				sde_cstate->cur_perf.max_per_pipe_ib);
+
+			bw_sum_of_intfs += sde_cstate->cur_perf.bw_ctl;
+
+			SDE_DEBUG("crtc=%d bw=%llu\n",
+				tmp_crtc->base.id,
+				sde_cstate->cur_perf.bw_ctl);
+		}
+	}
+
+	return bw_sum_of_intfs;
+}
+
+static void _sde_core_perf_crtc_update_client_vote(struct sde_kms *kms,
+	struct sde_core_perf_params *params, bool nrt_client, u64 bw_vote)
+{
+	struct msm_drm_private *priv = kms->dev->dev_private;
+	u64 bus_ab_quota, bus_ib_quota;
+
+	bus_ab_quota = max(bw_vote, kms->perf.perf_tune.min_bus_vote);
+	bus_ib_quota = params->max_per_pipe_ib;
+
+	SDE_ATRACE_INT("bus_quota", bus_ib_quota);
+	sde_power_data_bus_set_quota(&priv->phandle, kms->core_client,
+		nrt_client ? SDE_POWER_HANDLE_DATA_BUS_CLIENT_NRT :
+				SDE_POWER_HANDLE_DATA_BUS_CLIENT_RT,
+		bus_ab_quota, bus_ib_quota);
+	SDE_DEBUG("client:%s ab=%llu ib=%llu\n", nrt_client ? "nrt" : "rt",
+		bus_ab_quota, bus_ib_quota);
+}
+
+static void _sde_core_perf_crtc_update_bus(struct sde_kms *kms,
+		struct drm_crtc *crtc, u32 core_clk)
+{
+	u64 bw_sum_of_rt_intfs = 0, bw_sum_of_nrt_intfs = 0;
+	struct sde_core_perf_params params = {0};
+
+	SDE_ATRACE_BEGIN(__func__);
+
+	/*
+	 * non-real time client
+	 */
+	if (sde_crtc_is_nrt(crtc)) {
+		bw_sum_of_nrt_intfs = _sde_core_perf_crtc_calc_client_vote(
+				kms, crtc, &params, true, core_clk);
+		_sde_core_perf_crtc_update_client_vote(kms, &params, true,
+			bw_sum_of_nrt_intfs);
+	}
+
+	/*
+	 * real time client
+	 */
+	if (!sde_crtc_is_nrt(crtc) ||
+		sde_crtc_is_wb(crtc)) {
+		bw_sum_of_rt_intfs = _sde_core_perf_crtc_calc_client_vote(kms,
+				crtc, &params, false, core_clk);
+		_sde_core_perf_crtc_update_client_vote(kms, &params, false,
+			bw_sum_of_rt_intfs);
+	}
+
+	SDE_ATRACE_END(__func__);
+}
+
+/**
+ * @sde_core_perf_crtc_release_bw() - request zero bandwidth
+ * @crtc - pointer to a crtc
+ *
+ * Function checks a state variable for the crtc, if all pending commit
+ * requests are done, meaning no more bandwidth is needed, release
+ * bandwidth request.
+ */
+void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc)
+{
+	struct drm_crtc *tmp_crtc;
+	struct sde_crtc_state *sde_cstate;
+	struct sde_kms *kms;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	kms = _sde_crtc_get_kms(crtc);
+	if (!kms || !kms->catalog) {
+		SDE_ERROR("invalid kms\n");
+		return;
+	}
+
+	sde_cstate = to_sde_crtc_state(crtc->state);
+
+	/* only do this for command panel or writeback */
+	if ((sde_crtc_get_intf_mode(crtc) != INTF_MODE_CMD) &&
+			(sde_crtc_get_intf_mode(crtc) != INTF_MODE_WB_LINE))
+		return;
+
+	/*
+	 * If video interface present, cmd panel bandwidth cannot be
+	 * released.
+	 */
+	if (sde_crtc_get_intf_mode(crtc) == INTF_MODE_CMD)
+		drm_for_each_crtc(tmp_crtc, crtc->dev) {
+			if (_sde_core_perf_crtc_is_power_on(tmp_crtc) &&
+				sde_crtc_get_intf_mode(tmp_crtc) ==
+						INTF_MODE_VIDEO)
+				return;
+		}
+
+	/* Release the bandwidth */
+	if (kms->perf.enable_bw_release) {
+		trace_sde_cmd_release_bw(crtc->base.id);
+		sde_cstate->cur_perf.bw_ctl = 0;
+		sde_cstate->new_perf.bw_ctl = 0;
+		SDE_DEBUG("Release BW crtc=%d\n", crtc->base.id);
+		_sde_core_perf_crtc_update_bus(kms, crtc, 0);
+	}
+}
+
+static int _sde_core_select_clk_lvl(struct sde_kms *kms,
+			u32 clk_rate)
+{
+	return clk_round_rate(kms->perf.core_clk, clk_rate);
+}
+
+static u32 _sde_core_perf_get_core_clk_rate(struct sde_kms *kms)
+{
+	u32 clk_rate = 0;
+	struct drm_crtc *crtc;
+	struct sde_crtc_state *sde_cstate;
+	int ncrtc = 0;
+
+	drm_for_each_crtc(crtc, kms->dev) {
+		if (_sde_core_perf_crtc_is_power_on(crtc)) {
+			sde_cstate = to_sde_crtc_state(crtc->state);
+			clk_rate = max(sde_cstate->cur_perf.core_clk_rate,
+							clk_rate);
+			clk_rate = clk_round_rate(kms->perf.core_clk, clk_rate);
+		}
+		ncrtc++;
+	}
+	clk_rate = _sde_core_select_clk_lvl(kms, clk_rate);
+
+	SDE_DEBUG("clk:%u ncrtc:%d\n", clk_rate, ncrtc);
+
+	return clk_rate;
+}
+
+void sde_core_perf_crtc_update(struct drm_crtc *crtc,
+		int params_changed, bool stop_req)
+{
+	struct sde_core_perf_params *new, *old;
+	int update_bus = 0, update_clk = 0;
+	u32 clk_rate = 0;
+	struct sde_crtc *sde_crtc;
+	struct sde_crtc_state *sde_cstate;
+	int ret;
+	struct msm_drm_private *priv;
+	struct sde_kms *kms;
+
+	if (!crtc) {
+		SDE_ERROR("invalid crtc\n");
+		return;
+	}
+
+	kms = _sde_crtc_get_kms(crtc);
+	if (!kms || !kms->catalog) {
+		SDE_ERROR("invalid kms\n");
+		return;
+	}
+	priv = kms->dev->dev_private;
+
+	sde_crtc = to_sde_crtc(crtc);
+	sde_cstate = to_sde_crtc_state(crtc->state);
+
+	SDE_DEBUG("crtc:%d stop_req:%d core_clk:%u\n",
+			crtc->base.id, stop_req, kms->perf.core_clk_rate);
+
+	SDE_ATRACE_BEGIN(__func__);
+
+	old = &sde_cstate->cur_perf;
+	new = &sde_cstate->new_perf;
+
+	if (_sde_core_perf_crtc_is_power_on(crtc) && !stop_req) {
+		if (params_changed)
+			_sde_core_perf_calc_crtc(kms, crtc, new);
+
+		/*
+		 * cases for bus bandwidth update.
+		 * 1. new bandwidth vote or writeback output vote
+		 *    are higher than current vote for update request.
+		 * 2. new bandwidth vote or writeback output vote are
+		 *    lower than current vote at end of commit or stop.
+		 */
+		if ((params_changed && ((new->bw_ctl > old->bw_ctl))) ||
+		    (!params_changed && ((new->bw_ctl < old->bw_ctl)))) {
+			SDE_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
+				crtc->base.id, params_changed, new->bw_ctl,
+				old->bw_ctl);
+			old->bw_ctl = new->bw_ctl;
+			old->max_per_pipe_ib = new->max_per_pipe_ib;
+			update_bus = 1;
+		}
+
+		if ((params_changed &&
+				(new->core_clk_rate > old->core_clk_rate)) ||
+				(!params_changed &&
+				(new->core_clk_rate < old->core_clk_rate))) {
+			old->core_clk_rate = new->core_clk_rate;
+			update_clk = 1;
+		}
+	} else {
+		SDE_DEBUG("crtc=%d disable\n", crtc->base.id);
+		memset(old, 0, sizeof(*old));
+		memset(new, 0, sizeof(*new));
+		update_bus = 1;
+		update_clk = 1;
+	}
+
+	/*
+	 * Calculate mdp clock before bandwidth calculation. If traffic shaper
+	 * is enabled and clock increased, the bandwidth calculation can
+	 * use the new clock for the rotator bw calculation.
+	 */
+	if (update_clk)
+		clk_rate = _sde_core_perf_get_core_clk_rate(kms);
+
+	if (update_bus)
+		_sde_core_perf_crtc_update_bus(kms, crtc, clk_rate);
+
+	/*
+	 * Update the clock after bandwidth vote to ensure
+	 * bandwidth is available before clock rate is increased.
+	 */
+	if (update_clk) {
+		SDE_ATRACE_INT(kms->perf.clk_name, clk_rate);
+		SDE_EVT32(kms->dev, stop_req, clk_rate);
+		ret = sde_power_clk_set_rate(&priv->phandle,
+				kms->perf.clk_name, clk_rate);
+		if (ret) {
+			SDE_ERROR("failed to set %s clock rate %u\n",
+					kms->perf.clk_name, clk_rate);
+			goto end;
+		}
+
+		kms->perf.core_clk_rate = clk_rate;
+		SDE_DEBUG("update clk rate = %d HZ\n", clk_rate);
+	}
+
+end:
+	SDE_ATRACE_END(__func__);
+}
+
 #ifdef CONFIG_DEBUG_FS
 
+static ssize_t _sde_core_perf_mode_write(struct file *file,
+		    const char __user *user_buf, size_t count, loff_t *ppos)
+{
+	struct sde_core_perf *perf = file->private_data;
+	struct sde_perf_cfg *cfg = &perf->catalog->perf;
+	int perf_mode = 0;
+	char buf[10];
+
+	if (!perf)
+		return -ENODEV;
+
+	if (count >= sizeof(buf))
+		return -EFAULT;
+
+	if (copy_from_user(buf, user_buf, count))
+		return -EFAULT;
+
+	buf[count] = 0;	/* end of string */
+
+	if (kstrtoint(buf, 0, &perf_mode))
+		return -EFAULT;
+
+	if (perf_mode) {
+		/* run the driver with max clk and BW vote */
+		perf->perf_tune.min_core_clk = perf->max_core_clk_rate;
+		perf->perf_tune.min_bus_vote =
+				(u64) cfg->max_bw_high * 1000;
+	} else {
+		/* reset the perf tune params to 0 */
+		perf->perf_tune.min_core_clk = 0;
+		perf->perf_tune.min_bus_vote = 0;
+	}
+	return count;
+}
+
+static ssize_t _sde_core_perf_mode_read(struct file *file,
+			char __user *buff, size_t count, loff_t *ppos)
+{
+	struct sde_core_perf *perf = file->private_data;
+	int len = 0;
+	char buf[40] = {'\0'};
+
+	if (!perf)
+		return -ENODEV;
+
+	if (*ppos)
+		return 0;	/* the end */
+
+	len = snprintf(buf, sizeof(buf), "min_mdp_clk %lu min_bus_vote %llu\n",
+			perf->perf_tune.min_core_clk,
+			perf->perf_tune.min_bus_vote);
+	if (len < 0 || len >= sizeof(buf))
+		return 0;
+
+	if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
+		return -EFAULT;
+
+	*ppos += len;   /* increase offset */
+
+	return len;
+}
+
+static const struct file_operations sde_core_perf_mode_fops = {
+	.open = simple_open,
+	.read = _sde_core_perf_mode_read,
+	.write = _sde_core_perf_mode_write,
+};
+
 static void sde_debugfs_core_perf_destroy(struct sde_core_perf *perf)
 {
 	debugfs_remove_recursive(perf->debugfs_root);
@@ -44,6 +505,7 @@ static void sde_debugfs_core_perf_destroy(struct sde_core_perf *perf)
 static int sde_debugfs_core_perf_init(struct sde_core_perf *perf,
 		struct dentry *parent)
 {
+	struct sde_mdss_cfg *catalog = perf->catalog;
 	struct msm_drm_private *priv;
 	struct sde_kms *sde_kms;
 
@@ -65,6 +527,14 @@ static int sde_debugfs_core_perf_init(struct sde_core_perf *perf,
 			&perf->max_core_clk_rate);
 	debugfs_create_u32("core_clk_rate", 0644, perf->debugfs_root,
 			&perf->core_clk_rate);
+	debugfs_create_u32("enable_bw_release", 0644, perf->debugfs_root,
+			(u32 *)&perf->enable_bw_release);
+	debugfs_create_u32("threshold_low", 0644, perf->debugfs_root,
+			(u32 *)&catalog->perf.max_bw_low);
+	debugfs_create_u32("threshold_high", 0644, perf->debugfs_root,
+			(u32 *)&catalog->perf.max_bw_high);
+	debugfs_create_file("perf_mode", 0644, perf->debugfs_root,
+			(u32 *)perf, &sde_core_perf_mode_fops);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.h b/drivers/gpu/drm/msm/sde/sde_core_perf.h
index 172deb5f3208..e5dd9b6e6704 100644
--- a/drivers/gpu/drm/msm/sde/sde_core_perf.h
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.h
@@ -16,10 +16,33 @@
 #include <linux/types.h>
 #include <linux/dcache.h>
 #include <linux/mutex.h>
+#include <drm/drm_crtc.h>
 
 #include "sde_hw_catalog.h"
 #include "sde_power_handle.h"
 
+/**
+ * struct sde_core_perf_params - definition of performance parameters
+ * @max_per_pipe_ib: maximum instantaneous bandwidth request
+ * @bw_ctl: arbitrated bandwidth request
+ * @core_clk_rate: core clock rate request
+ */
+struct sde_core_perf_params {
+	u64 max_per_pipe_ib;
+	u64 bw_ctl;
+	u32 core_clk_rate;
+};
+
+/**
+ * struct sde_core_perf_tune - definition of performance tuning control
+ * @min_core_clk: minimum core clock
+ * @min_bus_vote: minimum bus vote
+ */
+struct sde_core_perf_tune {
+	unsigned long min_core_clk;
+	u64 min_bus_vote;
+};
+
 /**
  * struct sde_core_perf - definition of core performance context
  * @dev: Pointer to drm device
@@ -32,6 +55,8 @@
  * @core_clk: Pointer to core clock structure
  * @core_clk_rate: current core clock rate
  * @max_core_clk_rate: maximum allowable core clock rate
+ * @perf_tune: debug control for performance tuning
+ * @enable_bw_release: debug control for bandwidth release
  */
 struct sde_core_perf {
 	struct drm_device *dev;
@@ -44,8 +69,34 @@ struct sde_core_perf {
 	struct clk *core_clk;
 	u32 core_clk_rate;
 	u64 max_core_clk_rate;
+	struct sde_core_perf_tune perf_tune;
+	u32 enable_bw_release;
 };
 
+/**
+ * sde_core_perf_crtc_check - validate performance of the given crtc state
+ * @crtc: Pointer to crtc
+ * @state: Pointer to new crtc state
+ * return: zero if success, or error code otherwise
+ */
+int sde_core_perf_crtc_check(struct drm_crtc *crtc,
+		struct drm_crtc_state *state);
+
+/**
+ * sde_core_perf_crtc_update - update performance of the given crtc
+ * @crtc: Pointer to crtc
+ * @params_changed: true if crtc parameters are modified
+ * @stop_req: true if this is a stop request
+ */
+void sde_core_perf_crtc_update(struct drm_crtc *crtc,
+		int params_changed, bool stop_req);
+
+/**
+ * sde_core_perf_crtc_release_bw - release bandwidth of the given crtc
+ * @crtc: Pointer to crtc
+ */
+void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc);
+
 /**
  * sde_core_perf_destroy - destroy the given core performance context
  * @perf: Pointer to core performance context
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 6d12c0402240..083749885473 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -29,6 +29,7 @@
 #include "sde_encoder.h"
 #include "sde_connector.h"
 #include "sde_power_handle.h"
+#include "sde_core_perf.h"
 
 /* default input fence timeout, in ms */
 #define SDE_CRTC_INPUT_FENCE_TIMEOUT    2000
@@ -445,6 +446,7 @@ static void sde_crtc_frame_event_work(struct kthread_work *work)
 			SDE_EVT32(DRMID(crtc), fevent->event, 1);
 			sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
 					sde_kms->core_client, false);
+			sde_core_perf_crtc_release_bw(crtc);
 		} else {
 			SDE_EVT32(DRMID(crtc), fevent->event, 2);
 		}
@@ -765,6 +767,9 @@ static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
 	/* wait for acquire fences before anything else is done */
 	_sde_crtc_wait_for_fences(crtc);
 
+	/* update performance setting before crtc kickoff */
+	sde_core_perf_crtc_update(crtc, 1, false);
+
 	/*
 	 * Final plane updates: Give each plane a chance to complete all
 	 *                      required writes/flushing before crtc's "flush
@@ -970,9 +975,12 @@ static void sde_crtc_disable(struct drm_crtc *crtc)
 		SDE_EVT32(DRMID(crtc));
 		sde_power_data_bus_bandwidth_ctrl(&priv->phandle,
 				sde_kms->core_client, false);
+		sde_core_perf_crtc_release_bw(crtc);
 		atomic_set(&sde_crtc->frame_pending, 0);
 	}
 
+	sde_core_perf_crtc_update(crtc, 0, true);
+
 	drm_for_each_encoder(encoder, crtc->dev) {
 		if (encoder->crtc != crtc)
 			continue;
@@ -1160,6 +1168,13 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc,
 		SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos);
 	}
 
+	rc = sde_core_perf_crtc_check(crtc, state);
+	if (rc) {
+		SDE_ERROR("crtc%d failed performance check %d\n",
+				crtc->base.id, rc);
+		goto end;
+	}
+
 end:
 	return rc;
 }
@@ -1220,6 +1235,7 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
 	struct sde_crtc *sde_crtc;
 	struct drm_device *dev;
 	struct sde_kms_info *info;
+	struct sde_kms *sde_kms;
 
 	SDE_DEBUG("\n");
 
@@ -1230,6 +1246,7 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
 
 	sde_crtc = to_sde_crtc(crtc);
 	dev = crtc->dev;
+	sde_kms = _sde_crtc_get_kms(crtc);
 
 	info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
 	if (!info) {
@@ -1249,6 +1266,19 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
 			"output_fence_offset", 0x0, 0, 1, 0,
 			CRTC_PROP_OUTPUT_FENCE_OFFSET);
 
+	msm_property_install_range(&sde_crtc->property_info,
+			"core_clk", 0x0, 0, U64_MAX,
+			sde_kms->perf.max_core_clk_rate,
+			CRTC_PROP_CORE_CLK);
+	msm_property_install_range(&sde_crtc->property_info,
+			"core_ab", 0x0, 0, U64_MAX,
+			SDE_POWER_HANDLE_DATA_BUS_AB_QUOTA,
+			CRTC_PROP_CORE_AB);
+	msm_property_install_range(&sde_crtc->property_info,
+			"core_ib", 0x0, 0, U64_MAX,
+			SDE_POWER_HANDLE_DATA_BUS_IB_QUOTA,
+			CRTC_PROP_CORE_IB);
+
 	msm_property_install_blob(&sde_crtc->property_info, "capabilities",
 		DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
 	sde_kms_info_reset(info);
@@ -1545,6 +1575,10 @@ static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
 	seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
 	seq_printf(s, "is_rt: %d\n", cstate->is_rt);
 	seq_printf(s, "intf_mode: %d\n", cstate->intf_mode);
+	seq_printf(s, "bw_ctl: %llu\n", cstate->cur_perf.bw_ctl);
+	seq_printf(s, "core_clk_rate: %u\n", cstate->cur_perf.core_clk_rate);
+	seq_printf(s, "max_per_pipe_ib: %llu\n",
+			cstate->cur_perf.max_per_pipe_ib);
 
 	return 0;
 }
@@ -1568,6 +1602,10 @@ static void _sde_crtc_init_debugfs(struct sde_crtc *sde_crtc,
 			debugfs_create_file("status", S_IRUGO,
 					sde_crtc->debugfs_root,
 					sde_crtc, &debugfs_status_fops);
+			debugfs_create_file("state", S_IRUGO | S_IWUSR,
+					sde_crtc->debugfs_root,
+					&sde_crtc->base,
+					&sde_crtc_debugfs_state_fops);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
index dc5998a9124c..54c790142566 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.h
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -17,6 +17,7 @@
 #include "msm_prop.h"
 #include "sde_fence.h"
 #include "sde_kms.h"
+#include "sde_core_perf.h"
 
 #define SDE_CRTC_NAME_SIZE	12
 
@@ -146,6 +147,9 @@ struct sde_crtc_state {
 	uint64_t property_values[CRTC_PROP_COUNT];
 	uint64_t input_fence_timeout_ns;
 	struct drm_property_blob *property_blobs[CRTC_PROP_COUNT];
+
+	struct sde_core_perf_params cur_perf;
+	struct sde_core_perf_params new_perf;
 };
 
 #define to_sde_crtc_state(x) \
@@ -234,4 +238,46 @@ void sde_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
  */
 bool sde_crtc_is_rt(struct drm_crtc *crtc);
 
+/**
+ * sde_crtc_get_intf_mode - get interface mode of the given crtc
+ * @crtc: Pointert to crtc
+ */
+static inline enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc)
+{
+	struct sde_crtc_state *cstate =
+			crtc ? to_sde_crtc_state(crtc->state) : NULL;
+
+	return cstate ? cstate->intf_mode : INTF_MODE_NONE;
+}
+
+/**
+ * sde_core_perf_crtc_is_wb - check if writeback is primary output of this crtc
+ * @crtc: Pointer to crtc
+ */
+static inline bool sde_crtc_is_wb(struct drm_crtc *crtc)
+{
+	struct sde_crtc_state *cstate =
+			crtc ? to_sde_crtc_state(crtc->state) : NULL;
+
+	return cstate ? (cstate->intf_mode == INTF_MODE_WB_LINE) : false;
+}
+
+/**
+ * sde_crtc_is_nrt - check if primary output of this crtc is non-realtime client
+ * @crtc: Pointer to crtc
+ */
+static inline bool sde_crtc_is_nrt(struct drm_crtc *crtc)
+{
+	return sde_crtc_is_wb(crtc);
+}
+
+/**
+ * sde_crtc_is_enabled - check if sde crtc is enabled or not
+ * @crtc: Pointer to crtc
+ */
+static inline bool sde_crtc_is_enabled(struct drm_crtc *crtc)
+{
+	return crtc ? crtc->enabled : false;
+}
+
 #endif /* _SDE_CRTC_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index 72c0b5cfd094..1420ad67b28c 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -107,6 +107,12 @@ enum sde_prop {
 	SDE_PROP_MAX,
 };
 
+enum {
+	PERF_MAX_BW_LOW,
+	PERF_MAX_BW_HIGH,
+	PERF_PROP_MAX,
+};
+
 enum {
 	SSPP_OFF,
 	SSPP_SIZE,
@@ -267,6 +273,11 @@ static struct sde_prop_type sde_prop[] = {
 	{SRC_SPLIT, "qcom,sde-has-src-split", false, PROP_TYPE_BOOL},
 };
 
+static struct sde_prop_type sde_perf_prop[] = {
+	{PERF_MAX_BW_LOW, "qcom,sde-max-bw-low-kbps", false, PROP_TYPE_U32},
+	{PERF_MAX_BW_HIGH, "qcom,sde-max-bw-high-kbps", false, PROP_TYPE_U32},
+};
+
 static struct sde_prop_type sspp_prop[] = {
 	{SSPP_OFF, "qcom,sde-sspp-off", true, PROP_TYPE_U32_ARRAY},
 	{SSPP_SIZE, "qcom,sde-sspp-src-size", false, PROP_TYPE_U32},
@@ -1817,6 +1828,46 @@ end:
 	return rc;
 }
 
+static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
+{
+	int rc, len, prop_count[PERF_PROP_MAX];
+	struct sde_prop_value *prop_value = NULL;
+	bool prop_exists[PERF_PROP_MAX];
+
+	if (!cfg) {
+		SDE_ERROR("invalid argument\n");
+		rc = -EINVAL;
+		goto end;
+	}
+
+	prop_value = kzalloc(SDE_PROP_MAX *
+			sizeof(struct sde_prop_value), GFP_KERNEL);
+	if (!prop_value) {
+		rc = -ENOMEM;
+		goto end;
+	}
+
+	rc = _validate_dt_entry(np, sde_perf_prop, ARRAY_SIZE(sde_perf_prop),
+			prop_count, &len);
+	if (rc)
+		goto freeprop;
+
+	rc = _read_dt_entry(np, sde_perf_prop, ARRAY_SIZE(sde_perf_prop),
+			prop_count, prop_exists, prop_value);
+	if (rc)
+		goto freeprop;
+
+	cfg->perf.max_bw_low =
+			PROP_VALUE_ACCESS(prop_value, PERF_MAX_BW_LOW, 0);
+	cfg->perf.max_bw_high =
+			PROP_VALUE_ACCESS(prop_value, PERF_MAX_BW_HIGH, 0);
+
+freeprop:
+	kfree(prop_value);
+end:
+	return rc;
+}
+
 static void sde_hardware_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 {
 	switch (hw_rev) {
@@ -1918,6 +1969,10 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev)
 	if (rc)
 		goto end;
 
+	rc = sde_perf_parse_dt(np, sde_cfg);
+	if (rc)
+		goto end;
+
 	sde_hardware_caps(sde_cfg, hw_rev);
 
 	return sde_cfg;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 2625d3ea15ab..f504aa25515a 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -597,6 +597,16 @@ struct sde_vbif_cfg {
 	struct sde_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
 };
 
+/**
+ * struct sde_perf_cfg - performance control settings
+ * @max_bw_low         low threshold of maximum bandwidth (kbps)
+ * @max_bw_high        high threshold of maximum bandwidth (kbps)
+ */
+struct sde_perf_cfg {
+	u32 max_bw_low;
+	u32 max_bw_high;
+};
+
 /**
  * struct sde_mdss_cfg - information of MDSS HW
  * This is the main catalog data structure representing
@@ -658,6 +668,8 @@ struct sde_mdss_cfg {
 	u32 vbif_count;
 	struct sde_vbif_cfg vbif[MAX_BLOCKS];
 	/* Add additional block data structures here */
+
+	struct sde_perf_cfg perf;
 };
 
 struct sde_mdss_hw_cfg_handler {
diff --git a/drivers/gpu/drm/msm/sde/sde_trace.h b/drivers/gpu/drm/msm/sde/sde_trace.h
index 26e3afa50a3e..2a4e6b59a08c 100644
--- a/drivers/gpu/drm/msm/sde/sde_trace.h
+++ b/drivers/gpu/drm/msm/sde/sde_trace.h
@@ -113,6 +113,18 @@ TRACE_EVENT(sde_perf_update_bus,
 )
 
 
+TRACE_EVENT(sde_cmd_release_bw,
+	TP_PROTO(u32 crtc_id),
+	TP_ARGS(crtc_id),
+	TP_STRUCT__entry(
+			__field(u32, crtc_id)
+	),
+	TP_fast_assign(
+			__entry->crtc_id = crtc_id;
+	),
+	TP_printk("crtc:%d", __entry->crtc_id)
+);
+
 TRACE_EVENT(sde_mark_write,
 	TP_PROTO(int pid, const char *name, bool trace_begin),
 	TP_ARGS(pid, name, trace_begin),
-- 
cgit v1.2.3


From c58bfaf5bb0d72c12ab429a3ffae82ff62cac8ef Mon Sep 17 00:00:00 2001
From: Dhaval Patel <pdhaval@codeaurora.org>
Date: Thu, 12 Jan 2017 09:59:31 -0800
Subject: drm/msm/sde: parse csc type dtsi entry to select valid csc

msm8998 supports 10bit csc while msm8996 supports csc only.
This patch adds the dtsi entry to select the correct csc
type while parsing hardware catalog to configure the
valid csc hardware block.

Change-Id: I376f1e485a5de4a95d03e395e06d10b043036cb0
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
---
 .../devicetree/bindings/display/msm/sde.txt         |  5 ++++-
 arch/arm/boot/dts/qcom/msm8996-sde.dtsi             |  3 ++-
 drivers/gpu/drm/msm/sde/sde_hw_catalog.c            | 21 ++++++++++++++++++---
 drivers/gpu/drm/msm/sde/sde_hw_catalog.h            |  4 +++-
 4 files changed, 27 insertions(+), 6 deletions(-)

(limited to 'Documentation/devicetree')

diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 7e96a05440e9..c9e7d7423d7f 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -102,10 +102,13 @@ Optional properties:
 - qcom,sde-sspp-scale-size:	A u32 value indicates the scaling block size on sspp.
 - qcom,sde-mixer-blendstages:	A u32 value indicates the max mixer blend stages for
 				alpha blending.
-- qcom,sde-qseed-type:		A string entry indiates qseed support on sspp and wb.
+- qcom,sde-qseed-type:		A string entry indicates qseed support on sspp and wb.
 				It supports "qssedv3" and "qseedv2" entries for qseed
 				type. By default "qseedv2" is used if this optional property
 				is not defined.
+- qcom,sde-csc-type:		A string entry indicates csc support on sspp and wb.
+				It supports "csc" and "csc-10bit" entries for csc
+				type.
 - qcom,sde-highest-bank-bit:	A u32 property to indicate GPU/Camera/Video highest memory
 				bank bit used for tile format buffers.
 - qcom,sde-panic-per-pipe:	Boolean property to indicate if panic signal
diff --git a/arch/arm/boot/dts/qcom/msm8996-sde.dtsi b/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
index d59c8471418f..8aebac3b0e22 100644
--- a/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-sde.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -96,6 +96,7 @@
 				  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
 				  <0x3b0 16>;
 		qcom,sde-qseed-type = "qseedv2";
+		qcom,sde-csc-type = "csc";
 		qcom,sde-mixer-linewidth = <2560>;
 		qcom,sde-sspp-linewidth = <2560>;
 		qcom,sde-mixer-blendstages = <0x7>;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index 1420ad67b28c..31a6d985c38f 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -101,6 +101,7 @@ enum sde_prop {
 	WB_LINEWIDTH,
 	BANK_BIT,
 	QSEED_TYPE,
+	CSC_TYPE,
 	PANIC_PER_PIPE,
 	CDP,
 	SRC_SPLIT,
@@ -268,6 +269,7 @@ static struct sde_prop_type sde_prop[] = {
 	{WB_LINEWIDTH, "qcom,sde-wb-linewidth", false, PROP_TYPE_U32},
 	{BANK_BIT, "qcom,sde-highest-bank-bit", false, PROP_TYPE_U32},
 	{QSEED_TYPE, "qcom,sde-qseed-type", false, PROP_TYPE_STRING},
+	{CSC_TYPE, "qcom,sde-csc-type", false, PROP_TYPE_STRING},
 	{PANIC_PER_PIPE, "qcom,sde-panic-per-pipe", false, PROP_TYPE_BOOL},
 	{CDP, "qcom,sde-has-cdp", false, PROP_TYPE_BOOL},
 	{SRC_SPLIT, "qcom,sde-has-src-split", false, PROP_TYPE_BOOL},
@@ -674,8 +676,15 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg,
 	}
 
 	sblk->csc_blk.id = SDE_SSPP_CSC;
-	set_bit(SDE_SSPP_CSC, &sspp->features);
-	sblk->csc_blk.base = PROP_VALUE_ACCESS(prop_value, VIG_CSC_OFF, 0);
+	if (sde_cfg->csc_type == SDE_SSPP_CSC) {
+		set_bit(SDE_SSPP_CSC, &sspp->features);
+		sblk->csc_blk.base = PROP_VALUE_ACCESS(prop_value,
+							VIG_CSC_OFF, 0);
+	} else if (sde_cfg->csc_type == SDE_SSPP_CSC_10BIT) {
+		set_bit(SDE_SSPP_CSC_10BIT, &sspp->features);
+		sblk->csc_blk.base = PROP_VALUE_ACCESS(prop_value,
+							VIG_CSC_OFF, 0);
+	}
 
 	sblk->hsic_blk.id = SDE_SSPP_HSIC;
 	if (prop_exists[VIG_HSIC_PROP]) {
@@ -1822,6 +1831,12 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
 	else if (!rc && !strcmp(type, "qseedv2"))
 		cfg->qseed_type = SDE_SSPP_SCALER_QSEED2;
 
+	rc = of_property_read_string(np, sde_prop[CSC_TYPE].prop_name, &type);
+	if (!rc && !strcmp(type, "csc"))
+		cfg->csc_type = SDE_SSPP_CSC;
+	else if (!rc && !strcmp(type, "csc-10bit"))
+		cfg->csc_type = SDE_SSPP_CSC_10BIT;
+
 	cfg->has_src_split = PROP_VALUE_ACCESS(prop_value, SRC_SPLIT, 0);
 end:
 	kfree(prop_value);
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index f504aa25515a..a8f9169aaf35 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -620,6 +620,7 @@ struct sde_perf_cfg {
  * @max_wb_linewidth   max writeback line width support.
  * @highest_bank_bit   highest memory bit setting for tile buffers.
  * @qseed_type         qseed2 or qseed3 support.
+ * @csc_type           csc or csc_10bit support.
  * @has_src_split      source split feature status
  * @has_cdp            Client driver prefetch feature status
  */
@@ -632,6 +633,7 @@ struct sde_mdss_cfg {
 	u32 max_wb_linewidth;
 	u32 highest_bank_bit;
 	u32 qseed_type;
+	u32 csc_type;
 	bool has_src_split;
 	bool has_cdp;
 
-- 
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