From cb6db5d817cd31821c78170d2cfc269582d4a9e5 Mon Sep 17 00:00:00 2001 From: Maya Erez Date: Wed, 3 May 2017 11:36:41 +0300 Subject: ARM: dts: msm: enable SMMU stage1 for 11AD devices on msm8998 Set smmu-s1-en to enable SMMU stage1. This change also sets SMMU base address and size, required when SMMU stage1 is enabled. Change-Id: I30f4528c665c7623cb56de0773a0a3da2b4c21bf Signed-off-by: Maya Erez --- arch/arm/boot/dts/qcom/msm8998.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom/msm8998.dtsi b/arch/arm/boot/dts/qcom/msm8998.dtsi index c25f3ebcb113..c1d785e42669 100644 --- a/arch/arm/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998.dtsi @@ -3200,6 +3200,10 @@ <&clock_gcc clk_rf_clk3_pin>; clock-names = "rf_clk3_clk", "rf_clk3_pin_clk"; qcom,smmu-support; + qcom,smmu-s1-en; + qcom,smmu-fast-map; + qcom,smmu-coherent; + qcom,smmu-mapping = <0x20000000 0xe0000000>; status = "disabled"; }; -- cgit v1.2.3