From 51f105d3074e8711698902ff89fcdc56193389ff Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 29 Jan 2015 16:06:42 +0100 Subject: MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculation The Au1000 and Au1500 calculate the LRCLK a bit differently than newer models: a single bit in MEM_STCFG0 selects if pclk is divided by 4 or 5. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Patchwork: https://patchwork.linux-mips.org/patch/9148/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/clock.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'arch/mips/alchemy/common') diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c index 48a9dfc55b51..ade73375ede6 100644 --- a/arch/mips/alchemy/common/clock.c +++ b/arch/mips/alchemy/common/clock.c @@ -315,17 +315,26 @@ static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct) /* lrclk: external synchronous static bus clock ***********************/ -static struct clk __init *alchemy_clk_setup_lrclk(const char *pn) +static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t) { - /* MEM_STCFG0[15:13] = divisor. + /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5, + * otherwise lrclk=pclk/4. + * All other variants: MEM_STCFG0[15:13] = divisor. * L/RCLK = periph_clk / (divisor + 1) * On Au1000, Au1500, Au1100 it's called LCLK, * on later models it's called RCLK, but it's the same thing. */ struct clk *c; - unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13; + unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0); - v = (v & 7) + 1; + switch (t) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + v = 4 + ((v >> 11) & 1); + break; + default: /* all other models */ + v = ((v >> 13) & 7) + 1; + } c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK, pn, 0, 1, v); if (!IS_ERR(c)) @@ -1060,7 +1069,7 @@ static int __init alchemy_clk_init(void) ERRCK(c) /* L/RCLK: external static bus clock for synchronous mode */ - c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK); + c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype); ERRCK(c) /* Frequency dividers 0-5 */ -- cgit v1.2.3 From 45a848f7fa067a81ae606bb06b2edcdf53772eac Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 29 Jan 2015 16:06:43 +0100 Subject: MIPS: Alchemy: preset loops_per_jiffy based on CPU clock This was lost during the rewrite of clock framework support. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Patchwork: https://patchwork.linux-mips.org/patch/9149/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/clock.c | 6 ++++++ arch/mips/alchemy/common/setup.c | 3 +++ 2 files changed, 9 insertions(+) (limited to 'arch/mips/alchemy/common') diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c index ade73375ede6..3612d76007a4 100644 --- a/arch/mips/alchemy/common/clock.c +++ b/arch/mips/alchemy/common/clock.c @@ -133,6 +133,12 @@ static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw, return t; } +void __init alchemy_set_lpj(void) +{ + preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE); + preset_lpj /= 2 * HZ; +} + static struct clk_ops alchemy_clkops_cpu = { .recalc_rate = alchemy_clk_cpu_recalc, }; diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 4e72daf12c32..9a0c4c8da106 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -35,9 +35,12 @@ extern void __init board_setup(void); extern void set_cpuspec(void); +extern void __init alchemy_set_lpj(void); void __init plat_mem_setup(void) { + alchemy_set_lpj(); + if (au1xxx_cpu_needs_config_od()) /* Various early Au1xx0 errata corrected by this */ set_c0_config(1 << 19); /* Set Config[OD] */ -- cgit v1.2.3 From 200276e6730c2817a77cfa6fc7e39ab3a63c4646 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 29 Jan 2015 16:06:44 +0100 Subject: MIPS: Alchemy: remove declaration for set_cpuspec set_cpuspec() has been dropped with commit 074cf656700ddd1d2bd7f815f78e785418beb898 ("MIPS: Alchemy: remove cpu_table.") in late 2008. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Patchwork: https://patchwork.linux-mips.org/patch/9150/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/setup.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/alchemy/common') diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 9a0c4c8da106..2902138b3e0f 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -34,7 +34,6 @@ #include extern void __init board_setup(void); -extern void set_cpuspec(void); extern void __init alchemy_set_lpj(void); void __init plat_mem_setup(void) -- cgit v1.2.3 From 69e4e63ec816a7e22cc3aa14bc7ef4ac734d370c Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 18 Feb 2015 11:01:56 +0100 Subject: MIPS: Alchemy: Fix cpu clock calculation The current code uses bits 0-6 of the sys_cpupll register to calculate core clock speed. However this is only valid on Au1300, on all earlier models the hardware only uses bits 0-5 to generate core clock. This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll is set as well, which ultimately lead the code to calculate a bogus cpu core clock and also uart base clock down the line. Signed-off-by: Manuel Lauss Reported-by: John Crispin Tested-by: Bruno Randolf Cc: stable@vger.kernel.org [v3.17+] Cc: Linux-MIPS Patchwork: https://patchwork.linux-mips.org/patch/9279/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/clock.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/alchemy/common') diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c index 3612d76007a4..4b5ec49139c2 100644 --- a/arch/mips/alchemy/common/clock.c +++ b/arch/mips/alchemy/common/clock.c @@ -127,6 +127,8 @@ static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw, t = 396000000; else { t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f; + if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300) + t &= 0x3f; t *= parent_rate; } -- cgit v1.2.3