From 4481e8eea761857367162b0957277d5524fbea63 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 6 Jun 2005 13:35:57 -0700 Subject: [PATCH] ppc32: Fix incorrect CPU_FTR fixup usage for unified caches Runtime feature support for unified caches was testing a userland feature flag (PPC_FEATURE_UNIFIED_CACHE) instead of a cpu feature flag (CPU_FTR_SPLIT_ID_CACHE). Luckily the current defined bit mask for cpu features and userland features do not overlap so this only causes an issue on machines with a unified cache, which is extremely rare on PPC today. Signed-off-by: Kumar Gala Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/misc.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index e4f1615ec13f..7329ef177a18 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S @@ -619,7 +619,7 @@ _GLOBAL(flush_instruction_cache) _GLOBAL(flush_icache_range) BEGIN_FTR_SECTION blr /* for 601, do nothing */ -END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) +END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) li r5,L1_CACHE_LINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 @@ -736,7 +736,7 @@ _GLOBAL(flush_dcache_all) _GLOBAL(__flush_dcache_icache) BEGIN_FTR_SECTION blr /* for 601, do nothing */ -END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) +END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) rlwinm r3,r3,0,0,19 /* Get page base address */ li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */ mtctr r4 @@ -764,7 +764,7 @@ END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) _GLOBAL(__flush_dcache_icache_phys) BEGIN_FTR_SECTION blr /* for 601, do nothing */ -END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) +END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) mfmsr r10 rlwinm r0,r10,0,28,26 /* clear DR */ mtmsr r0 -- cgit v1.2.3 From ad95d6098dd1e94a09d2a1fdf39fd8281fcd8958 Mon Sep 17 00:00:00 2001 From: Eugene Surovegin Date: Tue, 7 Jun 2005 13:22:09 -0700 Subject: [PATCH] ppc32: add 405EP cpu_spec entry Add a definition for PPC 405EP which was lost somehow during 2.4 -> 2.6 transition. Recent change to arch/ppc/kernel/misc.S ("Fix incorrect CPU_FTR fixup usage for unified caches") triggered this bug and 405EP boards don't boot anymore. Signed-off-by: Eugene Surovegin Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/ppc') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 8aa5e8c69009..d44b7dc5390a 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -838,6 +838,17 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 405EP */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x51210000, + .cpu_name = "405EP", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | + PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_40x */ #ifdef CONFIG_44x -- cgit v1.2.3 From beb9e1c3f32a0f878765c7c1142f91083739c5bd Mon Sep 17 00:00:00 2001 From: Eugene Surovegin Date: Wed, 8 Jun 2005 15:48:42 -0700 Subject: [PATCH] ppc32: add 405EP cpu_spec entry Add a definition for PPC 405EP which was lost somehow during 2.4 -> 2.6 transition. Recent change to arch/ppc/kernel/misc.S ("Fix incorrect CPU_FTR fixup usage for unified caches") triggered this bug and 405EP boards don't boot anymore. Signed-off-by: Eugene Surovegin Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/ppc') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index d44b7dc5390a..17abf6cd0d90 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -849,6 +849,17 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 405EP */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x51210000, + .cpu_name = "405EP", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | + PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_40x */ #ifdef CONFIG_44x -- cgit v1.2.3 From 7fbdf1a23be1837b8bc5bcec096015ca99e00aa7 Mon Sep 17 00:00:00 2001 From: Eugene Surovegin Date: Thu, 9 Jun 2005 12:36:29 -0700 Subject: [PATCH] ppc32: add 405EP cpu_spec entry Add a definition for PPC 405EP which was lost somehow during 2.4 -> 2.6 transition. Recent change to arch/ppc/kernel/misc.S ("Fix incorrect CPU_FTR fixup usage for unified caches") triggered this bug and 405EP boards don't boot anymore. Signed-off-by: Eugene Surovegin Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/ppc') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 17abf6cd0d90..ce2618ac8ac2 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -860,6 +860,17 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 405EP */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x51210000, + .cpu_name = "405EP", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | + PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_40x */ #ifdef CONFIG_44x -- cgit v1.2.3 From 0086b5ec7834b78358dea3f713275a9ae2b229ec Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 10 Jun 2005 14:19:02 +1000 Subject: [PATCH] ppc32: Fix nasty sleep/wakeup problem Despite all the care lately in making the powermac sleep/wakeup as robust as possible, there is still a nasty related to the use of cpufreq on PMU based machines. Unfortunately, it affects paulus old powerbook so I have to fix it :) We didn't manage to understand what is precisely going on, it leads to memory corruption and might have to do with RAM not beeing properly refreshed when a cpufreq transition is done right before the sleep. The best workaround (and less intrusive at this point) we could come up with is included in this patch. We basically do _not_ force a switch to high speed on suspend anymore (that is what is causing the problem) on those machines. We still force a speed switch on wakeup (since we don't know what speed we are coming back from sleep at, and that seems to work fine). Since, during this short interval, the actual CPU speed might be incorrect, we also hack around by multiplying loops_per_jiffy by 2 (max speed factor on those machines) during early wakeup stage to make sure udelay's during that time aren't too short. For after 2.6.12, we'll change udelay implementation to use the CPU timebase (which is always constant) instead like we do on ppc64 and thus get rid of all those problems. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Linus Torvalds --- arch/ppc/platforms/pmac_cpufreq.c | 7 +++++-- drivers/macintosh/via-pmu.c | 6 ++++++ 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/platforms/pmac_cpufreq.c b/arch/ppc/platforms/pmac_cpufreq.c index 937f46df711e..5fdd4f607a40 100644 --- a/arch/ppc/platforms/pmac_cpufreq.c +++ b/arch/ppc/platforms/pmac_cpufreq.c @@ -83,7 +83,7 @@ static u32 frequency_gpio; static u32 slew_done_gpio; static int no_schedule; static int has_cpu_l2lve; - +static int is_pmu_based; /* There are only two frequency states for each processor. Values * are in kHz for the time being. @@ -463,7 +463,7 @@ static int __pmac pmac_cpufreq_suspend(struct cpufreq_policy *policy, u32 state) */ no_schedule = 1; sleep_freq = cur_freq; - if (cur_freq == low_freq) + if (cur_freq == low_freq && !is_pmu_based) do_set_cpu_speed(CPUFREQ_HIGH, 0); return 0; } @@ -588,6 +588,7 @@ static int __pmac pmac_cpufreq_init_MacRISC3(struct device_node *cpunode) return 1; hi_freq = (*value) / 1000; set_speed_proc = pmu_set_cpu_speed; + is_pmu_based = 1; return 0; } @@ -692,6 +693,7 @@ static int __init pmac_cpufreq_setup(void) hi_freq = cur_freq; low_freq = 400000; set_speed_proc = pmu_set_cpu_speed; + is_pmu_based = 1; } /* Else check for TiPb 400 & 500 */ else if (machine_is_compatible("PowerBook3,2")) { @@ -703,6 +705,7 @@ static int __init pmac_cpufreq_setup(void) hi_freq = cur_freq; low_freq = 300000; set_speed_proc = pmu_set_cpu_speed; + is_pmu_based = 1; } /* Else check for 750FX */ else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000) diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c index bb9f4044c74d..b941ee220997 100644 --- a/drivers/macintosh/via-pmu.c +++ b/drivers/macintosh/via-pmu.c @@ -2593,6 +2593,9 @@ powerbook_sleep_Core99(void) /* Restore VIA */ restore_via_state(); + /* tweak LPJ before cpufreq is there */ + loops_per_jiffy *= 2; + /* Restore video */ pmac_call_early_video_resume(); @@ -2613,6 +2616,9 @@ powerbook_sleep_Core99(void) pmu_request(&req, NULL, 2, PMU_SET_INTR_MASK, pmu_intr_mask); pmu_wait_complete(&req); + /* Restore LPJ, cpufreq will adjust the cpu frequency */ + loops_per_jiffy /= 2; + pmac_wakeup_devices(); return 0; -- cgit v1.2.3 From 90abb7b5f3bd9271a455cd640a70c285b4fd0c89 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Fri, 10 Jun 2005 09:37:21 -0700 Subject: ppc: remove two extraneous descriptors for the 405EP CPU The patch to add them keeps on getting applied, over and over again ;) Hopefully no more. --- arch/ppc/kernel/cputable.c | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index ce2618ac8ac2..d44b7dc5390a 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -849,28 +849,6 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, - { /* 405EP */ - .pvr_mask = 0xffff0000, - .pvr_value = 0x51210000, - .cpu_name = "405EP", - .cpu_features = CPU_FTR_SPLIT_ID_CACHE | - CPU_FTR_USE_TB, - .cpu_user_features = PPC_FEATURE_32 | - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, - .icache_bsize = 32, - .dcache_bsize = 32, - }, - { /* 405EP */ - .pvr_mask = 0xffff0000, - .pvr_value = 0x51210000, - .cpu_name = "405EP", - .cpu_features = CPU_FTR_SPLIT_ID_CACHE | - CPU_FTR_USE_TB, - .cpu_user_features = PPC_FEATURE_32 | - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, - .icache_bsize = 32, - .dcache_bsize = 32, - }, #endif /* CONFIG_40x */ #ifdef CONFIG_44x -- cgit v1.2.3