From 460d0d444822e9032a2573fc051b45c68b89a97a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 18 Jul 2014 15:48:35 -0300 Subject: clk: sunxi: Add a driver for the PLL2 The PLL2 on the A10 and later SoCs is the clock used for all the audio related operations. This clock has a somewhat complex output tree, with three outputs (2X, 4X and 8X) with a fixed divider from the base clock, and an output (1X) with a post divider. However, we can simplify things since the 1X divider can be fixed, and we end up by having a base clock not exposed to any device (or at least directly, since the 4X output doesn't have any divider), and 4 fixed divider clocks that will be exposed. This clock seems to have been introduced, at least in this form, in the revision B of the A10, but we don't have any information on the clock used on the revision A. Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai --- drivers/clk/sunxi/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/sunxi/Makefile') diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index f5a35b82cc1a..c658a18ba7cb 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -4,6 +4,7 @@ obj-y += clk-sunxi.o clk-factors.o obj-y += clk-a10-hosc.o +obj-y += clk-a10-pll2.o obj-y += clk-a20-gmac.o obj-y += clk-mod0.o obj-y += clk-simple-gates.o -- cgit v1.2.3