From 87b045969ad3fe021ccbd1ed88e7cb90adf4ca80 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 14 Sep 2015 11:55:37 +0300 Subject: dmaengine: idma64: convert to __ffs() We replace __fls() by __ffs() since we have to find a *minimum* data width that satisfies both source and destination. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/idma64.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/dma/idma64.c') diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c index 18c14e1f1414..13c52b87d59b 100644 --- a/drivers/dma/idma64.c +++ b/drivers/dma/idma64.c @@ -257,15 +257,15 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, dar = config->dst_addr; ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC | IDMA64C_CTLL_FC_M2P; - src_width = min_t(u32, 2, __fls(sar | hw->len)); - dst_width = __fls(config->dst_addr_width); + src_width = min_t(u32, 2, __ffs(sar | hw->len)); + dst_width = __ffs(config->dst_addr_width); } else { /* DMA_DEV_TO_MEM */ sar = config->src_addr; dar = hw->phys; ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX | IDMA64C_CTLL_FC_P2M; - src_width = __fls(config->src_addr_width); - dst_width = min_t(u32, 2, __fls(dar | hw->len)); + src_width = __ffs(config->src_addr_width); + dst_width = min_t(u32, 2, __ffs(dar | hw->len)); } lli->sar = sar; -- cgit v1.2.3 From 22b74406c5ac1829cd60f75c8c6a4ed1e0f4da03 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 14 Sep 2015 11:55:38 +0300 Subject: dmaengine: idma64: useless use of min_t() We use a pattern x = min_t(u32, , __ffs(expr)); There is no need to use min_t() since we can replace it by x = __ffs(expr | <2^LOG2_CONST>); and moreover guarantee that argument of __ffs() will be not zero. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/idma64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/dma/idma64.c') diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c index 13c52b87d59b..e91e499b0d91 100644 --- a/drivers/dma/idma64.c +++ b/drivers/dma/idma64.c @@ -257,7 +257,7 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, dar = config->dst_addr; ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC | IDMA64C_CTLL_FC_M2P; - src_width = min_t(u32, 2, __ffs(sar | hw->len)); + src_width = __ffs(sar | hw->len | 4); dst_width = __ffs(config->dst_addr_width); } else { /* DMA_DEV_TO_MEM */ sar = config->src_addr; @@ -265,7 +265,7 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX | IDMA64C_CTLL_FC_P2M; src_width = __ffs(config->src_addr_width); - dst_width = min_t(u32, 2, __ffs(dar | hw->len)); + dst_width = __ffs(dar | hw->len | 4); } lli->sar = sar; -- cgit v1.2.3 From 2e9b55becc905207eb01e24bc282f8062cc497b5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 14 Sep 2015 11:55:40 +0300 Subject: dmaengine: idma64: make better performance on pause / resume Accordingly to the documentation the CH_DRAIN bit enforses single bursts when channel is going to be suspended. This, in case when channel will be resumed, makes data to flow in non-optimal mode until DMA returns to full burst mode. The fix differentiates pause / resume cycle from pause / terminate and sets CH_DRAIN bit accordingly. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/idma64.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers/dma/idma64.c') diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c index e91e499b0d91..39e6ab1d01fb 100644 --- a/drivers/dma/idma64.c +++ b/drivers/dma/idma64.c @@ -65,9 +65,6 @@ static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c) u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0); u32 cfglo = 0; - /* Enforce FIFO drain when channel is suspended */ - cfglo |= IDMA64C_CFGL_CH_DRAIN; - /* Set default burst alignment */ cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN; @@ -428,12 +425,17 @@ static int idma64_slave_config(struct dma_chan *chan, return 0; } -static void idma64_chan_deactivate(struct idma64_chan *idma64c) +static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain) { unsigned short count = 100; u32 cfglo; cfglo = channel_readl(idma64c, CFG_LO); + if (drain) + cfglo |= IDMA64C_CFGL_CH_DRAIN; + else + cfglo &= ~IDMA64C_CFGL_CH_DRAIN; + channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP); do { udelay(1); @@ -456,7 +458,7 @@ static int idma64_pause(struct dma_chan *chan) spin_lock_irqsave(&idma64c->vchan.lock, flags); if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) { - idma64_chan_deactivate(idma64c); + idma64_chan_deactivate(idma64c, false); idma64c->desc->status = DMA_PAUSED; } spin_unlock_irqrestore(&idma64c->vchan.lock, flags); @@ -486,7 +488,7 @@ static int idma64_terminate_all(struct dma_chan *chan) LIST_HEAD(head); spin_lock_irqsave(&idma64c->vchan.lock, flags); - idma64_chan_deactivate(idma64c); + idma64_chan_deactivate(idma64c, true); idma64_stop_transfer(idma64c); if (idma64c->desc) { idma64_vdesc_free(&idma64c->desc->vdesc); -- cgit v1.2.3