From da23c02138f79eacef6f8adfbf75db2a4a14f3ad Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Tue, 27 Dec 2016 19:03:35 +0530 Subject: msm: Rename msmfalcon/apqfalcon to sdm660/sda660 Update the code name from msmfalcon/apqfalcon to sdm660/sda660. As part of this, update the filename containing "falcon" and files content containing "falcon". Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc Signed-off-by: Neeraj Upadhyay --- drivers/clk/msm/Kconfig | 2 +- drivers/clk/qcom/Kconfig | 22 +- drivers/clk/qcom/Makefile | 6 +- drivers/clk/qcom/clk-smd-rpm.c | 142 +- drivers/clk/qcom/gcc-msmfalcon.c | 3322 --------------------------- drivers/clk/qcom/gcc-sdm660.c | 3322 +++++++++++++++++++++++++++ drivers/clk/qcom/gpucc-msmfalcon.c | 498 ---- drivers/clk/qcom/gpucc-sdm660.c | 498 ++++ drivers/clk/qcom/mdss/mdss-pll.c | 6 +- drivers/clk/qcom/mdss/mdss-pll.h | 2 +- drivers/clk/qcom/mmcc-msmfalcon.c | 3056 ------------------------ drivers/clk/qcom/mmcc-sdm660.c | 3056 ++++++++++++++++++++++++ drivers/clk/qcom/vdd-level-660.h | 152 ++ drivers/clk/qcom/vdd-level-falcon.h | 152 -- drivers/crypto/Kconfig | 8 +- drivers/leds/leds-qpnp-flash-v2.c | 2 +- drivers/leds/leds-qpnp-wled.c | 34 +- drivers/phy/Makefile | 2 +- drivers/phy/phy-qcom-ufs-qmp-v3-660.c | 260 +++ drivers/phy/phy-qcom-ufs-qmp-v3-660.h | 283 +++ drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c | 260 --- drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h | 283 --- drivers/pinctrl/qcom/Kconfig | 6 +- drivers/pinctrl/qcom/Makefile | 2 +- drivers/pinctrl/qcom/pinctrl-msmfalcon.c | 1722 -------------- drivers/pinctrl/qcom/pinctrl-sdm660.c | 1722 ++++++++++++++ drivers/platform/msm/qpnp-revid.c | 4 +- drivers/power/qcom-charger/qpnp-fg-gen3.c | 2 +- drivers/power/qcom-charger/qpnp-smb2.c | 2 +- drivers/regulator/cpr4-mmss-ldo-regulator.c | 94 +- drivers/regulator/msm_gfx_ldo.c | 12 +- drivers/soc/qcom/socinfo.c | 14 +- drivers/thermal/msm-tsens.c | 8 +- 33 files changed, 9478 insertions(+), 9478 deletions(-) delete mode 100644 drivers/clk/qcom/gcc-msmfalcon.c create mode 100644 drivers/clk/qcom/gcc-sdm660.c delete mode 100644 drivers/clk/qcom/gpucc-msmfalcon.c create mode 100644 drivers/clk/qcom/gpucc-sdm660.c delete mode 100644 drivers/clk/qcom/mmcc-msmfalcon.c create mode 100644 drivers/clk/qcom/mmcc-sdm660.c create mode 100644 drivers/clk/qcom/vdd-level-660.h delete mode 100644 drivers/clk/qcom/vdd-level-falcon.h create mode 100644 drivers/phy/phy-qcom-ufs-qmp-v3-660.c create mode 100644 drivers/phy/phy-qcom-ufs-qmp-v3-660.h delete mode 100644 drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c delete mode 100644 drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h delete mode 100644 drivers/pinctrl/qcom/pinctrl-msmfalcon.c create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm660.c (limited to 'drivers') diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig index bfb697347ec5..3829f6aec124 100644 --- a/drivers/clk/msm/Kconfig +++ b/drivers/clk/msm/Kconfig @@ -7,7 +7,7 @@ config COMMON_CLK_MSM This support clock controller used by MSM devices which support global, mmss and gpu clock controller. Say Y if you want to support the clocks exposed by the MSM on - platforms such as msm8996, msm8998, msmfalcon etc. + platforms such as msm8996, msm8998 etc. config MSM_CLK_CONTROLLER_V2 bool "QTI clock driver" diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b5dd556b3f96..5a6b62892328 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -153,33 +153,33 @@ config MSM_MMCC_8996 Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. -config MSM_GCC_FALCON - tristate "MSMFALCON Global Clock Controller" +config MSM_GCC_660 + tristate "SDM660 Global Clock Controller" select QCOM_GDSC depends on COMMON_CLK_QCOM ---help--- Support for the global clock controller on Qualcomm Technologies, Inc - MSMfalcon devices. + SDM660 devices. Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SD/eMMC, PCIe, etc. -config MSM_GPUCC_FALCON - tristate "MSMFALCON Graphics Clock Controller" - select MSM_GCC_FALCON +config MSM_GPUCC_660 + tristate "SDM660 Graphics Clock Controller" + select MSM_GCC_660 depends on COMMON_CLK_QCOM help Support for the graphics clock controller on Qualcomm Technologies, Inc - MSMfalcon devices. + SDM660 devices. Say Y if you want to support graphics controller devices which will be required to enable those device. -config MSM_MMCC_FALCON - tristate "MSMFALCON Multimedia Clock Controller" - select MSM_GCC_FALCON +config MSM_MMCC_660 + tristate "SDM660 Multimedia Clock Controller" + select MSM_GCC_660 depends on COMMON_CLK_QCOM help Support for the multimedia clock controller on Qualcomm Technologies, Inc - MSMfalcon devices. + SDM660 devices. Say Y if you want to support multimedia devices such as display, video encode/decode, camera, etc. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index a63065c97319..481cda67974b 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -25,12 +25,12 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o -obj-$(CONFIG_MSM_GCC_FALCON) += gcc-msmfalcon.o +obj-$(CONFIG_MSM_GCC_660) += gcc-sdm660.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o -obj-$(CONFIG_MSM_GPUCC_FALCON) += gpucc-msmfalcon.o -obj-$(CONFIG_MSM_MMCC_FALCON) += mmcc-msmfalcon.o +obj-$(CONFIG_MSM_GPUCC_660) += gpucc-sdm660.o +obj-$(CONFIG_MSM_MMCC_660) += mmcc-sdm660.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) += hfpll.o obj-$(CONFIG_KRAITCC) += krait-cc.o diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index d14c32bffe14..9332e99e642b 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -656,75 +656,75 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .num_clks = ARRAY_SIZE(msm8996_clks), }; -/* msmfalcon */ -DEFINE_CLK_SMD_RPM_BRANCH(msmfalcon, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, +/* sdm660 */ +DEFINE_CLK_SMD_RPM_BRANCH(sdm660, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM(msmfalcon, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_periph_clk, cnoc_periph_a_clk, +DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, mmssnoc_axi_clk, mmssnoc_axi_a_clk, +DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, aggre2_noc_clk, aggre2_noc_a_clk, +DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_QDSS(msmfalcon, qdss_clk, qdss_a_clk, +DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, rf_clk1, rf_clk1_ao, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, div_clk1, div_clk1_ao, 0xb); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk1, ln_bb_clk1_ao, 0x1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk2, ln_bb_clk2_ao, 0x2); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk3, ln_bb_clk3_ao, 0x3); - -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, rf_clk1_pin, rf_clk1_ao_pin, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk1_pin, +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_ao, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_ao, 0xb); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_ao, 0x1); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_ao, 0x2); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_ao, 0x3); + +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_ao_pin, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin, ln_bb_clk1_pin_ao, 0x1); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin, +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin, ln_bb_clk2_pin_ao, 0x2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin, +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_ao, 0x3); -static struct clk_hw *msmfalcon_clks[] = { - [RPM_XO_CLK_SRC] = &msmfalcon_cxo.hw, - [RPM_XO_A_CLK_SRC] = &msmfalcon_cxo_a.hw, - [RPM_SNOC_CLK] = &msmfalcon_snoc_clk.hw, - [RPM_SNOC_A_CLK] = &msmfalcon_snoc_a_clk.hw, - [RPM_BIMC_CLK] = &msmfalcon_bimc_clk.hw, - [RPM_BIMC_A_CLK] = &msmfalcon_bimc_a_clk.hw, - [RPM_QDSS_CLK] = &msmfalcon_qdss_clk.hw, - [RPM_QDSS_A_CLK] = &msmfalcon_qdss_a_clk.hw, - [RPM_RF_CLK1] = &msmfalcon_rf_clk1.hw, - [RPM_RF_CLK1_A] = &msmfalcon_rf_clk1_ao.hw, - [RPM_RF_CLK1_PIN] = &msmfalcon_rf_clk1_pin.hw, - [RPM_RF_CLK1_A_PIN] = &msmfalcon_rf_clk1_ao_pin.hw, - [RPM_AGGR2_NOC_CLK] = &msmfalcon_aggre2_noc_clk.hw, - [RPM_AGGR2_NOC_A_CLK] = &msmfalcon_aggre2_noc_a_clk.hw, - [RPM_CNOC_CLK] = &msmfalcon_cnoc_clk.hw, - [RPM_CNOC_A_CLK] = &msmfalcon_cnoc_a_clk.hw, - [RPM_IPA_CLK] = &msmfalcon_ipa_clk.hw, - [RPM_IPA_A_CLK] = &msmfalcon_ipa_a_clk.hw, - [RPM_CE1_CLK] = &msmfalcon_ce1_clk.hw, - [RPM_CE1_A_CLK] = &msmfalcon_ce1_a_clk.hw, - [RPM_DIV_CLK1] = &msmfalcon_div_clk1.hw, - [RPM_DIV_CLK1_AO] = &msmfalcon_div_clk1_ao.hw, - [RPM_LN_BB_CLK1] = &msmfalcon_ln_bb_clk1.hw, - [RPM_LN_BB_CLK1] = &msmfalcon_ln_bb_clk1_ao.hw, - [RPM_LN_BB_CLK1_PIN] = &msmfalcon_ln_bb_clk1_pin.hw, - [RPM_LN_BB_CLK1_PIN_AO] = &msmfalcon_ln_bb_clk1_pin_ao.hw, - [RPM_LN_BB_CLK2] = &msmfalcon_ln_bb_clk2.hw, - [RPM_LN_BB_CLK2_AO] = &msmfalcon_ln_bb_clk2_ao.hw, - [RPM_LN_BB_CLK2_PIN] = &msmfalcon_ln_bb_clk2_pin.hw, - [RPM_LN_BB_CLK2_PIN_AO] = &msmfalcon_ln_bb_clk2_pin_ao.hw, - [RPM_LN_BB_CLK3] = &msmfalcon_ln_bb_clk3.hw, - [RPM_LN_BB_CLK3_AO] = &msmfalcon_ln_bb_clk3_ao.hw, - [RPM_LN_BB_CLK3_PIN] = &msmfalcon_ln_bb_clk3_pin.hw, - [RPM_LN_BB_CLK3_PIN_AO] = &msmfalcon_ln_bb_clk3_pin_ao.hw, - [RPM_CNOC_PERIPH_CLK] = &msmfalcon_cnoc_periph_clk.hw, - [RPM_CNOC_PERIPH_A_CLK] = &msmfalcon_cnoc_periph_a_clk.hw, - [MMSSNOC_AXI_CLK] = &msmfalcon_mmssnoc_axi_clk.hw, - [MMSSNOC_AXI_A_CLK] = &msmfalcon_mmssnoc_axi_a_clk.hw, +static struct clk_hw *sdm660_clks[] = { + [RPM_XO_CLK_SRC] = &sdm660_cxo.hw, + [RPM_XO_A_CLK_SRC] = &sdm660_cxo_a.hw, + [RPM_SNOC_CLK] = &sdm660_snoc_clk.hw, + [RPM_SNOC_A_CLK] = &sdm660_snoc_a_clk.hw, + [RPM_BIMC_CLK] = &sdm660_bimc_clk.hw, + [RPM_BIMC_A_CLK] = &sdm660_bimc_a_clk.hw, + [RPM_QDSS_CLK] = &sdm660_qdss_clk.hw, + [RPM_QDSS_A_CLK] = &sdm660_qdss_a_clk.hw, + [RPM_RF_CLK1] = &sdm660_rf_clk1.hw, + [RPM_RF_CLK1_A] = &sdm660_rf_clk1_ao.hw, + [RPM_RF_CLK1_PIN] = &sdm660_rf_clk1_pin.hw, + [RPM_RF_CLK1_A_PIN] = &sdm660_rf_clk1_ao_pin.hw, + [RPM_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk.hw, + [RPM_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk.hw, + [RPM_CNOC_CLK] = &sdm660_cnoc_clk.hw, + [RPM_CNOC_A_CLK] = &sdm660_cnoc_a_clk.hw, + [RPM_IPA_CLK] = &sdm660_ipa_clk.hw, + [RPM_IPA_A_CLK] = &sdm660_ipa_a_clk.hw, + [RPM_CE1_CLK] = &sdm660_ce1_clk.hw, + [RPM_CE1_A_CLK] = &sdm660_ce1_a_clk.hw, + [RPM_DIV_CLK1] = &sdm660_div_clk1.hw, + [RPM_DIV_CLK1_AO] = &sdm660_div_clk1_ao.hw, + [RPM_LN_BB_CLK1] = &sdm660_ln_bb_clk1.hw, + [RPM_LN_BB_CLK1] = &sdm660_ln_bb_clk1_ao.hw, + [RPM_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin.hw, + [RPM_LN_BB_CLK1_PIN_AO] = &sdm660_ln_bb_clk1_pin_ao.hw, + [RPM_LN_BB_CLK2] = &sdm660_ln_bb_clk2.hw, + [RPM_LN_BB_CLK2_AO] = &sdm660_ln_bb_clk2_ao.hw, + [RPM_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin.hw, + [RPM_LN_BB_CLK2_PIN_AO] = &sdm660_ln_bb_clk2_pin_ao.hw, + [RPM_LN_BB_CLK3] = &sdm660_ln_bb_clk3.hw, + [RPM_LN_BB_CLK3_AO] = &sdm660_ln_bb_clk3_ao.hw, + [RPM_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin.hw, + [RPM_LN_BB_CLK3_PIN_AO] = &sdm660_ln_bb_clk3_pin_ao.hw, + [RPM_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk.hw, + [RPM_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk.hw, + [MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk.hw, + [MMSSNOC_AXI_A_CLK] = &sdm660_mmssnoc_axi_a_clk.hw, /* Voter Clocks */ [BIMC_MSMBUS_CLK] = &bimc_msmbus_clk.hw, @@ -746,16 +746,16 @@ static struct clk_hw *msmfalcon_clks[] = { [CNOC_PERIPH_KEEPALIVE_A_CLK] = &cnoc_periph_keepalive_a_clk.hw, }; -static const struct rpm_smd_clk_desc rpm_clk_msmfalcon = { - .clks = msmfalcon_clks, +static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { + .clks = sdm660_clks, .num_rpm_clks = RPM_CNOC_PERIPH_A_CLK, - .num_clks = ARRAY_SIZE(msmfalcon_clks), + .num_clks = ARRAY_SIZE(sdm660_clks), }; static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916}, { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996}, - { .compatible = "qcom,rpmcc-msmfalcon", .data = &rpm_clk_msmfalcon}, + { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660}, { } }; MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); @@ -766,21 +766,21 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) struct clk *clk; struct rpm_cc *rcc; struct clk_onecell_data *data; - int ret, is_8996 = 0, is_falcon = 0; + int ret, is_8996 = 0, is_660 = 0; size_t num_clks, i; struct clk_hw **hw_clks; const struct rpm_smd_clk_desc *desc; is_8996 = of_device_is_compatible(pdev->dev.of_node, "qcom,rpmcc-msm8996"); - is_falcon = of_device_is_compatible(pdev->dev.of_node, - "qcom,rpmcc-msmfalcon"); + is_660 = of_device_is_compatible(pdev->dev.of_node, + "qcom,rpmcc-sdm660"); if (is_8996) { ret = clk_vote_bimc(&msm8996_bimc_clk.hw, INT_MAX); if (ret < 0) return ret; - } else if (is_falcon) { - ret = clk_vote_bimc(&msmfalcon_bimc_clk.hw, INT_MAX); + } else if (is_660) { + ret = clk_vote_bimc(&sdm660_bimc_clk.hw, INT_MAX); if (ret < 0) return ret; } @@ -849,8 +849,8 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk); clk_prepare_enable(mmssnoc_a_clk_cpu_vote.hw.clk); - } else if (is_falcon) { - clk_prepare_enable(msmfalcon_cxo_a.hw.clk); + } else if (is_660) { + clk_prepare_enable(sdm660_cxo_a.hw.clk); /* Hold an active set vote for the cnoc_periph resource */ clk_set_rate(cnoc_periph_keepalive_a_clk.hw.clk, 19200000); diff --git a/drivers/clk/qcom/gcc-msmfalcon.c b/drivers/clk/qcom/gcc-msmfalcon.c deleted file mode 100644 index 1e1c871ef22c..000000000000 --- a/drivers/clk/qcom/gcc-msmfalcon.c +++ /dev/null @@ -1,3322 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "common.h" -#include "clk-pll.h" -#include "clk-regmap.h" -#include "clk-rcg.h" -#include "reset.h" -#include "vdd-level-falcon.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - -static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner); - -enum { - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_MAIN, - P_GPLL1_OUT_MAIN, - P_GPLL4_OUT_MAIN, - P_PLL0_EARLY_DIV_CLK_SRC, - P_PLL1_EARLY_DIV_CLK_SRC, - P_SLEEP_CLK, - P_XO, -}; - -static const struct parent_map gcc_parent_map_0[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_0[] = { - "xo", - "gpll0_out_main", - "gpll0_out_early_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_1[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_1[] = { - "xo", - "gpll0_out_main", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_2[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_SLEEP_CLK, 5 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_2[] = { - "xo", - "gpll0_out_main", - "core_pi_sleep_clk", - "gpll0_out_early_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_3[] = { - { P_XO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_3[] = { - "xo", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_4[] = { - { P_XO, 0 }, - { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_4[] = { - "xo", - "core_pi_sleep_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_5[] = { - { P_XO, 0 }, - { P_GPLL4_OUT_MAIN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_5[] = { - "xo", - "gpll4_out_main", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_6[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 3 }, - { P_GPLL1_OUT_MAIN, 4 }, - { P_GPLL4_OUT_MAIN, 5 }, - { P_PLL1_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_6[] = { - "xo", - "gpll0_out_main", - "gpll0_out_early_div", - "gpll1_out_main", - "gpll4_out_main", - "gpll1_out_early_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL4_OUT_MAIN, 5 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_7[] = { - "xo", - "gpll0_out_main", - "gpll4_out_main", - "gpll0_out_early_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_8[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 2 }, - { P_GPLL4_OUT_MAIN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_8[] = { - "xo", - "gpll0_out_main", - "gpll0_out_early_div", - "gpll4_out_main", - "core_bi_pll_test_se", -}; - -static struct clk_fixed_factor xo = { - .mult = 1, - .div = 1, - .hw.init = &(struct clk_init_data){ - .name = "xo", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static struct clk_alpha_pll gpll0_out_main = { - .offset = 0x0, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_fixed_factor gpll0_out_early_div = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "gpll0_out_early_div", - .parent_names = (const char *[]){ "gpll0_out_main" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static struct clk_alpha_pll gpll1_out_main = { - .offset = 0x1000, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gpll1_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_fixed_factor gpll1_out_early_div = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "gpll1_out_early_div", - .parent_names = (const char *[]){ "gpll1_out_main" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static struct clk_alpha_pll gpll4_out_main = { - .offset = 0x77000, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - { } -}; - -static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { - .cmd_rcgr = 0x19020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { - F(960000, P_XO, 10, 1, 2), - F(4800000, P_XO, 4, 0, 0), - F(9600000, P_XO, 2, 0, 0), - F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), - F(19200000, P_XO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - { } -}; - -static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { - .cmd_rcgr = 0x1900c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { - .cmd_rcgr = 0x1b020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { - .cmd_rcgr = 0x1b00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { - .cmd_rcgr = 0x1d020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { - .cmd_rcgr = 0x1d00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { - .cmd_rcgr = 0x1f020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { - .cmd_rcgr = 0x1f00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { - F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), - F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), - F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), - F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), - F(19200000, P_XO, 1, 0, 0), - F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), - F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), - F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), - F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), - F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), - F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), - F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), - F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), - { } -}; - -static struct clk_rcg2 blsp1_uart1_apps_clk_src = { - .cmd_rcgr = 0x1a00c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 31578947, - NOMINAL, 63157895), - }, -}; - -static struct clk_rcg2 blsp1_uart2_apps_clk_src = { - .cmd_rcgr = 0x1c00c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 31578947, - NOMINAL, 63157895), - }, -}; - -static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { - .cmd_rcgr = 0x26020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup1_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { - .cmd_rcgr = 0x2600c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup1_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { - .cmd_rcgr = 0x28020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup2_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { - .cmd_rcgr = 0x2800c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup2_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { - .cmd_rcgr = 0x2a020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup3_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { - .cmd_rcgr = 0x2a00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup3_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { - .cmd_rcgr = 0x2c020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup4_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { - .cmd_rcgr = 0x2c00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup4_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_uart1_apps_clk_src = { - .cmd_rcgr = 0x2700c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_uart1_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 31578947, - NOMINAL, 63157895), - }, -}; - -static struct clk_rcg2 blsp2_uart2_apps_clk_src = { - .cmd_rcgr = 0x2900c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_uart2_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 31578947, - NOMINAL, 63157895), - }, -}; - -static const struct freq_tbl ftbl_gp1_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 gp1_clk_src = { - .cmd_rcgr = 0x64004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gp1_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static struct clk_rcg2 gp2_clk_src = { - .cmd_rcgr = 0x65004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gp2_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static struct clk_rcg2 gp3_clk_src = { - .cmd_rcgr = 0x66004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gp3_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 hmss_ahb_clk_src = { - .cmd_rcgr = 0x48014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_hmss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "hmss_ahb_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3_AO( - LOWER, 19200000, - LOW, 50000000, - NOMINAL, 100000000), - }, -}; - -static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { - F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 hmss_gpll0_clk_src = { - .cmd_rcgr = 0x4805c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_hmss_gpll0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "hmss_gpll0_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1_AO( - LOWER, 600000000), - }, -}; - -static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = { - F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), - F(768000000, P_GPLL4_OUT_MAIN, 2, 0, 0), - F(1536000000, P_GPLL4_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 hmss_gpll4_clk_src = { - .cmd_rcgr = 0x48074, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_hmss_gpll4_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "hmss_gpll4_clk_src", - .parent_names = gcc_parent_names_5, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3_AO( - LOWER, 400000000, - LOW, 800000000, - NOMINAL, 1600000000), - }, -}; - -static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 hmss_rbcpr_clk_src = { - .cmd_rcgr = 0x48044, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_hmss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "hmss_rbcpr_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - NOMINAL, 50000000), - }, -}; - -static const struct freq_tbl ftbl_pdm2_clk_src[] = { - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 pdm2_clk_src = { - .cmd_rcgr = 0x33010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pdm2_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 60000000), - }, -}; - -static const struct freq_tbl ftbl_qspi_ser_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(80200000, P_PLL1_EARLY_DIV_CLK_SRC, 5, 0, 0), - F(160400000, P_GPLL1_OUT_MAIN, 5, 0, 0), - F(267333333, P_GPLL1_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 qspi_ser_clk_src = { - .cmd_rcgr = 0x4d00c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_6, - .freq_tbl = ftbl_qspi_ser_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "qspi_ser_clk_src", - .parent_names = gcc_parent_names_6, - .num_parents = 7, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 80200000, - LOW, 160400000, - NOMINAL, 267333333), - }, -}; - -static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { - F(144000, P_XO, 16, 3, 25), - F(400000, P_XO, 12, 1, 4), - F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), - F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), - F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), - F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 sdcc1_apps_clk_src = { - .cmd_rcgr = 0x1602c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_7, - .freq_tbl = ftbl_sdcc1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "sdcc1_apps_clk_src", - .parent_names = gcc_parent_names_7, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 400000000), - }, -}; - -static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = { - F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 sdcc1_ice_core_clk_src = { - .cmd_rcgr = 0x16010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_sdcc1_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "sdcc1_ice_core_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 75000000, - LOW, 150000000, - NOMINAL, 300000000), - }, -}; - -static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { - F(144000, P_XO, 16, 3, 25), - F(400000, P_XO, 12, 1, 4), - F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), - F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), - F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 sdcc2_apps_clk_src = { - .cmd_rcgr = 0x14010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_8, - .freq_tbl = ftbl_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "sdcc2_apps_clk_src", - .parent_names = gcc_parent_names_8, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { - F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 ufs_axi_clk_src = { - .cmd_rcgr = 0x75018, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_ufs_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ufs_axi_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 50000000, - LOW, 100000000, - LOW_L1, 150000000, - NOMINAL, 200000000, - HIGH, 240000000), - }, -}; - -static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = { - F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 ufs_ice_core_clk_src = { - .cmd_rcgr = 0x76010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_ufs_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ufs_ice_core_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 75000000, - LOW, 150000000, - NOMINAL, 300000000), - }, -}; - -static struct clk_rcg2 ufs_phy_aux_clk_src = { - .cmd_rcgr = 0x76044, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_hmss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ufs_phy_aux_clk_src", - .parent_names = gcc_parent_names_3, - .num_parents = 2, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { - F(37500000, P_PLL0_EARLY_DIV_CLK_SRC, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 ufs_unipro_core_clk_src = { - .cmd_rcgr = 0x76028, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_ufs_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ufs_unipro_core_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 37500000, - LOW, 75000000, - NOMINAL, 150000000), - }, -}; - -static const struct freq_tbl ftbl_usb20_master_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), - { } -}; - -static struct clk_rcg2 usb20_master_clk_src = { - .cmd_rcgr = 0x2f010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_usb20_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb20_master_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 60000000, - NOMINAL, 120000000), - }, -}; - -static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 usb20_mock_utmi_clk_src = { - .cmd_rcgr = 0x2f024, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_usb20_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb20_mock_utmi_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 60000000), - }, -}; - -static const struct freq_tbl ftbl_usb30_master_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(66666667, P_PLL0_EARLY_DIV_CLK_SRC, 4.5, 0, 0), - F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 usb30_master_clk_src = { - .cmd_rcgr = 0xf014, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_usb30_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb30_master_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP4( - LOWER, 66666667, - LOW, 133333333, - NOMINAL, 200000000, - HIGH, 240000000), - }, -}; - -static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { - F(40000000, P_PLL0_EARLY_DIV_CLK_SRC, 7.5, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 usb30_mock_utmi_clk_src = { - .cmd_rcgr = 0xf028, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_usb30_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb30_mock_utmi_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 40000000, - LOW, 60000000), - }, -}; - -static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { - F(1200000, P_XO, 16, 0, 0), - F(19200000, P_XO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 usb3_phy_aux_clk_src = { - .cmd_rcgr = 0x5000c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_usb3_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb3_phy_aux_clk_src", - .parent_names = gcc_parent_names_4, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static struct clk_branch gcc_aggre2_ufs_axi_clk = { - .halt_reg = 0x75034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x75034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre2_ufs_axi_clk", - .parent_names = (const char *[]){ - "ufs_axi_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre2_usb3_axi_clk = { - .halt_reg = 0xf03c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre2_usb3_axi_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_bimc_gfx_clk = { - .halt_reg = 0x7106c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7106c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_bimc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_bimc_hmss_axi_clk = { - .halt_reg = 0x48004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_bimc_hmss_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_bimc_mss_q6_axi_clk = { - .halt_reg = 0x4401c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4401c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_bimc_mss_q6_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_ahb_clk", - .flags = CLK_ENABLE_HAND_OFF, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { - .halt_reg = 0x19008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x19008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { - .halt_reg = 0x19004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x19004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { - .halt_reg = 0x1b008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1b008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { - .halt_reg = 0x1b004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1b004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { - .halt_reg = 0x1d008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { - .halt_reg = 0x1d004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { - .halt_reg = 0x1f008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1f008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { - .halt_reg = 0x1f004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1f004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_uart1_apps_clk = { - .halt_reg = 0x1a004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1a004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart1_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_uart2_apps_clk = { - .halt_reg = 0x1c004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1c004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart2_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_ahb_clk = { - .halt_reg = 0x25004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_ahb_clk", - .flags = CLK_ENABLE_HAND_OFF, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { - .halt_reg = 0x26008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x26008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup1_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { - .halt_reg = 0x26004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x26004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup1_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { - .halt_reg = 0x28008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x28008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup2_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { - .halt_reg = 0x28004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x28004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup2_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { - .halt_reg = 0x2a008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2a008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup3_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { - .halt_reg = 0x2a004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2a004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup3_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { - .halt_reg = 0x2c008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2c008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup4_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { - .halt_reg = 0x2c004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2c004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup4_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_uart1_apps_clk = { - .halt_reg = 0x27004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x27004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart1_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_uart2_apps_clk = { - .halt_reg = 0x29004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x29004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart2_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_boot_rom_ahb_clk = { - .halt_reg = 0x38004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_boot_rom_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb2_axi_clk = { - .halt_reg = 0x5058, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb2_axi_clk", - .parent_names = (const char *[]){ - "usb20_master_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { - .halt_reg = 0x5018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_axi_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_dcc_ahb_clk = { - .halt_reg = 0x84004, - .clkr = { - .enable_reg = 0x84004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_dcc_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp1_clk = { - .halt_reg = 0x64000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x64000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk", - .parent_names = (const char *[]){ - "gp1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp2_clk = { - .halt_reg = 0x65000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x65000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk", - .parent_names = (const char *[]){ - "gp2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp3_clk = { - .halt_reg = 0x66000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x66000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk", - .parent_names = (const char *[]){ - "gp3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_bimc_gfx_clk = { - .halt_reg = 0x71010, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x71010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_bimc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { - .halt_reg = 0x7100c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7100c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_bimc_gfx_src_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x71004, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x71004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_gate2 gpll0_out_msscc = { - .udelay = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_out_msscc", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_clk = { - .halt_reg = 0x5200c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_clk", - .parent_names = (const char *[]){ - "gpll0_out_main", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_div_clk = { - .halt_reg = 0x5200c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_div_clk", - .parent_names = (const char *[]){ - "gpll0_out_early_div", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { - .halt_reg = 0x71018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x71018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_hmss_ahb_clk = { - .halt_reg = 0x48000, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_hmss_ahb_clk", - .parent_names = (const char *[]){ - "hmss_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_hmss_dvm_bus_clk = { - .halt_reg = 0x4808c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4808c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_hmss_dvm_bus_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_hmss_rbcpr_clk = { - .halt_reg = 0x48008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_hmss_rbcpr_clk", - .parent_names = (const char *[]){ - "hmss_rbcpr_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mmss_gpll0_clk = { - .halt_reg = 0x5200c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mmss_gpll0_clk", - .parent_names = (const char *[]){ - "gpll0_out_main", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mmss_gpll0_div_clk = { - .halt_reg = 0x5200c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mmss_gpll0_div_clk", - .parent_names = (const char *[]){ - "gpll0_out_early_div", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { - .halt_reg = 0x9004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mmss_noc_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mmss_sys_noc_axi_clk = { - .halt_reg = 0x9000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mmss_sys_noc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_cfg_ahb_clk = { - .halt_reg = 0x8a000, - .clkr = { - .enable_reg = 0x8a000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mss_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { - .halt_reg = 0x8a004, - .clkr = { - .enable_reg = 0x8a004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mss_mnoc_bimc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_q6_bimc_axi_clk = { - .halt_reg = 0x8a040, - .clkr = { - .enable_reg = 0x8a040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mss_q6_bimc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_snoc_axi_clk = { - .halt_reg = 0x8a03c, - .clkr = { - .enable_reg = 0x8a03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mss_snoc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm2_clk = { - .halt_reg = 0x3300c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3300c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk", - .parent_names = (const char *[]){ - "pdm2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_ahb_clk = { - .halt_reg = 0x33004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_prng_ahb_clk = { - .halt_reg = 0x34004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_prng_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_ahb_clk = { - .halt_reg = 0x4d004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_ser_clk = { - .halt_reg = 0x4d008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_ser_clk", - .parent_names = (const char *[]){ - "qspi_ser_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_rx0_usb2_clkref_clk = { - .halt_reg = 0x88018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x88018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_rx0_usb2_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_rx1_usb2_clkref_clk = { - .halt_reg = 0x88014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x88014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_rx1_usb2_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_rx2_qlink_clkref_clk = { - .halt_reg = 0x88034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x88034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_rx2_qlink_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc1_ahb_clk = { - .halt_reg = 0x16008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc1_apps_clk = { - .halt_reg = 0x16004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]){ - "sdcc1_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc1_ice_core_clk = { - .halt_reg = 0x1600c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1600c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_ice_core_clk", - .parent_names = (const char *[]){ - "sdcc1_ice_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_ahb_clk = { - .halt_reg = 0x14008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_apps_clk = { - .halt_reg = 0x14004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]){ - "sdcc2_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_ahb_clk = { - .halt_reg = 0x7500c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7500c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_axi_clk = { - .halt_reg = 0x75008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x75008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_axi_clk", - .parent_names = (const char *[]){ - "ufs_axi_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_axi_hw_ctl_clk = { - .halt_reg = 0x75008, - .clkr = { - .enable_reg = 0x75008, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_axi_hw_ctl_clk", - .parent_names = (const char *[]){ - "gcc_ufs_axi_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_hw_ctl_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_clkref_clk = { - .halt_reg = 0x88008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x88008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_ice_core_clk = { - .halt_reg = 0x7600c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7600c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_ice_core_clk", - .parent_names = (const char *[]){ - "ufs_ice_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_ice_core_hw_ctl_clk = { - .halt_reg = 0x7600c, - .clkr = { - .enable_reg = 0x7600c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_ice_core_hw_ctl_clk", - .parent_names = (const char *[]){ - "gcc_ufs_ice_core_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_hw_ctl_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_aux_clk = { - .halt_reg = 0x76040, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x76040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_aux_clk", - .parent_names = (const char *[]){ - "ufs_phy_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_aux_hw_ctl_clk = { - .halt_reg = 0x76040, - .clkr = { - .enable_reg = 0x76040, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_aux_hw_ctl_clk", - .parent_names = (const char *[]){ - "gcc_ufs_phy_aux_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_hw_ctl_ops, - }, - }, -}; - -static struct clk_gate2 gcc_ufs_rx_symbol_0_clk = { - .udelay = 500, - .clkr = { - .enable_reg = 0x75014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_rx_symbol_0_clk", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_gate2 gcc_ufs_rx_symbol_1_clk = { - .udelay = 500, - .clkr = { - .enable_reg = 0x7605c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_rx_symbol_1_clk", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_gate2 gcc_ufs_tx_symbol_0_clk = { - .udelay = 500, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_tx_symbol_0_clk", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_unipro_core_clk = { - .halt_reg = 0x76008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x76008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_unipro_core_clk", - .parent_names = (const char *[]){ - "ufs_unipro_core_clk_src", - }, - .flags = CLK_SET_RATE_PARENT, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_unipro_core_hw_ctl_clk = { - .halt_reg = 0x76008, - .clkr = { - .enable_reg = 0x76008, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_unipro_core_hw_ctl_clk", - .parent_names = (const char *[]){ - "gcc_ufs_unipro_core_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_hw_ctl_ops, - }, - }, -}; - -static struct clk_branch gcc_usb20_master_clk = { - .halt_reg = 0x2f004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2f004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb20_master_clk", - .parent_names = (const char *[]){ - "usb20_master_clk_src", - }, - .flags = CLK_SET_RATE_PARENT, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb20_mock_utmi_clk = { - .halt_reg = 0x2f00c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2f00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb20_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb20_mock_utmi_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb20_sleep_clk = { - .halt_reg = 0x2f008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2f008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb20_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_master_clk = { - .halt_reg = 0xf008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_master_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_mock_utmi_clk = { - .halt_reg = 0xf010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb30_mock_utmi_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sleep_clk = { - .halt_reg = 0xf00c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_clkref_clk = { - .halt_reg = 0x8800c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8800c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_phy_aux_clk = { - .halt_reg = 0x50000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x50000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_phy_aux_clk", - .parent_names = (const char *[]){ - "usb3_phy_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_gate2 gcc_usb3_phy_pipe_clk = { - .udelay = 50, - .clkr = { - .enable_reg = 0x50004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_phy_pipe_clk", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { - .halt_reg = 0x6a004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6a004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb_phy_cfg_ahb2phy_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { - .halt_reg = 0x7d014, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7d014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "hlos1_vote_lpass_adsp_smmu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = { - .halt_reg = 0x7d048, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7d048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "hlos1_vote_turing_adsp_smmu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = { - .halt_reg = 0x7e048, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7e048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "hlos2_vote_turing_adsp_smmu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_fixed_factor gcc_ce1_ahb_m_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gcc_ce1_ahb_m_clk", - .ops = &clk_dummy_ops, - }, -}; - -static struct clk_fixed_factor gcc_ce1_axi_m_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gcc_ce1_axi_m_clk", - .ops = &clk_dummy_ops, - }, -}; - -struct clk_hw *gcc_msmfalcon_hws[] = { - [GCC_XO] = &xo.hw, - [GCC_GPLL0_EARLY_DIV] = &gpll0_out_early_div.hw, - [GCC_GPLL1_EARLY_DIV] = &gpll1_out_early_div.hw, - [GCC_CE1_AHB_M_CLK] = &gcc_ce1_ahb_m_clk.hw, - [GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw, -}; - -static struct clk_regmap *gcc_falcon_clocks[] = { - [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, - [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, - [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, - [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, - [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, - [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, - [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, - [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, - [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, - [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, - [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, - [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, - [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, - [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, - [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, - [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, - [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, - [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, - [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, - [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, - [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, - [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, - [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, - [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, - [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, - [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, - [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, - [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, - [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, - [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, - [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, - [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, - [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, - [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, - [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, - [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, - [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, - [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, - [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, - [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, - [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, - [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, - [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, - [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, - [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr, - [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, - [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr, - [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, - [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, - [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, - [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, - [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, - [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, - [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, - [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, - [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, - [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr, - [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, - [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, - [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr, - [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, - [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, - [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, - [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, - [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, - [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, - [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, - [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, - [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr, - [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr, - [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, - [GCC_RX2_QLINK_CLKREF_CLK] = &gcc_rx2_qlink_clkref_clk.clkr, - [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, - [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, - [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, - [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, - [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, - [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, - [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, - [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, - [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, - [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, - [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, - [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, - [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, - [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, - [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, - [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, - [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, - [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, - [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, - [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, - [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, - [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, - [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, - [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, - [GP1_CLK_SRC] = &gp1_clk_src.clkr, - [GP2_CLK_SRC] = &gp2_clk_src.clkr, - [GP3_CLK_SRC] = &gp3_clk_src.clkr, - [GPLL0] = &gpll0_out_main.clkr, - [GPLL1] = &gpll1_out_main.clkr, - [GPLL4] = &gpll4_out_main.clkr, - [HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr, - [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, - [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, - [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr, - [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, - [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, - [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr, - [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, - [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, - [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, - [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, - [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr, - [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr, - [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, - [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr, - [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr, - [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, - [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, - [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, - [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, - [GCC_UFS_AXI_HW_CTL_CLK] = &gcc_ufs_axi_hw_ctl_clk.clkr, - [GCC_UFS_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_unipro_core_hw_ctl_clk.clkr, - [HLOS1_VOTE_TURING_ADSP_SMMU_CLK] = - &hlos1_vote_turing_adsp_smmu_clk.clkr, - [HLOS2_VOTE_TURING_ADSP_SMMU_CLK] = - &hlos2_vote_turing_adsp_smmu_clk.clkr, -}; - -static const struct qcom_reset_map gcc_falcon_resets[] = { - [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, - [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, - [GCC_UFS_BCR] = { 0x75000 }, - [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, - [GCC_USB3_PHY_BCR] = { 0x50020 }, - [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, - [GCC_USB_20_BCR] = { 0x2f000 }, - [GCC_USB_30_BCR] = { 0xf000 }, - [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, -}; - -static const struct regmap_config gcc_falcon_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x94000, - .fast_io = true, -}; - -static const struct qcom_cc_desc gcc_falcon_desc = { - .config = &gcc_falcon_regmap_config, - .clks = gcc_falcon_clocks, - .num_clks = ARRAY_SIZE(gcc_falcon_clocks), - .hwclks = gcc_msmfalcon_hws, - .num_hwclks = ARRAY_SIZE(gcc_msmfalcon_hws), - .resets = gcc_falcon_resets, - .num_resets = ARRAY_SIZE(gcc_falcon_resets), -}; - -static const struct of_device_id gcc_falcon_match_table[] = { - { .compatible = "qcom,gcc-msmfalcon" }, - { } -}; -MODULE_DEVICE_TABLE(of, gcc_falcon_match_table); - -static int gcc_falcon_probe(struct platform_device *pdev) -{ - int ret = 0; - struct regmap *regmap; - - regmap = qcom_cc_map(pdev, &gcc_falcon_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* - * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be - * turned off by hardware during certain apps low power modes. - */ - regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); - - vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); - if (IS_ERR(vdd_dig.regulator[0])) { - if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_dig regulator\n"); - return PTR_ERR(vdd_dig.regulator[0]); - } - - vdd_dig_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_ao"); - if (IS_ERR(vdd_dig_ao.regulator[0])) { - if (!(PTR_ERR(vdd_dig_ao.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_dig_ao regulator\n"); - return PTR_ERR(vdd_dig_ao.regulator[0]); - } - - ret = qcom_cc_really_probe(pdev, &gcc_falcon_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register GCC clocks\n"); - return ret; - } - - /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ - regmap_update_bits(regmap, 0x0902c, 0x3, 0x3); - regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - - /* This clock is used for all MMSSCC register access */ - clk_prepare_enable(gcc_mmss_noc_cfg_ahb_clk.clkr.hw.clk); - - /* This clock is used for all GPUCC register access */ - clk_prepare_enable(gcc_gpu_cfg_ahb_clk.clkr.hw.clk); - - dev_info(&pdev->dev, "Registered GCC clocks\n"); - - return ret; -} - -static struct platform_driver gcc_falcon_driver = { - .probe = gcc_falcon_probe, - .driver = { - .name = "gcc-msmfalcon", - .of_match_table = gcc_falcon_match_table, - }, -}; - -static int __init gcc_falcon_init(void) -{ - return platform_driver_register(&gcc_falcon_driver); -} -core_initcall_sync(gcc_falcon_init); - -static void __exit gcc_falcon_exit(void) -{ - platform_driver_unregister(&gcc_falcon_driver); -} -module_exit(gcc_falcon_exit); - -/* Debug Mux for measure */ -static struct measure_clk_data debug_mux_priv = { - .xo_div4_cbcr = 0x43008, - .ctl_reg = 0x62004, - .status_reg = 0x62008, -}; - -static const char *const debug_mux_parent_names[] = { - "snoc_clk", - "cnoc_clk", - "cnoc_periph_clk", - "bimc_clk", - "ce1_clk", - "ipa_clk", - "gcc_aggre2_ufs_axi_clk", - "gcc_aggre2_usb3_axi_clk", - "gcc_bimc_gfx_clk", - "gcc_bimc_hmss_axi_clk", - "gcc_bimc_mss_q6_axi_clk", - "gcc_blsp1_ahb_clk", - "gcc_blsp1_qup1_i2c_apps_clk", - "gcc_blsp1_qup1_spi_apps_clk", - "gcc_blsp1_qup2_i2c_apps_clk", - "gcc_blsp1_qup2_spi_apps_clk", - "gcc_blsp1_qup3_i2c_apps_clk", - "gcc_blsp1_qup3_spi_apps_clk", - "gcc_blsp1_qup4_i2c_apps_clk", - "gcc_blsp1_qup4_spi_apps_clk", - "gcc_blsp1_uart1_apps_clk", - "gcc_blsp1_uart2_apps_clk", - "gcc_blsp2_ahb_clk", - "gcc_blsp2_qup1_i2c_apps_clk", - "gcc_blsp2_qup1_spi_apps_clk", - "gcc_blsp2_qup2_i2c_apps_clk", - "gcc_blsp2_qup2_spi_apps_clk", - "gcc_blsp2_qup3_i2c_apps_clk", - "gcc_blsp2_qup3_spi_apps_clk", - "gcc_blsp2_qup4_i2c_apps_clk", - "gcc_blsp2_qup4_spi_apps_clk", - "gcc_blsp2_uart1_apps_clk", - "gcc_blsp2_uart2_apps_clk", - "gcc_boot_rom_ahb_clk", - "gcc_ce1_ahb_m_clk", - "gcc_ce1_axi_m_clk", - "gcc_cfg_noc_usb2_axi_clk", - "gcc_cfg_noc_usb3_axi_clk", - "gcc_dcc_ahb_clk", - "gcc_gp1_clk", - "gcc_gp2_clk", - "gcc_gp3_clk", - "gcc_gpu_bimc_gfx_clk", - "gcc_gpu_bimc_gfx_src_clk", - "gcc_gpu_cfg_ahb_clk", - "gcc_gpu_snoc_dvm_gfx_clk", - "gcc_hmss_ahb_clk", - "gcc_hmss_dvm_bus_clk", - "gcc_hmss_rbcpr_clk", - "gcc_mmss_noc_cfg_ahb_clk", - "gcc_mmss_sys_noc_axi_clk", - "gcc_mss_cfg_ahb_clk", - "gcc_mss_mnoc_bimc_axi_clk", - "gcc_mss_q6_bimc_axi_clk", - "gcc_mss_snoc_axi_clk", - "gcc_pdm2_clk", - "gcc_pdm_ahb_clk", - "gcc_prng_ahb_clk", - "gcc_qspi_ahb_clk", - "gcc_qspi_ser_clk", - "gcc_sdcc1_ahb_clk", - "gcc_sdcc1_apps_clk", - "gcc_sdcc1_ice_core_clk", - "gcc_sdcc2_ahb_clk", - "gcc_sdcc2_apps_clk", - "gcc_ufs_ahb_clk", - "gcc_ufs_axi_clk", - "gcc_ufs_ice_core_clk", - "gcc_ufs_phy_aux_clk", - "gcc_ufs_unipro_core_clk", - "gcc_usb20_master_clk", - "gcc_usb20_mock_utmi_clk", - "gcc_usb20_sleep_clk", - "gcc_usb30_master_clk", - "gcc_usb30_mock_utmi_clk", - "gcc_usb30_sleep_clk", - "gcc_usb3_phy_aux_clk", - "gcc_usb_phy_cfg_ahb2phy_clk", - "gcc_ufs_rx_symbol_0_clk", - "gcc_ufs_rx_symbol_1_clk", - "gcc_ufs_tx_symbol_0_clk", - "gcc_usb3_phy_pipe_clk", - "mmssnoc_axi_clk", - "mmss_bimc_smmu_ahb_clk", - "mmss_bimc_smmu_axi_clk", - "mmss_camss_ahb_clk", - "mmss_camss_cci_ahb_clk", - "mmss_camss_cci_clk", - "mmss_camss_cphy_csid0_clk", - "mmss_camss_cphy_csid1_clk", - "mmss_camss_cphy_csid2_clk", - "mmss_camss_cphy_csid3_clk", - "mmss_camss_cpp_ahb_clk", - "mmss_camss_cpp_axi_clk", - "mmss_camss_cpp_clk", - "mmss_camss_cpp_vbif_ahb_clk", - "mmss_camss_csi0_ahb_clk", - "mmss_camss_csi0_clk", - "mmss_camss_csi0phytimer_clk", - "mmss_camss_csi0pix_clk", - "mmss_camss_csi0rdi_clk", - "mmss_camss_csi1_ahb_clk", - "mmss_camss_csi1_clk", - "mmss_camss_csi1phytimer_clk", - "mmss_camss_csi1pix_clk", - "mmss_camss_csi1rdi_clk", - "mmss_camss_csi2_ahb_clk", - "mmss_camss_csi2_clk", - "mmss_camss_csi2phytimer_clk", - "mmss_camss_csi2pix_clk", - "mmss_camss_csi2rdi_clk", - "mmss_camss_csi3_ahb_clk", - "mmss_camss_csi3_clk", - "mmss_camss_csi3pix_clk", - "mmss_camss_csi3rdi_clk", - "mmss_camss_csi_vfe0_clk", - "mmss_camss_csi_vfe1_clk", - "mmss_camss_csiphy0_clk", - "mmss_camss_csiphy1_clk", - "mmss_camss_csiphy2_clk", - "mmss_camss_gp0_clk", - "mmss_camss_gp1_clk", - "mmss_camss_ispif_ahb_clk", - "mmss_camss_jpeg0_clk", - "mmss_camss_jpeg_ahb_clk", - "mmss_camss_jpeg_axi_clk", - "mmss_camss_mclk0_clk", - "mmss_camss_mclk1_clk", - "mmss_camss_mclk2_clk", - "mmss_camss_mclk3_clk", - "mmss_camss_micro_ahb_clk", - "mmss_camss_top_ahb_clk", - "mmss_camss_vfe0_ahb_clk", - "mmss_camss_vfe0_clk", - "mmss_camss_vfe0_stream_clk", - "mmss_camss_vfe1_ahb_clk", - "mmss_camss_vfe1_clk", - "mmss_camss_vfe1_stream_clk", - "mmss_camss_vfe_vbif_ahb_clk", - "mmss_camss_vfe_vbif_axi_clk", - "mmss_csiphy_ahb2crif_clk", - "mmss_mdss_ahb_clk", - "mmss_mdss_axi_clk", - "mmss_mdss_byte0_clk", - "mmss_mdss_byte0_intf_clk", - "mmss_mdss_byte1_clk", - "mmss_mdss_byte1_intf_clk", - "mmss_mdss_dp_aux_clk", - "mmss_mdss_dp_crypto_clk", - "mmss_mdss_dp_gtc_clk", - "mmss_mdss_dp_link_clk", - "mmss_mdss_dp_link_intf_clk", - "mmss_mdss_dp_pixel_clk", - "mmss_mdss_esc0_clk", - "mmss_mdss_esc1_clk", - "mmss_mdss_hdmi_dp_ahb_clk", - "mmss_mdss_mdp_clk", - "mmss_mdss_pclk0_clk", - "mmss_mdss_pclk1_clk", - "mmss_mdss_rot_clk", - "mmss_mdss_vsync_clk", - "mmss_misc_ahb_clk", - "mmss_misc_cxo_clk", - "mmss_mnoc_ahb_clk", - "mmss_snoc_dvm_axi_clk", - "mmss_video_ahb_clk", - "mmss_video_axi_clk", - "mmss_video_core_clk", - "mmss_video_subcore0_clk", - "gpucc_gfx3d_clk", - "gpucc_rbbmtimer_clk", - "gpucc_rbcpr_clk", - "pwrcl_clk", - "perfcl_clk", -}; - -static struct clk_debug_mux gcc_debug_mux = { - .priv = &debug_mux_priv, - .en_mask = BIT(16), - .mask = 0x3FF, - MUX_SRC_LIST( - { "snoc_clk", 0x000 }, - { "cnoc_clk", 0x00E }, - { "cnoc_periph_clk", 0x198 }, - { "bimc_clk", 0x14E }, - { "ce1_clk", 0x097 }, - { "ipa_clk", 0x11b }, - { "gcc_aggre2_ufs_axi_clk", 0x10B }, - { "gcc_aggre2_usb3_axi_clk", 0x10A }, - { "gcc_bimc_gfx_clk", 0x0AC }, - { "gcc_bimc_hmss_axi_clk", 0x0BB }, - { "gcc_bimc_mss_q6_axi_clk", 0x0A3 }, - { "gcc_blsp1_ahb_clk", 0x04A }, - { "gcc_blsp1_qup1_i2c_apps_clk", 0x04D }, - { "gcc_blsp1_qup1_spi_apps_clk", 0x04C }, - { "gcc_blsp1_qup2_i2c_apps_clk", 0x051 }, - { "gcc_blsp1_qup2_spi_apps_clk", 0x050 }, - { "gcc_blsp1_qup3_i2c_apps_clk", 0x055 }, - { "gcc_blsp1_qup3_spi_apps_clk", 0x054 }, - { "gcc_blsp1_qup4_i2c_apps_clk", 0x059 }, - { "gcc_blsp1_qup4_spi_apps_clk", 0x058 }, - { "gcc_blsp1_uart1_apps_clk", 0x04E }, - { "gcc_blsp1_uart2_apps_clk", 0x052 }, - { "gcc_blsp2_ahb_clk", 0x05E }, - { "gcc_blsp2_qup1_i2c_apps_clk", 0x061 }, - { "gcc_blsp2_qup1_spi_apps_clk", 0x060 }, - { "gcc_blsp2_qup2_i2c_apps_clk", 0x065 }, - { "gcc_blsp2_qup2_spi_apps_clk", 0x064 }, - { "gcc_blsp2_qup3_i2c_apps_clk", 0x069 }, - { "gcc_blsp2_qup3_spi_apps_clk", 0x068 }, - { "gcc_blsp2_qup4_i2c_apps_clk", 0x06D }, - { "gcc_blsp2_qup4_spi_apps_clk", 0x06C }, - { "gcc_blsp2_uart1_apps_clk", 0x062 }, - { "gcc_blsp2_uart2_apps_clk", 0x066 }, - { "gcc_boot_rom_ahb_clk", 0x07A }, - { "gcc_ce1_ahb_m_clk", 0x099 }, - { "gcc_ce1_axi_m_clk", 0x098 }, - { "gcc_cfg_noc_usb2_axi_clk", 0x168 }, - { "gcc_cfg_noc_usb3_axi_clk", 0x014 }, - { "gcc_dcc_ahb_clk", 0x119 }, - { "gcc_gp1_clk", 0x0DF }, - { "gcc_gp2_clk", 0x0E0 }, - { "gcc_gp3_clk", 0x0E1 }, - { "gcc_gpu_bimc_gfx_clk", 0x13F }, - { "gcc_gpu_bimc_gfx_src_clk", 0x13E }, - { "gcc_gpu_cfg_ahb_clk", 0x13B }, - { "gcc_gpu_snoc_dvm_gfx_clk", 0x141 }, - { "gcc_hmss_ahb_clk", 0x0BA }, - { "gcc_hmss_dvm_bus_clk", 0x0BF }, - { "gcc_hmss_rbcpr_clk", 0x0BC }, - { "gcc_mmss_noc_cfg_ahb_clk", 0x020 }, - { "gcc_mmss_sys_noc_axi_clk", 0x01F }, - { "gcc_mss_cfg_ahb_clk", 0x11F }, - { "gcc_mss_mnoc_bimc_axi_clk", 0x120 }, - { "gcc_mss_q6_bimc_axi_clk", 0x124 }, - { "gcc_mss_snoc_axi_clk", 0x123 }, - { "gcc_pdm2_clk", 0x074 }, - { "gcc_pdm_ahb_clk", 0x072 }, - { "gcc_prng_ahb_clk", 0x075 }, - { "gcc_qspi_ahb_clk", 0x172 }, - { "gcc_qspi_ser_clk", 0x173 }, - { "gcc_sdcc1_ahb_clk", 0x16E }, - { "gcc_sdcc1_apps_clk", 0x16D }, - { "gcc_sdcc1_ice_core_clk", 0x16F }, - { "gcc_sdcc2_ahb_clk", 0x047 }, - { "gcc_sdcc2_apps_clk", 0x046 }, - { "gcc_ufs_ahb_clk", 0x0EB }, - { "gcc_ufs_axi_clk", 0x0EA }, - { "gcc_ufs_ice_core_clk", 0x0F1 }, - { "gcc_ufs_phy_aux_clk", 0x0F2 }, - { "gcc_ufs_unipro_core_clk", 0x0F0 }, - { "gcc_usb20_master_clk", 0x169 }, - { "gcc_usb20_mock_utmi_clk", 0x16B }, - { "gcc_usb20_sleep_clk", 0x16A }, - { "gcc_usb30_master_clk", 0x03C }, - { "gcc_usb30_mock_utmi_clk", 0x03E }, - { "gcc_usb30_sleep_clk", 0x03D }, - { "gcc_usb3_phy_aux_clk", 0x03F }, - { "gcc_usb_phy_cfg_ahb2phy_clk", 0x045 }, - { "gcc_ufs_rx_symbol_0_clk", 0x0ED }, - { "gcc_ufs_rx_symbol_1_clk", 0x162 }, - { "gcc_ufs_tx_symbol_0_clk", 0x0EC }, - { "gcc_usb3_phy_pipe_clk", 0x040 }, - { "mmssnoc_axi_clk", 0x22, MMCC, 0x004 }, - { "mmss_bimc_smmu_ahb_clk", 0x22, MMCC, 0x00C }, - { "mmss_bimc_smmu_axi_clk", 0x22, MMCC, 0x00D }, - { "mmss_camss_ahb_clk", 0x22, MMCC, 0x037 }, - { "mmss_camss_cci_ahb_clk", 0x22, MMCC, 0x02E }, - { "mmss_camss_cci_clk", 0x22, MMCC, 0x02D }, - { "mmss_camss_cphy_csid0_clk", 0x22, MMCC, 0x08D }, - { "mmss_camss_cphy_csid1_clk", 0x22, MMCC, 0x08E }, - { "mmss_camss_cphy_csid2_clk", 0x22, MMCC, 0x08F }, - { "mmss_camss_cphy_csid3_clk", 0x22, MMCC, 0x090 }, - { "mmss_camss_cpp_ahb_clk", 0x22, MMCC, 0x03B }, - { "mmss_camss_cpp_axi_clk", 0x22, MMCC, 0x07A }, - { "mmss_camss_cpp_clk", 0x22, MMCC, 0x03A }, - { "mmss_camss_cpp_vbif_ahb_clk", 0x22, MMCC, 0x073 }, - { "mmss_camss_csi0_ahb_clk", 0x22, MMCC, 0x042 }, - { "mmss_camss_csi0_clk", 0x22, MMCC, 0x041 }, - { "mmss_camss_csi0phytimer_clk", 0x22, MMCC, 0x02F }, - { "mmss_camss_csi0pix_clk", 0x22, MMCC, 0x045 }, - { "mmss_camss_csi0rdi_clk", 0x22, MMCC, 0x044 }, - { "mmss_camss_csi1_ahb_clk", 0x22, MMCC, 0x047 }, - { "mmss_camss_csi1_clk", 0x22, MMCC, 0x046 }, - { "mmss_camss_csi1phytimer_clk", 0x22, MMCC, 0x030 }, - { "mmss_camss_csi1pix_clk", 0x22, MMCC, 0x04A }, - { "mmss_camss_csi1rdi_clk", 0x22, MMCC, 0x049 }, - { "mmss_camss_csi2_ahb_clk", 0x22, MMCC, 0x04C }, - { "mmss_camss_csi2_clk", 0x22, MMCC, 0x04B }, - { "mmss_camss_csi2phytimer_clk", 0x22, MMCC, 0x031 }, - { "mmss_camss_csi2pix_clk", 0x22, MMCC, 0x04F }, - { "mmss_camss_csi2rdi_clk", 0x22, MMCC, 0x04E }, - { "mmss_camss_csi3_ahb_clk", 0x22, MMCC, 0x051 }, - { "mmss_camss_csi3_clk", 0x22, MMCC, 0x050 }, - { "mmss_camss_csi3pix_clk", 0x22, MMCC, 0x054 }, - { "mmss_camss_csi3rdi_clk", 0x22, MMCC, 0x053 }, - { "mmss_camss_csi_vfe0_clk", 0x22, MMCC, 0x03F }, - { "mmss_camss_csi_vfe1_clk", 0x22, MMCC, 0x040 }, - { "mmss_camss_csiphy0_clk", 0x22, MMCC, 0x043 }, - { "mmss_camss_csiphy1_clk", 0x22, MMCC, 0x085 }, - { "mmss_camss_csiphy2_clk", 0x22, MMCC, 0x088 }, - { "mmss_camss_gp0_clk", 0x22, MMCC, 0x027 }, - { "mmss_camss_gp1_clk", 0x22, MMCC, 0x028 }, - { "mmss_camss_ispif_ahb_clk", 0x22, MMCC, 0x033 }, - { "mmss_camss_jpeg0_clk", 0x22, MMCC, 0x032 }, - { "mmss_camss_jpeg_ahb_clk", 0x22, MMCC, 0x035 }, - { "mmss_camss_jpeg_axi_clk", 0x22, MMCC, 0x036 }, - { "mmss_camss_mclk0_clk", 0x22, MMCC, 0x029 }, - { "mmss_camss_mclk1_clk", 0x22, MMCC, 0x02A }, - { "mmss_camss_mclk2_clk", 0x22, MMCC, 0x02B }, - { "mmss_camss_mclk3_clk", 0x22, MMCC, 0x02C }, - { "mmss_camss_micro_ahb_clk", 0x22, MMCC, 0x026 }, - { "mmss_camss_top_ahb_clk", 0x22, MMCC, 0x025 }, - { "mmss_camss_vfe0_ahb_clk", 0x22, MMCC, 0x086 }, - { "mmss_camss_vfe0_clk", 0x22, MMCC, 0x038 }, - { "mmss_camss_vfe0_stream_clk", 0x22, MMCC, 0x071 }, - { "mmss_camss_vfe1_ahb_clk", 0x22, MMCC, 0x087 }, - { "mmss_camss_vfe1_clk", 0x22, MMCC, 0x039 }, - { "mmss_camss_vfe1_stream_clk", 0x22, MMCC, 0x072 }, - { "mmss_camss_vfe_vbif_ahb_clk", 0x22, MMCC, 0x03C }, - { "mmss_camss_vfe_vbif_axi_clk", 0x22, MMCC, 0x03D }, - { "mmss_csiphy_ahb2crif_clk", 0x22, MMCC, 0x0B8 }, - { "mmss_mdss_ahb_clk", 0x22, MMCC, 0x022 }, - { "mmss_mdss_axi_clk", 0x22, MMCC, 0x024 }, - { "mmss_mdss_byte0_clk", 0x22, MMCC, 0x01E }, - { "mmss_mdss_byte0_intf_clk", 0x22, MMCC, 0x0AD }, - { "mmss_mdss_byte1_clk", 0x22, MMCC, 0x01F }, - { "mmss_mdss_byte1_intf_clk", 0x22, MMCC, 0x0B6 }, - { "mmss_mdss_dp_aux_clk", 0x22, MMCC, 0x09C }, - { "mmss_mdss_dp_crypto_clk", 0x22, MMCC, 0x09A }, - { "mmss_mdss_dp_gtc_clk", 0x22, MMCC, 0x09D }, - { "mmss_mdss_dp_link_clk", 0x22, MMCC, 0x098 }, - { "mmss_mdss_dp_link_intf_clk", 0x22, MMCC, 0x099 }, - { "mmss_mdss_dp_pixel_clk", 0x22, MMCC, 0x09B }, - { "mmss_mdss_esc0_clk", 0x22, MMCC, 0x020 }, - { "mmss_mdss_esc1_clk", 0x22, MMCC, 0x021 }, - { "mmss_mdss_hdmi_dp_ahb_clk", 0x22, MMCC, 0x023 }, - { "mmss_mdss_mdp_clk", 0x22, MMCC, 0x014 }, - { "mmss_mdss_pclk0_clk", 0x22, MMCC, 0x016 }, - { "mmss_mdss_pclk1_clk", 0x22, MMCC, 0x017 }, - { "mmss_mdss_rot_clk", 0x22, MMCC, 0x012 }, - { "mmss_mdss_vsync_clk", 0x22, MMCC, 0x01C }, - { "mmss_misc_ahb_clk", 0x22, MMCC, 0x003 }, - { "mmss_misc_cxo_clk", 0x22, MMCC, 0x077 }, - { "mmss_mnoc_ahb_clk", 0x22, MMCC, 0x001 }, - { "mmss_snoc_dvm_axi_clk", 0x22, MMCC, 0x013 }, - { "mmss_video_ahb_clk", 0x22, MMCC, 0x011 }, - { "mmss_video_axi_clk", 0x22, MMCC, 0x00F }, - { "mmss_video_core_clk", 0x22, MMCC, 0x00E }, - { "mmss_video_subcore0_clk", 0x22, MMCC, 0x01A }, - { "gpucc_gfx3d_clk", 0x13d, GPU, 0x008 }, - { "gpucc_rbbmtimer_clk", 0x13d, GPU, 0x005 }, - { "gpucc_rbcpr_clk", 0x13d, GPU, 0x003 }, - { "pwrcl_clk", 0x0c0, CPU, 0x000, 0x3, 8, 0x0FF }, - { "perfcl_clk", 0x0c0, CPU, 0x100, 0x3, 8, 0x0FF }, - ), - .hw.init = &(struct clk_init_data){ - .name = "gcc_debug_mux", - .ops = &clk_debug_mux_ops, - .parent_names = debug_mux_parent_names, - .num_parents = ARRAY_SIZE(debug_mux_parent_names), - .flags = CLK_IS_MEASURE, - }, -}; - -static const struct of_device_id clk_debug_match_table[] = { - { .compatible = "qcom,gcc-debug-msmfalcon" }, - {} -}; - -static int clk_debug_falcon_probe(struct platform_device *pdev) -{ - struct resource *res; - struct clk *clk; - int ret = 0, count; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbg_offset"); - if (!res) { - dev_err(&pdev->dev, "Failed to get debug offset.\n"); - return -EINVAL; - } - gcc_debug_mux.debug_offset = res->start; - - clk = devm_clk_get(&pdev->dev, "xo_clk_src"); - if (IS_ERR(clk)) { - if (PTR_ERR(clk) != -EPROBE_DEFER) - dev_err(&pdev->dev, "Unable to get xo clock\n"); - return PTR_ERR(clk); - } - - debug_mux_priv.cxo = clk; - - ret = of_property_read_u32(pdev->dev.of_node, "qcom,cc-count", - &count); - if (ret < 0) { - dev_err(&pdev->dev, "Num of debug clock controller not specified\n"); - return ret; - } - - if (!count) { - dev_err(&pdev->dev, "Count of CC cannot be zero\n"); - return -EINVAL; - } - - gcc_debug_mux.num_parent_regmap = count; - - gcc_debug_mux.regmap = devm_kzalloc(&pdev->dev, - sizeof(struct regmap *) * count, GFP_KERNEL); - if (!gcc_debug_mux.regmap) - return -ENOMEM; - - if (of_get_property(pdev->dev.of_node, "qcom,gcc", NULL)) { - gcc_debug_mux.regmap[GCC] = - syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "qcom,gcc"); - if (IS_ERR(gcc_debug_mux.regmap[GCC])) - return PTR_ERR(gcc_debug_mux.regmap[GCC]); - } - - if (of_get_property(pdev->dev.of_node, "qcom,cpu", NULL)) { - gcc_debug_mux.regmap[CPU] = - syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "qcom,cpu"); - if (IS_ERR(gcc_debug_mux.regmap[CPU])) - return PTR_ERR(gcc_debug_mux.regmap[CPU]); - } - - if (of_get_property(pdev->dev.of_node, "qcom,mmss", NULL)) { - gcc_debug_mux.regmap[MMCC] = - syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "qcom,mmss"); - if (IS_ERR(gcc_debug_mux.regmap[MMCC])) - return PTR_ERR(gcc_debug_mux.regmap[MMCC]); - - /* Clear the DBG_CLK_DIV bits of the MMSS debug register */ - regmap_update_bits(gcc_debug_mux.regmap[MMCC], 0x0, - 0x60000, 0x0); - } - - if (of_get_property(pdev->dev.of_node, "qcom,gpu", NULL)) { - gcc_debug_mux.regmap[GPU] = - syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "qcom,gpu"); - if (IS_ERR(gcc_debug_mux.regmap[GPU])) - return PTR_ERR(gcc_debug_mux.regmap[GPU]); - - /* Clear the DBG_CLK_DIV bits of the GPU debug register */ - regmap_update_bits(gcc_debug_mux.regmap[GPU], 0x0, - 0x60000, 0x0); - } - - clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); - if (IS_ERR(clk)) { - dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); - return PTR_ERR(clk); - } - - dev_info(&pdev->dev, "Registered debug mux successfully\n"); - - return ret; -} - -static struct platform_driver clk_debug_driver = { - .probe = clk_debug_falcon_probe, - .driver = { - .name = "gcc-debug-msmfalcon", - .of_match_table = clk_debug_match_table, - .owner = THIS_MODULE, - }, -}; - -int __init clk_debug_falcon_init(void) -{ - return platform_driver_register(&clk_debug_driver); -} -fs_initcall(clk_debug_falcon_init); diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c new file mode 100644 index 000000000000..da4c6e8797d7 --- /dev/null +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -0,0 +1,3322 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "common.h" +#include "clk-pll.h" +#include "clk-regmap.h" +#include "clk-rcg.h" +#include "reset.h" +#include "vdd-level-660.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner); + +enum { + P_CORE_BI_PLL_TEST_SE, + P_GPLL0_OUT_MAIN, + P_GPLL1_OUT_MAIN, + P_GPLL4_OUT_MAIN, + P_PLL0_EARLY_DIV_CLK_SRC, + P_PLL1_EARLY_DIV_CLK_SRC, + P_SLEEP_CLK, + P_XO, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_0[] = { + "xo", + "gpll0_out_main", + "gpll0_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_1[] = { + "xo", + "gpll0_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_2[] = { + "xo", + "gpll0_out_main", + "core_pi_sleep_clk", + "gpll0_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_XO, 0 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_3[] = { + "xo", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_XO, 0 }, + { P_SLEEP_CLK, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_4[] = { + "xo", + "core_pi_sleep_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_XO, 0 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_5[] = { + "xo", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_6[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 3 }, + { P_GPLL1_OUT_MAIN, 4 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_PLL1_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_6[] = { + "xo", + "gpll0_out_main", + "gpll0_out_early_div", + "gpll1_out_main", + "gpll4_out_main", + "gpll1_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_7[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_7[] = { + "xo", + "gpll0_out_main", + "gpll4_out_main", + "gpll0_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_8[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 2 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_8[] = { + "xo", + "gpll0_out_main", + "gpll0_out_early_div", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static struct clk_fixed_factor xo = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "xo", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll0_out_main = { + .offset = 0x0, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_out_early_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_early_div", + .parent_names = (const char *[]){ "gpll0_out_main" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll1_out_main = { + .offset = 0x1000, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll1_out_early_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll1_out_early_div", + .parent_names = (const char *[]){ "gpll1_out_main" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll4_out_main = { + .offset = 0x77000, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x19020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x1900c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x1b020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x1b00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x1d020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x1d00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x1f020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x1f00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { + F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), + F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), + F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), + F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), + F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), + F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), + F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .cmd_rcgr = 0x1a00c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart1_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .cmd_rcgr = 0x1c00c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart2_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x26020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x2600c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x28020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x2800c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x2a020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x2a00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x2c020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x2c00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_uart1_apps_clk_src = { + .cmd_rcgr = 0x2700c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart1_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static struct clk_rcg2 blsp2_uart2_apps_clk_src = { + .cmd_rcgr = 0x2900c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart2_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static const struct freq_tbl ftbl_gp1_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gp1_clk_src = { + .cmd_rcgr = 0x64004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp1_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static struct clk_rcg2 gp2_clk_src = { + .cmd_rcgr = 0x65004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp2_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static struct clk_rcg2 gp3_clk_src = { + .cmd_rcgr = 0x66004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp3_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_ahb_clk_src = { + .cmd_rcgr = 0x48014, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_hmss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_ahb_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3_AO( + LOWER, 19200000, + LOW, 50000000, + NOMINAL, 100000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { + F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_gpll0_clk_src = { + .cmd_rcgr = 0x4805c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_hmss_gpll0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll0_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1_AO( + LOWER, 600000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = { + F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + F(768000000, P_GPLL4_OUT_MAIN, 2, 0, 0), + F(1536000000, P_GPLL4_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_gpll4_clk_src = { + .cmd_rcgr = 0x48074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_hmss_gpll4_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll4_clk_src", + .parent_names = gcc_parent_names_5, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3_AO( + LOWER, 400000000, + LOW, 800000000, + NOMINAL, 1600000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_rbcpr_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + NOMINAL, 50000000), + }, +}; + +static const struct freq_tbl ftbl_pdm2_clk_src[] = { + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 pdm2_clk_src = { + .cmd_rcgr = 0x33010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_pdm2_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pdm2_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_qspi_ser_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(80200000, P_PLL1_EARLY_DIV_CLK_SRC, 5, 0, 0), + F(160400000, P_GPLL1_OUT_MAIN, 5, 0, 0), + F(267333333, P_GPLL1_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 qspi_ser_clk_src = { + .cmd_rcgr = 0x4d00c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_qspi_ser_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qspi_ser_clk_src", + .parent_names = gcc_parent_names_6, + .num_parents = 7, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 80200000, + LOW, 160400000, + NOMINAL, 267333333), + }, +}; + +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), + F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), + F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), + F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_apps_clk_src = { + .cmd_rcgr = 0x1602c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_sdcc1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_apps_clk_src", + .parent_names = gcc_parent_names_7, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 400000000), + }, +}; + +static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = { + F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_ice_core_clk_src = { + .cmd_rcgr = 0x16010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_sdcc1_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 75000000, + LOW, 150000000, + NOMINAL, 300000000), + }, +}; + +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), + F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), + F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc2_apps_clk_src = { + .cmd_rcgr = 0x14010, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_sdcc2_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc2_apps_clk_src", + .parent_names = gcc_parent_names_8, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { + F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 ufs_axi_clk_src = { + .cmd_rcgr = 0x75018, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_ufs_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_axi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 50000000, + LOW, 100000000, + LOW_L1, 150000000, + NOMINAL, 200000000, + HIGH, 240000000), + }, +}; + +static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = { + F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 ufs_ice_core_clk_src = { + .cmd_rcgr = 0x76010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_ufs_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 75000000, + LOW, 150000000, + NOMINAL, 300000000), + }, +}; + +static struct clk_rcg2 ufs_phy_aux_clk_src = { + .cmd_rcgr = 0x76044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_phy_aux_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = 2, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { + F(37500000, P_PLL0_EARLY_DIV_CLK_SRC, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 ufs_unipro_core_clk_src = { + .cmd_rcgr = 0x76028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_ufs_unipro_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_unipro_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 37500000, + LOW, 75000000, + NOMINAL, 150000000), + }, +}; + +static const struct freq_tbl ftbl_usb20_master_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 usb20_master_clk_src = { + .cmd_rcgr = 0x2f010, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb20_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_master_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 60000000, + NOMINAL, 120000000), + }, +}; + +static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 usb20_mock_utmi_clk_src = { + .cmd_rcgr = 0x2f024, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb20_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_mock_utmi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_usb30_master_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(66666667, P_PLL0_EARLY_DIV_CLK_SRC, 4.5, 0, 0), + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 usb30_master_clk_src = { + .cmd_rcgr = 0xf014, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb30_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_master_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4( + LOWER, 66666667, + LOW, 133333333, + NOMINAL, 200000000, + HIGH, 240000000), + }, +}; + +static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { + F(40000000, P_PLL0_EARLY_DIV_CLK_SRC, 7.5, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 usb30_mock_utmi_clk_src = { + .cmd_rcgr = 0xf028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb30_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_mock_utmi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 40000000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { + F(1200000, P_XO, 16, 0, 0), + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 usb3_phy_aux_clk_src = { + .cmd_rcgr = 0x5000c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_usb3_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb3_phy_aux_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static struct clk_branch gcc_aggre2_ufs_axi_clk = { + .halt_reg = 0x75034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x75034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_ufs_axi_clk", + .parent_names = (const char *[]){ + "ufs_axi_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre2_usb3_axi_clk = { + .halt_reg = 0xf03c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_usb3_axi_clk", + .parent_names = (const char *[]){ + "usb30_master_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gfx_clk = { + .halt_reg = 0x7106c, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7106c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_hmss_axi_clk = { + .halt_reg = 0x48004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(22), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_hmss_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_mss_q6_axi_clk = { + .halt_reg = 0x4401c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4401c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_mss_q6_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x17004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(17), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", + .flags = CLK_ENABLE_HAND_OFF, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .halt_reg = 0x19008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x19008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup1_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .halt_reg = 0x19004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x19004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup1_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { + .halt_reg = 0x1b008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup2_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { + .halt_reg = 0x1b004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup2_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { + .halt_reg = 0x1d008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup3_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { + .halt_reg = 0x1d004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1d004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup3_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { + .halt_reg = 0x1f008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1f008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup4_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { + .halt_reg = 0x1f004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1f004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup4_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart1_apps_clk = { + .halt_reg = 0x1a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart1_apps_clk", + .parent_names = (const char *[]){ + "blsp1_uart1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart2_apps_clk = { + .halt_reg = 0x1c004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart2_apps_clk", + .parent_names = (const char *[]){ + "blsp1_uart2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_ahb_clk = { + .halt_reg = 0x25004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_ahb_clk", + .flags = CLK_ENABLE_HAND_OFF, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { + .halt_reg = 0x26008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x26008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup1_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { + .halt_reg = 0x26004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x26004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup1_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { + .halt_reg = 0x28008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x28008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup2_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { + .halt_reg = 0x28004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x28004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup2_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { + .halt_reg = 0x2a008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup3_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { + .halt_reg = 0x2a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup3_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { + .halt_reg = 0x2c008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup4_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { + .halt_reg = 0x2c004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup4_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart1_apps_clk = { + .halt_reg = 0x27004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x27004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart1_apps_clk", + .parent_names = (const char *[]){ + "blsp2_uart1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart2_apps_clk = { + .halt_reg = 0x29004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x29004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart2_apps_clk", + .parent_names = (const char *[]){ + "blsp2_uart2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb2_axi_clk = { + .halt_reg = 0x5058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb2_axi_clk", + .parent_names = (const char *[]){ + "usb20_master_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { + .halt_reg = 0x5018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_axi_clk", + .parent_names = (const char *[]){ + "usb30_master_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_dcc_ahb_clk = { + .halt_reg = 0x84004, + .clkr = { + .enable_reg = 0x84004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_dcc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x64000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x64000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_names = (const char *[]){ + "gp1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x65000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x65000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_names = (const char *[]){ + "gp2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x66000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x66000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_names = (const char *[]){ + "gp3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_bimc_gfx_clk = { + .halt_reg = 0x71010, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x71010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_bimc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { + .halt_reg = 0x7100c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7100c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_bimc_gfx_src_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_cfg_ahb_clk = { + .halt_reg = 0x71004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x71004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_gate2 gpll0_out_msscc = { + .udelay = 1, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_msscc", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk", + .parent_names = (const char *[]){ + "gpll0_out_main", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk", + .parent_names = (const char *[]){ + "gpll0_out_early_div", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { + .halt_reg = 0x71018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x71018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_snoc_dvm_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_hmss_ahb_clk = { + .halt_reg = 0x48000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(21), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_ahb_clk", + .parent_names = (const char *[]){ + "hmss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_hmss_dvm_bus_clk = { + .halt_reg = 0x4808c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4808c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_dvm_bus_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_hmss_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_rbcpr_clk", + .parent_names = (const char *[]){ + "hmss_rbcpr_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_gpll0_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_clk", + .parent_names = (const char *[]){ + "gpll0_out_main", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_gpll0_div_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_div_clk", + .parent_names = (const char *[]){ + "gpll0_out_early_div", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { + .halt_reg = 0x9004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_noc_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_sys_noc_axi_clk = { + .halt_reg = 0x9000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_sys_noc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_cfg_ahb_clk = { + .halt_reg = 0x8a000, + .clkr = { + .enable_reg = 0x8a000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { + .halt_reg = 0x8a004, + .clkr = { + .enable_reg = 0x8a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_mnoc_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .halt_reg = 0x8a040, + .clkr = { + .enable_reg = 0x8a040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_q6_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_snoc_axi_clk = { + .halt_reg = 0x8a03c, + .clkr = { + .enable_reg = 0x8a03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_snoc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x3300c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3300c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_names = (const char *[]){ + "pdm2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x33004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x34004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qspi_ahb_clk = { + .halt_reg = 0x4d004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qspi_ser_clk = { + .halt_reg = 0x4d008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ser_clk", + .parent_names = (const char *[]){ + "qspi_ser_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx0_usb2_clkref_clk = { + .halt_reg = 0x88018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx0_usb2_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx1_usb2_clkref_clk = { + .halt_reg = 0x88014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx1_usb2_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx2_qlink_clkref_clk = { + .halt_reg = 0x88034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx2_qlink_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x16008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x16008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x16004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x16004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_names = (const char *[]){ + "sdcc1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk = { + .halt_reg = 0x1600c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", + .parent_names = (const char *[]){ + "sdcc1_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x14008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x14004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", + .parent_names = (const char *[]){ + "sdcc2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_ahb_clk = { + .halt_reg = 0x7500c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7500c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_axi_clk = { + .halt_reg = 0x75008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x75008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_axi_clk", + .parent_names = (const char *[]){ + "ufs_axi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_axi_hw_ctl_clk = { + .halt_reg = 0x75008, + .clkr = { + .enable_reg = 0x75008, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_axi_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_axi_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_clkref_clk = { + .halt_reg = 0x88008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_ice_core_clk = { + .halt_reg = 0x7600c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ice_core_clk", + .parent_names = (const char *[]){ + "ufs_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_ice_core_hw_ctl_clk = { + .halt_reg = 0x7600c, + .clkr = { + .enable_reg = 0x7600c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ice_core_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_ice_core_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_aux_clk = { + .halt_reg = 0x76040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x76040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_aux_clk", + .parent_names = (const char *[]){ + "ufs_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_aux_hw_ctl_clk = { + .halt_reg = 0x76040, + .clkr = { + .enable_reg = 0x76040, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_aux_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_aux_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_gate2 gcc_ufs_rx_symbol_0_clk = { + .udelay = 500, + .clkr = { + .enable_reg = 0x75014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_rx_symbol_0_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_gate2 gcc_ufs_rx_symbol_1_clk = { + .udelay = 500, + .clkr = { + .enable_reg = 0x7605c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_rx_symbol_1_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_gate2 gcc_ufs_tx_symbol_0_clk = { + .udelay = 500, + .clkr = { + .enable_reg = 0x75010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_tx_symbol_0_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_unipro_core_clk = { + .halt_reg = 0x76008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x76008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_unipro_core_clk", + .parent_names = (const char *[]){ + "ufs_unipro_core_clk_src", + }, + .flags = CLK_SET_RATE_PARENT, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_unipro_core_hw_ctl_clk = { + .halt_reg = 0x76008, + .clkr = { + .enable_reg = 0x76008, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_unipro_core_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_unipro_core_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_master_clk = { + .halt_reg = 0x2f004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2f004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_master_clk", + .parent_names = (const char *[]){ + "usb20_master_clk_src", + }, + .flags = CLK_SET_RATE_PARENT, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_mock_utmi_clk = { + .halt_reg = 0x2f00c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2f00c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_mock_utmi_clk", + .parent_names = (const char *[]){ + "usb20_mock_utmi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_sleep_clk = { + .halt_reg = 0x2f008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2f008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_master_clk = { + .halt_reg = 0xf008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_master_clk", + .parent_names = (const char *[]){ + "usb30_master_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mock_utmi_clk = { + .halt_reg = 0xf010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_mock_utmi_clk", + .parent_names = (const char *[]){ + "usb30_mock_utmi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sleep_clk = { + .halt_reg = 0xf00c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf00c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_clkref_clk = { + .halt_reg = 0x8800c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8800c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_phy_aux_clk = { + .halt_reg = 0x50000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_aux_clk", + .parent_names = (const char *[]){ + "usb3_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_gate2 gcc_usb3_phy_pipe_clk = { + .udelay = 50, + .clkr = { + .enable_reg = 0x50004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_pipe_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .halt_reg = 0x6a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb_phy_cfg_ahb2phy_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { + .halt_reg = 0x7d014, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7d014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "hlos1_vote_lpass_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = { + .halt_reg = 0x7d048, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7d048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "hlos1_vote_turing_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = { + .halt_reg = 0x7e048, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7e048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "hlos2_vote_turing_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_fixed_factor gcc_ce1_ahb_m_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_ahb_m_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_fixed_factor gcc_ce1_axi_m_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_axi_m_clk", + .ops = &clk_dummy_ops, + }, +}; + +struct clk_hw *gcc_sdm660_hws[] = { + [GCC_XO] = &xo.hw, + [GCC_GPLL0_EARLY_DIV] = &gpll0_out_early_div.hw, + [GCC_GPLL1_EARLY_DIV] = &gpll1_out_early_div.hw, + [GCC_CE1_AHB_M_CLK] = &gcc_ce1_ahb_m_clk.hw, + [GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw, +}; + +static struct clk_regmap *gcc_660_clocks[] = { + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, + [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, + [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, + [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, + [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, + [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, + [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, + [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, + [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, + [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, + [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, + [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, + [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, + [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, + [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, + [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, + [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, + [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, + [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, + [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr, + [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, + [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, + [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, + [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, + [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, + [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, + [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr, + [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, + [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, + [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr, + [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, + [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, + [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, + [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, + [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr, + [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr, + [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, + [GCC_RX2_QLINK_CLKREF_CLK] = &gcc_rx2_qlink_clkref_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, + [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, + [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, + [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, + [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, + [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, + [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, + [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, + [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, + [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, + [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, + [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, + [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, + [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, + [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, + [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, + [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GP1_CLK_SRC] = &gp1_clk_src.clkr, + [GP2_CLK_SRC] = &gp2_clk_src.clkr, + [GP3_CLK_SRC] = &gp3_clk_src.clkr, + [GPLL0] = &gpll0_out_main.clkr, + [GPLL1] = &gpll1_out_main.clkr, + [GPLL4] = &gpll4_out_main.clkr, + [HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr, + [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, + [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, + [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr, + [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, + [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, + [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, + [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, + [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr, + [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr, + [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, + [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr, + [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr, + [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, + [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, + [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, + [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, + [GCC_UFS_AXI_HW_CTL_CLK] = &gcc_ufs_axi_hw_ctl_clk.clkr, + [GCC_UFS_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_ice_core_hw_ctl_clk.clkr, + [GCC_UFS_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_aux_hw_ctl_clk.clkr, + [GCC_UFS_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_unipro_core_hw_ctl_clk.clkr, + [HLOS1_VOTE_TURING_ADSP_SMMU_CLK] = + &hlos1_vote_turing_adsp_smmu_clk.clkr, + [HLOS2_VOTE_TURING_ADSP_SMMU_CLK] = + &hlos2_vote_turing_adsp_smmu_clk.clkr, +}; + +static const struct qcom_reset_map gcc_660_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_UFS_BCR] = { 0x75000 }, + [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, + [GCC_USB3_PHY_BCR] = { 0x50020 }, + [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, + [GCC_USB_20_BCR] = { 0x2f000 }, + [GCC_USB_30_BCR] = { 0xf000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const struct regmap_config gcc_660_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x94000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_660_desc = { + .config = &gcc_660_regmap_config, + .clks = gcc_660_clocks, + .num_clks = ARRAY_SIZE(gcc_660_clocks), + .hwclks = gcc_sdm660_hws, + .num_hwclks = ARRAY_SIZE(gcc_sdm660_hws), + .resets = gcc_660_resets, + .num_resets = ARRAY_SIZE(gcc_660_resets), +}; + +static const struct of_device_id gcc_660_match_table[] = { + { .compatible = "qcom,gcc-sdm660" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_660_match_table); + +static int gcc_660_probe(struct platform_device *pdev) +{ + int ret = 0; + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_660_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* + * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be + * turned off by hardware during certain apps low power modes. + */ + regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); + + vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); + if (IS_ERR(vdd_dig.regulator[0])) { + if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig regulator\n"); + return PTR_ERR(vdd_dig.regulator[0]); + } + + vdd_dig_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_ao"); + if (IS_ERR(vdd_dig_ao.regulator[0])) { + if (!(PTR_ERR(vdd_dig_ao.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig_ao regulator\n"); + return PTR_ERR(vdd_dig_ao.regulator[0]); + } + + ret = qcom_cc_really_probe(pdev, &gcc_660_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GCC clocks\n"); + return ret; + } + + /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ + regmap_update_bits(regmap, 0x0902c, 0x3, 0x3); + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); + + /* This clock is used for all MMSSCC register access */ + clk_prepare_enable(gcc_mmss_noc_cfg_ahb_clk.clkr.hw.clk); + + /* This clock is used for all GPUCC register access */ + clk_prepare_enable(gcc_gpu_cfg_ahb_clk.clkr.hw.clk); + + dev_info(&pdev->dev, "Registered GCC clocks\n"); + + return ret; +} + +static struct platform_driver gcc_660_driver = { + .probe = gcc_660_probe, + .driver = { + .name = "gcc-sdm660", + .of_match_table = gcc_660_match_table, + }, +}; + +static int __init gcc_660_init(void) +{ + return platform_driver_register(&gcc_660_driver); +} +core_initcall_sync(gcc_660_init); + +static void __exit gcc_660_exit(void) +{ + platform_driver_unregister(&gcc_660_driver); +} +module_exit(gcc_660_exit); + +/* Debug Mux for measure */ +static struct measure_clk_data debug_mux_priv = { + .xo_div4_cbcr = 0x43008, + .ctl_reg = 0x62004, + .status_reg = 0x62008, +}; + +static const char *const debug_mux_parent_names[] = { + "snoc_clk", + "cnoc_clk", + "cnoc_periph_clk", + "bimc_clk", + "ce1_clk", + "ipa_clk", + "gcc_aggre2_ufs_axi_clk", + "gcc_aggre2_usb3_axi_clk", + "gcc_bimc_gfx_clk", + "gcc_bimc_hmss_axi_clk", + "gcc_bimc_mss_q6_axi_clk", + "gcc_blsp1_ahb_clk", + "gcc_blsp1_qup1_i2c_apps_clk", + "gcc_blsp1_qup1_spi_apps_clk", + "gcc_blsp1_qup2_i2c_apps_clk", + "gcc_blsp1_qup2_spi_apps_clk", + "gcc_blsp1_qup3_i2c_apps_clk", + "gcc_blsp1_qup3_spi_apps_clk", + "gcc_blsp1_qup4_i2c_apps_clk", + "gcc_blsp1_qup4_spi_apps_clk", + "gcc_blsp1_uart1_apps_clk", + "gcc_blsp1_uart2_apps_clk", + "gcc_blsp2_ahb_clk", + "gcc_blsp2_qup1_i2c_apps_clk", + "gcc_blsp2_qup1_spi_apps_clk", + "gcc_blsp2_qup2_i2c_apps_clk", + "gcc_blsp2_qup2_spi_apps_clk", + "gcc_blsp2_qup3_i2c_apps_clk", + "gcc_blsp2_qup3_spi_apps_clk", + "gcc_blsp2_qup4_i2c_apps_clk", + "gcc_blsp2_qup4_spi_apps_clk", + "gcc_blsp2_uart1_apps_clk", + "gcc_blsp2_uart2_apps_clk", + "gcc_boot_rom_ahb_clk", + "gcc_ce1_ahb_m_clk", + "gcc_ce1_axi_m_clk", + "gcc_cfg_noc_usb2_axi_clk", + "gcc_cfg_noc_usb3_axi_clk", + "gcc_dcc_ahb_clk", + "gcc_gp1_clk", + "gcc_gp2_clk", + "gcc_gp3_clk", + "gcc_gpu_bimc_gfx_clk", + "gcc_gpu_bimc_gfx_src_clk", + "gcc_gpu_cfg_ahb_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gcc_hmss_ahb_clk", + "gcc_hmss_dvm_bus_clk", + "gcc_hmss_rbcpr_clk", + "gcc_mmss_noc_cfg_ahb_clk", + "gcc_mmss_sys_noc_axi_clk", + "gcc_mss_cfg_ahb_clk", + "gcc_mss_mnoc_bimc_axi_clk", + "gcc_mss_q6_bimc_axi_clk", + "gcc_mss_snoc_axi_clk", + "gcc_pdm2_clk", + "gcc_pdm_ahb_clk", + "gcc_prng_ahb_clk", + "gcc_qspi_ahb_clk", + "gcc_qspi_ser_clk", + "gcc_sdcc1_ahb_clk", + "gcc_sdcc1_apps_clk", + "gcc_sdcc1_ice_core_clk", + "gcc_sdcc2_ahb_clk", + "gcc_sdcc2_apps_clk", + "gcc_ufs_ahb_clk", + "gcc_ufs_axi_clk", + "gcc_ufs_ice_core_clk", + "gcc_ufs_phy_aux_clk", + "gcc_ufs_unipro_core_clk", + "gcc_usb20_master_clk", + "gcc_usb20_mock_utmi_clk", + "gcc_usb20_sleep_clk", + "gcc_usb30_master_clk", + "gcc_usb30_mock_utmi_clk", + "gcc_usb30_sleep_clk", + "gcc_usb3_phy_aux_clk", + "gcc_usb_phy_cfg_ahb2phy_clk", + "gcc_ufs_rx_symbol_0_clk", + "gcc_ufs_rx_symbol_1_clk", + "gcc_ufs_tx_symbol_0_clk", + "gcc_usb3_phy_pipe_clk", + "mmssnoc_axi_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_cci_ahb_clk", + "mmss_camss_cci_clk", + "mmss_camss_cphy_csid0_clk", + "mmss_camss_cphy_csid1_clk", + "mmss_camss_cphy_csid2_clk", + "mmss_camss_cphy_csid3_clk", + "mmss_camss_cpp_ahb_clk", + "mmss_camss_cpp_axi_clk", + "mmss_camss_cpp_clk", + "mmss_camss_cpp_vbif_ahb_clk", + "mmss_camss_csi0_ahb_clk", + "mmss_camss_csi0_clk", + "mmss_camss_csi0phytimer_clk", + "mmss_camss_csi0pix_clk", + "mmss_camss_csi0rdi_clk", + "mmss_camss_csi1_ahb_clk", + "mmss_camss_csi1_clk", + "mmss_camss_csi1phytimer_clk", + "mmss_camss_csi1pix_clk", + "mmss_camss_csi1rdi_clk", + "mmss_camss_csi2_ahb_clk", + "mmss_camss_csi2_clk", + "mmss_camss_csi2phytimer_clk", + "mmss_camss_csi2pix_clk", + "mmss_camss_csi2rdi_clk", + "mmss_camss_csi3_ahb_clk", + "mmss_camss_csi3_clk", + "mmss_camss_csi3pix_clk", + "mmss_camss_csi3rdi_clk", + "mmss_camss_csi_vfe0_clk", + "mmss_camss_csi_vfe1_clk", + "mmss_camss_csiphy0_clk", + "mmss_camss_csiphy1_clk", + "mmss_camss_csiphy2_clk", + "mmss_camss_gp0_clk", + "mmss_camss_gp1_clk", + "mmss_camss_ispif_ahb_clk", + "mmss_camss_jpeg0_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk", + "mmss_camss_mclk0_clk", + "mmss_camss_mclk1_clk", + "mmss_camss_mclk2_clk", + "mmss_camss_mclk3_clk", + "mmss_camss_micro_ahb_clk", + "mmss_camss_top_ahb_clk", + "mmss_camss_vfe0_ahb_clk", + "mmss_camss_vfe0_clk", + "mmss_camss_vfe0_stream_clk", + "mmss_camss_vfe1_ahb_clk", + "mmss_camss_vfe1_clk", + "mmss_camss_vfe1_stream_clk", + "mmss_camss_vfe_vbif_ahb_clk", + "mmss_camss_vfe_vbif_axi_clk", + "mmss_csiphy_ahb2crif_clk", + "mmss_mdss_ahb_clk", + "mmss_mdss_axi_clk", + "mmss_mdss_byte0_clk", + "mmss_mdss_byte0_intf_clk", + "mmss_mdss_byte1_clk", + "mmss_mdss_byte1_intf_clk", + "mmss_mdss_dp_aux_clk", + "mmss_mdss_dp_crypto_clk", + "mmss_mdss_dp_gtc_clk", + "mmss_mdss_dp_link_clk", + "mmss_mdss_dp_link_intf_clk", + "mmss_mdss_dp_pixel_clk", + "mmss_mdss_esc0_clk", + "mmss_mdss_esc1_clk", + "mmss_mdss_hdmi_dp_ahb_clk", + "mmss_mdss_mdp_clk", + "mmss_mdss_pclk0_clk", + "mmss_mdss_pclk1_clk", + "mmss_mdss_rot_clk", + "mmss_mdss_vsync_clk", + "mmss_misc_ahb_clk", + "mmss_misc_cxo_clk", + "mmss_mnoc_ahb_clk", + "mmss_snoc_dvm_axi_clk", + "mmss_video_ahb_clk", + "mmss_video_axi_clk", + "mmss_video_core_clk", + "mmss_video_subcore0_clk", + "gpucc_gfx3d_clk", + "gpucc_rbbmtimer_clk", + "gpucc_rbcpr_clk", + "pwrcl_clk", + "perfcl_clk", +}; + +static struct clk_debug_mux gcc_debug_mux = { + .priv = &debug_mux_priv, + .en_mask = BIT(16), + .mask = 0x3FF, + MUX_SRC_LIST( + { "snoc_clk", 0x000 }, + { "cnoc_clk", 0x00E }, + { "cnoc_periph_clk", 0x198 }, + { "bimc_clk", 0x14E }, + { "ce1_clk", 0x097 }, + { "ipa_clk", 0x11b }, + { "gcc_aggre2_ufs_axi_clk", 0x10B }, + { "gcc_aggre2_usb3_axi_clk", 0x10A }, + { "gcc_bimc_gfx_clk", 0x0AC }, + { "gcc_bimc_hmss_axi_clk", 0x0BB }, + { "gcc_bimc_mss_q6_axi_clk", 0x0A3 }, + { "gcc_blsp1_ahb_clk", 0x04A }, + { "gcc_blsp1_qup1_i2c_apps_clk", 0x04D }, + { "gcc_blsp1_qup1_spi_apps_clk", 0x04C }, + { "gcc_blsp1_qup2_i2c_apps_clk", 0x051 }, + { "gcc_blsp1_qup2_spi_apps_clk", 0x050 }, + { "gcc_blsp1_qup3_i2c_apps_clk", 0x055 }, + { "gcc_blsp1_qup3_spi_apps_clk", 0x054 }, + { "gcc_blsp1_qup4_i2c_apps_clk", 0x059 }, + { "gcc_blsp1_qup4_spi_apps_clk", 0x058 }, + { "gcc_blsp1_uart1_apps_clk", 0x04E }, + { "gcc_blsp1_uart2_apps_clk", 0x052 }, + { "gcc_blsp2_ahb_clk", 0x05E }, + { "gcc_blsp2_qup1_i2c_apps_clk", 0x061 }, + { "gcc_blsp2_qup1_spi_apps_clk", 0x060 }, + { "gcc_blsp2_qup2_i2c_apps_clk", 0x065 }, + { "gcc_blsp2_qup2_spi_apps_clk", 0x064 }, + { "gcc_blsp2_qup3_i2c_apps_clk", 0x069 }, + { "gcc_blsp2_qup3_spi_apps_clk", 0x068 }, + { "gcc_blsp2_qup4_i2c_apps_clk", 0x06D }, + { "gcc_blsp2_qup4_spi_apps_clk", 0x06C }, + { "gcc_blsp2_uart1_apps_clk", 0x062 }, + { "gcc_blsp2_uart2_apps_clk", 0x066 }, + { "gcc_boot_rom_ahb_clk", 0x07A }, + { "gcc_ce1_ahb_m_clk", 0x099 }, + { "gcc_ce1_axi_m_clk", 0x098 }, + { "gcc_cfg_noc_usb2_axi_clk", 0x168 }, + { "gcc_cfg_noc_usb3_axi_clk", 0x014 }, + { "gcc_dcc_ahb_clk", 0x119 }, + { "gcc_gp1_clk", 0x0DF }, + { "gcc_gp2_clk", 0x0E0 }, + { "gcc_gp3_clk", 0x0E1 }, + { "gcc_gpu_bimc_gfx_clk", 0x13F }, + { "gcc_gpu_bimc_gfx_src_clk", 0x13E }, + { "gcc_gpu_cfg_ahb_clk", 0x13B }, + { "gcc_gpu_snoc_dvm_gfx_clk", 0x141 }, + { "gcc_hmss_ahb_clk", 0x0BA }, + { "gcc_hmss_dvm_bus_clk", 0x0BF }, + { "gcc_hmss_rbcpr_clk", 0x0BC }, + { "gcc_mmss_noc_cfg_ahb_clk", 0x020 }, + { "gcc_mmss_sys_noc_axi_clk", 0x01F }, + { "gcc_mss_cfg_ahb_clk", 0x11F }, + { "gcc_mss_mnoc_bimc_axi_clk", 0x120 }, + { "gcc_mss_q6_bimc_axi_clk", 0x124 }, + { "gcc_mss_snoc_axi_clk", 0x123 }, + { "gcc_pdm2_clk", 0x074 }, + { "gcc_pdm_ahb_clk", 0x072 }, + { "gcc_prng_ahb_clk", 0x075 }, + { "gcc_qspi_ahb_clk", 0x172 }, + { "gcc_qspi_ser_clk", 0x173 }, + { "gcc_sdcc1_ahb_clk", 0x16E }, + { "gcc_sdcc1_apps_clk", 0x16D }, + { "gcc_sdcc1_ice_core_clk", 0x16F }, + { "gcc_sdcc2_ahb_clk", 0x047 }, + { "gcc_sdcc2_apps_clk", 0x046 }, + { "gcc_ufs_ahb_clk", 0x0EB }, + { "gcc_ufs_axi_clk", 0x0EA }, + { "gcc_ufs_ice_core_clk", 0x0F1 }, + { "gcc_ufs_phy_aux_clk", 0x0F2 }, + { "gcc_ufs_unipro_core_clk", 0x0F0 }, + { "gcc_usb20_master_clk", 0x169 }, + { "gcc_usb20_mock_utmi_clk", 0x16B }, + { "gcc_usb20_sleep_clk", 0x16A }, + { "gcc_usb30_master_clk", 0x03C }, + { "gcc_usb30_mock_utmi_clk", 0x03E }, + { "gcc_usb30_sleep_clk", 0x03D }, + { "gcc_usb3_phy_aux_clk", 0x03F }, + { "gcc_usb_phy_cfg_ahb2phy_clk", 0x045 }, + { "gcc_ufs_rx_symbol_0_clk", 0x0ED }, + { "gcc_ufs_rx_symbol_1_clk", 0x162 }, + { "gcc_ufs_tx_symbol_0_clk", 0x0EC }, + { "gcc_usb3_phy_pipe_clk", 0x040 }, + { "mmssnoc_axi_clk", 0x22, MMCC, 0x004 }, + { "mmss_bimc_smmu_ahb_clk", 0x22, MMCC, 0x00C }, + { "mmss_bimc_smmu_axi_clk", 0x22, MMCC, 0x00D }, + { "mmss_camss_ahb_clk", 0x22, MMCC, 0x037 }, + { "mmss_camss_cci_ahb_clk", 0x22, MMCC, 0x02E }, + { "mmss_camss_cci_clk", 0x22, MMCC, 0x02D }, + { "mmss_camss_cphy_csid0_clk", 0x22, MMCC, 0x08D }, + { "mmss_camss_cphy_csid1_clk", 0x22, MMCC, 0x08E }, + { "mmss_camss_cphy_csid2_clk", 0x22, MMCC, 0x08F }, + { "mmss_camss_cphy_csid3_clk", 0x22, MMCC, 0x090 }, + { "mmss_camss_cpp_ahb_clk", 0x22, MMCC, 0x03B }, + { "mmss_camss_cpp_axi_clk", 0x22, MMCC, 0x07A }, + { "mmss_camss_cpp_clk", 0x22, MMCC, 0x03A }, + { "mmss_camss_cpp_vbif_ahb_clk", 0x22, MMCC, 0x073 }, + { "mmss_camss_csi0_ahb_clk", 0x22, MMCC, 0x042 }, + { "mmss_camss_csi0_clk", 0x22, MMCC, 0x041 }, + { "mmss_camss_csi0phytimer_clk", 0x22, MMCC, 0x02F }, + { "mmss_camss_csi0pix_clk", 0x22, MMCC, 0x045 }, + { "mmss_camss_csi0rdi_clk", 0x22, MMCC, 0x044 }, + { "mmss_camss_csi1_ahb_clk", 0x22, MMCC, 0x047 }, + { "mmss_camss_csi1_clk", 0x22, MMCC, 0x046 }, + { "mmss_camss_csi1phytimer_clk", 0x22, MMCC, 0x030 }, + { "mmss_camss_csi1pix_clk", 0x22, MMCC, 0x04A }, + { "mmss_camss_csi1rdi_clk", 0x22, MMCC, 0x049 }, + { "mmss_camss_csi2_ahb_clk", 0x22, MMCC, 0x04C }, + { "mmss_camss_csi2_clk", 0x22, MMCC, 0x04B }, + { "mmss_camss_csi2phytimer_clk", 0x22, MMCC, 0x031 }, + { "mmss_camss_csi2pix_clk", 0x22, MMCC, 0x04F }, + { "mmss_camss_csi2rdi_clk", 0x22, MMCC, 0x04E }, + { "mmss_camss_csi3_ahb_clk", 0x22, MMCC, 0x051 }, + { "mmss_camss_csi3_clk", 0x22, MMCC, 0x050 }, + { "mmss_camss_csi3pix_clk", 0x22, MMCC, 0x054 }, + { "mmss_camss_csi3rdi_clk", 0x22, MMCC, 0x053 }, + { "mmss_camss_csi_vfe0_clk", 0x22, MMCC, 0x03F }, + { "mmss_camss_csi_vfe1_clk", 0x22, MMCC, 0x040 }, + { "mmss_camss_csiphy0_clk", 0x22, MMCC, 0x043 }, + { "mmss_camss_csiphy1_clk", 0x22, MMCC, 0x085 }, + { "mmss_camss_csiphy2_clk", 0x22, MMCC, 0x088 }, + { "mmss_camss_gp0_clk", 0x22, MMCC, 0x027 }, + { "mmss_camss_gp1_clk", 0x22, MMCC, 0x028 }, + { "mmss_camss_ispif_ahb_clk", 0x22, MMCC, 0x033 }, + { "mmss_camss_jpeg0_clk", 0x22, MMCC, 0x032 }, + { "mmss_camss_jpeg_ahb_clk", 0x22, MMCC, 0x035 }, + { "mmss_camss_jpeg_axi_clk", 0x22, MMCC, 0x036 }, + { "mmss_camss_mclk0_clk", 0x22, MMCC, 0x029 }, + { "mmss_camss_mclk1_clk", 0x22, MMCC, 0x02A }, + { "mmss_camss_mclk2_clk", 0x22, MMCC, 0x02B }, + { "mmss_camss_mclk3_clk", 0x22, MMCC, 0x02C }, + { "mmss_camss_micro_ahb_clk", 0x22, MMCC, 0x026 }, + { "mmss_camss_top_ahb_clk", 0x22, MMCC, 0x025 }, + { "mmss_camss_vfe0_ahb_clk", 0x22, MMCC, 0x086 }, + { "mmss_camss_vfe0_clk", 0x22, MMCC, 0x038 }, + { "mmss_camss_vfe0_stream_clk", 0x22, MMCC, 0x071 }, + { "mmss_camss_vfe1_ahb_clk", 0x22, MMCC, 0x087 }, + { "mmss_camss_vfe1_clk", 0x22, MMCC, 0x039 }, + { "mmss_camss_vfe1_stream_clk", 0x22, MMCC, 0x072 }, + { "mmss_camss_vfe_vbif_ahb_clk", 0x22, MMCC, 0x03C }, + { "mmss_camss_vfe_vbif_axi_clk", 0x22, MMCC, 0x03D }, + { "mmss_csiphy_ahb2crif_clk", 0x22, MMCC, 0x0B8 }, + { "mmss_mdss_ahb_clk", 0x22, MMCC, 0x022 }, + { "mmss_mdss_axi_clk", 0x22, MMCC, 0x024 }, + { "mmss_mdss_byte0_clk", 0x22, MMCC, 0x01E }, + { "mmss_mdss_byte0_intf_clk", 0x22, MMCC, 0x0AD }, + { "mmss_mdss_byte1_clk", 0x22, MMCC, 0x01F }, + { "mmss_mdss_byte1_intf_clk", 0x22, MMCC, 0x0B6 }, + { "mmss_mdss_dp_aux_clk", 0x22, MMCC, 0x09C }, + { "mmss_mdss_dp_crypto_clk", 0x22, MMCC, 0x09A }, + { "mmss_mdss_dp_gtc_clk", 0x22, MMCC, 0x09D }, + { "mmss_mdss_dp_link_clk", 0x22, MMCC, 0x098 }, + { "mmss_mdss_dp_link_intf_clk", 0x22, MMCC, 0x099 }, + { "mmss_mdss_dp_pixel_clk", 0x22, MMCC, 0x09B }, + { "mmss_mdss_esc0_clk", 0x22, MMCC, 0x020 }, + { "mmss_mdss_esc1_clk", 0x22, MMCC, 0x021 }, + { "mmss_mdss_hdmi_dp_ahb_clk", 0x22, MMCC, 0x023 }, + { "mmss_mdss_mdp_clk", 0x22, MMCC, 0x014 }, + { "mmss_mdss_pclk0_clk", 0x22, MMCC, 0x016 }, + { "mmss_mdss_pclk1_clk", 0x22, MMCC, 0x017 }, + { "mmss_mdss_rot_clk", 0x22, MMCC, 0x012 }, + { "mmss_mdss_vsync_clk", 0x22, MMCC, 0x01C }, + { "mmss_misc_ahb_clk", 0x22, MMCC, 0x003 }, + { "mmss_misc_cxo_clk", 0x22, MMCC, 0x077 }, + { "mmss_mnoc_ahb_clk", 0x22, MMCC, 0x001 }, + { "mmss_snoc_dvm_axi_clk", 0x22, MMCC, 0x013 }, + { "mmss_video_ahb_clk", 0x22, MMCC, 0x011 }, + { "mmss_video_axi_clk", 0x22, MMCC, 0x00F }, + { "mmss_video_core_clk", 0x22, MMCC, 0x00E }, + { "mmss_video_subcore0_clk", 0x22, MMCC, 0x01A }, + { "gpucc_gfx3d_clk", 0x13d, GPU, 0x008 }, + { "gpucc_rbbmtimer_clk", 0x13d, GPU, 0x005 }, + { "gpucc_rbcpr_clk", 0x13d, GPU, 0x003 }, + { "pwrcl_clk", 0x0c0, CPU, 0x000, 0x3, 8, 0x0FF }, + { "perfcl_clk", 0x0c0, CPU, 0x100, 0x3, 8, 0x0FF }, + ), + .hw.init = &(struct clk_init_data){ + .name = "gcc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = debug_mux_parent_names, + .num_parents = ARRAY_SIZE(debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const struct of_device_id clk_debug_match_table[] = { + { .compatible = "qcom,gcc-debug-sdm660" }, + {} +}; + +static int clk_debug_660_probe(struct platform_device *pdev) +{ + struct resource *res; + struct clk *clk; + int ret = 0, count; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbg_offset"); + if (!res) { + dev_err(&pdev->dev, "Failed to get debug offset.\n"); + return -EINVAL; + } + gcc_debug_mux.debug_offset = res->start; + + clk = devm_clk_get(&pdev->dev, "xo_clk_src"); + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get xo clock\n"); + return PTR_ERR(clk); + } + + debug_mux_priv.cxo = clk; + + ret = of_property_read_u32(pdev->dev.of_node, "qcom,cc-count", + &count); + if (ret < 0) { + dev_err(&pdev->dev, "Num of debug clock controller not specified\n"); + return ret; + } + + if (!count) { + dev_err(&pdev->dev, "Count of CC cannot be zero\n"); + return -EINVAL; + } + + gcc_debug_mux.num_parent_regmap = count; + + gcc_debug_mux.regmap = devm_kzalloc(&pdev->dev, + sizeof(struct regmap *) * count, GFP_KERNEL); + if (!gcc_debug_mux.regmap) + return -ENOMEM; + + if (of_get_property(pdev->dev.of_node, "qcom,gcc", NULL)) { + gcc_debug_mux.regmap[GCC] = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "qcom,gcc"); + if (IS_ERR(gcc_debug_mux.regmap[GCC])) + return PTR_ERR(gcc_debug_mux.regmap[GCC]); + } + + if (of_get_property(pdev->dev.of_node, "qcom,cpu", NULL)) { + gcc_debug_mux.regmap[CPU] = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "qcom,cpu"); + if (IS_ERR(gcc_debug_mux.regmap[CPU])) + return PTR_ERR(gcc_debug_mux.regmap[CPU]); + } + + if (of_get_property(pdev->dev.of_node, "qcom,mmss", NULL)) { + gcc_debug_mux.regmap[MMCC] = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "qcom,mmss"); + if (IS_ERR(gcc_debug_mux.regmap[MMCC])) + return PTR_ERR(gcc_debug_mux.regmap[MMCC]); + + /* Clear the DBG_CLK_DIV bits of the MMSS debug register */ + regmap_update_bits(gcc_debug_mux.regmap[MMCC], 0x0, + 0x60000, 0x0); + } + + if (of_get_property(pdev->dev.of_node, "qcom,gpu", NULL)) { + gcc_debug_mux.regmap[GPU] = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "qcom,gpu"); + if (IS_ERR(gcc_debug_mux.regmap[GPU])) + return PTR_ERR(gcc_debug_mux.regmap[GPU]); + + /* Clear the DBG_CLK_DIV bits of the GPU debug register */ + regmap_update_bits(gcc_debug_mux.regmap[GPU], 0x0, + 0x60000, 0x0); + } + + clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); + return PTR_ERR(clk); + } + + dev_info(&pdev->dev, "Registered debug mux successfully\n"); + + return ret; +} + +static struct platform_driver clk_debug_driver = { + .probe = clk_debug_660_probe, + .driver = { + .name = "gcc-debug-sdm660", + .of_match_table = clk_debug_match_table, + .owner = THIS_MODULE, + }, +}; + +int __init clk_debug_660_init(void) +{ + return platform_driver_register(&clk_debug_driver); +} +fs_initcall(clk_debug_660_init); diff --git a/drivers/clk/qcom/gpucc-msmfalcon.c b/drivers/clk/qcom/gpucc-msmfalcon.c deleted file mode 100644 index 9b7dd907a6f3..000000000000 --- a/drivers/clk/qcom/gpucc-msmfalcon.c +++ /dev/null @@ -1,498 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk-alpha-pll.h" -#include "common.h" -#include "clk-regmap.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-branch.h" -#include "vdd-level-falcon.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } -#define F_GFX(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) } - -static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGS_INIT(vdd_gfx, 1); - -enum { - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_MAIN, - P_GPLL0_OUT_MAIN_DIV, - P_GPU_PLL0_PLL_OUT_MAIN, - P_GPU_PLL1_PLL_OUT_MAIN, - P_XO, -}; - -static const struct parent_map gpucc_parent_map_0[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gpucc_parent_names_0[] = { - "cxo_a", - "gcc_gpu_gpll0_clk", - "gcc_gpu_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map gpucc_parent_map_1[] = { - { P_XO, 0 }, - { P_GPU_PLL0_PLL_OUT_MAIN, 1 }, - { P_GPU_PLL1_PLL_OUT_MAIN, 3 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gpucc_parent_names_1[] = { - "xo", - "gpu_pll0_pll_out_main", - "gpu_pll1_pll_out_main", - "gcc_gpu_gpll0_clk", - "core_bi_pll_test_se", -}; - -static struct pll_vco gpu_vco[] = { - { 1000000000, 2000000000, 0 }, - { 500000000, 1000000000, 2 }, - { 250000000, 500000000, 3 }, -}; - -/* 800MHz configuration */ -static const struct pll_config gpu_pll0_config = { - .l = 0x29, - .config_ctl_val = 0x4001055b, - .alpha = 0xaaaaab00, - .alpha_u = 0xaa, - .alpha_en_mask = BIT(24), - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct pll_vco_data pll_data[] = { - /* Frequency post-div */ - { 640000000, 0x1 }, -}; - -static struct clk_alpha_pll gpu_pll0_pll_out_main = { - .offset = 0x0, - .vco_table = gpu_vco, - .num_vco = ARRAY_SIZE(gpu_vco), - .vco_data = pll_data, - .num_vco_data = ARRAY_SIZE(pll_data), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gpu_pll0_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000), - }, - }, -}; - -static struct clk_alpha_pll gpu_pll1_pll_out_main = { - .offset = 0x40, - .vco_table = gpu_vco, - .num_vco = ARRAY_SIZE(gpu_vco), - .vco_data = pll_data, - .num_vco_data = ARRAY_SIZE(pll_data), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gpu_pll1_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000), - }, - }, -}; - -/* GFX clock init data */ -static struct clk_init_data gpu_clks_init[] = { - [0] = { - .name = "gfx3d_clk_src", - .parent_names = gpucc_parent_names_1, - .num_parents = 3, - .ops = &clk_gfx3d_src_ops, - .flags = CLK_SET_RATE_PARENT, - }, - [1] = { - .name = "gpucc_gfx3d_clk", - .parent_names = (const char *[]){ - "gfx3d_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - .flags = CLK_SET_RATE_PARENT, - .vdd_class = &vdd_gfx, - }, -}; - -/* - * Frequencies and PLL configuration - * The PLL source would be to ping-pong between GPU-PLL0 - * and GPU-PLL1. - * ==================================================== - * | F | PLL SRC Freq | PLL postdiv | RCG Div | - * ==================================================== - * | 160000000 | 640000000 | 2 | 2 | - * | 266000000 | 532000000 | 1 | 2 | - * | 370000000 | 740000000 | 1 | 2 | - * | 465000000 | 930000000 | 1 | 2 | - * | 588000000 | 1176000000 | 1 | 2 | - * | 647000000 | 1294000000 | 1 | 2 | - * | 700000000 | 1400000000 | 1 | 2 | - * | 750000000 | 1500000000 | 1 | 2 | - * ==================================================== -*/ - -static const struct freq_tbl ftbl_gfx3d_clk_src[] = { - F_GFX( 19200000, 0, 1, 0, 0, 0), - F_GFX(160000000, 0, 2, 0, 0, 640000000), - F_GFX(266000000, 0, 2, 0, 0, 532000000), - F_GFX(370000000, 0, 2, 0, 0, 740000000), - F_GFX(465000000, 0, 2, 0, 0, 930000000), - F_GFX(588000000, 0, 2, 0, 0, 1176000000), - F_GFX(647000000, 0, 2, 0, 0, 1294000000), - F_GFX(700000000, 0, 2, 0, 0, 1400000000), - F_GFX(750000000, 0, 2, 0, 0, 1500000000), - { } -}; - -static const struct freq_tbl ftbl_gfx3d_clk_src_triton[] = { - F_GFX( 19200000, 0, 1, 0, 0, 0), - F_GFX(160000000, 0, 2, 0, 0, 640000000), - F_GFX(240000000, 0, 2, 0, 0, 480000000), - F_GFX(370000000, 0, 2, 0, 0, 740000000), - F_GFX(465000000, 0, 2, 0, 0, 930000000), - F_GFX(588000000, 0, 2, 0, 0, 1176000000), - F_GFX(647000000, 0, 2, 0, 0, 1294000000), - F_GFX(700000000, 0, 2, 0, 0, 1400000000), - F_GFX(775000000, 0, 2, 0, 0, 1550000000), - { } -}; - -static struct clk_rcg2 gfx3d_clk_src = { - .cmd_rcgr = 0x1070, - .mnd_width = 0, - .hid_width = 5, - .freq_tbl = ftbl_gfx3d_clk_src, - .parent_map = gpucc_parent_map_1, - .flags = FORCE_ENABLE_RCGR, - .clkr.hw.init = &gpu_clks_init[0], -}; - -static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 rbbmtimer_clk_src = { - .cmd_rcgr = 0x10b0, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gpucc_parent_map_0, - .freq_tbl = ftbl_rbbmtimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "rbbmtimer_clk_src", - .parent_names = gpucc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1(MIN, 19200000), - }, -}; - -static const struct freq_tbl ftbl_rbcpr_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), - { } -}; - -static struct clk_rcg2 rbcpr_clk_src = { - .cmd_rcgr = 0x1030, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gpucc_parent_map_0, - .freq_tbl = ftbl_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "rbcpr_clk_src", - .parent_names = gpucc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - MIN, 19200000, - NOMINAL, 50000000), - }, -}; - -static struct clk_branch gpucc_cxo_clk = { - .halt_reg = 0x1020, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_cxo_clk", - .parent_names = (const char *[]) { - "cxo_a", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gpucc_gfx3d_clk = { - .halt_reg = 0x1098, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1098, - .enable_mask = BIT(0), - .hw.init = &gpu_clks_init[1], - }, -}; - -static struct clk_branch gpucc_rbbmtimer_clk = { - .halt_reg = 0x10d0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10d0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_rbbmtimer_clk", - .parent_names = (const char *[]){ - "rbbmtimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gpucc_rbcpr_clk = { - .halt_reg = 0x1054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_rbcpr_clk", - .parent_names = (const char *[]){ - "rbcpr_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_regmap *gpucc_falcon_clocks[] = { - [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, - [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr, - [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr, - [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, - [GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr, - [GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr, - [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr, - [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, - [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, -}; - -static const struct regmap_config gpucc_falcon_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x9034, - .fast_io = true, -}; - -static const struct qcom_cc_desc gpucc_falcon_desc = { - .config = &gpucc_falcon_regmap_config, - .clks = gpucc_falcon_clocks, - .num_clks = ARRAY_SIZE(gpucc_falcon_clocks), -}; - -static const struct of_device_id gpucc_falcon_match_table[] = { - { .compatible = "qcom,gpucc-msmfalcon" }, - { .compatible = "qcom,gpucc-msmtriton" }, - { } -}; -MODULE_DEVICE_TABLE(of, gpucc_falcon_match_table); - -static int of_get_fmax_vdd_class(struct platform_device *pdev, - struct clk_hw *hw, char *prop_name, u32 index) -{ - struct device_node *of = pdev->dev.of_node; - int prop_len, i, j; - struct clk_vdd_class *vdd = hw->init->vdd_class; - int num = vdd->num_regulators + 1; - u32 *array; - - if (!of_find_property(of, prop_name, &prop_len)) { - dev_err(&pdev->dev, "missing %s\n", prop_name); - return -EINVAL; - } - - prop_len /= sizeof(u32); - if (prop_len % num) { - dev_err(&pdev->dev, "bad length %d\n", prop_len); - return -EINVAL; - } - - prop_len /= num; - vdd->level_votes = devm_kzalloc(&pdev->dev, prop_len * sizeof(int), - GFP_KERNEL); - if (!vdd->level_votes) - return -ENOMEM; - - vdd->vdd_uv = devm_kzalloc(&pdev->dev, - prop_len * sizeof(int) * (num - 1), GFP_KERNEL); - if (!vdd->vdd_uv) - return -ENOMEM; - - gpu_clks_init[index].rate_max = devm_kzalloc(&pdev->dev, prop_len * - sizeof(unsigned long), GFP_KERNEL); - if (!gpu_clks_init[index].rate_max) - return -ENOMEM; - - array = devm_kzalloc(&pdev->dev, prop_len * sizeof(u32) * num, - GFP_KERNEL); - if (!array) - return -ENOMEM; - - of_property_read_u32_array(of, prop_name, array, prop_len * num); - for (i = 0; i < prop_len; i++) { - gpu_clks_init[index].rate_max[i] = array[num * i]; - for (j = 1; j < num; j++) { - vdd->vdd_uv[(num - 1) * i + (j - 1)] = - array[num * i + j]; - } - } - - devm_kfree(&pdev->dev, array); - vdd->num_levels = prop_len; - vdd->cur_level = prop_len; - gpu_clks_init[index].num_rate_max = prop_len; - - return 0; -} - -static int gpucc_falcon_probe(struct platform_device *pdev) -{ - int ret = 0; - struct regmap *regmap; - bool is_triton = 0; - - regmap = qcom_cc_map(pdev, &gpucc_falcon_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* CX Regulator for RBBMTimer and RBCPR clock */ - vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_gfx"); - if (IS_ERR(vdd_dig.regulator[0])) { - if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_dig regulator\n"); - return PTR_ERR(vdd_dig.regulator[0]); - } - - /* Mx Regulator for GPU-PLLs */ - vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_gfx"); - if (IS_ERR(vdd_mx.regulator[0])) { - if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_mx regulator\n"); - return PTR_ERR(vdd_mx.regulator[0]); - } - - /* GFX Rail Regulator for GFX3D clock */ - vdd_gfx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gfx"); - if (IS_ERR(vdd_gfx.regulator[0])) { - if (!(PTR_ERR(vdd_gfx.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_gfx regulator\n"); - return PTR_ERR(vdd_gfx.regulator[0]); - } - - is_triton = of_device_is_compatible(pdev->dev.of_node, - "qcom,gpucc-msmtriton"); - if (is_triton) { - gpu_pll0_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] - = 1550000000; - gpu_pll1_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] - = 1550000000; - /* Add new frequency table */ - gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_triton; - } - - /* GFX rail fmax data linked to branch clock */ - of_get_fmax_vdd_class(pdev, &gpucc_gfx3d_clk.clkr.hw, - "qcom,gfxfreq-corner", 1); - - clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, - &gpu_pll0_config); - clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, - &gpu_pll0_config); - - ret = qcom_cc_really_probe(pdev, &gpucc_falcon_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register GPUCC clocks\n"); - return ret; - } - - clk_prepare_enable(gpucc_cxo_clk.clkr.hw.clk); - - dev_info(&pdev->dev, "Registered GPUCC clocks\n"); - - return ret; -} - -static struct platform_driver gpucc_falcon_driver = { - .probe = gpucc_falcon_probe, - .driver = { - .name = "gpucc-msmfalcon", - .of_match_table = gpucc_falcon_match_table, - }, -}; - -static int __init gpucc_falcon_init(void) -{ - return platform_driver_register(&gpucc_falcon_driver); -} -core_initcall_sync(gpucc_falcon_init); - -static void __exit gpucc_falcon_exit(void) -{ - platform_driver_unregister(&gpucc_falcon_driver); -} -module_exit(gpucc_falcon_exit); diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c new file mode 100644 index 000000000000..b16b17451c76 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -0,0 +1,498 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "vdd-level-660.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } +#define F_GFX(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) } + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGS_INIT(vdd_gfx, 1); + +enum { + P_CORE_BI_PLL_TEST_SE, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_PLL0_PLL_OUT_MAIN, + P_GPU_PLL1_PLL_OUT_MAIN, + P_XO, +}; + +static const struct parent_map gpucc_parent_map_0[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gpucc_parent_names_0[] = { + "cxo_a", + "gcc_gpu_gpll0_clk", + "gcc_gpu_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map gpucc_parent_map_1[] = { + { P_XO, 0 }, + { P_GPU_PLL0_PLL_OUT_MAIN, 1 }, + { P_GPU_PLL1_PLL_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gpucc_parent_names_1[] = { + "xo", + "gpu_pll0_pll_out_main", + "gpu_pll1_pll_out_main", + "gcc_gpu_gpll0_clk", + "core_bi_pll_test_se", +}; + +static struct pll_vco gpu_vco[] = { + { 1000000000, 2000000000, 0 }, + { 500000000, 1000000000, 2 }, + { 250000000, 500000000, 3 }, +}; + +/* 800MHz configuration */ +static const struct pll_config gpu_pll0_config = { + .l = 0x29, + .config_ctl_val = 0x4001055b, + .alpha = 0xaaaaab00, + .alpha_u = 0xaa, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct pll_vco_data pll_data[] = { + /* Frequency post-div */ + { 640000000, 0x1 }, +}; + +static struct clk_alpha_pll gpu_pll0_pll_out_main = { + .offset = 0x0, + .vco_table = gpu_vco, + .num_vco = ARRAY_SIZE(gpu_vco), + .vco_data = pll_data, + .num_vco_data = ARRAY_SIZE(pll_data), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_pll0_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000), + }, + }, +}; + +static struct clk_alpha_pll gpu_pll1_pll_out_main = { + .offset = 0x40, + .vco_table = gpu_vco, + .num_vco = ARRAY_SIZE(gpu_vco), + .vco_data = pll_data, + .num_vco_data = ARRAY_SIZE(pll_data), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_pll1_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000), + }, + }, +}; + +/* GFX clock init data */ +static struct clk_init_data gpu_clks_init[] = { + [0] = { + .name = "gfx3d_clk_src", + .parent_names = gpucc_parent_names_1, + .num_parents = 3, + .ops = &clk_gfx3d_src_ops, + .flags = CLK_SET_RATE_PARENT, + }, + [1] = { + .name = "gpucc_gfx3d_clk", + .parent_names = (const char *[]){ + "gfx3d_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + .vdd_class = &vdd_gfx, + }, +}; + +/* + * Frequencies and PLL configuration + * The PLL source would be to ping-pong between GPU-PLL0 + * and GPU-PLL1. + * ==================================================== + * | F | PLL SRC Freq | PLL postdiv | RCG Div | + * ==================================================== + * | 160000000 | 640000000 | 2 | 2 | + * | 266000000 | 532000000 | 1 | 2 | + * | 370000000 | 740000000 | 1 | 2 | + * | 465000000 | 930000000 | 1 | 2 | + * | 588000000 | 1176000000 | 1 | 2 | + * | 647000000 | 1294000000 | 1 | 2 | + * | 700000000 | 1400000000 | 1 | 2 | + * | 750000000 | 1500000000 | 1 | 2 | + * ==================================================== +*/ + +static const struct freq_tbl ftbl_gfx3d_clk_src[] = { + F_GFX( 19200000, 0, 1, 0, 0, 0), + F_GFX(160000000, 0, 2, 0, 0, 640000000), + F_GFX(266000000, 0, 2, 0, 0, 532000000), + F_GFX(370000000, 0, 2, 0, 0, 740000000), + F_GFX(465000000, 0, 2, 0, 0, 930000000), + F_GFX(588000000, 0, 2, 0, 0, 1176000000), + F_GFX(647000000, 0, 2, 0, 0, 1294000000), + F_GFX(700000000, 0, 2, 0, 0, 1400000000), + F_GFX(750000000, 0, 2, 0, 0, 1500000000), + { } +}; + +static const struct freq_tbl ftbl_gfx3d_clk_src_triton[] = { + F_GFX( 19200000, 0, 1, 0, 0, 0), + F_GFX(160000000, 0, 2, 0, 0, 640000000), + F_GFX(240000000, 0, 2, 0, 0, 480000000), + F_GFX(370000000, 0, 2, 0, 0, 740000000), + F_GFX(465000000, 0, 2, 0, 0, 930000000), + F_GFX(588000000, 0, 2, 0, 0, 1176000000), + F_GFX(647000000, 0, 2, 0, 0, 1294000000), + F_GFX(700000000, 0, 2, 0, 0, 1400000000), + F_GFX(775000000, 0, 2, 0, 0, 1550000000), + { } +}; + +static struct clk_rcg2 gfx3d_clk_src = { + .cmd_rcgr = 0x1070, + .mnd_width = 0, + .hid_width = 5, + .freq_tbl = ftbl_gfx3d_clk_src, + .parent_map = gpucc_parent_map_1, + .flags = FORCE_ENABLE_RCGR, + .clkr.hw.init = &gpu_clks_init[0], +}; + +static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 rbbmtimer_clk_src = { + .cmd_rcgr = 0x10b0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_0, + .freq_tbl = ftbl_rbbmtimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbbmtimer_clk_src", + .parent_names = gpucc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1(MIN, 19200000), + }, +}; + +static const struct freq_tbl ftbl_rbcpr_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_clk_src = { + .cmd_rcgr = 0x1030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_0, + .freq_tbl = ftbl_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_clk_src", + .parent_names = gpucc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + MIN, 19200000, + NOMINAL, 50000000), + }, +}; + +static struct clk_branch gpucc_cxo_clk = { + .halt_reg = 0x1020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cxo_clk", + .parent_names = (const char *[]) { + "cxo_a", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gfx3d_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &gpu_clks_init[1], + }, +}; + +static struct clk_branch gpucc_rbbmtimer_clk = { + .halt_reg = 0x10d0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10d0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_rbbmtimer_clk", + .parent_names = (const char *[]){ + "rbbmtimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_rbcpr_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_rbcpr_clk", + .parent_names = (const char *[]){ + "rbcpr_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gpucc_660_clocks[] = { + [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, + [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr, + [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr, + [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, + [GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr, + [GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr, + [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr, + [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, + [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, +}; + +static const struct regmap_config gpucc_660_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9034, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpucc_660_desc = { + .config = &gpucc_660_regmap_config, + .clks = gpucc_660_clocks, + .num_clks = ARRAY_SIZE(gpucc_660_clocks), +}; + +static const struct of_device_id gpucc_660_match_table[] = { + { .compatible = "qcom,gpucc-sdm660" }, + { .compatible = "qcom,gpucc-msmtriton" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpucc_660_match_table); + +static int of_get_fmax_vdd_class(struct platform_device *pdev, + struct clk_hw *hw, char *prop_name, u32 index) +{ + struct device_node *of = pdev->dev.of_node; + int prop_len, i, j; + struct clk_vdd_class *vdd = hw->init->vdd_class; + int num = vdd->num_regulators + 1; + u32 *array; + + if (!of_find_property(of, prop_name, &prop_len)) { + dev_err(&pdev->dev, "missing %s\n", prop_name); + return -EINVAL; + } + + prop_len /= sizeof(u32); + if (prop_len % num) { + dev_err(&pdev->dev, "bad length %d\n", prop_len); + return -EINVAL; + } + + prop_len /= num; + vdd->level_votes = devm_kzalloc(&pdev->dev, prop_len * sizeof(int), + GFP_KERNEL); + if (!vdd->level_votes) + return -ENOMEM; + + vdd->vdd_uv = devm_kzalloc(&pdev->dev, + prop_len * sizeof(int) * (num - 1), GFP_KERNEL); + if (!vdd->vdd_uv) + return -ENOMEM; + + gpu_clks_init[index].rate_max = devm_kzalloc(&pdev->dev, prop_len * + sizeof(unsigned long), GFP_KERNEL); + if (!gpu_clks_init[index].rate_max) + return -ENOMEM; + + array = devm_kzalloc(&pdev->dev, prop_len * sizeof(u32) * num, + GFP_KERNEL); + if (!array) + return -ENOMEM; + + of_property_read_u32_array(of, prop_name, array, prop_len * num); + for (i = 0; i < prop_len; i++) { + gpu_clks_init[index].rate_max[i] = array[num * i]; + for (j = 1; j < num; j++) { + vdd->vdd_uv[(num - 1) * i + (j - 1)] = + array[num * i + j]; + } + } + + devm_kfree(&pdev->dev, array); + vdd->num_levels = prop_len; + vdd->cur_level = prop_len; + gpu_clks_init[index].num_rate_max = prop_len; + + return 0; +} + +static int gpucc_660_probe(struct platform_device *pdev) +{ + int ret = 0; + struct regmap *regmap; + bool is_triton = 0; + + regmap = qcom_cc_map(pdev, &gpucc_660_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* CX Regulator for RBBMTimer and RBCPR clock */ + vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_gfx"); + if (IS_ERR(vdd_dig.regulator[0])) { + if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig regulator\n"); + return PTR_ERR(vdd_dig.regulator[0]); + } + + /* Mx Regulator for GPU-PLLs */ + vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_gfx"); + if (IS_ERR(vdd_mx.regulator[0])) { + if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_mx regulator\n"); + return PTR_ERR(vdd_mx.regulator[0]); + } + + /* GFX Rail Regulator for GFX3D clock */ + vdd_gfx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gfx"); + if (IS_ERR(vdd_gfx.regulator[0])) { + if (!(PTR_ERR(vdd_gfx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_gfx regulator\n"); + return PTR_ERR(vdd_gfx.regulator[0]); + } + + is_triton = of_device_is_compatible(pdev->dev.of_node, + "qcom,gpucc-msmtriton"); + if (is_triton) { + gpu_pll0_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] + = 1550000000; + gpu_pll1_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] + = 1550000000; + /* Add new frequency table */ + gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_triton; + } + + /* GFX rail fmax data linked to branch clock */ + of_get_fmax_vdd_class(pdev, &gpucc_gfx3d_clk.clkr.hw, + "qcom,gfxfreq-corner", 1); + + clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, + &gpu_pll0_config); + clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, + &gpu_pll0_config); + + ret = qcom_cc_really_probe(pdev, &gpucc_660_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GPUCC clocks\n"); + return ret; + } + + clk_prepare_enable(gpucc_cxo_clk.clkr.hw.clk); + + dev_info(&pdev->dev, "Registered GPUCC clocks\n"); + + return ret; +} + +static struct platform_driver gpucc_660_driver = { + .probe = gpucc_660_probe, + .driver = { + .name = "gpucc-sdm660", + .of_match_table = gpucc_660_match_table, + }, +}; + +static int __init gpucc_660_init(void) +{ + return platform_driver_register(&gpucc_660_driver); +} +core_initcall_sync(gpucc_660_init); + +static void __exit gpucc_660_exit(void) +{ + platform_driver_unregister(&gpucc_660_driver); +} +module_exit(gpucc_660_exit); diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c index b51ab4f21561..f356be38a25c 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.c +++ b/drivers/clk/qcom/mdss/mdss-pll.c @@ -133,9 +133,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, pll_res->pll_interface_type = MDSS_DSI_PLL_8996; pll_res->target_id = MDSS_PLL_TARGET_8996; pll_res->revision = 2; - } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_msmfalcon")) { + } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_sdm660")) { pll_res->pll_interface_type = MDSS_DSI_PLL_8996; - pll_res->target_id = MDSS_PLL_TARGET_MSMFALCON; + pll_res->target_id = MDSS_PLL_TARGET_SDM660; pll_res->revision = 2; } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) { pll_res->pll_interface_type = MDSS_DSI_PLL_8998; @@ -382,7 +382,7 @@ static const struct of_device_id mdss_pll_dt_match[] = { {.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"}, {.compatible = "qcom,mdss_dp_pll_8998"}, {.compatible = "qcom,mdss_hdmi_pll_8998"}, - {.compatible = "qcom,mdss_dsi_pll_msmfalcon"}, + {.compatible = "qcom,mdss_dsi_pll_sdm660"}, {} }; diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h index 01664eaa815c..e0e62a0f379b 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.h +++ b/drivers/clk/qcom/mdss/mdss-pll.h @@ -51,7 +51,7 @@ enum { enum { MDSS_PLL_TARGET_8996, - MDSS_PLL_TARGET_MSMFALCON, + MDSS_PLL_TARGET_SDM660, }; #define DFPS_MAX_NUM_OF_FRAME_RATES 20 diff --git a/drivers/clk/qcom/mmcc-msmfalcon.c b/drivers/clk/qcom/mmcc-msmfalcon.c deleted file mode 100644 index 59dbebd825fd..000000000000 --- a/drivers/clk/qcom/mmcc-msmfalcon.c +++ /dev/null @@ -1,3056 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "common.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-voter.h" -#include "reset.h" -#include "vdd-level-falcon.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } -#define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \ - (src_freq) } - -enum vdd_a_levels { - VDDA_NONE, - VDDA_LOWER, /* SVS2 */ - VDDA_NUM, -}; - -static int vdda_levels[] = { - 0, - 1800000, -}; - -#define VDDA_FMAX_MAP1(l1, f1) \ - .vdd_class = &vdda, \ - .rate_max = (unsigned long[VDDA_NUM]) { \ - [VDDA_##l1] = (f1), \ - }, \ - .num_rate_max = VDDA_NUM - -static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdda, VDDA_NUM, 1, vdda_levels); - -enum { - P_CORE_BI_PLL_TEST_SE, - P_CORE_PI_SLEEP_CLK, - P_CXO, - P_DP_PHY_PLL_LINK_CLK, - P_DP_PHY_PLL_VCO_DIV, - P_DSI0_PHY_PLL_OUT_BYTECLK, - P_DSI0_PHY_PLL_OUT_DSICLK, - P_DSI1_PHY_PLL_OUT_BYTECLK, - P_DSI1_PHY_PLL_OUT_DSICLK, - P_GPLL0_OUT_MAIN, - P_GPLL0_OUT_MAIN_DIV, - P_MMPLL0_PLL_OUT_MAIN, - P_MMPLL10_PLL_OUT_MAIN, - P_MMPLL3_PLL_OUT_MAIN, - P_MMPLL4_PLL_OUT_MAIN, - P_MMPLL5_PLL_OUT_MAIN, - P_MMPLL6_PLL_OUT_MAIN, - P_MMPLL7_PLL_OUT_MAIN, - P_MMPLL8_PLL_OUT_MAIN, -}; - -static const struct parent_map mmcc_parent_map_0[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL4_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_MMPLL8_PLL_OUT_MAIN, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_0[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll8_pll_out_main", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_1[] = { - { P_CXO, 0 }, - { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, - { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_1[] = { - "xo", - "dsi0pll_byte_clk_mux", - "dsi1pll_byte_clk_mux", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_2[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL4_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_MMPLL10_PLL_OUT_MAIN, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_2[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_3[] = { - { P_CXO, 0 }, - { P_MMPLL4_PLL_OUT_MAIN, 1 }, - { P_MMPLL7_PLL_OUT_MAIN, 2 }, - { P_MMPLL10_PLL_OUT_MAIN, 3 }, - { P_CORE_PI_SLEEP_CLK, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_3[] = { - "xo", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "core_pi_sleep_clk", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_4[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL7_PLL_OUT_MAIN, 2 }, - { P_MMPLL10_PLL_OUT_MAIN, 3 }, - { P_CORE_PI_SLEEP_CLK, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_4[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "core_pi_sleep_clk", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_5[] = { - { P_CXO, 0 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_5[] = { - "xo", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_6[] = { - { P_CXO, 0 }, - { P_DP_PHY_PLL_LINK_CLK, 1 }, - { P_DP_PHY_PLL_VCO_DIV, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_6[] = { - "xo", - "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_7[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL5_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_7[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll5_pll_out_main", - "mmpll7_pll_out_main", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_8[] = { - { P_CXO, 0 }, - { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_8[] = { - "xo", - "dsi0pll_pixel_clk_mux", - "dsi1pll_pixel_clk_mux", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_9[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL4_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_MMPLL10_PLL_OUT_MAIN, 4 }, - { P_MMPLL6_PLL_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_9[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "mmpll6_pll_out_main", - "gcc_mmss_gpll0_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_10[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_10[] = { - "xo", - "mmpll0_pll_out_main", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_11[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL4_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_MMPLL10_PLL_OUT_MAIN, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_MMPLL6_PLL_OUT_MAIN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_11[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "gcc_mmss_gpll0_clk", - "mmpll6_pll_out_main", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_12[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL8_PLL_OUT_MAIN, 2 }, - { P_MMPLL3_PLL_OUT_MAIN, 3 }, - { P_MMPLL6_PLL_OUT_MAIN, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_MMPLL7_PLL_OUT_MAIN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_12[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll8_pll_out_main", - "mmpll3_pll_out_main", - "mmpll6_pll_out_main", - "gcc_mmss_gpll0_clk", - "mmpll7_pll_out_main", - "core_bi_pll_test_se", -}; - -/* Voteable PLL */ -static struct clk_alpha_pll mmpll0_pll_out_main = { - .offset = 0xc000, - .clkr = { - .enable_reg = 0x1f0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmpll0_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 404000000, - LOW, 808000000), - }, - }, -}; - -static struct clk_alpha_pll mmpll6_pll_out_main = { - .offset = 0xf0, - .clkr = { - .enable_reg = 0x1f0, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "mmpll6_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 540000000, - LOW_L1, 1080000000), - }, - }, -}; - -/* APSS controlled PLLs */ -static struct pll_vco vco[] = { - { 1000000000, 2000000000, 0 }, - { 750000000, 1500000000, 1 }, - { 500000000, 1000000000, 2 }, - { 250000000, 500000000, 3 }, -}; - -static const struct pll_config mmpll10_config = { - .l = 0x1e, - .config_ctl_val = 0x00004289, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll10_pll_out_main = { - .offset = 0x190, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll10_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDDA_FMAX_MAP1(LOWER, 576000000), - }, - }, -}; - -static struct pll_vco mmpll3_vco[] = { - { 750000000, 1500000000, 1 }, -}; - -static const struct pll_config mmpll3_config = { - .l = 0x2e, - .config_ctl_val = 0x4001055b, - .vco_val = 0x1 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll3_pll_out_main = { - .offset = 0x0, - .vco_table = mmpll3_vco, - .num_vco = ARRAY_SIZE(mmpll3_vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll3_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_slew_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 441600000, - NOMINAL, 1036800000), - }, - }, -}; - -static const struct pll_config mmpll4_config = { - .l = 0x28, - .config_ctl_val = 0x4001055b, - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll4_pll_out_main = { - .offset = 0x50, - .vco_table = vco, - .num_vco = ARRAY_SIZE(vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll4_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 384000000, - LOW, 768000000), - }, - }, -}; - -static const struct pll_config mmpll5_config = { - .l = 0x2a, - .config_ctl_val = 0x4001055b, - .alpha_u = 0xf8, - .alpha_en_mask = BIT(24), - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll5_pll_out_main = { - .offset = 0xa0, - .vco_table = vco, - .num_vco = ARRAY_SIZE(vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll5_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 421500000, - LOW, 825000000), - }, - }, -}; - -static const struct pll_config mmpll7_config = { - .l = 0x32, - .config_ctl_val = 0x4001055b, - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll7_pll_out_main = { - .offset = 0x140, - .vco_table = vco, - .num_vco = ARRAY_SIZE(vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll7_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 480000000, - LOW, 960000000), - }, - }, -}; - -static const struct pll_config mmpll8_config = { - .l = 0x30, - .alpha_u = 0x70, - .alpha_en_mask = BIT(24), - .config_ctl_val = 0x4001055b, - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll8_pll_out_main = { - .offset = 0x1c0, - .vco_table = vco, - .num_vco = ARRAY_SIZE(vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll8_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 465000000, - LOW, 930000000), - }, - }, -}; - -static const struct freq_tbl ftbl_ahb_clk_src[] = { - F(19200000, P_CXO, 1, 0, 0), - F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), - F(80800000, P_MMPLL0_PLL_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 ahb_clk_src = { - .cmd_rcgr = 0x5000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_10, - .freq_tbl = ftbl_ahb_clk_src, - .flags = FORCE_ENABLE_RCGR, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ahb_clk_src", - .parent_names = mmcc_parent_names_10, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 40000000, - NOMINAL, 80800000), - }, -}; - -static struct clk_rcg2 byte0_clk_src = { - .cmd_rcgr = 0x2120, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_1, - .clkr.hw.init = &(struct clk_init_data){ - .name = "byte0_clk_src", - .parent_names = mmcc_parent_names_1, - .num_parents = 4, - .ops = &clk_byte2_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - VDD_DIG_FMAX_MAP3( - LOWER, 131250000, - LOW, 210000000, - NOMINAL, 262500000), - }, -}; - -static struct clk_rcg2 byte1_clk_src = { - .cmd_rcgr = 0x2140, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_1, - .clkr.hw.init = &(struct clk_init_data){ - .name = "byte1_clk_src", - .parent_names = mmcc_parent_names_1, - .num_parents = 4, - .ops = &clk_byte2_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - VDD_DIG_FMAX_MAP3( - LOWER, 131250000, - LOW, 210000000, - NOMINAL, 262500000), - }, -}; - -static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { - F(10000, P_CXO, 16, 1, 120), - F(24000, P_CXO, 16, 1, 50), - F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), - F(12000000, P_GPLL0_OUT_MAIN_DIV, 10, 2, 5), - F(13043478, P_GPLL0_OUT_MAIN_DIV, 1, 1, 23), - F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), - F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 camss_gp0_clk_src = { - .cmd_rcgr = 0x3420, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_4, - .freq_tbl = ftbl_camss_gp0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "camss_gp0_clk_src", - .parent_names = mmcc_parent_names_4, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static struct clk_rcg2 camss_gp1_clk_src = { - .cmd_rcgr = 0x3450, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_4, - .freq_tbl = ftbl_camss_gp0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "camss_gp1_clk_src", - .parent_names = mmcc_parent_names_4, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static const struct freq_tbl ftbl_cci_clk_src[] = { - F(37500000, P_GPLL0_OUT_MAIN_DIV, 8, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 cci_clk_src = { - .cmd_rcgr = 0x3300, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_4, - .freq_tbl = ftbl_cci_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cci_clk_src", - .parent_names = mmcc_parent_names_4, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 37500000, - LOW, 50000000, - NOMINAL, 100000000), - }, -}; - -static const struct freq_tbl ftbl_cpp_clk_src[] = { - F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), - F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), - F(384000000, P_MMPLL4_PLL_OUT_MAIN, 2, 0, 0), - F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), - F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), - F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cpp_clk_src = { - .cmd_rcgr = 0x3640, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_11, - .freq_tbl = ftbl_cpp_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cpp_clk_src", - .parent_names = mmcc_parent_names_11, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP6( - LOWER, 120000000, - LOW, 256000000, - LOW_L1, 384000000, - NOMINAL, 480000000, - NOMINAL_L1, 540000000, - HIGH, 576000000), - }, -}; - -static const struct freq_tbl ftbl_csi0_clk_src[] = { - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(310000000, P_MMPLL8_PLL_OUT_MAIN, 3, 0, 0), - F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), - F(465000000, P_MMPLL8_PLL_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 csi0_clk_src = { - .cmd_rcgr = 0x3090, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csi0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi0_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 310000000, - NOMINAL, 404000000, - NOMINAL_L1, 465000000), - }, -}; - -static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 csi0phytimer_clk_src = { - .cmd_rcgr = 0x3000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_2, - .freq_tbl = ftbl_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi0phytimer_clk_src", - .parent_names = mmcc_parent_names_2, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 269333333), - }, -}; - -static struct clk_rcg2 csi1_clk_src = { - .cmd_rcgr = 0x3100, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csi0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi1_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 310000000, - NOMINAL, 404000000, - NOMINAL_L1, 465000000), - }, -}; - -static struct clk_rcg2 csi1phytimer_clk_src = { - .cmd_rcgr = 0x3030, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_2, - .freq_tbl = ftbl_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi1phytimer_clk_src", - .parent_names = mmcc_parent_names_2, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 269333333), - }, -}; - -static struct clk_rcg2 csi2_clk_src = { - .cmd_rcgr = 0x3160, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csi0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi2_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 310000000, - NOMINAL, 404000000, - NOMINAL_L1, 465000000), - }, -}; - -static struct clk_rcg2 csi2phytimer_clk_src = { - .cmd_rcgr = 0x3060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_2, - .freq_tbl = ftbl_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi2phytimer_clk_src", - .parent_names = mmcc_parent_names_2, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 269333333), - }, -}; - -static struct clk_rcg2 csi3_clk_src = { - .cmd_rcgr = 0x31c0, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csi0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi3_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 310000000, - NOMINAL, 404000000, - NOMINAL_L1, 465000000), - }, -}; - -static const struct freq_tbl ftbl_csiphy_clk_src[] = { - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), - F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 csiphy_clk_src = { - .cmd_rcgr = 0x3800, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csiphy_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csiphy_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP4( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 269333333, - NOMINAL, 320000000), - }, -}; - -static const struct freq_tbl ftbl_dp_aux_clk_src[] = { - F(19200000, P_CXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 dp_aux_clk_src = { - .cmd_rcgr = 0x2260, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_5, - .freq_tbl = ftbl_dp_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_aux_clk_src", - .parent_names = mmcc_parent_names_5, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static const struct freq_tbl ftbl_dp_crypto_clk_src[] = { - F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), - F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), - F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), - { } -}; - -static struct clk_rcg2 dp_crypto_clk_src = { - .cmd_rcgr = 0x2220, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_6, - .freq_tbl = ftbl_dp_crypto_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_crypto_clk_src", - .parent_names = mmcc_parent_names_6, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 101250000, - LOW, 168750000, - NOMINAL, 337500000), - }, -}; - -static const struct freq_tbl ftbl_dp_gtc_clk_src[] = { - F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 dp_gtc_clk_src = { - .cmd_rcgr = 0x2280, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_5, - .freq_tbl = ftbl_dp_gtc_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_gtc_clk_src", - .parent_names = mmcc_parent_names_5, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 40000000, - LOW, 60000000), - }, -}; - -static const struct freq_tbl ftbl_dp_link_clk_src[] = { - F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), - F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), - F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), - { } -}; - -static struct clk_rcg2 dp_link_clk_src = { - .cmd_rcgr = 0x2200, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_6, - .freq_tbl = ftbl_dp_link_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_link_clk_src", - .parent_names = mmcc_parent_names_6, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, - VDD_DIG_FMAX_MAP3( - LOWER, 162000000, - LOW, 270000000, - NOMINAL, 540000000), - }, -}; - -static struct clk_rcg2 dp_pixel_clk_src = { - .cmd_rcgr = 0x2240, - .mnd_width = 16, - .hid_width = 5, - .parent_map = mmcc_parent_map_6, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_pixel_clk_src", - .parent_names = mmcc_parent_names_6, - .num_parents = 4, - .ops = &clk_dp_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 148380000, - LOW, 296740000, - NOMINAL, 593470000), - }, -}; - -static struct clk_rcg2 esc0_clk_src = { - .cmd_rcgr = 0x2160, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_1, - .freq_tbl = ftbl_dp_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "esc0_clk_src", - .parent_names = mmcc_parent_names_1, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static struct clk_rcg2 esc1_clk_src = { - .cmd_rcgr = 0x2180, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_1, - .freq_tbl = ftbl_dp_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "esc1_clk_src", - .parent_names = mmcc_parent_names_1, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static const struct freq_tbl ftbl_jpeg0_clk_src[] = { - F(66666667, P_GPLL0_OUT_MAIN_DIV, 4.5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(219428571, P_MMPLL4_PLL_OUT_MAIN, 3.5, 0, 0), - F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), - F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 jpeg0_clk_src = { - .cmd_rcgr = 0x3500, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_2, - .freq_tbl = ftbl_jpeg0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "jpeg0_clk_src", - .parent_names = mmcc_parent_names_2, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 66666667, - LOW, 133333333, - LOW_L1, 219428571, - NOMINAL, 320000000, - NOMINAL_L1, 480000000), - }, -}; - -static const struct freq_tbl ftbl_mclk0_clk_src[] = { - F(4800000, P_CXO, 4, 0, 0), - F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), - F(8000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 75), - F(9600000, P_CXO, 2, 0, 0), - F(16666667, P_GPLL0_OUT_MAIN_DIV, 2, 1, 9), - F(19200000, P_CXO, 1, 0, 0), - F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), - F(33333333, P_GPLL0_OUT_MAIN_DIV, 1, 1, 9), - F(48000000, P_GPLL0_OUT_MAIN, 1, 2, 25), - F(66666667, P_GPLL0_OUT_MAIN, 1, 1, 9), - { } -}; - -static struct clk_rcg2 mclk0_clk_src = { - .cmd_rcgr = 0x3360, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_3, - .freq_tbl = ftbl_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mclk0_clk_src", - .parent_names = mmcc_parent_names_3, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 33333333, - LOW, 66666667), - }, -}; - -static struct clk_rcg2 mclk1_clk_src = { - .cmd_rcgr = 0x3390, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_3, - .freq_tbl = ftbl_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mclk1_clk_src", - .parent_names = mmcc_parent_names_3, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 33333333, - LOW, 66666667), - }, -}; - -static struct clk_rcg2 mclk2_clk_src = { - .cmd_rcgr = 0x33c0, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_3, - .freq_tbl = ftbl_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mclk2_clk_src", - .parent_names = mmcc_parent_names_3, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 33333333, - LOW, 66666667), - }, -}; - -static struct clk_rcg2 mclk3_clk_src = { - .cmd_rcgr = 0x33f0, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_3, - .freq_tbl = ftbl_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mclk3_clk_src", - .parent_names = mmcc_parent_names_3, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 33333333, - LOW, 66666667), - }, -}; - -static const struct freq_tbl ftbl_mdp_clk_src[] = { - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), - F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), - F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 mdp_clk_src = { - .cmd_rcgr = 0x2040, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_7, - .freq_tbl = ftbl_mdp_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mdp_clk_src", - .parent_names = mmcc_parent_names_7, - .num_parents = 7, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 171428571, - LOW, 275000000, - LOW_L1, 300000000, - NOMINAL, 330000000, - HIGH, 412500000), - }, -}; - -static struct clk_rcg2 pclk0_clk_src = { - .cmd_rcgr = 0x2000, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_8, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pclk0_clk_src", - .parent_names = mmcc_parent_names_8, - .num_parents = 4, - .ops = &clk_pixel_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - VDD_DIG_FMAX_MAP3( - LOWER, 175000000, - LOW, 280000000, - NOMINAL, 350000000), - }, -}; - -static struct clk_rcg2 pclk1_clk_src = { - .cmd_rcgr = 0x2020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_8, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pclk1_clk_src", - .parent_names = mmcc_parent_names_8, - .num_parents = 4, - .ops = &clk_pixel_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - VDD_DIG_FMAX_MAP3( - LOWER, 175000000, - LOW, 280000000, - NOMINAL, 350000000), - }, -}; - -static const struct freq_tbl ftbl_rot_clk_src[] = { - F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), - F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), - F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 rot_clk_src = { - .cmd_rcgr = 0x21a0, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_7, - .freq_tbl = ftbl_rot_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "rot_clk_src", - .parent_names = mmcc_parent_names_7, - .num_parents = 7, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 171428571, - LOW, 275000000, - LOW_L1, 300000000, - NOMINAL, 330000000, - HIGH, 412500000), - }, -}; - -static const struct freq_tbl ftbl_vfe0_clk_src[] = { - F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), - F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), - F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), - F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 vfe0_clk_src = { - .cmd_rcgr = 0x3600, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_9, - .freq_tbl = ftbl_vfe0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "vfe0_clk_src", - .parent_names = mmcc_parent_names_9, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP6( - LOWER, 120000000, - LOW, 256000000, - LOW_L1, 404000000, - NOMINAL, 480000000, - NOMINAL_L1, 540000000, - HIGH, 576000000), - }, -}; - -static struct clk_rcg2 vfe1_clk_src = { - .cmd_rcgr = 0x3620, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_9, - .freq_tbl = ftbl_vfe0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "vfe1_clk_src", - .parent_names = mmcc_parent_names_9, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP6( - LOWER, 120000000, - LOW, 256000000, - LOW_L1, 404000000, - NOMINAL, 480000000, - NOMINAL_L1, 540000000, - HIGH, 576000000), - }, -}; - -static const struct freq_tbl ftbl_video_core_clk_src[] = { - F_SLEW(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0, FIXED_FREQ_SRC), - F_SLEW(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), - F_SLEW(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), - F_SLEW(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0, FIXED_FREQ_SRC), - F_SLEW(441600000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 883200000), - F_SLEW(518400000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 1036800000), - { } -}; - -static struct clk_rcg2 video_core_clk_src = { - .cmd_rcgr = 0x1000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_12, - .freq_tbl = ftbl_video_core_clk_src, - .flags = FORCE_ENABLE_RCGR, - .clkr.hw.init = &(struct clk_init_data){ - .name = "video_core_clk_src", - .parent_names = mmcc_parent_names_12, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP6( - LOWER, 133333333, - LOW, 269333333, - LOW_L1, 320000000, - NOMINAL, 404000000, - NOMINAL_L1, 441600000, - HIGH, 518400000), - }, -}; - -static struct clk_rcg2 vsync_clk_src = { - .cmd_rcgr = 0x2080, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_5, - .freq_tbl = ftbl_dp_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "vsync_clk_src", - .parent_names = mmcc_parent_names_5, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static struct clk_branch mmss_bimc_smmu_ahb_clk = { - .halt_reg = 0xe004, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0xe004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_bimc_smmu_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .flags = CLK_ENABLE_HAND_OFF, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_bimc_smmu_axi_clk = { - .halt_reg = 0xe008, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0xe008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_bimc_smmu_axi_clk", - .flags = CLK_ENABLE_HAND_OFF, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_ahb_clk = { - .halt_reg = 0x348c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x348c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cci_ahb_clk = { - .halt_reg = 0x3348, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3348, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cci_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cci_clk = { - .halt_reg = 0x3344, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3344, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cci_clk", - .parent_names = (const char *[]){ - "cci_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cphy_csid0_clk = { - .halt_reg = 0x3730, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3730, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cphy_csid0_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cphy_csid1_clk = { - .halt_reg = 0x3734, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3734, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cphy_csid1_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cphy_csid2_clk = { - .halt_reg = 0x3738, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3738, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cphy_csid2_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cphy_csid3_clk = { - .halt_reg = 0x373c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x373c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cphy_csid3_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cpp_ahb_clk = { - .halt_reg = 0x36b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cpp_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cpp_axi_clk = { - .halt_reg = 0x36c4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36c4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cpp_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cpp_clk = { - .halt_reg = 0x36b0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36b0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cpp_clk", - .parent_names = (const char *[]){ - "cpp_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cpp_vbif_ahb_clk = { - .halt_reg = 0x36c8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36c8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cpp_vbif_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0_ahb_clk = { - .halt_reg = 0x30bc, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x30bc, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0_clk = { - .halt_reg = 0x30b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x30b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0phytimer_clk = { - .halt_reg = 0x3024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0phytimer_clk", - .parent_names = (const char *[]){ - "csi0phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0pix_clk = { - .halt_reg = 0x30e4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x30e4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0pix_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0rdi_clk = { - .halt_reg = 0x30d4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x30d4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0rdi_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1_ahb_clk = { - .halt_reg = 0x3128, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3128, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1_clk = { - .halt_reg = 0x3124, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3124, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1phytimer_clk = { - .halt_reg = 0x3054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1phytimer_clk", - .parent_names = (const char *[]){ - "csi1phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1pix_clk = { - .halt_reg = 0x3154, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3154, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1pix_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1rdi_clk = { - .halt_reg = 0x3144, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3144, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1rdi_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2_ahb_clk = { - .halt_reg = 0x3188, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3188, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2_clk = { - .halt_reg = 0x3184, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3184, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2phytimer_clk = { - .halt_reg = 0x3084, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3084, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2phytimer_clk", - .parent_names = (const char *[]){ - "csi2phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2pix_clk = { - .halt_reg = 0x31b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x31b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2pix_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2rdi_clk = { - .halt_reg = 0x31a4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x31a4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2rdi_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi3_ahb_clk = { - .halt_reg = 0x31e8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x31e8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi3_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi3_clk = { - .halt_reg = 0x31e4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x31e4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi3_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi3pix_clk = { - .halt_reg = 0x3214, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3214, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi3pix_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi3rdi_clk = { - .halt_reg = 0x3204, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3204, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi3rdi_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi_vfe0_clk = { - .halt_reg = 0x3704, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3704, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi_vfe0_clk", - .parent_names = (const char *[]){ - "vfe0_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi_vfe1_clk = { - .halt_reg = 0x3714, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3714, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi_vfe1_clk", - .parent_names = (const char *[]){ - "vfe1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csiphy0_clk = { - .halt_reg = 0x3740, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3740, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csiphy0_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csiphy1_clk = { - .halt_reg = 0x3744, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3744, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csiphy1_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csiphy2_clk = { - .halt_reg = 0x3748, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3748, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csiphy2_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_gp0_clk = { - .halt_reg = 0x3444, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3444, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_gp0_clk", - .parent_names = (const char *[]){ - "camss_gp0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_gp1_clk = { - .halt_reg = 0x3474, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3474, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_gp1_clk", - .parent_names = (const char *[]){ - "camss_gp1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_ispif_ahb_clk = { - .halt_reg = 0x3224, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3224, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_ispif_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_jpeg0_clk = { - .halt_reg = 0x35a8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x35a8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_jpeg0_clk", - .parent_names = (const char *[]){ - "jpeg0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static DEFINE_CLK_VOTER(mmss_camss_jpeg0_vote_clk, mmss_camss_jpeg0_clk, 0); -static DEFINE_CLK_VOTER(mmss_camss_jpeg0_dma_vote_clk, - mmss_camss_jpeg0_clk, 0); - -static struct clk_branch mmss_camss_jpeg_ahb_clk = { - .halt_reg = 0x35b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x35b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_jpeg_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_jpeg_axi_clk = { - .halt_reg = 0x35b8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x35b8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_jpeg_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_mclk0_clk = { - .halt_reg = 0x3384, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3384, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_mclk0_clk", - .parent_names = (const char *[]){ - "mclk0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_mclk1_clk = { - .halt_reg = 0x33b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_mclk1_clk", - .parent_names = (const char *[]){ - "mclk1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_mclk2_clk = { - .halt_reg = 0x33e4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33e4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_mclk2_clk", - .parent_names = (const char *[]){ - "mclk2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_mclk3_clk = { - .halt_reg = 0x3414, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3414, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_mclk3_clk", - .parent_names = (const char *[]){ - "mclk3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_micro_ahb_clk = { - .halt_reg = 0x3494, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3494, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_micro_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_top_ahb_clk = { - .halt_reg = 0x3484, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3484, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_top_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe0_ahb_clk = { - .halt_reg = 0x3668, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3668, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe0_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe0_clk = { - .halt_reg = 0x36a8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36a8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe0_clk", - .parent_names = (const char *[]){ - "vfe0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe0_stream_clk = { - .halt_reg = 0x3720, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3720, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe0_stream_clk", - .parent_names = (const char *[]){ - "vfe0_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe1_ahb_clk = { - .halt_reg = 0x3678, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3678, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe1_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe1_clk = { - .halt_reg = 0x36ac, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe1_clk", - .parent_names = (const char *[]){ - "vfe1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe1_stream_clk = { - .halt_reg = 0x3724, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3724, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe1_stream_clk", - .parent_names = (const char *[]){ - "vfe1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe_vbif_ahb_clk = { - .halt_reg = 0x36b8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36b8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe_vbif_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe_vbif_axi_clk = { - .halt_reg = 0x36bc, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36bc, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe_vbif_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_csiphy_ahb2crif_clk = { - .halt_reg = 0x374c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x374c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_csiphy_ahb2crif_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_ahb_clk = { - .halt_reg = 0x2308, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2308, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .flags = CLK_ENABLE_HAND_OFF, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_axi_clk = { - .halt_reg = 0x2310, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2310, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_byte0_clk = { - .halt_reg = 0x233c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x233c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte0_clk", - .parent_names = (const char *[]){ - "byte0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_byte0_intf_clk = { - .halt_reg = 0x2374, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2374, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte0_intf_clk", - .parent_names = (const char *[]){ - "mmss_mdss_byte0_intf_div_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_regmap_div mmss_mdss_byte0_intf_div_clk = { - .reg = 0x237c, - .shift = 0, - .width = 2, - /* - * NOTE: Op does not work for div-3. Current assumption is that div-3 - * is not a recommended setting for this divider. - */ - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte0_intf_div_clk", - .parent_names = (const char *[]){ - "byte0_clk_src", - }, - .num_parents = 1, - .ops = &clk_regmap_div_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - }, - }, -}; - -static struct clk_branch mmss_mdss_byte1_clk = { - .halt_reg = 0x2340, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2340, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte1_clk", - .parent_names = (const char *[]){ - "byte1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_byte1_intf_clk = { - .halt_reg = 0x2378, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2378, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte1_intf_clk", - .parent_names = (const char *[]){ - "byte1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_aux_clk = { - .halt_reg = 0x2364, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2364, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_aux_clk", - .parent_names = (const char *[]){ - "dp_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_crypto_clk = { - .halt_reg = 0x235c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x235c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_crypto_clk", - .parent_names = (const char *[]){ - "dp_crypto_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_gtc_clk = { - .halt_reg = 0x2368, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2368, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_gtc_clk", - .parent_names = (const char *[]){ - "dp_gtc_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_link_clk = { - .halt_reg = 0x2354, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2354, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_link_clk", - .parent_names = (const char *[]){ - "dp_link_clk_src", - }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Reset state of MMSS_MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */ -static struct clk_branch mmss_mdss_dp_link_intf_clk = { - .halt_reg = 0x2358, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2358, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_link_intf_clk", - .parent_names = (const char *[]){ - "dp_link_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_pixel_clk = { - .halt_reg = 0x2360, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2360, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_pixel_clk", - .parent_names = (const char *[]){ - "dp_pixel_clk_src", - }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_esc0_clk = { - .halt_reg = 0x2344, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2344, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_esc0_clk", - .parent_names = (const char *[]){ - "esc0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_esc1_clk = { - .halt_reg = 0x2348, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2348, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_esc1_clk", - .parent_names = (const char *[]){ - "esc1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_hdmi_dp_ahb_clk = { - .halt_reg = 0x230c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x230c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_hdmi_dp_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_mdp_clk = { - .halt_reg = 0x231c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x231c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_mdp_clk", - .parent_names = (const char *[]){ - "mdp_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_ENABLE_HAND_OFF, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_pclk0_clk = { - .halt_reg = 0x2314, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2314, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_pclk0_clk", - .parent_names = (const char *[]){ - "pclk0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_pclk1_clk = { - .halt_reg = 0x2318, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2318, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_pclk1_clk", - .parent_names = (const char *[]){ - "pclk1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_rot_clk = { - .halt_reg = 0x2350, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2350, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_rot_clk", - .parent_names = (const char *[]){ - "rot_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_vsync_clk = { - .halt_reg = 0x2328, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2328, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_vsync_clk", - .parent_names = (const char *[]){ - "vsync_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_misc_ahb_clk = { - .halt_reg = 0x328, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x328, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_misc_ahb_clk", - /* - * Dependency to be enabled before the branch is - * enabled. - */ - .parent_names = (const char *[]){ - "mmss_mnoc_ahb_clk", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_misc_cxo_clk = { - .halt_reg = 0x324, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x324, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_misc_cxo_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mnoc_ahb_clk = { - .halt_reg = 0x5024, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x5024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mnoc_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_snoc_dvm_axi_clk = { - .halt_reg = 0xe040, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xe040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_snoc_dvm_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_video_ahb_clk = { - .halt_reg = 0x1030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_video_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_video_axi_clk = { - .halt_reg = 0x1034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_video_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_video_core_clk = { - .halt_reg = 0x1028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_video_core_clk", - .parent_names = (const char *[]){ - "video_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_video_subcore0_clk = { - .halt_reg = 0x1048, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_video_subcore0_clk", - .parent_names = (const char *[]){ - "video_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_branch2_ops, - }, - }, -}; - -struct clk_hw *mmcc_msmfalcon_hws[] = { - [MMSS_CAMSS_JPEG0_VOTE_CLK] = &mmss_camss_jpeg0_vote_clk.hw, - [MMSS_CAMSS_JPEG0_DMA_VOTE_CLK] = &mmss_camss_jpeg0_dma_vote_clk.hw, -}; - -static struct clk_regmap *mmcc_falcon_clocks[] = { - [AHB_CLK_SRC] = &ahb_clk_src.clkr, - [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, - [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, - [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, - [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, - [CCI_CLK_SRC] = &cci_clk_src.clkr, - [CPP_CLK_SRC] = &cpp_clk_src.clkr, - [CSI0_CLK_SRC] = &csi0_clk_src.clkr, - [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, - [CSI1_CLK_SRC] = &csi1_clk_src.clkr, - [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, - [CSI2_CLK_SRC] = &csi2_clk_src.clkr, - [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, - [CSI3_CLK_SRC] = &csi3_clk_src.clkr, - [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr, - [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr, - [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr, - [DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr, - [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr, - [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr, - [ESC0_CLK_SRC] = &esc0_clk_src.clkr, - [ESC1_CLK_SRC] = &esc1_clk_src.clkr, - [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, - [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, - [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, - [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, - [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, - [MDP_CLK_SRC] = &mdp_clk_src.clkr, - [MMPLL0_PLL] = &mmpll0_pll_out_main.clkr, - [MMPLL10_PLL] = &mmpll10_pll_out_main.clkr, - [MMPLL3_PLL] = &mmpll3_pll_out_main.clkr, - [MMPLL4_PLL] = &mmpll4_pll_out_main.clkr, - [MMPLL5_PLL] = &mmpll5_pll_out_main.clkr, - [MMPLL6_PLL] = &mmpll6_pll_out_main.clkr, - [MMPLL7_PLL] = &mmpll7_pll_out_main.clkr, - [MMPLL8_PLL] = &mmpll8_pll_out_main.clkr, - [MMSS_BIMC_SMMU_AHB_CLK] = &mmss_bimc_smmu_ahb_clk.clkr, - [MMSS_BIMC_SMMU_AXI_CLK] = &mmss_bimc_smmu_axi_clk.clkr, - [MMSS_CAMSS_AHB_CLK] = &mmss_camss_ahb_clk.clkr, - [MMSS_CAMSS_CCI_AHB_CLK] = &mmss_camss_cci_ahb_clk.clkr, - [MMSS_CAMSS_CCI_CLK] = &mmss_camss_cci_clk.clkr, - [MMSS_CAMSS_CPHY_CSID0_CLK] = &mmss_camss_cphy_csid0_clk.clkr, - [MMSS_CAMSS_CPHY_CSID1_CLK] = &mmss_camss_cphy_csid1_clk.clkr, - [MMSS_CAMSS_CPHY_CSID2_CLK] = &mmss_camss_cphy_csid2_clk.clkr, - [MMSS_CAMSS_CPHY_CSID3_CLK] = &mmss_camss_cphy_csid3_clk.clkr, - [MMSS_CAMSS_CPP_AHB_CLK] = &mmss_camss_cpp_ahb_clk.clkr, - [MMSS_CAMSS_CPP_AXI_CLK] = &mmss_camss_cpp_axi_clk.clkr, - [MMSS_CAMSS_CPP_CLK] = &mmss_camss_cpp_clk.clkr, - [MMSS_CAMSS_CPP_VBIF_AHB_CLK] = &mmss_camss_cpp_vbif_ahb_clk.clkr, - [MMSS_CAMSS_CSI0_AHB_CLK] = &mmss_camss_csi0_ahb_clk.clkr, - [MMSS_CAMSS_CSI0_CLK] = &mmss_camss_csi0_clk.clkr, - [MMSS_CAMSS_CSI0PHYTIMER_CLK] = &mmss_camss_csi0phytimer_clk.clkr, - [MMSS_CAMSS_CSI0PIX_CLK] = &mmss_camss_csi0pix_clk.clkr, - [MMSS_CAMSS_CSI0RDI_CLK] = &mmss_camss_csi0rdi_clk.clkr, - [MMSS_CAMSS_CSI1_AHB_CLK] = &mmss_camss_csi1_ahb_clk.clkr, - [MMSS_CAMSS_CSI1_CLK] = &mmss_camss_csi1_clk.clkr, - [MMSS_CAMSS_CSI1PHYTIMER_CLK] = &mmss_camss_csi1phytimer_clk.clkr, - [MMSS_CAMSS_CSI1PIX_CLK] = &mmss_camss_csi1pix_clk.clkr, - [MMSS_CAMSS_CSI1RDI_CLK] = &mmss_camss_csi1rdi_clk.clkr, - [MMSS_CAMSS_CSI2_AHB_CLK] = &mmss_camss_csi2_ahb_clk.clkr, - [MMSS_CAMSS_CSI2_CLK] = &mmss_camss_csi2_clk.clkr, - [MMSS_CAMSS_CSI2PHYTIMER_CLK] = &mmss_camss_csi2phytimer_clk.clkr, - [MMSS_CAMSS_CSI2PIX_CLK] = &mmss_camss_csi2pix_clk.clkr, - [MMSS_CAMSS_CSI2RDI_CLK] = &mmss_camss_csi2rdi_clk.clkr, - [MMSS_CAMSS_CSI3_AHB_CLK] = &mmss_camss_csi3_ahb_clk.clkr, - [MMSS_CAMSS_CSI3_CLK] = &mmss_camss_csi3_clk.clkr, - [MMSS_CAMSS_CSI3PIX_CLK] = &mmss_camss_csi3pix_clk.clkr, - [MMSS_CAMSS_CSI3RDI_CLK] = &mmss_camss_csi3rdi_clk.clkr, - [MMSS_CAMSS_CSI_VFE0_CLK] = &mmss_camss_csi_vfe0_clk.clkr, - [MMSS_CAMSS_CSI_VFE1_CLK] = &mmss_camss_csi_vfe1_clk.clkr, - [MMSS_CAMSS_CSIPHY0_CLK] = &mmss_camss_csiphy0_clk.clkr, - [MMSS_CAMSS_CSIPHY1_CLK] = &mmss_camss_csiphy1_clk.clkr, - [MMSS_CAMSS_CSIPHY2_CLK] = &mmss_camss_csiphy2_clk.clkr, - [MMSS_CAMSS_GP0_CLK] = &mmss_camss_gp0_clk.clkr, - [MMSS_CAMSS_GP1_CLK] = &mmss_camss_gp1_clk.clkr, - [MMSS_CAMSS_ISPIF_AHB_CLK] = &mmss_camss_ispif_ahb_clk.clkr, - [MMSS_CAMSS_JPEG0_CLK] = &mmss_camss_jpeg0_clk.clkr, - [MMSS_CAMSS_JPEG_AHB_CLK] = &mmss_camss_jpeg_ahb_clk.clkr, - [MMSS_CAMSS_JPEG_AXI_CLK] = &mmss_camss_jpeg_axi_clk.clkr, - [MMSS_CAMSS_MCLK0_CLK] = &mmss_camss_mclk0_clk.clkr, - [MMSS_CAMSS_MCLK1_CLK] = &mmss_camss_mclk1_clk.clkr, - [MMSS_CAMSS_MCLK2_CLK] = &mmss_camss_mclk2_clk.clkr, - [MMSS_CAMSS_MCLK3_CLK] = &mmss_camss_mclk3_clk.clkr, - [MMSS_CAMSS_MICRO_AHB_CLK] = &mmss_camss_micro_ahb_clk.clkr, - [MMSS_CAMSS_TOP_AHB_CLK] = &mmss_camss_top_ahb_clk.clkr, - [MMSS_CAMSS_VFE0_AHB_CLK] = &mmss_camss_vfe0_ahb_clk.clkr, - [MMSS_CAMSS_VFE0_CLK] = &mmss_camss_vfe0_clk.clkr, - [MMSS_CAMSS_VFE0_STREAM_CLK] = &mmss_camss_vfe0_stream_clk.clkr, - [MMSS_CAMSS_VFE1_AHB_CLK] = &mmss_camss_vfe1_ahb_clk.clkr, - [MMSS_CAMSS_VFE1_CLK] = &mmss_camss_vfe1_clk.clkr, - [MMSS_CAMSS_VFE1_STREAM_CLK] = &mmss_camss_vfe1_stream_clk.clkr, - [MMSS_CAMSS_VFE_VBIF_AHB_CLK] = &mmss_camss_vfe_vbif_ahb_clk.clkr, - [MMSS_CAMSS_VFE_VBIF_AXI_CLK] = &mmss_camss_vfe_vbif_axi_clk.clkr, - [MMSS_CSIPHY_AHB2CRIF_CLK] = &mmss_csiphy_ahb2crif_clk.clkr, - [MMSS_MDSS_AHB_CLK] = &mmss_mdss_ahb_clk.clkr, - [MMSS_MDSS_AXI_CLK] = &mmss_mdss_axi_clk.clkr, - [MMSS_MDSS_BYTE0_CLK] = &mmss_mdss_byte0_clk.clkr, - [MMSS_MDSS_BYTE0_INTF_CLK] = &mmss_mdss_byte0_intf_clk.clkr, - [MMSS_MDSS_BYTE0_INTF_DIV_CLK] = &mmss_mdss_byte0_intf_div_clk.clkr, - [MMSS_MDSS_BYTE1_CLK] = &mmss_mdss_byte1_clk.clkr, - [MMSS_MDSS_BYTE1_INTF_CLK] = &mmss_mdss_byte1_intf_clk.clkr, - [MMSS_MDSS_DP_AUX_CLK] = &mmss_mdss_dp_aux_clk.clkr, - [MMSS_MDSS_DP_CRYPTO_CLK] = &mmss_mdss_dp_crypto_clk.clkr, - [MMSS_MDSS_DP_GTC_CLK] = &mmss_mdss_dp_gtc_clk.clkr, - [MMSS_MDSS_DP_LINK_CLK] = &mmss_mdss_dp_link_clk.clkr, - [MMSS_MDSS_DP_LINK_INTF_CLK] = &mmss_mdss_dp_link_intf_clk.clkr, - [MMSS_MDSS_DP_PIXEL_CLK] = &mmss_mdss_dp_pixel_clk.clkr, - [MMSS_MDSS_ESC0_CLK] = &mmss_mdss_esc0_clk.clkr, - [MMSS_MDSS_ESC1_CLK] = &mmss_mdss_esc1_clk.clkr, - [MMSS_MDSS_HDMI_DP_AHB_CLK] = &mmss_mdss_hdmi_dp_ahb_clk.clkr, - [MMSS_MDSS_MDP_CLK] = &mmss_mdss_mdp_clk.clkr, - [MMSS_MDSS_PCLK0_CLK] = &mmss_mdss_pclk0_clk.clkr, - [MMSS_MDSS_PCLK1_CLK] = &mmss_mdss_pclk1_clk.clkr, - [MMSS_MDSS_ROT_CLK] = &mmss_mdss_rot_clk.clkr, - [MMSS_MDSS_VSYNC_CLK] = &mmss_mdss_vsync_clk.clkr, - [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, - [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, - [MMSS_MNOC_AHB_CLK] = &mmss_mnoc_ahb_clk.clkr, - [MMSS_SNOC_DVM_AXI_CLK] = &mmss_snoc_dvm_axi_clk.clkr, - [MMSS_VIDEO_AHB_CLK] = &mmss_video_ahb_clk.clkr, - [MMSS_VIDEO_AXI_CLK] = &mmss_video_axi_clk.clkr, - [MMSS_VIDEO_CORE_CLK] = &mmss_video_core_clk.clkr, - [MMSS_VIDEO_SUBCORE0_CLK] = &mmss_video_subcore0_clk.clkr, - [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, - [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, - [ROT_CLK_SRC] = &rot_clk_src.clkr, - [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, - [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, - [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, - [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, -}; - -static const struct qcom_reset_map mmcc_falcon_resets[] = { - [CAMSS_MICRO_BCR] = { 0x3490 }, -}; - -static const struct regmap_config mmcc_falcon_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x10004, - .fast_io = true, -}; - -static const struct qcom_cc_desc mmcc_falcon_desc = { - .config = &mmcc_falcon_regmap_config, - .clks = mmcc_falcon_clocks, - .num_clks = ARRAY_SIZE(mmcc_falcon_clocks), - .hwclks = mmcc_msmfalcon_hws, - .num_hwclks = ARRAY_SIZE(mmcc_msmfalcon_hws), - .resets = mmcc_falcon_resets, - .num_resets = ARRAY_SIZE(mmcc_falcon_resets), -}; - -static const struct of_device_id mmcc_falcon_match_table[] = { - { .compatible = "qcom,mmcc-msmfalcon" }, - { } -}; -MODULE_DEVICE_TABLE(of, mmcc_falcon_match_table); - -static int mmcc_falcon_probe(struct platform_device *pdev) -{ - int ret = 0; - struct regmap *regmap; - - regmap = qcom_cc_map(pdev, &mmcc_falcon_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* PLLs connected on Mx rails of MMSS_CC */ - vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_mmss"); - if (IS_ERR(vdd_mx.regulator[0])) { - if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_mx_mmss regulator\n"); - return PTR_ERR(vdd_mx.regulator[0]); - } - - vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_mmss"); - if (IS_ERR(vdd_dig.regulator[0])) { - if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_dig regulator\n"); - return PTR_ERR(vdd_dig.regulator[0]); - } - - /* MMPLL10 connected to the Analog Rail */ - vdda.regulator[0] = devm_regulator_get(&pdev->dev, "vdda"); - if (IS_ERR(vdda.regulator[0])) { - if (!(PTR_ERR(vdda.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdda regulator\n"); - return PTR_ERR(vdda.regulator[0]); - } - - clk_alpha_pll_configure(&mmpll3_pll_out_main, regmap, &mmpll3_config); - clk_alpha_pll_configure(&mmpll4_pll_out_main, regmap, &mmpll4_config); - clk_alpha_pll_configure(&mmpll5_pll_out_main, regmap, &mmpll5_config); - clk_alpha_pll_configure(&mmpll7_pll_out_main, regmap, &mmpll7_config); - clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config); - clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config); - - ret = qcom_cc_really_probe(pdev, &mmcc_falcon_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register MMSS clocks\n"); - return ret; - } - - dev_info(&pdev->dev, "Registered MMSS clocks\n"); - - return ret; -} - -static struct platform_driver mmcc_falcon_driver = { - .probe = mmcc_falcon_probe, - .driver = { - .name = "mmcc-msmfalcon", - .of_match_table = mmcc_falcon_match_table, - }, -}; - -static int __init mmcc_falcon_init(void) -{ - return platform_driver_register(&mmcc_falcon_driver); -} -core_initcall_sync(mmcc_falcon_init); - -static void __exit mmcc_falcon_exit(void) -{ - platform_driver_unregister(&mmcc_falcon_driver); -} -module_exit(mmcc_falcon_exit); diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c new file mode 100644 index 000000000000..daece455454c --- /dev/null +++ b/drivers/clk/qcom/mmcc-sdm660.c @@ -0,0 +1,3056 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "common.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-voter.h" +#include "reset.h" +#include "vdd-level-660.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } +#define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \ + (src_freq) } + +enum vdd_a_levels { + VDDA_NONE, + VDDA_LOWER, /* SVS2 */ + VDDA_NUM, +}; + +static int vdda_levels[] = { + 0, + 1800000, +}; + +#define VDDA_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdda, \ + .rate_max = (unsigned long[VDDA_NUM]) { \ + [VDDA_##l1] = (f1), \ + }, \ + .num_rate_max = VDDA_NUM + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdda, VDDA_NUM, 1, vdda_levels); + +enum { + P_CORE_BI_PLL_TEST_SE, + P_CORE_PI_SLEEP_CLK, + P_CXO, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_MMPLL0_PLL_OUT_MAIN, + P_MMPLL10_PLL_OUT_MAIN, + P_MMPLL3_PLL_OUT_MAIN, + P_MMPLL4_PLL_OUT_MAIN, + P_MMPLL5_PLL_OUT_MAIN, + P_MMPLL6_PLL_OUT_MAIN, + P_MMPLL7_PLL_OUT_MAIN, + P_MMPLL8_PLL_OUT_MAIN, +}; + +static const struct parent_map mmcc_parent_map_0[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL8_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_0[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll8_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_1[] = { + { P_CXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_1[] = { + "xo", + "dsi0pll_byte_clk_mux", + "dsi1pll_byte_clk_mux", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_2[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL10_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_2[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_3[] = { + { P_CXO, 0 }, + { P_MMPLL4_PLL_OUT_MAIN, 1 }, + { P_MMPLL7_PLL_OUT_MAIN, 2 }, + { P_MMPLL10_PLL_OUT_MAIN, 3 }, + { P_CORE_PI_SLEEP_CLK, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_3[] = { + "xo", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "core_pi_sleep_clk", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_4[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL7_PLL_OUT_MAIN, 2 }, + { P_MMPLL10_PLL_OUT_MAIN, 3 }, + { P_CORE_PI_SLEEP_CLK, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_4[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "core_pi_sleep_clk", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_5[] = { + { P_CXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_5[] = { + "xo", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_6[] = { + { P_CXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_6[] = { + "xo", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_7[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL5_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_7[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll5_pll_out_main", + "mmpll7_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_8[] = { + { P_CXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_8[] = { + "xo", + "dsi0pll_pixel_clk_mux", + "dsi1pll_pixel_clk_mux", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_9[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL10_PLL_OUT_MAIN, 4 }, + { P_MMPLL6_PLL_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_9[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "mmpll6_pll_out_main", + "gcc_mmss_gpll0_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_10[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_10[] = { + "xo", + "mmpll0_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_11[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL10_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_MMPLL6_PLL_OUT_MAIN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_11[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "gcc_mmss_gpll0_clk", + "mmpll6_pll_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_12[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL8_PLL_OUT_MAIN, 2 }, + { P_MMPLL3_PLL_OUT_MAIN, 3 }, + { P_MMPLL6_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_MMPLL7_PLL_OUT_MAIN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_12[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll8_pll_out_main", + "mmpll3_pll_out_main", + "mmpll6_pll_out_main", + "gcc_mmss_gpll0_clk", + "mmpll7_pll_out_main", + "core_bi_pll_test_se", +}; + +/* Voteable PLL */ +static struct clk_alpha_pll mmpll0_pll_out_main = { + .offset = 0xc000, + .clkr = { + .enable_reg = 0x1f0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmpll0_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 404000000, + LOW, 808000000), + }, + }, +}; + +static struct clk_alpha_pll mmpll6_pll_out_main = { + .offset = 0xf0, + .clkr = { + .enable_reg = 0x1f0, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "mmpll6_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 540000000, + LOW_L1, 1080000000), + }, + }, +}; + +/* APSS controlled PLLs */ +static struct pll_vco vco[] = { + { 1000000000, 2000000000, 0 }, + { 750000000, 1500000000, 1 }, + { 500000000, 1000000000, 2 }, + { 250000000, 500000000, 3 }, +}; + +static const struct pll_config mmpll10_config = { + .l = 0x1e, + .config_ctl_val = 0x00004289, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll10_pll_out_main = { + .offset = 0x190, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll10_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDDA_FMAX_MAP1(LOWER, 576000000), + }, + }, +}; + +static struct pll_vco mmpll3_vco[] = { + { 750000000, 1500000000, 1 }, +}; + +static const struct pll_config mmpll3_config = { + .l = 0x2e, + .config_ctl_val = 0x4001055b, + .vco_val = 0x1 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll3_pll_out_main = { + .offset = 0x0, + .vco_table = mmpll3_vco, + .num_vco = ARRAY_SIZE(mmpll3_vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll3_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_slew_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 441600000, + NOMINAL, 1036800000), + }, + }, +}; + +static const struct pll_config mmpll4_config = { + .l = 0x28, + .config_ctl_val = 0x4001055b, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll4_pll_out_main = { + .offset = 0x50, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll4_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 384000000, + LOW, 768000000), + }, + }, +}; + +static const struct pll_config mmpll5_config = { + .l = 0x2a, + .config_ctl_val = 0x4001055b, + .alpha_u = 0xf8, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll5_pll_out_main = { + .offset = 0xa0, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll5_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 421500000, + LOW, 825000000), + }, + }, +}; + +static const struct pll_config mmpll7_config = { + .l = 0x32, + .config_ctl_val = 0x4001055b, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll7_pll_out_main = { + .offset = 0x140, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll7_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 480000000, + LOW, 960000000), + }, + }, +}; + +static const struct pll_config mmpll8_config = { + .l = 0x30, + .alpha_u = 0x70, + .alpha_en_mask = BIT(24), + .config_ctl_val = 0x4001055b, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll8_pll_out_main = { + .offset = 0x1c0, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll8_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 465000000, + LOW, 930000000), + }, + }, +}; + +static const struct freq_tbl ftbl_ahb_clk_src[] = { + F(19200000, P_CXO, 1, 0, 0), + F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), + F(80800000, P_MMPLL0_PLL_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 ahb_clk_src = { + .cmd_rcgr = 0x5000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_10, + .freq_tbl = ftbl_ahb_clk_src, + .flags = FORCE_ENABLE_RCGR, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ahb_clk_src", + .parent_names = mmcc_parent_names_10, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 40000000, + NOMINAL, 80800000), + }, +}; + +static struct clk_rcg2 byte0_clk_src = { + .cmd_rcgr = 0x2120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "byte0_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_byte2_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 131250000, + LOW, 210000000, + NOMINAL, 262500000), + }, +}; + +static struct clk_rcg2 byte1_clk_src = { + .cmd_rcgr = 0x2140, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "byte1_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_byte2_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 131250000, + LOW, 210000000, + NOMINAL, 262500000), + }, +}; + +static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { + F(10000, P_CXO, 16, 1, 120), + F(24000, P_CXO, 16, 1, 50), + F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), + F(12000000, P_GPLL0_OUT_MAIN_DIV, 10, 2, 5), + F(13043478, P_GPLL0_OUT_MAIN_DIV, 1, 1, 23), + F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), + F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 camss_gp0_clk_src = { + .cmd_rcgr = 0x3420, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_4, + .freq_tbl = ftbl_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "camss_gp0_clk_src", + .parent_names = mmcc_parent_names_4, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static struct clk_rcg2 camss_gp1_clk_src = { + .cmd_rcgr = 0x3450, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_4, + .freq_tbl = ftbl_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "camss_gp1_clk_src", + .parent_names = mmcc_parent_names_4, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static const struct freq_tbl ftbl_cci_clk_src[] = { + F(37500000, P_GPLL0_OUT_MAIN_DIV, 8, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 cci_clk_src = { + .cmd_rcgr = 0x3300, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_4, + .freq_tbl = ftbl_cci_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cci_clk_src", + .parent_names = mmcc_parent_names_4, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 37500000, + LOW, 50000000, + NOMINAL, 100000000), + }, +}; + +static const struct freq_tbl ftbl_cpp_clk_src[] = { + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), + F(384000000, P_MMPLL4_PLL_OUT_MAIN, 2, 0, 0), + F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), + F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), + F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cpp_clk_src = { + .cmd_rcgr = 0x3640, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_11, + .freq_tbl = ftbl_cpp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cpp_clk_src", + .parent_names = mmcc_parent_names_11, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 120000000, + LOW, 256000000, + LOW_L1, 384000000, + NOMINAL, 480000000, + NOMINAL_L1, 540000000, + HIGH, 576000000), + }, +}; + +static const struct freq_tbl ftbl_csi0_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(310000000, P_MMPLL8_PLL_OUT_MAIN, 3, 0, 0), + F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), + F(465000000, P_MMPLL8_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 csi0_clk_src = { + .cmd_rcgr = 0x3090, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi0_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 csi0phytimer_clk_src = { + .cmd_rcgr = 0x3000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi0phytimer_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333), + }, +}; + +static struct clk_rcg2 csi1_clk_src = { + .cmd_rcgr = 0x3100, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi1_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static struct clk_rcg2 csi1phytimer_clk_src = { + .cmd_rcgr = 0x3030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi1phytimer_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333), + }, +}; + +static struct clk_rcg2 csi2_clk_src = { + .cmd_rcgr = 0x3160, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi2_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static struct clk_rcg2 csi2phytimer_clk_src = { + .cmd_rcgr = 0x3060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi2phytimer_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333), + }, +}; + +static struct clk_rcg2 csi3_clk_src = { + .cmd_rcgr = 0x31c0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi3_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static const struct freq_tbl ftbl_csiphy_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), + F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 csiphy_clk_src = { + .cmd_rcgr = 0x3800, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csiphy_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csiphy_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333, + NOMINAL, 320000000), + }, +}; + +static const struct freq_tbl ftbl_dp_aux_clk_src[] = { + F(19200000, P_CXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 dp_aux_clk_src = { + .cmd_rcgr = 0x2260, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_5, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_aux_clk_src", + .parent_names = mmcc_parent_names_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static const struct freq_tbl ftbl_dp_crypto_clk_src[] = { + F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), + F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), + F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), + { } +}; + +static struct clk_rcg2 dp_crypto_clk_src = { + .cmd_rcgr = 0x2220, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_6, + .freq_tbl = ftbl_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_crypto_clk_src", + .parent_names = mmcc_parent_names_6, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 101250000, + LOW, 168750000, + NOMINAL, 337500000), + }, +}; + +static const struct freq_tbl ftbl_dp_gtc_clk_src[] = { + F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 dp_gtc_clk_src = { + .cmd_rcgr = 0x2280, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_5, + .freq_tbl = ftbl_dp_gtc_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_gtc_clk_src", + .parent_names = mmcc_parent_names_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 40000000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_dp_link_clk_src[] = { + F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), + F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), + F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dp_link_clk_src = { + .cmd_rcgr = 0x2200, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_6, + .freq_tbl = ftbl_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_link_clk_src", + .parent_names = mmcc_parent_names_6, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + VDD_DIG_FMAX_MAP3( + LOWER, 162000000, + LOW, 270000000, + NOMINAL, 540000000), + }, +}; + +static struct clk_rcg2 dp_pixel_clk_src = { + .cmd_rcgr = 0x2240, + .mnd_width = 16, + .hid_width = 5, + .parent_map = mmcc_parent_map_6, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_pixel_clk_src", + .parent_names = mmcc_parent_names_6, + .num_parents = 4, + .ops = &clk_dp_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 148380000, + LOW, 296740000, + NOMINAL, 593470000), + }, +}; + +static struct clk_rcg2 esc0_clk_src = { + .cmd_rcgr = 0x2160, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "esc0_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static struct clk_rcg2 esc1_clk_src = { + .cmd_rcgr = 0x2180, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "esc1_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static const struct freq_tbl ftbl_jpeg0_clk_src[] = { + F(66666667, P_GPLL0_OUT_MAIN_DIV, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(219428571, P_MMPLL4_PLL_OUT_MAIN, 3.5, 0, 0), + F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), + F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 jpeg0_clk_src = { + .cmd_rcgr = 0x3500, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_jpeg0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "jpeg0_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 66666667, + LOW, 133333333, + LOW_L1, 219428571, + NOMINAL, 320000000, + NOMINAL_L1, 480000000), + }, +}; + +static const struct freq_tbl ftbl_mclk0_clk_src[] = { + F(4800000, P_CXO, 4, 0, 0), + F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), + F(8000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 75), + F(9600000, P_CXO, 2, 0, 0), + F(16666667, P_GPLL0_OUT_MAIN_DIV, 2, 1, 9), + F(19200000, P_CXO, 1, 0, 0), + F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), + F(33333333, P_GPLL0_OUT_MAIN_DIV, 1, 1, 9), + F(48000000, P_GPLL0_OUT_MAIN, 1, 2, 25), + F(66666667, P_GPLL0_OUT_MAIN, 1, 1, 9), + { } +}; + +static struct clk_rcg2 mclk0_clk_src = { + .cmd_rcgr = 0x3360, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk0_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static struct clk_rcg2 mclk1_clk_src = { + .cmd_rcgr = 0x3390, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk1_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static struct clk_rcg2 mclk2_clk_src = { + .cmd_rcgr = 0x33c0, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk2_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static struct clk_rcg2 mclk3_clk_src = { + .cmd_rcgr = 0x33f0, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk3_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static const struct freq_tbl ftbl_mdp_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), + F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 mdp_clk_src = { + .cmd_rcgr = 0x2040, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_7, + .freq_tbl = ftbl_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mdp_clk_src", + .parent_names = mmcc_parent_names_7, + .num_parents = 7, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 171428571, + LOW, 275000000, + LOW_L1, 300000000, + NOMINAL, 330000000, + HIGH, 412500000), + }, +}; + +static struct clk_rcg2 pclk0_clk_src = { + .cmd_rcgr = 0x2000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_8, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pclk0_clk_src", + .parent_names = mmcc_parent_names_8, + .num_parents = 4, + .ops = &clk_pixel_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 175000000, + LOW, 280000000, + NOMINAL, 350000000), + }, +}; + +static struct clk_rcg2 pclk1_clk_src = { + .cmd_rcgr = 0x2020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_8, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pclk1_clk_src", + .parent_names = mmcc_parent_names_8, + .num_parents = 4, + .ops = &clk_pixel_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 175000000, + LOW, 280000000, + NOMINAL, 350000000), + }, +}; + +static const struct freq_tbl ftbl_rot_clk_src[] = { + F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), + F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), + F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 rot_clk_src = { + .cmd_rcgr = 0x21a0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_7, + .freq_tbl = ftbl_rot_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rot_clk_src", + .parent_names = mmcc_parent_names_7, + .num_parents = 7, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 171428571, + LOW, 275000000, + LOW_L1, 300000000, + NOMINAL, 330000000, + HIGH, 412500000), + }, +}; + +static const struct freq_tbl ftbl_vfe0_clk_src[] = { + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), + F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), + F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), + F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 vfe0_clk_src = { + .cmd_rcgr = 0x3600, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_9, + .freq_tbl = ftbl_vfe0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vfe0_clk_src", + .parent_names = mmcc_parent_names_9, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 120000000, + LOW, 256000000, + LOW_L1, 404000000, + NOMINAL, 480000000, + NOMINAL_L1, 540000000, + HIGH, 576000000), + }, +}; + +static struct clk_rcg2 vfe1_clk_src = { + .cmd_rcgr = 0x3620, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_9, + .freq_tbl = ftbl_vfe0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vfe1_clk_src", + .parent_names = mmcc_parent_names_9, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 120000000, + LOW, 256000000, + LOW_L1, 404000000, + NOMINAL, 480000000, + NOMINAL_L1, 540000000, + HIGH, 576000000), + }, +}; + +static const struct freq_tbl ftbl_video_core_clk_src[] = { + F_SLEW(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0, FIXED_FREQ_SRC), + F_SLEW(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), + F_SLEW(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), + F_SLEW(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0, FIXED_FREQ_SRC), + F_SLEW(441600000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 883200000), + F_SLEW(518400000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 1036800000), + { } +}; + +static struct clk_rcg2 video_core_clk_src = { + .cmd_rcgr = 0x1000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_12, + .freq_tbl = ftbl_video_core_clk_src, + .flags = FORCE_ENABLE_RCGR, + .clkr.hw.init = &(struct clk_init_data){ + .name = "video_core_clk_src", + .parent_names = mmcc_parent_names_12, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 133333333, + LOW, 269333333, + LOW_L1, 320000000, + NOMINAL, 404000000, + NOMINAL_L1, 441600000, + HIGH, 518400000), + }, +}; + +static struct clk_rcg2 vsync_clk_src = { + .cmd_rcgr = 0x2080, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_5, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vsync_clk_src", + .parent_names = mmcc_parent_names_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static struct clk_branch mmss_bimc_smmu_ahb_clk = { + .halt_reg = 0xe004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0xe004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_bimc_smmu_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .flags = CLK_ENABLE_HAND_OFF, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_bimc_smmu_axi_clk = { + .halt_reg = 0xe008, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0xe008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_bimc_smmu_axi_clk", + .flags = CLK_ENABLE_HAND_OFF, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_ahb_clk = { + .halt_reg = 0x348c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x348c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cci_ahb_clk = { + .halt_reg = 0x3348, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3348, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cci_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cci_clk = { + .halt_reg = 0x3344, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3344, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cci_clk", + .parent_names = (const char *[]){ + "cci_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid0_clk = { + .halt_reg = 0x3730, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3730, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid0_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid1_clk = { + .halt_reg = 0x3734, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3734, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid1_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid2_clk = { + .halt_reg = 0x3738, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3738, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid2_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid3_clk = { + .halt_reg = 0x373c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x373c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid3_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_ahb_clk = { + .halt_reg = 0x36b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_axi_clk = { + .halt_reg = 0x36c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36c4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_clk = { + .halt_reg = 0x36b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36b0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_clk", + .parent_names = (const char *[]){ + "cpp_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_vbif_ahb_clk = { + .halt_reg = 0x36c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36c8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_vbif_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0_ahb_clk = { + .halt_reg = 0x30bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0_clk = { + .halt_reg = 0x30b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0_clk", + .parent_names = (const char *[]){ + "csi0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0phytimer_clk = { + .halt_reg = 0x3024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0phytimer_clk", + .parent_names = (const char *[]){ + "csi0phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0pix_clk = { + .halt_reg = 0x30e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30e4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0pix_clk", + .parent_names = (const char *[]){ + "csi0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0rdi_clk = { + .halt_reg = 0x30d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30d4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0rdi_clk", + .parent_names = (const char *[]){ + "csi0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1_ahb_clk = { + .halt_reg = 0x3128, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3128, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1_clk = { + .halt_reg = 0x3124, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3124, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1_clk", + .parent_names = (const char *[]){ + "csi1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1phytimer_clk = { + .halt_reg = 0x3054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1phytimer_clk", + .parent_names = (const char *[]){ + "csi1phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1pix_clk = { + .halt_reg = 0x3154, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3154, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1pix_clk", + .parent_names = (const char *[]){ + "csi1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1rdi_clk = { + .halt_reg = 0x3144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3144, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1rdi_clk", + .parent_names = (const char *[]){ + "csi1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2_ahb_clk = { + .halt_reg = 0x3188, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3188, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2_clk = { + .halt_reg = 0x3184, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3184, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2_clk", + .parent_names = (const char *[]){ + "csi2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2phytimer_clk = { + .halt_reg = 0x3084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2phytimer_clk", + .parent_names = (const char *[]){ + "csi2phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2pix_clk = { + .halt_reg = 0x31b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2pix_clk", + .parent_names = (const char *[]){ + "csi2_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2rdi_clk = { + .halt_reg = 0x31a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2rdi_clk", + .parent_names = (const char *[]){ + "csi2_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3_ahb_clk = { + .halt_reg = 0x31e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31e8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3_clk = { + .halt_reg = 0x31e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31e4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3_clk", + .parent_names = (const char *[]){ + "csi3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3pix_clk = { + .halt_reg = 0x3214, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3214, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3pix_clk", + .parent_names = (const char *[]){ + "csi3_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3rdi_clk = { + .halt_reg = 0x3204, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3204, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3rdi_clk", + .parent_names = (const char *[]){ + "csi3_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi_vfe0_clk = { + .halt_reg = 0x3704, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3704, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi_vfe0_clk", + .parent_names = (const char *[]){ + "vfe0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi_vfe1_clk = { + .halt_reg = 0x3714, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3714, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi_vfe1_clk", + .parent_names = (const char *[]){ + "vfe1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csiphy0_clk = { + .halt_reg = 0x3740, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3740, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csiphy0_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csiphy1_clk = { + .halt_reg = 0x3744, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3744, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csiphy1_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csiphy2_clk = { + .halt_reg = 0x3748, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3748, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csiphy2_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_gp0_clk = { + .halt_reg = 0x3444, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3444, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_gp0_clk", + .parent_names = (const char *[]){ + "camss_gp0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_gp1_clk = { + .halt_reg = 0x3474, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3474, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_gp1_clk", + .parent_names = (const char *[]){ + "camss_gp1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_ispif_ahb_clk = { + .halt_reg = 0x3224, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3224, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_ispif_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_jpeg0_clk = { + .halt_reg = 0x35a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x35a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_jpeg0_clk", + .parent_names = (const char *[]){ + "jpeg0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static DEFINE_CLK_VOTER(mmss_camss_jpeg0_vote_clk, mmss_camss_jpeg0_clk, 0); +static DEFINE_CLK_VOTER(mmss_camss_jpeg0_dma_vote_clk, + mmss_camss_jpeg0_clk, 0); + +static struct clk_branch mmss_camss_jpeg_ahb_clk = { + .halt_reg = 0x35b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x35b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_jpeg_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_jpeg_axi_clk = { + .halt_reg = 0x35b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x35b8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_jpeg_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk0_clk = { + .halt_reg = 0x3384, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3384, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk0_clk", + .parent_names = (const char *[]){ + "mclk0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk1_clk = { + .halt_reg = 0x33b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk1_clk", + .parent_names = (const char *[]){ + "mclk1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk2_clk = { + .halt_reg = 0x33e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33e4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk2_clk", + .parent_names = (const char *[]){ + "mclk2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk3_clk = { + .halt_reg = 0x3414, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3414, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk3_clk", + .parent_names = (const char *[]){ + "mclk3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_micro_ahb_clk = { + .halt_reg = 0x3494, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3494, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_micro_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_top_ahb_clk = { + .halt_reg = 0x3484, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3484, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_top_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe0_ahb_clk = { + .halt_reg = 0x3668, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3668, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe0_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe0_clk = { + .halt_reg = 0x36a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe0_clk", + .parent_names = (const char *[]){ + "vfe0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe0_stream_clk = { + .halt_reg = 0x3720, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3720, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe0_stream_clk", + .parent_names = (const char *[]){ + "vfe0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe1_ahb_clk = { + .halt_reg = 0x3678, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3678, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe1_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe1_clk = { + .halt_reg = 0x36ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36ac, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe1_clk", + .parent_names = (const char *[]){ + "vfe1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe1_stream_clk = { + .halt_reg = 0x3724, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3724, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe1_stream_clk", + .parent_names = (const char *[]){ + "vfe1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe_vbif_ahb_clk = { + .halt_reg = 0x36b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36b8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe_vbif_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe_vbif_axi_clk = { + .halt_reg = 0x36bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe_vbif_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_csiphy_ahb2crif_clk = { + .halt_reg = 0x374c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x374c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_csiphy_ahb2crif_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_ahb_clk = { + .halt_reg = 0x2308, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2308, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .flags = CLK_ENABLE_HAND_OFF, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_axi_clk = { + .halt_reg = 0x2310, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte0_clk = { + .halt_reg = 0x233c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x233c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte0_clk", + .parent_names = (const char *[]){ + "byte0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte0_intf_clk = { + .halt_reg = 0x2374, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2374, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte0_intf_clk", + .parent_names = (const char *[]){ + "mmss_mdss_byte0_intf_div_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_div mmss_mdss_byte0_intf_div_clk = { + .reg = 0x237c, + .shift = 0, + .width = 2, + /* + * NOTE: Op does not work for div-3. Current assumption is that div-3 + * is not a recommended setting for this divider. + */ + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte0_intf_div_clk", + .parent_names = (const char *[]){ + "byte0_clk_src", + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte1_clk = { + .halt_reg = 0x2340, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2340, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte1_clk", + .parent_names = (const char *[]){ + "byte1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte1_intf_clk = { + .halt_reg = 0x2378, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2378, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte1_intf_clk", + .parent_names = (const char *[]){ + "byte1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_aux_clk = { + .halt_reg = 0x2364, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2364, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_aux_clk", + .parent_names = (const char *[]){ + "dp_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_crypto_clk = { + .halt_reg = 0x235c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x235c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_crypto_clk", + .parent_names = (const char *[]){ + "dp_crypto_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_gtc_clk = { + .halt_reg = 0x2368, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2368, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_gtc_clk", + .parent_names = (const char *[]){ + "dp_gtc_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_link_clk = { + .halt_reg = 0x2354, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2354, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_link_clk", + .parent_names = (const char *[]){ + "dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* Reset state of MMSS_MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */ +static struct clk_branch mmss_mdss_dp_link_intf_clk = { + .halt_reg = 0x2358, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2358, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_link_intf_clk", + .parent_names = (const char *[]){ + "dp_link_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_pixel_clk = { + .halt_reg = 0x2360, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2360, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_pixel_clk", + .parent_names = (const char *[]){ + "dp_pixel_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_esc0_clk = { + .halt_reg = 0x2344, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2344, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_esc0_clk", + .parent_names = (const char *[]){ + "esc0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_esc1_clk = { + .halt_reg = 0x2348, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2348, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_esc1_clk", + .parent_names = (const char *[]){ + "esc1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_hdmi_dp_ahb_clk = { + .halt_reg = 0x230c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x230c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_hdmi_dp_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_mdp_clk = { + .halt_reg = 0x231c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x231c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_mdp_clk", + .parent_names = (const char *[]){ + "mdp_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_ENABLE_HAND_OFF, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_pclk0_clk = { + .halt_reg = 0x2314, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2314, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_pclk0_clk", + .parent_names = (const char *[]){ + "pclk0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_pclk1_clk = { + .halt_reg = 0x2318, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2318, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_pclk1_clk", + .parent_names = (const char *[]){ + "pclk1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_rot_clk = { + .halt_reg = 0x2350, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2350, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_rot_clk", + .parent_names = (const char *[]){ + "rot_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_vsync_clk = { + .halt_reg = 0x2328, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2328, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_vsync_clk", + .parent_names = (const char *[]){ + "vsync_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_misc_ahb_clk = { + .halt_reg = 0x328, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x328, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_misc_ahb_clk", + /* + * Dependency to be enabled before the branch is + * enabled. + */ + .parent_names = (const char *[]){ + "mmss_mnoc_ahb_clk", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_misc_cxo_clk = { + .halt_reg = 0x324, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x324, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_misc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mnoc_ahb_clk = { + .halt_reg = 0x5024, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mnoc_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_snoc_dvm_axi_clk = { + .halt_reg = 0xe040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xe040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_snoc_dvm_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_ahb_clk = { + .halt_reg = 0x1030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_axi_clk = { + .halt_reg = 0x1034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_core_clk = { + .halt_reg = 0x1028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_core_clk", + .parent_names = (const char *[]){ + "video_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_subcore0_clk = { + .halt_reg = 0x1048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_subcore0_clk", + .parent_names = (const char *[]){ + "video_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +struct clk_hw *mmcc_sdm660_hws[] = { + [MMSS_CAMSS_JPEG0_VOTE_CLK] = &mmss_camss_jpeg0_vote_clk.hw, + [MMSS_CAMSS_JPEG0_DMA_VOTE_CLK] = &mmss_camss_jpeg0_dma_vote_clk.hw, +}; + +static struct clk_regmap *mmcc_660_clocks[] = { + [AHB_CLK_SRC] = &ahb_clk_src.clkr, + [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, + [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, + [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, + [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, + [CCI_CLK_SRC] = &cci_clk_src.clkr, + [CPP_CLK_SRC] = &cpp_clk_src.clkr, + [CSI0_CLK_SRC] = &csi0_clk_src.clkr, + [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, + [CSI1_CLK_SRC] = &csi1_clk_src.clkr, + [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, + [CSI2_CLK_SRC] = &csi2_clk_src.clkr, + [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, + [CSI3_CLK_SRC] = &csi3_clk_src.clkr, + [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr, + [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr, + [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr, + [DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr, + [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr, + [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr, + [ESC0_CLK_SRC] = &esc0_clk_src.clkr, + [ESC1_CLK_SRC] = &esc1_clk_src.clkr, + [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, + [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, + [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, + [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, + [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, + [MDP_CLK_SRC] = &mdp_clk_src.clkr, + [MMPLL0_PLL] = &mmpll0_pll_out_main.clkr, + [MMPLL10_PLL] = &mmpll10_pll_out_main.clkr, + [MMPLL3_PLL] = &mmpll3_pll_out_main.clkr, + [MMPLL4_PLL] = &mmpll4_pll_out_main.clkr, + [MMPLL5_PLL] = &mmpll5_pll_out_main.clkr, + [MMPLL6_PLL] = &mmpll6_pll_out_main.clkr, + [MMPLL7_PLL] = &mmpll7_pll_out_main.clkr, + [MMPLL8_PLL] = &mmpll8_pll_out_main.clkr, + [MMSS_BIMC_SMMU_AHB_CLK] = &mmss_bimc_smmu_ahb_clk.clkr, + [MMSS_BIMC_SMMU_AXI_CLK] = &mmss_bimc_smmu_axi_clk.clkr, + [MMSS_CAMSS_AHB_CLK] = &mmss_camss_ahb_clk.clkr, + [MMSS_CAMSS_CCI_AHB_CLK] = &mmss_camss_cci_ahb_clk.clkr, + [MMSS_CAMSS_CCI_CLK] = &mmss_camss_cci_clk.clkr, + [MMSS_CAMSS_CPHY_CSID0_CLK] = &mmss_camss_cphy_csid0_clk.clkr, + [MMSS_CAMSS_CPHY_CSID1_CLK] = &mmss_camss_cphy_csid1_clk.clkr, + [MMSS_CAMSS_CPHY_CSID2_CLK] = &mmss_camss_cphy_csid2_clk.clkr, + [MMSS_CAMSS_CPHY_CSID3_CLK] = &mmss_camss_cphy_csid3_clk.clkr, + [MMSS_CAMSS_CPP_AHB_CLK] = &mmss_camss_cpp_ahb_clk.clkr, + [MMSS_CAMSS_CPP_AXI_CLK] = &mmss_camss_cpp_axi_clk.clkr, + [MMSS_CAMSS_CPP_CLK] = &mmss_camss_cpp_clk.clkr, + [MMSS_CAMSS_CPP_VBIF_AHB_CLK] = &mmss_camss_cpp_vbif_ahb_clk.clkr, + [MMSS_CAMSS_CSI0_AHB_CLK] = &mmss_camss_csi0_ahb_clk.clkr, + [MMSS_CAMSS_CSI0_CLK] = &mmss_camss_csi0_clk.clkr, + [MMSS_CAMSS_CSI0PHYTIMER_CLK] = &mmss_camss_csi0phytimer_clk.clkr, + [MMSS_CAMSS_CSI0PIX_CLK] = &mmss_camss_csi0pix_clk.clkr, + [MMSS_CAMSS_CSI0RDI_CLK] = &mmss_camss_csi0rdi_clk.clkr, + [MMSS_CAMSS_CSI1_AHB_CLK] = &mmss_camss_csi1_ahb_clk.clkr, + [MMSS_CAMSS_CSI1_CLK] = &mmss_camss_csi1_clk.clkr, + [MMSS_CAMSS_CSI1PHYTIMER_CLK] = &mmss_camss_csi1phytimer_clk.clkr, + [MMSS_CAMSS_CSI1PIX_CLK] = &mmss_camss_csi1pix_clk.clkr, + [MMSS_CAMSS_CSI1RDI_CLK] = &mmss_camss_csi1rdi_clk.clkr, + [MMSS_CAMSS_CSI2_AHB_CLK] = &mmss_camss_csi2_ahb_clk.clkr, + [MMSS_CAMSS_CSI2_CLK] = &mmss_camss_csi2_clk.clkr, + [MMSS_CAMSS_CSI2PHYTIMER_CLK] = &mmss_camss_csi2phytimer_clk.clkr, + [MMSS_CAMSS_CSI2PIX_CLK] = &mmss_camss_csi2pix_clk.clkr, + [MMSS_CAMSS_CSI2RDI_CLK] = &mmss_camss_csi2rdi_clk.clkr, + [MMSS_CAMSS_CSI3_AHB_CLK] = &mmss_camss_csi3_ahb_clk.clkr, + [MMSS_CAMSS_CSI3_CLK] = &mmss_camss_csi3_clk.clkr, + [MMSS_CAMSS_CSI3PIX_CLK] = &mmss_camss_csi3pix_clk.clkr, + [MMSS_CAMSS_CSI3RDI_CLK] = &mmss_camss_csi3rdi_clk.clkr, + [MMSS_CAMSS_CSI_VFE0_CLK] = &mmss_camss_csi_vfe0_clk.clkr, + [MMSS_CAMSS_CSI_VFE1_CLK] = &mmss_camss_csi_vfe1_clk.clkr, + [MMSS_CAMSS_CSIPHY0_CLK] = &mmss_camss_csiphy0_clk.clkr, + [MMSS_CAMSS_CSIPHY1_CLK] = &mmss_camss_csiphy1_clk.clkr, + [MMSS_CAMSS_CSIPHY2_CLK] = &mmss_camss_csiphy2_clk.clkr, + [MMSS_CAMSS_GP0_CLK] = &mmss_camss_gp0_clk.clkr, + [MMSS_CAMSS_GP1_CLK] = &mmss_camss_gp1_clk.clkr, + [MMSS_CAMSS_ISPIF_AHB_CLK] = &mmss_camss_ispif_ahb_clk.clkr, + [MMSS_CAMSS_JPEG0_CLK] = &mmss_camss_jpeg0_clk.clkr, + [MMSS_CAMSS_JPEG_AHB_CLK] = &mmss_camss_jpeg_ahb_clk.clkr, + [MMSS_CAMSS_JPEG_AXI_CLK] = &mmss_camss_jpeg_axi_clk.clkr, + [MMSS_CAMSS_MCLK0_CLK] = &mmss_camss_mclk0_clk.clkr, + [MMSS_CAMSS_MCLK1_CLK] = &mmss_camss_mclk1_clk.clkr, + [MMSS_CAMSS_MCLK2_CLK] = &mmss_camss_mclk2_clk.clkr, + [MMSS_CAMSS_MCLK3_CLK] = &mmss_camss_mclk3_clk.clkr, + [MMSS_CAMSS_MICRO_AHB_CLK] = &mmss_camss_micro_ahb_clk.clkr, + [MMSS_CAMSS_TOP_AHB_CLK] = &mmss_camss_top_ahb_clk.clkr, + [MMSS_CAMSS_VFE0_AHB_CLK] = &mmss_camss_vfe0_ahb_clk.clkr, + [MMSS_CAMSS_VFE0_CLK] = &mmss_camss_vfe0_clk.clkr, + [MMSS_CAMSS_VFE0_STREAM_CLK] = &mmss_camss_vfe0_stream_clk.clkr, + [MMSS_CAMSS_VFE1_AHB_CLK] = &mmss_camss_vfe1_ahb_clk.clkr, + [MMSS_CAMSS_VFE1_CLK] = &mmss_camss_vfe1_clk.clkr, + [MMSS_CAMSS_VFE1_STREAM_CLK] = &mmss_camss_vfe1_stream_clk.clkr, + [MMSS_CAMSS_VFE_VBIF_AHB_CLK] = &mmss_camss_vfe_vbif_ahb_clk.clkr, + [MMSS_CAMSS_VFE_VBIF_AXI_CLK] = &mmss_camss_vfe_vbif_axi_clk.clkr, + [MMSS_CSIPHY_AHB2CRIF_CLK] = &mmss_csiphy_ahb2crif_clk.clkr, + [MMSS_MDSS_AHB_CLK] = &mmss_mdss_ahb_clk.clkr, + [MMSS_MDSS_AXI_CLK] = &mmss_mdss_axi_clk.clkr, + [MMSS_MDSS_BYTE0_CLK] = &mmss_mdss_byte0_clk.clkr, + [MMSS_MDSS_BYTE0_INTF_CLK] = &mmss_mdss_byte0_intf_clk.clkr, + [MMSS_MDSS_BYTE0_INTF_DIV_CLK] = &mmss_mdss_byte0_intf_div_clk.clkr, + [MMSS_MDSS_BYTE1_CLK] = &mmss_mdss_byte1_clk.clkr, + [MMSS_MDSS_BYTE1_INTF_CLK] = &mmss_mdss_byte1_intf_clk.clkr, + [MMSS_MDSS_DP_AUX_CLK] = &mmss_mdss_dp_aux_clk.clkr, + [MMSS_MDSS_DP_CRYPTO_CLK] = &mmss_mdss_dp_crypto_clk.clkr, + [MMSS_MDSS_DP_GTC_CLK] = &mmss_mdss_dp_gtc_clk.clkr, + [MMSS_MDSS_DP_LINK_CLK] = &mmss_mdss_dp_link_clk.clkr, + [MMSS_MDSS_DP_LINK_INTF_CLK] = &mmss_mdss_dp_link_intf_clk.clkr, + [MMSS_MDSS_DP_PIXEL_CLK] = &mmss_mdss_dp_pixel_clk.clkr, + [MMSS_MDSS_ESC0_CLK] = &mmss_mdss_esc0_clk.clkr, + [MMSS_MDSS_ESC1_CLK] = &mmss_mdss_esc1_clk.clkr, + [MMSS_MDSS_HDMI_DP_AHB_CLK] = &mmss_mdss_hdmi_dp_ahb_clk.clkr, + [MMSS_MDSS_MDP_CLK] = &mmss_mdss_mdp_clk.clkr, + [MMSS_MDSS_PCLK0_CLK] = &mmss_mdss_pclk0_clk.clkr, + [MMSS_MDSS_PCLK1_CLK] = &mmss_mdss_pclk1_clk.clkr, + [MMSS_MDSS_ROT_CLK] = &mmss_mdss_rot_clk.clkr, + [MMSS_MDSS_VSYNC_CLK] = &mmss_mdss_vsync_clk.clkr, + [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, + [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, + [MMSS_MNOC_AHB_CLK] = &mmss_mnoc_ahb_clk.clkr, + [MMSS_SNOC_DVM_AXI_CLK] = &mmss_snoc_dvm_axi_clk.clkr, + [MMSS_VIDEO_AHB_CLK] = &mmss_video_ahb_clk.clkr, + [MMSS_VIDEO_AXI_CLK] = &mmss_video_axi_clk.clkr, + [MMSS_VIDEO_CORE_CLK] = &mmss_video_core_clk.clkr, + [MMSS_VIDEO_SUBCORE0_CLK] = &mmss_video_subcore0_clk.clkr, + [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, + [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, + [ROT_CLK_SRC] = &rot_clk_src.clkr, + [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, + [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, + [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, + [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, +}; + +static const struct qcom_reset_map mmcc_660_resets[] = { + [CAMSS_MICRO_BCR] = { 0x3490 }, +}; + +static const struct regmap_config mmcc_660_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10004, + .fast_io = true, +}; + +static const struct qcom_cc_desc mmcc_660_desc = { + .config = &mmcc_660_regmap_config, + .clks = mmcc_660_clocks, + .num_clks = ARRAY_SIZE(mmcc_660_clocks), + .hwclks = mmcc_sdm660_hws, + .num_hwclks = ARRAY_SIZE(mmcc_sdm660_hws), + .resets = mmcc_660_resets, + .num_resets = ARRAY_SIZE(mmcc_660_resets), +}; + +static const struct of_device_id mmcc_660_match_table[] = { + { .compatible = "qcom,mmcc-sdm660" }, + { } +}; +MODULE_DEVICE_TABLE(of, mmcc_660_match_table); + +static int mmcc_660_probe(struct platform_device *pdev) +{ + int ret = 0; + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &mmcc_660_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* PLLs connected on Mx rails of MMSS_CC */ + vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_mmss"); + if (IS_ERR(vdd_mx.regulator[0])) { + if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_mx_mmss regulator\n"); + return PTR_ERR(vdd_mx.regulator[0]); + } + + vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_mmss"); + if (IS_ERR(vdd_dig.regulator[0])) { + if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig regulator\n"); + return PTR_ERR(vdd_dig.regulator[0]); + } + + /* MMPLL10 connected to the Analog Rail */ + vdda.regulator[0] = devm_regulator_get(&pdev->dev, "vdda"); + if (IS_ERR(vdda.regulator[0])) { + if (!(PTR_ERR(vdda.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdda regulator\n"); + return PTR_ERR(vdda.regulator[0]); + } + + clk_alpha_pll_configure(&mmpll3_pll_out_main, regmap, &mmpll3_config); + clk_alpha_pll_configure(&mmpll4_pll_out_main, regmap, &mmpll4_config); + clk_alpha_pll_configure(&mmpll5_pll_out_main, regmap, &mmpll5_config); + clk_alpha_pll_configure(&mmpll7_pll_out_main, regmap, &mmpll7_config); + clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config); + clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config); + + ret = qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register MMSS clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered MMSS clocks\n"); + + return ret; +} + +static struct platform_driver mmcc_660_driver = { + .probe = mmcc_660_probe, + .driver = { + .name = "mmcc-sdm660", + .of_match_table = mmcc_660_match_table, + }, +}; + +static int __init mmcc_660_init(void) +{ + return platform_driver_register(&mmcc_660_driver); +} +core_initcall_sync(mmcc_660_init); + +static void __exit mmcc_660_exit(void) +{ + platform_driver_unregister(&mmcc_660_driver); +} +module_exit(mmcc_660_exit); diff --git a/drivers/clk/qcom/vdd-level-660.h b/drivers/clk/qcom/vdd-level-660.h new file mode 100644 index 000000000000..f98a96033ea9 --- /dev/null +++ b/drivers/clk/qcom/vdd-level-660.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H +#define __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H + +#include +#include + +#define VDD_DIG_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP5(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP6(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + [VDD_DIG_##l6] = (f6), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP7(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6, \ + l7, f7) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + [VDD_DIG_##l6] = (f6), \ + [VDD_DIG_##l7] = (f7), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP1_AO(l1, f1) \ + .vdd_class = &vdd_dig_ao, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP3_AO(l1, f1, l2, f2, l3, f3) \ + .vdd_class = &vdd_dig_ao, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_GPU_PLL_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_mx, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_MMSS_PLL_DIG_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_mx, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_MMSS_PLL_DIG_FMAX_MAP2(l1, f1, l2, f2) \ + .vdd_class = &vdd_mx, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +enum vdd_dig_levels { + VDD_DIG_NONE, + VDD_DIG_MIN, /* MIN SVS */ + VDD_DIG_LOWER, /* SVS2 */ + VDD_DIG_LOW, /* SVS */ + VDD_DIG_LOW_L1, /* SVSL1 */ + VDD_DIG_NOMINAL, /* NOM */ + VDD_DIG_NOMINAL_L1, /* NOM */ + VDD_DIG_HIGH, /* TURBO */ + VDD_DIG_NUM +}; + +static int vdd_corner[] = { + RPM_REGULATOR_LEVEL_NONE, /* VDD_DIG_NONE */ + RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_DIG_MIN */ + RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_DIG_LOWER */ + RPM_REGULATOR_LEVEL_SVS, /* VDD_DIG_LOW */ + RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_DIG_LOW_L1 */ + RPM_REGULATOR_LEVEL_NOM, /* VDD_DIG_NOMINAL */ + RPM_REGULATOR_LEVEL_NOM_PLUS, /* VDD_DIG_NOMINAL */ + RPM_REGULATOR_LEVEL_TURBO, /* VDD_DIG_HIGH */ +}; + +#endif diff --git a/drivers/clk/qcom/vdd-level-falcon.h b/drivers/clk/qcom/vdd-level-falcon.h deleted file mode 100644 index 75567dbe2329..000000000000 --- a/drivers/clk/qcom/vdd-level-falcon.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H -#define __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H - -#include -#include - -#define VDD_DIG_FMAX_MAP1(l1, f1) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - [VDD_DIG_##l4] = (f4), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP5(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - [VDD_DIG_##l4] = (f4), \ - [VDD_DIG_##l5] = (f5), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP6(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - [VDD_DIG_##l4] = (f4), \ - [VDD_DIG_##l5] = (f5), \ - [VDD_DIG_##l6] = (f6), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP7(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6, \ - l7, f7) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - [VDD_DIG_##l4] = (f4), \ - [VDD_DIG_##l5] = (f5), \ - [VDD_DIG_##l6] = (f6), \ - [VDD_DIG_##l7] = (f7), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP1_AO(l1, f1) \ - .vdd_class = &vdd_dig_ao, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP3_AO(l1, f1, l2, f2, l3, f3) \ - .vdd_class = &vdd_dig_ao, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_GPU_PLL_FMAX_MAP1(l1, f1) \ - .vdd_class = &vdd_mx, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_MMSS_PLL_DIG_FMAX_MAP1(l1, f1) \ - .vdd_class = &vdd_mx, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_MMSS_PLL_DIG_FMAX_MAP2(l1, f1, l2, f2) \ - .vdd_class = &vdd_mx, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -enum vdd_dig_levels { - VDD_DIG_NONE, - VDD_DIG_MIN, /* MIN SVS */ - VDD_DIG_LOWER, /* SVS2 */ - VDD_DIG_LOW, /* SVS */ - VDD_DIG_LOW_L1, /* SVSL1 */ - VDD_DIG_NOMINAL, /* NOM */ - VDD_DIG_NOMINAL_L1, /* NOM */ - VDD_DIG_HIGH, /* TURBO */ - VDD_DIG_NUM -}; - -static int vdd_corner[] = { - RPM_REGULATOR_LEVEL_NONE, /* VDD_DIG_NONE */ - RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_DIG_MIN */ - RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_DIG_LOWER */ - RPM_REGULATOR_LEVEL_SVS, /* VDD_DIG_LOW */ - RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_DIG_LOW_L1 */ - RPM_REGULATOR_LEVEL_NOM, /* VDD_DIG_NOMINAL */ - RPM_REGULATOR_LEVEL_NOM_PLUS, /* VDD_DIG_NOMINAL */ - RPM_REGULATOR_LEVEL_TURBO, /* VDD_DIG_HIGH */ -}; - -#endif diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 11d88df37d31..d45df18a7019 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -372,18 +372,18 @@ config CRYPTO_DEV_QCRYPTO config CRYPTO_DEV_QCOM_MSM_QCE tristate "Qualcomm Crypto Engine (QCE) module" - select CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_MSMFALCON || ARCH_MSMTRITON + select CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_SDM660 || ARCH_MSMTRITON default n help This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660 MSM8x55, MSM8960, MSM9615, MSM8916, MSM8994, MSM8996, FSM9900, - MSMTITANINUM, APQ8084, MSM8998, MSMFALCON and MSMTRITON. + MSMTITANINUM, APQ8084, MSM8998, SDM660 and MSMTRITON. To compile this driver as a module, choose M here: the For MSM7x30 MSM8660 and MSM8x55 the module is called qce For MSM8960, APQ8064 and MSM9615 the module is called qce40 For MSM8974, MSM8916, MSM8994, MSM8996, MSM8992, MSMTITANIUM, - APQ8084, MSM8998, MSMFALCON and MSMTRITON the module is called qce50. + APQ8084, MSM8998, SDM660 and MSMTRITON the module is called qce50. config CRYPTO_DEV_QCEDEV tristate "QCEDEV Interface to CE module" @@ -391,7 +391,7 @@ config CRYPTO_DEV_QCEDEV help This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660, MSM8960, MSM9615, APQ8064, MSM8974, MSM8916, MSM8994, MSM8996, - APQ8084, MSM8998, MSMFALCON, MSMTRITON. This exposes the + APQ8084, MSM8998, SDM660, MSMTRITON. This exposes the interface to the QCE hardware accelerator via IOCTLs. To compile this driver as a module, choose M here: the diff --git a/drivers/leds/leds-qpnp-flash-v2.c b/drivers/leds/leds-qpnp-flash-v2.c index 674ca6161af9..aa59677c4b6a 100644 --- a/drivers/leds/leds-qpnp-flash-v2.c +++ b/drivers/leds/leds-qpnp-flash-v2.c @@ -1733,7 +1733,7 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led, led->pdata->thermal_hysteresis = -EINVAL; rc = of_property_read_u32(node, "qcom,thermal-hysteresis", &val); if (!rc) { - if (led->pdata->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + if (led->pdata->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) val = THERMAL_HYST_TEMP_TO_VAL(val, 20); else val = THERMAL_HYST_TEMP_TO_VAL(val, 15); diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c index 56750ac8e9e2..718badb16ea1 100644 --- a/drivers/leds/leds-qpnp-wled.c +++ b/drivers/leds/leds-qpnp-wled.c @@ -479,7 +479,7 @@ static int qpnp_wled_swire_avdd_config(struct qpnp_wled *wled) u8 val; if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE && - wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) return 0; if (!wled->disp_type_amoled || wled->avdd_mode_spmi) @@ -1103,11 +1103,11 @@ static bool is_avdd_trim_adjustment_required(struct qpnp_wled *wled) u8 reg = 0; /* - * AVDD trim adjustment is not required for pmi8998/pm2falcon and not + * AVDD trim adjustment is not required for pmi8998/pm660l and not * supported for pmi8994. */ if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE || + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PMI8994_SUBTYPE) return false; @@ -1133,7 +1133,7 @@ static int qpnp_wled_gm_config(struct qpnp_wled *wled) /* Configure the LOOP COMP GM register */ if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { if (wled->loop_auto_gm_en) reg |= QPNP_WLED_VLOOP_COMP_AUTO_GM_EN; @@ -1179,7 +1179,7 @@ static int qpnp_wled_ovp_config(struct qpnp_wled *wled) return 0; if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) ovp_table = qpnp_wled_ovp_thresholds_pmi8998; else ovp_table = qpnp_wled_ovp_thresholds_pmi8994; @@ -1264,10 +1264,10 @@ static int qpnp_wled_avdd_mode_config(struct qpnp_wled *wled) /* * At present, configuring the mode to SPMI/SWIRE for controlling - * AVDD voltage is available only in pmi8998/pm2falcon. + * AVDD voltage is available only in pmi8998/pm660l. */ if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE && - wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) return 0; /* AMOLED_VOUT should be configured for AMOLED */ @@ -1313,7 +1313,7 @@ static int qpnp_wled_ilim_config(struct qpnp_wled *wled) wled->ilim_ma = PMI8994_WLED_ILIM_MIN_MA; if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { ilim_table = qpnp_wled_ilim_settings_pmi8998; if (wled->ilim_ma > PMI8998_WLED_ILIM_MAX_MA) wled->ilim_ma = PMI8998_WLED_ILIM_MAX_MA; @@ -1352,7 +1352,7 @@ static int qpnp_wled_vref_config(struct qpnp_wled *wled) u8 reg = 0; if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) vref_setting = vref_setting_pmi8998; else vref_setting = vref_setting_pmi8994; @@ -1420,7 +1420,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled) /* Configure auto PFM mode for LCD mode only */ if ((wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) && !wled->disp_type_amoled) { reg = 0; reg |= wled->lcd_auto_pfm_thresh; @@ -1563,7 +1563,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled) reg = QPNP_WLED_SINK_TEST5_DIG; } else { reg = QPNP_WLED_SINK_TEST5_HYB; - if (wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + if (wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) reg |= QPNP_WLED_SINK_TEST5_HVG_PULL_STR_BIT; } @@ -1816,7 +1816,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) if (wled->disp_type_amoled) { if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) wled->loop_ea_gm = QPNP_WLED_LOOP_GM_DFLT_AMOLED_PMI8998; else @@ -1836,7 +1836,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { wled->loop_auto_gm_en = of_property_read_bool(pdev->dev.of_node, "qcom,loop-auto-gm-en"); @@ -1852,7 +1852,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { if (wled->pmic_rev_id->rev4 == PMI8998_V2P0_REV4) wled->lcd_auto_pfm_en = false; @@ -1905,7 +1905,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) wled->vref_uv = vref_setting_pmi8998.default_uv; else wled->vref_uv = vref_setting_pmi8994.default_uv; @@ -1929,7 +1929,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) wled->ovp_mv = 29600; else wled->ovp_mv = 29500; @@ -1943,7 +1943,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { if (wled->disp_type_amoled) wled->ilim_ma = PMI8998_AMOLED_DFLT_ILIM_MA; else diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 223339ff119d..e1ef353aa1e1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -46,7 +46,7 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qrbtc-v2.o -obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3-falcon.o +obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3-660.o obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-660.c b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c new file mode 100644 index 000000000000..a0cb7d0896d1 --- /dev/null +++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "phy-qcom-ufs-qmp-v3-660.h" + +#define UFS_PHY_NAME "ufs_phy_qmp_v3_660" + +static +int ufs_qcom_phy_qmp_v3_660_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, + bool is_rate_B) +{ + int err; + int tbl_size_A, tbl_size_B; + struct ufs_qcom_phy_calibration *tbl_A, *tbl_B; + u8 major = ufs_qcom_phy->host_ctrl_rev_major; + u16 minor = ufs_qcom_phy->host_ctrl_rev_minor; + u16 step = ufs_qcom_phy->host_ctrl_rev_step; + + tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B); + tbl_B = phy_cal_table_rate_B; + + if ((major == 0x3) && (minor == 0x001) && (step == 0x001)) { + tbl_A = phy_cal_table_rate_A_3_1_1; + tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_3_1_1); + } else { + dev_err(ufs_qcom_phy->dev, + "%s: Unknown UFS-PHY version (major 0x%x minor 0x%x step 0x%x), no calibration values\n", + __func__, major, minor, step); + err = -ENODEV; + goto out; + } + + err = ufs_qcom_phy_calibrate(ufs_qcom_phy, + tbl_A, tbl_size_A, + tbl_B, tbl_size_B, + is_rate_B); + + if (err) + dev_err(ufs_qcom_phy->dev, + "%s: ufs_qcom_phy_calibrate() failed %d\n", + __func__, err); + +out: + return err; +} + +static int ufs_qcom_phy_qmp_v3_660_init(struct phy *generic_phy) +{ + struct ufs_qcom_phy_qmp_v3_660 *phy = phy_get_drvdata(generic_phy); + struct ufs_qcom_phy *phy_common = &phy->common_cfg; + int err; + + err = ufs_qcom_phy_init_clks(generic_phy, phy_common); + if (err) { + dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n", + __func__, err); + goto out; + } + + err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common); + if (err) { + dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n", + __func__, err); + goto out; + } + +out: + return err; +} + +static +void ufs_qcom_phy_qmp_v3_660_power_control(struct ufs_qcom_phy *phy, + bool power_ctrl) +{ + if (!power_ctrl) { + /* apply analog power collapse */ + writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); + /* + * Make sure that PHY knows its analog rail is going to be + * powered OFF. + */ + mb(); + } else { + /* bring PHY out of analog power collapse */ + writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); + + /* + * Before any transactions involving PHY, ensure PHY knows + * that it's analog rail is powered ON. + */ + mb(); + } +} + +static inline +void ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable(struct ufs_qcom_phy *phy, + u32 val) +{ + /* + * v3 PHY does not have TX_LANE_ENABLE register. + * Implement this function so as not to propagate error to caller. + */ +} + +static +void ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, + bool ctrl) +{ + u32 temp; + + temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE); + + if (ctrl) /* enable RX LineCfg */ + temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT; + else /* disable RX LineCfg */ + temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT; + + writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE); + /* Make sure that RX LineCfg config applied before we return */ + mb(); +} + +static inline void ufs_qcom_phy_qmp_v3_660_start_serdes( + struct ufs_qcom_phy *phy) +{ + u32 tmp; + + tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START); + tmp &= ~MASK_SERDES_START; + tmp |= (1 << OFFSET_SERDES_START); + writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START); + /* Ensure register value is committed */ + mb(); +} + +static int ufs_qcom_phy_qmp_v3_660_is_pcs_ready( + struct ufs_qcom_phy *phy_common) +{ + int err = 0; + u32 val; + + err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS, + val, (val & MASK_PCS_READY), 10, 1000000); + if (err) + dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n", + __func__, err); + return err; +} + +static void ufs_qcom_phy_qmp_v3_660_dbg_register_dump( + struct ufs_qcom_phy *phy) +{ + ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE, + "PHY QSERDES COM Registers "); + ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE, + "PHY Registers "); + ufs_qcom_phy_dump_regs(phy, RX_BASE, RX_SIZE, + "PHY RX0 Registers "); + ufs_qcom_phy_dump_regs(phy, TX_BASE, TX_SIZE, + "PHY TX0 Registers "); +} + +struct phy_ops ufs_qcom_phy_qmp_v3_660_phy_ops = { + .init = ufs_qcom_phy_qmp_v3_660_init, + .exit = ufs_qcom_phy_exit, + .power_on = ufs_qcom_phy_power_on, + .power_off = ufs_qcom_phy_power_off, + .owner = THIS_MODULE, +}; + +struct ufs_qcom_phy_specific_ops phy_v3_660_ops = { + .calibrate_phy = ufs_qcom_phy_qmp_v3_660_phy_calibrate, + .start_serdes = ufs_qcom_phy_qmp_v3_660_start_serdes, + .is_physical_coding_sublayer_ready = + ufs_qcom_phy_qmp_v3_660_is_pcs_ready, + .set_tx_lane_enable = ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable, + .ctrl_rx_linecfg = ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg, + .power_control = ufs_qcom_phy_qmp_v3_660_power_control, + .dbg_register_dump = ufs_qcom_phy_qmp_v3_660_dbg_register_dump, +}; + +static int ufs_qcom_phy_qmp_v3_660_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy *generic_phy; + struct ufs_qcom_phy_qmp_v3_660 *phy; + int err = 0; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) { + err = -ENOMEM; + goto out; + } + + generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg, + &ufs_qcom_phy_qmp_v3_660_phy_ops, + &phy_v3_660_ops); + + if (!generic_phy) { + dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n", + __func__); + err = -EIO; + goto out; + } + + phy_set_drvdata(generic_phy, phy); + + strlcpy(phy->common_cfg.name, UFS_PHY_NAME, + sizeof(phy->common_cfg.name)); + +out: + return err; +} + +static int ufs_qcom_phy_qmp_v3_660_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy *generic_phy = to_phy(dev); + struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); + int err = 0; + + err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy); + if (err) + dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n", + __func__, err); + + return err; +} + +static const struct of_device_id ufs_qcom_phy_qmp_v3_660_of_match[] = { + {.compatible = "qcom,ufs-phy-qmp-v3-660"}, + {}, +}; +MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_660_of_match); + +static struct platform_driver ufs_qcom_phy_qmp_v3_660_driver = { + .probe = ufs_qcom_phy_qmp_v3_660_probe, + .remove = ufs_qcom_phy_qmp_v3_660_remove, + .driver = { + .of_match_table = ufs_qcom_phy_qmp_v3_660_of_match, + .name = "ufs_qcom_phy_qmp_v3_660", + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(ufs_qcom_phy_qmp_v3_660_driver); + +MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 660"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-660.h b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h new file mode 100644 index 000000000000..8d0183d87e20 --- /dev/null +++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef UFS_QCOM_PHY_QMP_V3_660_H_ +#define UFS_QCOM_PHY_QMP_V3_660_H_ + +#include "phy-qcom-ufs-i.h" + +/* QCOM UFS PHY control registers */ +#define COM_BASE 0x000 +#define COM_OFF(x) (COM_BASE + x) +#define COM_SIZE 0x1C0 + +#define TX_BASE 0x400 +#define TX_OFF(x) (TX_BASE + x) +#define TX_SIZE 0x128 + +#define RX_BASE 0x600 +#define RX_OFF(x) (RX_BASE + x) +#define RX_SIZE 0x1FC + +#define PHY_BASE 0xC00 +#define PHY_OFF(x) (PHY_BASE + x) +#define PHY_SIZE 0x1B4 + +/* UFS PHY QSERDES COM registers */ +#define QSERDES_COM_ATB_SEL1 COM_OFF(0x00) +#define QSERDES_COM_ATB_SEL2 COM_OFF(0x04) +#define QSERDES_COM_FREQ_UPDATE COM_OFF(0x08) +#define QSERDES_COM_BG_TIMER COM_OFF(0x0C) +#define QSERDES_COM_SSC_EN_CENTER COM_OFF(0x10) +#define QSERDES_COM_SSC_ADJ_PER1 COM_OFF(0x14) +#define QSERDES_COM_SSC_ADJ_PER2 COM_OFF(0x18) +#define QSERDES_COM_SSC_PER1 COM_OFF(0x1C) +#define QSERDES_COM_SSC_PER2 COM_OFF(0x20) +#define QSERDES_COM_SSC_STEP_SIZE1 COM_OFF(0x24) +#define QSERDES_COM_SSC_STEP_SIZE2 COM_OFF(0x28) +#define QSERDES_COM_POST_DIV COM_OFF(0x2C) +#define QSERDES_COM_POST_DIV_MUX COM_OFF(0x30) +#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34) +#define QSERDES_COM_CLK_ENABLE1 COM_OFF(0x38) +#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C) +#define QSERDES_COM_SYSCLK_BUF_ENABLE COM_OFF(0x40) +#define QSERDES_COM_PLL_EN COM_OFF(0x44) +#define QSERDES_COM_PLL_IVCO COM_OFF(0x48) +#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0X4C) +#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0X50) +#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0X54) +#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0X58) +#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0X5C) +#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0X60) +#define QSERDES_COM_CMD_RSVD0 COM_OFF(0x64) +#define QSERDES_COM_EP_CLOCK_DETECT_CTRL COM_OFF(0x68) +#define QSERDES_COM_SYSCLK_DET_COMP_STATUS COM_OFF(0x6C) +#define QSERDES_COM_BG_TRIM COM_OFF(0x70) +#define QSERDES_COM_CLK_EP_DIV COM_OFF(0x74) +#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x78) +#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x7C) +#define QSERDES_COM_CMN_RSVD1 COM_OFF(0x80) +#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x84) +#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x88) +#define QSERDES_COM_CMN_RSVD2 COM_OFF(0x8C) +#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x90) +#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x94) +#define QSERDES_COM_CMN_RSVD3 COM_OFF(0x98) +#define QSERDES_COM_PLL_CNTRL COM_OFF(0x9C) +#define QSERDES_COM_PHASE_SEL_CTRL COM_OFF(0xA0) +#define QSERDES_COM_PHASE_SEL_DC COM_OFF(0xA4) +#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM COM_OFF(0xA8) +#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0xAC) +#define QSERDES_COM_CML_SYSCLK_SEL COM_OFF(0xB0) +#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0xB4) +#define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0xB8) +#define QSERDES_COM_RESTRIM_CTRL COM_OFF(0xBC) +#define QSERDES_COM_RESTRIM_CTRL2 COM_OFF(0xC0) +#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xC8) +#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0xCC) +#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xD0) +#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xD4) +#define QSERDES_COM_VCOCAL_DEADMAN_CTRL COM_OFF(0xD8) +#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xDC) +#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xE0) +#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xE4) +#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xE8) +#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xEC) +#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xF0) +#define QSERDES_COM_VCO_TUNE_MINVAL1 COM_OFF(0xF4) +#define QSERDES_COM_VCO_TUNE_MINVAL2 COM_OFF(0xF8) +#define QSERDES_COM_CMN_RSVD4 COM_OFF(0xFC) +#define QSERDES_COM_INTEGLOOP_INITVAL COM_OFF(0x100) +#define QSERDES_COM_INTEGLOOP_EN COM_OFF(0x104) +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0x108) +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0x10C) +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0x110) +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0x114) +#define QSERDES_COM_VCO_TUNE_MAXVAL1 COM_OFF(0x118) +#define QSERDES_COM_VCO_TUNE_MAXVAL2 COM_OFF(0x11C) +#define QSERDES_COM_RES_TRIM_CONTROL2 COM_OFF(0x120) +#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0x124) +#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x128) +#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0x12C) +#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0x130) +#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0x134) +#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x138) +#define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x13C) +#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x140) +#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x144) +#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x148) +#define QSERDES_COM_SAR COM_OFF(0x14C) +#define QSERDES_COM_SAR_CLK COM_OFF(0x150) +#define QSERDES_COM_SAR_CODE_OUT_STATUS COM_OFF(0x154) +#define QSERDES_COM_SAR_CODE_READY_STATUS COM_OFF(0x158) +#define QSERDES_COM_CMN_STATUS COM_OFF(0x15C) +#define QSERDES_COM_RESET_SM_STATUS COM_OFF(0x160) +#define QSERDES_COM_RESTRIM_CODE_STATUS COM_OFF(0x164) +#define QSERDES_COM_PLLCAL_CODE1_STATUS COM_OFF(0x168) +#define QSERDES_COM_PLLCAL_CODE2_STATUS COM_OFF(0x16C) +#define QSERDES_COM_BG_CTRL COM_OFF(0x170) +#define QSERDES_COM_CLK_SELECT COM_OFF(0x174) +#define QSERDES_COM_HSCLK_SEL COM_OFF(0x178) +#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS COM_OFF(0x17C) +#define QSERDES_COM_PLL_ANALOG COM_OFF(0x180) +#define QSERDES_COM_CORECLK_DIV COM_OFF(0x184) +#define QSERDES_COM_SW_RESET COM_OFF(0x188) +#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x18C) +#define QSERDES_COM_C_READY_STATUS COM_OFF(0x190) +#define QSERDES_COM_CMN_CONFIG COM_OFF(0x194) +#define QSERDES_COM_CMN_RATE_OVERRIDE COM_OFF(0x198) +#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x19C) +#define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x1A0) +#define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x1A4) +#define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x1A8) +#define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x1AC) +#define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x1B0) +#define QSERDES_COM_CMN_MISC1 COM_OFF(0x1B4) +#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC) +#define QSERDES_COM_CMN_RSVD5 COM_OFF(0x1C0) + +/* UFS PHY registers */ +#define UFS_PHY_PHY_START PHY_OFF(0x00) +#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04) +#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x34) +#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C) +#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC) +#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138) +#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x13C) +#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148) +#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154) +#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168) + +/* UFS PHY TX registers */ +#define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN TX_OFF(0x68) +#define QSERDES_TX_LANE_MODE TX_OFF(0x94) + +/* UFS PHY RX registers */ +#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF RX_OFF(0x30) +#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0x34) +#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH RX_OFF(0x38) +#define QSERDES_RX_UCDR_SVS_SO_GAIN RX_OFF(0x3C) +#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN RX_OFF(0x40) +#define QSERDES_RX_UCDR_SO_SATURATION_ENABLE RX_OFF(0x48) +#define QSERDES_RX_RX_TERM_BW RX_OFF(0x90) +#define QSERDES_RX_RX_EQ_GAIN1_LSB RX_OFF(0xC4) +#define QSERDES_RX_RX_EQ_GAIN1_MSB RX_OFF(0xC8) +#define QSERDES_RX_RX_EQ_GAIN2_LSB RX_OFF(0xCC) +#define QSERDES_RX_RX_EQ_GAIN2_MSB RX_OFF(0xD0) +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0xD8) +#define QSERDES_RX_SIGDET_CNTRL RX_OFF(0x114) +#define QSERDES_RX_SIGDET_LVL RX_OFF(0x118) +#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL RX_OFF(0x11C) +#define QSERDES_RX_RX_INTERFACE_MODE RX_OFF(0x12C) + + +#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) + +/* + * This structure represents the v3 660 specific phy. + * common_cfg MUST remain the first field in this structure + * in case extra fields are added. This way, when calling + * get_ufs_qcom_phy() of generic phy, we can extract the + * common phy structure (struct ufs_qcom_phy) out of it + * regardless of the relevant specific phy. + */ +struct ufs_qcom_phy_qmp_v3_660 { + struct ufs_qcom_phy common_cfg; +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_3_1_1[] = { + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44), +}; + +#endif diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c b/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c deleted file mode 100644 index e88c00e01e0b..000000000000 --- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include "phy-qcom-ufs-qmp-v3-falcon.h" - -#define UFS_PHY_NAME "ufs_phy_qmp_v3_falcon" - -static -int ufs_qcom_phy_qmp_v3_falcon_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, - bool is_rate_B) -{ - int err; - int tbl_size_A, tbl_size_B; - struct ufs_qcom_phy_calibration *tbl_A, *tbl_B; - u8 major = ufs_qcom_phy->host_ctrl_rev_major; - u16 minor = ufs_qcom_phy->host_ctrl_rev_minor; - u16 step = ufs_qcom_phy->host_ctrl_rev_step; - - tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B); - tbl_B = phy_cal_table_rate_B; - - if ((major == 0x3) && (minor == 0x001) && (step == 0x001)) { - tbl_A = phy_cal_table_rate_A_3_1_1; - tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_3_1_1); - } else { - dev_err(ufs_qcom_phy->dev, - "%s: Unknown UFS-PHY version (major 0x%x minor 0x%x step 0x%x), no calibration values\n", - __func__, major, minor, step); - err = -ENODEV; - goto out; - } - - err = ufs_qcom_phy_calibrate(ufs_qcom_phy, - tbl_A, tbl_size_A, - tbl_B, tbl_size_B, - is_rate_B); - - if (err) - dev_err(ufs_qcom_phy->dev, - "%s: ufs_qcom_phy_calibrate() failed %d\n", - __func__, err); - -out: - return err; -} - -static int ufs_qcom_phy_qmp_v3_falcon_init(struct phy *generic_phy) -{ - struct ufs_qcom_phy_qmp_v3_falcon *phy = phy_get_drvdata(generic_phy); - struct ufs_qcom_phy *phy_common = &phy->common_cfg; - int err; - - err = ufs_qcom_phy_init_clks(generic_phy, phy_common); - if (err) { - dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n", - __func__, err); - goto out; - } - - err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common); - if (err) { - dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n", - __func__, err); - goto out; - } - -out: - return err; -} - -static -void ufs_qcom_phy_qmp_v3_falcon_power_control(struct ufs_qcom_phy *phy, - bool power_ctrl) -{ - if (!power_ctrl) { - /* apply analog power collapse */ - writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); - /* - * Make sure that PHY knows its analog rail is going to be - * powered OFF. - */ - mb(); - } else { - /* bring PHY out of analog power collapse */ - writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); - - /* - * Before any transactions involving PHY, ensure PHY knows - * that it's analog rail is powered ON. - */ - mb(); - } -} - -static inline -void ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable(struct ufs_qcom_phy *phy, - u32 val) -{ - /* - * v3 PHY does not have TX_LANE_ENABLE register. - * Implement this function so as not to propagate error to caller. - */ -} - -static -void ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, - bool ctrl) -{ - u32 temp; - - temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE); - - if (ctrl) /* enable RX LineCfg */ - temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT; - else /* disable RX LineCfg */ - temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT; - - writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE); - /* Make sure that RX LineCfg config applied before we return */ - mb(); -} - -static inline void ufs_qcom_phy_qmp_v3_falcon_start_serdes( - struct ufs_qcom_phy *phy) -{ - u32 tmp; - - tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START); - tmp &= ~MASK_SERDES_START; - tmp |= (1 << OFFSET_SERDES_START); - writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START); - /* Ensure register value is committed */ - mb(); -} - -static int ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready( - struct ufs_qcom_phy *phy_common) -{ - int err = 0; - u32 val; - - err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS, - val, (val & MASK_PCS_READY), 10, 1000000); - if (err) - dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n", - __func__, err); - return err; -} - -static void ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump( - struct ufs_qcom_phy *phy) -{ - ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE, - "PHY QSERDES COM Registers "); - ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE, - "PHY Registers "); - ufs_qcom_phy_dump_regs(phy, RX_BASE, RX_SIZE, - "PHY RX0 Registers "); - ufs_qcom_phy_dump_regs(phy, TX_BASE, TX_SIZE, - "PHY TX0 Registers "); -} - -struct phy_ops ufs_qcom_phy_qmp_v3_falcon_phy_ops = { - .init = ufs_qcom_phy_qmp_v3_falcon_init, - .exit = ufs_qcom_phy_exit, - .power_on = ufs_qcom_phy_power_on, - .power_off = ufs_qcom_phy_power_off, - .owner = THIS_MODULE, -}; - -struct ufs_qcom_phy_specific_ops phy_v3_falcon_ops = { - .calibrate_phy = ufs_qcom_phy_qmp_v3_falcon_phy_calibrate, - .start_serdes = ufs_qcom_phy_qmp_v3_falcon_start_serdes, - .is_physical_coding_sublayer_ready = - ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready, - .set_tx_lane_enable = ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable, - .ctrl_rx_linecfg = ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg, - .power_control = ufs_qcom_phy_qmp_v3_falcon_power_control, - .dbg_register_dump = ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump, -}; - -static int ufs_qcom_phy_qmp_v3_falcon_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct phy *generic_phy; - struct ufs_qcom_phy_qmp_v3_falcon *phy; - int err = 0; - - phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); - if (!phy) { - err = -ENOMEM; - goto out; - } - - generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg, - &ufs_qcom_phy_qmp_v3_falcon_phy_ops, - &phy_v3_falcon_ops); - - if (!generic_phy) { - dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n", - __func__); - err = -EIO; - goto out; - } - - phy_set_drvdata(generic_phy, phy); - - strlcpy(phy->common_cfg.name, UFS_PHY_NAME, - sizeof(phy->common_cfg.name)); - -out: - return err; -} - -static int ufs_qcom_phy_qmp_v3_falcon_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct phy *generic_phy = to_phy(dev); - struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); - int err = 0; - - err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy); - if (err) - dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n", - __func__, err); - - return err; -} - -static const struct of_device_id ufs_qcom_phy_qmp_v3_falcon_of_match[] = { - {.compatible = "qcom,ufs-phy-qmp-v3-falcon"}, - {}, -}; -MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_falcon_of_match); - -static struct platform_driver ufs_qcom_phy_qmp_v3_falcon_driver = { - .probe = ufs_qcom_phy_qmp_v3_falcon_probe, - .remove = ufs_qcom_phy_qmp_v3_falcon_remove, - .driver = { - .of_match_table = ufs_qcom_phy_qmp_v3_falcon_of_match, - .name = "ufs_qcom_phy_qmp_v3_falcon", - .owner = THIS_MODULE, - }, -}; - -module_platform_driver(ufs_qcom_phy_qmp_v3_falcon_driver); - -MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 falcon"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h b/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h deleted file mode 100644 index e64601cc6b22..000000000000 --- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef UFS_QCOM_PHY_QMP_V3_FALCON_H_ -#define UFS_QCOM_PHY_QMP_V3_FALCON_H_ - -#include "phy-qcom-ufs-i.h" - -/* QCOM UFS PHY control registers */ -#define COM_BASE 0x000 -#define COM_OFF(x) (COM_BASE + x) -#define COM_SIZE 0x1C0 - -#define TX_BASE 0x400 -#define TX_OFF(x) (TX_BASE + x) -#define TX_SIZE 0x128 - -#define RX_BASE 0x600 -#define RX_OFF(x) (RX_BASE + x) -#define RX_SIZE 0x1FC - -#define PHY_BASE 0xC00 -#define PHY_OFF(x) (PHY_BASE + x) -#define PHY_SIZE 0x1B4 - -/* UFS PHY QSERDES COM registers */ -#define QSERDES_COM_ATB_SEL1 COM_OFF(0x00) -#define QSERDES_COM_ATB_SEL2 COM_OFF(0x04) -#define QSERDES_COM_FREQ_UPDATE COM_OFF(0x08) -#define QSERDES_COM_BG_TIMER COM_OFF(0x0C) -#define QSERDES_COM_SSC_EN_CENTER COM_OFF(0x10) -#define QSERDES_COM_SSC_ADJ_PER1 COM_OFF(0x14) -#define QSERDES_COM_SSC_ADJ_PER2 COM_OFF(0x18) -#define QSERDES_COM_SSC_PER1 COM_OFF(0x1C) -#define QSERDES_COM_SSC_PER2 COM_OFF(0x20) -#define QSERDES_COM_SSC_STEP_SIZE1 COM_OFF(0x24) -#define QSERDES_COM_SSC_STEP_SIZE2 COM_OFF(0x28) -#define QSERDES_COM_POST_DIV COM_OFF(0x2C) -#define QSERDES_COM_POST_DIV_MUX COM_OFF(0x30) -#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34) -#define QSERDES_COM_CLK_ENABLE1 COM_OFF(0x38) -#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C) -#define QSERDES_COM_SYSCLK_BUF_ENABLE COM_OFF(0x40) -#define QSERDES_COM_PLL_EN COM_OFF(0x44) -#define QSERDES_COM_PLL_IVCO COM_OFF(0x48) -#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0X4C) -#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0X50) -#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0X54) -#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0X58) -#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0X5C) -#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0X60) -#define QSERDES_COM_CMD_RSVD0 COM_OFF(0x64) -#define QSERDES_COM_EP_CLOCK_DETECT_CTRL COM_OFF(0x68) -#define QSERDES_COM_SYSCLK_DET_COMP_STATUS COM_OFF(0x6C) -#define QSERDES_COM_BG_TRIM COM_OFF(0x70) -#define QSERDES_COM_CLK_EP_DIV COM_OFF(0x74) -#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x78) -#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x7C) -#define QSERDES_COM_CMN_RSVD1 COM_OFF(0x80) -#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x84) -#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x88) -#define QSERDES_COM_CMN_RSVD2 COM_OFF(0x8C) -#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x90) -#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x94) -#define QSERDES_COM_CMN_RSVD3 COM_OFF(0x98) -#define QSERDES_COM_PLL_CNTRL COM_OFF(0x9C) -#define QSERDES_COM_PHASE_SEL_CTRL COM_OFF(0xA0) -#define QSERDES_COM_PHASE_SEL_DC COM_OFF(0xA4) -#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM COM_OFF(0xA8) -#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0xAC) -#define QSERDES_COM_CML_SYSCLK_SEL COM_OFF(0xB0) -#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0xB4) -#define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0xB8) -#define QSERDES_COM_RESTRIM_CTRL COM_OFF(0xBC) -#define QSERDES_COM_RESTRIM_CTRL2 COM_OFF(0xC0) -#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xC8) -#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0xCC) -#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xD0) -#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xD4) -#define QSERDES_COM_VCOCAL_DEADMAN_CTRL COM_OFF(0xD8) -#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xDC) -#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xE0) -#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xE4) -#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xE8) -#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xEC) -#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xF0) -#define QSERDES_COM_VCO_TUNE_MINVAL1 COM_OFF(0xF4) -#define QSERDES_COM_VCO_TUNE_MINVAL2 COM_OFF(0xF8) -#define QSERDES_COM_CMN_RSVD4 COM_OFF(0xFC) -#define QSERDES_COM_INTEGLOOP_INITVAL COM_OFF(0x100) -#define QSERDES_COM_INTEGLOOP_EN COM_OFF(0x104) -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0x108) -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0x10C) -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0x110) -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0x114) -#define QSERDES_COM_VCO_TUNE_MAXVAL1 COM_OFF(0x118) -#define QSERDES_COM_VCO_TUNE_MAXVAL2 COM_OFF(0x11C) -#define QSERDES_COM_RES_TRIM_CONTROL2 COM_OFF(0x120) -#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0x124) -#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x128) -#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0x12C) -#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0x130) -#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0x134) -#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x138) -#define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x13C) -#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x140) -#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x144) -#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x148) -#define QSERDES_COM_SAR COM_OFF(0x14C) -#define QSERDES_COM_SAR_CLK COM_OFF(0x150) -#define QSERDES_COM_SAR_CODE_OUT_STATUS COM_OFF(0x154) -#define QSERDES_COM_SAR_CODE_READY_STATUS COM_OFF(0x158) -#define QSERDES_COM_CMN_STATUS COM_OFF(0x15C) -#define QSERDES_COM_RESET_SM_STATUS COM_OFF(0x160) -#define QSERDES_COM_RESTRIM_CODE_STATUS COM_OFF(0x164) -#define QSERDES_COM_PLLCAL_CODE1_STATUS COM_OFF(0x168) -#define QSERDES_COM_PLLCAL_CODE2_STATUS COM_OFF(0x16C) -#define QSERDES_COM_BG_CTRL COM_OFF(0x170) -#define QSERDES_COM_CLK_SELECT COM_OFF(0x174) -#define QSERDES_COM_HSCLK_SEL COM_OFF(0x178) -#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS COM_OFF(0x17C) -#define QSERDES_COM_PLL_ANALOG COM_OFF(0x180) -#define QSERDES_COM_CORECLK_DIV COM_OFF(0x184) -#define QSERDES_COM_SW_RESET COM_OFF(0x188) -#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x18C) -#define QSERDES_COM_C_READY_STATUS COM_OFF(0x190) -#define QSERDES_COM_CMN_CONFIG COM_OFF(0x194) -#define QSERDES_COM_CMN_RATE_OVERRIDE COM_OFF(0x198) -#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x19C) -#define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x1A0) -#define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x1A4) -#define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x1A8) -#define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x1AC) -#define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x1B0) -#define QSERDES_COM_CMN_MISC1 COM_OFF(0x1B4) -#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC) -#define QSERDES_COM_CMN_RSVD5 COM_OFF(0x1C0) - -/* UFS PHY registers */ -#define UFS_PHY_PHY_START PHY_OFF(0x00) -#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04) -#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x34) -#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C) -#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC) -#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138) -#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x13C) -#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148) -#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154) -#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168) - -/* UFS PHY TX registers */ -#define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN TX_OFF(0x68) -#define QSERDES_TX_LANE_MODE TX_OFF(0x94) - -/* UFS PHY RX registers */ -#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF RX_OFF(0x30) -#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0x34) -#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH RX_OFF(0x38) -#define QSERDES_RX_UCDR_SVS_SO_GAIN RX_OFF(0x3C) -#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN RX_OFF(0x40) -#define QSERDES_RX_UCDR_SO_SATURATION_ENABLE RX_OFF(0x48) -#define QSERDES_RX_RX_TERM_BW RX_OFF(0x90) -#define QSERDES_RX_RX_EQ_GAIN1_LSB RX_OFF(0xC4) -#define QSERDES_RX_RX_EQ_GAIN1_MSB RX_OFF(0xC8) -#define QSERDES_RX_RX_EQ_GAIN2_LSB RX_OFF(0xCC) -#define QSERDES_RX_RX_EQ_GAIN2_MSB RX_OFF(0xD0) -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0xD8) -#define QSERDES_RX_SIGDET_CNTRL RX_OFF(0x114) -#define QSERDES_RX_SIGDET_LVL RX_OFF(0x118) -#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL RX_OFF(0x11C) -#define QSERDES_RX_RX_INTERFACE_MODE RX_OFF(0x12C) - - -#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) - -/* - * This structure represents the v3 falcon specific phy. - * common_cfg MUST remain the first field in this structure - * in case extra fields are added. This way, when calling - * get_ufs_qcom_phy() of generic phy, we can extract the - * common phy structure (struct ufs_qcom_phy) out of it - * regardless of the relevant specific phy. - */ -struct ufs_qcom_phy_qmp_v3_falcon { - struct ufs_qcom_phy common_cfg; -}; - -static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_3_1_1[] = { - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x14), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), - - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06), - - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), - - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), -}; - -static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44), -}; - -#endif diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 68546eec7f61..3f9f58f57393 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -112,13 +112,13 @@ config PINCTRL_MSM8996 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8996 platform. -config PINCTRL_MSMFALCON - tristate "Qualcomm MSMFALCON pin controller driver" +config PINCTRL_SDM660 + tristate "Qualcomm SDM660 pin controller driver" depends on GPIOLIB && OF select PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm MSMFALCON platform. + Qualcomm TLMM block found in the Qualcomm SDM660 platform. config PINCTRL_WCD tristate "Qualcomm Technologies, Inc WCD pin controller driver" diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index fa228c7243e2..502b91f455d7 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -14,6 +14,6 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o -obj-$(CONFIG_PINCTRL_MSMFALCON) += pinctrl-msmfalcon.o +obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_WCD) += pinctrl-wcd.o obj-$(CONFIG_PINCTRL_LPI) += pinctrl-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c b/drivers/pinctrl/qcom/pinctrl-msmfalcon.c deleted file mode 100644 index 91bbce2ce1d1..000000000000 --- a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c +++ /dev/null @@ -1,1722 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -#define FUNCTION(fname) \ - [msm_mux_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define NORTH 0x00900000 -#define CENTER 0x00500000 -#define SOUTH 0x00100000 -#define REG_SIZE 0x1000 -#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - msm_mux_gpio, /* gpio mode */ \ - msm_mux_##f1, \ - msm_mux_##f2, \ - msm_mux_##f3, \ - msm_mux_##f4, \ - msm_mux_##f5, \ - msm_mux_##f6, \ - msm_mux_##f7, \ - msm_mux_##f8, \ - msm_mux_##f9 \ - }, \ - .nfuncs = 10, \ - .ctl_reg = base + REG_SIZE * id, \ - .io_reg = base + 0x4 + REG_SIZE * id, \ - .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ - .intr_status_reg = base + 0xc + REG_SIZE * id, \ - .intr_target_reg = base + 0x8 + REG_SIZE * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_target_bit = 5, \ - .intr_target_kpss_val = 3, \ - .intr_raw_status_bit = 4, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 2, \ - } - -#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } -static const struct pinctrl_pin_desc msmfalcon_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - PINCTRL_PIN(69, "GPIO_69"), - PINCTRL_PIN(70, "GPIO_70"), - PINCTRL_PIN(71, "GPIO_71"), - PINCTRL_PIN(72, "GPIO_72"), - PINCTRL_PIN(73, "GPIO_73"), - PINCTRL_PIN(74, "GPIO_74"), - PINCTRL_PIN(75, "GPIO_75"), - PINCTRL_PIN(76, "GPIO_76"), - PINCTRL_PIN(77, "GPIO_77"), - PINCTRL_PIN(78, "GPIO_78"), - PINCTRL_PIN(79, "GPIO_79"), - PINCTRL_PIN(80, "GPIO_80"), - PINCTRL_PIN(81, "GPIO_81"), - PINCTRL_PIN(82, "GPIO_82"), - PINCTRL_PIN(83, "GPIO_83"), - PINCTRL_PIN(84, "GPIO_84"), - PINCTRL_PIN(85, "GPIO_85"), - PINCTRL_PIN(86, "GPIO_86"), - PINCTRL_PIN(87, "GPIO_87"), - PINCTRL_PIN(88, "GPIO_88"), - PINCTRL_PIN(89, "GPIO_89"), - PINCTRL_PIN(90, "GPIO_90"), - PINCTRL_PIN(91, "GPIO_91"), - PINCTRL_PIN(92, "GPIO_92"), - PINCTRL_PIN(93, "GPIO_93"), - PINCTRL_PIN(94, "GPIO_94"), - PINCTRL_PIN(95, "GPIO_95"), - PINCTRL_PIN(96, "GPIO_96"), - PINCTRL_PIN(97, "GPIO_97"), - PINCTRL_PIN(98, "GPIO_98"), - PINCTRL_PIN(99, "GPIO_99"), - PINCTRL_PIN(100, "GPIO_100"), - PINCTRL_PIN(101, "GPIO_101"), - PINCTRL_PIN(102, "GPIO_102"), - PINCTRL_PIN(103, "GPIO_103"), - PINCTRL_PIN(104, "GPIO_104"), - PINCTRL_PIN(105, "GPIO_105"), - PINCTRL_PIN(106, "GPIO_106"), - PINCTRL_PIN(107, "GPIO_107"), - PINCTRL_PIN(108, "GPIO_108"), - PINCTRL_PIN(109, "GPIO_109"), - PINCTRL_PIN(110, "GPIO_110"), - PINCTRL_PIN(111, "GPIO_111"), - PINCTRL_PIN(112, "GPIO_112"), - PINCTRL_PIN(113, "GPIO_113"), - PINCTRL_PIN(114, "SDC1_CLK"), - PINCTRL_PIN(115, "SDC1_CMD"), - PINCTRL_PIN(116, "SDC1_DATA"), - PINCTRL_PIN(117, "SDC2_CLK"), - PINCTRL_PIN(118, "SDC2_CMD"), - PINCTRL_PIN(119, "SDC2_DATA"), - PINCTRL_PIN(120, "SDC1_RCLK"), -}; - -#define DECLARE_MSM_GPIO_PINS(pin) \ - static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_MSM_GPIO_PINS(0); -DECLARE_MSM_GPIO_PINS(1); -DECLARE_MSM_GPIO_PINS(2); -DECLARE_MSM_GPIO_PINS(3); -DECLARE_MSM_GPIO_PINS(4); -DECLARE_MSM_GPIO_PINS(5); -DECLARE_MSM_GPIO_PINS(6); -DECLARE_MSM_GPIO_PINS(7); -DECLARE_MSM_GPIO_PINS(8); -DECLARE_MSM_GPIO_PINS(9); -DECLARE_MSM_GPIO_PINS(10); -DECLARE_MSM_GPIO_PINS(11); -DECLARE_MSM_GPIO_PINS(12); -DECLARE_MSM_GPIO_PINS(13); -DECLARE_MSM_GPIO_PINS(14); -DECLARE_MSM_GPIO_PINS(15); -DECLARE_MSM_GPIO_PINS(16); -DECLARE_MSM_GPIO_PINS(17); -DECLARE_MSM_GPIO_PINS(18); -DECLARE_MSM_GPIO_PINS(19); -DECLARE_MSM_GPIO_PINS(20); -DECLARE_MSM_GPIO_PINS(21); -DECLARE_MSM_GPIO_PINS(22); -DECLARE_MSM_GPIO_PINS(23); -DECLARE_MSM_GPIO_PINS(24); -DECLARE_MSM_GPIO_PINS(25); -DECLARE_MSM_GPIO_PINS(26); -DECLARE_MSM_GPIO_PINS(27); -DECLARE_MSM_GPIO_PINS(28); -DECLARE_MSM_GPIO_PINS(29); -DECLARE_MSM_GPIO_PINS(30); -DECLARE_MSM_GPIO_PINS(31); -DECLARE_MSM_GPIO_PINS(32); -DECLARE_MSM_GPIO_PINS(33); -DECLARE_MSM_GPIO_PINS(34); -DECLARE_MSM_GPIO_PINS(35); -DECLARE_MSM_GPIO_PINS(36); -DECLARE_MSM_GPIO_PINS(37); -DECLARE_MSM_GPIO_PINS(38); -DECLARE_MSM_GPIO_PINS(39); -DECLARE_MSM_GPIO_PINS(40); -DECLARE_MSM_GPIO_PINS(41); -DECLARE_MSM_GPIO_PINS(42); -DECLARE_MSM_GPIO_PINS(43); -DECLARE_MSM_GPIO_PINS(44); -DECLARE_MSM_GPIO_PINS(45); -DECLARE_MSM_GPIO_PINS(46); -DECLARE_MSM_GPIO_PINS(47); -DECLARE_MSM_GPIO_PINS(48); -DECLARE_MSM_GPIO_PINS(49); -DECLARE_MSM_GPIO_PINS(50); -DECLARE_MSM_GPIO_PINS(51); -DECLARE_MSM_GPIO_PINS(52); -DECLARE_MSM_GPIO_PINS(53); -DECLARE_MSM_GPIO_PINS(54); -DECLARE_MSM_GPIO_PINS(55); -DECLARE_MSM_GPIO_PINS(56); -DECLARE_MSM_GPIO_PINS(57); -DECLARE_MSM_GPIO_PINS(58); -DECLARE_MSM_GPIO_PINS(59); -DECLARE_MSM_GPIO_PINS(60); -DECLARE_MSM_GPIO_PINS(61); -DECLARE_MSM_GPIO_PINS(62); -DECLARE_MSM_GPIO_PINS(63); -DECLARE_MSM_GPIO_PINS(64); -DECLARE_MSM_GPIO_PINS(65); -DECLARE_MSM_GPIO_PINS(66); -DECLARE_MSM_GPIO_PINS(67); -DECLARE_MSM_GPIO_PINS(68); -DECLARE_MSM_GPIO_PINS(69); -DECLARE_MSM_GPIO_PINS(70); -DECLARE_MSM_GPIO_PINS(71); -DECLARE_MSM_GPIO_PINS(72); -DECLARE_MSM_GPIO_PINS(73); -DECLARE_MSM_GPIO_PINS(74); -DECLARE_MSM_GPIO_PINS(75); -DECLARE_MSM_GPIO_PINS(76); -DECLARE_MSM_GPIO_PINS(77); -DECLARE_MSM_GPIO_PINS(78); -DECLARE_MSM_GPIO_PINS(79); -DECLARE_MSM_GPIO_PINS(80); -DECLARE_MSM_GPIO_PINS(81); -DECLARE_MSM_GPIO_PINS(82); -DECLARE_MSM_GPIO_PINS(83); -DECLARE_MSM_GPIO_PINS(84); -DECLARE_MSM_GPIO_PINS(85); -DECLARE_MSM_GPIO_PINS(86); -DECLARE_MSM_GPIO_PINS(87); -DECLARE_MSM_GPIO_PINS(88); -DECLARE_MSM_GPIO_PINS(89); -DECLARE_MSM_GPIO_PINS(90); -DECLARE_MSM_GPIO_PINS(91); -DECLARE_MSM_GPIO_PINS(92); -DECLARE_MSM_GPIO_PINS(93); -DECLARE_MSM_GPIO_PINS(94); -DECLARE_MSM_GPIO_PINS(95); -DECLARE_MSM_GPIO_PINS(96); -DECLARE_MSM_GPIO_PINS(97); -DECLARE_MSM_GPIO_PINS(98); -DECLARE_MSM_GPIO_PINS(99); -DECLARE_MSM_GPIO_PINS(100); -DECLARE_MSM_GPIO_PINS(101); -DECLARE_MSM_GPIO_PINS(102); -DECLARE_MSM_GPIO_PINS(103); -DECLARE_MSM_GPIO_PINS(104); -DECLARE_MSM_GPIO_PINS(105); -DECLARE_MSM_GPIO_PINS(106); -DECLARE_MSM_GPIO_PINS(107); -DECLARE_MSM_GPIO_PINS(108); -DECLARE_MSM_GPIO_PINS(109); -DECLARE_MSM_GPIO_PINS(110); -DECLARE_MSM_GPIO_PINS(111); -DECLARE_MSM_GPIO_PINS(112); -DECLARE_MSM_GPIO_PINS(113); - -static const unsigned int sdc1_clk_pins[] = { 114 }; -static const unsigned int sdc1_cmd_pins[] = { 115 }; -static const unsigned int sdc1_data_pins[] = { 116 }; -static const unsigned int sdc2_clk_pins[] = { 117 }; -static const unsigned int sdc2_cmd_pins[] = { 118 }; -static const unsigned int sdc2_data_pins[] = { 119 }; -static const unsigned int sdc1_rclk_pins[] = { 120 }; - -enum msmfalcon_functions { - msm_mux_blsp_spi1, - msm_mux_gpio, - msm_mux_blsp_uim1, - msm_mux_tgu_ch0, - msm_mux_qdss_gpio4, - msm_mux_atest_gpsadc1, - msm_mux_blsp_uart1, - msm_mux_SMB_STAT, - msm_mux_phase_flag14, - msm_mux_blsp_i2c2, - msm_mux_phase_flag31, - msm_mux_blsp_spi3, - msm_mux_blsp_spi3_cs1, - msm_mux_blsp_spi3_cs2, - msm_mux_wlan1_adc1, - msm_mux_atest_usb13, - msm_mux_tgu_ch1, - msm_mux_qdss_gpio5, - msm_mux_atest_gpsadc0, - msm_mux_blsp_i2c1, - msm_mux_ddr_bist, - msm_mux_atest_tsens2, - msm_mux_atest_usb1, - msm_mux_blsp_spi2, - msm_mux_blsp_uim2, - msm_mux_phase_flag3, - msm_mux_bimc_dte1, - msm_mux_wlan1_adc0, - msm_mux_atest_usb12, - msm_mux_bimc_dte0, - msm_mux_blsp_i2c3, - msm_mux_wlan2_adc1, - msm_mux_atest_usb11, - msm_mux_dbg_out, - msm_mux_wlan2_adc0, - msm_mux_atest_usb10, - msm_mux_RCM_MARKER, - msm_mux_blsp_spi4, - msm_mux_pri_mi2s, - msm_mux_phase_flag26, - msm_mux_qdss_cti0_a, - msm_mux_qdss_cti0_b, - msm_mux_qdss_cti1_a, - msm_mux_qdss_cti1_b, - msm_mux_DP_HOT, - msm_mux_pri_mi2s_ws, - msm_mux_phase_flag27, - msm_mux_blsp_i2c4, - msm_mux_phase_flag28, - msm_mux_blsp_uart5, - msm_mux_blsp_spi5, - msm_mux_blsp_uim5, - msm_mux_phase_flag5, - msm_mux_blsp_i2c5, - msm_mux_blsp_spi6, - msm_mux_blsp_uart2, - msm_mux_blsp_uim6, - msm_mux_phase_flag11, - msm_mux_vsense_data0, - msm_mux_blsp_i2c6, - msm_mux_phase_flag12, - msm_mux_vsense_data1, - msm_mux_phase_flag13, - msm_mux_vsense_mode, - msm_mux_blsp_spi7, - msm_mux_blsp_uart6_a, - msm_mux_blsp_uart6_b, - msm_mux_sec_mi2s, - msm_mux_sndwire_clk, - msm_mux_phase_flag17, - msm_mux_vsense_clkout, - msm_mux_sndwire_data, - msm_mux_phase_flag18, - msm_mux_WSA_SPKR, - msm_mux_blsp_i2c7, - msm_mux_phase_flag19, - msm_mux_vfr_1, - msm_mux_phase_flag20, - msm_mux_NFC_INT, - msm_mux_blsp_spi8_cs1, - msm_mux_blsp_spi8_cs2, - msm_mux_m_voc, - msm_mux_phase_flag21, - msm_mux_NFC_EN, - msm_mux_phase_flag22, - msm_mux_NFC_DWL, - msm_mux_blsp_i2c8_a, - msm_mux_blsp_i2c8_b, - msm_mux_phase_flag23, - msm_mux_NFC_ESE, - msm_mux_pwr_modem, - msm_mux_phase_flag24, - msm_mux_qdss_gpio, - msm_mux_cam_mclk, - msm_mux_pwr_nav, - msm_mux_qdss_gpio0, - msm_mux_qspi_data0, - msm_mux_pwr_crypto, - msm_mux_qdss_gpio1, - msm_mux_qspi_data1, - msm_mux_agera_pll, - msm_mux_qdss_gpio2, - msm_mux_qspi_data2, - msm_mux_jitter_bist, - msm_mux_qdss_gpio3, - msm_mux_qdss_gpio7, - msm_mux_FL_R3LED, - msm_mux_CCI_TIMER0, - msm_mux_FL_STROBE, - msm_mux_CCI_TIMER1, - msm_mux_CAM_LDO1, - msm_mux_mdss_vsync0, - msm_mux_mdss_vsync1, - msm_mux_mdss_vsync2, - msm_mux_mdss_vsync3, - msm_mux_qdss_gpio9, - msm_mux_CAM_IRQ, - msm_mux_atest_usb2, - msm_mux_cci_i2c, - msm_mux_pll_bypassnl, - msm_mux_atest_tsens, - msm_mux_atest_usb21, - msm_mux_pll_reset, - msm_mux_atest_usb23, - msm_mux_qdss_gpio6, - msm_mux_CCI_TIMER3, - msm_mux_CCI_ASYNC, - msm_mux_qspi_cs, - msm_mux_qdss_gpio10, - msm_mux_CAM3_STANDBY, - msm_mux_CCI_TIMER4, - msm_mux_qdss_gpio11, - msm_mux_CAM_LDO2, - msm_mux_cci_async, - msm_mux_qdss_gpio12, - msm_mux_CAM0_RST, - msm_mux_qdss_gpio13, - msm_mux_CAM1_RST, - msm_mux_qspi_clk, - msm_mux_phase_flag30, - msm_mux_qdss_gpio14, - msm_mux_qspi_resetn, - msm_mux_phase_flag1, - msm_mux_qdss_gpio15, - msm_mux_CAM0_STANDBY, - msm_mux_phase_flag2, - msm_mux_CAM1_STANDBY, - msm_mux_phase_flag9, - msm_mux_CAM2_STANDBY, - msm_mux_qspi_data3, - msm_mux_phase_flag15, - msm_mux_qdss_gpio8, - msm_mux_CAM3_RST, - msm_mux_CCI_TIMER2, - msm_mux_phase_flag16, - msm_mux_LCD0_RESET, - msm_mux_phase_flag6, - msm_mux_SD_CARD, - msm_mux_phase_flag29, - msm_mux_DP_EN, - msm_mux_phase_flag25, - msm_mux_USBC_ORIENTATION, - msm_mux_phase_flag10, - msm_mux_atest_usb20, - msm_mux_gcc_gp1, - msm_mux_phase_flag4, - msm_mux_atest_usb22, - msm_mux_USB_PHY, - msm_mux_gcc_gp2, - msm_mux_atest_char, - msm_mux_mdp_vsync, - msm_mux_gcc_gp3, - msm_mux_atest_char3, - msm_mux_FORCE_TOUCH, - msm_mux_cri_trng0, - msm_mux_atest_char2, - msm_mux_cri_trng1, - msm_mux_atest_char1, - msm_mux_AUDIO_USBC, - msm_mux_audio_ref, - msm_mux_MDP_VSYNC, - msm_mux_cri_trng, - msm_mux_atest_char0, - msm_mux_US_EURO, - msm_mux_LCD_BACKLIGHT, - msm_mux_blsp_spi8_a, - msm_mux_blsp_spi8_b, - msm_mux_sp_cmu, - msm_mux_nav_pps_a, - msm_mux_nav_pps_b, - msm_mux_nav_pps_c, - msm_mux_gps_tx_a, - msm_mux_gps_tx_b, - msm_mux_gps_tx_c, - msm_mux_adsp_ext, - msm_mux_TS_RESET, - msm_mux_ssc_irq, - msm_mux_isense_dbg, - msm_mux_phase_flag0, - msm_mux_phase_flag7, - msm_mux_phase_flag8, - msm_mux_tsense_pwm1, - msm_mux_tsense_pwm2, - msm_mux_SENSOR_RST, - msm_mux_WMSS_RESETN, - msm_mux_HAPTICS_PWM, - msm_mux_GPS_eLNA, - msm_mux_mss_lte, - msm_mux_uim2_data, - msm_mux_uim2_clk, - msm_mux_uim2_reset, - msm_mux_uim2_present, - msm_mux_uim1_data, - msm_mux_uim1_clk, - msm_mux_uim1_reset, - msm_mux_uim1_present, - msm_mux_uim_batt, - msm_mux_pa_indicator, - msm_mux_ldo_en, - msm_mux_ldo_update, - msm_mux_qlink_request, - msm_mux_qlink_enable, - msm_mux_prng_rosc, - msm_mux_LCD_PWR, - msm_mux_NA, -}; - -static const char * const blsp_spi1_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3", "gpio46", -}; -static const char * const gpio_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", - "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", - "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", - "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", - "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", - "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", - "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", - "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", - "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", - "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", - "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", - "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", - "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", - "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", - "gpio111", "gpio112", "gpio113", -}; -static const char * const blsp_uim1_groups[] = { - "gpio0", "gpio1", -}; -static const char * const tgu_ch0_groups[] = { - "gpio0", -}; -static const char * const qdss_gpio4_groups[] = { - "gpio0", "gpio36", -}; -static const char * const atest_gpsadc1_groups[] = { - "gpio0", -}; -static const char * const blsp_uart1_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3", -}; -static const char * const SMB_STAT_groups[] = { - "gpio5", -}; -static const char * const phase_flag14_groups[] = { - "gpio5", -}; -static const char * const blsp_i2c2_groups[] = { - "gpio6", "gpio7", -}; -static const char * const phase_flag31_groups[] = { - "gpio6", -}; -static const char * const blsp_spi3_groups[] = { - "gpio8", "gpio9", "gpio10", "gpio11", -}; -static const char * const blsp_spi3_cs1_groups[] = { - "gpio30", -}; -static const char * const blsp_spi3_cs2_groups[] = { - "gpio65", -}; -static const char * const wlan1_adc1_groups[] = { - "gpio8", -}; -static const char * const atest_usb13_groups[] = { - "gpio8", -}; -static const char * const tgu_ch1_groups[] = { - "gpio1", -}; -static const char * const qdss_gpio5_groups[] = { - "gpio1", "gpio37", -}; -static const char * const atest_gpsadc0_groups[] = { - "gpio1", -}; -static const char * const blsp_i2c1_groups[] = { - "gpio2", "gpio3", -}; -static const char * const ddr_bist_groups[] = { - "gpio3", "gpio8", "gpio9", "gpio10", -}; -static const char * const atest_tsens2_groups[] = { - "gpio3", -}; -static const char * const atest_usb1_groups[] = { - "gpio3", -}; -static const char * const blsp_spi2_groups[] = { - "gpio4", "gpio5", "gpio6", "gpio7", -}; -static const char * const blsp_uim2_groups[] = { - "gpio4", "gpio5", -}; -static const char * const phase_flag3_groups[] = { - "gpio4", -}; -static const char * const bimc_dte1_groups[] = { - "gpio8", "gpio10", -}; -static const char * const wlan1_adc0_groups[] = { - "gpio9", -}; -static const char * const atest_usb12_groups[] = { - "gpio9", -}; -static const char * const bimc_dte0_groups[] = { - "gpio9", "gpio11", -}; -static const char * const blsp_i2c3_groups[] = { - "gpio10", "gpio11", -}; -static const char * const wlan2_adc1_groups[] = { - "gpio10", -}; -static const char * const atest_usb11_groups[] = { - "gpio10", -}; -static const char * const dbg_out_groups[] = { - "gpio11", -}; -static const char * const wlan2_adc0_groups[] = { - "gpio11", -}; -static const char * const atest_usb10_groups[] = { - "gpio11", -}; -static const char * const RCM_MARKER_groups[] = { - "gpio12", "gpio13", -}; -static const char * const blsp_spi4_groups[] = { - "gpio12", "gpio13", "gpio14", "gpio15", -}; -static const char * const pri_mi2s_groups[] = { - "gpio12", "gpio14", "gpio15", "gpio61", -}; -static const char * const phase_flag26_groups[] = { - "gpio12", -}; -static const char * const qdss_cti0_a_groups[] = { - "gpio49", "gpio50", -}; -static const char * const qdss_cti0_b_groups[] = { - "gpio13", "gpio21", -}; -static const char * const qdss_cti1_a_groups[] = { - "gpio53", "gpio55", -}; -static const char * const qdss_cti1_b_groups[] = { - "gpio12", "gpio66", -}; -static const char * const DP_HOT_groups[] = { - "gpio13", -}; -static const char * const pri_mi2s_ws_groups[] = { - "gpio13", -}; -static const char * const phase_flag27_groups[] = { - "gpio13", -}; -static const char * const blsp_i2c4_groups[] = { - "gpio14", "gpio15", -}; -static const char * const phase_flag28_groups[] = { - "gpio14", -}; -static const char * const blsp_uart5_groups[] = { - "gpio16", "gpio17", "gpio18", "gpio19", -}; -static const char * const blsp_spi5_groups[] = { - "gpio16", "gpio17", "gpio18", "gpio19", -}; -static const char * const blsp_uim5_groups[] = { - "gpio16", "gpio17", -}; -static const char * const phase_flag5_groups[] = { - "gpio17", -}; -static const char * const blsp_i2c5_groups[] = { - "gpio18", "gpio19", -}; -static const char * const blsp_spi6_groups[] = { - "gpio49", "gpio52", "gpio22", "gpio23", -}; -static const char * const blsp_uart2_groups[] = { - "gpio4", "gpio5", "gpio6", "gpio7", -}; -static const char * const blsp_uim6_groups[] = { - "gpio20", "gpio21", -}; -static const char * const phase_flag11_groups[] = { - "gpio21", -}; -static const char * const vsense_data0_groups[] = { - "gpio21", -}; -static const char * const blsp_i2c6_groups[] = { - "gpio22", "gpio23", -}; -static const char * const phase_flag12_groups[] = { - "gpio22", -}; -static const char * const vsense_data1_groups[] = { - "gpio22", -}; -static const char * const phase_flag13_groups[] = { - "gpio23", -}; -static const char * const vsense_mode_groups[] = { - "gpio23", -}; -static const char * const blsp_spi7_groups[] = { - "gpio24", "gpio25", "gpio26", "gpio27", -}; -static const char * const blsp_uart6_a_groups[] = { - "gpio24", "gpio25", "gpio26", "gpio27", -}; -static const char * const blsp_uart6_b_groups[] = { - "gpio28", "gpio29", "gpio30", "gpio31", -}; -static const char * const sec_mi2s_groups[] = { - "gpio24", "gpio25", "gpio26", "gpio27", "gpio62", -}; -static const char * const sndwire_clk_groups[] = { - "gpio24", -}; -static const char * const phase_flag17_groups[] = { - "gpio24", -}; -static const char * const vsense_clkout_groups[] = { - "gpio24", -}; -static const char * const sndwire_data_groups[] = { - "gpio25", -}; -static const char * const phase_flag18_groups[] = { - "gpio25", -}; -static const char * const WSA_SPKR_groups[] = { - "gpio26", "gpio27", -}; -static const char * const blsp_i2c7_groups[] = { - "gpio26", "gpio27", -}; -static const char * const phase_flag19_groups[] = { - "gpio26", -}; -static const char * const vfr_1_groups[] = { - "gpio27", -}; -static const char * const phase_flag20_groups[] = { - "gpio27", -}; -static const char * const NFC_INT_groups[] = { - "gpio28", -}; -static const char * const blsp_spi8_a_groups[] = { - "gpio28", "gpio29", "gpio30", "gpio31", -}; -static const char * const blsp_spi8_b_groups[] = { - "gpio40", "gpio41", "gpio44", "gpio52", -}; -static const char * const m_voc_groups[] = { - "gpio28", -}; -static const char * const phase_flag21_groups[] = { - "gpio28", -}; -static const char * const NFC_EN_groups[] = { - "gpio29", -}; -static const char * const phase_flag22_groups[] = { - "gpio29", -}; -static const char * const NFC_DWL_groups[] = { - "gpio30", -}; -static const char * const blsp_i2c8_a_groups[] = { - "gpio30", "gpio31", -}; -static const char * const blsp_i2c8_b_groups[] = { - "gpio44", "gpio52", -}; -static const char * const phase_flag23_groups[] = { - "gpio30", -}; -static const char * const NFC_ESE_groups[] = { - "gpio31", -}; -static const char * const pwr_modem_groups[] = { - "gpio31", -}; -static const char * const phase_flag24_groups[] = { - "gpio31", -}; -static const char * const qdss_gpio_groups[] = { - "gpio31", "gpio52", "gpio68", "gpio69", -}; -static const char * const cam_mclk_groups[] = { - "gpio32", "gpio33", "gpio34", "gpio35", -}; -static const char * const pwr_nav_groups[] = { - "gpio32", -}; -static const char * const qdss_gpio0_groups[] = { - "gpio32", "gpio67", -}; -static const char * const qspi_data0_groups[] = { - "gpio33", -}; -static const char * const pwr_crypto_groups[] = { - "gpio33", -}; -static const char * const qdss_gpio1_groups[] = { - "gpio33", "gpio63", -}; -static const char * const qspi_data1_groups[] = { - "gpio34", -}; -static const char * const agera_pll_groups[] = { - "gpio34", "gpio36", -}; -static const char * const qdss_gpio2_groups[] = { - "gpio34", "gpio64", -}; -static const char * const qspi_data2_groups[] = { - "gpio35", -}; -static const char * const jitter_bist_groups[] = { - "gpio35", -}; -static const char * const qdss_gpio3_groups[] = { - "gpio35", "gpio56", -}; -static const char * const qdss_gpio7_groups[] = { - "gpio39", "gpio71", -}; -static const char * const FL_R3LED_groups[] = { - "gpio40", -}; -static const char * const CCI_TIMER0_groups[] = { - "gpio40", -}; -static const char * const FL_STROBE_groups[] = { - "gpio41", -}; -static const char * const CCI_TIMER1_groups[] = { - "gpio41", -}; -static const char * const CAM_LDO1_groups[] = { - "gpio42", -}; -static const char * const mdss_vsync0_groups[] = { - "gpio42", -}; -static const char * const mdss_vsync1_groups[] = { - "gpio42", -}; -static const char * const mdss_vsync2_groups[] = { - "gpio42", -}; -static const char * const mdss_vsync3_groups[] = { - "gpio42", -}; -static const char * const qdss_gpio9_groups[] = { - "gpio42", "gpio76", -}; -static const char * const CAM_IRQ_groups[] = { - "gpio43", -}; -static const char * const atest_usb2_groups[] = { - "gpio35", -}; -static const char * const cci_i2c_groups[] = { - "gpio36", "gpio37", "gpio38", "gpio39", -}; -static const char * const pll_bypassnl_groups[] = { - "gpio36", -}; -static const char * const atest_tsens_groups[] = { - "gpio36", -}; -static const char * const atest_usb21_groups[] = { - "gpio36", -}; -static const char * const pll_reset_groups[] = { - "gpio37", -}; -static const char * const atest_usb23_groups[] = { - "gpio37", -}; -static const char * const qdss_gpio6_groups[] = { - "gpio38", "gpio70", -}; -static const char * const CCI_TIMER3_groups[] = { - "gpio43", -}; -static const char * const CCI_ASYNC_groups[] = { - "gpio43", "gpio44", -}; -static const char * const qspi_cs_groups[] = { - "gpio43", "gpio50", -}; -static const char * const qdss_gpio10_groups[] = { - "gpio43", "gpio77", -}; -static const char * const CAM3_STANDBY_groups[] = { - "gpio44", -}; -static const char * const CCI_TIMER4_groups[] = { - "gpio44", -}; -static const char * const qdss_gpio11_groups[] = { - "gpio44", "gpio79", -}; -static const char * const CAM_LDO2_groups[] = { - "gpio45", -}; -static const char * const cci_async_groups[] = { - "gpio45", -}; -static const char * const qdss_gpio12_groups[] = { - "gpio45", "gpio80", -}; -static const char * const CAM0_RST_groups[] = { - "gpio46", -}; -static const char * const qdss_gpio13_groups[] = { - "gpio46", "gpio78", -}; -static const char * const CAM1_RST_groups[] = { - "gpio47", -}; -static const char * const qspi_clk_groups[] = { - "gpio47", -}; -static const char * const phase_flag30_groups[] = { - "gpio47", -}; -static const char * const qdss_gpio14_groups[] = { - "gpio47", "gpio72", -}; -static const char * const qspi_resetn_groups[] = { - "gpio48", -}; -static const char * const phase_flag1_groups[] = { - "gpio48", -}; -static const char * const qdss_gpio15_groups[] = { - "gpio48", "gpio73", -}; -static const char * const CAM0_STANDBY_groups[] = { - "gpio49", -}; -static const char * const phase_flag2_groups[] = { - "gpio49", -}; -static const char * const CAM1_STANDBY_groups[] = { - "gpio50", -}; -static const char * const phase_flag9_groups[] = { - "gpio50", -}; -static const char * const CAM2_STANDBY_groups[] = { - "gpio51", -}; -static const char * const qspi_data3_groups[] = { - "gpio51", -}; -static const char * const phase_flag15_groups[] = { - "gpio51", -}; -static const char * const qdss_gpio8_groups[] = { - "gpio51", "gpio75", -}; -static const char * const CAM3_RST_groups[] = { - "gpio52", -}; -static const char * const CCI_TIMER2_groups[] = { - "gpio52", -}; -static const char * const phase_flag16_groups[] = { - "gpio52", -}; -static const char * const LCD0_RESET_groups[] = { - "gpio53", -}; -static const char * const phase_flag6_groups[] = { - "gpio53", -}; -static const char * const SD_CARD_groups[] = { - "gpio54", -}; -static const char * const phase_flag29_groups[] = { - "gpio54", -}; -static const char * const DP_EN_groups[] = { - "gpio55", -}; -static const char * const phase_flag25_groups[] = { - "gpio55", -}; -static const char * const USBC_ORIENTATION_groups[] = { - "gpio56", -}; -static const char * const phase_flag10_groups[] = { - "gpio56", -}; -static const char * const atest_usb20_groups[] = { - "gpio56", -}; -static const char * const gcc_gp1_groups[] = { - "gpio57", "gpio78", -}; -static const char * const phase_flag4_groups[] = { - "gpio57", -}; -static const char * const atest_usb22_groups[] = { - "gpio57", -}; -static const char * const USB_PHY_groups[] = { - "gpio58", -}; -static const char * const gcc_gp2_groups[] = { - "gpio58", "gpio81", -}; -static const char * const atest_char_groups[] = { - "gpio58", -}; -static const char * const mdp_vsync_groups[] = { - "gpio59", "gpio74", -}; -static const char * const gcc_gp3_groups[] = { - "gpio59", "gpio82", -}; -static const char * const atest_char3_groups[] = { - "gpio59", -}; -static const char * const FORCE_TOUCH_groups[] = { - "gpio60", "gpio73", -}; -static const char * const cri_trng0_groups[] = { - "gpio60", -}; -static const char * const atest_char2_groups[] = { - "gpio60", -}; -static const char * const cri_trng1_groups[] = { - "gpio61", -}; -static const char * const atest_char1_groups[] = { - "gpio61", -}; -static const char * const AUDIO_USBC_groups[] = { - "gpio62", -}; -static const char * const audio_ref_groups[] = { - "gpio62", -}; -static const char * const MDP_VSYNC_groups[] = { - "gpio62", -}; -static const char * const cri_trng_groups[] = { - "gpio62", -}; -static const char * const atest_char0_groups[] = { - "gpio62", -}; -static const char * const US_EURO_groups[] = { - "gpio63", -}; -static const char * const LCD_BACKLIGHT_groups[] = { - "gpio64", -}; -static const char * const blsp_spi8_cs1_groups[] = { - "gpio64", -}; -static const char * const blsp_spi8_cs2_groups[] = { - "gpio76", -}; -static const char * const sp_cmu_groups[] = { - "gpio64", -}; -static const char * const nav_pps_a_groups[] = { - "gpio65", -}; -static const char * const nav_pps_b_groups[] = { - "gpio98", -}; -static const char * const nav_pps_c_groups[] = { - "gpio80", -}; -static const char * const gps_tx_a_groups[] = { - "gpio65", -}; -static const char * const gps_tx_b_groups[] = { - "gpio98", -}; -static const char * const gps_tx_c_groups[] = { - "gpio80", -}; -static const char * const adsp_ext_groups[] = { - "gpio65", -}; -static const char * const TS_RESET_groups[] = { - "gpio66", -}; -static const char * const ssc_irq_groups[] = { - "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio74", - "gpio75", "gpio76", -}; -static const char * const isense_dbg_groups[] = { - "gpio68", -}; -static const char * const phase_flag0_groups[] = { - "gpio68", -}; -static const char * const phase_flag7_groups[] = { - "gpio69", -}; -static const char * const phase_flag8_groups[] = { - "gpio70", -}; -static const char * const tsense_pwm1_groups[] = { - "gpio71", -}; -static const char * const tsense_pwm2_groups[] = { - "gpio71", -}; -static const char * const SENSOR_RST_groups[] = { - "gpio77", -}; -static const char * const WMSS_RESETN_groups[] = { - "gpio78", -}; -static const char * const HAPTICS_PWM_groups[] = { - "gpio79", -}; -static const char * const GPS_eLNA_groups[] = { - "gpio80", -}; -static const char * const mss_lte_groups[] = { - "gpio81", "gpio82", -}; -static const char * const uim2_data_groups[] = { - "gpio83", -}; -static const char * const uim2_clk_groups[] = { - "gpio84", -}; -static const char * const uim2_reset_groups[] = { - "gpio85", -}; -static const char * const uim2_present_groups[] = { - "gpio86", -}; -static const char * const uim1_data_groups[] = { - "gpio87", -}; -static const char * const uim1_clk_groups[] = { - "gpio88", -}; -static const char * const uim1_reset_groups[] = { - "gpio89", -}; -static const char * const uim1_present_groups[] = { - "gpio90", -}; -static const char * const uim_batt_groups[] = { - "gpio91", -}; -static const char * const pa_indicator_groups[] = { - "gpio92", -}; -static const char * const ldo_en_groups[] = { - "gpio97", -}; -static const char * const ldo_update_groups[] = { - "gpio98", -}; -static const char * const qlink_request_groups[] = { - "gpio99", -}; -static const char * const qlink_enable_groups[] = { - "gpio100", -}; -static const char * const prng_rosc_groups[] = { - "gpio102", -}; -static const char * const LCD_PWR_groups[] = { - "gpio113", -}; - -static const struct msm_function msmfalcon_functions[] = { - FUNCTION(blsp_spi1), - FUNCTION(gpio), - FUNCTION(blsp_uim1), - FUNCTION(tgu_ch0), - FUNCTION(qdss_gpio4), - FUNCTION(atest_gpsadc1), - FUNCTION(blsp_uart1), - FUNCTION(SMB_STAT), - FUNCTION(phase_flag14), - FUNCTION(blsp_i2c2), - FUNCTION(phase_flag31), - FUNCTION(blsp_spi3), - FUNCTION(blsp_spi3_cs1), - FUNCTION(blsp_spi3_cs2), - FUNCTION(wlan1_adc1), - FUNCTION(atest_usb13), - FUNCTION(tgu_ch1), - FUNCTION(qdss_gpio5), - FUNCTION(atest_gpsadc0), - FUNCTION(blsp_i2c1), - FUNCTION(ddr_bist), - FUNCTION(atest_tsens2), - FUNCTION(atest_usb1), - FUNCTION(blsp_spi2), - FUNCTION(blsp_uim2), - FUNCTION(phase_flag3), - FUNCTION(bimc_dte1), - FUNCTION(wlan1_adc0), - FUNCTION(atest_usb12), - FUNCTION(bimc_dte0), - FUNCTION(blsp_i2c3), - FUNCTION(wlan2_adc1), - FUNCTION(atest_usb11), - FUNCTION(dbg_out), - FUNCTION(wlan2_adc0), - FUNCTION(atest_usb10), - FUNCTION(RCM_MARKER), - FUNCTION(blsp_spi4), - FUNCTION(pri_mi2s), - FUNCTION(phase_flag26), - FUNCTION(qdss_cti0_a), - FUNCTION(qdss_cti0_b), - FUNCTION(qdss_cti1_a), - FUNCTION(qdss_cti1_b), - FUNCTION(DP_HOT), - FUNCTION(pri_mi2s_ws), - FUNCTION(phase_flag27), - FUNCTION(blsp_i2c4), - FUNCTION(phase_flag28), - FUNCTION(blsp_uart5), - FUNCTION(blsp_spi5), - FUNCTION(blsp_uim5), - FUNCTION(phase_flag5), - FUNCTION(blsp_i2c5), - FUNCTION(blsp_spi6), - FUNCTION(blsp_uart2), - FUNCTION(blsp_uim6), - FUNCTION(phase_flag11), - FUNCTION(vsense_data0), - FUNCTION(blsp_i2c6), - FUNCTION(phase_flag12), - FUNCTION(vsense_data1), - FUNCTION(phase_flag13), - FUNCTION(vsense_mode), - FUNCTION(blsp_spi7), - FUNCTION(blsp_uart6_a), - FUNCTION(blsp_uart6_b), - FUNCTION(sec_mi2s), - FUNCTION(sndwire_clk), - FUNCTION(phase_flag17), - FUNCTION(vsense_clkout), - FUNCTION(sndwire_data), - FUNCTION(phase_flag18), - FUNCTION(WSA_SPKR), - FUNCTION(blsp_i2c7), - FUNCTION(phase_flag19), - FUNCTION(vfr_1), - FUNCTION(phase_flag20), - FUNCTION(NFC_INT), - FUNCTION(blsp_spi8_cs1), - FUNCTION(blsp_spi8_cs2), - FUNCTION(m_voc), - FUNCTION(phase_flag21), - FUNCTION(NFC_EN), - FUNCTION(phase_flag22), - FUNCTION(NFC_DWL), - FUNCTION(blsp_i2c8_a), - FUNCTION(blsp_i2c8_b), - FUNCTION(phase_flag23), - FUNCTION(NFC_ESE), - FUNCTION(pwr_modem), - FUNCTION(phase_flag24), - FUNCTION(qdss_gpio), - FUNCTION(cam_mclk), - FUNCTION(pwr_nav), - FUNCTION(qdss_gpio0), - FUNCTION(qspi_data0), - FUNCTION(pwr_crypto), - FUNCTION(qdss_gpio1), - FUNCTION(qspi_data1), - FUNCTION(agera_pll), - FUNCTION(qdss_gpio2), - FUNCTION(qspi_data2), - FUNCTION(jitter_bist), - FUNCTION(qdss_gpio3), - FUNCTION(qdss_gpio7), - FUNCTION(FL_R3LED), - FUNCTION(CCI_TIMER0), - FUNCTION(FL_STROBE), - FUNCTION(CCI_TIMER1), - FUNCTION(CAM_LDO1), - FUNCTION(mdss_vsync0), - FUNCTION(mdss_vsync1), - FUNCTION(mdss_vsync2), - FUNCTION(mdss_vsync3), - FUNCTION(qdss_gpio9), - FUNCTION(CAM_IRQ), - FUNCTION(atest_usb2), - FUNCTION(cci_i2c), - FUNCTION(pll_bypassnl), - FUNCTION(atest_tsens), - FUNCTION(atest_usb21), - FUNCTION(pll_reset), - FUNCTION(atest_usb23), - FUNCTION(qdss_gpio6), - FUNCTION(CCI_TIMER3), - FUNCTION(CCI_ASYNC), - FUNCTION(qspi_cs), - FUNCTION(qdss_gpio10), - FUNCTION(CAM3_STANDBY), - FUNCTION(CCI_TIMER4), - FUNCTION(qdss_gpio11), - FUNCTION(CAM_LDO2), - FUNCTION(cci_async), - FUNCTION(qdss_gpio12), - FUNCTION(CAM0_RST), - FUNCTION(qdss_gpio13), - FUNCTION(CAM1_RST), - FUNCTION(qspi_clk), - FUNCTION(phase_flag30), - FUNCTION(qdss_gpio14), - FUNCTION(qspi_resetn), - FUNCTION(phase_flag1), - FUNCTION(qdss_gpio15), - FUNCTION(CAM0_STANDBY), - FUNCTION(phase_flag2), - FUNCTION(CAM1_STANDBY), - FUNCTION(phase_flag9), - FUNCTION(CAM2_STANDBY), - FUNCTION(qspi_data3), - FUNCTION(phase_flag15), - FUNCTION(qdss_gpio8), - FUNCTION(CAM3_RST), - FUNCTION(CCI_TIMER2), - FUNCTION(phase_flag16), - FUNCTION(LCD0_RESET), - FUNCTION(phase_flag6), - FUNCTION(SD_CARD), - FUNCTION(phase_flag29), - FUNCTION(DP_EN), - FUNCTION(phase_flag25), - FUNCTION(USBC_ORIENTATION), - FUNCTION(phase_flag10), - FUNCTION(atest_usb20), - FUNCTION(gcc_gp1), - FUNCTION(phase_flag4), - FUNCTION(atest_usb22), - FUNCTION(USB_PHY), - FUNCTION(gcc_gp2), - FUNCTION(atest_char), - FUNCTION(mdp_vsync), - FUNCTION(gcc_gp3), - FUNCTION(atest_char3), - FUNCTION(FORCE_TOUCH), - FUNCTION(cri_trng0), - FUNCTION(atest_char2), - FUNCTION(cri_trng1), - FUNCTION(atest_char1), - FUNCTION(AUDIO_USBC), - FUNCTION(audio_ref), - FUNCTION(MDP_VSYNC), - FUNCTION(cri_trng), - FUNCTION(atest_char0), - FUNCTION(US_EURO), - FUNCTION(LCD_BACKLIGHT), - FUNCTION(blsp_spi8_a), - FUNCTION(blsp_spi8_b), - FUNCTION(sp_cmu), - FUNCTION(nav_pps_a), - FUNCTION(nav_pps_b), - FUNCTION(nav_pps_c), - FUNCTION(gps_tx_a), - FUNCTION(gps_tx_b), - FUNCTION(gps_tx_c), - FUNCTION(adsp_ext), - FUNCTION(TS_RESET), - FUNCTION(ssc_irq), - FUNCTION(isense_dbg), - FUNCTION(phase_flag0), - FUNCTION(phase_flag7), - FUNCTION(phase_flag8), - FUNCTION(tsense_pwm1), - FUNCTION(tsense_pwm2), - FUNCTION(SENSOR_RST), - FUNCTION(WMSS_RESETN), - FUNCTION(HAPTICS_PWM), - FUNCTION(GPS_eLNA), - FUNCTION(mss_lte), - FUNCTION(uim2_data), - FUNCTION(uim2_clk), - FUNCTION(uim2_reset), - FUNCTION(uim2_present), - FUNCTION(uim1_data), - FUNCTION(uim1_clk), - FUNCTION(uim1_reset), - FUNCTION(uim1_present), - FUNCTION(uim_batt), - FUNCTION(pa_indicator), - FUNCTION(ldo_en), - FUNCTION(ldo_update), - FUNCTION(qlink_request), - FUNCTION(qlink_enable), - FUNCTION(prng_rosc), - FUNCTION(LCD_PWR), -}; - -static const struct msm_pingroup msmfalcon_groups[] = { - PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, NA, NA, - qdss_gpio4, atest_gpsadc1, NA), - PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, NA, NA, - qdss_gpio5, atest_gpsadc0, NA), - PINGROUP(2, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, - NA, NA), - PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, ddr_bist, NA, NA, - atest_tsens2, atest_usb1, NA), - PINGROUP(4, NORTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag3, NA, - NA, NA, NA, NA), - PINGROUP(5, SOUTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag14, NA, - NA, NA, NA, NA), - PINGROUP(6, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, phase_flag31, NA, - NA, NA, NA, NA), - PINGROUP(7, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, NA, NA, NA, NA, - NA, NA), - PINGROUP(8, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc1, - atest_usb13, bimc_dte1, NA), - PINGROUP(9, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc0, - atest_usb12, bimc_dte0, NA), - PINGROUP(10, NORTH, blsp_spi3, blsp_i2c3, ddr_bist, NA, NA, wlan2_adc1, - atest_usb11, bimc_dte1, NA), - PINGROUP(11, NORTH, blsp_spi3, blsp_i2c3, NA, dbg_out, wlan2_adc0, - atest_usb10, bimc_dte0, NA, NA), - PINGROUP(12, NORTH, blsp_spi4, pri_mi2s, NA, phase_flag26, qdss_cti1_b, - NA, NA, NA, NA), - PINGROUP(13, NORTH, blsp_spi4, DP_HOT, pri_mi2s_ws, NA, NA, - phase_flag27, qdss_cti0_b, NA, NA), - PINGROUP(14, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, phase_flag28, - NA, NA, NA, NA), - PINGROUP(15, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, NA, NA, NA, NA, - NA), - PINGROUP(16, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, NA, NA, NA, - NA, NA), - PINGROUP(17, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, phase_flag5, - NA, NA, NA, NA), - PINGROUP(18, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, - NA, NA), - PINGROUP(19, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, - NA, NA), - PINGROUP(20, SOUTH, NA, NA, blsp_uim6, NA, NA, NA, NA, - NA, NA), - PINGROUP(21, SOUTH, NA, NA, blsp_uim6, NA, phase_flag11, - qdss_cti0_b, vsense_data0, NA, NA), - PINGROUP(22, CENTER, blsp_spi6, NA, blsp_i2c6, NA, - phase_flag12, vsense_data1, NA, NA, NA), - PINGROUP(23, CENTER, blsp_spi6, NA, blsp_i2c6, NA, - phase_flag13, vsense_mode, NA, NA, NA), - PINGROUP(24, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_clk, NA, - NA, phase_flag17, vsense_clkout, NA), - PINGROUP(25, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_data, NA, - NA, phase_flag18, NA, NA), - PINGROUP(26, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, sec_mi2s, NA, - phase_flag19, NA, NA, NA), - PINGROUP(27, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, vfr_1, sec_mi2s, - NA, phase_flag20, NA, NA), - PINGROUP(28, CENTER, blsp_spi8_a, blsp_uart6_b, m_voc, NA, phase_flag21, - NA, NA, NA, NA), - PINGROUP(29, CENTER, blsp_spi8_a, blsp_uart6_b, NA, NA, phase_flag22, - NA, NA, NA, NA), - PINGROUP(30, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, - blsp_spi3_cs1, NA, phase_flag23, NA, NA, NA), - PINGROUP(31, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, pwr_modem, - NA, phase_flag24, qdss_gpio, NA, NA), - PINGROUP(32, SOUTH, cam_mclk, pwr_nav, NA, NA, qdss_gpio0, NA, NA, NA, - NA), - PINGROUP(33, SOUTH, cam_mclk, qspi_data0, pwr_crypto, NA, NA, - qdss_gpio1, NA, NA, NA), - PINGROUP(34, SOUTH, cam_mclk, qspi_data1, agera_pll, NA, NA, - qdss_gpio2, NA, NA, NA), - PINGROUP(35, SOUTH, cam_mclk, qspi_data2, jitter_bist, NA, NA, - qdss_gpio3, NA, atest_usb2, NA), - PINGROUP(36, SOUTH, cci_i2c, pll_bypassnl, agera_pll, NA, NA, - qdss_gpio4, atest_tsens, atest_usb21, NA), - PINGROUP(37, SOUTH, cci_i2c, pll_reset, NA, NA, qdss_gpio5, - atest_usb23, NA, NA, NA), - PINGROUP(38, SOUTH, cci_i2c, NA, NA, qdss_gpio6, NA, NA, NA, NA, NA), - PINGROUP(39, SOUTH, cci_i2c, NA, NA, qdss_gpio7, NA, NA, NA, NA, NA), - PINGROUP(40, SOUTH, CCI_TIMER0, NA, blsp_spi8_b, NA, NA, NA, NA, NA, - NA), - PINGROUP(41, SOUTH, CCI_TIMER1, NA, blsp_spi8_b, NA, NA, NA, NA, NA, - NA), - PINGROUP(42, SOUTH, mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, - NA, NA, qdss_gpio9, NA, NA), - PINGROUP(43, SOUTH, CCI_TIMER3, CCI_ASYNC, qspi_cs, NA, NA, - qdss_gpio10, NA, NA, NA), - PINGROUP(44, SOUTH, CCI_TIMER4, CCI_ASYNC, blsp_spi8_b, blsp_i2c8_b, NA, - NA, qdss_gpio11, NA, NA), - PINGROUP(45, SOUTH, cci_async, NA, NA, qdss_gpio12, NA, NA, NA, NA, NA), - PINGROUP(46, SOUTH, blsp_spi1, NA, NA, qdss_gpio13, NA, NA, NA, NA, NA), - PINGROUP(47, SOUTH, qspi_clk, NA, phase_flag30, qdss_gpio14, NA, NA, - NA, NA, NA), - PINGROUP(48, SOUTH, NA, phase_flag1, qdss_gpio15, NA, NA, NA, NA, NA, - NA), - PINGROUP(49, SOUTH, blsp_spi6, phase_flag2, qdss_cti0_a, NA, NA, NA, - NA, NA, NA), - PINGROUP(50, SOUTH, qspi_cs, NA, phase_flag9, qdss_cti0_a, NA, NA, NA, - NA, NA), - PINGROUP(51, SOUTH, qspi_data3, NA, phase_flag15, qdss_gpio8, NA, NA, - NA, NA, NA), - PINGROUP(52, SOUTH, CCI_TIMER2, blsp_spi8_b, blsp_i2c8_b, blsp_spi6, - phase_flag16, qdss_gpio, NA, NA, NA), - PINGROUP(53, NORTH, NA, phase_flag6, qdss_cti1_a, NA, NA, NA, NA, NA, - NA), - PINGROUP(54, NORTH, NA, NA, phase_flag29, NA, NA, NA, NA, NA, NA), - PINGROUP(55, SOUTH, NA, phase_flag25, qdss_cti1_a, NA, NA, NA, NA, NA, - NA), - PINGROUP(56, SOUTH, NA, phase_flag10, qdss_gpio3, NA, atest_usb20, NA, - NA, NA, NA), - PINGROUP(57, SOUTH, gcc_gp1, NA, phase_flag4, atest_usb22, NA, NA, NA, - NA, NA), - PINGROUP(58, SOUTH, USB_PHY, gcc_gp2, NA, NA, atest_char, NA, NA, NA, - NA), - PINGROUP(59, NORTH, mdp_vsync, gcc_gp3, NA, NA, atest_char3, NA, NA, - NA, NA), - PINGROUP(60, NORTH, cri_trng0, NA, NA, atest_char2, NA, NA, NA, NA, NA), - PINGROUP(61, NORTH, pri_mi2s, cri_trng1, NA, NA, atest_char1, NA, NA, - NA, NA), - PINGROUP(62, NORTH, sec_mi2s, audio_ref, MDP_VSYNC, cri_trng, NA, NA, - atest_char0, NA, NA), - PINGROUP(63, NORTH, NA, NA, NA, qdss_gpio1, NA, NA, NA, NA, NA), - PINGROUP(64, SOUTH, blsp_spi8_cs1, sp_cmu, NA, NA, qdss_gpio2, NA, NA, - NA, NA), - PINGROUP(65, SOUTH, NA, nav_pps_a, nav_pps_a, gps_tx_a, blsp_spi3_cs2, - adsp_ext, NA, NA, NA), - PINGROUP(66, NORTH, NA, NA, qdss_cti1_b, NA, NA, NA, NA, NA, NA), - PINGROUP(67, NORTH, NA, NA, qdss_gpio0, NA, NA, NA, NA, NA, NA), - PINGROUP(68, NORTH, isense_dbg, NA, phase_flag0, qdss_gpio, NA, NA, NA, - NA, NA), - PINGROUP(69, NORTH, NA, phase_flag7, qdss_gpio, NA, NA, NA, NA, NA, NA), - PINGROUP(70, NORTH, NA, phase_flag8, qdss_gpio6, NA, NA, NA, NA, NA, - NA), - PINGROUP(71, NORTH, NA, NA, qdss_gpio7, tsense_pwm1, tsense_pwm2, NA, - NA, NA, NA), - PINGROUP(72, NORTH, NA, qdss_gpio14, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(73, NORTH, NA, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA), - PINGROUP(74, NORTH, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(75, NORTH, NA, NA, qdss_gpio8, NA, NA, NA, NA, NA, NA), - PINGROUP(76, NORTH, blsp_spi8_cs2, NA, NA, NA, qdss_gpio9, NA, NA, NA, - NA), - PINGROUP(77, NORTH, NA, NA, qdss_gpio10, NA, NA, NA, NA, NA, NA), - PINGROUP(78, NORTH, gcc_gp1, NA, qdss_gpio13, NA, NA, NA, NA, NA, NA), - PINGROUP(79, SOUTH, NA, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA), - PINGROUP(80, SOUTH, nav_pps_b, nav_pps_b, gps_tx_c, NA, NA, qdss_gpio12, - NA, NA, NA), - PINGROUP(81, CENTER, mss_lte, gcc_gp2, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(82, CENTER, mss_lte, gcc_gp3, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(83, SOUTH, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(84, SOUTH, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(85, SOUTH, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(86, SOUTH, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(87, SOUTH, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(88, SOUTH, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(89, SOUTH, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(90, SOUTH, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(91, SOUTH, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(92, SOUTH, NA, NA, pa_indicator, NA, NA, NA, NA, NA, NA), - PINGROUP(93, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(94, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(95, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(96, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(97, SOUTH, NA, ldo_en, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(98, SOUTH, NA, nav_pps_c, nav_pps_c, gps_tx_b, ldo_update, NA, - NA, NA, NA), - PINGROUP(99, SOUTH, qlink_request, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(100, SOUTH, qlink_enable, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(101, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(102, SOUTH, NA, prng_rosc, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(103, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(104, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(105, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(106, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(107, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(108, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(109, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(110, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(111, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(112, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(113, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - SDC_QDSD_PINGROUP(sdc1_clk, 0x99a000, 13, 6), - SDC_QDSD_PINGROUP(sdc1_cmd, 0x99a000, 11, 3), - SDC_QDSD_PINGROUP(sdc1_data, 0x99a000, 9, 0), - SDC_QDSD_PINGROUP(sdc2_clk, 0x99b000, 14, 6), - SDC_QDSD_PINGROUP(sdc2_cmd, 0x99b000, 11, 3), - SDC_QDSD_PINGROUP(sdc2_data, 0x99b000, 9, 0), - SDC_QDSD_PINGROUP(sdc1_rclk, 0x99a000, 15, 0), -}; - -static const struct msm_pinctrl_soc_data msmfalcon_pinctrl = { - .pins = msmfalcon_pins, - .npins = ARRAY_SIZE(msmfalcon_pins), - .functions = msmfalcon_functions, - .nfunctions = ARRAY_SIZE(msmfalcon_functions), - .groups = msmfalcon_groups, - .ngroups = ARRAY_SIZE(msmfalcon_groups), - .ngpios = 114, -}; - -static int msmfalcon_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &msmfalcon_pinctrl); -} - -static const struct of_device_id msmfalcon_pinctrl_of_match[] = { - { .compatible = "qcom,msmfalcon-pinctrl", }, - { }, -}; - -static struct platform_driver msmfalcon_pinctrl_driver = { - .driver = { - .name = "msmfalcon-pinctrl", - .owner = THIS_MODULE, - .of_match_table = msmfalcon_pinctrl_of_match, - }, - .probe = msmfalcon_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init msmfalcon_pinctrl_init(void) -{ - return platform_driver_register(&msmfalcon_pinctrl_driver); -} -arch_initcall(msmfalcon_pinctrl_init); - -static void __exit msmfalcon_pinctrl_exit(void) -{ - platform_driver_unregister(&msmfalcon_pinctrl_driver); -} -module_exit(msmfalcon_pinctrl_exit); - -MODULE_DESCRIPTION("QTI msmfalcon pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msmfalcon_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c new file mode 100644 index 000000000000..4dbb4cae2fae --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -0,0 +1,1722 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define NORTH 0x00900000 +#define CENTER 0x00500000 +#define SOUTH 0x00100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = base + REG_SIZE * id, \ + .io_reg = base + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ + .intr_status_reg = base + 0xc + REG_SIZE * id, \ + .intr_target_reg = base + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sdm660_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "SDC1_CLK"), + PINCTRL_PIN(115, "SDC1_CMD"), + PINCTRL_PIN(116, "SDC1_DATA"), + PINCTRL_PIN(117, "SDC2_CLK"), + PINCTRL_PIN(118, "SDC2_CMD"), + PINCTRL_PIN(119, "SDC2_DATA"), + PINCTRL_PIN(120, "SDC1_RCLK"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); + +static const unsigned int sdc1_clk_pins[] = { 114 }; +static const unsigned int sdc1_cmd_pins[] = { 115 }; +static const unsigned int sdc1_data_pins[] = { 116 }; +static const unsigned int sdc2_clk_pins[] = { 117 }; +static const unsigned int sdc2_cmd_pins[] = { 118 }; +static const unsigned int sdc2_data_pins[] = { 119 }; +static const unsigned int sdc1_rclk_pins[] = { 120 }; + +enum sdm660_functions { + msm_mux_blsp_spi1, + msm_mux_gpio, + msm_mux_blsp_uim1, + msm_mux_tgu_ch0, + msm_mux_qdss_gpio4, + msm_mux_atest_gpsadc1, + msm_mux_blsp_uart1, + msm_mux_SMB_STAT, + msm_mux_phase_flag14, + msm_mux_blsp_i2c2, + msm_mux_phase_flag31, + msm_mux_blsp_spi3, + msm_mux_blsp_spi3_cs1, + msm_mux_blsp_spi3_cs2, + msm_mux_wlan1_adc1, + msm_mux_atest_usb13, + msm_mux_tgu_ch1, + msm_mux_qdss_gpio5, + msm_mux_atest_gpsadc0, + msm_mux_blsp_i2c1, + msm_mux_ddr_bist, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_blsp_spi2, + msm_mux_blsp_uim2, + msm_mux_phase_flag3, + msm_mux_bimc_dte1, + msm_mux_wlan1_adc0, + msm_mux_atest_usb12, + msm_mux_bimc_dte0, + msm_mux_blsp_i2c3, + msm_mux_wlan2_adc1, + msm_mux_atest_usb11, + msm_mux_dbg_out, + msm_mux_wlan2_adc0, + msm_mux_atest_usb10, + msm_mux_RCM_MARKER, + msm_mux_blsp_spi4, + msm_mux_pri_mi2s, + msm_mux_phase_flag26, + msm_mux_qdss_cti0_a, + msm_mux_qdss_cti0_b, + msm_mux_qdss_cti1_a, + msm_mux_qdss_cti1_b, + msm_mux_DP_HOT, + msm_mux_pri_mi2s_ws, + msm_mux_phase_flag27, + msm_mux_blsp_i2c4, + msm_mux_phase_flag28, + msm_mux_blsp_uart5, + msm_mux_blsp_spi5, + msm_mux_blsp_uim5, + msm_mux_phase_flag5, + msm_mux_blsp_i2c5, + msm_mux_blsp_spi6, + msm_mux_blsp_uart2, + msm_mux_blsp_uim6, + msm_mux_phase_flag11, + msm_mux_vsense_data0, + msm_mux_blsp_i2c6, + msm_mux_phase_flag12, + msm_mux_vsense_data1, + msm_mux_phase_flag13, + msm_mux_vsense_mode, + msm_mux_blsp_spi7, + msm_mux_blsp_uart6_a, + msm_mux_blsp_uart6_b, + msm_mux_sec_mi2s, + msm_mux_sndwire_clk, + msm_mux_phase_flag17, + msm_mux_vsense_clkout, + msm_mux_sndwire_data, + msm_mux_phase_flag18, + msm_mux_WSA_SPKR, + msm_mux_blsp_i2c7, + msm_mux_phase_flag19, + msm_mux_vfr_1, + msm_mux_phase_flag20, + msm_mux_NFC_INT, + msm_mux_blsp_spi8_cs1, + msm_mux_blsp_spi8_cs2, + msm_mux_m_voc, + msm_mux_phase_flag21, + msm_mux_NFC_EN, + msm_mux_phase_flag22, + msm_mux_NFC_DWL, + msm_mux_blsp_i2c8_a, + msm_mux_blsp_i2c8_b, + msm_mux_phase_flag23, + msm_mux_NFC_ESE, + msm_mux_pwr_modem, + msm_mux_phase_flag24, + msm_mux_qdss_gpio, + msm_mux_cam_mclk, + msm_mux_pwr_nav, + msm_mux_qdss_gpio0, + msm_mux_qspi_data0, + msm_mux_pwr_crypto, + msm_mux_qdss_gpio1, + msm_mux_qspi_data1, + msm_mux_agera_pll, + msm_mux_qdss_gpio2, + msm_mux_qspi_data2, + msm_mux_jitter_bist, + msm_mux_qdss_gpio3, + msm_mux_qdss_gpio7, + msm_mux_FL_R3LED, + msm_mux_CCI_TIMER0, + msm_mux_FL_STROBE, + msm_mux_CCI_TIMER1, + msm_mux_CAM_LDO1, + msm_mux_mdss_vsync0, + msm_mux_mdss_vsync1, + msm_mux_mdss_vsync2, + msm_mux_mdss_vsync3, + msm_mux_qdss_gpio9, + msm_mux_CAM_IRQ, + msm_mux_atest_usb2, + msm_mux_cci_i2c, + msm_mux_pll_bypassnl, + msm_mux_atest_tsens, + msm_mux_atest_usb21, + msm_mux_pll_reset, + msm_mux_atest_usb23, + msm_mux_qdss_gpio6, + msm_mux_CCI_TIMER3, + msm_mux_CCI_ASYNC, + msm_mux_qspi_cs, + msm_mux_qdss_gpio10, + msm_mux_CAM3_STANDBY, + msm_mux_CCI_TIMER4, + msm_mux_qdss_gpio11, + msm_mux_CAM_LDO2, + msm_mux_cci_async, + msm_mux_qdss_gpio12, + msm_mux_CAM0_RST, + msm_mux_qdss_gpio13, + msm_mux_CAM1_RST, + msm_mux_qspi_clk, + msm_mux_phase_flag30, + msm_mux_qdss_gpio14, + msm_mux_qspi_resetn, + msm_mux_phase_flag1, + msm_mux_qdss_gpio15, + msm_mux_CAM0_STANDBY, + msm_mux_phase_flag2, + msm_mux_CAM1_STANDBY, + msm_mux_phase_flag9, + msm_mux_CAM2_STANDBY, + msm_mux_qspi_data3, + msm_mux_phase_flag15, + msm_mux_qdss_gpio8, + msm_mux_CAM3_RST, + msm_mux_CCI_TIMER2, + msm_mux_phase_flag16, + msm_mux_LCD0_RESET, + msm_mux_phase_flag6, + msm_mux_SD_CARD, + msm_mux_phase_flag29, + msm_mux_DP_EN, + msm_mux_phase_flag25, + msm_mux_USBC_ORIENTATION, + msm_mux_phase_flag10, + msm_mux_atest_usb20, + msm_mux_gcc_gp1, + msm_mux_phase_flag4, + msm_mux_atest_usb22, + msm_mux_USB_PHY, + msm_mux_gcc_gp2, + msm_mux_atest_char, + msm_mux_mdp_vsync, + msm_mux_gcc_gp3, + msm_mux_atest_char3, + msm_mux_FORCE_TOUCH, + msm_mux_cri_trng0, + msm_mux_atest_char2, + msm_mux_cri_trng1, + msm_mux_atest_char1, + msm_mux_AUDIO_USBC, + msm_mux_audio_ref, + msm_mux_MDP_VSYNC, + msm_mux_cri_trng, + msm_mux_atest_char0, + msm_mux_US_EURO, + msm_mux_LCD_BACKLIGHT, + msm_mux_blsp_spi8_a, + msm_mux_blsp_spi8_b, + msm_mux_sp_cmu, + msm_mux_nav_pps_a, + msm_mux_nav_pps_b, + msm_mux_nav_pps_c, + msm_mux_gps_tx_a, + msm_mux_gps_tx_b, + msm_mux_gps_tx_c, + msm_mux_adsp_ext, + msm_mux_TS_RESET, + msm_mux_ssc_irq, + msm_mux_isense_dbg, + msm_mux_phase_flag0, + msm_mux_phase_flag7, + msm_mux_phase_flag8, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_SENSOR_RST, + msm_mux_WMSS_RESETN, + msm_mux_HAPTICS_PWM, + msm_mux_GPS_eLNA, + msm_mux_mss_lte, + msm_mux_uim2_data, + msm_mux_uim2_clk, + msm_mux_uim2_reset, + msm_mux_uim2_present, + msm_mux_uim1_data, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_uim_batt, + msm_mux_pa_indicator, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_qlink_request, + msm_mux_qlink_enable, + msm_mux_prng_rosc, + msm_mux_LCD_PWR, + msm_mux_NA, +}; + +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio46", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", +}; +static const char * const blsp_uim1_groups[] = { + "gpio0", "gpio1", +}; +static const char * const tgu_ch0_groups[] = { + "gpio0", +}; +static const char * const qdss_gpio4_groups[] = { + "gpio0", "gpio36", +}; +static const char * const atest_gpsadc1_groups[] = { + "gpio0", +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const SMB_STAT_groups[] = { + "gpio5", +}; +static const char * const phase_flag14_groups[] = { + "gpio5", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const phase_flag31_groups[] = { + "gpio6", +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_spi3_cs1_groups[] = { + "gpio30", +}; +static const char * const blsp_spi3_cs2_groups[] = { + "gpio65", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio8", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const tgu_ch1_groups[] = { + "gpio1", +}; +static const char * const qdss_gpio5_groups[] = { + "gpio1", "gpio37", +}; +static const char * const atest_gpsadc0_groups[] = { + "gpio1", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const ddr_bist_groups[] = { + "gpio3", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio3", +}; +static const char * const atest_usb1_groups[] = { + "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim2_groups[] = { + "gpio4", "gpio5", +}; +static const char * const phase_flag3_groups[] = { + "gpio4", +}; +static const char * const bimc_dte1_groups[] = { + "gpio8", "gpio10", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio9", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const bimc_dte0_groups[] = { + "gpio9", "gpio11", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const RCM_MARKER_groups[] = { + "gpio12", "gpio13", +}; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const pri_mi2s_groups[] = { + "gpio12", "gpio14", "gpio15", "gpio61", +}; +static const char * const phase_flag26_groups[] = { + "gpio12", +}; +static const char * const qdss_cti0_a_groups[] = { + "gpio49", "gpio50", +}; +static const char * const qdss_cti0_b_groups[] = { + "gpio13", "gpio21", +}; +static const char * const qdss_cti1_a_groups[] = { + "gpio53", "gpio55", +}; +static const char * const qdss_cti1_b_groups[] = { + "gpio12", "gpio66", +}; +static const char * const DP_HOT_groups[] = { + "gpio13", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio13", +}; +static const char * const phase_flag27_groups[] = { + "gpio13", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio14", "gpio15", +}; +static const char * const phase_flag28_groups[] = { + "gpio14", +}; +static const char * const blsp_uart5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_uim5_groups[] = { + "gpio16", "gpio17", +}; +static const char * const phase_flag5_groups[] = { + "gpio17", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio18", "gpio19", +}; +static const char * const blsp_spi6_groups[] = { + "gpio49", "gpio52", "gpio22", "gpio23", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim6_groups[] = { + "gpio20", "gpio21", +}; +static const char * const phase_flag11_groups[] = { + "gpio21", +}; +static const char * const vsense_data0_groups[] = { + "gpio21", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const phase_flag12_groups[] = { + "gpio22", +}; +static const char * const vsense_data1_groups[] = { + "gpio22", +}; +static const char * const phase_flag13_groups[] = { + "gpio23", +}; +static const char * const vsense_mode_groups[] = { + "gpio23", +}; +static const char * const blsp_spi7_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const blsp_uart6_a_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const blsp_uart6_b_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const sec_mi2s_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", "gpio62", +}; +static const char * const sndwire_clk_groups[] = { + "gpio24", +}; +static const char * const phase_flag17_groups[] = { + "gpio24", +}; +static const char * const vsense_clkout_groups[] = { + "gpio24", +}; +static const char * const sndwire_data_groups[] = { + "gpio25", +}; +static const char * const phase_flag18_groups[] = { + "gpio25", +}; +static const char * const WSA_SPKR_groups[] = { + "gpio26", "gpio27", +}; +static const char * const blsp_i2c7_groups[] = { + "gpio26", "gpio27", +}; +static const char * const phase_flag19_groups[] = { + "gpio26", +}; +static const char * const vfr_1_groups[] = { + "gpio27", +}; +static const char * const phase_flag20_groups[] = { + "gpio27", +}; +static const char * const NFC_INT_groups[] = { + "gpio28", +}; +static const char * const blsp_spi8_a_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const blsp_spi8_b_groups[] = { + "gpio40", "gpio41", "gpio44", "gpio52", +}; +static const char * const m_voc_groups[] = { + "gpio28", +}; +static const char * const phase_flag21_groups[] = { + "gpio28", +}; +static const char * const NFC_EN_groups[] = { + "gpio29", +}; +static const char * const phase_flag22_groups[] = { + "gpio29", +}; +static const char * const NFC_DWL_groups[] = { + "gpio30", +}; +static const char * const blsp_i2c8_a_groups[] = { + "gpio30", "gpio31", +}; +static const char * const blsp_i2c8_b_groups[] = { + "gpio44", "gpio52", +}; +static const char * const phase_flag23_groups[] = { + "gpio30", +}; +static const char * const NFC_ESE_groups[] = { + "gpio31", +}; +static const char * const pwr_modem_groups[] = { + "gpio31", +}; +static const char * const phase_flag24_groups[] = { + "gpio31", +}; +static const char * const qdss_gpio_groups[] = { + "gpio31", "gpio52", "gpio68", "gpio69", +}; +static const char * const cam_mclk_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const pwr_nav_groups[] = { + "gpio32", +}; +static const char * const qdss_gpio0_groups[] = { + "gpio32", "gpio67", +}; +static const char * const qspi_data0_groups[] = { + "gpio33", +}; +static const char * const pwr_crypto_groups[] = { + "gpio33", +}; +static const char * const qdss_gpio1_groups[] = { + "gpio33", "gpio63", +}; +static const char * const qspi_data1_groups[] = { + "gpio34", +}; +static const char * const agera_pll_groups[] = { + "gpio34", "gpio36", +}; +static const char * const qdss_gpio2_groups[] = { + "gpio34", "gpio64", +}; +static const char * const qspi_data2_groups[] = { + "gpio35", +}; +static const char * const jitter_bist_groups[] = { + "gpio35", +}; +static const char * const qdss_gpio3_groups[] = { + "gpio35", "gpio56", +}; +static const char * const qdss_gpio7_groups[] = { + "gpio39", "gpio71", +}; +static const char * const FL_R3LED_groups[] = { + "gpio40", +}; +static const char * const CCI_TIMER0_groups[] = { + "gpio40", +}; +static const char * const FL_STROBE_groups[] = { + "gpio41", +}; +static const char * const CCI_TIMER1_groups[] = { + "gpio41", +}; +static const char * const CAM_LDO1_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync0_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync1_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync2_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync3_groups[] = { + "gpio42", +}; +static const char * const qdss_gpio9_groups[] = { + "gpio42", "gpio76", +}; +static const char * const CAM_IRQ_groups[] = { + "gpio43", +}; +static const char * const atest_usb2_groups[] = { + "gpio35", +}; +static const char * const cci_i2c_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio36", +}; +static const char * const atest_tsens_groups[] = { + "gpio36", +}; +static const char * const atest_usb21_groups[] = { + "gpio36", +}; +static const char * const pll_reset_groups[] = { + "gpio37", +}; +static const char * const atest_usb23_groups[] = { + "gpio37", +}; +static const char * const qdss_gpio6_groups[] = { + "gpio38", "gpio70", +}; +static const char * const CCI_TIMER3_groups[] = { + "gpio43", +}; +static const char * const CCI_ASYNC_groups[] = { + "gpio43", "gpio44", +}; +static const char * const qspi_cs_groups[] = { + "gpio43", "gpio50", +}; +static const char * const qdss_gpio10_groups[] = { + "gpio43", "gpio77", +}; +static const char * const CAM3_STANDBY_groups[] = { + "gpio44", +}; +static const char * const CCI_TIMER4_groups[] = { + "gpio44", +}; +static const char * const qdss_gpio11_groups[] = { + "gpio44", "gpio79", +}; +static const char * const CAM_LDO2_groups[] = { + "gpio45", +}; +static const char * const cci_async_groups[] = { + "gpio45", +}; +static const char * const qdss_gpio12_groups[] = { + "gpio45", "gpio80", +}; +static const char * const CAM0_RST_groups[] = { + "gpio46", +}; +static const char * const qdss_gpio13_groups[] = { + "gpio46", "gpio78", +}; +static const char * const CAM1_RST_groups[] = { + "gpio47", +}; +static const char * const qspi_clk_groups[] = { + "gpio47", +}; +static const char * const phase_flag30_groups[] = { + "gpio47", +}; +static const char * const qdss_gpio14_groups[] = { + "gpio47", "gpio72", +}; +static const char * const qspi_resetn_groups[] = { + "gpio48", +}; +static const char * const phase_flag1_groups[] = { + "gpio48", +}; +static const char * const qdss_gpio15_groups[] = { + "gpio48", "gpio73", +}; +static const char * const CAM0_STANDBY_groups[] = { + "gpio49", +}; +static const char * const phase_flag2_groups[] = { + "gpio49", +}; +static const char * const CAM1_STANDBY_groups[] = { + "gpio50", +}; +static const char * const phase_flag9_groups[] = { + "gpio50", +}; +static const char * const CAM2_STANDBY_groups[] = { + "gpio51", +}; +static const char * const qspi_data3_groups[] = { + "gpio51", +}; +static const char * const phase_flag15_groups[] = { + "gpio51", +}; +static const char * const qdss_gpio8_groups[] = { + "gpio51", "gpio75", +}; +static const char * const CAM3_RST_groups[] = { + "gpio52", +}; +static const char * const CCI_TIMER2_groups[] = { + "gpio52", +}; +static const char * const phase_flag16_groups[] = { + "gpio52", +}; +static const char * const LCD0_RESET_groups[] = { + "gpio53", +}; +static const char * const phase_flag6_groups[] = { + "gpio53", +}; +static const char * const SD_CARD_groups[] = { + "gpio54", +}; +static const char * const phase_flag29_groups[] = { + "gpio54", +}; +static const char * const DP_EN_groups[] = { + "gpio55", +}; +static const char * const phase_flag25_groups[] = { + "gpio55", +}; +static const char * const USBC_ORIENTATION_groups[] = { + "gpio56", +}; +static const char * const phase_flag10_groups[] = { + "gpio56", +}; +static const char * const atest_usb20_groups[] = { + "gpio56", +}; +static const char * const gcc_gp1_groups[] = { + "gpio57", "gpio78", +}; +static const char * const phase_flag4_groups[] = { + "gpio57", +}; +static const char * const atest_usb22_groups[] = { + "gpio57", +}; +static const char * const USB_PHY_groups[] = { + "gpio58", +}; +static const char * const gcc_gp2_groups[] = { + "gpio58", "gpio81", +}; +static const char * const atest_char_groups[] = { + "gpio58", +}; +static const char * const mdp_vsync_groups[] = { + "gpio59", "gpio74", +}; +static const char * const gcc_gp3_groups[] = { + "gpio59", "gpio82", +}; +static const char * const atest_char3_groups[] = { + "gpio59", +}; +static const char * const FORCE_TOUCH_groups[] = { + "gpio60", "gpio73", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const atest_char2_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const atest_char1_groups[] = { + "gpio61", +}; +static const char * const AUDIO_USBC_groups[] = { + "gpio62", +}; +static const char * const audio_ref_groups[] = { + "gpio62", +}; +static const char * const MDP_VSYNC_groups[] = { + "gpio62", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const atest_char0_groups[] = { + "gpio62", +}; +static const char * const US_EURO_groups[] = { + "gpio63", +}; +static const char * const LCD_BACKLIGHT_groups[] = { + "gpio64", +}; +static const char * const blsp_spi8_cs1_groups[] = { + "gpio64", +}; +static const char * const blsp_spi8_cs2_groups[] = { + "gpio76", +}; +static const char * const sp_cmu_groups[] = { + "gpio64", +}; +static const char * const nav_pps_a_groups[] = { + "gpio65", +}; +static const char * const nav_pps_b_groups[] = { + "gpio98", +}; +static const char * const nav_pps_c_groups[] = { + "gpio80", +}; +static const char * const gps_tx_a_groups[] = { + "gpio65", +}; +static const char * const gps_tx_b_groups[] = { + "gpio98", +}; +static const char * const gps_tx_c_groups[] = { + "gpio80", +}; +static const char * const adsp_ext_groups[] = { + "gpio65", +}; +static const char * const TS_RESET_groups[] = { + "gpio66", +}; +static const char * const ssc_irq_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio74", + "gpio75", "gpio76", +}; +static const char * const isense_dbg_groups[] = { + "gpio68", +}; +static const char * const phase_flag0_groups[] = { + "gpio68", +}; +static const char * const phase_flag7_groups[] = { + "gpio69", +}; +static const char * const phase_flag8_groups[] = { + "gpio70", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const SENSOR_RST_groups[] = { + "gpio77", +}; +static const char * const WMSS_RESETN_groups[] = { + "gpio78", +}; +static const char * const HAPTICS_PWM_groups[] = { + "gpio79", +}; +static const char * const GPS_eLNA_groups[] = { + "gpio80", +}; +static const char * const mss_lte_groups[] = { + "gpio81", "gpio82", +}; +static const char * const uim2_data_groups[] = { + "gpio83", +}; +static const char * const uim2_clk_groups[] = { + "gpio84", +}; +static const char * const uim2_reset_groups[] = { + "gpio85", +}; +static const char * const uim2_present_groups[] = { + "gpio86", +}; +static const char * const uim1_data_groups[] = { + "gpio87", +}; +static const char * const uim1_clk_groups[] = { + "gpio88", +}; +static const char * const uim1_reset_groups[] = { + "gpio89", +}; +static const char * const uim1_present_groups[] = { + "gpio90", +}; +static const char * const uim_batt_groups[] = { + "gpio91", +}; +static const char * const pa_indicator_groups[] = { + "gpio92", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const qlink_request_groups[] = { + "gpio99", +}; +static const char * const qlink_enable_groups[] = { + "gpio100", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; +static const char * const LCD_PWR_groups[] = { + "gpio113", +}; + +static const struct msm_function sdm660_functions[] = { + FUNCTION(blsp_spi1), + FUNCTION(gpio), + FUNCTION(blsp_uim1), + FUNCTION(tgu_ch0), + FUNCTION(qdss_gpio4), + FUNCTION(atest_gpsadc1), + FUNCTION(blsp_uart1), + FUNCTION(SMB_STAT), + FUNCTION(phase_flag14), + FUNCTION(blsp_i2c2), + FUNCTION(phase_flag31), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi3_cs1), + FUNCTION(blsp_spi3_cs2), + FUNCTION(wlan1_adc1), + FUNCTION(atest_usb13), + FUNCTION(tgu_ch1), + FUNCTION(qdss_gpio5), + FUNCTION(atest_gpsadc0), + FUNCTION(blsp_i2c1), + FUNCTION(ddr_bist), + FUNCTION(atest_tsens2), + FUNCTION(atest_usb1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_uim2), + FUNCTION(phase_flag3), + FUNCTION(bimc_dte1), + FUNCTION(wlan1_adc0), + FUNCTION(atest_usb12), + FUNCTION(bimc_dte0), + FUNCTION(blsp_i2c3), + FUNCTION(wlan2_adc1), + FUNCTION(atest_usb11), + FUNCTION(dbg_out), + FUNCTION(wlan2_adc0), + FUNCTION(atest_usb10), + FUNCTION(RCM_MARKER), + FUNCTION(blsp_spi4), + FUNCTION(pri_mi2s), + FUNCTION(phase_flag26), + FUNCTION(qdss_cti0_a), + FUNCTION(qdss_cti0_b), + FUNCTION(qdss_cti1_a), + FUNCTION(qdss_cti1_b), + FUNCTION(DP_HOT), + FUNCTION(pri_mi2s_ws), + FUNCTION(phase_flag27), + FUNCTION(blsp_i2c4), + FUNCTION(phase_flag28), + FUNCTION(blsp_uart5), + FUNCTION(blsp_spi5), + FUNCTION(blsp_uim5), + FUNCTION(phase_flag5), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uim6), + FUNCTION(phase_flag11), + FUNCTION(vsense_data0), + FUNCTION(blsp_i2c6), + FUNCTION(phase_flag12), + FUNCTION(vsense_data1), + FUNCTION(phase_flag13), + FUNCTION(vsense_mode), + FUNCTION(blsp_spi7), + FUNCTION(blsp_uart6_a), + FUNCTION(blsp_uart6_b), + FUNCTION(sec_mi2s), + FUNCTION(sndwire_clk), + FUNCTION(phase_flag17), + FUNCTION(vsense_clkout), + FUNCTION(sndwire_data), + FUNCTION(phase_flag18), + FUNCTION(WSA_SPKR), + FUNCTION(blsp_i2c7), + FUNCTION(phase_flag19), + FUNCTION(vfr_1), + FUNCTION(phase_flag20), + FUNCTION(NFC_INT), + FUNCTION(blsp_spi8_cs1), + FUNCTION(blsp_spi8_cs2), + FUNCTION(m_voc), + FUNCTION(phase_flag21), + FUNCTION(NFC_EN), + FUNCTION(phase_flag22), + FUNCTION(NFC_DWL), + FUNCTION(blsp_i2c8_a), + FUNCTION(blsp_i2c8_b), + FUNCTION(phase_flag23), + FUNCTION(NFC_ESE), + FUNCTION(pwr_modem), + FUNCTION(phase_flag24), + FUNCTION(qdss_gpio), + FUNCTION(cam_mclk), + FUNCTION(pwr_nav), + FUNCTION(qdss_gpio0), + FUNCTION(qspi_data0), + FUNCTION(pwr_crypto), + FUNCTION(qdss_gpio1), + FUNCTION(qspi_data1), + FUNCTION(agera_pll), + FUNCTION(qdss_gpio2), + FUNCTION(qspi_data2), + FUNCTION(jitter_bist), + FUNCTION(qdss_gpio3), + FUNCTION(qdss_gpio7), + FUNCTION(FL_R3LED), + FUNCTION(CCI_TIMER0), + FUNCTION(FL_STROBE), + FUNCTION(CCI_TIMER1), + FUNCTION(CAM_LDO1), + FUNCTION(mdss_vsync0), + FUNCTION(mdss_vsync1), + FUNCTION(mdss_vsync2), + FUNCTION(mdss_vsync3), + FUNCTION(qdss_gpio9), + FUNCTION(CAM_IRQ), + FUNCTION(atest_usb2), + FUNCTION(cci_i2c), + FUNCTION(pll_bypassnl), + FUNCTION(atest_tsens), + FUNCTION(atest_usb21), + FUNCTION(pll_reset), + FUNCTION(atest_usb23), + FUNCTION(qdss_gpio6), + FUNCTION(CCI_TIMER3), + FUNCTION(CCI_ASYNC), + FUNCTION(qspi_cs), + FUNCTION(qdss_gpio10), + FUNCTION(CAM3_STANDBY), + FUNCTION(CCI_TIMER4), + FUNCTION(qdss_gpio11), + FUNCTION(CAM_LDO2), + FUNCTION(cci_async), + FUNCTION(qdss_gpio12), + FUNCTION(CAM0_RST), + FUNCTION(qdss_gpio13), + FUNCTION(CAM1_RST), + FUNCTION(qspi_clk), + FUNCTION(phase_flag30), + FUNCTION(qdss_gpio14), + FUNCTION(qspi_resetn), + FUNCTION(phase_flag1), + FUNCTION(qdss_gpio15), + FUNCTION(CAM0_STANDBY), + FUNCTION(phase_flag2), + FUNCTION(CAM1_STANDBY), + FUNCTION(phase_flag9), + FUNCTION(CAM2_STANDBY), + FUNCTION(qspi_data3), + FUNCTION(phase_flag15), + FUNCTION(qdss_gpio8), + FUNCTION(CAM3_RST), + FUNCTION(CCI_TIMER2), + FUNCTION(phase_flag16), + FUNCTION(LCD0_RESET), + FUNCTION(phase_flag6), + FUNCTION(SD_CARD), + FUNCTION(phase_flag29), + FUNCTION(DP_EN), + FUNCTION(phase_flag25), + FUNCTION(USBC_ORIENTATION), + FUNCTION(phase_flag10), + FUNCTION(atest_usb20), + FUNCTION(gcc_gp1), + FUNCTION(phase_flag4), + FUNCTION(atest_usb22), + FUNCTION(USB_PHY), + FUNCTION(gcc_gp2), + FUNCTION(atest_char), + FUNCTION(mdp_vsync), + FUNCTION(gcc_gp3), + FUNCTION(atest_char3), + FUNCTION(FORCE_TOUCH), + FUNCTION(cri_trng0), + FUNCTION(atest_char2), + FUNCTION(cri_trng1), + FUNCTION(atest_char1), + FUNCTION(AUDIO_USBC), + FUNCTION(audio_ref), + FUNCTION(MDP_VSYNC), + FUNCTION(cri_trng), + FUNCTION(atest_char0), + FUNCTION(US_EURO), + FUNCTION(LCD_BACKLIGHT), + FUNCTION(blsp_spi8_a), + FUNCTION(blsp_spi8_b), + FUNCTION(sp_cmu), + FUNCTION(nav_pps_a), + FUNCTION(nav_pps_b), + FUNCTION(nav_pps_c), + FUNCTION(gps_tx_a), + FUNCTION(gps_tx_b), + FUNCTION(gps_tx_c), + FUNCTION(adsp_ext), + FUNCTION(TS_RESET), + FUNCTION(ssc_irq), + FUNCTION(isense_dbg), + FUNCTION(phase_flag0), + FUNCTION(phase_flag7), + FUNCTION(phase_flag8), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(SENSOR_RST), + FUNCTION(WMSS_RESETN), + FUNCTION(HAPTICS_PWM), + FUNCTION(GPS_eLNA), + FUNCTION(mss_lte), + FUNCTION(uim2_data), + FUNCTION(uim2_clk), + FUNCTION(uim2_reset), + FUNCTION(uim2_present), + FUNCTION(uim1_data), + FUNCTION(uim1_clk), + FUNCTION(uim1_reset), + FUNCTION(uim1_present), + FUNCTION(uim_batt), + FUNCTION(pa_indicator), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(qlink_request), + FUNCTION(qlink_enable), + FUNCTION(prng_rosc), + FUNCTION(LCD_PWR), +}; + +static const struct msm_pingroup sdm660_groups[] = { + PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, NA, NA, + qdss_gpio4, atest_gpsadc1, NA), + PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, NA, NA, + qdss_gpio5, atest_gpsadc0, NA), + PINGROUP(2, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, + NA, NA), + PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, ddr_bist, NA, NA, + atest_tsens2, atest_usb1, NA), + PINGROUP(4, NORTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag3, NA, + NA, NA, NA, NA), + PINGROUP(5, SOUTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag14, NA, + NA, NA, NA, NA), + PINGROUP(6, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, phase_flag31, NA, + NA, NA, NA, NA), + PINGROUP(7, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, NA, NA, NA, NA, + NA, NA), + PINGROUP(8, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc1, + atest_usb13, bimc_dte1, NA), + PINGROUP(9, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc0, + atest_usb12, bimc_dte0, NA), + PINGROUP(10, NORTH, blsp_spi3, blsp_i2c3, ddr_bist, NA, NA, wlan2_adc1, + atest_usb11, bimc_dte1, NA), + PINGROUP(11, NORTH, blsp_spi3, blsp_i2c3, NA, dbg_out, wlan2_adc0, + atest_usb10, bimc_dte0, NA, NA), + PINGROUP(12, NORTH, blsp_spi4, pri_mi2s, NA, phase_flag26, qdss_cti1_b, + NA, NA, NA, NA), + PINGROUP(13, NORTH, blsp_spi4, DP_HOT, pri_mi2s_ws, NA, NA, + phase_flag27, qdss_cti0_b, NA, NA), + PINGROUP(14, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, phase_flag28, + NA, NA, NA, NA), + PINGROUP(15, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, NA, NA, NA, NA, + NA), + PINGROUP(16, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, NA, NA, NA, + NA, NA), + PINGROUP(17, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, phase_flag5, + NA, NA, NA, NA), + PINGROUP(18, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, + NA, NA), + PINGROUP(19, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, + NA, NA), + PINGROUP(20, SOUTH, NA, NA, blsp_uim6, NA, NA, NA, NA, + NA, NA), + PINGROUP(21, SOUTH, NA, NA, blsp_uim6, NA, phase_flag11, + qdss_cti0_b, vsense_data0, NA, NA), + PINGROUP(22, CENTER, blsp_spi6, NA, blsp_i2c6, NA, + phase_flag12, vsense_data1, NA, NA, NA), + PINGROUP(23, CENTER, blsp_spi6, NA, blsp_i2c6, NA, + phase_flag13, vsense_mode, NA, NA, NA), + PINGROUP(24, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_clk, NA, + NA, phase_flag17, vsense_clkout, NA), + PINGROUP(25, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_data, NA, + NA, phase_flag18, NA, NA), + PINGROUP(26, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, sec_mi2s, NA, + phase_flag19, NA, NA, NA), + PINGROUP(27, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, vfr_1, sec_mi2s, + NA, phase_flag20, NA, NA), + PINGROUP(28, CENTER, blsp_spi8_a, blsp_uart6_b, m_voc, NA, phase_flag21, + NA, NA, NA, NA), + PINGROUP(29, CENTER, blsp_spi8_a, blsp_uart6_b, NA, NA, phase_flag22, + NA, NA, NA, NA), + PINGROUP(30, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, + blsp_spi3_cs1, NA, phase_flag23, NA, NA, NA), + PINGROUP(31, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, pwr_modem, + NA, phase_flag24, qdss_gpio, NA, NA), + PINGROUP(32, SOUTH, cam_mclk, pwr_nav, NA, NA, qdss_gpio0, NA, NA, NA, + NA), + PINGROUP(33, SOUTH, cam_mclk, qspi_data0, pwr_crypto, NA, NA, + qdss_gpio1, NA, NA, NA), + PINGROUP(34, SOUTH, cam_mclk, qspi_data1, agera_pll, NA, NA, + qdss_gpio2, NA, NA, NA), + PINGROUP(35, SOUTH, cam_mclk, qspi_data2, jitter_bist, NA, NA, + qdss_gpio3, NA, atest_usb2, NA), + PINGROUP(36, SOUTH, cci_i2c, pll_bypassnl, agera_pll, NA, NA, + qdss_gpio4, atest_tsens, atest_usb21, NA), + PINGROUP(37, SOUTH, cci_i2c, pll_reset, NA, NA, qdss_gpio5, + atest_usb23, NA, NA, NA), + PINGROUP(38, SOUTH, cci_i2c, NA, NA, qdss_gpio6, NA, NA, NA, NA, NA), + PINGROUP(39, SOUTH, cci_i2c, NA, NA, qdss_gpio7, NA, NA, NA, NA, NA), + PINGROUP(40, SOUTH, CCI_TIMER0, NA, blsp_spi8_b, NA, NA, NA, NA, NA, + NA), + PINGROUP(41, SOUTH, CCI_TIMER1, NA, blsp_spi8_b, NA, NA, NA, NA, NA, + NA), + PINGROUP(42, SOUTH, mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, + NA, NA, qdss_gpio9, NA, NA), + PINGROUP(43, SOUTH, CCI_TIMER3, CCI_ASYNC, qspi_cs, NA, NA, + qdss_gpio10, NA, NA, NA), + PINGROUP(44, SOUTH, CCI_TIMER4, CCI_ASYNC, blsp_spi8_b, blsp_i2c8_b, NA, + NA, qdss_gpio11, NA, NA), + PINGROUP(45, SOUTH, cci_async, NA, NA, qdss_gpio12, NA, NA, NA, NA, NA), + PINGROUP(46, SOUTH, blsp_spi1, NA, NA, qdss_gpio13, NA, NA, NA, NA, NA), + PINGROUP(47, SOUTH, qspi_clk, NA, phase_flag30, qdss_gpio14, NA, NA, + NA, NA, NA), + PINGROUP(48, SOUTH, NA, phase_flag1, qdss_gpio15, NA, NA, NA, NA, NA, + NA), + PINGROUP(49, SOUTH, blsp_spi6, phase_flag2, qdss_cti0_a, NA, NA, NA, + NA, NA, NA), + PINGROUP(50, SOUTH, qspi_cs, NA, phase_flag9, qdss_cti0_a, NA, NA, NA, + NA, NA), + PINGROUP(51, SOUTH, qspi_data3, NA, phase_flag15, qdss_gpio8, NA, NA, + NA, NA, NA), + PINGROUP(52, SOUTH, CCI_TIMER2, blsp_spi8_b, blsp_i2c8_b, blsp_spi6, + phase_flag16, qdss_gpio, NA, NA, NA), + PINGROUP(53, NORTH, NA, phase_flag6, qdss_cti1_a, NA, NA, NA, NA, NA, + NA), + PINGROUP(54, NORTH, NA, NA, phase_flag29, NA, NA, NA, NA, NA, NA), + PINGROUP(55, SOUTH, NA, phase_flag25, qdss_cti1_a, NA, NA, NA, NA, NA, + NA), + PINGROUP(56, SOUTH, NA, phase_flag10, qdss_gpio3, NA, atest_usb20, NA, + NA, NA, NA), + PINGROUP(57, SOUTH, gcc_gp1, NA, phase_flag4, atest_usb22, NA, NA, NA, + NA, NA), + PINGROUP(58, SOUTH, USB_PHY, gcc_gp2, NA, NA, atest_char, NA, NA, NA, + NA), + PINGROUP(59, NORTH, mdp_vsync, gcc_gp3, NA, NA, atest_char3, NA, NA, + NA, NA), + PINGROUP(60, NORTH, cri_trng0, NA, NA, atest_char2, NA, NA, NA, NA, NA), + PINGROUP(61, NORTH, pri_mi2s, cri_trng1, NA, NA, atest_char1, NA, NA, + NA, NA), + PINGROUP(62, NORTH, sec_mi2s, audio_ref, MDP_VSYNC, cri_trng, NA, NA, + atest_char0, NA, NA), + PINGROUP(63, NORTH, NA, NA, NA, qdss_gpio1, NA, NA, NA, NA, NA), + PINGROUP(64, SOUTH, blsp_spi8_cs1, sp_cmu, NA, NA, qdss_gpio2, NA, NA, + NA, NA), + PINGROUP(65, SOUTH, NA, nav_pps_a, nav_pps_a, gps_tx_a, blsp_spi3_cs2, + adsp_ext, NA, NA, NA), + PINGROUP(66, NORTH, NA, NA, qdss_cti1_b, NA, NA, NA, NA, NA, NA), + PINGROUP(67, NORTH, NA, NA, qdss_gpio0, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NORTH, isense_dbg, NA, phase_flag0, qdss_gpio, NA, NA, NA, + NA, NA), + PINGROUP(69, NORTH, NA, phase_flag7, qdss_gpio, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NORTH, NA, phase_flag8, qdss_gpio6, NA, NA, NA, NA, NA, + NA), + PINGROUP(71, NORTH, NA, NA, qdss_gpio7, tsense_pwm1, tsense_pwm2, NA, + NA, NA, NA), + PINGROUP(72, NORTH, NA, qdss_gpio14, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NORTH, NA, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NORTH, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NORTH, NA, NA, qdss_gpio8, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NORTH, blsp_spi8_cs2, NA, NA, NA, qdss_gpio9, NA, NA, NA, + NA), + PINGROUP(77, NORTH, NA, NA, qdss_gpio10, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NORTH, gcc_gp1, NA, qdss_gpio13, NA, NA, NA, NA, NA, NA), + PINGROUP(79, SOUTH, NA, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA), + PINGROUP(80, SOUTH, nav_pps_b, nav_pps_b, gps_tx_c, NA, NA, qdss_gpio12, + NA, NA, NA), + PINGROUP(81, CENTER, mss_lte, gcc_gp2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, CENTER, mss_lte, gcc_gp3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, SOUTH, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, SOUTH, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, SOUTH, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, SOUTH, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, SOUTH, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, SOUTH, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, SOUTH, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, SOUTH, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, SOUTH, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, SOUTH, NA, NA, pa_indicator, NA, NA, NA, NA, NA, NA), + PINGROUP(93, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, SOUTH, NA, ldo_en, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, SOUTH, NA, nav_pps_c, nav_pps_c, gps_tx_b, ldo_update, NA, + NA, NA, NA), + PINGROUP(99, SOUTH, qlink_request, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, SOUTH, qlink_enable, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, SOUTH, NA, prng_rosc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_QDSD_PINGROUP(sdc1_clk, 0x99a000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x99a000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x99a000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x99b000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x99b000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x99b000, 9, 0), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x99a000, 15, 0), +}; + +static const struct msm_pinctrl_soc_data sdm660_pinctrl = { + .pins = sdm660_pins, + .npins = ARRAY_SIZE(sdm660_pins), + .functions = sdm660_functions, + .nfunctions = ARRAY_SIZE(sdm660_functions), + .groups = sdm660_groups, + .ngroups = ARRAY_SIZE(sdm660_groups), + .ngpios = 114, +}; + +static int sdm660_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdm660_pinctrl); +} + +static const struct of_device_id sdm660_pinctrl_of_match[] = { + { .compatible = "qcom,sdm660-pinctrl", }, + { }, +}; + +static struct platform_driver sdm660_pinctrl_driver = { + .driver = { + .name = "sdm660-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sdm660_pinctrl_of_match, + }, + .probe = sdm660_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdm660_pinctrl_init(void) +{ + return platform_driver_register(&sdm660_pinctrl_driver); +} +arch_initcall(sdm660_pinctrl_init); + +static void __exit sdm660_pinctrl_exit(void) +{ + platform_driver_unregister(&sdm660_pinctrl_driver); +} +module_exit(sdm660_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdm660 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match); diff --git a/drivers/platform/msm/qpnp-revid.c b/drivers/platform/msm/qpnp-revid.c index cfc8093fa3dd..6b5db58f856a 100644 --- a/drivers/platform/msm/qpnp-revid.c +++ b/drivers/platform/msm/qpnp-revid.c @@ -56,8 +56,8 @@ static const char *const pmic_names[] = { [PMI8998_SUBTYPE] = "PMI8998", [PM8005_SUBTYPE] = "PM8005", [PM8937_SUBTYPE] = "PM8937", - [PM2FALCON_SUBTYPE] = "PM2FALCON", - [PMFALCON_SUBTYPE] = "PMFALCON", + [PM660L_SUBTYPE] = "PM660L", + [PM660_SUBTYPE] = "PM660", [PMI8937_SUBTYPE] = "PMI8937", }; diff --git a/drivers/power/qcom-charger/qpnp-fg-gen3.c b/drivers/power/qcom-charger/qpnp-fg-gen3.c index 7c1ece431beb..edd9b9ff28cf 100644 --- a/drivers/power/qcom-charger/qpnp-fg-gen3.c +++ b/drivers/power/qcom-charger/qpnp-fg-gen3.c @@ -3157,7 +3157,7 @@ static int fg_parse_dt(struct fg_chip *chip) return -EINVAL; } break; - case PMFALCON_SUBTYPE: + case PM660_SUBTYPE: chip->sp = pmi8998_v2_sram_params; chip->alg_flags = pmi8998_v2_alg_flags; break; diff --git a/drivers/power/qcom-charger/qpnp-smb2.c b/drivers/power/qcom-charger/qpnp-smb2.c index 90e3689086a6..463cbb7cb8ba 100644 --- a/drivers/power/qcom-charger/qpnp-smb2.c +++ b/drivers/power/qcom-charger/qpnp-smb2.c @@ -1453,7 +1453,7 @@ static int smb2_setup_wa_flags(struct smb2 *chip) if (pmic_rev_id->rev4 == PMI8998_V2P0_REV4) /* PMI rev 2.0 */ chg->wa_flags |= TYPEC_CC2_REMOVAL_WA_BIT; break; - case PMFALCON_SUBTYPE: + case PM660_SUBTYPE: chip->chg.wa_flags |= BOOST_BACK_WA; break; default: diff --git a/drivers/regulator/cpr4-mmss-ldo-regulator.c b/drivers/regulator/cpr4-mmss-ldo-regulator.c index 9fa5c309b02a..69c11a9e5da2 100644 --- a/drivers/regulator/cpr4-mmss-ldo-regulator.c +++ b/drivers/regulator/cpr4-mmss-ldo-regulator.c @@ -36,10 +36,10 @@ #include "cpr3-regulator.h" -#define MSMFALCON_MMSS_FUSE_CORNERS 6 +#define SDM660_MMSS_FUSE_CORNERS 6 /** - * struct cpr4_msmfalcon_mmss_fuses - MMSS specific fuse data for MSMFALCON + * struct cpr4_sdm660_mmss_fuses - MMSS specific fuse data for SDM660 * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value * for each fuse corner (raw, not converted to a voltage) * @offset_voltage: The closed-loop voltage margin adjustment fuse parameter @@ -55,19 +55,19 @@ * * This struct holds the values for all of the fuses read from memory. */ -struct cpr4_msmfalcon_mmss_fuses { - u64 init_voltage[MSMFALCON_MMSS_FUSE_CORNERS]; - u64 offset_voltage[MSMFALCON_MMSS_FUSE_CORNERS]; +struct cpr4_sdm660_mmss_fuses { + u64 init_voltage[SDM660_MMSS_FUSE_CORNERS]; + u64 offset_voltage[SDM660_MMSS_FUSE_CORNERS]; u64 cpr_fusing_rev; - u64 ldo_enable[MSMFALCON_MMSS_FUSE_CORNERS]; + u64 ldo_enable[SDM660_MMSS_FUSE_CORNERS]; u64 ldo_cpr_cl_enable; }; /* Fuse combos 0 - 7 map to CPR fusing revision 0 - 7 */ -#define CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT 8 +#define CPR4_SDM660_MMSS_FUSE_COMBO_COUNT 8 /* - * MSMFALCON MMSS fuse parameter locations: + * SDM660 MMSS fuse parameter locations: * * Structs are organized with the following dimensions: * Outer: 0 to 3 for fuse corners from lowest to highest corner @@ -79,7 +79,7 @@ struct cpr4_msmfalcon_mmss_fuses { * a given parameter may correspond to different fuse rows. */ static const struct cpr3_fuse_param -msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { +sdm660_mmss_init_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = { {{65, 39, 43}, {} }, {{65, 39, 43}, {} }, {{65, 34, 38}, {} }, @@ -88,13 +88,13 @@ msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { {{65, 24, 28}, {} }, }; -static const struct cpr3_fuse_param msmfalcon_cpr_fusing_rev_param[] = { +static const struct cpr3_fuse_param sdm660_cpr_fusing_rev_param[] = { {71, 34, 36}, {}, }; static const struct cpr3_fuse_param -msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { +sdm660_mmss_offset_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = { {{} }, {{} }, {{} }, @@ -104,7 +104,7 @@ msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { }; static const struct cpr3_fuse_param -msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { +sdm660_mmss_ldo_enable_param[SDM660_MMSS_FUSE_CORNERS][2] = { {{73, 62, 62}, {} }, {{73, 61, 61}, {} }, {{73, 60, 60}, {} }, @@ -113,15 +113,15 @@ msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { {{73, 57, 57}, {} }, }; -static const struct cpr3_fuse_param msmfalcon_ldo_cpr_cl_enable_param[] = { +static const struct cpr3_fuse_param sdm660_ldo_cpr_cl_enable_param[] = { {71, 38, 38}, {}, }; -/* Additional MSMFALCON specific data: */ +/* Additional SDM660 specific data: */ /* Open loop voltage fuse reference voltages in microvolts */ -static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = { +static const int sdm660_mmss_fuse_ref_volt[SDM660_MMSS_FUSE_CORNERS] = { 584000, 644000, 724000, @@ -130,36 +130,36 @@ static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = { 924000, }; -#define MSMFALCON_MMSS_FUSE_STEP_VOLT 10000 -#define MSMFALCON_MMSS_OFFSET_FUSE_STEP_VOLT 10000 -#define MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE 5 +#define SDM660_MMSS_FUSE_STEP_VOLT 10000 +#define SDM660_MMSS_OFFSET_FUSE_STEP_VOLT 10000 +#define SDM660_MMSS_VOLTAGE_FUSE_SIZE 5 -#define MSMFALCON_MMSS_CPR_SENSOR_COUNT 11 +#define SDM660_MMSS_CPR_SENSOR_COUNT 11 -#define MSMFALCON_MMSS_CPR_CLOCK_RATE 19200000 +#define SDM660_MMSS_CPR_CLOCK_RATE 19200000 /** - * cpr4_msmfalcon_mmss_read_fuse_data() - load MMSS specific fuse parameter + * cpr4_sdm660_mmss_read_fuse_data() - load MMSS specific fuse parameter * values * @vreg: Pointer to the CPR3 regulator * - * This function allocates a cpr4_msmfalcon_mmss_fuses struct, fills it with + * This function allocates a cpr4_sdm660_mmss_fuses struct, fills it with * values read out of hardware fuses, and finally copies common fuse values * into the regulator struct. * * Return: 0 on success, errno on failure */ -static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) +static int cpr4_sdm660_mmss_read_fuse_data(struct cpr3_regulator *vreg) { void __iomem *base = vreg->thread->ctrl->fuse_base; - struct cpr4_msmfalcon_mmss_fuses *fuse; + struct cpr4_sdm660_mmss_fuses *fuse; int i, rc; fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); if (!fuse) return -ENOMEM; - rc = cpr3_read_fuse_param(base, msmfalcon_cpr_fusing_rev_param, + rc = cpr3_read_fuse_param(base, sdm660_cpr_fusing_rev_param, &fuse->cpr_fusing_rev); if (rc) { cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n", @@ -168,7 +168,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev); - rc = cpr3_read_fuse_param(base, msmfalcon_ldo_cpr_cl_enable_param, + rc = cpr3_read_fuse_param(base, sdm660_ldo_cpr_cl_enable_param, &fuse->ldo_cpr_cl_enable); if (rc) { cpr3_err(vreg, "Unable to read ldo cpr closed-loop enable fuse, rc=%d\n", @@ -176,9 +176,9 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) return rc; } - for (i = 0; i < MSMFALCON_MMSS_FUSE_CORNERS; i++) { + for (i = 0; i < SDM660_MMSS_FUSE_CORNERS; i++) { rc = cpr3_read_fuse_param(base, - msmfalcon_mmss_init_voltage_param[i], + sdm660_mmss_init_voltage_param[i], &fuse->init_voltage[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n", @@ -187,7 +187,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmfalcon_mmss_offset_voltage_param[i], + sdm660_mmss_offset_voltage_param[i], &fuse->offset_voltage[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d offset voltage fuse, rc=%d\n", @@ -196,7 +196,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmfalcon_mmss_ldo_enable_param[i], + sdm660_mmss_ldo_enable_param[i], &fuse->ldo_enable[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d ldo enable fuse, rc=%d\n", @@ -206,31 +206,31 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } vreg->fuse_combo = fuse->cpr_fusing_rev; - if (vreg->fuse_combo >= CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT) { + if (vreg->fuse_combo >= CPR4_SDM660_MMSS_FUSE_COMBO_COUNT) { cpr3_err(vreg, "invalid CPR fuse combo = %d found, not in range 0 - %d\n", vreg->fuse_combo, - CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT - 1); + CPR4_SDM660_MMSS_FUSE_COMBO_COUNT - 1); return -EINVAL; } vreg->cpr_rev_fuse = fuse->cpr_fusing_rev; - vreg->fuse_corner_count = MSMFALCON_MMSS_FUSE_CORNERS; + vreg->fuse_corner_count = SDM660_MMSS_FUSE_CORNERS; vreg->platform_fuses = fuse; return 0; } /** - * cpr3_msmfalcon_mmss_calculate_open_loop_voltages() - calculate the open-loop + * cpr3_sdm660_mmss_calculate_open_loop_voltages() - calculate the open-loop * voltage for each corner of a CPR3 regulator * @vreg: Pointer to the CPR3 regulator * * Return: 0 on success, errno on failure */ -static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages( +static int cpr4_sdm660_mmss_calculate_open_loop_voltages( struct cpr3_regulator *vreg) { - struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses; + struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses; int i, rc = 0; const int *ref_volt; int *fuse_volt; @@ -240,11 +240,11 @@ static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages( if (!fuse_volt) return -ENOMEM; - ref_volt = msmfalcon_mmss_fuse_ref_volt; + ref_volt = sdm660_mmss_fuse_ref_volt; for (i = 0; i < vreg->fuse_corner_count; i++) { fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(ref_volt[i], - MSMFALCON_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i], - MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE); + SDM660_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i], + SDM660_MMSS_VOLTAGE_FUSE_SIZE); cpr3_info(vreg, "fuse_corner[%d] open-loop=%7d uV\n", i, fuse_volt[i]); } @@ -298,7 +298,7 @@ done: */ static int cpr4_mmss_parse_ldo_mode_data(struct cpr3_regulator *vreg) { - struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses; + struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses; int i, rc = 0; u32 *ldo_allowed; char *prop_str = "qcom,cpr-corner-allow-ldo-mode"; @@ -341,7 +341,7 @@ done: */ static int cpr4_mmss_parse_corner_operating_mode(struct cpr3_regulator *vreg) { - struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses; + struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses; int i, rc = 0; u32 *use_closed_loop; char *prop_str = "qcom,cpr-corner-allow-closed-loop"; @@ -476,7 +476,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread) vreg->ldo_regulator_bypass = BHS_MODE; vreg->ldo_type = CPR3_LDO300; - rc = cpr4_msmfalcon_mmss_read_fuse_data(vreg); + rc = cpr4_sdm660_mmss_read_fuse_data(vreg); if (rc) { cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc); return rc; @@ -489,7 +489,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread) return rc; } - rc = cpr4_msmfalcon_mmss_calculate_open_loop_voltages(vreg); + rc = cpr4_sdm660_mmss_calculate_open_loop_voltages(vreg); if (rc) { cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n", rc); @@ -548,7 +548,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl) return rc; } - ctrl->sensor_count = MSMFALCON_MMSS_CPR_SENSOR_COUNT; + ctrl->sensor_count = SDM660_MMSS_CPR_SENSOR_COUNT; /* * MMSS only has one thread (0) so the zeroed array does not need @@ -559,7 +559,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl) if (!ctrl->sensor_owner) return -ENOMEM; - ctrl->cpr_clock_rate = MSMFALCON_MMSS_CPR_CLOCK_RATE; + ctrl->cpr_clock_rate = SDM660_MMSS_CPR_CLOCK_RATE; ctrl->ctrl_type = CPR_CTRL_TYPE_CPR4; ctrl->support_ldo300_vreg = true; @@ -572,7 +572,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl) &ctrl->step_quot_fixed); ctrl->use_dynamic_step_quot = !ctrl->step_quot_fixed; - /* iface_clk is optional for msmfalcon */ + /* iface_clk is optional for sdm660 */ ctrl->iface_clk = NULL; ctrl->bus_clk = devm_clk_get(ctrl->dev, "bus_clk"); if (IS_ERR(ctrl->bus_clk)) { @@ -688,7 +688,7 @@ static int cpr4_mmss_regulator_resume(struct platform_device *pdev) /* Data corresponds to the SoC revision */ static const struct of_device_id cpr4_mmss_regulator_match_table[] = { { - .compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator", + .compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator", .data = (void *)NULL, }, }; diff --git a/drivers/regulator/msm_gfx_ldo.c b/drivers/regulator/msm_gfx_ldo.c index d2f743b8089a..265ca9ed5258 100644 --- a/drivers/regulator/msm_gfx_ldo.c +++ b/drivers/regulator/msm_gfx_ldo.c @@ -152,7 +152,7 @@ static struct ldo_config msm8953_ldo_config[] = { {LDO_MAX_OFFSET, LDO_MAX_OFFSET}, }; -static struct ldo_config msmfalcon_ldo_config[] = { +static struct ldo_config sdm660_ldo_config[] = { {LDO_ATEST_REG, 0x00000080}, {LDO_CFG0_REG, 0x0100A600}, {LDO_CFG1_REG, 0x000000A0}, @@ -185,7 +185,7 @@ static const int msm8953_fuse_ref_volt[MSM8953_LDO_FUSE_CORNERS] = { enum { MSM8953_SOC_ID, - MSMFALCON_SOC_ID, + SDM660_SOC_ID, }; static int convert_open_loop_voltage_fuse(int ref_volt, int step_volt, @@ -1516,8 +1516,8 @@ static const struct of_device_id msm_gfx_ldo_match_table[] = { .data = (void *)(uintptr_t)MSM8953_SOC_ID, }, { - .compatible = "qcom,msmfalcon-gfx-ldo", - .data = (void *)(uintptr_t)MSMFALCON_SOC_ID, + .compatible = "qcom,sdm660-gfx-ldo", + .data = (void *)(uintptr_t)SDM660_SOC_ID, }, {} }; @@ -1572,8 +1572,8 @@ static int msm_gfx_ldo_probe(struct platform_device *pdev) return rc; } break; - case MSMFALCON_SOC_ID: - ldo_vreg->ldo_init_config = msmfalcon_ldo_config; + case SDM660_SOC_ID: + ldo_vreg->ldo_init_config = sdm660_ldo_config; ldo_vreg->ops_type = VOLTAGE; init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_BYPASS; diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index bd58fcfe3061..ff5eca31323c 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -535,9 +535,9 @@ static struct msm_soc_info cpu_of_id[] = { /* Hamster ID */ [306] = {MSM_CPU_HAMSTER, "MSMHAMSTER"}, - /* falcon ID */ - [317] = {MSM_CPU_FALCON, "MSMFALCON"}, - [324] = {MSM_CPU_FALCON, "APQFALCON"}, + /* 660 ID */ + [317] = {MSM_CPU_660, "SDM660"}, + [324] = {MSM_CPU_660, "SDA660"}, /* triton ID */ [318] = {MSM_CPU_TRITON, "MSMTRITON"}, @@ -1208,13 +1208,13 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 306; strlcpy(dummy_socinfo.build_id, "msmhamster - ", sizeof(dummy_socinfo.build_id)); - } else if (early_machine_is_msmfalcon()) { + } else if (early_machine_is_sdm660()) { dummy_socinfo.id = 317; - strlcpy(dummy_socinfo.build_id, "msmfalcon - ", + strlcpy(dummy_socinfo.build_id, "sdm660 - ", sizeof(dummy_socinfo.build_id)); - } else if (early_machine_is_apqfalcon()) { + } else if (early_machine_is_sda660()) { dummy_socinfo.id = 324; - strlcpy(dummy_socinfo.build_id, "apqfalcon - ", + strlcpy(dummy_socinfo.build_id, "sda660 - ", sizeof(dummy_socinfo.build_id)); } else if (early_machine_is_msmtriton()) { dummy_socinfo.id = 318; diff --git a/drivers/thermal/msm-tsens.c b/drivers/thermal/msm-tsens.c index 243b3229f53e..07a1fad03c31 100644 --- a/drivers/thermal/msm-tsens.c +++ b/drivers/thermal/msm-tsens.c @@ -937,7 +937,7 @@ static struct of_device_id tsens_match[] = { { .compatible = "qcom,msmhamster-tsens", .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, }, - { .compatible = "qcom,msmfalcon-tsens", + { .compatible = "qcom,sdm660-tsens", .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, }, { .compatible = "qcom,msmtriton-tsens", @@ -5507,7 +5507,7 @@ static int get_device_tree_data(struct platform_device *pdev, (!strcmp(id->compatible, "qcom,msm8998-tsens"))) tmdev->tsens_type = TSENS_TYPE3; else if (!strcmp(id->compatible, "qcom,msmtitanium-tsens") || - (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || + (!strcmp(id->compatible, "qcom,sdm660-tsens") || (!strcmp(id->compatible, "qcom,msmtriton-tsens") || (!strcmp(id->compatible, "qcom,msmhamster-tsens"))))) { tmdev->tsens_type = TSENS_TYPE3; @@ -5530,7 +5530,7 @@ static int get_device_tree_data(struct platform_device *pdev, (!strcmp(id->compatible, "qcom,msm8937-tsens")) || (!strcmp(id->compatible, "qcom,msmtitanium-tsens")) || (!strcmp(id->compatible, "qcom,msm8998-tsens")) || - (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || + (!strcmp(id->compatible, "qcom,sdm660-tsens") || (!strcmp(id->compatible, "qcom,msmtriton-tsens") || (!strcmp(id->compatible, "qcom,msmhamster-tsens"))))) tmdev->tsens_valid_status_check = true; @@ -5547,7 +5547,7 @@ static int get_device_tree_data(struct platform_device *pdev, if (!strcmp(id->compatible, "qcom,msm8996-tsens") || (!strcmp(id->compatible, "qcom,msm8998-tsens")) || (!strcmp(id->compatible, "qcom,msmhamster-tsens")) || - (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || + (!strcmp(id->compatible, "qcom,sdm660-tsens") || (!strcmp(id->compatible, "qcom,msmtriton-tsens") || (!strcmp(id->compatible, "qcom,msmtitanium-tsens"))))) { tmdev->tsens_critical_irq = -- cgit v1.2.3