From aac8aa7717a23a9bf8740dbfb59755b1d62f04bf Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 14 Jun 2005 17:35:03 +0000 Subject: Enable a suitable ISA for the assembler around ll/sc so that code builds even for processors that don't support the instructions. Plus minor formatting fixes. Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 74 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 24 deletions(-) (limited to 'include/asm-mips/bitops.h') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index eb8d79dba11c..1dc35879b362 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -18,14 +18,16 @@ #if (_MIPS_SZLONG == 32) #define SZLONG_LOG 5 #define SZLONG_MASK 31UL -#define __LL "ll " -#define __SC "sc " +#define __LL "ll " +#define __SC "sc " +#define __SET_MIPS ".set mips2 " #define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) #elif (_MIPS_SZLONG == 64) #define SZLONG_LOG 6 #define SZLONG_MASK 63UL -#define __LL "lld " -#define __SC "scd " +#define __LL "lld " +#define __SC "scd " +#define __SET_MIPS ".set mips3 " #define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) #endif @@ -72,18 +74,22 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else if (cpu_has_llsc) { __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else { @@ -132,18 +138,22 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); } else if (cpu_has_llsc) { __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); } else { @@ -191,10 +201,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) unsigned long temp; __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else if (cpu_has_llsc) { @@ -202,10 +214,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) unsigned long temp; __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else { @@ -253,14 +267,16 @@ static inline int test_and_set_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP - "sync \n" + " sync \n" #endif + " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -271,16 +287,18 @@ static inline int test_and_set_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - " .set noreorder # test_and_set_bit \n" - "1: " __LL "%0, %1 \n" + " .set push \n" + " .set noreorder \n" + " " __SET_MIPS " \n" + "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqz %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP - "sync \n" + " sync \n" #endif - ".set\treorder" + " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -343,15 +361,17 @@ static inline int test_and_clear_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" - __SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -362,17 +382,19 @@ static inline int test_and_clear_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - " .set noreorder # test_and_clear_bit \n" - "1: " __LL "%0, %1 \n" + " .set push \n" + " .set noreorder \n" + " " __SET_MIPS " \n" + "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" - __SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqz %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif - " .set reorder \n" + " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -435,14 +457,16 @@ static inline int test_and_change_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - "1: " __LL " %0, %1 # test_and_change_bit \n" + " " __SET_MIPS " \n" + "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" - " "__SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -453,16 +477,18 @@ static inline int test_and_change_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - " .set noreorder # test_and_change_bit \n" - "1: " __LL " %0, %1 \n" + " .set push \n" + " .set noreorder \n" + " " __SET_MIPS " \n" + "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" - " "__SC "\t%2, %1 \n" + " " __SC "\t%2, %1 \n" " beqz %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif - " .set reorder \n" + " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); -- cgit v1.2.3 From c4559f67b73d6c34fde0faac5c6c890a2cf3527c Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Thu, 23 Jun 2005 15:57:15 +0000 Subject: Always use ".set mips3" rather than select between "mips2" or "mips3" for assembling ll/sc sequences to avoid problems with 64-bit configurations. Signed-off-by: Ralf Baechle --- arch/mips/kernel/semaphore.c | 4 ++-- include/asm-mips/atomic.h | 20 ++++++++++---------- include/asm-mips/bitops.h | 26 ++++++++++++-------------- include/asm-mips/system.h | 10 +++++----- 4 files changed, 29 insertions(+), 31 deletions(-) (limited to 'include/asm-mips/bitops.h') diff --git a/arch/mips/kernel/semaphore.c b/arch/mips/kernel/semaphore.c index dbb145ee00a7..1265358cdca1 100644 --- a/arch/mips/kernel/semaphore.c +++ b/arch/mips/kernel/semaphore.c @@ -42,7 +42,7 @@ static inline int __sem_update_count(struct semaphore *sem, int incr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" @@ -55,7 +55,7 @@ static inline int __sem_update_count(struct semaphore *sem, int incr) : "r" (incr), "m" (sem->count)); } else if (cpu_has_llsc) { __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 80ea3fbd3ece..6202eb8a14b7 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -62,7 +62,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %1 # atomic_add \n" " addu %0, %2 \n" " sc %0, %1 \n" @@ -74,7 +74,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %1 # atomic_add \n" " addu %0, %2 \n" " sc %0, %1 \n" @@ -104,7 +104,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %1 # atomic_sub \n" " subu %0, %2 \n" " sc %0, %1 \n" @@ -116,7 +116,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %1 # atomic_sub \n" " subu %0, %2 \n" " sc %0, %1 \n" @@ -144,7 +144,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %1, %2 # atomic_add_return \n" " addu %0, %1, %3 \n" " sc %0, %2 \n" @@ -159,7 +159,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %1, %2 # atomic_add_return \n" " addu %0, %1, %3 \n" " sc %0, %2 \n" @@ -191,7 +191,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %1, %2 # atomic_sub_return \n" " subu %0, %1, %3 \n" " sc %0, %2 \n" @@ -206,7 +206,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %1, %2 # atomic_sub_return \n" " subu %0, %1, %3 \n" " sc %0, %2 \n" @@ -245,7 +245,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -261,7 +261,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 1dc35879b362..d9c02bd0b18e 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -20,14 +20,12 @@ #define SZLONG_MASK 31UL #define __LL "ll " #define __SC "sc " -#define __SET_MIPS ".set mips2 " #define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) #elif (_MIPS_SZLONG == 64) #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld " #define __SC "scd " -#define __SET_MIPS ".set mips3 " #define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) #endif @@ -74,7 +72,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" " " __SC "%0, %1 \n" @@ -84,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else if (cpu_has_llsc) { __asm__ __volatile__( - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" " " __SC "%0, %1 \n" @@ -138,7 +136,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" @@ -148,7 +146,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); } else if (cpu_has_llsc) { __asm__ __volatile__( - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" @@ -201,7 +199,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) unsigned long temp; __asm__ __volatile__( - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" " " __SC "%0, %1 \n" @@ -214,7 +212,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) unsigned long temp; __asm__ __volatile__( - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" " " __SC "%0, %1 \n" @@ -267,7 +265,7 @@ static inline int test_and_set_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" @@ -289,7 +287,7 @@ static inline int test_and_set_bit(unsigned long nr, __asm__ __volatile__( " .set push \n" " .set noreorder \n" - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" @@ -361,7 +359,7 @@ static inline int test_and_clear_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" @@ -384,7 +382,7 @@ static inline int test_and_clear_bit(unsigned long nr, __asm__ __volatile__( " .set push \n" " .set noreorder \n" - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" @@ -457,7 +455,7 @@ static inline int test_and_change_bit(unsigned long nr, unsigned long temp, res; __asm__ __volatile__( - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" " " __SC "%2, %1 \n" @@ -479,7 +477,7 @@ static inline int test_and_change_bit(unsigned long nr, __asm__ __volatile__( " .set push \n" " .set noreorder \n" - " " __SET_MIPS " \n" + " .set mips3 \n" "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" " " __SC "\t%2, %1 \n" diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index b9c24bbad9e2..30c7ec1675ca 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -176,7 +176,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) unsigned long dummy; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %3 # xchg_u32 \n" " move %2, %z4 \n" " sc %2, %1 \n" @@ -193,7 +193,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) unsigned long dummy; __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %3 # xchg_u32 \n" " move %2, %z4 \n" " sc %2, %1 \n" @@ -301,7 +301,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, __asm__ __volatile__( " .set push \n" " .set noat \n" - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %2 # __cmpxchg_u32 \n" " bne %0, %z3, 2f \n" " move $1, %z4 \n" @@ -320,7 +320,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, __asm__ __volatile__( " .set push \n" " .set noat \n" - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %2 # __cmpxchg_u32 \n" " bne %0, %z3, 2f \n" " move $1, %z4 \n" @@ -376,7 +376,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, __asm__ __volatile__( " .set push \n" " .set noat \n" - " .set mips2 \n" + " .set mips3 \n" "1: lld %0, %2 # __cmpxchg_u64 \n" " bne %0, %z3, 2f \n" " move $1, %z4 \n" -- cgit v1.2.3 From 6590326505e3f7b4b57793e84760e9920c3c56b4 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 12 Jul 2005 12:50:30 +0000 Subject: Use clz / dclz on MIPS32 / MIPS64 processors. Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 137 ++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 115 insertions(+), 22 deletions(-) (limited to 'include/asm-mips/bitops.h') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index d9c02bd0b18e..2ba20730a3e5 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -546,17 +546,60 @@ static inline int test_bit(unsigned long nr, const volatile unsigned long *addr) return 1UL & (addr[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK)); } +#ifdef CONFIG_CPU_MIPS32_R1 /* - * ffz - find first zero in word. + * Return the bit position (0..31) of the most significant 1 bit in a word + * Returns -1 if no 1 bit exists + */ +static __inline__ int __ilog2(unsigned long x) +{ + int lz; + + __asm__ ( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (lz) + : "r" (x)); + + return 31 - lz; +} +#elif defined(CONFIG_CPU_MIPS64_R1) +/* + * Return the bit position (0..63) of the most significant 1 bit in a word + * Returns -1 if no 1 bit exists + */ +static __inline__ int __ilog2(unsigned long x) +{ + int lz; + + __asm__ ( + " .set push \n" + " .set mips64 \n" + " dclz %0, %1 \n" + " .set pop \n" + : "=r" (lz) + : "r" (x)); + + return 63 - lz; +} +#endif + +/* + * __ffs - find first bit in word. * @word: The word to search * - * Undefined if no zero exists, so code should check against ~0UL first. + * Returns 0..SZLONG-1 + * Undefined if no bit exists, so code should check against 0 first. */ -static inline unsigned long ffz(unsigned long word) +static inline unsigned long __ffs(unsigned long word) { +#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1) + return __ilog2(word & -word); +#else int b = 0, s; - word = ~word; #ifdef CONFIG_32BIT s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s; s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s; @@ -572,26 +615,87 @@ static inline unsigned long ffz(unsigned long word) s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s; s = 1; if (word << 63 != 0) s = 0; b += s; #endif - return b; +#endif } /* - * __ffs - find first bit in word. + * ffs - find first bit set. * @word: The word to search * - * Undefined if no bit exists, so code should check against 0 first. + * Returns 1..SZLONG + * Returns 0 if no bit exists */ -static inline unsigned long __ffs(unsigned long word) + +static inline unsigned long ffs(unsigned long word) { - return ffz(~word); + if (!word) + return 0; + + return __ffs(word) + 1; } /* - * fls: find last bit set. + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. */ +static inline unsigned long ffz(unsigned long word) +{ + return __ffs (~word); +} + +/* + * flz - find last zero in word. + * @word: The word to search + * + * Returns 0..SZLONG-1 + * Undefined if no zero exists, so code should check against ~0UL first. + */ +static inline unsigned long flz(unsigned long word) +{ +#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1) + return __ilog2(~word); +#else +#if defined(CONFIG_32BIT) + int r = 31, s; + word = ~word; + s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s; + s = 8; if ((word & 0xff000000)) s = 0; r -= s; word <<= s; + s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s; + s = 2; if ((word & 0xc0000000)) s = 0; r -= s; word <<= s; + s = 1; if ((word & 0x80000000)) s = 0; r -= s; +#endif +#if defined(CONFIG_64BIT) + int r = 63, s; + word = ~word; + s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s; + s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s; + s = 8; if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s; + s = 4; if ((word & 0xf000000000000000UL)) s = 0; r -= s; word <<= s; + s = 2; if ((word & 0xc000000000000000UL)) s = 0; r -= s; word <<= s; + s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s; +#endif + return r; +#endif +} + +/* + * fls - find last bit set. + * @word: The word to search + * + * Returns 1..SZLONG + * Returns 0 if no bit exists + */ +static inline unsigned long fls(unsigned long word) +{ + if (word == 0) + return 0; + + return flz(~word) + 1; +} -#define fls(x) generic_fls(x) /* * find_next_zero_bit - find the first zero bit in a memory region @@ -727,17 +831,6 @@ static inline int sched_find_first_bit(const unsigned long *b) #endif } -/* - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - /* * hweightN - returns the hamming weight of a N-bit word * @x: the word to weigh -- cgit v1.2.3 From ec917c2c1ab4359a1d438e62daeb50cc42e632e1 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 7 Oct 2005 16:58:15 +0100 Subject: Fixup a few lose ends in explicit support for MIPS R1/R2. Signed-off-by: Ralf Baechle --- arch/mips/kernel/Makefile | 4 +- arch/mips/kernel/r4k_switch.S | 2 +- arch/mips/kernel/traps.c | 2 +- arch/mips/lib-32/Makefile | 4 +- arch/mips/lib-64/Makefile | 4 +- arch/mips/mm/Makefile | 4 +- arch/mips/oprofile/Makefile | 4 +- include/asm-mips/addrspace.h | 2 +- include/asm-mips/bitops.h | 54 +++++++++++----------- include/asm-mips/hazards.h | 2 +- include/asm-mips/interrupt.h | 11 ++--- include/asm-mips/mach-mips/cpu-feature-overrides.h | 4 +- include/asm-mips/page.h | 2 +- 13 files changed, 49 insertions(+), 50 deletions(-) (limited to 'include/asm-mips/bitops.h') diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 0213b3496170..72f2126ad19d 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -28,8 +28,8 @@ obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS32_R1) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS64_R1) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 27361f44defe..d2afbd19a9c8 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -165,7 +165,7 @@ LEAF(_init_fpu) 1: #endif -#ifdef CONFIG_CPU_MIPS32_R1 +#ifdef CONFIG_CPU_MIPS32 mtc1 t1, $f0 mtc1 t1, $f1 mtc1 t1, $f2 diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e38f24b2b3db..eccae8191602 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -885,7 +885,7 @@ asmlinkage void cache_parity_error(void) reg_val & (1<<22) ? "E0 " : ""); printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); -#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1) +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) if (reg_val & (1<<22)) printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile index 8119996736ae..ad285786e74b 100644 --- a/arch/mips/lib-32/Makefile +++ b/arch/mips/lib-32/Makefile @@ -4,8 +4,8 @@ lib-y += csum_partial.o memset.o watch.o -obj-$(CONFIG_CPU_MIPS32_R1) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS64_R1) += dump_tlb.o +obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o +obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o obj-$(CONFIG_CPU_R10000) += dump_tlb.o obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile index 8119996736ae..ad285786e74b 100644 --- a/arch/mips/lib-64/Makefile +++ b/arch/mips/lib-64/Makefile @@ -4,8 +4,8 @@ lib-y += csum_partial.o memset.o watch.o -obj-$(CONFIG_CPU_MIPS32_R1) += dump_tlb.o -obj-$(CONFIG_CPU_MIPS64_R1) += dump_tlb.o +obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o +obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o obj-$(CONFIG_CPU_R10000) += dump_tlb.o obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 0b738ad60fb9..b0178da019f0 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -9,8 +9,8 @@ obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o -obj-$(CONFIG_CPU_MIPS32_R1) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o -obj-$(CONFIG_CPU_MIPS64_R1) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o +obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o +obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-andes.o obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o pg-r4k.o diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index 17b411b22063..354261d37d62 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -10,6 +10,6 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \ oprofile-y := $(DRIVER_OBJS) common.o -oprofile-$(CONFIG_CPU_MIPS32_R1) += op_model_mipsxx.o -oprofile-$(CONFIG_CPU_MIPS64_R1) += op_model_mipsxx.o +oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o +oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 7abdb926faf1..16c1c08d0a03 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -131,7 +131,7 @@ || defined (CONFIG_CPU_R5000) \ || defined (CONFIG_CPU_NEVADA) \ || defined (CONFIG_CPU_TX49XX) \ - || defined (CONFIG_CPU_MIPS64_R1) + || defined (CONFIG_CPU_MIPS64) #define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ #define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */ #define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */ diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 2ba20730a3e5..5496f9064a6a 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -12,6 +12,7 @@ #include #include #include +#include #include /* sigh ... */ #include @@ -546,33 +547,27 @@ static inline int test_bit(unsigned long nr, const volatile unsigned long *addr) return 1UL & (addr[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK)); } -#ifdef CONFIG_CPU_MIPS32_R1 /* - * Return the bit position (0..31) of the most significant 1 bit in a word + * Return the bit position (0..63) of the most significant 1 bit in a word * Returns -1 if no 1 bit exists */ -static __inline__ int __ilog2(unsigned long x) +static inline int __ilog2(unsigned long x) { int lz; - __asm__ ( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (lz) - : "r" (x)); + if (sizeof(x) == 4) { + __asm__ ( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (lz) + : "r" (x)); - return 31 - lz; -} -#elif defined(CONFIG_CPU_MIPS64_R1) -/* - * Return the bit position (0..63) of the most significant 1 bit in a word - * Returns -1 if no 1 bit exists - */ -static __inline__ int __ilog2(unsigned long x) -{ - int lz; + return 31 - lz; + } + + BUG_ON(sizeof(x) != 8); __asm__ ( " .set push \n" @@ -584,7 +579,6 @@ static __inline__ int __ilog2(unsigned long x) return 63 - lz; } -#endif /* * __ffs - find first bit in word. @@ -595,7 +589,7 @@ static __inline__ int __ilog2(unsigned long x) */ static inline unsigned long __ffs(unsigned long word) { -#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1) +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) return __ilog2(word & -word); #else int b = 0, s; @@ -606,6 +600,8 @@ static inline unsigned long __ffs(unsigned long word) s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s; s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s; s = 1; if (word << 31 != 0) s = 0; b += s; + + return b; #endif #ifdef CONFIG_64BIT s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s; @@ -614,9 +610,10 @@ static inline unsigned long __ffs(unsigned long word) s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s; s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s; s = 1; if (word << 63 != 0) s = 0; b += s; -#endif + return b; #endif +#endif } /* @@ -655,10 +652,10 @@ static inline unsigned long ffz(unsigned long word) */ static inline unsigned long flz(unsigned long word) { -#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1) +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) return __ilog2(~word); #else -#if defined(CONFIG_32BIT) +#ifdef CONFIG_32BIT int r = 31, s; word = ~word; s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s; @@ -666,8 +663,10 @@ static inline unsigned long flz(unsigned long word) s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s; s = 2; if ((word & 0xc0000000)) s = 0; r -= s; word <<= s; s = 1; if ((word & 0x80000000)) s = 0; r -= s; + + return r; #endif -#if defined(CONFIG_64BIT) +#ifdef CONFIG_64BIT int r = 63, s; word = ~word; s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s; @@ -676,9 +675,10 @@ static inline unsigned long flz(unsigned long word) s = 4; if ((word & 0xf000000000000000UL)) s = 0; r -= s; word <<= s; s = 2; if ((word & 0xc000000000000000UL)) s = 0; r -= s; word <<= s; s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s; -#endif + return r; #endif +#endif } /* diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 5250231e936e..7517189e469f 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -232,7 +232,7 @@ __asm__( #endif -#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2) +#ifdef CONFIG_CPU_MIPSR2 #define instruction_hazard() \ do { \ __label__ __next; \ diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h index 0ba99f019be9..a5735761f5e5 100644 --- a/include/asm-mips/interrupt.h +++ b/include/asm-mips/interrupt.h @@ -19,7 +19,7 @@ __asm__ ( " .set push \n" " .set reorder \n" " .set noat \n" -#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2) +#ifdef CONFIG_CPU_MIPSR2 " ei \n" #else " mfc0 $1,$12 \n" @@ -51,7 +51,7 @@ __asm__ ( " .macro local_irq_disable\n" " .set push \n" " .set noat \n" -#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2) +#ifdef CONFIG_CPU_MIPSR2 " di \n" #else " mfc0 $1,$12 \n" @@ -91,7 +91,7 @@ __asm__ ( " .set push \n" " .set reorder \n" " .set noat \n" -#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2) +#ifdef CONFIG_CPU_MIPSR2 " di \\result \n" #else " mfc0 \\result, $12 \n" @@ -115,8 +115,7 @@ __asm__ ( " .macro local_irq_restore flags \n" " .set noreorder \n" " .set noat \n" -#if (defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)) && \ - defined(CONFIG_IRQ_CPU) +#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) /* * Slow, but doesn't suffer from a relativly unlikely race * condition we're having since days 1. @@ -125,7 +124,7 @@ __asm__ ( " di \n" " ei \n" "1: \n" -#elif defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2) +#elif defined(CONFIG_CPU_MIPSR2) /* * Fast, dangerous. Life is fun, life is good. */ diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h index 5c5edbf93707..9f92aed17754 100644 --- a/include/asm-mips/mach-mips/cpu-feature-overrides.h +++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h @@ -14,7 +14,7 @@ /* * CPU feature overrides for MIPS boards */ -#ifdef CONFIG_CPU_MIPS32_R1 +#ifdef CONFIG_CPU_MIPS32 #define cpu_has_tlb 1 #define cpu_has_4kex 1 #define cpu_has_4kcache 1 @@ -40,7 +40,7 @@ #define cpu_icache_snoops_remote_store 1 #endif -#ifdef CONFIG_CPU_MIPS64_R1 +#ifdef CONFIG_CPU_MIPS64 #define cpu_has_tlb 1 #define cpu_has_4kex 1 #define cpu_has_4kcache 1 diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 0076a537cf0c..ee25a779bf49 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -76,7 +76,7 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, * These are used to make use of C type-checking.. */ #ifdef CONFIG_64BIT_PHYS_ADDR - #ifdef CONFIG_CPU_MIPS32_R1 + #ifdef CONFIG_CPU_MIPS32 typedef struct { unsigned long pte_low, pte_high; } pte_t; #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) #else -- cgit v1.2.3