From bc818247203a7bfc40296a3f5b760de84fb8e0d1 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 17 Apr 2006 21:19:12 +0900 Subject: [MIPS] Fix bitops for MIPS32/MIPS64 CPUs. With recent rewrite for generic bitops, fls() for 32bit kernel with MIPS64_CPU is broken. Also, ffs(), fls() should be defined the same way as the libc and compiler built-in routines (returns int instead of unsigned long). Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 56 ++++++++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 32 deletions(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index a1728f8c0705..d2f444537e4b 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -467,64 +467,56 @@ static inline unsigned long __ffs(unsigned long word) } /* - * ffs - find first bit set. + * fls - find last bit set. * @word: The word to search * - * Returns 1..SZLONG - * Returns 0 if no bit exists + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. */ - -static inline unsigned long ffs(unsigned long word) +static inline int fls(int word) { - if (!word) - return 0; + __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); - return __ffs(word) + 1; + return 32 - word; } -/* - * ffz - find first zero in word. - * @word: The word to search - * - * Undefined if no zero exists, so code should check against ~0UL first. - */ -static inline unsigned long ffz(unsigned long word) +#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) +static inline int fls64(__u64 word) { - return __ffs (~word); + __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); + + return 64 - word; } +#else +#include +#endif /* - * fls - find last bit set. + * ffs - find first bit set. * @word: The word to search * - * Returns 1..SZLONG - * Returns 0 if no bit exists + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). */ -static inline unsigned long fls(unsigned long word) +static inline int ffs(int word) { -#ifdef CONFIG_CPU_MIPS32 - __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); - - return 32 - word; -#endif - -#ifdef CONFIG_CPU_MIPS64 - __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); + if (!word) + return 0; - return 64 - word; -#endif + return fls(word & -word); } #else #include #include -#include #include +#include #endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */ -#include +#include #include #ifdef __KERNEL__ -- cgit v1.2.3 From 7a8341969fe0df4a1fffa141435e742456270ffd Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Sat, 15 Apr 2006 00:31:16 +0100 Subject: [MIPS] 24K LV: Add core card id. Signed-off-by: Ralf Baechle --- arch/mips/mips-boards/generic/init.c | 1 + arch/mips/mips-boards/generic/pci.c | 1 + arch/mips/mips-boards/malta/malta_int.c | 3 +++ include/asm-mips/mips-boards/generic.h | 1 + 4 files changed, 6 insertions(+) (limited to 'include/asm-mips') diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 17dfe6a8cab9..df4e94735604 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -337,6 +337,7 @@ void __init prom_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c index 1f6f9df74ab2..9337f6c8873a 100644 --- a/arch/mips/mips-boards/generic/pci.c +++ b/arch/mips/mips-boards/generic/pci.c @@ -198,6 +198,7 @@ void __init mips_pcibios_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: /* Set up resource ranges from the controller's registers. */ MSC_READ(MSC01_PCI_SC2PMBASL, start); diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index 64db07d4dbe5..7cc0ba4f553a 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c @@ -57,6 +57,7 @@ static inline int mips_pcibios_iack(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: MSC_READ(MSC01_PCI_IACK, irq); irq &= 0xff; @@ -143,6 +144,7 @@ void corehi_irqdispatch(struct pt_regs *regs) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: ll_msc_irq(regs); break; @@ -309,6 +311,7 @@ void __init arch_init_irq(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: if (cpu_has_veic) init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index 25b6ffc26623..fa8b913cc3e0 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -67,6 +67,7 @@ #define MIPS_REVISION_CORID_CORE_FPGA2 7 #define MIPS_REVISION_CORID_CORE_FPGAR2 8 #define MIPS_REVISION_CORID_CORE_FPGA3 9 +#define MIPS_REVISION_CORID_CORE_24K 10 /**** Artificial corid defines ****/ /* -- cgit v1.2.3