From 8cc9b35f9afa15b9aa45c7fc35ddcd958d3207cb Mon Sep 17 00:00:00 2001 From: Deepak Katragadda Date: Tue, 10 May 2016 16:29:54 -0700 Subject: clk: msm: clock-gcc-cobalt: Add reset capability to PCIE pipe clock Instead of having a separate reset clock for PCIE 0 reset, tag the BCR register with the gcc_pcie_0_pipe_clk directly. CRs-Fixed: 1014989 Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533 Signed-off-by: Deepak Katragadda --- include/dt-bindings/clock/msm-clocks-cobalt.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h index 99df0d53c312..607bcfb9b506 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-cobalt.h @@ -256,7 +256,6 @@ #define clk_gcc_pcie_clkref_clk 0xa2e247fa #define clk_gcc_rx2_qlink_clkref_clk 0xd0ba986d #define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 -#define clk_gcc_pcie_0_phy_reset 0xdc3201c1 #define clk_gcc_pcie_phy_reset 0x9bc3c959 #define clk_gcc_pcie_phy_com_reset 0x8bf513e6 #define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da -- cgit v1.2.3