From 7a10174eeafe737f3ccfcece5bdff749c3b044e0 Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Mon, 28 Apr 2008 17:30:37 +1000 Subject: [POWERPC] Define and use TLF_RESTORE_SIGMASK Replace TIF_RESTORE_SIGMASK with TLF_RESTORE_SIGMASK and define our own set_restore_sigmask() function. This saves the costly SMP-safe set_bit operation, which we do not need for the sigmask flag since TIF_SIGPENDING always has to be set too. Signed-off-by: Roland McGrath Signed-off-by: Paul Mackerras --- include/asm-powerpc/thread_info.h | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h index d030f5ce39ad..e079e81051fd 100644 --- a/include/asm-powerpc/thread_info.h +++ b/include/asm-powerpc/thread_info.h @@ -116,7 +116,6 @@ static inline struct thread_info *current_thread_info(void) #define TIF_SECCOMP 10 /* secure computing */ #define TIF_RESTOREALL 11 /* Restore all regs (implies NOERROR) */ #define TIF_NOERROR 12 /* Force successful syscall return */ -#define TIF_RESTORE_SIGMASK 13 /* Restore signal mask in do_signal */ #define TIF_FREEZE 14 /* Freezing for suspend */ #define TIF_RUNLATCH 15 /* Is the runlatch enabled? */ #define TIF_ABI_PENDING 16 /* 32/64 bit switch needed */ @@ -134,21 +133,31 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SECCOMP (1<local_flags |= _TLF_RESTORE_SIGMASK; + set_bit(TIF_SIGPENDING, &ti->flags); +} +#endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */ -- cgit v1.2.3 From 663276b7c6340e755ed62bed67a2b96f4fc3d513 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 30 Apr 2008 20:44:53 +1000 Subject: [POWERPC] Set lower flag bits in regs->trap to indicate debug level exception We use the low bits of regs->trap as flag bits. We already indicate critical and machine check level exceptions via this mechanism. Extend it to indicate debug level exceptions. Signed-off-by: Kumar Gala Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/head_booke.h | 2 +- include/asm-powerpc/ptrace.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index aefafc6330c9..721faef87095 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -272,7 +272,7 @@ label: /* continue normal handling for a critical exception... */ \ 2: mfspr r4,SPRN_DBSR; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc) + EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc) #define DEBUG_CRIT_EXCEPTION \ START_EXCEPTION(DebugCrit); \ diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h index 39023dde1cc4..38d87e5e569d 100644 --- a/include/asm-powerpc/ptrace.h +++ b/include/asm-powerpc/ptrace.h @@ -119,6 +119,7 @@ extern int ptrace_put_reg(struct task_struct *task, int regno, #ifndef __powerpc64__ #define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0) #define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0) +#define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0) #endif /* ! __powerpc64__ */ #define TRAP(regs) ((regs)->trap & ~0xF) #ifdef __powerpc64__ -- cgit v1.2.3 From 5f25f06529ecb4b20efc7ba00de599f5b9f4b63c Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Thu, 8 May 2008 14:27:07 +1000 Subject: [POWERPC] Move declaration of init_bootmem_done into system.h ... instead of having an extern declaration in a .c file. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras --- arch/powerpc/mm/init_32.c | 3 +-- include/asm-powerpc/system.h | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c index 1952b4d3fa7f..45418590b6a9 100644 --- a/arch/powerpc/mm/init_32.c +++ b/arch/powerpc/mm/init_32.c @@ -43,6 +43,7 @@ #include #include #include +#include #include "mmu_decl.h" @@ -76,8 +77,6 @@ void MMU_init(void); /* XXX should be in current.h -- paulus */ extern struct task_struct *current_set[NR_CPUS]; -extern int init_bootmem_done; - /* * this tells the system to map all of ram with the segregs * (i.e. page tables) instead of the bats. diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 2b6559a6d113..df781adac6dd 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -190,6 +190,7 @@ extern struct task_struct *_switch(struct thread_struct *prev, extern unsigned int rtas_data; extern int mem_init_done; /* set on boot once kmalloc can be called */ +extern int init_bootmem_done; /* set on !NUMA once bootmem is available */ extern unsigned long memory_limit; extern unsigned long klimit; -- cgit v1.2.3 From 572fb578de59efaaa8d197b0183db43b1128a06e Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Thu, 8 May 2008 14:27:08 +1000 Subject: [POWERPC] Move declaration of tce variables into mmu-hash64.h ... instead of having extern declarations in a .c file. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras --- arch/powerpc/mm/hash_utils_64.c | 2 -- include/asm-powerpc/mmu-hash64.h | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 1a4b4b36b0c6..05f955f8df35 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -509,8 +509,6 @@ void __init htab_initialize(void) unsigned long base = 0, size = 0, limit; int i; - extern unsigned long tce_alloc_start, tce_alloc_end; - DBG(" -> htab_initialize()\n"); /* Initialize segment sizes */ diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h index 0dff76776044..f35d1e164da8 100644 --- a/include/asm-powerpc/mmu-hash64.h +++ b/include/asm-powerpc/mmu-hash64.h @@ -181,6 +181,7 @@ extern int mmu_io_psize; extern int mmu_kernel_ssize; extern int mmu_highuser_ssize; extern u16 mmu_slb_size; +extern unsigned long tce_alloc_start, tce_alloc_end; /* * If the processor supports 64k normal pages but not 64k cache -- cgit v1.2.3 From 7d9e793463d854073f5c0dedea991a5b63336d6a Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Thu, 8 May 2008 14:27:13 +1000 Subject: [POWERPC] Add a declaration for xmon() Usually we call xmon() via debugger(), so this could be static. Sometimes when debugging it's nice to be able to call xmon() directly though, so add a declaration. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras --- include/asm-powerpc/xmon.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h index 88320a05f0a8..81477f24a188 100644 --- a/include/asm-powerpc/xmon.h +++ b/include/asm-powerpc/xmon.h @@ -15,6 +15,8 @@ #ifdef CONFIG_XMON extern void xmon_setup(void); extern void xmon_register_spus(struct list_head *list); +struct pt_regs; +extern int xmon(struct pt_regs *excp); #else static inline void xmon_setup(void) { }; static inline void xmon_register_spus(struct list_head *list) { }; -- cgit v1.2.3 From af3b74df1b2fa4dbfb0534818167f6393f5ae7c7 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Thu, 8 May 2008 14:27:15 +1000 Subject: [POWERPC] Move xmon_irq() declaration into xmon.h The typdef for irqreturn_t was moved into its own header a while back, so there's no reason we can't move xmon_irq() into xmon.h now. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras --- arch/powerpc/platforms/chrp/setup.c | 7 ------- arch/powerpc/platforms/powermac/pic.c | 8 +------- include/asm-powerpc/xmon.h | 3 +++ 3 files changed, 4 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c index 116babbaaf81..1ba7ce5aafae 100644 --- a/arch/powerpc/platforms/chrp/setup.c +++ b/arch/powerpc/platforms/chrp/setup.c @@ -63,13 +63,6 @@ static struct mpic *chrp_mpic; DEFINE_PER_CPU(struct timer_list, heartbeat_timer); unsigned long event_scan_interval; -/* - * XXX this should be in xmon.h, but putting it there means xmon.h - * has to include (to get irqreturn_t), which - * causes all sorts of problems. -- paulus - */ -extern irqreturn_t xmon_irq(int, void *); - extern unsigned long loops_per_jiffy; /* To be replaced by RTAS when available */ diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c index 829b8b02527b..6d149ae8ffa7 100644 --- a/arch/powerpc/platforms/powermac/pic.c +++ b/arch/powerpc/platforms/powermac/pic.c @@ -34,16 +34,10 @@ #include #include #include +#include #include "pmac.h" -/* - * XXX this should be in xmon.h, but putting it there means xmon.h - * has to include (to get irqreturn_t), which - * causes all sorts of problems. -- paulus - */ -extern irqreturn_t xmon_irq(int, void *); - #ifdef CONFIG_PPC32 struct pmac_irq_hw { unsigned int event; diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h index 81477f24a188..d83da3cbd085 100644 --- a/include/asm-powerpc/xmon.h +++ b/include/asm-powerpc/xmon.h @@ -12,11 +12,14 @@ #ifdef __KERNEL__ +#include + #ifdef CONFIG_XMON extern void xmon_setup(void); extern void xmon_register_spus(struct list_head *list); struct pt_regs; extern int xmon(struct pt_regs *excp); +extern irqreturn_t xmon_irq(int, void *); #else static inline void xmon_setup(void) { }; static inline void xmon_register_spus(struct list_head *list) { }; -- cgit v1.2.3 From 1c8950ff87de950a3b6ccfb26650fc0a56278836 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Thu, 8 May 2008 14:27:17 +1000 Subject: [POWERPC] Make cpus_in_xmon static and remove extern mess from hvc_console.c This is a little messier than I'd like because xmon.h only exists on powerpc and we can't have a static inline and an extern declaration visible at the same time. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras --- arch/powerpc/xmon/xmon.c | 7 ++++++- drivers/char/hvc_console.c | 8 +------- drivers/char/hvc_console.h | 10 ++++++++++ include/asm-powerpc/xmon.h | 4 ++++ 4 files changed, 21 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 95f24c9822b1..6726da07c065 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -54,7 +54,7 @@ #define skipbl xmon_skipbl #ifdef CONFIG_SMP -cpumask_t cpus_in_xmon = CPU_MASK_NONE; +static cpumask_t cpus_in_xmon = CPU_MASK_NONE; static unsigned long xmon_taken = 1; static int xmon_owner; static int xmon_gate; @@ -327,6 +327,11 @@ static void release_output_lock(void) { xmon_speaker = 0; } + +int cpus_are_in_xmon(void) +{ + return !cpus_empty(cpus_in_xmon); +} #endif static int xmon_core(struct pt_regs *regs, int fromipi) diff --git a/drivers/char/hvc_console.c b/drivers/char/hvc_console.c index 44160d5ebca0..2f9759d625cc 100644 --- a/drivers/char/hvc_console.c +++ b/drivers/char/hvc_console.c @@ -675,12 +675,6 @@ static int hvc_poll(struct hvc_struct *hp) return poll_mask; } -#if defined(CONFIG_XMON) && defined(CONFIG_SMP) -extern cpumask_t cpus_in_xmon; -#else -static const cpumask_t cpus_in_xmon = CPU_MASK_NONE; -#endif - /* * This kthread is either polling or interrupt driven. This is determined by * calling hvc_poll() who determines whether a console adapter support @@ -698,7 +692,7 @@ static int khvcd(void *unused) hvc_kicked = 0; try_to_freeze(); wmb(); - if (cpus_empty(cpus_in_xmon)) { + if (!cpus_are_in_xmon()) { spin_lock(&hvc_structs_lock); list_for_each_entry(hp, &hvc_structs, next) { poll_mask |= hvc_poll(hp); diff --git a/drivers/char/hvc_console.h b/drivers/char/hvc_console.h index 8c59818050e6..42ffb17e15df 100644 --- a/drivers/char/hvc_console.h +++ b/drivers/char/hvc_console.h @@ -60,4 +60,14 @@ extern struct hvc_struct * __devinit hvc_alloc(uint32_t vtermno, int irq, /* remove a vterm from hvc tty operation (modele_exit or hotplug remove) */ extern int __devexit hvc_remove(struct hvc_struct *hp); + +#if defined(CONFIG_XMON) && defined(CONFIG_SMP) +#include +#else +static inline int cpus_are_in_xmon(void) +{ + return 0; +} +#endif + #endif // HVC_CONSOLE_H diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h index d83da3cbd085..5eb8e599e5cc 100644 --- a/include/asm-powerpc/xmon.h +++ b/include/asm-powerpc/xmon.h @@ -25,5 +25,9 @@ static inline void xmon_setup(void) { }; static inline void xmon_register_spus(struct list_head *list) { }; #endif +#if defined(CONFIG_XMON) && defined(CONFIG_SMP) +extern int cpus_are_in_xmon(void); +#endif + #endif /* __KERNEL __ */ #endif /* __ASM_POWERPC_XMON_H */ -- cgit v1.2.3 From 1c21a2937b1f342a8f5d580203c3396557d53b6e Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Thu, 8 May 2008 14:27:19 +1000 Subject: [POWERPC] Fix sparse warnings in arch/powerpc/kernel Make a few things static in lparcfg.c Make init and exit routines static in rtas_flash.c Make things static in rtas_pci.c Make some functions static in rtas.c Make fops static in rtas-proc.c Remove unneeded extern for do_gtod in smp.c Make clocksource_init() static in time.c Make last_tick_len and ticklen_to_xs static in time.c Move the declaration of the pvr per-cpu into smp.h Make kexec_smp_down() and kexec_stack static in machine_kexec_64.c Don't return void in arch_teardown_msi_irqs() in msi.c Move declaration of GregorianDay()into asm/time.h Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/lparcfg.c | 6 +++--- arch/powerpc/kernel/machine_kexec_64.c | 4 ++-- arch/powerpc/kernel/msi.c | 2 +- arch/powerpc/kernel/rtas-proc.c | 14 +++++++------- arch/powerpc/kernel/rtas.c | 6 +++--- arch/powerpc/kernel/rtas_flash.c | 4 ++-- arch/powerpc/kernel/rtas_pci.c | 4 ++-- arch/powerpc/kernel/smp.c | 4 ---- arch/powerpc/kernel/time.c | 10 +++++----- arch/powerpc/platforms/maple/time.c | 2 -- include/asm-powerpc/smp.h | 2 ++ include/asm-powerpc/time.h | 1 + 12 files changed, 28 insertions(+), 31 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c index 1e656b43ad7f..827a5726a035 100644 --- a/arch/powerpc/kernel/lparcfg.c +++ b/arch/powerpc/kernel/lparcfg.c @@ -573,7 +573,7 @@ static int lparcfg_open(struct inode *inode, struct file *file) return single_open(file, lparcfg_data, NULL); } -const struct file_operations lparcfg_fops = { +static const struct file_operations lparcfg_fops = { .owner = THIS_MODULE, .read = seq_read, .write = lparcfg_write, @@ -581,7 +581,7 @@ const struct file_operations lparcfg_fops = { .release = single_release, }; -int __init lparcfg_init(void) +static int __init lparcfg_init(void) { struct proc_dir_entry *ent; mode_t mode = S_IRUSR | S_IRGRP | S_IROTH; @@ -601,7 +601,7 @@ int __init lparcfg_init(void) return 0; } -void __exit lparcfg_cleanup(void) +static void __exit lparcfg_cleanup(void) { if (proc_ppc64_lparcfg) remove_proc_entry("lparcfg", proc_ppc64_lparcfg->parent); diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c index 704375bda73a..631dfd614b21 100644 --- a/arch/powerpc/kernel/machine_kexec_64.c +++ b/arch/powerpc/kernel/machine_kexec_64.c @@ -158,7 +158,7 @@ void kexec_copy_flush(struct kimage *image) * on calling the interrupts, but we would like to call it off irq level * so that the interrupt controller is clean. */ -void kexec_smp_down(void *arg) +static void kexec_smp_down(void *arg) { if (ppc_md.kexec_cpu_down) ppc_md.kexec_cpu_down(0, 1); @@ -249,7 +249,7 @@ static void kexec_prepare_cpus(void) * We could use a smaller stack if we don't care about anything using * current, but that audit has not been performed. */ -union thread_union kexec_stack +static union thread_union kexec_stack __attribute__((__section__(".data.init_task"))) = { }; /* Our assembly helper, in kexec_stub.S */ diff --git a/arch/powerpc/kernel/msi.c b/arch/powerpc/kernel/msi.c index c62d1012c013..3bb7d3dd28be 100644 --- a/arch/powerpc/kernel/msi.c +++ b/arch/powerpc/kernel/msi.c @@ -34,5 +34,5 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) void arch_teardown_msi_irqs(struct pci_dev *dev) { - return ppc_md.teardown_msi_irqs(dev); + ppc_md.teardown_msi_irqs(dev); } diff --git a/arch/powerpc/kernel/rtas-proc.c b/arch/powerpc/kernel/rtas-proc.c index f9c6abc84a94..1be9fe38bcb5 100644 --- a/arch/powerpc/kernel/rtas-proc.c +++ b/arch/powerpc/kernel/rtas-proc.c @@ -160,7 +160,7 @@ static int sensors_open(struct inode *inode, struct file *file) return single_open(file, ppc_rtas_sensors_show, NULL); } -const struct file_operations ppc_rtas_sensors_operations = { +static const struct file_operations ppc_rtas_sensors_operations = { .open = sensors_open, .read = seq_read, .llseek = seq_lseek, @@ -172,7 +172,7 @@ static int poweron_open(struct inode *inode, struct file *file) return single_open(file, ppc_rtas_poweron_show, NULL); } -const struct file_operations ppc_rtas_poweron_operations = { +static const struct file_operations ppc_rtas_poweron_operations = { .open = poweron_open, .read = seq_read, .llseek = seq_lseek, @@ -185,7 +185,7 @@ static int progress_open(struct inode *inode, struct file *file) return single_open(file, ppc_rtas_progress_show, NULL); } -const struct file_operations ppc_rtas_progress_operations = { +static const struct file_operations ppc_rtas_progress_operations = { .open = progress_open, .read = seq_read, .llseek = seq_lseek, @@ -198,7 +198,7 @@ static int clock_open(struct inode *inode, struct file *file) return single_open(file, ppc_rtas_clock_show, NULL); } -const struct file_operations ppc_rtas_clock_operations = { +static const struct file_operations ppc_rtas_clock_operations = { .open = clock_open, .read = seq_read, .llseek = seq_lseek, @@ -211,7 +211,7 @@ static int tone_freq_open(struct inode *inode, struct file *file) return single_open(file, ppc_rtas_tone_freq_show, NULL); } -const struct file_operations ppc_rtas_tone_freq_operations = { +static const struct file_operations ppc_rtas_tone_freq_operations = { .open = tone_freq_open, .read = seq_read, .llseek = seq_lseek, @@ -224,7 +224,7 @@ static int tone_volume_open(struct inode *inode, struct file *file) return single_open(file, ppc_rtas_tone_volume_show, NULL); } -const struct file_operations ppc_rtas_tone_volume_operations = { +static const struct file_operations ppc_rtas_tone_volume_operations = { .open = tone_volume_open, .read = seq_read, .llseek = seq_lseek, @@ -237,7 +237,7 @@ static int rmo_buf_open(struct inode *inode, struct file *file) return single_open(file, ppc_rtas_rmo_buf_show, NULL); } -const struct file_operations ppc_rtas_rmo_buf_ops = { +static const struct file_operations ppc_rtas_rmo_buf_ops = { .open = rmo_buf_open, .read = seq_read, .llseek = seq_lseek, diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index 34843c318419..2a60bd3e3afa 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -340,8 +340,8 @@ int rtas_get_error_log_max(void) EXPORT_SYMBOL(rtas_get_error_log_max); -char rtas_err_buf[RTAS_ERROR_LOG_MAX]; -int rtas_last_error_token; +static char rtas_err_buf[RTAS_ERROR_LOG_MAX]; +static int rtas_last_error_token; /** Return a copy of the detailed error text associated with the * most recent failed call to rtas. Because the error text @@ -484,7 +484,7 @@ unsigned int rtas_busy_delay(int status) } EXPORT_SYMBOL(rtas_busy_delay); -int rtas_error_rc(int rtas_rc) +static int rtas_error_rc(int rtas_rc) { int rc; diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c index 0a5e22b22729..09ded5c424a9 100644 --- a/arch/powerpc/kernel/rtas_flash.c +++ b/arch/powerpc/kernel/rtas_flash.c @@ -731,7 +731,7 @@ static const struct file_operations validate_flash_operations = { .release = validate_flash_release, }; -int __init rtas_flash_init(void) +static int __init rtas_flash_init(void) { int rc; @@ -817,7 +817,7 @@ cleanup: return rc; } -void __exit rtas_flash_cleanup(void) +static void __exit rtas_flash_cleanup(void) { rtas_flash_term_hook = NULL; diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c index 3ab88a9dc70d..589a2797eac2 100644 --- a/arch/powerpc/kernel/rtas_pci.c +++ b/arch/powerpc/kernel/rtas_pci.c @@ -155,12 +155,12 @@ static int rtas_pci_write_config(struct pci_bus *bus, return PCIBIOS_DEVICE_NOT_FOUND; } -struct pci_ops rtas_pci_ops = { +static struct pci_ops rtas_pci_ops = { .read = rtas_pci_read_config, .write = rtas_pci_write_config, }; -int is_python(struct device_node *dev) +static int is_python(struct device_node *dev) { const char *model = of_get_property(dev, "model", NULL); diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 1457aa0a08f1..ba7989ffaeee 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -365,12 +365,8 @@ void smp_call_function_interrupt(void) } } -extern struct gettimeofday_struct do_gtod; - struct thread_info *current_set[NR_CPUS]; -DECLARE_PER_CPU(unsigned int, pvr); - static void __devinit smp_store_cpu_info(int id) { per_cpu(pvr, id) = mfspr(SPRN_PVR); diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 73401e83739a..c73fc33aa817 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -129,7 +129,7 @@ static unsigned long __initdata iSeries_recal_titan; static signed long __initdata iSeries_recal_tb; /* Forward declaration is only needed for iSereis compiles */ -void __init clocksource_init(void); +static void __init clocksource_init(void); #endif #define XSEC_PER_SEC (1024*1024) @@ -150,8 +150,8 @@ u64 tb_to_xs; unsigned tb_to_us; #define TICKLEN_SCALE NTP_SCALE_SHIFT -u64 last_tick_len; /* units are ns / 2^TICKLEN_SCALE */ -u64 ticklen_to_xs; /* 0.64 fraction */ +static u64 last_tick_len; /* units are ns / 2^TICKLEN_SCALE */ +static u64 ticklen_to_xs; /* 0.64 fraction */ /* If last_tick_len corresponds to about 1/HZ seconds, then last_tick_len << TICKLEN_SHIFT will be about 2^63. */ @@ -164,7 +164,7 @@ static u64 tb_to_ns_scale __read_mostly; static unsigned tb_to_ns_shift __read_mostly; static unsigned long boot_tb __read_mostly; -struct gettimeofday_struct do_gtod; +static struct gettimeofday_struct do_gtod; extern struct timezone sys_tz; static long timezone_offset; @@ -832,7 +832,7 @@ void update_vsyscall_tz(void) ++vdso_data->tb_update_count; } -void __init clocksource_init(void) +static void __init clocksource_init(void) { struct clocksource *clock; diff --git a/arch/powerpc/platforms/maple/time.c b/arch/powerpc/platforms/maple/time.c index 9f7579b38c72..53bca132fb48 100644 --- a/arch/powerpc/platforms/maple/time.c +++ b/arch/powerpc/platforms/maple/time.c @@ -41,8 +41,6 @@ #define DBG(x...) #endif -extern void GregorianDay(struct rtc_time * tm); - static int maple_rtc_addr; static int maple_clock_read(int addr) diff --git a/include/asm-powerpc/smp.h b/include/asm-powerpc/smp.h index 505f35bacaa9..1cd43e3d94fb 100644 --- a/include/asm-powerpc/smp.h +++ b/include/asm-powerpc/smp.h @@ -37,6 +37,8 @@ extern void cpu_die(void); extern void smp_send_debugger_break(int cpu); extern void smp_message_recv(int); +DECLARE_PER_CPU(unsigned int, pvr); + #ifdef CONFIG_HOTPLUG_CPU extern void fixup_irqs(cpumask_t map); int generic_cpu_disable(void); diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h index ce5de6e0e690..febd581ec9b0 100644 --- a/include/asm-powerpc/time.h +++ b/include/asm-powerpc/time.h @@ -33,6 +33,7 @@ extern unsigned tb_to_us; struct rtc_time; extern void to_tm(int tim, struct rtc_time * tm); +extern void GregorianDay(struct rtc_time *tm); extern time_t last_rtc_update; extern void generic_calibrate_decr(void); -- cgit v1.2.3 From a560643e21e1ac10f7398b45111aecdd7f47a4a5 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 14 May 2008 14:30:48 +1000 Subject: [POWERPC] Defer processing of interrupts when the CPU wakes from sleep mode This provides a way to defer processing of an interrupt that wakes the processor out of sleep mode. On 32-bit platforms that use an interrupt to wake the processor, we have to have interrupts enabled in hardware at the point where we go to sleep, otherwise the processor will never wake up. However, because interrupts are logically disabled at this point, we don't want to process the interrupt straight away. This is handled by setting the _TLF_SLEEPING flag. When we get an interrupt and _TLF_SLEEPING is set, we firstly clear the MSR_EE (external interrupt enable) bit in the saved MSR value, and secondly we then return to the address in the link register, like we do for _TLF_NAPPING, but without actually handling the interrupt. Note that this is handled somewhat differently on powerbooks, so this new code will only be used on non-Apple machines. Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/entry_32.S | 8 ++++++++ include/asm-powerpc/thread_info.h | 4 +++- 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 3a05e9f93d42..888a364043a8 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -147,6 +147,7 @@ transfer_to_handler: lwz r12,TI_LOCAL_FLAGS(r9) mtcrf 0x01,r12 bt- 31-TLF_NAPPING,4f + bt- 31-TLF_SLEEPING,7f #endif /* CONFIG_6xx */ .globl transfer_to_handler_cont transfer_to_handler_cont: @@ -164,6 +165,13 @@ transfer_to_handler_cont: 4: rlwinm r12,r12,0,~_TLF_NAPPING stw r12,TI_LOCAL_FLAGS(r9) b power_save_6xx_restore + +7: rlwinm r12,r12,0,~_TLF_SLEEPING + stw r12,TI_LOCAL_FLAGS(r9) + lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */ + rlwinm r9,r9,0,~MSR_EE + lwz r12,_LINK(r11) /* and return to address in LR */ + b fast_exception_return #endif /* diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h index e079e81051fd..b705c2a7651a 100644 --- a/include/asm-powerpc/thread_info.h +++ b/include/asm-powerpc/thread_info.h @@ -144,9 +144,11 @@ static inline struct thread_info *current_thread_info(void) /* Bits in local_flags */ /* Don't move TLF_NAPPING without adjusting the code in entry_32.S */ #define TLF_NAPPING 0 /* idle thread enabled NAP mode */ -#define TLF_RESTORE_SIGMASK 1 /* Restore signal mask in do_signal */ +#define TLF_SLEEPING 1 /* suspend code enabled SLEEP mode */ +#define TLF_RESTORE_SIGMASK 2 /* Restore signal mask in do_signal */ #define _TLF_NAPPING (1 << TLF_NAPPING) +#define _TLF_SLEEPING (1 << TLF_SLEEPING) #define _TLF_RESTORE_SIGMASK (1 << TLF_RESTORE_SIGMASK) #ifndef __ASSEMBLY__ -- cgit v1.2.3 From 0b2cca804ee40495bc92449c3e22f3c3a3f2977a Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 29 Apr 2008 01:38:13 +1000 Subject: [POWERPC] Add 6xx-style HID0_SLEEP support. This adds a function to put a 6xx/7xx/7xxx/83xx family CPU into sleep mode, and return after an interrupt has occurred. It expects to be called with interrupts disabled, and returns with interrupts disabled. Interrupts are enabled while the processor is asleep, but the interrupt that wakes the processor is not handled; it is still pending when this function returns. Signed-off-by: Scott Wood Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mackerras --- arch/powerpc/sysdev/6xx-suspend.S | 52 +++++++++++++++++++++++++++++++++++++++ arch/powerpc/sysdev/Makefile | 4 +++ include/asm-powerpc/mpc6xx.h | 6 +++++ 3 files changed, 62 insertions(+) create mode 100644 arch/powerpc/sysdev/6xx-suspend.S create mode 100644 include/asm-powerpc/mpc6xx.h (limited to 'include') diff --git a/arch/powerpc/sysdev/6xx-suspend.S b/arch/powerpc/sysdev/6xx-suspend.S new file mode 100644 index 000000000000..21cda085d926 --- /dev/null +++ b/arch/powerpc/sysdev/6xx-suspend.S @@ -0,0 +1,52 @@ +/* + * Enter and leave sleep state on chips with 6xx-style HID0 + * power management bits, which don't leave sleep state via reset. + * + * Author: Scott Wood + * + * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +_GLOBAL(mpc6xx_enter_standby) + mflr r4 + + mfspr r5, SPRN_HID0 + rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP) + oris r5, r5, HID0_SLEEP@h + mtspr SPRN_HID0, r5 + isync + + lis r5, ret_from_standby@h + ori r5, r5, ret_from_standby@l + mtlr r5 + + rlwinm r5, r1, 0, 0, 31-THREAD_SHIFT + lwz r6, TI_LOCAL_FLAGS(r5) + ori r6, r6, _TLF_SLEEPING + stw r6, TI_LOCAL_FLAGS(r5) + + mfmsr r5 + ori r5, r5, MSR_EE + oris r5, r5, MSR_POW@h + sync + mtmsr r5 + isync + +1: b 1b + +ret_from_standby: + mfspr r5, SPRN_HID0 + rlwinm r5, r5, 0, ~HID0_SLEEP + mtspr SPRN_HID0, r5 + + mtlr r4 + blr diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index 6d386d0071a0..2cc50520a698 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -44,3 +44,7 @@ obj-$(CONFIG_PPC_DCR) += dcr.o obj-$(CONFIG_8xx) += mpc8xx_pic.o cpm1.o obj-$(CONFIG_UCODE_PATCH) += micropatch.o endif + +ifeq ($(CONFIG_SUSPEND),y) +obj-$(CONFIG_6xx) += 6xx-suspend.o +endif diff --git a/include/asm-powerpc/mpc6xx.h b/include/asm-powerpc/mpc6xx.h new file mode 100644 index 000000000000..effc2291beb2 --- /dev/null +++ b/include/asm-powerpc/mpc6xx.h @@ -0,0 +1,6 @@ +#ifndef __ASM_POWERPC_MPC6xx_H +#define __ASM_POWERPC_MPC6xx_H + +void mpc6xx_enter_standby(void); + +#endif -- cgit v1.2.3 From 7bc228b1ef71f395aeb89bdf81bf95556b08b374 Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Thu, 15 May 2008 05:16:44 +1000 Subject: [POWERPC] Get most of ioctl.h content from Now that allows overriding of the most commonly changed macros, take advantage of that. Signed-off-by: Robert P. J. Day Signed-off-by: Paul Mackerras --- include/asm-powerpc/ioctl.h | 58 +-------------------------------------------- 1 file changed, 1 insertion(+), 57 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/ioctl.h b/include/asm-powerpc/ioctl.h index 8eb99848c402..57d68304218b 100644 --- a/include/asm-powerpc/ioctl.h +++ b/include/asm-powerpc/ioctl.h @@ -1,69 +1,13 @@ #ifndef _ASM_POWERPC_IOCTL_H #define _ASM_POWERPC_IOCTL_H - -/* - * this was copied from the alpha as it's a bit cleaner there. - * -- Cort - */ - -#define _IOC_NRBITS 8 -#define _IOC_TYPEBITS 8 #define _IOC_SIZEBITS 13 #define _IOC_DIRBITS 3 -#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) -#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) -#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) -#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) - -#define _IOC_NRSHIFT 0 -#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) -#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) -#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) - -/* - * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. - * And this turns out useful to catch old ioctl numbers in header - * files for us. - */ #define _IOC_NONE 1U #define _IOC_READ 2U #define _IOC_WRITE 4U -#define _IOC(dir,type,nr,size) \ - (((dir) << _IOC_DIRSHIFT) | \ - ((type) << _IOC_TYPESHIFT) | \ - ((nr) << _IOC_NRSHIFT) | \ - ((size) << _IOC_SIZESHIFT)) - -/* provoke compile error for invalid uses of size argument */ -extern unsigned int __invalid_size_argument_for_IOC; -#define _IOC_TYPECHECK(t) \ - ((sizeof(t) == sizeof(t[1]) && \ - sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ - sizeof(t) : __invalid_size_argument_for_IOC) - -/* used to create numbers */ -#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) - -/* used to decode them.. */ -#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) -#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) -#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) -#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) - -/* various drivers, such as the pcmcia stuff, need these... */ -#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) -#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) -#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) -#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) -#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) +#include #endif /* _ASM_POWERPC_IOCTL_H */ -- cgit v1.2.3 From 09e67ca2c523544e6b38aa570a5f62a0cf20b87b Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Fri, 16 May 2008 11:57:45 +1000 Subject: [POWERPC] Move of_device_get_modalias to drivers/of Commit 140b932f8cb6cced10b96860651a198b1b89cbb9 ("Create modalias file in sysfs for of_platform bus") needs this to avoid breaking the sparc builds. Just move the code and add whitespace around some binary operators. Signed-off-by: Stephen Rothwell Acked-by: David S. Miller Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/of_device.c | 48 ----------------------------------------- drivers/of/device.c | 48 +++++++++++++++++++++++++++++++++++++++++ include/asm-powerpc/of_device.h | 2 -- include/linux/of_device.h | 3 +++ 4 files changed, 51 insertions(+), 50 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/of_device.c b/arch/powerpc/kernel/of_device.c index 5748ddb47d9f..e9be908f199b 100644 --- a/arch/powerpc/kernel/of_device.c +++ b/arch/powerpc/kernel/of_device.c @@ -89,54 +89,6 @@ struct of_device *of_device_alloc(struct device_node *np, } EXPORT_SYMBOL(of_device_alloc); -ssize_t of_device_get_modalias(struct of_device *ofdev, - char *str, ssize_t len) -{ - const char *compat; - int cplen, i; - ssize_t tsize, csize, repend; - - /* Name & Type */ - csize = snprintf(str, len, "of:N%sT%s", - ofdev->node->name, ofdev->node->type); - - /* Get compatible property if any */ - compat = of_get_property(ofdev->node, "compatible", &cplen); - if (!compat) - return csize; - - /* Find true end (we tolerate multiple \0 at the end */ - for (i=(cplen-1); i>=0 && !compat[i]; i--) - cplen--; - if (!cplen) - return csize; - cplen++; - - /* Check space (need cplen+1 chars including final \0) */ - tsize = csize + cplen; - repend = tsize; - - if (csize>=len) /* @ the limit, all is already filled */ - return tsize; - - if (tsize>=len) { /* limit compat list */ - cplen = len-csize-1; - repend = len; - } - - /* Copy and do char replacement */ - memcpy(&str[csize+1], compat, cplen); - for (i=csize; idev); } EXPORT_SYMBOL(of_device_unregister); + +ssize_t of_device_get_modalias(struct of_device *ofdev, + char *str, ssize_t len) +{ + const char *compat; + int cplen, i; + ssize_t tsize, csize, repend; + + /* Name & Type */ + csize = snprintf(str, len, "of:N%sT%s", + ofdev->node->name, ofdev->node->type); + + /* Get compatible property if any */ + compat = of_get_property(ofdev->node, "compatible", &cplen); + if (!compat) + return csize; + + /* Find true end (we tolerate multiple \0 at the end */ + for (i = (cplen - 1); i >= 0 && !compat[i]; i--) + cplen--; + if (!cplen) + return csize; + cplen++; + + /* Check space (need cplen+1 chars including final \0) */ + tsize = csize + cplen; + repend = tsize; + + if (csize >= len) /* @ the limit, all is already filled */ + return tsize; + + if (tsize >= len) { /* limit compat list */ + cplen = len - csize - 1; + repend = len; + } + + /* Copy and do char replacement */ + memcpy(&str[csize + 1], compat, cplen); + for (i = csize; i < repend; i++) { + char c = str[i]; + if (c == '\0') + str[i] = 'C'; + else if (c == ' ') + str[i] = '_'; + } + + return tsize; +} diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h index 6526e139a463..3c123990ca2e 100644 --- a/include/asm-powerpc/of_device.h +++ b/include/asm-powerpc/of_device.h @@ -21,8 +21,6 @@ extern struct of_device *of_device_alloc(struct device_node *np, const char *bus_id, struct device *parent); -extern ssize_t of_device_get_modalias(struct of_device *ofdev, - char *str, ssize_t len); extern int of_device_uevent(struct device *dev, struct kobj_uevent_env *env); diff --git a/include/linux/of_device.h b/include/linux/of_device.h index afe338217d91..d3a74e00a3e1 100644 --- a/include/linux/of_device.h +++ b/include/linux/of_device.h @@ -24,4 +24,7 @@ static inline void of_device_free(struct of_device *dev) of_release_dev(&dev->dev); } +extern ssize_t of_device_get_modalias(struct of_device *ofdev, + char *str, ssize_t len); + #endif /* _LINUX_OF_DEVICE_H */ -- cgit v1.2.3 From 2ca7633dc73405ee775a2e9b7961b47a38bc882d Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Sun, 11 May 2008 10:40:47 +1000 Subject: [POWERPC] Tweak VDSO linker script to avoid upsetting old binutils This works around bugs in older binutils' objcopy. The placement of these sections does not really matter, but it confused the buggy old BFD libraries. Signed-off-by: Roland McGrath Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/vdso64/vdso64.lds.S | 6 +++--- include/asm-powerpc/ppc_asm.h | 6 ++++++ 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/vdso64/vdso64.lds.S b/arch/powerpc/kernel/vdso64/vdso64.lds.S index 932b3fdb34b9..7d6585f90277 100644 --- a/arch/powerpc/kernel/vdso64/vdso64.lds.S +++ b/arch/powerpc/kernel/vdso64/vdso64.lds.S @@ -43,15 +43,15 @@ SECTIONS .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } .rodata1 : { *(.rodata1) } + .dynamic : { *(.dynamic) } :text :dynamic + .eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr .eh_frame : { KEEP (*(.eh_frame)) } :text .gcc_except_table : { *(.gcc_except_table) } + .rela.dyn ALIGN(8) : { *(.rela.dyn) } .opd ALIGN(8) : { KEEP (*(.opd)) } .got ALIGN(8) : { *(.got .toc) } - .rela.dyn ALIGN(8) : { *(.rela.dyn) } - - .dynamic : { *(.dynamic) } :text :dynamic _end = .; PROVIDE(end = .); diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h index 2dbd4e7884fa..ef96bfd4ef4c 100644 --- a/include/asm-powerpc/ppc_asm.h +++ b/include/asm-powerpc/ppc_asm.h @@ -356,6 +356,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #define toreal(rd) #define fromreal(rd) +/* + * We use addis to ensure compatibility with the "classic" ppc versions of + * these macros, which use rs = 0 to get the tophys offset in rd, rather than + * converting the address in r0, and so this version has to do that too + * (i.e. set register rd to 0 when rs == 0). + */ #define tophys(rd,rs) \ addis rd,rs,0 -- cgit v1.2.3 From 475ca391b490a683d66bf19999a8a7a24913f139 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 22 May 2008 06:59:23 +1000 Subject: [POWERPC] mpic: Deal with bogus NIRQ in Feature Reporting Register Some chips (like the SoCs from Freescale) report the wrong value in NIRQ and this causes issues if its doesn't match or exceed the value of irq_count. Add a flag that board code can set to just use irq_count instead of FRR[NIRQ]. Eventually we'll add a device tree property with the number of sources. Signed-off-by: Kumar Gala Signed-off-by: Paul Mackerras --- arch/powerpc/sysdev/mpic.c | 9 ++++++--- include/asm-powerpc/mpic.h | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 8619f2a3f1f6..466e2183e86c 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -1144,9 +1144,12 @@ struct mpic * __init mpic_alloc(struct device_node *node, mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; if (isu_size == 0) - mpic->num_sources = - ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) - >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; + if (flags & MPIC_BROKEN_FRR_NIRQS) + mpic->num_sources = mpic->irq_count; + else + mpic->num_sources = + ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) + >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; /* Map the per-CPU registers */ for (i = 0; i < mpic->num_cpus; i++) { diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h index 943c5a3fac8a..6802570f4240 100644 --- a/include/asm-powerpc/mpic.h +++ b/include/asm-powerpc/mpic.h @@ -353,6 +353,8 @@ struct mpic #define MPIC_ENABLE_MCK 0x00000200 /* Disable bias among target selection, spread interrupts evenly */ #define MPIC_NO_BIAS 0x00000400 +/* Ignore NIRQS as reported by FRR */ +#define MPIC_BROKEN_FRR_NIRQS 0x00000800 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 -- cgit v1.2.3 From b786af117b360843349cf66165c4efa0217ca2a7 Mon Sep 17 00:00:00 2001 From: Stephen Neuendorffer Date: Wed, 7 May 2008 04:29:17 +1000 Subject: [POWERPC] Refactor DCR code Previously, DCR support was configured at compile time to either use MMIO or native dcr instructions. Although this works for most platforms, it fails on FPGA platforms: 1) Systems may include more than one DCR bus. 2) Systems may be native DCR capable and still use memory mapped DCR interface. This patch provides runtime support based on the device trees for the case where CONFIG_PPC_DCR_MMIO and CONFIG_PPC_DCR_NATIVE are both selected. Previously, this was a poorly defined configuration, which happened to provide NATIVE support. The runtime selection is made based on the dcr-controller having a 'dcr-access-method' attribute in the device tree. If only one of the above options is selected, then the code uses #defines to select only the used code in order to avoid introducing overhead in existing usage. Signed-off-by: Stephen Neuendorffer Signed-off-by: Josh Boyer --- arch/powerpc/sysdev/dcr.c | 154 ++++++++++++++++++++++++++++++-------- include/asm-powerpc/dcr-generic.h | 49 ++++++++++++ include/asm-powerpc/dcr-mmio.h | 20 +++-- include/asm-powerpc/dcr-native.h | 16 ++-- include/asm-powerpc/dcr.h | 39 +++++++++- 5 files changed, 231 insertions(+), 47 deletions(-) create mode 100644 include/asm-powerpc/dcr-generic.h (limited to 'include') diff --git a/arch/powerpc/sysdev/dcr.c b/arch/powerpc/sysdev/dcr.c index 437e48d3ae33..5f39a79b0660 100644 --- a/arch/powerpc/sysdev/dcr.c +++ b/arch/powerpc/sysdev/dcr.c @@ -23,6 +23,105 @@ #include #include +static struct device_node *find_dcr_parent(struct device_node *node) +{ + struct device_node *par, *tmp; + const u32 *p; + + for (par = of_node_get(node); par;) { + if (of_get_property(par, "dcr-controller", NULL)) + break; + p = of_get_property(par, "dcr-parent", NULL); + tmp = par; + if (p == NULL) + par = of_get_parent(par); + else + par = of_find_node_by_phandle(*p); + of_node_put(tmp); + } + return par; +} + +#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) + +bool dcr_map_ok_generic(dcr_host_t host) +{ + if (host.type == DCR_HOST_NATIVE) + return dcr_map_ok_native(host.host.native); + else if (host.type == DCR_HOST_MMIO) + return dcr_map_ok_mmio(host.host.mmio); + else + return 0; +} +EXPORT_SYMBOL_GPL(dcr_map_ok_generic); + +dcr_host_t dcr_map_generic(struct device_node *dev, + unsigned int dcr_n, + unsigned int dcr_c) +{ + dcr_host_t host; + struct device_node *dp; + const char *prop; + + host.type = DCR_HOST_INVALID; + + dp = find_dcr_parent(dev); + if (dp == NULL) + return host; + + prop = of_get_property(dp, "dcr-access-method", NULL); + + pr_debug("dcr_map_generic(dcr-access-method = %s)\n", prop); + + if (!strcmp(prop, "native")) { + host.type = DCR_HOST_NATIVE; + host.host.native = dcr_map_native(dev, dcr_n, dcr_c); + } else if (!strcmp(prop, "mmio")) { + host.type = DCR_HOST_MMIO; + host.host.mmio = dcr_map_mmio(dev, dcr_n, dcr_c); + } + + of_node_put(dp); + return host; +} +EXPORT_SYMBOL_GPL(dcr_map_generic); + +void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c) +{ + if (host.type == DCR_HOST_NATIVE) + dcr_unmap_native(host.host.native, dcr_c); + else if (host.type == DCR_HOST_MMIO) + dcr_unmap_mmio(host.host.mmio, dcr_c); + else /* host.type == DCR_HOST_INVALID */ + WARN_ON(true); +} +EXPORT_SYMBOL_GPL(dcr_unmap_generic); + +u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n) +{ + if (host.type == DCR_HOST_NATIVE) + return dcr_read_native(host.host.native, dcr_n); + else if (host.type == DCR_HOST_MMIO) + return dcr_read_mmio(host.host.mmio, dcr_n); + else /* host.type == DCR_HOST_INVALID */ + WARN_ON(true); + return 0; +} +EXPORT_SYMBOL_GPL(dcr_read_generic); + +void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value) +{ + if (host.type == DCR_HOST_NATIVE) + dcr_write_native(host.host.native, dcr_n, value); + else if (host.type == DCR_HOST_MMIO) + dcr_write_mmio(host.host.mmio, dcr_n, value); + else /* host.type == DCR_HOST_INVALID */ + WARN_ON(true); +} +EXPORT_SYMBOL_GPL(dcr_write_generic); + +#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */ + unsigned int dcr_resource_start(struct device_node *np, unsigned int index) { unsigned int ds; @@ -47,26 +146,7 @@ unsigned int dcr_resource_len(struct device_node *np, unsigned int index) } EXPORT_SYMBOL_GPL(dcr_resource_len); -#ifndef CONFIG_PPC_DCR_NATIVE - -static struct device_node * find_dcr_parent(struct device_node * node) -{ - struct device_node *par, *tmp; - const u32 *p; - - for (par = of_node_get(node); par;) { - if (of_get_property(par, "dcr-controller", NULL)) - break; - p = of_get_property(par, "dcr-parent", NULL); - tmp = par; - if (p == NULL) - par = of_get_parent(par); - else - par = of_find_node_by_phandle(*p); - of_node_put(tmp); - } - return par; -} +#ifdef CONFIG_PPC_DCR_MMIO u64 of_translate_dcr_address(struct device_node *dev, unsigned int dcr_n, @@ -75,7 +155,7 @@ u64 of_translate_dcr_address(struct device_node *dev, struct device_node *dp; const u32 *p; unsigned int stride; - u64 ret; + u64 ret = OF_BAD_ADDR; dp = find_dcr_parent(dev); if (dp == NULL) @@ -90,7 +170,7 @@ u64 of_translate_dcr_address(struct device_node *dev, if (p == NULL) p = of_get_property(dp, "dcr-mmio-space", NULL); if (p == NULL) - return OF_BAD_ADDR; + goto done; /* Maybe could do some better range checking here */ ret = of_translate_address(dp, p); @@ -98,21 +178,25 @@ u64 of_translate_dcr_address(struct device_node *dev, ret += (u64)(stride) * (u64)dcr_n; if (out_stride) *out_stride = stride; + + done: + of_node_put(dp); return ret; } -dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n, - unsigned int dcr_c) +dcr_host_mmio_t dcr_map_mmio(struct device_node *dev, + unsigned int dcr_n, + unsigned int dcr_c) { - dcr_host_t ret = { .token = NULL, .stride = 0, .base = dcr_n }; + dcr_host_mmio_t ret = { .token = NULL, .stride = 0, .base = dcr_n }; u64 addr; pr_debug("dcr_map(%s, 0x%x, 0x%x)\n", dev->full_name, dcr_n, dcr_c); addr = of_translate_dcr_address(dev, dcr_n, &ret.stride); - pr_debug("translates to addr: 0x%lx, stride: 0x%x\n", - addr, ret.stride); + pr_debug("translates to addr: 0x%llx, stride: 0x%x\n", + (unsigned long long) addr, ret.stride); if (addr == OF_BAD_ADDR) return ret; pr_debug("mapping 0x%x bytes\n", dcr_c * ret.stride); @@ -124,11 +208,11 @@ dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n, ret.token -= dcr_n * ret.stride; return ret; } -EXPORT_SYMBOL_GPL(dcr_map); +EXPORT_SYMBOL_GPL(dcr_map_mmio); -void dcr_unmap(dcr_host_t host, unsigned int dcr_c) +void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c) { - dcr_host_t h = host; + dcr_host_mmio_t h = host; if (h.token == NULL) return; @@ -136,7 +220,11 @@ void dcr_unmap(dcr_host_t host, unsigned int dcr_c) iounmap(h.token); h.token = NULL; } -EXPORT_SYMBOL_GPL(dcr_unmap); -#else /* defined(CONFIG_PPC_DCR_NATIVE) */ +EXPORT_SYMBOL_GPL(dcr_unmap_mmio); + +#endif /* defined(CONFIG_PPC_DCR_MMIO) */ + +#ifdef CONFIG_PPC_DCR_NATIVE DEFINE_SPINLOCK(dcr_ind_lock); -#endif /* !defined(CONFIG_PPC_DCR_NATIVE) */ +#endif /* defined(CONFIG_PPC_DCR_NATIVE) */ + diff --git a/include/asm-powerpc/dcr-generic.h b/include/asm-powerpc/dcr-generic.h new file mode 100644 index 000000000000..35b71599ec46 --- /dev/null +++ b/include/asm-powerpc/dcr-generic.h @@ -0,0 +1,49 @@ +/* + * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + * the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _ASM_POWERPC_DCR_GENERIC_H +#define _ASM_POWERPC_DCR_GENERIC_H +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + +enum host_type_t {DCR_HOST_MMIO, DCR_HOST_NATIVE, DCR_HOST_INVALID}; + +typedef struct { + enum host_type_t type; + union { + dcr_host_mmio_t mmio; + dcr_host_native_t native; + } host; +} dcr_host_t; + +extern bool dcr_map_ok_generic(dcr_host_t host); + +extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned int dcr_n, + unsigned int dcr_c); +extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c); + +extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n); + +extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value); + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL__ */ +#endif /* _ASM_POWERPC_DCR_GENERIC_H */ + + diff --git a/include/asm-powerpc/dcr-mmio.h b/include/asm-powerpc/dcr-mmio.h index 08532ff1899c..acd491dbd45a 100644 --- a/include/asm-powerpc/dcr-mmio.h +++ b/include/asm-powerpc/dcr-mmio.h @@ -27,20 +27,26 @@ typedef struct { void __iomem *token; unsigned int stride; unsigned int base; -} dcr_host_t; +} dcr_host_mmio_t; -#define DCR_MAP_OK(host) ((host).token != NULL) +static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host) +{ + return host.token != NULL; +} -extern dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n, - unsigned int dcr_c); -extern void dcr_unmap(dcr_host_t host, unsigned int dcr_c); +extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev, + unsigned int dcr_n, + unsigned int dcr_c); +extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c); -static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n) +static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int dcr_n) { return in_be32(host.token + ((host.base + dcr_n) * host.stride)); } -static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value) +static inline void dcr_write_mmio(dcr_host_mmio_t host, + unsigned int dcr_n, + u32 value) { out_be32(host.token + ((host.base + dcr_n) * host.stride), value); } diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h index f8398ce80372..72d2b72c7390 100644 --- a/include/asm-powerpc/dcr-native.h +++ b/include/asm-powerpc/dcr-native.h @@ -26,14 +26,18 @@ typedef struct { unsigned int base; -} dcr_host_t; +} dcr_host_native_t; -#define DCR_MAP_OK(host) (1) +static inline bool dcr_map_ok_native(dcr_host_native_t host) +{ + return 1; +} -#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) }) -#define dcr_unmap(host, dcr_c) do {} while (0) -#define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base) -#define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base, value) +#define dcr_map_native(dev, dcr_n, dcr_c) \ + ((dcr_host_native_t){ .base = (dcr_n) }) +#define dcr_unmap_native(host, dcr_c) do {} while (0) +#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base) +#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value) /* Device Control Registers */ void __mtdcr(int reg, unsigned int val); diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h index 9338d50538f1..53b283050ab3 100644 --- a/include/asm-powerpc/dcr.h +++ b/include/asm-powerpc/dcr.h @@ -20,14 +20,50 @@ #ifndef _ASM_POWERPC_DCR_H #define _ASM_POWERPC_DCR_H #ifdef __KERNEL__ +#ifndef __ASSEMBLY__ #ifdef CONFIG_PPC_DCR #ifdef CONFIG_PPC_DCR_NATIVE #include -#else +#endif + +#ifdef CONFIG_PPC_DCR_MMIO #include #endif + +/* Indirection layer for providing both NATIVE and MMIO support. */ + +#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) + +#include + +#define DCR_MAP_OK(host) dcr_map_ok_generic(host) +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c) +#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c) +#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n) +#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value) + +#else + +#ifdef CONFIG_PPC_DCR_NATIVE +typedef dcr_host_native_t dcr_host_t; +#define DCR_MAP_OK(host) dcr_map_ok_native(host) +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c) +#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c) +#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n) +#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value) +#else +typedef dcr_host_mmio_t dcr_host_t; +#define DCR_MAP_OK(host) dcr_map_ok_mmio(host) +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c) +#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c) +#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n) +#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value) +#endif + +#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */ + /* * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR * base from the device-tree @@ -41,5 +77,6 @@ extern unsigned int dcr_resource_len(struct device_node *np, #endif /* CONFIG_PPC_MERGE */ #endif /* CONFIG_PPC_DCR */ +#endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_DCR_H */ -- cgit v1.2.3 From bcf0b0880710409420a4e3b15dbf4b9a63542c0b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 30 Apr 2008 03:49:55 -0500 Subject: [POWERPC] Move to runtime allocated exception stacks For the additonal exception levels (critical, debug, machine check) on 40x/book-e we were using "static" allocations of the stack in the associated head.S. Move to a runtime allocation to make the code a bit easier to read as we mimic how we handle IRQ stacks. Its also a bit easier to setup the stack with a "dummy" thread_info in C code. Signed-off-by: Kumar Gala Acked-by: Paul Mackerras --- arch/powerpc/kernel/head_40x.S | 18 ++++-------------- arch/powerpc/kernel/head_44x.S | 9 --------- arch/powerpc/kernel/head_booke.h | 29 +++++++++++------------------ arch/powerpc/kernel/head_fsl_booke.S | 9 --------- arch/powerpc/kernel/irq.c | 33 +++++++++++++++++++++++++++++++++ arch/powerpc/kernel/setup_32.c | 24 ++++++++++++++++++++++++ include/asm-powerpc/irq.h | 13 +++++++++++++ 7 files changed, 85 insertions(+), 50 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S index 8552e67e3a8b..f2cf60d38f78 100644 --- a/arch/powerpc/kernel/head_40x.S +++ b/arch/powerpc/kernel/head_40x.S @@ -148,14 +148,14 @@ _ENTRY(crit_r11) mfcr r10; /* save CR in r10 for now */\ mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ andi. r11,r11,MSR_PR; \ - lis r11,critical_stack_top@h; \ - ori r11,r11,critical_stack_top@l; \ + lis r11,critirq_ctx@ha; \ + tophys(r11,r11); \ + lwz r11,critirq_ctx@l(r11); \ beq 1f; \ /* COMING FROM USER MODE */ \ mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ - addi r11,r11,THREAD_SIZE; \ -1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ +1: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\ tophys(r11,r11); \ stw r10,_CCR(r11); /* save various registers */\ stw r12,GPR12(r11); \ @@ -996,16 +996,6 @@ empty_zero_page: swapper_pg_dir: .space PGD_TABLE_SIZE - -/* Stack for handling critical exceptions from kernel mode */ - .section .bss - .align 12 -exception_stack_bottom: - .space 4096 -critical_stack_top: - .globl exception_stack_top -exception_stack_top: - /* Room for two PTE pointers, usually the kernel and current user pointers * to their respective root page table. */ diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index c2b9dc4fce5d..47ea8affad23 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -737,15 +737,6 @@ empty_zero_page: swapper_pg_dir: .space PGD_TABLE_SIZE -/* Reserved 4k for the critical exception stack & 4k for the machine - * check stack per CPU for kernel mode exceptions */ - .section .bss - .align 12 -exception_stack_bottom: - .space BOOKE_EXCEPTION_STACK_SIZE - .globl exception_stack_top -exception_stack_top: - /* * Room for two PTE pointers, usually the kernel and current user pointers * to their respective root page table. diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 721faef87095..9eacf4ca442a 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -43,9 +43,7 @@ SAVE_2GPRS(7, r11) /* To handle the additional exception priority levels on 40x and Book-E - * processors we allocate a 4k stack per additional priority level. The various - * head_xxx.S files allocate space (exception_stack_top) for each priority's - * stack times the number of CPUs + * processors we allocate a stack per additional priority level. * * On 40x critical is the only additional level * On 44x/e500 we have critical and machine check @@ -61,36 +59,31 @@ * going to critical or their own debug level we aren't currently * providing configurations that micro-optimize space usage. */ -#ifdef CONFIG_44x -#define NUM_EXCEPTION_LVLS 2 -#else -#define NUM_EXCEPTION_LVLS 3 -#endif -#define BOOKE_EXCEPTION_STACK_SIZE (4096 * NUM_EXCEPTION_LVLS) /* CRIT_SPRG only used in critical exception handling */ #define CRIT_SPRG SPRN_SPRG2 /* MCHECK_SPRG only used in machine check exception handling */ #define MCHECK_SPRG SPRN_SPRG6W -#define MCHECK_STACK_TOP (exception_stack_top - 4096) -#define CRIT_STACK_TOP (exception_stack_top) +#define MCHECK_STACK_BASE mcheckirq_ctx +#define CRIT_STACK_BASE critirq_ctx /* only on e200 for now */ -#define DEBUG_STACK_TOP (exception_stack_top - 8192) +#define DEBUG_STACK_BASE dbgirq_ctx #define DEBUG_SPRG SPRN_SPRG6W #ifdef CONFIG_SMP #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ mfspr r8,SPRN_PIR; \ - mulli r8,r8,BOOKE_EXCEPTION_STACK_SIZE; \ - neg r8,r8; \ - addis r8,r8,level##_STACK_TOP@ha; \ - addi r8,r8,level##_STACK_TOP@l + slwi r8,r8,2; \ + addis r8,r8,level##_STACK_BASE@ha; \ + lwz r8,level##_STACK_BASE@l(r8); \ + addi r8,r8,THREAD_SIZE; #else #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ - lis r8,level##_STACK_TOP@h; \ - ori r8,r8,level##_STACK_TOP@l + lis r8,level##_STACK_BASE@ha; \ + lwz r8,level##_STACK_BASE@l(r8); \ + addi r8,r8,THREAD_SIZE; #endif /* diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index e581524d85bc..503f86030b6e 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -1080,15 +1080,6 @@ empty_zero_page: swapper_pg_dir: .space PGD_TABLE_SIZE -/* Reserved 4k for the critical exception stack & 4k for the machine - * check stack per CPU for kernel mode exceptions */ - .section .bss - .align 12 -exception_stack_bottom: - .space BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS - .globl exception_stack_top -exception_stack_top: - /* * Room for two PTE pointers, usually the kernel and current user pointers * to their respective root page table. diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 2f73f705d564..b5199752ac60 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -356,9 +356,42 @@ void __init init_IRQ(void) { if (ppc_md.init_IRQ) ppc_md.init_IRQ(); + + exc_lvl_ctx_init(); + irq_ctx_init(); } +#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) +struct thread_info *critirq_ctx[NR_CPUS] __read_mostly; +struct thread_info *dbgirq_ctx[NR_CPUS] __read_mostly; +struct thread_info *mcheckirq_ctx[NR_CPUS] __read_mostly; + +void exc_lvl_ctx_init(void) +{ + struct thread_info *tp; + int i; + + for_each_possible_cpu(i) { + memset((void *)critirq_ctx[i], 0, THREAD_SIZE); + tp = critirq_ctx[i]; + tp->cpu = i; + tp->preempt_count = 0; + +#ifdef CONFIG_BOOKE + memset((void *)dbgirq_ctx[i], 0, THREAD_SIZE); + tp = dbgirq_ctx[i]; + tp->cpu = i; + tp->preempt_count = 0; + + memset((void *)mcheckirq_ctx[i], 0, THREAD_SIZE); + tp = mcheckirq_ctx[i]; + tp->cpu = i; + tp->preempt_count = HARDIRQ_OFFSET; +#endif + } +} +#endif #ifdef CONFIG_IRQSTACKS struct thread_info *softirq_ctx[NR_CPUS] __read_mostly; diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index 5112a4aa801d..bef0be3fd98b 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -248,6 +248,28 @@ static void __init irqstack_early_init(void) #define irqstack_early_init() #endif +#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) +static void __init exc_lvl_early_init(void) +{ + unsigned int i; + + /* interrupt stacks must be in lowmem, we get that for free on ppc32 + * as the lmb is limited to lowmem by LMB_REAL_LIMIT */ + for_each_possible_cpu(i) { + critirq_ctx[i] = (struct thread_info *) + __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); +#ifdef CONFIG_BOOKE + dbgirq_ctx[i] = (struct thread_info *) + __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); + mcheckirq_ctx[i] = (struct thread_info *) + __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); +#endif + } +} +#else +#define exc_lvl_early_init() +#endif + /* Warning, IO base is not yet inited */ void __init setup_arch(char **cmdline_p) { @@ -305,6 +327,8 @@ void __init setup_arch(char **cmdline_p) init_mm.end_data = (unsigned long) _edata; init_mm.brk = klimit; + exc_lvl_early_init(); + irqstack_early_init(); /* set up the bootmem stuff with available memory */ diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 5089deb8fec3..1ef8e304e0ea 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h @@ -619,6 +619,19 @@ struct pt_regs; #define __ARCH_HAS_DO_SOFTIRQ +#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) +/* + * Per-cpu stacks for handling critical, debug and machine check + * level interrupts. + */ +extern struct thread_info *critirq_ctx[NR_CPUS]; +extern struct thread_info *dbgirq_ctx[NR_CPUS]; +extern struct thread_info *mcheckirq_ctx[NR_CPUS]; +extern void exc_lvl_ctx_init(void); +#else +#define exc_lvl_ctx_init() +#endif + #ifdef CONFIG_IRQSTACKS /* * Per-cpu stacks for handling hard and soft interrupts. -- cgit v1.2.3 From a6a8d9f87eb8510a8f53672ea87703f62185d75f Mon Sep 17 00:00:00 2001 From: Chandra Seetharaman Date: Thu, 1 May 2008 14:49:46 -0700 Subject: [SCSI] scsi_dh: add infrastructure for SCSI Device Handlers Some of the storage devices (that can be accessed through multiple paths), do need some special handling for 1. Activating the passive path of the storage access. 2. Decode and handle the special sense codes returned by the devices. 3. Handle the I/Os being sent to the passive path, especially during the device probe time. when accessed through multiple paths. As of today this special device handling is done at the dm-multipath layer using dm-handlers. That works well for (1); for (2) to be handled at dm layer, scsi sense information need to be exported from SCSI to dm-layer, which is not very attractive; (3) cannot be done at all at the dm layer. Device handler has been moved to SCSI mainly to handle (2) and (3) properly. Signed-off-by: Chandra Seetharaman Signed-off-by: Mike Anderson Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/scsi/Kconfig | 2 + drivers/scsi/Makefile | 1 + drivers/scsi/device_handler/Kconfig | 12 +++ drivers/scsi/device_handler/Makefile | 4 + drivers/scsi/device_handler/scsi_dh.c | 162 ++++++++++++++++++++++++++++++++++ drivers/scsi/scsi_error.c | 11 +++ drivers/scsi/scsi_lib.c | 8 ++ drivers/scsi/scsi_sysfs.c | 1 + include/scsi/scsi.h | 1 + include/scsi/scsi_device.h | 22 +++++ include/scsi/scsi_dh.h | 59 +++++++++++++ 11 files changed, 283 insertions(+) create mode 100644 drivers/scsi/device_handler/Kconfig create mode 100644 drivers/scsi/device_handler/Makefile create mode 100644 drivers/scsi/device_handler/scsi_dh.c create mode 100644 include/scsi/scsi_dh.h (limited to 'include') diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 81ccbd7f9e34..7886ec6e5f87 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -1771,4 +1771,6 @@ endif # SCSI_LOWLEVEL source "drivers/scsi/pcmcia/Kconfig" +source "drivers/scsi/device_handler/Kconfig" + endmenu diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index 6c775e350c98..aa8272e188ea 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SCSI_ISCSI_ATTRS) += scsi_transport_iscsi.o obj-$(CONFIG_SCSI_SAS_ATTRS) += scsi_transport_sas.o obj-$(CONFIG_SCSI_SAS_LIBSAS) += libsas/ obj-$(CONFIG_SCSI_SRP_ATTRS) += scsi_transport_srp.o +obj-$(CONFIG_SCSI_DH) += device_handler/ obj-$(CONFIG_ISCSI_TCP) += libiscsi.o iscsi_tcp.o obj-$(CONFIG_INFINIBAND_ISER) += libiscsi.o diff --git a/drivers/scsi/device_handler/Kconfig b/drivers/scsi/device_handler/Kconfig new file mode 100644 index 000000000000..228241d1d98c --- /dev/null +++ b/drivers/scsi/device_handler/Kconfig @@ -0,0 +1,12 @@ +# +# SCSI Device Handler configuration +# + +menuconfig SCSI_DH + tristate "SCSI Device Handlers" + depends on SCSI + default n + help + SCSI Device Handlers provide device specific support for + devices utilized in multipath configurations. Say Y here to + select support for specific hardware. diff --git a/drivers/scsi/device_handler/Makefile b/drivers/scsi/device_handler/Makefile new file mode 100644 index 000000000000..f306e44e3837 --- /dev/null +++ b/drivers/scsi/device_handler/Makefile @@ -0,0 +1,4 @@ +# +# SCSI Device Handler +# +obj-$(CONFIG_SCSI_DH) += scsi_dh.o diff --git a/drivers/scsi/device_handler/scsi_dh.c b/drivers/scsi/device_handler/scsi_dh.c new file mode 100644 index 000000000000..ab6c21cd9689 --- /dev/null +++ b/drivers/scsi/device_handler/scsi_dh.c @@ -0,0 +1,162 @@ +/* + * SCSI device handler infrastruture. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright IBM Corporation, 2007 + * Authors: + * Chandra Seetharaman + * Mike Anderson + */ + +#include +#include "../scsi_priv.h" + +static DEFINE_SPINLOCK(list_lock); +static LIST_HEAD(scsi_dh_list); + +static struct scsi_device_handler *get_device_handler(const char *name) +{ + struct scsi_device_handler *tmp, *found = NULL; + + spin_lock(&list_lock); + list_for_each_entry(tmp, &scsi_dh_list, list) { + if (!strcmp(tmp->name, name)) { + found = tmp; + break; + } + } + spin_unlock(&list_lock); + return found; +} + +static int scsi_dh_notifier_add(struct device *dev, void *data) +{ + struct scsi_device_handler *scsi_dh = data; + + scsi_dh->nb.notifier_call(&scsi_dh->nb, BUS_NOTIFY_ADD_DEVICE, dev); + return 0; +} + +/* + * scsi_register_device_handler - register a device handler personality + * module. + * @scsi_dh - device handler to be registered. + * + * Returns 0 on success, -EBUSY if handler already registered. + */ +int scsi_register_device_handler(struct scsi_device_handler *scsi_dh) +{ + int ret = -EBUSY; + struct scsi_device_handler *tmp; + + tmp = get_device_handler(scsi_dh->name); + if (tmp) + goto done; + + ret = bus_register_notifier(&scsi_bus_type, &scsi_dh->nb); + + bus_for_each_dev(&scsi_bus_type, NULL, scsi_dh, scsi_dh_notifier_add); + spin_lock(&list_lock); + list_add(&scsi_dh->list, &scsi_dh_list); + spin_unlock(&list_lock); + +done: + return ret; +} +EXPORT_SYMBOL_GPL(scsi_register_device_handler); + +static int scsi_dh_notifier_remove(struct device *dev, void *data) +{ + struct scsi_device_handler *scsi_dh = data; + + scsi_dh->nb.notifier_call(&scsi_dh->nb, BUS_NOTIFY_DEL_DEVICE, dev); + return 0; +} + +/* + * scsi_unregister_device_handler - register a device handler personality + * module. + * @scsi_dh - device handler to be unregistered. + * + * Returns 0 on success, -ENODEV if handler not registered. + */ +int scsi_unregister_device_handler(struct scsi_device_handler *scsi_dh) +{ + int ret = -ENODEV; + struct scsi_device_handler *tmp; + + tmp = get_device_handler(scsi_dh->name); + if (!tmp) + goto done; + + ret = bus_unregister_notifier(&scsi_bus_type, &scsi_dh->nb); + + bus_for_each_dev(&scsi_bus_type, NULL, scsi_dh, + scsi_dh_notifier_remove); + spin_lock(&list_lock); + list_del(&scsi_dh->list); + spin_unlock(&list_lock); + +done: + return ret; +} +EXPORT_SYMBOL_GPL(scsi_unregister_device_handler); + +/* + * scsi_dh_activate - activate the path associated with the scsi_device + * corresponding to the given request queue. + * @q - Request queue that is associated with the scsi_device to be + * activated. + */ +int scsi_dh_activate(struct request_queue *q) +{ + int err = 0; + unsigned long flags; + struct scsi_device *sdev; + struct scsi_device_handler *scsi_dh = NULL; + + spin_lock_irqsave(q->queue_lock, flags); + sdev = q->queuedata; + if (sdev && sdev->scsi_dh_data) + scsi_dh = sdev->scsi_dh_data->scsi_dh; + if (!scsi_dh || !get_device(&sdev->sdev_gendev)) + err = SCSI_DH_NOSYS; + spin_unlock_irqrestore(q->queue_lock, flags); + + if (err) + return err; + + if (scsi_dh->activate) + err = scsi_dh->activate(sdev); + put_device(&sdev->sdev_gendev); + return err; +} +EXPORT_SYMBOL_GPL(scsi_dh_activate); + +/* + * scsi_dh_handler_exist - Return TRUE(1) if a device handler exists for + * the given name. FALSE(0) otherwise. + * @name - name of the device handler. + */ +int scsi_dh_handler_exist(const char *name) +{ + return (get_device_handler(name) != NULL); +} +EXPORT_SYMBOL_GPL(scsi_dh_handler_exist); + +MODULE_DESCRIPTION("SCSI device handler"); +MODULE_AUTHOR("Chandra Seetharaman "); +MODULE_LICENSE("GPL"); diff --git a/drivers/scsi/scsi_error.c b/drivers/scsi/scsi_error.c index eaf5a8add1ba..006a95916f72 100644 --- a/drivers/scsi/scsi_error.c +++ b/drivers/scsi/scsi_error.c @@ -298,6 +298,7 @@ static inline void scsi_eh_prt_fail_stats(struct Scsi_Host *shost, */ static int scsi_check_sense(struct scsi_cmnd *scmd) { + struct scsi_device *sdev = scmd->device; struct scsi_sense_hdr sshdr; if (! scsi_command_normalize_sense(scmd, &sshdr)) @@ -306,6 +307,16 @@ static int scsi_check_sense(struct scsi_cmnd *scmd) if (scsi_sense_is_deferred(&sshdr)) return NEEDS_RETRY; + if (sdev->scsi_dh_data && sdev->scsi_dh_data->scsi_dh && + sdev->scsi_dh_data->scsi_dh->check_sense) { + int rc; + + rc = sdev->scsi_dh_data->scsi_dh->check_sense(sdev, &sshdr); + if (rc != SCSI_RETURN_NOT_HANDLED) + return rc; + /* handler does not care. Drop down to default handling */ + } + /* * Previous logic looked for FILEMARK, EOM or ILI which are * mainly associated with tapes and returned SUCCESS. diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index a82d2fe80fb5..033c58a65f50 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c @@ -1160,6 +1160,14 @@ int scsi_setup_fs_cmnd(struct scsi_device *sdev, struct request *req) if (ret != BLKPREP_OK) return ret; + + if (unlikely(sdev->scsi_dh_data && sdev->scsi_dh_data->scsi_dh + && sdev->scsi_dh_data->scsi_dh->prep_fn)) { + ret = sdev->scsi_dh_data->scsi_dh->prep_fn(sdev, req); + if (ret != BLKPREP_OK) + return ret; + } + /* * Filesystem requests must transfer data. */ diff --git a/drivers/scsi/scsi_sysfs.c b/drivers/scsi/scsi_sysfs.c index 93d2b6714453..b6e561059779 100644 --- a/drivers/scsi/scsi_sysfs.c +++ b/drivers/scsi/scsi_sysfs.c @@ -439,6 +439,7 @@ struct bus_type scsi_bus_type = { .resume = scsi_bus_resume, .remove = scsi_bus_remove, }; +EXPORT_SYMBOL_GPL(scsi_bus_type); int scsi_sysfs_register(void) { diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h index 32742c4563de..2b5b9356c314 100644 --- a/include/scsi/scsi.h +++ b/include/scsi/scsi.h @@ -400,6 +400,7 @@ struct scsi_lun { #define SOFT_ERROR 0x2005 #define ADD_TO_MLQUEUE 0x2006 #define TIMEOUT_ERROR 0x2007 +#define SCSI_RETURN_NOT_HANDLED 0x2008 /* * Midlevel queue return values. diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h index f6a9fe0ef09c..06b979f105b7 100644 --- a/include/scsi/scsi_device.h +++ b/include/scsi/scsi_device.h @@ -161,9 +161,29 @@ struct scsi_device { struct execute_work ew; /* used to get process context on put */ + struct scsi_dh_data *scsi_dh_data; enum scsi_device_state sdev_state; unsigned long sdev_data[0]; } __attribute__((aligned(sizeof(unsigned long)))); + +struct scsi_device_handler { + /* Used by the infrastructure */ + struct list_head list; /* list of scsi_device_handlers */ + struct notifier_block nb; + + /* Filled by the hardware handler */ + struct module *module; + const char *name; + int (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *); + int (*activate)(struct scsi_device *); + int (*prep_fn)(struct scsi_device *, struct request *); +}; + +struct scsi_dh_data { + struct scsi_device_handler *scsi_dh; + char buf[0]; +}; + #define to_scsi_device(d) \ container_of(d, struct scsi_device, sdev_gendev) #define class_to_sdev(d) \ @@ -230,7 +250,9 @@ extern struct scsi_device *__scsi_add_device(struct Scsi_Host *, uint, uint, uint, void *hostdata); extern int scsi_add_device(struct Scsi_Host *host, uint channel, uint target, uint lun); +extern int scsi_register_device_handler(struct scsi_device_handler *scsi_dh); extern void scsi_remove_device(struct scsi_device *); +extern int scsi_unregister_device_handler(struct scsi_device_handler *scsi_dh); extern int scsi_device_get(struct scsi_device *); extern void scsi_device_put(struct scsi_device *); diff --git a/include/scsi/scsi_dh.h b/include/scsi/scsi_dh.h new file mode 100644 index 000000000000..04d0d8495c83 --- /dev/null +++ b/include/scsi/scsi_dh.h @@ -0,0 +1,59 @@ +/* + * Header file for SCSI device handler infrastruture. + * + * Modified version of patches posted by Mike Christie + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright IBM Corporation, 2007 + * Authors: + * Chandra Seetharaman + * Mike Anderson + */ + +#include + +enum { + SCSI_DH_OK = 0, + /* + * device errors + */ + SCSI_DH_DEV_FAILED, /* generic device error */ + SCSI_DH_DEV_TEMP_BUSY, + SCSI_DH_DEVICE_MAX, /* max device blkerr definition */ + + /* + * transport errors + */ + SCSI_DH_NOTCONN = SCSI_DH_DEVICE_MAX + 1, + SCSI_DH_CONN_FAILURE, + SCSI_DH_TRANSPORT_MAX, /* max transport blkerr definition */ + + /* + * driver and generic errors + */ + SCSI_DH_IO = SCSI_DH_TRANSPORT_MAX + 1, /* generic error */ + SCSI_DH_INVALID_IO, + SCSI_DH_RETRY, /* retry the req, but not immediately */ + SCSI_DH_IMM_RETRY, /* immediately retry the req */ + SCSI_DH_TIMED_OUT, + SCSI_DH_RES_TEMP_UNAVAIL, + SCSI_DH_DEV_OFFLINED, + SCSI_DH_NOSYS, + SCSI_DH_DRIVER_MAX, +}; + +extern int scsi_dh_activate(struct request_queue *); +extern int scsi_dh_handler_exist(const char *); -- cgit v1.2.3 From 7c4f10b9003dc8423df07574ba197bbbe3bc382b Mon Sep 17 00:00:00 2001 From: Rune Torgersen Date: Sat, 24 May 2008 01:59:15 +1000 Subject: powerpc: Check that TASK_SIZE does not overlap KERNEL_START Make sure CONFIG_TASK_SIZE does not overlap CONFIG_KERNEL_START This could happen when overriding settings to get 1GB lowmem, and would lead to userland mysteriousely hanging. This setting is only used by PPC32. Signed-off-by: Rune Torgersen Acked-by: Kumar Gala Signed-off-by: Paul Mackerras --- include/asm-powerpc/processor.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index cf83f2d7e2a5..a1deed85f31d 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h @@ -81,6 +81,10 @@ extern struct task_struct *last_task_used_altivec; extern struct task_struct *last_task_used_spe; #ifdef CONFIG_PPC32 + +#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START +#error User TASK_SIZE overlaps with KERNEL_START address +#endif #define TASK_SIZE (CONFIG_TASK_SIZE) /* This decides where the kernel will search for a free chunk of vm -- cgit v1.2.3 From 0f3d6bcd391b058c619fc30e8022e8a29fbf4bef Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 28 May 2008 09:48:32 +1000 Subject: powerpc: Improve (in|out)_[bl]eXX() asm code Since commit 4cb3cee03d558fd457cb58f56c80a2a09a66110c the code generated for the in_beXX() and out_beXX() mmio functions has been sub-optimal. The out_leXX() family of functions are created with the macro DEF_MMIO_OUT_LE() while the out_beXX() family are created with DEF_MMIO_OUT_BE(). In what was perhaps a bit too much macro use, both of these macros are in turn created via the macro DEF_MMIO_OUT(). For the LE versions, eventually they boil down to an asm that will look something like this: asm("sync; stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); The issue is that the "stwbrx" instruction only comes in an indexed, or 'x', version, in which the address is represented by the sum of two registers (the "0,%2"). Unfortunately, gcc doesn't have a constraint for an indexed memory reference. The "m" constraint allows both indexed and offset, i.e. register plus constant, memory references and there is no "stwbr" version for offset references. "m" also allows updating addresses and there is no 'u' version of "stwbrx" like there is with "stwux". The unused first operand to the asm is just to tell gcc that *addr is an output of the asm. The address used is passed in a single register via the third asm operand, and the index register is just hard coded as 0. This means gcc is forced to put the address in a single register and can't use index addressing, e.g. if one has the data in register 9, a base address in register 3 and an index in register 4, gcc must emit code like "add 11,4,3; stwbrx 9,0,11" instead of just "stwbrx 9,4,3". This costs an extra add instruction and another register. For gcc 4.0 and older, there doesn't appear to be anything that can be done. But for 4.1 and newer, there is a 'Z' constraint. It does not allow "updating" addresses, but does allow both indexed and offset addresses. However, the only allowed constant offset is 0. We can then use the undocumented 'y' operand modifier, which causes gcc to convert "0(reg)" into the equivilient "0,reg" format that can be used with stwbrx. This brings us the to problem with the BE version. In this case, the "stw" instruction does have both indexed and non-indexed versions. The final asm ends up looking like this: asm("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val), "r" (addr)); The undocumented codes "%U0" and "%0X" will generate a 'u' if the memory reference should be an auto-updating one, and an 'x' if the memory reference is indexed, respectively. The third operand is unused, it's just there because asm the code is reused from the LE version. However, gcc does not know this, and generates unnecessary code to stick addr in a register! To use the example from the LE version, gcc will generate "add 11,4,3; stwx 9,4,3". It is able to use the indexed address "4,3" for the "stwx", but still thinks it needs to put 4+3 into register 11, which will never be used. This also ends up happening a lot for the offset addressing mode, where common code like this: out_be32(&device_registers->some_register, data); uses an instruction like "stw 9, 42(3)", where register 3 has the pointer device_registers and 42 is the offset of some_register in that structure. gcc will be forced to generate the unnecessary instruction "addi 11, 3, 42" to put the address into a single (unused) register. The in_* versions end up having these exact same problems as well. Signed-off-by: Trent Piepho CC: Benjamin Herrenschmidt CC: Andreas Schwab Signed-off-by: Paul Mackerras --- include/asm-powerpc/io.h | 57 +++++++++++++++++++++++++++++++++++------------- 1 file changed, 42 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h index 89189488e286..6db422d8e2a0 100644 --- a/include/asm-powerpc/io.h +++ b/include/asm-powerpc/io.h @@ -95,33 +95,60 @@ extern resource_size_t isa_mem_base; #define IO_SET_SYNC_FLAG() #endif -#define DEF_MMIO_IN(name, type, insn) \ -static inline type name(const volatile type __iomem *addr) \ +/* gcc 4.0 and older doesn't have 'Z' constraint */ +#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0) +#define DEF_MMIO_IN_LE(name, size, insn) \ +static inline u##size name(const volatile u##size __iomem *addr) \ { \ - type ret; \ - __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync" \ + u##size ret; \ + __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \ : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \ return ret; \ } -#define DEF_MMIO_OUT(name, type, insn) \ -static inline void name(volatile type __iomem *addr, type val) \ +#define DEF_MMIO_OUT_LE(name, size, insn) \ +static inline void name(volatile u##size __iomem *addr, u##size val) \ { \ - __asm__ __volatile__("sync;" insn \ + __asm__ __volatile__("sync;"#insn" %1,0,%2" \ : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \ IO_SET_SYNC_FLAG(); \ } +#else /* newer gcc */ +#define DEF_MMIO_IN_LE(name, size, insn) \ +static inline u##size name(const volatile u##size __iomem *addr) \ +{ \ + u##size ret; \ + __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ + : "=r" (ret) : "Z" (*addr) : "memory"); \ + return ret; \ +} + +#define DEF_MMIO_OUT_LE(name, size, insn) \ +static inline void name(volatile u##size __iomem *addr, u##size val) \ +{ \ + __asm__ __volatile__("sync;"#insn" %1,%y0" \ + : "=Z" (*addr) : "r" (val) : "memory"); \ + IO_SET_SYNC_FLAG(); \ +} +#endif +#define DEF_MMIO_IN_BE(name, size, insn) \ +static inline u##size name(const volatile u##size __iomem *addr) \ +{ \ + u##size ret; \ + __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ + : "=r" (ret) : "m" (*addr) : "memory"); \ + return ret; \ +} -#define DEF_MMIO_IN_BE(name, size, insn) \ - DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2") -#define DEF_MMIO_IN_LE(name, size, insn) \ - DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1") +#define DEF_MMIO_OUT_BE(name, size, insn) \ +static inline void name(volatile u##size __iomem *addr, u##size val) \ +{ \ + __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ + : "=m" (*addr) : "r" (val) : "memory"); \ + IO_SET_SYNC_FLAG(); \ +} -#define DEF_MMIO_OUT_BE(name, size, insn) \ - DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0") -#define DEF_MMIO_OUT_LE(name, size, insn) \ - DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2") DEF_MMIO_IN_BE(in_8, 8, lbz); DEF_MMIO_IN_BE(in_be16, 16, lhz); -- cgit v1.2.3 From 917f0af9e5a9ceecf9e72537fabb501254ba321d Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Mon, 9 Jun 2008 14:01:46 +1000 Subject: powerpc: Remove arch/ppc and include/asm-ppc All the maintained platforms are now in arch/powerpc, so the old arch/ppc stuff can now go away. Acked-by: Adrian Bunk Acked-by: Arnd Bergmann Acked-by: Becky Bruce Acked-by: Benjamin Herrenschmidt Acked-by: Geert Uytterhoeven Acked-by: Grant Likely Acked-by: Jochen Friedrich Acked-by: John Linn Acked-by: Jon Loeliger Acked-by: Josh Boyer Acked-by: Kumar Gala Acked-by: Olof Johansson Acked-by: Peter Korsgaard Acked-by: Scott Wood Acked-by: Sean MacLennan Acked-by: Segher Boessenkool Acked-by: Stefan Roese Acked-by: Stephen Neuendorffer Acked-by: Wolfgang Denk Signed-off-by: Paul Mackerras --- arch/ppc/.gitignore | 1 - arch/ppc/4xx_io/Makefile | 6 - arch/ppc/4xx_io/serial_sicc.c | 2005 --------------- arch/ppc/8260_io/Kconfig | 65 - arch/ppc/8260_io/Makefile | 6 - arch/ppc/8260_io/enet.c | 865 ------- arch/ppc/8260_io/fcc_enet.c | 2379 ----------------- arch/ppc/8xx_io/Kconfig | 134 - arch/ppc/8xx_io/Makefile | 9 - arch/ppc/8xx_io/commproc.c | 432 ---- arch/ppc/8xx_io/enet.c | 982 ------- arch/ppc/8xx_io/fec.c | 1983 -------------- arch/ppc/8xx_io/micropatch.c | 743 ------ arch/ppc/Kconfig | 1186 --------- arch/ppc/Kconfig.debug | 66 - arch/ppc/Makefile | 135 - arch/ppc/boot/Makefile | 37 - arch/ppc/boot/common/Makefile | 10 - arch/ppc/boot/common/bootinfo.c | 68 - arch/ppc/boot/common/crt0.S | 80 - arch/ppc/boot/common/misc-common.c | 555 ---- arch/ppc/boot/common/ns16550.c | 103 - arch/ppc/boot/common/serial_stub.c | 21 - arch/ppc/boot/common/string.S | 150 -- arch/ppc/boot/common/util.S | 293 --- arch/ppc/boot/images/.gitignore | 6 - arch/ppc/boot/images/Makefile | 34 - arch/ppc/boot/include/cpc700.h | 26 - arch/ppc/boot/include/iso_font.h | 257 -- arch/ppc/boot/include/mpc10x.h | 63 - arch/ppc/boot/include/mpsc_defs.h | 146 -- arch/ppc/boot/include/nonstdio.h | 34 - arch/ppc/boot/include/of1275.h | 42 - arch/ppc/boot/include/rs6000.h | 243 -- arch/ppc/boot/include/serial.h | 46 - arch/ppc/boot/ld.script | 85 - arch/ppc/boot/lib/.gitignore | 3 - arch/ppc/boot/lib/Makefile | 23 - arch/ppc/boot/lib/div64.S | 58 - arch/ppc/boot/lib/kbd.c | 248 -- arch/ppc/boot/lib/vreset.c | 805 ------ arch/ppc/boot/of1275/Makefile | 6 - arch/ppc/boot/of1275/call_prom.c | 74 - arch/ppc/boot/of1275/claim.c | 92 - arch/ppc/boot/of1275/enter.c | 22 - arch/ppc/boot/of1275/exit.c | 24 - arch/ppc/boot/of1275/finddevice.c | 16 - arch/ppc/boot/of1275/getprop.c | 37 - arch/ppc/boot/of1275/map.c | 48 - arch/ppc/boot/of1275/ofinit.c | 27 - arch/ppc/boot/of1275/ofstdio.c | 32 - arch/ppc/boot/of1275/read.c | 35 - arch/ppc/boot/of1275/release.c | 30 - arch/ppc/boot/of1275/write.c | 35 - arch/ppc/boot/simple/Makefile | 277 -- arch/ppc/boot/simple/chrpmap.c | 12 - arch/ppc/boot/simple/clear.S | 19 - arch/ppc/boot/simple/cpc700_memory.c | 34 - arch/ppc/boot/simple/dummy.c | 4 - arch/ppc/boot/simple/embed_config.c | 938 ------- arch/ppc/boot/simple/head.S | 137 - arch/ppc/boot/simple/iic.c | 214 -- arch/ppc/boot/simple/m8260_tty.c | 325 --- arch/ppc/boot/simple/m8xx_tty.c | 289 --- arch/ppc/boot/simple/misc-chestnut.c | 32 - arch/ppc/boot/simple/misc-cpci690.c | 65 - arch/ppc/boot/simple/misc-embedded.c | 276 -- arch/ppc/boot/simple/misc-ev64260.c | 54 - arch/ppc/boot/simple/misc-ev64360.c | 42 - arch/ppc/boot/simple/misc-katana.c | 42 - arch/ppc/boot/simple/misc-mv64x60.c | 85 - arch/ppc/boot/simple/misc-prep.c | 209 -- arch/ppc/boot/simple/misc-radstone_ppc7d.c | 24 - arch/ppc/boot/simple/misc-spruce.c | 271 -- arch/ppc/boot/simple/misc.c | 278 -- arch/ppc/boot/simple/mpc10x_memory.c | 109 - arch/ppc/boot/simple/mpc52xx_tty.c | 137 - arch/ppc/boot/simple/mv64x60_tty.c | 364 --- arch/ppc/boot/simple/openbios.c | 128 - arch/ppc/boot/simple/pci.c | 274 -- arch/ppc/boot/simple/pibs.c | 104 - arch/ppc/boot/simple/prepmap.c | 12 - arch/ppc/boot/simple/qspan_pci.c | 269 -- arch/ppc/boot/simple/relocate.S | 213 -- arch/ppc/boot/simple/rw4/ppc_40x.h | 664 ----- arch/ppc/boot/simple/rw4/rw4_init.S | 78 - arch/ppc/boot/simple/rw4/rw4_init_brd.S | 1125 -------- arch/ppc/boot/simple/rw4/stb.h | 239 -- arch/ppc/boot/simple/uartlite_tty.c | 45 - arch/ppc/boot/utils/.gitignore | 3 - arch/ppc/boot/utils/elf.pl | 33 - arch/ppc/boot/utils/mkbugboot.c | 147 -- arch/ppc/boot/utils/mkprep.c | 241 -- arch/ppc/boot/utils/mktree.c | 152 -- arch/ppc/configs/FADS_defconfig | 520 ---- arch/ppc/configs/IVMS8_defconfig | 548 ---- arch/ppc/configs/TQM823L_defconfig | 521 ---- arch/ppc/configs/TQM8260_defconfig | 499 ---- arch/ppc/configs/TQM850L_defconfig | 521 ---- arch/ppc/configs/TQM860L_defconfig | 549 ---- arch/ppc/configs/bamboo_defconfig | 944 ------- arch/ppc/configs/bseip_defconfig | 517 ---- arch/ppc/configs/bubinga_defconfig | 592 ----- arch/ppc/configs/chestnut_defconfig | 794 ------ arch/ppc/configs/cpci405_defconfig | 631 ----- arch/ppc/configs/cpci690_defconfig | 798 ------ arch/ppc/configs/ebony_defconfig | 585 ----- arch/ppc/configs/ep405_defconfig | 572 ---- arch/ppc/configs/est8260_defconfig | 491 ---- arch/ppc/configs/ev64260_defconfig | 758 ------ arch/ppc/configs/ev64360_defconfig | 817 ------ arch/ppc/configs/hdpu_defconfig | 890 ------- arch/ppc/configs/katana_defconfig | 948 ------- arch/ppc/configs/lite5200_defconfig | 436 ---- arch/ppc/configs/lopec_defconfig | 814 ------ arch/ppc/configs/luan_defconfig | 668 ----- arch/ppc/configs/mbx_defconfig | 512 ---- arch/ppc/configs/ml300_defconfig | 739 ------ arch/ppc/configs/ml403_defconfig | 740 ------ arch/ppc/configs/mvme5100_defconfig | 746 ------ arch/ppc/configs/ocotea_defconfig | 599 ----- arch/ppc/configs/pplus_defconfig | 720 ------ arch/ppc/configs/prep_defconfig | 1679 ------------ arch/ppc/configs/prpmc750_defconfig | 594 ----- arch/ppc/configs/prpmc800_defconfig | 656 ----- arch/ppc/configs/radstone_ppc7d_defconfig | 991 ------- arch/ppc/configs/redwood5_defconfig | 557 ---- arch/ppc/configs/redwood6_defconfig | 535 ---- arch/ppc/configs/rpx8260_defconfig | 555 ---- arch/ppc/configs/rpxcllf_defconfig | 582 ----- arch/ppc/configs/rpxlite_defconfig | 581 ----- arch/ppc/configs/sandpoint_defconfig | 737 ------ arch/ppc/configs/spruce_defconfig | 577 ----- arch/ppc/configs/sycamore_defconfig | 663 ----- arch/ppc/configs/taishan_defconfig | 1077 -------- arch/ppc/configs/walnut_defconfig | 578 ----- arch/ppc/kernel/Makefile | 21 - arch/ppc/kernel/asm-offsets.c | 164 -- arch/ppc/kernel/cpu_setup_power4.S | 197 -- arch/ppc/kernel/entry.S | 960 ------- arch/ppc/kernel/head.S | 1220 --------- arch/ppc/kernel/head_44x.S | 769 ------ arch/ppc/kernel/head_4xx.S | 1021 -------- arch/ppc/kernel/head_8xx.S | 959 ------- arch/ppc/kernel/head_booke.h | 308 --- arch/ppc/kernel/machine_kexec.c | 118 - arch/ppc/kernel/misc.S | 868 ------- arch/ppc/kernel/pci.c | 1233 --------- arch/ppc/kernel/ppc-stub.c | 866 ------- arch/ppc/kernel/ppc_htab.c | 464 ---- arch/ppc/kernel/ppc_ksyms.c | 258 -- arch/ppc/kernel/relocate_kernel.S | 123 - arch/ppc/kernel/setup.c | 572 ---- arch/ppc/kernel/smp-tbsync.c | 180 -- arch/ppc/kernel/smp.c | 414 --- arch/ppc/kernel/softemu8xx.c | 147 -- arch/ppc/kernel/time.c | 445 ---- arch/ppc/kernel/traps.c | 826 ------ arch/ppc/kernel/vmlinux.lds.S | 164 -- arch/ppc/lib/Makefile | 5 - arch/ppc/lib/checksum.S | 225 -- arch/ppc/lib/div64.S | 58 - arch/ppc/lib/locks.c | 189 -- arch/ppc/lib/string.S | 732 ------ arch/ppc/mm/44x_mmu.c | 101 - arch/ppc/mm/4xx_mmu.c | 135 - arch/ppc/mm/Makefile | 10 - arch/ppc/mm/fault.c | 436 ---- arch/ppc/mm/hashtable.S | 617 ----- arch/ppc/mm/init.c | 603 ----- arch/ppc/mm/mem_pieces.c | 162 -- arch/ppc/mm/mem_pieces.h | 48 - arch/ppc/mm/mmu_context.c | 85 - arch/ppc/mm/mmu_decl.h | 79 - arch/ppc/mm/pgtable.c | 403 --- arch/ppc/mm/ppc_mmu.c | 269 -- arch/ppc/mm/tlb.c | 183 -- arch/ppc/platforms/4xx/Kconfig | 285 -- arch/ppc/platforms/4xx/Makefile | 31 - arch/ppc/platforms/4xx/bamboo.c | 442 ---- arch/ppc/platforms/4xx/bamboo.h | 133 - arch/ppc/platforms/4xx/bubinga.c | 265 -- arch/ppc/platforms/4xx/bubinga.h | 54 - arch/ppc/platforms/4xx/cpci405.c | 201 -- arch/ppc/platforms/4xx/cpci405.h | 28 - arch/ppc/platforms/4xx/ebony.c | 334 --- arch/ppc/platforms/4xx/ebony.h | 97 - arch/ppc/platforms/4xx/ep405.c | 196 -- arch/ppc/platforms/4xx/ep405.h | 52 - arch/ppc/platforms/4xx/ibm405ep.c | 141 - arch/ppc/platforms/4xx/ibm405ep.h | 145 -- arch/ppc/platforms/4xx/ibm405gp.c | 120 - arch/ppc/platforms/4xx/ibm405gp.h | 148 -- arch/ppc/platforms/4xx/ibm405gpr.c | 115 - arch/ppc/platforms/4xx/ibm405gpr.h | 148 -- arch/ppc/platforms/4xx/ibm440ep.c | 220 -- arch/ppc/platforms/4xx/ibm440ep.h | 73 - arch/ppc/platforms/4xx/ibm440gp.c | 163 -- arch/ppc/platforms/4xx/ibm440gp.h | 63 - arch/ppc/platforms/4xx/ibm440gx.c | 231 -- arch/ppc/platforms/4xx/ibm440gx.h | 71 - arch/ppc/platforms/4xx/ibm440sp.c | 129 - arch/ppc/platforms/4xx/ibm440sp.h | 61 - arch/ppc/platforms/4xx/ibmnp405h.c | 170 -- arch/ppc/platforms/4xx/ibmnp405h.h | 154 -- arch/ppc/platforms/4xx/ibmstb4.c | 122 - arch/ppc/platforms/4xx/ibmstb4.h | 235 -- arch/ppc/platforms/4xx/ibmstbx25.c | 66 - arch/ppc/platforms/4xx/ibmstbx25.h | 258 -- arch/ppc/platforms/4xx/luan.c | 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include/asm-ppc/zorro.h (limited to 'include') diff --git a/arch/ppc/.gitignore b/arch/ppc/.gitignore deleted file mode 100644 index 1e79a0ae4473..000000000000 --- a/arch/ppc/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/include diff --git a/arch/ppc/4xx_io/Makefile b/arch/ppc/4xx_io/Makefile deleted file mode 100644 index 6a8cd575f382..000000000000 --- a/arch/ppc/4xx_io/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the linux MPC4xx ppc-specific parts -# - - -obj-$(CONFIG_SERIAL_SICC) += serial_sicc.o diff --git a/arch/ppc/4xx_io/serial_sicc.c b/arch/ppc/4xx_io/serial_sicc.c deleted file mode 100644 index efa0a56e230b..000000000000 --- a/arch/ppc/4xx_io/serial_sicc.c +++ /dev/null @@ -1,2005 +0,0 @@ -/* - * Driver for IBM STB3xxx SICC serial port - * - * Based on drivers/char/serial_amba.c, by ARM Ltd. - * - * Copyright 2001 IBM Corp. - * Author: IBM China Research Lab - * Yudong Yang - * Yi Ge - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * - * This is a driver for SICC serial port on IBM Redwood 4 evaluation board. - * The driver support both as a console device and normal serial device and - * is compatible with normal ttyS* devices. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - - -#include - - -/* ----------------------------------------------------------------------------- - * From STB03xxx SICC UART Specification - * ----------------------------------------------------------------------------- - * UART Register Offsets. - */ - -#define BL_SICC_LSR 0x0000000 /* line status register read/clear */ -#define BL_SICC_LSRS 0x0000001 /* set line status register read/set */ -#define BL_SICC_HSR 0x0000002 /* handshake status register r/clear */ -#define BL_SICC_HSRS 0x0000003 /* set handshake status register r/set */ -#define BL_SICC_BRDH 0x0000004 /* baudrate divisor high reg r/w */ -#define BL_SICC_BRDL 0x0000005 /* baudrate divisor low reg r/w */ -#define BL_SICC_LCR 0x0000006 /* control register r/w */ -#define BL_SICC_RCR 0x0000007 /* receiver command register r/w */ -#define BL_SICC_TxCR 0x0000008 /* transmitter command register r/w */ -#define BL_SICC_RBR 0x0000009 /* receive buffer r */ -#define BL_SICC_TBR 0x0000009 /* transmit buffer w */ -#define BL_SICC_CTL2 0x000000A /* added for Vesta */ -#define BL_SICC_IrCR 0x000000B /* added for Vesta IR */ - -/* masks and definitions for serial port control register */ - -#define _LCR_LM_MASK 0xc0 /* loop back modes */ -#define _LCR_DTR_MASK 0x20 /* data terminal ready 0-inactive */ -#define _LCR_RTS_MASK 0x10 /* request to send 0-inactive */ -#define _LCR_DB_MASK 0x08 /* data bits mask */ -#define _LCR_PE_MASK 0x04 /* parity enable */ -#define _LCR_PTY_MASK 0x02 /* parity */ -#define _LCR_SB_MASK 0x01 /* stop bit mask */ - -#define _LCR_LM_NORM 0x00 /* normal operation */ -#define _LCR_LM_LOOP 0x40 /* internal loopback mode */ -#define _LCR_LM_ECHO 0x80 /* automatic echo mode */ -#define _LCR_LM_RES 0xc0 /* reserved */ - -#define _LCR_DTR_ACTIVE _LCR_DTR_MASK /* DTR is active */ -#define _LCR_RTS_ACTIVE _LCR_RTS_MASK /* RTS is active */ -#define _LCR_DB_8_BITS _LCR_DB_MASK /* 8 data bits */ -#define _LCR_DB_7_BITS 0x00 /* 7 data bits */ -#define _LCR_PE_ENABLE _LCR_PE_MASK /* parity enabled */ -#define _LCR_PE_DISABLE 0x00 /* parity disabled */ -#define _LCR_PTY_EVEN 0x00 /* even parity */ -#define _LCR_PTY_ODD _LCR_PTY_MASK /* odd parity */ -#define _LCR_SB_1_BIT 0x00 /* one stop bit */ -#define _LCR_SB_2_BIT _LCR_SB_MASK /* two stop bit */ - -/* serial port handshake register */ - -#define _HSR_DIS_MASK 0x80 /* DSR input inactive error mask */ -#define _HSR_CS_MASK 0x40 /* CTS input inactive error mask */ -#define _HSR_DIS_ACT 0x00 /* dsr input is active */ -#define _HSR_DIS_INACT _HSR_DIS_MASK /* dsr input is inactive */ -#define _HSR_CS_ACT 0x00 /* cts input is active */ -#define _HSR_CS_INACT _HSR_CS_MASK /* cts input is active */ - -/* serial port line status register */ - -#define _LSR_RBR_MASK 0x80 /* receive buffer ready mask */ -#define _LSR_FE_MASK 0x40 /* framing error */ -#define _LSR_OE_MASK 0x20 /* overrun error */ -#define _LSR_PE_MASK 0x10 /* parity error */ -#define _LSR_LB_MASK 0x08 /* line break */ -#define _LSR_TBR_MASK 0x04 /* transmit buffer ready */ -#define _LSR_TSR_MASK 0x02 /* transmit shift register ready */ - -#define _LSR_RBR_FULL _LSR_RBR_MASK /* receive buffer is full */ -#define _LSR_FE_ERROR _LSR_FE_MASK /* framing error detected */ -#define _LSR_OE_ERROR _LSR_OE_MASK /* overrun error detected */ -#define _LSR_PE_ERROR _LSR_PE_MASK /* parity error detected */ -#define _LSR_LB_BREAK _LSR_LB_MASK /* line break detected */ -#define _LSR_TBR_EMPTY _LSR_TBR_MASK /* transmit buffer is ready */ -#define _LSR_TSR_EMPTY _LSR_TSR_MASK /* transmit shift register is empty */ -#define _LSR_TX_ALL 0x06 /* all physical transmit is done */ - -#define _LSR_RX_ERR (_LSR_LB_BREAK | _LSR_FE_MASK | _LSR_OE_MASK | \ - _LSR_PE_MASK ) - -/* serial port receiver command register */ - -#define _RCR_ER_MASK 0x80 /* enable receiver mask */ -#define _RCR_DME_MASK 0x60 /* dma mode */ -#define _RCR_EIE_MASK 0x10 /* error interrupt enable mask */ -#define _RCR_PME_MASK 0x08 /* pause mode mask */ - -#define _RCR_ER_ENABLE _RCR_ER_MASK /* receiver enabled */ -#define _RCR_DME_DISABLE 0x00 /* dma disabled */ -#define _RCR_DME_RXRDY 0x20 /* dma disabled, RxRDY interrupt enabled*/ -#define _RCR_DME_ENABLE2 0x40 /* dma enabled,receiver src channel 2 */ -#define _RCR_DME_ENABLE3 0x60 /* dma enabled,receiver src channel 3 */ -#define _RCR_PME_HARD _RCR_PME_MASK /* RTS controlled by hardware */ -#define _RCR_PME_SOFT 0x00 /* RTS controlled by software */ - -/* serial port transmit command register */ - -#define _TxCR_ET_MASK 0x80 /* transmitter enable mask */ -#define _TxCR_DME_MASK 0x60 /* dma mode mask */ -#define _TxCR_TIE_MASK 0x10 /* empty interrupt enable mask */ -#define _TxCR_EIE_MASK 0x08 /* error interrupt enable mask */ -#define _TxCR_SPE_MASK 0x04 /* stop/pause mask */ -#define _TxCR_TB_MASK 0x02 /* transmit break mask */ - -#define _TxCR_ET_ENABLE _TxCR_ET_MASK /* transmitter enabled */ -#define _TxCR_DME_DISABLE 0x00 /* transmitter disabled, TBR intr disabled */ -#define _TxCR_DME_TBR 0x20 /* transmitter disabled, TBR intr enabled */ -#define _TxCR_DME_CHAN_2 0x40 /* dma enabled, destination chann 2 */ -#define _TxCR_DME_CHAN_3 0x60 /* dma enabled, destination chann 3 */ - -/* serial ctl reg 2 - added for Vesta */ - -#define _CTL2_EXTERN 0x80 /* */ -#define _CTL2_USEFIFO 0x40 /* */ -#define _CTL2_RESETRF 0x08 /* */ -#define _CTL2_RESETTF 0x04 /* */ - - - -#define SERIAL_SICC_NAME "ttySICC" -#define SERIAL_SICC_MAJOR 150 -#define SERIAL_SICC_MINOR 1 -#define SERIAL_SICC_NR 1 - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -/* - * Things needed by tty driver - */ -static struct tty_driver *siccnormal_driver; - -#if defined(CONFIG_SERIAL_SICC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) -#define SUPPORT_SYSRQ -#endif - -/* - * Things needed internally to this driver - */ - -/* - * tmp_buf is used as a temporary buffer by serial_write. We need to - * lock it in case the copy_from_user blocks while swapping in a page, - * and some other program tries to do a serial write at the same time. - * Since the lock will only come under contention when the system is - * swapping and available memory is low, it makes sense to share one - * buffer across all the serial ports, since it significantly saves - * memory if large numbers of serial ports are open. - */ -static u_char *tmp_buf; - -#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) - -/* number of characters left in xmit buffer before we ask for more */ -#define WAKEUP_CHARS 256 -#define SICC_ISR_PASS_LIMIT 256 - -#define EVT_WRITE_WAKEUP 0 - -struct SICC_icount { - __u32 cts; - __u32 dsr; - __u32 rng; - __u32 dcd; - __u32 rx; - __u32 tx; - __u32 frame; - __u32 overrun; - __u32 parity; - __u32 brk; - __u32 buf_overrun; -}; - -/* - * Static information about the port - */ -struct SICC_port { - unsigned int uart_base; - unsigned int uart_base_phys; - unsigned int irqrx; - unsigned int irqtx; - unsigned int uartclk; - unsigned int fifosize; - unsigned int tiocm_support; - void (*set_mctrl)(struct SICC_port *, u_int mctrl); -}; - -/* - * This is the state information which is persistent across opens - */ -struct SICC_state { - struct SICC_icount icount; - unsigned int line; - unsigned int close_delay; - unsigned int closing_wait; - unsigned int custom_divisor; - unsigned int flags; - int count; - struct SICC_info *info; - spinlock_t sicc_lock; -}; - -#define SICC_XMIT_SIZE 1024 -/* - * This is the state information which is only valid when the port is open. - */ -struct SICC_info { - struct SICC_port *port; - struct SICC_state *state; - struct tty_struct *tty; - unsigned char x_char; - unsigned char old_status; - unsigned char read_status_mask; - unsigned char ignore_status_mask; - struct circ_buf xmit; - unsigned int flags; -#ifdef SUPPORT_SYSRQ - unsigned long sysrq; -#endif - - unsigned int event; - unsigned int timeout; - unsigned int lcr_h; - unsigned int mctrl; - int blocked_open; - - struct tasklet_struct tlet; - - wait_queue_head_t open_wait; - wait_queue_head_t close_wait; - wait_queue_head_t delta_msr_wait; -}; - -#ifdef CONFIG_SERIAL_SICC_CONSOLE -static struct console siccuart_cons; -#endif -static void siccuart_change_speed(struct SICC_info *info, struct termios *old_termios); -static void siccuart_wait_until_sent(struct tty_struct *tty, int timeout); - - - -static void powerpcMtcic_cr(unsigned long value) -{ - mtdcr(DCRN_CICCR, value); -} - -static unsigned long powerpcMfcic_cr(void) -{ - return mfdcr(DCRN_CICCR); -} - -static unsigned long powerpcMfclkgpcr(void) -{ - return mfdcr(DCRN_SCCR); -} - -static void sicc_set_mctrl_null(struct SICC_port *port, u_int mctrl) -{ -} - -static struct SICC_port sicc_ports[SERIAL_SICC_NR] = { - { - .uart_base = 0, - .uart_base_phys = SICC0_IO_BASE, - .irqrx = SICC0_INTRX, - .irqtx = SICC0_INTTX, -// .uartclk = 0, - .fifosize = 1, - .set_mctrl = sicc_set_mctrl_null, - } -}; - -static struct SICC_state sicc_state[SERIAL_SICC_NR]; - -static void siccuart_enable_rx_interrupt(struct SICC_info *info) -{ - unsigned char cr; - - cr = readb(info->port->uart_base+BL_SICC_RCR); - cr &= ~_RCR_DME_MASK; - cr |= _RCR_DME_RXRDY; - writeb(cr, info->port->uart_base+BL_SICC_RCR); -} - -static void siccuart_disable_rx_interrupt(struct SICC_info *info) -{ - unsigned char cr; - - cr = readb(info->port->uart_base+BL_SICC_RCR); - cr &= ~_RCR_DME_MASK; - cr |= _RCR_DME_DISABLE; - writeb(cr, info->port->uart_base+BL_SICC_RCR); -} - - -static void siccuart_enable_tx_interrupt(struct SICC_info *info) -{ - unsigned char cr; - - cr = readb(info->port->uart_base+BL_SICC_TxCR); - cr &= ~_TxCR_DME_MASK; - cr |= _TxCR_DME_TBR; - writeb(cr, info->port->uart_base+BL_SICC_TxCR); -} - -static void siccuart_disable_tx_interrupt(struct SICC_info *info) -{ - unsigned char cr; - - cr = readb(info->port->uart_base+BL_SICC_TxCR); - cr &= ~_TxCR_DME_MASK; - cr |= _TxCR_DME_DISABLE; - writeb(cr, info->port->uart_base+BL_SICC_TxCR); -} - - -static void siccuart_stop(struct tty_struct *tty) -{ - struct SICC_info *info = tty->driver_data; - unsigned long flags; - - /* disable interrupts while stopping serial port interrupts */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - siccuart_disable_tx_interrupt(info); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); -} - -static void siccuart_start(struct tty_struct *tty) -{ - struct SICC_info *info = tty->driver_data; - unsigned long flags; - - /* disable interrupts while starting serial port interrupts */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - if (info->xmit.head != info->xmit.tail - && info->xmit.buf) - siccuart_enable_tx_interrupt(info); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); -} - - -/* - * This routine is used by the interrupt handler to schedule - * processing in the software interrupt portion of the driver. - */ -static void siccuart_event(struct SICC_info *info, int event) -{ - info->event |= 1 << event; - tasklet_schedule(&info->tlet); -} - -static void -siccuart_rx_chars(struct SICC_info *info) -{ - struct tty_struct *tty = info->tty; - unsigned int status, ch, rsr, flg, ignored = 0; - struct SICC_icount *icount = &info->state->icount; - struct SICC_port *port = info->port; - - status = readb(port->uart_base+BL_SICC_LSR ); - while (status & _LSR_RBR_FULL) { - ch = readb(port->uart_base+BL_SICC_RBR); - - if (tty->flip.count >= TTY_FLIPBUF_SIZE) - goto ignore_char; - icount->rx++; - - flg = TTY_NORMAL; - - /* - * Note that the error handling code is - * out of the main execution path - */ - rsr = readb(port->uart_base+BL_SICC_LSR); - if (rsr & _LSR_RX_ERR) - goto handle_error; -#ifdef SUPPORT_SYSRQ - if (info->sysrq) { - if (ch && time_before(jiffies, info->sysrq)) { - handle_sysrq(ch, NULL); - info->sysrq = 0; - goto ignore_char; - } - info->sysrq = 0; - } -#endif - error_return: - *tty->flip.flag_buf_ptr++ = flg; - *tty->flip.char_buf_ptr++ = ch; - tty->flip.count++; - ignore_char: - status = readb(port->uart_base+BL_SICC_LSR ); - } -out: - tty_flip_buffer_push(tty); - return; - -handle_error: - if (rsr & _LSR_LB_BREAK) { - rsr &= ~(_LSR_FE_MASK | _LSR_PE_MASK); - icount->brk++; - -#ifdef SUPPORT_SYSRQ - if (info->state->line == siccuart_cons.index) { - if (!info->sysrq) { - info->sysrq = jiffies + HZ*5; - goto ignore_char; - } - } -#endif - } else if (rsr & _LSR_PE_MASK) - icount->parity++; - else if (rsr & _LSR_FE_MASK) - icount->frame++; - if (rsr & _LSR_OE_MASK) - icount->overrun++; - - if (rsr & info->ignore_status_mask) { - if (++ignored > 100) - goto out; - goto ignore_char; - } - rsr &= info->read_status_mask; - - if (rsr & _LSR_LB_BREAK) - flg = TTY_BREAK; - else if (rsr & _LSR_PE_MASK) - flg = TTY_PARITY; - else if (rsr & _LSR_FE_MASK) - flg = TTY_FRAME; - - if (rsr & _LSR_OE_MASK) { - /* - * CHECK: does overrun affect the current character? - * ASSUMPTION: it does not. - */ - *tty->flip.flag_buf_ptr++ = flg; - *tty->flip.char_buf_ptr++ = ch; - tty->flip.count++; - if (tty->flip.count >= TTY_FLIPBUF_SIZE) - goto ignore_char; - ch = 0; - flg = TTY_OVERRUN; - } -#ifdef SUPPORT_SYSRQ - info->sysrq = 0; -#endif - goto error_return; -} - -static void siccuart_tx_chars(struct SICC_info *info) -{ - struct SICC_port *port = info->port; - int count; - unsigned char status; - - - if (info->x_char) { - writeb(info->x_char, port->uart_base+ BL_SICC_TBR); - info->state->icount.tx++; - info->x_char = 0; - return; - } - if (info->xmit.head == info->xmit.tail - || info->tty->stopped - || info->tty->hw_stopped) { - siccuart_disable_tx_interrupt(info); - writeb(status&(~_LSR_RBR_MASK),port->uart_base+BL_SICC_LSR); - return; - } - - count = port->fifosize; - do { - writeb(info->xmit.buf[info->xmit.tail], port->uart_base+ BL_SICC_TBR); - info->xmit.tail = (info->xmit.tail + 1) & (SICC_XMIT_SIZE - 1); - info->state->icount.tx++; - if (info->xmit.head == info->xmit.tail) - break; - } while (--count > 0); - - if (CIRC_CNT(info->xmit.head, - info->xmit.tail, - SICC_XMIT_SIZE) < WAKEUP_CHARS) - siccuart_event(info, EVT_WRITE_WAKEUP); - - if (info->xmit.head == info->xmit.tail) { - siccuart_disable_tx_interrupt(info); - } -} - - -static irqreturn_t siccuart_int_rx(int irq, void *dev_id) -{ - struct SICC_info *info = dev_id; - siccuart_rx_chars(info) - return IRQ_HANDLED; -} - - -static irqreturn_t siccuart_int_tx(int irq, void *dev_id) -{ - struct SICC_info *info = dev_id; - siccuart_tx_chars(info); - return IRQ_HANDLED; -} - -static void siccuart_tasklet_action(unsigned long data) -{ - struct SICC_info *info = (struct SICC_info *)data; - struct tty_struct *tty; - - tty = info->tty; - if (!tty || !test_and_clear_bit(EVT_WRITE_WAKEUP, &info->event)) - return; - - if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && - tty->ldisc.write_wakeup) - (tty->ldisc.write_wakeup)(tty); - wake_up_interruptible(&tty->write_wait); -} - -static int siccuart_startup(struct SICC_info *info) -{ - unsigned long flags; - unsigned long page; - int retval = 0; - - if (info->flags & ASYNC_INITIALIZED) { - return 0; - } - - page = get_zeroed_page(GFP_KERNEL); - if (!page) - return -ENOMEM; - - if (info->port->uart_base == 0) - info->port->uart_base = (int)ioremap(info->port->uart_base_phys, PAGE_SIZE); - if (info->port->uart_base == 0) { - free_page(page); - return -ENOMEM; - } - - /* lock access to info while doing setup */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - - if (info->xmit.buf) - free_page(page); - else - info->xmit.buf = (unsigned char *) page; - - - info->mctrl = 0; - if (info->tty->termios->c_cflag & CBAUD) - info->mctrl = TIOCM_RTS | TIOCM_DTR; - info->port->set_mctrl(info->port, info->mctrl); - - /* - * initialise the old status of the modem signals - */ - info->old_status = 0; // UART_GET_FR(info->port) & AMBA_UARTFR_MODEM_ANY; - - - if (info->tty) - clear_bit(TTY_IO_ERROR, &info->tty->flags); - info->xmit.head = info->xmit.tail = 0; - - /* - * Set up the tty->alt_speed kludge - */ - if (info->tty) { - if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) - info->tty->alt_speed = 57600; - if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) - info->tty->alt_speed = 115200; - if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) - info->tty->alt_speed = 230400; - if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) - info->tty->alt_speed = 460800; - } - - - writeb( 0x00, info->port->uart_base + BL_SICC_IrCR ); // disable IrDA - - - /* - * and set the speed of the serial port - */ - siccuart_change_speed(info, 0); - - // enable rx/tx ports - writeb(_RCR_ER_ENABLE /*| _RCR_PME_HARD*/, info->port->uart_base + BL_SICC_RCR); - writeb(_TxCR_ET_ENABLE , info->port->uart_base + BL_SICC_TxCR); - - readb(info->port->uart_base + BL_SICC_RBR); // clear rx port - - writeb(0xf8, info->port->uart_base + BL_SICC_LSR); /* reset bits 0-4 of LSR */ - - /* - * Finally, enable interrupts - */ - - /* - * Allocate the IRQ - */ - retval = request_irq(info->port->irqrx, siccuart_int_rx, 0, "SICC rx", info); - if (retval) { - if (capable(CAP_SYS_ADMIN)) { - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - retval = 0; - } - goto errout; - } - retval = request_irq(info->port->irqtx, siccuart_int_tx, 0, "SICC tx", info); - if (retval) { - if (capable(CAP_SYS_ADMIN)) { - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - retval = 0; - } - free_irq(info->port->irqrx, info); - goto errout; - } - - siccuart_enable_rx_interrupt(info); - - info->flags |= ASYNC_INITIALIZED; - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - return 0; - - -errout: - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - return retval; -} - -/* - * This routine will shutdown a serial port; interrupts are disabled, and - * DTR is dropped if the hangup on close termio flag is on. - */ -static void siccuart_shutdown(struct SICC_info *info) -{ - unsigned long flags; - - if (!(info->flags & ASYNC_INITIALIZED)) - return; - - /* lock while shutting down port */ - spin_lock_irqsave(&info->state->sicc_lock,flags); /* Disable interrupts */ - - /* - * clear delta_msr_wait queue to avoid mem leaks: we may free the irq - * here so the queue might never be woken up - */ - wake_up_interruptible(&info->delta_msr_wait); - - /* - * disable all interrupts, disable the port - */ - siccuart_disable_rx_interrupt(info); - siccuart_disable_tx_interrupt(info); - - /* - * Free the IRQ - */ - free_irq(info->port->irqtx, info); - free_irq(info->port->irqrx, info); - - if (info->xmit.buf) { - unsigned long pg = (unsigned long) info->xmit.buf; - info->xmit.buf = NULL; - free_page(pg); - } - - - if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) - info->mctrl &= ~(TIOCM_DTR|TIOCM_RTS); - info->port->set_mctrl(info->port, info->mctrl); - - /* kill off our tasklet */ - tasklet_kill(&info->tlet); - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - - info->flags &= ~ASYNC_INITIALIZED; - - spin_unlock_irqrestore(&info->state->sicc_lock,flags); -} - - -static void siccuart_change_speed(struct SICC_info *info, struct termios *old_termios) -{ - unsigned int lcr_h, baud, quot, cflag, old_rcr, old_tcr, bits; - unsigned long flags; - - if (!info->tty || !info->tty->termios) - return; - - cflag = info->tty->termios->c_cflag; - - pr_debug("siccuart_set_cflag(0x%x) called\n", cflag); - /* byte size and parity */ - switch (cflag & CSIZE) { - case CS7: lcr_h = _LCR_PE_DISABLE | _LCR_DB_7_BITS | _LCR_SB_1_BIT; bits = 9; break; - default: lcr_h = _LCR_PE_DISABLE | _LCR_DB_8_BITS | _LCR_SB_1_BIT; bits = 10; break; // CS8 - } - if (cflag & CSTOPB) { - lcr_h |= _LCR_SB_2_BIT; - bits ++; - } - if (cflag & PARENB) { - lcr_h |= _LCR_PE_ENABLE; - bits++; - if (!(cflag & PARODD)) - lcr_h |= _LCR_PTY_ODD; - else - lcr_h |= _LCR_PTY_EVEN; - } - - do { - /* Determine divisor based on baud rate */ - baud = tty_get_baud_rate(info->tty); - if (!baud) - baud = 9600; - - - { - // here is ppc403SetBaud(com_port, baud); - unsigned long divisor, clockSource, temp; - - /* Ensure CICCR[7] is 0 to select Internal Baud Clock */ - powerpcMtcic_cr((unsigned long)(powerpcMfcic_cr() & 0xFEFFFFFF)); - - /* Determine Internal Baud Clock Frequency */ - /* powerpcMfclkgpcr() reads DCR 0x120 - the*/ - /* SCCR (Serial Clock Control Register) on Vesta */ - temp = powerpcMfclkgpcr(); - - if(temp & 0x00000080) { - clockSource = 324000000; - } - else { - clockSource = 216000000; - } - clockSource = clockSource/(unsigned long)((temp&0x00FC0000)>>18); - divisor = clockSource/(16*baud) - 1; - /* divisor has only 12 bits of resolution */ - if(divisor>0x00000FFF){ - divisor=0x00000FFF; - } - - quot = divisor; - } - - if (baud == 38400 && - ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) - quot = info->state->custom_divisor; - - if (!quot && old_termios) { - info->tty->termios->c_cflag &= ~CBAUD; - info->tty->termios->c_cflag |= (old_termios->c_cflag & CBAUD); - old_termios = NULL; - } - } while (quot == 0 && old_termios); - - /* As a last resort, if the quotient is zero, default to 9600 bps */ - if (!quot) - quot = (info->port->uartclk / (16 * 9600)) - 1; - - info->timeout = info->port->fifosize * HZ * bits / baud; - info->timeout += HZ/50; /* Add .02 seconds of slop */ - - if (cflag & CRTSCTS) - info->flags |= ASYNC_CTS_FLOW; - else - info->flags &= ~ASYNC_CTS_FLOW; - if (cflag & CLOCAL) - info->flags &= ~ASYNC_CHECK_CD; - else - info->flags |= ASYNC_CHECK_CD; - - /* - * Set up parity check flag - */ -#define RELEVENT_IFLAG(iflag) ((iflag) & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) - - info->read_status_mask = _LSR_OE_MASK; - if (I_INPCK(info->tty)) - info->read_status_mask |= _LSR_FE_MASK | _LSR_PE_MASK; - if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) - info->read_status_mask |= _LSR_LB_MASK; - - /* - * Characters to ignore - */ - info->ignore_status_mask = 0; - if (I_IGNPAR(info->tty)) - info->ignore_status_mask |= _LSR_FE_MASK | _LSR_PE_MASK; - if (I_IGNBRK(info->tty)) { - info->ignore_status_mask |= _LSR_LB_MASK; - /* - * If we're ignoring parity and break indicators, - * ignore overruns to (for real raw support). - */ - if (I_IGNPAR(info->tty)) - info->ignore_status_mask |= _LSR_OE_MASK; - } - - /* disable interrupts while reading and clearing registers */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - - old_rcr = readb(info->port->uart_base + BL_SICC_RCR); - old_tcr = readb(info->port->uart_base + BL_SICC_TxCR); - - - writeb(0, info->port->uart_base + BL_SICC_RCR); - writeb(0, info->port->uart_base + BL_SICC_TxCR); - - /*RLBtrace (&ppc403Chan0, 0x2000000c, 0, 0);*/ - - - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - - - /* Set baud rate */ - writeb((quot & 0x00000F00)>>8, info->port->uart_base + BL_SICC_BRDH ); - writeb( quot & 0x00000FF, info->port->uart_base + BL_SICC_BRDL ); - - /* Set CTL2 reg to use external clock (ExtClk) and enable FIFOs. */ - /* For now, do NOT use FIFOs since 403 UART did not have this */ - /* capability and this driver was inherited from 403UART. */ - writeb(_CTL2_EXTERN, info->port->uart_base + BL_SICC_CTL2); - - writeb(lcr_h, info->port->uart_base + BL_SICC_LCR); - - writeb(old_rcr, info->port->uart_base + BL_SICC_RCR); // restore rcr - writeb(old_tcr, info->port->uart_base + BL_SICC_TxCR); // restore txcr - -} - - -static void siccuart_put_char(struct tty_struct *tty, u_char ch) -{ - struct SICC_info *info = tty->driver_data; - unsigned long flags; - - if (!tty || !info->xmit.buf) - return; - - /* lock info->xmit while adding character to tx buffer */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - if (CIRC_SPACE(info->xmit.head, info->xmit.tail, SICC_XMIT_SIZE) != 0) { - info->xmit.buf[info->xmit.head] = ch; - info->xmit.head = (info->xmit.head + 1) & (SICC_XMIT_SIZE - 1); - } - spin_unlock_irqrestore(&info->state->sicc_lock,flags); -} - -static void siccuart_flush_chars(struct tty_struct *tty) -{ - struct SICC_info *info = tty->driver_data; - unsigned long flags; - - if (info->xmit.head == info->xmit.tail - || tty->stopped - || tty->hw_stopped - || !info->xmit.buf) - return; - - /* disable interrupts while transmitting characters */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - siccuart_enable_tx_interrupt(info); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); -} - -static int siccuart_write(struct tty_struct *tty, - const u_char * buf, int count) -{ - struct SICC_info *info = tty->driver_data; - unsigned long flags; - int c, ret = 0; - - if (!tty || !info->xmit.buf || !tmp_buf) - return 0; - - /* lock info->xmit while removing characters from buffer */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - while (1) { - c = CIRC_SPACE_TO_END(info->xmit.head, - info->xmit.tail, - SICC_XMIT_SIZE); - if (count < c) - c = count; - if (c <= 0) - break; - memcpy(info->xmit.buf + info->xmit.head, buf, c); - info->xmit.head = (info->xmit.head + c) & - (SICC_XMIT_SIZE - 1); - buf += c; - count -= c; - ret += c; - } - if (info->xmit.head != info->xmit.tail - && !tty->stopped - && !tty->hw_stopped) - siccuart_enable_tx_interrupt(info); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - return ret; -} - -static int siccuart_write_room(struct tty_struct *tty) -{ - struct SICC_info *info = tty->driver_data; - - return CIRC_SPACE(info->xmit.head, info->xmit.tail, SICC_XMIT_SIZE); -} - -static int siccuart_chars_in_buffer(struct tty_struct *tty) -{ - struct SICC_info *info = tty->driver_data; - - return CIRC_CNT(info->xmit.head, info->xmit.tail, SICC_XMIT_SIZE); -} - -static void siccuart_flush_buffer(struct tty_struct *tty) -{ - struct SICC_info *info = tty->driver_data; - unsigned long flags; - - pr_debug("siccuart_flush_buffer(%d) called\n", tty->index); - /* lock info->xmit while zeroing buffer counts */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - info->xmit.head = info->xmit.tail = 0; - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - wake_up_interruptible(&tty->write_wait); - if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && - tty->ldisc.write_wakeup) - (tty->ldisc.write_wakeup)(tty); -} - -/* - * This function is used to send a high-priority XON/XOFF character to - * the device - */ -static void siccuart_send_xchar(struct tty_struct *tty, char ch) -{ - struct SICC_info *info = tty->driver_data; - - info->x_char = ch; - if (ch) - siccuart_enable_tx_interrupt(info); -} - -static void siccuart_throttle(struct tty_struct *tty) -{ - struct SICC_info *info = tty->driver_data; - unsigned long flags; - - if (I_IXOFF(tty)) - siccuart_send_xchar(tty, STOP_CHAR(tty)); - - if (tty->termios->c_cflag & CRTSCTS) { - /* disable interrupts while setting modem control lines */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - info->mctrl &= ~TIOCM_RTS; - info->port->set_mctrl(info->port, info->mctrl); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - } -} - -static void siccuart_unthrottle(struct tty_struct *tty) -{ - struct SICC_info *info = (struct SICC_info *) tty->driver_data; - unsigned long flags; - - if (I_IXOFF(tty)) { - if (info->x_char) - info->x_char = 0; - else - siccuart_send_xchar(tty, START_CHAR(tty)); - } - - if (tty->termios->c_cflag & CRTSCTS) { - /* disable interrupts while setting modem control lines */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - info->mctrl |= TIOCM_RTS; - info->port->set_mctrl(info->port, info->mctrl); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - } -} - -static int get_serial_info(struct SICC_info *info, struct serial_struct *retinfo) -{ - struct SICC_state *state = info->state; - struct SICC_port *port = info->port; - struct serial_struct tmp; - - memset(&tmp, 0, sizeof(tmp)); - tmp.type = 0; - tmp.line = state->line; - tmp.port = port->uart_base; - if (HIGH_BITS_OFFSET) - tmp.port_high = port->uart_base >> HIGH_BITS_OFFSET; - tmp.irq = port->irqrx; - tmp.flags = 0; - tmp.xmit_fifo_size = port->fifosize; - tmp.baud_base = port->uartclk / 16; - tmp.close_delay = state->close_delay; - tmp.closing_wait = state->closing_wait; - tmp.custom_divisor = state->custom_divisor; - - if (copy_to_user(retinfo, &tmp, sizeof(*retinfo))) - return -EFAULT; - return 0; -} - -static int set_serial_info(struct SICC_info *info, - struct serial_struct *newinfo) -{ - struct serial_struct new_serial; - struct SICC_state *state, old_state; - struct SICC_port *port; - unsigned long new_port; - unsigned int i, change_irq, change_port; - int retval = 0; - - if (copy_from_user(&new_serial, newinfo, sizeof(new_serial))) - return -EFAULT; - - state = info->state; - old_state = *state; - port = info->port; - - new_port = new_serial.port; - if (HIGH_BITS_OFFSET) - new_port += (unsigned long) new_serial.port_high << HIGH_BITS_OFFSET; - - change_irq = new_serial.irq != port->irqrx; - change_port = new_port != port->uart_base; - - if (!capable(CAP_SYS_ADMIN)) { - if (change_irq || change_port || - (new_serial.baud_base != port->uartclk / 16) || - (new_serial.close_delay != state->close_delay) || - (new_serial.xmit_fifo_size != port->fifosize) || - ((new_serial.flags & ~ASYNC_USR_MASK) != - (state->flags & ~ASYNC_USR_MASK))) - return -EPERM; - state->flags = ((state->flags & ~ASYNC_USR_MASK) | - (new_serial.flags & ASYNC_USR_MASK)); - info->flags = ((info->flags & ~ASYNC_USR_MASK) | - (new_serial.flags & ASYNC_USR_MASK)); - state->custom_divisor = new_serial.custom_divisor; - goto check_and_exit; - } - - if ((new_serial.irq >= NR_IRQS) || (new_serial.irq < 0) || - (new_serial.baud_base < 9600)) - return -EINVAL; - - if (new_serial.type && change_port) { - for (i = 0; i < SERIAL_SICC_NR; i++) - if ((port != sicc_ports + i) && - sicc_ports[i].uart_base != new_port) - return -EADDRINUSE; - } - - if ((change_port || change_irq) && (state->count > 1)) - return -EBUSY; - - /* - * OK, past this point, all the error checking has been done. - * At this point, we start making changes..... - */ - port->uartclk = new_serial.baud_base * 16; - state->flags = ((state->flags & ~ASYNC_FLAGS) | - (new_serial.flags & ASYNC_FLAGS)); - info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) | - (info->flags & ASYNC_INTERNAL_FLAGS)); - state->custom_divisor = new_serial.custom_divisor; - state->close_delay = msecs_to_jiffies(10 * new_serial.close_delay); - state->closing_wait = msecs_to_jiffies(10 * new_serial.closing_wait); - info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; - port->fifosize = new_serial.xmit_fifo_size; - - if (change_port || change_irq) { - /* - * We need to shutdown the serial port at the old - * port/irq combination. - */ - siccuart_shutdown(info); - port->irqrx = new_serial.irq; - port->uart_base = new_port; - } - -check_and_exit: - if (!port->uart_base) - return 0; - if (info->flags & ASYNC_INITIALIZED) { - if ((old_state.flags & ASYNC_SPD_MASK) != - (state->flags & ASYNC_SPD_MASK) || - (old_state.custom_divisor != state->custom_divisor)) { - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) - info->tty->alt_speed = 57600; - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) - info->tty->alt_speed = 115200; - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) - info->tty->alt_speed = 230400; - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) - info->tty->alt_speed = 460800; - siccuart_change_speed(info, NULL); - } - } else - retval = siccuart_startup(info); - return retval; -} - - -/* - * get_lsr_info - get line status register info - */ -static int get_lsr_info(struct SICC_info *info, unsigned int *value) -{ - unsigned int result, status; - unsigned long flags; - - /* disable interrupts while reading status from port */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - status = readb(info->port->uart_base + BL_SICC_LSR); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - result = status & _LSR_TSR_EMPTY ? TIOCSER_TEMT : 0; - - /* - * If we're about to load something into the transmit - * register, we'll pretend the transmitter isn't empty to - * avoid a race condition (depending on when the transmit - * interrupt happens). - */ - if (info->x_char || - ((CIRC_CNT(info->xmit.head, info->xmit.tail, - SICC_XMIT_SIZE) > 0) && - !info->tty->stopped && !info->tty->hw_stopped)) - result &= TIOCSER_TEMT; - - return put_user(result, value); -} - -static int get_modem_info(struct SICC_info *info, unsigned int *value) -{ - unsigned int result = info->mctrl; - - return put_user(result, value); -} - -static int set_modem_info(struct SICC_info *info, unsigned int cmd, - unsigned int *value) -{ - unsigned int arg, old; - unsigned long flags; - - if (get_user(arg, value)) - return -EFAULT; - - old = info->mctrl; - switch (cmd) { - case TIOCMBIS: - info->mctrl |= arg; - break; - - case TIOCMBIC: - info->mctrl &= ~arg; - break; - - case TIOCMSET: - info->mctrl = arg; - break; - - default: - return -EINVAL; - } - /* disable interrupts while setting modem control lines */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - if (old != info->mctrl) - info->port->set_mctrl(info->port, info->mctrl); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - return 0; -} - -static void siccuart_break_ctl(struct tty_struct *tty, int break_state) -{ - struct SICC_info *info = tty->driver_data; - unsigned long flags; - unsigned int lcr_h; - - - /* disable interrupts while setting break state */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - lcr_h = readb(info->port + BL_SICC_LSR); - if (break_state == -1) - lcr_h |= _LSR_LB_MASK; - else - lcr_h &= ~_LSR_LB_MASK; - writeb(lcr_h, info->port + BL_SICC_LSRS); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); -} - -static int siccuart_ioctl(struct tty_struct *tty, struct file *file, - unsigned int cmd, unsigned long arg) -{ - struct SICC_info *info = tty->driver_data; - struct SICC_icount cnow; - struct serial_icounter_struct icount; - unsigned long flags; - - if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && - (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) && - (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { - if (tty->flags & (1 << TTY_IO_ERROR)) - return -EIO; - } - - switch (cmd) { - case TIOCMGET: - return get_modem_info(info, (unsigned int *)arg); - case TIOCMBIS: - case TIOCMBIC: - case TIOCMSET: - return set_modem_info(info, cmd, (unsigned int *)arg); - case TIOCGSERIAL: - return get_serial_info(info, - (struct serial_struct *)arg); - case TIOCSSERIAL: - return set_serial_info(info, - (struct serial_struct *)arg); - case TIOCSERGETLSR: /* Get line status register */ - return get_lsr_info(info, (unsigned int *)arg); - /* - * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change - * - mask passed in arg for lines of interest - * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) - * Caller should use TIOCGICOUNT to see which one it was - */ - case TIOCMIWAIT: - return 0; - /* - * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) - * Return: write counters to the user passed counter struct - * NB: both 1->0 and 0->1 transitions are counted except for - * RI where only 0->1 is counted. - */ - case TIOCGICOUNT: - /* disable interrupts while getting interrupt count */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - cnow = info->state->icount; - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - icount.cts = cnow.cts; - icount.dsr = cnow.dsr; - icount.rng = cnow.rng; - icount.dcd = cnow.dcd; - icount.rx = cnow.rx; - icount.tx = cnow.tx; - icount.frame = cnow.frame; - icount.overrun = cnow.overrun; - icount.parity = cnow.parity; - icount.brk = cnow.brk; - icount.buf_overrun = cnow.buf_overrun; - - return copy_to_user((void *)arg, &icount, sizeof(icount)) - ? -EFAULT : 0; - - default: - return -ENOIOCTLCMD; - } - return 0; -} - -static void siccuart_set_termios(struct tty_struct *tty, struct termios *old_termios) -{ - struct SICC_info *info = tty->driver_data; - unsigned long flags; - unsigned int cflag = tty->termios->c_cflag; - - if ((cflag ^ old_termios->c_cflag) == 0 && - RELEVENT_IFLAG(tty->termios->c_iflag ^ old_termios->c_iflag) == 0) - return; - - siccuart_change_speed(info, old_termios); - - /* Handle transition to B0 status */ - if ((old_termios->c_cflag & CBAUD) && - !(cflag & CBAUD)) { - /* disable interrupts while setting break state */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - info->mctrl &= ~(TIOCM_RTS | TIOCM_DTR); - info->port->set_mctrl(info->port, info->mctrl); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - } - - /* Handle transition away from B0 status */ - if (!(old_termios->c_cflag & CBAUD) && - (cflag & CBAUD)) { - /* disable interrupts while setting break state */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - info->mctrl |= TIOCM_DTR; - if (!(cflag & CRTSCTS) || - !test_bit(TTY_THROTTLED, &tty->flags)) - info->mctrl |= TIOCM_RTS; - info->port->set_mctrl(info->port, info->mctrl); - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - } - - /* Handle turning off CRTSCTS */ - if ((old_termios->c_cflag & CRTSCTS) && - !(cflag & CRTSCTS)) { - tty->hw_stopped = 0; - siccuart_start(tty); - } - -#if 0 - /* - * No need to wake up processes in open wait, since they - * sample the CLOCAL flag once, and don't recheck it. - * XXX It's not clear whether the current behavior is correct - * or not. Hence, this may change..... - */ - if (!(old_termios->c_cflag & CLOCAL) && - (tty->termios->c_cflag & CLOCAL)) - wake_up_interruptible(&info->open_wait); -#endif -} - -static void siccuart_close(struct tty_struct *tty, struct file *filp) -{ - struct SICC_info *info = tty->driver_data; - struct SICC_state *state; - unsigned long flags; - - if (!info) - return; - - state = info->state; - - //pr_debug("siccuart_close() called\n"); - - /* lock tty->driver_data while closing port */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - - if (tty_hung_up_p(filp)) { - goto quick_close; - } - - if ((tty->count == 1) && (state->count != 1)) { - /* - * Uh, oh. tty->count is 1, which means that the tty - * structure will be freed. state->count should always - * be one in these conditions. If it's greater than - * one, we've got real problems, since it means the - * serial port won't be shutdown. - */ - printk("siccuart_close: bad serial port count; tty->count is 1, state->count is %d\n", state->count); - state->count = 1; - } - if (--state->count < 0) { - printk("rs_close: bad serial port count for %s: %d\n", tty->name, state->count); - state->count = 0; - } - if (state->count) { - goto quick_close; - } - info->flags |= ASYNC_CLOSING; - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - /* - * Now we wait for the transmit buffer to clear; and we notify - * the line discipline to only process XON/XOFF characters. - */ - tty->closing = 1; - if (info->state->closing_wait != ASYNC_CLOSING_WAIT_NONE) - tty_wait_until_sent(tty, info->state->closing_wait); - /* - * At this point, we stop accepting input. To do this, we - * disable the receive line status interrupts. - */ - if (info->flags & ASYNC_INITIALIZED) { - siccuart_disable_rx_interrupt(info); - /* - * Before we drop DTR, make sure the UART transmitter - * has completely drained; this is especially - * important if there is a transmit FIFO! - */ - siccuart_wait_until_sent(tty, info->timeout); - } - siccuart_shutdown(info); - if (tty->driver->flush_buffer) - tty->driver->flush_buffer(tty); - if (tty->ldisc.flush_buffer) - tty->ldisc.flush_buffer(tty); - tty->closing = 0; - info->event = 0; - info->tty = NULL; - if (info->blocked_open) { - if (info->state->close_delay) - schedule_timeout_interruptible(info->state->close_delay); - wake_up_interruptible(&info->open_wait); - } - info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); - wake_up_interruptible(&info->close_wait); - return; - -quick_close: - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - return; -} - -static void siccuart_wait_until_sent(struct tty_struct *tty, int timeout) -{ - struct SICC_info *info = (struct SICC_info *) tty->driver_data; - unsigned long char_time, expire; - - if (info->port->fifosize == 0) - return; - - /* - * Set the check interval to be 1/5 of the estimated time to - * send a single character, and make it at least 1. The check - * interval should also be less than the timeout. - * - * Note: we have to use pretty tight timings here to satisfy - * the NIST-PCTS. - */ - char_time = (info->timeout - msecs_to_jiffies(20)) / info->port->fifosize; - char_time = char_time / 5; - if (char_time == 0) - char_time = 1; - - // Crazy!! sometimes the input arg 'timeout' can be negtive numbers :-( - if (timeout >= 0 && timeout < char_time) - char_time = timeout; - /* - * If the transmitter hasn't cleared in twice the approximate - * amount of time to send the entire FIFO, it probably won't - * ever clear. This assumes the UART isn't doing flow - * control, which is currently the case. Hence, if it ever - * takes longer than info->timeout, this is probably due to a - * UART bug of some kind. So, we clamp the timeout parameter at - * 2*info->timeout. - */ - if (!timeout || timeout > 2 * info->timeout) - timeout = 2 * info->timeout; - - expire = jiffies + timeout; - pr_debug("siccuart_wait_until_sent(%d), jiff=%lu, expire=%lu char_time=%lu...\n", - tty->index, jiffies, - expire, char_time); - while ((readb(info->port->uart_base + BL_SICC_LSR) & _LSR_TX_ALL) != _LSR_TX_ALL) { - schedule_timeout_interruptible(char_time); - if (signal_pending(current)) - break; - if (timeout && time_after(jiffies, expire)) - break; - } - set_current_state(TASK_RUNNING); -} - -static void siccuart_hangup(struct tty_struct *tty) -{ - struct SICC_info *info = tty->driver_data; - struct SICC_state *state = info->state; - - siccuart_flush_buffer(tty); - if (info->flags & ASYNC_CLOSING) - return; - siccuart_shutdown(info); - info->event = 0; - state->count = 0; - info->flags &= ~ASYNC_NORMAL_ACTIVE; - info->tty = NULL; - wake_up_interruptible(&info->open_wait); -} - -static int block_til_ready(struct tty_struct *tty, struct file *filp, - struct SICC_info *info) -{ - DECLARE_WAITQUEUE(wait, current); - struct SICC_state *state = info->state; - unsigned long flags; - int do_clocal = 0, extra_count = 0, retval; - - /* - * If the device is in the middle of being closed, then block - * until it's done, and then try again. - */ - if (tty_hung_up_p(filp) || - (info->flags & ASYNC_CLOSING)) { - if (info->flags & ASYNC_CLOSING) - interruptible_sleep_on(&info->close_wait); - return (info->flags & ASYNC_HUP_NOTIFY) ? - -EAGAIN : -ERESTARTSYS; - } - - /* - * If non-blocking mode is set, or the port is not enabled, - * then make the check up front and then exit. - */ - if ((filp->f_flags & O_NONBLOCK) || - (tty->flags & (1 << TTY_IO_ERROR))) { - info->flags |= ASYNC_NORMAL_ACTIVE; - return 0; - } - - if (tty->termios->c_cflag & CLOCAL) - do_clocal = 1; - - /* - * Block waiting for the carrier detect and the line to become - * free (i.e., not in use by the callout). While we are in - * this loop, state->count is dropped by one, so that - * rs_close() knows when to free things. We restore it upon - * exit, either normal or abnormal. - */ - retval = 0; - add_wait_queue(&info->open_wait, &wait); - /* lock while decrementing state->count */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - if (!tty_hung_up_p(filp)) { - extra_count = 1; - state->count--; - } - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - info->blocked_open++; - while (1) { - /* disable interrupts while setting modem control lines */ - spin_lock_irqsave(&info->state->sicc_lock,flags); - if (tty->termios->c_cflag & CBAUD) { - info->mctrl = TIOCM_DTR | TIOCM_RTS; - info->port->set_mctrl(info->port, info->mctrl); - } - spin_unlock_irqrestore(&info->state->sicc_lock,flags); - set_current_state(TASK_INTERRUPTIBLE); - if (tty_hung_up_p(filp) || - !(info->flags & ASYNC_INITIALIZED)) { - if (info->flags & ASYNC_HUP_NOTIFY) - retval = -EAGAIN; - else - retval = -ERESTARTSYS; - break; - } - if (!(info->flags & ASYNC_CLOSING) && - (do_clocal /*|| (UART_GET_FR(info->port) & SICC_UARTFR_DCD)*/)) - break; - if (signal_pending(current)) { - retval = -ERESTARTSYS; - break; - } - schedule(); - } - set_current_state(TASK_RUNNING); - remove_wait_queue(&info->open_wait, &wait); - if (extra_count) - state->count++; - info->blocked_open--; - if (retval) - return retval; - info->flags |= ASYNC_NORMAL_ACTIVE; - return 0; -} - -static struct SICC_info *siccuart_get(int line) -{ - struct SICC_info *info; - struct SICC_state *state = sicc_state + line; - - state->count++; - if (state->info) - return state->info; - info = kzalloc(sizeof(struct SICC_info), GFP_KERNEL); - if (info) { - init_waitqueue_head(&info->open_wait); - init_waitqueue_head(&info->close_wait); - init_waitqueue_head(&info->delta_msr_wait); - info->flags = state->flags; - info->state = state; - info->port = sicc_ports + line; - tasklet_init(&info->tlet, siccuart_tasklet_action, - (unsigned long)info); - } - if (state->info) { - kfree(info); - return state->info; - } - state->info = info; - return info; -} - -static int siccuart_open(struct tty_struct *tty, struct file *filp) -{ - struct SICC_info *info; - int retval, line = tty->index; - - - // is this a line that we've got? - if (line >= SERIAL_SICC_NR) { - return -ENODEV; - } - - info = siccuart_get(line); - if (!info) - return -ENOMEM; - - tty->driver_data = info; - info->tty = tty; - info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; - - /* - * Make sure we have the temporary buffer allocated - */ - if (!tmp_buf) { - unsigned long page = get_zeroed_page(GFP_KERNEL); - if (tmp_buf) - free_page(page); - else if (!page) { - return -ENOMEM; - } - tmp_buf = (u_char *)page; - } - - /* - * If the port is in the middle of closing, bail out now. - */ - if (tty_hung_up_p(filp) || - (info->flags & ASYNC_CLOSING)) { - if (info->flags & ASYNC_CLOSING) - interruptible_sleep_on(&info->close_wait); - return -EAGAIN; - } - - /* - * Start up the serial port - */ - retval = siccuart_startup(info); - if (retval) { - return retval; - } - - retval = block_til_ready(tty, filp, info); - if (retval) { - return retval; - } - -#ifdef CONFIG_SERIAL_SICC_CONSOLE - if (siccuart_cons.cflag && siccuart_cons.index == line) { - tty->termios->c_cflag = siccuart_cons.cflag; - siccuart_cons.cflag = 0; - siccuart_change_speed(info, NULL); - } -#endif - return 0; -} - -static const struct tty_operations sicc_ops = { - .open = siccuart_open, - .close = siccuart_close, - .write = siccuart_write, - .put_char = siccuart_put_char, - .flush_chars = siccuart_flush_chars, - .write_room = siccuart_write_room, - .chars_in_buffer = siccuart_chars_in_buffer, - .flush_buffer = siccuart_flush_buffer, - .ioctl = siccuart_ioctl, - .throttle = siccuart_throttle, - .unthrottle = siccuart_unthrottle, - .send_xchar = siccuart_send_xchar, - .set_termios = siccuart_set_termios, - .stop = siccuart_stop, - .start = siccuart_start, - .hangup = siccuart_hangup, - .break_ctl = siccuart_break_ctl, - .wait_until_sent = siccuart_wait_until_sent, -}; - -int __init siccuart_init(void) -{ - int i; - siccnormal_driver = alloc_tty_driver(SERIAL_SICC_NR); - if (!siccnormal_driver) - return -ENOMEM; - printk("IBM Vesta SICC serial port driver V 0.1 by Yudong Yang and Yi Ge / IBM CRL .\n"); - siccnormal_driver->driver_name = "serial_sicc"; - siccnormal_driver->owner = THIS_MODULE; - siccnormal_driver->name = SERIAL_SICC_NAME; - siccnormal_driver->major = SERIAL_SICC_MAJOR; - siccnormal_driver->minor_start = SERIAL_SICC_MINOR; - siccnormal_driver->type = TTY_DRIVER_TYPE_SERIAL; - siccnormal_driver->subtype = SERIAL_TYPE_NORMAL; - siccnormal_driver->init_termios = tty_std_termios; - siccnormal_driver->init_termios.c_cflag = B9600 | CS8 | CREAD | HUPCL | CLOCAL; - siccnormal_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; - tty_set_operations(siccnormal_driver, &sicc_ops); - - if (tty_register_driver(siccnormal_driver)) - panic("Couldn't register SICC serial driver\n"); - - for (i = 0; i < SERIAL_SICC_NR; i++) { - struct SICC_state *state = sicc_state + i; - state->line = i; - state->close_delay = msecs_to_jiffies(500); - state->closing_wait = 30 * HZ; - spin_lock_init(&state->sicc_lock); - } - - - return 0; -} - -__initcall(siccuart_init); - -#ifdef CONFIG_SERIAL_SICC_CONSOLE -/************** console driver *****************/ - -/* - * This code is currently never used; console->read is never called. - * Therefore, although we have an implementation, we don't use it. - * FIXME: the "const char *s" should be fixed to "char *s" some day. - * (when the definition in include/linux/console.h is also fixed) - */ -#ifdef used_and_not_const_char_pointer -static int siccuart_console_read(struct console *co, const char *s, u_int count) -{ - struct SICC_port *port = &sicc_ports[co->index]; - unsigned int status; - char *w; - int c; - - pr_debug("siccuart_console_read() called\n"); - - c = 0; - w = s; - while (c < count) { - if(readb(port->uart_base + BL_SICC_LSR) & _LSR_RBR_FULL) { - *w++ = readb(port->uart_base + BL_SICC_RBR); - c++; - } else { - // nothing more to get, return - return c; - } - } - // return the count - return c; -} -#endif - -/* - * Print a string to the serial port trying not to disturb - * any possible real use of the port... - * - * The console_lock must be held when we get here. - */ -static void siccuart_console_write(struct console *co, const char *s, u_int count) -{ - struct SICC_port *port = &sicc_ports[co->index]; - unsigned int old_cr; - int i; - - /* - * First save the CR then disable the interrupts - */ - old_cr = readb(port->uart_base + BL_SICC_TxCR); - writeb(old_cr & ~_TxCR_DME_MASK, port->uart_base + BL_SICC_TxCR); - - /* - * Now, do each character - */ - for (i = 0; i < count; i++) { - while ((readb(port->uart_base + BL_SICC_LSR)&_LSR_TX_ALL) != _LSR_TX_ALL); - writeb(s[i], port->uart_base + BL_SICC_TBR); - if (s[i] == '\n') { - while ((readb(port->uart_base + BL_SICC_LSR)&_LSR_TX_ALL) != _LSR_TX_ALL); - writeb('\r', port->uart_base + BL_SICC_TBR); - } - } - - /* - * Finally, wait for transmitter to become empty - * and restore the TCR - */ - while ((readb(port->uart_base + BL_SICC_LSR)&_LSR_TX_ALL) != _LSR_TX_ALL); - writeb(old_cr, port->uart_base + BL_SICC_TxCR); -} - -/* - * Receive character from the serial port - */ -static int siccuart_console_wait_key(struct console *co) -{ - struct SICC_port *port = &sicc_ports[co->index]; - int c; - - while(!(readb(port->uart_base + BL_SICC_LSR) & _LSR_RBR_FULL)); - c = readb(port->uart_base + BL_SICC_RBR); - return c; -} - -static struct tty_driver *siccuart_console_device(struct console *c, int *index) -{ - *index = c->index; - return siccnormal_driver; -} - -static int __init siccuart_console_setup(struct console *co, char *options) -{ - struct SICC_port *port; - int baud = 9600; - int bits = 8; - int parity = 'n'; - u_int cflag = CREAD | HUPCL | CLOCAL; - u_int lcr_h, quot; - - - if (co->index >= SERIAL_SICC_NR) - co->index = 0; - - port = &sicc_ports[co->index]; - - if (port->uart_base == 0) - port->uart_base = (int)ioremap(port->uart_base_phys, PAGE_SIZE); - - if (options) { - char *s = options; - baud = simple_strtoul(s, NULL, 10); - while (*s >= '0' && *s <= '9') - s++; - if (*s) parity = *s++; - if (*s) bits = *s - '0'; - } - - /* - * Now construct a cflag setting. - */ - switch (baud) { - case 1200: cflag |= B1200; break; - case 2400: cflag |= B2400; break; - case 4800: cflag |= B4800; break; - default: cflag |= B9600; baud = 9600; break; - case 19200: cflag |= B19200; break; - case 38400: cflag |= B38400; break; - case 57600: cflag |= B57600; break; - case 115200: cflag |= B115200; break; - } - switch (bits) { - case 7: cflag |= CS7; lcr_h = _LCR_PE_DISABLE | _LCR_DB_7_BITS | _LCR_SB_1_BIT; break; - default: cflag |= CS8; lcr_h = _LCR_PE_DISABLE | _LCR_DB_8_BITS | _LCR_SB_1_BIT; break; - } - switch (parity) { - case 'o': - case 'O': cflag |= PARODD; lcr_h |= _LCR_PTY_ODD; break; - case 'e': - case 'E': cflag |= PARENB; lcr_h |= _LCR_PE_ENABLE | _LCR_PTY_ODD; break; - } - - co->cflag = cflag; - - - { - // a copy of is inserted here ppc403SetBaud(com_port, (int)9600); - unsigned long divisor, clockSource, temp; - unsigned int rate = baud; - - /* Ensure CICCR[7] is 0 to select Internal Baud Clock */ - powerpcMtcic_cr((unsigned long)(powerpcMfcic_cr() & 0xFEFFFFFF)); - - /* Determine Internal Baud Clock Frequency */ - /* powerpcMfclkgpcr() reads DCR 0x120 - the*/ - /* SCCR (Serial Clock Control Register) on Vesta */ - temp = powerpcMfclkgpcr(); - - if(temp & 0x00000080) { - clockSource = 324000000; - } - else { - clockSource = 216000000; - } - clockSource = clockSource/(unsigned long)((temp&0x00FC0000)>>18); - divisor = clockSource/(16*rate) - 1; - /* divisor has only 12 bits of resolution */ - if(divisor>0x00000FFF){ - divisor=0x00000FFF; - } - - quot = divisor; - } - - writeb((quot & 0x00000F00)>>8, port->uart_base + BL_SICC_BRDH ); - writeb( quot & 0x00000FF, port->uart_base + BL_SICC_BRDL ); - - /* Set CTL2 reg to use external clock (ExtClk) and enable FIFOs. */ - /* For now, do NOT use FIFOs since 403 UART did not have this */ - /* capability and this driver was inherited from 403UART. */ - writeb(_CTL2_EXTERN, port->uart_base + BL_SICC_CTL2); - - writeb(lcr_h, port->uart_base + BL_SICC_LCR); - writeb(_RCR_ER_ENABLE | _RCR_PME_HARD, port->uart_base + BL_SICC_RCR); - writeb( _TxCR_ET_ENABLE , port->uart_base + BL_SICC_TxCR); - - // writeb(, info->port->uart_base + BL_SICC_RCR ); - /* - * Transmitter Command Register: Transmitter enabled & DMA + TBR interrupt - * + Transmitter Empty interrupt + Transmitter error interrupt disabled & - * Stop mode when CTS active enabled & Transmit Break + Pattern Generation - * mode disabled. - */ - - writeb( 0x00, port->uart_base + BL_SICC_IrCR ); // disable IrDA - - readb(port->uart_base + BL_SICC_RBR); - - writeb(0xf8, port->uart_base + BL_SICC_LSR); /* reset bits 0-4 of LSR */ - - /* we will enable the port as we need it */ - - return 0; -} - -static struct console siccuart_cons = -{ - .name = SERIAL_SICC_NAME, - .write = siccuart_console_write, -#ifdef used_and_not_const_char_pointer - .read = siccuart_console_read, -#endif - .device = siccuart_console_device, - .wait_key = siccuart_console_wait_key, - .setup = siccuart_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -void __init sicc_console_init(void) -{ - register_console(&siccuart_cons); -} - -#endif /* CONFIG_SERIAL_SICC_CONSOLE */ diff --git a/arch/ppc/8260_io/Kconfig b/arch/ppc/8260_io/Kconfig deleted file mode 100644 index ea9651e2dd6a..000000000000 --- a/arch/ppc/8260_io/Kconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# CPM2 Communication options -# - -menu "CPM2 Options" - depends on CPM2 - -config SCC_ENET - bool "CPM SCC Ethernet" - depends on NET_ETHERNET - -# -# CONFIG_FEC_ENET is only used to get netdevices to call our init -# function. Any combination of FCC1,2,3 are supported. -# -config FEC_ENET - bool "FCC Ethernet" - depends on NET_ETHERNET - -config FCC1_ENET - bool "Ethernet on FCC1" - depends on FEC_ENET - help - Use CPM2 fast Ethernet controller 1 to drive Ethernet (default). - -config FCC2_ENET - bool "Ethernet on FCC2" - depends on FEC_ENET - help - Use CPM2 fast Ethernet controller 2 to drive Ethernet. - -config FCC3_ENET - bool "Ethernet on FCC3" - depends on FEC_ENET - help - Use CPM2 fast Ethernet controller 3 to drive Ethernet. - -config USE_MDIO - bool "Use MDIO for PHY configuration" - depends on FEC_ENET - -choice - prompt "Type of PHY" - depends on 8260 && USE_MDIO - default FCC_GENERIC_PHY - -config FCC_LXT970 - bool "LXT970" - -config FCC_LXT971 - bool "LXT971" - -config FCC_QS6612 - bool "QS6612" - -config FCC_DM9131 - bool "DM9131" - -config FCC_DM9161 - bool "DM9161" - -config FCC_GENERIC_PHY - bool "Generic" -endchoice -endmenu diff --git a/arch/ppc/8260_io/Makefile b/arch/ppc/8260_io/Makefile deleted file mode 100644 index 971f292c5d48..000000000000 --- a/arch/ppc/8260_io/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the linux ppc-specific parts of comm processor (v2) -# - -obj-$(CONFIG_FEC_ENET) += fcc_enet.o -obj-$(CONFIG_SCC_ENET) += enet.o diff --git a/arch/ppc/8260_io/enet.c b/arch/ppc/8260_io/enet.c deleted file mode 100644 index ec1defea9c1e..000000000000 --- a/arch/ppc/8260_io/enet.c +++ /dev/null @@ -1,865 +0,0 @@ -/* - * Ethernet driver for Motorola MPC8260. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * Copyright (c) 2000 MontaVista Software Inc. (source@mvista.com) - * 2.3.99 Updates - * - * I copied this from the 8xx CPM Ethernet driver, so follow the - * credits back through that. - * - * This version of the driver is somewhat selectable for the different - * processor/board combinations. It works for the boards I know about - * now, and should be easily modified to include others. Some of the - * configuration information is contained in and the - * remainder is here. - * - * Buffer descriptors are kept in the CPM dual port RAM, and the frame - * buffers are in the host memory. - * - * Right now, I am very watseful with the buffers. I allocate memory - * pages and then divide them into 2K frame buffers. This way I know I - * have buffers large enough to hold one frame within one buffer descriptor. - * Once I get this working, I will use 64 or 128 byte CPM buffers, which - * will be much more memory efficient and will easily handle lots of - * small packets. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* - * Theory of Operation - * - * The MPC8260 CPM performs the Ethernet processing on an SCC. It can use - * an aribtrary number of buffers on byte boundaries, but must have at - * least two receive buffers to prevent constant overrun conditions. - * - * The buffer descriptors are allocated from the CPM dual port memory - * with the data buffers allocated from host memory, just like all other - * serial communication protocols. The host memory buffers are allocated - * from the free page pool, and then divided into smaller receive and - * transmit buffers. The size of the buffers should be a power of two, - * since that nicely divides the page. This creates a ring buffer - * structure similar to the LANCE and other controllers. - * - * Like the LANCE driver: - * The driver runs as two independent, single-threaded flows of control. One - * is the send-packet routine, which enforces single-threaded use by the - * cep->tx_busy flag. The other thread is the interrupt handler, which is - * single threaded by the hardware and other software. - */ - -/* The transmitter timeout - */ -#define TX_TIMEOUT (2*HZ) - -/* The number of Tx and Rx buffers. These are allocated from the page - * pool. The code may assume these are power of two, so it is best - * to keep them that size. - * We don't need to allocate pages for the transmitter. We just use - * the skbuffer directly. - */ -#define CPM_ENET_RX_PAGES 4 -#define CPM_ENET_RX_FRSIZE 2048 -#define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE) -#define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES) -#define TX_RING_SIZE 8 /* Must be power of two */ -#define TX_RING_MOD_MASK 7 /* for this to work */ - -/* The CPM stores dest/src/type, data, and checksum for receive packets. - */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1520 - -/* The CPM buffer descriptors track the ring buffers. The rx_bd_base and - * tx_bd_base always point to the base of the buffer descriptors. The - * cur_rx and cur_tx point to the currently available buffer. - * The dirty_tx tracks the current buffer that is being sent by the - * controller. The cur_tx and dirty_tx are equal under both completely - * empty and completely full conditions. The empty/ready indicator in - * the buffer descriptor determines the actual condition. - */ -struct scc_enet_private { - /* The saved address of a sent-in-place packet/buffer, for skfree(). */ - struct sk_buff* tx_skbuff[TX_RING_SIZE]; - ushort skb_cur; - ushort skb_dirty; - - /* CPM dual port RAM relative addresses. - */ - cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ - cbd_t *tx_bd_base; - cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ - cbd_t *dirty_tx; /* The ring entries to be free()ed. */ - scc_t *sccp; - struct net_device_stats stats; - uint tx_full; - spinlock_t lock; -}; - -static int scc_enet_open(struct net_device *dev); -static int scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); -static int scc_enet_rx(struct net_device *dev); -static irqreturn_t scc_enet_interrupt(int irq, void *dev_id); -static int scc_enet_close(struct net_device *dev); -static struct net_device_stats *scc_enet_get_stats(struct net_device *dev); -static void set_multicast_list(struct net_device *dev); - -/* These will be configurable for the SCC choice. -*/ -#define CPM_ENET_BLOCK CPM_CR_SCC1_SBLOCK -#define CPM_ENET_PAGE CPM_CR_SCC1_PAGE -#define PROFF_ENET PROFF_SCC1 -#define SCC_ENET 0 -#define SIU_INT_ENET SIU_INT_SCC1 - -/* These are both board and SCC dependent.... -*/ -#define PD_ENET_RXD ((uint)0x00000001) -#define PD_ENET_TXD ((uint)0x00000002) -#define PD_ENET_TENA ((uint)0x00000004) -#define PC_ENET_RENA ((uint)0x00020000) -#define PC_ENET_CLSN ((uint)0x00000004) -#define PC_ENET_TXCLK ((uint)0x00000800) -#define PC_ENET_RXCLK ((uint)0x00000400) -#define CMX_CLK_ROUTE ((uint)0x25000000) -#define CMX_CLK_MASK ((uint)0xff000000) - -/* Specific to a board. -*/ -#define PC_EST8260_ENET_LOOPBACK ((uint)0x80000000) -#define PC_EST8260_ENET_SQE ((uint)0x40000000) -#define PC_EST8260_ENET_NOTFD ((uint)0x20000000) - -static int -scc_enet_open(struct net_device *dev) -{ - - /* I should reset the ring buffers here, but I don't yet know - * a simple way to do that. - */ - netif_start_queue(dev); - return 0; /* Always succeed */ -} - -static int -scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv; - volatile cbd_t *bdp; - - - /* Fill in a Tx ring entry */ - bdp = cep->cur_tx; - -#ifndef final_version - if (bdp->cbd_sc & BD_ENET_TX_READY) { - /* Ooops. All transmit buffers are full. Bail out. - * This should not happen, since cep->tx_full should be set. - */ - printk("%s: tx queue full!.\n", dev->name); - return 1; - } -#endif - - /* Clear all of the status flags. - */ - bdp->cbd_sc &= ~BD_ENET_TX_STATS; - - /* If the frame is short, tell CPM to pad it. - */ - if (skb->len <= ETH_ZLEN) - bdp->cbd_sc |= BD_ENET_TX_PAD; - else - bdp->cbd_sc &= ~BD_ENET_TX_PAD; - - /* Set buffer length and buffer pointer. - */ - bdp->cbd_datlen = skb->len; - bdp->cbd_bufaddr = __pa(skb->data); - - /* Save skb pointer. - */ - cep->tx_skbuff[cep->skb_cur] = skb; - - cep->stats.tx_bytes += skb->len; - cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK; - - spin_lock_irq(&cep->lock); - - /* Send it on its way. Tell CPM its ready, interrupt when done, - * its the last BD of the frame, and to put the CRC on the end. - */ - bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC); - - dev->trans_start = jiffies; - - /* If this was the last BD in the ring, start at the beginning again. - */ - if (bdp->cbd_sc & BD_ENET_TX_WRAP) - bdp = cep->tx_bd_base; - else - bdp++; - - if (bdp->cbd_sc & BD_ENET_TX_READY) { - netif_stop_queue(dev); - cep->tx_full = 1; - } - - cep->cur_tx = (cbd_t *)bdp; - - spin_unlock_irq(&cep->lock); - - return 0; -} - -static void -scc_enet_timeout(struct net_device *dev) -{ - struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv; - - printk("%s: transmit timed out.\n", dev->name); - cep->stats.tx_errors++; -#ifndef final_version - { - int i; - cbd_t *bdp; - printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n", - cep->cur_tx, cep->tx_full ? " (full)" : "", - cep->cur_rx); - bdp = cep->tx_bd_base; - printk(" Tx @base %p :\n", bdp); - for (i = 0 ; i < TX_RING_SIZE; i++, bdp++) - printk("%04x %04x %08x\n", - bdp->cbd_sc, - bdp->cbd_datlen, - bdp->cbd_bufaddr); - bdp = cep->rx_bd_base; - printk(" Rx @base %p :\n", bdp); - for (i = 0 ; i < RX_RING_SIZE; i++, bdp++) - printk("%04x %04x %08x\n", - bdp->cbd_sc, - bdp->cbd_datlen, - bdp->cbd_bufaddr); - } -#endif - if (!cep->tx_full) - netif_wake_queue(dev); -} - -/* The interrupt handler. - * This is called from the CPM handler, not the MPC core interrupt. - */ -static irqreturn_t -scc_enet_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - volatile struct scc_enet_private *cep; - volatile cbd_t *bdp; - ushort int_events; - int must_restart; - - cep = dev->priv; - - /* Get the interrupt events that caused us to be here. - */ - int_events = cep->sccp->scc_scce; - cep->sccp->scc_scce = int_events; - must_restart = 0; - - /* Handle receive event in its own function. - */ - if (int_events & SCCE_ENET_RXF) - scc_enet_rx(dev_id); - - /* Check for a transmit error. The manual is a little unclear - * about this, so the debug code until I get it figured out. It - * appears that if TXE is set, then TXB is not set. However, - * if carrier sense is lost during frame transmission, the TXE - * bit is set, "and continues the buffer transmission normally." - * I don't know if "normally" implies TXB is set when the buffer - * descriptor is closed.....trial and error :-). - */ - - /* Transmit OK, or non-fatal error. Update the buffer descriptors. - */ - if (int_events & (SCCE_ENET_TXE | SCCE_ENET_TXB)) { - spin_lock(&cep->lock); - bdp = cep->dirty_tx; - while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) { - if ((bdp==cep->cur_tx) && (cep->tx_full == 0)) - break; - - if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */ - cep->stats.tx_heartbeat_errors++; - if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */ - cep->stats.tx_window_errors++; - if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */ - cep->stats.tx_aborted_errors++; - if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */ - cep->stats.tx_fifo_errors++; - if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */ - cep->stats.tx_carrier_errors++; - - - /* No heartbeat or Lost carrier are not really bad errors. - * The others require a restart transmit command. - */ - if (bdp->cbd_sc & - (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) { - must_restart = 1; - cep->stats.tx_errors++; - } - - cep->stats.tx_packets++; - - /* Deferred means some collisions occurred during transmit, - * but we eventually sent the packet OK. - */ - if (bdp->cbd_sc & BD_ENET_TX_DEF) - cep->stats.collisions++; - - /* Free the sk buffer associated with this last transmit. - */ - dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]); - cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK; - - /* Update pointer to next buffer descriptor to be transmitted. - */ - if (bdp->cbd_sc & BD_ENET_TX_WRAP) - bdp = cep->tx_bd_base; - else - bdp++; - - /* I don't know if we can be held off from processing these - * interrupts for more than one frame time. I really hope - * not. In such a case, we would now want to check the - * currently available BD (cur_tx) and determine if any - * buffers between the dirty_tx and cur_tx have also been - * sent. We would want to process anything in between that - * does not have BD_ENET_TX_READY set. - */ - - /* Since we have freed up a buffer, the ring is no longer - * full. - */ - if (cep->tx_full) { - cep->tx_full = 0; - if (netif_queue_stopped(dev)) { - netif_wake_queue(dev); - } - } - - cep->dirty_tx = (cbd_t *)bdp; - } - - if (must_restart) { - volatile cpm_cpm2_t *cp; - - /* Some transmit errors cause the transmitter to shut - * down. We now issue a restart transmit. Since the - * errors close the BD and update the pointers, the restart - * _should_ pick up without having to reset any of our - * pointers either. - */ - - cp = cpmp; - cp->cp_cpcr = - mk_cr_cmd(CPM_ENET_PAGE, CPM_ENET_BLOCK, 0, - CPM_CR_RESTART_TX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - } - spin_unlock(&cep->lock); - } - - /* Check for receive busy, i.e. packets coming but no place to - * put them. This "can't happen" because the receive interrupt - * is tossing previous frames. - */ - if (int_events & SCCE_ENET_BSY) { - cep->stats.rx_dropped++; - printk("SCC ENET: BSY can't happen.\n"); - } - - return IRQ_HANDLED; -} - -/* During a receive, the cur_rx points to the current incoming buffer. - * When we update through the ring, if the next incoming buffer has - * not been given to the system, we just set the empty indicator, - * effectively tossing the packet. - */ -static int -scc_enet_rx(struct net_device *dev) -{ - struct scc_enet_private *cep; - volatile cbd_t *bdp; - struct sk_buff *skb; - ushort pkt_len; - - cep = dev->priv; - - /* First, grab all of the stats for the incoming packet. - * These get messed up if we get called due to a busy condition. - */ - bdp = cep->cur_rx; - -for (;;) { - if (bdp->cbd_sc & BD_ENET_RX_EMPTY) - break; - -#ifndef final_version - /* Since we have allocated space to hold a complete frame, both - * the first and last indicators should be set. - */ - if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) != - (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) - printk("CPM ENET: rcv is not first+last\n"); -#endif - - /* Frame too long or too short. - */ - if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) - cep->stats.rx_length_errors++; - if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */ - cep->stats.rx_frame_errors++; - if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */ - cep->stats.rx_crc_errors++; - if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */ - cep->stats.rx_crc_errors++; - - /* Report late collisions as a frame error. - * On this error, the BD is closed, but we don't know what we - * have in the buffer. So, just drop this frame on the floor. - */ - if (bdp->cbd_sc & BD_ENET_RX_CL) { - cep->stats.rx_frame_errors++; - } - else { - - /* Process the incoming frame. - */ - cep->stats.rx_packets++; - pkt_len = bdp->cbd_datlen; - cep->stats.rx_bytes += pkt_len; - - /* This does 16 byte alignment, much more than we need. - * The packet length includes FCS, but we don't want to - * include that when passing upstream as it messes up - * bridging applications. - */ - skb = dev_alloc_skb(pkt_len-4); - - if (skb == NULL) { - printk("%s: Memory squeeze, dropping packet.\n", dev->name); - cep->stats.rx_dropped++; - } - else { - skb_put(skb,pkt_len-4); /* Make room */ - skb_copy_to_linear_data(skb, - (unsigned char *)__va(bdp->cbd_bufaddr), - pkt_len-4); - skb->protocol=eth_type_trans(skb,dev); - netif_rx(skb); - } - } - - /* Clear the status flags for this buffer. - */ - bdp->cbd_sc &= ~BD_ENET_RX_STATS; - - /* Mark the buffer empty. - */ - bdp->cbd_sc |= BD_ENET_RX_EMPTY; - - /* Update BD pointer to next entry. - */ - if (bdp->cbd_sc & BD_ENET_RX_WRAP) - bdp = cep->rx_bd_base; - else - bdp++; - - } - cep->cur_rx = (cbd_t *)bdp; - - return 0; -} - -static int -scc_enet_close(struct net_device *dev) -{ - /* Don't know what to do yet. - */ - netif_stop_queue(dev); - - return 0; -} - -static struct net_device_stats *scc_enet_get_stats(struct net_device *dev) -{ - struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv; - - return &cep->stats; -} - -/* Set or clear the multicast filter for this adaptor. - * Skeleton taken from sunlance driver. - * The CPM Ethernet implementation allows Multicast as well as individual - * MAC address filtering. Some of the drivers check to make sure it is - * a group multicast address, and discard those that are not. I guess I - * will do the same for now, but just remove the test if you want - * individual filtering as well (do the upper net layers want or support - * this kind of feature?). - */ - -static void set_multicast_list(struct net_device *dev) -{ - struct scc_enet_private *cep; - struct dev_mc_list *dmi; - u_char *mcptr, *tdptr; - volatile scc_enet_t *ep; - int i, j; - cep = (struct scc_enet_private *)dev->priv; - - /* Get pointer to SCC area in parameter RAM. - */ - ep = (scc_enet_t *)dev->base_addr; - - if (dev->flags&IFF_PROMISC) { - - /* Log any net taps. */ - printk("%s: Promiscuous mode enabled.\n", dev->name); - cep->sccp->scc_psmr |= SCC_PSMR_PRO; - } else { - - cep->sccp->scc_psmr &= ~SCC_PSMR_PRO; - - if (dev->flags & IFF_ALLMULTI) { - /* Catch all multicast addresses, so set the - * filter to all 1's. - */ - ep->sen_gaddr1 = 0xffff; - ep->sen_gaddr2 = 0xffff; - ep->sen_gaddr3 = 0xffff; - ep->sen_gaddr4 = 0xffff; - } - else { - /* Clear filter and add the addresses in the list. - */ - ep->sen_gaddr1 = 0; - ep->sen_gaddr2 = 0; - ep->sen_gaddr3 = 0; - ep->sen_gaddr4 = 0; - - dmi = dev->mc_list; - - for (i=0; imc_count; i++) { - - /* Only support group multicast for now. - */ - if (!(dmi->dmi_addr[0] & 1)) - continue; - - /* The address in dmi_addr is LSB first, - * and taddr is MSB first. We have to - * copy bytes MSB first from dmi_addr. - */ - mcptr = (u_char *)dmi->dmi_addr + 5; - tdptr = (u_char *)&ep->sen_taddrh; - for (j=0; j<6; j++) - *tdptr++ = *mcptr--; - - /* Ask CPM to run CRC and set bit in - * filter mask. - */ - cpmp->cp_cpcr = mk_cr_cmd(CPM_ENET_PAGE, - CPM_ENET_BLOCK, 0, - CPM_CR_SET_GADDR) | CPM_CR_FLG; - /* this delay is necessary here -- Cort */ - udelay(10); - while (cpmp->cp_cpcr & CPM_CR_FLG); - } - } - } -} - -/* Initialize the CPM Ethernet on SCC. - */ -static int __init scc_enet_init(void) -{ - struct net_device *dev; - struct scc_enet_private *cep; - int i, j, err; - uint dp_offset; - unsigned char *eap; - unsigned long mem_addr; - bd_t *bd; - volatile cbd_t *bdp; - volatile cpm_cpm2_t *cp; - volatile scc_t *sccp; - volatile scc_enet_t *ep; - volatile cpm2_map_t *immap; - volatile iop_cpm2_t *io; - - cp = cpmp; /* Get pointer to Communication Processor */ - - immap = (cpm2_map_t *)CPM_MAP_ADDR; /* and to internal registers */ - io = &immap->im_ioport; - - bd = (bd_t *)__res; - - /* Create an Ethernet device instance. - */ - dev = alloc_etherdev(sizeof(*cep)); - if (!dev) - return -ENOMEM; - - cep = dev->priv; - spin_lock_init(&cep->lock); - - /* Get pointer to SCC area in parameter RAM. - */ - ep = (scc_enet_t *)(&immap->im_dprambase[PROFF_ENET]); - - /* And another to the SCC register area. - */ - sccp = (volatile scc_t *)(&immap->im_scc[SCC_ENET]); - cep->sccp = (scc_t *)sccp; /* Keep the pointer handy */ - - /* Disable receive and transmit in case someone left it running. - */ - sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* Configure port C and D pins for SCC Ethernet. This - * won't work for all SCC possibilities....it will be - * board/port specific. - */ - io->iop_pparc |= - (PC_ENET_RENA | PC_ENET_CLSN | PC_ENET_TXCLK | PC_ENET_RXCLK); - io->iop_pdirc &= - ~(PC_ENET_RENA | PC_ENET_CLSN | PC_ENET_TXCLK | PC_ENET_RXCLK); - io->iop_psorc &= - ~(PC_ENET_RENA | PC_ENET_TXCLK | PC_ENET_RXCLK); - io->iop_psorc |= PC_ENET_CLSN; - - io->iop_ppard |= (PD_ENET_RXD | PD_ENET_TXD | PD_ENET_TENA); - io->iop_pdird |= (PD_ENET_TXD | PD_ENET_TENA); - io->iop_pdird &= ~PD_ENET_RXD; - io->iop_psord |= PD_ENET_TXD; - io->iop_psord &= ~(PD_ENET_RXD | PD_ENET_TENA); - - /* Configure Serial Interface clock routing. - * First, clear all SCC bits to zero, then set the ones we want. - */ - immap->im_cpmux.cmx_scr &= ~CMX_CLK_MASK; - immap->im_cpmux.cmx_scr |= CMX_CLK_ROUTE; - - /* Allocate space for the buffer descriptors in the DP ram. - * These are relative offsets in the DP ram address space. - * Initialize base addresses for the buffer descriptors. - */ - dp_offset = cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8); - ep->sen_genscc.scc_rbase = dp_offset; - cep->rx_bd_base = (cbd_t *)cpm_dpram_addr(dp_offset); - - dp_offset = cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8); - ep->sen_genscc.scc_tbase = dp_offset; - cep->tx_bd_base = (cbd_t *)cpm_dpram_addr(dp_offset); - - cep->dirty_tx = cep->cur_tx = cep->tx_bd_base; - cep->cur_rx = cep->rx_bd_base; - - ep->sen_genscc.scc_rfcr = CPMFCR_GBL | CPMFCR_EB; - ep->sen_genscc.scc_tfcr = CPMFCR_GBL | CPMFCR_EB; - - /* Set maximum bytes per receive buffer. - * This appears to be an Ethernet frame size, not the buffer - * fragment size. It must be a multiple of four. - */ - ep->sen_genscc.scc_mrblr = PKT_MAXBLR_SIZE; - - /* Set CRC preset and mask. - */ - ep->sen_cpres = 0xffffffff; - ep->sen_cmask = 0xdebb20e3; - - ep->sen_crcec = 0; /* CRC Error counter */ - ep->sen_alec = 0; /* alignment error counter */ - ep->sen_disfc = 0; /* discard frame counter */ - - ep->sen_pads = 0x8888; /* Tx short frame pad character */ - ep->sen_retlim = 15; /* Retry limit threshold */ - - ep->sen_maxflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - ep->sen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ - - ep->sen_maxd1 = PKT_MAXBLR_SIZE; /* maximum DMA1 length */ - ep->sen_maxd2 = PKT_MAXBLR_SIZE; /* maximum DMA2 length */ - - /* Clear hash tables. - */ - ep->sen_gaddr1 = 0; - ep->sen_gaddr2 = 0; - ep->sen_gaddr3 = 0; - ep->sen_gaddr4 = 0; - ep->sen_iaddr1 = 0; - ep->sen_iaddr2 = 0; - ep->sen_iaddr3 = 0; - ep->sen_iaddr4 = 0; - - /* Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - */ - eap = (unsigned char *)&(ep->sen_paddrh); - for (i=5; i>=0; i--) - *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i]; - - ep->sen_pper = 0; /* 'cause the book says so */ - ep->sen_taddrl = 0; /* temp address (LSB) */ - ep->sen_taddrm = 0; - ep->sen_taddrh = 0; /* temp address (MSB) */ - - /* Now allocate the host memory pages and initialize the - * buffer descriptors. - */ - bdp = cep->tx_bd_base; - for (i=0; icbd_sc = 0; - bdp->cbd_bufaddr = 0; - bdp++; - } - - /* Set the last buffer to wrap. - */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; - - bdp = cep->rx_bd_base; - for (i=0; icbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR; - bdp->cbd_bufaddr = __pa(mem_addr); - mem_addr += CPM_ENET_RX_FRSIZE; - bdp++; - } - } - - /* Set the last buffer to wrap. - */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; - - /* Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cpmp->cp_cpcr = mk_cr_cmd(CPM_ENET_PAGE, CPM_ENET_BLOCK, 0, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - cep->skb_cur = cep->skb_dirty = 0; - - sccp->scc_scce = 0xffff; /* Clear any pending events */ - - /* Enable interrupts for transmit error, complete frame - * received, and any transmit buffer we have also set the - * interrupt flag. - */ - sccp->scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB); - - /* Install our interrupt handler. - */ - request_irq(SIU_INT_ENET, scc_enet_interrupt, 0, "enet", dev); - /* BUG: no check for failure */ - - /* Set GSMR_H to enable all normal operating modes. - * Set GSMR_L to enable Ethernet to MC68160. - */ - sccp->scc_gsmrh = 0; - sccp->scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET); - - /* Set sync/delimiters. - */ - sccp->scc_dsr = 0xd555; - - /* Set processing mode. Use Ethernet CRC, catch broadcast, and - * start frame search 22 bit times after RENA. - */ - sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22); - - /* It is now OK to enable the Ethernet transmitter. - * Unfortunately, there are board implementation differences here. - */ - io->iop_pparc &= ~(PC_EST8260_ENET_LOOPBACK | - PC_EST8260_ENET_SQE | PC_EST8260_ENET_NOTFD); - io->iop_psorc &= ~(PC_EST8260_ENET_LOOPBACK | - PC_EST8260_ENET_SQE | PC_EST8260_ENET_NOTFD); - io->iop_pdirc |= (PC_EST8260_ENET_LOOPBACK | - PC_EST8260_ENET_SQE | PC_EST8260_ENET_NOTFD); - io->iop_pdatc &= ~(PC_EST8260_ENET_LOOPBACK | PC_EST8260_ENET_SQE); - io->iop_pdatc |= PC_EST8260_ENET_NOTFD; - - dev->base_addr = (unsigned long)ep; - - /* The CPM Ethernet specific entries in the device structure. */ - dev->open = scc_enet_open; - dev->hard_start_xmit = scc_enet_start_xmit; - dev->tx_timeout = scc_enet_timeout; - dev->watchdog_timeo = TX_TIMEOUT; - dev->stop = scc_enet_close; - dev->get_stats = scc_enet_get_stats; - dev->set_multicast_list = set_multicast_list; - - /* And last, enable the transmit and receive processing. - */ - sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - err = register_netdev(dev); - if (err) { - free_netdev(dev); - return err; - } - - printk("%s: SCC ENET Version 0.1, ", dev->name); - for (i=0; i<5; i++) - printk("%02x:", dev->dev_addr[i]); - printk("%02x\n", dev->dev_addr[5]); - - return 0; -} - -module_init(scc_enet_init); diff --git a/arch/ppc/8260_io/fcc_enet.c b/arch/ppc/8260_io/fcc_enet.c deleted file mode 100644 index d38b57e24cee..000000000000 --- a/arch/ppc/8260_io/fcc_enet.c +++ /dev/null @@ -1,2379 +0,0 @@ -/* - * Fast Ethernet Controller (FCC) driver for Motorola MPC8260. - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * This version of the driver is a combination of the 8xx fec and - * 8260 SCC Ethernet drivers. This version has some additional - * configuration options, which should probably be moved out of - * here. This driver currently works for the EST SBC8260, - * SBS Diablo/BCM, Embedded Planet RPX6, TQM8260, and others. - * - * Right now, I am very watseful with the buffers. I allocate memory - * pages and then divide them into 2K frame buffers. This way I know I - * have buffers large enough to hold one frame within one buffer descriptor. - * Once I get this working, I will use 64 or 128 byte CPM buffers, which - * will be much more memory efficient and will easily handle lots of - * small packets. Since this is a cache coherent processor and CPM, - * I could also preallocate SKB's and use them directly on the interface. - * - * 2004-12 Leo Li (leoli@freescale.com) - * - Rework the FCC clock configuration part, make it easier to configure. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* We can't use the PHY interrupt if we aren't using MDIO. */ -#if !defined(CONFIG_USE_MDIO) -#undef PHY_INTERRUPT -#endif - -/* If we have a PHY interrupt, we will advertise both full-duplex and half- - * duplex capabilities. If we don't have a PHY interrupt, then we will only - * advertise half-duplex capabilities. - */ -#define MII_ADVERTISE_HALF (ADVERTISE_100HALF | ADVERTISE_10HALF | \ - ADVERTISE_CSMA) -#define MII_ADVERTISE_ALL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - MII_ADVERTISE_HALF) -#ifdef PHY_INTERRUPT -#define MII_ADVERTISE_DEFAULT MII_ADVERTISE_ALL -#else -#define MII_ADVERTISE_DEFAULT MII_ADVERTISE_HALF -#endif -#include - -/* The transmitter timeout - */ -#define TX_TIMEOUT (2*HZ) - -#ifdef CONFIG_USE_MDIO -/* Forward declarations of some structures to support different PHYs */ - -typedef struct { - uint mii_data; - void (*funct)(uint mii_reg, struct net_device *dev); -} phy_cmd_t; - -typedef struct { - uint id; - char *name; - - const phy_cmd_t *config; - const phy_cmd_t *startup; - const phy_cmd_t *ack_int; - const phy_cmd_t *shutdown; -} phy_info_t; - -/* values for phy_status */ - -#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ -#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ -#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ -#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ -#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ -#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ -#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ - -#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ -#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ -#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ -#define PHY_STAT_SPMASK 0xf000 /* mask for speed */ -#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ -#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ -#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ -#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ -#endif /* CONFIG_USE_MDIO */ - -/* The number of Tx and Rx buffers. These are allocated from the page - * pool. The code may assume these are power of two, so it is best - * to keep them that size. - * We don't need to allocate pages for the transmitter. We just use - * the skbuffer directly. - */ -#define FCC_ENET_RX_PAGES 16 -#define FCC_ENET_RX_FRSIZE 2048 -#define FCC_ENET_RX_FRPPG (PAGE_SIZE / FCC_ENET_RX_FRSIZE) -#define RX_RING_SIZE (FCC_ENET_RX_FRPPG * FCC_ENET_RX_PAGES) -#define TX_RING_SIZE 16 /* Must be power of two */ -#define TX_RING_MOD_MASK 15 /* for this to work */ - -/* The FCC stores dest/src/type, data, and checksum for receive packets. - * size includes support for VLAN - */ -#define PKT_MAXBUF_SIZE 1522 -#define PKT_MINBUF_SIZE 64 - -/* Maximum input DMA size. Must be a should(?) be a multiple of 4. - * size includes support for VLAN - */ -#define PKT_MAXDMA_SIZE 1524 - -/* Maximum input buffer size. Must be a multiple of 32. -*/ -#define PKT_MAXBLR_SIZE 1536 - -static int fcc_enet_open(struct net_device *dev); -static int fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); -static int fcc_enet_rx(struct net_device *dev); -static irqreturn_t fcc_enet_interrupt(int irq, void *dev_id); -static int fcc_enet_close(struct net_device *dev); -static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev); -/* static void set_multicast_list(struct net_device *dev); */ -static void fcc_restart(struct net_device *dev, int duplex); -static void fcc_stop(struct net_device *dev); -static int fcc_enet_set_mac_address(struct net_device *dev, void *addr); - -/* These will be configurable for the FCC choice. - * Multiple ports can be configured. There is little choice among the - * I/O pins to the PHY, except the clocks. We will need some board - * dependent clock selection. - * Why in the hell did I put these inside #ifdef's? I dunno, maybe to - * help show what pins are used for each device. - */ - -/* Since the CLK setting changes greatly from board to board, I changed - * it to a easy way. You just need to specify which CLK number to use. - * Note that only limited choices can be make on each port. - */ - -/* FCC1 Clock Source Configuration. There are board specific. - Can only choose from CLK9-12 */ -#ifdef CONFIG_SBC82xx -#define F1_RXCLK 9 -#define F1_TXCLK 10 -#else -#define F1_RXCLK 12 -#define F1_TXCLK 11 -#endif - -/* FCC2 Clock Source Configuration. There are board specific. - Can only choose from CLK13-16 */ -#define F2_RXCLK 13 -#define F2_TXCLK 14 - -/* FCC3 Clock Source Configuration. There are board specific. - Can only choose from CLK13-16 */ -#define F3_RXCLK 15 -#define F3_TXCLK 16 - -/* Automatically generates register configurations */ -#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ - -#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ -#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ -#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ -#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ -#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ -#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ - -#define PC_F1RXCLK PC_CLK(F1_RXCLK) -#define PC_F1TXCLK PC_CLK(F1_TXCLK) -#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) -#define CMX1_CLK_MASK ((uint)0xff000000) - -#define PC_F2RXCLK PC_CLK(F2_RXCLK) -#define PC_F2TXCLK PC_CLK(F2_TXCLK) -#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) -#define CMX2_CLK_MASK ((uint)0x00ff0000) - -#define PC_F3RXCLK PC_CLK(F3_RXCLK) -#define PC_F3TXCLK PC_CLK(F3_TXCLK) -#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) -#define CMX3_CLK_MASK ((uint)0x0000ff00) - - -/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, - * but there is little variation among the choices. - */ -#define PA1_COL ((uint)0x00000001) -#define PA1_CRS ((uint)0x00000002) -#define PA1_TXER ((uint)0x00000004) -#define PA1_TXEN ((uint)0x00000008) -#define PA1_RXDV ((uint)0x00000010) -#define PA1_RXER ((uint)0x00000020) -#define PA1_TXDAT ((uint)0x00003c00) -#define PA1_RXDAT ((uint)0x0003c000) -#define PA1_PSORA_BOUT (PA1_RXDAT | PA1_TXDAT) -#define PA1_PSORA_BIN (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ - PA1_RXDV | PA1_RXER) -#define PA1_DIRA_BOUT (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) -#define PA1_DIRA_BIN (PA1_TXDAT | PA1_TXEN | PA1_TXER) - - -/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, - * but there is little variation among the choices. - */ -#define PB2_TXER ((uint)0x00000001) -#define PB2_RXDV ((uint)0x00000002) -#define PB2_TXEN ((uint)0x00000004) -#define PB2_RXER ((uint)0x00000008) -#define PB2_COL ((uint)0x00000010) -#define PB2_CRS ((uint)0x00000020) -#define PB2_TXDAT ((uint)0x000003c0) -#define PB2_RXDAT ((uint)0x00003c00) -#define PB2_PSORB_BOUT (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ - PB2_RXER | PB2_RXDV | PB2_TXER) -#define PB2_PSORB_BIN (PB2_TXEN) -#define PB2_DIRB_BOUT (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) -#define PB2_DIRB_BIN (PB2_TXDAT | PB2_TXEN | PB2_TXER) - - -/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, - * but there is little variation among the choices. - */ -#define PB3_RXDV ((uint)0x00004000) -#define PB3_RXER ((uint)0x00008000) -#define PB3_TXER ((uint)0x00010000) -#define PB3_TXEN ((uint)0x00020000) -#define PB3_COL ((uint)0x00040000) -#define PB3_CRS ((uint)0x00080000) -#ifndef CONFIG_RPX8260 -#define PB3_TXDAT ((uint)0x0f000000) -#define PC3_TXDAT ((uint)0x00000000) -#else -#define PB3_TXDAT ((uint)0x0f000000) -#define PC3_TXDAT 0 -#endif -#define PB3_RXDAT ((uint)0x00f00000) -#define PB3_PSORB_BOUT (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ - PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) -#define PB3_PSORB_BIN (0) -#define PB3_DIRB_BOUT (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) -#define PB3_DIRB_BIN (PB3_TXDAT | PB3_TXEN | PB3_TXER) - -#define PC3_PSORC_BOUT (PC3_TXDAT) -#define PC3_PSORC_BIN (0) -#define PC3_DIRC_BOUT (0) -#define PC3_DIRC_BIN (PC3_TXDAT) - - -/* MII status/control serial interface. -*/ -#if defined(CONFIG_RPX8260) -/* The EP8260 doesn't use Port C for MDIO */ -#define PC_MDIO ((uint)0x00000000) -#define PC_MDCK ((uint)0x00000000) -#elif defined(CONFIG_TQM8260) -/* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */ -#define PC_MDIO ((uint)0x00000002) -#define PC_MDCK ((uint)0x00000001) -#elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260) -#define PC_MDIO ((uint)0x00400000) -#define PC_MDCK ((uint)0x00200000) -#else -#define PC_MDIO ((uint)0x00000004) -#define PC_MDCK ((uint)0x00000020) -#endif - -#if defined(CONFIG_USE_MDIO) && (!defined(PC_MDIO) || !defined(PC_MDCK)) -#error "Must define PC_MDIO and PC_MDCK if using MDIO" -#endif - -/* PHY addresses */ -/* default to dynamic config of phy addresses */ -#define FCC1_PHY_ADDR 0 -#ifdef CONFIG_PQ2FADS -#define FCC2_PHY_ADDR 0 -#else -#define FCC2_PHY_ADDR 2 -#endif -#define FCC3_PHY_ADDR 3 - -/* A table of information for supporting FCCs. This does two things. - * First, we know how many FCCs we have and they are always externally - * numbered from zero. Second, it holds control register and I/O - * information that could be different among board designs. - */ -typedef struct fcc_info { - uint fc_fccnum; - uint fc_phyaddr; - uint fc_cpmblock; - uint fc_cpmpage; - uint fc_proff; - uint fc_interrupt; - uint fc_trxclocks; - uint fc_clockroute; - uint fc_clockmask; - uint fc_mdio; - uint fc_mdck; -} fcc_info_t; - -static fcc_info_t fcc_ports[] = { -#ifdef CONFIG_FCC1_ENET - { 0, FCC1_PHY_ADDR, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, PROFF_FCC1, SIU_INT_FCC1, - (PC_F1RXCLK | PC_F1TXCLK), CMX1_CLK_ROUTE, CMX1_CLK_MASK, - PC_MDIO, PC_MDCK }, -#endif -#ifdef CONFIG_FCC2_ENET - { 1, FCC2_PHY_ADDR, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, PROFF_FCC2, SIU_INT_FCC2, - (PC_F2RXCLK | PC_F2TXCLK), CMX2_CLK_ROUTE, CMX2_CLK_MASK, - PC_MDIO, PC_MDCK }, -#endif -#ifdef CONFIG_FCC3_ENET - { 2, FCC3_PHY_ADDR, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3, - (PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK, - PC_MDIO, PC_MDCK }, -#endif -}; - -/* The FCC buffer descriptors track the ring buffers. The rx_bd_base and - * tx_bd_base always point to the base of the buffer descriptors. The - * cur_rx and cur_tx point to the currently available buffer. - * The dirty_tx tracks the current buffer that is being sent by the - * controller. The cur_tx and dirty_tx are equal under both completely - * empty and completely full conditions. The empty/ready indicator in - * the buffer descriptor determines the actual condition. - */ -struct fcc_enet_private { - /* The saved address of a sent-in-place packet/buffer, for skfree(). */ - struct sk_buff* tx_skbuff[TX_RING_SIZE]; - ushort skb_cur; - ushort skb_dirty; - - /* CPM dual port RAM relative addresses. - */ - cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ - cbd_t *tx_bd_base; - cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ - cbd_t *dirty_tx; /* The ring entries to be free()ed. */ - volatile fcc_t *fccp; - volatile fcc_enet_t *ep; - struct net_device_stats stats; - uint tx_free; - spinlock_t lock; - -#ifdef CONFIG_USE_MDIO - uint phy_id; - uint phy_id_done; - uint phy_status; - phy_info_t *phy; - struct work_struct phy_relink; - struct work_struct phy_display_config; - struct net_device *dev; - - uint sequence_done; - - uint phy_addr; -#endif /* CONFIG_USE_MDIO */ - - int link; - int old_link; - int full_duplex; - - fcc_info_t *fip; -}; - -static void init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep, - volatile cpm2_map_t *immap); -static void init_fcc_startup(fcc_info_t *fip, struct net_device *dev); -static void init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io, - volatile cpm2_map_t *immap); -static void init_fcc_param(fcc_info_t *fip, struct net_device *dev, - volatile cpm2_map_t *immap); - -#ifdef CONFIG_USE_MDIO -static int mii_queue(struct net_device *dev, int request, void (*func)(uint, struct net_device *)); -static uint mii_send_receive(fcc_info_t *fip, uint cmd); -static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c); - -/* Make MII read/write commands for the FCC. -*/ -#define mk_mii_read(REG) (0x60020000 | (((REG) & 0x1f) << 18)) -#define mk_mii_write(REG, VAL) (0x50020000 | (((REG) & 0x1f) << 18) | \ - ((VAL) & 0xffff)) -#define mk_mii_end 0 -#endif /* CONFIG_USE_MDIO */ - - -static int -fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv; - volatile cbd_t *bdp; - - /* Fill in a Tx ring entry */ - bdp = cep->cur_tx; - -#ifndef final_version - if (!cep->tx_free || (bdp->cbd_sc & BD_ENET_TX_READY)) { - /* Ooops. All transmit buffers are full. Bail out. - * This should not happen, since the tx queue should be stopped. - */ - printk("%s: tx queue full!.\n", dev->name); - return 1; - } -#endif - - /* Clear all of the status flags. */ - bdp->cbd_sc &= ~BD_ENET_TX_STATS; - - /* If the frame is short, tell CPM to pad it. */ - if (skb->len <= ETH_ZLEN) - bdp->cbd_sc |= BD_ENET_TX_PAD; - else - bdp->cbd_sc &= ~BD_ENET_TX_PAD; - - /* Set buffer length and buffer pointer. */ - bdp->cbd_datlen = skb->len; - bdp->cbd_bufaddr = __pa(skb->data); - - spin_lock_irq(&cep->lock); - - /* Save skb pointer. */ - cep->tx_skbuff[cep->skb_cur] = skb; - - cep->stats.tx_bytes += skb->len; - cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK; - - /* Send it on its way. Tell CPM its ready, interrupt when done, - * its the last BD of the frame, and to put the CRC on the end. - */ - bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC); - -#if 0 - /* Errata says don't do this. */ - cep->fccp->fcc_ftodr = 0x8000; -#endif - dev->trans_start = jiffies; - - /* If this was the last BD in the ring, start at the beginning again. */ - if (bdp->cbd_sc & BD_ENET_TX_WRAP) - bdp = cep->tx_bd_base; - else - bdp++; - - if (!--cep->tx_free) - netif_stop_queue(dev); - - cep->cur_tx = (cbd_t *)bdp; - - spin_unlock_irq(&cep->lock); - - return 0; -} - - -static void -fcc_enet_timeout(struct net_device *dev) -{ - struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv; - - printk("%s: transmit timed out.\n", dev->name); - cep->stats.tx_errors++; -#ifndef final_version - { - int i; - cbd_t *bdp; - printk(" Ring data dump: cur_tx %p tx_free %d cur_rx %p.\n", - cep->cur_tx, cep->tx_free, - cep->cur_rx); - bdp = cep->tx_bd_base; - printk(" Tx @base %p :\n", bdp); - for (i = 0 ; i < TX_RING_SIZE; i++, bdp++) - printk("%04x %04x %08x\n", - bdp->cbd_sc, - bdp->cbd_datlen, - bdp->cbd_bufaddr); - bdp = cep->rx_bd_base; - printk(" Rx @base %p :\n", bdp); - for (i = 0 ; i < RX_RING_SIZE; i++, bdp++) - printk("%04x %04x %08x\n", - bdp->cbd_sc, - bdp->cbd_datlen, - bdp->cbd_bufaddr); - } -#endif - if (cep->tx_free) - netif_wake_queue(dev); -} - -/* The interrupt handler. */ -static irqreturn_t -fcc_enet_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - volatile struct fcc_enet_private *cep; - volatile cbd_t *bdp; - ushort int_events; - int must_restart; - - cep = dev->priv; - - /* Get the interrupt events that caused us to be here. - */ - int_events = cep->fccp->fcc_fcce; - cep->fccp->fcc_fcce = (int_events & cep->fccp->fcc_fccm); - must_restart = 0; - -#ifdef PHY_INTERRUPT - /* We have to be careful here to make sure that we aren't - * interrupted by a PHY interrupt. - */ - disable_irq_nosync(PHY_INTERRUPT); -#endif - - /* Handle receive event in its own function. - */ - if (int_events & FCC_ENET_RXF) - fcc_enet_rx(dev_id); - - /* Check for a transmit error. The manual is a little unclear - * about this, so the debug code until I get it figured out. It - * appears that if TXE is set, then TXB is not set. However, - * if carrier sense is lost during frame transmission, the TXE - * bit is set, "and continues the buffer transmission normally." - * I don't know if "normally" implies TXB is set when the buffer - * descriptor is closed.....trial and error :-). - */ - - /* Transmit OK, or non-fatal error. Update the buffer descriptors. - */ - if (int_events & (FCC_ENET_TXE | FCC_ENET_TXB)) { - spin_lock(&cep->lock); - bdp = cep->dirty_tx; - while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) { - if (cep->tx_free == TX_RING_SIZE) - break; - - if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */ - cep->stats.tx_heartbeat_errors++; - if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */ - cep->stats.tx_window_errors++; - if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */ - cep->stats.tx_aborted_errors++; - if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */ - cep->stats.tx_fifo_errors++; - if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */ - cep->stats.tx_carrier_errors++; - - - /* No heartbeat or Lost carrier are not really bad errors. - * The others require a restart transmit command. - */ - if (bdp->cbd_sc & - (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) { - must_restart = 1; - cep->stats.tx_errors++; - } - - cep->stats.tx_packets++; - - /* Deferred means some collisions occurred during transmit, - * but we eventually sent the packet OK. - */ - if (bdp->cbd_sc & BD_ENET_TX_DEF) - cep->stats.collisions++; - - /* Free the sk buffer associated with this last transmit. */ - dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]); - cep->tx_skbuff[cep->skb_dirty] = NULL; - cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK; - - /* Update pointer to next buffer descriptor to be transmitted. */ - if (bdp->cbd_sc & BD_ENET_TX_WRAP) - bdp = cep->tx_bd_base; - else - bdp++; - - /* I don't know if we can be held off from processing these - * interrupts for more than one frame time. I really hope - * not. In such a case, we would now want to check the - * currently available BD (cur_tx) and determine if any - * buffers between the dirty_tx and cur_tx have also been - * sent. We would want to process anything in between that - * does not have BD_ENET_TX_READY set. - */ - - /* Since we have freed up a buffer, the ring is no longer - * full. - */ - if (!cep->tx_free++) { - if (netif_queue_stopped(dev)) { - netif_wake_queue(dev); - } - } - - cep->dirty_tx = (cbd_t *)bdp; - } - - if (must_restart) { - volatile cpm_cpm2_t *cp; - - /* Some transmit errors cause the transmitter to shut - * down. We now issue a restart transmit. Since the - * errors close the BD and update the pointers, the restart - * _should_ pick up without having to reset any of our - * pointers either. Also, To workaround 8260 device erratum - * CPM37, we must disable and then re-enable the transmitter - * following a Late Collision, Underrun, or Retry Limit error. - */ - cep->fccp->fcc_gfmr &= ~FCC_GFMR_ENT; - udelay(10); /* wait a few microseconds just on principle */ - cep->fccp->fcc_gfmr |= FCC_GFMR_ENT; - - cp = cpmp; - cp->cp_cpcr = - mk_cr_cmd(cep->fip->fc_cpmpage, cep->fip->fc_cpmblock, - 0x0c, CPM_CR_RESTART_TX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - } - spin_unlock(&cep->lock); - } - - /* Check for receive busy, i.e. packets coming but no place to - * put them. - */ - if (int_events & FCC_ENET_BSY) { - cep->fccp->fcc_fcce = FCC_ENET_BSY; - cep->stats.rx_dropped++; - } - -#ifdef PHY_INTERRUPT - enable_irq(PHY_INTERRUPT); -#endif - return IRQ_HANDLED; -} - -/* During a receive, the cur_rx points to the current incoming buffer. - * When we update through the ring, if the next incoming buffer has - * not been given to the system, we just set the empty indicator, - * effectively tossing the packet. - */ -static int -fcc_enet_rx(struct net_device *dev) -{ - struct fcc_enet_private *cep; - volatile cbd_t *bdp; - struct sk_buff *skb; - ushort pkt_len; - - cep = dev->priv; - - /* First, grab all of the stats for the incoming packet. - * These get messed up if we get called due to a busy condition. - */ - bdp = cep->cur_rx; - -for (;;) { - if (bdp->cbd_sc & BD_ENET_RX_EMPTY) - break; - -#ifndef final_version - /* Since we have allocated space to hold a complete frame, both - * the first and last indicators should be set. - */ - if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) != - (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) - printk("CPM ENET: rcv is not first+last\n"); -#endif - - /* Frame too long or too short. */ - if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) - cep->stats.rx_length_errors++; - if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */ - cep->stats.rx_frame_errors++; - if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */ - cep->stats.rx_crc_errors++; - if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */ - cep->stats.rx_crc_errors++; - if (bdp->cbd_sc & BD_ENET_RX_CL) /* Late Collision */ - cep->stats.rx_frame_errors++; - - if (!(bdp->cbd_sc & - (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | BD_ENET_RX_CR - | BD_ENET_RX_OV | BD_ENET_RX_CL))) - { - /* Process the incoming frame. */ - cep->stats.rx_packets++; - - /* Remove the FCS from the packet length. */ - pkt_len = bdp->cbd_datlen - 4; - cep->stats.rx_bytes += pkt_len; - - /* This does 16 byte alignment, much more than we need. */ - skb = dev_alloc_skb(pkt_len); - - if (skb == NULL) { - printk("%s: Memory squeeze, dropping packet.\n", dev->name); - cep->stats.rx_dropped++; - } - else { - skb_put(skb,pkt_len); /* Make room */ - skb_copy_to_linear_data(skb, - (unsigned char *)__va(bdp->cbd_bufaddr), - pkt_len); - skb->protocol=eth_type_trans(skb,dev); - netif_rx(skb); - } - } - - /* Clear the status flags for this buffer. */ - bdp->cbd_sc &= ~BD_ENET_RX_STATS; - - /* Mark the buffer empty. */ - bdp->cbd_sc |= BD_ENET_RX_EMPTY; - - /* Update BD pointer to next entry. */ - if (bdp->cbd_sc & BD_ENET_RX_WRAP) - bdp = cep->rx_bd_base; - else - bdp++; - - } - cep->cur_rx = (cbd_t *)bdp; - - return 0; -} - -static int -fcc_enet_close(struct net_device *dev) -{ -#ifdef CONFIG_USE_MDIO - struct fcc_enet_private *fep = dev->priv; -#endif - - netif_stop_queue(dev); - fcc_stop(dev); -#ifdef CONFIG_USE_MDIO - if (fep->phy) - mii_do_cmd(dev, fep->phy->shutdown); -#endif - - return 0; -} - -static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev) -{ - struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv; - - return &cep->stats; -} - -#ifdef CONFIG_USE_MDIO - -/* NOTE: Most of the following comes from the FEC driver for 860. The - * overall structure of MII code has been retained (as it's proved stable - * and well-tested), but actual transfer requests are processed "at once" - * instead of being queued (there's no interrupt-driven MII transfer - * mechanism, one has to toggle the data/clock bits manually). - */ -static int -mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) -{ - struct fcc_enet_private *fep; - int retval, tmp; - - /* Add PHY address to register command. */ - fep = dev->priv; - regval |= fep->phy_addr << 23; - - retval = 0; - - tmp = mii_send_receive(fep->fip, regval); - if (func) - func(tmp, dev); - - return retval; -} - -static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) -{ - int k; - - if(!c) - return; - - for(k = 0; (c+k)->mii_data != mk_mii_end; k++) - mii_queue(dev, (c+k)->mii_data, (c+k)->funct); -} - -static void mii_parse_sr(uint mii_reg, struct net_device *dev) -{ - volatile struct fcc_enet_private *fep = dev->priv; - uint s = fep->phy_status; - - s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); - - if (mii_reg & BMSR_LSTATUS) - s |= PHY_STAT_LINK; - if (mii_reg & BMSR_RFAULT) - s |= PHY_STAT_FAULT; - if (mii_reg & BMSR_ANEGCOMPLETE) - s |= PHY_STAT_ANC; - - fep->phy_status = s; -} - -static void mii_parse_cr(uint mii_reg, struct net_device *dev) -{ - volatile struct fcc_enet_private *fep = dev->priv; - uint s = fep->phy_status; - - s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP); - - if (mii_reg & BMCR_ANENABLE) - s |= PHY_CONF_ANE; - if (mii_reg & BMCR_LOOPBACK) - s |= PHY_CONF_LOOP; - - fep->phy_status = s; -} - -static void mii_parse_anar(uint mii_reg, struct net_device *dev) -{ - volatile struct fcc_enet_private *fep = dev->priv; - uint s = fep->phy_status; - - s &= ~(PHY_CONF_SPMASK); - - if (mii_reg & ADVERTISE_10HALF) - s |= PHY_CONF_10HDX; - if (mii_reg & ADVERTISE_10FULL) - s |= PHY_CONF_10FDX; - if (mii_reg & ADVERTISE_100HALF) - s |= PHY_CONF_100HDX; - if (mii_reg & ADVERTISE_100FULL) - s |= PHY_CONF_100FDX; - - fep->phy_status = s; -} - -/* ------------------------------------------------------------------------- */ -/* Generic PHY support. Should work for all PHYs, but does not support link - * change interrupts. - */ -#ifdef CONFIG_FCC_GENERIC_PHY - -static phy_info_t phy_info_generic = { - 0x00000000, /* 0-->match any PHY */ - "GENERIC", - - (const phy_cmd_t []) { /* config */ - /* advertise only half-duplex capabilities */ - { mk_mii_write(MII_ADVERTISE, MII_ADVERTISE_HALF), - mii_parse_anar }, - - /* enable auto-negotiation */ - { mk_mii_write(MII_BMCR, BMCR_ANENABLE), mii_parse_cr }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* startup */ - /* restart auto-negotiation */ - { mk_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART), - NULL }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* ack_int */ - /* We don't actually use the ack_int table with a generic - * PHY, but putting a reference to mii_parse_sr here keeps - * us from getting a compiler warning about unused static - * functions in the case where we only compile in generic - * PHY support. - */ - { mk_mii_read(MII_BMSR), mii_parse_sr }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* shutdown */ - { mk_mii_end, } - }, -}; -#endif /* ifdef CONFIG_FCC_GENERIC_PHY */ - -/* ------------------------------------------------------------------------- */ -/* The Level one LXT970 is used by many boards */ - -#ifdef CONFIG_FCC_LXT970 - -#define MII_LXT970_MIRROR 16 /* Mirror register */ -#define MII_LXT970_IER 17 /* Interrupt Enable Register */ -#define MII_LXT970_ISR 18 /* Interrupt Status Register */ -#define MII_LXT970_CONFIG 19 /* Configuration Register */ -#define MII_LXT970_CSR 20 /* Chip Status Register */ - -static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) -{ - volatile struct fcc_enet_private *fep = dev->priv; - uint s = fep->phy_status; - - s &= ~(PHY_STAT_SPMASK); - - if (mii_reg & 0x0800) { - if (mii_reg & 0x1000) - s |= PHY_STAT_100FDX; - else - s |= PHY_STAT_100HDX; - } else { - if (mii_reg & 0x1000) - s |= PHY_STAT_10FDX; - else - s |= PHY_STAT_10HDX; - } - - fep->phy_status = s; -} - -static phy_info_t phy_info_lxt970 = { - 0x07810000, - "LXT970", - - (const phy_cmd_t []) { /* config */ -#if 0 -// { mk_mii_write(MII_ADVERTISE, 0x0021), NULL }, - - /* Set default operation of 100-TX....for some reason - * some of these bits are set on power up, which is wrong. - */ - { mk_mii_write(MII_LXT970_CONFIG, 0), NULL }, -#endif - { mk_mii_read(MII_BMCR), mii_parse_cr }, - { mk_mii_read(MII_ADVERTISE), mii_parse_anar }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* startup - enable interrupts */ - { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, - { mk_mii_write(MII_BMCR, 0x1200), NULL }, /* autonegotiate */ - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* ack_int */ - /* read SR and ISR to acknowledge */ - - { mk_mii_read(MII_BMSR), mii_parse_sr }, - { mk_mii_read(MII_LXT970_ISR), NULL }, - - /* find out the current status */ - - { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* shutdown - disable interrupts */ - { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, - { mk_mii_end, } - }, -}; - -#endif /* CONFIG_FEC_LXT970 */ - -/* ------------------------------------------------------------------------- */ -/* The Level one LXT971 is used on some of my custom boards */ - -#ifdef CONFIG_FCC_LXT971 - -/* register definitions for the 971 */ - -#define MII_LXT971_PCR 16 /* Port Control Register */ -#define MII_LXT971_SR2 17 /* Status Register 2 */ -#define MII_LXT971_IER 18 /* Interrupt Enable Register */ -#define MII_LXT971_ISR 19 /* Interrupt Status Register */ -#define MII_LXT971_LCR 20 /* LED Control Register */ -#define MII_LXT971_TCR 30 /* Transmit Control Register */ - -/* - * I had some nice ideas of running the MDIO faster... - * The 971 should support 8MHz and I tried it, but things acted really - * weird, so 2.5 MHz ought to be enough for anyone... - */ - -static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) -{ - volatile struct fcc_enet_private *fep = dev->priv; - uint s = fep->phy_status; - - s &= ~(PHY_STAT_SPMASK); - - if (mii_reg & 0x4000) { - if (mii_reg & 0x0200) - s |= PHY_STAT_100FDX; - else - s |= PHY_STAT_100HDX; - } else { - if (mii_reg & 0x0200) - s |= PHY_STAT_10FDX; - else - s |= PHY_STAT_10HDX; - } - if (mii_reg & 0x0008) - s |= PHY_STAT_FAULT; - - fep->phy_status = s; -} - -static phy_info_t phy_info_lxt971 = { - 0x0001378e, - "LXT971", - - (const phy_cmd_t []) { /* config */ - /* configure link capabilities to advertise */ - { mk_mii_write(MII_ADVERTISE, MII_ADVERTISE_DEFAULT), - mii_parse_anar }, - - /* enable auto-negotiation */ - { mk_mii_write(MII_BMCR, BMCR_ANENABLE), mii_parse_cr }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* startup - enable interrupts */ - { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, - - /* restart auto-negotiation */ - { mk_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART), - NULL }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* ack_int */ - /* find out the current status */ - { mk_mii_read(MII_BMSR), NULL }, - { mk_mii_read(MII_BMSR), mii_parse_sr }, - { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, - - /* we only need to read ISR to acknowledge */ - { mk_mii_read(MII_LXT971_ISR), NULL }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* shutdown - disable interrupts */ - { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, - { mk_mii_end, } - }, -}; - -#endif /* CONFIG_FCC_LXT971 */ - -/* ------------------------------------------------------------------------- */ -/* The Quality Semiconductor QS6612 is used on the RPX CLLF */ - -#ifdef CONFIG_FCC_QS6612 - -/* register definitions */ - -#define MII_QS6612_MCR 17 /* Mode Control Register */ -#define MII_QS6612_FTR 27 /* Factory Test Register */ -#define MII_QS6612_MCO 28 /* Misc. Control Register */ -#define MII_QS6612_ISR 29 /* Interrupt Source Register */ -#define MII_QS6612_IMR 30 /* Interrupt Mask Register */ -#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ - -static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) -{ - volatile struct fcc_enet_private *fep = dev->priv; - uint s = fep->phy_status; - - s &= ~(PHY_STAT_SPMASK); - - switch((mii_reg >> 2) & 7) { - case 1: s |= PHY_STAT_10HDX; break; - case 2: s |= PHY_STAT_100HDX; break; - case 5: s |= PHY_STAT_10FDX; break; - case 6: s |= PHY_STAT_100FDX; break; - } - - fep->phy_status = s; -} - -static phy_info_t phy_info_qs6612 = { - 0x00181440, - "QS6612", - - (const phy_cmd_t []) { /* config */ -// { mk_mii_write(MII_ADVERTISE, 0x061), NULL }, /* 10 Mbps */ - - /* The PHY powers up isolated on the RPX, - * so send a command to allow operation. - */ - - { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, - - /* parse cr and anar to get some info */ - - { mk_mii_read(MII_BMCR), mii_parse_cr }, - { mk_mii_read(MII_ADVERTISE), mii_parse_anar }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* startup - enable interrupts */ - { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, - { mk_mii_write(MII_BMCR, 0x1200), NULL }, /* autonegotiate */ - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* ack_int */ - - /* we need to read ISR, SR and ANER to acknowledge */ - - { mk_mii_read(MII_QS6612_ISR), NULL }, - { mk_mii_read(MII_BMSR), mii_parse_sr }, - { mk_mii_read(MII_EXPANSION), NULL }, - - /* read pcr to get info */ - - { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* shutdown - disable interrupts */ - { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, - { mk_mii_end, } - }, -}; - - -#endif /* CONFIG_FEC_QS6612 */ - - -/* ------------------------------------------------------------------------- */ -/* The Davicom DM9131 is used on the HYMOD board */ - -#ifdef CONFIG_FCC_DM9131 - -/* register definitions */ - -#define MII_DM9131_ACR 16 /* Aux. Config Register */ -#define MII_DM9131_ACSR 17 /* Aux. Config/Status Register */ -#define MII_DM9131_10TCSR 18 /* 10BaseT Config/Status Reg. */ -#define MII_DM9131_INTR 21 /* Interrupt Register */ -#define MII_DM9131_RECR 22 /* Receive Error Counter Reg. */ -#define MII_DM9131_DISCR 23 /* Disconnect Counter Register */ - -static void mii_parse_dm9131_acsr(uint mii_reg, struct net_device *dev) -{ - volatile struct fcc_enet_private *fep = dev->priv; - uint s = fep->phy_status; - - s &= ~(PHY_STAT_SPMASK); - - switch ((mii_reg >> 12) & 0xf) { - case 1: s |= PHY_STAT_10HDX; break; - case 2: s |= PHY_STAT_10FDX; break; - case 4: s |= PHY_STAT_100HDX; break; - case 8: s |= PHY_STAT_100FDX; break; - } - - fep->phy_status = s; -} - -static phy_info_t phy_info_dm9131 = { - 0x00181b80, - "DM9131", - - (const phy_cmd_t []) { /* config */ - /* parse cr and anar to get some info */ - { mk_mii_read(MII_BMCR), mii_parse_cr }, - { mk_mii_read(MII_ADVERTISE), mii_parse_anar }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* startup - enable interrupts */ - { mk_mii_write(MII_DM9131_INTR, 0x0002), NULL }, - { mk_mii_write(MII_BMCR, 0x1200), NULL }, /* autonegotiate */ - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* ack_int */ - - /* we need to read INTR, SR and ANER to acknowledge */ - - { mk_mii_read(MII_DM9131_INTR), NULL }, - { mk_mii_read(MII_BMSR), mii_parse_sr }, - { mk_mii_read(MII_EXPANSION), NULL }, - - /* read acsr to get info */ - - { mk_mii_read(MII_DM9131_ACSR), mii_parse_dm9131_acsr }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* shutdown - disable interrupts */ - { mk_mii_write(MII_DM9131_INTR, 0x0f00), NULL }, - { mk_mii_end, } - }, -}; - - -#endif /* CONFIG_FEC_DM9131 */ -#ifdef CONFIG_FCC_DM9161 -/* ------------------------------------------------------------------------- */ -/* DM9161 Control register values */ -#define MIIM_DM9161_CR_STOP 0x0400 -#define MIIM_DM9161_CR_RSTAN 0x1200 - -#define MIIM_DM9161_SCR 0x10 -#define MIIM_DM9161_SCR_INIT 0x0610 - -/* DM9161 Specified Configuration and Status Register */ -#define MIIM_DM9161_SCSR 0x11 -#define MIIM_DM9161_SCSR_100F 0x8000 -#define MIIM_DM9161_SCSR_100H 0x4000 -#define MIIM_DM9161_SCSR_10F 0x2000 -#define MIIM_DM9161_SCSR_10H 0x1000 -/* DM9161 10BT register */ -#define MIIM_DM9161_10BTCSR 0x12 -#define MIIM_DM9161_10BTCSR_INIT 0x7800 -/* DM9161 Interrupt Register */ -#define MIIM_DM9161_INTR 0x15 -#define MIIM_DM9161_INTR_PEND 0x8000 -#define MIIM_DM9161_INTR_DPLX_MASK 0x0800 -#define MIIM_DM9161_INTR_SPD_MASK 0x0400 -#define MIIM_DM9161_INTR_LINK_MASK 0x0200 -#define MIIM_DM9161_INTR_MASK 0x0100 -#define MIIM_DM9161_INTR_DPLX_CHANGE 0x0010 -#define MIIM_DM9161_INTR_SPD_CHANGE 0x0008 -#define MIIM_DM9161_INTR_LINK_CHANGE 0x0004 -#define MIIM_DM9161_INTR_INIT 0x0000 -#define MIIM_DM9161_INTR_STOP \ -(MIIM_DM9161_INTR_DPLX_MASK | MIIM_DM9161_INTR_SPD_MASK \ - | MIIM_DM9161_INTR_LINK_MASK | MIIM_DM9161_INTR_MASK) - -static void mii_parse_dm9161_sr(uint mii_reg, struct net_device * dev) -{ - volatile struct fcc_enet_private *fep = dev->priv; - uint regstat, timeout=0xffff; - - while(!(mii_reg & 0x0020) && timeout--) - { - regstat=mk_mii_read(MII_BMSR); - regstat |= fep->phy_addr <<23; - mii_reg = mii_send_receive(fep->fip,regstat); - } - - mii_parse_sr(mii_reg, dev); -} - -static void mii_parse_dm9161_scsr(uint mii_reg, struct net_device * dev) -{ - volatile struct fcc_enet_private *fep = dev->priv; - uint s = fep->phy_status; - - s &= ~(PHY_STAT_SPMASK); - switch((mii_reg >>12) & 0xf) { - case 1: - { - s |= PHY_STAT_10HDX; - printk("10BaseT Half Duplex\n"); - break; - } - case 2: - { - s |= PHY_STAT_10FDX; - printk("10BaseT Full Duplex\n"); - break; - } - case 4: - { - s |= PHY_STAT_100HDX; - printk("100BaseT Half Duplex\n"); - break; - } - case 8: - { - s |= PHY_STAT_100FDX; - printk("100BaseT Full Duplex\n"); - break; - } - } - - fep->phy_status = s; - -} - -static void mii_dm9161_wait(uint mii_reg, struct net_device *dev) -{ - int timeout = HZ; - - /* Davicom takes a bit to come up after a reset, - * so wait here for a bit */ - schedule_timeout_uninterruptible(timeout); -} - -static phy_info_t phy_info_dm9161 = { - 0x00181b88, - "Davicom DM9161E", - (const phy_cmd_t[]) { /* config */ - { mk_mii_write(MII_BMCR, MIIM_DM9161_CR_STOP), NULL}, - /* Do not bypass the scrambler/descrambler */ - { mk_mii_write(MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT), NULL}, - /* Configure 10BTCSR register */ - { mk_mii_write(MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT),NULL}, - /* Configure some basic stuff */ - { mk_mii_write(MII_BMCR, 0x1000), NULL}, - { mk_mii_read(MII_BMCR), mii_parse_cr }, - { mk_mii_read(MII_ADVERTISE), mii_parse_anar }, - { mk_mii_end,} - }, - (const phy_cmd_t[]) { /* startup */ - /* Restart Auto Negotiation */ - { mk_mii_write(MII_BMCR, MIIM_DM9161_CR_RSTAN), NULL}, - /* Status is read once to clear old link state */ - { mk_mii_read(MII_BMSR), mii_dm9161_wait}, - /* Auto-negotiate */ - { mk_mii_read(MII_BMSR), mii_parse_dm9161_sr}, - /* Read the status */ - { mk_mii_read(MIIM_DM9161_SCSR), mii_parse_dm9161_scsr}, - /* Clear any pending interrupts */ - { mk_mii_read(MIIM_DM9161_INTR), NULL}, - /* Enable Interrupts */ - { mk_mii_write(MIIM_DM9161_INTR, MIIM_DM9161_INTR_INIT), NULL}, - { mk_mii_end,} - }, - (const phy_cmd_t[]) { /* ack_int */ - { mk_mii_read(MIIM_DM9161_INTR), NULL}, -#if 0 - { mk_mii_read(MII_BMSR), NULL}, - { mk_mii_read(MII_BMSR), mii_parse_dm9161_sr}, - { mk_mii_read(MIIM_DM9161_SCSR), mii_parse_dm9161_scsr}, -#endif - { mk_mii_end,} - }, - (const phy_cmd_t[]) { /* shutdown */ - { mk_mii_read(MIIM_DM9161_INTR),NULL}, - { mk_mii_write(MIIM_DM9161_INTR, MIIM_DM9161_INTR_STOP), NULL}, - { mk_mii_end,} - }, -}; -#endif /* CONFIG_FCC_DM9161 */ - -static phy_info_t *phy_info[] = { - -#ifdef CONFIG_FCC_LXT970 - &phy_info_lxt970, -#endif /* CONFIG_FEC_LXT970 */ - -#ifdef CONFIG_FCC_LXT971 - &phy_info_lxt971, -#endif /* CONFIG_FEC_LXT971 */ - -#ifdef CONFIG_FCC_QS6612 - &phy_info_qs6612, -#endif /* CONFIG_FEC_QS6612 */ - -#ifdef CONFIG_FCC_DM9131 - &phy_info_dm9131, -#endif /* CONFIG_FEC_DM9131 */ - -#ifdef CONFIG_FCC_DM9161 - &phy_info_dm9161, -#endif /* CONFIG_FCC_DM9161 */ - -#ifdef CONFIG_FCC_GENERIC_PHY - /* Generic PHY support. This must be the last PHY in the table. - * It will be used to support any PHY that doesn't match a previous - * entry in the table. - */ - &phy_info_generic, -#endif /* CONFIG_FCC_GENERIC_PHY */ - - NULL -}; - -static void mii_display_status(struct work_struct *work) -{ - volatile struct fcc_enet_private *fep = - container_of(work, struct fcc_enet_private, phy_relink); - struct net_device *dev = fep->dev; - uint s = fep->phy_status; - - if (!fep->link && !fep->old_link) { - /* Link is still down - don't print anything */ - return; - } - - printk("%s: status: ", dev->name); - - if (!fep->link) { - printk("link down"); - } else { - printk("link up"); - - switch(s & PHY_STAT_SPMASK) { - case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break; - case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break; - case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break; - case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break; - default: - printk(", Unknown speed/duplex"); - } - - if (s & PHY_STAT_ANC) - printk(", auto-negotiation complete"); - } - - if (s & PHY_STAT_FAULT) - printk(", remote fault"); - - printk(".\n"); -} - -static void mii_display_config(struct work_struct *work) -{ - volatile struct fcc_enet_private *fep = - container_of(work, struct fcc_enet_private, - phy_display_config); - struct net_device *dev = fep->dev; - uint s = fep->phy_status; - - printk("%s: config: auto-negotiation ", dev->name); - - if (s & PHY_CONF_ANE) - printk("on"); - else - printk("off"); - - if (s & PHY_CONF_100FDX) - printk(", 100FDX"); - if (s & PHY_CONF_100HDX) - printk(", 100HDX"); - if (s & PHY_CONF_10FDX) - printk(", 10FDX"); - if (s & PHY_CONF_10HDX) - printk(", 10HDX"); - if (!(s & PHY_CONF_SPMASK)) - printk(", No speed/duplex selected?"); - - if (s & PHY_CONF_LOOP) - printk(", loopback enabled"); - - printk(".\n"); - - fep->sequence_done = 1; -} - -static void mii_relink(struct net_device *dev) -{ - struct fcc_enet_private *fep = dev->priv; - int duplex = 0; - - fep->old_link = fep->link; - fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; - -#ifdef MDIO_DEBUG - printk(" mii_relink: link=%d\n", fep->link); -#endif - - if (fep->link) { - if (fep->phy_status - & (PHY_STAT_100FDX | PHY_STAT_10FDX)) - duplex = 1; - fcc_restart(dev, duplex); -#ifdef MDIO_DEBUG - printk(" mii_relink: duplex=%d\n", duplex); -#endif - } -} - -static void mii_queue_relink(uint mii_reg, struct net_device *dev) -{ - struct fcc_enet_private *fep = dev->priv; - - mii_relink(dev); - - schedule_work(&fep->phy_relink); -} - -static void mii_queue_config(uint mii_reg, struct net_device *dev) -{ - struct fcc_enet_private *fep = dev->priv; - - schedule_work(&fep->phy_display_config); -} - -phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_BMCR), mii_queue_relink }, - { mk_mii_end, } }; -phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_BMCR), mii_queue_config }, - { mk_mii_end, } }; - - -/* Read remainder of PHY ID. -*/ -static void -mii_discover_phy3(uint mii_reg, struct net_device *dev) -{ - struct fcc_enet_private *fep; - int i; - - fep = dev->priv; - printk("mii_reg: %08x\n", mii_reg); - fep->phy_id |= (mii_reg & 0xffff); - - for(i = 0; phy_info[i]; i++) - if((phy_info[i]->id == (fep->phy_id >> 4)) || !phy_info[i]->id) - break; - - if(!phy_info[i]) - panic("%s: PHY id 0x%08x is not supported!\n", - dev->name, fep->phy_id); - - fep->phy = phy_info[i]; - fep->phy_id_done = 1; - - printk("%s: Phy @ 0x%x, type %s (0x%08x)\n", - dev->name, fep->phy_addr, fep->phy->name, fep->phy_id); -} - -/* Scan all of the MII PHY addresses looking for someone to respond - * with a valid ID. This usually happens quickly. - */ -static void -mii_discover_phy(uint mii_reg, struct net_device *dev) -{ - struct fcc_enet_private *fep; - uint phytype; - - fep = dev->priv; - - if ((phytype = (mii_reg & 0xffff)) != 0xffff) { - - /* Got first part of ID, now get remainder. */ - fep->phy_id = phytype << 16; - mii_queue(dev, mk_mii_read(MII_PHYSID2), mii_discover_phy3); - } else { - fep->phy_addr++; - if (fep->phy_addr < 32) { - mii_queue(dev, mk_mii_read(MII_PHYSID1), - mii_discover_phy); - } else { - printk("fec: No PHY device found.\n"); - } - } -} -#endif /* CONFIG_USE_MDIO */ - -#ifdef PHY_INTERRUPT -/* This interrupt occurs when the PHY detects a link change. */ -static irqreturn_t -mii_link_interrupt(int irq, void * dev_id) -{ - struct net_device *dev = dev_id; - struct fcc_enet_private *fep = dev->priv; - fcc_info_t *fip = fep->fip; - - if (fep->phy) { - /* We don't want to be interrupted by an FCC - * interrupt here. - */ - disable_irq_nosync(fip->fc_interrupt); - - mii_do_cmd(dev, fep->phy->ack_int); - /* restart and display status */ - mii_do_cmd(dev, phy_cmd_relink); - - enable_irq(fip->fc_interrupt); - } - return IRQ_HANDLED; -} -#endif /* ifdef PHY_INTERRUPT */ - -#if 0 /* This should be fixed someday */ -/* Set or clear the multicast filter for this adaptor. - * Skeleton taken from sunlance driver. - * The CPM Ethernet implementation allows Multicast as well as individual - * MAC address filtering. Some of the drivers check to make sure it is - * a group multicast address, and discard those that are not. I guess I - * will do the same for now, but just remove the test if you want - * individual filtering as well (do the upper net layers want or support - * this kind of feature?). - */ -static void -set_multicast_list(struct net_device *dev) -{ - struct fcc_enet_private *cep; - struct dev_mc_list *dmi; - u_char *mcptr, *tdptr; - volatile fcc_enet_t *ep; - int i, j; - - cep = (struct fcc_enet_private *)dev->priv; - -return; - /* Get pointer to FCC area in parameter RAM. - */ - ep = (fcc_enet_t *)dev->base_addr; - - if (dev->flags&IFF_PROMISC) { - - /* Log any net taps. */ - printk("%s: Promiscuous mode enabled.\n", dev->name); - cep->fccp->fcc_fpsmr |= FCC_PSMR_PRO; - } else { - - cep->fccp->fcc_fpsmr &= ~FCC_PSMR_PRO; - - if (dev->flags & IFF_ALLMULTI) { - /* Catch all multicast addresses, so set the - * filter to all 1's. - */ - ep->fen_gaddrh = 0xffffffff; - ep->fen_gaddrl = 0xffffffff; - } - else { - /* Clear filter and add the addresses in the list. - */ - ep->fen_gaddrh = 0; - ep->fen_gaddrl = 0; - - dmi = dev->mc_list; - - for (i=0; imc_count; i++, dmi = dmi->next) { - - /* Only support group multicast for now. - */ - if (!(dmi->dmi_addr[0] & 1)) - continue; - - /* The address in dmi_addr is LSB first, - * and taddr is MSB first. We have to - * copy bytes MSB first from dmi_addr. - */ - mcptr = (u_char *)dmi->dmi_addr + 5; - tdptr = (u_char *)&ep->fen_taddrh; - for (j=0; j<6; j++) - *tdptr++ = *mcptr--; - - /* Ask CPM to run CRC and set bit in - * filter mask. - */ - cpmp->cp_cpcr = mk_cr_cmd(cep->fip->fc_cpmpage, - cep->fip->fc_cpmblock, 0x0c, - CPM_CR_SET_GADDR) | CPM_CR_FLG; - udelay(10); - while (cpmp->cp_cpcr & CPM_CR_FLG); - } - } - } -} -#endif /* if 0 */ - - -/* Set the individual MAC address. - */ -int fcc_enet_set_mac_address(struct net_device *dev, void *p) -{ - struct sockaddr *addr= (struct sockaddr *) p; - struct fcc_enet_private *cep; - volatile fcc_enet_t *ep; - unsigned char *eap; - int i; - - cep = (struct fcc_enet_private *)(dev->priv); - ep = cep->ep; - - if (netif_running(dev)) - return -EBUSY; - - memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); - - eap = (unsigned char *) &(ep->fen_paddrh); - for (i=5; i>=0; i--) - *eap++ = addr->sa_data[i]; - - return 0; -} - - -/* Initialize the CPM Ethernet on FCC. - */ -static int __init fec_enet_init(void) -{ - struct net_device *dev; - struct fcc_enet_private *cep; - fcc_info_t *fip; - int i, np, err; - volatile cpm2_map_t *immap; - volatile iop_cpm2_t *io; - - immap = (cpm2_map_t *)CPM_MAP_ADDR; /* and to internal registers */ - io = &immap->im_ioport; - - np = sizeof(fcc_ports) / sizeof(fcc_info_t); - fip = fcc_ports; - - while (np-- > 0) { - /* Create an Ethernet device instance. - */ - dev = alloc_etherdev(sizeof(*cep)); - if (!dev) - return -ENOMEM; - - cep = dev->priv; - spin_lock_init(&cep->lock); - cep->fip = fip; - - init_fcc_shutdown(fip, cep, immap); - init_fcc_ioports(fip, io, immap); - init_fcc_param(fip, dev, immap); - - dev->base_addr = (unsigned long)(cep->ep); - - /* The CPM Ethernet specific entries in the device - * structure. - */ - dev->open = fcc_enet_open; - dev->hard_start_xmit = fcc_enet_start_xmit; - dev->tx_timeout = fcc_enet_timeout; - dev->watchdog_timeo = TX_TIMEOUT; - dev->stop = fcc_enet_close; - dev->get_stats = fcc_enet_get_stats; - /* dev->set_multicast_list = set_multicast_list; */ - dev->set_mac_address = fcc_enet_set_mac_address; - - init_fcc_startup(fip, dev); - - err = register_netdev(dev); - if (err) { - free_netdev(dev); - return err; - } - - printk("%s: FCC ENET Version 0.3, ", dev->name); - for (i=0; i<5; i++) - printk("%02x:", dev->dev_addr[i]); - printk("%02x\n", dev->dev_addr[5]); - -#ifdef CONFIG_USE_MDIO - /* Queue up command to detect the PHY and initialize the - * remainder of the interface. - */ - cep->phy_id_done = 0; - cep->phy_addr = fip->fc_phyaddr; - mii_queue(dev, mk_mii_read(MII_PHYSID1), mii_discover_phy); - INIT_WORK(&cep->phy_relink, mii_display_status); - INIT_WORK(&cep->phy_display_config, mii_display_config); - cep->dev = dev; -#endif /* CONFIG_USE_MDIO */ - - fip++; - } - - return 0; -} -module_init(fec_enet_init); - -/* Make sure the device is shut down during initialization. -*/ -static void __init -init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep, - volatile cpm2_map_t *immap) -{ - volatile fcc_enet_t *ep; - volatile fcc_t *fccp; - - /* Get pointer to FCC area in parameter RAM. - */ - ep = (fcc_enet_t *)(&immap->im_dprambase[fip->fc_proff]); - - /* And another to the FCC register area. - */ - fccp = (volatile fcc_t *)(&immap->im_fcc[fip->fc_fccnum]); - cep->fccp = fccp; /* Keep the pointers handy */ - cep->ep = ep; - - /* Disable receive and transmit in case someone left it running. - */ - fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT); -} - -/* Initialize the I/O pins for the FCC Ethernet. -*/ -static void __init -init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io, - volatile cpm2_map_t *immap) -{ - - /* FCC1 pins are on port A/C. FCC2/3 are port B/C. - */ - if (fip->fc_proff == PROFF_FCC1) { - /* Configure port A and C pins for FCC1 Ethernet. - */ - io->iop_pdira &= ~PA1_DIRA_BOUT; - io->iop_pdira |= PA1_DIRA_BIN; - io->iop_psora &= ~PA1_PSORA_BOUT; - io->iop_psora |= PA1_PSORA_BIN; - io->iop_ppara |= (PA1_DIRA_BOUT | PA1_DIRA_BIN); - } - if (fip->fc_proff == PROFF_FCC2) { - /* Configure port B and C pins for FCC Ethernet. - */ - io->iop_pdirb &= ~PB2_DIRB_BOUT; - io->iop_pdirb |= PB2_DIRB_BIN; - io->iop_psorb &= ~PB2_PSORB_BOUT; - io->iop_psorb |= PB2_PSORB_BIN; - io->iop_pparb |= (PB2_DIRB_BOUT | PB2_DIRB_BIN); - } - if (fip->fc_proff == PROFF_FCC3) { - /* Configure port B and C pins for FCC Ethernet. - */ - io->iop_pdirb &= ~PB3_DIRB_BOUT; - io->iop_pdirb |= PB3_DIRB_BIN; - io->iop_psorb &= ~PB3_PSORB_BOUT; - io->iop_psorb |= PB3_PSORB_BIN; - io->iop_pparb |= (PB3_DIRB_BOUT | PB3_DIRB_BIN); - - io->iop_pdirc &= ~PC3_DIRC_BOUT; - io->iop_pdirc |= PC3_DIRC_BIN; - io->iop_psorc &= ~PC3_PSORC_BOUT; - io->iop_psorc |= PC3_PSORC_BIN; - io->iop_pparc |= (PC3_DIRC_BOUT | PC3_DIRC_BIN); - - } - - /* Port C has clocks...... - */ - io->iop_psorc &= ~(fip->fc_trxclocks); - io->iop_pdirc &= ~(fip->fc_trxclocks); - io->iop_pparc |= fip->fc_trxclocks; - -#ifdef CONFIG_USE_MDIO - /* ....and the MII serial clock/data. - */ - io->iop_pdatc |= (fip->fc_mdio | fip->fc_mdck); - io->iop_podrc &= ~(fip->fc_mdio | fip->fc_mdck); - io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck); - io->iop_pparc &= ~(fip->fc_mdio | fip->fc_mdck); -#endif /* CONFIG_USE_MDIO */ - - /* Configure Serial Interface clock routing. - * First, clear all FCC bits to zero, - * then set the ones we want. - */ - immap->im_cpmux.cmx_fcr &= ~(fip->fc_clockmask); - immap->im_cpmux.cmx_fcr |= fip->fc_clockroute; -} - -static void __init -init_fcc_param(fcc_info_t *fip, struct net_device *dev, - volatile cpm2_map_t *immap) -{ - unsigned char *eap; - unsigned long mem_addr; - bd_t *bd; - int i, j; - struct fcc_enet_private *cep; - volatile fcc_enet_t *ep; - volatile cbd_t *bdp; - volatile cpm_cpm2_t *cp; - - cep = (struct fcc_enet_private *)(dev->priv); - ep = cep->ep; - cp = cpmp; - - bd = (bd_t *)__res; - - /* Zero the whole thing.....I must have missed some individually. - * It works when I do this. - */ - memset((char *)ep, 0, sizeof(fcc_enet_t)); - - /* Allocate space for the buffer descriptors from regular memory. - * Initialize base addresses for the buffer descriptors. - */ - cep->rx_bd_base = kmalloc(sizeof(cbd_t) * RX_RING_SIZE, - GFP_KERNEL | GFP_DMA); - ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base); - cep->tx_bd_base = kmalloc(sizeof(cbd_t) * TX_RING_SIZE, - GFP_KERNEL | GFP_DMA); - ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base); - - cep->dirty_tx = cep->cur_tx = cep->tx_bd_base; - cep->cur_rx = cep->rx_bd_base; - - ep->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24; - ep->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24; - - /* Set maximum bytes per receive buffer. - * It must be a multiple of 32. - */ - ep->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; - - /* Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - */ - mem_addr = CPM_FCC_SPECIAL_BASE + (fip->fc_fccnum * 128); - ep->fen_genfcc.fcc_riptr = mem_addr; - ep->fen_genfcc.fcc_tiptr = mem_addr+32; - ep->fen_padptr = mem_addr+64; - memset((char *)(&(immap->im_dprambase[(mem_addr+64)])), 0x88, 32); - - ep->fen_genfcc.fcc_rbptr = 0; - ep->fen_genfcc.fcc_tbptr = 0; - ep->fen_genfcc.fcc_rcrc = 0; - ep->fen_genfcc.fcc_tcrc = 0; - ep->fen_genfcc.fcc_res1 = 0; - ep->fen_genfcc.fcc_res2 = 0; - - ep->fen_camptr = 0; /* CAM isn't used in this driver */ - - /* Set CRC preset and mask. - */ - ep->fen_cmask = 0xdebb20e3; - ep->fen_cpres = 0xffffffff; - - ep->fen_crcec = 0; /* CRC Error counter */ - ep->fen_alec = 0; /* alignment error counter */ - ep->fen_disfc = 0; /* discard frame counter */ - ep->fen_retlim = 15; /* Retry limit threshold */ - ep->fen_pper = 0; /* Normal persistence */ - - /* Clear hash filter tables. - */ - ep->fen_gaddrh = 0; - ep->fen_gaddrl = 0; - ep->fen_iaddrh = 0; - ep->fen_iaddrl = 0; - - /* Clear the Out-of-sequence TxBD. - */ - ep->fen_tfcstat = 0; - ep->fen_tfclen = 0; - ep->fen_tfcptr = 0; - - ep->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - ep->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ - - /* Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So, far we have only been given one Ethernet address. We make - * it unique by setting a few bits in the upper byte of the - * non-static part of the address. - */ - eap = (unsigned char *)&(ep->fen_paddrh); - for (i=5; i>=0; i--) { - -/* - * The EP8260 only uses FCC3, so we can safely give it the real - * MAC address. - */ -#ifdef CONFIG_SBC82xx - if (i == 5) { - /* bd->bi_enetaddr holds the SCC0 address; the FCC - devices count up from there */ - dev->dev_addr[i] = bd->bi_enetaddr[i] & ~3; - dev->dev_addr[i] += 1 + fip->fc_fccnum; - *eap++ = dev->dev_addr[i]; - } -#else -#ifndef CONFIG_RPX8260 - if (i == 3) { - dev->dev_addr[i] = bd->bi_enetaddr[i]; - dev->dev_addr[i] |= (1 << (7 - fip->fc_fccnum)); - *eap++ = dev->dev_addr[i]; - } else -#endif - { - *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i]; - } -#endif - } - - ep->fen_taddrh = 0; - ep->fen_taddrm = 0; - ep->fen_taddrl = 0; - - ep->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */ - ep->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */ - - /* Clear stat counters, in case we ever enable RMON. - */ - ep->fen_octc = 0; - ep->fen_colc = 0; - ep->fen_broc = 0; - ep->fen_mulc = 0; - ep->fen_uspc = 0; - ep->fen_frgc = 0; - ep->fen_ospc = 0; - ep->fen_jbrc = 0; - ep->fen_p64c = 0; - ep->fen_p65c = 0; - ep->fen_p128c = 0; - ep->fen_p256c = 0; - ep->fen_p512c = 0; - ep->fen_p1024c = 0; - - ep->fen_rfthr = 0; /* Suggested by manual */ - ep->fen_rfcnt = 0; - ep->fen_cftype = 0; - - /* Now allocate the host memory pages and initialize the - * buffer descriptors. - */ - bdp = cep->tx_bd_base; - for (i=0; icbd_sc = 0; - bdp->cbd_datlen = 0; - bdp->cbd_bufaddr = 0; - bdp++; - } - - /* Set the last buffer to wrap. - */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; - - bdp = cep->rx_bd_base; - for (i=0; icbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR; - bdp->cbd_datlen = 0; - bdp->cbd_bufaddr = __pa(mem_addr); - mem_addr += FCC_ENET_RX_FRSIZE; - bdp++; - } - } - - /* Set the last buffer to wrap. - */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; - - /* Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock, 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - cep->skb_cur = cep->skb_dirty = 0; -} - -/* Let 'er rip. -*/ -static void __init -init_fcc_startup(fcc_info_t *fip, struct net_device *dev) -{ - volatile fcc_t *fccp; - struct fcc_enet_private *cep; - - cep = (struct fcc_enet_private *)(dev->priv); - fccp = cep->fccp; - -#ifdef CONFIG_RPX8260 -#ifdef PHY_INTERRUPT - /* Route PHY interrupt to IRQ. The following code only works for - * IRQ1 - IRQ7. It does not work for Port C interrupts. - */ - *((volatile u_char *) (RPX_CSR_ADDR + 13)) &= ~BCSR13_FETH_IRQMASK; - *((volatile u_char *) (RPX_CSR_ADDR + 13)) |= - ((PHY_INTERRUPT - SIU_INT_IRQ1 + 1) << 4); -#endif - /* Initialize MDIO pins. */ - *((volatile u_char *) (RPX_CSR_ADDR + 4)) &= ~BCSR4_MII_MDC; - *((volatile u_char *) (RPX_CSR_ADDR + 4)) |= - BCSR4_MII_READ | BCSR4_MII_MDIO; - /* Enable external LXT971 PHY. */ - *((volatile u_char *) (RPX_CSR_ADDR + 4)) |= BCSR4_EN_PHY; - udelay(1000); - *((volatile u_char *) (RPX_CSR_ADDR+ 4)) |= BCSR4_EN_MII; - udelay(1000); -#endif /* ifdef CONFIG_RPX8260 */ - - fccp->fcc_fcce = 0xffff; /* Clear any pending events */ - - /* Leave FCC interrupts masked for now. Will be unmasked by - * fcc_restart(). - */ - fccp->fcc_fccm = 0; - - /* Install our interrupt handler. - */ - if (request_irq(fip->fc_interrupt, fcc_enet_interrupt, 0, "fenet", - dev) < 0) - printk("Can't get FCC IRQ %d\n", fip->fc_interrupt); - -#ifdef PHY_INTERRUPT - /* Make IRQn edge triggered. This does not work if PHY_INTERRUPT is - * on Port C. - */ - ((volatile cpm2_map_t *) CPM_MAP_ADDR)->im_intctl.ic_siexr |= - (1 << (14 - (PHY_INTERRUPT - SIU_INT_IRQ1))); - - if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0, - "mii", dev) < 0) - printk(KERN_CRIT "Can't get MII IRQ %d\n", PHY_INTERRUPT); -#endif /* PHY_INTERRUPT */ - - /* Set GFMR to enable Ethernet operating mode. - */ - fccp->fcc_gfmr = (FCC_GFMR_TCI | FCC_GFMR_MODE_ENET); - - /* Set sync/delimiters. - */ - fccp->fcc_fdsr = 0xd555; - - /* Set protocol specific processing mode for Ethernet. - * This has to be adjusted for Full Duplex operation after we can - * determine how to detect that. - */ - fccp->fcc_fpsmr = FCC_PSMR_ENCRC; - -#ifdef CONFIG_PQ2ADS - /* Enable the PHY. */ - *(volatile uint *)(BCSR_ADDR + 4) &= ~BCSR1_FETHIEN; - *(volatile uint *)(BCSR_ADDR + 4) |= BCSR1_FETH_RST; -#endif -#if defined(CONFIG_PQ2ADS) || defined(CONFIG_PQ2FADS) - /* Enable the 2nd PHY. */ - *(volatile uint *)(BCSR_ADDR + 12) &= ~BCSR3_FETHIEN2; - *(volatile uint *)(BCSR_ADDR + 12) |= BCSR3_FETH2_RST; -#endif - -#if defined(CONFIG_USE_MDIO) || defined(CONFIG_TQM8260) - /* start in full duplex mode, and negotiate speed - */ - fcc_restart (dev, 1); -#else - /* start in half duplex mode - */ - fcc_restart (dev, 0); -#endif -} - -#ifdef CONFIG_USE_MDIO -/* MII command/status interface. - * I'm not going to describe all of the details. You can find the - * protocol definition in many other places, including the data sheet - * of most PHY parts. - * I wonder what "they" were thinking (maybe weren't) when they leave - * the I2C in the CPM but I have to toggle these bits...... - */ -#ifdef CONFIG_RPX8260 - /* The EP8260 has the MDIO pins in a BCSR instead of on Port C - * like most other boards. - */ -#define MDIO_ADDR ((volatile u_char *)(RPX_CSR_ADDR + 4)) -#define MAKE_MDIO_OUTPUT *MDIO_ADDR &= ~BCSR4_MII_READ -#define MAKE_MDIO_INPUT *MDIO_ADDR |= BCSR4_MII_READ | BCSR4_MII_MDIO -#define OUT_MDIO(bit) \ - if (bit) \ - *MDIO_ADDR |= BCSR4_MII_MDIO; \ - else \ - *MDIO_ADDR &= ~BCSR4_MII_MDIO; -#define IN_MDIO (*MDIO_ADDR & BCSR4_MII_MDIO) -#define OUT_MDC(bit) \ - if (bit) \ - *MDIO_ADDR |= BCSR4_MII_MDC; \ - else \ - *MDIO_ADDR &= ~BCSR4_MII_MDC; -#else /* ifdef CONFIG_RPX8260 */ - /* This is for the usual case where the MDIO pins are on Port C. - */ -#define MDIO_ADDR (((volatile cpm2_map_t *)CPM_MAP_ADDR)->im_ioport) -#define MAKE_MDIO_OUTPUT MDIO_ADDR.iop_pdirc |= fip->fc_mdio -#define MAKE_MDIO_INPUT MDIO_ADDR.iop_pdirc &= ~fip->fc_mdio -#define OUT_MDIO(bit) \ - if (bit) \ - MDIO_ADDR.iop_pdatc |= fip->fc_mdio; \ - else \ - MDIO_ADDR.iop_pdatc &= ~fip->fc_mdio; -#define IN_MDIO ((MDIO_ADDR.iop_pdatc) & fip->fc_mdio) -#define OUT_MDC(bit) \ - if (bit) \ - MDIO_ADDR.iop_pdatc |= fip->fc_mdck; \ - else \ - MDIO_ADDR.iop_pdatc &= ~fip->fc_mdck; -#endif /* ifdef CONFIG_RPX8260 */ - -static uint -mii_send_receive(fcc_info_t *fip, uint cmd) -{ - uint retval; - int read_op, i, off; - const int us = 1; - - read_op = ((cmd & 0xf0000000) == 0x60000000); - - /* Write preamble - */ - OUT_MDIO(1); - MAKE_MDIO_OUTPUT; - OUT_MDIO(1); - for (i = 0; i < 32; i++) - { - udelay(us); - OUT_MDC(1); - udelay(us); - OUT_MDC(0); - } - - /* Write data - */ - for (i = 0, off = 31; i < (read_op ? 14 : 32); i++, --off) - { - OUT_MDIO((cmd >> off) & 0x00000001); - udelay(us); - OUT_MDC(1); - udelay(us); - OUT_MDC(0); - } - - retval = cmd; - - if (read_op) - { - retval >>= 16; - - MAKE_MDIO_INPUT; - udelay(us); - OUT_MDC(1); - udelay(us); - OUT_MDC(0); - - for (i = 0; i < 16; i++) - { - udelay(us); - OUT_MDC(1); - udelay(us); - retval <<= 1; - if (IN_MDIO) - retval++; - OUT_MDC(0); - } - } - - MAKE_MDIO_INPUT; - udelay(us); - OUT_MDC(1); - udelay(us); - OUT_MDC(0); - - return retval; -} -#endif /* CONFIG_USE_MDIO */ - -static void -fcc_stop(struct net_device *dev) -{ - struct fcc_enet_private *fep= (struct fcc_enet_private *)(dev->priv); - volatile fcc_t *fccp = fep->fccp; - fcc_info_t *fip = fep->fip; - volatile fcc_enet_t *ep = fep->ep; - volatile cpm_cpm2_t *cp = cpmp; - volatile cbd_t *bdp; - int i; - - if ((fccp->fcc_gfmr & (FCC_GFMR_ENR | FCC_GFMR_ENT)) == 0) - return; /* already down */ - - fccp->fcc_fccm = 0; - - /* issue the graceful stop tx command */ - while (cp->cp_cpcr & CPM_CR_FLG); - cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock, - 0x0c, CPM_CR_GRA_STOP_TX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - /* Disable transmit/receive */ - fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT); - - /* issue the restart tx command */ - fccp->fcc_fcce = FCC_ENET_GRA; - while (cp->cp_cpcr & CPM_CR_FLG); - cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock, - 0x0c, CPM_CR_RESTART_TX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - /* free tx buffers */ - fep->skb_cur = fep->skb_dirty = 0; - for (i=0; i<=TX_RING_MOD_MASK; i++) { - if (fep->tx_skbuff[i] != NULL) { - dev_kfree_skb(fep->tx_skbuff[i]); - fep->tx_skbuff[i] = NULL; - } - } - fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; - fep->tx_free = TX_RING_SIZE; - ep->fen_genfcc.fcc_tbptr = ep->fen_genfcc.fcc_tbase; - - /* Initialize the tx buffer descriptors. */ - bdp = fep->tx_bd_base; - for (i=0; icbd_sc = 0; - bdp->cbd_datlen = 0; - bdp->cbd_bufaddr = 0; - bdp++; - } - /* Set the last buffer to wrap. */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; -} - -static void -fcc_restart(struct net_device *dev, int duplex) -{ - struct fcc_enet_private *fep = (struct fcc_enet_private *)(dev->priv); - volatile fcc_t *fccp = fep->fccp; - - /* stop any transmissions in progress */ - fcc_stop(dev); - - if (duplex) - fccp->fcc_fpsmr |= FCC_PSMR_FDE | FCC_PSMR_LPB; - else - fccp->fcc_fpsmr &= ~(FCC_PSMR_FDE | FCC_PSMR_LPB); - - /* Enable interrupts for transmit error, complete frame - * received, and any transmit buffer we have also set the - * interrupt flag. - */ - fccp->fcc_fccm = (FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB); - - /* Enable transmit/receive */ - fccp->fcc_gfmr |= FCC_GFMR_ENR | FCC_GFMR_ENT; -} - -static int -fcc_enet_open(struct net_device *dev) -{ - struct fcc_enet_private *fep = dev->priv; - -#ifdef CONFIG_USE_MDIO - fep->sequence_done = 0; - fep->link = 0; - - if (fep->phy) { - fcc_restart(dev, 0); /* always start in half-duplex */ - mii_do_cmd(dev, fep->phy->ack_int); - mii_do_cmd(dev, fep->phy->config); - mii_do_cmd(dev, phy_cmd_config); /* display configuration */ - while(!fep->sequence_done) - schedule(); - - mii_do_cmd(dev, fep->phy->startup); - netif_start_queue(dev); - return 0; /* Success */ - } - return -ENODEV; /* No PHY we understand */ -#else - fep->link = 1; - fcc_restart(dev, 0); /* always start in half-duplex */ - netif_start_queue(dev); - return 0; /* Always succeed */ -#endif /* CONFIG_USE_MDIO */ -} - diff --git a/arch/ppc/8xx_io/Kconfig b/arch/ppc/8xx_io/Kconfig deleted file mode 100644 index c623e44f01ad..000000000000 --- a/arch/ppc/8xx_io/Kconfig +++ /dev/null @@ -1,134 +0,0 @@ -# -# MPC8xx Communication options -# - -menu "MPC8xx CPM Options" - depends on 8xx - -config SCC_ENET - bool "CPM SCC Ethernet" - depends on NET_ETHERNET - help - Enable Ethernet support via the Motorola MPC8xx serial - communications controller. - -choice - prompt "SCC used for Ethernet" - depends on SCC_ENET - default SCC1_ENET - -config SCC1_ENET - bool "SCC1" - help - Use MPC8xx serial communications controller 1 to drive Ethernet - (default). - -config SCC2_ENET - bool "SCC2" - help - Use MPC8xx serial communications controller 2 to drive Ethernet. - -config SCC3_ENET - bool "SCC3" - help - Use MPC8xx serial communications controller 3 to drive Ethernet. - -endchoice - -config FEC_ENET - bool "860T FEC Ethernet" - depends on NET_ETHERNET - help - Enable Ethernet support via the Fast Ethernet Controller (FCC) on - the Motorola MPC8260. - -config USE_MDIO - bool "Use MDIO for PHY configuration" - depends on FEC_ENET - help - On some boards the hardware configuration of the ethernet PHY can be - used without any software interaction over the MDIO interface, so - all MII code can be omitted. Say N here if unsure or if you don't - need link status reports. - -config FEC_AM79C874 - bool "Support AMD79C874 PHY" - depends on USE_MDIO - -config FEC_LXT970 - bool "Support LXT970 PHY" - depends on USE_MDIO - -config FEC_LXT971 - bool "Support LXT971 PHY" - depends on USE_MDIO - -config FEC_QS6612 - bool "Support QS6612 PHY" - depends on USE_MDIO - -config ENET_BIG_BUFFERS - bool "Use Big CPM Ethernet Buffers" - depends on SCC_ENET || FEC_ENET - help - Allocate large buffers for MPC8xx Ethernet. Increases throughput - and decreases the likelihood of dropped packets, but costs memory. - -# This doesn't really belong here, but it is convenient to ask -# 8xx specific questions. -comment "Generic MPC8xx Options" - -config 8xx_COPYBACK - bool "Copy-Back Data Cache (else Writethrough)" - help - Saying Y here will cause the cache on an MPC8xx processor to be used - in Copy-Back mode. If you say N here, it is used in Writethrough - mode. - - If in doubt, say Y here. - -config 8xx_CPU6 - bool "CPU6 Silicon Errata (860 Pre Rev. C)" - help - MPC860 CPUs, prior to Rev C have some bugs in the silicon, which - require workarounds for Linux (and most other OSes to work). If you - get a BUG() very early in boot, this might fix the problem. For - more details read the document entitled "MPC860 Family Device Errata - Reference" on Motorola's website. This option also incurs a - performance hit. - - If in doubt, say N here. - -choice - prompt "Microcode patch selection" - default NO_UCODE_PATCH - help - Help not implemented yet, coming soon. - -config NO_UCODE_PATCH - bool "None" - -config USB_SOF_UCODE_PATCH - bool "USB SOF patch" - help - Help not implemented yet, coming soon. - -config I2C_SPI_UCODE_PATCH - bool "I2C/SPI relocation patch" - help - Help not implemented yet, coming soon. - -config I2C_SPI_SMC1_UCODE_PATCH - bool "I2C/SPI/SMC1 relocation patch" - help - Help not implemented yet, coming soon. - -endchoice - -config UCODE_PATCH - bool - default y - depends on !NO_UCODE_PATCH - -endmenu - diff --git a/arch/ppc/8xx_io/Makefile b/arch/ppc/8xx_io/Makefile deleted file mode 100644 index 1051a06df7e0..000000000000 --- a/arch/ppc/8xx_io/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile for the linux MPC8xx ppc-specific parts of comm processor -# - -obj-y := commproc.o - -obj-$(CONFIG_FEC_ENET) += fec.o -obj-$(CONFIG_SCC_ENET) += enet.o -obj-$(CONFIG_UCODE_PATCH) += micropatch.o diff --git a/arch/ppc/8xx_io/commproc.c b/arch/ppc/8xx_io/commproc.c deleted file mode 100644 index 752443df5ecf..000000000000 --- a/arch/ppc/8xx_io/commproc.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * General Purpose functions for the global management of the - * Communication Processor Module. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - * The amount of space available is platform dependent. On the - * MBX, the EPPC software loads additional microcode into the - * communication processor, and uses some of the DP ram for this - * purpose. Current, the first 512 bytes and the last 256 bytes of - * memory are used. Right now I am conservative and only use the - * memory that can never be used for microcode. If there are - * applications that require more DP ram, we can expand the boundaries - * but then we have to be careful of any downloaded microcode. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define immr_map(member) \ -({ \ - u32 offset = offsetof(immap_t, member); \ - void *addr = ioremap (IMAP_ADDR + offset, \ - FIELD_SIZEOF(immap_t, member)); \ - addr; \ -}) - -#define immr_map_size(member, size) \ -({ \ - u32 offset = offsetof(immap_t, member); \ - void *addr = ioremap (IMAP_ADDR + offset, size); \ - addr; \ -}) - -static void m8xx_cpm_dpinit(void); -cpm8xx_t *cpmp; /* Pointer to comm processor space */ - -/* CPM interrupt vector functions. -*/ -struct cpm_action { - void (*handler)(void *); - void *dev_id; -}; -static struct cpm_action cpm_vecs[CPMVEC_NR]; -static irqreturn_t cpm_interrupt(int irq, void * dev); -static irqreturn_t cpm_error_interrupt(int irq, void *dev); -/* Define a table of names to identify CPM interrupt handlers in - * /proc/interrupts. - */ -const char *cpm_int_name[] = - { "error", "PC4", "PC5", "SMC2", - "SMC1", "SPI", "PC6", "Timer 4", - "", "PC7", "PC8", "PC9", - "Timer 3", "", "PC10", "PC11", - "I2C", "RISC Timer", "Timer 2", "", - "IDMA2", "IDMA1", "SDMA error", "PC12", - "PC13", "Timer 1", "PC14", "SCC4", - "SCC3", "SCC2", "SCC1", "PC15" - }; - -static void -cpm_mask_irq(unsigned int irq) -{ - int cpm_vec = irq - CPM_IRQ_OFFSET; - - clrbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec)); -} - -static void -cpm_unmask_irq(unsigned int irq) -{ - int cpm_vec = irq - CPM_IRQ_OFFSET; - - setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec)); -} - -static void -cpm_ack(unsigned int irq) -{ - /* We do not need to do anything here. */ -} - -static void -cpm_eoi(unsigned int irq) -{ - int cpm_vec = irq - CPM_IRQ_OFFSET; - - out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr, (1 << cpm_vec)); -} - -struct hw_interrupt_type cpm_pic = { - .typename = " CPM ", - .enable = cpm_unmask_irq, - .disable = cpm_mask_irq, - .ack = cpm_ack, - .end = cpm_eoi, -}; - -void -m8xx_cpm_reset(void) -{ - volatile immap_t *imp; - volatile cpm8xx_t *commproc; - - imp = (immap_t *)IMAP_ADDR; - commproc = (cpm8xx_t *)&imp->im_cpm; - -#ifdef CONFIG_UCODE_PATCH - /* Perform a reset. - */ - commproc->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG); - - /* Wait for it. - */ - while (commproc->cp_cpcr & CPM_CR_FLG); - - cpm_load_patch(imp); -#endif - - /* Set SDMA Bus Request priority 5. - * On 860T, this also enables FEC priority 6. I am not sure - * this is what we really want for some applications, but the - * manual recommends it. - * Bit 25, FAM can also be set to use FEC aggressive mode (860T). - */ - out_be32(&imp->im_siu_conf.sc_sdcr, 1), - - /* Reclaim the DP memory for our use. */ - m8xx_cpm_dpinit(); - - /* Tell everyone where the comm processor resides. - */ - cpmp = (cpm8xx_t *)commproc; -} - -/* This is called during init_IRQ. We used to do it above, but this - * was too early since init_IRQ was not yet called. - */ -static struct irqaction cpm_error_irqaction = { - .handler = cpm_error_interrupt, - .mask = CPU_MASK_NONE, -}; -static struct irqaction cpm_interrupt_irqaction = { - .handler = cpm_interrupt, - .mask = CPU_MASK_NONE, - .name = "CPM cascade", -}; - -void -cpm_interrupt_init(void) -{ - int i; - - /* Initialize the CPM interrupt controller. - */ - out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, - (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | - ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK); - out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, 0); - - /* install the CPM interrupt controller routines for the CPM - * interrupt vectors - */ - for ( i = CPM_IRQ_OFFSET ; i < CPM_IRQ_OFFSET + NR_CPM_INTS ; i++ ) - irq_desc[i].chip = &cpm_pic; - - /* Set our interrupt handler with the core CPU. */ - if (setup_irq(CPM_INTERRUPT, &cpm_interrupt_irqaction)) - panic("Could not allocate CPM IRQ!"); - - /* Install our own error handler. */ - cpm_error_irqaction.name = cpm_int_name[CPMVEC_ERROR]; - if (setup_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, &cpm_error_irqaction)) - panic("Could not allocate CPM error IRQ!"); - - setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, CICR_IEN); -} - -/* - * Get the CPM interrupt vector. - */ -int -cpm_get_irq(void) -{ - int cpm_vec; - - /* Get the vector by setting the ACK bit and then reading - * the register. - */ - out_be16(&((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr, 1); - cpm_vec = in_be16(&((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr); - cpm_vec >>= 11; - - return cpm_vec; -} - -/* CPM interrupt controller cascade interrupt. -*/ -static irqreturn_t -cpm_interrupt(int irq, void * dev) -{ - /* This interrupt handler never actually gets called. It is - * installed only to unmask the CPM cascade interrupt in the SIU - * and to make the CPM cascade interrupt visible in /proc/interrupts. - */ - return IRQ_HANDLED; -} - -/* The CPM can generate the error interrupt when there is a race condition - * between generating and masking interrupts. All we have to do is ACK it - * and return. This is a no-op function so we don't need any special - * tests in the interrupt handler. - */ -static irqreturn_t -cpm_error_interrupt(int irq, void *dev) -{ - return IRQ_HANDLED; -} - -/* A helper function to translate the handler prototype required by - * request_irq() to the handler prototype required by cpm_install_handler(). - */ -static irqreturn_t -cpm_handler_helper(int irq, void *dev_id) -{ - int cpm_vec = irq - CPM_IRQ_OFFSET; - - (*cpm_vecs[cpm_vec].handler)(dev_id); - - return IRQ_HANDLED; -} - -/* Install a CPM interrupt handler. - * This routine accepts a CPM interrupt vector in the range 0 to 31. - * This routine is retained for backward compatibility. Rather than using - * this routine to install a CPM interrupt handler, you can now use - * request_irq() with an IRQ in the range CPM_IRQ_OFFSET to - * CPM_IRQ_OFFSET + NR_CPM_INTS - 1 (16 to 47). - * - * Notice that the prototype of the interrupt handler function must be - * different depending on whether you install the handler with - * request_irq() or cpm_install_handler(). - */ -void -cpm_install_handler(int cpm_vec, void (*handler)(void *), void *dev_id) -{ - int err; - - /* If null handler, assume we are trying to free the IRQ. - */ - if (!handler) { - free_irq(CPM_IRQ_OFFSET + cpm_vec, dev_id); - return; - } - - if (cpm_vecs[cpm_vec].handler != 0) - printk(KERN_INFO "CPM interrupt %x replacing %x\n", - (uint)handler, (uint)cpm_vecs[cpm_vec].handler); - cpm_vecs[cpm_vec].handler = handler; - cpm_vecs[cpm_vec].dev_id = dev_id; - - if ((err = request_irq(CPM_IRQ_OFFSET + cpm_vec, cpm_handler_helper, - 0, cpm_int_name[cpm_vec], dev_id))) - printk(KERN_ERR "request_irq() returned %d for CPM vector %d\n", - err, cpm_vec); -} - -/* Free a CPM interrupt handler. - * This routine accepts a CPM interrupt vector in the range 0 to 31. - * This routine is retained for backward compatibility. - */ -void -cpm_free_handler(int cpm_vec) -{ - request_irq(CPM_IRQ_OFFSET + cpm_vec, NULL, 0, 0, - cpm_vecs[cpm_vec].dev_id); - - cpm_vecs[cpm_vec].handler = NULL; - cpm_vecs[cpm_vec].dev_id = NULL; -} - -/* Set a baud rate generator. This needs lots of work. There are - * four BRGs, any of which can be wired to any channel. - * The internal baud rate clock is the system clock divided by 16. - * This assumes the baudrate is 16x oversampled by the uart. - */ -#define BRG_INT_CLK (((bd_t *)__res)->bi_intfreq) -#define BRG_UART_CLK (BRG_INT_CLK/16) -#define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16) - -void -cpm_setbrg(uint brg, uint rate) -{ - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - bp = (uint *)&cpmp->cp_brgc1; - bp += brg; - /* The BRG has a 12-bit counter. For really slow baud rates (or - * really fast processors), we may have to further divide by 16. - */ - if (((BRG_UART_CLK / rate) - 1) < 4096) - *bp = (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN; - else - *bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) | - CPM_BRG_EN | CPM_BRG_DIV16; -} - -/* - * dpalloc / dpfree bits. - */ -static spinlock_t cpm_dpmem_lock; -/* - * 16 blocks should be enough to satisfy all requests - * until the memory subsystem goes up... - */ -static rh_block_t cpm_boot_dpmem_rh_block[16]; -static rh_info_t cpm_dpmem_info; - -#define CPM_DPMEM_ALIGNMENT 8 -static u8* dpram_vbase; -static uint dpram_pbase; - -void m8xx_cpm_dpinit(void) -{ - spin_lock_init(&cpm_dpmem_lock); - - dpram_vbase = immr_map_size(im_cpm.cp_dpmem, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE); - dpram_pbase = (uint)&((immap_t *)IMAP_ADDR)->im_cpm.cp_dpmem; - - /* Initialize the info header */ - rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT, - sizeof(cpm_boot_dpmem_rh_block) / - sizeof(cpm_boot_dpmem_rh_block[0]), - cpm_boot_dpmem_rh_block); - - /* - * Attach the usable dpmem area. - * XXX: This is actually crap. CPM_DATAONLY_BASE and - * CPM_DATAONLY_SIZE are a subset of the available dparm. It varies - * with the processor and the microcode patches applied / activated. - * But the following should be at least safe. - */ - rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE); -} - -/* - * Allocate the requested size worth of DP memory. - * This function returns an offset into the DPRAM area. - * Use cpm_dpram_addr() to get the virtual address of the area. - */ -unsigned long cpm_dpalloc(uint size, uint align) -{ - unsigned long start; - unsigned long flags; - - spin_lock_irqsave(&cpm_dpmem_lock, flags); - cpm_dpmem_info.alignment = align; - start = rh_alloc(&cpm_dpmem_info, size, "commproc"); - spin_unlock_irqrestore(&cpm_dpmem_lock, flags); - - return start; -} -EXPORT_SYMBOL(cpm_dpalloc); - -int cpm_dpfree(unsigned long offset) -{ - int ret; - unsigned long flags; - - spin_lock_irqsave(&cpm_dpmem_lock, flags); - ret = rh_free(&cpm_dpmem_info, offset); - spin_unlock_irqrestore(&cpm_dpmem_lock, flags); - - return ret; -} -EXPORT_SYMBOL(cpm_dpfree); - -unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align) -{ - unsigned long start; - unsigned long flags; - - spin_lock_irqsave(&cpm_dpmem_lock, flags); - cpm_dpmem_info.alignment = align; - start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc"); - spin_unlock_irqrestore(&cpm_dpmem_lock, flags); - - return start; -} -EXPORT_SYMBOL(cpm_dpalloc_fixed); - -void cpm_dpdump(void) -{ - rh_dump(&cpm_dpmem_info); -} -EXPORT_SYMBOL(cpm_dpdump); - -void *cpm_dpram_addr(unsigned long offset) -{ - return (void *)(dpram_vbase + offset); -} -EXPORT_SYMBOL(cpm_dpram_addr); - -uint cpm_dpram_phys(u8* addr) -{ - return (dpram_pbase + (uint)(addr - dpram_vbase)); -} -EXPORT_SYMBOL(cpm_dpram_phys); diff --git a/arch/ppc/8xx_io/enet.c b/arch/ppc/8xx_io/enet.c deleted file mode 100644 index 5899aea1644b..000000000000 --- a/arch/ppc/8xx_io/enet.c +++ /dev/null @@ -1,982 +0,0 @@ -/* - * Ethernet driver for Motorola MPC8xx. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * I copied the basic skeleton from the lance driver, because I did not - * know how to write the Linux driver, but I did know how the LANCE worked. - * - * This version of the driver is somewhat selectable for the different - * processor/board combinations. It works for the boards I know about - * now, and should be easily modified to include others. Some of the - * configuration information is contained in and the - * remainder is here. - * - * Buffer descriptors are kept in the CPM dual port RAM, and the frame - * buffers are in the host memory. - * - * Right now, I am very watseful with the buffers. I allocate memory - * pages and then divide them into 2K frame buffers. This way I know I - * have buffers large enough to hold one frame within one buffer descriptor. - * Once I get this working, I will use 64 or 128 byte CPM buffers, which - * will be much more memory efficient and will easily handle lots of - * small packets. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* - * Theory of Operation - * - * The MPC8xx CPM performs the Ethernet processing on SCC1. It can use - * an aribtrary number of buffers on byte boundaries, but must have at - * least two receive buffers to prevent constant overrun conditions. - * - * The buffer descriptors are allocated from the CPM dual port memory - * with the data buffers allocated from host memory, just like all other - * serial communication protocols. The host memory buffers are allocated - * from the free page pool, and then divided into smaller receive and - * transmit buffers. The size of the buffers should be a power of two, - * since that nicely divides the page. This creates a ring buffer - * structure similar to the LANCE and other controllers. - * - * Like the LANCE driver: - * The driver runs as two independent, single-threaded flows of control. One - * is the send-packet routine, which enforces single-threaded use by the - * cep->tx_busy flag. The other thread is the interrupt handler, which is - * single threaded by the hardware and other software. - * - * The send packet thread has partial control over the Tx ring and the - * 'cep->tx_busy' flag. It sets the tx_busy flag whenever it's queuing a Tx - * packet. If the next queue slot is empty, it clears the tx_busy flag when - * finished otherwise it sets the 'lp->tx_full' flag. - * - * The MBX has a control register external to the MPC8xx that has some - * control of the Ethernet interface. Information is in the manual for - * your board. - * - * The RPX boards have an external control/status register. Consult the - * programming documents for details unique to your board. - * - * For the TQM8xx(L) modules, there is no control register interface. - * All functions are directly controlled using I/O pins. See . - */ - -/* The transmitter timeout - */ -#define TX_TIMEOUT (2*HZ) - -/* The number of Tx and Rx buffers. These are allocated from the page - * pool. The code may assume these are power of two, so it is best - * to keep them that size. - * We don't need to allocate pages for the transmitter. We just use - * the skbuffer directly. - */ -#ifdef CONFIG_ENET_BIG_BUFFERS -#define CPM_ENET_RX_PAGES 32 -#define CPM_ENET_RX_FRSIZE 2048 -#define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE) -#define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES) -#define TX_RING_SIZE 64 /* Must be power of two */ -#define TX_RING_MOD_MASK 63 /* for this to work */ -#else -#define CPM_ENET_RX_PAGES 4 -#define CPM_ENET_RX_FRSIZE 2048 -#define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE) -#define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES) -#define TX_RING_SIZE 8 /* Must be power of two */ -#define TX_RING_MOD_MASK 7 /* for this to work */ -#endif - -/* The CPM stores dest/src/type, data, and checksum for receive packets. - */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1520 - -/* The CPM buffer descriptors track the ring buffers. The rx_bd_base and - * tx_bd_base always point to the base of the buffer descriptors. The - * cur_rx and cur_tx point to the currently available buffer. - * The dirty_tx tracks the current buffer that is being sent by the - * controller. The cur_tx and dirty_tx are equal under both completely - * empty and completely full conditions. The empty/ready indicator in - * the buffer descriptor determines the actual condition. - */ -struct scc_enet_private { - /* The saved address of a sent-in-place packet/buffer, for skfree(). */ - struct sk_buff* tx_skbuff[TX_RING_SIZE]; - ushort skb_cur; - ushort skb_dirty; - - /* CPM dual port RAM relative addresses. - */ - cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ - cbd_t *tx_bd_base; - cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ - cbd_t *dirty_tx; /* The ring entries to be free()ed. */ - scc_t *sccp; - - /* Virtual addresses for the receive buffers because we can't - * do a __va() on them anymore. - */ - unsigned char *rx_vaddr[RX_RING_SIZE]; - struct net_device_stats stats; - uint tx_full; - spinlock_t lock; -}; - -static int scc_enet_open(struct net_device *dev); -static int scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); -static int scc_enet_rx(struct net_device *dev); -static void scc_enet_interrupt(void *dev_id); -static int scc_enet_close(struct net_device *dev); -static struct net_device_stats *scc_enet_get_stats(struct net_device *dev); -static void set_multicast_list(struct net_device *dev); - -/* Get this from various configuration locations (depends on board). -*/ -/*static ushort my_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };*/ - -/* Typically, 860(T) boards use SCC1 for Ethernet, and other 8xx boards - * use SCC2. Some even may use SCC3. - * This is easily extended if necessary. - */ -#if defined(CONFIG_SCC3_ENET) -#define CPM_CR_ENET CPM_CR_CH_SCC3 -#define PROFF_ENET PROFF_SCC3 -#define SCC_ENET 2 /* Index, not number! */ -#define CPMVEC_ENET CPMVEC_SCC3 -#elif defined(CONFIG_SCC2_ENET) -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define PROFF_ENET PROFF_SCC2 -#define SCC_ENET 1 /* Index, not number! */ -#define CPMVEC_ENET CPMVEC_SCC2 -#elif defined(CONFIG_SCC1_ENET) -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define PROFF_ENET PROFF_SCC1 -#define SCC_ENET 0 /* Index, not number! */ -#define CPMVEC_ENET CPMVEC_SCC1 -#else -#error CONFIG_SCCx_ENET not defined -#endif - -static int -scc_enet_open(struct net_device *dev) -{ - - /* I should reset the ring buffers here, but I don't yet know - * a simple way to do that. - */ - - netif_start_queue(dev); - return 0; /* Always succeed */ -} - -static int -scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv; - volatile cbd_t *bdp; - - /* Fill in a Tx ring entry */ - bdp = cep->cur_tx; - -#ifndef final_version - if (bdp->cbd_sc & BD_ENET_TX_READY) { - /* Ooops. All transmit buffers are full. Bail out. - * This should not happen, since cep->tx_busy should be set. - */ - printk("%s: tx queue full!.\n", dev->name); - return 1; - } -#endif - - /* Clear all of the status flags. - */ - bdp->cbd_sc &= ~BD_ENET_TX_STATS; - - /* If the frame is short, tell CPM to pad it. - */ - if (skb->len <= ETH_ZLEN) - bdp->cbd_sc |= BD_ENET_TX_PAD; - else - bdp->cbd_sc &= ~BD_ENET_TX_PAD; - - /* Set buffer length and buffer pointer. - */ - bdp->cbd_datlen = skb->len; - bdp->cbd_bufaddr = __pa(skb->data); - - /* Save skb pointer. - */ - cep->tx_skbuff[cep->skb_cur] = skb; - - cep->stats.tx_bytes += skb->len; - cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK; - - /* Push the data cache so the CPM does not get stale memory - * data. - */ - flush_dcache_range((unsigned long)(skb->data), - (unsigned long)(skb->data + skb->len)); - - spin_lock_irq(&cep->lock); - - /* Send it on its way. Tell CPM its ready, interrupt when done, - * its the last BD of the frame, and to put the CRC on the end. - */ - bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC); - - dev->trans_start = jiffies; - - /* If this was the last BD in the ring, start at the beginning again. - */ - if (bdp->cbd_sc & BD_ENET_TX_WRAP) - bdp = cep->tx_bd_base; - else - bdp++; - - if (bdp->cbd_sc & BD_ENET_TX_READY) { - netif_stop_queue(dev); - cep->tx_full = 1; - } - - cep->cur_tx = (cbd_t *)bdp; - - spin_unlock_irq(&cep->lock); - - return 0; -} - -static void -scc_enet_timeout(struct net_device *dev) -{ - struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv; - - printk("%s: transmit timed out.\n", dev->name); - cep->stats.tx_errors++; -#ifndef final_version - { - int i; - cbd_t *bdp; - printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n", - cep->cur_tx, cep->tx_full ? " (full)" : "", - cep->cur_rx); - bdp = cep->tx_bd_base; - for (i = 0 ; i < TX_RING_SIZE; i++, bdp++) - printk("%04x %04x %08x\n", - bdp->cbd_sc, - bdp->cbd_datlen, - bdp->cbd_bufaddr); - bdp = cep->rx_bd_base; - for (i = 0 ; i < RX_RING_SIZE; i++, bdp++) - printk("%04x %04x %08x\n", - bdp->cbd_sc, - bdp->cbd_datlen, - bdp->cbd_bufaddr); - } -#endif - if (!cep->tx_full) - netif_wake_queue(dev); -} - -/* The interrupt handler. - * This is called from the CPM handler, not the MPC core interrupt. - */ -static void -scc_enet_interrupt(void *dev_id) -{ - struct net_device *dev = dev_id; - volatile struct scc_enet_private *cep; - volatile cbd_t *bdp; - ushort int_events; - int must_restart; - - cep = (struct scc_enet_private *)dev->priv; - - /* Get the interrupt events that caused us to be here. - */ - int_events = cep->sccp->scc_scce; - cep->sccp->scc_scce = int_events; - must_restart = 0; - - /* Handle receive event in its own function. - */ - if (int_events & SCCE_ENET_RXF) - scc_enet_rx(dev_id); - - /* Check for a transmit error. The manual is a little unclear - * about this, so the debug code until I get it figured out. It - * appears that if TXE is set, then TXB is not set. However, - * if carrier sense is lost during frame transmission, the TXE - * bit is set, "and continues the buffer transmission normally." - * I don't know if "normally" implies TXB is set when the buffer - * descriptor is closed.....trial and error :-). - */ - - /* Transmit OK, or non-fatal error. Update the buffer descriptors. - */ - if (int_events & (SCCE_ENET_TXE | SCCE_ENET_TXB)) { - spin_lock(&cep->lock); - bdp = cep->dirty_tx; - while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) { - if ((bdp==cep->cur_tx) && (cep->tx_full == 0)) - break; - - if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */ - cep->stats.tx_heartbeat_errors++; - if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */ - cep->stats.tx_window_errors++; - if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */ - cep->stats.tx_aborted_errors++; - if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */ - cep->stats.tx_fifo_errors++; - if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */ - cep->stats.tx_carrier_errors++; - - - /* No heartbeat or Lost carrier are not really bad errors. - * The others require a restart transmit command. - */ - if (bdp->cbd_sc & - (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) { - must_restart = 1; - cep->stats.tx_errors++; - } - - cep->stats.tx_packets++; - - /* Deferred means some collisions occurred during transmit, - * but we eventually sent the packet OK. - */ - if (bdp->cbd_sc & BD_ENET_TX_DEF) - cep->stats.collisions++; - - /* Free the sk buffer associated with this last transmit. - */ - dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]); - cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK; - - /* Update pointer to next buffer descriptor to be transmitted. - */ - if (bdp->cbd_sc & BD_ENET_TX_WRAP) - bdp = cep->tx_bd_base; - else - bdp++; - - /* I don't know if we can be held off from processing these - * interrupts for more than one frame time. I really hope - * not. In such a case, we would now want to check the - * currently available BD (cur_tx) and determine if any - * buffers between the dirty_tx and cur_tx have also been - * sent. We would want to process anything in between that - * does not have BD_ENET_TX_READY set. - */ - - /* Since we have freed up a buffer, the ring is no longer - * full. - */ - if (cep->tx_full) { - cep->tx_full = 0; - if (netif_queue_stopped(dev)) - netif_wake_queue(dev); - } - - cep->dirty_tx = (cbd_t *)bdp; - } - - if (must_restart) { - volatile cpm8xx_t *cp; - - /* Some transmit errors cause the transmitter to shut - * down. We now issue a restart transmit. Since the - * errors close the BD and update the pointers, the restart - * _should_ pick up without having to reset any of our - * pointers either. - */ - cp = cpmp; - cp->cp_cpcr = - mk_cr_cmd(CPM_CR_ENET, CPM_CR_RESTART_TX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - } - spin_unlock(&cep->lock); - } - - /* Check for receive busy, i.e. packets coming but no place to - * put them. This "can't happen" because the receive interrupt - * is tossing previous frames. - */ - if (int_events & SCCE_ENET_BSY) { - cep->stats.rx_dropped++; - printk("CPM ENET: BSY can't happen.\n"); - } - - return; -} - -/* During a receive, the cur_rx points to the current incoming buffer. - * When we update through the ring, if the next incoming buffer has - * not been given to the system, we just set the empty indicator, - * effectively tossing the packet. - */ -static int -scc_enet_rx(struct net_device *dev) -{ - struct scc_enet_private *cep; - volatile cbd_t *bdp; - struct sk_buff *skb; - ushort pkt_len; - - cep = (struct scc_enet_private *)dev->priv; - - /* First, grab all of the stats for the incoming packet. - * These get messed up if we get called due to a busy condition. - */ - bdp = cep->cur_rx; - -for (;;) { - if (bdp->cbd_sc & BD_ENET_RX_EMPTY) - break; - -#ifndef final_version - /* Since we have allocated space to hold a complete frame, both - * the first and last indicators should be set. - */ - if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) != - (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) - printk("CPM ENET: rcv is not first+last\n"); -#endif - - /* Frame too long or too short. - */ - if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) - cep->stats.rx_length_errors++; - if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */ - cep->stats.rx_frame_errors++; - if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */ - cep->stats.rx_crc_errors++; - if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */ - cep->stats.rx_crc_errors++; - - /* Report late collisions as a frame error. - * On this error, the BD is closed, but we don't know what we - * have in the buffer. So, just drop this frame on the floor. - */ - if (bdp->cbd_sc & BD_ENET_RX_CL) { - cep->stats.rx_frame_errors++; - } - else { - - /* Process the incoming frame. - */ - cep->stats.rx_packets++; - pkt_len = bdp->cbd_datlen; - cep->stats.rx_bytes += pkt_len; - - /* This does 16 byte alignment, much more than we need. - * The packet length includes FCS, but we don't want to - * include that when passing upstream as it messes up - * bridging applications. - */ - skb = dev_alloc_skb(pkt_len-4); - - if (skb == NULL) { - printk("%s: Memory squeeze, dropping packet.\n", dev->name); - cep->stats.rx_dropped++; - } - else { - skb_put(skb,pkt_len-4); /* Make room */ - skb_copy_to_linear_data(skb, - cep->rx_vaddr[bdp - cep->rx_bd_base], - pkt_len-4); - skb->protocol=eth_type_trans(skb,dev); - netif_rx(skb); - } - } - - /* Clear the status flags for this buffer. - */ - bdp->cbd_sc &= ~BD_ENET_RX_STATS; - - /* Mark the buffer empty. - */ - bdp->cbd_sc |= BD_ENET_RX_EMPTY; - - /* Update BD pointer to next entry. - */ - if (bdp->cbd_sc & BD_ENET_RX_WRAP) - bdp = cep->rx_bd_base; - else - bdp++; - - } - cep->cur_rx = (cbd_t *)bdp; - - return 0; -} - -static int -scc_enet_close(struct net_device *dev) -{ - /* Don't know what to do yet. - */ - netif_stop_queue(dev); - - return 0; -} - -static struct net_device_stats *scc_enet_get_stats(struct net_device *dev) -{ - struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv; - - return &cep->stats; -} - -/* Set or clear the multicast filter for this adaptor. - * Skeleton taken from sunlance driver. - * The CPM Ethernet implementation allows Multicast as well as individual - * MAC address filtering. Some of the drivers check to make sure it is - * a group multicast address, and discard those that are not. I guess I - * will do the same for now, but just remove the test if you want - * individual filtering as well (do the upper net layers want or support - * this kind of feature?). - */ - -static void set_multicast_list(struct net_device *dev) -{ - struct scc_enet_private *cep; - struct dev_mc_list *dmi; - u_char *mcptr, *tdptr; - volatile scc_enet_t *ep; - int i, j; - cep = (struct scc_enet_private *)dev->priv; - - /* Get pointer to SCC area in parameter RAM. - */ - ep = (scc_enet_t *)dev->base_addr; - - if (dev->flags&IFF_PROMISC) { - - /* Log any net taps. */ - printk("%s: Promiscuous mode enabled.\n", dev->name); - cep->sccp->scc_psmr |= SCC_PSMR_PRO; - } else { - - cep->sccp->scc_psmr &= ~SCC_PSMR_PRO; - - if (dev->flags & IFF_ALLMULTI) { - /* Catch all multicast addresses, so set the - * filter to all 1's. - */ - ep->sen_gaddr1 = 0xffff; - ep->sen_gaddr2 = 0xffff; - ep->sen_gaddr3 = 0xffff; - ep->sen_gaddr4 = 0xffff; - } - else { - /* Clear filter and add the addresses in the list. - */ - ep->sen_gaddr1 = 0; - ep->sen_gaddr2 = 0; - ep->sen_gaddr3 = 0; - ep->sen_gaddr4 = 0; - - dmi = dev->mc_list; - - for (i=0; imc_count; i++) { - - /* Only support group multicast for now. - */ - if (!(dmi->dmi_addr[0] & 1)) - continue; - - /* The address in dmi_addr is LSB first, - * and taddr is MSB first. We have to - * copy bytes MSB first from dmi_addr. - */ - mcptr = (u_char *)dmi->dmi_addr + 5; - tdptr = (u_char *)&ep->sen_taddrh; - for (j=0; j<6; j++) - *tdptr++ = *mcptr--; - - /* Ask CPM to run CRC and set bit in - * filter mask. - */ - cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_SET_GADDR) | CPM_CR_FLG; - /* this delay is necessary here -- Cort */ - udelay(10); - while (cpmp->cp_cpcr & CPM_CR_FLG); - } - } - } -} - -/* Initialize the CPM Ethernet on SCC. If EPPC-Bug loaded us, or performed - * some other network I/O, a whole bunch of this has already been set up. - * It is no big deal if we do it again, we just have to disable the - * transmit and receive to make sure we don't catch the CPM with some - * inconsistent control information. - */ -static int __init scc_enet_init(void) -{ - struct net_device *dev; - struct scc_enet_private *cep; - int i, j, k, err; - uint dp_offset; - unsigned char *eap, *ba; - dma_addr_t mem_addr; - bd_t *bd; - volatile cbd_t *bdp; - volatile cpm8xx_t *cp; - volatile scc_t *sccp; - volatile scc_enet_t *ep; - volatile immap_t *immap; - - cp = cpmp; /* Get pointer to Communication Processor */ - - immap = (immap_t *)(mfspr(SPRN_IMMR) & 0xFFFF0000); /* and to internal registers */ - - bd = (bd_t *)__res; - - dev = alloc_etherdev(sizeof(*cep)); - if (!dev) - return -ENOMEM; - - cep = dev->priv; - spin_lock_init(&cep->lock); - - /* Get pointer to SCC area in parameter RAM. - */ - ep = (scc_enet_t *)(&cp->cp_dparam[PROFF_ENET]); - - /* And another to the SCC register area. - */ - sccp = (volatile scc_t *)(&cp->cp_scc[SCC_ENET]); - cep->sccp = (scc_t *)sccp; /* Keep the pointer handy */ - - /* Disable receive and transmit in case EPPC-Bug started it. - */ - sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* Cookbook style from the MPC860 manual..... - * Not all of this is necessary if EPPC-Bug has initialized - * the network. - * So far we are lucky, all board configurations use the same - * pins, or at least the same I/O Port for these functions..... - * It can't last though...... - */ - -#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) - /* Configure port A pins for Txd and Rxd. - */ - immap->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); - immap->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); - immap->im_ioport.iop_paodr &= ~PA_ENET_TXD; -#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) - /* Configure port B pins for Txd and Rxd. - */ - immap->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); - immap->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); - immap->im_cpm.cp_pbodr &= ~PB_ENET_TXD; -#else -#error Exactly ONE pair of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined -#endif - -#if defined(PC_ENET_LBK) - /* Configure port C pins to disable External Loopback - */ - immap->im_ioport.iop_pcpar &= ~PC_ENET_LBK; - immap->im_ioport.iop_pcdir |= PC_ENET_LBK; - immap->im_ioport.iop_pcso &= ~PC_ENET_LBK; - immap->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ -#endif /* PC_ENET_LBK */ - -#ifdef PE_ENET_TCLK - /* Configure port E for TCLK and RCLK. - */ - cp->cp_pepar |= (PE_ENET_TCLK | PE_ENET_RCLK); - cp->cp_pedir &= ~(PE_ENET_TCLK | PE_ENET_RCLK); - cp->cp_peso &= ~(PE_ENET_TCLK | PE_ENET_RCLK); -#else - /* Configure port A for TCLK and RCLK. - */ - immap->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); - immap->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); -#endif - - /* Configure port C pins to enable CLSN and RENA. - */ - immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immap->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); - - /* Configure Serial Interface clock routing. - * First, clear all SCC bits to zero, then set the ones we want. - */ - cp->cp_sicr &= ~SICR_ENET_MASK; - cp->cp_sicr |= SICR_ENET_CLKRT; - - /* Manual says set SDDR, but I can't find anything with that - * name. I think it is a misprint, and should be SDCR. This - * has already been set by the communication processor initialization. - */ - - /* Allocate space for the buffer descriptors in the DP ram. - * These are relative offsets in the DP ram address space. - * Initialize base addresses for the buffer descriptors. - */ - dp_offset = cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8); - ep->sen_genscc.scc_rbase = dp_offset; - cep->rx_bd_base = cpm_dpram_addr(dp_offset); - - dp_offset = cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8); - ep->sen_genscc.scc_tbase = dp_offset; - cep->tx_bd_base = cpm_dpram_addr(dp_offset); - - cep->dirty_tx = cep->cur_tx = cep->tx_bd_base; - cep->cur_rx = cep->rx_bd_base; - - /* Issue init Rx BD command for SCC. - * Manual says to perform an Init Rx parameters here. We have - * to perform both Rx and Tx because the SCC may have been - * already running. - * In addition, we have to do it later because we don't yet have - * all of the BD control/status set properly. - cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_RX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - */ - - /* Initialize function code registers for big-endian. - */ - ep->sen_genscc.scc_rfcr = SCC_EB; - ep->sen_genscc.scc_tfcr = SCC_EB; - - /* Set maximum bytes per receive buffer. - * This appears to be an Ethernet frame size, not the buffer - * fragment size. It must be a multiple of four. - */ - ep->sen_genscc.scc_mrblr = PKT_MAXBLR_SIZE; - - /* Set CRC preset and mask. - */ - ep->sen_cpres = 0xffffffff; - ep->sen_cmask = 0xdebb20e3; - - ep->sen_crcec = 0; /* CRC Error counter */ - ep->sen_alec = 0; /* alignment error counter */ - ep->sen_disfc = 0; /* discard frame counter */ - - ep->sen_pads = 0x8888; /* Tx short frame pad character */ - ep->sen_retlim = 15; /* Retry limit threshold */ - - ep->sen_maxflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - ep->sen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ - - ep->sen_maxd1 = PKT_MAXBLR_SIZE; /* maximum DMA1 length */ - ep->sen_maxd2 = PKT_MAXBLR_SIZE; /* maximum DMA2 length */ - - /* Clear hash tables. - */ - ep->sen_gaddr1 = 0; - ep->sen_gaddr2 = 0; - ep->sen_gaddr3 = 0; - ep->sen_gaddr4 = 0; - ep->sen_iaddr1 = 0; - ep->sen_iaddr2 = 0; - ep->sen_iaddr3 = 0; - ep->sen_iaddr4 = 0; - - /* Set Ethernet station address. - */ - eap = (unsigned char *)&(ep->sen_paddrh); - for (i=5; i>=0; i--) - *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i]; - - ep->sen_pper = 0; /* 'cause the book says so */ - ep->sen_taddrl = 0; /* temp address (LSB) */ - ep->sen_taddrm = 0; - ep->sen_taddrh = 0; /* temp address (MSB) */ - - /* Now allocate the host memory pages and initialize the - * buffer descriptors. - */ - bdp = cep->tx_bd_base; - for (i=0; icbd_sc = 0; - bdp->cbd_bufaddr = 0; - bdp++; - } - - /* Set the last buffer to wrap. - */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; - - bdp = cep->rx_bd_base; - k = 0; - for (i=0; icbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR; - bdp->cbd_bufaddr = mem_addr; - cep->rx_vaddr[k++] = ba; - mem_addr += CPM_ENET_RX_FRSIZE; - ba += CPM_ENET_RX_FRSIZE; - bdp++; - } - } - - /* Set the last buffer to wrap. - */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; - - /* Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - cep->skb_cur = cep->skb_dirty = 0; - - sccp->scc_scce = 0xffff; /* Clear any pending events */ - - /* Enable interrupts for transmit error, complete frame - * received, and any transmit buffer we have also set the - * interrupt flag. - */ - sccp->scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB); - - /* Install our interrupt handler. - */ - cpm_install_handler(CPMVEC_ENET, scc_enet_interrupt, dev); - - /* Set GSMR_H to enable all normal operating modes. - * Set GSMR_L to enable Ethernet to MC68160. - */ - sccp->scc_gsmrh = 0; - sccp->scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET); - - /* Set sync/delimiters. - */ - sccp->scc_dsr = 0xd555; - - /* Set processing mode. Use Ethernet CRC, catch broadcast, and - * start frame search 22 bit times after RENA. - */ - sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22); - - /* It is now OK to enable the Ethernet transmitter. - * Unfortunately, there are board implementation differences here. - */ -#if (!defined (PB_ENET_TENA) && defined (PC_ENET_TENA) && !defined (PE_ENET_TENA)) - immap->im_ioport.iop_pcpar |= PC_ENET_TENA; - immap->im_ioport.iop_pcdir &= ~PC_ENET_TENA; -#elif ( defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && !defined (PE_ENET_TENA)) - cp->cp_pbpar |= PB_ENET_TENA; - cp->cp_pbdir |= PB_ENET_TENA; -#elif ( !defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && defined (PE_ENET_TENA)) - cp->cp_pepar |= PE_ENET_TENA; - cp->cp_pedir &= ~PE_ENET_TENA; - cp->cp_peso |= PE_ENET_TENA; -#else -#error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA, PE_ENET_TENA -#endif - -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) - /* And while we are here, set the configuration to enable ethernet. - */ - *((volatile uint *)RPX_CSR_ADDR) &= ~BCSR0_ETHLPBK; - *((volatile uint *)RPX_CSR_ADDR) |= - (BCSR0_ETHEN | BCSR0_COLTESTDIS | BCSR0_FULLDPLXDIS); -#endif - -#ifdef CONFIG_BSEIP - /* BSE uses port B and C for PHY control. - */ - cp->cp_pbpar &= ~(PB_BSE_POWERUP | PB_BSE_FDXDIS); - cp->cp_pbdir |= (PB_BSE_POWERUP | PB_BSE_FDXDIS); - cp->cp_pbdat |= (PB_BSE_POWERUP | PB_BSE_FDXDIS); - - immap->im_ioport.iop_pcpar &= ~PC_BSE_LOOPBACK; - immap->im_ioport.iop_pcdir |= PC_BSE_LOOPBACK; - immap->im_ioport.iop_pcso &= ~PC_BSE_LOOPBACK; - immap->im_ioport.iop_pcdat &= ~PC_BSE_LOOPBACK; -#endif - -#ifdef CONFIG_FADS - cp->cp_pbpar |= PB_ENET_TENA; - cp->cp_pbdir |= PB_ENET_TENA; - - /* Enable the EEST PHY. - */ - *((volatile uint *)BCSR1) &= ~BCSR1_ETHEN; -#endif - - dev->base_addr = (unsigned long)ep; -#if 0 - dev->name = "CPM_ENET"; -#endif - - /* The CPM Ethernet specific entries in the device structure. */ - dev->open = scc_enet_open; - dev->hard_start_xmit = scc_enet_start_xmit; - dev->tx_timeout = scc_enet_timeout; - dev->watchdog_timeo = TX_TIMEOUT; - dev->stop = scc_enet_close; - dev->get_stats = scc_enet_get_stats; - dev->set_multicast_list = set_multicast_list; - - err = register_netdev(dev); - if (err) { - free_netdev(dev); - return err; - } - - /* And last, enable the transmit and receive processing. - */ - sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - printk("%s: CPM ENET Version 0.2 on SCC%d, ", dev->name, SCC_ENET+1); - for (i=0; i<5; i++) - printk("%02x:", dev->dev_addr[i]); - printk("%02x\n", dev->dev_addr[5]); - - return 0; -} - -module_init(scc_enet_init); - diff --git a/arch/ppc/8xx_io/fec.c b/arch/ppc/8xx_io/fec.c deleted file mode 100644 index 2c604d4f6e8b..000000000000 --- a/arch/ppc/8xx_io/fec.c +++ /dev/null @@ -1,1983 +0,0 @@ -/* - * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * This version of the driver is specific to the FADS implementation, - * since the board contains control registers external to the processor - * for the control of the LevelOne LXT970 transceiver. The MPC860T manual - * describes connections using the internal parallel port I/O, which - * is basically all of Port D. - * - * Includes support for the following PHYs: QS6612, LXT970, LXT971/2. - * - * Right now, I am very wasteful with the buffers. I allocate memory - * pages and then divide them into 2K frame buffers. This way I know I - * have buffers large enough to hold one frame within one buffer descriptor. - * Once I get this working, I will use 64 or 128 byte CPM buffers, which - * will be much more memory efficient and will easily handle lots of - * small packets. - * - * Much better multiple PHY support by Magnus Damm. - * Copyright (c) 2000 Ericsson Radio Systems AB. - * - * Make use of MII for PHY control configurable. - * Some fixes. - * Copyright (c) 2000-2002 Wolfgang Denk, DENX Software Engineering. - * - * Support for AMD AM79C874 added. - * Thomas Lange, thomas@corelatus.com - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_FEC_PACKETHOOK -#include -#endif - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_USE_MDIO -/* Forward declarations of some structures to support different PHYs -*/ - -typedef struct { - uint mii_data; - void (*funct)(uint mii_reg, struct net_device *dev); -} phy_cmd_t; - -typedef struct { - uint id; - char *name; - - const phy_cmd_t *config; - const phy_cmd_t *startup; - const phy_cmd_t *ack_int; - const phy_cmd_t *shutdown; -} phy_info_t; -#endif /* CONFIG_USE_MDIO */ - -/* The number of Tx and Rx buffers. These are allocated from the page - * pool. The code may assume these are power of two, so it is best - * to keep them that size. - * We don't need to allocate pages for the transmitter. We just use - * the skbuffer directly. - */ -#ifdef CONFIG_ENET_BIG_BUFFERS -#define FEC_ENET_RX_PAGES 16 -#define FEC_ENET_RX_FRSIZE 2048 -#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) -#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) -#define TX_RING_SIZE 16 /* Must be power of two */ -#define TX_RING_MOD_MASK 15 /* for this to work */ -#else -#define FEC_ENET_RX_PAGES 4 -#define FEC_ENET_RX_FRSIZE 2048 -#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) -#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) -#define TX_RING_SIZE 8 /* Must be power of two */ -#define TX_RING_MOD_MASK 7 /* for this to work */ -#endif - -/* Interrupt events/masks. -*/ -#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ -#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ -#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ -#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ -#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ -#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ -#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ -#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ -#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ -#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ - -/* -*/ -#define FEC_ECNTRL_PINMUX 0x00000004 -#define FEC_ECNTRL_ETHER_EN 0x00000002 -#define FEC_ECNTRL_RESET 0x00000001 - -#define FEC_RCNTRL_BC_REJ 0x00000010 -#define FEC_RCNTRL_PROM 0x00000008 -#define FEC_RCNTRL_MII_MODE 0x00000004 -#define FEC_RCNTRL_DRT 0x00000002 -#define FEC_RCNTRL_LOOP 0x00000001 - -#define FEC_TCNTRL_FDEN 0x00000004 -#define FEC_TCNTRL_HBC 0x00000002 -#define FEC_TCNTRL_GTS 0x00000001 - -/* Delay to wait for FEC reset command to complete (in us) -*/ -#define FEC_RESET_DELAY 50 - -/* The FEC stores dest/src/type, data, and checksum for receive packets. - */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1520 - -/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and - * tx_bd_base always point to the base of the buffer descriptors. The - * cur_rx and cur_tx point to the currently available buffer. - * The dirty_tx tracks the current buffer that is being sent by the - * controller. The cur_tx and dirty_tx are equal under both completely - * empty and completely full conditions. The empty/ready indicator in - * the buffer descriptor determines the actual condition. - */ -struct fec_enet_private { - /* The saved address of a sent-in-place packet/buffer, for skfree(). */ - struct sk_buff* tx_skbuff[TX_RING_SIZE]; - ushort skb_cur; - ushort skb_dirty; - - /* CPM dual port RAM relative addresses. - */ - cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ - cbd_t *tx_bd_base; - cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ - cbd_t *dirty_tx; /* The ring entries to be free()ed. */ - - /* Virtual addresses for the receive buffers because we can't - * do a __va() on them anymore. - */ - unsigned char *rx_vaddr[RX_RING_SIZE]; - - struct net_device_stats stats; - uint tx_full; - spinlock_t lock; - -#ifdef CONFIG_USE_MDIO - uint phy_id; - uint phy_id_done; - uint phy_status; - uint phy_speed; - phy_info_t *phy; - struct work_struct phy_task; - struct net_device *dev; - - uint sequence_done; - - uint phy_addr; -#endif /* CONFIG_USE_MDIO */ - - int link; - int old_link; - int full_duplex; - -#ifdef CONFIG_FEC_PACKETHOOK - unsigned long ph_lock; - fec_ph_func *ph_rxhandler; - fec_ph_func *ph_txhandler; - __u16 ph_proto; - volatile __u32 *ph_regaddr; - void *ph_priv; -#endif -}; - -static int fec_enet_open(struct net_device *dev); -static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); -#ifdef CONFIG_USE_MDIO -static void fec_enet_mii(struct net_device *dev); -#endif /* CONFIG_USE_MDIO */ -#ifdef CONFIG_FEC_PACKETHOOK -static void fec_enet_tx(struct net_device *dev, __u32 regval); -static void fec_enet_rx(struct net_device *dev, __u32 regval); -#else -static void fec_enet_tx(struct net_device *dev); -static void fec_enet_rx(struct net_device *dev); -#endif -static int fec_enet_close(struct net_device *dev); -static struct net_device_stats *fec_enet_get_stats(struct net_device *dev); -static void set_multicast_list(struct net_device *dev); -static void fec_restart(struct net_device *dev, int duplex); -static void fec_stop(struct net_device *dev); -static ushort my_enet_addr[3]; - -#ifdef CONFIG_USE_MDIO -/* MII processing. We keep this as simple as possible. Requests are - * placed on the list (if there is room). When the request is finished - * by the MII, an optional function may be called. - */ -typedef struct mii_list { - uint mii_regval; - void (*mii_func)(uint val, struct net_device *dev); - struct mii_list *mii_next; -} mii_list_t; - -#define NMII 20 -mii_list_t mii_cmds[NMII]; -mii_list_t *mii_free; -mii_list_t *mii_head; -mii_list_t *mii_tail; - -static int mii_queue(struct net_device *dev, int request, - void (*func)(uint, struct net_device *)); - -/* Make MII read/write commands for the FEC. -*/ -#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) -#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ - (VAL & 0xffff)) -#define mk_mii_end 0 -#endif /* CONFIG_USE_MDIO */ - -/* Transmitter timeout. -*/ -#define TX_TIMEOUT (2*HZ) - -#ifdef CONFIG_USE_MDIO -/* Register definitions for the PHY. -*/ - -#define MII_REG_CR 0 /* Control Register */ -#define MII_REG_SR 1 /* Status Register */ -#define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ -#define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ -#define MII_REG_ANAR 4 /* A-N Advertisement Register */ -#define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ -#define MII_REG_ANER 6 /* A-N Expansion Register */ -#define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ -#define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ - -/* values for phy_status */ - -#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ -#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ -#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ -#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ -#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ -#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ -#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ - -#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ -#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ -#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ -#define PHY_STAT_SPMASK 0xf000 /* mask for speed */ -#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ -#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ -#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ -#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ -#endif /* CONFIG_USE_MDIO */ - -#ifdef CONFIG_FEC_PACKETHOOK -int -fec_register_ph(struct net_device *dev, fec_ph_func *rxfun, fec_ph_func *txfun, - __u16 proto, volatile __u32 *regaddr, void *priv) -{ - struct fec_enet_private *fep; - int retval = 0; - - fep = dev->priv; - - if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) { - /* Someone is messing with the packet hook */ - return -EAGAIN; - } - if (fep->ph_rxhandler != NULL || fep->ph_txhandler != NULL) { - retval = -EBUSY; - goto out; - } - fep->ph_rxhandler = rxfun; - fep->ph_txhandler = txfun; - fep->ph_proto = proto; - fep->ph_regaddr = regaddr; - fep->ph_priv = priv; - - out: - fep->ph_lock = 0; - - return retval; -} - - -int -fec_unregister_ph(struct net_device *dev) -{ - struct fec_enet_private *fep; - int retval = 0; - - fep = dev->priv; - - if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) { - /* Someone is messing with the packet hook */ - return -EAGAIN; - } - - fep->ph_rxhandler = fep->ph_txhandler = NULL; - fep->ph_proto = 0; - fep->ph_regaddr = NULL; - fep->ph_priv = NULL; - - fep->ph_lock = 0; - - return retval; -} - -EXPORT_SYMBOL(fec_register_ph); -EXPORT_SYMBOL(fec_unregister_ph); - -#endif /* CONFIG_FEC_PACKETHOOK */ - -static int -fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct fec_enet_private *fep; - volatile fec_t *fecp; - volatile cbd_t *bdp; - - fep = dev->priv; - fecp = (volatile fec_t*)dev->base_addr; - - if (!fep->link) { - /* Link is down or autonegotiation is in progress. */ - return 1; - } - - /* Fill in a Tx ring entry */ - bdp = fep->cur_tx; - -#ifndef final_version - if (bdp->cbd_sc & BD_ENET_TX_READY) { - /* Ooops. All transmit buffers are full. Bail out. - * This should not happen, since dev->tbusy should be set. - */ - printk("%s: tx queue full!.\n", dev->name); - return 1; - } -#endif - - /* Clear all of the status flags. - */ - bdp->cbd_sc &= ~BD_ENET_TX_STATS; - - /* Set buffer length and buffer pointer. - */ - bdp->cbd_bufaddr = __pa(skb->data); - bdp->cbd_datlen = skb->len; - - /* Save skb pointer. - */ - fep->tx_skbuff[fep->skb_cur] = skb; - - fep->stats.tx_bytes += skb->len; - fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; - - /* Push the data cache so the CPM does not get stale memory - * data. - */ - flush_dcache_range((unsigned long)skb->data, - (unsigned long)skb->data + skb->len); - - /* disable interrupts while triggering transmit */ - spin_lock_irq(&fep->lock); - - /* Send it on its way. Tell FEC its ready, interrupt when done, - * its the last BD of the frame, and to put the CRC on the end. - */ - - bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR - | BD_ENET_TX_LAST | BD_ENET_TX_TC); - - dev->trans_start = jiffies; - - /* Trigger transmission start */ - fecp->fec_x_des_active = 0x01000000; - - /* If this was the last BD in the ring, start at the beginning again. - */ - if (bdp->cbd_sc & BD_ENET_TX_WRAP) { - bdp = fep->tx_bd_base; - } else { - bdp++; - } - - if (bdp->cbd_sc & BD_ENET_TX_READY) { - netif_stop_queue(dev); - fep->tx_full = 1; - } - - fep->cur_tx = (cbd_t *)bdp; - - spin_unlock_irq(&fep->lock); - - return 0; -} - -static void -fec_timeout(struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - - printk("%s: transmit timed out.\n", dev->name); - fep->stats.tx_errors++; -#ifndef final_version - { - int i; - cbd_t *bdp; - - printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n", - (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", - (unsigned long)fep->dirty_tx, - (unsigned long)fep->cur_rx); - - bdp = fep->tx_bd_base; - printk(" tx: %u buffers\n", TX_RING_SIZE); - for (i = 0 ; i < TX_RING_SIZE; i++) { - printk(" %08x: %04x %04x %08x\n", - (uint) bdp, - bdp->cbd_sc, - bdp->cbd_datlen, - bdp->cbd_bufaddr); - bdp++; - } - - bdp = fep->rx_bd_base; - printk(" rx: %lu buffers\n", RX_RING_SIZE); - for (i = 0 ; i < RX_RING_SIZE; i++) { - printk(" %08x: %04x %04x %08x\n", - (uint) bdp, - bdp->cbd_sc, - bdp->cbd_datlen, - bdp->cbd_bufaddr); - bdp++; - } - } -#endif - if (!fep->tx_full) - netif_wake_queue(dev); -} - -/* The interrupt handler. - * This is called from the MPC core interrupt. - */ -static irqreturn_t -fec_enet_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - volatile fec_t *fecp; - uint int_events; -#ifdef CONFIG_FEC_PACKETHOOK - struct fec_enet_private *fep = dev->priv; - __u32 regval; - - if (fep->ph_regaddr) regval = *fep->ph_regaddr; -#endif - fecp = (volatile fec_t*)dev->base_addr; - - /* Get the interrupt events that caused us to be here. - */ - while ((int_events = fecp->fec_ievent) != 0) { - fecp->fec_ievent = int_events; - if ((int_events & (FEC_ENET_HBERR | FEC_ENET_BABR | - FEC_ENET_BABT | FEC_ENET_EBERR)) != 0) { - printk("FEC ERROR %x\n", int_events); - } - - /* Handle receive event in its own function. - */ - if (int_events & FEC_ENET_RXF) { -#ifdef CONFIG_FEC_PACKETHOOK - fec_enet_rx(dev, regval); -#else - fec_enet_rx(dev); -#endif - } - - /* Transmit OK, or non-fatal error. Update the buffer - descriptors. FEC handles all errors, we just discover - them as part of the transmit process. - */ - if (int_events & FEC_ENET_TXF) { -#ifdef CONFIG_FEC_PACKETHOOK - fec_enet_tx(dev, regval); -#else - fec_enet_tx(dev); -#endif - } - - if (int_events & FEC_ENET_MII) { -#ifdef CONFIG_USE_MDIO - fec_enet_mii(dev); -#else -printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__, __LINE__, __func__); -#endif /* CONFIG_USE_MDIO */ - } - - } - return IRQ_RETVAL(IRQ_HANDLED); -} - - -static void -#ifdef CONFIG_FEC_PACKETHOOK -fec_enet_tx(struct net_device *dev, __u32 regval) -#else -fec_enet_tx(struct net_device *dev) -#endif -{ - struct fec_enet_private *fep; - volatile cbd_t *bdp; - struct sk_buff *skb; - - fep = dev->priv; - /* lock while transmitting */ - spin_lock(&fep->lock); - bdp = fep->dirty_tx; - - while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) { - if (bdp == fep->cur_tx && fep->tx_full == 0) break; - - skb = fep->tx_skbuff[fep->skb_dirty]; - /* Check for errors. */ - if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC | - BD_ENET_TX_RL | BD_ENET_TX_UN | - BD_ENET_TX_CSL)) { - fep->stats.tx_errors++; - if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */ - fep->stats.tx_heartbeat_errors++; - if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */ - fep->stats.tx_window_errors++; - if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */ - fep->stats.tx_aborted_errors++; - if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */ - fep->stats.tx_fifo_errors++; - if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */ - fep->stats.tx_carrier_errors++; - } else { -#ifdef CONFIG_FEC_PACKETHOOK - /* Packet hook ... */ - if (fep->ph_txhandler && - ((struct ethhdr *)skb->data)->h_proto - == fep->ph_proto) { - fep->ph_txhandler((__u8*)skb->data, skb->len, - regval, fep->ph_priv); - } -#endif - fep->stats.tx_packets++; - } - -#ifndef final_version - if (bdp->cbd_sc & BD_ENET_TX_READY) - printk("HEY! Enet xmit interrupt and TX_READY.\n"); -#endif - /* Deferred means some collisions occurred during transmit, - * but we eventually sent the packet OK. - */ - if (bdp->cbd_sc & BD_ENET_TX_DEF) - fep->stats.collisions++; - - /* Free the sk buffer associated with this last transmit. - */ -#if 0 -printk("TXI: %x %x %x\n", bdp, skb, fep->skb_dirty); -#endif - dev_kfree_skb_irq (skb/*, FREE_WRITE*/); - fep->tx_skbuff[fep->skb_dirty] = NULL; - fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; - - /* Update pointer to next buffer descriptor to be transmitted. - */ - if (bdp->cbd_sc & BD_ENET_TX_WRAP) - bdp = fep->tx_bd_base; - else - bdp++; - - /* Since we have freed up a buffer, the ring is no longer - * full. - */ - if (fep->tx_full) { - fep->tx_full = 0; - if (netif_queue_stopped(dev)) - netif_wake_queue(dev); - } -#ifdef CONFIG_FEC_PACKETHOOK - /* Re-read register. Not exactly guaranteed to be correct, - but... */ - if (fep->ph_regaddr) regval = *fep->ph_regaddr; -#endif - } - fep->dirty_tx = (cbd_t *)bdp; - spin_unlock(&fep->lock); -} - - -/* During a receive, the cur_rx points to the current incoming buffer. - * When we update through the ring, if the next incoming buffer has - * not been given to the system, we just set the empty indicator, - * effectively tossing the packet. - */ -static void -#ifdef CONFIG_FEC_PACKETHOOK -fec_enet_rx(struct net_device *dev, __u32 regval) -#else -fec_enet_rx(struct net_device *dev) -#endif -{ - struct fec_enet_private *fep; - volatile fec_t *fecp; - volatile cbd_t *bdp; - struct sk_buff *skb; - ushort pkt_len; - __u8 *data; - - fep = dev->priv; - fecp = (volatile fec_t*)dev->base_addr; - - /* First, grab all of the stats for the incoming packet. - * These get messed up if we get called due to a busy condition. - */ - bdp = fep->cur_rx; - -while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) { - -#ifndef final_version - /* Since we have allocated space to hold a complete frame, - * the last indicator should be set. - */ - if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0) - printk("FEC ENET: rcv is not +last\n"); -#endif - - /* Check for errors. */ - if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | - BD_ENET_RX_CR | BD_ENET_RX_OV)) { - fep->stats.rx_errors++; - if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { - /* Frame too long or too short. */ - fep->stats.rx_length_errors++; - } - if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */ - fep->stats.rx_frame_errors++; - if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */ - fep->stats.rx_crc_errors++; - if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */ - fep->stats.rx_crc_errors++; - } - - /* Report late collisions as a frame error. - * On this error, the BD is closed, but we don't know what we - * have in the buffer. So, just drop this frame on the floor. - */ - if (bdp->cbd_sc & BD_ENET_RX_CL) { - fep->stats.rx_errors++; - fep->stats.rx_frame_errors++; - goto rx_processing_done; - } - - /* Process the incoming frame. - */ - fep->stats.rx_packets++; - pkt_len = bdp->cbd_datlen; - fep->stats.rx_bytes += pkt_len; - data = fep->rx_vaddr[bdp - fep->rx_bd_base]; - -#ifdef CONFIG_FEC_PACKETHOOK - /* Packet hook ... */ - if (fep->ph_rxhandler) { - if (((struct ethhdr *)data)->h_proto == fep->ph_proto) { - switch (fep->ph_rxhandler(data, pkt_len, regval, - fep->ph_priv)) { - case 1: - goto rx_processing_done; - break; - case 0: - break; - default: - fep->stats.rx_errors++; - goto rx_processing_done; - } - } - } - - /* If it wasn't filtered - copy it to an sk buffer. */ -#endif - - /* This does 16 byte alignment, exactly what we need. - * The packet length includes FCS, but we don't want to - * include that when passing upstream as it messes up - * bridging applications. - */ - skb = dev_alloc_skb(pkt_len-4); - - if (skb == NULL) { - printk("%s: Memory squeeze, dropping packet.\n", dev->name); - fep->stats.rx_dropped++; - } else { - skb_put(skb,pkt_len-4); /* Make room */ - skb_copy_to_linear_data(skb, data, pkt_len-4); - skb->protocol=eth_type_trans(skb,dev); - netif_rx(skb); - } - rx_processing_done: - - /* Clear the status flags for this buffer. - */ - bdp->cbd_sc &= ~BD_ENET_RX_STATS; - - /* Mark the buffer empty. - */ - bdp->cbd_sc |= BD_ENET_RX_EMPTY; - - /* Update BD pointer to next entry. - */ - if (bdp->cbd_sc & BD_ENET_RX_WRAP) - bdp = fep->rx_bd_base; - else - bdp++; - -#if 1 - /* Doing this here will keep the FEC running while we process - * incoming frames. On a heavily loaded network, we should be - * able to keep up at the expense of system resources. - */ - fecp->fec_r_des_active = 0x01000000; -#endif -#ifdef CONFIG_FEC_PACKETHOOK - /* Re-read register. Not exactly guaranteed to be correct, - but... */ - if (fep->ph_regaddr) regval = *fep->ph_regaddr; -#endif - } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */ - fep->cur_rx = (cbd_t *)bdp; - -#if 0 - /* Doing this here will allow us to process all frames in the - * ring before the FEC is allowed to put more there. On a heavily - * loaded network, some frames may be lost. Unfortunately, this - * increases the interrupt overhead since we can potentially work - * our way back to the interrupt return only to come right back - * here. - */ - fecp->fec_r_des_active = 0x01000000; -#endif -} - - -#ifdef CONFIG_USE_MDIO -static void -fec_enet_mii(struct net_device *dev) -{ - struct fec_enet_private *fep; - volatile fec_t *ep; - mii_list_t *mip; - uint mii_reg; - - fep = (struct fec_enet_private *)dev->priv; - ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec); - mii_reg = ep->fec_mii_data; - - if ((mip = mii_head) == NULL) { - printk("MII and no head!\n"); - return; - } - - if (mip->mii_func != NULL) - (*(mip->mii_func))(mii_reg, dev); - - mii_head = mip->mii_next; - mip->mii_next = mii_free; - mii_free = mip; - - if ((mip = mii_head) != NULL) { - ep->fec_mii_data = mip->mii_regval; - - } -} - -static int -mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) -{ - struct fec_enet_private *fep; - unsigned long flags; - mii_list_t *mip; - int retval; - - /* Add PHY address to register command. - */ - fep = dev->priv; - regval |= fep->phy_addr << 23; - - retval = 0; - - /* lock while modifying mii_list */ - spin_lock_irqsave(&fep->lock, flags); - - if ((mip = mii_free) != NULL) { - mii_free = mip->mii_next; - mip->mii_regval = regval; - mip->mii_func = func; - mip->mii_next = NULL; - if (mii_head) { - mii_tail->mii_next = mip; - mii_tail = mip; - } else { - mii_head = mii_tail = mip; - (&(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec))->fec_mii_data = regval; - } - } else { - retval = 1; - } - - spin_unlock_irqrestore(&fep->lock, flags); - - return(retval); -} - -static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) -{ - int k; - - if(!c) - return; - - for(k = 0; (c+k)->mii_data != mk_mii_end; k++) - mii_queue(dev, (c+k)->mii_data, (c+k)->funct); -} - -static void mii_parse_sr(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - volatile uint *s = &(fep->phy_status); - - *s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); - - if (mii_reg & 0x0004) - *s |= PHY_STAT_LINK; - if (mii_reg & 0x0010) - *s |= PHY_STAT_FAULT; - if (mii_reg & 0x0020) - *s |= PHY_STAT_ANC; - - fep->link = (*s & PHY_STAT_LINK) ? 1 : 0; -} - -static void mii_parse_cr(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - volatile uint *s = &(fep->phy_status); - - *s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP); - - if (mii_reg & 0x1000) - *s |= PHY_CONF_ANE; - if (mii_reg & 0x4000) - *s |= PHY_CONF_LOOP; -} - -static void mii_parse_anar(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - volatile uint *s = &(fep->phy_status); - - *s &= ~(PHY_CONF_SPMASK); - - if (mii_reg & 0x0020) - *s |= PHY_CONF_10HDX; - if (mii_reg & 0x0040) - *s |= PHY_CONF_10FDX; - if (mii_reg & 0x0080) - *s |= PHY_CONF_100HDX; - if (mii_reg & 0x00100) - *s |= PHY_CONF_100FDX; -} -#if 0 -static void mii_disp_reg(uint mii_reg, struct net_device *dev) -{ - printk("reg %u = 0x%04x\n", (mii_reg >> 18) & 0x1f, mii_reg & 0xffff); -} -#endif - -/* ------------------------------------------------------------------------- */ -/* The Level one LXT970 is used by many boards */ - -#ifdef CONFIG_FEC_LXT970 - -#define MII_LXT970_MIRROR 16 /* Mirror register */ -#define MII_LXT970_IER 17 /* Interrupt Enable Register */ -#define MII_LXT970_ISR 18 /* Interrupt Status Register */ -#define MII_LXT970_CONFIG 19 /* Configuration Register */ -#define MII_LXT970_CSR 20 /* Chip Status Register */ - -static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - volatile uint *s = &(fep->phy_status); - - *s &= ~(PHY_STAT_SPMASK); - - if (mii_reg & 0x0800) { - if (mii_reg & 0x1000) - *s |= PHY_STAT_100FDX; - else - *s |= PHY_STAT_100HDX; - } - else { - if (mii_reg & 0x1000) - *s |= PHY_STAT_10FDX; - else - *s |= PHY_STAT_10HDX; - } -} - -static phy_info_t phy_info_lxt970 = { - 0x07810000, - "LXT970", - - (const phy_cmd_t []) { /* config */ -#if 0 -// { mk_mii_write(MII_REG_ANAR, 0x0021), NULL }, - - /* Set default operation of 100-TX....for some reason - * some of these bits are set on power up, which is wrong. - */ - { mk_mii_write(MII_LXT970_CONFIG, 0), NULL }, -#endif - { mk_mii_read(MII_REG_CR), mii_parse_cr }, - { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* startup - enable interrupts */ - { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, - { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* ack_int */ - /* read SR and ISR to acknowledge */ - - { mk_mii_read(MII_REG_SR), mii_parse_sr }, - { mk_mii_read(MII_LXT970_ISR), NULL }, - - /* find out the current status */ - - { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* shutdown - disable interrupts */ - { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, - { mk_mii_end, } - }, -}; - -#endif /* CONFIG_FEC_LXT970 */ - -/* ------------------------------------------------------------------------- */ -/* The Level one LXT971 is used on some of my custom boards */ - -#ifdef CONFIG_FEC_LXT971 - -/* register definitions for the 971 */ - -#define MII_LXT971_PCR 16 /* Port Control Register */ -#define MII_LXT971_SR2 17 /* Status Register 2 */ -#define MII_LXT971_IER 18 /* Interrupt Enable Register */ -#define MII_LXT971_ISR 19 /* Interrupt Status Register */ -#define MII_LXT971_LCR 20 /* LED Control Register */ -#define MII_LXT971_TCR 30 /* Transmit Control Register */ - -/* - * I had some nice ideas of running the MDIO faster... - * The 971 should support 8MHz and I tried it, but things acted really - * weird, so 2.5 MHz ought to be enough for anyone... - */ - -static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - volatile uint *s = &(fep->phy_status); - - *s &= ~(PHY_STAT_SPMASK); - - if (mii_reg & 0x4000) { - if (mii_reg & 0x0200) - *s |= PHY_STAT_100FDX; - else - *s |= PHY_STAT_100HDX; - } - else { - if (mii_reg & 0x0200) - *s |= PHY_STAT_10FDX; - else - *s |= PHY_STAT_10HDX; - } - if (mii_reg & 0x0008) - *s |= PHY_STAT_FAULT; -} - -static phy_info_t phy_info_lxt971 = { - 0x0001378e, - "LXT971", - - (const phy_cmd_t []) { /* config */ -// { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */ - { mk_mii_read(MII_REG_CR), mii_parse_cr }, - { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* startup - enable interrupts */ - { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, - { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ - - /* Somehow does the 971 tell me that the link is down - * the first read after power-up. - * read here to get a valid value in ack_int */ - - { mk_mii_read(MII_REG_SR), mii_parse_sr }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* ack_int */ - /* find out the current status */ - - { mk_mii_read(MII_REG_SR), mii_parse_sr }, - { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, - - /* we only need to read ISR to acknowledge */ - - { mk_mii_read(MII_LXT971_ISR), NULL }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* shutdown - disable interrupts */ - { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, - { mk_mii_end, } - }, -}; - -#endif /* CONFIG_FEC_LXT970 */ - - -/* ------------------------------------------------------------------------- */ -/* The Quality Semiconductor QS6612 is used on the RPX CLLF */ - -#ifdef CONFIG_FEC_QS6612 - -/* register definitions */ - -#define MII_QS6612_MCR 17 /* Mode Control Register */ -#define MII_QS6612_FTR 27 /* Factory Test Register */ -#define MII_QS6612_MCO 28 /* Misc. Control Register */ -#define MII_QS6612_ISR 29 /* Interrupt Source Register */ -#define MII_QS6612_IMR 30 /* Interrupt Mask Register */ -#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ - -static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - volatile uint *s = &(fep->phy_status); - - *s &= ~(PHY_STAT_SPMASK); - - switch((mii_reg >> 2) & 7) { - case 1: *s |= PHY_STAT_10HDX; break; - case 2: *s |= PHY_STAT_100HDX; break; - case 5: *s |= PHY_STAT_10FDX; break; - case 6: *s |= PHY_STAT_100FDX; break; - } -} - -static phy_info_t phy_info_qs6612 = { - 0x00181440, - "QS6612", - - (const phy_cmd_t []) { /* config */ -// { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */ - - /* The PHY powers up isolated on the RPX, - * so send a command to allow operation. - */ - - { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, - - /* parse cr and anar to get some info */ - - { mk_mii_read(MII_REG_CR), mii_parse_cr }, - { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* startup - enable interrupts */ - { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, - { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* ack_int */ - - /* we need to read ISR, SR and ANER to acknowledge */ - - { mk_mii_read(MII_QS6612_ISR), NULL }, - { mk_mii_read(MII_REG_SR), mii_parse_sr }, - { mk_mii_read(MII_REG_ANER), NULL }, - - /* read pcr to get info */ - - { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* shutdown - disable interrupts */ - { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, - { mk_mii_end, } - }, -}; - -#endif /* CONFIG_FEC_QS6612 */ - -/* ------------------------------------------------------------------------- */ -/* The Advanced Micro Devices AM79C874 is used on the ICU862 */ - -#ifdef CONFIG_FEC_AM79C874 - -/* register definitions for the 79C874 */ - -#define MII_AM79C874_MFR 16 /* Miscellaneous Features Register */ -#define MII_AM79C874_ICSR 17 /* Interrupt Control/Status Register */ -#define MII_AM79C874_DR 18 /* Diagnostic Register */ -#define MII_AM79C874_PMLR 19 /* Power Management & Loopback Register */ -#define MII_AM79C874_MCR 21 /* Mode Control Register */ -#define MII_AM79C874_DC 23 /* Disconnect Counter */ -#define MII_AM79C874_REC 24 /* Receiver Error Counter */ - -static void mii_parse_amd79c874_dr(uint mii_reg, struct net_device *dev, uint data) -{ - volatile struct fec_enet_private *fep = dev->priv; - uint s = fep->phy_status; - - s &= ~(PHY_STAT_SPMASK); - - /* Register 18: Bit 10 is data rate, 11 is Duplex */ - switch ((mii_reg >> 10) & 3) { - case 0: s |= PHY_STAT_10HDX; break; - case 1: s |= PHY_STAT_100HDX; break; - case 2: s |= PHY_STAT_10FDX; break; - case 3: s |= PHY_STAT_100FDX; break; - } - - fep->phy_status = s; -} - -static phy_info_t phy_info_amd79c874 = { - 0x00022561, - "AM79C874", - - (const phy_cmd_t []) { /* config */ -// { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */ - { mk_mii_read(MII_REG_CR), mii_parse_cr }, - { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* startup - enable interrupts */ - { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, - { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* ack_int */ - /* find out the current status */ - - { mk_mii_read(MII_REG_SR), mii_parse_sr }, - { mk_mii_read(MII_AM79C874_DR), mii_parse_amd79c874_dr }, - - /* we only need to read ICSR to acknowledge */ - - { mk_mii_read(MII_AM79C874_ICSR), NULL }, - { mk_mii_end, } - }, - (const phy_cmd_t []) { /* shutdown - disable interrupts */ - { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, - { mk_mii_end, } - }, -}; - -#endif /* CONFIG_FEC_AM79C874 */ - -static phy_info_t *phy_info[] = { - -#ifdef CONFIG_FEC_LXT970 - &phy_info_lxt970, -#endif /* CONFIG_FEC_LXT970 */ - -#ifdef CONFIG_FEC_LXT971 - &phy_info_lxt971, -#endif /* CONFIG_FEC_LXT971 */ - -#ifdef CONFIG_FEC_QS6612 - &phy_info_qs6612, -#endif /* CONFIG_FEC_QS6612 */ - -#ifdef CONFIG_FEC_AM79C874 - &phy_info_amd79c874, -#endif /* CONFIG_FEC_AM79C874 */ - - NULL -}; - -static void mii_display_status(struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - volatile uint *s = &(fep->phy_status); - - if (!fep->link && !fep->old_link) { - /* Link is still down - don't print anything */ - return; - } - - printk("%s: status: ", dev->name); - - if (!fep->link) { - printk("link down"); - } else { - printk("link up"); - - switch(*s & PHY_STAT_SPMASK) { - case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break; - case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break; - case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break; - case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break; - default: - printk(", Unknown speed/duplex"); - } - - if (*s & PHY_STAT_ANC) - printk(", auto-negotiation complete"); - } - - if (*s & PHY_STAT_FAULT) - printk(", remote fault"); - - printk(".\n"); -} - -static void mii_display_config(struct work_struct *work) -{ - struct fec_enet_private *fep = - container_of(work, struct fec_enet_private, phy_task); - struct net_device *dev = fep->dev; - volatile uint *s = &(fep->phy_status); - - printk("%s: config: auto-negotiation ", dev->name); - - if (*s & PHY_CONF_ANE) - printk("on"); - else - printk("off"); - - if (*s & PHY_CONF_100FDX) - printk(", 100FDX"); - if (*s & PHY_CONF_100HDX) - printk(", 100HDX"); - if (*s & PHY_CONF_10FDX) - printk(", 10FDX"); - if (*s & PHY_CONF_10HDX) - printk(", 10HDX"); - if (!(*s & PHY_CONF_SPMASK)) - printk(", No speed/duplex selected?"); - - if (*s & PHY_CONF_LOOP) - printk(", loopback enabled"); - - printk(".\n"); - - fep->sequence_done = 1; -} - -static void mii_relink(struct work_struct *work) -{ - struct fec_enet_private *fep = - container_of(work, struct fec_enet_private, phy_task); - struct net_device *dev = fep->dev; - int duplex; - - fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; - mii_display_status(dev); - fep->old_link = fep->link; - - if (fep->link) { - duplex = 0; - if (fep->phy_status - & (PHY_STAT_100FDX | PHY_STAT_10FDX)) - duplex = 1; - fec_restart(dev, duplex); - } - else - fec_stop(dev); - -#if 0 - enable_irq(fep->mii_irq); -#endif - -} - -static void mii_queue_relink(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - - fep->dev = dev; - INIT_WORK(&fep->phy_task, mii_relink); - schedule_work(&fep->phy_task); -} - -static void mii_queue_config(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - - fep->dev = dev; - INIT_WORK(&fep->phy_task, mii_display_config); - schedule_work(&fep->phy_task); -} - - - -phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink }, - { mk_mii_end, } }; -phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config }, - { mk_mii_end, } }; - - - -/* Read remainder of PHY ID. -*/ -static void -mii_discover_phy3(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep; - int i; - - fep = dev->priv; - fep->phy_id |= (mii_reg & 0xffff); - - for(i = 0; phy_info[i]; i++) - if(phy_info[i]->id == (fep->phy_id >> 4)) - break; - - if(!phy_info[i]) - panic("%s: PHY id 0x%08x is not supported!\n", - dev->name, fep->phy_id); - - fep->phy = phy_info[i]; - fep->phy_id_done = 1; - - printk("%s: Phy @ 0x%x, type %s (0x%08x)\n", - dev->name, fep->phy_addr, fep->phy->name, fep->phy_id); -} - -/* Scan all of the MII PHY addresses looking for someone to respond - * with a valid ID. This usually happens quickly. - */ -static void -mii_discover_phy(uint mii_reg, struct net_device *dev) -{ - struct fec_enet_private *fep; - uint phytype; - - fep = dev->priv; - - if ((phytype = (mii_reg & 0xffff)) != 0xffff) { - - /* Got first part of ID, now get remainder. - */ - fep->phy_id = phytype << 16; - mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3); - } else { - fep->phy_addr++; - if (fep->phy_addr < 32) { - mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), - mii_discover_phy); - } else { - printk("fec: No PHY device found.\n"); - } - } -} -#endif /* CONFIG_USE_MDIO */ - -/* This interrupt occurs when the PHY detects a link change. -*/ -static -#ifdef CONFIG_RPXCLASSIC -void mii_link_interrupt(void *dev_id) -#else -irqreturn_t mii_link_interrupt(int irq, void * dev_id) -#endif -{ -#ifdef CONFIG_USE_MDIO - struct net_device *dev = dev_id; - struct fec_enet_private *fep = dev->priv; - volatile immap_t *immap = (immap_t *)IMAP_ADDR; - volatile fec_t *fecp = &(immap->im_cpm.cp_fec); - unsigned int ecntrl = fecp->fec_ecntrl; - - /* We need the FEC enabled to access the MII - */ - if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) { - fecp->fec_ecntrl |= FEC_ECNTRL_ETHER_EN; - } -#endif /* CONFIG_USE_MDIO */ - -#if 0 - disable_irq(fep->mii_irq); /* disable now, enable later */ -#endif - - -#ifdef CONFIG_USE_MDIO - mii_do_cmd(dev, fep->phy->ack_int); - mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ - - if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) { - fecp->fec_ecntrl = ecntrl; /* restore old settings */ - } -#else -printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__, __LINE__, __func__); -#endif /* CONFIG_USE_MDIO */ - -#ifndef CONFIG_RPXCLASSIC - return IRQ_RETVAL(IRQ_HANDLED); -#endif /* CONFIG_RPXCLASSIC */ -} - -static int -fec_enet_open(struct net_device *dev) -{ - struct fec_enet_private *fep = dev->priv; - - /* I should reset the ring buffers here, but I don't yet know - * a simple way to do that. - */ - -#ifdef CONFIG_USE_MDIO - fep->sequence_done = 0; - fep->link = 0; - - if (fep->phy) { - mii_do_cmd(dev, fep->phy->ack_int); - mii_do_cmd(dev, fep->phy->config); - mii_do_cmd(dev, phy_cmd_config); /* display configuration */ - while(!fep->sequence_done) - schedule(); - - mii_do_cmd(dev, fep->phy->startup); - netif_start_queue(dev); - return 0; /* Success */ - } - return -ENODEV; /* No PHY we understand */ -#else - fep->link = 1; - netif_start_queue(dev); - return 0; /* Success */ -#endif /* CONFIG_USE_MDIO */ - -} - -static int -fec_enet_close(struct net_device *dev) -{ - /* Don't know what to do yet. - */ - netif_stop_queue(dev); - fec_stop(dev); - - return 0; -} - -static struct net_device_stats *fec_enet_get_stats(struct net_device *dev) -{ - struct fec_enet_private *fep = (struct fec_enet_private *)dev->priv; - - return &fep->stats; -} - -/* Set or clear the multicast filter for this adaptor. - * Skeleton taken from sunlance driver. - * The CPM Ethernet implementation allows Multicast as well as individual - * MAC address filtering. Some of the drivers check to make sure it is - * a group multicast address, and discard those that are not. I guess I - * will do the same for now, but just remove the test if you want - * individual filtering as well (do the upper net layers want or support - * this kind of feature?). - */ - -static void set_multicast_list(struct net_device *dev) -{ - struct fec_enet_private *fep; - volatile fec_t *ep; - - fep = (struct fec_enet_private *)dev->priv; - ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec); - - if (dev->flags&IFF_PROMISC) { - - /* Log any net taps. */ - printk("%s: Promiscuous mode enabled.\n", dev->name); - ep->fec_r_cntrl |= FEC_RCNTRL_PROM; - } else { - - ep->fec_r_cntrl &= ~FEC_RCNTRL_PROM; - - if (dev->flags & IFF_ALLMULTI) { - /* Catch all multicast addresses, so set the - * filter to all 1's. - */ - ep->fec_hash_table_high = 0xffffffff; - ep->fec_hash_table_low = 0xffffffff; - } -#if 0 - else { - /* Clear filter and add the addresses in the list. - */ - ep->sen_gaddr1 = 0; - ep->sen_gaddr2 = 0; - ep->sen_gaddr3 = 0; - ep->sen_gaddr4 = 0; - - dmi = dev->mc_list; - - for (i=0; imc_count; i++) { - - /* Only support group multicast for now. - */ - if (!(dmi->dmi_addr[0] & 1)) - continue; - - /* The address in dmi_addr is LSB first, - * and taddr is MSB first. We have to - * copy bytes MSB first from dmi_addr. - */ - mcptr = (u_char *)dmi->dmi_addr + 5; - tdptr = (u_char *)&ep->sen_taddrh; - for (j=0; j<6; j++) - *tdptr++ = *mcptr--; - - /* Ask CPM to run CRC and set bit in - * filter mask. - */ - cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC1, CPM_CR_SET_GADDR) | CPM_CR_FLG; - /* this delay is necessary here -- Cort */ - udelay(10); - while (cpmp->cp_cpcr & CPM_CR_FLG); - } - } -#endif - } -} - -/* Initialize the FEC Ethernet on 860T. - */ -static int __init fec_enet_init(void) -{ - struct net_device *dev; - struct fec_enet_private *fep; - int i, j, k, err; - unsigned char *eap, *iap, *ba; - dma_addr_t mem_addr; - volatile cbd_t *bdp; - cbd_t *cbd_base; - volatile immap_t *immap; - volatile fec_t *fecp; - bd_t *bd; -#ifdef CONFIG_SCC_ENET - unsigned char tmpaddr[6]; -#endif - - immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ - - bd = (bd_t *)__res; - - dev = alloc_etherdev(sizeof(*fep)); - if (!dev) - return -ENOMEM; - - fep = dev->priv; - - fecp = &(immap->im_cpm.cp_fec); - - /* Whack a reset. We should wait for this. - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printk ("FEC Reset timeout!\n"); - } - - /* Set the Ethernet address. If using multiple Enets on the 8xx, - * this needs some work to get unique addresses. - */ - eap = (unsigned char *)my_enet_addr; - iap = bd->bi_enetaddr; - -#ifdef CONFIG_SCC_ENET - /* - * If a board has Ethernet configured both on a SCC and the - * FEC, it needs (at least) 2 MAC addresses (we know that Sun - * disagrees, but anyway). For the FEC port, we create - * another address by setting one of the address bits above - * something that would have (up to now) been allocated. - */ - for (i=0; i<6; i++) - tmpaddr[i] = *iap++; - tmpaddr[3] |= 0x80; - iap = tmpaddr; -#endif - - for (i=0; i<6; i++) { - dev->dev_addr[i] = *eap++ = *iap++; - } - - /* Allocate memory for buffer descriptors. - */ - if (((RX_RING_SIZE + TX_RING_SIZE) * sizeof(cbd_t)) > PAGE_SIZE) { - printk("FEC init error. Need more space.\n"); - printk("FEC initialization failed.\n"); - return 1; - } - cbd_base = (cbd_t *)dma_alloc_coherent(dev->class_dev.dev, PAGE_SIZE, - &mem_addr, GFP_KERNEL); - - /* Set receive and transmit descriptor base. - */ - fep->rx_bd_base = cbd_base; - fep->tx_bd_base = cbd_base + RX_RING_SIZE; - - fep->skb_cur = fep->skb_dirty = 0; - - /* Initialize the receive buffer descriptors. - */ - bdp = fep->rx_bd_base; - k = 0; - for (i=0; iclass_dev.dev, - PAGE_SIZE, - &mem_addr, - GFP_KERNEL); - /* BUG: no check for failure */ - - /* Initialize the BD for every fragment in the page. - */ - for (j=0; jcbd_sc = BD_ENET_RX_EMPTY; - bdp->cbd_bufaddr = mem_addr; - fep->rx_vaddr[k++] = ba; - mem_addr += FEC_ENET_RX_FRSIZE; - ba += FEC_ENET_RX_FRSIZE; - bdp++; - } - } - - /* Set the last buffer to wrap. - */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; - -#ifdef CONFIG_FEC_PACKETHOOK - fep->ph_lock = 0; - fep->ph_rxhandler = fep->ph_txhandler = NULL; - fep->ph_proto = 0; - fep->ph_regaddr = NULL; - fep->ph_priv = NULL; -#endif - - /* Install our interrupt handler. - */ - if (request_irq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0) - panic("Could not allocate FEC IRQ!"); - -#ifdef CONFIG_RPXCLASSIC - /* Make Port C, bit 15 an input that causes interrupts. - */ - immap->im_ioport.iop_pcpar &= ~0x0001; - immap->im_ioport.iop_pcdir &= ~0x0001; - immap->im_ioport.iop_pcso &= ~0x0001; - immap->im_ioport.iop_pcint |= 0x0001; - cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev); - - /* Make LEDS reflect Link status. - */ - *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE; -#endif - -#ifdef PHY_INTERRUPT - ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |= - (0x80000000 >> PHY_INTERRUPT); - - if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0, "mii", dev) != 0) - panic("Could not allocate MII IRQ!"); -#endif - - dev->base_addr = (unsigned long)fecp; - - /* The FEC Ethernet specific entries in the device structure. */ - dev->open = fec_enet_open; - dev->hard_start_xmit = fec_enet_start_xmit; - dev->tx_timeout = fec_timeout; - dev->watchdog_timeo = TX_TIMEOUT; - dev->stop = fec_enet_close; - dev->get_stats = fec_enet_get_stats; - dev->set_multicast_list = set_multicast_list; - -#ifdef CONFIG_USE_MDIO - for (i=0; iim_ioport.iop_pdpar = 0x1fff; - - /* Bits moved from Rev. D onward. - */ - if ((mfspr(SPRN_IMMR) & 0xffff) < 0x0501) - immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ - else - immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ - -#ifdef CONFIG_USE_MDIO - /* Set MII speed to 2.5 MHz - */ - fecp->fec_mii_speed = fep->phy_speed = - (( (bd->bi_intfreq + 500000) / 2500000 / 2 ) & 0x3F ) << 1; -#else - fecp->fec_mii_speed = 0; /* turn off MDIO */ -#endif /* CONFIG_USE_MDIO */ - - err = register_netdev(dev); - if (err) { - free_netdev(dev); - return err; - } - - printk ("%s: FEC ENET Version 0.2, FEC irq %d" -#ifdef PHY_INTERRUPT - ", MII irq %d" -#endif - ", addr ", - dev->name, FEC_INTERRUPT -#ifdef PHY_INTERRUPT - , PHY_INTERRUPT -#endif - ); - for (i=0; i<6; i++) - printk("%02x%c", dev->dev_addr[i], (i==5) ? '\n' : ':'); - -#ifdef CONFIG_USE_MDIO /* start in full duplex mode, and negotiate speed */ - fec_restart (dev, 1); -#else /* always use half duplex mode only */ - fec_restart (dev, 0); -#endif - -#ifdef CONFIG_USE_MDIO - /* Queue up command to detect the PHY and initialize the - * remainder of the interface. - */ - fep->phy_id_done = 0; - fep->phy_addr = 0; - mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); -#endif /* CONFIG_USE_MDIO */ - - return 0; -} -module_init(fec_enet_init); - -/* This function is called to start or restart the FEC during a link - * change. This only happens when switching between half and full - * duplex. - */ -static void -fec_restart(struct net_device *dev, int duplex) -{ - struct fec_enet_private *fep; - int i; - volatile cbd_t *bdp; - volatile immap_t *immap; - volatile fec_t *fecp; - - immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ - - fecp = &(immap->im_cpm.cp_fec); - - fep = dev->priv; - - /* Whack a reset. We should wait for this. - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printk ("FEC Reset timeout!\n"); - } - - /* Set station address. - */ - fecp->fec_addr_low = (my_enet_addr[0] << 16) | my_enet_addr[1]; - fecp->fec_addr_high = my_enet_addr[2]; - - /* Reset all multicast. - */ - fecp->fec_hash_table_high = 0; - fecp->fec_hash_table_low = 0; - - /* Set maximum receive buffer size. - */ - fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; - fecp->fec_r_hash = PKT_MAXBUF_SIZE; - - /* Set receive and transmit descriptor base. - */ - fecp->fec_r_des_start = iopa((uint)(fep->rx_bd_base)); - fecp->fec_x_des_start = iopa((uint)(fep->tx_bd_base)); - - fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; - fep->cur_rx = fep->rx_bd_base; - - /* Reset SKB transmit buffers. - */ - fep->skb_cur = fep->skb_dirty = 0; - for (i=0; i<=TX_RING_MOD_MASK; i++) { - if (fep->tx_skbuff[i] != NULL) { - dev_kfree_skb(fep->tx_skbuff[i]); - fep->tx_skbuff[i] = NULL; - } - } - - /* Initialize the receive buffer descriptors. - */ - bdp = fep->rx_bd_base; - for (i=0; icbd_sc = BD_ENET_RX_EMPTY; - bdp++; - } - - /* Set the last buffer to wrap. - */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; - - /* ...and the same for transmit. - */ - bdp = fep->tx_bd_base; - for (i=0; icbd_sc = 0; - bdp->cbd_bufaddr = 0; - bdp++; - } - - /* Set the last buffer to wrap. - */ - bdp--; - bdp->cbd_sc |= BD_SC_WRAP; - - /* Enable MII mode. - */ - if (duplex) { - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; /* MII enable */ - fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; /* FD enable */ - } - else { - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; - fecp->fec_x_cntrl = 0; - } - fep->full_duplex = duplex; - - /* Enable big endian and don't care about SDMA FC. - */ - fecp->fec_fun_code = 0x78000000; - -#ifdef CONFIG_USE_MDIO - /* Set MII speed. - */ - fecp->fec_mii_speed = fep->phy_speed; -#endif /* CONFIG_USE_MDIO */ - - /* Clear any outstanding interrupt. - */ - fecp->fec_ievent = 0xffc0; - - fecp->fec_ivec = (FEC_INTERRUPT/2) << 29; - - /* Enable interrupts we wish to service. - */ - fecp->fec_imask = ( FEC_ENET_TXF | FEC_ENET_TXB | - FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII ); - - /* And last, enable the transmit and receive processing. - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; - fecp->fec_r_des_active = 0x01000000; -} - -static void -fec_stop(struct net_device *dev) -{ - volatile immap_t *immap; - volatile fec_t *fecp; - struct fec_enet_private *fep; - int i; - - immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ - - fecp = &(immap->im_cpm.cp_fec); - - if ((fecp->fec_ecntrl & FEC_ECNTRL_ETHER_EN) == 0) - return; /* already down */ - - fep = dev->priv; - - - fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */ - - for (i = 0; - ((fecp->fec_ievent & 0x10000000) == 0) && (i < FEC_RESET_DELAY); - ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printk ("FEC timeout on graceful transmit stop\n"); - } - - /* Clear outstanding MII command interrupts. - */ - fecp->fec_ievent = FEC_ENET_MII; - - /* Enable MII command finished interrupt - */ - fecp->fec_ivec = (FEC_INTERRUPT/2) << 29; - fecp->fec_imask = FEC_ENET_MII; - -#ifdef CONFIG_USE_MDIO - /* Set MII speed. - */ - fecp->fec_mii_speed = fep->phy_speed; -#endif /* CONFIG_USE_MDIO */ - - /* Disable FEC - */ - fecp->fec_ecntrl &= ~(FEC_ECNTRL_ETHER_EN); -} diff --git a/arch/ppc/8xx_io/micropatch.c b/arch/ppc/8xx_io/micropatch.c deleted file mode 100644 index 9a5d95da7c28..000000000000 --- a/arch/ppc/8xx_io/micropatch.c +++ /dev/null @@ -1,743 +0,0 @@ - -/* Microcode patches for the CPM as supplied by Motorola. - * This is the one for IIC/SPI. There is a newer one that - * also relocates SMC2, but this would require additional changes - * to uart.c, so I am holding off on that for a moment. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * I2C/SPI relocation patch arrays. - */ - -#ifdef CONFIG_I2C_SPI_UCODE_PATCH - -uint patch_2000[] = { - 0x7FFFEFD9, - 0x3FFD0000, - 0x7FFB49F7, - 0x7FF90000, - 0x5FEFADF7, - 0x5F89ADF7, - 0x5FEFAFF7, - 0x5F89AFF7, - 0x3A9CFBC8, - 0xE7C0EDF0, - 0x77C1E1BB, - 0xF4DC7F1D, - 0xABAD932F, - 0x4E08FDCF, - 0x6E0FAFF8, - 0x7CCF76CF, - 0xFD1FF9CF, - 0xABF88DC6, - 0xAB5679F7, - 0xB0937383, - 0xDFCE79F7, - 0xB091E6BB, - 0xE5BBE74F, - 0xB3FA6F0F, - 0x6FFB76CE, - 0xEE0DF9CF, - 0x2BFBEFEF, - 0xCFEEF9CF, - 0x76CEAD24, - 0x90B2DF9A, - 0x7FDDD0BF, - 0x4BF847FD, - 0x7CCF76CE, - 0xCFEF7E1F, - 0x7F1D7DFD, - 0xF0B6EF71, - 0x7FC177C1, - 0xFBC86079, - 0xE722FBC8, - 0x5FFFDFFF, - 0x5FB2FFFB, - 0xFBC8F3C8, - 0x94A67F01, - 0x7F1D5F39, - 0xAFE85F5E, - 0xFFDFDF96, - 0xCB9FAF7D, - 0x5FC1AFED, - 0x8C1C5FC1, - 0xAFDD5FC3, - 0xDF9A7EFD, - 0xB0B25FB2, - 0xFFFEABAD, - 0x5FB2FFFE, - 0x5FCE600B, - 0xE6BB600B, - 0x5FCEDFC6, - 0x27FBEFDF, - 0x5FC8CFDE, - 0x3A9CE7C0, - 0xEDF0F3C8, - 0x7F0154CD, - 0x7F1D2D3D, - 0x363A7570, - 0x7E0AF1CE, - 0x37EF2E68, - 0x7FEE10EC, - 0xADF8EFDE, - 0xCFEAE52F, - 0x7D0FE12B, - 0xF1CE5F65, - 0x7E0A4DF8, - 0xCFEA5F72, - 0x7D0BEFEE, - 0xCFEA5F74, - 0xE522EFDE, - 0x5F74CFDA, - 0x0B627385, - 0xDF627E0A, - 0x30D8145B, - 0xBFFFF3C8, - 0x5FFFDFFF, - 0xA7F85F5E, - 0xBFFE7F7D, - 0x10D31450, - 0x5F36BFFF, - 0xAF785F5E, - 0xBFFDA7F8, - 0x5F36BFFE, - 0x77FD30C0, - 0x4E08FDCF, - 0xE5FF6E0F, - 0xAFF87E1F, - 0x7E0FFD1F, - 0xF1CF5F1B, - 0xABF80D5E, - 0x5F5EFFEF, - 0x79F730A2, - 0xAFDD5F34, - 0x47F85F34, - 0xAFED7FDD, - 0x50B24978, - 0x47FD7F1D, - 0x7DFD70AD, - 0xEF717EC1, - 0x6BA47F01, - 0x2D267EFD, - 0x30DE5F5E, - 0xFFFD5F5E, - 0xFFEF5F5E, - 0xFFDF0CA0, - 0xAFED0A9E, - 0xAFDD0C3A, - 0x5F3AAFBD, - 0x7FBDB082, - 0x5F8247F8 -}; - -uint patch_2f00[] = { - 0x3E303430, - 0x34343737, - 0xABF7BF9B, - 0x994B4FBD, - 0xBD599493, - 0x349FFF37, - 0xFB9B177D, - 0xD9936956, - 0xBBFDD697, - 0xBDD2FD11, - 0x31DB9BB3, - 0x63139637, - 0x93733693, - 0x193137F7, - 0x331737AF, - 0x7BB9B999, - 0xBB197957, - 0x7FDFD3D5, - 0x73B773F7, - 0x37933B99, - 0x1D115316, - 0x99315315, - 0x31694BF4, - 0xFBDBD359, - 0x31497353, - 0x76956D69, - 0x7B9D9693, - 0x13131979, - 0x79376935 -}; -#endif - -/* - * I2C/SPI/SMC1 relocation patch arrays. - */ - -#ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH - -uint patch_2000[] = { - 0x3fff0000, - 0x3ffd0000, - 0x3ffb0000, - 0x3ff90000, - 0x5f13eff8, - 0x5eb5eff8, - 0x5f88adf7, - 0x5fefadf7, - 0x3a9cfbc8, - 0x77cae1bb, - 0xf4de7fad, - 0xabae9330, - 0x4e08fdcf, - 0x6e0faff8, - 0x7ccf76cf, - 0xfdaff9cf, - 0xabf88dc8, - 0xab5879f7, - 0xb0925d8d, - 0xdfd079f7, - 0xb090e6bb, - 0xe5bbe74f, - 0x9e046f0f, - 0x6ffb76ce, - 0xee0cf9cf, - 0x2bfbefef, - 0xcfeef9cf, - 0x76cead23, - 0x90b3df99, - 0x7fddd0c1, - 0x4bf847fd, - 0x7ccf76ce, - 0xcfef77ca, - 0x7eaf7fad, - 0x7dfdf0b7, - 0xef7a7fca, - 0x77cafbc8, - 0x6079e722, - 0xfbc85fff, - 0xdfff5fb3, - 0xfffbfbc8, - 0xf3c894a5, - 0xe7c9edf9, - 0x7f9a7fad, - 0x5f36afe8, - 0x5f5bffdf, - 0xdf95cb9e, - 0xaf7d5fc3, - 0xafed8c1b, - 0x5fc3afdd, - 0x5fc5df99, - 0x7efdb0b3, - 0x5fb3fffe, - 0xabae5fb3, - 0xfffe5fd0, - 0x600be6bb, - 0x600b5fd0, - 0xdfc827fb, - 0xefdf5fca, - 0xcfde3a9c, - 0xe7c9edf9, - 0xf3c87f9e, - 0x54ca7fed, - 0x2d3a3637, - 0x756f7e9a, - 0xf1ce37ef, - 0x2e677fee, - 0x10ebadf8, - 0xefdecfea, - 0xe52f7d9f, - 0xe12bf1ce, - 0x5f647e9a, - 0x4df8cfea, - 0x5f717d9b, - 0xefeecfea, - 0x5f73e522, - 0xefde5f73, - 0xcfda0b61, - 0x5d8fdf61, - 0xe7c9edf9, - 0x7e9a30d5, - 0x1458bfff, - 0xf3c85fff, - 0xdfffa7f8, - 0x5f5bbffe, - 0x7f7d10d0, - 0x144d5f33, - 0xbfffaf78, - 0x5f5bbffd, - 0xa7f85f33, - 0xbffe77fd, - 0x30bd4e08, - 0xfdcfe5ff, - 0x6e0faff8, - 0x7eef7e9f, - 0xfdeff1cf, - 0x5f17abf8, - 0x0d5b5f5b, - 0xffef79f7, - 0x309eafdd, - 0x5f3147f8, - 0x5f31afed, - 0x7fdd50af, - 0x497847fd, - 0x7f9e7fed, - 0x7dfd70a9, - 0xef7e7ece, - 0x6ba07f9e, - 0x2d227efd, - 0x30db5f5b, - 0xfffd5f5b, - 0xffef5f5b, - 0xffdf0c9c, - 0xafed0a9a, - 0xafdd0c37, - 0x5f37afbd, - 0x7fbdb081, - 0x5f8147f8, - 0x3a11e710, - 0xedf0ccdd, - 0xf3186d0a, - 0x7f0e5f06, - 0x7fedbb38, - 0x3afe7468, - 0x7fedf4fc, - 0x8ffbb951, - 0xb85f77fd, - 0xb0df5ddd, - 0xdefe7fed, - 0x90e1e74d, - 0x6f0dcbf7, - 0xe7decfed, - 0xcb74cfed, - 0xcfeddf6d, - 0x91714f74, - 0x5dd2deef, - 0x9e04e7df, - 0xefbb6ffb, - 0xe7ef7f0e, - 0x9e097fed, - 0xebdbeffa, - 0xeb54affb, - 0x7fea90d7, - 0x7e0cf0c3, - 0xbffff318, - 0x5fffdfff, - 0xac59efea, - 0x7fce1ee5, - 0xe2ff5ee1, - 0xaffbe2ff, - 0x5ee3affb, - 0xf9cc7d0f, - 0xaef8770f, - 0x7d0fb0c6, - 0xeffbbfff, - 0xcfef5ede, - 0x7d0fbfff, - 0x5ede4cf8, - 0x7fddd0bf, - 0x49f847fd, - 0x7efdf0bb, - 0x7fedfffd, - 0x7dfdf0b7, - 0xef7e7e1e, - 0x5ede7f0e, - 0x3a11e710, - 0xedf0ccab, - 0xfb18ad2e, - 0x1ea9bbb8, - 0x74283b7e, - 0x73c2e4bb, - 0x2ada4fb8, - 0xdc21e4bb, - 0xb2a1ffbf, - 0x5e2c43f8, - 0xfc87e1bb, - 0xe74ffd91, - 0x6f0f4fe8, - 0xc7ba32e2, - 0xf396efeb, - 0x600b4f78, - 0xe5bb760b, - 0x53acaef8, - 0x4ef88b0e, - 0xcfef9e09, - 0xabf8751f, - 0xefef5bac, - 0x741f4fe8, - 0x751e760d, - 0x7fdbf081, - 0x741cafce, - 0xefcc7fce, - 0x751e70ac, - 0x741ce7bb, - 0x3372cfed, - 0xafdbefeb, - 0xe5bb760b, - 0x53f2aef8, - 0xafe8e7eb, - 0x4bf8771e, - 0x7e247fed, - 0x4fcbe2cc, - 0x7fbc30a9, - 0x7b0f7a0f, - 0x34d577fd, - 0x308b5db7, - 0xde553e5f, - 0xaf78741f, - 0x741f30f0, - 0xcfef5e2c, - 0x741f3eac, - 0xafb8771e, - 0x5e677fed, - 0x0bd3e2cc, - 0x741ccfec, - 0xe5ca53cd, - 0x6fcb4f74, - 0x5dadde4b, - 0x2ab63d38, - 0x4bb3de30, - 0x751f741c, - 0x6c42effa, - 0xefea7fce, - 0x6ffc30be, - 0xefec3fca, - 0x30b3de2e, - 0xadf85d9e, - 0xaf7daefd, - 0x5d9ede2e, - 0x5d9eafdd, - 0x761f10ac, - 0x1da07efd, - 0x30adfffe, - 0x4908fb18, - 0x5fffdfff, - 0xafbb709b, - 0x4ef85e67, - 0xadf814ad, - 0x7a0f70ad, - 0xcfef50ad, - 0x7a0fde30, - 0x5da0afed, - 0x3c12780f, - 0xefef780f, - 0xefef790f, - 0xa7f85e0f, - 0xffef790f, - 0xefef790f, - 0x14adde2e, - 0x5d9eadfd, - 0x5e2dfffb, - 0xe79addfd, - 0xeff96079, - 0x607ae79a, - 0xddfceff9, - 0x60795dff, - 0x607acfef, - 0xefefefdf, - 0xefbfef7f, - 0xeeffedff, - 0xebffe7ff, - 0xafefafdf, - 0xafbfaf7f, - 0xaeffadff, - 0xabffa7ff, - 0x6fef6fdf, - 0x6fbf6f7f, - 0x6eff6dff, - 0x6bff67ff, - 0x2fef2fdf, - 0x2fbf2f7f, - 0x2eff2dff, - 0x2bff27ff, - 0x4e08fd1f, - 0xe5ff6e0f, - 0xaff87eef, - 0x7e0ffdef, - 0xf11f6079, - 0xabf8f542, - 0x7e0af11c, - 0x37cfae3a, - 0x7fec90be, - 0xadf8efdc, - 0xcfeae52f, - 0x7d0fe12b, - 0xf11c6079, - 0x7e0a4df8, - 0xcfea5dc4, - 0x7d0befec, - 0xcfea5dc6, - 0xe522efdc, - 0x5dc6cfda, - 0x4e08fd1f, - 0x6e0faff8, - 0x7c1f761f, - 0xfdeff91f, - 0x6079abf8, - 0x761cee24, - 0xf91f2bfb, - 0xefefcfec, - 0xf91f6079, - 0x761c27fb, - 0xefdf5da7, - 0xcfdc7fdd, - 0xd09c4bf8, - 0x47fd7c1f, - 0x761ccfcf, - 0x7eef7fed, - 0x7dfdf093, - 0xef7e7f1e, - 0x771efb18, - 0x6079e722, - 0xe6bbe5bb, - 0xae0ae5bb, - 0x600bae85, - 0xe2bbe2bb, - 0xe2bbe2bb, - 0xaf02e2bb, - 0xe2bb2ff9, - 0x6079e2bb -}; - -uint patch_2f00[] = { - 0x30303030, - 0x3e3e3434, - 0xabbf9b99, - 0x4b4fbdbd, - 0x59949334, - 0x9fff37fb, - 0x9b177dd9, - 0x936956bb, - 0xfbdd697b, - 0xdd2fd113, - 0x1db9f7bb, - 0x36313963, - 0x79373369, - 0x3193137f, - 0x7331737a, - 0xf7bb9b99, - 0x9bb19795, - 0x77fdfd3d, - 0x573b773f, - 0x737933f7, - 0xb991d115, - 0x31699315, - 0x31531694, - 0xbf4fbdbd, - 0x35931497, - 0x35376956, - 0xbd697b9d, - 0x96931313, - 0x19797937, - 0x6935af78, - 0xb9b3baa3, - 0xb8788683, - 0x368f78f7, - 0x87778733, - 0x3ffffb3b, - 0x8e8f78b8, - 0x1d118e13, - 0xf3ff3f8b, - 0x6bd8e173, - 0xd1366856, - 0x68d1687b, - 0x3daf78b8, - 0x3a3a3f87, - 0x8f81378f, - 0xf876f887, - 0x77fd8778, - 0x737de8d6, - 0xbbf8bfff, - 0xd8df87f7, - 0xfd876f7b, - 0x8bfff8bd, - 0x8683387d, - 0xb873d87b, - 0x3b8fd7f8, - 0xf7338883, - 0xbb8ee1f8, - 0xef837377, - 0x3337b836, - 0x817d11f8, - 0x7378b878, - 0xd3368b7d, - 0xed731b7d, - 0x833731f3, - 0xf22f3f23 -}; - -uint patch_2e00[] = { - 0x27eeeeee, - 0xeeeeeeee, - 0xeeeeeeee, - 0xeeeeeeee, - 0xee4bf4fb, - 0xdbd259bb, - 0x1979577f, - 0xdfd2d573, - 0xb773f737, - 0x4b4fbdbd, - 0x25b9b177, - 0xd2d17376, - 0x956bbfdd, - 0x697bdd2f, - 0xff9f79ff, - 0xff9ff22f -}; -#endif - -/* - * USB SOF patch arrays. - */ - -#ifdef CONFIG_USB_SOF_UCODE_PATCH - -uint patch_2000[] = { - 0x7fff0000, - 0x7ffd0000, - 0x7ffb0000, - 0x49f7ba5b, - 0xba383ffb, - 0xf9b8b46d, - 0xe5ab4e07, - 0xaf77bffe, - 0x3f7bbf79, - 0xba5bba38, - 0xe7676076, - 0x60750000 -}; - -uint patch_2f00[] = { - 0x3030304c, - 0xcab9e441, - 0xa1aaf220 -}; -#endif - -void -cpm_load_patch(volatile immap_t *immr) -{ - volatile uint *dp; /* Dual-ported RAM. */ - volatile cpm8xx_t *commproc; - volatile iic_t *iip; - volatile spi_t *spp; - volatile smc_uart_t *smp; - int i; - - commproc = (cpm8xx_t *)&immr->im_cpm; - -#ifdef CONFIG_USB_SOF_UCODE_PATCH - commproc->cp_rccr = 0; - - dp = (uint *)(commproc->cp_dpmem); - for (i=0; i<(sizeof(patch_2000)/4); i++) - *dp++ = patch_2000[i]; - - dp = (uint *)&(commproc->cp_dpmem[0x0f00]); - for (i=0; i<(sizeof(patch_2f00)/4); i++) - *dp++ = patch_2f00[i]; - - commproc->cp_rccr = 0x0009; - - printk("USB SOF microcode patch installed\n"); -#endif /* CONFIG_USB_SOF_UCODE_PATCH */ - -#if defined(CONFIG_I2C_SPI_UCODE_PATCH) || \ - defined(CONFIG_I2C_SPI_SMC1_UCODE_PATCH) - - commproc->cp_rccr = 0; - - dp = (uint *)(commproc->cp_dpmem); - for (i=0; i<(sizeof(patch_2000)/4); i++) - *dp++ = patch_2000[i]; - - dp = (uint *)&(commproc->cp_dpmem[0x0f00]); - for (i=0; i<(sizeof(patch_2f00)/4); i++) - *dp++ = patch_2f00[i]; - - iip = (iic_t *)&commproc->cp_dparam[PROFF_IIC]; -# define RPBASE 0x0500 - iip->iic_rpbase = RPBASE; - - /* Put SPI above the IIC, also 32-byte aligned. - */ - i = (RPBASE + sizeof(iic_t) + 31) & ~31; - spp = (spi_t *)&commproc->cp_dparam[PROFF_SPI]; - spp->spi_rpbase = i; - -# if defined(CONFIG_I2C_SPI_UCODE_PATCH) - commproc->cp_cpmcr1 = 0x802a; - commproc->cp_cpmcr2 = 0x8028; - commproc->cp_cpmcr3 = 0x802e; - commproc->cp_cpmcr4 = 0x802c; - commproc->cp_rccr = 1; - - printk("I2C/SPI microcode patch installed.\n"); -# endif /* CONFIG_I2C_SPI_UCODE_PATCH */ - -# if defined(CONFIG_I2C_SPI_SMC1_UCODE_PATCH) - - dp = (uint *)&(commproc->cp_dpmem[0x0e00]); - for (i=0; i<(sizeof(patch_2e00)/4); i++) - *dp++ = patch_2e00[i]; - - commproc->cp_cpmcr1 = 0x8080; - commproc->cp_cpmcr2 = 0x808a; - commproc->cp_cpmcr3 = 0x8028; - commproc->cp_cpmcr4 = 0x802a; - commproc->cp_rccr = 3; - - smp = (smc_uart_t *)&commproc->cp_dparam[PROFF_SMC1]; - smp->smc_rpbase = 0x1FC0; - - printk("I2C/SPI/SMC1 microcode patch installed.\n"); -# endif /* CONFIG_I2C_SPI_SMC1_UCODE_PATCH) */ - -#endif /* some variation of the I2C/SPI patch was selected */ -} - -/* - * Take this entire routine out, since no one calls it and its - * logic is suspect. - */ - -#if 0 -void -verify_patch(volatile immap_t *immr) -{ - volatile uint *dp; - volatile cpm8xx_t *commproc; - int i; - - commproc = (cpm8xx_t *)&immr->im_cpm; - - printk("cp_rccr %x\n", commproc->cp_rccr); - commproc->cp_rccr = 0; - - dp = (uint *)(commproc->cp_dpmem); - for (i=0; i<(sizeof(patch_2000)/4); i++) - if (*dp++ != patch_2000[i]) { - printk("patch_2000 bad at %d\n", i); - dp--; - printk("found 0x%X, wanted 0x%X\n", *dp, patch_2000[i]); - break; - } - - dp = (uint *)&(commproc->cp_dpmem[0x0f00]); - for (i=0; i<(sizeof(patch_2f00)/4); i++) - if (*dp++ != patch_2f00[i]) { - printk("patch_2f00 bad at %d\n", i); - dp--; - printk("found 0x%X, wanted 0x%X\n", *dp, patch_2f00[i]); - break; - } - - commproc->cp_rccr = 0x0009; -} -#endif diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig deleted file mode 100644 index 0f1863ed9c1c..000000000000 --- a/arch/ppc/Kconfig +++ /dev/null @@ -1,1186 +0,0 @@ -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Linux/PowerPC Kernel Configuration" - -config WORD_SIZE - int - default 32 - -config MMU - bool - default y - -config GENERIC_HARDIRQS - bool - default y - -config RWSEM_GENERIC_SPINLOCK - bool - -config RWSEM_XCHGADD_ALGORITHM - bool - default y - -config ARCH_HAS_ILOG2_U32 - bool - default y - -config ARCH_HAS_ILOG2_U64 - bool - default n - -config GENERIC_HWEIGHT - bool - default y - -config GENERIC_CALIBRATE_DELAY - bool - default y - -config PPC - bool - default y - select HAVE_IDE - select HAVE_OPROFILE - select HAVE_KPROBES - -config PPC32 - bool - default y - -# All PPCs use generic nvram driver through ppc_md -config GENERIC_NVRAM - bool - default y - -config GENERIC_FIND_NEXT_BIT - bool - default y - -config SCHED_NO_NO_OMIT_FRAME_POINTER - bool - default y - -config ARCH_MAY_HAVE_PC_FDC - bool - default y - -config GENERIC_BUG - bool - default y - depends on BUG - -source "init/Kconfig" - -menu "Processor" - -choice - prompt "Processor Type" - default 6xx - -config 6xx - bool "6xx/7xx/74xx/52xx/82xx" - select PPC_FPU - help - There are four types of PowerPC chips supported. The more common - types (601, 603, 604, 740, 750, 7400), the older Freescale - (formerly Motorola) embedded versions (821, 823, 850, 855, 860, - 52xx, 82xx), the IBM embedded versions (403 and 405) and - the Book E embedded processors from IBM (44x) and Freescale (85xx). - For support for 64-bit processors, set ARCH=powerpc. - Unless you are building a kernel for one of the embedded processor - systems, choose 6xx. - Also note that because the 52xx, 82xx family have a 603e - core, specific support for that chipset is asked later on. - -config 40x - bool "40x" - select PPC_DCR_NATIVE - -config 44x - bool "44x" - select PPC_DCR_NATIVE - -config 8xx - bool "8xx" - select PPC_LIB_RHEAP - -endchoice - -config PPC_FPU - bool - -config PPC_DCR_NATIVE - bool - default n - -config PPC_DCR - bool - depends on PPC_DCR_NATIVE - default y - -config PTE_64BIT - bool - depends on 44x - default y if 44x - -config PHYS_64BIT - bool - depends on 44x - default y if 44x - ---help--- - This option enables kernel support for larger than 32-bit physical - addresses. This features is not be available on all e500 cores. - - If in doubt, say N here. - -config ALTIVEC - bool "AltiVec Support" - depends on 6xx - depends on !8260 - ---help--- - This option enables kernel support for the Altivec extensions to the - PowerPC processor. The kernel currently supports saving and restoring - altivec registers, and turning on the 'altivec enable' bit so user - processes can execute altivec instructions. - - This option is only usefully if you have a processor that supports - altivec (G4, otherwise known as 74xx series), but does not have - any affect on a non-altivec cpu (it does, however add code to the - kernel). - - If in doubt, say Y here. - -config TAU - bool "Thermal Management Support" - depends on 6xx && !8260 - help - G3 and G4 processors have an on-chip temperature sensor called the - 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die - temperature within 2-4 degrees Celsius. This option shows the current - on-die temperature in /proc/cpuinfo if the cpu supports it. - - Unfortunately, on some chip revisions, this sensor is very inaccurate - and in some cases, does not work at all, so don't assume the cpu - temp is actually what /proc/cpuinfo says it is. - -config TAU_INT - bool "Interrupt driven TAU driver (DANGEROUS)" - depends on TAU - ---help--- - The TAU supports an interrupt driven mode which causes an interrupt - whenever the temperature goes out of range. This is the fastest way - to get notified the temp has exceeded a range. With this option off, - a timer is used to re-check the temperature periodically. - - However, on some cpus it appears that the TAU interrupt hardware - is buggy and can cause a situation which would lead unexplained hard - lockups. - - Unless you are extending the TAU driver, or enjoy kernel/hardware - debugging, leave this option off. - -config TAU_AVERAGE - bool "Average high and low temp" - depends on TAU - ---help--- - The TAU hardware can compare the temperature to an upper and lower - bound. The default behavior is to show both the upper and lower - bound in /proc/cpuinfo. If the range is large, the temperature is - either changing a lot, or the TAU hardware is broken (likely on some - G4's). If the range is small (around 4 degrees), the temperature is - relatively stable. If you say Y here, a single temperature value, - halfway between the upper and lower bounds, will be reported in - /proc/cpuinfo. - - If in doubt, say N here. - -config MATH_EMULATION - bool "Math emulation" - depends on 4xx || 8xx - ---help--- - Some PowerPC chips designed for embedded applications do not have - a floating-point unit and therefore do not implement the - floating-point instructions in the PowerPC instruction set. If you - say Y here, the kernel will include code to emulate a floating-point - unit, which will allow programs that use floating-point - instructions to run. - - If you have an Apple machine or an IBM RS/6000 or pSeries machine, - or any machine with a 6xx, 7xx or 7xxx series processor, say N - here. Saying Y here will not hurt performance (on any machine) but - will increase the size of the kernel. - -config KEXEC - bool "kexec system call (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - kexec is a system call that implements the ability to shutdown your - current kernel, and to start another kernel. It is like a reboot - but it is independent of the system firmware. And like a reboot - you can start any kernel with it, not just Linux. - - The name comes from the similarity to the exec system call. - - It is an ongoing process to be certain the hardware in a machine - is properly shutdown, so do not be surprised if this code does not - initially work for you. It may help to enable device hotplugging - support. As of this writing the exact hardware interface is - strongly in flux, so no good recommendation can be made. - - In the GameCube implementation, kexec allows you to load and - run DOL files, including kernel and homebrew DOLs. - -source "drivers/cpufreq/Kconfig" - -config PPC601_SYNC_FIX - bool "Workarounds for PPC601 bugs" - depends on 6xx && PPC_PREP - help - Some versions of the PPC601 (the first PowerPC chip) have bugs which - mean that extra synchronization instructions are required near - certain instructions, typically those that make major changes to the - CPU state. These extra instructions reduce performance slightly. - If you say N here, these extra instructions will not be included, - resulting in a kernel which will run faster but may not run at all - on some systems with the PPC601 chip. - - If in doubt, say Y here. - -source arch/ppc/platforms/4xx/Kconfig - -config PPC_STD_MMU - bool - depends on 6xx - default y - -config NOT_COHERENT_CACHE - bool - depends on 4xx || 8xx - default y - -endmenu - -menu "Platform options" - -config FADS - bool - -choice - prompt "8xx Machine Type" - depends on 8xx - default RPXLITE - -config RPXLITE - bool "RPX-Lite" - ---help--- - Single-board computers based around the PowerPC MPC8xx chips and - intended for embedded applications. The following types are - supported: - - RPX-Lite: - Embedded Planet RPX Lite. PC104 form-factor SBC based on the MPC823. - - RPX-Classic: - Embedded Planet RPX Classic Low-fat. Credit-card-size SBC based on - the MPC 860 - - BSE-IP: - Bright Star Engineering ip-Engine. - - TQM823L: - TQM850L: - TQM855L: - TQM860L: - MPC8xx based family of mini modules, half credit card size, - up to 64 MB of RAM, 8 MB Flash, (Fast) Ethernet, 2 x serial ports, - 2 x CAN bus interface, ... - Manufacturer: TQ Components, www.tq-group.de - Date of Release: October (?) 1999 - End of Life: not yet :-) - URL: - - module: - - starter kit: - - images: - - FPS850L: - FingerPrint Sensor System (based on TQM850L) - Manufacturer: IKENDI AG, - Date of Release: November 1999 - End of life: end 2000 ? - URL: see TQM850L - - IVMS8: - MPC860 based board used in the "Integrated Voice Mail System", - Small Version (8 voice channels) - Manufacturer: Speech Design, - Date of Release: December 2000 (?) - End of life: - - URL: - - IVML24: - MPC860 based board used in the "Integrated Voice Mail System", - Large Version (24 voice channels) - Manufacturer: Speech Design, - Date of Release: March 2001 (?) - End of life: - - URL: - - HERMES: - Hermes-Pro ISDN/LAN router with integrated 8 x hub - Manufacturer: Multidata Gesellschaft fur Datentechnik und Informatik - - Date of Release: 2000 (?) - End of life: - - URL: - - IP860: - VMEBus IP (Industry Pack) carrier board with MPC860 - Manufacturer: MicroSys GmbH, - Date of Release: ? - End of life: - - URL: - - PCU_E: - PCU = Peripheral Controller Unit, Extended - Manufacturer: Siemens AG, ICN (Information and Communication Networks) - - Date of Release: April 2001 - End of life: August 2001 - URL: n. a. - -config RPXCLASSIC - bool "RPX-Classic" - help - The RPX-Classic is a single-board computer based on the Motorola - MPC860. It features 16MB of DRAM and a variable amount of flash, - I2C EEPROM, thermal monitoring, a PCMCIA slot, a DIP switch and two - LEDs. Variants with Ethernet ports exist. Say Y here to support it - directly. - -config BSEIP - bool "BSE-IP" - help - Say Y here to support the Bright Star Engineering ipEngine SBC. - This is a credit-card-sized device featuring a MPC823 processor, - 26MB DRAM, 4MB flash, Ethernet, a 16K-gate FPGA, USB, an LCD/video - controller, and two RS232 ports. - -config MPC8XXFADS - bool "FADS" - select FADS - -config TQM823L - bool "TQM823L" - help - Say Y here to support the TQM823L, one of an MPC8xx-based family of - mini SBCs (half credit-card size) from TQ Components first released - in late 1999. Technical references are at - , and - , and an image at - . - -config TQM850L - bool "TQM850L" - help - Say Y here to support the TQM850L, one of an MPC8xx-based family of - mini SBCs (half credit-card size) from TQ Components first released - in late 1999. Technical references are at - , and - , and an image at - . - -config TQM855L - bool "TQM855L" - help - Say Y here to support the TQM855L, one of an MPC8xx-based family of - mini SBCs (half credit-card size) from TQ Components first released - in late 1999. Technical references are at - , and - , and an image at - . - -config TQM860L - bool "TQM860L" - help - Say Y here to support the TQM860L, one of an MPC8xx-based family of - mini SBCs (half credit-card size) from TQ Components first released - in late 1999. Technical references are at - , and - , and an image at - . - -config FPS850L - bool "FPS850L" - -config IVMS8 - bool "IVMS8" - help - Say Y here to support the Integrated Voice-Mail Small 8-channel SBC - from Speech Design, released March 2001. The manufacturer's website - is at . - -config IVML24 - bool "IVML24" - help - Say Y here to support the Integrated Voice-Mail Large 24-channel SBC - from Speech Design, released March 2001. The manufacturer's website - is at . - -config HERMES_PRO - bool "HERMES" - -config IP860 - bool "IP860" - -config LWMON - bool "LWMON" - -config PCU_E - bool "PCU_E" - -config CCM - bool "CCM" - -config LANTEC - bool "LANTEC" - -config MBX - bool "MBX" - help - MBX is a line of Motorola single-board computer based around the - MPC821 and MPC860 processors, and intended for embedded-controller - applications. Say Y here to support these boards directly. - -config WINCEPT - bool "WinCept" - help - The Wincept 100/110 is a Motorola single-board computer based on the - MPC821 PowerPC, introduced in 1998 and designed to be used in - thin-client machines. Say Y to support it directly. - -endchoice - -choice - prompt "Machine Type" - depends on 6xx - default PPC_PREP - ---help--- - Linux currently supports several different kinds of PowerPC-based - machines: Apple Power Macintoshes and clones (such as the Motorola - Starmax series), PReP (PowerPC Reference Platform) machines (such - as the Motorola PowerStacks, Motorola cPCI/VME embedded systems, - and some IBM RS/6000 systems), CHRP (Common Hardware Reference - Platform) machines (including all of the recent IBM RS/6000 and - pSeries machines), and several embedded PowerPC systems containing - 4xx, 6xx, 7xx, 8xx, 74xx, and 82xx processors. Currently, the - default option is to build a kernel which works on PReP. - - Note that support for Apple and CHRP machines is now only available - with ARCH=powerpc, and has been removed from this menu. If you - wish to build a kernel for an Apple or CHRP machine, exit this - configuration process and re-run it with ARCH=powerpc. - - Select PReP if configuring for a PReP machine. - -config PPC_PREP - bool "PReP" - -config KATANA - bool "Artesyn-Katana" - help - Select KATANA if configuring an Artesyn KATANA 750i or 3750 - cPCI board. - -config WILLOW - bool "Cogent-Willow" - -config CPCI690 - bool "Force-CPCI690" - help - Select CPCI690 if configuring a Force CPCI690 cPCI board. - -config POWERPMC250 - bool "Force-PowerPMC250" - -config CHESTNUT - bool "IBM 750FX Eval board or 750GX Eval board" - help - Select CHESTNUT if configuring an IBM 750FX Eval Board or a - IBM 750GX Eval board. - -config SPRUCE - bool "IBM-Spruce" - select PPC_INDIRECT_PCI - -config HDPU - bool "Sky-HDPU" - help - Select HDPU if configuring a Sky Computers Compute Blade. - -config HDPU_FEATURES - depends on HDPU - tristate "HDPU-Features" - help - Select to enable HDPU enhanced features. - -config EV64260 - bool "Marvell-EV64260BP" - help - Select EV64260 if configuring a Marvell (formerly Galileo) - EV64260BP Evaluation platform. - -config LOPEC - bool "Motorola-LoPEC" - select PPC_I8259 - -config MVME5100 - bool "Motorola-MVME5100" - select PPC_INDIRECT_PCI - -config PPLUS - bool "Motorola-PowerPlus" - select PPC_I8259 - select PPC_INDIRECT_PCI - -config PRPMC750 - bool "Motorola-PrPMC750" - select PPC_INDIRECT_PCI - -config PRPMC800 - bool "Motorola-PrPMC800" - select PPC_INDIRECT_PCI - -config SANDPOINT - bool "Motorola-Sandpoint" - select PPC_I8259 - help - Select SANDPOINT if configuring for a Motorola Sandpoint X3 - (any flavor). - -config RADSTONE_PPC7D - bool "Radstone Technology PPC7D board" - select PPC_I8259 - -config PAL4 - bool "SBS-Palomar4" - -config EST8260 - bool "EST8260" - ---help--- - The EST8260 is a single-board computer manufactured by Wind River - Systems, Inc. (formerly Embedded Support Tools Corp.) and based on - the MPC8260. Wind River Systems has a website at - , but the EST8260 cannot be found on it - and has probably been discontinued or rebadged. - -config SBC82xx - bool "SBC82xx" - ---help--- - SBC PowerQUICC II, single-board computer with MPC82xx CPU - Manufacturer: Wind River Systems, Inc. - Date of Release: May 2003 - End of Life: - - URL: - -config SBS8260 - bool "SBS8260" - -config RPX8260 - bool "RPXSUPER" - -config TQM8260 - bool "TQM8260" - ---help--- - MPC8260 based module, little larger than credit card, - up to 128 MB global + 64 MB local RAM, 32 MB Flash, - 32 kB EEPROM, 256 kB L@ Cache, 10baseT + 100baseT Ethernet, - 2 x serial ports, ... - Manufacturer: TQ Components, www.tq-group.de - Date of Release: June 2001 - End of Life: not yet :-) - URL: - -config PQ2FADS - bool "Freescale-PQ2FADS" - help - Select PQ2FADS if you wish to configure for a Freescale - PQ2FADS board (-VR or -ZU). - -config LITE5200 - bool "Freescale LITE5200 / (IceCube)" - select PPC_MPC52xx - help - Support for the LITE5200 dev board for the MPC5200 from Freescale. - This is for the LITE5200 version 2.0 board. Don't know if it changes - much but it's only been tested on this board version. I think this - board is also known as IceCube. - -config LITE5200B - bool "Freescale LITE5200B" - depends on LITE5200 - help - Support for the LITE5200B dev board for the MPC5200 from Freescale. - This is the new board with 2 PCI slots. - -config EV64360 - bool "Marvell-EV64360BP" - help - Select EV64360 if configuring a Marvell EV64360BP Evaluation - platform. -endchoice - -config TQM8xxL - bool - depends on 8xx && (TQM823L || TQM850L || FPS850L || TQM855L || TQM860L) - default y - -config EMBEDDEDBOOT - bool - depends on 8xx || 8260 - default y - -config PPC_MPC52xx - bool - -config 8260 - bool "CPM2 Support" if WILLOW - depends on 6xx - default y if TQM8260 || RPX8260 || EST8260 || SBS8260 || SBC82xx || PQ2FADS - help - The MPC8260 is a typical embedded CPU made by Motorola. Selecting - this option means that you wish to build a kernel for a machine with - an 8260 class CPU. - -config CPM1 - bool - depends on 8xx - default y - help - The CPM1 (Communications Processor Module) is a coprocessor on - embedded CPUs made by Motorola. Selecting this option means that - you wish to build a kernel for a machine with a CPM1 coprocessor - on it (8xx, 827x, 8560). - -config CPM2 - bool - depends on 8260 || MPC8560 || MPC8555 - select PPC_LIB_RHEAP - default y - help - The CPM2 (Communications Processor Module) is a coprocessor on - embedded CPUs made by Motorola. Selecting this option means that - you wish to build a kernel for a machine with a CPM2 coprocessor - on it (826x, 827x, 8560). - -config PPC_GEN550 - bool - depends on SANDPOINT || SPRUCE || PPLUS || \ - PRPMC750 || PRPMC800 || LOPEC || \ - (EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D - default y - -config FORCE - bool - depends on 6xx && POWERPMC250 - default y - -config GT64260 - bool - depends on EV64260 || CPCI690 - default y - -config MV64360 # Really MV64360 & MV64460 - bool - depends on CHESTNUT || KATANA || RADSTONE_PPC7D || HDPU || EV64360 - default y - -config MV64X60 - bool - depends on (GT64260 || MV64360) - select PPC_INDIRECT_PCI - default y - -config MV643XX_ETH_0 - bool - depends on MV643XX_ETH && (KATANA || RADSTONE_PPC7D || EV64360 || HDPU) - default y - -config MV643XX_ETH_1 - bool - depends on MV643XX_ETH && (KATANA || RADSTONE_PPC7D || EV64360) - default y - -config MV643XX_ETH_2 - bool - depends on MV643XX_ETH && (KATANA || RADSTONE_PPC7D || EV64360) - default y - -menu "Set bridge options" - depends on MV64X60 - -config NOT_COHERENT_CACHE - bool "Turn off Cache Coherency" - default n - help - Some 64x60 bridges lock up when trying to enforce cache coherency. - When this option is selected, cache coherency will be turned off. - Note that this can cause other problems (e.g., stale data being - speculatively loaded via a cached mapping). Use at your own risk. - -config MV64X60_BASE - hex "Set bridge base used by firmware" - default "0xf1000000" - help - A firmware can leave the base address of the bridge's registers at - a non-standard location. If so, set this value to reflect the - address of that non-standard location. - -config MV64X60_NEW_BASE - hex "Set bridge base used by kernel" - default "0xf1000000" - help - If the current base address of the bridge's registers is not where - you want it, set this value to the address that you want it moved to. - -endmenu - -config NONMONARCH_SUPPORT - bool "Enable Non-Monarch Support" - depends on PRPMC800 - -config HARRIER - bool - depends on PRPMC800 - default y - -config EPIC_SERIAL_MODE - bool - depends on 6xx && (LOPEC || SANDPOINT) - default y - -config MPC10X_BRIDGE - bool - depends on POWERPMC250 || LOPEC || SANDPOINT - select PPC_INDIRECT_PCI - default y - -config MPC10X_OPENPIC - bool - depends on POWERPMC250 || LOPEC || SANDPOINT - default y - -config MPC10X_STORE_GATHERING - bool "Enable MPC10x store gathering" - depends on MPC10X_BRIDGE - -config SANDPOINT_ENABLE_UART1 - bool "Enable DUART mode on Sandpoint" - depends on SANDPOINT - help - If this option is enabled then the MPC824x processor will run - in DUART mode instead of UART mode. - -config HARRIER_STORE_GATHERING - bool "Enable Harrier store gathering" - depends on HARRIER - -config MVME5100_IPMC761_PRESENT - bool "MVME5100 configured with an IPMC761" - depends on MVME5100 - select PPC_I8259 - -config SPRUCE_BAUD_33M - bool "Spruce baud clock support" - depends on SPRUCE - -config PC_KEYBOARD - bool "PC PS/2 style Keyboard" - depends on 4xx || CPM2 - -config PPCBUG_NVRAM - bool "Enable reading PPCBUG NVRAM during boot" if PPLUS || LOPEC - default y if PPC_PREP - -config SMP - depends on PPC_STD_MMU - bool "Symmetric multi-processing support" - ---help--- - This enables support for systems with more than one CPU. If you have - a system with only one CPU, say N. If you have a system with more - than one CPU, say Y. Note that the kernel does not currently - support SMP machines with 603/603e/603ev or PPC750 ("G3") processors - since they have inadequate hardware support for multiprocessor - operation. - - If you say N here, the kernel will run on single and multiprocessor - machines, but will use only one CPU of a multiprocessor machine. If - you say Y here, the kernel will run on single-processor machines. - On a single-processor machine, the kernel will run faster if you say - N here. - - If you don't know what to do here, say N. - -config IRQ_ALL_CPUS - bool "Distribute interrupts on all CPUs by default" - depends on SMP && !MV64360 - help - This option gives the kernel permission to distribute IRQs across - multiple CPUs. Saying N here will route all IRQs to the first - CPU. Generally saying Y is safe, although some problems have been - reported with SMP Power Macintoshes with this option enabled. - -config NR_CPUS - int "Maximum number of CPUs (2-32)" - range 2 32 - depends on SMP - default "4" - -config HIGHMEM - bool "High memory support" - -config ARCH_POPULATES_NODE_MAP - def_bool y - -source kernel/Kconfig.hz -source kernel/Kconfig.preempt -source "mm/Kconfig" - -source "fs/Kconfig.binfmt" - -config PREP_RESIDUAL - bool "Support for PReP Residual Data" - depends on PPC_PREP - help - Some PReP systems have residual data passed to the kernel by the - firmware. This allows detection of memory size, devices present and - other useful pieces of information. Sometimes this information is - not present or incorrect, in which case it could lead to the machine - behaving incorrectly. If this happens, either disable PREP_RESIDUAL - or pass the 'noresidual' option to the kernel. - - If you are running a PReP system, say Y here, otherwise say N. - -config PROC_PREPRESIDUAL - bool "Support for reading of PReP Residual Data in /proc" - depends on PREP_RESIDUAL && PROC_FS - help - Enabling this option will create a /proc/residual file which allows - you to get at the residual data on PReP systems. You will need a tool - (lsresidual) to parse it. If you aren't on a PReP system, you don't - want this. - -config CMDLINE_BOOL - bool "Default bootloader kernel arguments" - -config CMDLINE - string "Initial kernel command string" - depends on CMDLINE_BOOL - default "console=ttyS0,9600 console=tty0 root=/dev/sda2" - help - On some platforms, there is currently no way for the boot loader to - pass arguments to the kernel. For these platforms, you can supply - some command-line options at build time by entering them here. In - most cases you will need to specify the root device here. - -if BROKEN -source kernel/power/Kconfig -endif - -config SECCOMP - bool "Enable seccomp to safely compute untrusted bytecode" - depends on PROC_FS - default y - help - This kernel feature is useful for number crunching applications - that may need to compute untrusted bytecode during their - execution. By using pipes or other transports made available to - the process as file descriptors supporting the read/write - syscalls, it's possible to isolate those applications in - their own address space using seccomp. Once seccomp is - enabled via /proc//seccomp, it cannot be disabled - and the task is only allowed to execute a few safe syscalls - defined by each seccomp mode. - - If unsure, say Y. Only embedded should say N here. - -endmenu - -config ISA_DMA_API - bool - default y - -menu "Bus options" - -config ISA - bool "Support for ISA-bus hardware" - depends on PPC_PREP - help - Find out whether you have ISA slots on your motherboard. ISA is the - name of a bus system, i.e. the way the CPU talks to the other stuff - inside your box. If you have an Apple machine, say N here; if you - have an IBM RS/6000 or pSeries machine or a PReP machine, say Y. If - you have an embedded board, consult your board documentation. - -config ZONE_DMA - bool - default y - -config GENERIC_ISA_DMA - bool - depends on 6xx && !CPM2 - default y - -config PPC_I8259 - bool - default y if PPC_PREP - default n - -config PPC_INDIRECT_PCI - bool - depends on PCI - default y if 40x || 44x || PPC_PREP - default n - -config EISA - bool - help - The Extended Industry Standard Architecture (EISA) bus is a bus - architecture used on some older intel-based PCs. - -config SBUS - bool - -# Yes MCA RS/6000s exist but Linux-PPC does not currently support any -config MCA - bool - -config PCI - bool "PCI support" if 40x || CPM2 || PPC_MPC52xx - default y if !40x && !CPM2 && !8xx - default PCI_QSPAN if !4xx && !CPM2 && 8xx - help - Find out whether your system includes a PCI bus. PCI is the name of - a bus system, i.e. the way the CPU talks to the other stuff inside - your box. If you say Y here, the kernel will include drivers and - infrastructure code to support PCI bus devices. - -config PCI_DOMAINS - def_bool PCI - -config PCI_SYSCALL - def_bool PCI - -config PCI_QSPAN - bool "QSpan PCI" - depends on !4xx && !CPM2 && 8xx - select PPC_I8259 - help - Say Y here if you have a system based on a Motorola 8xx-series - embedded processor with a QSPAN PCI interface, otherwise say N. - -config PCI_8260 - bool - depends on PCI && 8260 - select PPC_INDIRECT_PCI - default y - -config 8260_PCI9 - bool "Enable workaround for MPC826x erratum PCI 9" - depends on PCI_8260 - default y - -choice - prompt "IDMA channel for PCI 9 workaround" - depends on 8260_PCI9 - -config 8260_PCI9_IDMA1 - bool "IDMA1" - -config 8260_PCI9_IDMA2 - bool "IDMA2" - -config 8260_PCI9_IDMA3 - bool "IDMA3" - -config 8260_PCI9_IDMA4 - bool "IDMA4" - -endchoice - -source "drivers/pci/Kconfig" - -source "drivers/pcmcia/Kconfig" - -config RAPIDIO - bool "RapidIO support" if MPC8540 || MPC8560 - help - If you say Y here, the kernel will include drivers and - infrastructure code to support RapidIO interconnect devices. - -source "drivers/rapidio/Kconfig" - -endmenu - -menu "Advanced setup" - -config ADVANCED_OPTIONS - bool "Prompt for advanced kernel configuration options" - help - This option will enable prompting for a variety of advanced kernel - configuration options. These options can cause the kernel to not - work if they are set incorrectly, but can be used to optimize certain - aspects of kernel memory management. - - Unless you know what you are doing, say N here. - -comment "Default settings for advanced configuration options are used" - depends on !ADVANCED_OPTIONS - -config HIGHMEM_START_BOOL - bool "Set high memory pool address" - depends on ADVANCED_OPTIONS && HIGHMEM - help - This option allows you to set the base address of the kernel virtual - area used to map high memory pages. This can be useful in - optimizing the layout of kernel virtual memory. - - Say N here unless you know what you are doing. - -config HIGHMEM_START - hex "Virtual start address of high memory pool" if HIGHMEM_START_BOOL - default "0xfe000000" - -config LOWMEM_SIZE_BOOL - bool "Set maximum low memory" - depends on ADVANCED_OPTIONS - help - This option allows you to set the maximum amount of memory which - will be used as "low memory", that is, memory which the kernel can - access directly, without having to set up a kernel virtual mapping. - This can be useful in optimizing the layout of kernel virtual - memory. - - Say N here unless you know what you are doing. - -config LOWMEM_SIZE - hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL - default "0x30000000" - -config KERNEL_START_BOOL - bool "Set custom kernel base address" - depends on ADVANCED_OPTIONS - help - This option allows you to set the kernel virtual address at which - the kernel will map low memory (the kernel image will be linked at - this address). This can be useful in optimizing the virtual memory - layout of the system. - - Say N here unless you know what you are doing. - -config KERNEL_START - hex "Virtual address of kernel base" if KERNEL_START_BOOL - default "0xc0000000" - -config TASK_SIZE_BOOL - bool "Set custom user task size" - depends on ADVANCED_OPTIONS - help - This option allows you to set the amount of virtual address space - allocated to user tasks. This can be useful in optimizing the - virtual memory layout of the system. - - Say N here unless you know what you are doing. - -config TASK_SIZE - hex "Size of user task space" if TASK_SIZE_BOOL - default "0x80000000" - -config CONSISTENT_START_BOOL - bool "Set custom consistent memory pool address" - depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE - help - This option allows you to set the base virtual address - of the consistent memory pool. This pool of virtual - memory is used to make consistent memory allocations. - -config CONSISTENT_START - hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL - default "0xff100000" if NOT_COHERENT_CACHE - -config CONSISTENT_SIZE_BOOL - bool "Set custom consistent memory pool size" - depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE - help - This option allows you to set the size of the - consistent memory pool. This pool of virtual memory - is used to make consistent memory allocations. - -config CONSISTENT_SIZE - hex "Size of consistent memory pool" if CONSISTENT_SIZE_BOOL - default "0x00200000" if NOT_COHERENT_CACHE - -config BOOT_LOAD_BOOL - bool "Set the boot link/load address" - depends on ADVANCED_OPTIONS && !PPC_PREP - help - This option allows you to set the initial load address of the zImage - or zImage.initrd file. This can be useful if you are on a board - which has a small amount of memory. - - Say N here unless you know what you are doing. - -config BOOT_LOAD - hex "Link/load address for booting" if BOOT_LOAD_BOOL - default "0x00400000" if 40x || 8xx || 8260 - default "0x01000000" if 44x - default "0x00800000" - -config PIN_TLB - bool "Pinned Kernel TLBs (860 ONLY)" - depends on ADVANCED_OPTIONS && 8xx - -config PPC_LIB_RHEAP - bool - -endmenu - -source "net/Kconfig" - -source "drivers/Kconfig" - -source "fs/Kconfig" - -source "arch/ppc/8xx_io/Kconfig" - -source "arch/ppc/8260_io/Kconfig" - - -menu "IBM 40x options" - depends on 40x - -config SERIAL_SICC - bool "SICC Serial port" - depends on STB03xxx - -config UART1_DFLT_CONSOLE - bool - depends on SERIAL_SICC && UART0_TTYS1 - default y - -config SERIAL_SICC_CONSOLE - bool - depends on SERIAL_SICC && UART0_TTYS1 - default y - -endmenu - -source "lib/Kconfig" - -source "arch/ppc/Kconfig.debug" - -source "security/Kconfig" - -source "crypto/Kconfig" diff --git a/arch/ppc/Kconfig.debug b/arch/ppc/Kconfig.debug deleted file mode 100644 index f94b87740973..000000000000 --- a/arch/ppc/Kconfig.debug +++ /dev/null @@ -1,66 +0,0 @@ -menu "Kernel hacking" - -source "lib/Kconfig.debug" - -config KGDB - bool "Include kgdb kernel debugger" - depends on DEBUG_KERNEL && (BROKEN || PPC_GEN550 || 4xx) - select DEBUG_INFO - help - Include in-kernel hooks for kgdb, the Linux kernel source level - debugger. See for more information. - Unless you are intending to debug the kernel, say N here. - -choice - prompt "Serial Port" - depends on KGDB - default KGDB_TTYS1 - -config KGDB_TTYS0 - bool "ttyS0" - -config KGDB_TTYS1 - bool "ttyS1" - -config KGDB_TTYS2 - bool "ttyS2" - -config KGDB_TTYS3 - bool "ttyS3" - -endchoice - -config KGDB_CONSOLE - bool "Enable serial console thru kgdb port" - depends on KGDB && 8xx || CPM2 - help - If you enable this, all serial console messages will be sent - over the gdb stub. - If unsure, say N. - -config XMON - bool "Include xmon kernel debugger" - depends on DEBUG_KERNEL - help - Include in-kernel hooks for the xmon kernel monitor/debugger. - Unless you are intending to debug the kernel, say N here. - -config BDI_SWITCH - bool "Include BDI-2000 user context switcher" - depends on DEBUG_KERNEL - help - Include in-kernel support for the Abatron BDI2000 debugger. - Unless you are intending to debug the kernel with one of these - machines, say N here. - -config SERIAL_TEXT_DEBUG - bool "Support for early boot texts over serial port" - depends on 4xx || LOPEC || MV64X60 || PPLUS || PRPMC800 || \ - PPC_GEN550 || PPC_MPC52xx - -config PPC_OCP - bool - depends on IBM_OCP - default y - -endmenu diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile deleted file mode 100644 index 2352d139b262..000000000000 --- a/arch/ppc/Makefile +++ /dev/null @@ -1,135 +0,0 @@ -# This file is included by the global makefile so that you can add your own -# architecture-specific flags and dependencies. -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright (C) 1994 by Linus Torvalds -# Changes for PPC by Gary Thomas -# Rewritten by Cort Dougan and Paul Mackerras -# - -# This must match PAGE_OFFSET in include/asm-ppc/page.h. -KERNELLOAD := $(CONFIG_KERNEL_START) - -HAS_BIARCH := $(call cc-option-yn, -m32) -ifeq ($(HAS_BIARCH),y) -AS := $(AS) -a32 -LD := $(LD) -m elf32ppc -CC := $(CC) -m32 -endif - -LDFLAGS_vmlinux := -Ttext $(KERNELLOAD) -Bstatic -# The -Iarch/$(ARCH)/include is temporary while we are merging -KBUILD_CPPFLAGS += -Iarch/$(ARCH) -Iarch/$(ARCH)/include -KBUILD_AFLAGS += -Iarch/$(ARCH) -KBUILD_CFLAGS += -Iarch/$(ARCH) -msoft-float -pipe \ - -ffixed-r2 -mmultiple - -# No AltiVec instruction when building kernel -KBUILD_CFLAGS += $(call cc-option, -mno-altivec) - -CPP = $(CC) -E $(KBUILD_CFLAGS) -# Temporary hack until we have migrated to asm-powerpc -LINUXINCLUDE += -Iarch/$(ARCH)/include - -CHECKFLAGS += -D__powerpc__ - -cpu-as-$(CONFIG_4xx) += -Wa,-m405 -cpu-as-$(CONFIG_6xx) += -Wa,-maltivec - -KBUILD_AFLAGS += $(cpu-as-y) -KBUILD_CFLAGS += $(cpu-as-y) - -# Default to the common case. -KBUILD_DEFCONFIG := ebony_defconfig - -head-y := arch/ppc/kernel/head.o -head-$(CONFIG_8xx) := arch/ppc/kernel/head_8xx.o -head-$(CONFIG_4xx) := arch/ppc/kernel/head_4xx.o -head-$(CONFIG_44x) := arch/ppc/kernel/head_44x.o - -head-$(CONFIG_PPC_FPU) += arch/powerpc/kernel/fpu.o - -core-y += arch/ppc/kernel/ arch/powerpc/kernel/ \ - arch/ppc/platforms/ \ - arch/ppc/mm/ arch/ppc/lib/ \ - arch/ppc/syslib/ arch/powerpc/sysdev/ \ - arch/powerpc/lib/ -core-$(CONFIG_4xx) += arch/ppc/platforms/4xx/ -core-$(CONFIG_MATH_EMULATION) += arch/powerpc/math-emu/ -core-$(CONFIG_XMON) += arch/ppc/xmon/ -drivers-$(CONFIG_8xx) += arch/ppc/8xx_io/ -drivers-$(CONFIG_4xx) += arch/ppc/4xx_io/ -drivers-$(CONFIG_CPM2) += arch/ppc/8260_io/ - -drivers-$(CONFIG_OPROFILE) += arch/powerpc/oprofile/ - -BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd vmlinux.sm - -PHONY += $(BOOT_TARGETS) - -all: uImage zImage - -CPPFLAGS_vmlinux.lds := -Upowerpc - -# All the instructions talk about "make bzImage". -bzImage: zImage - -boot := arch/$(ARCH)/boot - -$(BOOT_TARGETS): vmlinux - $(Q)$(MAKE) $(build)=$(boot) $@ - -uImage: vmlinux - $(Q)$(MAKE) $(build)=$(boot)/images $(boot)/images/$@ - -define archhelp - @echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/images/zImage.*)' - @echo ' uImage - Create a bootable image for U-Boot / PPCBoot' - @echo ' install - Install kernel using' - @echo ' (your) ~/bin/installkernel or' - @echo ' (distribution) /sbin/installkernel or' - @echo ' install to $$(INSTALL_PATH) and run lilo' - @echo ' *_defconfig - Select default config from arch/$(ARCH)/ppc/configs' -endef - -archclean: - $(Q)$(MAKE) $(clean)=arch/ppc/boot - # Temporary hack until we have migrated to asm-powerpc - $(Q)rm -rf arch/$(ARCH)/include - -archprepare: checkbin - -# Temporary hack until we have migrated to asm-powerpc -include/asm: arch/$(ARCH)/include/asm -arch/$(ARCH)/include/asm: - $(Q)if [ ! -d arch/$(ARCH)/include ]; then mkdir -p arch/$(ARCH)/include; fi - $(Q)ln -fsn $(srctree)/include/asm-powerpc arch/$(ARCH)/include/asm - -# Use the file '.tmp_gas_check' for binutils tests, as gas won't output -# to stdout and these checks are run even on install targets. -TOUT := .tmp_gas_check -# Ensure this is binutils 2.12.1 (or 2.12.90.0.7) or later for altivec -# instructions. -# gcc-3.4 and binutils-2.14 are a fatal combination. - -checkbin: - @if test "$(call cc-version)" = "0304" ; then \ - if ! /bin/echo mftb 5 | $(AS) -v -mppc -many -o $(TOUT) >/dev/null 2>&1 ; then \ - echo -n '*** ${VERSION}.${PATCHLEVEL} kernels no longer build '; \ - echo 'correctly with gcc-3.4 and your version of binutils.'; \ - echo '*** Please upgrade your binutils or downgrade your gcc'; \ - false; \ - fi ; \ - fi - @if ! /bin/echo dssall | $(AS) -many -o $(TOUT) >/dev/null 2>&1 ; then \ - echo -n '*** ${VERSION}.${PATCHLEVEL} kernels no longer build ' ; \ - echo 'correctly with old versions of binutils.' ; \ - echo '*** Please upgrade your binutils to 2.12.1 or newer' ; \ - false ; \ - fi - -CLEAN_FILES += $(TOUT) - diff --git a/arch/ppc/boot/Makefile b/arch/ppc/boot/Makefile deleted file mode 100644 index 500497e3c72d..000000000000 --- a/arch/ppc/boot/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -# -# arch/ppc/boot/Makefile -# -# This file is included by the global makefile so that you can add your own -# architecture-specific flags and dependencies. -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright (C) 1994 by Linus Torvalds -# Adapted for PowerPC by Gary Thomas -# modified by Cort (cort@cs.nmt.edu) -# - -# KBUILD_CFLAGS used when building rest of boot (takes effect recursively) -KBUILD_CFLAGS += -fno-builtin -D__BOOTER__ -Iarch/$(ARCH)/boot/include -HOSTCFLAGS += -Iarch/$(ARCH)/boot/include - -BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd - -bootdir-y := simple -subdir-y := lib common images -subdir-$(CONFIG_PPC_PREP) += of1275 - -# for cleaning -subdir- += simple - -hostprogs-y := $(addprefix utils/, mkprep mkbugboot mktree) - -PHONY += $(BOOT_TARGETS) $(bootdir-y) - -$(BOOT_TARGETS): $(bootdir-y) - -$(bootdir-y): $(addprefix $(obj)/,$(subdir-y)) \ - $(addprefix $(obj)/,$(hostprogs-y)) - $(Q)$(MAKE) $(build)=$(obj)/$@ $(MAKECMDGOALS) diff --git a/arch/ppc/boot/common/Makefile b/arch/ppc/boot/common/Makefile deleted file mode 100644 index a2e85e3beb88..000000000000 --- a/arch/ppc/boot/common/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Tom Rini January 2001 -# - -lib-y := string.o util.o misc-common.o \ - serial_stub.o bootinfo.o -lib-$(CONFIG_SERIAL_8250_CONSOLE) += ns16550.o diff --git a/arch/ppc/boot/common/bootinfo.c b/arch/ppc/boot/common/bootinfo.c deleted file mode 100644 index f4dc9b9fab9c..000000000000 --- a/arch/ppc/boot/common/bootinfo.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * General bootinfo record utilities - * Author: Randy Vinson - * - * 2002 (c) MontaVista Software, Inc. This file is licensed under the terms - * of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#include -#include -#include - -#include "nonstdio.h" - -static struct bi_record * birec = NULL; - -static struct bi_record * -__bootinfo_build(struct bi_record *rec, unsigned long tag, unsigned long size, - void *data) -{ - /* set the tag */ - rec->tag = tag; - - /* if the caller has any data, copy it */ - if (size) - memcpy(rec->data, (char *)data, size); - - /* set the record size */ - rec->size = sizeof(struct bi_record) + size; - - /* advance to the next available space */ - rec = (struct bi_record *)((unsigned long)rec + rec->size); - - return rec; -} - -void -bootinfo_init(struct bi_record *rec) -{ - - /* save start of birec area */ - birec = rec; - - /* create an empty list */ - rec = __bootinfo_build(rec, BI_FIRST, 0, NULL); - (void) __bootinfo_build(rec, BI_LAST, 0, NULL); - -} - -void -bootinfo_append(unsigned long tag, unsigned long size, void * data) -{ - - struct bi_record *rec = birec; - - /* paranoia */ - if ((rec == NULL) || (rec->tag != BI_FIRST)) - return; - - /* find the last entry in the list */ - while (rec->tag != BI_LAST) - rec = (struct bi_record *)((ulong)rec + rec->size); - - /* overlay BI_LAST record with new one and tag on a new BI_LAST */ - rec = __bootinfo_build(rec, tag, size, data); - (void) __bootinfo_build(rec, BI_LAST, 0, NULL); -} diff --git a/arch/ppc/boot/common/crt0.S b/arch/ppc/boot/common/crt0.S deleted file mode 100644 index 8f0ef04b8de5..000000000000 --- a/arch/ppc/boot/common/crt0.S +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright (c) 1997 Paul Mackerras - * Initial Power Macintosh COFF version. - * Copyright (c) 1999 Grant Erickson - * Modifications for IBM PowerPC 400-class processor evaluation - * boards. - * - * Module name: crt0.S - * - * Description: - * Boot loader execution entry point. Clears out .bss section as per - * ANSI C requirements. Invalidates and flushes the caches over the - * range covered by the boot loader's .text section. Sets up a stack - * below the .text section entry point. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include - - .text - - .globl _start -_start: -#ifdef XCOFF - .long __start,0,0 - - .globl __start -__start: -#endif - - ## Flush and invalidate the caches for the range in memory covering - ## the .text section of the boot loader - - lis r9,_start@h # r9 = &_start - lis r8,_etext@ha # - addi r8,r8,_etext@l # r8 = &_etext -3: dcbf r0,r9 # Flush the data cache - icbi r0,r9 # Invalidate the instruction cache - addi r9,r9,0x10 # Increment by one cache line - cmplw cr0,r9,r8 # Are we at the end yet? - blt 3b # No, keep flushing and invalidating - sync # sync ; isync after flushing the icache - isync - - ## Clear out the BSS as per ANSI C requirements - - lis r7,_end@ha - addi r7,r7,_end@l # r7 = &_end - lis r8,__bss_start@ha # - addi r8,r8,__bss_start@l # r8 = &_bss_start - - ## Determine how large an area, in number of words, to clear - - subf r7,r8,r7 # r7 = &_end - &_bss_start + 1 - addi r7,r7,3 # r7 += 3 - srwi. r7,r7,2 # r7 = size in words. - beq 2f # If the size is zero, do not bother - addi r8,r8,-4 # r8 -= 4 - mtctr r7 # SPRN_CTR = number of words to clear - li r0,0 # r0 = 0 -1: stwu r0,4(r8) # Clear out a word - bdnz 1b # If we are not done yet, keep clearing -2: - -#ifdef CONFIG_40x - ## Set up the stack - - lis r9,_start@h # r9 = &_start (text section entry) - ori r9,r9,_start@l - subi r1,r9,64 # Start the stack 64 bytes below _start - clrrwi r1,r1,4 # Make sure it is aligned on 16 bytes. - li r0,0 - stwu r0,-16(r1) - mtlr r9 -#endif - - b start # All done, start the real work. diff --git a/arch/ppc/boot/common/misc-common.c b/arch/ppc/boot/common/misc-common.c deleted file mode 100644 index 9589969cec72..000000000000 --- a/arch/ppc/boot/common/misc-common.c +++ /dev/null @@ -1,555 +0,0 @@ -/* - * Misc. bootloader code (almost) all platforms can use - * - * Author: Johnnie Peters - * Editor: Tom Rini - * - * Derived from arch/ppc/boot/prep/misc.c - * - * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include /* for va_ bits */ -#include -#include -#include "nonstdio.h" - -/* If we're on a PReP, assume we have a keyboard controller - * Also note, if we're not PReP, we assume you are a serial - * console - Tom */ -#if defined(CONFIG_PPC_PREP) && defined(CONFIG_VGA_CONSOLE) -extern void cursor(int x, int y); -extern void scroll(void); -extern char *vidmem; -extern int lines, cols; -extern int orig_x, orig_y; -extern int keyb_present; -extern int CRT_tstc(void); -extern int CRT_getc(void); -#else -int cursor(int x, int y) {return 0;} -void scroll(void) {} -char vidmem[1]; -#define lines 0 -#define cols 0 -int orig_x = 0; -int orig_y = 0; -#define keyb_present 0 -int CRT_tstc(void) {return 0;} -int CRT_getc(void) {return 0;} -#endif - -extern char *avail_ram; -extern char *end_avail; -extern char _end[]; - -void puts(const char *); -void putc(const char c); -void puthex(unsigned long val); -void gunzip(void *, int, unsigned char *, int *); -static int _cvt(unsigned long val, char *buf, long radix, char *digits); - -void _vprintk(void(*putc)(const char), const char *fmt0, va_list ap); -unsigned char *ISA_io = NULL; - -#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \ - || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \ - || defined(CONFIG_SERIAL_MPSC_CONSOLE) \ - || defined(CONFIG_SERIAL_UARTLITE_CONSOLE) -extern unsigned long com_port; - -extern int serial_tstc(unsigned long com_port); -extern unsigned char serial_getc(unsigned long com_port); -extern void serial_putc(unsigned long com_port, unsigned char c); -#endif - -void pause(void) -{ - puts("pause\n"); -} - -void exit(void) -{ - puts("exit\n"); - while(1); -} - -int tstc(void) -{ -#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \ - || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \ - || defined(CONFIG_SERIAL_MPSC_CONSOLE) \ - || defined(CONFIG_SERIAL_UARTLITE_CONSOLE) - if(keyb_present) - return (CRT_tstc() || serial_tstc(com_port)); - else - return (serial_tstc(com_port)); -#else - return CRT_tstc(); -#endif -} - -int getc(void) -{ - while (1) { -#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \ - || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \ - || defined(CONFIG_SERIAL_MPSC_CONSOLE) \ - || defined(CONFIG_SERIAL_UARTLITE_CONSOLE) - if (serial_tstc(com_port)) - return (serial_getc(com_port)); -#endif /* serial console */ - if (keyb_present) - if(CRT_tstc()) - return (CRT_getc()); - } -} - -void -putc(const char c) -{ - int x,y; - -#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \ - || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \ - || defined(CONFIG_SERIAL_MPSC_CONSOLE) \ - || defined(CONFIG_SERIAL_UARTLITE_CONSOLE) - serial_putc(com_port, c); - if ( c == '\n' ) - serial_putc(com_port, '\r'); -#endif /* serial console */ - - x = orig_x; - y = orig_y; - - if ( c == '\n' ) { - x = 0; - if ( ++y >= lines ) { - scroll(); - y--; - } - } else if (c == '\r') { - x = 0; - } else if (c == '\b') { - if (x > 0) { - x--; - } - } else { - vidmem [ ( x + cols * y ) * 2 ] = c; - if ( ++x >= cols ) { - x = 0; - if ( ++y >= lines ) { - scroll(); - y--; - } - } - } - - cursor(x, y); - - orig_x = x; - orig_y = y; -} - -void puts(const char *s) -{ - int x,y; - char c; - - x = orig_x; - y = orig_y; - - while ( ( c = *s++ ) != '\0' ) { -#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \ - || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \ - || defined(CONFIG_SERIAL_MPSC_CONSOLE) \ - || defined(CONFIG_SERIAL_UARTLITE_CONSOLE) - serial_putc(com_port, c); - if ( c == '\n' ) serial_putc(com_port, '\r'); -#endif /* serial console */ - - if ( c == '\n' ) { - x = 0; - if ( ++y >= lines ) { - scroll(); - y--; - } - } else if (c == '\b') { - if (x > 0) { - x--; - } - } else { - vidmem [ ( x + cols * y ) * 2 ] = c; - if ( ++x >= cols ) { - x = 0; - if ( ++y >= lines ) { - scroll(); - y--; - } - } - } - } - - cursor(x, y); - - orig_x = x; - orig_y = y; -} - -void error(char *x) -{ - puts("\n\n"); - puts(x); - puts("\n\n -- System halted"); - - while(1); /* Halt */ -} - -static void *zalloc(unsigned size) -{ - void *p = avail_ram; - - size = (size + 7) & -8; - avail_ram += size; - if (avail_ram > end_avail) { - puts("oops... out of memory\n"); - pause(); - } - return p; -} - -#define HEAD_CRC 2 -#define EXTRA_FIELD 4 -#define ORIG_NAME 8 -#define COMMENT 0x10 -#define RESERVED 0xe0 - -void gunzip(void *dst, int dstlen, unsigned char *src, int *lenp) -{ - z_stream s; - int r, i, flags; - - /* skip header */ - i = 10; - flags = src[3]; - if (src[2] != Z_DEFLATED || (flags & RESERVED) != 0) { - puts("bad gzipped data\n"); - exit(); - } - if ((flags & EXTRA_FIELD) != 0) - i = 12 + src[10] + (src[11] << 8); - if ((flags & ORIG_NAME) != 0) - while (src[i++] != 0) - ; - if ((flags & COMMENT) != 0) - while (src[i++] != 0) - ; - if ((flags & HEAD_CRC) != 0) - i += 2; - if (i >= *lenp) { - puts("gunzip: ran out of data in header\n"); - exit(); - } - - /* Initialize ourself. */ - s.workspace = zalloc(zlib_inflate_workspacesize()); - r = zlib_inflateInit2(&s, -MAX_WBITS); - if (r != Z_OK) { - puts("zlib_inflateInit2 returned "); puthex(r); puts("\n"); - exit(); - } - s.next_in = src + i; - s.avail_in = *lenp - i; - s.next_out = dst; - s.avail_out = dstlen; - r = zlib_inflate(&s, Z_FINISH); - if (r != Z_OK && r != Z_STREAM_END) { - puts("inflate returned "); puthex(r); puts("\n"); - exit(); - } - *lenp = s.next_out - (unsigned char *) dst; - zlib_inflateEnd(&s); -} - -void -puthex(unsigned long val) -{ - - unsigned char buf[10]; - int i; - for (i = 7; i >= 0; i--) - { - buf[i] = "0123456789ABCDEF"[val & 0x0F]; - val >>= 4; - } - buf[8] = '\0'; - puts(buf); -} - -#define FALSE 0 -#define TRUE 1 - -void -_printk(char const *fmt, ...) -{ - va_list ap; - - va_start(ap, fmt); - _vprintk(putc, fmt, ap); - va_end(ap); - return; -} - -#define is_digit(c) ((c >= '0') && (c <= '9')) - -void -_vprintk(void(*putc)(const char), const char *fmt0, va_list ap) -{ - char c, sign, *cp = 0; - int left_prec, right_prec, zero_fill, length = 0, pad, pad_on_right; - char buf[32]; - long val; - while ((c = *fmt0++)) - { - if (c == '%') - { - c = *fmt0++; - left_prec = right_prec = pad_on_right = 0; - if (c == '-') - { - c = *fmt0++; - pad_on_right++; - } - if (c == '0') - { - zero_fill = TRUE; - c = *fmt0++; - } else - { - zero_fill = FALSE; - } - while (is_digit(c)) - { - left_prec = (left_prec * 10) + (c - '0'); - c = *fmt0++; - } - if (c == '.') - { - c = *fmt0++; - zero_fill++; - while (is_digit(c)) - { - right_prec = (right_prec * 10) + (c - '0'); - c = *fmt0++; - } - } else - { - right_prec = left_prec; - } - sign = '\0'; - switch (c) - { - case 'd': - case 'x': - case 'X': - val = va_arg(ap, long); - switch (c) - { - case 'd': - if (val < 0) - { - sign = '-'; - val = -val; - } - length = _cvt(val, buf, 10, "0123456789"); - break; - case 'x': - length = _cvt(val, buf, 16, "0123456789abcdef"); - break; - case 'X': - length = _cvt(val, buf, 16, "0123456789ABCDEF"); - break; - } - cp = buf; - break; - case 's': - cp = va_arg(ap, char *); - length = strlen(cp); - break; - case 'c': - c = va_arg(ap, long /*char*/); - (*putc)(c); - continue; - default: - (*putc)('?'); - } - pad = left_prec - length; - if (sign != '\0') - { - pad--; - } - if (zero_fill) - { - c = '0'; - if (sign != '\0') - { - (*putc)(sign); - sign = '\0'; - } - } else - { - c = ' '; - } - if (!pad_on_right) - { - while (pad-- > 0) - { - (*putc)(c); - } - } - if (sign != '\0') - { - (*putc)(sign); - } - while (length-- > 0) - { - (*putc)(c = *cp++); - if (c == '\n') - { - (*putc)('\r'); - } - } - if (pad_on_right) - { - while (pad-- > 0) - { - (*putc)(c); - } - } - } else - { - (*putc)(c); - if (c == '\n') - { - (*putc)('\r'); - } - } - } -} - -int -_cvt(unsigned long val, char *buf, long radix, char *digits) -{ - char temp[80]; - char *cp = temp; - int length = 0; - if (val == 0) - { /* Special case */ - *cp++ = '0'; - } else - while (val) - { - *cp++ = digits[val % radix]; - val /= radix; - } - while (cp != temp) - { - *buf++ = *--cp; - length++; - } - *buf = '\0'; - return (length); -} - -void -_dump_buf_with_offset(unsigned char *p, int s, unsigned char *base) -{ - int i, c; - if ((unsigned int)s > (unsigned int)p) - { - s = (unsigned int)s - (unsigned int)p; - } - while (s > 0) - { - if (base) - { - _printk("%06X: ", (int)p - (int)base); - } else - { - _printk("%06X: ", p); - } - for (i = 0; i < 16; i++) - { - if (i < s) - { - _printk("%02X", p[i] & 0xFF); - } else - { - _printk(" "); - } - if ((i % 2) == 1) _printk(" "); - if ((i % 8) == 7) _printk(" "); - } - _printk(" |"); - for (i = 0; i < 16; i++) - { - if (i < s) - { - c = p[i] & 0xFF; - if ((c < 0x20) || (c >= 0x7F)) c = '.'; - } else - { - c = ' '; - } - _printk("%c", c); - } - _printk("|\n"); - s -= 16; - p += 16; - } -} - -void -_dump_buf(unsigned char *p, int s) -{ - _printk("\n"); - _dump_buf_with_offset(p, s, 0); -} - -/* Very simple inb/outb routines. We declare ISA_io to be 0 above, and - * then modify it on platforms which need to. We do it like this - * because on some platforms we give inb/outb an exact location, and - * on others it's an offset from a given location. -- Tom - */ - -void ISA_init(unsigned long base) -{ - ISA_io = (unsigned char *)base; -} - -void -outb(int port, unsigned char val) -{ - /* Ensure I/O operations complete */ - __asm__ volatile("eieio"); - ISA_io[port] = val; -} - -unsigned char -inb(int port) -{ - /* Ensure I/O operations complete */ - __asm__ volatile("eieio"); - return (ISA_io[port]); -} - -/* - * Local variables: - * c-indent-level: 8 - * c-basic-offset: 8 - * tab-width: 8 - * End: - */ diff --git a/arch/ppc/boot/common/ns16550.c b/arch/ppc/boot/common/ns16550.c deleted file mode 100644 index fc5b72041948..000000000000 --- a/arch/ppc/boot/common/ns16550.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * COM1 NS16550 support - */ - -#include -#include -#include -#include - -#if defined(CONFIG_XILINX_VIRTEX) -#include -#endif -#include "nonstdio.h" -#include "serial.h" - -#define SERIAL_BAUD 9600 - -extern unsigned long ISA_io; - -static struct serial_state rs_table[RS_TABLE_SIZE] = { - SERIAL_PORT_DFNS /* Defined in */ -}; - -static int shift; - -unsigned long serial_init(int chan, void *ignored) -{ - unsigned long com_port, base_baud; - unsigned char lcr, dlm; - - /* We need to find out which type io we're expecting. If it's - * 'SERIAL_IO_PORT', we get an offset from the isa_io_base. - * If it's 'SERIAL_IO_MEM', we can the exact location. -- Tom */ - switch (rs_table[chan].io_type) { - case SERIAL_IO_PORT: - com_port = rs_table[chan].port; - break; - case SERIAL_IO_MEM: - com_port = (unsigned long)rs_table[chan].iomem_base; - break; - default: - /* We can't deal with it. */ - return -1; - } - - /* How far apart the registers are. */ - shift = rs_table[chan].iomem_reg_shift; - /* Base baud.. */ - base_baud = rs_table[chan].baud_base; - - /* save the LCR */ - lcr = inb(com_port + (UART_LCR << shift)); - /* Access baud rate */ - outb(com_port + (UART_LCR << shift), 0x80); - dlm = inb(com_port + (UART_DLM << shift)); - /* - * Test if serial port is unconfigured. - * We assume that no-one uses less than 110 baud or - * less than 7 bits per character these days. - * -- paulus. - */ - - if ((dlm <= 4) && (lcr & 2)) - /* port is configured, put the old LCR back */ - outb(com_port + (UART_LCR << shift), lcr); - else { - /* Input clock. */ - outb(com_port + (UART_DLL << shift), - (base_baud / SERIAL_BAUD) & 0xFF); - outb(com_port + (UART_DLM << shift), - (base_baud / SERIAL_BAUD) >> 8); - /* 8 data, 1 stop, no parity */ - outb(com_port + (UART_LCR << shift), 0x03); - /* RTS/DTR */ - outb(com_port + (UART_MCR << shift), 0x03); - } - /* Clear & enable FIFOs */ - outb(com_port + (UART_FCR << shift), 0x07); - - return (com_port); -} - -void -serial_putc(unsigned long com_port, unsigned char c) -{ - while ((inb(com_port + (UART_LSR << shift)) & UART_LSR_THRE) == 0) - ; - outb(com_port, c); -} - -unsigned char -serial_getc(unsigned long com_port) -{ - while ((inb(com_port + (UART_LSR << shift)) & UART_LSR_DR) == 0) - ; - return inb(com_port); -} - -int -serial_tstc(unsigned long com_port) -{ - return ((inb(com_port + (UART_LSR << shift)) & UART_LSR_DR) != 0); -} diff --git a/arch/ppc/boot/common/serial_stub.c b/arch/ppc/boot/common/serial_stub.c deleted file mode 100644 index 5cc9ae66a8ba..000000000000 --- a/arch/ppc/boot/common/serial_stub.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This is a few stub routines to make the boot code cleaner looking when - * there is no serial port support doesn't need to be closed, for example. - * - * Author: Tom Rini - * - * 2003 (c) MontaVista, Software, Inc. This file is licensed under the terms - * of the GNU General Public License version 2. This program is licensed "as - * is" without any warranty of any kind, whether express or implied. - */ - -unsigned long __attribute__ ((weak)) -serial_init(int chan, void *ignored) -{ - return 0; -} - -void __attribute__ ((weak)) -serial_close(unsigned long com_port) -{ -} diff --git a/arch/ppc/boot/common/string.S b/arch/ppc/boot/common/string.S deleted file mode 100644 index 8016e43c4771..000000000000 --- a/arch/ppc/boot/common/string.S +++ /dev/null @@ -1,150 +0,0 @@ -/* - * String handling functions for PowerPC. - * - * Copyright (C) 1996 Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#define r0 0 -#define r3 3 -#define r4 4 -#define r5 5 -#define r6 6 -#define r7 7 -#define r8 8 - - .globl strlen -strlen: - addi r4,r3,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - bne 1b - subf r3,r3,r4 - blr - - .globl memset -memset: - rlwimi r4,r4,8,16,23 - rlwimi r4,r4,16,0,15 - addi r6,r3,-4 - cmplwi 0,r5,4 - blt 7f - stwu r4,4(r6) - beqlr - andi. r0,r6,3 - add r5,r0,r5 - subf r6,r0,r6 - rlwinm r0,r5,32-2,2,31 - mtctr r0 - bdz 6f -1: stwu r4,4(r6) - bdnz 1b -6: andi. r5,r5,3 -7: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r6,3 -8: stbu r4,1(r6) - bdnz 8b - blr - - .globl memmove -memmove: - cmplw 0,r3,r4 - bgt backwards_memcpy - /* fall through */ - - .globl memcpy -memcpy: - rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ - addi r6,r3,-4 - addi r4,r4,-4 - beq 2f /* if less than 8 bytes to do */ - andi. r0,r6,3 /* get dest word aligned */ - mtctr r7 - bne 5f -1: lwz r7,4(r4) - lwzu r8,8(r4) - stw r7,4(r6) - stwu r8,8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,4(r4) - addi r5,r5,-4 - stwu r0,4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r4,r4,3 - addi r6,r6,3 -4: lbzu r0,1(r4) - stbu r0,1(r6) - bdnz 4b - blr -5: subfic r0,r0,4 - mtctr r0 -6: lbz r7,4(r4) - addi r4,r4,1 - stb r7,4(r6) - addi r6,r6,1 - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - - .globl backwards_memcpy -backwards_memcpy: - rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ - add r6,r3,r5 - add r4,r4,r5 - beq 2f - andi. r0,r6,3 - mtctr r7 - bne 5f -1: lwz r7,-4(r4) - lwzu r8,-8(r4) - stw r7,-4(r6) - stwu r8,-8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,-4(r4) - subi r5,r5,4 - stwu r0,-4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 -4: lbzu r0,-1(r4) - stbu r0,-1(r6) - bdnz 4b - blr -5: mtctr r0 -6: lbzu r7,-1(r4) - stbu r7,-1(r6) - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - - .globl memcmp -memcmp: - cmpwi 0,r5,0 - blelr - mtctr r5 - addi r6,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r6) - lbzu r0,1(r4) - subf. r3,r0,r3 - bdnzt 2,1b - blr diff --git a/arch/ppc/boot/common/util.S b/arch/ppc/boot/common/util.S deleted file mode 100644 index 0c5e43c4ae06..000000000000 --- a/arch/ppc/boot/common/util.S +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Useful bootup functions, which are more easily done in asm than C. - * - * NOTE: Be very very careful about the registers you use here. - * We don't follow any ABI calling convention among the - * assembler functions that call each other, especially early - * in the initialization. Please preserve at least r3 and r4 - * for these early functions, as they often contain information - * passed from boot roms into the C decompress function. - * - * Author: Tom Rini - * trini@mvista.com - * Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others). - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include - - - .text - -#ifdef CONFIG_6xx - .globl disable_6xx_mmu -disable_6xx_mmu: - /* Establish default MSR value, exception prefix 0xFFF. - * If necessary, this function must fix up the LR if we - * return to a different address space once the MMU is - * disabled. - */ - li r8,MSR_IP|MSR_FP - mtmsr r8 - isync - - /* Test for a 601 */ - mfpvr r10 - srwi r10,r10,16 - cmpwi 0,r10,1 /* 601 ? */ - beq .clearbats_601 - - /* Clear BATs */ - li r8,0 - mtspr SPRN_DBAT0U,r8 - mtspr SPRN_DBAT0L,r8 - mtspr SPRN_DBAT1U,r8 - mtspr SPRN_DBAT1L,r8 - mtspr SPRN_DBAT2U,r8 - mtspr SPRN_DBAT2L,r8 - mtspr SPRN_DBAT3U,r8 - mtspr SPRN_DBAT3L,r8 -.clearbats_601: - mtspr SPRN_IBAT0U,r8 - mtspr SPRN_IBAT0L,r8 - mtspr SPRN_IBAT1U,r8 - mtspr SPRN_IBAT1L,r8 - mtspr SPRN_IBAT2U,r8 - mtspr SPRN_IBAT2L,r8 - mtspr SPRN_IBAT3U,r8 - mtspr SPRN_IBAT3L,r8 - isync - sync - sync - - /* Set segment registers */ - li r8,16 /* load up segment register values */ - mtctr r8 /* for context 0 */ - lis r8,0x2000 /* Ku = 1, VSID = 0 */ - li r10,0 -3: mtsrin r8,r10 - addi r8,r8,0x111 /* increment VSID */ - addis r10,r10,0x1000 /* address of next segment */ - bdnz 3b - blr - - .globl disable_6xx_l1cache -disable_6xx_l1cache: - /* Enable, invalidate and then disable the L1 icache/dcache. */ - li r8,0 - ori r8,r8,(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) - mfspr r11,SPRN_HID0 - or r11,r11,r8 - andc r10,r11,r8 - isync - mtspr SPRN_HID0,r8 - sync - isync - mtspr SPRN_HID0,r10 - sync - isync - blr -#endif - - .globl _setup_L2CR -_setup_L2CR: -/* - * We should be skipping this section on CPUs where this results in an - * illegal instruction. If not, please send trini@kernel.crashing.org - * the PVR of your CPU. - */ - /* Invalidate/disable L2 cache */ - sync - isync - mfspr r8,SPRN_L2CR - rlwinm r8,r8,0,1,31 - oris r8,r8,L2CR_L2I@h - sync - isync - mtspr SPRN_L2CR,r8 - sync - isync - - /* Wait for the invalidation to complete */ - mfspr r8,SPRN_PVR - srwi r8,r8,16 - cmplwi cr0,r8,0x8000 /* 7450 */ - cmplwi cr1,r8,0x8001 /* 7455 */ - cmplwi cr2,r8,0x8002 /* 7457 */ - cror 4*cr0+eq,4*cr0+eq,4*cr1+eq /* Now test if any are true. */ - cror 4*cr0+eq,4*cr0+eq,4*cr2+eq - bne 2f - -1: mfspr r8,SPRN_L2CR /* On 745x, poll L2I bit (bit 10) */ - rlwinm. r9,r8,0,10,10 - bne 1b - b 3f - -2: mfspr r8,SPRN_L2CR /* On 75x & 74[01]0, poll L2IP bit (bit 31) */ - rlwinm. r9,r8,0,31,31 - bne 2b - -3: rlwinm r8,r8,0,11,9 /* Turn off L2I bit */ - sync - isync - mtspr SPRN_L2CR,r8 - sync - isync - blr - - .globl _setup_L3CR -_setup_L3CR: - /* Invalidate/disable L3 cache */ - sync - isync - mfspr r8,SPRN_L3CR - rlwinm r8,r8,0,1,31 - ori r8,r8,L3CR_L3I@l - sync - isync - mtspr SPRN_L3CR,r8 - sync - isync - - /* Wait for the invalidation to complete */ -1: mfspr r8,SPRN_L3CR - rlwinm. r9,r8,0,21,21 - bne 1b - - rlwinm r8,r8,0,22,20 /* Turn off L3I bit */ - sync - isync - mtspr SPRN_L3CR,r8 - sync - isync - blr - - -/* udelay (on non-601 processors) needs to know the period of the - * timebase in nanoseconds. This used to be hardcoded to be 60ns - * (period of 66MHz/4). Now a variable is used that is initialized to - * 60 for backward compatibility, but it can be overridden as necessary - * with code something like this: - * extern unsigned long timebase_period_ns; - * timebase_period_ns = 1000000000 / bd->bi_tbfreq; - */ - .data - .globl timebase_period_ns -timebase_period_ns: - .long 60 - - .text -/* - * Delay for a number of microseconds - */ - .globl udelay -udelay: - mfspr r4,SPRN_PVR - srwi r4,r4,16 - cmpwi 0,r4,1 /* 601 ? */ - bne .udelay_not_601 -00: li r0,86 /* Instructions / microsecond? */ - mtctr r0 -10: addi r0,r0,0 /* NOP */ - bdnz 10b - subic. r3,r3,1 - bne 00b - blr - -.udelay_not_601: - mulli r4,r3,1000 /* nanoseconds */ - /* Change r4 to be the number of ticks using: - * (nanoseconds + (timebase_period_ns - 1 )) / timebase_period_ns - * timebase_period_ns defaults to 60 (16.6MHz) */ - lis r5,timebase_period_ns@ha - lwz r5,timebase_period_ns@l(r5) - add r4,r4,r5 - addi r4,r4,-1 - divw r4,r4,r5 /* BUS ticks */ -1: mftbu r5 - mftb r6 - mftbu r7 - cmpw 0,r5,r7 - bne 1b /* Get [synced] base time */ - addc r9,r6,r4 /* Compute end time */ - addze r8,r5 -2: mftbu r5 - cmpw 0,r5,r8 - blt 2b - bgt 3f - mftb r6 - cmpw 0,r6,r9 - blt 2b -3: blr - - .section ".relocate_code","xa" -/* - * Flush and enable instruction cache - * First, flush the data cache in case it was enabled and may be - * holding instructions for copy back. - */ - .globl flush_instruction_cache -flush_instruction_cache: - mflr r6 - bl flush_data_cache - -#ifdef CONFIG_8xx - lis r3, IDC_INVALL@h - mtspr SPRN_IC_CST, r3 - lis r3, IDC_ENABLE@h - mtspr SPRN_IC_CST, r3 - lis r3, IDC_DISABLE@h - mtspr SPRN_DC_CST, r3 -#elif CONFIG_4xx - lis r3,start@h # r9 = &_start - lis r4,_etext@ha - addi r4,r4,_etext@l # r8 = &_etext -1: dcbf r0,r3 # Flush the data cache - icbi r0,r3 # Invalidate the instruction cache - addi r3,r3,0x10 # Increment by one cache line - cmplw cr0,r3,r4 # Are we at the end yet? - blt 1b # No, keep flushing and invalidating -#else - /* Enable, invalidate and then disable the L1 icache/dcache. */ - li r3,0 - ori r3,r3,(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) - mfspr r4,SPRN_HID0 - or r5,r4,r3 - isync - mtspr SPRN_HID0,r5 - sync - isync - ori r5,r4,HID0_ICE /* Enable cache */ - mtspr SPRN_HID0,r5 - sync - isync -#endif - mtlr r6 - blr - -#define NUM_CACHE_LINES 128*8 -#define cache_flush_buffer 0x1000 - -/* - * Flush data cache - * Do this by just reading lots of stuff into the cache. - */ - .globl flush_data_cache -flush_data_cache: - lis r3,cache_flush_buffer@h - ori r3,r3,cache_flush_buffer@l - li r4,NUM_CACHE_LINES - mtctr r4 -00: lwz r4,0(r3) - addi r3,r3,L1_CACHE_BYTES /* Next line, please */ - bdnz 00b -10: blr - - .previous - diff --git a/arch/ppc/boot/images/.gitignore b/arch/ppc/boot/images/.gitignore deleted file mode 100644 index 21c2dc5b6b78..000000000000 --- a/arch/ppc/boot/images/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -sImage -vmapus -vmlinux* -miboot* -zImage* -uImage diff --git a/arch/ppc/boot/images/Makefile b/arch/ppc/boot/images/Makefile deleted file mode 100644 index 58415d5718e3..000000000000 --- a/arch/ppc/boot/images/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -# -# This dir holds all of the images for PPC machines. -# Tom Rini January 2001 - -MKIMAGE := $(srctree)/scripts/mkuboot.sh - -extra-y := vmlinux.bin vmlinux.gz - -# two make processes may write to vmlinux.gz at the same time with make -j -quiet_cmd_mygzip = GZIP $@ -cmd_mygzip = gzip -f -9 < $< > $@.$$$$ && mv $@.$$$$ $@ - - -OBJCOPYFLAGS_vmlinux.bin := -O binary -$(obj)/vmlinux.bin: vmlinux FORCE - $(call if_changed,objcopy) - -$(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE - $(call if_changed,mygzip) - -quiet_cmd_uimage = UIMAGE $@ - cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A ppc -O linux -T kernel \ - -C gzip -a 00000000 -e 00000000 -n 'Linux-$(KERNELRELEASE)' \ - -d $< $@ - -targets += uImage -$(obj)/uImage: $(obj)/vmlinux.gz - $(Q)rm -f $@ - $(call cmd,uimage) - @echo -n ' Image: $@ ' - @if [ -f $@ ]; then echo 'is ready' ; else echo 'not made'; fi - -# Files generated that shall be removed upon make clean -clean-files := sImage vmapus vmlinux* miboot* zImage* uImage diff --git a/arch/ppc/boot/include/cpc700.h b/arch/ppc/boot/include/cpc700.h deleted file mode 100644 index 28cfcde44909..000000000000 --- a/arch/ppc/boot/include/cpc700.h +++ /dev/null @@ -1,26 +0,0 @@ - -#ifndef __PPC_BOOT_CPC700_H -#define __PPC_BOOT_CPC700_H - -#define CPC700_MEM_CFGADDR 0xff500008 -#define CPC700_MEM_CFGDATA 0xff50000c - -#define CPC700_MB0SA 0x38 -#define CPC700_MB0EA 0x58 -#define CPC700_MB1SA 0x3c -#define CPC700_MB1EA 0x5c -#define CPC700_MB2SA 0x40 -#define CPC700_MB2EA 0x60 -#define CPC700_MB3SA 0x44 -#define CPC700_MB3EA 0x64 -#define CPC700_MB4SA 0x48 -#define CPC700_MB4EA 0x68 - -static inline long -cpc700_read_memreg(int reg) -{ - out_be32((volatile unsigned int *) CPC700_MEM_CFGADDR, reg); - return in_be32((volatile unsigned int *) CPC700_MEM_CFGDATA); -} - -#endif diff --git a/arch/ppc/boot/include/iso_font.h b/arch/ppc/boot/include/iso_font.h deleted file mode 100644 index bff050e002b7..000000000000 --- a/arch/ppc/boot/include/iso_font.h +++ /dev/null @@ -1,257 +0,0 @@ -static const unsigned char font[] = { -/* 0x00 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x01 */ 0x00,0x00,0x7E,0x81,0xA5,0x81,0x81,0xBD,0x99,0x81,0x81,0x7E,0x00,0x00,0x00,0x00, -/* 0x02 */ 0x00,0x00,0x7E,0xFF,0xDB,0xFF,0xFF,0xC3,0xC3,0xE7,0xFF,0x7E,0x00,0x00,0x00,0x00, -/* 0x03 */ 0x00,0x00,0x00,0x00,0x6C,0xFE,0xFE,0xFE,0xFE,0x7C,0x38,0x10,0x00,0x00,0x00,0x00, -/* 0x04 */ 0x00,0x00,0x00,0x00,0x10,0x38,0x7C,0xFE,0x7C,0x38,0x10,0x00,0x00,0x00,0x00,0x00, -/* 0x05 */ 0x00,0x00,0x00,0x18,0x3C,0x3C,0xE7,0xE7,0xE7,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x06 */ 0x00,0x00,0x00,0x18,0x3C,0x7E,0xFF,0xFF,0x7E,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x07 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x3C,0x3C,0x18,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x08 */ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE7,0xC3,0xC3,0xE7,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, -/* 0x09 */ 0x00,0x00,0x00,0x00,0x00,0x3C,0x66,0x42,0x42,0x66,0x3C,0x00,0x00,0x00,0x00,0x00, -/* 0x0A */ 0xFF,0xFF,0xFF,0xFF,0xFF,0xC3,0x99,0xBD,0xBD,0x99,0xC3,0xFF,0xFF,0xFF,0xFF,0xFF, -/* 0x0B */ 0x00,0x00,0x3E,0x0E,0x1A,0x32,0x78,0xCC,0xCC,0xCC,0xCC,0x78,0x00,0x00,0x00,0x00, -/* 0x0C */ 0x00,0x00,0x3C,0x66,0x66,0x66,0x66,0x3C,0x18,0x7E,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0x0D */ 0x00,0x00,0x30,0x38,0x3C,0x36,0x33,0x30,0x30,0x70,0xF0,0xE0,0x00,0x00,0x00,0x00, -/* 0x0E */ 0x00,0x00,0x7F,0x63,0x7F,0x63,0x63,0x63,0x63,0x67,0xE7,0xE6,0xC0,0x00,0x00,0x00, -/* 0x0F */ 0x00,0x00,0x00,0x18,0x18,0xDB,0x3C,0xE7,0x3C,0xDB,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0x10 */ 0x00,0x80,0xC0,0xE0,0xF0,0xF8,0xFE,0xF8,0xF0,0xE0,0xC0,0x80,0x00,0x00,0x00,0x00, -/* 0x11 */ 0x00,0x02,0x06,0x0E,0x1E,0x3E,0xFE,0x3E,0x1E,0x0E,0x06,0x02,0x00,0x00,0x00,0x00, -/* 0x12 */ 0x00,0x00,0x18,0x3C,0x7E,0x18,0x18,0x18,0x7E,0x3C,0x18,0x00,0x00,0x00,0x00,0x00, -/* 0x13 */ 0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x66,0x66,0x00,0x66,0x66,0x00,0x00,0x00,0x00, -/* 0x14 */ 0x00,0x00,0x7F,0xDB,0xDB,0xDB,0x7B,0x1B,0x1B,0x1B,0x1B,0x1B,0x00,0x00,0x00,0x00, -/* 0x15 */ 0x00,0x7C,0xC6,0x60,0x38,0x6C,0xC6,0xC6,0x6C,0x38,0x0C,0xC6,0x7C,0x00,0x00,0x00, -/* 0x16 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0xFE,0xFE,0xFE,0x00,0x00,0x00,0x00, -/* 0x17 */ 0x00,0x00,0x18,0x3C,0x7E,0x18,0x18,0x18,0x7E,0x3C,0x18,0x7E,0x00,0x00,0x00,0x00, -/* 0x18 */ 0x00,0x00,0x18,0x3C,0x7E,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0x19 */ 0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x7E,0x3C,0x18,0x00,0x00,0x00,0x00, -/* 0x1A */ 0x00,0x00,0x00,0x00,0x00,0x18,0x0C,0xFE,0x0C,0x18,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x1B */ 0x00,0x00,0x00,0x00,0x00,0x30,0x60,0xFE,0x60,0x30,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x1C */ 0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0xC0,0xC0,0xFE,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x1D */ 0x00,0x00,0x00,0x00,0x00,0x28,0x6C,0xFE,0x6C,0x28,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x1E */ 0x00,0x00,0x00,0x00,0x10,0x38,0x38,0x7C,0x7C,0xFE,0xFE,0x00,0x00,0x00,0x00,0x00, -/* 0x1F */ 0x00,0x00,0x00,0x00,0xFE,0xFE,0x7C,0x7C,0x38,0x38,0x10,0x00,0x00,0x00,0x00,0x00, -/* 0x20 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x21 */ 0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0x22 */ 0x00,0x66,0x66,0x66,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x23 */ 0x00,0x00,0x00,0x6C,0x6C,0xFE,0x6C,0x6C,0x6C,0xFE,0x6C,0x6C,0x00,0x00,0x00,0x00, -/* 0x24 */ 0x18,0x18,0x7C,0xC6,0xC2,0xC0,0x7C,0x06,0x06,0x86,0xC6,0x7C,0x18,0x18,0x00,0x00, -/* 0x25 */ 0x00,0x00,0x00,0x00,0xC2,0xC6,0x0C,0x18,0x30,0x60,0xC6,0x86,0x00,0x00,0x00,0x00, -/* 0x26 */ 0x00,0x00,0x38,0x6C,0x6C,0x38,0x76,0xDC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x27 */ 0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x28 */ 0x00,0x00,0x0C,0x18,0x30,0x30,0x30,0x30,0x30,0x30,0x18,0x0C,0x00,0x00,0x00,0x00, -/* 0x29 */ 0x00,0x00,0x30,0x18,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x18,0x30,0x00,0x00,0x00,0x00, -/* 0x2A */ 0x00,0x00,0x00,0x00,0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x2B */ 0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x7E,0x18,0x18,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x2C */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00,0x00, -/* 0x2D */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x2E */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0x2F */ 0x00,0x00,0x00,0x00,0x02,0x06,0x0C,0x18,0x30,0x60,0xC0,0x80,0x00,0x00,0x00,0x00, -/* 0x30 */ 0x00,0x00,0x38,0x6C,0xC6,0xC6,0xD6,0xD6,0xC6,0xC6,0x6C,0x38,0x00,0x00,0x00,0x00, -/* 0x31 */ 0x00,0x00,0x18,0x38,0x78,0x18,0x18,0x18,0x18,0x18,0x18,0x7E,0x00,0x00,0x00,0x00, -/* 0x32 */ 0x00,0x00,0x7C,0xC6,0x06,0x0C,0x18,0x30,0x60,0xC0,0xC6,0xFE,0x00,0x00,0x00,0x00, -/* 0x33 */ 0x00,0x00,0x7C,0xC6,0x06,0x06,0x3C,0x06,0x06,0x06,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x34 */ 0x00,0x00,0x0C,0x1C,0x3C,0x6C,0xCC,0xFE,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00, -/* 0x35 */ 0x00,0x00,0xFE,0xC0,0xC0,0xC0,0xFC,0x06,0x06,0x06,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x36 */ 0x00,0x00,0x38,0x60,0xC0,0xC0,0xFC,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x37 */ 0x00,0x00,0xFE,0xC6,0x06,0x06,0x0C,0x18,0x30,0x30,0x30,0x30,0x00,0x00,0x00,0x00, -/* 0x38 */ 0x00,0x00,0x7C,0xC6,0xC6,0xC6,0x7C,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x39 */ 0x00,0x00,0x7C,0xC6,0xC6,0xC6,0x7E,0x06,0x06,0x06,0x0C,0x78,0x00,0x00,0x00,0x00, -/* 0x3A */ 0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x00, -/* 0x3B */ 0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x30,0x00,0x00,0x00,0x00, -/* 0x3C */ 0x00,0x00,0x00,0x06,0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x06,0x00,0x00,0x00,0x00, -/* 0x3D */ 0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x3E */ 0x00,0x00,0x00,0x60,0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x60,0x00,0x00,0x00,0x00, -/* 0x3F */ 0x00,0x00,0x7C,0xC6,0xC6,0x0C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0x40 */ 0x00,0x00,0x00,0x7C,0xC6,0xC6,0xDE,0xDE,0xDE,0xDC,0xC0,0x7C,0x00,0x00,0x00,0x00, -/* 0x41 */ 0x00,0x00,0x10,0x38,0x6C,0xC6,0xC6,0xFE,0xC6,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0x42 */ 0x00,0x00,0xFC,0x66,0x66,0x66,0x7C,0x66,0x66,0x66,0x66,0xFC,0x00,0x00,0x00,0x00, -/* 0x43 */ 0x00,0x00,0x3C,0x66,0xC2,0xC0,0xC0,0xC0,0xC0,0xC2,0x66,0x3C,0x00,0x00,0x00,0x00, -/* 0x44 */ 0x00,0x00,0xF8,0x6C,0x66,0x66,0x66,0x66,0x66,0x66,0x6C,0xF8,0x00,0x00,0x00,0x00, -/* 0x45 */ 0x00,0x00,0xFE,0x66,0x62,0x68,0x78,0x68,0x60,0x62,0x66,0xFE,0x00,0x00,0x00,0x00, -/* 0x46 */ 0x00,0x00,0xFE,0x66,0x62,0x68,0x78,0x68,0x60,0x60,0x60,0xF0,0x00,0x00,0x00,0x00, -/* 0x47 */ 0x00,0x00,0x3C,0x66,0xC2,0xC0,0xC0,0xDE,0xC6,0xC6,0x66,0x3A,0x00,0x00,0x00,0x00, -/* 0x48 */ 0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xFE,0xC6,0xC6,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0x49 */ 0x00,0x00,0x3C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x4A */ 0x00,0x00,0x1E,0x0C,0x0C,0x0C,0x0C,0x0C,0xCC,0xCC,0xCC,0x78,0x00,0x00,0x00,0x00, -/* 0x4B */ 0x00,0x00,0xE6,0x66,0x66,0x6C,0x78,0x78,0x6C,0x66,0x66,0xE6,0x00,0x00,0x00,0x00, -/* 0x4C */ 0x00,0x00,0xF0,0x60,0x60,0x60,0x60,0x60,0x60,0x62,0x66,0xFE,0x00,0x00,0x00,0x00, -/* 0x4D */ 0x00,0x00,0xC6,0xEE,0xFE,0xFE,0xD6,0xC6,0xC6,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0x4E */ 0x00,0x00,0xC6,0xE6,0xF6,0xFE,0xDE,0xCE,0xC6,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0x4F */ 0x00,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x50 */ 0x00,0x00,0xFC,0x66,0x66,0x66,0x7C,0x60,0x60,0x60,0x60,0xF0,0x00,0x00,0x00,0x00, -/* 0x51 */ 0x00,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xD6,0xDE,0x7C,0x0C,0x0E,0x00,0x00, -/* 0x52 */ 0x00,0x00,0xFC,0x66,0x66,0x66,0x7C,0x6C,0x66,0x66,0x66,0xE6,0x00,0x00,0x00,0x00, -/* 0x53 */ 0x00,0x00,0x7C,0xC6,0xC6,0x60,0x38,0x0C,0x06,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x54 */ 0x00,0x00,0x7E,0x7E,0x5A,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x55 */ 0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x56 */ 0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x6C,0x38,0x10,0x00,0x00,0x00,0x00, -/* 0x57 */ 0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xD6,0xD6,0xD6,0xFE,0xEE,0x6C,0x00,0x00,0x00,0x00, -/* 0x58 */ 0x00,0x00,0xC6,0xC6,0x6C,0x7C,0x38,0x38,0x7C,0x6C,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0x59 */ 0x00,0x00,0x66,0x66,0x66,0x66,0x3C,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x5A */ 0x00,0x00,0xFE,0xC6,0x86,0x0C,0x18,0x30,0x60,0xC2,0xC6,0xFE,0x00,0x00,0x00,0x00, -/* 0x5B */ 0x00,0x00,0x3C,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x3C,0x00,0x00,0x00,0x00, -/* 0x5C */ 0x00,0x00,0x00,0x80,0xC0,0xE0,0x70,0x38,0x1C,0x0E,0x06,0x02,0x00,0x00,0x00,0x00, -/* 0x5D */ 0x00,0x00,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00,0x00,0x00,0x00, -/* 0x5E */ 0x10,0x38,0x6C,0xC6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x5F */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00, -/* 0x60 */ 0x30,0x30,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x61 */ 0x00,0x00,0x00,0x00,0x00,0x78,0x0C,0x7C,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x62 */ 0x00,0x00,0xE0,0x60,0x60,0x78,0x6C,0x66,0x66,0x66,0x66,0x7C,0x00,0x00,0x00,0x00, -/* 0x63 */ 0x00,0x00,0x00,0x00,0x00,0x7C,0xC6,0xC0,0xC0,0xC0,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x64 */ 0x00,0x00,0x1C,0x0C,0x0C,0x3C,0x6C,0xCC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x65 */ 0x00,0x00,0x00,0x00,0x00,0x7C,0xC6,0xFE,0xC0,0xC0,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x66 */ 0x00,0x00,0x38,0x6C,0x64,0x60,0xF0,0x60,0x60,0x60,0x60,0xF0,0x00,0x00,0x00,0x00, -/* 0x67 */ 0x00,0x00,0x00,0x00,0x00,0x3E,0x66,0x66,0x66,0x66,0x66,0x3E,0x06,0x66,0x3C,0x00, -/* 0x68 */ 0x00,0x00,0xE0,0x60,0x60,0x6C,0x76,0x66,0x66,0x66,0x66,0xE6,0x00,0x00,0x00,0x00, -/* 0x69 */ 0x00,0x00,0x18,0x18,0x00,0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x6A */ 0x00,0x00,0x06,0x06,0x00,0x0E,0x06,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00, -/* 0x6B */ 0x00,0x00,0xE0,0x60,0x60,0x66,0x6C,0x78,0x78,0x6C,0x66,0xE6,0x00,0x00,0x00,0x00, -/* 0x6C */ 0x00,0x00,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x6D */ 0x00,0x00,0x00,0x00,0x00,0x6C,0xFE,0xD6,0xD6,0xD6,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0x6E */ 0x00,0x00,0x00,0x00,0x00,0xDC,0x66,0x66,0x66,0x66,0x66,0x66,0x00,0x00,0x00,0x00, -/* 0x6F */ 0x00,0x00,0x00,0x00,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x70 */ 0x00,0x00,0x00,0x00,0x00,0xFC,0x66,0x66,0x66,0x66,0x66,0x7C,0x60,0x60,0xF0,0x00, -/* 0x71 */ 0x00,0x00,0x00,0x00,0x00,0x7E,0xCC,0xCC,0xCC,0xCC,0xCC,0x7C,0x0C,0x0C,0x1E,0x00, -/* 0x72 */ 0x00,0x00,0x00,0x00,0x00,0xDC,0x76,0x66,0x60,0x60,0x60,0xF0,0x00,0x00,0x00,0x00, -/* 0x73 */ 0x00,0x00,0x00,0x00,0x00,0x7C,0xC6,0x60,0x38,0x0C,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x74 */ 0x00,0x00,0x10,0x30,0x30,0xFC,0x30,0x30,0x30,0x30,0x36,0x1C,0x00,0x00,0x00,0x00, -/* 0x75 */ 0x00,0x00,0x00,0x00,0x00,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x76 */ 0x00,0x00,0x00,0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00,0x00,0x00,0x00, -/* 0x77 */ 0x00,0x00,0x00,0x00,0x00,0xC6,0xC6,0xD6,0xD6,0xD6,0xFE,0x6C,0x00,0x00,0x00,0x00, -/* 0x78 */ 0x00,0x00,0x00,0x00,0x00,0xC6,0x6C,0x38,0x38,0x38,0x6C,0xC6,0x00,0x00,0x00,0x00, -/* 0x79 */ 0x00,0x00,0x00,0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x7E,0x06,0x0C,0xF8,0x00, -/* 0x7A */ 0x00,0x00,0x00,0x00,0x00,0xFE,0xCC,0x18,0x30,0x60,0xC6,0xFE,0x00,0x00,0x00,0x00, -/* 0x7B */ 0x00,0x00,0x0E,0x18,0x18,0x18,0x70,0x18,0x18,0x18,0x18,0x0E,0x00,0x00,0x00,0x00, -/* 0x7C */ 0x00,0x00,0x18,0x18,0x18,0x18,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0x7D */ 0x00,0x00,0x70,0x18,0x18,0x18,0x0E,0x18,0x18,0x18,0x18,0x70,0x00,0x00,0x00,0x00, -/* 0x7E */ 0x00,0x00,0x76,0xDC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0x7F */ 0x00,0x00,0x00,0x00,0x10,0x38,0x6C,0xC6,0xC6,0xC6,0xFE,0x00,0x00,0x00,0x00,0x00, -/* 0x80 */ 0x00,0x00,0x3C,0x66,0xC2,0xC0,0xC0,0xC0,0xC2,0x66,0x3C,0x0C,0x06,0x7C,0x00,0x00, -/* 0x81 */ 0x00,0x00,0xCC,0x00,0x00,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x82 */ 0x00,0x0C,0x18,0x30,0x00,0x7C,0xC6,0xC6,0xFE,0xC0,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x83 */ 0x00,0x10,0x38,0x6C,0x00,0x78,0x0C,0x7C,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x84 */ 0x00,0x00,0xCC,0x00,0x00,0x78,0x0C,0x7C,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x85 */ 0x00,0x60,0x30,0x18,0x00,0x78,0x0C,0x7C,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x86 */ 0x00,0x38,0x6C,0x38,0x00,0x78,0x0C,0x7C,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x87 */ 0x00,0x00,0x00,0x00,0x3C,0x66,0x60,0x60,0x66,0x3C,0x0C,0x06,0x3C,0x00,0x00,0x00, -/* 0x88 */ 0x00,0x10,0x38,0x6C,0x00,0x7C,0xC6,0xC6,0xFE,0xC0,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x89 */ 0x00,0x00,0xC6,0x00,0x00,0x7C,0xC6,0xC6,0xFE,0xC0,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x8A */ 0x00,0x60,0x30,0x18,0x00,0x7C,0xC6,0xC6,0xFE,0xC0,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x8B */ 0x00,0x00,0x66,0x00,0x00,0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x8C */ 0x00,0x18,0x3C,0x66,0x00,0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x8D */ 0x00,0x60,0x30,0x18,0x00,0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0x8E */ 0x00,0xC6,0x00,0x10,0x38,0x6C,0xC6,0xC6,0xFE,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0x8F */ 0x38,0x6C,0x38,0x00,0x38,0x6C,0xC6,0xC6,0xFE,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0x90 */ 0x18,0x30,0x60,0x00,0xFE,0x66,0x60,0x7C,0x60,0x60,0x66,0xFE,0x00,0x00,0x00,0x00, -/* 0x91 */ 0x00,0x00,0x00,0x00,0x00,0xCC,0x76,0x36,0x7E,0xD8,0xD8,0x6E,0x00,0x00,0x00,0x00, -/* 0x92 */ 0x00,0x00,0x3E,0x6C,0xCC,0xCC,0xFE,0xCC,0xCC,0xCC,0xCC,0xCE,0x00,0x00,0x00,0x00, -/* 0x93 */ 0x00,0x10,0x38,0x6C,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x94 */ 0x00,0x00,0xC6,0x00,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x95 */ 0x00,0x60,0x30,0x18,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x96 */ 0x00,0x30,0x78,0xCC,0x00,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x97 */ 0x00,0x60,0x30,0x18,0x00,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0x98 */ 0x00,0x00,0xC6,0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x7E,0x06,0x0C,0x78,0x00, -/* 0x99 */ 0x00,0xC6,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x9A */ 0x00,0xC6,0x00,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0x9B */ 0x00,0x18,0x18,0x3C,0x66,0x60,0x60,0x60,0x66,0x3C,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0x9C */ 0x00,0x38,0x6C,0x64,0x60,0xF8,0x60,0x60,0x60,0x60,0xE6,0xFC,0x00,0x00,0x00,0x00, -/* 0x9D */ 0x00,0x00,0x66,0x66,0x3C,0x18,0x7E,0x18,0x7E,0x18,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0x9E */ 0x00,0xF8,0xCC,0xCC,0xF8,0xC4,0xCC,0xDE,0xCC,0xCC,0xCC,0xC6,0x00,0x00,0x00,0x00, -/* 0x9F */ 0x00,0x0E,0x1B,0x18,0x18,0x18,0x7E,0x18,0x18,0x18,0x18,0x18,0xD8,0x70,0x00,0x00, -/* 0xA0 */ 0x00,0x18,0x30,0x60,0x00,0x78,0x0C,0x7C,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0xA1 */ 0x00,0x0C,0x18,0x30,0x00,0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00, -/* 0xA2 */ 0x00,0x18,0x30,0x60,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0xA3 */ 0x00,0x18,0x30,0x60,0x00,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00, -/* 0xA4 */ 0x00,0x00,0x76,0xDC,0x00,0xDC,0x66,0x66,0x66,0x66,0x66,0x66,0x00,0x00,0x00,0x00, -/* 0xA5 */ 0x76,0xDC,0x00,0xC6,0xE6,0xF6,0xFE,0xDE,0xCE,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0xA6 */ 0x00,0x3C,0x6C,0x6C,0x3E,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xA7 */ 0x00,0x38,0x6C,0x6C,0x38,0x00,0x7C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xA8 */ 0x00,0x00,0x30,0x30,0x00,0x30,0x30,0x60,0xC0,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00, -/* 0xA9 */ 0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00, -/* 0xAA */ 0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x06,0x06,0x06,0x06,0x00,0x00,0x00,0x00,0x00, -/* 0xAB */ 0x00,0xC0,0xC0,0xC2,0xC6,0xCC,0x18,0x30,0x60,0xDC,0x86,0x0C,0x18,0x3E,0x00,0x00, -/* 0xAC */ 0x00,0xC0,0xC0,0xC2,0xC6,0xCC,0x18,0x30,0x66,0xCE,0x9E,0x3E,0x06,0x06,0x00,0x00, -/* 0xAD */ 0x00,0x00,0x18,0x18,0x00,0x18,0x18,0x18,0x3C,0x3C,0x3C,0x18,0x00,0x00,0x00,0x00, -/* 0xAE */ 0x00,0x00,0x00,0x00,0x00,0x36,0x6C,0xD8,0x6C,0x36,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xAF */ 0x00,0x00,0x00,0x00,0x00,0xD8,0x6C,0x36,0x6C,0xD8,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xB0 */ 0x11,0x44,0x11,0x44,0x11,0x44,0x11,0x44,0x11,0x44,0x11,0x44,0x11,0x44,0x11,0x44, -/* 0xB1 */ 0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA, -/* 0xB2 */ 0xDD,0x77,0xDD,0x77,0xDD,0x77,0xDD,0x77,0xDD,0x77,0xDD,0x77,0xDD,0x77,0xDD,0x77, -/* 0xB3 */ 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xB4 */ 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0xF8,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xB5 */ 0x18,0x18,0x18,0x18,0x18,0xF8,0x18,0xF8,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xB6 */ 0x36,0x36,0x36,0x36,0x36,0x36,0x36,0xF6,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xB7 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xB8 */ 0x00,0x00,0x00,0x00,0x00,0xF8,0x18,0xF8,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xB9 */ 0x36,0x36,0x36,0x36,0x36,0xF6,0x06,0xF6,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xBA */ 0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xBB */ 0x00,0x00,0x00,0x00,0x00,0xFE,0x06,0xF6,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xBC */ 0x36,0x36,0x36,0x36,0x36,0xF6,0x06,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xBD */ 0x36,0x36,0x36,0x36,0x36,0x36,0x36,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xBE */ 0x18,0x18,0x18,0x18,0x18,0xF8,0x18,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xBF */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xC0 */ 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xC1 */ 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xC2 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xC3 */ 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1F,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xC4 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xC5 */ 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0xFF,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xC6 */ 0x18,0x18,0x18,0x18,0x18,0x1F,0x18,0x1F,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xC7 */ 0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x37,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xC8 */ 0x36,0x36,0x36,0x36,0x36,0x37,0x30,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xC9 */ 0x00,0x00,0x00,0x00,0x00,0x3F,0x30,0x37,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xCA */ 0x36,0x36,0x36,0x36,0x36,0xF7,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xCB */ 0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0xF7,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xCC */ 0x36,0x36,0x36,0x36,0x36,0x37,0x30,0x37,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xCD */ 0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xCE */ 0x36,0x36,0x36,0x36,0x36,0xF7,0x00,0xF7,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xCF */ 0x18,0x18,0x18,0x18,0x18,0xFF,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xD0 */ 0x36,0x36,0x36,0x36,0x36,0x36,0x36,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xD1 */ 0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0xFF,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xD2 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xD3 */ 0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xD4 */ 0x18,0x18,0x18,0x18,0x18,0x1F,0x18,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xD5 */ 0x00,0x00,0x00,0x00,0x00,0x1F,0x18,0x1F,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xD6 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xD7 */ 0x36,0x36,0x36,0x36,0x36,0x36,0x36,0xFF,0x36,0x36,0x36,0x36,0x36,0x36,0x36,0x36, -/* 0xD8 */ 0x18,0x18,0x18,0x18,0x18,0xFF,0x18,0xFF,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xD9 */ 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xDA */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xDB */ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, -/* 0xDC */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, -/* 0xDD */ 0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0,0xF0, -/* 0xDE */ 0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F, -/* 0xDF */ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xE0 */ 0x00,0x00,0x00,0x00,0x00,0x76,0xDC,0xD8,0xD8,0xD8,0xDC,0x76,0x00,0x00,0x00,0x00, -/* 0xE1 */ 0x00,0x00,0x7C,0xC6,0xC6,0xC6,0xFC,0xC6,0xC6,0xC6,0xC6,0xDC,0xC0,0xC0,0x00,0x00, -/* 0xE2 */ 0x00,0x00,0xFE,0xC6,0xC6,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x00,0x00, -/* 0xE3 */ 0x00,0x00,0x00,0x00,0x00,0xFE,0x6C,0x6C,0x6C,0x6C,0x6C,0x6C,0x00,0x00,0x00,0x00, -/* 0xE4 */ 0x00,0x00,0xFE,0xC6,0x60,0x30,0x18,0x18,0x30,0x60,0xC6,0xFE,0x00,0x00,0x00,0x00, -/* 0xE5 */ 0x00,0x00,0x00,0x00,0x00,0x7E,0xD8,0xD8,0xD8,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00, -/* 0xE6 */ 0x00,0x00,0x00,0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x7C,0x60,0xC0,0x00,0x00,0x00, -/* 0xE7 */ 0x00,0x00,0x00,0x00,0x00,0x76,0xDC,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00,0x00, -/* 0xE8 */ 0x00,0x00,0x7E,0x18,0x3C,0x66,0x66,0x66,0x66,0x3C,0x18,0x7E,0x00,0x00,0x00,0x00, -/* 0xE9 */ 0x00,0x00,0x38,0x6C,0xC6,0xC6,0xFE,0xC6,0xC6,0xC6,0x6C,0x38,0x00,0x00,0x00,0x00, -/* 0xEA */ 0x00,0x00,0x38,0x6C,0xC6,0xC6,0xC6,0x6C,0x6C,0x6C,0x6C,0xEE,0x00,0x00,0x00,0x00, -/* 0xEB */ 0x00,0x00,0x1E,0x30,0x18,0x0C,0x3E,0x66,0x66,0x66,0x66,0x3C,0x00,0x00,0x00,0x00, -/* 0xEC */ 0x00,0x00,0x00,0x00,0x00,0x7E,0xDB,0xDB,0xDB,0x7E,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xED */ 0x00,0x00,0x00,0x03,0x06,0x7E,0xDB,0xDB,0xF3,0x7E,0x60,0xC0,0x00,0x00,0x00,0x00, -/* 0xEE */ 0x00,0x00,0x1C,0x30,0x60,0x60,0x7C,0x60,0x60,0x60,0x30,0x1C,0x00,0x00,0x00,0x00, -/* 0xEF */ 0x00,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00, -/* 0xF0 */ 0x00,0x00,0x00,0x00,0xFE,0x00,0x00,0xFE,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00, -/* 0xF1 */ 0x00,0x00,0x00,0x00,0x18,0x18,0x7E,0x18,0x18,0x00,0x00,0xFF,0x00,0x00,0x00,0x00, -/* 0xF2 */ 0x00,0x00,0x00,0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x00,0x7E,0x00,0x00,0x00,0x00, -/* 0xF3 */ 0x00,0x00,0x00,0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x00,0x7E,0x00,0x00,0x00,0x00, -/* 0xF4 */ 0x00,0x0E,0x1B,0x1B,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, -/* 0xF5 */ 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0xD8,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00, -/* 0xF6 */ 0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x7E,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x00, -/* 0xF7 */ 0x00,0x00,0x00,0x00,0x00,0x76,0xDC,0x00,0x76,0xDC,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xF8 */ 0x00,0x38,0x6C,0x6C,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xF9 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xFA */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xFB */ 0x00,0x0F,0x0C,0x0C,0x0C,0x0C,0x0C,0xEC,0x6C,0x6C,0x3C,0x1C,0x00,0x00,0x00,0x00, -/* 0xFC */ 0x00,0xD8,0x6C,0x6C,0x6C,0x6C,0x6C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xFD */ 0x00,0x70,0xD8,0x30,0x60,0xC8,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -/* 0xFE */ 0x00,0x00,0x00,0x00,0x7C,0x7C,0x7C,0x7C,0x7C,0x7C,0x7C,0x00,0x00,0x00,0x00,0x00, -}; diff --git a/arch/ppc/boot/include/mpc10x.h b/arch/ppc/boot/include/mpc10x.h deleted file mode 100644 index 6e5d540d8d3e..000000000000 --- a/arch/ppc/boot/include/mpc10x.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Common defines for the Motorola SPS MPC106/8240/107 Host bridge/Mem - * ctrl/EPIC/etc. - * - * Author: Tom Rini - * - * This is a heavily stripped down version of: - * include/asm-ppc/mpc10x.h - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __BOOT_MPC10X_H__ -#define __BOOT_MPC10X_H__ - -/* - * The values here don't completely map everything but should work in most - * cases. - * - * MAP A (PReP Map) - * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff - * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff - * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 - * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) - * - * MAP B (CHRP Map) - * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff - * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff - * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 - * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) - */ - -/* Define the type of map to use */ -#define MPC10X_MEM_MAP_A 1 -#define MPC10X_MEM_MAP_B 2 - -/* Map A (PReP Map) Defines */ -#define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 -#define MPC10X_MAPA_CNFG_DATA 0x80000cfc - -/* Map B (CHRP Map) Defines */ -#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 -#define MPC10X_MAPB_CNFG_DATA 0xfee00000 - -/* Define offsets for the memory controller registers in the config space */ -#define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ -#define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ -#define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ -#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ - -#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ -#define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ -#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ -#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ - -#define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 - -#endif /* __BOOT_MPC10X_H__ */ diff --git a/arch/ppc/boot/include/mpsc_defs.h b/arch/ppc/boot/include/mpsc_defs.h deleted file mode 100644 index 9f37e1355b17..000000000000 --- a/arch/ppc/boot/include/mpsc_defs.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * arch/ppc/boot/include/mpsc_defs.h - * - * Register definitions for the Marvell Multi-Protocol Serial Controller (MPSC), - * Serial DMA Controller (SDMA), and Baud Rate Generator (BRG). - * - * Author: Mark A. Greer - * - * 2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef _PPC_BOOT_MPSC_DEFS_H__ -#define _PPC_BOOT_MPSC_DEFS_H__ - -#define MPSC_NUM_CTLRS 2 - -/* - ***************************************************************************** - * - * Multi-Protocol Serial Controller Interface Registers - * - ***************************************************************************** - */ - -/* Main Configuratino Register Offsets */ -#define MPSC_MMCRL 0x0000 -#define MPSC_MMCRH 0x0004 -#define MPSC_MPCR 0x0008 -#define MPSC_CHR_1 0x000c -#define MPSC_CHR_2 0x0010 -#define MPSC_CHR_3 0x0014 -#define MPSC_CHR_4 0x0018 -#define MPSC_CHR_5 0x001c -#define MPSC_CHR_6 0x0020 -#define MPSC_CHR_7 0x0024 -#define MPSC_CHR_8 0x0028 -#define MPSC_CHR_9 0x002c -#define MPSC_CHR_10 0x0030 -#define MPSC_CHR_11 0x0034 - -#define MPSC_MPCR_CL_5 0 -#define MPSC_MPCR_CL_6 1 -#define MPSC_MPCR_CL_7 2 -#define MPSC_MPCR_CL_8 3 -#define MPSC_MPCR_SBL_1 0 -#define MPSC_MPCR_SBL_2 3 - -#define MPSC_CHR_2_TEV (1<<1) -#define MPSC_CHR_2_TA (1<<7) -#define MPSC_CHR_2_TTCS (1<<9) -#define MPSC_CHR_2_REV (1<<17) -#define MPSC_CHR_2_RA (1<<23) -#define MPSC_CHR_2_CRD (1<<25) -#define MPSC_CHR_2_EH (1<<31) -#define MPSC_CHR_2_PAR_ODD 0 -#define MPSC_CHR_2_PAR_SPACE 1 -#define MPSC_CHR_2_PAR_EVEN 2 -#define MPSC_CHR_2_PAR_MARK 3 - -/* MPSC Signal Routing */ -#define MPSC_MRR 0x0000 -#define MPSC_RCRR 0x0004 -#define MPSC_TCRR 0x0008 - -/* - ***************************************************************************** - * - * Serial DMA Controller Interface Registers - * - ***************************************************************************** - */ - -#define SDMA_SDC 0x0000 -#define SDMA_SDCM 0x0008 -#define SDMA_RX_DESC 0x0800 -#define SDMA_RX_BUF_PTR 0x0808 -#define SDMA_SCRDP 0x0810 -#define SDMA_TX_DESC 0x0c00 -#define SDMA_SCTDP 0x0c10 -#define SDMA_SFTDP 0x0c14 - -#define SDMA_DESC_CMDSTAT_PE (1<<0) -#define SDMA_DESC_CMDSTAT_CDL (1<<1) -#define SDMA_DESC_CMDSTAT_FR (1<<3) -#define SDMA_DESC_CMDSTAT_OR (1<<6) -#define SDMA_DESC_CMDSTAT_BR (1<<9) -#define SDMA_DESC_CMDSTAT_MI (1<<10) -#define SDMA_DESC_CMDSTAT_A (1<<11) -#define SDMA_DESC_CMDSTAT_AM (1<<12) -#define SDMA_DESC_CMDSTAT_CT (1<<13) -#define SDMA_DESC_CMDSTAT_C (1<<14) -#define SDMA_DESC_CMDSTAT_ES (1<<15) -#define SDMA_DESC_CMDSTAT_L (1<<16) -#define SDMA_DESC_CMDSTAT_F (1<<17) -#define SDMA_DESC_CMDSTAT_P (1<<18) -#define SDMA_DESC_CMDSTAT_EI (1<<23) -#define SDMA_DESC_CMDSTAT_O (1<<31) - -#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \ - SDMA_DESC_CMDSTAT_EI) - -#define SDMA_SDC_RFT (1<<0) -#define SDMA_SDC_SFM (1<<1) -#define SDMA_SDC_BLMR (1<<6) -#define SDMA_SDC_BLMT (1<<7) -#define SDMA_SDC_POVR (1<<8) -#define SDMA_SDC_RIFB (1<<9) - -#define SDMA_SDCM_ERD (1<<7) -#define SDMA_SDCM_AR (1<<15) -#define SDMA_SDCM_STD (1<<16) -#define SDMA_SDCM_TXD (1<<23) -#define SDMA_SDCM_AT (1<<31) - -#define SDMA_0_CAUSE_RXBUF (1<<0) -#define SDMA_0_CAUSE_RXERR (1<<1) -#define SDMA_0_CAUSE_TXBUF (1<<2) -#define SDMA_0_CAUSE_TXEND (1<<3) -#define SDMA_1_CAUSE_RXBUF (1<<8) -#define SDMA_1_CAUSE_RXERR (1<<9) -#define SDMA_1_CAUSE_TXBUF (1<<10) -#define SDMA_1_CAUSE_TXEND (1<<11) - -#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \ - SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR) -#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \ - SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND) - -/* SDMA Interrupt registers */ -#define SDMA_INTR_CAUSE 0x0000 -#define SDMA_INTR_MASK 0x0080 - -/* - ***************************************************************************** - * - * Baud Rate Generator Interface Registers - * - ***************************************************************************** - */ - -#define BRG_BCR 0x0000 -#define BRG_BTR 0x0004 - -#endif /*_PPC_BOOT_MPSC_DEFS_H__ */ diff --git a/arch/ppc/boot/include/nonstdio.h b/arch/ppc/boot/include/nonstdio.h deleted file mode 100644 index f2b5526faef3..000000000000 --- a/arch/ppc/boot/include/nonstdio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * This is sort of a catchall for I/O related functions. Stuff that - * wouldn't be in 'stdio.h' normally is here, and it's 'nonstdio.h' - * for a reason. -- Tom - */ -typedef int FILE; -extern FILE *stdin, *stdout; -#define NULL ((void *)0) -#define EOF (-1) -#define fopen(n, m) NULL -#define fflush(f) 0 -#define fclose(f) 0 -#define perror(s) printf("%s: no files!\n", (s)) - -extern int getc(void); -extern int printf(const char *format, ...); -extern int sprintf(char *str, const char *format, ...); -extern int tstc(void); -extern void exit(void); -extern void outb(int port, unsigned char val); -extern void putc(const char c); -extern void puthex(unsigned long val); -extern void puts(const char *); -extern void udelay(long delay); -extern unsigned char inb(int port); -extern void board_isa_init(void); -extern void ISA_init(unsigned long base); diff --git a/arch/ppc/boot/include/of1275.h b/arch/ppc/boot/include/of1275.h deleted file mode 100644 index 4ed88acfa73a..000000000000 --- a/arch/ppc/boot/include/of1275.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -typedef void *prom_handle; -typedef void *ihandle; -typedef void *phandle; -typedef int (*prom_entry)(void *); - -#define OF_INVALID_HANDLE ((prom_handle)-1UL) - -extern prom_entry of_prom_entry; - -/* function declarations */ - -int call_prom(const char *service, int nargs, int nret, ...); -int call_prom_ret(const char *service, int nargs, int nret, - unsigned int *rets, ...); -void * claim(unsigned int virt, unsigned int size, unsigned int align); -int map(unsigned int phys, unsigned int virt, unsigned int size); -void enter(void); -void exit(void); -phandle finddevice(const char *name); -int getprop(phandle node, const char *name, void *buf, int buflen); -void ofinit(prom_entry entry); -int ofstdio(ihandle *stdin, ihandle *stdout, ihandle *stderr); -int read(ihandle instance, void *buf, int buflen); -void release(void *virt, unsigned int size); -int write(ihandle instance, void *buf, int buflen); - -/* inlines */ - -extern inline void pause(void) -{ - enter(); -} diff --git a/arch/ppc/boot/include/rs6000.h b/arch/ppc/boot/include/rs6000.h deleted file mode 100644 index 433f45084e41..000000000000 --- a/arch/ppc/boot/include/rs6000.h +++ /dev/null @@ -1,243 +0,0 @@ -/* IBM RS/6000 "XCOFF" file definitions for BFD. - Copyright (C) 1990, 1991 Free Software Foundation, Inc. - FIXME: Can someone provide a transliteration of this name into ASCII? - Using the following chars caused a compiler warning on HIUX (so I replaced - them with octal escapes), and isn't useful without an understanding of what - character set it is. - Written by Mimi Ph\373\364ng-Th\345o V\365 of IBM - and John Gilmore of Cygnus Support. */ - -/********************** FILE HEADER **********************/ - -struct external_filehdr { - char f_magic[2]; /* magic number */ - char f_nscns[2]; /* number of sections */ - char f_timdat[4]; /* time & date stamp */ - char f_symptr[4]; /* file pointer to symtab */ - char f_nsyms[4]; /* number of symtab entries */ - char f_opthdr[2]; /* sizeof(optional hdr) */ - char f_flags[2]; /* flags */ -}; - - /* IBM RS/6000 */ -#define U802WRMAGIC 0730 /* writeable text segments **chh** */ -#define U802ROMAGIC 0735 /* readonly sharable text segments */ -#define U802TOCMAGIC 0737 /* readonly text segments and TOC */ - -#define BADMAG(x) \ - ((x).f_magic != U802ROMAGIC && (x).f_magic != U802WRMAGIC && \ - (x).f_magic != U802TOCMAGIC) - -#define FILHDR struct external_filehdr -#define FILHSZ 20 - - -/********************** AOUT "OPTIONAL HEADER" **********************/ - - -typedef struct -{ - unsigned char magic[2]; /* type of file */ - unsigned char vstamp[2]; /* version stamp */ - unsigned char tsize[4]; /* text size in bytes, padded to FW bdry */ - unsigned char dsize[4]; /* initialized data " " */ - unsigned char bsize[4]; /* uninitialized data " " */ - unsigned char entry[4]; /* entry pt. */ - unsigned char text_start[4]; /* base of text used for this file */ - unsigned char data_start[4]; /* base of data used for this file */ - unsigned char o_toc[4]; /* address of TOC */ - unsigned char o_snentry[2]; /* section number of entry point */ - unsigned char o_sntext[2]; /* section number of .text section */ - unsigned char o_sndata[2]; /* section number of .data section */ - unsigned char o_sntoc[2]; /* section number of TOC */ - unsigned char o_snloader[2]; /* section number of .loader section */ - unsigned char o_snbss[2]; /* section number of .bss section */ - unsigned char o_algntext[2]; /* .text alignment */ - unsigned char o_algndata[2]; /* .data alignment */ - unsigned char o_modtype[2]; /* module type (??) */ - unsigned char o_cputype[2]; /* cpu type */ - unsigned char o_maxstack[4]; /* max stack size (??) */ - unsigned char o_maxdata[4]; /* max data size (??) */ - unsigned char o_resv2[12]; /* reserved */ -} -AOUTHDR; - -#define AOUTSZ 72 -#define SMALL_AOUTSZ (28) -#define AOUTHDRSZ 72 - -#define RS6K_AOUTHDR_OMAGIC 0x0107 /* old: text & data writeable */ -#define RS6K_AOUTHDR_NMAGIC 0x0108 /* new: text r/o, data r/w */ -#define RS6K_AOUTHDR_ZMAGIC 0x010B /* paged: text r/o, both page-aligned */ - - -/********************** SECTION HEADER **********************/ - - -struct external_scnhdr { - char s_name[8]; /* section name */ - char s_paddr[4]; /* physical address, aliased s_nlib */ - char s_vaddr[4]; /* virtual address */ - char s_size[4]; /* section size */ - char s_scnptr[4]; /* file ptr to raw data for section */ - char s_relptr[4]; /* file ptr to relocation */ - char s_lnnoptr[4]; /* file ptr to line numbers */ - char s_nreloc[2]; /* number of relocation entries */ - char s_nlnno[2]; /* number of line number entries*/ - char s_flags[4]; /* flags */ -}; - -/* - * names of "special" sections - */ -#define _TEXT ".text" -#define _DATA ".data" -#define _BSS ".bss" -#define _PAD ".pad" -#define _LOADER ".loader" - -#define SCNHDR struct external_scnhdr -#define SCNHSZ 40 - -/* XCOFF uses a special .loader section with type STYP_LOADER. */ -#define STYP_LOADER 0x1000 - -/* XCOFF uses a special .debug section with type STYP_DEBUG. */ -#define STYP_DEBUG 0x2000 - -/* XCOFF handles line number or relocation overflow by creating - another section header with STYP_OVRFLO set. */ -#define STYP_OVRFLO 0x8000 - -/********************** LINE NUMBERS **********************/ - -/* 1 line number entry for every "breakpointable" source line in a section. - * Line numbers are grouped on a per function basis; first entry in a function - * grouping will have l_lnno = 0 and in place of physical address will be the - * symbol table index of the function name. - */ -struct external_lineno { - union { - char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ - char l_paddr[4]; /* (physical) address of line number */ - } l_addr; - char l_lnno[2]; /* line number */ -}; - - -#define LINENO struct external_lineno -#define LINESZ 6 - - -/********************** SYMBOLS **********************/ - -#define E_SYMNMLEN 8 /* # characters in a symbol name */ -#define E_FILNMLEN 14 /* # characters in a file name */ -#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ - -struct external_syment -{ - union { - char e_name[E_SYMNMLEN]; - struct { - char e_zeroes[4]; - char e_offset[4]; - } e; - } e; - char e_value[4]; - char e_scnum[2]; - char e_type[2]; - char e_sclass[1]; - char e_numaux[1]; -}; - - - -#define N_BTMASK (017) -#define N_TMASK (060) -#define N_BTSHFT (4) -#define N_TSHIFT (2) - - -union external_auxent { - struct { - char x_tagndx[4]; /* str, un, or enum tag indx */ - union { - struct { - char x_lnno[2]; /* declaration line number */ - char x_size[2]; /* str/union/array size */ - } x_lnsz; - char x_fsize[4]; /* size of function */ - } x_misc; - union { - struct { /* if ISFCN, tag, or .bb */ - char x_lnnoptr[4]; /* ptr to fcn line # */ - char x_endndx[4]; /* entry ndx past block end */ - } x_fcn; - struct { /* if ISARY, up to 4 dimen. */ - char x_dimen[E_DIMNUM][2]; - } x_ary; - } x_fcnary; - char x_tvndx[2]; /* tv index */ - } x_sym; - - union { - char x_fname[E_FILNMLEN]; - struct { - char x_zeroes[4]; - char x_offset[4]; - } x_n; - } x_file; - - struct { - char x_scnlen[4]; /* section length */ - char x_nreloc[2]; /* # relocation entries */ - char x_nlinno[2]; /* # line numbers */ - } x_scn; - - struct { - char x_tvfill[4]; /* tv fill value */ - char x_tvlen[2]; /* length of .tv */ - char x_tvran[2][2]; /* tv range */ - } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ - - struct { - unsigned char x_scnlen[4]; - unsigned char x_parmhash[4]; - unsigned char x_snhash[2]; - unsigned char x_smtyp[1]; - unsigned char x_smclas[1]; - unsigned char x_stab[4]; - unsigned char x_snstab[2]; - } x_csect; - -}; - -#define SYMENT struct external_syment -#define SYMESZ 18 -#define AUXENT union external_auxent -#define AUXESZ 18 -#define DBXMASK 0x80 /* for dbx storage mask */ -#define SYMNAME_IN_DEBUG(symptr) ((symptr)->n_sclass & DBXMASK) - - - -/********************** RELOCATION DIRECTIVES **********************/ - - -struct external_reloc { - char r_vaddr[4]; - char r_symndx[4]; - char r_size[1]; - char r_type[1]; -}; - - -#define RELOC struct external_reloc -#define RELSZ 10 - -#define DEFAULT_DATA_SECTION_ALIGNMENT 4 -#define DEFAULT_BSS_SECTION_ALIGNMENT 4 -#define DEFAULT_TEXT_SECTION_ALIGNMENT 4 -/* For new sections we havn't heard of before */ -#define DEFAULT_SECTION_ALIGNMENT 4 diff --git a/arch/ppc/boot/include/serial.h b/arch/ppc/boot/include/serial.h deleted file mode 100644 index d710eabb4256..000000000000 --- a/arch/ppc/boot/include/serial.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * A really private header file for the (dumb) serial driver in arch/ppc/boot - * - * Shamelessly taken from include/linux/serialP.h: - * - * Copyright (C) 1997 by Theodore Ts'o. - * - * Redistribution of this file is permitted under the terms of the GNU - * Public License (GPL) - */ - -#ifndef _PPC_BOOT_SERIALP_H -#define _PPC_BOOT_SERIALP_H - -/* - * This is our internal structure for each serial port's state. - * - * Many fields are paralleled by the structure used by the serial_struct - * structure. - * - * Given that this is how SERIAL_PORT_DFNS are done, and that we need - * to use a few of their fields, we need to have our own copy of it. - */ -struct serial_state { - int magic; - int baud_base; - unsigned long port; - int irq; - int flags; - int hub6; - int type; - int line; - int revision; /* Chip revision (950) */ - int xmit_fifo_size; - int custom_divisor; - int count; - u8 *iomem_base; - u16 iomem_reg_shift; - unsigned short close_delay; - unsigned short closing_wait; /* time to wait before closing */ - unsigned long icount; - int io_type; - void *info; - void *dev; -}; -#endif /* _PPC_BOOT_SERIAL_H */ diff --git a/arch/ppc/boot/ld.script b/arch/ppc/boot/ld.script deleted file mode 100644 index d4dd8f15395e..000000000000 --- a/arch/ppc/boot/ld.script +++ /dev/null @@ -1,85 +0,0 @@ -OUTPUT_ARCH(powerpc:common) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .plt : { *(.plt) } - .text : - { - *(.text) - *(.fixup) - __relocate_start = .; - *(.relocate_code) - __relocate_end = .; - } - _etext = .; - PROVIDE (etext = .); - - /* Read-write section, merged into data segment: */ - . = ALIGN(4096); - .data : - { - *(.data) - *(.data1) - *(.data.boot) - *(.sdata) - *(.sdata2) - *(.got.plt) *(.got) - *(.dynamic) - *(.rodata) - *(.rodata.*) - *(.rodata1) - *(.got1) - __image_begin = .; - *(.image) - __image_end = .; - . = ALIGN(4096); - __ramdisk_begin = .; - *(.ramdisk) - __ramdisk_end = .; - . = ALIGN(4096); - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = ALIGN(4096); - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); - - /DISCARD/ : { - *(__ksymtab) - *(__ksymtab_strings) - *(__bug_table) - *(__kcrctab) - } - -} diff --git a/arch/ppc/boot/lib/.gitignore b/arch/ppc/boot/lib/.gitignore deleted file mode 100644 index 1629a6167755..000000000000 --- a/arch/ppc/boot/lib/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -inffast.c -inflate.c -inftrees.c diff --git a/arch/ppc/boot/lib/Makefile b/arch/ppc/boot/lib/Makefile deleted file mode 100644 index 2f995f712ec5..000000000000 --- a/arch/ppc/boot/lib/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# Makefile for some libs needed by zImage. -# - -CFLAGS_kbd.o := -Idrivers/char -CFLAGS_vreset.o := -Iarch/ppc/boot/include - -zlib := inffast.c inflate.c inftrees.c - -lib-y += $(zlib:.c=.o) div64.o -lib-$(CONFIG_VGA_CONSOLE) += vreset.o kbd.o - - -# zlib files needs header from their original place -EXTRA_CFLAGS += -Ilib/zlib_inflate - -quiet_cmd_copy_zlib = COPY $@ - cmd_copy_zlib = cat $< > $@ - -$(addprefix $(obj)/,$(zlib)): $(obj)/%: $(srctree)/lib/zlib_inflate/% - $(call cmd,copy_zlib) - -clean-files := $(zlib) diff --git a/arch/ppc/boot/lib/div64.S b/arch/ppc/boot/lib/div64.S deleted file mode 100644 index 3527569e9926..000000000000 --- a/arch/ppc/boot/lib/div64.S +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Divide a 64-bit unsigned number by a 32-bit unsigned number. - * This routine assumes that the top 32 bits of the dividend are - * non-zero to start with. - * On entry, r3 points to the dividend, which get overwritten with - * the 64-bit quotient, and r4 contains the divisor. - * On exit, r3 contains the remainder. - * - * Copyright (C) 2002 Paul Mackerras, IBM Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#include -#include - -_GLOBAL(__div64_32) - lwz r5,0(r3) # get the dividend into r5/r6 - lwz r6,4(r3) - cmplw r5,r4 - li r7,0 - li r8,0 - blt 1f - divwu r7,r5,r4 # if dividend.hi >= divisor, - mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor - subf. r5,r0,r5 # dividend.hi %= divisor - beq 3f -1: mr r11,r5 # here dividend.hi != 0 - andis. r0,r5,0xc000 - bne 2f - cntlzw r0,r5 # we are shifting the dividend right - li r10,-1 # to make it < 2^32, and shifting - srw r10,r10,r0 # the divisor right the same amount, - add r9,r4,r10 # rounding up (so the estimate cannot - andc r11,r6,r10 # ever be too large, only too small) - andc r9,r9,r10 - or r11,r5,r11 - rotlw r9,r9,r0 - rotlw r11,r11,r0 - divwu r11,r11,r9 # then we divide the shifted quantities -2: mullw r10,r11,r4 # to get an estimate of the quotient, - mulhwu r9,r11,r4 # multiply the estimate by the divisor, - subfc r6,r10,r6 # take the product from the divisor, - add r8,r8,r11 # and add the estimate to the accumulated - subfe. r5,r9,r5 # quotient - bne 1b -3: cmplw r6,r4 - blt 4f - divwu r0,r6,r4 # perform the remaining 32-bit division - mullw r10,r0,r4 # and get the remainder - add r8,r8,r0 - subf r6,r10,r6 -4: stw r7,0(r3) # return the quotient in *r3 - stw r8,4(r3) - mr r3,r6 # return the remainder in r3 - blr diff --git a/arch/ppc/boot/lib/kbd.c b/arch/ppc/boot/lib/kbd.c deleted file mode 100644 index 3931727434de..000000000000 --- a/arch/ppc/boot/lib/kbd.c +++ /dev/null @@ -1,248 +0,0 @@ -#include - -#include "defkeymap.c" /* yeah I know it's bad -- Cort */ - - -unsigned char shfts, ctls, alts, caps; - -#define KBDATAP 0x60 /* kbd data port */ -#define KBSTATUSPORT 0x61 /* kbd status */ -#define KBSTATP 0x64 /* kbd status port */ -#define KBINRDY 0x01 -#define KBOUTRDY 0x02 - -extern unsigned char inb(int port); -extern void outb(int port, char val); -extern void puts(const char *); -extern void puthex(unsigned long val); -extern void udelay(long x); - -static int kbd(int noblock) -{ - unsigned char dt, brk, val; - unsigned code; -loop: - if (noblock) { - if ((inb(KBSTATP) & KBINRDY) == 0) - return (-1); - } else while((inb(KBSTATP) & KBINRDY) == 0) ; - - dt = inb(KBDATAP); - - brk = dt & 0x80; /* brk == 1 on key release */ - dt = dt & 0x7f; /* keycode */ - - if (shfts) - code = shift_map[dt]; - else if (ctls) - code = ctrl_map[dt]; - else - code = plain_map[dt]; - - val = KVAL(code); - switch (KTYP(code) & 0x0f) { - case KT_LATIN: - if (brk) - break; - if (alts) - val |= 0x80; - if (val == 0x7f) /* map delete to backspace */ - val = '\b'; - return val; - - case KT_LETTER: - if (brk) - break; - if (caps) - val -= 'a'-'A'; - return val; - - case KT_SPEC: - if (brk) - break; - if (val == KVAL(K_CAPS)) - caps = !caps; - else if (val == KVAL(K_ENTER)) { -enter: /* Wait for key up */ - while (1) { - while((inb(KBSTATP) & KBINRDY) == 0) ; - dt = inb(KBDATAP); - if (dt & 0x80) /* key up */ break; - } - return 10; - } - break; - - case KT_PAD: - if (brk) - break; - if (val < 10) - return val; - if (val == KVAL(K_PENTER)) - goto enter; - break; - - case KT_SHIFT: - switch (val) { - case KG_SHIFT: - case KG_SHIFTL: - case KG_SHIFTR: - shfts = brk ? 0 : 1; - break; - case KG_ALT: - case KG_ALTGR: - alts = brk ? 0 : 1; - break; - case KG_CTRL: - case KG_CTRLL: - case KG_CTRLR: - ctls = brk ? 0 : 1; - break; - } - break; - - case KT_LOCK: - switch (val) { - case KG_SHIFT: - case KG_SHIFTL: - case KG_SHIFTR: - if (brk) - shfts = !shfts; - break; - case KG_ALT: - case KG_ALTGR: - if (brk) - alts = !alts; - break; - case KG_CTRL: - case KG_CTRLL: - case KG_CTRLR: - if (brk) - ctls = !ctls; - break; - } - break; - } - if (brk) return (-1); /* Ignore initial 'key up' codes */ - goto loop; -} - -static int __kbdreset(void) -{ - unsigned char c; - int i, t; - - /* flush input queue */ - t = 2000; - while ((inb(KBSTATP) & KBINRDY)) - { - (void)inb(KBDATAP); - if (--t == 0) - return 1; - } - /* Send self-test */ - t = 20000; - while (inb(KBSTATP) & KBOUTRDY) - if (--t == 0) - return 2; - outb(KBSTATP,0xAA); - t = 200000; - while ((inb(KBSTATP) & KBINRDY) == 0) /* wait input ready */ - if (--t == 0) - return 3; - if ((c = inb(KBDATAP)) != 0x55) - { - puts("Keyboard self test failed - result:"); - puthex(c); - puts("\n"); - } - /* Enable interrupts and keyboard controller */ - t = 20000; - while (inb(KBSTATP) & KBOUTRDY) - if (--t == 0) return 4; - outb(KBSTATP,0x60); - t = 20000; - while (inb(KBSTATP) & KBOUTRDY) - if (--t == 0) return 5; - outb(KBDATAP,0x45); - for (i = 0; i < 10000; i++) udelay(1); - - t = 20000; - while (inb(KBSTATP) & KBOUTRDY) - if (--t == 0) return 6; - outb(KBSTATP,0x20); - t = 200000; - while ((inb(KBSTATP) & KBINRDY) == 0) /* wait input ready */ - if (--t == 0) return 7; - if (! (inb(KBDATAP) & 0x40)) { - /* - * Quote from PS/2 System Reference Manual: - * - * "Address hex 0060 and address hex 0064 should be - * written only when the input-buffer-full bit and - * output-buffer-full bit in the Controller Status - * register are set 0." (KBINRDY and KBOUTRDY) - */ - t = 200000; - while (inb(KBSTATP) & (KBINRDY | KBOUTRDY)) - if (--t == 0) return 8; - outb(KBDATAP,0xF0); - t = 200000; - while (inb(KBSTATP) & (KBINRDY | KBOUTRDY)) - if (--t == 0) return 9; - outb(KBDATAP,0x01); - } - t = 20000; - while (inb(KBSTATP) & KBOUTRDY) - if (--t == 0) return 10; - outb(KBSTATP,0xAE); - return 0; -} - -static void kbdreset(void) -{ - int ret = __kbdreset(); - - if (ret) { - puts("__kbdreset failed: "); - puthex(ret); - puts("\n"); - } -} - -/* We have to actually read the keyboard when CRT_tstc is called, - * since the pending data might be a key release code, and therefore - * not valid data. In this case, kbd() will return -1, even though there's - * data to be read. Of course, we might actually read a valid key press, - * in which case it gets queued into key_pending for use by CRT_getc. - */ - -static int kbd_reset = 0; - -static int key_pending = -1; - -int CRT_getc(void) -{ - int c; - if (!kbd_reset) {kbdreset(); kbd_reset++; } - - if (key_pending != -1) { - c = key_pending; - key_pending = -1; - return c; - } else { - while ((c = kbd(0)) == 0) ; - return c; - } -} - -int CRT_tstc(void) -{ - if (!kbd_reset) {kbdreset(); kbd_reset++; } - - while (key_pending == -1 && ((inb(KBSTATP) & KBINRDY) != 0)) { - key_pending = kbd(1); - } - - return (key_pending != -1); -} diff --git a/arch/ppc/boot/lib/vreset.c b/arch/ppc/boot/lib/vreset.c deleted file mode 100644 index 98539e9f7f96..000000000000 --- a/arch/ppc/boot/lib/vreset.c +++ /dev/null @@ -1,805 +0,0 @@ -/* - * vreset.c - * - * Initialize the VGA control registers to 80x25 text mode. - * - * Adapted from a program by: - * Steve Sellgren - * San Francisco Indigo Company - * sfindigo!sellgren@uunet.uu.net - * - * Original concept by: - * Gary Thomas - * Adapted for Moto boxes by: - * Pat Kane & Mark Scott, 1996 - * Adapted for IBM portables by: - * Takeshi Ishimoto - * Multi-console support: - * Terje Malmedal - */ - -#include "iso_font.h" -#include "nonstdio.h" - -extern char *vidmem; -extern int lines, cols; -struct VaRegs; - -/* - * VGA Register - */ -struct VgaRegs -{ - unsigned short io_port; - unsigned char io_index; - unsigned char io_value; -}; - -void unlockVideo(int slot); -void setTextRegs(struct VgaRegs *svp); -void setTextCLUT(int shift); -void clearVideoMemory(void); -void loadFont(unsigned char *ISA_mem); - -static void mdelay(int ms) -{ - for (; ms > 0; --ms) - udelay(1000); -} - -/* - * Default console text mode registers used to reset - * graphics adapter. - */ -#define NREGS 54 -#define ENDMK 0xFFFF /* End marker */ - -#define S3Vendor 0x5333 -#define CirrusVendor 0x1013 -#define DiamondVendor 0x100E -#define MatroxVendor 0x102B -#define ParadiseVendor 0x101C - -struct VgaRegs GenVgaTextRegs[NREGS+1] = { - /* port index value */ - /* SR Regs */ - { 0x3c4, 0x1, 0x0 }, - { 0x3c4, 0x2, 0x3 }, - { 0x3c4, 0x3, 0x0 }, - { 0x3c4, 0x4, 0x2 }, - /* CR Regs */ - { 0x3d4, 0x0, 0x5f }, - { 0x3d4, 0x1, 0x4f }, - { 0x3d4, 0x2, 0x50 }, - { 0x3d4, 0x3, 0x82 }, - { 0x3d4, 0x4, 0x55 }, - { 0x3d4, 0x5, 0x81 }, - { 0x3d4, 0x6, 0xbf }, - { 0x3d4, 0x7, 0x1f }, - { 0x3d4, 0x8, 0x00 }, - { 0x3d4, 0x9, 0x4f }, - { 0x3d4, 0xa, 0x0d }, - { 0x3d4, 0xb, 0x0e }, - { 0x3d4, 0xc, 0x00 }, - { 0x3d4, 0xd, 0x00 }, - { 0x3d4, 0xe, 0x00 }, - { 0x3d4, 0xf, 0x00 }, - { 0x3d4, 0x10, 0x9c }, - { 0x3d4, 0x11, 0x8e }, - { 0x3d4, 0x12, 0x8f }, - { 0x3d4, 0x13, 0x28 }, - { 0x3d4, 0x14, 0x1f }, - { 0x3d4, 0x15, 0x96 }, - { 0x3d4, 0x16, 0xb9 }, - { 0x3d4, 0x17, 0xa3 }, - /* GR Regs */ - { 0x3ce, 0x0, 0x0 }, - { 0x3ce, 0x1, 0x0 }, - { 0x3ce, 0x2, 0x0 }, - { 0x3ce, 0x3, 0x0 }, - { 0x3ce, 0x4, 0x0 }, - { 0x3ce, 0x5, 0x10 }, - { 0x3ce, 0x6, 0xe }, - { 0x3ce, 0x7, 0x0 }, - { 0x3ce, 0x8, 0xff }, - { ENDMK } -}; - -struct RGBColors -{ - unsigned char r, g, b; -}; - -/* - * Default console text mode color table. - * These values were obtained by booting Linux with - * text mode firmware & then dumping the registers. - */ -struct RGBColors TextCLUT[256] = -{ - /* red green blue */ - { 0x0, 0x0, 0x0 }, - { 0x0, 0x0, 0x2a }, - { 0x0, 0x2a, 0x0 }, - { 0x0, 0x2a, 0x2a }, - { 0x2a, 0x0, 0x0 }, - { 0x2a, 0x0, 0x2a }, - { 0x2a, 0x2a, 0x0 }, - { 0x2a, 0x2a, 0x2a }, - { 0x0, 0x0, 0x15 }, - { 0x0, 0x0, 0x3f }, - { 0x0, 0x2a, 0x15 }, - { 0x0, 0x2a, 0x3f }, - { 0x2a, 0x0, 0x15 }, - { 0x2a, 0x0, 0x3f }, - { 0x2a, 0x2a, 0x15 }, - { 0x2a, 0x2a, 0x3f }, - { 0x0, 0x15, 0x0 }, - { 0x0, 0x15, 0x2a }, - { 0x0, 0x3f, 0x0 }, - { 0x0, 0x3f, 0x2a }, - { 0x2a, 0x15, 0x0 }, - { 0x2a, 0x15, 0x2a }, - { 0x2a, 0x3f, 0x0 }, - { 0x2a, 0x3f, 0x2a }, - { 0x0, 0x15, 0x15 }, - { 0x0, 0x15, 0x3f }, - { 0x0, 0x3f, 0x15 }, - { 0x0, 0x3f, 0x3f }, - { 0x2a, 0x15, 0x15 }, - { 0x2a, 0x15, 0x3f }, - { 0x2a, 0x3f, 0x15 }, - { 0x2a, 0x3f, 0x3f }, - { 0x15, 0x0, 0x0 }, - { 0x15, 0x0, 0x2a }, - { 0x15, 0x2a, 0x0 }, - { 0x15, 0x2a, 0x2a }, - { 0x3f, 0x0, 0x0 }, - { 0x3f, 0x0, 0x2a }, - { 0x3f, 0x2a, 0x0 }, - { 0x3f, 0x2a, 0x2a }, - { 0x15, 0x0, 0x15 }, - { 0x15, 0x0, 0x3f }, - { 0x15, 0x2a, 0x15 }, - { 0x15, 0x2a, 0x3f }, - { 0x3f, 0x0, 0x15 }, - { 0x3f, 0x0, 0x3f }, - { 0x3f, 0x2a, 0x15 }, - { 0x3f, 0x2a, 0x3f }, - { 0x15, 0x15, 0x0 }, - { 0x15, 0x15, 0x2a }, - { 0x15, 0x3f, 0x0 }, - { 0x15, 0x3f, 0x2a }, - { 0x3f, 0x15, 0x0 }, - { 0x3f, 0x15, 0x2a }, - { 0x3f, 0x3f, 0x0 }, - { 0x3f, 0x3f, 0x2a }, - { 0x15, 0x15, 0x15 }, - { 0x15, 0x15, 0x3f }, - { 0x15, 0x3f, 0x15 }, - { 0x15, 0x3f, 0x3f }, - { 0x3f, 0x15, 0x15 }, - { 0x3f, 0x15, 0x3f }, - { 0x3f, 0x3f, 0x15 }, - { 0x3f, 0x3f, 0x3f }, - { 0x39, 0xc, 0x5 }, - { 0x15, 0x2c, 0xf }, - { 0x26, 0x10, 0x3d }, - { 0x29, 0x29, 0x38 }, - { 0x4, 0x1a, 0xe }, - { 0x2, 0x1e, 0x3a }, - { 0x3c, 0x25, 0x33 }, - { 0x3c, 0xc, 0x2c }, - { 0x3f, 0x3, 0x2b }, - { 0x1c, 0x9, 0x13 }, - { 0x25, 0x2a, 0x35 }, - { 0x1e, 0xa, 0x38 }, - { 0x24, 0x8, 0x3 }, - { 0x3, 0xe, 0x36 }, - { 0xc, 0x6, 0x2a }, - { 0x26, 0x3, 0x32 }, - { 0x5, 0x2f, 0x33 }, - { 0x3c, 0x35, 0x2f }, - { 0x2d, 0x26, 0x3e }, - { 0xd, 0xa, 0x10 }, - { 0x25, 0x3c, 0x11 }, - { 0xd, 0x4, 0x2e }, - { 0x5, 0x19, 0x3e }, - { 0xc, 0x13, 0x34 }, - { 0x2b, 0x6, 0x24 }, - { 0x4, 0x3, 0xd }, - { 0x2f, 0x3c, 0xc }, - { 0x2a, 0x37, 0x1f }, - { 0xf, 0x12, 0x38 }, - { 0x38, 0xe, 0x2a }, - { 0x12, 0x2f, 0x19 }, - { 0x29, 0x2e, 0x31 }, - { 0x25, 0x13, 0x3e }, - { 0x33, 0x3e, 0x33 }, - { 0x1d, 0x2c, 0x25 }, - { 0x15, 0x15, 0x5 }, - { 0x32, 0x25, 0x39 }, - { 0x1a, 0x7, 0x1f }, - { 0x13, 0xe, 0x1d }, - { 0x36, 0x17, 0x34 }, - { 0xf, 0x15, 0x23 }, - { 0x2, 0x35, 0xd }, - { 0x15, 0x3f, 0xc }, - { 0x14, 0x2f, 0xf }, - { 0x19, 0x21, 0x3e }, - { 0x27, 0x11, 0x2f }, - { 0x38, 0x3f, 0x3c }, - { 0x36, 0x2d, 0x15 }, - { 0x16, 0x17, 0x2 }, - { 0x1, 0xa, 0x3d }, - { 0x1b, 0x11, 0x3f }, - { 0x21, 0x3c, 0xd }, - { 0x1a, 0x39, 0x3d }, - { 0x8, 0xe, 0xe }, - { 0x22, 0x21, 0x23 }, - { 0x1e, 0x30, 0x5 }, - { 0x1f, 0x22, 0x3d }, - { 0x1e, 0x2f, 0xa }, - { 0x0, 0x1c, 0xe }, - { 0x0, 0x1c, 0x15 }, - { 0x0, 0x1c, 0x1c }, - { 0x0, 0x15, 0x1c }, - { 0x0, 0xe, 0x1c }, - { 0x0, 0x7, 0x1c }, - { 0xe, 0xe, 0x1c }, - { 0x11, 0xe, 0x1c }, - { 0x15, 0xe, 0x1c }, - { 0x18, 0xe, 0x1c }, - { 0x1c, 0xe, 0x1c }, - { 0x1c, 0xe, 0x18 }, - { 0x1c, 0xe, 0x15 }, - { 0x1c, 0xe, 0x11 }, - { 0x1c, 0xe, 0xe }, - { 0x1c, 0x11, 0xe }, - { 0x1c, 0x15, 0xe }, - { 0x1c, 0x18, 0xe }, - { 0x1c, 0x1c, 0xe }, - { 0x18, 0x1c, 0xe }, - { 0x15, 0x1c, 0xe }, - { 0x11, 0x1c, 0xe }, - { 0xe, 0x1c, 0xe }, - { 0xe, 0x1c, 0x11 }, - { 0xe, 0x1c, 0x15 }, - { 0xe, 0x1c, 0x18 }, - { 0xe, 0x1c, 0x1c }, - { 0xe, 0x18, 0x1c }, - { 0xe, 0x15, 0x1c }, - { 0xe, 0x11, 0x1c }, - { 0x14, 0x14, 0x1c }, - { 0x16, 0x14, 0x1c }, - { 0x18, 0x14, 0x1c }, - { 0x1a, 0x14, 0x1c }, - { 0x1c, 0x14, 0x1c }, - { 0x1c, 0x14, 0x1a }, - { 0x1c, 0x14, 0x18 }, - { 0x1c, 0x14, 0x16 }, - { 0x1c, 0x14, 0x14 }, - { 0x1c, 0x16, 0x14 }, - { 0x1c, 0x18, 0x14 }, - { 0x1c, 0x1a, 0x14 }, - { 0x1c, 0x1c, 0x14 }, - { 0x1a, 0x1c, 0x14 }, - { 0x18, 0x1c, 0x14 }, - { 0x16, 0x1c, 0x14 }, - { 0x14, 0x1c, 0x14 }, - { 0x14, 0x1c, 0x16 }, - { 0x14, 0x1c, 0x18 }, - { 0x14, 0x1c, 0x1a }, - { 0x14, 0x1c, 0x1c }, - { 0x14, 0x1a, 0x1c }, - { 0x14, 0x18, 0x1c }, - { 0x14, 0x16, 0x1c }, - { 0x0, 0x0, 0x10 }, - { 0x4, 0x0, 0x10 }, - { 0x8, 0x0, 0x10 }, - { 0xc, 0x0, 0x10 }, - { 0x10, 0x0, 0x10 }, - { 0x10, 0x0, 0xc }, - { 0x10, 0x0, 0x8 }, - { 0x10, 0x0, 0x4 }, - { 0x10, 0x0, 0x0 }, - { 0x10, 0x4, 0x0 }, - { 0x10, 0x8, 0x0 }, - { 0x10, 0xc, 0x0 }, - { 0x10, 0x10, 0x0 }, - { 0xc, 0x10, 0x0 }, - { 0x8, 0x10, 0x0 }, - { 0x4, 0x10, 0x0 }, - { 0x0, 0x10, 0x0 }, - { 0x0, 0x10, 0x4 }, - { 0x0, 0x10, 0x8 }, - { 0x0, 0x10, 0xc }, - { 0x0, 0x10, 0x10 }, - { 0x0, 0xc, 0x10 }, - { 0x0, 0x8, 0x10 }, - { 0x0, 0x4, 0x10 }, - { 0x8, 0x8, 0x10 }, - { 0xa, 0x8, 0x10 }, - { 0xc, 0x8, 0x10 }, - { 0xe, 0x8, 0x10 }, - { 0x10, 0x8, 0x10 }, - { 0x10, 0x8, 0xe }, - { 0x10, 0x8, 0xc }, - { 0x10, 0x8, 0xa }, - { 0x10, 0x8, 0x8 }, - { 0x10, 0xa, 0x8 }, - { 0x10, 0xc, 0x8 }, - { 0x10, 0xe, 0x8 }, - { 0x10, 0x10, 0x8 }, - { 0xe, 0x10, 0x8 }, - { 0xc, 0x10, 0x8 }, - { 0xa, 0x10, 0x8 }, - { 0x8, 0x10, 0x8 }, - { 0x8, 0x10, 0xa }, - { 0x8, 0x10, 0xc }, - { 0x8, 0x10, 0xe }, - { 0x8, 0x10, 0x10 }, - { 0x8, 0xe, 0x10 }, - { 0x8, 0xc, 0x10 }, - { 0x8, 0xa, 0x10 }, - { 0xb, 0xb, 0x10 }, - { 0xc, 0xb, 0x10 }, - { 0xd, 0xb, 0x10 }, - { 0xf, 0xb, 0x10 }, - { 0x10, 0xb, 0x10 }, - { 0x10, 0xb, 0xf }, - { 0x10, 0xb, 0xd }, - { 0x10, 0xb, 0xc }, - { 0x10, 0xb, 0xb }, - { 0x10, 0xc, 0xb }, - { 0x10, 0xd, 0xb }, - { 0x10, 0xf, 0xb }, - { 0x10, 0x10, 0xb }, - { 0xf, 0x10, 0xb }, - { 0xd, 0x10, 0xb }, - { 0xc, 0x10, 0xb }, - { 0xb, 0x10, 0xb }, - { 0xb, 0x10, 0xc }, - { 0xb, 0x10, 0xd }, - { 0xb, 0x10, 0xf }, - { 0xb, 0x10, 0x10 }, - { 0xb, 0xf, 0x10 }, - { 0xb, 0xd, 0x10 }, - { 0xb, 0xc, 0x10 }, - { 0x0, 0x0, 0x0 }, - { 0x0, 0x0, 0x0 }, - { 0x0, 0x0, 0x0 }, - { 0x0, 0x0, 0x0 }, - { 0x0, 0x0, 0x0 }, - { 0x0, 0x0, 0x0 }, - { 0x0, 0x0, 0x0 } -}; - -unsigned char AC[21] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, - 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, - 0x0C, 0x00, 0x0F, 0x08, 0x00}; - -static int scanPCI(int start_slt); -static int PCIVendor(int); -#ifdef DEBUG -static void printslots(void); -#endif -extern void puthex(unsigned long); -extern void puts(const char *); -static void unlockS3(void); - -static inline void -outw(int port, unsigned short val) -{ - outb(port, val >> 8); - outb(port+1, val); -} - -int -vga_init(unsigned char *ISA_mem) -{ - int slot; - struct VgaRegs *VgaTextRegs; - - /* See if VGA already in TEXT mode - exit if so! */ - outb(0x3CE, 0x06); - if ((inb(0x3CF) & 0x01) == 0){ - puts("VGA already in text mode\n"); - return 0; - } - - /* If no VGA responding in text mode, then we have some work to do... - */ - slot = -1; - while((slot = scanPCI(slot)) > -1) { /* find video card in use */ - unlockVideo(slot); /* enable I/O to card */ - VgaTextRegs = GenVgaTextRegs; - - switch (PCIVendor(slot)) { - default: - break; - case(S3Vendor): - unlockS3(); - break; - - case(CirrusVendor): - outw(0x3C4, 0x0612); /* unlock ext regs */ - outw(0x3C4, 0x0700); /* reset ext sequence mode */ - break; - - case(ParadiseVendor): /* IBM Portable 850 */ - outw(0x3ce, 0x0f05); /* unlock pardise registers */ - outw(0x3c4, 0x0648); - outw(0x3d4, 0x2985); - outw(0x3d4, 0x34a6); - outb(0x3ce, 0x0b); /* disable linear addressing */ - outb(0x3cf, inb(0x3cf) & ~0x30); - outw(0x3c4, 0x1400); - outb(0x3ce, 0x0e); /* disable 256 color mode */ - outb(0x3cf, inb(0x3cf) & ~0x01); - outb(0xd00, 0xff); /* enable auto-centering */ - if (!(inb(0xd01) & 0x03)) { - outb(0x3d4, 0x33); - outb(0x3d5, inb(0x3d5) & ~0x90); - outb(0x3d4, 0x32); - outb(0x3d5, inb(0x3d5) | 0x04); - outw(0x3d4, 0x0250); - outw(0x3d4, 0x07ba); - outw(0x3d4, 0x0900); - outw(0x3d4, 0x15e7); - outw(0x3d4, 0x2a95); - } - outw(0x3d4, 0x34a0); - break; - - #if 0 /* Untested - probably doesn't work */ - case(MatroxVendor): - case(DiamondVendor): - puts("VGA Chip Vendor ID: "); - puthex(PCIVendor(slot)); - puts("\n"); - mdelay(1000); - #endif - }; - - outw(0x3C4, 0x0120); /* disable video */ - setTextRegs(VgaTextRegs); /* initial register setup */ - setTextCLUT(0); /* load color lookup table */ - loadFont(ISA_mem); /* load font */ - setTextRegs(VgaTextRegs); /* reload registers */ - outw(0x3C4, 0x0100); /* re-enable video */ - clearVideoMemory(); - - if (PCIVendor(slot) == S3Vendor) { - outb(0x3c2, 0x63); /* MISC */ - } /* endif */ - - #ifdef DEBUG - printslots(); - mdelay(5000); - #endif - - mdelay(1000); /* give time for the video monitor to come up */ - } - return (1); /* 'CRT' I/O supported */ -} - -/* - * Write to VGA Attribute registers. - */ -void -writeAttr(unsigned char index, unsigned char data, unsigned char videoOn) -{ - unsigned char v; - v = inb(0x3da); /* reset attr. address toggle */ - if (videoOn) - outb(0x3c0, (index & 0x1F) | 0x20); - else - outb(0x3c0, (index & 0x1F)); - outb(0x3c0, data); -} - -void -setTextRegs(struct VgaRegs *svp) -{ - int i; - - /* - * saved settings - */ - while( svp->io_port != ENDMK ) { - outb(svp->io_port, svp->io_index); - outb(svp->io_port+1, svp->io_value); - svp++; - } - - outb(0x3c2, 0x67); /* MISC */ - outb(0x3c6, 0xff); /* MASK */ - - for ( i = 0; i < 0x10; i++) - writeAttr(i, AC[i], 0); /* palette */ - writeAttr(0x10, 0x0c, 0); /* text mode */ - writeAttr(0x11, 0x00, 0); /* overscan color (border) */ - writeAttr(0x12, 0x0f, 0); /* plane enable */ - writeAttr(0x13, 0x08, 0); /* pixel panning */ - writeAttr(0x14, 0x00, 1); /* color select; video on */ -} - -void -setTextCLUT(int shift) -{ - int i; - - outb(0x3C6, 0xFF); - i = inb(0x3C7); - outb(0x3C8, 0); - i = inb(0x3C7); - - for ( i = 0; i < 256; i++) { - outb(0x3C9, TextCLUT[i].r << shift); - outb(0x3C9, TextCLUT[i].g << shift); - outb(0x3C9, TextCLUT[i].b << shift); - } -} - -void -loadFont(unsigned char *ISA_mem) -{ - int i, j; - unsigned char *font_page = (unsigned char *) &ISA_mem[0xA0000]; - - outb(0x3C2, 0x67); - /* - * Load font - */ - i = inb(0x3DA); /* Reset Attr toggle */ - - outb(0x3C0,0x30); - outb(0x3C0, 0x01); /* graphics mode */ - - outw(0x3C4, 0x0001); /* reset sequencer */ - outw(0x3C4, 0x0204); /* write to plane 2 */ - outw(0x3C4, 0x0406); /* enable plane graphics */ - outw(0x3C4, 0x0003); /* reset sequencer */ - outw(0x3CE, 0x0402); /* read plane 2 */ - outw(0x3CE, 0x0500); /* write mode 0, read mode 0 */ - outw(0x3CE, 0x0605); /* set graphics mode */ - - for (i = 0; i < sizeof(font); i += 16) { - for (j = 0; j < 16; j++) { - __asm__ volatile("eieio"); - font_page[(2*i)+j] = font[i+j]; - } - } -} - -static void -unlockS3(void) -{ - int s3_device_id; - outw(0x3d4, 0x3848); - outw(0x3d4, 0x39a5); - outb(0x3d4, 0x2d); - s3_device_id = inb(0x3d5) << 8; - outb(0x3d4, 0x2e); - s3_device_id |= inb(0x3d5); - - if (s3_device_id != 0x8812) { - /* From the S3 manual */ - outb(0x46E8, 0x10); /* Put into setup mode */ - outb(0x3C3, 0x10); - outb(0x102, 0x01); /* Enable registers */ - outb(0x46E8, 0x08); /* Enable video */ - outb(0x3C3, 0x08); - outb(0x4AE8, 0x00); - -#if 0 - outb(0x42E8, 0x80); /* Reset graphics engine? */ -#endif - - outb(0x3D4, 0x38); /* Unlock all registers */ - outb(0x3D5, 0x48); - outb(0x3D4, 0x39); - outb(0x3D5, 0xA5); - outb(0x3D4, 0x40); - outb(0x3D5, inb(0x3D5)|0x01); - outb(0x3D4, 0x33); - outb(0x3D5, inb(0x3D5)&~0x52); - outb(0x3D4, 0x35); - outb(0x3D5, inb(0x3D5)&~0x30); - outb(0x3D4, 0x3A); - outb(0x3D5, 0x00); - outb(0x3D4, 0x53); - outb(0x3D5, 0x00); - outb(0x3D4, 0x31); - outb(0x3D5, inb(0x3D5)&~0x4B); - outb(0x3D4, 0x58); - - outb(0x3D5, 0); - - outb(0x3D4, 0x54); - outb(0x3D5, 0x38); - outb(0x3D4, 0x60); - outb(0x3D5, 0x07); - outb(0x3D4, 0x61); - outb(0x3D5, 0x80); - outb(0x3D4, 0x62); - outb(0x3D5, 0xA1); - outb(0x3D4, 0x69); /* High order bits for cursor address */ - outb(0x3D5, 0); - - outb(0x3D4, 0x32); - outb(0x3D5, inb(0x3D5)&~0x10); - } else { - outw(0x3c4, 0x0806); /* IBM Portable 860 */ - outw(0x3c4, 0x1041); - outw(0x3c4, 0x1128); - outw(0x3d4, 0x4000); - outw(0x3d4, 0x3100); - outw(0x3d4, 0x3a05); - outw(0x3d4, 0x6688); - outw(0x3d4, 0x5800); /* disable linear addressing */ - outw(0x3d4, 0x4500); /* disable H/W cursor */ - outw(0x3c4, 0x5410); /* enable auto-centering */ - outw(0x3c4, 0x561f); - outw(0x3c4, 0x1b80); /* lock DCLK selection */ - outw(0x3d4, 0x3900); /* lock S3 registers */ - outw(0x3d4, 0x3800); - } /* endif */ -} - -/* - * cursor() sets an offset (0-1999) into the 80x25 text area. - */ -void -cursor(int x, int y) -{ - int pos = (y*cols)+x; - outb(0x3D4, 14); - outb(0x3D5, pos >> 8); - outb(0x3D4, 15); - outb(0x3D5, pos); -} - -void -clearVideoMemory(void) -{ - int i, j; - for (i = 0; i < lines; i++) { - for (j = 0; j < cols; j++) { - vidmem[((i*cols)+j)*2] = 0x20; /* fill with space character */ - vidmem[((i*cols)+j)*2+1] = 0x07; /* set bg & fg attributes */ - } - } -} - -/* ============ */ - - -#define NSLOTS 8 -#define NPCIREGS 5 - - -/* - should use devfunc number/indirect method to be totally safe on - all machines, this works for now on 3 slot Moto boxes -*/ - -struct PCI_ConfigInfo { - unsigned long * config_addr; - unsigned long regs[NPCIREGS]; -} PCI_slots [NSLOTS] = { - - { (unsigned long *)0x80808000, {0xDEADBEEF,} }, /* onboard */ - { (unsigned long *)0x80800800, {0xDEADBEEF,} }, /* onboard */ - { (unsigned long *)0x80801000, {0xDEADBEEF,} }, /* onboard */ - { (unsigned long *)0x80802000, {0xDEADBEEF,} }, /* onboard */ - { (unsigned long *)0x80804000, {0xDEADBEEF,} }, /* onboard */ - { (unsigned long *)0x80810000, {0xDEADBEEF,} }, /* slot A/1 */ - { (unsigned long *)0x80820000, {0xDEADBEEF,} }, /* slot B/2 */ - { (unsigned long *)0x80840000, {0xDEADBEEF,} } /* slot C/3 */ -}; - - - -/* - * The following code modifies the PCI Command register - * to enable memory and I/O accesses. - */ -void -unlockVideo(int slot) -{ - volatile unsigned char * ppci; - - ppci = (unsigned char * )PCI_slots[slot].config_addr; - ppci[4] = 0x0003; /* enable memory and I/O accesses */ - ppci[0x10] = 0x00000; /* turn off memory mapping */ - ppci[0x11] = 0x00000; /* mem_base = 0 */ - ppci[0x12] = 0x00000; - ppci[0x13] = 0x00000; - __asm__ volatile("eieio"); - - outb(0x3d4, 0x11); - outb(0x3d5, 0x0e); /* unlock CR0-CR7 */ -} - -long -SwapBytes(long lv) /* turn little endian into big indian long */ -{ - long t; - t = (lv&0x000000FF) << 24; - t |= (lv&0x0000FF00) << 8; - t |= (lv&0x00FF0000) >> 8; - t |= (lv&0xFF000000) >> 24; - return(t); -} - - -#define DEVID 0 -#define CMD 1 -#define CLASS 2 -#define MEMBASE 4 - -int -scanPCI(int start_slt) -{ - int slt, r; - struct PCI_ConfigInfo *pslot; - int theSlot = -1; - int highVgaSlot = 0; - - for ( slt = start_slt + 1; slt < NSLOTS; slt++) { - pslot = &PCI_slots[slt]; - for ( r = 0; r < NPCIREGS; r++) { - pslot->regs[r] = SwapBytes ( pslot->config_addr[r] ); - } - /* card in slot ? */ - if ( pslot->regs[DEVID] != 0xFFFFFFFF ) { - /* VGA ? */ - if ( ((pslot->regs[CLASS] & 0xFFFFFF00) == 0x03000000) || - ((pslot->regs[CLASS] & 0xFFFFFF00) == 0x00010000)) { - highVgaSlot = slt; - /* did firmware enable it ? */ - if ( (pslot->regs[CMD] & 0x03) ) { - theSlot = slt; - break; - } - } - } - } - - return ( theSlot ); -} - -/* return Vendor ID of card in the slot */ -static -int PCIVendor(int slotnum) { - struct PCI_ConfigInfo *pslot; - - pslot = &PCI_slots[slotnum]; - -return (pslot->regs[DEVID] & 0xFFFF); -} - -#ifdef DEBUG -static -void printslots(void) -{ - int i; -#if 0 - struct PCI_ConfigInfo *pslot; -#endif - for(i=0; i < NSLOTS; i++) { -#if 0 - pslot = &PCI_slots[i]; - printf("Slot: %d, Addr: %x, Vendor: %08x, Class: %08x\n", - i, pslot->config_addr, pslot->regs[0], pslot->regs[2]); -#else - puts("PCI Slot number: "); puthex(i); - puts(" Vendor ID: "); - puthex(PCIVendor(i)); puts("\n"); -#endif - } -} -#endif /* DEBUG */ diff --git a/arch/ppc/boot/of1275/Makefile b/arch/ppc/boot/of1275/Makefile deleted file mode 100644 index 0b979c004972..000000000000 --- a/arch/ppc/boot/of1275/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile of1275 stuff -# - -lib-y := claim.o enter.o exit.o finddevice.o getprop.o ofinit.o \ - ofstdio.o read.o release.o write.o map.o call_prom.o diff --git a/arch/ppc/boot/of1275/call_prom.c b/arch/ppc/boot/of1275/call_prom.c deleted file mode 100644 index 9479a3a2b8c7..000000000000 --- a/arch/ppc/boot/of1275/call_prom.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 1996-2005 Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" -#include - -int call_prom(const char *service, int nargs, int nret, ...) -{ - int i; - struct prom_args { - const char *service; - int nargs; - int nret; - unsigned int args[12]; - } args; - va_list list; - - args.service = service; - args.nargs = nargs; - args.nret = nret; - - va_start(list, nret); - for (i = 0; i < nargs; i++) - args.args[i] = va_arg(list, unsigned int); - va_end(list); - - for (i = 0; i < nret; i++) - args.args[nargs+i] = 0; - - if (of_prom_entry(&args) < 0) - return -1; - - return (nret > 0)? args.args[nargs]: 0; -} - -int call_prom_ret(const char *service, int nargs, int nret, - unsigned int *rets, ...) -{ - int i; - struct prom_args { - const char *service; - int nargs; - int nret; - unsigned int args[12]; - } args; - va_list list; - - args.service = service; - args.nargs = nargs; - args.nret = nret; - - va_start(list, rets); - for (i = 0; i < nargs; i++) - args.args[i] = va_arg(list, unsigned int); - va_end(list); - - for (i = 0; i < nret; i++) - args.args[nargs+i] = 0; - - if (of_prom_entry(&args) < 0) - return -1; - - if (rets != (void *) 0) - for (i = 1; i < nret; ++i) - rets[i-1] = args.args[nargs+i]; - - return (nret > 0)? args.args[nargs]: 0; -} diff --git a/arch/ppc/boot/of1275/claim.c b/arch/ppc/boot/of1275/claim.c deleted file mode 100644 index 1ed3aeeff8ae..000000000000 --- a/arch/ppc/boot/of1275/claim.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" -#include "nonstdio.h" - -/* - * Older OF's require that when claiming a specific range of addresses, - * we claim the physical space in the /memory node and the virtual - * space in the chosen mmu node, and then do a map operation to - * map virtual to physical. - */ -static int need_map = -1; -static ihandle chosen_mmu; -static phandle memory; - -/* returns true if s2 is a prefix of s1 */ -static int string_match(const char *s1, const char *s2) -{ - for (; *s2; ++s2) - if (*s1++ != *s2) - return 0; - return 1; -} - -static int check_of_version(void) -{ - phandle oprom, chosen; - char version[64]; - - oprom = finddevice("/openprom"); - if (oprom == OF_INVALID_HANDLE) - return 0; - if (getprop(oprom, "model", version, sizeof(version)) <= 0) - return 0; - version[sizeof(version)-1] = 0; - printf("OF version = '%s'\n", version); - if (!string_match(version, "Open Firmware, 1.") - && !string_match(version, "FirmWorks,3.")) - return 0; - chosen = finddevice("/chosen"); - if (chosen == OF_INVALID_HANDLE) { - chosen = finddevice("/chosen@0"); - if (chosen == OF_INVALID_HANDLE) { - printf("no chosen\n"); - return 0; - } - } - if (getprop(chosen, "mmu", &chosen_mmu, sizeof(chosen_mmu)) <= 0) { - printf("no mmu\n"); - return 0; - } - memory = (ihandle) call_prom("open", 1, 1, "/memory"); - if (memory == OF_INVALID_HANDLE) { - memory = (ihandle) call_prom("open", 1, 1, "/memory@0"); - if (memory == OF_INVALID_HANDLE) { - printf("no memory node\n"); - return 0; - } - } - printf("old OF detected\n"); - return 1; -} - -void *claim(unsigned int virt, unsigned int size, unsigned int align) -{ - int ret; - unsigned int result; - - if (need_map < 0) - need_map = check_of_version(); - if (align || !need_map) - return (void *) call_prom("claim", 3, 1, virt, size, align); - - ret = call_prom_ret("call-method", 5, 2, &result, "claim", memory, - align, size, virt); - if (ret != 0 || result == -1) - return (void *) -1; - ret = call_prom_ret("call-method", 5, 2, &result, "claim", chosen_mmu, - align, size, virt); - /* 0x12 == coherent + read/write */ - ret = call_prom("call-method", 6, 1, "map", chosen_mmu, - 0x12, size, virt, virt); - return virt; -} diff --git a/arch/ppc/boot/of1275/enter.c b/arch/ppc/boot/of1275/enter.c deleted file mode 100644 index abe87a8fe2db..000000000000 --- a/arch/ppc/boot/of1275/enter.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" - -void -enter(void) -{ - struct prom_args { - char *service; - } args; - - args.service = "enter"; - (*of_prom_entry)(&args); -} diff --git a/arch/ppc/boot/of1275/exit.c b/arch/ppc/boot/of1275/exit.c deleted file mode 100644 index b9f89b6a8b45..000000000000 --- a/arch/ppc/boot/of1275/exit.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" - -void -exit(void) -{ - struct prom_args { - char *service; - } args; - - for (;;) { - args.service = "exit"; - (*of_prom_entry)(&args); - } -} diff --git a/arch/ppc/boot/of1275/finddevice.c b/arch/ppc/boot/of1275/finddevice.c deleted file mode 100644 index 0dcb1201b772..000000000000 --- a/arch/ppc/boot/of1275/finddevice.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" - -phandle finddevice(const char *name) -{ - return (phandle) call_prom("finddevice", 1, 1, name); -} diff --git a/arch/ppc/boot/of1275/getprop.c b/arch/ppc/boot/of1275/getprop.c deleted file mode 100644 index 0cf75f035e4e..000000000000 --- a/arch/ppc/boot/of1275/getprop.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" - -int -getprop(phandle node, const char *name, void *buf, int buflen) -{ - struct prom_args { - char *service; - int nargs; - int nret; - phandle node; - const char *name; - void *buf; - int buflen; - int size; - } args; - - args.service = "getprop"; - args.nargs = 4; - args.nret = 1; - args.node = node; - args.name = name; - args.buf = buf; - args.buflen = buflen; - args.size = -1; - (*of_prom_entry)(&args); - return args.size; -} diff --git a/arch/ppc/boot/of1275/map.c b/arch/ppc/boot/of1275/map.c deleted file mode 100644 index 443256c6f6d6..000000000000 --- a/arch/ppc/boot/of1275/map.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" -#include "nonstdio.h" - -extern ihandle of_prom_mmu; - -int -map(unsigned int phys, unsigned int virt, unsigned int size) -{ - struct prom_args { - char *service; - int nargs; - int nret; - char *method; - ihandle mmu_ihandle; - int misc; - unsigned int size; - unsigned int virt; - unsigned int phys; - int ret0; - } args; - - if (of_prom_mmu == 0) { - printf("map() called, no MMU found\n"); - return -1; - } - args.service = "call-method"; - args.nargs = 6; - args.nret = 1; - args.method = "map"; - args.mmu_ihandle = of_prom_mmu; - args.misc = 0; - args.phys = phys; - args.virt = virt; - args.size = size; - (*of_prom_entry)(&args); - - return (int)args.ret0; -} diff --git a/arch/ppc/boot/of1275/ofinit.c b/arch/ppc/boot/of1275/ofinit.c deleted file mode 100644 index 0ee8af7639e9..000000000000 --- a/arch/ppc/boot/of1275/ofinit.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" - -prom_entry of_prom_entry; -ihandle of_prom_mmu; - -void -ofinit(prom_entry prom_ptr) -{ - phandle chosen; - - of_prom_entry = prom_ptr; - - if ((chosen = finddevice("/chosen")) == OF_INVALID_HANDLE) - return; - if (getprop(chosen, "mmu", &of_prom_mmu, sizeof(ihandle)) != 4) - return; -} diff --git a/arch/ppc/boot/of1275/ofstdio.c b/arch/ppc/boot/of1275/ofstdio.c deleted file mode 100644 index 10abbe32b31f..000000000000 --- a/arch/ppc/boot/of1275/ofstdio.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" - -int -ofstdio(ihandle *stdin, ihandle *stdout, ihandle *stderr) -{ - ihandle in, out; - phandle chosen; - - if ((chosen = finddevice("/chosen")) == OF_INVALID_HANDLE) - goto err; - if (getprop(chosen, "stdout", &out, sizeof(out)) != 4) - goto err; - if (getprop(chosen, "stdin", &in, sizeof(in)) != 4) - goto err; - - *stdin = in; - *stdout = out; - *stderr = out; - return 0; -err: - return -1; -} diff --git a/arch/ppc/boot/of1275/read.c b/arch/ppc/boot/of1275/read.c deleted file mode 100644 index 122813649fce..000000000000 --- a/arch/ppc/boot/of1275/read.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" - -int -read(ihandle instance, void *buf, int buflen) -{ - struct prom_args { - char *service; - int nargs; - int nret; - ihandle instance; - void *buf; - int buflen; - int actual; - } args; - - args.service = "read"; - args.nargs = 3; - args.nret = 1; - args.instance = instance; - args.buf = buf; - args.buflen = buflen; - args.actual = -1; - (*of_prom_entry)(&args); - return args.actual; -} diff --git a/arch/ppc/boot/of1275/release.c b/arch/ppc/boot/of1275/release.c deleted file mode 100644 index 28032d37145d..000000000000 --- a/arch/ppc/boot/of1275/release.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" - -void -release(void *virt, unsigned int size) -{ - struct prom_args { - char *service; - int nargs; - int nret; - void *virt; - unsigned int size; - } args; - - args.service = "release"; - args.nargs = 2; - args.nret = 0; - args.virt = virt; - args.size = size; - (*of_prom_entry)(&args); -} diff --git a/arch/ppc/boot/of1275/write.c b/arch/ppc/boot/of1275/write.c deleted file mode 100644 index 7361b9b2fca5..000000000000 --- a/arch/ppc/boot/of1275/write.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) Paul Mackerras 1997. - * Copyright (C) Leigh Brown 2002. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include "of1275.h" - -int -write(ihandle instance, void *buf, int buflen) -{ - struct prom_args { - char *service; - int nargs; - int nret; - ihandle instance; - void *buf; - int buflen; - int actual; - } args; - - args.service = "write"; - args.nargs = 3; - args.nret = 1; - args.instance = instance; - args.buf = buf; - args.buflen = buflen; - args.actual = -1; - (*of_prom_entry)(&args); - return args.actual; -} diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile deleted file mode 100644 index 5b877792d14f..000000000000 --- a/arch/ppc/boot/simple/Makefile +++ /dev/null @@ -1,277 +0,0 @@ -# This is far from simple, but I couldn't think of a good name. This is -# for making the 'zImage' or 'zImage.initrd' on a number of targets. -# -# Author: Tom Rini -# -# Notes: -# (1) For machines that do not want to use the ELF image directly (including -# stripping just the ELF header off), they must set the variables -# zimage-$(CONFIG_MACHINE) and zimagerd-$(CONFIG_MACHINE) to the target -# that produces the desired image and they must set end-$(CONFIG_MACHINE) -# to what will be suffixed to the image filename. -# (2) Regardless of (1), to have the resulting image be something other -# than 'zImage.elf', set end-$(CONFIG_MACHINE) to be the suffix used for -# the zImage, znetboot, and znetbootrd targets. -# (3) For machine targets which use the mktree program, you can optionally -# set entrypoint-$(CONFIG_MACHINE) to the location which the image should be -# loaded at. The optimal setting for entrypoint-$(CONFIG_MACHINE) is the link -# address. -# (4) It is advisable to pass in the memory size using BI_MEMSIZE and -# get_mem_size(), which is memory controller dependent. Add in the correct -# XXX_memory.o file for this to work, as well as editing the -# misc-$(CONFIG_MACHINE) variable. - -boot := arch/ppc/boot -common := $(boot)/common -utils := $(boot)/utils -bootlib := $(boot)/lib -images := $(boot)/images -of1275 := $(boot)/of1275 -tftpboot := /tftpboot - -# Normally, we use the 'misc.c' file for decompress_kernel and -# whatnot. Sometimes we need to override this however. -misc-y := misc.o - -# Normally, we have our images end in .elf, but something we want to -# change this. -end-y := elf - -# Additionally, we normally don't need to mess with the L2 / L3 caches -# if present on 'classic' PPC. -cacheflag-y := -DCLEAR_CACHES="" -# This file will flush / disable the L2, and L3 if present. -clear_L2_L3 := $(srctree)/$(boot)/simple/clear.S - -# -# See arch/ppc/kconfig and arch/ppc/platforms/Kconfig -# for definition of what platform each config option refer to. -#---------------------------------------------------------------------------- - zimage-$(CONFIG_CPCI690) := zImage-STRIPELF -zimageinitrd-$(CONFIG_CPCI690) := zImage.initrd-STRIPELF - extra.o-$(CONFIG_CPCI690) := misc-cpci690.o - end-$(CONFIG_CPCI690) := cpci690 - cacheflag-$(CONFIG_CPCI690) := -include $(clear_L2_L3) - - zimage-$(CONFIG_IBM_OPENBIOS) := zImage-TREE -zimageinitrd-$(CONFIG_IBM_OPENBIOS) := zImage.initrd-TREE - end-$(CONFIG_IBM_OPENBIOS) := treeboot - misc-$(CONFIG_IBM_OPENBIOS) := misc-embedded.o - - end-$(CONFIG_EMBEDDEDBOOT) := embedded - misc-$(CONFIG_EMBEDDEDBOOT) := misc-embedded.o - - zimage-$(CONFIG_BAMBOO) := zImage-TREE -zimageinitrd-$(CONFIG_BAMBOO) := zImage.initrd-TREE - end-$(CONFIG_BAMBOO) := bamboo - entrypoint-$(CONFIG_BAMBOO) := 0x01000000 - extra.o-$(CONFIG_BAMBOO) := pibs.o - - zimage-$(CONFIG_BUBINGA) := zImage-TREE -zimageinitrd-$(CONFIG_BUBINGA) := zImage.initrd-TREE - end-$(CONFIG_BUBINGA) := bubinga - entrypoint-$(CONFIG_BUBINGA) := 0x01000000 - extra.o-$(CONFIG_BUBINGA) := openbios.o - - zimage-$(CONFIG_EBONY) := zImage-TREE -zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE - end-$(CONFIG_EBONY) := ebony - entrypoint-$(CONFIG_EBONY) := 0x01000000 - extra.o-$(CONFIG_EBONY) := openbios.o - - zimage-$(CONFIG_LUAN) := zImage-TREE -zimageinitrd-$(CONFIG_LUAN) := zImage.initrd-TREE - end-$(CONFIG_LUAN) := luan - entrypoint-$(CONFIG_LUAN) := 0x01000000 - extra.o-$(CONFIG_LUAN) := pibs.o - - zimage-$(CONFIG_YUCCA) := zImage-TREE -zimageinitrd-$(CONFIG_YUCCA) := zImage.initrd-TREE - end-$(CONFIG_YUCCA) := yucca - entrypoint-$(CONFIG_YUCCA) := 0x01000000 - extra.o-$(CONFIG_YUCCA) := pibs.o - - zimage-$(CONFIG_OCOTEA) := zImage-TREE -zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE - end-$(CONFIG_OCOTEA) := ocotea - entrypoint-$(CONFIG_OCOTEA) := 0x01000000 - extra.o-$(CONFIG_OCOTEA) := pibs.o - - zimage-$(CONFIG_SYCAMORE) := zImage-TREE -zimageinitrd-$(CONFIG_SYCAMORE) := zImage.initrd-TREE - end-$(CONFIG_SYCAMORE) := sycamore - entrypoint-$(CONFIG_SYCAMORE) := 0x01000000 - extra.o-$(CONFIG_SYCAMORE) := openbios.o - - zimage-$(CONFIG_WALNUT) := zImage-TREE -zimageinitrd-$(CONFIG_WALNUT) := zImage.initrd-TREE - end-$(CONFIG_WALNUT) := walnut - entrypoint-$(CONFIG_WALNUT) := 0x01000000 - extra.o-$(CONFIG_WALNUT) := openbios.o - - extra.o-$(CONFIG_EV64260) := misc-ev64260.o - end-$(CONFIG_EV64260) := ev64260 - cacheflag-$(CONFIG_EV64260) := -include $(clear_L2_L3) - - extra.o-$(CONFIG_CHESTNUT) := misc-chestnut.o - end-$(CONFIG_CHESTNUT) := chestnut - - extra.o-$(CONFIG_KATANA) := misc-katana.o - end-$(CONFIG_KATANA) := katana - cacheflag-$(CONFIG_KATANA) := -include $(clear_L2_L3) - - extra.o-$(CONFIG_RADSTONE_PPC7D) := misc-radstone_ppc7d.o - end-$(CONFIG_RADSTONE_PPC7D) := radstone_ppc7d - cacheflag-$(CONFIG_RADSTONE_PPC7D) := -include $(clear_L2_L3) - - extra.o-$(CONFIG_EV64360) := misc-ev64360.o - end-$(CONFIG_EV64360) := ev64360 - cacheflag-$(CONFIG_EV64360) := -include $(clear_L2_L3) - -# kconfig 'feature', only one of these will ever be 'y' at a time. -# The rest will be unset. -motorola := $(CONFIG_MVME5100)$(CONFIG_PRPMC750) \ -$(CONFIG_PRPMC800)$(CONFIG_LOPEC)$(CONFIG_PPLUS) -motorola := $(strip $(motorola)) - - zimage-$(motorola) := zImage-PPLUS -zimageinitrd-$(motorola) := zImage.initrd-PPLUS - end-$(motorola) := pplus - -# Overrides previous assingment - extra.o-$(CONFIG_PPLUS) := prepmap.o - extra.o-$(CONFIG_LOPEC) := mpc10x_memory.o - -# Really only valid if CONFIG_6xx=y - zimage-$(CONFIG_PPC_PREP) := zImage-PPLUS -zimageinitrd-$(CONFIG_PPC_PREP) := zImage.initrd-PPLUS -ifeq ($(CONFIG_6xx),y) - extra.o-$(CONFIG_PPC_PREP) := prepmap.o - misc-$(CONFIG_PPC_PREP) += misc-prep.o mpc10x_memory.o -endif - end-$(CONFIG_PPC_PREP) := prep - - end-$(CONFIG_SANDPOINT) := sandpoint - cacheflag-$(CONFIG_SANDPOINT) := -include $(clear_L2_L3) - - zimage-$(CONFIG_SPRUCE) := zImage-TREE -zimageinitrd-$(CONFIG_SPRUCE) := zImage.initrd-TREE - end-$(CONFIG_SPRUCE) := spruce - entrypoint-$(CONFIG_SPRUCE) := 0x00800000 - misc-$(CONFIG_SPRUCE) += misc-spruce.o - - zimage-$(CONFIG_LITE5200) := zImage-STRIPELF -zimageinitrd-$(CONFIG_LITE5200) := zImage.initrd-STRIPELF - end-$(CONFIG_LITE5200) := lite5200 - cacheflag-$(CONFIG_LITE5200) := -include $(clear_L2_L3) - - -# SMP images should have a '.smp' suffix. - end-$(CONFIG_SMP) := $(end-y).smp - -# This is a treeboot that needs init functions until the -# boot rom is sorted out (i.e. this is short lived) -EXTRA_AFLAGS := $(extra-aflags-y) -# head.o needs to get the cacheflags defined. -AFLAGS_head.o += $(cacheflag-y) - -# Linker args. This specifies where the image will be run at. -LD_ARGS := -T $(srctree)/$(boot)/ld.script \ - -Ttext $(CONFIG_BOOT_LOAD) -Bstatic -OBJCOPY_ARGS := -O elf32-powerpc - -# head.o and relocate.o must be at the start. -boot-y := head.o relocate.o $(extra.o-y) $(misc-y) -boot-$(CONFIG_REDWOOD_5) += embed_config.o -boot-$(CONFIG_REDWOOD_6) += embed_config.o -boot-$(CONFIG_8xx) += embed_config.o -boot-$(CONFIG_8260) += embed_config.o -boot-$(CONFIG_EP405) += embed_config.o -boot-$(CONFIG_XILINX_ML300) += embed_config.o -boot-$(CONFIG_XILINX_ML403) += embed_config.o -boot-$(CONFIG_BSEIP) += iic.o -boot-$(CONFIG_MBX) += iic.o pci.o qspan_pci.o -boot-$(CONFIG_MV64X60) += misc-mv64x60.o -boot-$(CONFIG_RPXCLASSIC) += iic.o pci.o qspan_pci.o -boot-$(CONFIG_RPXLITE) += iic.o -# Different boards need different serial implementations. -ifeq ($(CONFIG_SERIAL_CPM_CONSOLE),y) -boot-$(CONFIG_8xx) += m8xx_tty.o -boot-$(CONFIG_8260) += m8260_tty.o -endif -boot-$(CONFIG_SERIAL_MPC52xx_CONSOLE) += mpc52xx_tty.o -boot-$(CONFIG_SERIAL_MPSC_CONSOLE) += mv64x60_tty.o -boot-$(CONFIG_SERIAL_UARTLITE_CONSOLE) += uartlite_tty.o - -LIBS := $(common)/lib.a $(bootlib)/lib.a -ifeq ($(CONFIG_PPC_PREP),y) -LIBS += $(of1275)/lib.a -endif - -OBJS := $(addprefix $(obj)/,$(boot-y)) - -# Tools -MKBUGBOOT := $(utils)/mkbugboot -MKPREP := $(utils)/mkprep -MKTREE := $(utils)/mktree - -targets := dummy.o - -$(obj)/zvmlinux: $(OBJS) $(LIBS) $(srctree)/$(boot)/ld.script \ - $(images)/vmlinux.gz $(obj)/dummy.o - $(OBJCOPY) $(OBJCOPY_ARGS) \ - --add-section=.image=$(images)/vmlinux.gz \ - --set-section-flags=.image=contents,alloc,load,readonly,data \ - $(obj)/dummy.o $(obj)/image.o - $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/image.o $(LIBS) - $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab \ - -R .stabstr -R .ramdisk - -$(obj)/zvmlinux.initrd: $(OBJS) $(LIBS) $(srctree)/$(boot)/ld.script \ - $(images)/vmlinux.gz $(obj)/dummy.o - $(OBJCOPY) $(OBJCOPY_ARGS) \ - --add-section=.ramdisk=$(images)/ramdisk.image.gz \ - --set-section-flags=.ramdisk=contents,alloc,load,readonly,data \ - --add-section=.image=$(images)/vmlinux.gz \ - --set-section-flags=.image=contents,alloc,load,readonly,data \ - $(obj)/dummy.o $(obj)/image.o - $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/image.o $(LIBS) - $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab \ - -R .stabstr - -# Sort-of dummy rules, that let us format the image we want. -zImage: $(images)/$(zimage-y) $(obj)/zvmlinux - cp -f $(obj)/zvmlinux $(images)/zImage.elf - rm -f $(obj)/zvmlinux - -zImage.initrd: $(images)/$(zimageinitrd-y) $(obj)/zvmlinux.initrd - cp -f $(obj)/zvmlinux.initrd $(images)/zImage.initrd.elf - rm -f $(obj)/zvmlinux.initrd - -znetboot: zImage - cp $(images)/zImage.$(end-y) $(tftpboot)/zImage.$(end-y) - -znetboot.initrd: zImage.initrd - cp $(images)/zImage.initrd.$(end-y) $(tftpboot)/zImage.initrd.$(end-y) - -$(images)/zImage-STRIPELF: $(obj)/zvmlinux - dd if=$(obj)/zvmlinux of=$(images)/zImage.$(end-y) skip=64 bs=1k - -$(images)/zImage.initrd-STRIPELF: $(obj)/zvmlinux.initrd - dd if=$(obj)/zvmlinux.initrd of=$(images)/zImage.initrd.$(end-y) \ - skip=64 bs=1k - -$(images)/zImage-TREE: $(obj)/zvmlinux $(MKTREE) - $(MKTREE) $(obj)/zvmlinux $(images)/zImage.$(end-y) $(entrypoint-y) - -$(images)/zImage.initrd-TREE: $(obj)/zvmlinux.initrd $(MKTREE) - $(MKTREE) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y) \ - $(entrypoint-y) - -$(images)/zImage-PPLUS: $(obj)/zvmlinux $(MKPREP) $(MKBUGBOOT) - $(MKPREP) -pbp $(obj)/zvmlinux $(images)/zImage.$(end-y) - $(MKBUGBOOT) $(obj)/zvmlinux $(images)/zImage.bugboot - -$(images)/zImage.initrd-PPLUS: $(obj)/zvmlinux.initrd $(MKPREP) $(MKBUGBOOT) - $(MKPREP) -pbp $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y) - $(MKBUGBOOT) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.bugboot diff --git a/arch/ppc/boot/simple/chrpmap.c b/arch/ppc/boot/simple/chrpmap.c deleted file mode 100644 index 14d9e05d98bb..000000000000 --- a/arch/ppc/boot/simple/chrpmap.c +++ /dev/null @@ -1,12 +0,0 @@ -/* - * 2004 (C) IBM. This file is licensed under the terms of the GNU General - * Public License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - -void board_isa_init(void) -{ - ISA_init(0xFE000000); -} diff --git a/arch/ppc/boot/simple/clear.S b/arch/ppc/boot/simple/clear.S deleted file mode 100644 index 95c5647a0f51..000000000000 --- a/arch/ppc/boot/simple/clear.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Code to call _setup_L2CR to flus, invalidate and disable the L2, - * and if present, do the same to the L3. - */ - -#define CLEAR_CACHES \ - bl _setup_L2CR; \ - \ - /* If 745x, turn off L3CR as well */ \ - mfspr r8,SPRN_PVR; \ - srwi r8,r8,16; \ - \ - cmpli cr0,r8,0x8000; /* 7450 */ \ - cmpli cr1,r8,0x8001; /* 7455 */ \ - cmpli cr2,r8,0x8002; /* 7457 */ \ - /* Now test if any are true. */ \ - cror 4*cr0+eq,4*cr0+eq,4*cr1+eq; \ - cror 4*cr0+eq,4*cr0+eq,4*cr2+eq; \ - beql _setup_L3CR diff --git a/arch/ppc/boot/simple/cpc700_memory.c b/arch/ppc/boot/simple/cpc700_memory.c deleted file mode 100644 index d75420a45a59..000000000000 --- a/arch/ppc/boot/simple/cpc700_memory.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Find memory based upon settings in the CPC700 bridge - * - * Author: Dan Cox - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include "cpc700.h" - -unsigned long -cpc700_get_mem_size(void) -{ - int i; - unsigned long len, amt; - - /* Start at MB1EA, since MB0EA will most likely be the ending address - for ROM space. */ - for(len = 0, i = CPC700_MB1EA; i <= CPC700_MB4EA; i+=4) { - amt = cpc700_read_memreg(i); - if (amt == 0) - break; - len = amt; - } - - return len; -} - - diff --git a/arch/ppc/boot/simple/dummy.c b/arch/ppc/boot/simple/dummy.c deleted file mode 100644 index 31dbf45bf99c..000000000000 --- a/arch/ppc/boot/simple/dummy.c +++ /dev/null @@ -1,4 +0,0 @@ -int main(void) -{ - return 0; -} diff --git a/arch/ppc/boot/simple/embed_config.c b/arch/ppc/boot/simple/embed_config.c deleted file mode 100644 index 3b46792d7b8b..000000000000 --- a/arch/ppc/boot/simple/embed_config.c +++ /dev/null @@ -1,938 +0,0 @@ -/* Board specific functions for those embedded 8xx boards that do - * not have boot monitor support for board information. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#ifdef CONFIG_8xx -#include -#endif -#ifdef CONFIG_8260 -#include -#include -#endif -#ifdef CONFIG_40x -#include -#endif -#ifdef CONFIG_XILINX_VIRTEX -#include -#endif -extern unsigned long timebase_period_ns; - -/* For those boards that don't provide one. -*/ -#if !defined(CONFIG_MBX) -static bd_t bdinfo; -#endif - -/* IIC functions. - * These are just the basic master read/write operations so we can - * examine serial EEPROM. - */ -extern void iic_read(uint devaddr, u_char *buf, uint offset, uint count); - -/* Supply a default Ethernet address for those eval boards that don't - * ship with one. This is an address from the MBX board I have, so - * it is unlikely you will find it on your network. - */ -static ushort def_enet_addr[] = { 0x0800, 0x3e26, 0x1559 }; - -#if defined(CONFIG_MBX) - -/* The MBX hands us a pretty much ready to go board descriptor. This - * is where the idea started in the first place. - */ -void -embed_config(bd_t **bdp) -{ - u_char *mp; - u_char eebuf[128]; - int i = 8; - bd_t *bd; - - bd = *bdp; - - /* Read the first 128 bytes of the EEPROM. There is more, - * but this is all we need. - */ - iic_read(0xa4, eebuf, 0, 128); - - /* All we are looking for is the Ethernet MAC address. The - * first 8 bytes are 'MOTOROLA', so check for part of that. - * Next, the VPD describes a MAC 'packet' as being of type 08 - * and size 06. So we look for that and the MAC must follow. - * If there are more than one, we still only care about the first. - * If it's there, assume we have a valid MAC address. If not, - * grab our default one. - */ - if ((*(uint *)eebuf) == 0x4d4f544f) { - while (i < 127 && !(eebuf[i] == 0x08 && eebuf[i + 1] == 0x06)) - i += eebuf[i + 1] + 2; /* skip this packet */ - - if (i == 127) /* Couldn't find. */ - mp = (u_char *)def_enet_addr; - else - mp = &eebuf[i + 2]; - } - else - mp = (u_char *)def_enet_addr; - - for (i=0; i<6; i++) - bd->bi_enetaddr[i] = *mp++; - - /* The boot rom passes these to us in MHz. Linux now expects - * them to be in Hz. - */ - bd->bi_intfreq *= 1000000; - bd->bi_busfreq *= 1000000; - - /* Stuff a baud rate here as well. - */ - bd->bi_baudrate = 9600; -} -#endif /* CONFIG_MBX */ - -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || \ - defined(CONFIG_RPX8260) || defined(CONFIG_EP405) -/* Helper functions for Embedded Planet boards. -*/ -/* Because I didn't find anything that would do this....... -*/ -u_char -aschex_to_byte(u_char *cp) -{ - u_char byte, c; - - c = *cp++; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else - c -= '0'; - - byte = c * 16; - - c = *cp; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else - c -= '0'; - - byte += c; - - return(byte); -} - -static void -rpx_eth(bd_t *bd, u_char *cp) -{ - int i; - - for (i=0; i<6; i++) { - bd->bi_enetaddr[i] = aschex_to_byte(cp); - cp += 2; - } -} - -#ifdef CONFIG_RPX8260 -static uint -rpx_baseten(u_char *cp) -{ - uint retval; - - retval = 0; - - while (*cp != '\n') { - retval *= 10; - retval += (*cp) - '0'; - cp++; - } - return(retval); -} -#endif - -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) -static void -rpx_brate(bd_t *bd, u_char *cp) -{ - uint rate; - - rate = 0; - - while (*cp != '\n') { - rate *= 10; - rate += (*cp) - '0'; - cp++; - } - - bd->bi_baudrate = rate * 100; -} - -static void -rpx_cpuspeed(bd_t *bd, u_char *cp) -{ - uint num, den; - - num = den = 0; - - while (*cp != '\n') { - num *= 10; - num += (*cp) - '0'; - cp++; - if (*cp == '/') { - cp++; - den = (*cp) - '0'; - break; - } - } - - /* I don't know why the RPX just can't state the actual - * CPU speed..... - */ - if (den) { - num /= den; - num *= den; - } - bd->bi_intfreq = bd->bi_busfreq = num * 1000000; - - /* The 8xx can only run a maximum 50 MHz bus speed (until - * Motorola changes this :-). Greater than 50 MHz parts - * run internal/2 for bus speed. - */ - if (num > 50) - bd->bi_busfreq /= 2; -} -#endif - -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_EP405) -static void -rpx_memsize(bd_t *bd, u_char *cp) -{ - uint size; - - size = 0; - - while (*cp != '\n') { - size *= 10; - size += (*cp) - '0'; - cp++; - } - - bd->bi_memsize = size * 1024 * 1024; -} -#endif /* LITE || CLASSIC || EP405 */ -#if defined(CONFIG_EP405) -static void -rpx_nvramsize(bd_t *bd, u_char *cp) -{ - uint size; - - size = 0; - - while (*cp != '\n') { - size *= 10; - size += (*cp) - '0'; - cp++; - } - - bd->bi_nvramsize = size * 1024; -} -#endif /* CONFIG_EP405 */ - -#endif /* Embedded Planet boards */ - -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) - -/* Read the EEPROM on the RPX-Lite board. -*/ -void -embed_config(bd_t **bdp) -{ - u_char eebuf[256], *cp; - bd_t *bd; - - /* Read the first 256 bytes of the EEPROM. I think this - * is really all there is, and I hope if it gets bigger the - * info we want is still up front. - */ - bd = &bdinfo; - *bdp = bd; - -#if 1 - iic_read(0xa8, eebuf, 0, 128); - iic_read(0xa8, &eebuf[128], 128, 128); - - /* We look for two things, the Ethernet address and the - * serial baud rate. The records are separated by - * newlines. - */ - cp = eebuf; - for (;;) { - if (*cp == 'E') { - cp++; - if (*cp == 'A') { - cp += 2; - rpx_eth(bd, cp); - } - } - if (*cp == 'S') { - cp++; - if (*cp == 'B') { - cp += 2; - rpx_brate(bd, cp); - } - } - if (*cp == 'D') { - cp++; - if (*cp == '1') { - cp += 2; - rpx_memsize(bd, cp); - } - } - if (*cp == 'H') { - cp++; - if (*cp == 'Z') { - cp += 2; - rpx_cpuspeed(bd, cp); - } - } - - /* Scan to the end of the record. - */ - while ((*cp != '\n') && (*cp != 0xff)) - cp++; - - /* If the next character is a 0 or ff, we are done. - */ - cp++; - if ((*cp == 0) || (*cp == 0xff)) - break; - } - bd->bi_memstart = 0; -#else - /* For boards without initialized EEPROM. - */ - bd->bi_memstart = 0; - bd->bi_memsize = (8 * 1024 * 1024); - bd->bi_intfreq = 48000000; - bd->bi_busfreq = 48000000; - bd->bi_baudrate = 9600; -#endif -} -#endif /* RPXLITE || RPXCLASSIC */ - -#ifdef CONFIG_BSEIP -/* Build a board information structure for the BSE ip-Engine. - * There is more to come since we will add some environment - * variables and a function to read them. - */ -void -embed_config(bd_t **bdp) -{ - u_char *cp; - int i; - bd_t *bd; - - bd = &bdinfo; - *bdp = bd; - - /* Baud rate and processor speed will eventually come - * from the environment variables. - */ - bd->bi_baudrate = 9600; - - /* Get the Ethernet station address from the Flash ROM. - */ - cp = (u_char *)0xfe003ffa; - for (i=0; i<6; i++) { - bd->bi_enetaddr[i] = *cp++; - } - - /* The rest of this should come from the environment as well. - */ - bd->bi_memstart = 0; - bd->bi_memsize = (16 * 1024 * 1024); - bd->bi_intfreq = 48000000; - bd->bi_busfreq = 48000000; -} -#endif /* BSEIP */ - -#ifdef CONFIG_FADS -/* Build a board information structure for the FADS. - */ -void -embed_config(bd_t **bdp) -{ - u_char *cp; - int i; - bd_t *bd; - - bd = &bdinfo; - *bdp = bd; - - /* Just fill in some known values. - */ - bd->bi_baudrate = 9600; - - /* Use default enet. - */ - cp = (u_char *)def_enet_addr; - for (i=0; i<6; i++) { - bd->bi_enetaddr[i] = *cp++; - } - - bd->bi_memstart = 0; - bd->bi_memsize = (8 * 1024 * 1024); - bd->bi_intfreq = 40000000; - bd->bi_busfreq = 40000000; -} -#endif /* FADS */ - -#ifdef CONFIG_8260 -/* Compute 8260 clock values if the rom doesn't provide them. - */ -static unsigned char bus2core_8260[] = { -/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ - 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, 2, - 6, 5, 13, 2, 14, 4, 15, 2, 3, 11, 8, 10, 16, 12, 7, 2, -}; - -static void -clk_8260(bd_t *bd) -{ - uint scmr, vco_out, clkin; - uint plldf, pllmf, corecnf; - volatile cpm2_map_t *ip; - - ip = (cpm2_map_t *)CPM_MAP_ADDR; - scmr = ip->im_clkrst.car_scmr; - - /* The clkin is always bus frequency. - */ - clkin = bd->bi_busfreq; - - /* Collect the bits from the scmr. - */ - plldf = (scmr >> 12) & 1; - pllmf = scmr & 0xfff; - corecnf = (scmr >> 24) &0x1f; - - /* This is arithmetic from the 8260 manual. - */ - vco_out = clkin / (plldf + 1); - vco_out *= 2 * (pllmf + 1); - bd->bi_vco = vco_out; /* Save for later */ - - bd->bi_cpmfreq = vco_out / 2; /* CPM Freq, in MHz */ - bd->bi_intfreq = bd->bi_busfreq * bus2core_8260[corecnf] / 2; - - /* Set Baud rate divisor. The power up default is divide by 16, - * but we set it again here in case it was changed. - */ - ip->im_clkrst.car_sccr = 1; /* DIV 16 BRG */ - bd->bi_brgfreq = vco_out / 16; -} - -static unsigned char bus2core_8280[] = { -/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ - 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, 2, - 6, 5, 13, 2, 14, 2, 15, 2, 3, 2, 2, 2, 16, 2, 2, 2, -}; - -static void -clk_8280(bd_t *bd) -{ - uint scmr, main_clk, clkin; - uint pllmf, corecnf; - volatile cpm2_map_t *ip; - - ip = (cpm2_map_t *)CPM_MAP_ADDR; - scmr = ip->im_clkrst.car_scmr; - - /* The clkin is always bus frequency. - */ - clkin = bd->bi_busfreq; - - /* Collect the bits from the scmr. - */ - pllmf = scmr & 0xf; - corecnf = (scmr >> 24) & 0x1f; - - /* This is arithmetic from the 8280 manual. - */ - main_clk = clkin * (pllmf + 1); - - bd->bi_cpmfreq = main_clk / 2; /* CPM Freq, in MHz */ - bd->bi_intfreq = bd->bi_busfreq * bus2core_8280[corecnf] / 2; - - /* Set Baud rate divisor. The power up default is divide by 16, - * but we set it again here in case it was changed. - */ - ip->im_clkrst.car_sccr = (ip->im_clkrst.car_sccr & 0x3) | 0x1; - bd->bi_brgfreq = main_clk / 16; -} -#endif - -#ifdef CONFIG_SBC82xx -void -embed_config(bd_t **bdp) -{ - u_char *cp; - int i; - bd_t *bd; - unsigned long pvr; - - bd = *bdp; - - bd = &bdinfo; - *bdp = bd; - bd->bi_baudrate = 9600; - bd->bi_memsize = 256 * 1024 * 1024; /* just a guess */ - - cp = (void*)SBC82xx_MACADDR_NVRAM_SCC1; - memcpy(bd->bi_enetaddr, cp, 6); - - /* can busfreq be calculated? */ - pvr = mfspr(SPRN_PVR); - if ((pvr & 0xffff0000) == 0x80820000) { - bd->bi_busfreq = 100000000; - clk_8280(bd); - } else { - bd->bi_busfreq = 66000000; - clk_8260(bd); - } - -} -#endif /* SBC82xx */ - -#if defined(CONFIG_EST8260) || defined(CONFIG_TQM8260) -void -embed_config(bd_t **bdp) -{ - u_char *cp; - int i; - bd_t *bd; - - bd = *bdp; -#if 0 - /* This is actually provided by my boot rom. I have it - * here for those people that may load the kernel with - * a JTAG/COP tool and not the rom monitor. - */ - bd->bi_baudrate = 115200; - bd->bi_intfreq = 200000000; - bd->bi_busfreq = 66666666; - bd->bi_cpmfreq = 66666666; - bd->bi_brgfreq = 33333333; - bd->bi_memsize = 16 * 1024 * 1024; -#else - /* The boot rom passes these to us in MHz. Linux now expects - * them to be in Hz. - */ - bd->bi_intfreq *= 1000000; - bd->bi_busfreq *= 1000000; - bd->bi_cpmfreq *= 1000000; - bd->bi_brgfreq *= 1000000; -#endif - - cp = (u_char *)def_enet_addr; - for (i=0; i<6; i++) { - bd->bi_enetaddr[i] = *cp++; - } -} -#endif /* EST8260 */ - -#ifdef CONFIG_SBS8260 -void -embed_config(bd_t **bdp) -{ - u_char *cp; - int i; - bd_t *bd; - - /* This should provided by the boot rom. - */ - bd = &bdinfo; - *bdp = bd; - bd->bi_baudrate = 9600; - bd->bi_memsize = 64 * 1024 * 1024; - - /* Set all of the clocks. We have to know the speed of the - * external clock. The development board had 66 MHz. - */ - bd->bi_busfreq = 66666666; - clk_8260(bd); - - /* I don't know how to compute this yet. - */ - bd->bi_intfreq = 133000000; - - - cp = (u_char *)def_enet_addr; - for (i=0; i<6; i++) { - bd->bi_enetaddr[i] = *cp++; - } -} -#endif /* SBS8260 */ - -#ifdef CONFIG_RPX8260 -void -embed_config(bd_t **bdp) -{ - u_char *cp, *keyvals; - int i; - bd_t *bd; - - keyvals = (u_char *)*bdp; - - bd = &bdinfo; - *bdp = bd; - - /* This is almost identical to the RPX-Lite/Classic functions - * on the 8xx boards. It would be nice to have a key lookup - * function in a string, but the format of all of the fields - * is slightly different. - */ - cp = keyvals; - for (;;) { - if (*cp == 'E') { - cp++; - if (*cp == 'A') { - cp += 2; - rpx_eth(bd, cp); - } - } - if (*cp == 'S') { - cp++; - if (*cp == 'B') { - cp += 2; - bd->bi_baudrate = rpx_baseten(cp); - } - } - if (*cp == 'D') { - cp++; - if (*cp == '1') { - cp += 2; - bd->bi_memsize = rpx_baseten(cp) * 1024 * 1024; - } - } - if (*cp == 'X') { - cp++; - if (*cp == 'T') { - cp += 2; - bd->bi_busfreq = rpx_baseten(cp); - } - } - if (*cp == 'N') { - cp++; - if (*cp == 'V') { - cp += 2; - bd->bi_nvsize = rpx_baseten(cp) * 1024 * 1024; - } - } - - /* Scan to the end of the record. - */ - while ((*cp != '\n') && (*cp != 0xff)) - cp++; - - /* If the next character is a 0 or ff, we are done. - */ - cp++; - if ((*cp == 0) || (*cp == 0xff)) - break; - } - bd->bi_memstart = 0; - - /* The memory size includes both the 60x and local bus DRAM. - * I don't want to use the local bus DRAM for real memory, - * so subtract it out. It would be nice if they were separate - * keys. - */ - bd->bi_memsize -= 32 * 1024 * 1024; - - /* Set all of the clocks. We have to know the speed of the - * external clock. - */ - clk_8260(bd); - - /* I don't know how to compute this yet. - */ - bd->bi_intfreq = 200000000; -} -#endif /* RPX6 for testing */ - -#ifdef CONFIG_ADS8260 -void -embed_config(bd_t **bdp) -{ - u_char *cp; - int i; - bd_t *bd; - - /* This should provided by the boot rom. - */ - bd = &bdinfo; - *bdp = bd; - bd->bi_baudrate = 9600; - bd->bi_memsize = 16 * 1024 * 1024; - - /* Set all of the clocks. We have to know the speed of the - * external clock. The development board had 66 MHz. - */ - bd->bi_busfreq = 66666666; - clk_8260(bd); - - /* I don't know how to compute this yet. - */ - bd->bi_intfreq = 200000000; - - - cp = (u_char *)def_enet_addr; - for (i=0; i<6; i++) { - bd->bi_enetaddr[i] = *cp++; - } -} -#endif /* ADS8260 */ - -#ifdef CONFIG_WILLOW -void -embed_config(bd_t **bdp) -{ - u_char *cp; - int i; - bd_t *bd; - - /* Willow has Open Firmware....I should learn how to get this - * information from it. - */ - bd = &bdinfo; - *bdp = bd; - bd->bi_baudrate = 9600; - bd->bi_memsize = 32 * 1024 * 1024; - - /* Set all of the clocks. We have to know the speed of the - * external clock. The development board had 66 MHz. - */ - bd->bi_busfreq = 66666666; - clk_8260(bd); - - /* I don't know how to compute this yet. - */ - bd->bi_intfreq = 200000000; - - - cp = (u_char *)def_enet_addr; - for (i=0; i<6; i++) { - bd->bi_enetaddr[i] = *cp++; - } -} -#endif /* WILLOW */ - -#if defined(CONFIG_XILINX_ML300) || defined(CONFIG_XILINX_ML403) -void -embed_config(bd_t ** bdp) -{ - static const unsigned long line_size = 32; - static const unsigned long congruence_classes = 256; - unsigned long addr; - unsigned long dccr; - uint8_t* cp; - bd_t *bd; - int i; - - /* - * Invalidate the data cache if the data cache is turned off. - * - The 405 core does not invalidate the data cache on power-up - * or reset but does turn off the data cache. We cannot assume - * that the cache contents are valid. - * - If the data cache is turned on this must have been done by - * a bootloader and we assume that the cache contents are - * valid. - */ - __asm__("mfdccr %0": "=r" (dccr)); - if (dccr == 0) { - for (addr = 0; - addr < (congruence_classes * line_size); - addr += line_size) { - __asm__("dccci 0,%0": :"b"(addr)); - } - } - - bd = &bdinfo; - *bdp = bd; - bd->bi_memsize = XPAR_DDR_0_SIZE; - bd->bi_intfreq = XPAR_CORE_CLOCK_FREQ_HZ; - bd->bi_busfreq = XPAR_PLB_CLOCK_FREQ_HZ; - bd->bi_pci_busfreq = XPAR_PCI_0_CLOCK_FREQ_HZ; - - /* Copy the default ethernet address */ - cp = (u_char *)def_enet_addr; - for (i=0; i<6; i++) - bd->bi_enetaddr[i] = *cp++; - - timebase_period_ns = 1000000000 / bd->bi_tbfreq; - /* see bi_tbfreq definition in arch/ppc/platforms/4xx/xilinx_ml300.h */ -} -#endif /* CONFIG_XILINX_ML300 || CONFIG_XILINX_ML403 */ - -#ifdef CONFIG_IBM_OPENBIOS -/* This could possibly work for all treeboot roms. -*/ -#if defined(CONFIG_BUBINGA) -#define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */ -#else -#define BOARD_INFO_VECTOR 0xFFFE0B50 -#endif - -void -embed_config(bd_t **bdp) -{ - u_char *cp; - int i; - bd_t *bd, *treeboot_bd; - bd_t *(*get_board_info)(void) = - (bd_t *(*)(void))(*(unsigned long *)BOARD_INFO_VECTOR); -#if !defined(CONFIG_STB03xxx) - - /* shut down the Ethernet controller that the boot rom - * sometimes leaves running. - */ - mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */ - while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */ - out_be32((volatile u32*)EMAC0_BASE,0x20000000); /* then reset EMAC */ -#endif - - bd = &bdinfo; - *bdp = bd; - if ((treeboot_bd = get_board_info()) != NULL) { - memcpy(bd, treeboot_bd, sizeof(bd_t)); - } - else { - /* Hmmm...better try to stuff some defaults. - */ - bd->bi_memsize = 16 * 1024 * 1024; - cp = (u_char *)def_enet_addr; - for (i=0; i<6; i++) { - /* I should probably put different ones here, - * hopefully only one is used. - */ - bd->BD_EMAC_ADDR(0,i) = *cp; - -#ifdef CONFIG_PCI - bd->bi_pci_enetaddr[i] = *cp++; -#endif - } - bd->bi_tbfreq = 200 * 1000 * 1000; - bd->bi_intfreq = 200000000; - bd->bi_busfreq = 100000000; -#ifdef CONFIG_PCI - bd->bi_pci_busfreq = 66666666; -#endif - } - /* Yeah, this look weird, but on Redwood 4 they are - * different object in the structure. Sincr Redwwood 5 - * and Redwood 6 use OpenBIOS, it requires a special value. - */ -#if defined(CONFIG_REDWOOD_5) || defined (CONFIG_REDWOOD_6) - bd->bi_tbfreq = 27 * 1000 * 1000; -#endif - timebase_period_ns = 1000000000 / bd->bi_tbfreq; -} -#endif /* CONFIG_IBM_OPENBIOS */ - -#ifdef CONFIG_EP405 -#include - -void -embed_config(bd_t **bdp) -{ - u32 chcr0; - u_char *cp; - bd_t *bd; - - /* Different versions of the PlanetCore firmware vary in how - they set up the serial port - in particular whether they - use the internal or external serial clock for UART0. Make - sure the UART is in a known state. */ - /* FIXME: We should use the board's 11.0592MHz external serial - clock - it will be more accurate for serial rates. For - now, however the baud rates in ep405.h are for the internal - clock. */ - chcr0 = mfdcr(DCRN_CHCR0); - if ( (chcr0 & 0x1fff) != 0x103e ) { - mtdcr(DCRN_CHCR0, (chcr0 & 0xffffe000) | 0x103e); - /* The following tricks serial_init() into resetting the baud rate */ - writeb(0, UART0_IO_BASE + UART_LCR); - } - - /* We haven't seen actual problems with the EP405 leaving the - * EMAC running (as we have on Walnut). But the registers - * suggest it may not be left completely quiescent. Reset it - * just to be sure. */ - mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */ - while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */ - out_be32((unsigned *)EMAC0_BASE,0x20000000); /* then reset EMAC */ - - bd = &bdinfo; - *bdp = bd; -#if 1 - cp = (u_char *)0xF0000EE0; - for (;;) { - if (*cp == 'E') { - cp++; - if (*cp == 'A') { - cp += 2; - rpx_eth(bd, cp); - } - } - - if (*cp == 'D') { - cp++; - if (*cp == '1') { - cp += 2; - rpx_memsize(bd, cp); - } - } - - if (*cp == 'N') { - cp++; - if (*cp == 'V') { - cp += 2; - rpx_nvramsize(bd, cp); - } - } - while ((*cp != '\n') && (*cp != 0xff)) - cp++; - - cp++; - if ((*cp == 0) || (*cp == 0xff)) - break; - } - bd->bi_intfreq = 200000000; - bd->bi_busfreq = 100000000; - bd->bi_pci_busfreq= 33000000 ; -#else - - bd->bi_memsize = 64000000; - bd->bi_intfreq = 200000000; - bd->bi_busfreq = 100000000; - bd->bi_pci_busfreq= 33000000 ; -#endif -} -#endif diff --git a/arch/ppc/boot/simple/head.S b/arch/ppc/boot/simple/head.S deleted file mode 100644 index 1b4d7b1d4ec1..000000000000 --- a/arch/ppc/boot/simple/head.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Initial board bringup code for many different boards. - * - * Author: Tom Rini - * trini@mvista.com - * Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others). - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include - - .text - -/* - * Begin at some arbitrary location in RAM or Flash - * Initialize core registers - * Configure memory controller (Not executing from RAM) - * Move the boot code to the link address (8M) - * Setup C stack - * Initialize UART - * Decompress the kernel to 0x0 - * Jump to the kernel entry - * - */ - - .globl start -start: - bl start_ -#ifdef CONFIG_IBM_OPENBIOS - /* The IBM "Tree" bootrom knows that the address of the bootrom - * read only structure is 4 bytes after _start. - */ - .long 0x62726f6d # structure ID - "brom" - .long 0x5f726f00 # - "_ro\0" - .long 1 # structure version - .long bootrom_cmdline # address of *bootrom_cmdline -#endif - -start_: -#ifdef CONFIG_FORCE - /* We have some really bad firmware. We must disable the L1 - * icache/dcache now or the board won't boot. - */ - li r4,0x0000 - isync - mtspr SPRN_HID0,r4 - sync - isync -#endif - -#if defined(CONFIG_MBX) || defined(CONFIG_RPX8260) || defined(CONFIG_PPC_PREP) - mr r29,r3 /* On the MBX860, r3 is the board info pointer. - * On the RPXSUPER, r3 points to the NVRAM - * configuration keys. - * On PReP, r3 is the pointer to the residual data. - */ -#endif - -#if defined(CONFIG_XILINX_VIRTEX_4_FX) - /* PPC errata 213: only for Virtex-4 FX */ - mfccr0 0 - oris 0,0,0x50000000@h - mtccr0 0 -#endif - - mflr r3 /* Save our actual starting address. */ - - /* The following functions we call must not modify r3 or r4..... - */ -#ifdef CONFIG_6xx - /* On PReP we must look at the OpenFirmware pointer and sanity - * test it. On other platforms, we disable the MMU right now - * and other bits. - */ -#ifdef CONFIG_PPC_PREP -/* - * Save the OF pointer to r25, but only if the entry point is in a sane - * location; if not we store 0. If there is no entry point, or it is - * invalid, we establish the default MSR value immediately. Otherwise, - * we defer doing that, to allow OF functions to be called, until we - * begin uncompressing the kernel. - */ - lis r8,0x0fff /* r8 = 0x0fffffff */ - ori r8,r8,0xffff - - subc r8,r8,r5 /* r8 = (r5 <= r8) ? ~0 : 0 */ - subfe r8,r8,r8 - nand r8,r8,r8 - - and. r5,r5,r8 /* r5 will be cleared if (r5 > r8) */ - bne+ haveOF - - li r8,MSR_IP|MSR_FP /* Not OF: set MSR immediately */ - mtmsr r8 - isync -haveOF: - mr r25,r5 -#else - bl disable_6xx_mmu -#endif - bl disable_6xx_l1cache - - CLEAR_CACHES -#endif - -#ifdef CONFIG_8xx - mfmsr r8 /* Turn off interrupts */ - li r9,0 - ori r9,r9,MSR_EE - andc r8,r8,r9 - mtmsr r8 - - /* We do this because some boot roms don't initialize the - * processor correctly. Don't do this if you want to debug - * using a BDM device. - */ - li r4,0 /* Zero DER to prevent FRZ */ - mtspr SPRN_DER,r4 -#endif - -#if defined(CONFIG_MBX) || defined(CONFIG_RPX8260) || defined(CONFIG_PPC_PREP) - mr r4,r29 /* put the board info pointer where the relocate - * routine will find it - */ -#endif - - /* Get the load address. - */ - subi r3, r3, 4 /* Get the actual IP, not NIP */ - b relocate - diff --git a/arch/ppc/boot/simple/iic.c b/arch/ppc/boot/simple/iic.c deleted file mode 100644 index 5e91489426b4..000000000000 --- a/arch/ppc/boot/simple/iic.c +++ /dev/null @@ -1,214 +0,0 @@ -/* Minimal support functions to read configuration from IIC EEPROMS - * on MPC8xx boards. Originally written for RPGC RPX-Lite. - * Dan Malek (dmalek@jlc.net). - */ -#include -#include -#include -#include - - -/* IIC functions. - * These are just the basic master read/write operations so we can - * examine serial EEPROM. - */ -void iic_read(uint devaddr, u_char *buf, uint offset, uint count); - -static int iic_init_done; - -static void -iic_init(void) -{ - volatile iic_t *iip; - volatile i2c8xx_t *i2c; - volatile cpm8xx_t *cp; - volatile immap_t *immap; - uint dpaddr; - - immap = (immap_t *)IMAP_ADDR; - cp = (cpm8xx_t *)&(immap->im_cpm); - - /* Reset the CPM. This is necessary on the 860 processors - * that may have started the SCC1 ethernet without relocating - * the IIC. - * This also stops the Ethernet in case we were loaded by a - * BOOTP rom monitor. - */ - cp->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG); - - /* Wait for it. - */ - while (cp->cp_cpcr & (CPM_CR_RST | CPM_CR_FLG)); - - /* Remove any microcode patches. We will install our own - * later. - */ - cp->cp_cpmcr1 = 0; - cp->cp_cpmcr2 = 0; - cp->cp_cpmcr3 = 0; - cp->cp_cpmcr4 = 0; - cp->cp_rccr = 0; - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - i2c = (i2c8xx_t *)&(immap->im_i2c); - - /* Initialize Port B IIC pins. - */ - cp->cp_pbpar |= 0x00000030; - cp->cp_pbdir |= 0x00000030; - cp->cp_pbodr |= 0x00000030; - - /* Initialize the parameter ram. - */ - - /* Allocate space for a two transmit and one receive buffer - * descriptor in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - */ - dpaddr = 0x0840; - - /* Set up the IIC parameters in the parameter ram. - */ - iip->iic_tbase = dpaddr; - iip->iic_rbase = dpaddr + (2 * sizeof(cbd_t)); - - iip->iic_tfcr = SMC_EB; - iip->iic_rfcr = SMC_EB; - - /* This should really be done by the reader/writer. - */ - iip->iic_mrblr = 128; - - /* Initialize Tx/Rx parameters. - */ - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - /* Select an arbitrary address. Just make sure it is unique. - */ - i2c->i2c_i2add = 0x34; - - /* Make clock run maximum slow. - */ - i2c->i2c_i2brg = 7; - - /* Disable interrupts. - */ - i2c->i2c_i2cmr = 0; - i2c->i2c_i2cer = 0xff; - - /* Enable SDMA. - */ - immap->im_siu_conf.sc_sdcr = 1; - - iic_init_done = 1; -} - -/* Read from IIC. - * Caller provides device address, memory buffer, and byte count. - */ -static u_char iitemp[32]; - -void -iic_read(uint devaddr, u_char *buf, uint offset, uint count) -{ - volatile iic_t *iip; - volatile i2c8xx_t *i2c; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp; - volatile immap_t *immap; - u_char *tb; - uint temp; - - /* If the interface has not been initialized, do that now. - */ - if (!iic_init_done) - iic_init(); - - immap = (immap_t *)IMAP_ADDR; - cp = (cpm8xx_t *)&(immap->im_cpm); - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - i2c = (i2c8xx_t *)&(immap->im_i2c); - - tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase]; - rbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_rbase]; - - /* Send a "dummy write" operation. This is a write request with - * only the offset sent, followed by another start condition. - * This will ensure we start reading from the first location - * of the EEPROM. - */ - tb = iitemp; - tb = (u_char *)(((uint)tb + 15) & ~15); - tbdf->cbd_bufaddr = (int)tb; - *tb = devaddr & 0xfe; /* Device address */ - *(tb+1) = offset; /* Offset */ - tbdf->cbd_datlen = 2; /* Length */ - tbdf->cbd_sc = - BD_SC_READY | BD_SC_LAST | BD_SC_WRAP | BD_IIC_START; - - i2c->i2c_i2mod = 1; /* Enable */ - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2com = 0x81; /* Start master */ - - /* Wait for IIC transfer. - */ -#if 0 - while ((i2c->i2c_i2cer & 3) == 0); - - if (tbdf->cbd_sc & BD_SC_READY) - printf("IIC ra complete but tbuf ready\n"); -#else - temp = 10000000; - while ((tbdf->cbd_sc & BD_SC_READY) && (temp != 0)) - temp--; -#if 0 - /* We can't do this...there is no serial port yet! - */ - if (temp == 0) { - printf("Timeout reading EEPROM\n"); - return; - } -#endif -#endif - - /* Chip errata, clear enable. - */ - i2c->i2c_i2mod = 0; - - /* To read, we need an empty buffer of the proper length. - * All that is used is the first byte for address, the remainder - * is just used for timing (and doesn't really have to exist). - */ - tbdf->cbd_bufaddr = (int)tb; - *tb = devaddr | 1; /* Device address */ - rbdf->cbd_bufaddr = (uint)buf; /* Desination buffer */ - tbdf->cbd_datlen = rbdf->cbd_datlen = count + 1; /* Length */ - tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP | BD_IIC_START; - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - - /* Chip bug, set enable here. - */ - i2c->i2c_i2mod = 1; /* Enable */ - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2com = 0x81; /* Start master */ - - /* Wait for IIC transfer. - */ -#if 0 - while ((i2c->i2c_i2cer & 1) == 0); - - if (rbdf->cbd_sc & BD_SC_EMPTY) - printf("IIC read complete but rbuf empty\n"); -#else - temp = 10000000; - while ((tbdf->cbd_sc & BD_SC_READY) && (temp != 0)) - temp--; -#endif - - /* Chip errata, clear enable. - */ - i2c->i2c_i2mod = 0; -} diff --git a/arch/ppc/boot/simple/m8260_tty.c b/arch/ppc/boot/simple/m8260_tty.c deleted file mode 100644 index d770947e9b8f..000000000000 --- a/arch/ppc/boot/simple/m8260_tty.c +++ /dev/null @@ -1,325 +0,0 @@ -/* Minimal serial functions needed to send messages out the serial - * port on SMC1. - */ -#include -#include -#include -#include - -uint no_print; -extern char *params[]; -extern int nparams; -static u_char cons_hold[128], *sgptr; -static int cons_hold_cnt; - -/* If defined, enables serial console. The value (1 through 4) - * should designate which SCC is used, but this isn't complete. Only - * SCC1 is known to work at this time. - * We're only linked if SERIAL_CPM_CONSOLE=y, so we only need to test - * SERIAL_CPM_SCC1. - */ -#ifdef CONFIG_SERIAL_CPM_SCC1 -#define SCC_CONSOLE 1 -#endif - -unsigned long -serial_init(int ignored, bd_t *bd) -{ -#ifdef SCC_CONSOLE - volatile scc_t *sccp; - volatile scc_uart_t *sup; -#else - volatile smc_t *sp; - volatile smc_uart_t *up; -#endif - volatile cbd_t *tbdf, *rbdf; - volatile cpm2_map_t *ip; - volatile iop_cpm2_t *io; - volatile cpm_cpm2_t *cp; - uint dpaddr, memaddr; - - ip = (cpm2_map_t *)CPM_MAP_ADDR; - cp = &ip->im_cpm; - io = &ip->im_ioport; - - /* Perform a reset. - */ - cp->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG); - - /* Wait for it. - */ - while (cp->cp_cpcr & CPM_CR_FLG); - -#ifdef CONFIG_ADS8260 - /* Enable the RS-232 transceivers. - */ - *(volatile uint *)(BCSR_ADDR + 4) &= - ~(BCSR1_RS232_EN1 | BCSR1_RS232_EN2); -#endif - -#ifdef SCC_CONSOLE - sccp = (scc_t *)&(ip->im_scc[SCC_CONSOLE-1]); - sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)]; - sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX); - sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* Use Port D for SCC1 instead of other functions. - */ - io->iop_ppard |= 0x00000003; - io->iop_psord &= ~0x00000001; /* Rx */ - io->iop_psord |= 0x00000002; /* Tx */ - io->iop_pdird &= ~0x00000001; /* Rx */ - io->iop_pdird |= 0x00000002; /* Tx */ - -#else - sp = (smc_t*)&(ip->im_smc[0]); - *(ushort *)(&ip->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1; - up = (smc_uart_t *)&ip->im_dprambase[PROFF_SMC1]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Use Port D for SMC1 instead of other functions. - */ - io->iop_ppard |= 0x00c00000; - io->iop_pdird |= 0x00400000; - io->iop_pdird &= ~0x00800000; - io->iop_psord &= ~0x00c00000; -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - */ - dpaddr = 0x0800; - - /* Grab a few bytes from the top of memory. - */ - memaddr = (bd->bi_memsize - 256) & ~15; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&ip->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = memaddr; - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = memaddr+128; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ -#ifdef SCC_CONSOLE - sup->scc_genscc.scc_rbase = dpaddr; - sup->scc_genscc.scc_tbase = dpaddr + sizeof(cbd_t); - - /* Set up the uart parameters in the - * parameter ram. - */ - sup->scc_genscc.scc_rfcr = CPMFCR_GBL | CPMFCR_EB; - sup->scc_genscc.scc_tfcr = CPMFCR_GBL | CPMFCR_EB; - - sup->scc_genscc.scc_mrblr = 128; - sup->scc_maxidl = 8; - sup->scc_brkcr = 1; - sup->scc_parec = 0; - sup->scc_frmec = 0; - sup->scc_nosec = 0; - sup->scc_brkec = 0; - sup->scc_uaddr1 = 0; - sup->scc_uaddr2 = 0; - sup->scc_toseq = 0; - sup->scc_char1 = 0x8000; - sup->scc_char2 = 0x8000; - sup->scc_char3 = 0x8000; - sup->scc_char4 = 0x8000; - sup->scc_char5 = 0x8000; - sup->scc_char6 = 0x8000; - sup->scc_char7 = 0x8000; - sup->scc_char8 = 0x8000; - sup->scc_rccm = 0xc0ff; - - /* Send the CPM an initialize command. - */ - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sccp->scc_gsmrh = 0; - sccp->scc_gsmrl = - (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); - - /* Disable all interrupts and clear all pending - * events. - */ - sccp->scc_sccm = 0; - sccp->scc_scce = 0xffff; - sccp->scc_dsr = 0x7e7e; - sccp->scc_psmr = 0x3000; - - /* Wire BRG1 to SCC1. The console driver will take care of - * others. - */ - ip->im_cpmux.cmx_scr = 0; -#else - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = CPMFCR_EB; - up->smc_tfcr = CPMFCR_EB; - up->smc_brklen = 0; - up->smc_brkec = 0; - up->smc_brkcr = 0; - up->smc_mrblr = 128; - up->smc_maxidl = 8; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - */ - ip->im_cpmux.cmx_smr = 0; -#endif - - /* The baud rate divisor needs to be coordinated with clk_8260(). - */ - ip->im_brgc1 = - (((bd->bi_brgfreq/16) / bd->bi_baudrate) << 1) | - CPM_BRG_EN; - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Initialize Tx/Rx parameters. - */ -#ifdef SCC_CONSOLE - sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); -#else - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; -#endif - - /* This is ignored. - */ - return 0; -} - -int -serial_readbuf(u_char *cbuf) -{ - volatile cbd_t *rbdf; - volatile char *buf; -#ifdef SCC_CONSOLE - volatile scc_uart_t *sup; -#else - volatile smc_uart_t *up; -#endif - volatile cpm2_map_t *ip; - int i, nc; - - ip = (cpm2_map_t *)CPM_MAP_ADDR; - -#ifdef SCC_CONSOLE - sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)]; - rbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_rbase]; -#else - up = (smc_uart_t *)&(ip->im_dprambase[PROFF_SMC1]); - rbdf = (cbd_t *)&ip->im_dprambase[up->smc_rbase]; -#endif - - /* Wait for character to show up. - */ - buf = (char *)rbdf->cbd_bufaddr; - while (rbdf->cbd_sc & BD_SC_EMPTY); - nc = rbdf->cbd_datlen; - for (i=0; icbd_sc |= BD_SC_EMPTY; - - return(nc); -} - -void -serial_putc(void *ignored, const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; -#ifdef SCC_CONSOLE - volatile scc_uart_t *sup; -#else - volatile smc_uart_t *up; -#endif - volatile cpm2_map_t *ip; - - ip = (cpm2_map_t *)CPM_MAP_ADDR; -#ifdef SCC_CONSOLE - sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)]; - tbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_tbase]; -#else - up = (smc_uart_t *)&(ip->im_dprambase[PROFF_SMC1]); - tbdf = (cbd_t *)&ip->im_dprambase[up->smc_tbase]; -#endif - - /* Wait for last character to go. - */ - buf = (char *)tbdf->cbd_bufaddr; - while (tbdf->cbd_sc & BD_SC_READY); - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -char -serial_getc(void *ignored) -{ - char c; - - if (cons_hold_cnt <= 0) { - cons_hold_cnt = serial_readbuf(cons_hold); - sgptr = cons_hold; - } - c = *sgptr++; - cons_hold_cnt--; - - return(c); -} - -int -serial_tstc(void *ignored) -{ - volatile cbd_t *rbdf; -#ifdef SCC_CONSOLE - volatile scc_uart_t *sup; -#else - volatile smc_uart_t *up; -#endif - volatile cpm2_map_t *ip; - - ip = (cpm2_map_t *)CPM_MAP_ADDR; -#ifdef SCC_CONSOLE - sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)]; - rbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_rbase]; -#else - up = (smc_uart_t *)&(ip->im_dprambase[PROFF_SMC1]); - rbdf = (cbd_t *)&ip->im_dprambase[up->smc_rbase]; -#endif - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} diff --git a/arch/ppc/boot/simple/m8xx_tty.c b/arch/ppc/boot/simple/m8xx_tty.c deleted file mode 100644 index f28924e6aeb4..000000000000 --- a/arch/ppc/boot/simple/m8xx_tty.c +++ /dev/null @@ -1,289 +0,0 @@ -/* Minimal serial functions needed to send messages out the serial - * port on the MBX console. - * - * The MBX uses SMC1 for the serial port. We reset the port and use - * only the first BD that EPPC-Bug set up as a character FIFO. - * - * Later versions (at least 1.4, maybe earlier) of the MBX EPPC-Bug - * use COM1 instead of SMC1 as the console port. This kinda sucks - * for the rest of the kernel, so here we force the use of SMC1 again. - */ -#include -#include -#include -#include - -#ifdef CONFIG_MBX -#define MBX_CSR1 ((volatile u_char *)0xfa100000) -#define CSR1_COMEN (u_char)0x02 -#endif - -#ifdef TQM_SMC2_CONSOLE -#define PROFF_CONS PROFF_SMC2 -#define CPM_CR_CH_CONS CPM_CR_CH_SMC2 -#define SMC_INDEX 1 -static volatile iop8xx_t *iopp = (iop8xx_t *)&(((immap_t *)IMAP_ADDR)->im_ioport); -#else -#define PROFF_CONS PROFF_SMC1 -#define CPM_CR_CH_CONS CPM_CR_CH_SMC1 -#define SMC_INDEX 0 -#endif - -static cpm8xx_t *cpmp = (cpm8xx_t *)&(((immap_t *)IMAP_ADDR)->im_cpm); - -unsigned long -serial_init(int ignored, bd_t *bd) -{ - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp; - uint dpaddr, memaddr; -#ifndef CONFIG_MBX - uint ui; -#endif - - cp = cpmp; - sp = (smc_t*)&(cp->cp_smc[SMC_INDEX]); - up = (smc_uart_t *)&cp->cp_dparam[PROFF_CONS]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - -#ifdef CONFIG_FADS - /* Enable SMC1/2 transceivers. - */ - *((volatile uint *)BCSR1) &= ~(BCSR1_RS232EN_1|BCSR1_RS232EN_2); -#endif - -#ifndef CONFIG_MBX - { - /* Initialize SMCx and use it for the console port. - */ - - /* Enable SDMA. - */ - ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sdcr = 1; - -#ifdef TQM_SMC2_CONSOLE - /* Use Port A for SMC2 instead of other functions. - */ - iopp->iop_papar |= 0x00c0; - iopp->iop_padir &= ~0x00c0; - iopp->iop_paodr &= ~0x00c0; -#else - /* Use Port B for SMCs instead of other functions. - */ - cp->cp_pbpar |= 0x00000cc0; - cp->cp_pbdir &= ~0x00000cc0; - cp->cp_pbodr &= ~0x00000cc0; -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - */ - dpaddr = 0x0800; - - /* Grab a few bytes from the top of memory for SMC FIFOs. - */ - memaddr = (bd->bi_memsize - 32) & ~15; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = memaddr; - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = memaddr+4; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * This wires BRG1 to SMC1 and BRG2 to SMC2; - */ - cp->cp_simode = 0x10000000; - ui = bd->bi_intfreq / 16 / bd->bi_baudrate; -#ifdef TQM_SMC2_CONSOLE - cp->cp_brgc2 = -#else - cp->cp_brgc1 = -#endif - ((ui - 1) < 4096) - ? (((ui - 1) << 1) | CPM_BRG_EN) - : ((((ui / 16) - 1) << 1) | CPM_BRG_EN | CPM_BRG_DIV16); - -#else /* CONFIG_MBX */ - if (*MBX_CSR1 & CSR1_COMEN) { - /* COM1 is enabled. Initialize SMC1 and use it for - * the console port. - */ - - /* Enable SDMA. - */ - ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sdcr = 1; - - /* Use Port B for SMCs instead of other functions. - */ - cp->cp_pbpar |= 0x00000cc0; - cp->cp_pbdir &= ~0x00000cc0; - cp->cp_pbodr &= ~0x00000cc0; - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - */ - dpaddr = 0x0800; - - /* Grab a few bytes from the top of memory. EPPC-Bug isn't - * running any more, so we can do this. - */ - memaddr = (bd->bi_memsize - 32) & ~15; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = memaddr; - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = memaddr+4; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - */ - cp->cp_simode = 0x10000000; - cp->cp_brgc1 = - (((bd->bi_intfreq/16) / 9600) << 1) | CPM_BRG_EN; - - /* Enable SMC1 for console output. - */ - *MBX_CSR1 &= ~CSR1_COMEN; - } - else { -#endif /* ndef CONFIG_MBX */ - /* SMCx is used as console port. - */ - tbdf = (cbd_t *)&cp->cp_dpmem[up->smc_tbase]; - rbdf = (cbd_t *)&cp->cp_dpmem[up->smc_rbase]; - - /* Issue a stop transmit, and wait for it. - */ - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_CONS, - CPM_CR_STOP_TX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - } - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_CONS, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - /* This is ignored. - */ - return 0; -} - -void -serial_putc(void *ignored, const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS]; - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - buf = (char *)tbdf->cbd_bufaddr; - while (tbdf->cbd_sc & BD_SC_READY); - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -char -serial_getc(void *ignored) -{ - volatile cbd_t *rbdf; - volatile char *buf; - volatile smc_uart_t *up; - char c; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS]; - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (char *)rbdf->cbd_bufaddr; - while (rbdf->cbd_sc & BD_SC_EMPTY); - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -int -serial_tstc(void *ignored) -{ - volatile cbd_t *rbdf; - volatile smc_uart_t *up; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS]; - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} diff --git a/arch/ppc/boot/simple/misc-chestnut.c b/arch/ppc/boot/simple/misc-chestnut.c deleted file mode 100644 index 14a4b56d4f84..000000000000 --- a/arch/ppc/boot/simple/misc-chestnut.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Setup for the IBM Chestnut (ibm-750fxgx_eval) - * - * Author: Mark A. Greer - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include - -/* Not in the kernel so won't include kernel.h to get its 'max' definition */ -#define max(a,b) (((a) > (b)) ? (a) : (b)) - -void -mv64x60_board_init(void __iomem *old_base, void __iomem *new_base) -{ -#ifdef CONFIG_SERIAL_8250_CONSOLE - /* - * Change device bus 2 window so that bootoader can do I/O thru - * 8250/16550 UART that's mapped in that window. - */ - out_le32(new_base + MV64x60_CPU2DEV_2_BASE, CHESTNUT_UART_BASE >> 16); - out_le32(new_base + MV64x60_CPU2DEV_2_SIZE, CHESTNUT_UART_SIZE >> 16); - __asm__ __volatile__("sync"); -#endif -} diff --git a/arch/ppc/boot/simple/misc-cpci690.c b/arch/ppc/boot/simple/misc-cpci690.c deleted file mode 100644 index 8a8614d11a32..000000000000 --- a/arch/ppc/boot/simple/misc-cpci690.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Add birec data for Force CPCI690 board. - * - * Author: Mark A. Greer - * - * 2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include - -#define KB (1024UL) -#define MB (1024UL*KB) -#define GB (1024UL*MB) - -extern u32 mv64x60_console_baud; -extern u32 mv64x60_mpsc_clk_src; -extern u32 mv64x60_mpsc_clk_freq; - -u32 mag = 0xffff; - -unsigned long -get_mem_size(void) -{ - u32 size; - - switch (in_8(((void __iomem *)CPCI690_BR_BASE + CPCI690_BR_MEM_CTLR)) - & 0x07) { - case 0x01: - size = 256*MB; - break; - case 0x02: - size = 512*MB; - break; - case 0x03: - size = 768*MB; - break; - case 0x04: - size = 1*GB; - break; - case 0x05: - size = 1*GB + 512*MB; - break; - case 0x06: - size = 2*GB; - break; - default: - size = 0; - } - - return size; -} - -void -mv64x60_board_init(void __iomem *old_base, void __iomem *new_base) -{ - mv64x60_console_baud = CPCI690_MPSC_BAUD; - mv64x60_mpsc_clk_src = CPCI690_MPSC_CLK_SRC; - mv64x60_mpsc_clk_freq = - (get_mem_size() >= (1*GB)) ? 100000000 : 133333333; -} diff --git a/arch/ppc/boot/simple/misc-embedded.c b/arch/ppc/boot/simple/misc-embedded.c deleted file mode 100644 index d5a00eb0e4eb..000000000000 --- a/arch/ppc/boot/simple/misc-embedded.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Originally adapted by Gary Thomas. Much additional work by - * Cort Dougan . On top of that still more work by - * Dan Malek . - * - * Currently maintained by: Tom Rini - */ - -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_4xx) -#include -#elif defined(CONFIG_8xx) -#include -#elif defined(CONFIG_8260) -#include -#endif - -#include "nonstdio.h" - -/* The linker tells us where the image is. */ -extern char __image_begin, __image_end; -extern char __ramdisk_begin, __ramdisk_end; -extern char _end[]; - -/* Because of the limited amount of memory on embedded, it presents - * loading problems. The biggest is that we load this boot program - * into a relatively low memory address, and the Linux kernel Bss often - * extends into this space when it get loaded. When the kernel starts - * and zeros the BSS space, it also writes over the information we - * save here and pass to the kernel (usually board info). - * On these boards, we grab some known memory holes to hold this information. - */ -char cmd_buf[256]; -char *cmd_line = cmd_buf; -char *avail_ram; -char *end_avail; -char *zimage_start; - -/* This is for 4xx treeboot. It provides a place for the bootrom - * give us a pointer to a rom environment command line. - */ -char *bootrom_cmdline = ""; - -/* This is the default cmdline that will be given to the user at boot time.. - * If none was specified at compile time, we'll give it one that should work. - * -- Tom */ -#ifdef CONFIG_CMDLINE_BOOL -char compiled_string[] = CONFIG_CMDLINE; -#endif -char ramroot_string[] = "root=/dev/ram"; -char netroot_string[] = "root=/dev/nfs rw ip=on"; - -/* Serial port to use. */ -unsigned long com_port; - -/* We need to make sure that this is before the images to ensure - * that it's in a mapped location. - Tom */ -bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot"))); -bd_t *hold_residual = &hold_resid_buf; - -extern unsigned long serial_init(int chan, bd_t *bp); -extern void serial_close(unsigned long com_port); -extern unsigned long start; -extern void flush_instruction_cache(void); -extern void gunzip(void *, int, unsigned char *, int *); -extern void embed_config(bd_t **bp); - -/* Weak function for boards which don't need to build the - * board info struct because they are using PPCBoot/U-Boot. - */ -void __attribute__ ((weak)) -embed_config(bd_t **bdp) -{ -} - -unsigned long -load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, bd_t *bp) -{ - char *cp, ch; - int timer = 0, zimage_size; - unsigned long initrd_size; - - /* First, capture the embedded board information. Then - * initialize the serial console port. - */ - embed_config(&bp); -#if defined(CONFIG_SERIAL_CPM_CONSOLE) || \ - defined(CONFIG_SERIAL_8250_CONSOLE) || \ - defined(CONFIG_SERIAL_UARTLITE_CONSOLE) - com_port = serial_init(0, bp); -#endif - - /* Grab some space for the command line and board info. Since - * we no longer use the ELF header, but it was loaded, grab - * that space. - */ -#ifdef CONFIG_MBX - /* Because of the way the MBX loads the ELF image, we can't - * tell where we started. We read a magic variable from the NVRAM - * that gives us the intermediate buffer load address. - */ - load_addr = *(uint *)0xfa000020; - load_addr += 0x10000; /* Skip ELF header */ -#endif - /* copy board data */ - if (bp) - memcpy(hold_residual,bp,sizeof(bd_t)); - - /* Set end of memory available to us. It is always the highest - * memory address provided by the board information. - */ - end_avail = (char *)(bp->bi_memsize); - - puts("\nloaded at: "); puthex(load_addr); - puts(" "); puthex((unsigned long)(load_addr + (4*num_words))); puts("\n"); - if ( (unsigned long)load_addr != (unsigned long)&start ) { - puts("relocated to: "); puthex((unsigned long)&start); - puts(" "); - puthex((unsigned long)((unsigned long)&start + (4*num_words))); - puts("\n"); - } - - if ( bp ) { - puts("board data at: "); puthex((unsigned long)bp); - puts(" "); - puthex((unsigned long)((unsigned long)bp + sizeof(bd_t))); - puts("\nrelocated to: "); - puthex((unsigned long)hold_residual); - puts(" "); - puthex((unsigned long)((unsigned long)hold_residual + sizeof(bd_t))); - puts("\n"); - } - - /* - * We link ourself to an arbitrary low address. When we run, we - * relocate ourself to that address. __image_being points to - * the part of the image where the zImage is. -- Tom - */ - zimage_start = (char *)(unsigned long)(&__image_begin); - zimage_size = (unsigned long)(&__image_end) - - (unsigned long)(&__image_begin); - - initrd_size = (unsigned long)(&__ramdisk_end) - - (unsigned long)(&__ramdisk_begin); - - /* - * The zImage and initrd will be between start and _end, so they've - * already been moved once. We're good to go now. -- Tom - */ - puts("zimage at: "); puthex((unsigned long)zimage_start); - puts(" "); puthex((unsigned long)(zimage_size+zimage_start)); - puts("\n"); - - if ( initrd_size ) { - puts("initrd at: "); - puthex((unsigned long)(&__ramdisk_begin)); - puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n"); - } - - /* - * setup avail_ram - this is the first part of ram usable - * by the uncompress code. Anything after this program in RAM - * is now fair game. -- Tom - */ - avail_ram = (char *)PAGE_ALIGN((unsigned long)_end); - - puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" "); - puthex((unsigned long)end_avail); puts("\n"); - puts("\nLinux/PPC load: "); - cp = cmd_line; - /* This is where we try and pick the right command line for booting. - * If we were given one at compile time, use it. It Is Right. - * If we weren't, see if we have a ramdisk. If so, thats root. - * When in doubt, give them the netroot (root=/dev/nfs rw) -- Tom - */ -#ifdef CONFIG_CMDLINE_BOOL - memcpy (cmd_line, compiled_string, sizeof(compiled_string)); -#else - if ( initrd_size ) - memcpy (cmd_line, ramroot_string, sizeof(ramroot_string)); - else - memcpy (cmd_line, netroot_string, sizeof(netroot_string)); -#endif - while ( *cp ) - putc(*cp++); - while (timer++ < 5*1000) { - if (tstc()) { - while ((ch = getc()) != '\n' && ch != '\r') { - if (ch == '\b' || ch == '\177') { - if (cp != cmd_line) { - cp--; - puts("\b \b"); - } - } else if (ch == '\030' /* ^x */ - || ch == '\025') { /* ^u */ - while (cp != cmd_line) { - cp--; - puts("\b \b"); - } - } else { - *cp++ = ch; - putc(ch); - } - } - break; /* Exit 'timer' loop */ - } - udelay(1000); /* 1 msec */ - } - *cp = 0; - puts("\nUncompressing Linux..."); - - gunzip(0, 0x400000, zimage_start, &zimage_size); - flush_instruction_cache(); - puts("done.\n"); - { - struct bi_record *rec; - unsigned long initrd_loc = 0; - unsigned long rec_loc = _ALIGN((unsigned long)(zimage_size) + - (1 << 20) - 1, (1 << 20)); - rec = (struct bi_record *)rec_loc; - - /* We need to make sure that the initrd and bi_recs do not - * overlap. */ - if ( initrd_size ) { - initrd_loc = (unsigned long)(&__ramdisk_begin); - /* If the bi_recs are in the middle of the current - * initrd, move the initrd to the next MB - * boundary. */ - if ((rec_loc > initrd_loc) && - ((initrd_loc + initrd_size) - > rec_loc)) { - initrd_loc = _ALIGN((unsigned long)(zimage_size) - + (2 << 20) - 1, (2 << 20)); - memmove((void *)initrd_loc, &__ramdisk_begin, - initrd_size); - puts("initrd moved: "); puthex(initrd_loc); - puts(" "); puthex(initrd_loc + initrd_size); - puts("\n"); - } - } - - rec->tag = BI_FIRST; - rec->size = sizeof(struct bi_record); - rec = (struct bi_record *)((unsigned long)rec + rec->size); - - rec->tag = BI_CMD_LINE; - memcpy( (char *)rec->data, cmd_line, strlen(cmd_line)+1); - rec->size = sizeof(struct bi_record) + strlen(cmd_line) + 1; - rec = (struct bi_record *)((unsigned long)rec + rec->size); - - if ( initrd_size ) { - rec->tag = BI_INITRD; - rec->data[0] = initrd_loc; - rec->data[1] = initrd_size; - rec->size = sizeof(struct bi_record) + 2 * - sizeof(unsigned long); - rec = (struct bi_record *)((unsigned long)rec + - rec->size); - } - - rec->tag = BI_LAST; - rec->size = sizeof(struct bi_record); - rec = (struct bi_record *)((unsigned long)rec + rec->size); - } - puts("Now booting the kernel\n"); -#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) - serial_close(com_port); -#endif - - return (unsigned long)hold_residual; -} diff --git a/arch/ppc/boot/simple/misc-ev64260.c b/arch/ppc/boot/simple/misc-ev64260.c deleted file mode 100644 index 0b3978632aca..000000000000 --- a/arch/ppc/boot/simple/misc-ev64260.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Host bridge init code for the Marvell/Galileo EV-64260-BP evaluation board - * with a GT64260 onboard. - * - * Author: Mark A. Greer - * - * 2001 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_MPSC_CONSOLE -extern u32 mv64x60_console_baud; -extern u32 mv64x60_mpsc_clk_src; -extern u32 mv64x60_mpsc_clk_freq; -#endif - -void -mv64x60_board_init(void __iomem *old_base, void __iomem *new_base) -{ - u32 p, v; - - /* DINK doesn't enable 745x timebase, so enable here (Adrian Cox) */ - p = mfspr(SPRN_PVR); - p >>= 16; - - /* Reasonable SWAG at a 745x PVR value */ - if (((p & 0xfff0) == 0x8000) && (p != 0x800c)) { - v = mfspr(SPRN_HID0); - v |= HID0_TBEN; - mtspr(SPRN_HID0, v); - } - -#ifdef CONFIG_SERIAL_8250_CONSOLE - /* - * Change device bus 2 window so that bootoader can do I/O thru - * 8250/16550 UART that's mapped in that window. - */ - out_le32(new_base + MV64x60_CPU2DEV_2_BASE, EV64260_UART_BASE >> 20); - out_le32(new_base + MV64x60_CPU2DEV_2_SIZE, EV64260_UART_END >> 20); - __asm__ __volatile__("sync"); -#elif defined(CONFIG_SERIAL_MPSC_CONSOLE) - mv64x60_console_baud = EV64260_DEFAULT_BAUD; - mv64x60_mpsc_clk_src = EV64260_MPSC_CLK_SRC; - mv64x60_mpsc_clk_freq = EV64260_MPSC_CLK_FREQ; -#endif -} diff --git a/arch/ppc/boot/simple/misc-ev64360.c b/arch/ppc/boot/simple/misc-ev64360.c deleted file mode 100644 index 96eaebb78df5..000000000000 --- a/arch/ppc/boot/simple/misc-ev64360.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2005 Lee Nicks - * - * Based on arch/ppc/boot/simple/misc-katana.c from: - * Mark A. Greer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#include -#include -#include -#include - -extern u32 mv64x60_console_baud; -extern u32 mv64x60_mpsc_clk_src; -extern u32 mv64x60_mpsc_clk_freq; - -/* Not in the kernel so won't include kernel.h to get its 'min' definition */ -#ifndef min -#define min(a,b) (((a) < (b)) ? (a) : (b)) -#endif - -void -mv64x60_board_init(void __iomem *old_base, void __iomem *new_base) -{ - mv64x60_console_baud = EV64360_DEFAULT_BAUD; - mv64x60_mpsc_clk_src = EV64360_MPSC_CLK_SRC; - mv64x60_mpsc_clk_freq = EV64360_MPSC_CLK_FREQ; -} diff --git a/arch/ppc/boot/simple/misc-katana.c b/arch/ppc/boot/simple/misc-katana.c deleted file mode 100644 index 79a1bbcbc6c5..000000000000 --- a/arch/ppc/boot/simple/misc-katana.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Set up MPSC values to bootwrapper can prompt user. - * - * Author: Mark A. Greer - * - * 2004 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include - -extern u32 mv64x60_console_baud; -extern u32 mv64x60_mpsc_clk_src; -extern u32 mv64x60_mpsc_clk_freq; - -/* Not in the kernel so won't include kernel.h to get its 'min' definition */ -#ifndef min -#define min(a,b) (((a) < (b)) ? (a) : (b)) -#endif - -unsigned long mv64360_get_mem_size(void); - -void -mv64x60_board_init(void __iomem *old_base, void __iomem *new_base) -{ - mv64x60_console_baud = KATANA_DEFAULT_BAUD; - mv64x60_mpsc_clk_src = KATANA_MPSC_CLK_SRC; - mv64x60_mpsc_clk_freq = - min(katana_bus_freq((void __iomem *)KATANA_CPLD_BASE), - MV64x60_TCLK_FREQ_MAX); -} - -unsigned long -get_mem_size(void) -{ - return mv64360_get_mem_size(); -} diff --git a/arch/ppc/boot/simple/misc-mv64x60.c b/arch/ppc/boot/simple/misc-mv64x60.c deleted file mode 100644 index 28b3108083ed..000000000000 --- a/arch/ppc/boot/simple/misc-mv64x60.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Relocate bridge's register base and call board specific routine. - * - * Author: Mark A. Greer - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include - -extern struct bi_record *decompress_kernel(unsigned long load_addr, - int num_words, unsigned long cksum); - - -u32 size_reg[MV64x60_CPU2MEM_WINDOWS] = { - MV64x60_CPU2MEM_0_SIZE, MV64x60_CPU2MEM_1_SIZE, - MV64x60_CPU2MEM_2_SIZE, MV64x60_CPU2MEM_3_SIZE -}; - -/* Read mem ctlr to get the amount of mem in system */ -unsigned long -mv64360_get_mem_size(void) -{ - u32 enables, i, v; - u32 mem = 0; - - enables = in_le32((void __iomem *)CONFIG_MV64X60_NEW_BASE + - MV64360_CPU_BAR_ENABLE) & 0xf; - - for (i=0; i> (32 - bits)); - out_le32(old_base + MV64x60_INTERNAL_SPACE_DECODE, b); - - __asm__ __volatile__("sync"); - - /* Wait for change to happen (in accordance with the manual) */ - while (in_le32(new_base + MV64x60_INTERNAL_SPACE_DECODE) != b); - } -} - -void __attribute__ ((weak)) -mv64x60_board_init(void __iomem *old_base, void __iomem *new_base) -{ -} - -void * -load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, - void *ign1, void *ign2) -{ - mv64x60_move_base((void __iomem *)CONFIG_MV64X60_BASE, - (void __iomem *)CONFIG_MV64X60_NEW_BASE); - mv64x60_board_init((void __iomem *)CONFIG_MV64X60_BASE, - (void __iomem *)CONFIG_MV64X60_NEW_BASE); - return decompress_kernel(load_addr, num_words, cksum); -} diff --git a/arch/ppc/boot/simple/misc-prep.c b/arch/ppc/boot/simple/misc-prep.c deleted file mode 100644 index 0086e1cfb48c..000000000000 --- a/arch/ppc/boot/simple/misc-prep.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Maintainer: Tom Rini - * - * In the past: Gary Thomas, Cort Dougan - */ - -#include -#include -#include -#include -#include -#include "mpc10x.h" -#include "of1275.h" -#include "nonstdio.h" - -extern int keyb_present; /* keyboard controller is present by default */ -RESIDUAL hold_resid_buf; -RESIDUAL *hold_residual = &hold_resid_buf; -static void *OFW_interface; /* Pointer to OF, if available. */ - -#ifdef CONFIG_VGA_CONSOLE -char *vidmem = (char *)0xC00B8000; -int lines = 25, cols = 80; -int orig_x, orig_y = 24; -#endif /* CONFIG_VGA_CONSOLE */ - -extern int CRT_tstc(void); -extern int vga_init(unsigned char *ISA_mem); -extern void gunzip(void *, int, unsigned char *, int *); -extern unsigned long serial_init(int chan, void *ignored); -extern void serial_fixups(void); -extern struct bi_record *decompress_kernel(unsigned long load_addr, - int num_words, unsigned long cksum); -extern void disable_6xx_mmu(void); -extern unsigned long mpc10x_get_mem_size(void); - -static void -writel(unsigned int val, unsigned int address) -{ - /* Ensure I/O operations complete */ - __asm__ volatile("eieio"); - *(unsigned int *)address = cpu_to_le32(val); -} - -#define PCI_CFG_ADDR(dev,off) ((0x80<<24) | (dev<<8) | (off&0xfc)) -#define PCI_CFG_DATA(off) (MPC10X_MAPA_CNFG_DATA+(off&3)) - -static void -pci_read_config_32(unsigned char devfn, - unsigned char offset, - unsigned int *val) -{ - /* Ensure I/O operations complete */ - __asm__ volatile("eieio"); - *(unsigned int *)PCI_CFG_ADDR(devfn,offset) = - cpu_to_le32(MPC10X_MAPA_CNFG_ADDR); - /* Ensure I/O operations complete */ - __asm__ volatile("eieio"); - *val = le32_to_cpu(*(unsigned int *)PCI_CFG_DATA(offset)); - return; -} - -#ifdef CONFIG_VGA_CONSOLE -void -scroll(void) -{ - int i; - - memcpy ( vidmem, vidmem + cols * 2, ( lines - 1 ) * cols * 2 ); - for ( i = ( lines - 1 ) * cols * 2; i < lines * cols * 2; i += 2 ) - vidmem[i] = ' '; -} -#endif /* CONFIG_VGA_CONSOLE */ - -unsigned long -load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, - RESIDUAL *residual, void *OFW) -{ - int start_multi = 0; - unsigned int pci_viddid, pci_did, tulip_pci_base, tulip_base; - - /* If we have Open Firmware, initialise it immediately */ - if (OFW) { - OFW_interface = OFW; - ofinit(OFW_interface); - } - - board_isa_init(); -#if defined(CONFIG_VGA_CONSOLE) - vga_init((unsigned char *)0xC0000000); -#endif /* CONFIG_VGA_CONSOLE */ - - if (residual) { - /* Is this Motorola PPCBug? */ - if ((1 & residual->VitalProductData.FirmwareSupports) && - (1 == residual->VitalProductData.FirmwareSupplier)) { - unsigned char base_mod; - unsigned char board_type = inb(0x801) & 0xF0; - - /* - * Reset the onboard 21x4x Ethernet - * Motorola Ethernet is at IDSEL 14 (devfn 0x70) - */ - pci_read_config_32(0x70, 0x00, &pci_viddid); - pci_did = (pci_viddid & 0xffff0000) >> 16; - /* Be sure we've really found a 21x4x chip */ - if (((pci_viddid & 0xffff) == PCI_VENDOR_ID_DEC) && - ((pci_did == PCI_DEVICE_ID_DEC_TULIP_FAST) || - (pci_did == PCI_DEVICE_ID_DEC_TULIP) || - (pci_did == PCI_DEVICE_ID_DEC_TULIP_PLUS) || - (pci_did == PCI_DEVICE_ID_DEC_21142))) { - pci_read_config_32(0x70, - 0x10, - &tulip_pci_base); - /* Get the physical base address */ - tulip_base = - (tulip_pci_base & ~0x03UL) + 0x80000000; - /* Strobe the 21x4x reset bit in CSR0 */ - writel(0x1, tulip_base); - } - - /* If this is genesis 2 board then check for no - * keyboard controller and more than one processor. - */ - if (board_type == 0xe0) { - base_mod = inb(0x803); - /* if a MVME2300/2400 or a Sitka then no keyboard */ - if((base_mod == 0xFA) || (base_mod == 0xF9) || - (base_mod == 0xE1)) { - keyb_present = 0; /* no keyboard */ - } - } - /* If this is a multiprocessor system then - * park the other processor so that the - * kernel knows where to find them. - */ - if (residual->MaxNumCpus > 1) - start_multi = 1; - } - memcpy(hold_residual,residual,sizeof(RESIDUAL)); - } - - /* Call decompress_kernel */ - decompress_kernel(load_addr, num_words, cksum); - - if (start_multi) { - residual->VitalProductData.SmpIar = (unsigned long)0xc0; - residual->Cpus[1].CpuState = CPU_GOOD; - hold_residual->VitalProductData.Reserved5 = 0xdeadbeef; - } - - /* Now go and clear out the BATs and ensure that our MSR is - * correct .*/ - disable_6xx_mmu(); - - /* Make r3 be a pointer to the residual data. */ - return (unsigned long)hold_residual; -} - -unsigned long -get_mem_size(void) -{ - unsigned int pci_viddid, pci_did; - - /* First, figure out what kind of host bridge we are on. If it's - * an MPC10x, we can ask it directly how much memory it has. - * Otherwise, see if the residual data has anything. This isn't - * the best way, but it can be the only way. If there's nothing, - * assume 32MB. -- Tom. - */ - /* See what our host bridge is. */ - pci_read_config_32(0x00, 0x00, &pci_viddid); - pci_did = (pci_viddid & 0xffff0000) >> 16; - /* See if we are on an MPC10x. */ - if (((pci_viddid & 0xffff) == PCI_VENDOR_ID_MOTOROLA) - && ((pci_did == PCI_DEVICE_ID_MOTOROLA_MPC105) - || (pci_did == PCI_DEVICE_ID_MOTOROLA_MPC106) - || (pci_did == PCI_DEVICE_ID_MOTOROLA_MPC107))) - return mpc10x_get_mem_size(); - /* If it's not, see if we have anything in the residual data. */ - else if (hold_residual && hold_residual->TotalMemory) - return hold_residual->TotalMemory; - else if (OFW_interface) { - /* - * This is a 'best guess' check. We want to make sure - * we don't try this on a PReP box without OF - * -- Cort - */ - while (OFW_interface) - { - phandle dev_handle; - int mem_info[2]; - - /* get handle to memory description */ - if (!(dev_handle = finddevice("/memory@0"))) - break; - - /* get the info */ - if (getprop(dev_handle, "reg", mem_info, - sizeof(mem_info)) != 8) - break; - - return mem_info[1]; - } - } - - /* Fall back to hard-coding 32MB. */ - return 32*1024*1024; -} diff --git a/arch/ppc/boot/simple/misc-radstone_ppc7d.c b/arch/ppc/boot/simple/misc-radstone_ppc7d.c deleted file mode 100644 index 0f302ea9c3d1..000000000000 --- a/arch/ppc/boot/simple/misc-radstone_ppc7d.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Misc data for Radstone PPC7D board. - * - * Author: James Chapman - */ - -#include -#include - -#if defined(CONFIG_SERIAL_MPSC_CONSOLE) -extern u32 mv64x60_console_baud; -extern u32 mv64x60_mpsc_clk_src; -extern u32 mv64x60_mpsc_clk_freq; -#endif - -void -mv64x60_board_init(void __iomem *old_base, void __iomem *new_base) -{ -#if defined(CONFIG_SERIAL_MPSC_CONSOLE) - mv64x60_console_baud = PPC7D_DEFAULT_BAUD; - mv64x60_mpsc_clk_src = PPC7D_MPSC_CLK_SRC; - mv64x60_mpsc_clk_freq = PPC7D_MPSC_CLK_FREQ; -#endif -} diff --git a/arch/ppc/boot/simple/misc-spruce.c b/arch/ppc/boot/simple/misc-spruce.c deleted file mode 100644 index 5b3a6c6f113b..000000000000 --- a/arch/ppc/boot/simple/misc-spruce.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Misc. bootloader code for IBM Spruce reference platform - * - * Authors: Johnnie Peters - * Matt Porter - * - * Derived from arch/ppc/boot/prep/misc.c - * - * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include - -#include - -extern unsigned long decompress_kernel(unsigned long load_addr, int num_words, - unsigned long cksum); - -/* Define some important locations of the Spruce. */ -#define SPRUCE_PCI_CONFIG_ADDR 0xfec00000 -#define SPRUCE_PCI_CONFIG_DATA 0xfec00004 - -/* PCI configuration space access routines. */ -unsigned int *pci_config_address = (unsigned int *)SPRUCE_PCI_CONFIG_ADDR; -unsigned char *pci_config_data = (unsigned char *)SPRUCE_PCI_CONFIG_DATA; - -void cpc700_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned char *val) -{ - out_le32(pci_config_address, - (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000)); - - *val= (in_le32((unsigned *)pci_config_data) >> (8 * (offset & 3))) & 0xff; -} - -void cpc700_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned char val) -{ - out_le32(pci_config_address, - (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000)); - - out_8(pci_config_data + (offset&3), val); -} - -void cpc700_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned short *val) -{ - out_le32(pci_config_address, - (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000)); - - *val= in_le16((unsigned short *)(pci_config_data + (offset&3))); -} - -void cpc700_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned short val) -{ - out_le32(pci_config_address, - (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000)); - - out_le16((unsigned short *)(pci_config_data + (offset&3)), val); -} - -void cpc700_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned int *val) -{ - out_le32(pci_config_address, - (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000)); - - *val= in_le32((unsigned *)pci_config_data); -} - -void cpc700_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned int val) -{ - out_le32(pci_config_address, - (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000)); - - out_le32((unsigned *)pci_config_data, val); -} - -#define PCNET32_WIO_RDP 0x10 -#define PCNET32_WIO_RAP 0x12 -#define PCNET32_WIO_RESET 0x14 - -#define PCNET32_DWIO_RDP 0x10 -#define PCNET32_DWIO_RAP 0x14 -#define PCNET32_DWIO_RESET 0x18 - -/* Processor interface config register access */ -#define PIFCFGADDR 0xff500000 -#define PIFCFGDATA 0xff500004 - -#define PLBMIFOPT 0x18 /* PLB Master Interface Options */ - -#define MEM_MBEN 0x24 -#define MEM_TYPE 0x28 -#define MEM_B1SA 0x3c -#define MEM_B1EA 0x5c -#define MEM_B2SA 0x40 -#define MEM_B2EA 0x60 - -unsigned long -get_mem_size(void) -{ - int loop; - unsigned long mem_size = 0; - unsigned long mem_mben; - unsigned long mem_type; - unsigned long mem_start; - unsigned long mem_end; - volatile int *mem_addr = (int *)0xff500008; - volatile int *mem_data = (int *)0xff50000c; - - /* Get the size of memory from the memory controller. */ - *mem_addr = MEM_MBEN; - asm("sync"); - mem_mben = *mem_data; - asm("sync"); - for(loop = 0; loop < 1000; loop++); - - *mem_addr = MEM_TYPE; - asm("sync"); - mem_type = *mem_data; - asm("sync"); - for(loop = 0; loop < 1000; loop++); - - *mem_addr = MEM_TYPE; - /* Confirm bank 1 has DRAM memory */ - if ((mem_mben & 0x40000000) && - ((mem_type & 0x30000000) == 0x10000000)) { - *mem_addr = MEM_B1SA; - asm("sync"); - mem_start = *mem_data; - asm("sync"); - for(loop = 0; loop < 1000; loop++); - - *mem_addr = MEM_B1EA; - asm("sync"); - mem_end = *mem_data; - asm("sync"); - for(loop = 0; loop < 1000; loop++); - - mem_size = mem_end - mem_start + 0x100000; - } - - /* Confirm bank 2 has DRAM memory */ - if ((mem_mben & 0x20000000) && - ((mem_type & 0xc000000) == 0x4000000)) { - *mem_addr = MEM_B2SA; - asm("sync"); - mem_start = *mem_data; - asm("sync"); - for(loop = 0; loop < 1000; loop++); - - *mem_addr = MEM_B2EA; - asm("sync"); - mem_end = *mem_data; - asm("sync"); - for(loop = 0; loop < 1000; loop++); - - mem_size += mem_end - mem_start + 0x100000; - } - return mem_size; -} - -unsigned long -load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, - void *ign1, void *ign2) -{ - int csr0; - int csr_id; - int pci_devfn; - int found_multi = 0; - unsigned short vendor; - unsigned short device; - unsigned short command; - unsigned char header_type; - unsigned int bar0; - volatile int *pif_addr = (int *)0xff500000; - volatile int *pif_data = (int *)0xff500004; - - /* - * Gah, these firmware guys need to learn that hardware - * byte swapping is evil! Disable all hardware byte - * swapping so it doesn't hurt anyone. - */ - *pif_addr = PLBMIFOPT; - asm("sync"); - *pif_data = 0x00000000; - asm("sync"); - - /* Search out and turn off the PcNet ethernet boot device. */ - for (pci_devfn = 1; pci_devfn < 0xff; pci_devfn++) { - if (PCI_FUNC(pci_devfn) && !found_multi) - continue; - - cpc700_pcibios_read_config_byte(0, pci_devfn, - PCI_HEADER_TYPE, &header_type); - - if (!PCI_FUNC(pci_devfn)) - found_multi = header_type & 0x80; - - cpc700_pcibios_read_config_word(0, pci_devfn, PCI_VENDOR_ID, - &vendor); - - if (vendor != 0xffff) { - cpc700_pcibios_read_config_word(0, pci_devfn, - PCI_DEVICE_ID, &device); - - /* If this PCI device is the Lance PCNet board then turn it off */ - if ((vendor == PCI_VENDOR_ID_AMD) && - (device == PCI_DEVICE_ID_AMD_LANCE)) { - - /* Turn on I/O Space on the board. */ - cpc700_pcibios_read_config_word(0, pci_devfn, - PCI_COMMAND, &command); - command |= 0x1; - cpc700_pcibios_write_config_word(0, pci_devfn, - PCI_COMMAND, command); - - /* Get the I/O space address */ - cpc700_pcibios_read_config_dword(0, pci_devfn, - PCI_BASE_ADDRESS_0, &bar0); - bar0 &= 0xfffffffe; - - /* Reset the PCNet Board */ - inl (bar0+PCNET32_DWIO_RESET); - inw (bar0+PCNET32_WIO_RESET); - - /* First do a work oriented read of csr0. If the value is - * 4 then this is the correct mode to access the board. - * If not try a double word ortiented read. - */ - outw(0, bar0 + PCNET32_WIO_RAP); - csr0 = inw(bar0 + PCNET32_WIO_RDP); - - if (csr0 == 4) { - /* Check the Chip id register */ - outw(88, bar0 + PCNET32_WIO_RAP); - csr_id = inw(bar0 + PCNET32_WIO_RDP); - - if (csr_id) { - /* This is the valid mode - set the stop bit */ - outw(0, bar0 + PCNET32_WIO_RAP); - outw(csr0, bar0 + PCNET32_WIO_RDP); - } - } else { - outl(0, bar0 + PCNET32_DWIO_RAP); - csr0 = inl(bar0 + PCNET32_DWIO_RDP); - if (csr0 == 4) { - /* Check the Chip id register */ - outl(88, bar0 + PCNET32_WIO_RAP); - csr_id = inl(bar0 + PCNET32_WIO_RDP); - - if (csr_id) { - /* This is the valid mode - set the stop bit*/ - outl(0, bar0 + PCNET32_WIO_RAP); - outl(csr0, bar0 + PCNET32_WIO_RDP); - } - } - } - } - } - } - - return decompress_kernel(load_addr, num_words, cksum); -} diff --git a/arch/ppc/boot/simple/misc.c b/arch/ppc/boot/simple/misc.c deleted file mode 100644 index c3d3305eb5ca..000000000000 --- a/arch/ppc/boot/simple/misc.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Misc. bootloader code for many machines. This assumes you have are using - * a 6xx/7xx/74xx CPU in your machine. This assumes the chunk of memory - * below 8MB is free. Finally, it assumes you have a NS16550-style uart for - * your serial console. If a machine meets these requirements, it can quite - * likely use this code during boot. - * - * Author: Matt Porter - * Derived from arch/ppc/boot/prep/misc.c - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include - -#include -#include -#include -#ifdef CONFIG_4xx -#include -#endif -#include - -#include "nonstdio.h" - -/* Default cmdline */ -#ifdef CONFIG_CMDLINE -#define CMDLINE CONFIG_CMDLINE -#else -#define CMDLINE "" -#endif - -/* Keyboard (and VGA console)? */ -#ifdef CONFIG_VGA_CONSOLE -#define HAS_KEYB 1 -#else -#define HAS_KEYB 0 -#endif - -/* Will / Can the user give input? - */ -#if (defined(CONFIG_SERIAL_8250_CONSOLE) \ - || defined(CONFIG_VGA_CONSOLE) \ - || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \ - || defined(CONFIG_SERIAL_MPSC_CONSOLE)) -#define INTERACTIVE_CONSOLE 1 -#endif - -char *avail_ram; -char *end_avail; -char *zimage_start; -char cmd_preset[] = CMDLINE; -char cmd_buf[256]; -char *cmd_line = cmd_buf; -int keyb_present = HAS_KEYB; -int zimage_size; - -unsigned long com_port; -unsigned long initrd_size = 0; - -/* The linker tells us various locations in the image */ -extern char __image_begin, __image_end; -extern char __ramdisk_begin, __ramdisk_end; -extern char _end[]; -/* Original location */ -extern unsigned long start; - -extern int CRT_tstc(void); -extern unsigned long serial_init(int chan, void *ignored); -extern void serial_close(unsigned long com_port); -extern void gunzip(void *, int, unsigned char *, int *); -extern void serial_fixups(void); - -/* Allow get_mem_size to be hooked into. This is the default. */ -unsigned long __attribute__ ((weak)) -get_mem_size(void) -{ - return 0; -} - -#if defined(CONFIG_40x) -#define PPC4xx_EMAC0_MR0 EMAC0_BASE -#endif - -#if defined(CONFIG_44x) && defined(PPC44x_EMAC0_MR0) -#define PPC4xx_EMAC0_MR0 PPC44x_EMAC0_MR0 -#endif - -struct bi_record * -decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum) -{ -#ifdef INTERACTIVE_CONSOLE - int timer = 0; - char ch; -#endif - char *cp; - struct bi_record *rec; - unsigned long initrd_loc = 0, TotalMemory = 0; - -#if defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_SERIAL_MPSC_CONSOLE) - com_port = serial_init(0, NULL); -#endif - -#if defined(PPC4xx_EMAC0_MR0) - /* Reset MAL */ - mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); - /* Wait for reset */ - while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; - /* Reset EMAC */ - *(volatile unsigned long *)PPC4xx_EMAC0_MR0 = 0x20000000; - __asm__ __volatile__("eieio"); -#endif - - /* - * Call get_mem_size(), which is memory controller dependent, - * and we must have the correct file linked in here. - */ - TotalMemory = get_mem_size(); - - /* assume the chunk below 8M is free */ - end_avail = (char *)0x00800000; - - /* - * Reveal where we were loaded at and where we - * were relocated to. - */ - puts("loaded at: "); puthex(load_addr); - puts(" "); puthex((unsigned long)(load_addr + (4*num_words))); - puts("\n"); - if ( (unsigned long)load_addr != (unsigned long)&start ) - { - puts("relocated to: "); puthex((unsigned long)&start); - puts(" "); - puthex((unsigned long)((unsigned long)&start + (4*num_words))); - puts("\n"); - } - - /* - * We link ourself to 0x00800000. When we run, we relocate - * ourselves there. So we just need __image_begin for the - * start. -- Tom - */ - zimage_start = (char *)(unsigned long)(&__image_begin); - zimage_size = (unsigned long)(&__image_end) - - (unsigned long)(&__image_begin); - - initrd_size = (unsigned long)(&__ramdisk_end) - - (unsigned long)(&__ramdisk_begin); - - /* - * The zImage and initrd will be between start and _end, so they've - * already been moved once. We're good to go now. -- Tom - */ - avail_ram = (char *)PAGE_ALIGN((unsigned long)_end); - puts("zimage at: "); puthex((unsigned long)zimage_start); - puts(" "); puthex((unsigned long)(zimage_size+zimage_start)); - puts("\n"); - - if ( initrd_size ) { - puts("initrd at: "); - puthex((unsigned long)(&__ramdisk_begin)); - puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n"); - } - -#ifndef CONFIG_40x /* don't overwrite the 40x image located at 0x00400000! */ - avail_ram = (char *)0x00400000; -#endif - end_avail = (char *)0x00800000; - puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" "); - puthex((unsigned long)end_avail); puts("\n"); - - if (keyb_present) - CRT_tstc(); /* Forces keyboard to be initialized */ - - /* Display standard Linux/PPC boot prompt for kernel args */ - puts("\nLinux/PPC load: "); - cp = cmd_line; - memcpy (cmd_line, cmd_preset, sizeof(cmd_preset)); - while ( *cp ) putc(*cp++); - -#ifdef INTERACTIVE_CONSOLE - /* - * If they have a console, allow them to edit the command line. - * Otherwise, don't bother wasting the five seconds. - */ - while (timer++ < 5*1000) { - if (tstc()) { - while ((ch = getc()) != '\n' && ch != '\r') { - /* Test for backspace/delete */ - if (ch == '\b' || ch == '\177') { - if (cp != cmd_line) { - cp--; - puts("\b \b"); - } - /* Test for ^x/^u (and wipe the line) */ - } else if (ch == '\030' || ch == '\025') { - while (cp != cmd_line) { - cp--; - puts("\b \b"); - } - } else { - *cp++ = ch; - putc(ch); - } - } - break; /* Exit 'timer' loop */ - } - udelay(1000); /* 1 msec */ - } - *cp = 0; -#endif - puts("\n"); - - puts("Uncompressing Linux..."); - gunzip(NULL, 0x400000, zimage_start, &zimage_size); - puts("done.\n"); - - /* get the bi_rec address */ - rec = bootinfo_addr(zimage_size); - - /* We need to make sure that the initrd and bi_recs do not - * overlap. */ - if ( initrd_size ) { - unsigned long rec_loc = (unsigned long) rec; - initrd_loc = (unsigned long)(&__ramdisk_begin); - /* If the bi_recs are in the middle of the current - * initrd, move the initrd to the next MB - * boundary. */ - if ((rec_loc > initrd_loc) && - ((initrd_loc + initrd_size) > rec_loc)) { - initrd_loc = _ALIGN((unsigned long)(zimage_size) - + (2 << 20) - 1, (2 << 20)); - memmove((void *)initrd_loc, &__ramdisk_begin, - initrd_size); - puts("initrd moved: "); puthex(initrd_loc); - puts(" "); puthex(initrd_loc + initrd_size); - puts("\n"); - } - } - - bootinfo_init(rec); - if ( TotalMemory ) - bootinfo_append(BI_MEMSIZE, sizeof(int), (void*)&TotalMemory); - - bootinfo_append(BI_CMD_LINE, strlen(cmd_line)+1, (void*)cmd_line); - - /* add a bi_rec for the initrd if it exists */ - if (initrd_size) { - unsigned long initrd[2]; - - initrd[0] = initrd_loc; - initrd[1] = initrd_size; - - bootinfo_append(BI_INITRD, sizeof(initrd), &initrd); - } - puts("Now booting the kernel\n"); - serial_close(com_port); - - return rec; -} - -void __attribute__ ((weak)) -board_isa_init(void) -{ -} - -/* Allow decompress_kernel to be hooked into. This is the default. */ -void * __attribute__ ((weak)) -load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, - void *ign1, void *ign2) -{ - board_isa_init(); - return decompress_kernel(load_addr, num_words, cksum); -} diff --git a/arch/ppc/boot/simple/mpc10x_memory.c b/arch/ppc/boot/simple/mpc10x_memory.c deleted file mode 100644 index 8da8f576031d..000000000000 --- a/arch/ppc/boot/simple/mpc10x_memory.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * A routine to find out how much memory the machine has. - * - * Based on: - * arch/ppc/kernel/mpc10x_common.c - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include "mpc10x.h" - -/* - * *** WARNING - A BAT MUST be set to access the PCI config addr/data regs *** - */ - -/* - * PCI config space macros, similar to indirect_xxx and early_xxx macros. - * We assume bus 0. - */ -#define MPC10X_CFG_read(val, addr, type, op) *val = op((type)(addr)) -#define MPC10X_CFG_write(val, addr, type, op) op((type *)(addr), (val)) - -#define MPC10X_PCI_OP(rw, size, type, op, mask) \ -static void \ -mpc10x_##rw##_config_##size(unsigned int __iomem *cfg_addr, \ - unsigned int *cfg_data, int devfn, int offset, \ - type val) \ -{ \ - out_be32(cfg_addr, \ - ((offset & 0xfc) << 24) | (devfn << 16) \ - | (0 << 8) | 0x80); \ - MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op); \ - return; \ -} - -MPC10X_PCI_OP(read, byte, u8 *, in_8, 3) -MPC10X_PCI_OP(read, dword, u32 *, in_le32, 0) - -/* - * Read the memory controller registers to determine the amount of memory in - * the system. This assumes that the firmware has correctly set up the memory - * controller registers. On CONFIG_PPC_PREP, we know we are being called - * under a PReP memory map. On all other machines, we assume we are under - * a CHRP memory map. Further, on CONFIG_PPC_PREP we must rename - * this function. - */ -#ifdef CONFIG_PPC_PREP -#define get_mem_size mpc10x_get_mem_size -#endif -unsigned long -get_mem_size(void) -{ - unsigned int *config_addr, *config_data, val; - unsigned long start, end, total, offset; - int i; - unsigned char bank_enables; - -#ifdef CONFIG_PPC_PREP - config_addr = (unsigned int *)MPC10X_MAPA_CNFG_ADDR; - config_data = (unsigned int *)MPC10X_MAPA_CNFG_DATA; -#else - config_addr = (unsigned int *)MPC10X_MAPB_CNFG_ADDR; - config_data = (unsigned int *)MPC10X_MAPB_CNFG_DATA; -#endif - - mpc10x_read_config_byte(config_addr, config_data, PCI_DEVFN(0,0), - MPC10X_MCTLR_MEM_BANK_ENABLES, &bank_enables); - - total = 0; - - for (i = 0; i < 8; i++) { - if (bank_enables & (1 << i)) { - offset = MPC10X_MCTLR_MEM_START_1 + ((i > 3) ? 4 : 0); - mpc10x_read_config_dword(config_addr, config_data, - PCI_DEVFN(0,0), offset, &val); - start = (val >> ((i & 3) << 3)) & 0xff; - - offset = MPC10X_MCTLR_EXT_MEM_START_1 + ((i>3) ? 4 : 0); - mpc10x_read_config_dword(config_addr, config_data, - PCI_DEVFN(0,0), offset, &val); - val = (val >> ((i & 3) << 3)) & 0x03; - start = (val << 28) | (start << 20); - - offset = MPC10X_MCTLR_MEM_END_1 + ((i > 3) ? 4 : 0); - mpc10x_read_config_dword(config_addr, config_data, - PCI_DEVFN(0,0), offset, &val); - end = (val >> ((i & 3) << 3)) & 0xff; - - offset = MPC10X_MCTLR_EXT_MEM_END_1 + ((i > 3) ? 4 : 0); - mpc10x_read_config_dword(config_addr, config_data, - PCI_DEVFN(0,0), offset, &val); - val = (val >> ((i & 3) << 3)) & 0x03; - end = (val << 28) | (end << 20) | 0xfffff; - - total += (end - start + 1); - } - } - - return total; -} diff --git a/arch/ppc/boot/simple/mpc52xx_tty.c b/arch/ppc/boot/simple/mpc52xx_tty.c deleted file mode 100644 index 6955891fb031..000000000000 --- a/arch/ppc/boot/simple/mpc52xx_tty.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Minimal serial functions needed to send messages out a MPC52xx - * Programmable Serial Controller (PSC). - * - * Author: Dale Farnsworth - * - * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include - - -#ifdef MPC52xx_PF_CONSOLE_PORT -#define MPC52xx_CONSOLE MPC52xx_PSCx_OFFSET(MPC52xx_PF_CONSOLE_PORT) -#define MPC52xx_PSC_CONFIG_SHIFT ((MPC52xx_PF_CONSOLE_PORT-1)<<2) -#else -#error "MPC52xx_PF_CONSOLE_PORT not defined" -#endif - -static struct mpc52xx_psc __iomem *psc = - (struct mpc52xx_psc __iomem *) MPC52xx_PA(MPC52xx_CONSOLE); - -/* The decrementer counts at the system bus clock frequency - * divided by four. The most accurate time base is connected to the - * rtc. We read the decrementer change during one rtc tick - * and multiply by 4 to get the system bus clock frequency. Since a - * rtc tick is one seconds, and that's pretty long, we change the rtc - * dividers temporarily to set them 64x faster ;) - */ -static int -mpc52xx_ipbfreq(void) -{ - struct mpc52xx_rtc __iomem *rtc = - (struct mpc52xx_rtc __iomem *) MPC52xx_PA(MPC52xx_RTC_OFFSET); - struct mpc52xx_cdm __iomem *cdm = - (struct mpc52xx_cdm __iomem *) MPC52xx_PA(MPC52xx_CDM_OFFSET); - int current_time, previous_time; - int tbl_start, tbl_end; - int xlbfreq, ipbfreq; - - out_be32(&rtc->dividers, 0x8f1f0000); /* Set RTC 64x faster */ - previous_time = in_be32(&rtc->time); - while ((current_time = in_be32(&rtc->time)) == previous_time) ; - tbl_start = get_tbl(); - previous_time = current_time; - while ((current_time = in_be32(&rtc->time)) == previous_time) ; - tbl_end = get_tbl(); - out_be32(&rtc->dividers, 0xffff0000); /* Restore RTC */ - - xlbfreq = (tbl_end - tbl_start) << 8; - ipbfreq = (in_8(&cdm->ipb_clk_sel) & 1) ? xlbfreq / 2 : xlbfreq; - - return ipbfreq; -} - -unsigned long -serial_init(int ignored, void *ignored2) -{ - struct mpc52xx_gpio __iomem *gpio = - (struct mpc52xx_gpio __iomem *) MPC52xx_PA(MPC52xx_GPIO_OFFSET); - int divisor; - int mode1; - int mode2; - u32 val32; - - static int been_here = 0; - - if (been_here) - return 0; - - been_here = 1; - - val32 = in_be32(&gpio->port_config); - val32 &= ~(0x7 << MPC52xx_PSC_CONFIG_SHIFT); - val32 |= MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD - << MPC52xx_PSC_CONFIG_SHIFT; - out_be32(&gpio->port_config, val32); - - out_8(&psc->command, MPC52xx_PSC_RST_TX - | MPC52xx_PSC_RX_DISABLE | MPC52xx_PSC_TX_ENABLE); - out_8(&psc->command, MPC52xx_PSC_RST_RX); - - out_be32(&psc->sicr, 0x0); - out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); - out_be16(&psc->tfalarm, 0xf8); - - out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1 - | MPC52xx_PSC_RX_ENABLE - | MPC52xx_PSC_TX_ENABLE); - - divisor = ((mpc52xx_ipbfreq() - / (CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD * 16)) + 1) >> 1; - - mode1 = MPC52xx_PSC_MODE_8_BITS | MPC52xx_PSC_MODE_PARNONE - | MPC52xx_PSC_MODE_ERR; - mode2 = MPC52xx_PSC_MODE_ONE_STOP; - - out_8(&psc->ctur, divisor>>8); - out_8(&psc->ctlr, divisor); - out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); - out_8(&psc->mode, mode1); - out_8(&psc->mode, mode2); - - return 0; /* ignored */ -} - -void -serial_putc(void *ignored, const char c) -{ - serial_init(0, NULL); - - while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP)) ; - out_8(&psc->mpc52xx_psc_buffer_8, c); - while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP)) ; -} - -char -serial_getc(void *ignored) -{ - while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY)) ; - - return in_8(&psc->mpc52xx_psc_buffer_8); -} - -int -serial_tstc(void *ignored) -{ - return (in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY) != 0; -} diff --git a/arch/ppc/boot/simple/mv64x60_tty.c b/arch/ppc/boot/simple/mv64x60_tty.c deleted file mode 100644 index 8a735787a6e9..000000000000 --- a/arch/ppc/boot/simple/mv64x60_tty.c +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Bootloader version of the embedded MPSC/UART driver for the Marvell 64x60. - * Note: Due to a GT64260A erratum, DMA will be used for UART input (via SDMA). - * - * Author: Mark A. Greer - * - * 2001 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* This code assumes that the data cache has been disabled (L1, L2, L3). */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_EV64360 -#include -u32 mv64x60_console_baud = EV64360_DEFAULT_BAUD; -u32 mv64x60_mpsc_clk_src = EV64360_MPSC_CLK_SRC; /* TCLK */ -u32 mv64x60_mpsc_clk_freq = EV64360_MPSC_CLK_FREQ; -#else -u32 mv64x60_console_baud = 9600; -u32 mv64x60_mpsc_clk_src = 8; /* TCLK */ -u32 mv64x60_mpsc_clk_freq = 100000000; -#endif - -extern void udelay(long); -static void stop_dma(int chan); - -static void __iomem *mv64x60_base = (void __iomem *)CONFIG_MV64X60_NEW_BASE; - -struct sdma_regs { - u32 sdc; - u32 sdcm; - u32 rx_desc; - u32 rx_buf_ptr; - u32 scrdp; - u32 tx_desc; - u32 sctdp; - u32 sftdp; -}; - -static struct sdma_regs sdma_regs[2]; - -#define SDMA_REGS_INIT(s, reg_base) { \ - (s)->sdc = (reg_base) + SDMA_SDC; \ - (s)->sdcm = (reg_base) + SDMA_SDCM; \ - (s)->rx_desc = (reg_base) + SDMA_RX_DESC; \ - (s)->rx_buf_ptr = (reg_base) + SDMA_RX_BUF_PTR; \ - (s)->scrdp = (reg_base) + SDMA_SCRDP; \ - (s)->tx_desc = (reg_base) + SDMA_TX_DESC; \ - (s)->sctdp = (reg_base) + SDMA_SCTDP; \ - (s)->sftdp = (reg_base) + SDMA_SFTDP; \ -} - -static u32 mpsc_base[2] = { MV64x60_MPSC_0_OFFSET, MV64x60_MPSC_1_OFFSET }; - -struct mv64x60_rx_desc { - u16 bufsize; - u16 bytecnt; - u32 cmd_stat; - u32 next_desc_ptr; - u32 buffer; -}; - -struct mv64x60_tx_desc { - u16 bytecnt; - u16 shadow; - u32 cmd_stat; - u32 next_desc_ptr; - u32 buffer; -}; - -#define MAX_RESET_WAIT 10000 -#define MAX_TX_WAIT 10000 - -#define RX_NUM_DESC 2 -#define TX_NUM_DESC 2 - -#define RX_BUF_SIZE 32 -#define TX_BUF_SIZE 32 - -static struct mv64x60_rx_desc rd[2][RX_NUM_DESC] __attribute__ ((aligned(32))); -static struct mv64x60_tx_desc td[2][TX_NUM_DESC] __attribute__ ((aligned(32))); - -static char rx_buf[2][RX_NUM_DESC * RX_BUF_SIZE] __attribute__ ((aligned(32))); -static char tx_buf[2][TX_NUM_DESC * TX_BUF_SIZE] __attribute__ ((aligned(32))); - -static int cur_rd[2] = { 0, 0 }; -static int cur_td[2] = { 0, 0 }; - -static char chan_initialized[2] = { 0, 0 }; - - -#define RX_INIT_RDP(rdp) { \ - (rdp)->bufsize = 2; \ - (rdp)->bytecnt = 0; \ - (rdp)->cmd_stat = SDMA_DESC_CMDSTAT_L | SDMA_DESC_CMDSTAT_F | \ - SDMA_DESC_CMDSTAT_O; \ -} - -#ifdef CONFIG_MV64360 -static u32 cpu2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = { - { MV64x60_CPU2MEM_0_BASE, MV64x60_CPU2MEM_0_SIZE }, - { MV64x60_CPU2MEM_1_BASE, MV64x60_CPU2MEM_1_SIZE }, - { MV64x60_CPU2MEM_2_BASE, MV64x60_CPU2MEM_2_SIZE }, - { MV64x60_CPU2MEM_3_BASE, MV64x60_CPU2MEM_3_SIZE } -}; - -static u32 com2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = { - { MV64360_MPSC2MEM_0_BASE, MV64360_MPSC2MEM_0_SIZE }, - { MV64360_MPSC2MEM_1_BASE, MV64360_MPSC2MEM_1_SIZE }, - { MV64360_MPSC2MEM_2_BASE, MV64360_MPSC2MEM_2_SIZE }, - { MV64360_MPSC2MEM_3_BASE, MV64360_MPSC2MEM_3_SIZE } -}; - -static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] = { 0xe, 0xd, 0xb, 0x7 }; -#endif - -unsigned long -serial_init(int chan, void *ignored) -{ - u32 mpsc_routing_base, sdma_base, brg_bcr, cdv; - int i; - - chan = (chan == 1); /* default to chan 0 if anything but 1 */ - - if (chan_initialized[chan]) - return chan; - - chan_initialized[chan] = 1; - - if (chan == 0) { - sdma_base = MV64x60_SDMA_0_OFFSET; - brg_bcr = MV64x60_BRG_0_OFFSET + BRG_BCR; - SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_0_OFFSET); - } else { - sdma_base = MV64x60_SDMA_1_OFFSET; - brg_bcr = MV64x60_BRG_1_OFFSET + BRG_BCR; - SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_1_OFFSET); - } - - mpsc_routing_base = MV64x60_MPSC_ROUTING_OFFSET; - - stop_dma(chan); - - /* Set up ring buffers */ - for (i=0; i= TX_NUM_DESC) - cur_td[com_port] = 0; - - *(unchar *)(tdp->buffer ^ 7) = c; - tdp->bytecnt = 1; - tdp->shadow = 1; - tdp->cmd_stat = SDMA_DESC_CMDSTAT_L | SDMA_DESC_CMDSTAT_F | - SDMA_DESC_CMDSTAT_O; - - out_le32(mv64x60_base + sdma_regs[com_port].sctdp, (int)tdp); - out_le32(mv64x60_base + sdma_regs[com_port].sftdp, (int)tdp); - out_le32(mv64x60_base + sdma_regs[com_port].sdcm, - in_le32(mv64x60_base + sdma_regs[com_port].sdcm) | - SDMA_SDCM_TXD); -} - -unsigned char -serial_getc(unsigned long com_port) -{ - struct mv64x60_rx_desc *rdp; - unchar c = '\0'; - - rdp = &rd[com_port][cur_rd[com_port]]; - - if ((rdp->cmd_stat & (SDMA_DESC_CMDSTAT_O|SDMA_DESC_CMDSTAT_ES)) == 0) { - c = *(unchar *)(rdp->buffer ^ 7); - RX_INIT_RDP(rdp); - if (++cur_rd[com_port] >= RX_NUM_DESC) - cur_rd[com_port] = 0; - } - - return c; -} - -int -serial_tstc(unsigned long com_port) -{ - struct mv64x60_rx_desc *rdp; - int loop_count = 0; - int rc = 0; - - rdp = &rd[com_port][cur_rd[com_port]]; - - /* Go through rcv descs until empty looking for one with data (no error)*/ - while (((rdp->cmd_stat & SDMA_DESC_CMDSTAT_O) == 0) && - (loop_count++ < RX_NUM_DESC)) { - - /* If there was an error, reinit the desc & continue */ - if ((rdp->cmd_stat & SDMA_DESC_CMDSTAT_ES) != 0) { - RX_INIT_RDP(rdp); - if (++cur_rd[com_port] >= RX_NUM_DESC) - cur_rd[com_port] = 0; - rdp = (struct mv64x60_rx_desc *)rdp->next_desc_ptr; - } else { - rc = 1; - break; - } - } - - return rc; -} - -void -serial_close(unsigned long com_port) -{ - stop_dma(com_port); -} diff --git a/arch/ppc/boot/simple/openbios.c b/arch/ppc/boot/simple/openbios.c deleted file mode 100644 index 6ff2701598f2..000000000000 --- a/arch/ppc/boot/simple/openbios.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2005 DENX Software Engineering - * Stefan Roese - * - * Based on original work by - * 2005 (c) SYSGO AG - g.jaeger@sysgo.com - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - */ - -#include -#include -#include -#include -#include -#ifdef CONFIG_40x -#include -#endif - -#if defined(CONFIG_BUBINGA) -#define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */ -#else -#define BOARD_INFO_VECTOR 0xFFFE0B50 -#endif - -#ifdef CONFIG_40x -/* Supply a default Ethernet address for those eval boards that don't - * ship with one. This is an address from the MBX board I have, so - * it is unlikely you will find it on your network. - */ -static ushort def_enet_addr[] = { 0x0800, 0x3e26, 0x1559 }; - -extern unsigned long timebase_period_ns; -#endif /* CONFIG_40x */ - -extern unsigned long decompress_kernel(unsigned long load_addr, int num_words, - unsigned long cksum); - -/* We need to make sure that this is before the images to ensure - * that it's in a mapped location. */ -bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot"))); -bd_t *hold_residual = &hold_resid_buf; - -typedef struct openbios_board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ -#ifdef CONFIG_405EP - unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */ -#else /* CONFIG_405EP */ - unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ -#endif /* CONFIG_405EP */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ -#ifdef CONFIG_405EP - unsigned int bi_opb_busfreq; /* OPB Bus speed, in Hz */ - unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */ -#endif /* CONFIG_405EP */ -} openbios_bd_t; - -void * -load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, - void *ign1, void *ign2) -{ -#ifdef CONFIG_40x - openbios_bd_t *openbios_bd = NULL; - openbios_bd_t *(*get_board_info)(void) = - (openbios_bd_t *(*)(void))(*(unsigned long *)BOARD_INFO_VECTOR); - - /* - * On 40x platforms we not only need the MAC-addresses, but also the - * clocks and memsize. Now try to get all values using the OpenBIOS - * "get_board_info()" callback. - */ - if ((openbios_bd = get_board_info()) != NULL) { - /* - * Copy bd_info from OpenBIOS struct into U-Boot struct - * used by kernel - */ - hold_residual->bi_memsize = openbios_bd->bi_memsize; - hold_residual->bi_intfreq = openbios_bd->bi_intfreq; - hold_residual->bi_busfreq = openbios_bd->bi_busfreq; - hold_residual->bi_pci_busfreq = openbios_bd->bi_pci_busfreq; - memcpy(hold_residual->bi_pci_enetaddr, openbios_bd->bi_pci_enetaddr, 6); -#ifdef CONFIG_405EP - memcpy(hold_residual->bi_enetaddr, openbios_bd->bi_enetaddr[0], 6); - memcpy(hold_residual->bi_enet1addr, openbios_bd->bi_enetaddr[1], 6); - hold_residual->bi_opbfreq = openbios_bd->bi_opb_busfreq; - hold_residual->bi_procfreq = openbios_bd->bi_pllouta_freq; -#else /* CONFIG_405EP */ - memcpy(hold_residual->bi_enetaddr, openbios_bd->bi_enetaddr, 6); -#endif /* CONFIG_405EP */ - } else { - /* Hmmm...better try to stuff some defaults. - */ - hold_residual->bi_memsize = 16 * 1024 * 1024; - hold_residual->bi_intfreq = 200000000; - hold_residual->bi_busfreq = 100000000; - hold_residual->bi_pci_busfreq = 66666666; - - /* - * Only supply one mac-address in this fallback - */ - memcpy(hold_residual->bi_enetaddr, (void *)def_enet_addr, 6); -#ifdef CONFIG_405EP - hold_residual->bi_opbfreq = 50000000; - hold_residual->bi_procfreq = 200000000; -#endif /* CONFIG_405EP */ - } - - timebase_period_ns = 1000000000 / hold_residual->bi_intfreq; -#endif /* CONFIG_40x */ - -#ifdef CONFIG_440GP - /* simply copy the MAC addresses */ - memcpy(hold_residual->bi_enetaddr, (char *)OPENBIOS_MAC_BASE, 6); - memcpy(hold_residual->bi_enet1addr, (char *)(OPENBIOS_MAC_BASE+OPENBIOS_MAC_OFFSET), 6); -#endif /* CONFIG_440GP */ - - decompress_kernel(load_addr, num_words, cksum); - - return (void *)hold_residual; -} diff --git a/arch/ppc/boot/simple/pci.c b/arch/ppc/boot/simple/pci.c deleted file mode 100644 index b0f673c8b7d9..000000000000 --- a/arch/ppc/boot/simple/pci.c +++ /dev/null @@ -1,274 +0,0 @@ -/* Stand alone funtions for QSpan Tundra support. - */ -#include -#include -#include - -extern void puthex(unsigned long val); -extern void puts(const char *); - -/* To map PCI devices, you first write 0xffffffff into the device - * base address registers. When the register is read back, the - * number of most significant '1' bits describes the amount of address - * space needed for mapping. If the most significant bit is not set, - * either the device does not use that address register, or it has - * a fixed address that we can't change. After the address is assigned, - * the command register has to be written to enable the card. - */ -typedef struct { - u_char pci_bus; - u_char pci_devfn; - ushort pci_command; - uint pci_addrs[6]; -} pci_map_t; - -/* We should probably dynamically allocate these structures. -*/ -#define MAX_PCI_DEVS 32 -int pci_dev_cnt; -pci_map_t pci_map[MAX_PCI_DEVS]; - -void pci_conf_write(int bus, int device, int func, int reg, uint writeval); -void pci_conf_read(int bus, int device, int func, int reg, void *readval); -void probe_addresses(int bus, int devfn); -void map_pci_addrs(void); - -extern int -qs_pci_read_config_byte(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned char *val); -extern int -qs_pci_read_config_word(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned short *val); -extern int -qs_pci_read_config_dword(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned int *val); -extern int -qs_pci_write_config_byte(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned char val); -extern int -qs_pci_write_config_word(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned short val); -extern int -qs_pci_write_config_dword(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned int val); - - -/* This is a really stripped version of PCI bus scan. All we are - * looking for are devices that exist. - */ -void -pci_scanner(int addr_probe) -{ - unsigned int devfn, l, class, bus_number; - unsigned char hdr_type, is_multi; - - is_multi = 0; - bus_number = 0; - for (devfn = 0; devfn < 0xff; ++devfn) { - /* The device numbers are comprised of upper 5 bits of - * device number and lower 3 bits of multi-function number. - */ - if ((devfn & 7) && !is_multi) { - /* Don't scan multifunction addresses if this is - * not a multifunction device. - */ - continue; - } - - /* Read the header to determine card type. - */ - qs_pci_read_config_byte(bus_number, devfn, PCI_HEADER_TYPE, - &hdr_type); - - /* If this is a base device number, check the header to - * determine if it is mulifunction. - */ - if ((devfn & 7) == 0) - is_multi = hdr_type & 0x80; - - /* Check to see if the board is really in the slot. - */ - qs_pci_read_config_dword(bus_number, devfn, PCI_VENDOR_ID, &l); - /* some broken boards return 0 if a slot is empty: */ - if (l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || - l == 0xffff0000) { - /* Nothing there. - */ - is_multi = 0; - continue; - } - - /* If we are not performing an address probe, - * just simply print out some information. - */ - if (!addr_probe) { - qs_pci_read_config_dword(bus_number, devfn, - PCI_CLASS_REVISION, &class); - - class >>= 8; /* upper 3 bytes */ - -#if 0 - printf("Found (%3d:%d): vendor 0x%04x, device 0x%04x, class 0x%06x\n", - (devfn >> 3), (devfn & 7), - (l & 0xffff), (l >> 16) & 0xffff, class); -#else - puts("Found ("); puthex(devfn >> 3); - puts(":"); puthex(devfn & 7); - puts("): vendor "); puthex(l & 0xffff); - puts(", device "); puthex((l >> 16) & 0xffff); - puts(", class "); puthex(class); puts("\n"); -#endif - } - else { - /* If this is a "normal" device, build address list. - */ - if ((hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) - probe_addresses(bus_number, devfn); - } - } - - /* Now map the boards. - */ - if (addr_probe) - map_pci_addrs(); -} - -/* Probe addresses for the specified device. This is a destructive - * operation because it writes the registers. - */ -void -probe_addresses(bus, devfn) -{ - int i; - uint pciaddr; - ushort pcicmd; - pci_map_t *pm; - - if (pci_dev_cnt >= MAX_PCI_DEVS) { - puts("Too many PCI devices\n"); - return; - } - - pm = &pci_map[pci_dev_cnt++]; - - pm->pci_bus = bus; - pm->pci_devfn = devfn; - - for (i=0; i<6; i++) { - qs_pci_write_config_dword(bus, devfn, PCI_BASE_ADDRESS_0 + (i * 4), -1); - qs_pci_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0 + (i * 4), - &pciaddr); - pm->pci_addrs[i] = pciaddr; - qs_pci_read_config_word(bus, devfn, PCI_COMMAND, &pcicmd); - pm->pci_command = pcicmd; - } -} - -/* Map the cards into the PCI space. The PCI has separate memory - * and I/O spaces. In addition, some memory devices require mapping - * below 1M. The least significant 4 bits of the address register - * provide information. If this is an I/O device, only the LS bit - * is used to indicate that, so I/O devices can be mapped to a two byte - * boundard. Memory addresses can be mapped to a 32 byte boundary. - * The QSpan implementations usually have a 1Gbyte space for each - * memory and I/O spaces. - * - * This isn't a terribly fancy algorithm. I just map the spaces from - * the top starting with the largest address space. When finished, - * the registers are written and the card enabled. - * - * While the Tundra can map a large address space on most boards, we - * need to be careful because it may overlap other devices (like IMMR). - */ -#define MEMORY_SPACE_SIZE 0x20000000 -#define IO_SPACE_SIZE 0x20000000 - -void -map_pci_addrs() -{ - uint pci_mem_top, pci_mem_low; - uint pci_io_top; - uint addr_mask, reg_addr, space; - int i, j; - pci_map_t *pm; - - pci_mem_top = MEMORY_SPACE_SIZE; - pci_io_top = IO_SPACE_SIZE; - pci_mem_low = (1 * 1024 * 1024); /* Below one meg addresses */ - - /* We can't map anything more than the maximum space, but test - * for it anyway to catch devices out of range. - */ - addr_mask = 0x80000000; - - do { - space = (~addr_mask) + 1; /* Size of the space */ - for (i=0; ipci_addrs[j]; - if ((reg_addr & 0x80000000) == 0) - continue; - if (reg_addr & PCI_BASE_ADDRESS_SPACE_IO) { - if ((reg_addr & PCI_BASE_ADDRESS_IO_MASK) != addr_mask) - continue; - if (pci_io_top < space) { - puts("Out of PCI I/O space\n"); - } - else { - pci_io_top -= space; - pm->pci_addrs[j] = pci_io_top; - pm->pci_command |= PCI_COMMAND_IO; - } - } - else { - if ((reg_addr & PCI_BASE_ADDRESS_MEM_MASK) != addr_mask) - continue; - - /* Memory space. Test if below 1M. - */ - if (reg_addr & PCI_BASE_ADDRESS_MEM_TYPE_1M) { - if (pci_mem_low < space) { - puts("Out of PCI 1M space\n"); - } - else { - pci_mem_low -= space; - pm->pci_addrs[j] = pci_mem_low; - } - } - else { - if (pci_mem_top < space) { - puts("Out of PCI Mem space\n"); - } - else { - pci_mem_top -= space; - pm->pci_addrs[j] = pci_mem_top; - } - } - pm->pci_command |= PCI_COMMAND_MEMORY; - } - } - } - addr_mask >>= 1; - addr_mask |= 0x80000000; - } while (addr_mask != 0xfffffffe); - - /* Now, run the list one more time and map everything. - */ - for (i=0; ipci_bus, pm->pci_devfn, - PCI_BASE_ADDRESS_0 + (j * 4), pm->pci_addrs[j]); - } - - /* Enable memory or address mapping. - */ - qs_pci_write_config_word(pm->pci_bus, pm->pci_devfn, PCI_COMMAND, - pm->pci_command); - } -} - diff --git a/arch/ppc/boot/simple/pibs.c b/arch/ppc/boot/simple/pibs.c deleted file mode 100644 index f39d01e0619d..000000000000 --- a/arch/ppc/boot/simple/pibs.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * 2004-2005 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include - -extern unsigned long decompress_kernel(unsigned long load_addr, int num_words, - unsigned long cksum); - -/* We need to make sure that this is before the images to ensure - * that it's in a mapped location. - Tom */ -bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot"))); -bd_t *hold_residual = &hold_resid_buf; - -/* String functions lifted from lib/vsprintf.c and lib/ctype.c */ -unsigned char _ctype[] = { -_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ -_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ -_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ -_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ -_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ -_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ -_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ -_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ -_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ -_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ -_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */ -_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */ -_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */ -_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */ -_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */ -_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */ - -/** - * simple_strtoull - convert a string to an unsigned long long - * @cp: The start of the string - * @endp: A pointer to the end of the parsed string will be placed here - * @base: The number base to use - */ -unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base) -{ - unsigned long long result = 0,value; - - if (!base) { - base = 10; - if (*cp == '0') { - base = 8; - cp++; - if ((toupper(*cp) == 'X') && isxdigit(cp[1])) { - cp++; - base = 16; - } - } - } else if (base == 16) { - if (cp[0] == '0' && toupper(cp[1]) == 'X') - cp += 2; - } - while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) - ? toupper(*cp) : *cp)-'A'+10) < base) { - result = result*base + value; - cp++; - } - if (endp) - *endp = (char *)cp; - return result; -} - -void * -load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, - void *ign1, void *ign2) -{ - unsigned long long mac64; - - decompress_kernel(load_addr, num_words, cksum); - - mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16); - memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6); -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) - mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16); - memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6); -#endif -#ifdef CONFIG_440GX - mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16); - memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6); - mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16); - memcpy(hold_residual->bi_enet3addr, (char *)&mac64+2, 6); -#endif - return (void *)hold_residual; -} diff --git a/arch/ppc/boot/simple/prepmap.c b/arch/ppc/boot/simple/prepmap.c deleted file mode 100644 index c871a4db6e8c..000000000000 --- a/arch/ppc/boot/simple/prepmap.c +++ /dev/null @@ -1,12 +0,0 @@ -/* - * 2004 (C) IBM. This file is licensed under the terms of the GNU General - * Public License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - -void board_isa_init(void) -{ - ISA_init(0x80000000); -} diff --git a/arch/ppc/boot/simple/qspan_pci.c b/arch/ppc/boot/simple/qspan_pci.c deleted file mode 100644 index d2966d032a4c..000000000000 --- a/arch/ppc/boot/simple/qspan_pci.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * LinuxPPC arch/ppc/kernel/qspan_pci.c Dan Malek (dmalek@jlc.net) - * - * QSpan Motorola bus to PCI bridge. The config address register - * is located 0x500 from the base of the bridge control/status registers. - * The data register is located at 0x504. - * This is a two step operation. First, the address register is written, - * then the data register is read/written as required. - * I don't know what to do about interrupts (yet). - */ - -#include -#include -#include -#include - -/* - * When reading the configuration space, if something does not respond - * the bus times out and we get a machine check interrupt. So, the - * good ol' exception tables come to mind to trap it and return some - * value. - * - * On an error we just return a -1, since that is what the caller wants - * returned if nothing is present. I copied this from __get_user_asm, - * with the only difference of returning -1 instead of EFAULT. - * There is an associated hack in the machine check trap code. - * - * The QSPAN is also a big endian device, that is it makes the PCI - * look big endian to us. This presents a problem for the Linux PCI - * functions, which assume little endian. For example, we see the - * first 32-bit word like this: - * ------------------------ - * | Device ID | Vendor ID | - * ------------------------ - * If we read/write as a double word, that's OK. But in our world, - * when read as a word, device ID is at location 0, not location 2 as - * the little endian PCI would believe. We have to switch bits in - * the PCI addresses given to us to get the data to/from the correct - * byte lanes. - * - * The QSPAN only supports 4 bits of "slot" in the dev_fn instead of 5. - * It always forces the MS bit to zero. Therefore, dev_fn values - * greater than 128 are returned as "no device found" errors. - * - * The QSPAN can only perform long word (32-bit) configuration cycles. - * The "offset" must have the two LS bits set to zero. Read operations - * require we read the entire word and then sort out what should be - * returned. Write operations other than long word require that we - * read the long word, update the proper word or byte, then write the - * entire long word back. - * - * PCI Bridge hack. We assume (correctly) that bus 0 is the primary - * PCI bus from the QSPAN. If we are called with a bus number other - * than zero, we create a Type 1 configuration access that a downstream - * PCI bridge will interpret. - */ - -#define __get_pci_config(x, addr, op) \ - __asm__ __volatile__( \ - "1: "op" %0,0(%1)\n" \ - " eieio\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r"(x) : "r"(addr)) - -#define QS_CONFIG_ADDR ((volatile uint *)(PCI_CSR_ADDR + 0x500)) -#define QS_CONFIG_DATA ((volatile uint *)(PCI_CSR_ADDR + 0x504)) - -#define mk_config_addr(bus, dev, offset) \ - (((bus)<<16) | ((dev)<<8) | (offset & 0xfc)) - -#define mk_config_type1(bus, dev, offset) \ - mk_config_addr(bus, dev, offset) | 1; - -/* Initialize the QSpan device registers after power up. -*/ -void -qspan_init(void) -{ - uint *qptr; - - - - qptr = (uint *)PCI_CSR_ADDR; - - /* PCI Configuration/status. Upper bits written to clear - * pending interrupt or status. Lower bits enable QSPAN as - * PCI master, enable memory and I/O cycles, and enable PCI - * parity error checking. - * IMPORTANT: The last two bits of this word enable PCI - * master cycles into the QBus. The QSpan is broken and can't - * meet the timing specs of the PQ bus for this to work. Therefore, - * if you don't have external bus arbitration, you can't use - * this function. - */ -#ifdef EXTERNAL_PQ_ARB - qptr[1] = 0xf9000147; -#else - qptr[1] = 0xf9000144; -#endif - - /* PCI Misc configuration. Set PCI latency timer resolution - * of 8 cycles, set cache size to 4 x 32. - */ - qptr[3] = 0; - - /* Set up PCI Target address mapping. Enable, Posted writes, - * 2Gbyte space (processor memory controller determines actual size). - */ - qptr[64] = 0x8f000080; - - /* Map processor 0x80000000 to PCI 0x00000000. - * Processor address bit 1 determines I/O type access (0x80000000) - * or memory type access (0xc0000000). - */ - qptr[65] = 0x80000000; - - /* Enable error logging and clear any pending error status. - */ - qptr[80] = 0x90000000; - - qptr[512] = 0x000c0003; - - /* Set up Qbus slave image. - */ - qptr[960] = 0x01000000; - qptr[961] = 0x000000d1; - qptr[964] = 0x00000000; - qptr[965] = 0x000000d1; - -} - -/* Functions to support PCI bios-like features to read/write configuration - * space. If the function fails for any reason, a -1 (0xffffffff) value - * must be returned. - */ -#define DEVICE_NOT_FOUND (-1) -#define SUCCESSFUL 0 - -int qs_pci_read_config_byte(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned char *val) -{ - uint temp; - u_char *cp; - - if ((bus > 7) || (dev_fn > 127)) { - *val = 0xff; - return DEVICE_NOT_FOUND; - } - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - __get_pci_config(temp, QS_CONFIG_DATA, "lwz"); - - offset ^= 0x03; - cp = ((u_char *)&temp) + (offset & 0x03); - *val = *cp; - return SUCCESSFUL; -} - -int qs_pci_read_config_word(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned short *val) -{ - uint temp; - ushort *sp; - - if ((bus > 7) || (dev_fn > 127)) { - *val = 0xffff; - return DEVICE_NOT_FOUND; - } - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - __get_pci_config(temp, QS_CONFIG_DATA, "lwz"); - offset ^= 0x02; - - sp = ((ushort *)&temp) + ((offset >> 1) & 1); - *val = *sp; - return SUCCESSFUL; -} - -int qs_pci_read_config_dword(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned int *val) -{ - if ((bus > 7) || (dev_fn > 127)) { - *val = 0xffffffff; - return DEVICE_NOT_FOUND; - } - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - __get_pci_config(*val, QS_CONFIG_DATA, "lwz"); - return SUCCESSFUL; -} - -int qs_pci_write_config_byte(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned char val) -{ - uint temp; - u_char *cp; - - if ((bus > 7) || (dev_fn > 127)) - return DEVICE_NOT_FOUND; - - qs_pci_read_config_dword(bus, dev_fn, offset, &temp); - - offset ^= 0x03; - cp = ((u_char *)&temp) + (offset & 0x03); - *cp = val; - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - *QS_CONFIG_DATA = temp; - - return SUCCESSFUL; -} - -int qs_pci_write_config_word(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned short val) -{ - uint temp; - ushort *sp; - - if ((bus > 7) || (dev_fn > 127)) - return DEVICE_NOT_FOUND; - - qs_pci_read_config_dword(bus, dev_fn, offset, &temp); - - offset ^= 0x02; - sp = ((ushort *)&temp) + ((offset >> 1) & 1); - *sp = val; - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - *QS_CONFIG_DATA = temp; - - return SUCCESSFUL; -} - -int qs_pci_write_config_dword(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned int val) -{ - if ((bus > 7) || (dev_fn > 127)) - return DEVICE_NOT_FOUND; - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - *(unsigned int *)QS_CONFIG_DATA = val; - - return SUCCESSFUL; -} - diff --git a/arch/ppc/boot/simple/relocate.S b/arch/ppc/boot/simple/relocate.S deleted file mode 100644 index 1bbbcd2f2bcb..000000000000 --- a/arch/ppc/boot/simple/relocate.S +++ /dev/null @@ -1,213 +0,0 @@ -/* - * This is the common part of the loader relocation and initialization - * process. All of the board/processor specific initialization is - * done before we get here. - * - * Author: Tom Rini - * trini@mvista.com - * Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others). - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include - -#define GETSYM(reg, sym) \ - lis reg, sym@h; ori reg, reg, sym@l - - .text - /* We get called from the early initialization code. - * Register 3 has the address where we were loaded, - * Register 4 contains any residual data passed from the - * boot rom. - */ - .globl relocate -relocate: - /* Save r3, r4 for later. - * The r8/r11 are legacy registers so I don't have to - * rewrite the code below :-). - */ - mr r8, r3 - mr r11, r4 - - /* compute the size of the whole image in words. */ - GETSYM(r4,start) - GETSYM(r5,end) - - addi r5,r5,3 /* round up */ - sub r5,r5,r4 /* end - start */ - srwi r5,r5,2 - mr r7,r5 /* Save for later use. */ - - /* - * Check if we need to relocate ourselves to the link addr or were - * we loaded there to begin with. - */ - cmpw cr0,r3,r4 - beq start_ldr /* If 0, we don't need to relocate */ - - /* Move this code somewhere safe. This is max(load + size, end) - * r8 == load address - */ - GETSYM(r4, start) - GETSYM(r5, end) - - sub r6,r5,r4 - add r6,r8,r6 /* r6 == phys(load + size) */ - - cmpw r5,r6 - bgt 1f - b 2f -1: - mr r6, r5 -2: - /* dest is in r6 */ - /* Ensure alignment --- this code is precautionary */ - addi r6,r6,4 - li r5,0x0003 - andc r6,r6,r5 - - /* Find physical address and size of do_relocate */ - GETSYM(r5, __relocate_start) - GETSYM(r4, __relocate_end) - GETSYM(r3, start) - - /* Size to copy */ - sub r4,r4,r5 - srwi r4,r4,2 - - /* Src addr to copy (= __relocate_start - start + where_loaded) */ - sub r3,r5,r3 - add r5,r8,r3 - - /* Save dest */ - mr r3, r6 - - /* Do the copy */ - mtctr r4 -3: lwz r4,0(r5) - stw r4,0(r3) - addi r3,r3,4 - addi r5,r5,4 - bdnz 3b - - GETSYM(r4, __relocate_start) - GETSYM(r5, do_relocate) - - sub r4,r5,r4 /* Get entry point for do_relocate in */ - add r6,r6,r4 /* relocated section */ - - /* This will return to the relocated do_relocate */ - mtlr r6 - b flush_instruction_cache - - .section ".relocate_code","xa" - -do_relocate: - /* We have 2 cases --- start < load, or start > load - * This determines whether we copy from the end, or the start. - * Its easier to have 2 loops than to have paramaterised - * loops. Sigh. - */ - li r6,0 /* Clear checksum */ - mtctr r7 /* Setup for a loop */ - - GETSYM(r4, start) - mr r3,r8 /* Get the load addr */ - - cmpw cr0,r4,r3 /* If we need to copy from the end, do so */ - bgt do_relocate_from_end - -do_relocate_from_start: -1: lwz r5,0(r3) /* Load and decrement */ - stw r5,0(r4) /* Store and decrement */ - addi r3,r3,4 - addi r4,r4,4 - xor r6,r6,r5 /* Update checksum */ - bdnz 1b /* Are we done? */ - b do_relocate_out /* Finished */ - -do_relocate_from_end: - GETSYM(r3, end) - slwi r4,r7,2 - add r4,r8,r4 /* Get the physical end */ -1: lwzu r5,-4(r4) - stwu r5, -4(r3) - xor r6,r6,r5 - bdnz 1b - -do_relocate_out: - GETSYM(r3,start_ldr) - mtlr r3 /* Easiest way to do an absolute jump */ -/* Some boards don't boot up with the I-cache enabled. Do that - * now because the decompress runs much faster that way. - * As a side effect, we have to ensure the data cache is not enabled - * so we can access the serial I/O without trouble. - */ - b flush_instruction_cache - - .previous - -start_ldr: -/* Clear all of BSS and set up stack for C calls */ - lis r3,__bss_start@h - ori r3,r3,__bss_start@l - lis r4,end@h - ori r4,r4,end@l - subi r3,r3,4 - subi r4,r4,4 - li r0,0 -50: stwu r0,4(r3) - cmpw cr0,r3,r4 - blt 50b -90: mr r9,r1 /* Save old stack pointer (in case it matters) */ - lis r1,.stack@h - ori r1,r1,.stack@l - addi r1,r1,4096*2 - subi r1,r1,256 - li r2,0x000F /* Mask pointer to 16-byte boundary */ - andc r1,r1,r2 - - /* - * Exec kernel loader - */ - mr r3,r8 /* Load point */ - mr r4,r7 /* Program length */ - mr r5,r6 /* Checksum */ - mr r6,r11 /* Residual data */ - mr r7,r25 /* Validated OFW interface */ - bl load_kernel - - /* - * Make sure the kernel knows we don't have things set in - * registers. -- Tom - */ - li r4,0 - li r5,0 - li r6,0 - - /* - * Start at the begining. - */ -#ifdef CONFIG_PPC_PREP - li r9,0xc - mtlr r9 - /* tell kernel we're prep, by putting 0xdeadc0de at KERNELLOAD, - * and tell the kernel to start on the 4th instruction since we - * overwrite the first 3 sometimes (which are 'nop'). - */ - lis r10,0xdeadc0de@h - ori r10,r10,0xdeadc0de@l - li r9,0 - stw r10,0(r9) -#else - li r9,0 - mtlr r9 -#endif - blr - - .comm .stack,4096*2,4 diff --git a/arch/ppc/boot/simple/rw4/ppc_40x.h b/arch/ppc/boot/simple/rw4/ppc_40x.h deleted file mode 100644 index 561fb26f5a93..000000000000 --- a/arch/ppc/boot/simple/rw4/ppc_40x.h +++ /dev/null @@ -1,664 +0,0 @@ -/*----------------------------------------------------------------------------+ -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1997 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Author: Tony J. Cerreto -| Component: Assembler include file. -| File: ppc_40x.h -| Purpose: Include file containing PPC DCR defines. -| -| Changes: -| Date Author Comment -| --------- ------ -------------------------------------------------------- -| 01-Mar-00 tjc Created -+----------------------------------------------------------------------------*/ -/* added by linguohui*/ -#define MW -/*----------------------------------------------------------------------------+ -| PPC Special purpose registers Numbers -+----------------------------------------------------------------------------*/ -#define ccr0 0x3b3 /* core configuration reg */ -#define ctr 0x009 /* count register */ -#define ctrreg 0x009 /* count register */ -#define dbcr0 0x3f2 /* debug control register 0 */ -#define dbcr1 0x3bd /* debug control register 1 */ -#define dbsr 0x3f0 /* debug status register */ -#define dccr 0x3fa /* data cache control reg. */ -#define dcwr 0x3ba /* data cache write-thru reg */ -#define dear 0x3d5 /* data exception address reg */ -#define esr 0x3d4 /* exception syndrome register */ -#define evpr 0x3d6 /* exception vector prefix reg */ -#define iccr 0x3fb /* instruction cache cntrl re */ -#define icdbdr 0x3d3 /* instr cache dbug data reg */ -#define lrreg 0x008 /* link register */ -#define pid 0x3b1 /* process id reg */ -#define pit 0x3db /* programmable interval time */ -#define pvr 0x11f /* processor version register */ -#define sgr 0x3b9 /* storage guarded reg */ -#define sler 0x3bb /* storage little endian reg */ -#define sprg0 0x110 /* special general purpose 0 */ -#define sprg1 0x111 /* special general purpose 1 */ -#define sprg2 0x112 /* special general purpose 2 */ -#define sprg3 0x113 /* special general purpose 3 */ -#define sprg4 0x114 /* special general purpose 4 */ -#define sprg5 0x115 /* special general purpose 5 */ -#define sprg6 0x116 /* special general purpose 6 */ -#define sprg7 0x117 /* special general purpose 7 */ -#define srr0 0x01a /* save/restore register 0 */ -#define srr1 0x01b /* save/restore register 1 */ -#define srr2 0x3de /* save/restore register 2 */ -#define srr3 0x3df /* save/restore register 3 */ -#define tbhi 0x11D -#define tblo 0x11C -#define tcr 0x3da /* timer control register */ -#define tsr 0x3d8 /* timer status register */ -#define xerreg 0x001 /* fixed point exception */ -#define xer 0x001 /* fixed point exception */ -#define zpr 0x3b0 /* zone protection reg */ - -/*----------------------------------------------------------------------------+ -| Decompression Controller -+----------------------------------------------------------------------------*/ -#define kiar 0x014 /* Decompression cntl addr reg */ -#define kidr 0x015 /* Decompression cntl data reg */ -#define kitor0 0x00 /* index table origin Reg 0 */ -#define kitor1 0x01 /* index table origin Reg 1 */ -#define kitor2 0x02 /* index table origin Reg 2 */ -#define kitor3 0x03 /* index table origin Reg 3 */ -#define kaddr0 0x04 /* addr decode Definition Reg 0 */ -#define kaddr1 0x05 /* addr decode Definition Reg 1 */ -#define kconf 0x40 /* Decompression cntl config reg */ -#define kid 0x41 /* Decompression cntl id reg */ -#define kver 0x42 /* Decompression cntl ver number */ -#define kpear 0x50 /* bus error addr reg (PLB) */ -#define kbear 0x51 /* bus error addr reg (DCP-EBC) */ -#define kesr0 0x52 /* bus error status reg 0 */ - -/*----------------------------------------------------------------------------+ -| Romeo Specific Device Control Register Numbers. -+----------------------------------------------------------------------------*/ -#ifndef VESTA -#define cdbcr 0x3d7 /* cache debug cntrl reg */ - -#define a_latcnt 0x1a9 /* PLB Latency count */ -#define a_tgval 0x1ac /* tone generation value */ -#define a_plb_pr 0x1bf /* PLB priority */ - -#define cic_sel1 0x031 /* select register 1 */ -#define cic_sel2 0x032 /* select register 2 */ - -#define clkgcrst 0x122 /* chip reset register */ - -#define cp_cpmsr 0x100 /*rstatus register */ -#define cp_cpmer 0x101 /* enable register */ - -#define dcp_kiar 0x190 /* indirect address register */ -#define dcp_kidr 0x191 /* indirect data register */ - -#define hsmc_mcgr 0x1c0 /* HSMC global register */ -#define hsmc_mcbesr 0x1c1 /* bus error status register */ -#define hsmc_mcbear 0x1c2 /* bus error address register*/ -#define hsmc_mcbr0 0x1c4 /* SDRAM sub-ctrl bank reg 0 */ -#define hsmc_mccr0 0x1c5 /* SDRAM sub-ctrl ctrl reg 0 */ -#define hsmc_mcbr1 0x1c7 /* SDRAM sub-ctrl bank reg 1 */ -#define hsmc_mccr1 0x1c8 /* SDRAM sub-ctrl ctrl reg 1 */ -#define hsmc_sysr 0x1d1 /* system register */ -#define hsmc_data 0x1d2 /* data register */ -#define hsmc_mccrr 0x1d3 /* refresh register */ - -#define ocm_pbar 0x1E0 /* base address register */ - -#define plb0_pacr0 0x057 /* PLB arbiter control reg */ -#define plb1_pacr1 0x067 /* PLB arbiter control reg */ - -#define v_displb 0x157 /* set left border of display*/ -#define v_disptb 0x158 /* top border of display */ -#define v_osd_la 0x159 /* first link address for OSD*/ -#define v_ptsdlta 0x15E /* PTS delta register */ -#define v_v0base 0x16C /* base mem add for VBI-0 */ -#define v_v1base 0x16D /* base mem add for VBI-1 */ -#define v_osbase 0x16E /* base mem add for OSD data */ -#endif - -/*----------------------------------------------------------------------------+ -| Vesta Device Control Register Numbers. -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Cross bar switch. -+----------------------------------------------------------------------------*/ -#define cbs0_cr 0x010 /* CBS configuration register */ - -/*----------------------------------------------------------------------------+ -| DCR external master (DCRX). -+----------------------------------------------------------------------------*/ -#define dcrx0_icr 0x020 /* internal control register */ -#define dcrx0_isr 0x021 /* internal status register */ -#define dcrx0_ecr 0x022 /* external control register */ -#define dcrx0_esr 0x023 /* external status register */ -#define dcrx0_tar 0x024 /* target address register */ -#define dcrx0_tdr 0x025 /* target data register */ -#define dcrx0_igr 0x026 /* interrupt generation register */ -#define dcrx0_bcr 0x027 /* buffer control register */ - -/*----------------------------------------------------------------------------+ -| Chip interconnect configuration. -+----------------------------------------------------------------------------*/ -#define cic0_cr 0x030 /* CIC control register */ -#define cic0_vcr 0x033 /* video macro control reg */ -#define cic0_sel3 0x035 /* select register 3 */ - -/*----------------------------------------------------------------------------+ -| Chip interconnect configuration. -+----------------------------------------------------------------------------*/ -#define sgpo0_sgpO 0x036 /* simplified GPIO output */ -#define sgpo0_gpod 0x037 /* simplified GPIO open drain */ -#define sgpo0_gptc 0x038 /* simplified GPIO tristate cntl */ -#define sgpo0_gpi 0x039 /* simplified GPIO input */ - -/*----------------------------------------------------------------------------+ -| Universal interrupt controller. -+----------------------------------------------------------------------------*/ -#define uic0_sr 0x040 /* status register */ -#define uic0_srs 0x041 /* status register set */ -#define uic0_er 0x042 /* enable register */ -#define uic0_cr 0x043 /* critical register */ -#define uic0_pr 0x044 /* parity register */ -#define uic0_tr 0x045 /* triggering register */ -#define uic0_msr 0x046 /* masked status register */ -#define uic0_vr 0x047 /* vector register */ -#define uic0_vcr 0x048 /* enable config register */ - -/*----------------------------------------------------------------------------+ -| PLB 0 and 1. -+----------------------------------------------------------------------------*/ -#define pb0_pesr 0x054 /* PLB error status reg 0 */ -#define pb0_pesrs 0x055 /* PLB error status reg 0 set */ -#define pb0_pear 0x056 /* PLB error address reg */ - -#define pb1_pesr 0x064 /* PLB error status reg 1 */ -#define pb1_pesrs 0x065 /* PLB error status reg 1 set */ -#define pb1_pear 0x066 /* PLB error address reg */ - -/*----------------------------------------------------------------------------+ -| EBIU DCR registers. -+----------------------------------------------------------------------------*/ -#define ebiu0_brcrh0 0x070 /* bus region register 0 high */ -#define ebiu0_brcrh1 0x071 /* bus region register 1 high */ -#define ebiu0_brcrh2 0x072 /* bus region register 2 high */ -#define ebiu0_brcrh3 0x073 /* bus region register 3 high */ -#define ebiu0_brcrh4 0x074 /* bus region register 4 high */ -#define ebiu0_brcrh5 0x075 /* bus region register 5 high */ -#define ebiu0_brcrh6 0x076 /* bus region register 6 high */ -#define ebiu0_brcrh7 0x077 /* bus region register 7 high */ -#define ebiu0_brcr0 0x080 /* bus region register 0 */ -#define ebiu0_brcr1 0x081 /* bus region register 1 */ -#define ebiu0_brcr2 0x082 /* bus region register 2 */ -#define ebiu0_brcr3 0x083 /* bus region register 3 */ -#define ebiu0_brcr4 0x084 /* bus region register 4 */ -#define ebiu0_brcr5 0x085 /* bus region register 5 */ -#define ebiu0_brcr6 0x086 /* bus region register 6 */ -#define ebiu0_brcr7 0x087 /* bus region register 7 */ -#define ebiu0_bear 0x090 /* bus error address register */ -#define ebiu0_besr 0x091 /* bus error syndrome reg */ -#define ebiu0_besr0s 0x093 /* bus error syndrome reg */ -#define ebiu0_biucr 0x09a /* bus interface control reg */ - -/*----------------------------------------------------------------------------+ -| OPB bridge. -+----------------------------------------------------------------------------*/ -#define opbw0_gesr 0x0b0 /* error status reg */ -#define opbw0_gesrs 0x0b1 /* error status reg */ -#define opbw0_gear 0x0b2 /* error address reg */ - -/*----------------------------------------------------------------------------+ -| DMA. -+----------------------------------------------------------------------------*/ -#define dma0_cr0 0x0c0 /* DMA channel control reg 0 */ -#define dma0_ct0 0x0c1 /* DMA count register 0 */ -#define dma0_da0 0x0c2 /* DMA destination addr reg 0 */ -#define dma0_sa0 0x0c3 /* DMA source addr register 0 */ -#define dma0_cc0 0x0c4 /* DMA chained count 0 */ -#define dma0_cr1 0x0c8 /* DMA channel control reg 1 */ -#define dma0_ct1 0x0c9 /* DMA count register 1 */ -#define dma0_da1 0x0ca /* DMA destination addr reg 1 */ -#define dma0_sa1 0x0cb /* DMA source addr register 1 */ -#define dma0_cc1 0x0cc /* DMA chained count 1 */ -#define dma0_cr2 0x0d0 /* DMA channel control reg 2 */ -#define dma0_ct2 0x0d1 /* DMA count register 2 */ -#define dma0_da2 0x0d2 /* DMA destination addr reg 2 */ -#define dma0_sa2 0x0d3 /* DMA source addr register 2 */ -#define dma0_cc2 0x0d4 /* DMA chained count 2 */ -#define dma0_cr3 0x0d8 /* DMA channel control reg 3 */ -#define dma0_ct3 0x0d9 /* DMA count register 3 */ -#define dma0_da3 0x0da /* DMA destination addr reg 3 */ -#define dma0_sa3 0x0db /* DMA source addr register 3 */ -#define dma0_cc3 0x0dc /* DMA chained count 3 */ -#define dma0_sr 0x0e0 /* DMA status register */ -#define dma0_srs 0x0e1 /* DMA status register */ -#define dma0_s1 0x031 /* DMA select1 register */ -#define dma0_s2 0x032 /* DMA select2 register */ - -/*---------------------------------------------------------------------------+ -| Clock and power management. -+----------------------------------------------------------------------------*/ -#define cpm0_fr 0x102 /* force register */ - -/*----------------------------------------------------------------------------+ -| Serial Clock Control. -+----------------------------------------------------------------------------*/ -#define ser0_ccr 0x120 /* serial clock control register */ - -/*----------------------------------------------------------------------------+ -| Audio Clock Control. -+----------------------------------------------------------------------------*/ -#define aud0_apcr 0x121 /* audio clock ctrl register */ - -/*----------------------------------------------------------------------------+ -| DENC. -+----------------------------------------------------------------------------*/ -#define denc0_idr 0x130 /* DENC ID register */ -#define denc0_cr1 0x131 /* control register 1 */ -#define denc0_rr1 0x132 /* microvision 1 (reserved 1) */ -#define denc0_cr2 0x133 /* control register 2 */ -#define denc0_rr2 0x134 /* microvision 2 (reserved 2) */ -#define denc0_rr3 0x135 /* microvision 3 (reserved 3) */ -#define denc0_rr4 0x136 /* microvision 4 (reserved 4) */ -#define denc0_rr5 0x137 /* microvision 5 (reserved 5) */ -#define denc0_ccdr 0x138 /* closed caption data */ -#define denc0_cccr 0x139 /* closed caption control */ -#define denc0_trr 0x13A /* teletext request register */ -#define denc0_tosr 0x13B /* teletext odd field line se */ -#define denc0_tesr 0x13C /* teletext even field line s */ -#define denc0_rlsr 0x13D /* RGB rhift left register */ -#define denc0_vlsr 0x13E /* video level shift register */ -#define denc0_vsr 0x13F /* video scaling register */ - -/*----------------------------------------------------------------------------+ -| Video decoder. Suspect 0x179, 0x169, 0x16a, 0x152 (rc). -+----------------------------------------------------------------------------*/ -#define vid0_ccntl 0x140 /* control decoder operation */ -#define vid0_cmode 0x141 /* video operational mode */ -#define vid0_sstc0 0x142 /* STC high order bits 31:0 */ -#define vid0_sstc1 0x143 /* STC low order bit 32 */ -#define vid0_spts0 0x144 /* PTS high order bits 31:0 */ -#define vid0_spts1 0x145 /* PTS low order bit 32 */ -#define vid0_fifo 0x146 /* FIFO data port */ -#define vid0_fifos 0x147 /* FIFO status */ -#define vid0_cmd 0x148 /* send command to decoder */ -#define vid0_cmdd 0x149 /* port for command params */ -#define vid0_cmdst 0x14A /* command status */ -#define vid0_cmdad 0x14B /* command address */ -#define vid0_procia 0x14C /* instruction store */ -#define vid0_procid 0x14D /* data port for I_Store */ -#define vid0_osdm 0x151 /* OSD mode control */ -#define vid0_hosti 0x152 /* base interrupt register */ -#define vid0_mask 0x153 /* interrupt mask register */ -#define vid0_dispm 0x154 /* operational mode for Disp */ -#define vid0_dispd 0x155 /* setting for 'Sync' delay */ -#define vid0_vbctl 0x156 /* VBI */ -#define vid0_ttxctl 0x157 /* teletext control */ -#define vid0_disptb 0x158 /* display left/top border */ -#define vid0_osdgla 0x159 /* Graphics plane link addr */ -#define vid0_osdila 0x15A /* Image plane link addr */ -#define vid0_rbthr 0x15B /* rate buffer threshold */ -#define vid0_osdcla 0x15C /* Cursor link addr */ -#define vid0_stcca 0x15D /* STC common address */ -#define vid0_ptsctl 0x15F /* PTS Control */ -#define vid0_wprot 0x165 /* write protect for I_Store */ -#define vid0_vcqa 0x167 /* video clip queued block Ad */ -#define vid0_vcql 0x168 /* video clip queued block Le */ -#define vid0_blksz 0x169 /* block size bytes for copy op */ -#define vid0_srcad 0x16a /* copy source address bits 6-31 */ -#define vid0_udbas 0x16B /* base mem add for user data */ -#define vid0_vbibas 0x16C /* base mem add for VBI 0/1 */ -#define vid0_osdibas 0x16D /* Image plane base address */ -#define vid0_osdgbas 0x16E /* Graphic plane base address */ -#define vid0_rbbase 0x16F /* base mem add for video buf */ -#define vid0_dramad 0x170 /* DRAM address */ -#define vid0_dramdt 0x171 /* data port for DRAM access */ -#define vid0_dramcs 0x172 /* DRAM command and statusa */ -#define vid0_vcwa 0x173 /* v clip work address */ -#define vid0_vcwl 0x174 /* v clip work length */ -#define vid0_mseg0 0x175 /* segment address 0 */ -#define vid0_mseg1 0x176 /* segment address 1 */ -#define vid0_mseg2 0x177 /* segment address 2 */ -#define vid0_mseg3 0x178 /* segment address 3 */ -#define vid0_fbbase 0x179 /* frame buffer base memory */ -#define vid0_osdcbas 0x17A /* Cursor base addr */ -#define vid0_lboxtb 0x17B /* top left border */ -#define vid0_trdly 0x17C /* transparency gate delay */ -#define vid0_sbord 0x17D /* left/top small pict. bord. */ -#define vid0_zoffs 0x17E /* hor/ver zoom window */ -#define vid0_rbsz 0x17F /* rate buffer size read */ - -/*----------------------------------------------------------------------------+ -| Transport demultiplexer. -+----------------------------------------------------------------------------*/ -#define xpt0_lr 0x180 /* demux location register */ -#define xpt0_data 0x181 /* demux data register */ -#define xpt0_ir 0x182 /* demux interrupt register */ - -#define xpt0_config1 0x0000 /* configuration 1 */ -#define xpt0_control1 0x0001 /* control 1 */ -#define xpt0_festat 0x0002 /* Front-end status */ -#define xpt0_feimask 0x0003 /* Front_end interrupt Mask */ -#define xpt0_ocmcnfg 0x0004 /* OCM Address */ -#define xpt0_settapi 0x0005 /* Set TAP Interrupt */ - -#define xpt0_pcrhi 0x0010 /* PCR High */ -#define xpt0_pcrlow 0x0011 /* PCR Low */ -#define xpt0_lstchi 0x0012 /* Latched STC High */ -#define xpt0_lstclow 0x0013 /* Latched STC Low */ -#define xpt0_stchi 0x0014 /* STC High */ -#define xpt0_stclow 0x0015 /* STC Low */ -#define xpt0_pwm 0x0016 /* PWM */ -#define xpt0_pcrstct 0x0017 /* PCR-STC Threshold */ -#define xpt0_pcrstcd 0x0018 /* PCR-STC Delta */ -#define xpt0_stccomp 0x0019 /* STC Compare */ -#define xpt0_stccmpd 0x001a /* STC Compare Disarm */ - -#define xpt0_dsstat 0x0048 /* Descrambler Status */ -#define xpt0_dsimask 0x0049 /* Descrambler Interrupt Mask */ - -#define xpt0_vcchng 0x01f0 /* Video Channel Change */ -#define xpt0_acchng 0x01f1 /* Audio Channel Change */ -#define xpt0_axenable 0x01fe /* Aux PID Enables */ -#define xpt0_pcrpid 0x01ff /* PCR PID */ - -#define xpt0_config2 0x1000 /* Configuration 2 */ -#define xpt0_pbuflvl 0x1002 /* Packet Buffer Level */ -#define xpt0_intmask 0x1003 /* Interrupt Mask */ -#define xpt0_plbcnfg 0x1004 /* PLB Configuration */ - -#define xpt0_qint 0x1010 /* Queues Interrupts */ -#define xpt0_qintmsk 0x1011 /* Queues Interrupts Mask */ -#define xpt0_astatus 0x1012 /* Audio Status */ -#define xpt0_aintmask 0x1013 /* Audio Interrupt Mask */ -#define xpt0_vstatus 0x1014 /* Video Status */ -#define xpt0_vintmask 0x1015 /* Video Interrupt Mask */ - -#define xpt0_qbase 0x1020 /* Queue Base */ -#define xpt0_bucketq 0x1021 /* Bucket Queue */ -#define xpt0_qstops 0x1024 /* Queue Stops */ -#define xpt0_qresets 0x1025 /* Queue Resets */ -#define xpt0_sfchng 0x1026 /* Section Filter Change */ - -/*----------------------------------------------------------------------------+ -| Audio decoder. Suspect 0x1ad, 0x1b4, 0x1a3, 0x1a5 (read/write status) -+----------------------------------------------------------------------------*/ -#define aud0_ctrl0 0x1a0 /* control 0 */ -#define aud0_ctrl1 0x1a1 /* control 1 */ -#define aud0_ctrl2 0x1a2 /* control 2 */ -#define aud0_cmd 0x1a3 /* command register */ -#define aud0_isr 0x1a4 /* interrupt status register */ -#define aud0_imr 0x1a5 /* interrupt mask register */ -#define aud0_dsr 0x1a6 /* decoder status register */ -#define aud0_stc 0x1a7 /* system time clock */ -#define aud0_csr 0x1a8 /* channel status register */ -#define aud0_lcnt 0x1a9 /* queued address register 2 */ -#define aud0_pts 0x1aa /* presentation time stamp */ -#define aud0_tgctrl 0x1ab /* tone generation control */ -#define aud0_qlr2 0x1ac /* queued length register 2 */ -#define aud0_auxd 0x1ad /* aux data */ -#define aud0_strmid 0x1ae /* stream ID */ -#define aud0_qar 0x1af /* queued address register */ -#define aud0_dsps 0x1b0 /* DSP status */ -#define aud0_qlr 0x1b1 /* queued len address */ -#define aud0_dspc 0x1b2 /* DSP control */ -#define aud0_wlr2 0x1b3 /* working length register 2 */ -#define aud0_instd 0x1b4 /* instruction download */ -#define aud0_war 0x1b5 /* working address register */ -#define aud0_seg1 0x1b6 /* segment 1 base register */ -#define aud0_seg2 0x1b7 /* segment 2 base register */ -#define aud0_avf 0x1b9 /* audio att value front */ -#define aud0_avr 0x1ba /* audio att value rear */ -#define aud0_avc 0x1bb /* audio att value center */ -#define aud0_seg3 0x1bc /* segment 3 base register */ -#define aud0_offset 0x1bd /* offset address */ -#define aud0_wrl 0x1be /* working length register */ -#define aud0_war2 0x1bf /* working address register 2 */ - -/*----------------------------------------------------------------------------+ -| High speed memory controller 0 and 1. -+----------------------------------------------------------------------------*/ -#define hsmc0_gr 0x1e0 /* HSMC global register */ -#define hsmc0_besr 0x1e1 /* bus error status register */ -#define hsmc0_bear 0x1e2 /* bus error address register */ -#define hsmc0_br0 0x1e4 /* SDRAM sub-ctrl bank reg 0 */ -#define hsmc0_cr0 0x1e5 /* SDRAM sub-ctrl ctrl reg 0 */ -#define hsmc0_br1 0x1e7 /* SDRAM sub-ctrl bank reg 1 */ -#define hsmc0_cr1 0x1e8 /* SDRAM sub-ctrl ctrl reg 1 */ -#define hsmc0_sysr 0x1f1 /* system register */ -#define hsmc0_data 0x1f2 /* data register */ -#define hsmc0_crr 0x1f3 /* refresh register */ - -#define hsmc1_gr 0x1c0 /* HSMC global register */ -#define hsmc1_besr 0x1c1 /* bus error status register */ -#define hsmc1_bear 0x1c2 /* bus error address register */ -#define hsmc1_br0 0x1c4 /* SDRAM sub-ctrl bank reg 0 */ -#define hsmc1_cr0 0x1c5 /* SDRAM sub-ctrl ctrl reg 0 */ -#define hsmc1_br1 0x1c7 /* SDRAM sub-ctrl bank reg 1 */ -#define hsmc1_cr1 0x1c8 /* SDRAM sub-ctrl ctrl reg 1 */ -#define hsmc1_sysr 0x1d1 /* system register */ -#define hsmc1_data 0x1d2 /* data register */ -#define hsmc1_crr 0x1d3 /* refresh register */ - -/*----------------------------------------------------------------------------+ -| Machine State Register bit definitions. -+----------------------------------------------------------------------------*/ -#define msr_ape 0x00100000 -#define msr_apa 0x00080000 -#define msr_we 0x00040000 -#define msr_ce 0x00020000 -#define msr_ile 0x00010000 -#define msr_ee 0x00008000 -#define msr_pr 0x00004000 -#define msr_me 0x00001000 -#define msr_de 0x00000200 -#define msr_ir 0x00000020 -#define msr_dr 0x00000010 -#define msr_le 0x00000001 - -/*----------------------------------------------------------------------------+ -| Used during interrupt processing. -+----------------------------------------------------------------------------*/ -#define stack_reg_image_size 160 - -/*----------------------------------------------------------------------------+ -| Function prolog definition and other Metaware (EABI) defines. -+----------------------------------------------------------------------------*/ -#ifdef MW - -#define r0 0 -#define r1 1 -#define r2 2 -#define r3 3 -#define r4 4 -#define r5 5 -#define r6 6 -#define r7 7 -#define r8 8 -#define r9 9 -#define r10 10 -#define r11 11 -#define r12 12 -#define r13 13 -#define r14 14 -#define r15 15 -#define r16 16 -#define r17 17 -#define r18 18 -#define r19 19 -#define r20 20 -#define r21 21 -#define r22 22 -#define r23 23 -#define r24 24 -#define r25 25 -#define r26 26 -#define r27 27 -#define r28 28 -#define r29 29 -#define r30 30 -#define r31 31 - -#define cr0 0 -#define cr1 1 -#define cr2 2 -#define cr3 3 -#define cr4 4 -#define cr5 5 -#define cr6 6 -#define cr7 7 - -#define function_prolog(func_name) .text; \ - .align 2; \ - .globl func_name; \ - func_name: -#define function_epilog(func_name) .type func_name,@function; \ - .size func_name,.-func_name - -#define function_call(func_name) bl func_name - -#define stack_frame_min 8 -#define stack_frame_bc 0 -#define stack_frame_lr 4 -#define stack_neg_off 0 - -#endif - -/*----------------------------------------------------------------------------+ -| Function prolog definition and other DIAB (Elf) defines. -+----------------------------------------------------------------------------*/ -#ifdef ELF_DIAB - -fprolog: macro f_name - .text - .align 2 - .globl f_name -f_name: - endm - -fepilog: macro f_name - .type f_name,@function - .size f_name,.-f_name - endm - -#define function_prolog(func_name) fprolog func_name -#define function_epilog(func_name) fepilog func_name -#define function_call(func_name) bl func_name - -#define stack_frame_min 8 -#define stack_frame_bc 0 -#define stack_frame_lr 4 -#define stack_neg_off 0 - -#endif - -/*----------------------------------------------------------------------------+ -| Function prolog definition and other Xlc (XCOFF) defines. -+----------------------------------------------------------------------------*/ -#ifdef XCOFF - -.machine "403ga" - -#define r0 0 -#define r1 1 -#define r2 2 -#define r3 3 -#define r4 4 -#define r5 5 -#define r6 6 -#define r7 7 -#define r8 8 -#define r9 9 -#define r10 10 -#define r11 11 -#define r12 12 -#define r13 13 -#define r14 14 -#define r15 15 -#define r16 16 -#define r17 17 -#define r18 18 -#define r19 19 -#define r20 20 -#define r21 21 -#define r22 22 -#define r23 23 -#define r24 24 -#define r25 25 -#define r26 26 -#define r27 27 -#define r28 28 -#define r29 29 -#define r30 30 -#define r31 31 - -#define cr0 0 -#define cr1 1 -#define cr2 2 -#define cr3 3 -#define cr4 4 -#define cr5 5 -#define cr6 6 -#define cr7 7 - -#define function_prolog(func_name) .csect .func_name[PR]; \ - .globl .func_name[PR]; \ - func_name: - -#define function_epilog(func_name) .toc; \ - .csect func_name[DS]; \ - .globl func_name[DS]; \ - .long .func_name[PR]; \ - .long TOC[tc0] - -#define function_call(func_name) .extern .func_name[PR]; \ - stw r2,stack_frame_toc(r1); \ - mfspr r2,sprg0; \ - bl .func_name[PR]; \ - lwz r2,stack_frame_toc(r1) - -#define stack_frame_min 56 -#define stack_frame_bc 0 -#define stack_frame_lr 8 -#define stack_frame_toc 20 -#define stack_neg_off 276 - -#endif -#define function_prolog(func_name) .text; \ - .align 2; \ - .globl func_name; \ - func_name: -#define function_epilog(func_name) .type func_name,@function; \ - .size func_name,.-func_name - -#define function_call(func_name) bl func_name - -/*----------------------------------------------------------------------------+ -| Function prolog definition for GNU -+----------------------------------------------------------------------------*/ -#ifdef _GNU_TOOL - -#define function_prolog(func_name) .globl func_name; \ - func_name: -#define function_epilog(func_name) - -#endif diff --git a/arch/ppc/boot/simple/rw4/rw4_init.S b/arch/ppc/boot/simple/rw4/rw4_init.S deleted file mode 100644 index b1061962e46b..000000000000 --- a/arch/ppc/boot/simple/rw4/rw4_init.S +++ /dev/null @@ -1,78 +0,0 @@ -#define VESTA -#include "ppc_40x.h" -# - .align 2 - .text -# -# added by linguohui - .extern initb_ebiu0, initb_config, hdw_init_finish - .extern initb_hsmc0, initb_hsmc1, initb_cache -# end added - .globl HdwInit -# -HdwInit: -# -#-----------------------------------------------------------------------* -# If we are not executing from the FLASH get out * -#-----------------------------------------------------------------------* -# SAW keep this or comment out a la Hawthorne? -# r3 contains NIP when used with Linux -# rlwinm r28, r3, 8, 24, 31 # if MSB == 0xFF -> FLASH address -# cmpwi r28, 0xff -# bne locn01 -# -# -#------------------------------------------------------------------------ -# Init_cpu. Bank registers are setup for the IBM STB. -#------------------------------------------------------------------------ -# -# Setup processor core clock to be driven off chip. This is GPI4 bit -# twenty. Setup Open Drain, Output Select, Three-State Control, and -# Three-State Select registers. -# - - - pb0pesr = 0x054 - pb0pear = 0x056 - - mflr r30 - -#----------------------------------------------------------------------------- -# Vectors will be at 0x1F000000 -# Dummy Machine check handler just does RFI before true handler gets installed -#----------------------------------------------------------------------------- -#if 1 /* xuwentao added*/ -#ifdef SDRAM16MB - lis r10,0x0000 - addi r10,r10,0x0000 -#else - lis r10,0x1F00 - addi r10,r10,0x0000 -#endif - - mtspr evpr,r10 #EVPR: 0x0 or 0x1f000000 depending - isync # on SDRAM memory model used. - - lis r10,0xFFFF # clear PB0_PESR because some - ori r10,r10,0xFFFF # transitions from flash,changed by linguohui - mtdcr pb0pesr,r10 # to load RAM image via RiscWatch - lis r10,0x0000 # cause PB0_PESR machine checks - mtdcr pb0pear,r10 - addis r10,r10,0x0000 # clear the - mtxer r10 # XER just in case... -#endif /* xuwentao*/ - - bl initb_ebiu0 # init EBIU - - bl initb_config # config PPC and board - - - - -#------------------------------------------------------------------------ -# EVPR setup moved to top of this function. -#------------------------------------------------------------------------ -# - mtlr r30 - blr - .end diff --git a/arch/ppc/boot/simple/rw4/rw4_init_brd.S b/arch/ppc/boot/simple/rw4/rw4_init_brd.S deleted file mode 100644 index 386afdaad6c7..000000000000 --- a/arch/ppc/boot/simple/rw4/rw4_init_brd.S +++ /dev/null @@ -1,1125 +0,0 @@ -/*----------------------------------------------------------------------------+ -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1997 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Author: Tony J. Cerreto -| Component: BSPS -| File: init_brd.s -| Purpose: Vesta Evaluation Board initialization subroutines. The following -| routines are available: -| 1. INITB_EBIU0: Initialize EBIU0. -| 2. INITB_CONFIG: Configure board. -| 3. INITB_HSMC0: Initialize HSMC0 (SDRAM). -| 4. INITB_HSMC1: Initialize HSMC1 (SDRAM). -| 5. INITB_CACHE: Initialize Data and Instruction Cache. -| 6. INITB_DCACHE: Initialize Data Cache. -| 7. INITB_ICACHE: Initialize Instruction Cache. -| 8. INITB_GET_CSPD: Get CPU Speed (Bus Speed and Processor Speed) -| -| Changes: -| Date: Author Comment: -| --------- ------ -------- -| 01-Mar-00 tjc Created -| 04-Mar-00 jfh Modified CIC_SEL3_VAL to support 1284 (Mux3 & GPIO 21-28) -| 04-Mar-00 jfh Modified XILINIX Reg 0 to support 1284 (Mux3 & GPIO 21-28) -| 04-Mar-00 jfh Modified XILINIX Reg 1 to support 1284 (Mux3 & GPIO 21-28) -| 04-Mar-00 jfh Modified XILINIX Reg 4 to support 1284 (Mux3 & GPIO 21-28) -| 19-May-00 rlb Relcoated HSMC0 to 0x1F000000 to support 32MB of contiguous -| SDRAM space. Changed cache ctl regs to reflect this. -| 22-May-00 tjc Changed initb_get_cspd interface and eliminated -| initb_get_bspd routines. -| 26-May-00 tjc Added two nop instructions after all mtxxx/mfxxx -| instructions due to PPC405 bug. -+----------------------------------------------------------------------------*/ -#define VESTA -#include "ppc_40x.h" -#include "stb.h" - -/*----------------------------------------------------------------------------+ -| BOARD CONFIGURATION DEFINES -+----------------------------------------------------------------------------*/ -#define CBS0_CR_VAL 0x00000002 /* CBS control reg value */ -#define CIC0_CR_VAL 0xD0800448 /* CIC control reg value */ -#define CIC0_SEL3_VAL 0x11500000 /* CIC select 3 reg value */ -#define CIC0_VCR_VAL 0x00631700 /* CIC video cntl reg value */ - -/*----------------------------------------------------------------------------+ -| EBIU0 BANK REGISTERS DEFINES -+----------------------------------------------------------------------------*/ -#define EBIU0_BRCRH0_VAL 0x00000000 /* BR High 0 (Extension Reg)*/ -#define EBIU0_BRCRH1_VAL 0x00000000 /* BR High 1 (Extension Reg)*/ -#define EBIU0_BRCRH2_VAL 0x40000000 /* BR High 2 (Extension Reg)*/ -#define EBIU0_BRCRH3_VAL 0x40000000 /* BR High 3 (Extension Reg)*/ -#define EBIU0_BRCRH4_VAL 0x00000000 /* BR High 4 (Extension Reg)*/ -#define EBIU0_BRCRH5_VAL 0x00000000 /* BR High 5 (Extension Reg)*/ -#define EBIU0_BRCRH6_VAL 0x00000000 /* BR High 6 (Extension Reg)*/ -#define EBIU0_BRCRH7_VAL 0x40000000 /* BR High 7 (Extension Reg)*/ - -#define EBIU0_BRCR0_VAL 0xFC58BFFE /* BR 0: 16 bit Flash 4 MB */ -#define EBIU0_BRCR1_VAL 0xFF00BFFE /* BR 1: Ext Connector 1 MB */ -#if 1 -#define EBIU0_BRCR2_VAL 0x207CFFBE /* BR 2: Xilinx 8 MB */ - /* twt == 0x3f */ -#else -#define EBIU0_BRCR2_VAL 0x207CCFBE /* BR 2: Xilinx 8 MB */ - /* twt == 0x0f */ -#endif -#define EBIU0_BRCR3_VAL 0x407CBFBE /* BR 3: IDE Drive 8 MB */ -#define EBIU0_BRCR4_VAL 0xFF00BFFF /* BR 4: Disabled. 0 MB */ -#define EBIU0_BRCR5_VAL 0xFF00BFFF /* BR 5: Disabled. 0 MB */ -#define EBIU0_BRCR6_VAL 0xFF00BFFF /* BR 6: Disabled. 0 MB */ -#define EBIU0_BRCR7_VAL 0xCE3F0003 /* BR 7: Line Mode DMA 2 MB */ - -/*----------------------------------------------------------------------------+ -| GPIO DEFINES -+----------------------------------------------------------------------------*/ -#define STB_GPIO0_OUTPUT (STB_GPIO0_BASE_ADDRESS+ 0x00) -#define STB_GPIO0_TC (STB_GPIO0_BASE_ADDRESS+ 0x04) -#define STB_GPIO0_OS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x08) -#define STB_GPIO0_OS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x0C) -#define STB_GPIO0_TS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x10) -#define STB_GPIO0_TS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x14) -#define STB_GPIO0_OD (STB_GPIO0_BASE_ADDRESS+ 0x18) -#define STB_GPIO0_INPUT (STB_GPIO0_BASE_ADDRESS+ 0x1C) -#define STB_GPIO0_R1 (STB_GPIO0_BASE_ADDRESS+ 0x20) -#define STB_GPIO0_R2 (STB_GPIO0_BASE_ADDRESS+ 0x24) -#define STB_GPIO0_R3 (STB_GPIO0_BASE_ADDRESS+ 0x28) -#define STB_GPIO0_IS_1_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x30) -#define STB_GPIO0_IS_1_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x34) -#define STB_GPIO0_IS_2_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x38) -#define STB_GPIO0_IS_2_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x3C) -#define STB_GPIO0_IS_3_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x40) -#define STB_GPIO0_IS_3_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x44) -#define STB_GPIO0_SS_1 (STB_GPIO0_BASE_ADDRESS+ 0x50) -#define STB_GPIO0_SS_2 (STB_GPIO0_BASE_ADDRESS+ 0x54) -#define STB_GPIO0_SS_3 (STB_GPIO0_BASE_ADDRESS+ 0x58) - -#define GPIO0_TC_VAL 0x0C020004 /* three-state control val */ -#define GPIO0_OS_0_31_VAL 0x51A00004 /* output select 0-31 val */ -#define GPIO0_OS_32_63_VAL 0x0000002F /* output select 32-63 val */ -#define GPIO0_TS_0_31_VAL 0x51A00000 /* three-state sel 0-31 val*/ -#define GPIO0_TS_32_63_VAL 0x0000000F /* three-state sel 32-63 val*/ -#define GPIO0_OD_VAL 0xC0000004 /* open drain val */ -#define GPIO0_IS_1_0_31_VAL 0x50000151 /* input select 1 0-31 val */ -#define GPIO0_IS_1_32_63_VAL 0x00000000 /* input select 1 32-63 val */ -#define GPIO0_IS_2_0_31_VAL 0x00000000 /* input select 2 0-31 val */ -#define GPIO0_IS_2_32_63_VAL 0x00000000 /* input select 2 32-63 val */ -#define GPIO0_IS_3_0_31_VAL 0x00000440 /* input select 3 0-31 val */ -#define GPIO0_IS_3_32_63_VAL 0x00000000 /* input select 3 32-63 val */ -#define GPIO0_SS_1_VAL 0x00000000 /* sync select 1 val */ -#define GPIO0_SS_2_VAL 0x00000000 /* sync select 2 val */ -#define GPIO0_SS_3_VAL 0x00000000 /* sync select 3 val */ - -/*----------------------------------------------------------------------------+ -| XILINX DEFINES -+----------------------------------------------------------------------------*/ -#define STB_XILINX_LED (STB_FPGA_BASE_ADDRESS+ 0x0100) -#define STB_XILINX1_REG0 (STB_FPGA_BASE_ADDRESS+ 0x40000) -#define STB_XILINX1_REG1 (STB_FPGA_BASE_ADDRESS+ 0x40002) -#define STB_XILINX1_REG2 (STB_FPGA_BASE_ADDRESS+ 0x40004) -#define STB_XILINX1_REG3 (STB_FPGA_BASE_ADDRESS+ 0x40006) -#define STB_XILINX1_REG4 (STB_FPGA_BASE_ADDRESS+ 0x40008) -#define STB_XILINX1_REG5 (STB_FPGA_BASE_ADDRESS+ 0x4000A) -#define STB_XILINX1_REG6 (STB_FPGA_BASE_ADDRESS+ 0x4000C) -#define STB_XILINX1_ID (STB_FPGA_BASE_ADDRESS+ 0x4000E) -#define STB_XILINX1_FLUSH (STB_FPGA_BASE_ADDRESS+ 0x4000E) -#define STB_XILINX2_REG0 (STB_FPGA_BASE_ADDRESS+ 0x80000) -#define STB_XILINX2_REG1 (STB_FPGA_BASE_ADDRESS+ 0x80002) -#define STB_XILINX2_REG2 (STB_FPGA_BASE_ADDRESS+ 0x80004) - -#define XILINX1_R0_VAL 0x2440 /* Xilinx 1 Register 0 Val */ -#define XILINX1_R1_VAL 0x0025 /* Xilinx 1 Register 1 Val */ -#define XILINX1_R2_VAL 0x0441 /* Xilinx 1 Register 2 Val */ -#define XILINX1_R3_VAL 0x0008 /* Xilinx 1 Register 3 Val */ -#define XILINX1_R4_VAL 0x0100 /* Xilinx 1 Register 4 Val */ -#define XILINX1_R5_VAL 0x6810 /* Xilinx 1 Register 5 Val */ -#define XILINX1_R6_VAL 0x0000 /* Xilinx 1 Register 6 Val */ -#if 0 -#define XILINX2_R0_VAL 0x0008 /* Xilinx 2 Register 0 Val */ -#define XILINX2_R1_VAL 0x0000 /* Xilinx 2 Register 1 Val */ -#else -#define XILINX2_R0_VAL 0x0018 /* disable IBM IrDA RxD */ -#define XILINX2_R1_VAL 0x0008 /* enable SICC MAX chip */ -#endif -#define XILINX2_R2_VAL 0x0000 /* Xilinx 2 Register 2 Val */ - -/*----------------------------------------------------------------------------+ -| HSMC BANK REGISTERS DEFINES -+----------------------------------------------------------------------------*/ -#ifdef SDRAM16MB -#define HSMC0_BR0_VAL 0x000D2D55 /* 0x1F000000-007FFFFF R/W */ -#define HSMC0_BR1_VAL 0x008D2D55 /* 0x1F800000-1FFFFFFF R/W */ -#else -#define HSMC0_BR0_VAL 0x1F0D2D55 /* 0x1F000000-007FFFFF R/W */ -#define HSMC0_BR1_VAL 0x1F8D2D55 /* 0x1F800000-1FFFFFFF R/W */ -#endif -#define HSMC1_BR0_VAL 0xA00D2D55 /* 0xA0000000-A07FFFFF R/W */ -#define HSMC1_BR1_VAL 0xA08D2D55 /* 0xA0800000-A0FFFFFF R/W */ - -/*----------------------------------------------------------------------------+ -| CACHE DEFINES -+----------------------------------------------------------------------------*/ -#define DCACHE_NLINES 128 /* no. D-cache lines */ -#define DCACHE_NBYTES 32 /* no. bytes/ D-cache line */ -#define ICACHE_NLINES 256 /* no. I-cache lines */ -#define ICACHE_NBYTES 32 /* no. bytes/ I-cache line */ -#ifdef SDRAM16MB -#define DCACHE_ENABLE 0x80000000 /* D-cache regions to enable*/ -#define ICACHE_ENABLE 0x80000001 /* I-cache regions to enable*/ -#else -#define DCACHE_ENABLE 0x18000000 /* D-cache regions to enable*/ -#define ICACHE_ENABLE 0x18000001 /* I-cache regions to enable*/ -#endif - -/*----------------------------------------------------------------------------+ -| CPU CORE SPEED CALCULATION DEFINES -+----------------------------------------------------------------------------*/ -#define GCS_LCNT 500000 /* CPU speed loop count */ -#define GCS_TROW_BYTES 8 /* no. bytes in table row */ -#define GCS_CTICK_TOL 100 /* allowable clock tick tol */ -#define GCS_NMULT 4 /* no. of core speed mults */ - - /*--------------------------------------------------------------------+ - | No. 13.5Mhz - | Clock Ticks - | based on a - | loop count Bus - | of 100,000 Speed - +--------------------------------------------------------------------*/ -gcs_lookup_table: - .int 50000, 54000000 /* 54.0 Mhz */ - .int 66667, 40500000 /* 40.5 Mhz */ - .int 54545, 49500000 /* 49.5 Mhz */ - .int 46154, 58500000 /* 58.5 Mhz */ - .int 0, 0 /* end of table flag */ - - -/*****************************************************************************+ -| XXXXXXX XXX XXX XXXXXX XXXXXXX XXXXXX XX XX XX XXXX -| XX X XX XX X XX X XX X XX XX XXX XX XXXX XX -| XX X XXX XX XX X XX XX XXXX XX XX XX XX -| XXXX X XX XXXX XXXXX XX XXXX XX XX XX -| XX X XXX XX XX X XX XX XX XXX XXXXXX XX -| XX X XX XX XX XX X XX XX XX XX XX XX XX XX -| XXXXXXX XXX XXX XXXX XXXXXXX XXX XX XX XX XX XX XXXXXXX -+*****************************************************************************/ -/****************************************************************************** -| -| Routine: INITB_EBIU0. -| -| Purpose: Initialize all the EBIU0 Bank Registers -| Parameters: None. -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_ebiu0) - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 0 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR0_VAL@h - ori r10,r10,EBIU0_BRCR0_VAL@l - mtdcr ebiu0_brcr0,r10 - lis r10,EBIU0_BRCRH0_VAL@h - ori r10,r10,EBIU0_BRCRH0_VAL@l - mtdcr ebiu0_brcrh0,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 1 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR1_VAL@h - ori r10,r10,EBIU0_BRCR1_VAL@l - mtdcr ebiu0_brcr1,r10 - lis r10,EBIU0_BRCRH1_VAL@h - ori r10,r10,EBIU0_BRCRH1_VAL@l - mtdcr ebiu0_brcrh1,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 2 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR2_VAL@h - ori r10,r10,EBIU0_BRCR2_VAL@l - mtdcr ebiu0_brcr2,r10 - lis r10,EBIU0_BRCRH2_VAL@h - ori r10,r10,EBIU0_BRCRH2_VAL@l - mtdcr ebiu0_brcrh2,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 3 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR3_VAL@h - ori r10,r10,EBIU0_BRCR3_VAL@l - mtdcr ebiu0_brcr3,r10 - lis r10,EBIU0_BRCRH3_VAL@h - ori r10,r10,EBIU0_BRCRH3_VAL@l - mtdcr ebiu0_brcrh3,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 4 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR4_VAL@h - ori r10,r10,EBIU0_BRCR4_VAL@l - mtdcr ebiu0_brcr4,r10 - lis r10,EBIU0_BRCRH4_VAL@h - ori r10,r10,EBIU0_BRCRH4_VAL@l - mtdcr ebiu0_brcrh4,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 5 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR5_VAL@h - ori r10,r10,EBIU0_BRCR5_VAL@l - mtdcr ebiu0_brcr5,r10 - lis r10,EBIU0_BRCRH5_VAL@h - ori r10,r10,EBIU0_BRCRH5_VAL@l - mtdcr ebiu0_brcrh5,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 6 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR6_VAL@h - ori r10,r10,EBIU0_BRCR6_VAL@l - mtdcr ebiu0_brcr6,r10 - lis r10,EBIU0_BRCRH6_VAL@h - ori r10,r10,EBIU0_BRCRH6_VAL@l - mtdcr ebiu0_brcrh6,r10 - - /*--------------------------------------------------------------------+ - | Set EBIU0 Bank 7 - +--------------------------------------------------------------------*/ - lis r10,EBIU0_BRCR7_VAL@h - ori r10,r10,EBIU0_BRCR7_VAL@l - mtdcr ebiu0_brcr7,r10 - lis r10,EBIU0_BRCRH7_VAL@h - ori r10,r10,EBIU0_BRCRH7_VAL@l - mtdcr ebiu0_brcrh7,r10 - - blr - function_epilog(initb_ebiu0) - - -/****************************************************************************** -| -| Routine: INITB_CONFIG -| -| Purpose: Configure the Vesta Evaluation Board. The following items -| will be configured: -| 1. Cross-Bar Switch. -| 2. Chip Interconnect. -| 3. Clear/reset key PPC registers. -| 4. Xilinx and GPIO Registers. -| -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_config) - /*--------------------------------------------------------------------+ - | Init CROSS-BAR SWITCH - +--------------------------------------------------------------------*/ - lis r10,CBS0_CR_VAL@h /* r10 <- CBS Cntl Reg val */ - ori r10,r10,CBS0_CR_VAL@l - mtdcr cbs0_cr,r10 - - /*--------------------------------------------------------------------+ - | Init Chip-Interconnect (CIC) Registers - +--------------------------------------------------------------------*/ - lis r10,CIC0_CR_VAL@h /* r10 <- CIC Cntl Reg val */ - ori r10,r10,CIC0_CR_VAL@l - mtdcr cic0_cr,r10 - - lis r10,CIC0_SEL3_VAL@h /* r10 <- CIC SEL3 Reg val */ - ori r10,r10,CIC0_SEL3_VAL@l - mtdcr cic0_sel3,r10 - - lis r10,CIC0_VCR_VAL@h /* r10 <- CIC Vid C-Reg val */ - ori r10,r10,CIC0_VCR_VAL@l - mtdcr cic0_vcr,r10 - - /*--------------------------------------------------------------------+ - | Clear SGR and DCWR - +--------------------------------------------------------------------*/ - li r10,0x0000 - mtspr sgr,r10 - mtspr dcwr,r10 - - /*--------------------------------------------------------------------+ - | Clear/set up some machine state registers. - +--------------------------------------------------------------------*/ - li r10,0x0000 /* r10 <- 0 */ - mtdcr ebiu0_besr,r10 /* clr Bus Err Syndrome Reg */ - mtspr esr,r10 /* clr Exceptn Syndrome Reg */ - mttcr r10 /* timer control register */ - - mtdcr uic0_er,r10 /* disable all interrupts */ - - /* UIC_IIC0 | UIC_IIC1 | UIC_U0 | UIC_IR_RCV | UIC_IR_XMIT */ - lis r10, 0x00600e00@h - ori r10,r10,0x00600e00@l - mtdcr uic0_pr,r10 - - li r10,0x00000020 /* UIC_EIR1 */ - mtdcr uic0_tr,r10 - - lis r10,0xFFFF /* r10 <- 0xFFFFFFFF */ - ori r10,r10,0xFFFF /* */ - mtdbsr r10 /* clear/reset the dbsr */ - mtdcr uic0_sr,r10 /* clear pending interrupts */ - - li r10,0x1000 /* set Machine Exception bit*/ - oris r10,r10,0x2 /* set Criticl Exception bit*/ - mtmsr r10 /* change MSR */ - - /*--------------------------------------------------------------------+ - | Clear XER. - +--------------------------------------------------------------------*/ - li r10,0x0000 - mtxer r10 - - /*--------------------------------------------------------------------+ - | Init GPIO0 Registers - +--------------------------------------------------------------------*/ - lis r10, STB_GPIO0_TC@h /* Three-state control */ - ori r10,r10,STB_GPIO0_TC@l - lis r11, GPIO0_TC_VAL@h - ori r11,r11,GPIO0_TC_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_OS_0_31@h /* output select 0-31 */ - ori r10,r10,STB_GPIO0_OS_0_31@l - lis r11, GPIO0_OS_0_31_VAL@h - ori r11,r11,GPIO0_OS_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_OS_32_63@h /* output select 32-63 */ - ori r10,r10,STB_GPIO0_OS_32_63@l - lis r11, GPIO0_OS_32_63_VAL@h - ori r11,r11,GPIO0_OS_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_TS_0_31@h /* three-state select 0-31 */ - ori r10,r10,STB_GPIO0_TS_0_31@l - lis r11, GPIO0_TS_0_31_VAL@h - ori r11,r11,GPIO0_TS_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_TS_32_63@h /* three-state select 32-63 */ - ori r10,r10,STB_GPIO0_TS_32_63@l - lis r11, GPIO0_TS_32_63_VAL@h - ori r11,r11,GPIO0_TS_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_OD@h /* open drain */ - ori r10,r10,STB_GPIO0_OD@l - lis r11, GPIO0_OD_VAL@h - ori r11,r11,GPIO0_OD_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_1_0_31@h /* input select 1, 0-31 */ - ori r10,r10,STB_GPIO0_IS_1_0_31@l - lis r11, GPIO0_IS_1_0_31_VAL@h - ori r11,r11,GPIO0_IS_1_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_1_32_63@h /* input select 1, 32-63 */ - ori r10,r10,STB_GPIO0_IS_1_32_63@l - lis r11, GPIO0_IS_1_32_63_VAL@h - ori r11,r11,GPIO0_IS_1_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_2_0_31@h /* input select 2, 0-31 */ - ori r10,r10,STB_GPIO0_IS_2_0_31@l - lis r11, GPIO0_IS_2_0_31_VAL@h - ori r11,r11,GPIO0_IS_2_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_2_32_63@h /* input select 2, 32-63 */ - ori r10,r10,STB_GPIO0_IS_2_32_63@l - lis r11, GPIO0_IS_2_32_63_VAL@h - ori r11,r11,GPIO0_IS_2_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_3_0_31@h /* input select 3, 0-31 */ - ori r10,r10,STB_GPIO0_IS_3_0_31@l - lis r11, GPIO0_IS_3_0_31_VAL@h - ori r11,r11,GPIO0_IS_3_0_31_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_IS_3_32_63@h /* input select 3, 32-63 */ - ori r10,r10,STB_GPIO0_IS_3_32_63@l - lis r11, GPIO0_IS_3_32_63_VAL@h - ori r11,r11,GPIO0_IS_3_32_63_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_SS_1@h /* sync select 1 */ - ori r10,r10,STB_GPIO0_SS_1@l - lis r11, GPIO0_SS_1_VAL@h - ori r11,r11,GPIO0_SS_1_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_SS_2@h /* sync select 2 */ - ori r10,r10,STB_GPIO0_SS_2@l - lis r11, GPIO0_SS_2_VAL@h - ori r11,r11,GPIO0_SS_2_VAL@l - stw r11,0(r10) - - lis r10, STB_GPIO0_SS_3@h /* sync select 3 */ - ori r10,r10,STB_GPIO0_SS_3@l - lis r11, GPIO0_SS_3_VAL@h - ori r11,r11,GPIO0_SS_3_VAL@l - stw r11,0(r10) - - /*--------------------------------------------------------------------+ - | Init Xilinx #1 Registers - +--------------------------------------------------------------------*/ - lis r10, STB_XILINX1_REG0@h /* init Xilinx1 Reg 0 */ - ori r10,r10,STB_XILINX1_REG0@l - li r11,XILINX1_R0_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG1@h /* init Xilinx1 Reg 1 */ - ori r10,r10,STB_XILINX1_REG1@l - li r11,XILINX1_R1_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG2@h /* init Xilinx1 Reg 2 */ - ori r10,r10,STB_XILINX1_REG2@l - li r11,XILINX1_R2_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG3@h /* init Xilinx1 Reg 3 */ - ori r10,r10,STB_XILINX1_REG3@l - li r11,XILINX1_R3_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG4@h /* init Xilinx1 Reg 4 */ - ori r10,r10,STB_XILINX1_REG4@l - li r11,XILINX1_R4_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG5@h /* init Xilinx1 Reg 5 */ - ori r10,r10,STB_XILINX1_REG5@l - li r11,XILINX1_R5_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_REG6@h /* init Xilinx1 Reg 6 */ - ori r10,r10,STB_XILINX1_REG6@l - li r11,XILINX1_R6_VAL - sth r11,0(r10) - - lis r10, STB_XILINX1_FLUSH@h /* latch registers in Xilinx*/ - ori r10,r10,STB_XILINX1_FLUSH@l - li r11,0x0000 - sth r11,0(r10) - - /*--------------------------------------------------------------------+ - | Init Xilinx #2 Registers - +--------------------------------------------------------------------*/ - lis r10, STB_XILINX2_REG0@h /* init Xilinx2 Reg 0 */ - ori r10,r10,STB_XILINX2_REG0@l - li r11,XILINX2_R0_VAL - sth r11,0(r10) - - lis r10, STB_XILINX2_REG1@h /* init Xilinx2 Reg 1 */ - ori r10,r10,STB_XILINX2_REG1@l - li r11,XILINX2_R1_VAL - sth r11,0(r10) - - lis r10, STB_XILINX2_REG2@h /* init Xilinx2 Reg 2 */ - ori r10,r10,STB_XILINX2_REG2@l - li r11,XILINX2_R2_VAL - sth r11,0(r10) - - blr - function_epilog(initb_config) - - -/****************************************************************************** -| -| Routine: INITB_HSMC0. -| -| Purpose: Initialize the HSMC0 Registers for SDRAM -| Parameters: None. -| Returns: R3 = 0: Successful -| = -1: Unsuccessful, SDRAM did not reset properly. -| -******************************************************************************/ - function_prolog(initb_hsmc0) - mflr r0 /* Save return addr */ - - /*--------------------------------------------------------------------+ - | Set Global SDRAM Controller to recommended default - +--------------------------------------------------------------------*/ - lis r10,0x6C00 - ori r10,r10,0x0000 - mtdcr hsmc0_gr,r10 - - /*--------------------------------------------------------------------+ - | Set HSMC0 Data Register to recommended default - +--------------------------------------------------------------------*/ - lis r10,0x0037 - ori r10,r10,0x0000 - mtdcr hsmc0_data,r10 - - /*--------------------------------------------------------------------+ - | Init HSMC0 Bank Register 0 - +--------------------------------------------------------------------*/ - lis r10,HSMC0_BR0_VAL@h - ori r10,r10,HSMC0_BR0_VAL@l - mtdcr hsmc0_br0,r10 - - /*--------------------------------------------------------------------+ - | Init HSMC0 Bank Register 1 - +--------------------------------------------------------------------*/ - lis r10,HSMC0_BR1_VAL@h - ori r10,r10,HSMC0_BR1_VAL@l - mtdcr hsmc0_br1,r10 - - /*--------------------------------------------------------------------+ - | Set HSMC0 Control Reg 0 - +--------------------------------------------------------------------*/ - lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */ - ori r10,r10,0x0000 - mtdcr hsmc0_cr0,r10 - li r3,0x0000 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - lis r10,0x8078 /* AUTO-REFRESH */ - ori r10,r10,0x0000 - mtdcr hsmc0_cr0,r10 - li r3,0x0000 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - lis r10,0x8070 /* PROG MODE W/DATA REG VAL */ - ori r10,r10,0x8000 - mtdcr hsmc0_cr0,r10 - li r3,0x0000 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne hsmc0_err - - /*--------------------------------------------------------------------+ - | Set HSMC0 Control Reg 1 - +--------------------------------------------------------------------*/ - lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */ - ori r10,r10,0x0000 - mtdcr hsmc0_cr1,r10 - li r3,0x0001 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - lis r10,0x8078 /* AUTO-REFRESH */ - ori r10,r10,0x0000 - mtdcr hsmc0_cr1,r10 - li r3,0x0001 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - lis r10,0x8070 /* PROG MODE W/DATA REG VAL */ - ori r10,r10,0x8000 - mtdcr hsmc0_cr1,r10 - li r3,0x0001 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne cr0,hsmc0_err - - /*--------------------------------------------------------------------+ - | Set HSMC0 Refresh Register - +--------------------------------------------------------------------*/ - lis r10,0x0FE1 - ori r10,r10,0x0000 - mtdcr hsmc0_crr,r10 - li r3,0 - -hsmc0_err: - mtlr r0 - blr - function_epilog(initb_hsmc0) - - -/****************************************************************************** -| -| Routine: INITB_HSMC1. -| -| Purpose: Initialize the HSMC1 Registers for SDRAM -| Parameters: None. -| Returns: R3 = 0: Successful -| = -1: Unsuccessful, SDRAM did not reset properly. -| -******************************************************************************/ - function_prolog(initb_hsmc1) - mflr r0 /* Save return addr */ - - /*--------------------------------------------------------------------+ - | Set Global SDRAM Controller to recommended default - +--------------------------------------------------------------------*/ - lis r10,0x6C00 - ori r10,r10,0x0000 - mtdcr hsmc1_gr,r10 - - /*--------------------------------------------------------------------+ - | Set HSMC1 Data Register to recommended default - +--------------------------------------------------------------------*/ - lis r10,0x0037 - ori r10,r10,0x0000 - mtdcr hsmc1_data,r10 - - /*--------------------------------------------------------------------+ - | Init HSMC1 Bank Register 0 - +--------------------------------------------------------------------*/ - lis r10,HSMC1_BR0_VAL@h - ori r10,r10,HSMC1_BR0_VAL@l - mtdcr hsmc1_br0,r10 - - /*--------------------------------------------------------------------+ - | Init HSMC1 Bank Register 1 - +--------------------------------------------------------------------*/ - lis r10,HSMC1_BR1_VAL@h - ori r10,r10,HSMC1_BR1_VAL@l - mtdcr hsmc1_br1,r10 - - /*--------------------------------------------------------------------+ - | Set HSMC1 Control Reg 0 - +--------------------------------------------------------------------*/ - lis r10,0x8077 /* PRECHARGE ALL DEVICE BANKS */ - ori r10,r10,0x0000 - mtdcr hsmc1_cr0,r10 - li r3,0x0002 - bl hsmc_cr_wait /* wait for operation completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - lis r10,0x8078 /* AUTO-REFRESH */ - ori r10,r10,0x0000 - mtdcr hsmc1_cr0,r10 - li r3,0x0002 - bl hsmc_cr_wait /* wait for operation completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - lis r10,0x8070 /* PROGRAM MODE W/DATA REG VALUE */ - ori r10,r10,0x8000 - mtdcr hsmc1_cr0,r10 - li r3,0x0002 - bl hsmc_cr_wait /* wait for operation completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - /*--------------------------------------------------------------------+ - | Set HSMC1 Control Reg 1 - +--------------------------------------------------------------------*/ - lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */ - ori r10,r10,0x0000 - mtdcr hsmc1_cr1,r10 - li r3,0x0003 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - lis r10,0x8078 /* AUTO-REFRESH */ - ori r10,r10,0x0000 - mtdcr hsmc1_cr1,r10 - li r3,0x0003 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - lis r10,0x8070 /* PROG MODE W/DATA REG VAL */ - ori r10,r10,0x8000 - mtdcr hsmc1_cr1,r10 - li r3,0x0003 - bl hsmc_cr_wait /* wait for op completion */ - cmpwi cr0,r3,0x0000 - bne hsmc1_err - - /*--------------------------------------------------------------------+ - | Set HSMC1 Refresh Register - +--------------------------------------------------------------------*/ - lis r10,0x0FE1 - ori r10,r10,0x0000 - mtdcr hsmc1_crr,r10 - xor r3,r3,r3 - -hsmc1_err: - mtlr r0 - blr - function_epilog(initb_hsmc1) - - -/****************************************************************************** -| -| Routine: INITB_CACHE -| -| Purpose: This routine will enable Data and Instruction Cache. -| The Data Cache is an 8K two-way set associative and the -| Instruction Cache is an 16K two-way set associative cache. -| -| Parameters: None. -| -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_cache) - mflr r0 /* Save return addr */ - - bl initb_Dcache /* enable D-Cache */ - bl initb_Icache /* enable I-Cache */ - - mtlr r0 - blr - function_epilog(initb_cache) - - -/****************************************************************************** -| -| Routine: INITB_DCACHE -| -| Purpose: This routine will invalidate all data in the Data Cache and -| then enable D-Cache. If cache is enabled already, the D-Cache -| will be flushed before the data is invalidated. -| -| Parameters: None. -| -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_Dcache) - /*--------------------------------------------------------------------+ - | Flush Data Cache if enabled - +--------------------------------------------------------------------*/ - mfdccr r10 /* r10 <- DCCR */ - isync /* ensure prev insts done */ - cmpwi r10,0x00 - beq ic_dcinv /* D-cache off, invalidate */ - - /*--------------------------------------------------------------------+ - | Data Cache enabled, force known memory addresses to be Cached - +--------------------------------------------------------------------*/ - lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */ - andis. r10,r10,0xFFF0 - li r11,DCACHE_NLINES /* r11 <- # A-way addresses */ - addi r11,r11,DCACHE_NLINES /* r11 <- # B-way addresses */ - mtctr r11 /* set loop counter */ - -ic_dcload: - lwz r12,0(r10) /* force cache of address */ - addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */ - bdnz ic_dcload - sync /* ensure prev insts done */ - isync - - /*--------------------------------------------------------------------+ - | Flush the known memory addresses from Cache - +--------------------------------------------------------------------*/ - lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */ - andis. r10,r10,0xFFF0 - mtctr r11 /* set loop counter */ - -ic_dcflush: - dcbf 0,r10 /* flush D-cache line */ - addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */ - bdnz ic_dcflush - sync /* ensure prev insts done */ - isync - - /*--------------------------------------------------------------------+ - | Disable then invalidate Data Cache - +--------------------------------------------------------------------*/ - li r10,0 /* r10 <- 0 */ - mtdccr r10 /* disable the D-Cache */ - isync /* ensure prev insts done */ - -ic_dcinv: - li r10,0 /* r10 <- line address */ - li r11,DCACHE_NLINES /* r11 <- # lines in cache */ - mtctr r11 /* set loop counter */ - -ic_dcloop: - dccci 0,r10 /* invalidate A/B cache lns */ - addi r10,r10,DCACHE_NBYTES /* bump to next line */ - bdnz ic_dcloop - sync /* ensure prev insts done */ - isync - - /*--------------------------------------------------------------------+ - | Enable Data Cache - +--------------------------------------------------------------------*/ - lis r10,DCACHE_ENABLE@h /* r10 <- D-cache enable msk*/ - ori r10,r10,DCACHE_ENABLE@l - mtdccr r10 - sync /* ensure prev insts done */ - isync - - blr - function_epilog(initb_Dcache) - - -/****************************************************************************** -| -| Routine: INITB_ICACHE -| -| Purpose: This routine will invalidate all data in the Instruction -| Cache then enable I-Cache. -| -| Parameters: None. -| -| Returns: None. -| -******************************************************************************/ - function_prolog(initb_Icache) - /*--------------------------------------------------------------------+ - | Invalidate Instruction Cache - +--------------------------------------------------------------------*/ - li r10,0 /* r10 <- lines address */ - iccci 0,r10 /* invalidate all I-cache */ - sync /* ensure prev insts done */ - isync - - /*--------------------------------------------------------------------+ - | Enable Instruction Cache - +--------------------------------------------------------------------*/ - lis r10,ICACHE_ENABLE@h /* r10 <- I-cache enable msk*/ - ori r10,r10,ICACHE_ENABLE@l - mticcr r10 - sync /* ensure prev insts done */ - isync - - blr - function_epilog(initb_Icache) - -#if 0 -/****************************************************************************** -| -| Routine: INITB_GET_CSPD -| -| Purpose: Determine the CPU Core Speed. The 13.5 Mhz Time Base -| Counter (TBC) is used to measure a conditional branch -| instruction. -| -| Parameters: R3 = Address of Bus Speed -| R4 = Address of Core Speed -| -| Returns: (R3) = >0: Bus Speed. -| 0: Bus Speed not found in Look-Up Table. -| (R4) = >0: Core Speed. -| 0: Core Speed not found in Look-Up Table. -| -| Note: 1. This routine assumes the bdnz branch instruction takes -| two instruction cycles to complete. -| 2. This routine must be called before interrupts are enabled. -| -******************************************************************************/ - function_prolog(initb_get_cspd) - mflr r0 /* Save return address */ - /*--------------------------------------------------------------------+ - | Set-up timed loop - +--------------------------------------------------------------------*/ - lis r9,gcs_time_loop@h /* r9 <- addr loop instr */ - ori r9,r9,gcs_time_loop@l - lis r10,GCS_LCNT@h /* r10 <- loop count */ - ori r10,r10,GCS_LCNT@l - mtctr r10 /* ctr <- loop count */ - lis r11,STB_TIMERS_TBC@h /* r11 <- TBC register addr */ - ori r11,r11,STB_TIMERS_TBC@l - li r12,0 /* r12 <- 0 */ - - /*--------------------------------------------------------------------+ - | Cache timed-loop instruction - +--------------------------------------------------------------------*/ - icbt 0,r9 - sync - isync - - /*--------------------------------------------------------------------+ - | Get number of 13.5 Mhz cycles to execute time-loop - +--------------------------------------------------------------------*/ - stw r12,0(r11) /* reset TBC */ -gcs_time_loop: - bdnz+ gcs_time_loop /* force branch pred taken */ - lwz r5,0(r11) /* r5 <- num 13.5 Mhz ticks */ - li r6,5 /* LUT based on 1/5th the...*/ - divw r5,r5,r6 /*..loop count used */ - sync - isync - - /*--------------------------------------------------------------------+ - | Look-up core speed based on TBC value - +--------------------------------------------------------------------*/ - lis r6,gcs_lookup_table@h /* r6 <- pts at core spd LUT*/ - ori r6,r6,gcs_lookup_table@l - bl gcs_cspd_lookup /* find core speed in LUT */ - - mtlr r0 /* set return address */ - blr - function_epilog(initb_get_cspd) - -#endif -/*****************************************************************************+ -| XXXX XX XX XXXXXX XXXXXXX XXXXXX XX XX XX XXXX -| XX XXX XX X XX X XX X XX XX XXX XX XXXX XX -| XX XXXX XX XX XX X XX XX XXXX XX XX XX XX -| XX XX XXXX XX XXXX XXXXX XX XXXX XX XX XX -| XX XX XXX XX XX X XX XX XX XXX XXXXXX XX -| XX XX XX XX XX X XX XX XX XX XX XX XX XX -| XXXX XX XX XXXX XXXXXXX XXX XX XX XX XX XX XXXXXXX -+*****************************************************************************/ -/****************************************************************************** -| -| Routine: HSMC_CR_WAIT -| -| Purpose: Wait for the HSMC Control Register (bits 12-16) to be reset -| after an auto-refresh, pre-charge or program mode register -| command execution. -| -| Parameters: R3 = HSMC Control Register ID. -| 0: HSMC0 CR0 -| 1: HSMC0 CR1 -| 2: HSMC1 CR0 -| 3: HSMC1 CR1 -| -| Returns: R3 = 0: Successful -| -1: Unsuccessful -| -******************************************************************************/ -hsmc_cr_wait: - - li r11,10 /* r11 <- retry counter */ - mtctr r11 /* set retry counter */ - mr r11,r3 /* r11 <- HSMC CR reg id */ - -hsmc_cr_rep: - bdz hsmc_cr_err /* branch if max retries hit*/ - - /*--------------------------------------------------------------------+ - | GET HSMCx_CRx value based on HSMC Control Register ID - +--------------------------------------------------------------------*/ -try_hsmc0_cr0: /* CHECK IF ID=HSMC0 CR0 REG*/ - cmpwi cr0,r11,0x0000 - bne cr0,try_hsmc0_cr1 - mfdcr r10,hsmc0_cr0 /* r11 <- HSMC0 CR0 value */ - b hsmc_cr_read - -try_hsmc0_cr1: /* CHECK IF ID=HSMC0 CR1 REG*/ - cmpwi cr0,r11,0x0001 - bne cr0,try_hsmc1_cr0 - mfdcr r10,hsmc0_cr1 /* r10 <- HSMC0 CR1 value */ - b hsmc_cr_read - -try_hsmc1_cr0: /* CHECK IF ID=HSMC1 CR0 REG*/ - cmpwi cr0,r11,0x0002 - bne cr0,try_hsmc1_cr1 - mfdcr r10,hsmc1_cr0 /* r10 <- HSMC1 CR0 value */ - b hsmc_cr_read - -try_hsmc1_cr1: /* CHECK IF ID=HSMC1 CR1 REG*/ - cmpwi cr0,r11,0x0003 - bne cr0,hsmc_cr_err - mfdcr r10,hsmc1_cr1 /* r10 <- HSMC1 CR1 value */ - - /*--------------------------------------------------------------------+ - | Check if HSMC CR register was reset after command execution - +--------------------------------------------------------------------*/ -hsmc_cr_read: - lis r12,0x000F /* create "AND" mask */ - ori r12,r12,0x8000 - and. r10,r10,r12 /* r10 <- HSMC CR bits 12-16*/ - bne cr0,hsmc_cr_rep /* wait for bits to reset */ - li r3,0 /* set return code = success*/ - b hsmc_cr_done - -hsmc_cr_err: /* ERROR: SDRAM didn't reset*/ - li r3,-1 /* set RC=unsuccessful */ - -hsmc_cr_done: - blr - -#if 0 -/****************************************************************************** -| -| Routine: GCS_CSPD_LOOKUP -| -| Purpose: Uses the number of 13.5 Mhz clock ticks found after executing -| the branch instruction time loop to look-up the CPU Core Speed -| in the Core Speed Look-up Table. -| -| Parameters: R3 = Address of Bus Speed -| R4 = Address of Core Speed -| R5 = Number of 13.5 Mhz clock ticks found in time loop. -| R6 = Pointer to Core-Speed Look-Up Table -| -| Returns: (R3) = >0: Bus Speed. -| 0: Bus Speed not found in Look-Up Table. -| (R4) = >0: Core Speed. -| 0: Core Speed not found in Look-Up Table. -| -| Note: Core Speed = Bus Speed * Mult Factor (1-4x). -| -******************************************************************************/ -gcs_cspd_lookup: - - li r9,1 /* r9 <- core speed mult */ - /*--------------------------------------------------------------------+ - | Get theoritical number 13.5 Mhz ticks for a given Bus Speed from - | Look-up Table. Check all mult factors to determine if calculated - | value matches theoretical value (within a tolerance). - +--------------------------------------------------------------------*/ -gcs_cspd_loop: - lwz r10,0(r6) /* r10 <- no. ticks from LUT*/ - divw r10,r10,r9 /* r10 <- div mult (1-4x) */ - subi r11,r10,GCS_CTICK_TOL /* r11 <- no. tks low range */ - addi r12,r10,GCS_CTICK_TOL /* r12 <- no. tks high range*/ - - cmpw cr0,r5,r11 /* calc value within range? */ - blt gcs_cspd_retry /* less than low range */ - cmpw cr0,r5,r12 - bgt gcs_cspd_retry /* greater than high range */ - b gcs_cspd_fnd /* calc value within range */ - - /*--------------------------------------------------------------------+ - | SO FAR CORE SPEED NOT FOUND: Check next mult factor - +--------------------------------------------------------------------*/ -gcs_cspd_retry: - addi r9,r9,1 /* bump mult factor (1-4x) */ - cmpwi cr0,r9,GCS_NMULT - ble gcs_cspd_loop - - /*--------------------------------------------------------------------+ - | SO FAR CORE SPEED NOT FOUND: Point at next Bus Speed in LUT - +--------------------------------------------------------------------*/ - li r9,1 /* reset mult factor */ - addi r6,r6,GCS_TROW_BYTES /* point at next table entry*/ - lwz r10,0(r6) - cmpwi cr0,r10,0 /* check for EOT flag */ - bne gcs_cspd_loop - - /*--------------------------------------------------------------------+ - | COMPUTE CORE SPEED AND GET BUS SPEED FROM LOOK-UP TABLE - +--------------------------------------------------------------------*/ -gcs_cspd_fnd: - lwz r5,4(r6) /* r5 <- Bus Speed in LUT */ - mullw r6,r5,r9 /* r6 <- Core speed */ - stw r5,0(r3) /* (r3) <- Bus Speed */ - stw r6,0(r4) /* (r4) <- Core Speed */ - - blr -#endif diff --git a/arch/ppc/boot/simple/rw4/stb.h b/arch/ppc/boot/simple/rw4/stb.h deleted file mode 100644 index 9afa5ab24d26..000000000000 --- a/arch/ppc/boot/simple/rw4/stb.h +++ /dev/null @@ -1,239 +0,0 @@ -/*----------------------------------------------------------------------------+ -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Author: Maciej P. Tyrlik -| Component: Include file. -| File: stb.h -| Purpose: Common Set-tob-box definitions. -| Changes: -| Date: Comment: -| ----- -------- -| 14-Jan-97 Created for ElPaso pass 1 MPT -| 13-May-97 Added function prototype and global variables MPT -| 08-Dec-98 Added RAW IR task information MPT -| 19-Jan-99 Port to Romeo MPT -| 19-May-00 Changed SDRAM to 32MB contiguous 0x1F000000 - 0x20FFFFFF RLB -+----------------------------------------------------------------------------*/ - -#ifndef _stb_h_ -#define _stb_h_ - -/*----------------------------------------------------------------------------+ -| Read/write from I/O macros. -+----------------------------------------------------------------------------*/ -#define inbyte(port) (*((unsigned char volatile *)(port))) -#define outbyte(port,data) *(unsigned char volatile *)(port)=\ - (unsigned char)(data) - -#define inshort(port) (*((unsigned short volatile *)(port))) -#define outshort(port,data) *(unsigned short volatile *)(port)=\ - (unsigned short)(data) - -#define inword(port) (*((unsigned long volatile *)(port))) -#define outword(port,data) *(unsigned long volatile *)(port)=\ - (unsigned long)(data) - -/*----------------------------------------------------------------------------+ -| STB interrupts. -+----------------------------------------------------------------------------*/ -#define STB_XP_TP_INT 0 -#define STB_XP_APP_INT 1 -#define STB_AUD_INT 2 -#define STB_VID_INT 3 -#define STB_DMA0_INT 4 -#define STB_DMA1_INT 5 -#define STB_DMA2_INT 6 -#define STB_DMA3_INT 7 -#define STB_SCI_INT 8 -#define STB_I2C1_INT 9 -#define STB_I2C2_INT 10 -#define STB_GPT_PWM0 11 -#define STB_GPT_PWM1 12 -#define STB_SCP_INT 13 -#define STB_SSP_INT 14 -#define STB_GPT_PWM2 15 -#define STB_EXT5_INT 16 -#define STB_EXT6_INT 17 -#define STB_EXT7_INT 18 -#define STB_EXT8_INT 19 -#define STB_SCC_INT 20 -#define STB_SICC_RECV_INT 21 -#define STB_SICC_TRAN_INT 22 -#define STB_PPU_INT 23 -#define STB_DCRX_INT 24 -#define STB_EXT0_INT 25 -#define STB_EXT1_INT 26 -#define STB_EXT2_INT 27 -#define STB_EXT3_INT 28 -#define STB_EXT4_INT 29 -#define STB_REDWOOD_ENET_INT STB_EXT1_INT - -/*----------------------------------------------------------------------------+ -| STB tasks, task stack sizes, and task priorities. The actual task priority -| is 1 more than the specified number since priority 0 is reserved (system -| internally adds 1 to supplied priority number). -+----------------------------------------------------------------------------*/ -#define STB_IDLE_TASK_SS (5* 1024) -#define STB_IDLE_TASK_PRIO 0 -#define STB_LEDTEST_SS (2* 1024) -#define STB_LEDTEST_PRIO 0 -#define STB_CURSOR_TASK_SS (10* 1024) -#define STB_CURSOR_TASK_PRIO 7 -#define STB_MPEG_TASK_SS (10* 1024) -#define STB_MPEG_TASK_PRIO 9 -#define STB_DEMUX_TASK_SS (10* 1024) -#define STB_DEMUX_TASK_PRIO 20 -#define RAW_STB_IR_TASK_SS (10* 1024) -#define RAW_STB_IR_TASK_PRIO 20 - -#define STB_SERIAL_ER_TASK_SS (10* 1024) -#define STB_SERIAL_ER_TASK_PRIO 1 -#define STB_CA_TASK_SS (10* 1024) -#define STB_CA_TASK_PRIO 8 - -#define INIT_DEFAULT_VIDEO_SS (10* 1024) -#define INIT_DEFAULT_VIDEO_PRIO 8 -#define INIT_DEFAULT_SERVI_SS (10* 1024) -#define INIT_DEFAULT_SERVI_PRIO 8 -#define INIT_DEFAULT_POST_SS (10* 1024) -#define INIT_DEFAULT_POST_PRIO 8 -#define INIT_DEFAULT_INTER_SS (10* 1024) -#define INIT_DEFAULT_INTER_PRIO 8 -#define INIT_DEFAULT_BR_SS (10* 1024) -#define INIT_DEFAULT_BR_PRIO 8 -#define INITIAL_TASK_STACK_SIZE (32* 1024) - -#ifdef VESTA -/*----------------------------------------------------------------------------+ -| Vesta Overall Address Map (all addresses are double mapped, bit 0 of the -| address is not decoded. Numbers below are dependent on board configuration. -| FLASH, SDRAM, DRAM numbers can be affected by actual board setup. -| -| FFE0,0000 - FFFF,FFFF FLASH -| F200,0000 - F210,FFFF FPGA logic -| Ethernet = F200,0000 -| LED Display = F200,0100 -| Xilinx #1 Regs = F204,0000 -| Xilinx #2 Regs = F208,0000 -| Spare = F20C,0000 -| IDE CS0 = F210,0000 -| F410,0000 - F410,FFFF IDE CS1 -| C000,0000 - C7FF,FFFF OBP -| C000,0000 - C000,0014 SICC (16550 + infra red) -| C001,0000 - C001,0018 PPU (Parallel Port) -| C002,0000 - C002,001B SC0 (Smart Card 0) -| C003,0000 - C003,000F I2C0 -| C004,0000 - C004,0009 SCC (16550 UART) -| C005,0000 - C005,0124 GPT (Timers) -| C006,0000 - C006,0058 GPIO0 -| C007,0000 - C007,001b SC1 (Smart Card 1) -| C008,0000 - C008,FFFF Unused -| C009,0000 - C009,FFFF Unused -| C00A,0000 - C00A,FFFF Unused -| C00B,0000 - C00B,000F I2C1 -| C00C,0000 - C00C,0006 SCP -| C00D,0000 - C00D,0010 SSP -| A000,0000 - A0FF,FFFF SDRAM1 (16M) -| 0000,0000 - 00FF,FFFF SDRAM0 (16M) -+----------------------------------------------------------------------------*/ -#define STB_FLASH_BASE_ADDRESS 0xFFE00000 -#define STB_FPGA_BASE_ADDRESS 0xF2000000 -#define STB_SICC_BASE_ADDRESS 0xC0000000 -#define STB_PPU_BASE_ADDR 0xC0010000 -#define STB_SC0_BASE_ADDRESS 0xC0020000 -#define STB_I2C1_BASE_ADDRESS 0xC0030000 -#define STB_SCC_BASE_ADDRESS 0xC0040000 -#define STB_TIMERS_BASE_ADDRESS 0xC0050000 -#define STB_GPIO0_BASE_ADDRESS 0xC0060000 -#define STB_SC1_BASE_ADDRESS 0xC0070000 -#define STB_I2C2_BASE_ADDRESS 0xC00B0000 -#define STB_SCP_BASE_ADDRESS 0xC00C0000 -#define STB_SSP_BASE_ADDRESS 0xC00D0000 -/*----------------------------------------------------------------------------+ -|The following are used by the IBM RTOS SW. -|15-May-00 Changed these values to reflect movement of base addresses in -|order to support 32MB of contiguous SDRAM space. -|Points to the cacheable region since these values are used in IBM RTOS -|to establish the vector address. -+----------------------------------------------------------------------------*/ -#define STB_SDRAM1_BASE_ADDRESS 0x20000000 -#define STB_SDRAM1_SIZE 0x01000000 -#define STB_SDRAM0_BASE_ADDRESS 0x1F000000 -#define STB_SDRAM0_SIZE 0x01000000 - -#else -/*----------------------------------------------------------------------------+ -| ElPaso Overall Address Map (all addresses are double mapped, bit 0 of the -| address is not decoded. Numbers below are dependent on board configuration. -| FLASH, SDRAM, DRAM numbers can be affected by actual board setup. OPB -| devices are inside the ElPaso chip. -| FFE0,0000 - FFFF,FFFF FLASH -| F144,0000 - F104,FFFF FPGA logic -| F140,0000 - F100,0000 ethernet (through FPGA logic) -| C000,0000 - C7FF,FFFF OBP -| C000,0000 - C000,0014 SICC (16550+ infra red) -| C001,0000 - C001,0016 PPU (parallel port) -| C002,0000 - C002,001B SC (smart card) -| C003,0000 - C003,000F I2C 1 -| C004,0000 - C004,0009 SCC (16550 UART) -| C005,0000 - C005,0124 Timers -| C006,0000 - C006,0058 GPIO0 -| C007,0000 - C007,0058 GPIO1 -| C008,0000 - C008,0058 GPIO2 -| C009,0000 - C009,0058 GPIO3 -| C00A,0000 - C00A,0058 GPIO4 -| C00B,0000 - C00B,000F I2C 2 -| C00C,0000 - C00C,0006 SCP -| C00D,0000 - C00D,0006 SSP -| A000,0000 - A0FF,FFFF SDRAM 16M -| 0000,0000 - 00FF,FFFF DRAM 16M -+----------------------------------------------------------------------------*/ -#define STB_FLASH_BASE_ADDRESS 0xFFE00000 -#define STB_FPGA_BASE_ADDRESS 0xF1440000 -#define STB_ENET_BASE_ADDRESS 0xF1400000 -#define STB_SICC_BASE_ADDRESS 0xC0000000 -#define STB_PPU_BASE_ADDR 0xC0010000 -#define STB_SC_BASE_ADDRESS 0xC0020000 -#define STB_I2C1_BASE_ADDRESS 0xC0030000 -#define STB_SCC_BASE_ADDRESS 0xC0040000 -#define STB_TIMERS_BASE_ADDRESS 0xC0050000 -#define STB_GPIO0_BASE_ADDRESS 0xC0060000 -#define STB_GPIO1_BASE_ADDRESS 0xC0070000 -#define STB_GPIO2_BASE_ADDRESS 0xC0080000 -#define STB_GPIO3_BASE_ADDRESS 0xC0090000 -#define STB_GPIO4_BASE_ADDRESS 0xC00A0000 -#define STB_I2C2_BASE_ADDRESS 0xC00B0000 -#define STB_SCP_BASE_ADDRESS 0xC00C0000 -#define STB_SSP_BASE_ADDRESS 0xC00D0000 -#define STB_SDRAM_BASE_ADDRESS 0xA0000000 -#endif - -/*----------------------------------------------------------------------------+ -| Other common defines. -+----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif /* _stb_h_ */ diff --git a/arch/ppc/boot/simple/uartlite_tty.c b/arch/ppc/boot/simple/uartlite_tty.c deleted file mode 100644 index ca1743e3e912..000000000000 --- a/arch/ppc/boot/simple/uartlite_tty.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Xilinx UARTLITE bootloader driver - * - * Copyright (c) 2007 Secret Lab Technologies Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include - -#define UARTLITE_BASEADDR ((void*)(XPAR_UARTLITE_0_BASEADDR)) - -unsigned long -serial_init(int chan, void *ignored) -{ - /* Clear the RX FIFO */ - out_be32(UARTLITE_BASEADDR + 0x0C, 0x2); - return 0; -} - -void -serial_putc(unsigned long com_port, unsigned char c) -{ - while ((in_be32(UARTLITE_BASEADDR + 0x8) & 0x08) != 0); /* spin */ - out_be32(UARTLITE_BASEADDR + 0x4, c); -} - -unsigned char -serial_getc(unsigned long com_port) -{ - while ((in_be32(UARTLITE_BASEADDR + 0x8) & 0x01) == 0); /* spin */ - return in_be32(UARTLITE_BASEADDR); -} - -int -serial_tstc(unsigned long com_port) -{ - return ((in_be32(UARTLITE_BASEADDR + 0x8) & 0x01) != 0); -} diff --git a/arch/ppc/boot/utils/.gitignore b/arch/ppc/boot/utils/.gitignore deleted file mode 100644 index bbdfb3b9c532..000000000000 --- a/arch/ppc/boot/utils/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -mkprep -mkbugboot -mktree diff --git a/arch/ppc/boot/utils/elf.pl b/arch/ppc/boot/utils/elf.pl deleted file mode 100644 index d3e9d9d5b84e..000000000000 --- a/arch/ppc/boot/utils/elf.pl +++ /dev/null @@ -1,33 +0,0 @@ -# -# ELF header field numbers -# - -$e_ident = 0; # Identification bytes / magic number -$e_type = 1; # ELF file type -$e_machine = 2; # Target machine type -$e_version = 3; # File version -$e_entry = 4; # Start address -$e_phoff = 5; # Program header file offset -$e_shoff = 6; # Section header file offset -$e_flags = 7; # File flags -$e_ehsize = 8; # Size of ELF header -$e_phentsize = 9; # Size of program header -$e_phnum = 10; # Number of program header entries -$e_shentsize = 11; # Size of section header -$e_shnum = 12; # Number of section header entries -$e_shstrndx = 13; # Section header table string index - -# -# Section header field numbers -# - -$sh_name = 0; # Section name -$sh_type = 1; # Section header type -$sh_flags = 2; # Section header flags -$sh_addr = 3; # Virtual address -$sh_offset = 4; # File offset -$sh_size = 5; # Section size -$sh_link = 6; # Miscellaneous info -$sh_info = 7; # More miscellaneous info -$sh_addralign = 8; # Memory alignment -$sh_entsize = 9; # Entry size if this is a table diff --git a/arch/ppc/boot/utils/mkbugboot.c b/arch/ppc/boot/utils/mkbugboot.c deleted file mode 100644 index 1640c4199ca6..000000000000 --- a/arch/ppc/boot/utils/mkbugboot.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Makes a Motorola PPCBUG ROM bootable image which can be flashed - * into one of the FLASH banks on a Motorola PowerPlus board. - * - * Author: Matt Porter - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#define ELF_HEADER_SIZE 65536 - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef __sun__ -#include -#else -#include -#endif - -/* size of read buffer */ -#define SIZE 0x1000 - -/* PPCBUG ROM boot header */ -typedef struct bug_boot_header { - uint8_t magic_word[4]; /* "BOOT" */ - uint32_t entry_offset; /* Offset from top of header to code */ - uint32_t routine_length; /* Length of code */ - uint8_t routine_name[8]; /* Name of the boot code */ -} bug_boot_header_t; - -#define HEADER_SIZE sizeof(bug_boot_header_t) - -void update_checksum(void *buf, size_t size, uint16_t *sum) -{ - uint32_t csum = *sum; - - while (size) { - csum += *(uint16_t *)buf; - if (csum > 0xffff) - csum -= 0xffff; - buf = (uint16_t *)buf + 1; - size -= 2; - } - *sum = csum; -} - -uint32_t copy_image(int in_fd, int out_fd, uint16_t *sum) -{ - uint8_t buf[SIZE]; - int offset = 0; - int n; - uint32_t image_size = 0; - - lseek(in_fd, ELF_HEADER_SIZE, SEEK_SET); - - /* Copy an image while recording its size */ - while ( (n = read(in_fd, buf + offset, SIZE - offset)) > 0 ) { - n += offset; - offset = n & 1; - n -= offset; - image_size = image_size + n; - /* who's going to deal with short writes? */ - write(out_fd, buf, n); - update_checksum(buf, n, sum); - if (offset) - buf[0] = buf[n]; - } - - /* BUG romboot requires that our size is divisible by 2 */ - /* align image to 2 byte boundary */ - if (offset) { - image_size += 2; - buf[1] = '\0'; - write(out_fd, buf, 2); - update_checksum(buf, 2, sum); - } - return image_size; -} - -void write_bugboot_header(int out_fd, uint32_t boot_size, uint16_t *sum) -{ - static bug_boot_header_t bbh = { - .magic_word = "BOOT", - .routine_name = "LINUXROM" - }; - - /* Fill in the PPCBUG ROM boot header */ - bbh.entry_offset = htonl(HEADER_SIZE); /* Entry address */ - bbh.routine_length= htonl(HEADER_SIZE+boot_size+2); /* Routine length */ - - /* Output the header and bootloader to the file */ - write(out_fd, &bbh, sizeof(bug_boot_header_t)); - update_checksum(&bbh, sizeof(bug_boot_header_t), sum); -} - -int main(int argc, char *argv[]) -{ - int image_fd, bugboot_fd; - uint32_t kernel_size = 0; - uint16_t checksum = 0; - - if (argc != 3) { - fprintf(stderr, "usage: %s \n",argv[0]); - exit(-1); - } - - /* Get file args */ - - /* kernel image file */ - if ((image_fd = open(argv[1] , 0)) < 0) - exit(-1); - - /* bugboot file */ - if (!strcmp(argv[2], "-")) - bugboot_fd = 1; /* stdout */ - else if ((bugboot_fd = creat(argv[2] , 0755)) < 0) - exit(-1); - - /* Set file position after ROM header block where zImage will be written */ - lseek(bugboot_fd, HEADER_SIZE, SEEK_SET); - - /* Copy kernel image into bugboot image */ - kernel_size = copy_image(image_fd, bugboot_fd, &checksum); - - /* Set file position to beginning where header/romboot will be written */ - lseek(bugboot_fd, 0, SEEK_SET); - - /* Write out BUG header/romboot */ - write_bugboot_header(bugboot_fd, kernel_size, &checksum); - - /* Write out the calculated checksum */ - lseek(bugboot_fd, 0, SEEK_END); - write(bugboot_fd, &checksum, 2); - - /* Close bugboot file */ - close(bugboot_fd); - return 0; -} diff --git a/arch/ppc/boot/utils/mkprep.c b/arch/ppc/boot/utils/mkprep.c deleted file mode 100644 index 192bb397126f..000000000000 --- a/arch/ppc/boot/utils/mkprep.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Makes a prep bootable image which can be dd'd onto - * a disk device to make a bootdisk. Will take - * as input a elf executable, strip off the header - * and write out a boot image as: - * 1) default - strips elf header - * suitable as a network boot image - * 2) -pbp - strips elf header and writes out prep boot partition image - * cat or dd onto disk for booting - * 3) -asm - strips elf header and writes out as asm data - * useful for generating data for a compressed image - * -- Cort - * - * Modified for x86 hosted builds by Matt Porter - * Modified for Sparc hosted builds by Peter Wahl - */ - -#include -#include -#include - -/* size of read buffer */ -#define SIZE 0x1000 - -/* - * Partition table entry - * - from the PReP spec - */ -typedef struct partition_entry { - unsigned char boot_indicator; - unsigned char starting_head; - unsigned char starting_sector; - unsigned char starting_cylinder; - - unsigned char system_indicator; - unsigned char ending_head; - unsigned char ending_sector; - unsigned char ending_cylinder; - - unsigned char beginning_sector[4]; - unsigned char number_of_sectors[4]; -} partition_entry_t; - -#define BootActive 0x80 -#define SystemPrep 0x41 - -void copy_image(FILE *, FILE *); -void write_prep_partition(FILE *, FILE *); -void write_asm_data(FILE *, FILE *); - -unsigned int elfhdr_size = 65536; - -int main(int argc, char *argv[]) -{ - FILE *in, *out; - int argptr = 1; - int prep = 0; - int asmoutput = 0; - - if (argc < 3 || argc > 4) { - fprintf(stderr, "usage: %s [-pbp] [-asm] \n", - argv[0]); - exit(-1); - } - -/* needs to handle args more elegantly -- but this is a small/simple program */ - - /* check for -pbp */ - if (!strcmp(argv[argptr], "-pbp")) { - prep = 1; - argptr++; - } - - /* check for -asm */ - if (!strcmp(argv[argptr], "-asm")) { - asmoutput = 1; - argptr++; - } - - /* input file */ - if (!strcmp(argv[argptr], "-")) - in = stdin; - else if (!(in = fopen(argv[argptr], "r"))) - exit(-1); - argptr++; - - /* output file */ - if (!strcmp(argv[argptr], "-")) - out = stdout; - else if (!(out = fopen(argv[argptr], "w"))) - exit(-1); - argptr++; - - /* skip elf header in input file */ - /*if ( !prep )*/ - fseek(in, elfhdr_size, SEEK_SET); - - /* write prep partition if necessary */ - if (prep) - write_prep_partition(in, out); - - /* write input image to bootimage */ - if (asmoutput) - write_asm_data(in, out); - else - copy_image(in, out); - - return 0; -} - -void store_le32(unsigned int v, unsigned char *p) -{ - p[0] = v; - p[1] = v >>= 8; - p[2] = v >>= 8; - p[3] = v >> 8; -} - -void write_prep_partition(FILE *in, FILE *out) -{ - unsigned char block[512]; - partition_entry_t pe; - unsigned char *entry = block; - unsigned char *length = block + 4; - long pos = ftell(in), size; - - if (fseek(in, 0, SEEK_END) < 0) { - fprintf(stderr,"info failed\n"); - exit(-1); - } - size = ftell(in); - if (fseek(in, pos, SEEK_SET) < 0) { - fprintf(stderr,"info failed\n"); - exit(-1); - } - - memset(block, '\0', sizeof(block)); - - /* set entry point and boot image size skipping over elf header */ - store_le32(0x400/*+65536*/, entry); - store_le32(size-elfhdr_size+0x400, length); - - /* sets magic number for msdos partition (used by linux) */ - block[510] = 0x55; - block[511] = 0xAA; - - /* - * Build a "PReP" partition table entry in the boot record - * - "PReP" may only look at the system_indicator - */ - pe.boot_indicator = BootActive; - pe.system_indicator = SystemPrep; - /* - * The first block of the diskette is used by this "boot record" which - * actually contains the partition table. (The first block of the - * partition contains the boot image, but I digress...) We'll set up - * one partition on the diskette and it shall contain the rest of the - * diskette. - */ - pe.starting_head = 0; /* zero-based */ - pe.starting_sector = 2; /* one-based */ - pe.starting_cylinder = 0; /* zero-based */ - pe.ending_head = 1; /* assumes two heads */ - pe.ending_sector = 18; /* assumes 18 sectors/track */ - pe.ending_cylinder = 79; /* assumes 80 cylinders/diskette */ - - /* - * The "PReP" software ignores the above fields and just looks at - * the next two. - * - size of the diskette is (assumed to be) - * (2 tracks/cylinder)(18 sectors/tracks)(80 cylinders/diskette) - * - unlike the above sector numbers, the beginning sector is zero-based! - */ -#if 0 - store_le32(1, pe.beginning_sector); -#else - /* This has to be 0 on the PowerStack? */ - store_le32(0, pe.beginning_sector); -#endif - - store_le32(2*18*80-1, pe.number_of_sectors); - - memcpy(&block[0x1BE], &pe, sizeof(pe)); - - fwrite(block, sizeof(block), 1, out); - fwrite(entry, 4, 1, out); - fwrite(length, 4, 1, out); - /* set file position to 2nd sector where image will be written */ - fseek( out, 0x400, SEEK_SET ); -} - - - -void copy_image(FILE *in, FILE *out) -{ - char buf[SIZE]; - int n; - - while ( (n = fread(buf, 1, SIZE, in)) > 0 ) - fwrite(buf, 1, n, out); -} - - -void -write_asm_data(FILE *in, FILE *out) -{ - int i, cnt, pos = 0; - unsigned int cksum = 0, val; - unsigned char *lp; - unsigned char buf[SIZE]; - size_t len; - - fputs("\t.data\n\t.globl input_data\ninput_data:\n", out); - while ((len = fread(buf, 1, sizeof(buf), in)) > 0) { - cnt = 0; - lp = buf; - /* Round up to longwords */ - while (len & 3) - buf[len++] = '\0'; - for (i = 0; i < len; i += 4) { - if (cnt == 0) - fputs("\t.long\t", out); - fprintf(out, "0x%02X%02X%02X%02X", - lp[0], lp[1], lp[2], lp[3]); - val = *(unsigned long *)lp; - cksum ^= val; - lp += 4; - if (++cnt == 4) { - cnt = 0; - fprintf(out, " # %x \n", pos+i-12); - } else { - fputs(",", out); - } - } - if (cnt) - fputs("0\n", out); - pos += len; - } - fprintf(out, "\t.globl input_len\ninput_len:\t.long\t0x%x\n", pos); - fprintf(stderr, "cksum = %x\n", cksum); -} diff --git a/arch/ppc/boot/utils/mktree.c b/arch/ppc/boot/utils/mktree.c deleted file mode 100644 index 2be22e28f2b3..000000000000 --- a/arch/ppc/boot/utils/mktree.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Makes a tree bootable image for IBM Evaluation boards. - * Basically, just take a zImage, skip the ELF header, and stuff - * a 32 byte header on the front. - * - * We use htonl, which is a network macro, to make sure we're doing - * The Right Thing on an LE machine. It's non-obvious, but it should - * work on anything BSD'ish. - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef __sun__ -#include -#else -#include -#endif - -/* This gets tacked on the front of the image. There are also a few - * bytes allocated after the _start label used by the boot rom (see - * head.S for details). - */ -typedef struct boot_block { - uint32_t bb_magic; /* 0x0052504F */ - uint32_t bb_dest; /* Target address of the image */ - uint32_t bb_num_512blocks; /* Size, rounded-up, in 512 byte blks */ - uint32_t bb_debug_flag; /* Run debugger or image after load */ - uint32_t bb_entry_point; /* The image address to start */ - uint32_t bb_checksum; /* 32 bit checksum including header */ - uint32_t reserved[2]; -} boot_block_t; - -#define IMGBLK 512 -char tmpbuf[IMGBLK]; - -int main(int argc, char *argv[]) -{ - int in_fd, out_fd; - int nblks, i; - uint cksum, *cp; - struct stat st; - boot_block_t bt; - - if (argc < 3) { - fprintf(stderr, "usage: %s [entry-point]\n",argv[0]); - exit(1); - } - - if (stat(argv[1], &st) < 0) { - perror("stat"); - exit(2); - } - - nblks = (st.st_size + IMGBLK) / IMGBLK; - - bt.bb_magic = htonl(0x0052504F); - - /* If we have the optional entry point parameter, use it */ - if (argc == 4) - bt.bb_dest = bt.bb_entry_point = htonl(strtoul(argv[3], NULL, 0)); - else - bt.bb_dest = bt.bb_entry_point = htonl(0x500000); - - /* We know these from the linker command. - * ...and then move it up into memory a little more so the - * relocation can happen. - */ - bt.bb_num_512blocks = htonl(nblks); - bt.bb_debug_flag = 0; - - bt.bb_checksum = 0; - - /* To be neat and tidy :-). - */ - bt.reserved[0] = 0; - bt.reserved[1] = 0; - - if ((in_fd = open(argv[1], O_RDONLY)) < 0) { - perror("zImage open"); - exit(3); - } - - if ((out_fd = open(argv[2], (O_RDWR | O_CREAT | O_TRUNC), 0666)) < 0) { - perror("bootfile open"); - exit(3); - } - - cksum = 0; - cp = (void *)&bt; - for (i=0; i 0) { - if (read(in_fd, tmpbuf, IMGBLK) < 0) { - perror("zImage read"); - exit(5); - } - cp = (uint *)tmpbuf; - for (i=0; i kernelspace linker -# -# CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -# CONFIG_MTD_CFI_I1 is not set -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0xff000000 -CONFIG_MTD_PHYSMAP_LEN=0x01000000 -CONFIG_MTD_PHYSMAP_BANKWIDTH=4 -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_SLRAM is not set -CONFIG_MTD_PHRAM=y -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=32768 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# - -# -# Ethernet (10 or 100Mbit) -# -# CONFIG_NET_ETHERNET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_MV643XX_ETH=y -CONFIG_MV643XX_ETH_0=y -# CONFIG_MV643XX_ETH_1 is not set -# CONFIG_MV643XX_ETH_2 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_MPSC=y -CONFIG_SERIAL_MPSC_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_MV64X60_WDT=y - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Misc devices -# - -# -# Multimedia Capabilities Port drivers -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# SN Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_RELAYFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# diff --git a/arch/ppc/configs/hdpu_defconfig b/arch/ppc/configs/hdpu_defconfig deleted file mode 100644 index 956a17897e33..000000000000 --- a/arch/ppc/configs/hdpu_defconfig +++ /dev/null @@ -1,890 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.11 -# Wed Mar 16 12:43:19 2005 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_LOCK_KERNEL=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_HOTPLUG=y -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -# CONFIG_CPUSETS is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y -CONFIG_STOP_MACHINE=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_E500 is not set -CONFIG_ALTIVEC=y -# CONFIG_TAU is not set -# CONFIG_CPU_FREQ is not set -# CONFIG_PM is not set -CONFIG_PPC_STD_MMU=y -# CONFIG_NOT_COHERENT_CACHE is not set - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_KATANA is not set -# CONFIG_WILLOW is not set -# CONFIG_CPCI690 is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_CHESTNUT is not set -# CONFIG_SPRUCE is not set -CONFIG_HDPU=y -# CONFIG_EV64260 is not set -# CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_RADSTONE_PPC7D is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBC82xx is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX8260 is not set -# CONFIG_TQM8260 is not set -# CONFIG_ADS8272 is not set -# CONFIG_PQ2FADS is not set -# CONFIG_LITE5200 is not set -# CONFIG_MPC834x_SYS is not set -CONFIG_MV64360=y -CONFIG_MV64X60=y - -# -# Set bridge options -# -CONFIG_MV64X60_BASE=0xf1000000 -CONFIG_MV64X60_NEW_BASE=0xf1000000 -# CONFIG_SMP is not set -# CONFIG_IRQ_ALL_CPUS is not set -# CONFIG_NR_CPUS is not set -CONFIG_PREEMPT=y -CONFIG_HIGHMEM=y -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=y -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="root=/dev/nfs ip=auto" - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# Advanced setup -# -CONFIG_ADVANCED_OPTIONS=y -# CONFIG_HIGHMEM_START_BOOL is not set -CONFIG_HIGHMEM_START=0xfe000000 -# CONFIG_LOWMEM_SIZE_BOOL is not set -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START_BOOL=y -CONFIG_KERNEL_START=0x80000000 -# CONFIG_TASK_SIZE_BOOL is not set -CONFIG_TASK_SIZE=0x80000000 -# CONFIG_BOOT_LOAD_BOOL is not set -CONFIG_BOOT_LOAD=0x00800000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -# CONFIG_MTD_BLOCK is not set -# CONFIG_MTD_BLOCK_RO is not set -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0xfc000000 -CONFIG_MTD_PHYSMAP_LEN=0x04000000 -CONFIG_MTD_PHYSMAP_BANKWIDTH=4 - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_CHR_DEV_SG=y - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI Transport Attributes -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -CONFIG_SCSI_AIC7XXX=y -CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 -CONFIG_AIC7XXX_RESET_DELAY_MS=15000 -# CONFIG_AIC7XXX_DEBUG_ENABLE is not set -CONFIG_AIC7XXX_DEBUG_MASK=0 -# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=y -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_IP_TCPDIAG is not set -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set -CONFIG_MV643XX_ETH=y -CONFIG_MV643XX_ETH_0=y -# CONFIG_MV643XX_ETH_1 is not set -# CONFIG_MV643XX_ETH_2 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_MPSC=y -CONFIG_SERIAL_MPSC_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -# CONFIG_ZISOFS is not set -CONFIG_UDF_FS=y -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFFS2_FS_NAND is not set -# CONFIG_JFFS2_FS_NOR_ECC is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_NFS_DIRECTIO=y -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V4=y -CONFIG_NFSD_TCP=y -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_TGR192 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# diff --git a/arch/ppc/configs/katana_defconfig b/arch/ppc/configs/katana_defconfig deleted file mode 100644 index 7311fe6b42de..000000000000 --- a/arch/ppc/configs/katana_defconfig +++ /dev/null @@ -1,948 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-mm1 -# Thu Sep 1 17:16:03 2005 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_EMBEDDED is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_E200 is not set -# CONFIG_E500 is not set -CONFIG_PPC_FPU=y -CONFIG_ALTIVEC=y -# CONFIG_TAU is not set -# CONFIG_KEXEC is not set -# CONFIG_CPU_FREQ is not set -# CONFIG_WANT_EARLY_SERIAL is not set -CONFIG_PPC_STD_MMU=y -CONFIG_NOT_COHERENT_CACHE=y - -# -# Performance-monitoring counters support -# -# CONFIG_PERFCTR is not set - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -CONFIG_KATANA=y -# CONFIG_WILLOW is not set -# CONFIG_CPCI690 is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_CHESTNUT is not set -# CONFIG_SPRUCE is not set -# CONFIG_HDPU is not set -# CONFIG_EV64260 is not set -# CONFIG_LOPEC is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_RADSTONE_PPC7D is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBC82xx is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX8260 is not set -# CONFIG_TQM8260 is not set -# CONFIG_ADS8272 is not set -# CONFIG_PQ2FADS is not set -# CONFIG_LITE5200 is not set -# CONFIG_MPC834x_SYS is not set -# CONFIG_EV64360 is not set -CONFIG_MV64360=y -CONFIG_MV64X60=y - -# -# Set bridge options -# -CONFIG_MV64X60_BASE=0xf8100000 -CONFIG_MV64X60_NEW_BASE=0xf8100000 -# CONFIG_SMP is not set -CONFIG_HIGHMEM=y -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=y -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyMM0 ip=on" -# CONFIG_PM is not set -CONFIG_SECCOMP=y -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LEGACY_PROC=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# Advanced setup -# -CONFIG_ADVANCED_OPTIONS=y -# CONFIG_HIGHMEM_START_BOOL is not set -CONFIG_HIGHMEM_START=0xfe000000 -# CONFIG_LOWMEM_SIZE_BOOL is not set -CONFIG_LOWMEM_SIZE=0x30000000 -# CONFIG_KERNEL_START_BOOL is not set -CONFIG_KERNEL_START=0xc0000000 -# CONFIG_TASK_SIZE_BOOL is not set -CONFIG_TASK_SIZE=0x80000000 -CONFIG_CONSISTENT_START_BOOL=y -CONFIG_CONSISTENT_START=0xf0000000 -CONFIG_CONSISTENT_SIZE_BOOL=y -CONFIG_CONSISTENT_SIZE=0x00400000 -# CONFIG_BOOT_LOAD_BOOL is not set -CONFIG_BOOT_LOAD=0x00800000 - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETFILTER_NETLINK is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_IEEE80211 is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -# CONFIG_MTD_CFI_I1 is not set -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0xe0000000 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_BANKWIDTH=4 -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_SLRAM is not set -CONFIG_MTD_PHRAM=y -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -# CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -CONFIG_NET_TULIP=y -# CONFIG_DE2104X is not set -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -# CONFIG_TULIP_MMIO is not set -# CONFIG_TULIP_NAPI is not set -# CONFIG_DE4X5 is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_ULI526X is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -CONFIG_E100=y -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -CONFIG_E1000=y -# CONFIG_E1000_NAPI is not set -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_MV643XX_ETH=y -CONFIG_MV643XX_ETH_0=y -CONFIG_MV643XX_ETH_1=y -CONFIG_MV643XX_ETH_2=y - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_KGDBOE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NETPOLL_RX is not set -# CONFIG_NETPOLL_TRAP is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_MPSC=y -CONFIG_SERIAL_MPSC_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y - -# -# I2C Algorithms -# -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# -# I2C Hardware Bus support -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_MPC is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_SCx200_ACB is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_VOODOO3 is not set -# CONFIG_I2C_PCA_ISA is not set -CONFIG_I2C_MV64XXX=y - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_RTC8564 is not set -CONFIG_SENSORS_M41T00=y -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Misc devices -# - -# -# Multimedia Capabilities Port drivers -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Speakup console speech -# -# CONFIG_SPEAKUP is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# SN Devices -# - -# -# Distributed Lock Manager -# -# CONFIG_DLM is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISER4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set -# CONFIG_RELAYFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_ASFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# diff --git a/arch/ppc/configs/lite5200_defconfig b/arch/ppc/configs/lite5200_defconfig deleted file mode 100644 index 7e7a943d8cfe..000000000000 --- a/arch/ppc/configs/lite5200_defconfig +++ /dev/null @@ -1,436 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_STANDALONE=y -CONFIG_BROKEN_ON_SMP=y -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -# CONFIG_EMBEDDED is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y -CONFIG_KMOD=y -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_E500 is not set -# CONFIG_ALTIVEC is not set -# CONFIG_TAU is not set -# CONFIG_CPU_FREQ is not set -CONFIG_FSL_OCP=y -CONFIG_PPC_STD_MMU=y -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_WILLOW is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_EV64260 is not set -# CONFIG_SPRUCE is not set -# CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBC82xx is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX6 is not set -# CONFIG_TQM8260 is not set -# CONFIG_ADS8272 is not set -CONFIG_LITE5200=y -CONFIG_PPC_MPC52xx=y -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyS0 root=/dev/ram0 rw" -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set -# -# Advanced setup -# -CONFIG_ADVANCED_OPTIONS=y -CONFIG_HIGHMEM_START=0xfe000000 -# CONFIG_LOWMEM_SIZE_BOOL is not set -CONFIG_LOWMEM_SIZE=0x30000000 -# CONFIG_KERNEL_START_BOOL is not set -CONFIG_KERNEL_START=0xc0000000 -# CONFIG_TASK_SIZE_BOOL is not set -CONFIG_TASK_SIZE=0x80000000 -# CONFIG_BOOT_LOAD_BOOL is not set -CONFIG_BOOT_LOAD=0x00800000 -# -# Device Drivers -# -# -# Generic Driver Options -# -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_DEBUG_DRIVER is not set -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set -# -# Parallel port support -# -# CONFIG_PARPORT is not set -# -# Plug and Play support -# -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set -# -# SCSI device support -# -# CONFIG_SCSI is not set -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# -# Fusion MPT device support -# -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set -# -# I2O device support -# -# CONFIG_I2O is not set -# -# Macintosh device drivers -# -# -# Networking support -# -# CONFIG_NET is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# -# ISDN subsystem -# -# -# Telephony Support -# -# CONFIG_PHONE is not set -# -# Input device support -# -CONFIG_INPUT=y -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=y -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_MPC52xx=y -CONFIG_SERIAL_MPC52xx_CONSOLE=y -CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD=9600 -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set -# -# I2C support -# -# CONFIG_I2C is not set -# -# Misc devices -# -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -# -# Digital Video Broadcasting Devices -# -# -# Graphics support -# -# CONFIG_FB is not set -# -# Console display driver support -# -CONFIG_VGA_CONSOLE=y -# CONFIG_MDA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# -# Sound -# -# CONFIG_SOUND is not set -# -# USB support -# -# CONFIG_USB is not set -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# -# Native Language Support -# -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=m -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# -# Library routines -# -# CONFIG_CRC16 is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -# -# Profiling support -# -# CONFIG_PROFILING is not set -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SLAB is not set -CONFIG_MAGIC_SYSRQ=y -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_SPINLOCK_SLEEP=y -# CONFIG_KGDB is not set -# CONFIG_XMON is not set -# CONFIG_BDI_SWITCH is not set -CONFIG_DEBUG_INFO=y -CONFIG_SERIAL_TEXT_DEBUG=y -CONFIG_PPC_OCP=y -# -# Security options -# -# CONFIG_SECURITY is not set -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/lopec_defconfig b/arch/ppc/configs/lopec_defconfig deleted file mode 100644 index 85ea06b3b5c6..000000000000 --- a/arch/ppc/configs/lopec_defconfig +++ /dev/null @@ -1,814 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_STANDALONE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_HOTPLUG=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -CONFIG_ALTIVEC=y -# CONFIG_TAU is not set -# CONFIG_CPU_FREQ is not set -CONFIG_PPC_STD_MMU=y - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_WILLOW is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_EV64260 is not set -# CONFIG_SPRUCE is not set -CONFIG_LOPEC=y -# CONFIG_MCPN765 is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX6 is not set -# CONFIG_TQM8260 is not set -CONFIG_EPIC_SERIAL_MODE=y -CONFIG_MPC10X_BRIDGE=y -# CONFIG_MPC10X_STORE_GATHERING is not set -CONFIG_PPCBUG_NVRAM=y -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=m -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -CONFIG_PCI_NAMES=y - -# -# PCMCIA/CardBus support -# -# CONFIG_PCMCIA is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -CONFIG_BLK_DEV_LOOP=m -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_CARMEL is not set -CONFIG_BLK_DEV_RAM=m -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y -# CONFIG_IDEDISK_STROKE is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_IDE_TASK_IOCTL is not set -# CONFIG_IDE_TASKFILE_IO is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -CONFIG_BLK_DEV_IDEPCI=y -# CONFIG_IDEPCI_SHARE_IRQ is not set -# CONFIG_BLK_DEV_OFFBOARD is not set -CONFIG_BLK_DEV_GENERIC=y -# CONFIG_BLK_DEV_OPTI621 is not set -CONFIG_BLK_DEV_SL82C105=y -CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -CONFIG_IDEDMA_PCI_AUTO=y -# CONFIG_IDEDMA_ONLYDISK is not set -CONFIG_BLK_DEV_ADMA=y -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_SC1200 is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -CONFIG_IDEDMA_AUTO=y -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_REPORT_LUNS is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=y -# CONFIG_SCSI_FC_ATTRS is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INIA100 is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=y -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_QLA6322 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -CONFIG_E100=y -# CONFIG_E100_NAPI is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Userland interfaces -# - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB=m -# CONFIG_USB_DEBUG is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_BANDWIDTH is not set -# CONFIG_USB_DYNAMIC_MINORS is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_EHCI_HCD is not set -CONFIG_USB_OHCI_HCD=m -# CONFIG_USB_UHCI_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_BLUETOOTH_TTY is not set -CONFIG_USB_ACM=m -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_STORAGE is not set - -# -# USB Human Interface Devices (HID) -# -CONFIG_USB_HID=m - -# -# Input core support is needed for USB HID input layer or HIDBP support -# -# CONFIG_USB_HIDDEV is not set - -# -# USB HID Boot Protocol drivers -# - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# -# CONFIG_USB_DABUSB is not set - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# - -# -# USB Serial Converter support -# -CONFIG_USB_SERIAL=m -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -CONFIG_USB_SERIAL_VISOR=m -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_TIGL is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGETSERVO is not set -# CONFIG_USB_TEST is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/luan_defconfig b/arch/ppc/configs/luan_defconfig deleted file mode 100644 index 71d7bf192e0e..000000000000 --- a/arch/ppc/configs/luan_defconfig +++ /dev/null @@ -1,668 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Mon Jan 31 16:26:31 2005 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_FUTEX=y -CONFIG_EPOLL=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Processor -# -# CONFIG_6xx is not set -# CONFIG_40x is not set -CONFIG_44x=y -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_E500 is not set -CONFIG_BOOKE=y -CONFIG_PTE_64BIT=y -CONFIG_PHYS_64BIT=y -# CONFIG_MATH_EMULATION is not set -# CONFIG_CPU_FREQ is not set -CONFIG_4xx=y - -# -# IBM 4xx options -# -# CONFIG_EBONY is not set -CONFIG_LUAN=y -# CONFIG_OCOTEA is not set -CONFIG_440SP=y -CONFIG_440=y -CONFIG_IBM_OCP=y -CONFIG_IBM_EMAC4=y -# CONFIG_PPC4xx_DMA is not set -CONFIG_PPC_GEN550=y -# CONFIG_PM is not set -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_PC_KEYBOARD is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on console=ttyS0,115200" - -# -# Bus options -# -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PC-card bridges -# - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_CONSISTENT_START=0xff100000 -CONFIG_CONSISTENT_SIZE=0x00200000 -CONFIG_BOOT_LOAD=0x01000000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# -# CONFIG_STANDALONE is not set -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_CONNTRACK_MARK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_IBM_EMAC=y -# CONFIG_IBM_EMAC_ERRMSG is not set -CONFIG_IBM_EMAC_RXB=128 -CONFIG_IBM_EMAC_TXB=128 -CONFIG_IBM_EMAC_FGAP=8 -CONFIG_IBM_EMAC_SKBRES=0 -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -# CONFIG_SERIAL_8250_MANY_PORTS is not set -CONFIG_SERIAL_8250_SHARE_IRQ=y -# CONFIG_SERIAL_8250_DETECT_IRQ is not set -# CONFIG_SERIAL_8250_MULTIPORT is not set -# CONFIG_SERIAL_8250_RSA is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_FS is not set -# CONFIG_KGDB is not set -# CONFIG_XMON is not set -CONFIG_BDI_SWITCH=y -# CONFIG_SERIAL_TEXT_DEBUG is not set -CONFIG_PPC_OCP=y - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# diff --git a/arch/ppc/configs/mbx_defconfig b/arch/ppc/configs/mbx_defconfig deleted file mode 100644 index 52c3799e67ba..000000000000 --- a/arch/ppc/configs/mbx_defconfig +++ /dev/null @@ -1,512 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EMBEDDED=y -CONFIG_FUTEX=y -# CONFIG_EPOLL is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Platform support -# -CONFIG_PPC=y -CONFIG_PPC32=y -# CONFIG_6xx is not set -# CONFIG_40x is not set -# CONFIG_POWER3 is not set -CONFIG_8xx=y - -# -# IBM 4xx options -# -CONFIG_EMBEDDEDBOOT=y -CONFIG_SERIAL_CONSOLE=y -CONFIG_NOT_COHERENT_CACHE=y -# CONFIG_RPXLITE is not set -# CONFIG_RPXCLASSIC is not set -# CONFIG_BSEIP is not set -# CONFIG_FADS is not set -# CONFIG_TQM823L is not set -# CONFIG_TQM850L is not set -# CONFIG_TQM855L is not set -# CONFIG_TQM860L is not set -# CONFIG_FPS850L is not set -# CONFIG_SPD823TS is not set -# CONFIG_IVMS8 is not set -# CONFIG_IVML24 is not set -# CONFIG_SM850 is not set -# CONFIG_HERMES_PRO is not set -# CONFIG_IP860 is not set -# CONFIG_LWMON is not set -# CONFIG_PCU_E is not set -# CONFIG_CCM is not set -# CONFIG_LANTEC is not set -CONFIG_MBX=y -# CONFIG_WINCEPT is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -CONFIG_MATH_EMULATION=y -# CONFIG_CPU_FREQ is not set - -# -# General setup -# -# CONFIG_HIGHMEM is not set -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set -# CONFIG_PCI_QSPAN is not set -CONFIG_KCORE_ELF=y -CONFIG_BINFMT_ELF=y -CONFIG_KERNEL_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_HOTPLUG is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set -# CONFIG_CMDLINE_BOOL is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play support -# -# CONFIG_PNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# ATA/IDE/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Fusion MPT device support -# - -# -# I2O device support -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK_DEV is not set -# CONFIG_NETFILTER is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_INET_ECN is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_XFRM_USER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -CONFIG_IPV6_SCTP__=y -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_LLC is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices (depends on LLC=y) -# -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# IrDA (infrared) support -# -# CONFIG_IRDA is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN_BOOL is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Old CD-ROM drivers (not SCSI, not IDE) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Userland interfaces -# - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set - -# -# Input Device Drivers -# - -# -# Macintosh device drivers -# - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_CPM=y -CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -CONFIG_SERIAL_CPM_SCC2=y -CONFIG_SERIAL_CPM_SCC3=y -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -CONFIG_SERIAL_CPM_SMC2=y -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# I2C Hardware Sensors Mainboard support -# - -# -# I2C Hardware Sensors Chip support -# -# CONFIG_I2C_SENSOR is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_HANGCHECK_TIMER is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -CONFIG_TMPFS=y -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_SUNRPC_GSS is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MSDOS_PARTITION is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_NEC98_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_EFI_PARTITION is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# MPC8xx CPM Options -# -CONFIG_SCC_ENET=y -CONFIG_SCC1_ENET=y -# CONFIG_SCC2_ENET is not set -# CONFIG_SCC3_ENET is not set -# CONFIG_FEC_ENET is not set -CONFIG_ENET_BIG_BUFFERS=y - -# -# Generic MPC8xx Options -# -CONFIG_8xx_COPYBACK=y -CONFIG_8xx_CPU6=y -# CONFIG_UCODE_PATCH is not set - -# -# USB support -# -# CONFIG_USB_GADGET is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Library routines -# -# CONFIG_CRC32 is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_KALLSYMS is not set - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/ml300_defconfig b/arch/ppc/configs/ml300_defconfig deleted file mode 100644 index d66cacdb95be..000000000000 --- a/arch/ppc/configs/ml300_defconfig +++ /dev/null @@ -1,739 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.16-rc1 -# Wed Jan 18 00:49:20 2006 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_EMBEDDED is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -CONFIG_SLAB=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# -CONFIG_LBD=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Processor -# -# CONFIG_6xx is not set -CONFIG_40x=y -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_8xx is not set -# CONFIG_E200 is not set -# CONFIG_E500 is not set -# CONFIG_MATH_EMULATION is not set -# CONFIG_KEXEC is not set -# CONFIG_CPU_FREQ is not set -CONFIG_4xx=y -# CONFIG_WANT_EARLY_SERIAL is not set - -# -# IBM 4xx options -# -# CONFIG_BUBINGA is not set -# CONFIG_CPCI405 is not set -# CONFIG_EP405 is not set -# CONFIG_REDWOOD_5 is not set -# CONFIG_REDWOOD_6 is not set -# CONFIG_SYCAMORE is not set -# CONFIG_WALNUT is not set -CONFIG_XILINX_ML300=y -CONFIG_IBM405_ERR77=y -CONFIG_IBM405_ERR51=y -CONFIG_XILINX_VIRTEX=y -CONFIG_EMBEDDEDBOOT=y -# CONFIG_PPC4xx_DMA is not set -CONFIG_PPC_GEN550=y -CONFIG_UART0_TTYS0=y -# CONFIG_UART0_TTYS1 is not set -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_PC_KEYBOARD is not set -# CONFIG_HIGHMEM is not set -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyS0,9600" -# CONFIG_PM is not set -# CONFIG_HIBERNATION is not set -CONFIG_SECCOMP=y -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -# CONFIG_PPC_I8259 is not set -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_CONSISTENT_START=0xff100000 -CONFIG_CONSISTENT_SIZE=0x00200000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_IEEE80211 is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -# CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Macintosh device drivers -# -# CONFIG_WINDFARM is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -CONFIG_TUN=y - -# -# PHY device support -# - -# -# Ethernet (10 or 100Mbit) -# -# CONFIG_NET_ETHERNET is not set -# CONFIG_IBM_EMAC is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia Capabilities Port drivers -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Console display driver support -# -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# - -# -# SN Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_RELAYFS_FS is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -# CONFIG_NFS_FS is not set -# CONFIG_NFSD is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y - -# -# IBM 40x options -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_VM is not set -CONFIG_FORCED_INLINING=y -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_KGDB is not set -# CONFIG_XMON is not set -# CONFIG_BDI_SWITCH is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# diff --git a/arch/ppc/configs/ml403_defconfig b/arch/ppc/configs/ml403_defconfig deleted file mode 100644 index 71bcfa7ab7f7..000000000000 --- a/arch/ppc/configs/ml403_defconfig +++ /dev/null @@ -1,740 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.16-rc1 -# Wed Jan 18 01:11:41 2006 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_EMBEDDED is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -CONFIG_SLAB=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# -CONFIG_LBD=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Processor -# -# CONFIG_6xx is not set -CONFIG_40x=y -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_8xx is not set -# CONFIG_E200 is not set -# CONFIG_E500 is not set -# CONFIG_MATH_EMULATION is not set -# CONFIG_KEXEC is not set -# CONFIG_CPU_FREQ is not set -CONFIG_4xx=y -# CONFIG_WANT_EARLY_SERIAL is not set - -# -# IBM 4xx options -# -# CONFIG_BUBINGA is not set -# CONFIG_CPCI405 is not set -# CONFIG_EP405 is not set -# CONFIG_REDWOOD_5 is not set -# CONFIG_REDWOOD_6 is not set -# CONFIG_SYCAMORE is not set -# CONFIG_WALNUT is not set -# CONFIG_XILINX_ML300 is not set -CONFIG_XILINX_ML403=y -CONFIG_IBM405_ERR77=y -CONFIG_IBM405_ERR51=y -CONFIG_XILINX_VIRTEX=y -CONFIG_EMBEDDEDBOOT=y -# CONFIG_PPC4xx_DMA is not set -CONFIG_PPC_GEN550=y -CONFIG_UART0_TTYS0=y -# CONFIG_UART0_TTYS1 is not set -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_PC_KEYBOARD is not set -# CONFIG_HIGHMEM is not set -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyS0,9600" -# CONFIG_PM is not set -# CONFIG_HIBERNATION is not set -CONFIG_SECCOMP=y -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -# CONFIG_PPC_I8259 is not set -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_CONSISTENT_START=0xff100000 -CONFIG_CONSISTENT_SIZE=0x00200000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_IEEE80211 is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -# CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Macintosh device drivers -# -# CONFIG_WINDFARM is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -CONFIG_TUN=y - -# -# PHY device support -# - -# -# Ethernet (10 or 100Mbit) -# -# CONFIG_NET_ETHERNET is not set -# CONFIG_IBM_EMAC is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia Capabilities Port drivers -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Console display driver support -# -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# - -# -# SN Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_RELAYFS_FS is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -# CONFIG_NFS_FS is not set -# CONFIG_NFSD is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y - -# -# IBM 40x options -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_VM is not set -CONFIG_FORCED_INLINING=y -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_KGDB is not set -# CONFIG_XMON is not set -# CONFIG_BDI_SWITCH is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# diff --git a/arch/ppc/configs/mvme5100_defconfig b/arch/ppc/configs/mvme5100_defconfig deleted file mode 100644 index 46776b9c1a33..000000000000 --- a/arch/ppc/configs/mvme5100_defconfig +++ /dev/null @@ -1,746 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.9-rc2 -# Wed Sep 22 09:53:26 2004 -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y -CONFIG_GENERIC_IOMAP=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SHMEM=y -# CONFIG_TINY_SHMEM is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_E500 is not set -CONFIG_ALTIVEC=y -# CONFIG_TAU is not set -# CONFIG_CPU_FREQ is not set -CONFIG_PPC_STD_MMU=y - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_WILLOW is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_EV64260 is not set -# CONFIG_SPRUCE is not set -# CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set -CONFIG_MVME5100=y -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBC82xx is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX8260 is not set -# CONFIG_TQM8260 is not set -# CONFIG_ADS8272 is not set -# CONFIG_LITE5200 is not set -# CONFIG_MVME5100_IPMC761_PRESENT is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_IDE_TASK_IOCTL is not set -# CONFIG_IDE_TASKFILE_IO is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_IDE_ARM is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=y -# CONFIG_SCSI_FC_ATTRS is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INIA100 is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=8 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=32 -# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=y -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_QLA6322 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -# CONFIG_IP_NF_CT_ACCT is not set -# CONFIG_IP_NF_CT_PROTO_SCTP is not set -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -# CONFIG_IP_NF_QUEUE is not set -CONFIG_IP_NF_IPTABLES=m -# CONFIG_IP_NF_MATCH_LIMIT is not set -# CONFIG_IP_NF_MATCH_IPRANGE is not set -# CONFIG_IP_NF_MATCH_MAC is not set -# CONFIG_IP_NF_MATCH_PKTTYPE is not set -# CONFIG_IP_NF_MATCH_MARK is not set -# CONFIG_IP_NF_MATCH_MULTIPORT is not set -# CONFIG_IP_NF_MATCH_TOS is not set -# CONFIG_IP_NF_MATCH_RECENT is not set -# CONFIG_IP_NF_MATCH_ECN is not set -# CONFIG_IP_NF_MATCH_DSCP is not set -# CONFIG_IP_NF_MATCH_AH_ESP is not set -# CONFIG_IP_NF_MATCH_LENGTH is not set -# CONFIG_IP_NF_MATCH_TTL is not set -# CONFIG_IP_NF_MATCH_TCPMSS is not set -CONFIG_IP_NF_MATCH_HELPER=m -# CONFIG_IP_NF_MATCH_STATE is not set -# CONFIG_IP_NF_MATCH_CONNTRACK is not set -# CONFIG_IP_NF_MATCH_OWNER is not set -# CONFIG_IP_NF_MATCH_ADDRTYPE is not set -# CONFIG_IP_NF_MATCH_REALM is not set -# CONFIG_IP_NF_MATCH_SCTP is not set -# CONFIG_IP_NF_FILTER is not set -# CONFIG_IP_NF_TARGET_LOG is not set -# CONFIG_IP_NF_TARGET_ULOG is not set -# CONFIG_IP_NF_TARGET_TCPMSS is not set -# CONFIG_IP_NF_NAT is not set -# CONFIG_IP_NF_MANGLE is not set -# CONFIG_IP_NF_RAW is not set -# CONFIG_IP_NF_ARPTABLES is not set -# CONFIG_IP_NF_COMPAT_IPCHAINS is not set -# CONFIG_IP_NF_COMPAT_IPFWADM is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=y - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -CONFIG_NET_TULIP=y -# CONFIG_DE2104X is not set -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -# CONFIG_TULIP_MMIO is not set -# CONFIG_TULIP_NAPI is not set -# CONFIG_DE4X5 is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -CONFIG_E100=y -# CONFIG_E100_NAPI is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_VELOCITY is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Userland interfaces -# - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/ocotea_defconfig b/arch/ppc/configs/ocotea_defconfig deleted file mode 100644 index 9dcf575c706f..000000000000 --- a/arch/ppc/configs/ocotea_defconfig +++ /dev/null @@ -1,599 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -# CONFIG_STANDALONE is not set -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -# CONFIG_6xx is not set -# CONFIG_40x is not set -CONFIG_44x=y -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_E500 is not set -CONFIG_BOOKE=y -CONFIG_PTE_64BIT=y -# CONFIG_MATH_EMULATION is not set -# CONFIG_CPU_FREQ is not set -CONFIG_4xx=y - -# -# IBM 4xx options -# -# CONFIG_EBONY is not set -CONFIG_OCOTEA=y -CONFIG_440GX=y -CONFIG_440A=y -CONFIG_IBM_OCP=y -CONFIG_IBM_EMAC4=y -# CONFIG_PM is not set -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_PC_KEYBOARD is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on console=ttyS0,115200" - -# -# Bus options -# -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_CONSISTENT_START=0xff100000 -CONFIG_CONSISTENT_SIZE=0x00200000 -CONFIG_BOOT_LOAD=0x01000000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_DEBUG_DRIVER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set -# CONFIG_IP_NF_COMPAT_IPCHAINS is not set -# CONFIG_IP_NF_COMPAT_IPFWADM is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_OAKNET is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_IBM_EMAC=y -# CONFIG_IBM_EMAC_ERRMSG is not set -CONFIG_IBM_EMAC_RXB=128 -CONFIG_IBM_EMAC_TXB=128 -CONFIG_IBM_EMAC_FGAP=8 -CONFIG_IBM_EMAC_SKBRES=0 -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -# CONFIG_SERIAL_8250_MANY_PORTS is not set -CONFIG_SERIAL_8250_SHARE_IRQ=y -# CONFIG_SERIAL_8250_DETECT_IRQ is not set -# CONFIG_SERIAL_8250_MULTIPORT is not set -# CONFIG_SERIAL_8250_RSA is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_KGDB is not set -# CONFIG_XMON is not set -CONFIG_BDI_SWITCH=y -CONFIG_DEBUG_INFO=y -# CONFIG_SERIAL_TEXT_DEBUG is not set -CONFIG_PPC_OCP=y - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/pplus_defconfig b/arch/ppc/configs/pplus_defconfig deleted file mode 100644 index 5e459bcbf591..000000000000 --- a/arch/ppc/configs/pplus_defconfig +++ /dev/null @@ -1,720 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_STANDALONE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_ALTIVEC is not set -# CONFIG_TAU is not set -# CONFIG_CPU_FREQ is not set -CONFIG_PPC_STD_MMU=y - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_WILLOW is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_EV64260 is not set -# CONFIG_SPRUCE is not set -# CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set -# CONFIG_MVME5100 is not set -CONFIG_PPLUS=y -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX6 is not set -# CONFIG_TQM8260 is not set -CONFIG_PPC_GEN550=y -# CONFIG_PPCBUG_NVRAM is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -CONFIG_BLK_DEV_FD=y -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_IDEDISK_STROKE is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=y -CONFIG_BLK_DEV_IDESCSI=y -# CONFIG_IDE_TASK_IOCTL is not set -# CONFIG_IDE_TASKFILE_IO is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_REPORT_LUNS is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=y -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_QLA6322 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_INET_ECN is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -CONFIG_IP_NF_FTP=m -# CONFIG_IP_NF_IRC is not set -# CONFIG_IP_NF_TFTP is not set -# CONFIG_IP_NF_AMANDA is not set -# CONFIG_IP_NF_QUEUE is not set -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m -# CONFIG_IP_NF_MATCH_IPRANGE is not set -CONFIG_IP_NF_MATCH_MAC=m -CONFIG_IP_NF_MATCH_PKTTYPE=m -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m -CONFIG_IP_NF_MATCH_TOS=m -# CONFIG_IP_NF_MATCH_RECENT is not set -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_DSCP=m -CONFIG_IP_NF_MATCH_AH_ESP=m -# CONFIG_IP_NF_MATCH_LENGTH is not set -# CONFIG_IP_NF_MATCH_TTL is not set -# CONFIG_IP_NF_MATCH_TCPMSS is not set -CONFIG_IP_NF_MATCH_HELPER=m -CONFIG_IP_NF_MATCH_STATE=m -CONFIG_IP_NF_MATCH_CONNTRACK=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_NF_TARGET_SAME is not set -# CONFIG_IP_NF_NAT_SNMP_BASIC is not set -CONFIG_IP_NF_NAT_FTP=m -# CONFIG_IP_NF_MANGLE is not set -# CONFIG_IP_NF_TARGET_LOG is not set -CONFIG_IP_NF_TARGET_ULOG=m -# CONFIG_IP_NF_TARGET_TCPMSS is not set -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -# CONFIG_IP_NF_ARP_MANGLE is not set -CONFIG_IP_NF_COMPAT_IPCHAINS=m -# CONFIG_IP_NF_COMPAT_IPFWADM is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -CONFIG_IPV6_SCTP__=y -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_CRC32=y -# CONFIG_OAKNET is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -CONFIG_NET_TULIP=y -# CONFIG_DE2104X is not set -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -# CONFIG_TULIP_MMIO is not set -# CONFIG_TULIP_NAPI is not set -# CONFIG_DE4X5 is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -CONFIG_EEPRO100=y -# CONFIG_EEPRO100_PIO is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# IrDA (infrared) support -# -# CONFIG_IRDA is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Userland interfaces -# - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_ZISOFS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_SUNRPC_GSS is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/prep_defconfig b/arch/ppc/configs/prep_defconfig deleted file mode 100644 index b7cee2d71405..000000000000 --- a/arch/ppc/configs/prep_defconfig +++ /dev/null @@ -1,1679 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc6 -# Wed Sep 6 15:09:32 2006 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="-prep" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -# CONFIG_RELAY is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_EMBEDDED is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Block layer -# -CONFIG_LBD=y -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_8xx is not set -# CONFIG_E200 is not set -# CONFIG_E500 is not set -CONFIG_PPC_FPU=y -# CONFIG_ALTIVEC is not set -# CONFIG_TAU is not set -# CONFIG_KEXEC is not set -# CONFIG_CPU_FREQ is not set -CONFIG_PPC601_SYNC_FIX=y -# CONFIG_WANT_EARLY_SERIAL is not set -CONFIG_PPC_STD_MMU=y - -# -# Platform options -# -CONFIG_PPC_PREP=y -# CONFIG_APUS is not set -# CONFIG_KATANA is not set -# CONFIG_WILLOW is not set -# CONFIG_CPCI690 is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_CHESTNUT is not set -# CONFIG_SPRUCE is not set -# CONFIG_HDPU is not set -# CONFIG_EV64260 is not set -# CONFIG_LOPEC is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_RADSTONE_PPC7D is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBC82xx is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX8260 is not set -# CONFIG_TQM8260 is not set -# CONFIG_ADS8272 is not set -# CONFIG_PQ2FADS is not set -# CONFIG_LITE5200 is not set -# CONFIG_MPC834x_SYS is not set -# CONFIG_EV64360 is not set -CONFIG_PPCBUG_NVRAM=y -# CONFIG_SMP is not set -# CONFIG_HIGHMEM is not set -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=m -CONFIG_PREP_RESIDUAL=y -CONFIG_PROC_PREPRESIDUAL=y -# CONFIG_CMDLINE_BOOL is not set -CONFIG_PM=y -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_DEBUG is not set -CONFIG_HIBERNATION=y -CONFIG_PM_STD_PARTITION="" -# CONFIG_SECCOMP is not set -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -CONFIG_ISA=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PPC_I8259=y -CONFIG_PPC_INDIRECT_PCI=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_DEBUG is not set - -# -# PCCARD (PCMCIA/CardBus) support -# -CONFIG_PCCARD=m -# CONFIG_PCMCIA_DEBUG is not set -# CONFIG_PCMCIA is not set -CONFIG_CARDBUS=y - -# -# PC-card bridges -# -CONFIG_YENTA=m -CONFIG_YENTA_O2=y -CONFIG_YENTA_RICOH=y -CONFIG_YENTA_TI=y -CONFIG_YENTA_ENE_TUNE=y -CONFIG_YENTA_TOSHIBA=y -CONFIG_PCMCIA_PROBE=y -CONFIG_PCCARD_NONSTATIC=m - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m - -# -# IP: Netfilter Configuration -# -CONFIG_IP_NF_CONNTRACK=m -# CONFIG_IP_NF_CT_ACCT is not set -CONFIG_IP_NF_CONNTRACK_MARK=y -# CONFIG_IP_NF_CONNTRACK_EVENTS is not set -# CONFIG_IP_NF_CONNTRACK_NETLINK is not set -# CONFIG_IP_NF_CT_PROTO_SCTP is not set -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -# CONFIG_IP_NF_NETBIOS_NS is not set -CONFIG_IP_NF_TFTP=m -CONFIG_IP_NF_AMANDA=m -# CONFIG_IP_NF_PPTP is not set -# CONFIG_IP_NF_H323 is not set -# CONFIG_IP_NF_SIP is not set -CONFIG_IP_NF_QUEUE=m -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_IEEE80211 is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -# CONFIG_STANDALONE is not set -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -# CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -CONFIG_PARPORT=m -CONFIG_PARPORT_PC=m -CONFIG_PARPORT_SERIAL=m -CONFIG_PARPORT_PC_FIFO=y -CONFIG_PARPORT_PC_SUPERIO=y -# CONFIG_PARPORT_GSC is not set -# CONFIG_PARPORT_AX88796 is not set -CONFIG_PARPORT_1284=y - -# -# Plug and Play support -# -# CONFIG_PNP is not set - -# -# Block devices -# -CONFIG_BLK_DEV_FD=m -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -CONFIG_BLK_DEV_IDESCSI=y -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -CONFIG_BLK_DEV_IDEPCI=y -CONFIG_IDEPCI_SHARE_IRQ=y -# CONFIG_BLK_DEV_OFFBOARD is not set -CONFIG_BLK_DEV_GENERIC=y -# CONFIG_BLK_DEV_OPTI621 is not set -CONFIG_BLK_DEV_SL82C105=y -CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -CONFIG_IDEDMA_PCI_AUTO=y -# CONFIG_IDEDMA_ONLYDISK is not set -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_SC1200 is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT821X is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_IDE_ARM is not set -# CONFIG_IDE_CHIPSETS is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -CONFIG_IDEDMA_AUTO=y -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=y -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set - -# -# SCSI low-level drivers -# -# CONFIG_ISCSI_TCP is not set -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_PPA is not set -# CONFIG_SCSI_IMM is not set -# CONFIG_SCSI_NCR53C406A is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -CONFIG_SCSI_SYM53C8XX_MMIO=y -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Old CD-ROM drivers (not SCSI, not IDE) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set - -# -# IEEE 1394 (FireWire) support -# -CONFIG_IEEE1394=m - -# -# Subsystem Options -# -# CONFIG_IEEE1394_VERBOSEDEBUG is not set -CONFIG_IEEE1394_OUI_DB=y -CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y -CONFIG_IEEE1394_CONFIG_ROM_IP1394=y -# CONFIG_IEEE1394_EXPORT_FULL_API is not set - -# -# Device Drivers -# -# CONFIG_IEEE1394_PCILYNX is not set -CONFIG_IEEE1394_OHCI1394=m - -# -# Protocol Drivers -# -CONFIG_IEEE1394_VIDEO1394=m -CONFIG_IEEE1394_SBP2=m -CONFIG_IEEE1394_ETH1394=m -CONFIG_IEEE1394_DV1394=m -CONFIG_IEEE1394_RAWIO=m - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# -# CONFIG_WINDFARM is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -CONFIG_TUN=m - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -# CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set - -# -# Tulip family network device support -# -CONFIG_NET_TULIP=y -CONFIG_DE2104X=y -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -CONFIG_TULIP_MMIO=y -# CONFIG_TULIP_NAPI is not set -CONFIG_DE4X5=m -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_ULI526X is not set -# CONFIG_PCMCIA_XIRCOM is not set -# CONFIG_PCMCIA_XIRTULIP is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_AC3200 is not set -# CONFIG_APRICOT is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_CS89x0 is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -CONFIG_NET_RADIO=y -# CONFIG_NET_WIRELESS_RTNETLINK is not set - -# -# Obsolete Wireless cards support (pre-802.11) -# -# CONFIG_STRIP is not set -# CONFIG_ARLAN is not set -# CONFIG_WAVELAN is not set - -# -# Wireless 802.11b ISA/PCI cards support -# -# CONFIG_IPW2100 is not set -# CONFIG_IPW2200 is not set -# CONFIG_AIRO is not set -CONFIG_HERMES=m -# CONFIG_PLX_HERMES is not set -# CONFIG_TMD_HERMES is not set -# CONFIG_NORTEL_HERMES is not set -# CONFIG_PCI_HERMES is not set -# CONFIG_ATMEL is not set - -# -# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support -# -# CONFIG_PRISM54 is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_HOSTAP is not set -CONFIG_NET_WIRELESS=y - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -CONFIG_PPP=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=m -# CONFIG_PPP_MPPE is not set -CONFIG_PPPOE=m -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -CONFIG_NETCONSOLE=m -CONFIG_NETPOLL=y -# CONFIG_NETPOLL_RX is not set -# CONFIG_NETPOLL_TRAP is not set -CONFIG_NET_POLL_CONTROLLER=y - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_INPORT is not set -# CONFIG_MOUSE_LOGIBM is not set -# CONFIG_MOUSE_PC110PAD is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -CONFIG_INPUT_MISC=y -CONFIG_INPUT_PCSPKR=m -CONFIG_INPUT_UINPUT=m - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_PARKBD is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_PRINTER is not set -# CONFIG_PPDEV is not set -# CONFIG_TIPAR is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -CONFIG_NVRAM=y -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=m - -# -# I2C Algorithms -# -CONFIG_I2C_ALGOBIT=y -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# -# I2C Hardware Bus support -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_ELEKTOR is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_MPC is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_VOODOO3 is not set -# CONFIG_I2C_PCA_ISA is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_M41T00 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set -# CONFIG_USB_DABUSB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_CT65550 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -CONFIG_FB_MATROX=y -CONFIG_FB_MATROX_MILLENIUM=y -CONFIG_FB_MATROX_MYSTIQUE=y -CONFIG_FB_MATROX_G=y -CONFIG_FB_MATROX_I2C=y -CONFIG_FB_MATROX_MAVEN=m -# CONFIG_FB_MATROX_MULTIHEAD is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_VIRTUAL is not set - -# -# Console display driver support -# -CONFIG_VGA_CONSOLE=y -# CONFIG_VGACON_SOFT_SCROLLBACK is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y - -# -# Logo configuration -# -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -CONFIG_SOUND=m - -# -# Advanced Linux Sound Architecture -# -CONFIG_SND=m -CONFIG_SND_TIMER=m -CONFIG_SND_PCM=m -CONFIG_SND_HWDEP=m -CONFIG_SND_RAWMIDI=m -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set - -# -# Generic devices -# -CONFIG_SND_MPU401_UART=m -CONFIG_SND_OPL3_LIB=m -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set - -# -# ISA devices -# -CONFIG_SND_CS4231_LIB=m -# CONFIG_SND_ADLIB is not set -# CONFIG_SND_AD1848 is not set -# CONFIG_SND_CMI8330 is not set -# CONFIG_SND_CS4231 is not set -CONFIG_SND_CS4232=m -# CONFIG_SND_CS4236 is not set -# CONFIG_SND_ES1688 is not set -# CONFIG_SND_ES18XX is not set -# CONFIG_SND_GUSCLASSIC is not set -# CONFIG_SND_GUSEXTREME is not set -# CONFIG_SND_GUSMAX is not set -# CONFIG_SND_OPL3SA2 is not set -# CONFIG_SND_OPTI92X_AD1848 is not set -# CONFIG_SND_OPTI92X_CS4231 is not set -# CONFIG_SND_OPTI93X is not set -# CONFIG_SND_MIRO is not set -# CONFIG_SND_SB8 is not set -# CONFIG_SND_SB16 is not set -# CONFIG_SND_SBAWE is not set -# CONFIG_SND_SGALAXY is not set -# CONFIG_SND_SSCAPE is not set -# CONFIG_SND_WAVEFRONT is not set - -# -# PCI devices -# -# CONFIG_SND_AD1889 is not set -# CONFIG_SND_ALS300 is not set -# CONFIG_SND_ALS4000 is not set -# CONFIG_SND_ALI5451 is not set -# CONFIG_SND_ATIIXP is not set -# CONFIG_SND_ATIIXP_MODEM is not set -# CONFIG_SND_AU8810 is not set -# CONFIG_SND_AU8820 is not set -# CONFIG_SND_AU8830 is not set -# CONFIG_SND_AZT3328 is not set -# CONFIG_SND_BT87X is not set -# CONFIG_SND_CA0106 is not set -# CONFIG_SND_CMIPCI is not set -# CONFIG_SND_CS4281 is not set -# CONFIG_SND_CS46XX is not set -# CONFIG_SND_DARLA20 is not set -# CONFIG_SND_GINA20 is not set -# CONFIG_SND_LAYLA20 is not set -# CONFIG_SND_DARLA24 is not set -# CONFIG_SND_GINA24 is not set -# CONFIG_SND_LAYLA24 is not set -# CONFIG_SND_MONA is not set -# CONFIG_SND_MIA is not set -# CONFIG_SND_ECHO3G is not set -# CONFIG_SND_INDIGO is not set -# CONFIG_SND_INDIGOIO is not set -# CONFIG_SND_INDIGODJ is not set -# CONFIG_SND_EMU10K1 is not set -# CONFIG_SND_EMU10K1X is not set -# CONFIG_SND_ENS1370 is not set -# CONFIG_SND_ENS1371 is not set -# CONFIG_SND_ES1938 is not set -# CONFIG_SND_ES1968 is not set -# CONFIG_SND_FM801 is not set -# CONFIG_SND_HDA_INTEL is not set -# CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set -# CONFIG_SND_ICE1712 is not set -# CONFIG_SND_ICE1724 is not set -# CONFIG_SND_INTEL8X0 is not set -# CONFIG_SND_INTEL8X0M is not set -# CONFIG_SND_KORG1212 is not set -# CONFIG_SND_MAESTRO3 is not set -# CONFIG_SND_MIXART is not set -# CONFIG_SND_NM256 is not set -# CONFIG_SND_PCXHR is not set -# CONFIG_SND_RIPTIDE is not set -# CONFIG_SND_RME32 is not set -# CONFIG_SND_RME96 is not set -# CONFIG_SND_RME9652 is not set -# CONFIG_SND_SONICVIBES is not set -# CONFIG_SND_TRIDENT is not set -# CONFIG_SND_VIA82XX is not set -# CONFIG_SND_VIA82XX_MODEM is not set -# CONFIG_SND_VX222 is not set -# CONFIG_SND_YMFPCI is not set - -# -# ALSA PowerMac devices -# - -# -# Apple Onboard Audio driver -# -# CONFIG_SND_AOA is not set -# CONFIG_SND_AOA_SOUNDBUS is not set - -# -# USB devices -# -CONFIG_SND_USB_AUDIO=m -# CONFIG_SND_USB_USX2Y is not set - -# -# Open Sound System -# -# CONFIG_SOUND_PRIME is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_BANDWIDTH is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_OTG is not set - -# -# USB Host Controller Drivers -# -CONFIG_USB_EHCI_HCD=m -CONFIG_USB_EHCI_SPLIT_ISO=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -# CONFIG_USB_ISP116X_HCD is not set -CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_BIG_ENDIAN is not set -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_UHCI_HCD=m -# CONFIG_USB_SL811_HCD is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# may also be needed; see USB_STORAGE Help for more information -# -CONFIG_USB_STORAGE=m -# CONFIG_USB_STORAGE_DEBUG is not set -CONFIG_USB_STORAGE_DATAFAB=y -CONFIG_USB_STORAGE_FREECOM=y -CONFIG_USB_STORAGE_ISD200=y -CONFIG_USB_STORAGE_DPCM=y -CONFIG_USB_STORAGE_USBAT=y -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_JUMPSHOT=y -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -CONFIG_USB_HIDINPUT=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set -CONFIG_USB_HIDDEV=y -# CONFIG_USB_AIPTEK is not set -# CONFIG_USB_WACOM is not set -# CONFIG_USB_ACECAD is not set -# CONFIG_USB_KBTAB is not set -# CONFIG_USB_POWERMATE is not set -# CONFIG_USB_TOUCHSCREEN is not set -# CONFIG_USB_YEALINK is not set -# CONFIG_USB_XPAD is not set -# CONFIG_USB_ATI_REMOTE is not set -# CONFIG_USB_ATI_REMOTE2 is not set -# CONFIG_USB_KEYSPAN_REMOTE is not set -# CONFIG_USB_APPLETOUCH is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -CONFIG_USB_PEGASUS=m -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_USB_MON is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -CONFIG_USB_SERIAL=m -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_AIRPRIME is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP2101 is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_FUNSOFT is not set -CONFIG_USB_SERIAL_VISOR=m -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OMNINET is not set -CONFIG_USB_EZUSB=y - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGETKIT is not set -# CONFIG_USB_PHIDGETSERVO is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TEST is not set - -# -# USB DSL modem support -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=y -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -CONFIG_XFS_SECURITY=y -CONFIG_XFS_POSIX_ACL=y -# CONFIG_XFS_RT is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=m -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_ZISOFS is not set -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_CRAMFS=m -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -# CONFIG_NFSD_V4 is not set -CONFIG_NFSD_TCP=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -CONFIG_MAC_PARTITION=y -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# -CONFIG_NLS=m -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m - -# -# Library routines -# -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_MAGIC_SYSRQ=y -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_RWSEMS is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_VM is not set -CONFIG_FORCED_INLINING=y -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_XMON is not set -# CONFIG_BDI_SWITCH is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# diff --git a/arch/ppc/configs/prpmc750_defconfig b/arch/ppc/configs/prpmc750_defconfig deleted file mode 100644 index 82d52f66b742..000000000000 --- a/arch/ppc/configs/prpmc750_defconfig +++ /dev/null @@ -1,594 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_STANDALONE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_FUTEX=y -# CONFIG_EPOLL is not set -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_ALTIVEC is not set -# CONFIG_TAU is not set -# CONFIG_CPU_FREQ is not set -CONFIG_PPC_STD_MMU=y - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_WILLOW is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_EV64260 is not set -# CONFIG_SPRUCE is not set -# CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -CONFIG_PRPMC750=y -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX6 is not set -# CONFIG_TQM8260 is not set -CONFIG_PPC_GEN550=y -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_CARMEL is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -CONFIG_NET_TULIP=y -# CONFIG_DE2104X is not set -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -CONFIG_TULIP_MMIO=y -# CONFIG_TULIP_NAPI is not set -# CONFIG_DE4X5 is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -CONFIG_EEPRO100=y -# CONFIG_EEPRO100_PIO is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -CONFIG_CRC32=y - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/prpmc800_defconfig b/arch/ppc/configs/prpmc800_defconfig deleted file mode 100644 index 613c2664d3e8..000000000000 --- a/arch/ppc/configs/prpmc800_defconfig +++ /dev/null @@ -1,656 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_STANDALONE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_FUTEX=y -# CONFIG_EPOLL is not set -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -CONFIG_ALTIVEC=y -# CONFIG_TAU is not set -# CONFIG_CPU_FREQ is not set -CONFIG_PPC_STD_MMU=y - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_WILLOW is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_EV64260 is not set -# CONFIG_SPRUCE is not set -# CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -CONFIG_PRPMC800=y -# CONFIG_SANDPOINT is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX6 is not set -# CONFIG_TQM8260 is not set -CONFIG_PPC_GEN550=y -# CONFIG_NONMONARCH_SUPPORT is not set -CONFIG_HARRIER=y -# CONFIG_HARRIER_STORE_GATHERING is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_CARMEL is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_REPORT_LUNS is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=y -# CONFIG_SCSI_FC_ATTRS is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INIA100 is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=y -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_QLA6322 is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -CONFIG_EEPRO100=y -# CONFIG_EEPRO100_PIO is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -# CONFIG_CRC32 is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/radstone_ppc7d_defconfig b/arch/ppc/configs/radstone_ppc7d_defconfig deleted file mode 100644 index 9f64532f2a81..000000000000 --- a/arch/ppc/configs/radstone_ppc7d_defconfig +++ /dev/null @@ -1,991 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc3 -# Tue Jul 26 00:02:09 2005 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_E200 is not set -# CONFIG_E500 is not set -CONFIG_PPC_FPU=y -CONFIG_ALTIVEC=y -# CONFIG_TAU is not set -# CONFIG_KEXEC is not set -# CONFIG_CPU_FREQ is not set -CONFIG_PPC_GEN550=y -# CONFIG_PM is not set -CONFIG_PPC_STD_MMU=y -# CONFIG_NOT_COHERENT_CACHE is not set - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_KATANA is not set -# CONFIG_WILLOW is not set -# CONFIG_CPCI690 is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_CHESTNUT is not set -# CONFIG_SPRUCE is not set -# CONFIG_HDPU is not set -# CONFIG_EV64260 is not set -# CONFIG_LOPEC is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -CONFIG_RADSTONE_PPC7D=y -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBC82xx is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX8260 is not set -# CONFIG_TQM8260 is not set -# CONFIG_ADS8272 is not set -# CONFIG_PQ2FADS is not set -# CONFIG_LITE5200 is not set -# CONFIG_MPC834x_SYS is not set -CONFIG_MV64360=y -CONFIG_MV64X60=y - -# -# Set bridge options -# -CONFIG_MV64X60_BASE=0xfef00000 -CONFIG_MV64X60_NEW_BASE=0xfef00000 -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=y -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyS0,9600" -CONFIG_SECCOMP=y -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LEGACY_PROC=y -CONFIG_PCI_NAMES=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# Advanced setup -# -CONFIG_ADVANCED_OPTIONS=y -CONFIG_HIGHMEM_START=0xfe000000 -# CONFIG_LOWMEM_SIZE_BOOL is not set -CONFIG_LOWMEM_SIZE=0x30000000 -# CONFIG_KERNEL_START_BOOL is not set -CONFIG_KERNEL_START=0xc0000000 -# CONFIG_TASK_SIZE_BOOL is not set -CONFIG_TASK_SIZE=0x80000000 -# CONFIG_BOOT_LOAD_BOOL is not set -CONFIG_BOOT_LOAD=0x00800000 - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -CONFIG_BRIDGE=y -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_PARTITIONS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_FTL=y -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_GEOMETRY is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y - -# -# SCSI Transport Attributes -# -CONFIG_SCSI_SPI_ATTRS=y -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -CONFIG_SCSI_QLA2XXX=y -# CONFIG_SCSI_QLA21XX is not set -# CONFIG_SCSI_QLA22XX is not set -# CONFIG_SCSI_QLA2300 is not set -# CONFIG_SCSI_QLA2322 is not set -# CONFIG_SCSI_QLA6312 is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -CONFIG_NET_TULIP=y -# CONFIG_DE2104X is not set -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -# CONFIG_TULIP_MMIO is not set -# CONFIG_TULIP_NAPI is not set -# CONFIG_DE4X5 is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -CONFIG_E100=y -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -CONFIG_R8169=y -CONFIG_R8169_NAPI=y -# CONFIG_SKGE is not set -CONFIG_SK98LIN=y -# CONFIG_VIA_VELOCITY is not set -CONFIG_TIGON3=y -# CONFIG_BNX2 is not set -CONFIG_MV643XX_ETH=y -CONFIG_MV643XX_ETH_0=y -CONFIG_MV643XX_ETH_1=y -# CONFIG_MV643XX_ETH_2 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_XTKBD=y -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -# CONFIG_VT_CONSOLE is not set -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_MPSC=y -# CONFIG_SERIAL_MPSC_CONSOLE is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y - -# -# I2C Algorithms -# -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# -# I2C Hardware Bus support -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_MPC is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_SCx200_ACB is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_VOODOO3 is not set -# CONFIG_I2C_PCA_ISA is not set -CONFIG_I2C_MV64XXX=y -CONFIG_I2C_SENSOR=y - -# -# Miscellaneous I2C Chip support -# -CONFIG_SENSORS_DS1337=y -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_RTC8564 is not set -# CONFIG_SENSORS_M41T00 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -CONFIG_HWMON=y -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -CONFIG_SENSORS_LM90=y -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# SN Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_ZISOFS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -CONFIG_CRC_CCITT=y -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# diff --git a/arch/ppc/configs/redwood5_defconfig b/arch/ppc/configs/redwood5_defconfig deleted file mode 100644 index 4c5486da4139..000000000000 --- a/arch/ppc/configs/redwood5_defconfig +++ /dev/null @@ -1,557 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -# CONFIG_STANDALONE is not set -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_FUTEX=y -# CONFIG_EPOLL is not set -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -# CONFIG_6xx is not set -CONFIG_40x=y -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_MATH_EMULATION is not set -# CONFIG_CPU_FREQ is not set -CONFIG_4xx=y - -# -# IBM 4xx options -# -# CONFIG_ASH is not set -# CONFIG_CPCI405 is not set -# CONFIG_EP405 is not set -# CONFIG_OAK is not set -CONFIG_REDWOOD_5=y -# CONFIG_REDWOOD_6 is not set -# CONFIG_SYCAMORE is not set -# CONFIG_WALNUT is not set -CONFIG_IBM405_ERR77=y -CONFIG_IBM405_ERR51=y -CONFIG_IBM_OCP=y -CONFIG_PPC_OCP=y -CONFIG_STB03xxx=y -CONFIG_IBM_OPENBIOS=y -# CONFIG_PM is not set -CONFIG_UART0_TTYS0=y -# CONFIG_UART0_TTYS1 is not set -# CONFIG_SERIAL_SICC is not set -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_PC_KEYBOARD is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_IDEDISK_STROKE is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_IDE_TASK_IOCTL is not set -# CONFIG_IDE_TASKFILE_IO is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IBM_EMAC is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# IrDA (infrared) support -# -# CONFIG_IRDA is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_CT82C710 is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_UNIX98_PTYS is not set -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -# CONFIG_DEVFS_FS is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# IBM 40x options -# - -# -# Library routines -# -# CONFIG_CRC32 is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set -CONFIG_OCP=y - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/redwood6_defconfig b/arch/ppc/configs/redwood6_defconfig deleted file mode 100644 index 5752845c2601..000000000000 --- a/arch/ppc/configs/redwood6_defconfig +++ /dev/null @@ -1,535 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -# CONFIG_STANDALONE is not set -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_FUTEX=y -# CONFIG_EPOLL is not set -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -# CONFIG_MODULE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -# CONFIG_6xx is not set -CONFIG_40x=y -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_MATH_EMULATION is not set -# CONFIG_CPU_FREQ is not set -CONFIG_4xx=y - -# -# IBM 4xx options -# -# CONFIG_ASH is not set -# CONFIG_CPCI405 is not set -# CONFIG_EP405 is not set -# CONFIG_OAK is not set -# CONFIG_REDWOOD_5 is not set -CONFIG_REDWOOD_6=y -# CONFIG_SYCAMORE is not set -# CONFIG_WALNUT is not set -CONFIG_IBM405_ERR77=y -CONFIG_IBM405_ERR51=y -CONFIG_IBM_OCP=y -CONFIG_PPC_OCP=y -CONFIG_STB03xxx=y -CONFIG_IBM_OPENBIOS=y -# CONFIG_PM is not set -CONFIG_UART0_TTYS0=y -# CONFIG_UART0_TTYS1 is not set -# CONFIG_SERIAL_SICC is not set -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_PC_KEYBOARD is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IBM_EMAC is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# IrDA (infrared) support -# -# CONFIG_IRDA is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_CT82C710 is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# IBM 40x options -# - -# -# Library routines -# -# CONFIG_CRC32 is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set -CONFIG_OCP=y - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/rpx8260_defconfig b/arch/ppc/configs/rpx8260_defconfig deleted file mode 100644 index a9c4544ae560..000000000000 --- a/arch/ppc/configs/rpx8260_defconfig +++ /dev/null @@ -1,555 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_STANDALONE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_FUTEX=y -# CONFIG_EPOLL is not set -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_E500 is not set -# CONFIG_CPU_FREQ is not set -CONFIG_EMBEDDEDBOOT=y -CONFIG_PPC_STD_MMU=y - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_WILLOW is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_EV64260 is not set -# CONFIG_SPRUCE is not set -# CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBC82xx is not set -# CONFIG_SBS8260 is not set -CONFIG_RPX8260=y -# CONFIG_TQM8260 is not set -# CONFIG_ADS8272 is not set -CONFIG_8260=y -CONFIG_CPM2=y -# CONFIG_PC_KEYBOARD is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_CMDLINE_BOOL is not set - -# -# Bus options -# -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_PREVENT_FIRMWARE_BUILD=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_OAKNET is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Userland interfaces -# - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_CPM=y -CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -# CONFIG_SERIAL_CPM_SMC2 is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MSDOS_PARTITION is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# -# CONFIG_NLS is not set -# CONFIG_SCC_ENET is not set -CONFIG_FEC_ENET=y -# CONFIG_USE_MDIO is not set - -# -# CPM2 Options -# -# CONFIG_FCC1_ENET is not set -# CONFIG_FCC2_ENET is not set -CONFIG_FCC3_ENET=y - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_KGDB_CONSOLE is not set - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/rpxcllf_defconfig b/arch/ppc/configs/rpxcllf_defconfig deleted file mode 100644 index cf932f13fa86..000000000000 --- a/arch/ppc/configs/rpxcllf_defconfig +++ /dev/null @@ -1,582 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.10-rc1 -# Mon Nov 1 16:41:04 2004 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -# CONFIG_CLEAN_COMPILE is not set -CONFIG_BROKEN=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_KOBJECT_UEVENT is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -# CONFIG_FUTEX is not set -# CONFIG_EPOLL is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -# CONFIG_SHMEM is not set -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -CONFIG_TINY_SHMEM=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Processor -# -# CONFIG_6xx is not set -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -CONFIG_8xx=y -# CONFIG_E500 is not set -CONFIG_MATH_EMULATION=y -# CONFIG_CPU_FREQ is not set -CONFIG_EMBEDDEDBOOT=y -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_RPXLITE is not set -CONFIG_RPXCLASSIC=y -# CONFIG_BSEIP is not set -# CONFIG_FADS is not set -# CONFIG_TQM823L is not set -# CONFIG_TQM850L is not set -# CONFIG_TQM855L is not set -# CONFIG_TQM860L is not set -# CONFIG_FPS850L is not set -# CONFIG_SPD823TS is not set -# CONFIG_IVMS8 is not set -# CONFIG_IVML24 is not set -# CONFIG_SM850 is not set -# CONFIG_HERMES_PRO is not set -# CONFIG_IP860 is not set -# CONFIG_LWMON is not set -# CONFIG_PCU_E is not set -# CONFIG_CCM is not set -# CONFIG_LANTEC is not set -# CONFIG_MBX is not set -# CONFIG_WINCEPT is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_CMDLINE_BOOL is not set - -# -# Bus options -# -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set -# CONFIG_PCI_QSPAN is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_CONSISTENT_START=0xff100000 -CONFIG_CONSISTENT_SIZE=0x00200000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_OAKNET is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Userland interfaces -# - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_CPM=y -CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -CONFIG_SERIAL_CPM_SCC2=y -CONFIG_SERIAL_CPM_SCC3=y -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -CONFIG_SERIAL_CPM_SMC2=y -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set -# CONFIG_HUGETLBFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MSDOS_PARTITION is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# MPC8xx CPM Options -# -CONFIG_SCC_ENET=y -CONFIG_SCC1_ENET=y -# CONFIG_SCC2_ENET is not set -# CONFIG_SCC3_ENET is not set -CONFIG_FEC_ENET=y -# CONFIG_USE_MDIO is not set -CONFIG_ENET_BIG_BUFFERS=y - -# -# Generic MPC8xx Options -# -CONFIG_8xx_COPYBACK=y -# CONFIG_8xx_CPU6 is not set -CONFIG_NO_UCODE_PATCH=y -# CONFIG_USB_SOF_UCODE_PATCH is not set -# CONFIG_I2C_SPI_UCODE_PATCH is not set -# CONFIG_I2C_SPI_SMC1_UCODE_PATCH is not set - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/rpxlite_defconfig b/arch/ppc/configs/rpxlite_defconfig deleted file mode 100644 index 828dd6eb5b43..000000000000 --- a/arch/ppc/configs/rpxlite_defconfig +++ /dev/null @@ -1,581 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.10-rc1 -# Mon Nov 1 16:41:09 2004 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -# CONFIG_CLEAN_COMPILE is not set -CONFIG_BROKEN=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_KOBJECT_UEVENT is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -# CONFIG_FUTEX is not set -# CONFIG_EPOLL is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -# CONFIG_SHMEM is not set -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -CONFIG_TINY_SHMEM=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Processor -# -# CONFIG_6xx is not set -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -CONFIG_8xx=y -# CONFIG_E500 is not set -CONFIG_MATH_EMULATION=y -# CONFIG_CPU_FREQ is not set -CONFIG_EMBEDDEDBOOT=y -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -CONFIG_RPXLITE=y -# CONFIG_RPXCLASSIC is not set -# CONFIG_BSEIP is not set -# CONFIG_FADS is not set -# CONFIG_TQM823L is not set -# CONFIG_TQM850L is not set -# CONFIG_TQM855L is not set -# CONFIG_TQM860L is not set -# CONFIG_FPS850L is not set -# CONFIG_SPD823TS is not set -# CONFIG_IVMS8 is not set -# CONFIG_IVML24 is not set -# CONFIG_SM850 is not set -# CONFIG_HERMES_PRO is not set -# CONFIG_IP860 is not set -# CONFIG_LWMON is not set -# CONFIG_PCU_E is not set -# CONFIG_CCM is not set -# CONFIG_LANTEC is not set -# CONFIG_MBX is not set -# CONFIG_WINCEPT is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_CMDLINE_BOOL is not set - -# -# Bus options -# -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set -# CONFIG_PCI_QSPAN is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_CONSISTENT_START=0xff100000 -CONFIG_CONSISTENT_SIZE=0x00200000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_OAKNET is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Userland interfaces -# - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_SERIAL_CPM=y -CONFIG_SERIAL_CPM_CONSOLE=y -# CONFIG_SERIAL_CPM_SCC1 is not set -# CONFIG_SERIAL_CPM_SCC2 is not set -# CONFIG_SERIAL_CPM_SCC3 is not set -# CONFIG_SERIAL_CPM_SCC4 is not set -CONFIG_SERIAL_CPM_SMC1=y -# CONFIG_SERIAL_CPM_SMC2 is not set -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set -# CONFIG_HUGETLBFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MSDOS_PARTITION is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# MPC8xx CPM Options -# -CONFIG_SCC_ENET=y -# CONFIG_SCC1_ENET is not set -CONFIG_SCC2_ENET=y -# CONFIG_SCC3_ENET is not set -# CONFIG_FEC_ENET is not set -# CONFIG_ENET_BIG_BUFFERS is not set - -# -# Generic MPC8xx Options -# -CONFIG_8xx_COPYBACK=y -# CONFIG_8xx_CPU6 is not set -CONFIG_NO_UCODE_PATCH=y -# CONFIG_USB_SOF_UCODE_PATCH is not set -# CONFIG_I2C_SPI_UCODE_PATCH is not set -# CONFIG_I2C_SPI_SMC1_UCODE_PATCH is not set - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/sandpoint_defconfig b/arch/ppc/configs/sandpoint_defconfig deleted file mode 100644 index 9525e34138fc..000000000000 --- a/arch/ppc/configs/sandpoint_defconfig +++ /dev/null @@ -1,737 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_STANDALONE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_HOTPLUG=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -CONFIG_ALTIVEC=y -# CONFIG_TAU is not set -# CONFIG_CPU_FREQ is not set -CONFIG_PPC_STD_MMU=y - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_WILLOW is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_EV64260 is not set -# CONFIG_SPRUCE is not set -# CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -CONFIG_SANDPOINT=y -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX6 is not set -# CONFIG_TQM8260 is not set -CONFIG_PPC_GEN550=y -CONFIG_EPIC_SERIAL_MODE=y -CONFIG_MPC10X_BRIDGE=y -# CONFIG_MPC10X_STORE_GATHERING is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=m -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set - -# -# PCMCIA/CardBus support -# -# CONFIG_PCMCIA is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_CARMEL is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_IDEDISK_STROKE is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_IDE_TASK_IOCTL is not set -CONFIG_IDE_TASKFILE_IO=y - -# -# IDE chipset support/bugfixes -# -CONFIG_BLK_DEV_SL82C105=y -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -CONFIG_NET_VENDOR_3COM=y -CONFIG_VORTEX=y -# CONFIG_TYPHOON is not set - -# -# Tulip family network device support -# -CONFIG_NET_TULIP=y -# CONFIG_DE2104X is not set -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -# CONFIG_TULIP_MMIO is not set -# CONFIG_TULIP_NAPI is not set -# CONFIG_DE4X5 is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -CONFIG_E100=y -# CONFIG_E100_NAPI is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -CONFIG_8139TOO=y -CONFIG_8139TOO_PIO=y -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_8139_OLD_RX_RESET is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PPP=m -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -# CONFIG_PPPOE is not set -# CONFIG_SLIP is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Userland interfaces -# - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -# CONFIG_SERIO is not set -# CONFIG_SERIO_I8042 is not set - -# -# Input Device Drivers -# - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_BANDWIDTH is not set -# CONFIG_USB_DYNAMIC_MINORS is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_EHCI_HCD is not set -CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_UHCI_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_BLUETOOTH_TTY is not set -CONFIG_USB_ACM=m -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_STORAGE is not set - -# -# USB Human Interface Devices (HID) -# -# CONFIG_USB_HID is not set - -# -# Input core support is needed for USB HID input layer or HIDBP support -# - -# -# USB HID Boot Protocol drivers -# - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set - -# -# USB Multimedia devices -# -# CONFIG_USB_DABUSB is not set - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# - -# -# USB Serial Converter support -# -CONFIG_USB_SERIAL=m -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -CONFIG_USB_SERIAL_VISOR=m -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_TIGL is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGETSERVO is not set -# CONFIG_USB_TEST is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_ZISOFS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/spruce_defconfig b/arch/ppc/configs/spruce_defconfig deleted file mode 100644 index 430dd9c59feb..000000000000 --- a/arch/ppc/configs/spruce_defconfig +++ /dev/null @@ -1,577 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_STANDALONE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -CONFIG_6xx=y -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_ALTIVEC is not set -# CONFIG_TAU is not set -# CONFIG_CPU_FREQ is not set -CONFIG_PPC_STD_MMU=y - -# -# Platform options -# -# CONFIG_PPC_MULTIPLATFORM is not set -# CONFIG_APUS is not set -# CONFIG_WILLOW is not set -# CONFIG_PCORE is not set -# CONFIG_POWERPMC250 is not set -# CONFIG_EV64260 is not set -CONFIG_SPRUCE=y -# CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set -# CONFIG_MVME5100 is not set -# CONFIG_PPLUS is not set -# CONFIG_PRPMC750 is not set -# CONFIG_PRPMC800 is not set -# CONFIG_SANDPOINT is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set -# CONFIG_PAL4 is not set -# CONFIG_GEMINI is not set -# CONFIG_EST8260 is not set -# CONFIG_SBS8260 is not set -# CONFIG_RPX6 is not set -# CONFIG_TQM8260 is not set -CONFIG_PPC_GEN550=y -CONFIG_SPRUCE_BAUD_33M=y -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -CONFIG_GENERIC_ISA_DMA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LEGACY_PROC=y -# CONFIG_PCI_NAMES is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00800000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_CARMEL is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Userland interfaces -# - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -CONFIG_SERIO_PCIPS2=y - -# -# Input Device Drivers -# - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=2 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_GEN_RTC=y -# CONFIG_GEN_RTC_X is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_ZISOFS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Library routines -# -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/sycamore_defconfig b/arch/ppc/configs/sycamore_defconfig deleted file mode 100644 index 6996cca18f3e..000000000000 --- a/arch/ppc/configs/sycamore_defconfig +++ /dev/null @@ -1,663 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_STANDALONE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_FUTEX=y -# CONFIG_EPOLL is not set -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y -CONFIG_KMOD=y - -# -# Processor -# -# CONFIG_6xx is not set -CONFIG_40x=y -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_MATH_EMULATION is not set -# CONFIG_CPU_FREQ is not set -CONFIG_4xx=y - -# -# IBM 4xx options -# -# CONFIG_ASH is not set -# CONFIG_CPCI405 is not set -# CONFIG_EP405 is not set -# CONFIG_EVB405EP is not set -# CONFIG_OAK is not set -# CONFIG_REDWOOD_5 is not set -# CONFIG_REDWOOD_6 is not set -CONFIG_SYCAMORE=y -# CONFIG_WALNUT is not set -CONFIG_IBM_OCP=y -CONFIG_PPC_OCP=y -CONFIG_BIOS_FIXUP=y -CONFIG_405GPR=y -CONFIG_IBM_OPENBIOS=y -# CONFIG_PM is not set -CONFIG_UART0_TTYS0=y -# CONFIG_UART0_TTYS1 is not set -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_PC_KEYBOARD is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_CARMEL is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -CONFIG_IBM_EMAC=y -# CONFIG_IBM_EMAC_ERRMSG is not set -CONFIG_IBM_EMAC_RXB=64 -CONFIG_IBM_EMAC_TXB=8 -CONFIG_IBM_EMAC_FGAP=8 -CONFIG_IBM_EMAC_SKBRES=0 -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# IrDA (infrared) support -# -# CONFIG_IRDA is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y - -# -# I2C Algorithms -# -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set - -# -# I2C Hardware Bus support -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set -# CONFIG_I2C_IBM_IIC is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_SCx200_ACB is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_VOODOO3 is not set - -# -# Hardware Sensors Chip support -# -# CONFIG_I2C_SENSOR is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83627HF is not set - -# -# Other I2C Chip support -# -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MSDOS_PARTITION is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_NEC98_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# IBM 40x options -# - -# -# Library routines -# -CONFIG_CRC32=y - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set -CONFIG_OCP=y - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/taishan_defconfig b/arch/ppc/configs/taishan_defconfig deleted file mode 100644 index 1ca0204267b1..000000000000 --- a/arch/ppc/configs/taishan_defconfig +++ /dev/null @@ -1,1077 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Mon Feb 12 11:11:58 2007 -# -CONFIG_MMU=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_ARCH_HAS_ILOG2_U32=y -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_GENERIC_BUG=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_SYSFS_DEPRECATED=y -# CONFIG_RELAY is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_HOTPLUG is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Block layer -# -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Processor -# -# CONFIG_6xx is not set -# CONFIG_40x is not set -CONFIG_44x=y -# CONFIG_8xx is not set -# CONFIG_E200 is not set -# CONFIG_E500 is not set -CONFIG_PPC_DCR_NATIVE=y -CONFIG_PPC_DCR=y -CONFIG_BOOKE=y -CONFIG_PTE_64BIT=y -CONFIG_PHYS_64BIT=y -# CONFIG_MATH_EMULATION is not set -# CONFIG_KEXEC is not set -# CONFIG_CPU_FREQ is not set -CONFIG_4xx=y -CONFIG_WANT_EARLY_SERIAL=y - -# -# IBM 4xx options -# -# CONFIG_BAMBOO is not set -# CONFIG_EBONY is not set -# CONFIG_LUAN is not set -# CONFIG_YUCCA is not set -# CONFIG_OCOTEA is not set -CONFIG_TAISHAN=y -CONFIG_440GX=y -CONFIG_440A=y -CONFIG_IBM_OCP=y -CONFIG_IBM_EMAC4=y -CONFIG_PPC4xx_DMA=y -CONFIG_PPC4xx_EDMA=y -CONFIG_PPC_GEN550=y -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_PC_KEYBOARD is not set -# CONFIG_HIGHMEM is not set -CONFIG_ARCH_POPULATES_NODE_MAP=y -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on console=ttyS0,115200" -CONFIG_SECCOMP=y -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -CONFIG_ZONE_DMA=y -# CONFIG_PPC_I8259 is not set -CONFIG_PPC_INDIRECT_PCI=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PCI_DEBUG is not set - -# -# PCCARD (PCMCIA/CardBus) support -# - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_CONSISTENT_START=0xff100000 -CONFIG_CONSISTENT_SIZE=0x00200000 -CONFIG_BOOT_LOAD=0x01000000 - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_MULTIPLE_TABLES is not set -# CONFIG_IP_ROUTE_MULTIPATH is not set -# CONFIG_IP_ROUTE_VERBOSE is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -CONFIG_BRIDGE=y -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_IEEE80211 is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -# CONFIG_STANDALONE is not set -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -# CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_GEOMETRY is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set - -# -# Mapping drivers for chip access -# -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0x8000000 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -# CONFIG_MTD_PCI is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set -# CONFIG_MTD_NAND_CAFE is not set - -# -# OneNAND Flash Device Drivers -# -# CONFIG_MTD_ONENAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set - -# -# Misc devices -# -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_NETLINK is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# -# CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# -# CONFIG_MAC_EMUMOUSEBTN is not set -# CONFIG_WINDFARM is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -# CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_IBM_EMAC=y -CONFIG_IBM_EMAC_RXB=128 -CONFIG_IBM_EMAC_TXB=128 -CONFIG_IBM_EMAC_POLL_WEIGHT=32 -CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256 -CONFIG_IBM_EMAC_RX_SKB_HEADROOM=0 -CONFIG_IBM_EMAC_PHY_RX_CLK_FIX=y -# CONFIG_IBM_EMAC_DEBUG is not set -CONFIG_IBM_EMAC_ZMII=y -CONFIG_IBM_EMAC_RGMII=y -CONFIG_IBM_EMAC_TAH=y -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -CONFIG_E100=y -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_SC92031 is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_QLA3XXX is not set -# CONFIG_ATL1 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -# CONFIG_NETXEN_NIC is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -# CONFIG_PPP_ASYNC is not set -# CONFIG_PPP_SYNC_TTY is not set -# CONFIG_PPP_DEFLATE is not set -# CONFIG_PPP_BSDCOMP is not set -# CONFIG_PPP_MPPE is not set -CONFIG_PPPOE=y -# CONFIG_SLIP is not set -CONFIG_SLHC=y -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -# CONFIG_SERIAL_8250_MANY_PORTS is not set -CONFIG_SERIAL_8250_SHARE_IRQ=y -# CONFIG_SERIAL_8250_DETECT_IRQ is not set -# CONFIG_SERIAL_8250_RSA is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -CONFIG_HW_RANDOM=m -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y - -# -# I2C Algorithms -# -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# -# I2C Hardware Bus support -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set -CONFIG_I2C_IBM_IIC=y -# CONFIG_I2C_MPC is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_VOODOO3 is not set -# CONFIG_I2C_PCA_ISA is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set -CONFIG_SENSORS_EEPROM=y -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_M41T00 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -CONFIG_FIRMWARE_EDID=y -# CONFIG_FB is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT2_FS_XIP=y -CONFIG_FS_XIP=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -CONFIG_JBD_DEBUG=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -CONFIG_JFFS2_SUMMARY=y -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Distributed Lock Manager -# -# CONFIG_DLM is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_LIST is not set -CONFIG_FORCED_INLINING=y -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_KGDB is not set -# CONFIG_XMON is not set -CONFIG_BDI_SWITCH=y -# CONFIG_SERIAL_TEXT_DEBUG is not set -CONFIG_PPC_OCP=y - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/configs/walnut_defconfig b/arch/ppc/configs/walnut_defconfig deleted file mode 100644 index bf9721a7a818..000000000000 --- a/arch/ppc/configs/walnut_defconfig +++ /dev/null @@ -1,578 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MMU=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_GENERIC_NVRAM=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -# CONFIG_STANDALONE is not set -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_HOTPLUG is not set -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_FUTEX=y -# CONFIG_EPOLL is not set -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# Processor -# -# CONFIG_6xx is not set -CONFIG_40x=y -# CONFIG_44x is not set -# CONFIG_POWER3 is not set -# CONFIG_POWER4 is not set -# CONFIG_8xx is not set -# CONFIG_MATH_EMULATION is not set -# CONFIG_CPU_FREQ is not set -CONFIG_4xx=y - -# -# IBM 4xx options -# -# CONFIG_ASH is not set -# CONFIG_BUBINGA is not set -# CONFIG_CPCI405 is not set -# CONFIG_EP405 is not set -# CONFIG_OAK is not set -# CONFIG_REDWOOD_5 is not set -# CONFIG_REDWOOD_6 is not set -# CONFIG_SYCAMORE is not set -CONFIG_WALNUT=y -CONFIG_IBM405_ERR77=y -CONFIG_IBM405_ERR51=y -CONFIG_IBM_OCP=y -CONFIG_BIOS_FIXUP=y -CONFIG_405GP=y -CONFIG_IBM_OPENBIOS=y -# CONFIG_PM is not set -CONFIG_UART0_TTYS0=y -# CONFIG_UART0_TTYS1 is not set -CONFIG_NOT_COHERENT_CACHE=y - -# -# Platform options -# -# CONFIG_PC_KEYBOARD is not set -# CONFIG_SMP is not set -# CONFIG_PREEMPT is not set -# CONFIG_HIGHMEM is not set -CONFIG_KERNEL_ELF=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="ip=on" - -# -# Bus options -# -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LEGACY_PROC=y -# CONFIG_PCI_NAMES is not set - -# -# Advanced setup -# -# CONFIG_ADVANCED_OPTIONS is not set - -# -# Default settings for advanced configuration options are used -# -CONFIG_HIGHMEM_START=0xfe000000 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_KERNEL_START=0xc0000000 -CONFIG_TASK_SIZE=0x80000000 -CONFIG_BOOT_LOAD=0x00400000 - -# -# Device Drivers -# - -# -# Generic Driver Options -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_CARMEL is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_LBD is not set - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Macintosh device drivers -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_OAKNET is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PCIPS2 is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_QIC02_TAPE is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_FAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -# CONFIG_EXPORTFS is not set -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MSDOS_PARTITION is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_NEC98_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# IBM 40x options -# - -# -# Library routines -# -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set - -# -# Kernel hacking -# -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SERIAL_TEXT_DEBUG is not set -CONFIG_PPC_OCP=y - -# -# Security options -# -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set diff --git a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile deleted file mode 100644 index 7b739054968f..000000000000 --- a/arch/ppc/kernel/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Makefile for the linux kernel. -# -extra-$(CONFIG_PPC_STD_MMU) := head.o -extra-$(CONFIG_40x) := head_4xx.o -extra-$(CONFIG_44x) := head_44x.o -extra-$(CONFIG_8xx) := head_8xx.o -extra-y += vmlinux.lds - -obj-y := entry.o traps.o time.o misc.o \ - setup.o \ - ppc_htab.o -obj-$(CONFIG_MODULES) += ppc_ksyms.o -obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_KGDB) += ppc-stub.o -obj-$(CONFIG_SMP) += smp.o smp-tbsync.o -obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o - -ifndef CONFIG_MATH_EMULATION -obj-$(CONFIG_8xx) += softemu8xx.o -endif diff --git a/arch/ppc/kernel/asm-offsets.c b/arch/ppc/kernel/asm-offsets.c deleted file mode 100644 index 8dcbdd6c2d2c..000000000000 --- a/arch/ppc/kernel/asm-offsets.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -int -main(void) -{ - DEFINE(THREAD, offsetof(struct task_struct, thread)); - DEFINE(THREAD_INFO, offsetof(struct task_struct, stack)); - DEFINE(MM, offsetof(struct task_struct, mm)); - DEFINE(PTRACE, offsetof(struct task_struct, ptrace)); - DEFINE(KSP, offsetof(struct thread_struct, ksp)); - DEFINE(PGDIR, offsetof(struct thread_struct, pgdir)); - DEFINE(PT_REGS, offsetof(struct thread_struct, regs)); - DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode)); - DEFINE(THREAD_FPR0, offsetof(struct thread_struct, fpr[0])); - DEFINE(THREAD_FPSCR, offsetof(struct thread_struct, fpscr)); -#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) - DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0)); - DEFINE(PT_PTRACED, PT_PTRACED); -#endif -#ifdef CONFIG_ALTIVEC - DEFINE(THREAD_VR0, offsetof(struct thread_struct, vr[0])); - DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave)); - DEFINE(THREAD_VSCR, offsetof(struct thread_struct, vscr)); - DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr)); -#endif /* CONFIG_ALTIVEC */ - /* Interrupt register frame */ - DEFINE(STACK_FRAME_OVERHEAD, STACK_FRAME_OVERHEAD); - DEFINE(INT_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); - /* in fact we only use gpr0 - gpr9 and gpr20 - gpr23 */ - DEFINE(GPR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[0])); - DEFINE(GPR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[1])); - DEFINE(GPR2, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[2])); - DEFINE(GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[3])); - DEFINE(GPR4, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[4])); - DEFINE(GPR5, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[5])); - DEFINE(GPR6, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[6])); - DEFINE(GPR7, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[7])); - DEFINE(GPR8, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[8])); - DEFINE(GPR9, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[9])); - DEFINE(GPR10, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[10])); - DEFINE(GPR11, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[11])); - DEFINE(GPR12, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[12])); - DEFINE(GPR13, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[13])); - DEFINE(GPR14, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[14])); - DEFINE(GPR15, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[15])); - DEFINE(GPR16, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[16])); - DEFINE(GPR17, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[17])); - DEFINE(GPR18, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[18])); - DEFINE(GPR19, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[19])); - DEFINE(GPR20, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[20])); - DEFINE(GPR21, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[21])); - DEFINE(GPR22, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[22])); - DEFINE(GPR23, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[23])); - DEFINE(GPR24, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[24])); - DEFINE(GPR25, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[25])); - DEFINE(GPR26, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[26])); - DEFINE(GPR27, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[27])); - DEFINE(GPR28, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[28])); - DEFINE(GPR29, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[29])); - DEFINE(GPR30, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[30])); - DEFINE(GPR31, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[31])); - /* Note: these symbols include _ because they overlap with special - * register names - */ - DEFINE(_NIP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, nip)); - DEFINE(_MSR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, msr)); - DEFINE(_CTR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ctr)); - DEFINE(_LINK, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, link)); - DEFINE(_CCR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ccr)); - DEFINE(_MQ, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, mq)); - DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer)); - DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); - DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); - /* The PowerPC 400-class & Book-E processors have neither the DAR nor the DSISR - * SPRs. Hence, we overload them to hold the similar DEAR and ESR SPRs - * for such processors. For critical interrupts we use them to - * hold SRR0 and SRR1. - */ - DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); - DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); - DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3)); - DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result)); - DEFINE(TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap)); - DEFINE(CLONE_VM, CLONE_VM); - DEFINE(CLONE_UNTRACED, CLONE_UNTRACED); - DEFINE(MM_PGD, offsetof(struct mm_struct, pgd)); - - /* About the CPU features table */ - DEFINE(CPU_SPEC_ENTRY_SIZE, sizeof(struct cpu_spec)); - DEFINE(CPU_SPEC_PVR_MASK, offsetof(struct cpu_spec, pvr_mask)); - DEFINE(CPU_SPEC_PVR_VALUE, offsetof(struct cpu_spec, pvr_value)); - DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features)); - DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup)); - - DEFINE(TI_TASK, offsetof(struct thread_info, task)); - DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain)); - DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); - DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags)); - DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); - DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); - - DEFINE(pbe_address, offsetof(struct pbe, address)); - DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address)); - DEFINE(pbe_next, offsetof(struct pbe, next)); - - DEFINE(TASK_SIZE, TASK_SIZE); - DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28); - - /* datapage offsets for use by vdso */ - DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct vdso_data, tb_orig_stamp)); - DEFINE(CFG_TB_TICKS_PER_SEC, offsetof(struct vdso_data, tb_ticks_per_sec)); - DEFINE(CFG_TB_TO_XS, offsetof(struct vdso_data, tb_to_xs)); - DEFINE(CFG_STAMP_XSEC, offsetof(struct vdso_data, stamp_xsec)); - DEFINE(CFG_TB_UPDATE_COUNT, offsetof(struct vdso_data, tb_update_count)); - DEFINE(CFG_TZ_MINUTEWEST, offsetof(struct vdso_data, tz_minuteswest)); - DEFINE(CFG_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime)); - DEFINE(CFG_SYSCALL_MAP32, offsetof(struct vdso_data, syscall_map_32)); - DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec)); - DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec)); - DEFINE(TVAL32_TV_SEC, offsetof(struct timeval, tv_sec)); - DEFINE(TVAL32_TV_USEC, offsetof(struct timeval, tv_usec)); - DEFINE(TSPEC32_TV_SEC, offsetof(struct timespec, tv_sec)); - DEFINE(TSPEC32_TV_NSEC, offsetof(struct timespec, tv_nsec)); - - /* timeval/timezone offsets for use by vdso */ - DEFINE(TZONE_TZ_MINWEST, offsetof(struct timezone, tz_minuteswest)); - DEFINE(TZONE_TZ_DSTTIME, offsetof(struct timezone, tz_dsttime)); - - /* Other bits used by the vdso */ - DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); - DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC); - DEFINE(NSEC_PER_SEC, NSEC_PER_SEC); - DEFINE(CLOCK_REALTIME_RES, TICK_NSEC); - - return 0; -} diff --git a/arch/ppc/kernel/cpu_setup_power4.S b/arch/ppc/kernel/cpu_setup_power4.S deleted file mode 100644 index 6a674e834eeb..000000000000 --- a/arch/ppc/kernel/cpu_setup_power4.S +++ /dev/null @@ -1,197 +0,0 @@ -/* - * This file contains low level CPU setup functions. - * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include - -_GLOBAL(__970_cpu_preinit) - /* - * Deal only with PPC970 and PPC970FX. - */ - mfspr r0,SPRN_PVR - srwi r0,r0,16 - cmpwi cr0,r0,0x39 - cmpwi cr1,r0,0x3c - cror 4*cr0+eq,4*cr0+eq,4*cr1+eq - bnelr - - /* Make sure HID4:rm_ci is off before MMU is turned off, that large - * pages are enabled with HID4:61 and clear HID5:DCBZ_size and - * HID5:DCBZ32_ill - */ - li r0,0 - mfspr r11,SPRN_HID4 - rldimi r11,r0,40,23 /* clear bit 23 (rm_ci) */ - rldimi r11,r0,2,61 /* clear bit 61 (lg_pg_en) */ - sync - mtspr SPRN_HID4,r11 - isync - sync - mfspr r11,SPRN_HID5 - rldimi r11,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */ - sync - mtspr SPRN_HID5,r11 - isync - sync - - /* Setup some basic HID1 features */ - mfspr r0,SPRN_HID1 - li r11,0x1200 /* enable i-fetch cacheability */ - sldi r11,r11,44 /* and prefetch */ - or r0,r0,r11 - mtspr SPRN_HID1,r0 - mtspr SPRN_HID1,r0 - isync - - /* Clear HIOR */ - li r0,0 - sync - mtspr SPRN_HIOR,0 /* Clear interrupt prefix */ - isync - blr - -_GLOBAL(__setup_cpu_ppc970) - mfspr r0,SPRN_HID0 - li r11,5 /* clear DOZE and SLEEP */ - rldimi r0,r11,52,8 /* set NAP and DPM */ - mtspr SPRN_HID0,r0 - mfspr r0,SPRN_HID0 - mfspr r0,SPRN_HID0 - mfspr r0,SPRN_HID0 - mfspr r0,SPRN_HID0 - mfspr r0,SPRN_HID0 - mfspr r0,SPRN_HID0 - sync - isync - blr - -/* Definitions for the table use to save CPU states */ -#define CS_HID0 0 -#define CS_HID1 8 -#define CS_HID4 16 -#define CS_HID5 24 -#define CS_SIZE 32 - - .data - .balign L1_CACHE_BYTES -cpu_state_storage: - .space CS_SIZE - .balign L1_CACHE_BYTES,0 - .text - -/* Called in normal context to backup CPU 0 state. This - * does not include cache settings. This function is also - * called for machine sleep. This does not include the MMU - * setup, BATs, etc... but rather the "special" registers - * like HID0, HID1, HID4, etc... - */ -_GLOBAL(__save_cpu_setup) - /* Some CR fields are volatile, we back it up all */ - mfcr r7 - - /* Get storage ptr */ - lis r5,cpu_state_storage@h - ori r5,r5,cpu_state_storage@l - - /* We only deal with 970 for now */ - mfspr r0,SPRN_PVR - srwi r0,r0,16 - cmpwi cr0,r0,0x39 - cmpwi cr1,r0,0x3c - cror 4*cr0+eq,4*cr0+eq,4*cr1+eq - bne 1f - - /* Save HID0,1,4 and 5 */ - mfspr r3,SPRN_HID0 - std r3,CS_HID0(r5) - mfspr r3,SPRN_HID1 - std r3,CS_HID1(r5) - mfspr r3,SPRN_HID4 - std r3,CS_HID4(r5) - mfspr r3,SPRN_HID5 - std r3,CS_HID5(r5) - -1: - mtcr r7 - blr - -/* Called with no MMU context (typically MSR:IR/DR off) to - * restore CPU state as backed up by the previous - * function. This does not include cache setting - */ -_GLOBAL(__restore_cpu_setup) - /* Some CR fields are volatile, we back it up all */ - mfcr r7 - - /* Get storage ptr */ - lis r5,(cpu_state_storage-KERNELBASE)@h - ori r5,r5,cpu_state_storage@l - - /* We only deal with 970 for now */ - mfspr r0,SPRN_PVR - srwi r0,r0,16 - cmpwi cr0,r0,0x39 - cmpwi cr1,r0,0x3c - cror 4*cr0+eq,4*cr0+eq,4*cr1+eq - bne 1f - - /* Clear interrupt prefix */ - li r0,0 - sync - mtspr SPRN_HIOR,0 - isync - - /* Restore HID0 */ - ld r3,CS_HID0(r5) - sync - isync - mtspr SPRN_HID0,r3 - mfspr r3,SPRN_HID0 - mfspr r3,SPRN_HID0 - mfspr r3,SPRN_HID0 - mfspr r3,SPRN_HID0 - mfspr r3,SPRN_HID0 - mfspr r3,SPRN_HID0 - sync - isync - - /* Restore HID1 */ - ld r3,CS_HID1(r5) - sync - isync - mtspr SPRN_HID1,r3 - mtspr SPRN_HID1,r3 - sync - isync - - /* Restore HID4 */ - ld r3,CS_HID4(r5) - sync - isync - mtspr SPRN_HID4,r3 - sync - isync - - /* Restore HID5 */ - ld r3,CS_HID5(r5) - sync - isync - mtspr SPRN_HID5,r3 - sync - isync -1: - mtcr r7 - blr - diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S deleted file mode 100644 index fcd830a292e2..000000000000 --- a/arch/ppc/kernel/entry.S +++ /dev/null @@ -1,960 +0,0 @@ -/* - * PowerPC version - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP - * Copyright (C) 1996 Cort Dougan - * Adapted for Power Macintosh by Paul Mackerras. - * Low-level exception handlers and MMU support - * rewritten by Paul Mackerras. - * Copyright (C) 1996 Paul Mackerras. - * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). - * - * This file contains the system call entry code, context switch - * code, and exception/interrupt return code for PowerPC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef SHOW_SYSCALLS -#undef SHOW_SYSCALLS_TASK - -/* - * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE. - */ -#if MSR_KERNEL >= 0x10000 -#define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l -#else -#define LOAD_MSR_KERNEL(r, x) li r,(x) -#endif - -#ifdef CONFIG_BOOKE -#include "head_booke.h" -#define TRANSFER_TO_HANDLER_EXC_LEVEL(exc_level) \ - mtspr exc_level##_SPRG,r8; \ - BOOKE_LOAD_EXC_LEVEL_STACK(exc_level); \ - lwz r0,GPR10-INT_FRAME_SIZE(r8); \ - stw r0,GPR10(r11); \ - lwz r0,GPR11-INT_FRAME_SIZE(r8); \ - stw r0,GPR11(r11); \ - mfspr r8,exc_level##_SPRG - - .globl mcheck_transfer_to_handler -mcheck_transfer_to_handler: - TRANSFER_TO_HANDLER_EXC_LEVEL(MCHECK) - b transfer_to_handler_full - - .globl debug_transfer_to_handler -debug_transfer_to_handler: - TRANSFER_TO_HANDLER_EXC_LEVEL(DEBUG) - b transfer_to_handler_full - - .globl crit_transfer_to_handler -crit_transfer_to_handler: - TRANSFER_TO_HANDLER_EXC_LEVEL(CRIT) - /* fall through */ -#endif - -#ifdef CONFIG_40x - .globl crit_transfer_to_handler -crit_transfer_to_handler: - lwz r0,crit_r10@l(0) - stw r0,GPR10(r11) - lwz r0,crit_r11@l(0) - stw r0,GPR11(r11) - /* fall through */ -#endif - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception, turning - * on address translation. - * Note that we rely on the caller having set cr0.eq iff the exception - * occurred in kernel mode (i.e. MSR:PR = 0). - */ - .globl transfer_to_handler_full -transfer_to_handler_full: - SAVE_NVGPRS(r11) - /* fall through */ - - .globl transfer_to_handler -transfer_to_handler: - stw r2,GPR2(r11) - stw r12,_NIP(r11) - stw r9,_MSR(r11) - andi. r2,r9,MSR_PR - mfctr r12 - mfspr r2,SPRN_XER - stw r12,_CTR(r11) - stw r2,_XER(r11) - mfspr r12,SPRN_SPRG3 - addi r2,r12,-THREAD - tovirt(r2,r2) /* set r2 to current */ - beq 2f /* if from user, fix up THREAD.regs */ - addi r11,r1,STACK_FRAME_OVERHEAD - stw r11,PT_REGS(r12) -#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) - /* Check to see if the dbcr0 register is set up to debug. Use the - single-step bit to do this. */ - lwz r12,THREAD_DBCR0(r12) - andis. r12,r12,DBCR0_IC@h - beq+ 3f - /* From user and task is ptraced - load up global dbcr0 */ - li r12,-1 /* clear all pending debug events */ - mtspr SPRN_DBSR,r12 - lis r11,global_dbcr0@ha - tophys(r11,r11) - addi r11,r11,global_dbcr0@l - lwz r12,0(r11) - mtspr SPRN_DBCR0,r12 - lwz r12,4(r11) - addi r12,r12,-1 - stw r12,4(r11) -#endif - b 3f - -2: /* if from kernel, check interrupted DOZE/NAP mode and - * check for stack overflow - */ - lwz r9,THREAD_INFO-THREAD(r12) - cmplw r1,r9 /* if r1 <= current->thread_info */ - ble- stack_ovf /* then the kernel stack overflowed */ -5: -#ifdef CONFIG_6xx - tophys(r9,r9) /* check local flags */ - lwz r12,TI_LOCAL_FLAGS(r9) - mtcrf 0x01,r12 - bt- 31-TLF_NAPPING,4f -#endif /* CONFIG_6xx */ - .globl transfer_to_handler_cont -transfer_to_handler_cont: -3: - mflr r9 - lwz r11,0(r9) /* virtual address of handler */ - lwz r9,4(r9) /* where to go when done */ - mtspr SPRN_SRR0,r11 - mtspr SPRN_SRR1,r10 - mtlr r9 - SYNC - RFI /* jump to handler, enable MMU */ - -#ifdef CONFIG_6xx -4: rlwinm r12,r12,0,~_TLF_NAPPING - stw r12,TI_LOCAL_FLAGS(r9) - b power_save_6xx_restore -#endif - -/* - * On kernel stack overflow, load up an initial stack pointer - * and call StackOverflow(regs), which should not return. - */ -stack_ovf: - /* sometimes we use a statically-allocated stack, which is OK. */ - lis r12,_end@h - ori r12,r12,_end@l - cmplw r1,r12 - ble 5b /* r1 <= &_end is OK */ - SAVE_NVGPRS(r11) - addi r3,r1,STACK_FRAME_OVERHEAD - lis r1,init_thread_union@ha - addi r1,r1,init_thread_union@l - addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD - lis r9,StackOverflow@ha - addi r9,r9,StackOverflow@l - LOAD_MSR_KERNEL(r10,MSR_KERNEL) - FIX_SRR1(r10,r12) - mtspr SPRN_SRR0,r9 - mtspr SPRN_SRR1,r10 - SYNC - RFI - -/* - * Handle a system call. - */ - .stabs "arch/ppc/kernel/",N_SO,0,0,0f - .stabs "entry.S",N_SO,0,0,0f -0: - -_GLOBAL(DoSyscall) - stw r3,ORIG_GPR3(r1) - li r12,0 - stw r12,RESULT(r1) - lwz r11,_CCR(r1) /* Clear SO bit in CR */ - rlwinm r11,r11,0,4,2 - stw r11,_CCR(r1) -#ifdef SHOW_SYSCALLS - bl do_show_syscall -#endif /* SHOW_SYSCALLS */ - rlwinm r10,r1,0,0,18 /* current_thread_info() */ - lwz r11,TI_FLAGS(r10) - andi. r11,r11,_TIF_SYSCALL_T_OR_A - bne- syscall_dotrace -syscall_dotrace_cont: - cmplwi 0,r0,NR_syscalls - lis r10,sys_call_table@h - ori r10,r10,sys_call_table@l - slwi r0,r0,2 - bge- 66f - lwzx r10,r10,r0 /* Fetch system call handler [ptr] */ - mtlr r10 - addi r9,r1,STACK_FRAME_OVERHEAD - PPC440EP_ERR42 - blrl /* Call handler */ - .globl ret_from_syscall -ret_from_syscall: -#ifdef SHOW_SYSCALLS - bl do_show_syscall_exit -#endif - mr r6,r3 - rlwinm r12,r1,0,0,18 /* current_thread_info() */ - /* disable interrupts so current_thread_info()->flags can't change */ - LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ - SYNC - MTMSRD(r10) - lwz r9,TI_FLAGS(r12) - li r8,-_LAST_ERRNO - andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) - bne- syscall_exit_work - cmplw 0,r3,r8 - blt+ syscall_exit_cont - lwz r11,_CCR(r1) /* Load CR */ - neg r3,r3 - oris r11,r11,0x1000 /* Set SO bit in CR */ - stw r11,_CCR(r1) -syscall_exit_cont: -#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) - /* If the process has its own DBCR0 value, load it up. The single - step bit tells us that dbcr0 should be loaded. */ - lwz r0,THREAD+THREAD_DBCR0(r2) - andis. r10,r0,DBCR0_IC@h - bnel- load_dbcr0 -#endif -#ifdef CONFIG_44x - lis r4,icache_44x_need_flush@ha - lwz r5,icache_44x_need_flush@l(r4) - cmplwi cr0,r5,0 - bne- 2f -1: -#endif /* CONFIG_44x */ -BEGIN_FTR_SECTION - lwarx r7,0,r1 -END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) - stwcx. r0,0,r1 /* to clear the reservation */ - lwz r4,_LINK(r1) - lwz r5,_CCR(r1) - mtlr r4 - mtcr r5 - lwz r7,_NIP(r1) - lwz r8,_MSR(r1) - FIX_SRR1(r8, r0) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - mtspr SPRN_SRR0,r7 - mtspr SPRN_SRR1,r8 - SYNC - RFI -#ifdef CONFIG_44x -2: li r7,0 - iccci r0,r0 - stw r7,icache_44x_need_flush@l(r4) - b 1b -#endif /* CONFIG_44x */ - -66: li r3,-ENOSYS - b ret_from_syscall - - .globl ret_from_fork -ret_from_fork: - REST_NVGPRS(r1) - bl schedule_tail - li r3,0 - b ret_from_syscall - -/* Traced system call support */ -syscall_dotrace: - SAVE_NVGPRS(r1) - li r0,0xc00 - stw r0,TRAP(r1) - addi r3,r1,STACK_FRAME_OVERHEAD - bl do_syscall_trace_enter - lwz r0,GPR0(r1) /* Restore original registers */ - lwz r3,GPR3(r1) - lwz r4,GPR4(r1) - lwz r5,GPR5(r1) - lwz r6,GPR6(r1) - lwz r7,GPR7(r1) - lwz r8,GPR8(r1) - REST_NVGPRS(r1) - b syscall_dotrace_cont - -syscall_exit_work: - andi. r0,r9,_TIF_RESTOREALL - beq+ 0f - REST_NVGPRS(r1) - b 2f -0: cmplw 0,r3,r8 - blt+ 1f - andi. r0,r9,_TIF_NOERROR - bne- 1f - lwz r11,_CCR(r1) /* Load CR */ - neg r3,r3 - oris r11,r11,0x1000 /* Set SO bit in CR */ - stw r11,_CCR(r1) - -1: stw r6,RESULT(r1) /* Save result */ - stw r3,GPR3(r1) /* Update return value */ -2: andi. r0,r9,(_TIF_PERSYSCALL_MASK) - beq 4f - - /* Clear per-syscall TIF flags if any are set. */ - - li r11,_TIF_PERSYSCALL_MASK - addi r12,r12,TI_FLAGS -3: lwarx r8,0,r12 - andc r8,r8,r11 -#ifdef CONFIG_IBM405_ERR77 - dcbt 0,r12 -#endif - stwcx. r8,0,r12 - bne- 3b - subi r12,r12,TI_FLAGS - -4: /* Anything which requires enabling interrupts? */ - andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) - beq ret_from_except - - /* Re-enable interrupts */ - ori r10,r10,MSR_EE - SYNC - MTMSRD(r10) - - /* Save NVGPRS if they're not saved already */ - lwz r4,TRAP(r1) - andi. r4,r4,1 - beq 5f - SAVE_NVGPRS(r1) - li r4,0xc00 - stw r4,TRAP(r1) -5: - addi r3,r1,STACK_FRAME_OVERHEAD - bl do_syscall_trace_leave - b ret_from_except_full - -#ifdef SHOW_SYSCALLS -do_show_syscall: -#ifdef SHOW_SYSCALLS_TASK - lis r11,show_syscalls_task@ha - lwz r11,show_syscalls_task@l(r11) - cmp 0,r2,r11 - bnelr -#endif - stw r31,GPR31(r1) - mflr r31 - lis r3,7f@ha - addi r3,r3,7f@l - lwz r4,GPR0(r1) - lwz r5,GPR3(r1) - lwz r6,GPR4(r1) - lwz r7,GPR5(r1) - lwz r8,GPR6(r1) - lwz r9,GPR7(r1) - bl printk - lis r3,77f@ha - addi r3,r3,77f@l - lwz r4,GPR8(r1) - mr r5,r2 - bl printk - lwz r0,GPR0(r1) - lwz r3,GPR3(r1) - lwz r4,GPR4(r1) - lwz r5,GPR5(r1) - lwz r6,GPR6(r1) - lwz r7,GPR7(r1) - lwz r8,GPR8(r1) - mtlr r31 - lwz r31,GPR31(r1) - blr - -do_show_syscall_exit: -#ifdef SHOW_SYSCALLS_TASK - lis r11,show_syscalls_task@ha - lwz r11,show_syscalls_task@l(r11) - cmp 0,r2,r11 - bnelr -#endif - stw r31,GPR31(r1) - mflr r31 - stw r3,RESULT(r1) /* Save result */ - mr r4,r3 - lis r3,79f@ha - addi r3,r3,79f@l - bl printk - lwz r3,RESULT(r1) - mtlr r31 - lwz r31,GPR31(r1) - blr - -7: .string "syscall %d(%x, %x, %x, %x, %x, " -77: .string "%x), current=%p\n" -79: .string " -> %x\n" - .align 2,0 - -#ifdef SHOW_SYSCALLS_TASK - .data - .globl show_syscalls_task -show_syscalls_task: - .long -1 - .text -#endif -#endif /* SHOW_SYSCALLS */ - -/* - * The fork/clone functions need to copy the full register set into - * the child process. Therefore we need to save all the nonvolatile - * registers (r13 - r31) before calling the C code. - */ - .globl ppc_fork -ppc_fork: - SAVE_NVGPRS(r1) - lwz r0,TRAP(r1) - rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ - stw r0,TRAP(r1) /* register set saved */ - b sys_fork - - .globl ppc_vfork -ppc_vfork: - SAVE_NVGPRS(r1) - lwz r0,TRAP(r1) - rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ - stw r0,TRAP(r1) /* register set saved */ - b sys_vfork - - .globl ppc_clone -ppc_clone: - SAVE_NVGPRS(r1) - lwz r0,TRAP(r1) - rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ - stw r0,TRAP(r1) /* register set saved */ - b sys_clone - - .globl ppc_swapcontext -ppc_swapcontext: - SAVE_NVGPRS(r1) - lwz r0,TRAP(r1) - rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ - stw r0,TRAP(r1) /* register set saved */ - b sys_swapcontext - -/* - * Top-level page fault handling. - * This is in assembler because if do_page_fault tells us that - * it is a bad kernel page fault, we want to save the non-volatile - * registers before calling bad_page_fault. - */ - .globl handle_page_fault -handle_page_fault: - stw r4,_DAR(r1) - addi r3,r1,STACK_FRAME_OVERHEAD - bl do_page_fault - cmpwi r3,0 - beq+ ret_from_except - SAVE_NVGPRS(r1) - lwz r0,TRAP(r1) - clrrwi r0,r0,1 - stw r0,TRAP(r1) - mr r5,r3 - addi r3,r1,STACK_FRAME_OVERHEAD - lwz r4,_DAR(r1) - bl bad_page_fault - b ret_from_except_full - -/* - * This routine switches between two different tasks. The process - * state of one is saved on its kernel stack. Then the state - * of the other is restored from its kernel stack. The memory - * management hardware is updated to the second process's state. - * Finally, we can return to the second process. - * On entry, r3 points to the THREAD for the current task, r4 - * points to the THREAD for the new task. - * - * This routine is always called with interrupts disabled. - * - * Note: there are two ways to get to the "going out" portion - * of this code; either by coming in via the entry (_switch) - * or via "fork" which must set up an environment equivalent - * to the "_switch" path. If you change this , you'll have to - * change the fork code also. - * - * The code which creates the new task context is in 'copy_thread' - * in arch/ppc/kernel/process.c - */ -_GLOBAL(_switch) - stwu r1,-INT_FRAME_SIZE(r1) - mflr r0 - stw r0,INT_FRAME_SIZE+4(r1) - /* r3-r12 are caller saved -- Cort */ - SAVE_NVGPRS(r1) - stw r0,_NIP(r1) /* Return to switch caller */ - mfmsr r11 - li r0,MSR_FP /* Disable floating-point */ -#ifdef CONFIG_ALTIVEC -BEGIN_FTR_SECTION - oris r0,r0,MSR_VEC@h /* Disable altivec */ - mfspr r12,SPRN_VRSAVE /* save vrsave register value */ - stw r12,THREAD+THREAD_VRSAVE(r2) -END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) -#endif /* CONFIG_ALTIVEC */ - and. r0,r0,r11 /* FP or altivec enabled? */ - beq+ 1f - andc r11,r11,r0 - MTMSRD(r11) - isync -1: stw r11,_MSR(r1) - mfcr r10 - stw r10,_CCR(r1) - stw r1,KSP(r3) /* Set old stack pointer */ - -#ifdef CONFIG_SMP - /* We need a sync somewhere here to make sure that if the - * previous task gets rescheduled on another CPU, it sees all - * stores it has performed on this one. - */ - sync -#endif /* CONFIG_SMP */ - - tophys(r0,r4) - CLR_TOP32(r0) - mtspr SPRN_SPRG3,r0 /* Update current THREAD phys addr */ - lwz r1,KSP(r4) /* Load new stack pointer */ - - /* save the old current 'last' for return value */ - mr r3,r2 - addi r2,r4,-THREAD /* Update current */ - -#ifdef CONFIG_ALTIVEC -BEGIN_FTR_SECTION - lwz r0,THREAD+THREAD_VRSAVE(r2) - mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ -END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) -#endif /* CONFIG_ALTIVEC */ - lwz r0,_CCR(r1) - mtcrf 0xFF,r0 - /* r3-r12 are destroyed -- Cort */ - REST_NVGPRS(r1) - - lwz r4,_NIP(r1) /* Return to _switch caller in new task */ - mtlr r4 - addi r1,r1,INT_FRAME_SIZE - blr - - .globl fast_exception_return -fast_exception_return: -#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) - andi. r10,r9,MSR_RI /* check for recoverable interrupt */ - beq 1f /* if not, we've got problems */ -#endif - -2: REST_4GPRS(3, r11) - lwz r10,_CCR(r11) - REST_GPR(1, r11) - mtcr r10 - lwz r10,_LINK(r11) - mtlr r10 - REST_GPR(10, r11) - mtspr SPRN_SRR1,r9 - mtspr SPRN_SRR0,r12 - REST_GPR(9, r11) - REST_GPR(12, r11) - lwz r11,GPR11(r11) - SYNC - RFI - -#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) -/* check if the exception happened in a restartable section */ -1: lis r3,exc_exit_restart_end@ha - addi r3,r3,exc_exit_restart_end@l - cmplw r12,r3 - bge 3f - lis r4,exc_exit_restart@ha - addi r4,r4,exc_exit_restart@l - cmplw r12,r4 - blt 3f - lis r3,fee_restarts@ha - tophys(r3,r3) - lwz r5,fee_restarts@l(r3) - addi r5,r5,1 - stw r5,fee_restarts@l(r3) - mr r12,r4 /* restart at exc_exit_restart */ - b 2b - - .section .bss - .align 2 -fee_restarts: - .space 4 - .previous - -/* aargh, a nonrecoverable interrupt, panic */ -/* aargh, we don't know which trap this is */ -/* but the 601 doesn't implement the RI bit, so assume it's OK */ -3: -BEGIN_FTR_SECTION - b 2b -END_FTR_SECTION_IFSET(CPU_FTR_601) - li r10,-1 - stw r10,TRAP(r11) - addi r3,r1,STACK_FRAME_OVERHEAD - lis r10,MSR_KERNEL@h - ori r10,r10,MSR_KERNEL@l - bl transfer_to_handler_full - .long nonrecoverable_exception - .long ret_from_except -#endif - - .globl ret_from_except_full -ret_from_except_full: - REST_NVGPRS(r1) - /* fall through */ - - .globl ret_from_except -ret_from_except: - /* Hard-disable interrupts so that current_thread_info()->flags - * can't change between when we test it and when we return - * from the interrupt. */ - LOAD_MSR_KERNEL(r10,MSR_KERNEL) - SYNC /* Some chip revs have problems here... */ - MTMSRD(r10) /* disable interrupts */ - - lwz r3,_MSR(r1) /* Returning to user mode? */ - andi. r0,r3,MSR_PR - beq resume_kernel - -user_exc_return: /* r10 contains MSR_KERNEL here */ - /* Check current_thread_info()->flags */ - rlwinm r9,r1,0,0,18 - lwz r9,TI_FLAGS(r9) - andi. r0,r9,_TIF_USER_WORK_MASK - bne do_work - -restore_user: -#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) - /* Check whether this process has its own DBCR0 value. The single - step bit tells us that dbcr0 should be loaded. */ - lwz r0,THREAD+THREAD_DBCR0(r2) - andis. r10,r0,DBCR0_IC@h - bnel- load_dbcr0 -#endif - -#ifdef CONFIG_PREEMPT - b restore - -/* N.B. the only way to get here is from the beq following ret_from_except. */ -resume_kernel: - /* check current_thread_info->preempt_count */ - rlwinm r9,r1,0,0,18 - lwz r0,TI_PREEMPT(r9) - cmpwi 0,r0,0 /* if non-zero, just restore regs and return */ - bne restore - lwz r0,TI_FLAGS(r9) - andi. r0,r0,_TIF_NEED_RESCHED - beq+ restore - andi. r0,r3,MSR_EE /* interrupts off? */ - beq restore /* don't schedule if so */ -1: bl preempt_schedule_irq - rlwinm r9,r1,0,0,18 - lwz r3,TI_FLAGS(r9) - andi. r0,r3,_TIF_NEED_RESCHED - bne- 1b -#else -resume_kernel: -#endif /* CONFIG_PREEMPT */ - - /* interrupts are hard-disabled at this point */ -restore: -#ifdef CONFIG_44x - lis r4,icache_44x_need_flush@ha - lwz r5,icache_44x_need_flush@l(r4) - cmplwi cr0,r5,0 - beq+ 1f - li r6,0 - iccci r0,r0 - stw r6,icache_44x_need_flush@l(r4) -1: -#endif /* CONFIG_44x */ - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - REST_4GPRS(3, r1) - REST_2GPRS(7, r1) - - lwz r10,_XER(r1) - lwz r11,_CTR(r1) - mtspr SPRN_XER,r10 - mtctr r11 - - PPC405_ERR77(0,r1) -BEGIN_FTR_SECTION - lwarx r11,0,r1 -END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) - stwcx. r0,0,r1 /* to clear the reservation */ - -#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) - lwz r9,_MSR(r1) - andi. r10,r9,MSR_RI /* check if this exception occurred */ - beql nonrecoverable /* at a bad place (MSR:RI = 0) */ - - lwz r10,_CCR(r1) - lwz r11,_LINK(r1) - mtcrf 0xFF,r10 - mtlr r11 - - /* - * Once we put values in SRR0 and SRR1, we are in a state - * where exceptions are not recoverable, since taking an - * exception will trash SRR0 and SRR1. Therefore we clear the - * MSR:RI bit to indicate this. If we do take an exception, - * we can't return to the point of the exception but we - * can restart the exception exit path at the label - * exc_exit_restart below. -- paulus - */ - LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI) - SYNC - MTMSRD(r10) /* clear the RI bit */ - .globl exc_exit_restart -exc_exit_restart: - lwz r9,_MSR(r1) - lwz r12,_NIP(r1) - FIX_SRR1(r9,r10) - mtspr SPRN_SRR0,r12 - mtspr SPRN_SRR1,r9 - REST_4GPRS(9, r1) - lwz r1,GPR1(r1) - .globl exc_exit_restart_end -exc_exit_restart_end: - SYNC - RFI - -#else /* !(CONFIG_4xx || CONFIG_BOOKE) */ - /* - * This is a bit different on 4xx/Book-E because it doesn't have - * the RI bit in the MSR. - * The TLB miss handler checks if we have interrupted - * the exception exit path and restarts it if so - * (well maybe one day it will... :). - */ - lwz r11,_LINK(r1) - mtlr r11 - lwz r10,_CCR(r1) - mtcrf 0xff,r10 - REST_2GPRS(9, r1) - .globl exc_exit_restart -exc_exit_restart: - lwz r11,_NIP(r1) - lwz r12,_MSR(r1) -exc_exit_start: - mtspr SPRN_SRR0,r11 - mtspr SPRN_SRR1,r12 - REST_2GPRS(11, r1) - lwz r1,GPR1(r1) - .globl exc_exit_restart_end -exc_exit_restart_end: - PPC405_ERR77_SYNC - rfi - b . /* prevent prefetch past rfi */ - -/* - * Returning from a critical interrupt in user mode doesn't need - * to be any different from a normal exception. For a critical - * interrupt in the kernel, we just return (without checking for - * preemption) since the interrupt may have happened at some crucial - * place (e.g. inside the TLB miss handler), and because we will be - * running with r1 pointing into critical_stack, not the current - * process's kernel stack (and therefore current_thread_info() will - * give the wrong answer). - * We have to restore various SPRs that may have been in use at the - * time of the critical interrupt. - * - */ -#ifdef CONFIG_40x -#define PPC_40x_TURN_OFF_MSR_DR \ - /* avoid any possible TLB misses here by turning off MSR.DR, we \ - * assume the instructions here are mapped by a pinned TLB entry */ \ - li r10,MSR_IR; \ - mtmsr r10; \ - isync; \ - tophys(r1, r1); -#else -#define PPC_40x_TURN_OFF_MSR_DR -#endif - -#define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \ - REST_NVGPRS(r1); \ - lwz r3,_MSR(r1); \ - andi. r3,r3,MSR_PR; \ - LOAD_MSR_KERNEL(r10,MSR_KERNEL); \ - bne user_exc_return; \ - lwz r0,GPR0(r1); \ - lwz r2,GPR2(r1); \ - REST_4GPRS(3, r1); \ - REST_2GPRS(7, r1); \ - lwz r10,_XER(r1); \ - lwz r11,_CTR(r1); \ - mtspr SPRN_XER,r10; \ - mtctr r11; \ - PPC405_ERR77(0,r1); \ - stwcx. r0,0,r1; /* to clear the reservation */ \ - lwz r11,_LINK(r1); \ - mtlr r11; \ - lwz r10,_CCR(r1); \ - mtcrf 0xff,r10; \ - PPC_40x_TURN_OFF_MSR_DR; \ - lwz r9,_DEAR(r1); \ - lwz r10,_ESR(r1); \ - mtspr SPRN_DEAR,r9; \ - mtspr SPRN_ESR,r10; \ - lwz r11,_NIP(r1); \ - lwz r12,_MSR(r1); \ - mtspr exc_lvl_srr0,r11; \ - mtspr exc_lvl_srr1,r12; \ - lwz r9,GPR9(r1); \ - lwz r12,GPR12(r1); \ - lwz r10,GPR10(r1); \ - lwz r11,GPR11(r1); \ - lwz r1,GPR1(r1); \ - PPC405_ERR77_SYNC; \ - exc_lvl_rfi; \ - b .; /* prevent prefetch past exc_lvl_rfi */ - - .globl ret_from_crit_exc -ret_from_crit_exc: - RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI) - -#ifdef CONFIG_BOOKE - .globl ret_from_debug_exc -ret_from_debug_exc: - RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, RFDI) - - .globl ret_from_mcheck_exc -ret_from_mcheck_exc: - RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, RFMCI) -#endif /* CONFIG_BOOKE */ - -/* - * Load the DBCR0 value for a task that is being ptraced, - * having first saved away the global DBCR0. Note that r0 - * has the dbcr0 value to set upon entry to this. - */ -load_dbcr0: - mfmsr r10 /* first disable debug exceptions */ - rlwinm r10,r10,0,~MSR_DE - mtmsr r10 - isync - mfspr r10,SPRN_DBCR0 - lis r11,global_dbcr0@ha - addi r11,r11,global_dbcr0@l - stw r10,0(r11) - mtspr SPRN_DBCR0,r0 - lwz r10,4(r11) - addi r10,r10,1 - stw r10,4(r11) - li r11,-1 - mtspr SPRN_DBSR,r11 /* clear all pending debug events */ - blr - - .section .bss - .align 4 -global_dbcr0: - .space 8 - .previous -#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */ - -do_work: /* r10 contains MSR_KERNEL here */ - andi. r0,r9,_TIF_NEED_RESCHED - beq do_user_signal - -do_resched: /* r10 contains MSR_KERNEL here */ - ori r10,r10,MSR_EE - SYNC - MTMSRD(r10) /* hard-enable interrupts */ - bl schedule -recheck: - LOAD_MSR_KERNEL(r10,MSR_KERNEL) - SYNC - MTMSRD(r10) /* disable interrupts */ - rlwinm r9,r1,0,0,18 - lwz r9,TI_FLAGS(r9) - andi. r0,r9,_TIF_NEED_RESCHED - bne- do_resched - andi. r0,r9,_TIF_USER_WORK_MASK - beq restore_user -do_user_signal: /* r10 contains MSR_KERNEL here */ - ori r10,r10,MSR_EE - SYNC - MTMSRD(r10) /* hard-enable interrupts */ - /* save r13-r31 in the exception frame, if not already done */ - lwz r3,TRAP(r1) - andi. r0,r3,1 - beq 2f - SAVE_NVGPRS(r1) - rlwinm r3,r3,0,0,30 - stw r3,TRAP(r1) -2: li r3,0 - addi r4,r1,STACK_FRAME_OVERHEAD - bl do_signal - REST_NVGPRS(r1) - b recheck - -/* - * We come here when we are at the end of handling an exception - * that occurred at a place where taking an exception will lose - * state information, such as the contents of SRR0 and SRR1. - */ -nonrecoverable: - lis r10,exc_exit_restart_end@ha - addi r10,r10,exc_exit_restart_end@l - cmplw r12,r10 - bge 3f - lis r11,exc_exit_restart@ha - addi r11,r11,exc_exit_restart@l - cmplw r12,r11 - blt 3f - lis r10,ee_restarts@ha - lwz r12,ee_restarts@l(r10) - addi r12,r12,1 - stw r12,ee_restarts@l(r10) - mr r12,r11 /* restart at exc_exit_restart */ - blr -3: /* OK, we can't recover, kill this process */ - /* but the 601 doesn't implement the RI bit, so assume it's OK */ -BEGIN_FTR_SECTION - blr -END_FTR_SECTION_IFSET(CPU_FTR_601) - lwz r3,TRAP(r1) - andi. r0,r3,1 - beq 4f - SAVE_NVGPRS(r1) - rlwinm r3,r3,0,0,30 - stw r3,TRAP(r1) -4: addi r3,r1,STACK_FRAME_OVERHEAD - bl nonrecoverable_exception - /* shouldn't return */ - b 4b - - .section .bss - .align 2 -ee_restarts: - .space 4 - .previous diff --git a/arch/ppc/kernel/head.S b/arch/ppc/kernel/head.S deleted file mode 100644 index e7e642b95138..000000000000 --- a/arch/ppc/kernel/head.S +++ /dev/null @@ -1,1220 +0,0 @@ -/* - * PowerPC version - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP - * Copyright (C) 1996 Cort Dougan - * Adapted for Power Macintosh by Paul Mackerras. - * Low-level exception handlers and MMU support - * rewritten by Paul Mackerras. - * Copyright (C) 1996 Paul Mackerras. - * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). - * - * This file contains the low-level support and setup for the - * PowerPC platform, including trap and interrupt dispatch. - * (The PPC 8xx embedded CPUs use head_8xx.S instead.) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ -#define LOAD_BAT(n, reg, RA, RB) \ - /* see the comment for clear_bats() -- Cort */ \ - li RA,0; \ - mtspr SPRN_IBAT##n##U,RA; \ - mtspr SPRN_DBAT##n##U,RA; \ - lwz RA,(n*16)+0(reg); \ - lwz RB,(n*16)+4(reg); \ - mtspr SPRN_IBAT##n##U,RA; \ - mtspr SPRN_IBAT##n##L,RB; \ - beq 1f; \ - lwz RA,(n*16)+8(reg); \ - lwz RB,(n*16)+12(reg); \ - mtspr SPRN_DBAT##n##U,RA; \ - mtspr SPRN_DBAT##n##L,RB; \ -1: - - .text - .stabs "arch/ppc/kernel/",N_SO,0,0,0f - .stabs "head.S",N_SO,0,0,0f -0: - .globl _stext -_stext: - -/* - * _start is defined this way because the XCOFF loader in the OpenFirmware - * on the powermac expects the entry point to be a procedure descriptor. - */ - .text - .globl _start -_start: - /* - * These are here for legacy reasons, the kernel used to - * need to look like a coff function entry for the pmac - * but we're always started by some kind of bootloader now. - * -- Cort - */ - nop /* used by __secondary_hold on prep (mtx) and chrp smp */ - nop /* used by __secondary_hold on prep (mtx) and chrp smp */ - nop - -/* PMAC - * Enter here with the kernel text, data and bss loaded starting at - * 0, running with virtual == physical mapping. - * r5 points to the prom entry point (the client interface handler - * address). Address translation is turned on, with the prom - * managing the hash table. Interrupts are disabled. The stack - * pointer (r1) points to just below the end of the half-meg region - * from 0x380000 - 0x400000, which is mapped in already. - * - * If we are booted from MacOS via BootX, we enter with the kernel - * image loaded somewhere, and the following values in registers: - * r3: 'BooX' (0x426f6f58) - * r4: virtual address of boot_infos_t - * r5: 0 - * - * APUS - * r3: 'APUS' - * r4: physical address of memory base - * Linux/m68k style BootInfo structure at &_end. - * - * PREP - * This is jumped to on prep systems right after the kernel is relocated - * to its proper place in memory by the boot loader. The expected layout - * of the regs is: - * r3: ptr to residual data - * r4: initrd_start or if no initrd then 0 - * r5: initrd_end - unused if r4 is 0 - * r6: Start of command line string - * r7: End of command line string - * - * This just gets a minimal mmu environment setup so we can call - * start_here() to do the real work. - * -- Cort - */ - - .globl __start -__start: - mr r31,r3 /* save parameters */ - mr r30,r4 - mr r29,r5 - mr r28,r6 - mr r27,r7 - li r24,0 /* cpu # */ - -/* - * early_init() does the early machine identification and does - * the necessary low-level setup and clears the BSS - * -- Cort - */ - bl early_init - -/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains - * the physical address we are running at, returned by early_init() - */ - bl mmu_off -__after_mmu_off: - bl clear_bats - bl flush_tlbs - - bl initial_bats -#ifdef CONFIG_BOOTX_TEXT - bl setup_disp_bat -#endif - -/* - * Call setup_cpu for CPU 0 and initialize 6xx Idle - */ - bl reloc_offset - li r24,0 /* cpu# */ - bl call_setup_cpu /* Call setup_cpu for this CPU */ -#ifdef CONFIG_6xx - bl reloc_offset - bl init_idle_6xx -#endif /* CONFIG_6xx */ - - -/* - * We need to run with _start at physical address 0. - * If the MMU is already turned on, we copy stuff to KERNELBASE, - * otherwise we copy it to 0. - */ - bl reloc_offset - mr r26,r3 - addis r4,r3,KERNELBASE@h /* current address of _start */ - cmpwi 0,r4,0 /* are we already running at 0? */ - bne relocate_kernel - -/* - * we now have the 1st 16M of ram mapped with the bats. - * prep needs the mmu to be turned on here, but pmac already has it on. - * this shouldn't bother the pmac since it just gets turned on again - * as we jump to our code at KERNELBASE. -- Cort - * Actually no, pmac doesn't have it on any more. BootX enters with MMU - * off, and in other cases, we now turn it off before changing BATs above. - */ -turn_on_mmu: - mfmsr r0 - ori r0,r0,MSR_DR|MSR_IR - mtspr SPRN_SRR1,r0 - lis r0,start_here@h - ori r0,r0,start_here@l - mtspr SPRN_SRR0,r0 - SYNC - RFI /* enables MMU */ - -/* - * We need __secondary_hold as a place to hold the other cpus on - * an SMP machine, even when we are running a UP kernel. - */ - . = 0xc0 /* for prep bootloader */ - li r3,1 /* MTX only has 1 cpu */ - .globl __secondary_hold -__secondary_hold: - /* tell the master we're here */ - stw r3,4(0) -#ifdef CONFIG_SMP -100: lwz r4,0(0) - /* wait until we're told to start */ - cmpw 0,r4,r3 - bne 100b - /* our cpu # was at addr 0 - go */ - mr r24,r3 /* cpu # */ - b __secondary_start -#else - b . -#endif /* CONFIG_SMP */ - -/* - * Exception entry code. This code runs with address translation - * turned off, i.e. using physical addresses. - * We assume sprg3 has the physical address of the current - * task's thread_struct. - */ -#define EXCEPTION_PROLOG \ - mtspr SPRN_SPRG0,r10; \ - mtspr SPRN_SPRG1,r11; \ - mfcr r10; \ - EXCEPTION_PROLOG_1; \ - EXCEPTION_PROLOG_2 - -#define EXCEPTION_PROLOG_1 \ - mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ - andi. r11,r11,MSR_PR; \ - tophys(r11,r1); /* use tophys(r1) if kernel */ \ - beq 1f; \ - mfspr r11,SPRN_SPRG3; \ - lwz r11,THREAD_INFO-THREAD(r11); \ - addi r11,r11,THREAD_SIZE; \ - tophys(r11,r11); \ -1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ - - -#define EXCEPTION_PROLOG_2 \ - CLR_TOP32(r11); \ - stw r10,_CCR(r11); /* save registers */ \ - stw r12,GPR12(r11); \ - stw r9,GPR9(r11); \ - mfspr r10,SPRN_SPRG0; \ - stw r10,GPR10(r11); \ - mfspr r12,SPRN_SPRG1; \ - stw r12,GPR11(r11); \ - mflr r10; \ - stw r10,_LINK(r11); \ - mfspr r12,SPRN_SRR0; \ - mfspr r9,SPRN_SRR1; \ - stw r1,GPR1(r11); \ - stw r1,0(r11); \ - tovirt(r1,r11); /* set new kernel sp */ \ - li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ - MTMSRD(r10); /* (except for mach check in rtas) */ \ - stw r0,GPR0(r11); \ - SAVE_4GPRS(3, r11); \ - SAVE_2GPRS(7, r11) - -/* - * Note: code which follows this uses cr0.eq (set if from kernel), - * r11, r12 (SRR0), and r9 (SRR1). - * - * Note2: once we have set r1 we are in a position to take exceptions - * again, and we could thus set MSR:RI at that point. - */ - -/* - * Exception vectors. - */ -#define EXCEPTION(n, label, hdlr, xfer) \ - . = n; \ -label: \ - EXCEPTION_PROLOG; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - xfer(n, hdlr) - -#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ - li r10,trap; \ - stw r10,TRAP(r11); \ - li r10,MSR_KERNEL; \ - copyee(r10, r9); \ - bl tfer; \ -i##n: \ - .long hdlr; \ - .long ret - -#define COPY_EE(d, s) rlwimi d,s,0,16,16 -#define NOCOPY(d, s) - -#define EXC_XFER_STD(n, hdlr) \ - EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ - ret_from_except) - -#define EXC_XFER_EE(n, hdlr) \ - EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_EE_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ - ret_from_except) - -/* System reset */ -/* core99 pmac starts the seconary here by changing the vector, and - putting it back to what it was (unknown_exception) when done. */ - EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) - -/* Machine check */ - . = 0x200 - mtspr SPRN_SPRG0,r10 - mtspr SPRN_SPRG1,r11 - mfcr r10 - EXCEPTION_PROLOG_1 -7: EXCEPTION_PROLOG_2 - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_STD(0x200, machine_check_exception) - -/* Data access exception. */ - . = 0x300 -DataAccess: - EXCEPTION_PROLOG - mfspr r10,SPRN_DSISR - andis. r0,r10,0xa470 /* weird error? */ - bne 1f /* if not, try to put a PTE */ - mfspr r4,SPRN_DAR /* into the hash table */ - rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */ - bl hash_page -1: stw r10,_DSISR(r11) - mr r5,r10 - mfspr r4,SPRN_DAR - EXC_XFER_EE_LITE(0x300, handle_page_fault) - -/* Instruction access exception. */ - . = 0x400 -InstructionAccess: - EXCEPTION_PROLOG - andis. r0,r9,0x4000 /* no pte found? */ - beq 1f /* if so, try to put a PTE */ - li r3,0 /* into the hash table */ - mr r4,r12 /* SRR0 is fault address */ - bl hash_page -1: mr r4,r12 - mr r5,r9 - EXC_XFER_EE_LITE(0x400, handle_page_fault) - -/* External interrupt */ - EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) - -/* Alignment exception */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,SPRN_DAR - stw r4,_DAR(r11) - mfspr r5,SPRN_DSISR - stw r5,_DSISR(r11) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_EE(0x600, alignment_exception) - -/* Program check exception */ - EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) - -/* Floating-point unavailable */ - . = 0x800 -FPUnavailable: - EXCEPTION_PROLOG - bne load_up_fpu /* if from user, just load it up */ - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) - -/* Decrementer */ - EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) - - EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) - EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) - -/* System call */ - . = 0xc00 -SystemCall: - EXCEPTION_PROLOG - EXC_XFER_EE_LITE(0xc00, DoSyscall) - -/* Single step - not used on 601 */ - EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) - EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) - -/* - * The Altivec unavailable trap is at 0x0f20. Foo. - * We effectively remap it to 0x3000. - * We include an altivec unavailable exception vector even if - * not configured for Altivec, so that you can't panic a - * non-altivec kernel running on a machine with altivec just - * by executing an altivec instruction. - */ - . = 0xf00 - b Trap_0f - - . = 0xf20 - b AltiVecUnavailable - -Trap_0f: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_EE(0xf00, unknown_exception) - -/* - * Handle TLB miss for instruction on 603/603e. - * Note: we get an alternate set of r0 - r3 to use automatically. - */ - . = 0x1000 -InstructionTLBMiss: -/* - * r0: stored ctr - * r1: linux style pte ( later becomes ppc hardware pte ) - * r2: ptr to linux-style pte - * r3: scratch - */ - mfctr r0 - /* Get PTE (linux-style) and check access */ - mfspr r3,SPRN_IMISS - lis r1,KERNELBASE@h /* check if kernel address */ - cmplw 0,r3,r1 - mfspr r2,SPRN_SPRG3 - li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ - lwz r2,PGDIR(r2) - blt+ 112f - lis r2,swapper_pg_dir@ha /* if kernel address, use */ - addi r2,r2,swapper_pg_dir@l /* kernel page table */ - mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ - rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ -112: tophys(r2,r2) - rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ - lwz r2,0(r2) /* get pmd entry */ - rlwinm. r2,r2,0,0,19 /* extract address of pte page */ - beq- InstructionAddressInvalid /* return if no mapping */ - rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ - lwz r3,0(r2) /* get linux-style pte */ - andc. r1,r1,r3 /* check access & ~permission */ - bne- InstructionAddressInvalid /* return if access not permitted */ - ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ - /* - * NOTE! We are assuming this is not an SMP system, otherwise - * we would need to update the pte atomically with lwarx/stwcx. - */ - stw r3,0(r2) /* update PTE (accessed bit) */ - /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ - rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ - and r1,r1,r2 /* writable if _RW and _DIRTY */ - rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ - rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ - ori r1,r1,0xe14 /* clear out reserved bits and M */ - andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ - mtspr SPRN_RPA,r1 - mfspr r3,SPRN_IMISS - tlbli r3 - mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ - mtcrf 0x80,r3 - rfi -InstructionAddressInvalid: - mfspr r3,SPRN_SRR1 - rlwinm r1,r3,9,6,6 /* Get load/store bit */ - - addis r1,r1,0x2000 - mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */ - mtctr r0 /* Restore CTR */ - andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ - or r2,r2,r1 - mtspr SPRN_SRR1,r2 - mfspr r1,SPRN_IMISS /* Get failing address */ - rlwinm. r2,r2,0,31,31 /* Check for little endian access */ - rlwimi r2,r2,1,30,30 /* change 1 -> 3 */ - xor r1,r1,r2 - mtspr SPRN_DAR,r1 /* Set fault address */ - mfmsr r0 /* Restore "normal" registers */ - xoris r0,r0,MSR_TGPR>>16 - mtcrf 0x80,r3 /* Restore CR0 */ - mtmsr r0 - b InstructionAccess - -/* - * Handle TLB miss for DATA Load operation on 603/603e - */ - . = 0x1100 -DataLoadTLBMiss: -/* - * r0: stored ctr - * r1: linux style pte ( later becomes ppc hardware pte ) - * r2: ptr to linux-style pte - * r3: scratch - */ - mfctr r0 - /* Get PTE (linux-style) and check access */ - mfspr r3,SPRN_DMISS - lis r1,KERNELBASE@h /* check if kernel address */ - cmplw 0,r3,r1 - mfspr r2,SPRN_SPRG3 - li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ - lwz r2,PGDIR(r2) - blt+ 112f - lis r2,swapper_pg_dir@ha /* if kernel address, use */ - addi r2,r2,swapper_pg_dir@l /* kernel page table */ - mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ - rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ -112: tophys(r2,r2) - rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ - lwz r2,0(r2) /* get pmd entry */ - rlwinm. r2,r2,0,0,19 /* extract address of pte page */ - beq- DataAddressInvalid /* return if no mapping */ - rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ - lwz r3,0(r2) /* get linux-style pte */ - andc. r1,r1,r3 /* check access & ~permission */ - bne- DataAddressInvalid /* return if access not permitted */ - ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ - /* - * NOTE! We are assuming this is not an SMP system, otherwise - * we would need to update the pte atomically with lwarx/stwcx. - */ - stw r3,0(r2) /* update PTE (accessed bit) */ - /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ - rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ - and r1,r1,r2 /* writable if _RW and _DIRTY */ - rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ - rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ - ori r1,r1,0xe14 /* clear out reserved bits and M */ - andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ - mtspr SPRN_RPA,r1 - mfspr r3,SPRN_DMISS - tlbld r3 - mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ - mtcrf 0x80,r3 - rfi -DataAddressInvalid: - mfspr r3,SPRN_SRR1 - rlwinm r1,r3,9,6,6 /* Get load/store bit */ - addis r1,r1,0x2000 - mtspr SPRN_DSISR,r1 - mtctr r0 /* Restore CTR */ - andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ - mtspr SPRN_SRR1,r2 - mfspr r1,SPRN_DMISS /* Get failing address */ - rlwinm. r2,r2,0,31,31 /* Check for little endian access */ - beq 20f /* Jump if big endian */ - xori r1,r1,3 -20: mtspr SPRN_DAR,r1 /* Set fault address */ - mfmsr r0 /* Restore "normal" registers */ - xoris r0,r0,MSR_TGPR>>16 - mtcrf 0x80,r3 /* Restore CR0 */ - mtmsr r0 - b DataAccess - -/* - * Handle TLB miss for DATA Store on 603/603e - */ - . = 0x1200 -DataStoreTLBMiss: -/* - * r0: stored ctr - * r1: linux style pte ( later becomes ppc hardware pte ) - * r2: ptr to linux-style pte - * r3: scratch - */ - mfctr r0 - /* Get PTE (linux-style) and check access */ - mfspr r3,SPRN_DMISS - lis r1,KERNELBASE@h /* check if kernel address */ - cmplw 0,r3,r1 - mfspr r2,SPRN_SPRG3 - li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */ - lwz r2,PGDIR(r2) - blt+ 112f - lis r2,swapper_pg_dir@ha /* if kernel address, use */ - addi r2,r2,swapper_pg_dir@l /* kernel page table */ - mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ - rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ -112: tophys(r2,r2) - rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ - lwz r2,0(r2) /* get pmd entry */ - rlwinm. r2,r2,0,0,19 /* extract address of pte page */ - beq- DataAddressInvalid /* return if no mapping */ - rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ - lwz r3,0(r2) /* get linux-style pte */ - andc. r1,r1,r3 /* check access & ~permission */ - bne- DataAddressInvalid /* return if access not permitted */ - ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY - /* - * NOTE! We are assuming this is not an SMP system, otherwise - * we would need to update the pte atomically with lwarx/stwcx. - */ - stw r3,0(r2) /* update PTE (accessed/dirty bits) */ - /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ - li r1,0xe15 /* clear out reserved bits and M */ - andc r1,r3,r1 /* PP = user? 2: 0 */ - mtspr SPRN_RPA,r1 - mfspr r3,SPRN_DMISS - tlbld r3 - mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ - mtcrf 0x80,r3 - rfi - -#ifndef CONFIG_ALTIVEC -#define altivec_assist_exception unknown_exception -#endif - - EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE) - EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE) - EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE) - EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD) - EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE) - EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE) - - .globl mol_trampoline - .set mol_trampoline, i0x2f00 - - . = 0x3000 - -AltiVecUnavailable: - EXCEPTION_PROLOG -#ifdef CONFIG_ALTIVEC - bne load_up_altivec /* if from user, just load it up */ -#endif /* CONFIG_ALTIVEC */ - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception) - -#ifdef CONFIG_ALTIVEC -/* Note that the AltiVec support is closely modeled after the FP - * support. Changes to one are likely to be applicable to the - * other! */ -load_up_altivec: -/* - * Disable AltiVec for the task which had AltiVec previously, - * and save its AltiVec registers in its thread_struct. - * Enables AltiVec for use in the kernel on return. - * On SMP we know the AltiVec units are free, since we give it up every - * switch. -- Kumar - */ - mfmsr r5 - oris r5,r5,MSR_VEC@h - MTMSRD(r5) /* enable use of AltiVec now */ - isync -/* - * For SMP, we don't do lazy AltiVec switching because it just gets too - * horrendously complex, especially when a task switches from one CPU - * to another. Instead we call giveup_altivec in switch_to. - */ -#ifndef CONFIG_SMP - tophys(r6,0) - addis r3,r6,last_task_used_altivec@ha - lwz r4,last_task_used_altivec@l(r3) - cmpwi 0,r4,0 - beq 1f - add r4,r4,r6 - addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */ - SAVE_32VRS(0,r10,r4) - mfvscr vr0 - li r10,THREAD_VSCR - stvx vr0,r10,r4 - lwz r5,PT_REGS(r4) - add r5,r5,r6 - lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) - lis r10,MSR_VEC@h - andc r4,r4,r10 /* disable altivec for previous task */ - stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) -1: -#endif /* CONFIG_SMP */ - /* enable use of AltiVec after return */ - oris r9,r9,MSR_VEC@h - mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ - li r4,1 - li r10,THREAD_VSCR - stw r4,THREAD_USED_VR(r5) - lvx vr0,r10,r5 - mtvscr vr0 - REST_32VRS(0,r10,r5) -#ifndef CONFIG_SMP - subi r4,r5,THREAD - sub r4,r4,r6 - stw r4,last_task_used_altivec@l(r3) -#endif /* CONFIG_SMP */ - /* restore registers and return */ - /* we haven't used ctr or xer or lr */ - b fast_exception_return - -/* - * giveup_altivec(tsk) - * Disable AltiVec for the task given as the argument, - * and save the AltiVec registers in its thread_struct. - * Enables AltiVec for use in the kernel on return. - */ - - .globl giveup_altivec -giveup_altivec: - mfmsr r5 - oris r5,r5,MSR_VEC@h - SYNC - MTMSRD(r5) /* enable use of AltiVec now */ - isync - cmpwi 0,r3,0 - beqlr- /* if no previous owner, done */ - addi r3,r3,THREAD /* want THREAD of task */ - lwz r5,PT_REGS(r3) - cmpwi 0,r5,0 - SAVE_32VRS(0, r4, r3) - mfvscr vr0 - li r4,THREAD_VSCR - stvx vr0,r4,r3 - beq 1f - lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) - lis r3,MSR_VEC@h - andc r4,r4,r3 /* disable AltiVec for previous task */ - stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) -1: -#ifndef CONFIG_SMP - li r5,0 - lis r4,last_task_used_altivec@ha - stw r5,last_task_used_altivec@l(r4) -#endif /* CONFIG_SMP */ - blr -#endif /* CONFIG_ALTIVEC */ - -/* - * This code is jumped to from the startup code to copy - * the kernel image to physical address 0. - */ -relocate_kernel: - addis r9,r26,klimit@ha /* fetch klimit */ - lwz r25,klimit@l(r9) - addis r25,r25,-KERNELBASE@h - li r3,0 /* Destination base address */ - li r6,0 /* Destination offset */ - li r5,0x4000 /* # bytes of memory to copy */ - bl copy_and_flush /* copy the first 0x4000 bytes */ - addi r0,r3,4f@l /* jump to the address of 4f */ - mtctr r0 /* in copy and do the rest. */ - bctr /* jump to the copy */ -4: mr r5,r25 - bl copy_and_flush /* copy the rest */ - b turn_on_mmu - -/* - * Copy routine used to copy the kernel to start at physical address 0 - * and flush and invalidate the caches as needed. - * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset - * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. - */ -copy_and_flush: - addi r5,r5,-4 - addi r6,r6,-4 -4: li r0,L1_CACHE_BYTES/4 - mtctr r0 -3: addi r6,r6,4 /* copy a cache line */ - lwzx r0,r6,r4 - stwx r0,r6,r3 - bdnz 3b - dcbst r6,r3 /* write it to memory */ - sync - icbi r6,r3 /* flush the icache line */ - cmplw 0,r6,r5 - blt 4b - sync /* additional sync needed on g4 */ - isync - addi r5,r5,4 - addi r6,r6,4 - blr - -#ifdef CONFIG_SMP - .globl __secondary_start_pmac_0 -__secondary_start_pmac_0: - /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ - li r24,0 - b 1f - li r24,1 - b 1f - li r24,2 - b 1f - li r24,3 -1: - /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0 - set to map the 0xf0000000 - 0xffffffff region */ - mfmsr r0 - rlwinm r0,r0,0,28,26 /* clear DR (0x10) */ - SYNC - mtmsr r0 - isync - - .globl __secondary_start -__secondary_start: - /* Copy some CPU settings from CPU 0 */ - bl __restore_cpu_setup - - lis r3,-KERNELBASE@h - mr r4,r24 - bl call_setup_cpu /* Call setup_cpu for this CPU */ -#ifdef CONFIG_6xx - lis r3,-KERNELBASE@h - bl init_idle_6xx -#endif /* CONFIG_6xx */ - - /* get current_thread_info and current */ - lis r1,secondary_ti@ha - tophys(r1,r1) - lwz r1,secondary_ti@l(r1) - tophys(r2,r1) - lwz r2,TI_TASK(r2) - - /* stack */ - addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD - li r0,0 - tophys(r3,r1) - stw r0,0(r3) - - /* load up the MMU */ - bl load_up_mmu - - /* ptr to phys current thread */ - tophys(r4,r2) - addi r4,r4,THREAD /* phys address of our thread_struct */ - CLR_TOP32(r4) - mtspr SPRN_SPRG3,r4 - li r3,0 - mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ - - /* enable MMU and jump to start_secondary */ - li r4,MSR_KERNEL - FIX_SRR1(r4,r5) - lis r3,start_secondary@h - ori r3,r3,start_secondary@l - mtspr SPRN_SRR0,r3 - mtspr SPRN_SRR1,r4 - SYNC - RFI -#endif /* CONFIG_SMP */ - -/* - * Those generic dummy functions are kept for CPUs not - * included in CONFIG_6xx - */ -#if !defined(CONFIG_6xx) -_GLOBAL(__save_cpu_setup) - blr -_GLOBAL(__restore_cpu_setup) - blr -#endif /* !defined(CONFIG_6xx) */ - - -/* - * Load stuff into the MMU. Intended to be called with - * IR=0 and DR=0. - */ -load_up_mmu: - sync /* Force all PTE updates to finish */ - isync - tlbia /* Clear all TLB entries */ - sync /* wait for tlbia/tlbie to finish */ - TLBSYNC /* ... on all CPUs */ - /* Load the SDR1 register (hash table base & size) */ - lis r6,_SDR1@ha - tophys(r6,r6) - lwz r6,_SDR1@l(r6) - mtspr SPRN_SDR1,r6 - li r0,16 /* load up segment register values */ - mtctr r0 /* for context 0 */ - lis r3,0x2000 /* Ku = 1, VSID = 0 */ - li r4,0 -3: mtsrin r3,r4 - addi r3,r3,0x111 /* increment VSID */ - addis r4,r4,0x1000 /* address of next segment */ - bdnz 3b - -/* Load the BAT registers with the values set up by MMU_init. - MMU_init takes care of whether we're on a 601 or not. */ - mfpvr r3 - srwi r3,r3,16 - cmpwi r3,1 - lis r3,BATS@ha - addi r3,r3,BATS@l - tophys(r3,r3) - LOAD_BAT(0,r3,r4,r5) - LOAD_BAT(1,r3,r4,r5) - LOAD_BAT(2,r3,r4,r5) - LOAD_BAT(3,r3,r4,r5) - - blr - -/* - * This is where the main kernel code starts. - */ -start_here: - /* ptr to current */ - lis r2,init_task@h - ori r2,r2,init_task@l - /* Set up for using our exception vectors */ - /* ptr to phys current thread */ - tophys(r4,r2) - addi r4,r4,THREAD /* init task's THREAD */ - CLR_TOP32(r4) - mtspr SPRN_SPRG3,r4 - li r3,0 - mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ - - /* stack */ - lis r1,init_thread_union@ha - addi r1,r1,init_thread_union@l - li r0,0 - stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) -/* - * Do early bootinfo parsing, platform-specific initialization, - * and set up the MMU. - */ - mr r3,r31 - mr r4,r30 - mr r5,r29 - mr r6,r28 - mr r7,r27 - bl machine_init - bl MMU_init - -/* - * Go back to running unmapped so we can load up new values - * for SDR1 (hash table pointer) and the segment registers - * and change to using our exception vectors. - */ - lis r4,2f@h - ori r4,r4,2f@l - tophys(r4,r4) - li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) - FIX_SRR1(r3,r5) - mtspr SPRN_SRR0,r4 - mtspr SPRN_SRR1,r3 - SYNC - RFI -/* Load up the kernel context */ -2: bl load_up_mmu - -#ifdef CONFIG_BDI_SWITCH - /* Add helper information for the Abatron bdiGDB debugger. - * We do this here because we know the mmu is disabled, and - * will be enabled for real in just a few instructions. - */ - lis r5, abatron_pteptrs@h - ori r5, r5, abatron_pteptrs@l - stw r5, 0xf0(r0) /* This much match your Abatron config */ - lis r6, swapper_pg_dir@h - ori r6, r6, swapper_pg_dir@l - tophys(r5, r5) - stw r6, 0(r5) -#endif /* CONFIG_BDI_SWITCH */ - -/* Now turn on the MMU for real! */ - li r4,MSR_KERNEL - FIX_SRR1(r4,r5) - lis r3,start_kernel@h - ori r3,r3,start_kernel@l - mtspr SPRN_SRR0,r3 - mtspr SPRN_SRR1,r4 - SYNC - RFI - -/* - * Set up the segment registers for a new context. - */ -_GLOBAL(set_context) - mulli r3,r3,897 /* multiply context by skew factor */ - rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ - addis r3,r3,0x6000 /* Set Ks, Ku bits */ - li r0,NUM_USER_SEGMENTS - mtctr r0 - -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is passed as second argument. - */ - lis r5, KERNELBASE@h - lwz r5, 0xf0(r5) - stw r4, 0x4(r5) -#endif - li r4,0 - isync -3: - mtsrin r3,r4 - addi r3,r3,0x111 /* next VSID */ - rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */ - addis r4,r4,0x1000 /* address of next segment */ - bdnz 3b - sync - isync - blr - -/* - * An undocumented "feature" of 604e requires that the v bit - * be cleared before changing BAT values. - * - * Also, newer IBM firmware does not clear bat3 and 4 so - * this makes sure it's done. - * -- Cort - */ -clear_bats: - li r10,0 - mfspr r9,SPRN_PVR - rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ - cmpwi r9, 1 - beq 1f - - mtspr SPRN_DBAT0U,r10 - mtspr SPRN_DBAT0L,r10 - mtspr SPRN_DBAT1U,r10 - mtspr SPRN_DBAT1L,r10 - mtspr SPRN_DBAT2U,r10 - mtspr SPRN_DBAT2L,r10 - mtspr SPRN_DBAT3U,r10 - mtspr SPRN_DBAT3L,r10 -1: - mtspr SPRN_IBAT0U,r10 - mtspr SPRN_IBAT0L,r10 - mtspr SPRN_IBAT1U,r10 - mtspr SPRN_IBAT1L,r10 - mtspr SPRN_IBAT2U,r10 - mtspr SPRN_IBAT2L,r10 - mtspr SPRN_IBAT3U,r10 - mtspr SPRN_IBAT3L,r10 -BEGIN_FTR_SECTION - /* Here's a tweak: at this point, CPU setup have - * not been called yet, so HIGH_BAT_EN may not be - * set in HID0 for the 745x processors. However, it - * seems that doesn't affect our ability to actually - * write to these SPRs. - */ - mtspr SPRN_DBAT4U,r10 - mtspr SPRN_DBAT4L,r10 - mtspr SPRN_DBAT5U,r10 - mtspr SPRN_DBAT5L,r10 - mtspr SPRN_DBAT6U,r10 - mtspr SPRN_DBAT6L,r10 - mtspr SPRN_DBAT7U,r10 - mtspr SPRN_DBAT7L,r10 - mtspr SPRN_IBAT4U,r10 - mtspr SPRN_IBAT4L,r10 - mtspr SPRN_IBAT5U,r10 - mtspr SPRN_IBAT5L,r10 - mtspr SPRN_IBAT6U,r10 - mtspr SPRN_IBAT6L,r10 - mtspr SPRN_IBAT7U,r10 - mtspr SPRN_IBAT7L,r10 -END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) - blr - -flush_tlbs: - lis r10, 0x40 -1: addic. r10, r10, -0x1000 - tlbie r10 - blt 1b - sync - blr - -mmu_off: - addi r4, r3, __after_mmu_off - _start - mfmsr r3 - andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */ - beqlr - andc r3,r3,r0 - mtspr SPRN_SRR0,r4 - mtspr SPRN_SRR1,r3 - sync - RFI - -/* - * Use the first pair of BAT registers to map the 1st 16MB - * of RAM to KERNELBASE. From this point on we can't safely - * call OF any more. - */ -initial_bats: - lis r11,KERNELBASE@h - mfspr r9,SPRN_PVR - rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ - cmpwi 0,r9,1 - bne 4f - ori r11,r11,4 /* set up BAT registers for 601 */ - li r8,0x7f /* valid, block length = 8MB */ - oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */ - oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */ - mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ - mtspr SPRN_IBAT0L,r8 /* lower BAT register */ - mtspr SPRN_IBAT1U,r9 - mtspr SPRN_IBAT1L,r10 - isync - blr - -4: tophys(r8,r11) -#ifdef CONFIG_SMP - ori r8,r8,0x12 /* R/W access, M=1 */ -#else - ori r8,r8,2 /* R/W access */ -#endif /* CONFIG_SMP */ - ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */ - - mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ - mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */ - mtspr SPRN_IBAT0L,r8 - mtspr SPRN_IBAT0U,r11 - isync - blr - -#ifdef CONFIG_BOOTX_TEXT -setup_disp_bat: - /* - * setup the display bat prepared for us in prom.c - */ - mflr r8 - bl reloc_offset - mtlr r8 - addis r8,r3,disp_BAT@ha - addi r8,r8,disp_BAT@l - lwz r11,0(r8) - lwz r8,4(r8) - mfspr r9,SPRN_PVR - rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ - cmpwi 0,r9,1 - beq 1f - mtspr SPRN_DBAT3L,r8 - mtspr SPRN_DBAT3U,r11 - blr -1: mtspr SPRN_IBAT3L,r8 - mtspr SPRN_IBAT3U,r11 - blr - -#endif /* defined(CONFIG_BOOTX_TEXT) */ - -#ifdef CONFIG_8260 -/* Jump into the system reset for the rom. - * We first disable the MMU, and then jump to the ROM reset address. - * - * r3 is the board info structure, r4 is the location for starting. - * I use this for building a small kernel that can load other kernels, - * rather than trying to write or rely on a rom monitor that can tftp load. - */ - .globl m8260_gorom -m8260_gorom: - mfmsr r0 - rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */ - sync - mtmsr r0 - sync - mfspr r11, SPRN_HID0 - lis r10, 0 - ori r10,r10,HID0_ICE|HID0_DCE - andc r11, r11, r10 - mtspr SPRN_HID0, r11 - isync - li r5, MSR_ME|MSR_RI - lis r6,2f@h - addis r6,r6,-KERNELBASE@h - ori r6,r6,2f@l - mtspr SPRN_SRR0,r6 - mtspr SPRN_SRR1,r5 - isync - sync - rfi -2: - mtlr r4 - blr -#endif - - -/* - * We put a few things here that have to be page-aligned. - * This stuff goes at the beginning of the data segment, - * which is page-aligned. - */ - .data - .globl sdata -sdata: - .globl empty_zero_page -empty_zero_page: - .space 4096 - - .globl swapper_pg_dir -swapper_pg_dir: - .space 4096 - -/* - * This space gets a copy of optional info passed to us by the bootstrap - * Used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space 512 - - .globl intercept_table -intercept_table: - .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700 - .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0 - .long 0, 0, 0, i0x1300, 0, 0, 0, 0 - .long 0, 0, 0, 0, 0, 0, 0, 0 - .long 0, 0, 0, 0, 0, 0, 0, 0 - .long 0, 0, 0, 0, 0, 0, 0, 0 - -/* Room for two PTE pointers, usually the kernel and current user pointers - * to their respective root page table. - */ -abatron_pteptrs: - .space 8 diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S deleted file mode 100644 index ebb5a403829f..000000000000 --- a/arch/ppc/kernel/head_44x.S +++ /dev/null @@ -1,769 +0,0 @@ -/* - * Kernel execution entry point code. - * - * Copyright (c) 1995-1996 Gary Thomas - * Initial PowerPC version. - * Copyright (c) 1996 Cort Dougan - * Rewritten for PReP - * Copyright (c) 1996 Paul Mackerras - * Low-level exception handers, MMU support, and rewrite. - * Copyright (c) 1997 Dan Malek - * PowerPC 8xx modifications. - * Copyright (c) 1998-1999 TiVo, Inc. - * PowerPC 403GCX modifications. - * Copyright (c) 1999 Grant Erickson - * PowerPC 403GCX/405GP modifications. - * Copyright 2000 MontaVista Software Inc. - * PPC405 modifications - * PowerPC 403GCX/405GP modifications. - * Author: MontaVista Software, Inc. - * frank_rowand@mvista.com or source@mvista.com - * debbie_chu@mvista.com - * Copyright 2002-2005 MontaVista Software, Inc. - * PowerPC 44x support, Matt Porter - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "head_booke.h" - - -/* As with the other PowerPC ports, it is expected that when code - * execution begins here, the following registers contain valid, yet - * optional, information: - * - * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) - * r4 - Starting address of the init RAM disk - * r5 - Ending address of the init RAM disk - * r6 - Start of kernel command line string (e.g. "mem=128") - * r7 - End of kernel command line string - * - */ - .text -_GLOBAL(_stext) -_GLOBAL(_start) - /* - * Reserve a word at a fixed location to store the address - * of abatron_pteptrs - */ - nop -/* - * Save parameters we are passed - */ - mr r31,r3 - mr r30,r4 - mr r29,r5 - mr r28,r6 - mr r27,r7 - li r24,0 /* CPU number */ - -/* - * Set up the initial MMU state - * - * We are still executing code at the virtual address - * mappings set by the firmware for the base of RAM. - * - * We first invalidate all TLB entries but the one - * we are running from. We then load the KERNELBASE - * mappings so we can begin to use kernel addresses - * natively and so the interrupt vector locations are - * permanently pinned (necessary since Book E - * implementations always have translation enabled). - * - * TODO: Use the known TLB entry we are running from to - * determine which physical region we are located - * in. This can be used to determine where in RAM - * (on a shared CPU system) or PCI memory space - * (on a DRAMless system) we are located. - * For now, we assume a perfect world which means - * we are located at the base of DRAM (physical 0). - */ - -/* - * Search TLB for entry that we are currently using. - * Invalidate all entries but the one we are using. - */ - /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ - mfspr r3,SPRN_PID /* Get PID */ - mfmsr r4 /* Get MSR */ - andi. r4,r4,MSR_IS@l /* TS=1? */ - beq wmmucr /* If not, leave STS=0 */ - oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */ -wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ - sync - - bl invstr /* Find our address */ -invstr: mflr r5 /* Make it accessible */ - tlbsx r23,0,r5 /* Find entry we are in */ - li r4,0 /* Start at TLB entry 0 */ - li r3,0 /* Set PAGEID inval value */ -1: cmpw r23,r4 /* Is this our entry? */ - beq skpinv /* If so, skip the inval */ - tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ -skpinv: addi r4,r4,1 /* Increment */ - cmpwi r4,64 /* Are we done? */ - bne 1b /* If not, repeat */ - isync /* If so, context change */ - -/* - * Configure and load pinned entry into TLB slot 63. - */ - - lis r3,KERNELBASE@h /* Load the kernel virtual address */ - ori r3,r3,KERNELBASE@l - - /* Kernel is at the base of RAM */ - li r4, 0 /* Load the kernel physical address */ - - /* Load the kernel PID = 0 */ - li r0,0 - mtspr SPRN_PID,r0 - sync - - /* Initialize MMUCR */ - li r5,0 - mtspr SPRN_MMUCR,r5 - sync - - /* pageid fields */ - clrrwi r3,r3,10 /* Mask off the effective page number */ - ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M - - /* xlat fields */ - clrrwi r4,r4,10 /* Mask off the real page number */ - /* ERPN is 0 for first 4GB page */ - - /* attrib fields */ - /* Added guarded bit to protect against speculative loads/stores */ - li r5,0 - ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) - - li r0,63 /* TLB slot 63 */ - - tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ - tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ - tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ - - /* Force context change */ - mfmsr r0 - mtspr SPRN_SRR1, r0 - lis r0,3f@h - ori r0,r0,3f@l - mtspr SPRN_SRR0,r0 - sync - rfi - - /* If necessary, invalidate original entry we used */ -3: cmpwi r23,63 - beq 4f - li r6,0 - tlbwe r6,r23,PPC44x_TLB_PAGEID - isync - -4: -#ifdef CONFIG_SERIAL_TEXT_DEBUG - /* - * Add temporary UART mapping for early debug. - * We can map UART registers wherever we want as long as they don't - * interfere with other system mappings (e.g. with pinned entries). - * For an example of how we handle this - see ocotea.h. --ebs - */ - /* pageid fields */ - lis r3,UART0_IO_BASE@h - ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_4K - - /* xlat fields */ - lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ -#ifdef UART0_PHYS_ERPN - ori r4,r4,UART0_PHYS_ERPN /* Add ERPN if above 4GB */ -#endif - - /* attrib fields */ - li r5,0 - ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G) - - li r0,62 /* TLB slot 62 */ - - tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ - tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ - tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ - - /* Force context change */ - isync -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ - - /* Establish the interrupt vector offsets */ - SET_IVOR(0, CriticalInput); - SET_IVOR(1, MachineCheck); - SET_IVOR(2, DataStorage); - SET_IVOR(3, InstructionStorage); - SET_IVOR(4, ExternalInput); - SET_IVOR(5, Alignment); - SET_IVOR(6, Program); - SET_IVOR(7, FloatingPointUnavailable); - SET_IVOR(8, SystemCall); - SET_IVOR(9, AuxillaryProcessorUnavailable); - SET_IVOR(10, Decrementer); - SET_IVOR(11, FixedIntervalTimer); - SET_IVOR(12, WatchdogTimer); - SET_IVOR(13, DataTLBError); - SET_IVOR(14, InstructionTLBError); - SET_IVOR(15, Debug); - - /* Establish the interrupt vector base */ - lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ - mtspr SPRN_IVPR,r4 - - /* - * This is where the main kernel code starts. - */ - - /* ptr to current */ - lis r2,init_task@h - ori r2,r2,init_task@l - - /* ptr to current thread */ - addi r4,r2,THREAD /* init task's THREAD */ - mtspr SPRN_SPRG3,r4 - - /* stack */ - lis r1,init_thread_union@h - ori r1,r1,init_thread_union@l - li r0,0 - stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) - - bl early_init - -/* - * Decide what sort of machine this is and initialize the MMU. - */ - mr r3,r31 - mr r4,r30 - mr r5,r29 - mr r6,r28 - mr r7,r27 - bl machine_init - bl MMU_init - - /* Setup PTE pointers for the Abatron bdiGDB */ - lis r6, swapper_pg_dir@h - ori r6, r6, swapper_pg_dir@l - lis r5, abatron_pteptrs@h - ori r5, r5, abatron_pteptrs@l - lis r4, KERNELBASE@h - ori r4, r4, KERNELBASE@l - stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ - stw r6, 0(r5) - - /* Let's move on */ - lis r4,start_kernel@h - ori r4,r4,start_kernel@l - lis r3,MSR_KERNEL@h - ori r3,r3,MSR_KERNEL@l - mtspr SPRN_SRR0,r4 - mtspr SPRN_SRR1,r3 - rfi /* change context and jump to start_kernel */ - -/* - * Interrupt vector entry code - * - * The Book E MMUs are always on so we don't need to handle - * interrupts in real mode as with previous PPC processors. In - * this case we handle interrupts in the kernel virtual address - * space. - * - * Interrupt vectors are dynamically placed relative to the - * interrupt prefix as determined by the address of interrupt_base. - * The interrupt vectors offsets are programmed using the labels - * for each interrupt vector entry. - * - * Interrupt vectors must be aligned on a 16 byte boundary. - * We align on a 32 byte cache line boundary for good measure. - */ - -interrupt_base: - /* Critical Input Interrupt */ - CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception) - - /* Machine Check Interrupt */ -#ifdef CONFIG_440A - MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) -#else - CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) -#endif - - /* Data Storage Interrupt */ - START_EXCEPTION(DataStorage) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 - mtspr SPRN_SPRG4W, r12 - mtspr SPRN_SPRG5W, r13 - mfcr r11 - mtspr SPRN_SPRG7W, r11 - - /* - * Check if it was a store fault, if not then bail - * because a user tried to access a kernel or - * read-protected page. Otherwise, get the - * offending address and handle it. - */ - mfspr r10, SPRN_ESR - andis. r10, r10, ESR_ST@h - beq 2f - - mfspr r10, SPRN_DEAR /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, TASK_SIZE@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - - mfspr r12,SPRN_MMUCR - rlwinm r12,r12,0,0,23 /* Clear TID */ - - b 4f - - /* Get the PGD for the current thread */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) - - /* Load PID into MMUCR TID */ - mfspr r12,SPRN_MMUCR /* Get MMUCR */ - mfspr r13,SPRN_PID /* Get PID */ - rlwimi r12,r13,0,24,31 /* Set TID */ - -4: - mtspr SPRN_MMUCR,r12 - - rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ - lwzx r11, r12, r11 /* Get pgd/pmd entry */ - rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ - lwz r11, 4(r12) /* Get pte entry */ - - andi. r13, r11, _PAGE_RW /* Is it writeable? */ - beq 2f /* Bail if not */ - - /* Update 'changed'. - */ - ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE - stw r11, 4(r12) /* Update Linux page table */ - - li r13, PPC44x_TLB_SR@l /* Set SR */ - rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */ - rlwimi r13, r11, 0, 30, 30 /* SW = _PAGE_RW */ - rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */ - rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */ - rlwimi r12, r11, 29, 30, 30 /* (_PAGE_USER>>3)->r12 */ - and r12, r12, r11 /* HWEXEC/RW & USER */ - rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */ - rlwimi r13, r12, 3, 27, 27 /* UW = RW & USER */ - - rlwimi r11,r13,0,26,31 /* Insert static perms */ - - rlwinm r11,r11,0,20,15 /* Clear U0-U3 */ - - /* find the TLB index that caused the fault. It has to be here. */ - tlbsx r10, 0, r10 - - tlbwe r11, r10, PPC44x_TLB_ATTRIB /* Write ATTRIB */ - - /* Done...restore registers and get out of here. - */ - mfspr r11, SPRN_SPRG7R - mtcr r11 - mfspr r13, SPRN_SPRG5R - mfspr r12, SPRN_SPRG4R - - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - rfi /* Force context change */ - -2: - /* - * The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ - mfspr r11, SPRN_SPRG7R - mtcr r11 - mfspr r13, SPRN_SPRG5R - mfspr r12, SPRN_SPRG4R - - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b data_access - - /* Instruction Storage Interrupt */ - INSTRUCTION_STORAGE_EXCEPTION - - /* External Input Interrupt */ - EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE) - - /* Alignment Interrupt */ - ALIGNMENT_EXCEPTION - - /* Program Interrupt */ - PROGRAM_EXCEPTION - - /* Floating Point Unavailable Interrupt */ -#ifdef CONFIG_PPC_FPU - FP_UNAVAILABLE_EXCEPTION -#else - EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) -#endif - - /* System Call Interrupt */ - START_EXCEPTION(SystemCall) - NORMAL_EXCEPTION_PROLOG - EXC_XFER_EE_LITE(0x0c00, DoSyscall) - - /* Auxillary Processor Unavailable Interrupt */ - EXCEPTION(0x2020, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) - - /* Decrementer Interrupt */ - DECREMENTER_EXCEPTION - - /* Fixed Internal Timer Interrupt */ - /* TODO: Add FIT support */ - EXCEPTION(0x1010, FixedIntervalTimer, unknown_exception, EXC_XFER_EE) - - /* Watchdog Timer Interrupt */ - /* TODO: Add watchdog support */ -#ifdef CONFIG_BOOKE_WDT - CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException) -#else - CRITICAL_EXCEPTION(0x1020, WatchdogTimer, unknown_exception) -#endif - - /* Data TLB Error Interrupt */ - START_EXCEPTION(DataTLBError) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 - mtspr SPRN_SPRG4W, r12 - mtspr SPRN_SPRG5W, r13 - mfcr r11 - mtspr SPRN_SPRG7W, r11 - mfspr r10, SPRN_DEAR /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, TASK_SIZE@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - - mfspr r12,SPRN_MMUCR - rlwinm r12,r12,0,0,23 /* Clear TID */ - - b 4f - - /* Get the PGD for the current thread */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) - - /* Load PID into MMUCR TID */ - mfspr r12,SPRN_MMUCR - mfspr r13,SPRN_PID /* Get PID */ - rlwimi r12,r13,0,24,31 /* Set TID */ - -4: - mtspr SPRN_MMUCR,r12 - - rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ - lwzx r11, r12, r11 /* Get pgd/pmd entry */ - rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ - lwz r11, 4(r12) /* Get pte entry */ - andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ - beq 2f /* Bail if not present */ - - ori r11, r11, _PAGE_ACCESSED - stw r11, 4(r12) - - /* Jump to common tlb load */ - b finish_tlb_load - -2: - /* The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ - mfspr r11, SPRN_SPRG7R - mtcr r11 - mfspr r13, SPRN_SPRG5R - mfspr r12, SPRN_SPRG4R - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b data_access - - /* Instruction TLB Error Interrupt */ - /* - * Nearly the same as above, except we get our - * information from different registers and bailout - * to a different point. - */ - START_EXCEPTION(InstructionTLBError) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 - mtspr SPRN_SPRG4W, r12 - mtspr SPRN_SPRG5W, r13 - mfcr r11 - mtspr SPRN_SPRG7W, r11 - mfspr r10, SPRN_SRR0 /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, TASK_SIZE@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - - mfspr r12,SPRN_MMUCR - rlwinm r12,r12,0,0,23 /* Clear TID */ - - b 4f - - /* Get the PGD for the current thread */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) - - /* Load PID into MMUCR TID */ - mfspr r12,SPRN_MMUCR - mfspr r13,SPRN_PID /* Get PID */ - rlwimi r12,r13,0,24,31 /* Set TID */ - -4: - mtspr SPRN_MMUCR,r12 - - rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ - lwzx r11, r12, r11 /* Get pgd/pmd entry */ - rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ - lwz r11, 4(r12) /* Get pte entry */ - andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ - beq 2f /* Bail if not present */ - - ori r11, r11, _PAGE_ACCESSED - stw r11, 4(r12) - - /* Jump to common TLB load point */ - b finish_tlb_load - -2: - /* The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ - mfspr r11, SPRN_SPRG7R - mtcr r11 - mfspr r13, SPRN_SPRG5R - mfspr r12, SPRN_SPRG4R - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b InstructionStorage - - /* Debug Interrupt */ - DEBUG_EXCEPTION - -/* - * Local functions - */ - /* - * Data TLB exceptions will bail out to this point - * if they can't resolve the lightweight TLB fault. - */ -data_access: - NORMAL_EXCEPTION_PROLOG - mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ - stw r5,_ESR(r11) - mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ - EXC_XFER_EE_LITE(0x0300, handle_page_fault) - -/* - - * Both the instruction and data TLB miss get to this - * point to load the TLB. - * r10 - EA of fault - * r11 - available to use - * r12 - Pointer to the 64-bit PTE - * r13 - available to use - * MMUCR - loaded with proper value when we get here - * Upon exit, we reload everything and RFI. - */ -finish_tlb_load: - /* - * We set execute, because we don't have the granularity to - * properly set this at the page level (Linux problem). - * If shared is set, we cause a zero PID->TID load. - * Many of these bits are software only. Bits we don't set - * here we (properly should) assume have the appropriate value. - */ - - /* Load the next available TLB index */ - lis r13, tlb_44x_index@ha - lwz r13, tlb_44x_index@l(r13) - /* Load the TLB high watermark */ - lis r11, tlb_44x_hwater@ha - lwz r11, tlb_44x_hwater@l(r11) - - /* Increment, rollover, and store TLB index */ - addi r13, r13, 1 - cmpw 0, r13, r11 /* reserve entries */ - ble 7f - li r13, 0 -7: - /* Store the next available TLB index */ - lis r11, tlb_44x_index@ha - stw r13, tlb_44x_index@l(r11) - - lwz r11, 0(r12) /* Get MS word of PTE */ - lwz r12, 4(r12) /* Get LS word of PTE */ - rlwimi r11, r12, 0, 0 , 19 /* Insert RPN */ - tlbwe r11, r13, PPC44x_TLB_XLAT /* Write XLAT */ - - /* - * Create PAGEID. This is the faulting address, - * page size, and valid flag. - */ - li r11, PPC44x_TLB_VALID | PPC44x_TLB_4K - rlwimi r10, r11, 0, 20, 31 /* Insert valid and page size */ - tlbwe r10, r13, PPC44x_TLB_PAGEID /* Write PAGEID */ - - li r10, PPC44x_TLB_SR@l /* Set SR */ - rlwimi r10, r12, 0, 30, 30 /* Set SW = _PAGE_RW */ - rlwimi r10, r12, 29, 29, 29 /* SX = _PAGE_HWEXEC */ - rlwimi r10, r12, 29, 28, 28 /* UR = _PAGE_USER */ - rlwimi r11, r12, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */ - and r11, r12, r11 /* HWEXEC & USER */ - rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */ - - rlwimi r12, r10, 0, 26, 31 /* Insert static perms */ - rlwinm r12, r12, 0, 20, 15 /* Clear U0-U3 */ - tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */ - - /* Done...restore registers and get out of here. - */ - mfspr r11, SPRN_SPRG7R - mtcr r11 - mfspr r13, SPRN_SPRG5R - mfspr r12, SPRN_SPRG4R - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - rfi /* Force context change */ - -/* - * Global functions - */ - -/* - * extern void giveup_altivec(struct task_struct *prev) - * - * The 44x core does not have an AltiVec unit. - */ -_GLOBAL(giveup_altivec) - blr - -/* - * extern void giveup_fpu(struct task_struct *prev) - * - * The 44x core does not have an FPU. - */ -#ifndef CONFIG_PPC_FPU -_GLOBAL(giveup_fpu) - blr -#endif - -/* - * extern void abort(void) - * - * At present, this routine just applies a system reset. - */ -_GLOBAL(abort) - mfspr r13,SPRN_DBCR0 - oris r13,r13,DBCR0_RST_SYSTEM@h - mtspr SPRN_DBCR0,r13 - -_GLOBAL(set_context) - -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is the second parameter. - */ - lis r5, abatron_pteptrs@h - ori r5, r5, abatron_pteptrs@l - stw r4, 0x4(r5) -#endif - mtspr SPRN_PID,r3 - isync /* Force context change */ - blr - -/* - * We put a few things here that have to be page-aligned. This stuff - * goes at the beginning of the data segment, which is page-aligned. - */ - .data - .align 12 - .globl sdata -sdata: - .globl empty_zero_page -empty_zero_page: - .space 4096 - -/* - * To support >32-bit physical addresses, we use an 8KB pgdir. - */ - .globl swapper_pg_dir -swapper_pg_dir: - .space 8192 - -/* Reserved 4k for the critical exception stack & 4k for the machine - * check stack per CPU for kernel mode exceptions */ - .section .bss - .align 12 -exception_stack_bottom: - .space BOOKE_EXCEPTION_STACK_SIZE - .globl exception_stack_top -exception_stack_top: - -/* - * This space gets a copy of optional info passed to us by the bootstrap - * which is used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space 512 - -/* - * Room for two PTE pointers, usually the kernel and current user pointers - * to their respective root page table. - */ -abatron_pteptrs: - .space 8 diff --git a/arch/ppc/kernel/head_4xx.S b/arch/ppc/kernel/head_4xx.S deleted file mode 100644 index 51da157a629e..000000000000 --- a/arch/ppc/kernel/head_4xx.S +++ /dev/null @@ -1,1021 +0,0 @@ -/* - * Copyright (c) 1995-1996 Gary Thomas - * Initial PowerPC version. - * Copyright (c) 1996 Cort Dougan - * Rewritten for PReP - * Copyright (c) 1996 Paul Mackerras - * Low-level exception handers, MMU support, and rewrite. - * Copyright (c) 1997 Dan Malek - * PowerPC 8xx modifications. - * Copyright (c) 1998-1999 TiVo, Inc. - * PowerPC 403GCX modifications. - * Copyright (c) 1999 Grant Erickson - * PowerPC 403GCX/405GP modifications. - * Copyright 2000 MontaVista Software Inc. - * PPC405 modifications - * PowerPC 403GCX/405GP modifications. - * Author: MontaVista Software, Inc. - * frank_rowand@mvista.com or source@mvista.com - * debbie_chu@mvista.com - * - * - * Module name: head_4xx.S - * - * Description: - * Kernel execution entry point code. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* As with the other PowerPC ports, it is expected that when code - * execution begins here, the following registers contain valid, yet - * optional, information: - * - * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) - * r4 - Starting address of the init RAM disk - * r5 - Ending address of the init RAM disk - * r6 - Start of kernel command line string (e.g. "mem=96m") - * r7 - End of kernel command line string - * - * This is all going to change RSN when we add bi_recs....... -- Dan - */ - .text -_GLOBAL(_stext) -_GLOBAL(_start) - - /* Save parameters we are passed. - */ - mr r31,r3 - mr r30,r4 - mr r29,r5 - mr r28,r6 - mr r27,r7 - - /* We have to turn on the MMU right away so we get cache modes - * set correctly. - */ - bl initial_mmu - -/* We now have the lower 16 Meg mapped into TLB entries, and the caches - * ready to work. - */ -turn_on_mmu: - lis r0,MSR_KERNEL@h - ori r0,r0,MSR_KERNEL@l - mtspr SPRN_SRR1,r0 - lis r0,start_here@h - ori r0,r0,start_here@l - mtspr SPRN_SRR0,r0 - SYNC - rfi /* enables MMU */ - b . /* prevent prefetch past rfi */ - -/* - * This area is used for temporarily saving registers during the - * critical exception prolog. - */ - . = 0xc0 -crit_save: -_GLOBAL(crit_r10) - .space 4 -_GLOBAL(crit_r11) - .space 4 - -/* - * Exception vector entry code. This code runs with address translation - * turned off (i.e. using physical addresses). We assume SPRG3 has the - * physical address of the current task thread_struct. - * Note that we have to have decremented r1 before we write to any fields - * of the exception frame, since a critical interrupt could occur at any - * time, and it will write to the area immediately below the current r1. - */ -#define NORMAL_EXCEPTION_PROLOG \ - mtspr SPRN_SPRG0,r10; /* save two registers to work with */\ - mtspr SPRN_SPRG1,r11; \ - mtspr SPRN_SPRG2,r1; \ - mfcr r10; /* save CR in r10 for now */\ - mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ - andi. r11,r11,MSR_PR; \ - beq 1f; \ - mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\ - lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ - addi r1,r1,THREAD_SIZE; \ -1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ - tophys(r11,r1); \ - stw r10,_CCR(r11); /* save various registers */\ - stw r12,GPR12(r11); \ - stw r9,GPR9(r11); \ - mfspr r10,SPRN_SPRG0; \ - stw r10,GPR10(r11); \ - mfspr r12,SPRN_SPRG1; \ - stw r12,GPR11(r11); \ - mflr r10; \ - stw r10,_LINK(r11); \ - mfspr r10,SPRN_SPRG2; \ - mfspr r12,SPRN_SRR0; \ - stw r10,GPR1(r11); \ - mfspr r9,SPRN_SRR1; \ - stw r10,0(r11); \ - rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ - stw r0,GPR0(r11); \ - SAVE_4GPRS(3, r11); \ - SAVE_2GPRS(7, r11) - -/* - * Exception prolog for critical exceptions. This is a little different - * from the normal exception prolog above since a critical exception - * can potentially occur at any point during normal exception processing. - * Thus we cannot use the same SPRG registers as the normal prolog above. - * Instead we use a couple of words of memory at low physical addresses. - * This is OK since we don't support SMP on these processors. - */ -#define CRITICAL_EXCEPTION_PROLOG \ - stw r10,crit_r10@l(0); /* save two registers to work with */\ - stw r11,crit_r11@l(0); \ - mfcr r10; /* save CR in r10 for now */\ - mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ - andi. r11,r11,MSR_PR; \ - lis r11,critical_stack_top@h; \ - ori r11,r11,critical_stack_top@l; \ - beq 1f; \ - /* COMING FROM USER MODE */ \ - mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ - lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ - addi r11,r11,THREAD_SIZE; \ -1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ - tophys(r11,r11); \ - stw r10,_CCR(r11); /* save various registers */\ - stw r12,GPR12(r11); \ - stw r9,GPR9(r11); \ - mflr r10; \ - stw r10,_LINK(r11); \ - mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ - stw r12,_DEAR(r11); /* since they may have had stuff */\ - mfspr r9,SPRN_ESR; /* in them at the point where the */\ - stw r9,_ESR(r11); /* exception was taken */\ - mfspr r12,SPRN_SRR2; \ - stw r1,GPR1(r11); \ - mfspr r9,SPRN_SRR3; \ - stw r1,0(r11); \ - tovirt(r1,r11); \ - rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ - stw r0,GPR0(r11); \ - SAVE_4GPRS(3, r11); \ - SAVE_2GPRS(7, r11) - - /* - * State at this point: - * r9 saved in stack frame, now saved SRR3 & ~MSR_WE - * r10 saved in crit_r10 and in stack frame, trashed - * r11 saved in crit_r11 and in stack frame, - * now phys stack/exception frame pointer - * r12 saved in stack frame, now saved SRR2 - * CR saved in stack frame, CR0.EQ = !SRR3.PR - * LR, DEAR, ESR in stack frame - * r1 saved in stack frame, now virt stack/excframe pointer - * r0, r3-r8 saved in stack frame - */ - -/* - * Exception vectors. - */ -#define START_EXCEPTION(n, label) \ - . = n; \ -label: - -#define EXCEPTION(n, label, hdlr, xfer) \ - START_EXCEPTION(n, label); \ - NORMAL_EXCEPTION_PROLOG; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - xfer(n, hdlr) - -#define CRITICAL_EXCEPTION(n, label, hdlr) \ - START_EXCEPTION(n, label); \ - CRITICAL_EXCEPTION_PROLOG; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ - NOCOPY, crit_transfer_to_handler, \ - ret_from_crit_exc) - -#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ - li r10,trap; \ - stw r10,TRAP(r11); \ - lis r10,msr@h; \ - ori r10,r10,msr@l; \ - copyee(r10, r9); \ - bl tfer; \ - .long hdlr; \ - .long ret - -#define COPY_EE(d, s) rlwimi d,s,0,16,16 -#define NOCOPY(d, s) - -#define EXC_XFER_STD(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ - ret_from_except) - -#define EXC_XFER_EE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_EE_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ - ret_from_except) - - -/* - * 0x0100 - Critical Interrupt Exception - */ - CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception) - -/* - * 0x0200 - Machine Check Exception - */ - CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) - -/* - * 0x0300 - Data Storage Exception - * This happens for just a few reasons. U0 set (but we don't do that), - * or zone protection fault (user violation, write to protected page). - * If this is just an update of modified status, we do that quickly - * and exit. Otherwise, we call heavywight functions to do the work. - */ - START_EXCEPTION(0x0300, DataStorage) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 -#ifdef CONFIG_403GCX - stw r12, 0(r0) - stw r9, 4(r0) - mfcr r11 - mfspr r12, SPRN_PID - stw r11, 8(r0) - stw r12, 12(r0) -#else - mtspr SPRN_SPRG4, r12 - mtspr SPRN_SPRG5, r9 - mfcr r11 - mfspr r12, SPRN_PID - mtspr SPRN_SPRG7, r11 - mtspr SPRN_SPRG6, r12 -#endif - - /* First, check if it was a zone fault (which means a user - * tried to access a kernel or read-protected page - always - * a SEGV). All other faults here must be stores, so no - * need to check ESR_DST as well. */ - mfspr r10, SPRN_ESR - andis. r10, r10, ESR_DIZ@h - bne 2f - - mfspr r10, SPRN_DEAR /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, TASK_SIZE@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - li r9, 0 - mtspr SPRN_PID, r9 /* TLB will have 0 TID */ - b 4f - - /* Get the PGD for the current thread. - */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) -4: - tophys(r11, r11) - rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ - lwz r11, 0(r11) /* Get L1 entry */ - rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ - lwz r11, 0(r12) /* Get Linux PTE */ - - andi. r9, r11, _PAGE_RW /* Is it writeable? */ - beq 2f /* Bail if not */ - - /* Update 'changed'. - */ - ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE - stw r11, 0(r12) /* Update Linux page table */ - - /* Most of the Linux PTE is ready to load into the TLB LO. - * We set ZSEL, where only the LS-bit determines user access. - * We set execute, because we don't have the granularity to - * properly set this at the page level (Linux problem). - * If shared is set, we cause a zero PID->TID load. - * Many of these bits are software only. Bits we don't set - * here we (properly should) assume have the appropriate value. - */ - li r12, 0x0ce2 - andc r11, r11, r12 /* Make sure 20, 21 are zero */ - - /* find the TLB index that caused the fault. It has to be here. - */ - tlbsx r9, 0, r10 - - tlbwe r11, r9, TLB_DATA /* Load TLB LO */ - - /* Done...restore registers and get out of here. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - PPC405_ERR77_SYNC - rfi /* Should sync shadow TLBs */ - b . /* prevent prefetch past rfi */ - -2: - /* The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b DataAccess - -/* - * 0x0400 - Instruction Storage Exception - * This is caused by a fetch from non-execute or guarded pages. - */ - START_EXCEPTION(0x0400, InstructionAccess) - NORMAL_EXCEPTION_PROLOG - mr r4,r12 /* Pass SRR0 as arg2 */ - li r5,0 /* Pass zero as arg3 */ - EXC_XFER_EE_LITE(0x400, handle_page_fault) - -/* 0x0500 - External Interrupt Exception */ - EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) - -/* 0x0600 - Alignment Exception */ - START_EXCEPTION(0x0600, Alignment) - NORMAL_EXCEPTION_PROLOG - mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ - stw r4,_DEAR(r11) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_EE(0x600, alignment_exception) - -/* 0x0700 - Program Exception */ - START_EXCEPTION(0x0700, ProgramCheck) - NORMAL_EXCEPTION_PROLOG - mfspr r4,SPRN_ESR /* Grab the ESR and save it */ - stw r4,_ESR(r11) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_STD(0x700, program_check_exception) - - EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) - -/* 0x0C00 - System Call Exception */ - START_EXCEPTION(0x0C00, SystemCall) - NORMAL_EXCEPTION_PROLOG - EXC_XFER_EE_LITE(0xc00, DoSyscall) - - EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) - -/* 0x1000 - Programmable Interval Timer (PIT) Exception */ - START_EXCEPTION(0x1000, Decrementer) - NORMAL_EXCEPTION_PROLOG - lis r0,TSR_PIS@h - mtspr SPRN_TSR,r0 /* Clear the PIT exception */ - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_LITE(0x1000, timer_interrupt) - -#if 0 -/* NOTE: - * FIT and WDT handlers are not implemented yet. - */ - -/* 0x1010 - Fixed Interval Timer (FIT) Exception -*/ - STND_EXCEPTION(0x1010, FITException, unknown_exception) - -/* 0x1020 - Watchdog Timer (WDT) Exception -*/ -#ifdef CONFIG_BOOKE_WDT - CRITICAL_EXCEPTION(0x1020, WDTException, WatchdogException) -#else - CRITICAL_EXCEPTION(0x1020, WDTException, unknown_exception) -#endif -#endif - -/* 0x1100 - Data TLB Miss Exception - * As the name implies, translation is not in the MMU, so search the - * page tables and fix it. The only purpose of this function is to - * load TLB entries from the page table if they exist. - */ - START_EXCEPTION(0x1100, DTLBMiss) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 -#ifdef CONFIG_403GCX - stw r12, 0(r0) - stw r9, 4(r0) - mfcr r11 - mfspr r12, SPRN_PID - stw r11, 8(r0) - stw r12, 12(r0) -#else - mtspr SPRN_SPRG4, r12 - mtspr SPRN_SPRG5, r9 - mfcr r11 - mfspr r12, SPRN_PID - mtspr SPRN_SPRG7, r11 - mtspr SPRN_SPRG6, r12 -#endif - mfspr r10, SPRN_DEAR /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, TASK_SIZE@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - li r9, 0 - mtspr SPRN_PID, r9 /* TLB will have 0 TID */ - b 4f - - /* Get the PGD for the current thread. - */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) -4: - tophys(r11, r11) - rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ - lwz r12, 0(r11) /* Get L1 entry */ - andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ - lwz r11, 0(r12) /* Get Linux PTE */ - andi. r9, r11, _PAGE_PRESENT - beq 5f - - ori r11, r11, _PAGE_ACCESSED - stw r11, 0(r12) - - /* Create TLB tag. This is the faulting address plus a static - * set of bits. These are size, valid, E, U0. - */ - li r12, 0x00c0 - rlwimi r10, r12, 0, 20, 31 - - b finish_tlb_load - -2: /* Check for possible large-page pmd entry */ - rlwinm. r9, r12, 2, 22, 24 - beq 5f - - /* Create TLB tag. This is the faulting address, plus a static - * set of bits (valid, E, U0) plus the size from the PMD. - */ - ori r9, r9, 0x40 - rlwimi r10, r9, 0, 20, 31 - mr r11, r12 - - b finish_tlb_load - -5: - /* The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b DataAccess - -/* 0x1200 - Instruction TLB Miss Exception - * Nearly the same as above, except we get our information from different - * registers and bailout to a different point. - */ - START_EXCEPTION(0x1200, ITLBMiss) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 -#ifdef CONFIG_403GCX - stw r12, 0(r0) - stw r9, 4(r0) - mfcr r11 - mfspr r12, SPRN_PID - stw r11, 8(r0) - stw r12, 12(r0) -#else - mtspr SPRN_SPRG4, r12 - mtspr SPRN_SPRG5, r9 - mfcr r11 - mfspr r12, SPRN_PID - mtspr SPRN_SPRG7, r11 - mtspr SPRN_SPRG6, r12 -#endif - mfspr r10, SPRN_SRR0 /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, TASK_SIZE@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - li r9, 0 - mtspr SPRN_PID, r9 /* TLB will have 0 TID */ - b 4f - - /* Get the PGD for the current thread. - */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) -4: - tophys(r11, r11) - rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ - lwz r12, 0(r11) /* Get L1 entry */ - andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ - lwz r11, 0(r12) /* Get Linux PTE */ - andi. r9, r11, _PAGE_PRESENT - beq 5f - - ori r11, r11, _PAGE_ACCESSED - stw r11, 0(r12) - - /* Create TLB tag. This is the faulting address plus a static - * set of bits. These are size, valid, E, U0. - */ - li r12, 0x00c0 - rlwimi r10, r12, 0, 20, 31 - - b finish_tlb_load - -2: /* Check for possible large-page pmd entry */ - rlwinm. r9, r12, 2, 22, 24 - beq 5f - - /* Create TLB tag. This is the faulting address, plus a static - * set of bits (valid, E, U0) plus the size from the PMD. - */ - ori r9, r9, 0x40 - rlwimi r10, r9, 0, 20, 31 - mr r11, r12 - - b finish_tlb_load - -5: - /* The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b InstructionAccess - - EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) -#ifdef CONFIG_IBM405_ERR51 - /* 405GP errata 51 */ - START_EXCEPTION(0x1700, Trap_17) - b DTLBMiss -#else - EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) -#endif - EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE) - -/* Check for a single step debug exception while in an exception - * handler before state has been saved. This is to catch the case - * where an instruction that we are trying to single step causes - * an exception (eg ITLB/DTLB miss) and thus the first instruction of - * the exception handler generates a single step debug exception. - * - * If we get a debug trap on the first instruction of an exception handler, - * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is - * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). - * The exception handler was handling a non-critical interrupt, so it will - * save (and later restore) the MSR via SPRN_SRR1, which will still have - * the MSR_DE bit set. - */ - /* 0x2000 - Debug Exception */ - START_EXCEPTION(0x2000, DebugTrap) - CRITICAL_EXCEPTION_PROLOG - - /* - * If this is a single step or branch-taken exception in an - * exception entry sequence, it was probably meant to apply to - * the code where the exception occurred (since exception entry - * doesn't turn off DE automatically). We simulate the effect - * of turning off DE on entry to an exception handler by turning - * off DE in the SRR3 value and clearing the debug status. - */ - mfspr r10,SPRN_DBSR /* check single-step/branch taken */ - andis. r10,r10,DBSR_IC@h - beq+ 2f - - andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ - beq 1f /* branch and fix it up */ - - mfspr r10,SPRN_SRR2 /* Faulting instruction address */ - cmplwi r10,0x2100 - bgt+ 2f /* address above exception vectors */ - - /* here it looks like we got an inappropriate debug exception. */ -1: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ - lis r10,DBSR_IC@h /* clear the IC event */ - mtspr SPRN_DBSR,r10 - /* restore state and get out */ - lwz r10,_CCR(r11) - lwz r0,GPR0(r11) - lwz r1,GPR1(r11) - mtcrf 0x80,r10 - mtspr SPRN_SRR2,r12 - mtspr SPRN_SRR3,r9 - lwz r9,GPR9(r11) - lwz r12,GPR12(r11) - lwz r10,crit_r10@l(0) - lwz r11,crit_r11@l(0) - PPC405_ERR77_SYNC - rfci - b . - - /* continue normal handling for a critical exception... */ -2: mfspr r4,SPRN_DBSR - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(DebugException, 0x2002, \ - (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ - NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) - -/* - * The other Data TLB exceptions bail out to this point - * if they can't resolve the lightweight TLB fault. - */ -DataAccess: - NORMAL_EXCEPTION_PROLOG - mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ - stw r5,_ESR(r11) - mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ - EXC_XFER_EE_LITE(0x300, handle_page_fault) - -/* Other PowerPC processors, namely those derived from the 6xx-series - * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. - * However, for the 4xx-series processors these are neither defined nor - * reserved. - */ - - /* Damn, I came up one instruction too many to fit into the - * exception space :-). Both the instruction and data TLB - * miss get to this point to load the TLB. - * r10 - TLB_TAG value - * r11 - Linux PTE - * r12, r9 - avilable to use - * PID - loaded with proper value when we get here - * Upon exit, we reload everything and RFI. - * Actually, it will fit now, but oh well.....a common place - * to load the TLB. - */ -tlb_4xx_index: - .long 0 -finish_tlb_load: - /* load the next available TLB index. - */ - lwz r9, tlb_4xx_index@l(0) - addi r9, r9, 1 - andi. r9, r9, (PPC4XX_TLB_SIZE-1) - stw r9, tlb_4xx_index@l(0) - -6: - /* - * Clear out the software-only bits in the PTE to generate the - * TLB_DATA value. These are the bottom 2 bits of the RPM, the - * top 3 bits of the zone field, and M. - */ - li r12, 0x0ce2 - andc r11, r11, r12 - - tlbwe r11, r9, TLB_DATA /* Load TLB LO */ - tlbwe r10, r9, TLB_TAG /* Load TLB HI */ - - /* Done...restore registers and get out of here. - */ -#ifdef CONFIG_403GCX - lwz r12, 12(r0) - lwz r11, 8(r0) - mtspr SPRN_PID, r12 - mtcr r11 - lwz r9, 4(r0) - lwz r12, 0(r0) -#else - mfspr r12, SPRN_SPRG6 - mfspr r11, SPRN_SPRG7 - mtspr SPRN_PID, r12 - mtcr r11 - mfspr r9, SPRN_SPRG5 - mfspr r12, SPRN_SPRG4 -#endif - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - PPC405_ERR77_SYNC - rfi /* Should sync shadow TLBs */ - b . /* prevent prefetch past rfi */ - -/* extern void giveup_fpu(struct task_struct *prev) - * - * The PowerPC 4xx family of processors do not have an FPU, so this just - * returns. - */ -_GLOBAL(giveup_fpu) - blr - -/* This is where the main kernel code starts. - */ -start_here: - - /* ptr to current */ - lis r2,init_task@h - ori r2,r2,init_task@l - - /* ptr to phys current thread */ - tophys(r4,r2) - addi r4,r4,THREAD /* init task's THREAD */ - mtspr SPRN_SPRG3,r4 - - /* stack */ - lis r1,init_thread_union@ha - addi r1,r1,init_thread_union@l - li r0,0 - stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) - - bl early_init /* We have to do this with MMU on */ - -/* - * Decide what sort of machine this is and initialize the MMU. - */ - mr r3,r31 - mr r4,r30 - mr r5,r29 - mr r6,r28 - mr r7,r27 - bl machine_init - bl MMU_init - -/* Go back to running unmapped so we can load up new values - * and change to using our exception vectors. - * On the 4xx, all we have to do is invalidate the TLB to clear - * the old 16M byte TLB mappings. - */ - lis r4,2f@h - ori r4,r4,2f@l - tophys(r4,r4) - lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h - ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l - mtspr SPRN_SRR0,r4 - mtspr SPRN_SRR1,r3 - rfi - b . /* prevent prefetch past rfi */ - -/* Load up the kernel context */ -2: - sync /* Flush to memory before changing TLB */ - tlbia - isync /* Flush shadow TLBs */ - - /* set up the PTE pointers for the Abatron bdiGDB. - */ - lis r6, swapper_pg_dir@h - ori r6, r6, swapper_pg_dir@l - lis r5, abatron_pteptrs@h - ori r5, r5, abatron_pteptrs@l - stw r5, 0xf0(r0) /* Must match your Abatron config file */ - tophys(r5,r5) - stw r6, 0(r5) - -/* Now turn on the MMU for real! */ - lis r4,MSR_KERNEL@h - ori r4,r4,MSR_KERNEL@l - lis r3,start_kernel@h - ori r3,r3,start_kernel@l - mtspr SPRN_SRR0,r3 - mtspr SPRN_SRR1,r4 - rfi /* enable MMU and jump to start_kernel */ - b . /* prevent prefetch past rfi */ - -/* Set up the initial MMU state so we can do the first level of - * kernel initialization. This maps the first 16 MBytes of memory 1:1 - * virtual to physical and more importantly sets the cache mode. - */ -initial_mmu: - tlbia /* Invalidate all TLB entries */ - isync - - /* We should still be executing code at physical address 0x0000xxxx - * at this point. However, start_here is at virtual address - * 0xC000xxxx. So, set up a TLB mapping to cover this once - * translation is enabled. - */ - - lis r3,KERNELBASE@h /* Load the kernel virtual address */ - ori r3,r3,KERNELBASE@l - tophys(r4,r3) /* Load the kernel physical address */ - - iccci r0,r3 /* Invalidate the i-cache before use */ - - /* Load the kernel PID. - */ - li r0,0 - mtspr SPRN_PID,r0 - sync - - /* Configure and load two entries into TLB slots 62 and 63. - * In case we are pinning TLBs, these are reserved in by the - * other TLB functions. If not reserving, then it doesn't - * matter where they are loaded. - */ - clrrwi r4,r4,10 /* Mask off the real page number */ - ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ - - clrrwi r3,r3,10 /* Mask off the effective page number */ - ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) - - li r0,63 /* TLB slot 63 */ - - tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ - tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE) - - /* Load a TLB entry for the UART, so that ppc4xx_progress() can use - * the UARTs nice and early. We use a 4k real==virtual mapping. */ - - lis r3,SERIAL_DEBUG_IO_BASE@h - ori r3,r3,SERIAL_DEBUG_IO_BASE@l - mr r4,r3 - clrrwi r4,r4,12 - ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G) - - clrrwi r3,r3,12 - ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) - - li r0,0 /* TLB slot 0 */ - tlbwe r4,r0,TLB_DATA - tlbwe r3,r0,TLB_TAG -#endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */ - - isync - - /* Establish the exception vector base - */ - lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ - tophys(r0,r4) /* Use the physical address */ - mtspr SPRN_EVPR,r0 - - blr - -_GLOBAL(abort) - mfspr r13,SPRN_DBCR0 - oris r13,r13,DBCR0_RST_SYSTEM@h - mtspr SPRN_DBCR0,r13 - -_GLOBAL(set_context) - -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is the second parameter. - */ - lis r5, KERNELBASE@h - lwz r5, 0xf0(r5) - stw r4, 0x4(r5) -#endif - sync - mtspr SPRN_PID,r3 - isync /* Need an isync to flush shadow */ - /* TLBs after changing PID */ - blr - -/* We put a few things here that have to be page-aligned. This stuff - * goes at the beginning of the data segment, which is page-aligned. - */ - .data - .align 12 - .globl sdata -sdata: - .globl empty_zero_page -empty_zero_page: - .space 4096 - .globl swapper_pg_dir -swapper_pg_dir: - .space 4096 - - -/* Stack for handling critical exceptions from kernel mode */ - .section .bss - .align 12 -exception_stack_bottom: - .space 4096 -critical_stack_top: - .globl exception_stack_top -exception_stack_top: - -/* This space gets a copy of optional info passed to us by the bootstrap - * which is used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space 512 - -/* Room for two PTE pointers, usually the kernel and current user pointers - * to their respective root page table. - */ -abatron_pteptrs: - .space 8 diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S deleted file mode 100644 index 321bda2de2cb..000000000000 --- a/arch/ppc/kernel/head_8xx.S +++ /dev/null @@ -1,959 +0,0 @@ -/* - * PowerPC version - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP - * Copyright (C) 1996 Cort Dougan - * Low-level exception handlers and MMU support - * rewritten by Paul Mackerras. - * Copyright (C) 1996 Paul Mackerras. - * MPC8xx modifications by Dan Malek - * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). - * - * This file contains low-level support and setup for PowerPC 8xx - * embedded processors, including trap and interrupt dispatch. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Macro to make the code more readable. */ -#ifdef CONFIG_8xx_CPU6 -#define DO_8xx_CPU6(val, reg) \ - li reg, val; \ - stw reg, 12(r0); \ - lwz reg, 12(r0); -#else -#define DO_8xx_CPU6(val, reg) -#endif - .text - .globl _stext -_stext: - .text - .globl _start -_start: - -/* MPC8xx - * This port was done on an MBX board with an 860. Right now I only - * support an ELF compressed (zImage) boot from EPPC-Bug because the - * code there loads up some registers before calling us: - * r3: ptr to board info data - * r4: initrd_start or if no initrd then 0 - * r5: initrd_end - unused if r4 is 0 - * r6: Start of command line string - * r7: End of command line string - * - * I decided to use conditional compilation instead of checking PVR and - * adding more processor specific branches around code I don't need. - * Since this is an embedded processor, I also appreciate any memory - * savings I can get. - * - * The MPC8xx does not have any BATs, but it supports large page sizes. - * We first initialize the MMU to support 8M byte pages, then load one - * entry into each of the instruction and data TLBs to map the first - * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to - * the "internal" processor registers before MMU_init is called. - * - * The TLB code currently contains a major hack. Since I use the condition - * code register, I have to save and restore it. I am out of registers, so - * I just store it in memory location 0 (the TLB handlers are not reentrant). - * To avoid making any decisions, I need to use the "segment" valid bit - * in the first level table, but that would require many changes to the - * Linux page directory/table functions that I don't want to do right now. - * - * I used to use SPRG2 for a temporary register in the TLB handler, but it - * has since been put to other uses. I now use a hack to save a register - * and the CCR at memory location 0.....Someday I'll fix this..... - * -- Dan - */ - .globl __start -__start: - mr r31,r3 /* save parameters */ - mr r30,r4 - mr r29,r5 - mr r28,r6 - mr r27,r7 - - /* We have to turn on the MMU right away so we get cache modes - * set correctly. - */ - bl initial_mmu - -/* We now have the lower 8 Meg mapped into TLB entries, and the caches - * ready to work. - */ - -turn_on_mmu: - mfmsr r0 - ori r0,r0,MSR_DR|MSR_IR - mtspr SPRN_SRR1,r0 - lis r0,start_here@h - ori r0,r0,start_here@l - mtspr SPRN_SRR0,r0 - SYNC - rfi /* enables MMU */ - -/* - * Exception entry code. This code runs with address translation - * turned off, i.e. using physical addresses. - * We assume sprg3 has the physical address of the current - * task's thread_struct. - */ -#define EXCEPTION_PROLOG \ - mtspr SPRN_SPRG0,r10; \ - mtspr SPRN_SPRG1,r11; \ - mfcr r10; \ - EXCEPTION_PROLOG_1; \ - EXCEPTION_PROLOG_2 - -#define EXCEPTION_PROLOG_1 \ - mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ - andi. r11,r11,MSR_PR; \ - tophys(r11,r1); /* use tophys(r1) if kernel */ \ - beq 1f; \ - mfspr r11,SPRN_SPRG3; \ - lwz r11,THREAD_INFO-THREAD(r11); \ - addi r11,r11,THREAD_SIZE; \ - tophys(r11,r11); \ -1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ - - -#define EXCEPTION_PROLOG_2 \ - CLR_TOP32(r11); \ - stw r10,_CCR(r11); /* save registers */ \ - stw r12,GPR12(r11); \ - stw r9,GPR9(r11); \ - mfspr r10,SPRN_SPRG0; \ - stw r10,GPR10(r11); \ - mfspr r12,SPRN_SPRG1; \ - stw r12,GPR11(r11); \ - mflr r10; \ - stw r10,_LINK(r11); \ - mfspr r12,SPRN_SRR0; \ - mfspr r9,SPRN_SRR1; \ - stw r1,GPR1(r11); \ - stw r1,0(r11); \ - tovirt(r1,r11); /* set new kernel sp */ \ - li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ - MTMSRD(r10); /* (except for mach check in rtas) */ \ - stw r0,GPR0(r11); \ - SAVE_4GPRS(3, r11); \ - SAVE_2GPRS(7, r11) - -/* - * Note: code which follows this uses cr0.eq (set if from kernel), - * r11, r12 (SRR0), and r9 (SRR1). - * - * Note2: once we have set r1 we are in a position to take exceptions - * again, and we could thus set MSR:RI at that point. - */ - -/* - * Exception vectors. - */ -#define EXCEPTION(n, label, hdlr, xfer) \ - . = n; \ -label: \ - EXCEPTION_PROLOG; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - xfer(n, hdlr) - -#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ - li r10,trap; \ - stw r10,TRAP(r11); \ - li r10,MSR_KERNEL; \ - copyee(r10, r9); \ - bl tfer; \ -i##n: \ - .long hdlr; \ - .long ret - -#define COPY_EE(d, s) rlwimi d,s,0,16,16 -#define NOCOPY(d, s) - -#define EXC_XFER_STD(n, hdlr) \ - EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ - ret_from_except) - -#define EXC_XFER_EE(n, hdlr) \ - EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_EE_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ - ret_from_except) - -/* System reset */ - EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) - -/* Machine check */ - . = 0x200 -MachineCheck: - EXCEPTION_PROLOG - mfspr r4,SPRN_DAR - stw r4,_DAR(r11) - mfspr r5,SPRN_DSISR - stw r5,_DSISR(r11) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_STD(0x200, machine_check_exception) - -/* Data access exception. - * This is "never generated" by the MPC8xx. We jump to it for other - * translation errors. - */ - . = 0x300 -DataAccess: - EXCEPTION_PROLOG - mfspr r10,SPRN_DSISR - stw r10,_DSISR(r11) - mr r5,r10 - mfspr r4,SPRN_DAR - EXC_XFER_EE_LITE(0x300, handle_page_fault) - -/* Instruction access exception. - * This is "never generated" by the MPC8xx. We jump to it for other - * translation errors. - */ - . = 0x400 -InstructionAccess: - EXCEPTION_PROLOG - mr r4,r12 - mr r5,r9 - EXC_XFER_EE_LITE(0x400, handle_page_fault) - -/* External interrupt */ - EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) - -/* Alignment exception */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,SPRN_DAR - stw r4,_DAR(r11) - mfspr r5,SPRN_DSISR - stw r5,_DSISR(r11) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_EE(0x600, alignment_exception) - -/* Program check exception */ - EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) - -/* No FPU on MPC8xx. This exception is not supposed to happen. -*/ - EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) - -/* Decrementer */ - EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) - - EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) - EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) - -/* System call */ - . = 0xc00 -SystemCall: - EXCEPTION_PROLOG - EXC_XFER_EE_LITE(0xc00, DoSyscall) - -/* Single step - not used on 601 */ - EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) - EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) - EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) - -/* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. - */ - EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) - - . = 0x1100 -/* - * For the MPC8xx, this is a software tablewalk to load the instruction - * TLB. It is modelled after the example in the Motorola manual. The task - * switch loads the M_TWB register with the pointer to the first level table. - * If we discover there is no second level table (value is zero) or if there - * is an invalid pte, we load that into the TLB, which causes another fault - * into the TLB Error interrupt where we can handle such problems. - * We have to use the MD_xxx registers for the tablewalk because the - * equivalent MI_xxx registers only perform the attribute functions. - */ -InstructionTLBMiss: -#ifdef CONFIG_8xx_CPU6 - stw r3, 8(r0) -#endif - DO_8xx_CPU6(0x3f80, r3) - mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ - mfcr r10 - stw r10, 0(r0) - stw r11, 4(r0) - mfspr r10, SPRN_SRR0 /* Get effective address of fault */ - DO_8xx_CPU6(0x3780, r3) - mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ - mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - andi. r11, r10, 0x0800 /* Address >= 0x80000000 */ - beq 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - rlwimi r10, r11, 0, 2, 19 -3: - lwz r11, 0(r10) /* Get the level 1 entry */ - rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ - beq 2f /* If zero, don't try to find a pte */ - - /* We have a pte table, so load the MI_TWC with the attributes - * for this "segment." - */ - ori r11,r11,1 /* Set valid bit */ - DO_8xx_CPU6(0x2b80, r3) - mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ - DO_8xx_CPU6(0x3b80, r3) - mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ - mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ - lwz r10, 0(r11) /* Get the pte */ - -#ifdef CONFIG_SWAP - /* do not set the _PAGE_ACCESSED bit of a non-present page */ - andi. r11, r10, _PAGE_PRESENT - beq 4f - ori r10, r10, _PAGE_ACCESSED - mfspr r11, SPRN_MD_TWC /* get the pte address again */ - stw r10, 0(r11) -4: -#else - ori r10, r10, _PAGE_ACCESSED - stw r10, 0(r11) -#endif - - /* The Linux PTE won't go exactly into the MMU TLB. - * Software indicator bits 21, 22 and 28 must be clear. - * Software indicator bits 24, 25, 26, and 27 must be - * set. All other Linux PTE bits control the behavior - * of the MMU. - */ -2: li r11, 0x00f0 - rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ - DO_8xx_CPU6(0x2d80, r3) - mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ - - mfspr r10, SPRN_M_TW /* Restore registers */ - lwz r11, 0(r0) - mtcr r11 - lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 - lwz r3, 8(r0) -#endif - rfi - - . = 0x1200 -DataStoreTLBMiss: - stw r3, 8(r0) - DO_8xx_CPU6(0x3f80, r3) - mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ - mfcr r10 - stw r10, 0(r0) - stw r11, 4(r0) - mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - andi. r11, r10, 0x0800 - beq 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - rlwimi r10, r11, 0, 2, 19 - stw r12, 16(r0) - b LoadLargeDTLB -3: - lwz r11, 0(r10) /* Get the level 1 entry */ - rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ - beq 2f /* If zero, don't try to find a pte */ - - /* We have a pte table, so load fetch the pte from the table. - */ - ori r11, r11, 1 /* Set valid bit in physical L2 page */ - DO_8xx_CPU6(0x3b80, r3) - mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ - mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ - lwz r10, 0(r10) /* Get the pte */ - - /* Insert the Guarded flag into the TWC from the Linux PTE. - * It is bit 27 of both the Linux PTE and the TWC (at least - * I got that right :-). It will be better when we can put - * this into the Linux pgd/pmd and load it in the operation - * above. - */ - rlwimi r11, r10, 0, 27, 27 - DO_8xx_CPU6(0x3b80, r3) - mtspr SPRN_MD_TWC, r11 - -#ifdef CONFIG_SWAP - /* do not set the _PAGE_ACCESSED bit of a non-present page */ - andi. r11, r10, _PAGE_PRESENT - beq 4f - ori r10, r10, _PAGE_ACCESSED -4: - /* and update pte in table */ -#else - ori r10, r10, _PAGE_ACCESSED -#endif - mfspr r11, SPRN_MD_TWC /* get the pte address again */ - stw r10, 0(r11) - - /* The Linux PTE won't go exactly into the MMU TLB. - * Software indicator bits 21, 22 and 28 must be clear. - * Software indicator bits 24, 25, 26, and 27 must be - * set. All other Linux PTE bits control the behavior - * of the MMU. - */ -2: li r11, 0x00f0 - rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ - DO_8xx_CPU6(0x3d80, r3) - mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ - - mfspr r10, SPRN_M_TW /* Restore registers */ - lwz r11, 0(r0) - mtcr r11 - lwz r11, 4(r0) - lwz r3, 8(r0) - rfi - -/* This is an instruction TLB error on the MPC8xx. This could be due - * to many reasons, such as executing guarded memory or illegal instruction - * addresses. There is nothing to do but handle a big time error fault. - */ - . = 0x1300 -InstructionTLBError: - b InstructionAccess - -LoadLargeDTLB: - li r12, 0 - lwz r11, 0(r10) /* Get the level 1 entry */ - rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ - beq 3f /* If zero, don't try to find a pte */ - - /* We have a pte table, so load fetch the pte from the table. - */ - ori r11, r11, 1 /* Set valid bit in physical L2 page */ - DO_8xx_CPU6(0x3b80, r3) - mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ - mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ - lwz r10, 0(r10) /* Get the pte */ - - /* Insert the Guarded flag into the TWC from the Linux PTE. - * It is bit 27 of both the Linux PTE and the TWC (at least - * I got that right :-). It will be better when we can put - * this into the Linux pgd/pmd and load it in the operation - * above. - */ - rlwimi r11, r10, 0, 27, 27 - - rlwimi r12, r10, 0, 0, 9 /* extract phys. addr */ - mfspr r3, SPRN_MD_EPN - rlwinm r3, r3, 0, 0, 9 /* extract virtual address */ - tophys(r3, r3) - cmpw r3, r12 /* only use 8M page if it is a direct - kernel mapping */ - bne 1f - ori r11, r11, MD_PS8MEG - li r12, 1 - b 2f -1: - li r12, 0 /* can't use 8MB TLB, so zero r12. */ -2: - DO_8xx_CPU6(0x3b80, r3) - mtspr SPRN_MD_TWC, r11 - - /* The Linux PTE won't go exactly into the MMU TLB. - * Software indicator bits 21, 22 and 28 must be clear. - * Software indicator bits 24, 25, 26, and 27 must be - * set. All other Linux PTE bits control the behavior - * of the MMU. - */ -3: li r11, 0x00f0 - rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ - cmpwi r12, 1 - bne 4f - ori r10, r10, 0x8 - - mfspr r12, SPRN_MD_EPN - lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */ - ori r3, r3, 0x0fff - and r12, r3, r12 - DO_8xx_CPU6(0x3780, r3) - mtspr SPRN_MD_EPN, r12 - - lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */ - ori r3, r3, 0x0fff - and r10, r3, r10 -4: - DO_8xx_CPU6(0x3d80, r3) - mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ - - mfspr r10, SPRN_M_TW /* Restore registers */ - lwz r11, 0(r0) - mtcr r11 - lwz r11, 4(r0) - - lwz r12, 16(r0) - lwz r3, 8(r0) - rfi - -/* This is the data TLB error on the MPC8xx. This could be due to - * many reasons, including a dirty update to a pte. We can catch that - * one here, but anything else is an error. First, we track down the - * Linux pte. If it is valid, write access is allowed, but the - * page dirty bit is not set, we will set it and reload the TLB. For - * any other case, we bail out to a higher level function that can - * handle it. - */ - . = 0x1400 -DataTLBError: -#ifdef CONFIG_8xx_CPU6 - stw r3, 8(r0) -#endif - DO_8xx_CPU6(0x3f80, r3) - mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ - mfcr r10 - stw r10, 0(r0) - stw r11, 4(r0) - - /* First, make sure this was a store operation. - */ - mfspr r10, SPRN_DSISR - andis. r11, r10, 0x0200 /* If set, indicates store op */ - beq 2f - - /* The EA of a data TLB miss is automatically stored in the MD_EPN - * register. The EA of a data TLB error is automatically stored in - * the DAR, but not the MD_EPN register. We must copy the 20 most - * significant bits of the EA from the DAR to MD_EPN before we - * start walking the page tables. We also need to copy the CASID - * value from the M_CASID register. - * Addendum: The EA of a data TLB error is _supposed_ to be stored - * in DAR, but it seems that this doesn't happen in some cases, such - * as when the error is due to a dcbi instruction to a page with a - * TLB that doesn't have the changed bit set. In such cases, there - * does not appear to be any way to recover the EA of the error - * since it is neither in DAR nor MD_EPN. As a workaround, the - * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs - * are initialized in mapin_ram(). This will avoid the problem, - * assuming we only use the dcbi instruction on kernel addresses. - */ - mfspr r10, SPRN_DAR - rlwinm r11, r10, 0, 0, 19 - ori r11, r11, MD_EVALID - mfspr r10, SPRN_M_CASID - rlwimi r11, r10, 0, 28, 31 - DO_8xx_CPU6(0x3780, r3) - mtspr SPRN_MD_EPN, r11 - - mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - andi. r11, r10, 0x0800 - beq 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - rlwimi r10, r11, 0, 2, 19 -3: - lwz r11, 0(r10) /* Get the level 1 entry */ - rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ - beq 2f /* If zero, bail */ - - /* We have a pte table, so fetch the pte from the table. - */ - ori r11, r11, 1 /* Set valid bit in physical L2 page */ - DO_8xx_CPU6(0x3b80, r3) - mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ - mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ - lwz r10, 0(r11) /* Get the pte */ - - andi. r11, r10, _PAGE_RW /* Is it writeable? */ - beq 2f /* Bail out if not */ - - /* Update 'changed', among others. - */ -#ifdef CONFIG_SWAP - ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE - /* do not set the _PAGE_ACCESSED bit of a non-present page */ - andi. r11, r10, _PAGE_PRESENT - beq 4f - ori r10, r10, _PAGE_ACCESSED -4: -#else - ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE -#endif - mfspr r11, SPRN_MD_TWC /* Get pte address again */ - stw r10, 0(r11) /* and update pte in table */ - - /* The Linux PTE won't go exactly into the MMU TLB. - * Software indicator bits 21, 22 and 28 must be clear. - * Software indicator bits 24, 25, 26, and 27 must be - * set. All other Linux PTE bits control the behavior - * of the MMU. - */ - li r11, 0x00f0 - rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ - DO_8xx_CPU6(0x3d80, r3) - mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ - - mfspr r10, SPRN_M_TW /* Restore registers */ - lwz r11, 0(r0) - mtcr r11 - lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 - lwz r3, 8(r0) -#endif - rfi -2: - mfspr r10, SPRN_M_TW /* Restore registers */ - lwz r11, 0(r0) - mtcr r11 - lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 - lwz r3, 8(r0) -#endif - b DataAccess - - EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) - -/* On the MPC8xx, these next four traps are used for development - * support of breakpoints and such. Someday I will get around to - * using them. - */ - EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) - - . = 0x2000 - - .globl giveup_fpu -giveup_fpu: - blr - -/* - * This is where the main kernel code starts. - */ -start_here: - /* ptr to current */ - lis r2,init_task@h - ori r2,r2,init_task@l - - /* ptr to phys current thread */ - tophys(r4,r2) - addi r4,r4,THREAD /* init task's THREAD */ - mtspr SPRN_SPRG3,r4 - li r3,0 - mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */ - - /* stack */ - lis r1,init_thread_union@ha - addi r1,r1,init_thread_union@l - li r0,0 - stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) - - bl early_init /* We have to do this with MMU on */ - -/* - * Decide what sort of machine this is and initialize the MMU. - */ - mr r3,r31 - mr r4,r30 - mr r5,r29 - mr r6,r28 - mr r7,r27 - bl machine_init - bl MMU_init - -/* - * Go back to running unmapped so we can load up new values - * and change to using our exception vectors. - * On the 8xx, all we have to do is invalidate the TLB to clear - * the old 8M byte TLB mappings and load the page table base register. - */ - /* The right way to do this would be to track it down through - * init's THREAD like the context switch code does, but this is - * easier......until someone changes init's static structures. - */ - lis r6, swapper_pg_dir@h - ori r6, r6, swapper_pg_dir@l - tophys(r6,r6) -#ifdef CONFIG_8xx_CPU6 - lis r4, cpu6_errata_word@h - ori r4, r4, cpu6_errata_word@l - li r3, 0x3980 - stw r3, 12(r4) - lwz r3, 12(r4) -#endif - mtspr SPRN_M_TWB, r6 - lis r4,2f@h - ori r4,r4,2f@l - tophys(r4,r4) - li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) - mtspr SPRN_SRR0,r4 - mtspr SPRN_SRR1,r3 - rfi -/* Load up the kernel context */ -2: - SYNC /* Force all PTE updates to finish */ - tlbia /* Clear all TLB entries */ - sync /* wait for tlbia/tlbie to finish */ - TLBSYNC /* ... on all CPUs */ - - /* set up the PTE pointers for the Abatron bdiGDB. - */ - tovirt(r6,r6) - lis r5, abatron_pteptrs@h - ori r5, r5, abatron_pteptrs@l - stw r5, 0xf0(r0) /* Must match your Abatron config file */ - tophys(r5,r5) - stw r6, 0(r5) - -/* Now turn on the MMU for real! */ - li r4,MSR_KERNEL - lis r3,start_kernel@h - ori r3,r3,start_kernel@l - mtspr SPRN_SRR0,r3 - mtspr SPRN_SRR1,r4 - rfi /* enable MMU and jump to start_kernel */ - -/* Set up the initial MMU state so we can do the first level of - * kernel initialization. This maps the first 8 MBytes of memory 1:1 - * virtual to physical. Also, set the cache mode since that is defined - * by TLB entries and perform any additional mapping (like of the IMMR). - * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, - * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by - * these mappings is mapped by page tables. - */ -initial_mmu: - tlbia /* Invalidate all TLB entries */ -#ifdef CONFIG_PIN_TLB - lis r8, MI_RSV4I@h - ori r8, r8, 0x1c00 -#else - li r8, 0 -#endif - mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ - -#ifdef CONFIG_PIN_TLB - lis r10, (MD_RSV4I | MD_RESETVAL)@h - ori r10, r10, 0x1c00 - mr r8, r10 -#else - lis r10, MD_RESETVAL@h -#endif -#ifndef CONFIG_8xx_COPYBACK - oris r10, r10, MD_WTDEF@h -#endif - mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ - - /* Now map the lower 8 Meg into the TLBs. For this quick hack, - * we can load the instruction and data TLB registers with the - * same values. - */ - lis r8, KERNELBASE@h /* Create vaddr for TLB */ - ori r8, r8, MI_EVALID /* Mark it valid */ - mtspr SPRN_MI_EPN, r8 - mtspr SPRN_MD_EPN, r8 - li r8, MI_PS8MEG /* Set 8M byte page */ - ori r8, r8, MI_SVALID /* Make it valid */ - mtspr SPRN_MI_TWC, r8 - mtspr SPRN_MD_TWC, r8 - li r8, MI_BOOTINIT /* Create RPN for address 0 */ - mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ - mtspr SPRN_MD_RPN, r8 - lis r8, MI_Kp@h /* Set the protection mode */ - mtspr SPRN_MI_AP, r8 - mtspr SPRN_MD_AP, r8 - - /* Map another 8 MByte at the IMMR to get the processor - * internal registers (among other things). - */ -#ifdef CONFIG_PIN_TLB - addi r10, r10, 0x0100 - mtspr SPRN_MD_CTR, r10 -#endif - mfspr r9, 638 /* Get current IMMR */ - andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ - - mr r8, r9 /* Create vaddr for TLB */ - ori r8, r8, MD_EVALID /* Mark it valid */ - mtspr SPRN_MD_EPN, r8 - li r8, MD_PS8MEG /* Set 8M byte page */ - ori r8, r8, MD_SVALID /* Make it valid */ - mtspr SPRN_MD_TWC, r8 - mr r8, r9 /* Create paddr for TLB */ - ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ - mtspr SPRN_MD_RPN, r8 - -#ifdef CONFIG_PIN_TLB - /* Map two more 8M kernel data pages. - */ - addi r10, r10, 0x0100 - mtspr SPRN_MD_CTR, r10 - - lis r8, KERNELBASE@h /* Create vaddr for TLB */ - addis r8, r8, 0x0080 /* Add 8M */ - ori r8, r8, MI_EVALID /* Mark it valid */ - mtspr SPRN_MD_EPN, r8 - li r9, MI_PS8MEG /* Set 8M byte page */ - ori r9, r9, MI_SVALID /* Make it valid */ - mtspr SPRN_MD_TWC, r9 - li r11, MI_BOOTINIT /* Create RPN for address 0 */ - addis r11, r11, 0x0080 /* Add 8M */ - mtspr SPRN_MD_RPN, r11 - - addi r10, r10, 0x0100 - mtspr SPRN_MD_CTR, r10 - - addis r8, r8, 0x0080 /* Add 8M */ - mtspr SPRN_MD_EPN, r8 - mtspr SPRN_MD_TWC, r9 - addis r11, r11, 0x0080 /* Add 8M */ - mtspr SPRN_MD_RPN, r11 -#endif - - /* Since the cache is enabled according to the information we - * just loaded into the TLB, invalidate and enable the caches here. - * We should probably check/set other modes....later. - */ - lis r8, IDC_INVALL@h - mtspr SPRN_IC_CST, r8 - mtspr SPRN_DC_CST, r8 - lis r8, IDC_ENABLE@h - mtspr SPRN_IC_CST, r8 -#ifdef CONFIG_8xx_COPYBACK - mtspr SPRN_DC_CST, r8 -#else - /* For a debug option, I left this here to easily enable - * the write through cache mode - */ - lis r8, DC_SFWT@h - mtspr SPRN_DC_CST, r8 - lis r8, IDC_ENABLE@h - mtspr SPRN_DC_CST, r8 -#endif - blr - - -/* - * Set up to use a given MMU context. - * r3 is context number, r4 is PGD pointer. - * - * We place the physical address of the new task page directory loaded - * into the MMU base register, and set the ASID compare register with - * the new "context." - */ -_GLOBAL(set_context) - -#ifdef CONFIG_BDI_SWITCH - /* Context switch the PTE pointer for the Abatron BDI2000. - * The PGDIR is passed as second argument. - */ - lis r5, KERNELBASE@h - lwz r5, 0xf0(r5) - stw r4, 0x4(r5) -#endif - -#ifdef CONFIG_8xx_CPU6 - lis r6, cpu6_errata_word@h - ori r6, r6, cpu6_errata_word@l - tophys (r4, r4) - li r7, 0x3980 - stw r7, 12(r6) - lwz r7, 12(r6) - mtspr SPRN_M_TWB, r4 /* Update MMU base address */ - li r7, 0x3380 - stw r7, 12(r6) - lwz r7, 12(r6) - mtspr SPRN_M_CASID, r3 /* Update context */ -#else - mtspr SPRN_M_CASID,r3 /* Update context */ - tophys (r4, r4) - mtspr SPRN_M_TWB, r4 /* and pgd */ -#endif - SYNC - blr - -#ifdef CONFIG_8xx_CPU6 -/* It's here because it is unique to the 8xx. - * It is important we get called with interrupts disabled. I used to - * do that, but it appears that all code that calls this already had - * interrupt disabled. - */ - .globl set_dec_cpu6 -set_dec_cpu6: - lis r7, cpu6_errata_word@h - ori r7, r7, cpu6_errata_word@l - li r4, 0x2c00 - stw r4, 8(r7) - lwz r4, 8(r7) - mtspr 22, r3 /* Update Decrementer */ - SYNC - blr -#endif - -/* - * We put a few things here that have to be page-aligned. - * This stuff goes at the beginning of the data segment, - * which is page-aligned. - */ - .data - .globl sdata -sdata: - .globl empty_zero_page -empty_zero_page: - .space 4096 - - .globl swapper_pg_dir -swapper_pg_dir: - .space 4096 - -/* - * This space gets a copy of optional info passed to us by the bootstrap - * Used to pass parameters into the kernel like root=/dev/sda1, etc. - */ - .globl cmd_line -cmd_line: - .space 512 - -/* Room for two PTE table poiners, usually the kernel and current user - * pointer to their respective root page table (pgdir). - */ -abatron_pteptrs: - .space 8 - -#ifdef CONFIG_8xx_CPU6 - .globl cpu6_errata_word -cpu6_errata_word: - .space 16 -#endif - diff --git a/arch/ppc/kernel/head_booke.h b/arch/ppc/kernel/head_booke.h deleted file mode 100644 index 166d597b6db2..000000000000 --- a/arch/ppc/kernel/head_booke.h +++ /dev/null @@ -1,308 +0,0 @@ -#ifndef __HEAD_BOOKE_H__ -#define __HEAD_BOOKE_H__ - -/* - * Macros used for common Book-e exception handling - */ - -#define SET_IVOR(vector_number, vector_label) \ - li r26,vector_label@l; \ - mtspr SPRN_IVOR##vector_number,r26; \ - sync - -#define NORMAL_EXCEPTION_PROLOG \ - mtspr SPRN_SPRG0,r10; /* save two registers to work with */\ - mtspr SPRN_SPRG1,r11; \ - mtspr SPRN_SPRG4W,r1; \ - mfcr r10; /* save CR in r10 for now */\ - mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ - andi. r11,r11,MSR_PR; \ - beq 1f; \ - mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\ - lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ - addi r1,r1,THREAD_SIZE; \ -1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ - mr r11,r1; \ - stw r10,_CCR(r11); /* save various registers */\ - stw r12,GPR12(r11); \ - stw r9,GPR9(r11); \ - mfspr r10,SPRN_SPRG0; \ - stw r10,GPR10(r11); \ - mfspr r12,SPRN_SPRG1; \ - stw r12,GPR11(r11); \ - mflr r10; \ - stw r10,_LINK(r11); \ - mfspr r10,SPRN_SPRG4R; \ - mfspr r12,SPRN_SRR0; \ - stw r10,GPR1(r11); \ - mfspr r9,SPRN_SRR1; \ - stw r10,0(r11); \ - rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ - stw r0,GPR0(r11); \ - SAVE_4GPRS(3, r11); \ - SAVE_2GPRS(7, r11) - -/* To handle the additional exception priority levels on 40x and Book-E - * processors we allocate a 4k stack per additional priority level. The various - * head_xxx.S files allocate space (exception_stack_top) for each priority's - * stack times the number of CPUs - * - * On 40x critical is the only additional level - * On 44x/e500 we have critical and machine check - * On e200 we have critical and debug (machine check occurs via critical) - * - * Additionally we reserve a SPRG for each priority level so we can free up a - * GPR to use as the base for indirect access to the exception stacks. This - * is necessary since the MMU is always on, for Book-E parts, and the stacks - * are offset from KERNELBASE. - * - */ -#define BOOKE_EXCEPTION_STACK_SIZE (8192) - -/* CRIT_SPRG only used in critical exception handling */ -#define CRIT_SPRG SPRN_SPRG2 -/* MCHECK_SPRG only used in machine check exception handling */ -#define MCHECK_SPRG SPRN_SPRG6W - -#define MCHECK_STACK_TOP (exception_stack_top - 4096) -#define CRIT_STACK_TOP (exception_stack_top) - -/* only on e200 for now */ -#define DEBUG_STACK_TOP (exception_stack_top - 4096) -#define DEBUG_SPRG SPRN_SPRG6W - -#ifdef CONFIG_SMP -#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ - mfspr r8,SPRN_PIR; \ - mulli r8,r8,BOOKE_EXCEPTION_STACK_SIZE; \ - neg r8,r8; \ - addis r8,r8,level##_STACK_TOP@ha; \ - addi r8,r8,level##_STACK_TOP@l -#else -#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ - lis r8,level##_STACK_TOP@h; \ - ori r8,r8,level##_STACK_TOP@l -#endif - -/* - * Exception prolog for critical/machine check exceptions. This is a - * little different from the normal exception prolog above since a - * critical/machine check exception can potentially occur at any point - * during normal exception processing. Thus we cannot use the same SPRG - * registers as the normal prolog above. Instead we use a portion of the - * critical/machine check exception stack at low physical addresses. - */ -#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \ - mtspr exc_level##_SPRG,r8; \ - BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \ - stw r10,GPR10-INT_FRAME_SIZE(r8); \ - stw r11,GPR11-INT_FRAME_SIZE(r8); \ - mfcr r10; /* save CR in r10 for now */\ - mfspr r11,exc_level_srr1; /* check whether user or kernel */\ - andi. r11,r11,MSR_PR; \ - mr r11,r8; \ - mfspr r8,exc_level##_SPRG; \ - beq 1f; \ - /* COMING FROM USER MODE */ \ - mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ - lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ - addi r11,r11,THREAD_SIZE; \ -1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ - stw r10,_CCR(r11); /* save various registers */\ - stw r12,GPR12(r11); \ - stw r9,GPR9(r11); \ - mflr r10; \ - stw r10,_LINK(r11); \ - mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ - stw r12,_DEAR(r11); /* since they may have had stuff */\ - mfspr r9,SPRN_ESR; /* in them at the point where the */\ - stw r9,_ESR(r11); /* exception was taken */\ - mfspr r12,exc_level_srr0; \ - stw r1,GPR1(r11); \ - mfspr r9,exc_level_srr1; \ - stw r1,0(r11); \ - mr r1,r11; \ - rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ - stw r0,GPR0(r11); \ - SAVE_4GPRS(3, r11); \ - SAVE_2GPRS(7, r11) - -#define CRITICAL_EXCEPTION_PROLOG \ - EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1) -#define DEBUG_EXCEPTION_PROLOG \ - EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1) -#define MCHECK_EXCEPTION_PROLOG \ - EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1) - -/* - * Exception vectors. - */ -#define START_EXCEPTION(label) \ - .align 5; \ -label: - -#define FINISH_EXCEPTION(func) \ - bl transfer_to_handler_full; \ - .long func; \ - .long ret_from_except_full - -#define EXCEPTION(n, label, hdlr, xfer) \ - START_EXCEPTION(label); \ - NORMAL_EXCEPTION_PROLOG; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - xfer(n, hdlr) - -#define CRITICAL_EXCEPTION(n, label, hdlr) \ - START_EXCEPTION(label); \ - CRITICAL_EXCEPTION_PROLOG; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ - NOCOPY, crit_transfer_to_handler, \ - ret_from_crit_exc) - -#define MCHECK_EXCEPTION(n, label, hdlr) \ - START_EXCEPTION(label); \ - MCHECK_EXCEPTION_PROLOG; \ - mfspr r5,SPRN_ESR; \ - stw r5,_ESR(r11); \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ - NOCOPY, mcheck_transfer_to_handler, \ - ret_from_mcheck_exc) - -#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ - li r10,trap; \ - stw r10,TRAP(r11); \ - lis r10,msr@h; \ - ori r10,r10,msr@l; \ - copyee(r10, r9); \ - bl tfer; \ - .long hdlr; \ - .long ret - -#define COPY_EE(d, s) rlwimi d,s,0,16,16 -#define NOCOPY(d, s) - -#define EXC_XFER_STD(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ - ret_from_except) - -#define EXC_XFER_EE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ - ret_from_except_full) - -#define EXC_XFER_EE_LITE(n, hdlr) \ - EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ - ret_from_except) - -/* Check for a single step debug exception while in an exception - * handler before state has been saved. This is to catch the case - * where an instruction that we are trying to single step causes - * an exception (eg ITLB/DTLB miss) and thus the first instruction of - * the exception handler generates a single step debug exception. - * - * If we get a debug trap on the first instruction of an exception handler, - * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is - * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). - * The exception handler was handling a non-critical interrupt, so it will - * save (and later restore) the MSR via SPRN_CSRR1, which will still have - * the MSR_DE bit set. - */ -#define DEBUG_EXCEPTION \ - START_EXCEPTION(Debug); \ - CRITICAL_EXCEPTION_PROLOG; \ - \ - /* \ - * If there is a single step or branch-taken exception in an \ - * exception entry sequence, it was probably meant to apply to \ - * the code where the exception occurred (since exception entry \ - * doesn't turn off DE automatically). We simulate the effect \ - * of turning off DE on entry to an exception handler by turning \ - * off DE in the CSRR1 value and clearing the debug status. \ - */ \ - mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ - andis. r10,r10,DBSR_IC@h; \ - beq+ 2f; \ - \ - lis r10,KERNELBASE@h; /* check if exception in vectors */ \ - ori r10,r10,KERNELBASE@l; \ - cmplw r12,r10; \ - blt+ 2f; /* addr below exception vectors */ \ - \ - lis r10,Debug@h; \ - ori r10,r10,Debug@l; \ - cmplw r12,r10; \ - bgt+ 2f; /* addr above exception vectors */ \ - \ - /* here it looks like we got an inappropriate debug exception. */ \ -1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ - lis r10,DBSR_IC@h; /* clear the IC event */ \ - mtspr SPRN_DBSR,r10; \ - /* restore state and get out */ \ - lwz r10,_CCR(r11); \ - lwz r0,GPR0(r11); \ - lwz r1,GPR1(r11); \ - mtcrf 0x80,r10; \ - mtspr SPRN_CSRR0,r12; \ - mtspr SPRN_CSRR1,r9; \ - lwz r9,GPR9(r11); \ - lwz r12,GPR12(r11); \ - mtspr CRIT_SPRG,r8; \ - BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \ - lwz r10,GPR10-INT_FRAME_SIZE(r8); \ - lwz r11,GPR11-INT_FRAME_SIZE(r8); \ - mfspr r8,CRIT_SPRG; \ - \ - rfci; \ - b .; \ - \ - /* continue normal handling for a critical exception... */ \ -2: mfspr r4,SPRN_DBSR; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) - -#define INSTRUCTION_STORAGE_EXCEPTION \ - START_EXCEPTION(InstructionStorage) \ - NORMAL_EXCEPTION_PROLOG; \ - mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ - stw r5,_ESR(r11); \ - mr r4,r12; /* Pass SRR0 as arg2 */ \ - li r5,0; /* Pass zero as arg3 */ \ - EXC_XFER_EE_LITE(0x0400, handle_page_fault) - -#define ALIGNMENT_EXCEPTION \ - START_EXCEPTION(Alignment) \ - NORMAL_EXCEPTION_PROLOG; \ - mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \ - stw r4,_DEAR(r11); \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_EE(0x0600, alignment_exception) - -#define PROGRAM_EXCEPTION \ - START_EXCEPTION(Program) \ - NORMAL_EXCEPTION_PROLOG; \ - mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \ - stw r4,_ESR(r11); \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_STD(0x0700, program_check_exception) - -#define DECREMENTER_EXCEPTION \ - START_EXCEPTION(Decrementer) \ - NORMAL_EXCEPTION_PROLOG; \ - lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \ - mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_LITE(0x0900, timer_interrupt) - -#define FP_UNAVAILABLE_EXCEPTION \ - START_EXCEPTION(FloatingPointUnavailable) \ - NORMAL_EXCEPTION_PROLOG; \ - bne load_up_fpu; /* if from user, just load it up */ \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) - -#endif /* __HEAD_BOOKE_H__ */ diff --git a/arch/ppc/kernel/machine_kexec.c b/arch/ppc/kernel/machine_kexec.c deleted file mode 100644 index a469ba438cbe..000000000000 --- a/arch/ppc/kernel/machine_kexec.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * machine_kexec.c - handle transition of Linux booting another kernel - * Copyright (C) 2002-2003 Eric Biederman - * - * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz - * - * This source code is licensed under the GNU General Public License, - * Version 2. See the file COPYING for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -typedef NORET_TYPE void (*relocate_new_kernel_t)( - unsigned long indirection_page, - unsigned long reboot_code_buffer, - unsigned long start_address) ATTRIB_NORET; - -extern const unsigned char relocate_new_kernel[]; -extern const unsigned int relocate_new_kernel_size; - -void machine_shutdown(void) -{ - if (ppc_md.machine_shutdown) - ppc_md.machine_shutdown(); -} - -void machine_crash_shutdown(struct pt_regs *regs) -{ - if (ppc_md.machine_crash_shutdown) - ppc_md.machine_crash_shutdown(); -} - -/* - * Do what every setup is needed on image and the - * reboot code buffer to allow us to avoid allocations - * later. - */ -int machine_kexec_prepare(struct kimage *image) -{ - if (ppc_md.machine_kexec_prepare) - return ppc_md.machine_kexec_prepare(image); - /* - * Fail if platform doesn't provide its own machine_kexec_prepare - * implementation. - */ - return -ENOSYS; -} - -void machine_kexec_cleanup(struct kimage *image) -{ - if (ppc_md.machine_kexec_cleanup) - ppc_md.machine_kexec_cleanup(image); -} - -/* - * Do not allocate memory (or fail in any way) in machine_kexec(). - * We are past the point of no return, committed to rebooting now. - */ -NORET_TYPE void machine_kexec(struct kimage *image) -{ - if (ppc_md.machine_kexec) - ppc_md.machine_kexec(image); - else { - /* - * Fall back to normal restart if platform doesn't provide - * its own kexec function, and user insist to kexec... - */ - machine_restart(NULL); - } - for(;;); -} - -/* - * This is a generic machine_kexec function suitable at least for - * non-OpenFirmware embedded platforms. - * It merely copies the image relocation code to the control page and - * jumps to it. - * A platform specific function may just call this one. - */ -void machine_kexec_simple(struct kimage *image) -{ - unsigned long page_list; - unsigned long reboot_code_buffer, reboot_code_buffer_phys; - relocate_new_kernel_t rnk; - - /* Interrupts aren't acceptable while we reboot */ - local_irq_disable(); - - page_list = image->head; - - /* we need both effective and real address here */ - reboot_code_buffer = - (unsigned long)page_address(image->control_code_page); - reboot_code_buffer_phys = virt_to_phys((void *)reboot_code_buffer); - - /* copy our kernel relocation code to the control code page */ - memcpy((void *)reboot_code_buffer, relocate_new_kernel, - relocate_new_kernel_size); - - flush_icache_range(reboot_code_buffer, - reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE); - printk(KERN_INFO "Bye!\n"); - - /* now call it */ - rnk = (relocate_new_kernel_t) reboot_code_buffer; - (*rnk)(page_list, reboot_code_buffer_phys, image->start); -} - diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S deleted file mode 100644 index d5e0dfc9ffec..000000000000 --- a/arch/ppc/kernel/misc.S +++ /dev/null @@ -1,868 +0,0 @@ -/* - * This file contains miscellaneous low-level functions. - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_8xx -#define ISYNC_8xx isync -#else -#define ISYNC_8xx -#endif - .text - - .align 5 -_GLOBAL(__delay) - cmpwi 0,r3,0 - mtctr r3 - beqlr -1: bdnz 1b - blr - -/* - * Returns (address we're running at) - (address we were linked at) - * for use before the text and data are mapped to KERNELBASE. - */ -_GLOBAL(reloc_offset) - mflr r0 - bl 1f -1: mflr r3 - lis r4,1b@ha - addi r4,r4,1b@l - subf r3,r4,r3 - mtlr r0 - blr - -/* - * add_reloc_offset(x) returns x + reloc_offset(). - */ -_GLOBAL(add_reloc_offset) - mflr r0 - bl 1f -1: mflr r5 - lis r4,1b@ha - addi r4,r4,1b@l - subf r5,r4,r5 - add r3,r3,r5 - mtlr r0 - blr - -/* - * sub_reloc_offset(x) returns x - reloc_offset(). - */ -_GLOBAL(sub_reloc_offset) - mflr r0 - bl 1f -1: mflr r5 - lis r4,1b@ha - addi r4,r4,1b@l - subf r5,r4,r5 - subf r3,r5,r3 - mtlr r0 - blr - -/* - * reloc_got2 runs through the .got2 section adding an offset - * to each entry. - */ -_GLOBAL(reloc_got2) - mflr r11 - lis r7,__got2_start@ha - addi r7,r7,__got2_start@l - lis r8,__got2_end@ha - addi r8,r8,__got2_end@l - subf r8,r7,r8 - srwi. r8,r8,2 - beqlr - mtctr r8 - bl 1f -1: mflr r0 - lis r4,1b@ha - addi r4,r4,1b@l - subf r0,r4,r0 - add r7,r0,r7 -2: lwz r0,0(r7) - add r0,r0,r3 - stw r0,0(r7) - addi r7,r7,4 - bdnz 2b - mtlr r11 - blr - -/* - * call_setup_cpu - call the setup_cpu function for this cpu - * r3 = data offset, r24 = cpu number - * - * Setup function is called with: - * r3 = data offset - * r4 = ptr to CPU spec (relocated) - */ -_GLOBAL(call_setup_cpu) - addis r4,r3,cur_cpu_spec@ha - addi r4,r4,cur_cpu_spec@l - lwz r4,0(r4) - add r4,r4,r3 - lwz r5,CPU_SPEC_SETUP(r4) - cmpi 0,r5,0 - add r5,r5,r3 - beqlr - mtctr r5 - bctr - -/* - * complement mask on the msr then "or" some values on. - * _nmask_and_or_msr(nmask, value_to_or) - */ -_GLOBAL(_nmask_and_or_msr) - mfmsr r0 /* Get current msr */ - andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ - or r0,r0,r4 /* Or on the bits in r4 (second parm) */ - SYNC /* Some chip revs have problems here... */ - mtmsr r0 /* Update machine state */ - isync - blr /* Done */ - - -/* - * Flush MMU TLB - */ -_GLOBAL(_tlbia) -#if defined(CONFIG_40x) - sync /* Flush to memory before changing mapping */ - tlbia - isync /* Flush shadow TLB */ -#elif defined(CONFIG_44x) - li r3,0 - sync - - /* Load high watermark */ - lis r4,tlb_44x_hwater@ha - lwz r5,tlb_44x_hwater@l(r4) - -1: tlbwe r3,r3,PPC44x_TLB_PAGEID - addi r3,r3,1 - cmpw 0,r3,r5 - ble 1b - - isync -#else /* !(CONFIG_40x || CONFIG_44x) */ -#if defined(CONFIG_SMP) - rlwinm r8,r1,0,0,18 - lwz r8,TI_CPU(r8) - oris r8,r8,10 - mfmsr r10 - SYNC - rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ - rlwinm r0,r0,0,28,26 /* clear DR */ - mtmsr r0 - SYNC_601 - isync - lis r9,mmu_hash_lock@h - ori r9,r9,mmu_hash_lock@l - tophys(r9,r9) -10: lwarx r7,0,r9 - cmpwi 0,r7,0 - bne- 10b - stwcx. r8,0,r9 - bne- 10b - sync - tlbia - sync - TLBSYNC - li r0,0 - stw r0,0(r9) /* clear mmu_hash_lock */ - mtmsr r10 - SYNC_601 - isync -#else /* CONFIG_SMP */ - sync - tlbia - sync -#endif /* CONFIG_SMP */ -#endif /* ! defined(CONFIG_40x) */ - blr - -/* - * Flush MMU TLB for a particular address - */ -_GLOBAL(_tlbie) -#if defined(CONFIG_40x) - /* We run the search with interrupts disabled because we have to change - * the PID and I don't want to preempt when that happens. - */ - mfmsr r5 - mfspr r6,SPRN_PID - wrteei 0 - mtspr SPRN_PID,r4 - tlbsx. r3, 0, r3 - mtspr SPRN_PID,r6 - wrtee r5 - bne 10f - sync - /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear. - * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate - * the TLB entry. */ - tlbwe r3, r3, TLB_TAG - isync -10: -#elif defined(CONFIG_44x) - mfspr r5,SPRN_MMUCR - rlwimi r5,r4,0,24,31 /* Set TID */ - - /* We have to run the search with interrupts disabled, even critical - * and debug interrupts (in fact the only critical exceptions we have - * are debug and machine check). Otherwise an interrupt which causes - * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */ - mfmsr r4 - lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha - addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l - andc r6,r4,r6 - mtmsr r6 - mtspr SPRN_MMUCR,r5 - tlbsx. r3, 0, r3 - mtmsr r4 - bne 10f - sync - /* There are only 64 TLB entries, so r3 < 64, - * which means bit 22, is clear. Since 22 is - * the V bit in the TLB_PAGEID, loading this - * value will invalidate the TLB entry. - */ - tlbwe r3, r3, PPC44x_TLB_PAGEID - isync -10: -#else /* !(CONFIG_40x || CONFIG_44x) */ -#if defined(CONFIG_SMP) - rlwinm r8,r1,0,0,18 - lwz r8,TI_CPU(r8) - oris r8,r8,11 - mfmsr r10 - SYNC - rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ - rlwinm r0,r0,0,28,26 /* clear DR */ - mtmsr r0 - SYNC_601 - isync - lis r9,mmu_hash_lock@h - ori r9,r9,mmu_hash_lock@l - tophys(r9,r9) -10: lwarx r7,0,r9 - cmpwi 0,r7,0 - bne- 10b - stwcx. r8,0,r9 - bne- 10b - eieio - tlbie r3 - sync - TLBSYNC - li r0,0 - stw r0,0(r9) /* clear mmu_hash_lock */ - mtmsr r10 - SYNC_601 - isync -#else /* CONFIG_SMP */ - tlbie r3 - sync -#endif /* CONFIG_SMP */ -#endif /* ! CONFIG_40x */ - blr - -/* - * Flush instruction cache. - * This is a no-op on the 601. - */ -_GLOBAL(flush_instruction_cache) -#if defined(CONFIG_8xx) - isync - lis r5, IDC_INVALL@h - mtspr SPRN_IC_CST, r5 -#elif defined(CONFIG_4xx) -#ifdef CONFIG_403GCX - li r3, 512 - mtctr r3 - lis r4, KERNELBASE@h -1: iccci 0, r4 - addi r4, r4, 16 - bdnz 1b -#else - lis r3, KERNELBASE@h - iccci 0,r3 -#endif -#else - mfspr r3,SPRN_PVR - rlwinm r3,r3,16,16,31 - cmpwi 0,r3,1 - beqlr /* for 601, do nothing */ - /* 603/604 processor - use invalidate-all bit in HID0 */ - mfspr r3,SPRN_HID0 - ori r3,r3,HID0_ICFI - mtspr SPRN_HID0,r3 -#endif /* CONFIG_8xx/4xx */ - isync - blr - -/* - * Write any modified data cache blocks out to memory - * and invalidate the corresponding instruction cache blocks. - * This is a no-op on the 601. - * - * __flush_icache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(__flush_icache_range) -BEGIN_FTR_SECTION - blr /* for 601, do nothing */ -END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) - li r5,L1_CACHE_BYTES-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,L1_CACHE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,L1_CACHE_BYTES - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,L1_CACHE_BYTES - bdnz 2b - sync /* additional sync needed on g4 */ - isync - blr -/* - * Write any modified data cache blocks out to memory. - * Does not invalidate the corresponding cache lines (especially for - * any corresponding instruction cache). - * - * clean_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(clean_dcache_range) - li r5,L1_CACHE_BYTES-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,L1_CACHE_SHIFT - beqlr - mtctr r4 - -1: dcbst 0,r3 - addi r3,r3,L1_CACHE_BYTES - bdnz 1b - sync /* wait for dcbst's to get to ram */ - blr - -/* - * Write any modified data cache blocks out to memory and invalidate them. - * Does not invalidate the corresponding instruction cache blocks. - * - * flush_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(flush_dcache_range) - li r5,L1_CACHE_BYTES-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,L1_CACHE_SHIFT - beqlr - mtctr r4 - -1: dcbf 0,r3 - addi r3,r3,L1_CACHE_BYTES - bdnz 1b - sync /* wait for dcbst's to get to ram */ - blr - -/* - * Like above, but invalidate the D-cache. This is used by the 8xx - * to invalidate the cache so the PPC core doesn't get stale data - * from the CPM (no cache snooping here :-). - * - * invalidate_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(invalidate_dcache_range) - li r5,L1_CACHE_BYTES-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,L1_CACHE_SHIFT - beqlr - mtctr r4 - -1: dcbi 0,r3 - addi r3,r3,L1_CACHE_BYTES - bdnz 1b - sync /* wait for dcbi's to get to ram */ - blr - -#ifdef CONFIG_NOT_COHERENT_CACHE -/* - * 40x cores have 8K or 16K dcache and 32 byte line size. - * 44x has a 32K dcache and 32 byte line size. - * 8xx has 1, 2, 4, 8K variants. - * For now, cover the worst case of the 44x. - * Must be called with external interrupts disabled. - */ -#define CACHE_NWAYS 64 -#define CACHE_NLINES 16 - -_GLOBAL(flush_dcache_all) - li r4, (2 * CACHE_NWAYS * CACHE_NLINES) - mtctr r4 - lis r5, KERNELBASE@h -1: lwz r3, 0(r5) /* Load one word from every line */ - addi r5, r5, L1_CACHE_BYTES - bdnz 1b - blr -#endif /* CONFIG_NOT_COHERENT_CACHE */ - -/* - * Flush a particular page from the data cache to RAM. - * Note: this is necessary because the instruction cache does *not* - * snoop from the data cache. - * This is a no-op on the 601 which has a unified cache. - * - * void __flush_dcache_icache(void *page) - */ -_GLOBAL(__flush_dcache_icache) -BEGIN_FTR_SECTION - blr /* for 601, do nothing */ -END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) - rlwinm r3,r3,0,0,19 /* Get page base address */ - li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ - mtctr r4 - mr r6,r3 -0: dcbst 0,r3 /* Write line to ram */ - addi r3,r3,L1_CACHE_BYTES - bdnz 0b - sync -#ifndef CONFIG_44x - /* We don't flush the icache on 44x. Those have a virtual icache - * and we don't have access to the virtual address here (it's - * not the page vaddr but where it's mapped in user space). The - * flushing of the icache on these is handled elsewhere, when - * a change in the address space occurs, before returning to - * user space - */ - mtctr r4 -1: icbi 0,r6 - addi r6,r6,L1_CACHE_BYTES - bdnz 1b - sync - isync -#endif /* CONFIG_44x */ - blr - -/* - * Flush a particular page from the data cache to RAM, identified - * by its physical address. We turn off the MMU so we can just use - * the physical address (this may be a highmem page without a kernel - * mapping). - * - * void __flush_dcache_icache_phys(unsigned long physaddr) - */ -_GLOBAL(__flush_dcache_icache_phys) -BEGIN_FTR_SECTION - blr /* for 601, do nothing */ -END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) - mfmsr r10 - rlwinm r0,r10,0,28,26 /* clear DR */ - mtmsr r0 - isync - rlwinm r3,r3,0,0,19 /* Get page base address */ - li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ - mtctr r4 - mr r6,r3 -0: dcbst 0,r3 /* Write line to ram */ - addi r3,r3,L1_CACHE_BYTES - bdnz 0b - sync - mtctr r4 -1: icbi 0,r6 - addi r6,r6,L1_CACHE_BYTES - bdnz 1b - sync - mtmsr r10 /* restore DR */ - isync - blr - -/* - * Clear pages using the dcbz instruction, which doesn't cause any - * memory traffic (except to write out any cache lines which get - * displaced). This only works on cacheable memory. - * - * void clear_pages(void *page, int order) ; - */ -_GLOBAL(clear_pages) - li r0,4096/L1_CACHE_BYTES - slw r0,r0,r4 - mtctr r0 -#ifdef CONFIG_8xx - li r4, 0 -1: stw r4, 0(r3) - stw r4, 4(r3) - stw r4, 8(r3) - stw r4, 12(r3) -#else -1: dcbz 0,r3 -#endif - addi r3,r3,L1_CACHE_BYTES - bdnz 1b - blr - -/* - * Copy a whole page. We use the dcbz instruction on the destination - * to reduce memory traffic (it eliminates the unnecessary reads of - * the destination into cache). This requires that the destination - * is cacheable. - */ -#define COPY_16_BYTES \ - lwz r6,4(r4); \ - lwz r7,8(r4); \ - lwz r8,12(r4); \ - lwzu r9,16(r4); \ - stw r6,4(r3); \ - stw r7,8(r3); \ - stw r8,12(r3); \ - stwu r9,16(r3) - -_GLOBAL(copy_page) - addi r3,r3,-4 - addi r4,r4,-4 - -#ifdef CONFIG_8xx - /* don't use prefetch on 8xx */ - li r0,4096/L1_CACHE_BYTES - mtctr r0 -1: COPY_16_BYTES - bdnz 1b - blr - -#else /* not 8xx, we can prefetch */ - li r5,4 - -#if MAX_COPY_PREFETCH > 1 - li r0,MAX_COPY_PREFETCH - li r11,4 - mtctr r0 -11: dcbt r11,r4 - addi r11,r11,L1_CACHE_BYTES - bdnz 11b -#else /* MAX_COPY_PREFETCH == 1 */ - dcbt r5,r4 - li r11,L1_CACHE_BYTES+4 -#endif /* MAX_COPY_PREFETCH */ - li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH - crclr 4*cr0+eq -2: - mtctr r0 -1: - dcbt r11,r4 - dcbz r5,r3 - COPY_16_BYTES -#if L1_CACHE_BYTES >= 32 - COPY_16_BYTES -#if L1_CACHE_BYTES >= 64 - COPY_16_BYTES - COPY_16_BYTES -#if L1_CACHE_BYTES >= 128 - COPY_16_BYTES - COPY_16_BYTES - COPY_16_BYTES - COPY_16_BYTES -#endif -#endif -#endif - bdnz 1b - beqlr - crnot 4*cr0+eq,4*cr0+eq - li r0,MAX_COPY_PREFETCH - li r11,4 - b 2b -#endif /* CONFIG_8xx */ - -/* - * void atomic_clear_mask(atomic_t mask, atomic_t *addr) - * void atomic_set_mask(atomic_t mask, atomic_t *addr); - */ -_GLOBAL(atomic_clear_mask) -10: lwarx r5,0,r4 - andc r5,r5,r3 - PPC405_ERR77(0,r4) - stwcx. r5,0,r4 - bne- 10b - blr -_GLOBAL(atomic_set_mask) -10: lwarx r5,0,r4 - or r5,r5,r3 - PPC405_ERR77(0,r4) - stwcx. r5,0,r4 - bne- 10b - blr - -/* - * I/O string operations - * - * insb(port, buf, len) - * outsb(port, buf, len) - * insw(port, buf, len) - * outsw(port, buf, len) - * insl(port, buf, len) - * outsl(port, buf, len) - * insw_ns(port, buf, len) - * outsw_ns(port, buf, len) - * insl_ns(port, buf, len) - * outsl_ns(port, buf, len) - * - * The *_ns versions don't do byte-swapping. - */ -_GLOBAL(_insb) - cmpwi 0,r5,0 - mtctr r5 - subi r4,r4,1 - blelr- -00: lbz r5,0(r3) -01: eieio -02: stbu r5,1(r4) - ISYNC_8xx - .section .fixup,"ax" -03: blr - .text - .section __ex_table, "a" - .align 2 - .long 00b, 03b - .long 01b, 03b - .long 02b, 03b - .text - bdnz 00b - blr - -_GLOBAL(_outsb) - cmpwi 0,r5,0 - mtctr r5 - subi r4,r4,1 - blelr- -00: lbzu r5,1(r4) -01: stb r5,0(r3) -02: eieio - ISYNC_8xx - .section .fixup,"ax" -03: blr - .text - .section __ex_table, "a" - .align 2 - .long 00b, 03b - .long 01b, 03b - .long 02b, 03b - .text - bdnz 00b - blr - -_GLOBAL(_insw_ns) - cmpwi 0,r5,0 - mtctr r5 - subi r4,r4,2 - blelr- -00: lhz r5,0(r3) -01: eieio -02: sthu r5,2(r4) - ISYNC_8xx - .section .fixup,"ax" -03: blr - .text - .section __ex_table, "a" - .align 2 - .long 00b, 03b - .long 01b, 03b - .long 02b, 03b - .text - bdnz 00b - blr - -_GLOBAL(_outsw_ns) - cmpwi 0,r5,0 - mtctr r5 - subi r4,r4,2 - blelr- -00: lhzu r5,2(r4) -01: sth r5,0(r3) -02: eieio - ISYNC_8xx - .section .fixup,"ax" -03: blr - .text - .section __ex_table, "a" - .align 2 - .long 00b, 03b - .long 01b, 03b - .long 02b, 03b - .text - bdnz 00b - blr - -_GLOBAL(_insl_ns) - cmpwi 0,r5,0 - mtctr r5 - subi r4,r4,4 - blelr- -00: lwz r5,0(r3) -01: eieio -02: stwu r5,4(r4) - ISYNC_8xx - .section .fixup,"ax" -03: blr - .text - .section __ex_table, "a" - .align 2 - .long 00b, 03b - .long 01b, 03b - .long 02b, 03b - .text - bdnz 00b - blr - -_GLOBAL(_outsl_ns) - cmpwi 0,r5,0 - mtctr r5 - subi r4,r4,4 - blelr- -00: lwzu r5,4(r4) -01: stw r5,0(r3) -02: eieio - ISYNC_8xx - .section .fixup,"ax" -03: blr - .text - .section __ex_table, "a" - .align 2 - .long 00b, 03b - .long 01b, 03b - .long 02b, 03b - .text - bdnz 00b - blr - -/* - * Extended precision shifts. - * - * Updated to be valid for shift counts from 0 to 63 inclusive. - * -- Gabriel - * - * R3/R4 has 64 bit value - * R5 has shift count - * result in R3/R4 - * - * ashrdi3: arithmetic right shift (sign propagation) - * lshrdi3: logical right shift - * ashldi3: left shift - */ -_GLOBAL(__ashrdi3) - subfic r6,r5,32 - srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count - addi r7,r5,32 # could be xori, or addi with -32 - slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) - rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 - sraw r7,r3,r7 # t2 = MSW >> (count-32) - or r4,r4,r6 # LSW |= t1 - slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 - sraw r3,r3,r5 # MSW = MSW >> count - or r4,r4,r7 # LSW |= t2 - blr - -_GLOBAL(__ashldi3) - subfic r6,r5,32 - slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count - addi r7,r5,32 # could be xori, or addi with -32 - srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) - slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) - or r3,r3,r6 # MSW |= t1 - slw r4,r4,r5 # LSW = LSW << count - or r3,r3,r7 # MSW |= t2 - blr - -_GLOBAL(__lshrdi3) - subfic r6,r5,32 - srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count - addi r7,r5,32 # could be xori, or addi with -32 - slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) - srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) - or r4,r4,r6 # LSW |= t1 - srw r3,r3,r5 # MSW = MSW >> count - or r4,r4,r7 # LSW |= t2 - blr - -_GLOBAL(abs) - srawi r4,r3,31 - xor r3,r3,r4 - sub r3,r3,r4 - blr - -_GLOBAL(_get_SP) - mr r3,r1 /* Close enough */ - blr - -/* - * Create a kernel thread - * kernel_thread(fn, arg, flags) - */ -_GLOBAL(kernel_thread) - stwu r1,-16(r1) - stw r30,8(r1) - stw r31,12(r1) - mr r30,r3 /* function */ - mr r31,r4 /* argument */ - ori r3,r5,CLONE_VM /* flags */ - oris r3,r3,CLONE_UNTRACED>>16 - li r4,0 /* new sp (unused) */ - li r0,__NR_clone - sc - cmpwi 0,r3,0 /* parent or child? */ - bne 1f /* return if parent */ - li r0,0 /* make top-level stack frame */ - stwu r0,-16(r1) - mtlr r30 /* fn addr in lr */ - mr r3,r31 /* load arg and call fn */ - PPC440EP_ERR42 - blrl - li r0,__NR_exit /* exit if function returns */ - li r3,0 - sc -1: lwz r30,8(r1) - lwz r31,12(r1) - addi r1,r1,16 - blr - -_GLOBAL(kernel_execve) - li r0,__NR_execve - sc - bnslr - neg r3,r3 - blr - -/* - * This routine is just here to keep GCC happy - sigh... - */ -_GLOBAL(__main) - blr - diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c deleted file mode 100644 index df3ef6db072c..000000000000 --- a/arch/ppc/kernel/pci.c +++ /dev/null @@ -1,1233 +0,0 @@ -/* - * Common prep/chrp pci routines. -- Cort - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -unsigned long isa_io_base = 0; -unsigned long isa_mem_base = 0; -unsigned long pci_dram_offset = 0; -int pcibios_assign_bus_offset = 1; - -void pcibios_make_OF_bus_map(void); - -static int pci_relocate_bridge_resource(struct pci_bus *bus, int i); -static int probe_resource(struct pci_bus *parent, struct resource *pr, - struct resource *res, struct resource **conflict); -static void update_bridge_base(struct pci_bus *bus, int i); -static void pcibios_fixup_resources(struct pci_dev* dev); -static void fixup_broken_pcnet32(struct pci_dev* dev); -static int reparent_resources(struct resource *parent, struct resource *res); -static void fixup_cpc710_pci64(struct pci_dev* dev); - -/* By default, we don't re-assign bus numbers. - */ -int pci_assign_all_buses; - -struct pci_controller* hose_head; -struct pci_controller** hose_tail = &hose_head; - -static int pci_bus_count; - -static void -fixup_broken_pcnet32(struct pci_dev* dev) -{ - if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { - dev->vendor = PCI_VENDOR_ID_AMD; - pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); - -static void -fixup_cpc710_pci64(struct pci_dev* dev) -{ - /* Hide the PCI64 BARs from the kernel as their content doesn't - * fit well in the resource management - */ - dev->resource[0].start = dev->resource[0].end = 0; - dev->resource[0].flags = 0; - dev->resource[1].start = dev->resource[1].end = 0; - dev->resource[1].flags = 0; -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64); - -static void -pcibios_fixup_resources(struct pci_dev *dev) -{ - struct pci_controller* hose = (struct pci_controller *)dev->sysdata; - int i; - unsigned long offset; - - if (!hose) { - printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev)); - return; - } - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - struct resource *res = dev->resource + i; - if (!res->flags) - continue; - if (res->end == 0xffffffff) { - DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n", - pci_name(dev), i, - (unsigned long long)res->start, - (unsigned long long)res->end); - res->end -= res->start; - res->start = 0; - res->flags |= IORESOURCE_UNSET; - continue; - } - offset = 0; - if (res->flags & IORESOURCE_MEM) { - offset = hose->pci_mem_offset; - } else if (res->flags & IORESOURCE_IO) { - offset = (unsigned long) hose->io_base_virt - - isa_io_base; - } - if (offset != 0) { - res->start += offset; - res->end += offset; -#ifdef DEBUG - printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n", - i, res->flags, pci_name(dev), - res->start - offset, res->start); -#endif - } - } - - /* Call machine specific resource fixup */ - if (ppc_md.pcibios_fixup_resources) - ppc_md.pcibios_fixup_resources(dev); -} -DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); - -void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, - struct resource *res) -{ - unsigned long offset = 0; - struct pci_controller *hose = dev->sysdata; - - if (hose && res->flags & IORESOURCE_IO) - offset = (unsigned long)hose->io_base_virt - isa_io_base; - else if (hose && res->flags & IORESOURCE_MEM) - offset = hose->pci_mem_offset; - region->start = res->start - offset; - region->end = res->end - offset; -} -EXPORT_SYMBOL(pcibios_resource_to_bus); - -void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, - struct pci_bus_region *region) -{ - unsigned long offset = 0; - struct pci_controller *hose = dev->sysdata; - - if (hose && res->flags & IORESOURCE_IO) - offset = (unsigned long)hose->io_base_virt - isa_io_base; - else if (hose && res->flags & IORESOURCE_MEM) - offset = hose->pci_mem_offset; - res->start = region->start + offset; - res->end = region->end + offset; -} -EXPORT_SYMBOL(pcibios_bus_to_resource); - -/* - * We need to avoid collisions with `mirrored' VGA ports - * and other strange ISA hardware, so we always want the - * addresses to be allocated in the 0x000-0x0ff region - * modulo 0x400. - * - * Why? Because some silly external IO cards only decode - * the low 10 bits of the IO address. The 0x00-0xff region - * is reserved for motherboard devices that decode all 16 - * bits, so it's ok to allocate at, say, 0x2800-0x28ff, - * but we want to try to avoid allocating at 0x2900-0x2bff - * which might have be mirrored at 0x0100-0x03ff.. - */ -void pcibios_align_resource(void *data, struct resource *res, - resource_size_t size, resource_size_t align) -{ - struct pci_dev *dev = data; - - if (res->flags & IORESOURCE_IO) { - resource_size_t start = res->start; - - if (size > 0x100) { - printk(KERN_ERR "PCI: I/O Region %s/%d too large" - " (%lld bytes)\n", pci_name(dev), - dev->resource - res, (unsigned long long)size); - } - - if (start & 0x300) { - start = (start + 0x3ff) & ~0x3ff; - res->start = start; - } - } -} -EXPORT_SYMBOL(pcibios_align_resource); - -/* - * Handle resources of PCI devices. If the world were perfect, we could - * just allocate all the resource regions and do nothing more. It isn't. - * On the other hand, we cannot just re-allocate all devices, as it would - * require us to know lots of host bridge internals. So we attempt to - * keep as much of the original configuration as possible, but tweak it - * when it's found to be wrong. - * - * Known BIOS problems we have to work around: - * - I/O or memory regions not configured - * - regions configured, but not enabled in the command register - * - bogus I/O addresses above 64K used - * - expansion ROMs left enabled (this may sound harmless, but given - * the fact the PCI specs explicitly allow address decoders to be - * shared between expansion ROMs and other resource regions, it's - * at least dangerous) - * - * Our solution: - * (1) Allocate resources for all buses behind PCI-to-PCI bridges. - * This gives us fixed barriers on where we can allocate. - * (2) Allocate resources for all enabled devices. If there is - * a collision, just mark the resource as unallocated. Also - * disable expansion ROMs during this step. - * (3) Try to allocate resources for disabled devices. If the - * resources were assigned correctly, everything goes well, - * if they weren't, they won't disturb allocation of other - * resources. - * (4) Assign new addresses to resources which were either - * not configured at all or misconfigured. If explicitly - * requested by the user, configure expansion ROM address - * as well. - */ - -static void __init -pcibios_allocate_bus_resources(struct list_head *bus_list) -{ - struct pci_bus *bus; - int i; - struct resource *res, *pr; - - /* Depth-First Search on bus tree */ - list_for_each_entry(bus, bus_list, node) { - for (i = 0; i < 4; ++i) { - if ((res = bus->resource[i]) == NULL || !res->flags - || res->start > res->end) - continue; - if (bus->parent == NULL) - pr = (res->flags & IORESOURCE_IO)? - &ioport_resource: &iomem_resource; - else { - pr = pci_find_parent_resource(bus->self, res); - if (pr == res) { - /* this happens when the generic PCI - * code (wrongly) decides that this - * bridge is transparent -- paulus - */ - continue; - } - } - - DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n", - (unsigned long long)res->start, - (unsigned long long)res->end, res->flags, pr); - if (pr) { - if (request_resource(pr, res) == 0) - continue; - /* - * Must be a conflict with an existing entry. - * Move that entry (or entries) under the - * bridge resource and try again. - */ - if (reparent_resources(pr, res) == 0) - continue; - } - printk(KERN_ERR "PCI: Cannot allocate resource region " - "%d of PCI bridge %d\n", i, bus->number); - if (pci_relocate_bridge_resource(bus, i)) - bus->resource[i] = NULL; - } - pcibios_allocate_bus_resources(&bus->children); - } -} - -/* - * Reparent resource children of pr that conflict with res - * under res, and make res replace those children. - */ -static int __init -reparent_resources(struct resource *parent, struct resource *res) -{ - struct resource *p, **pp; - struct resource **firstpp = NULL; - - for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { - if (p->end < res->start) - continue; - if (res->end < p->start) - break; - if (p->start < res->start || p->end > res->end) - return -1; /* not completely contained */ - if (firstpp == NULL) - firstpp = pp; - } - if (firstpp == NULL) - return -1; /* didn't find any conflicting entries? */ - res->parent = parent; - res->child = *firstpp; - res->sibling = *pp; - *firstpp = res; - *pp = NULL; - for (p = res->child; p != NULL; p = p->sibling) { - p->parent = res; - DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n", - p->name, (unsigned long long)p->start, - (unsigned long long)p->end, res->name); - } - return 0; -} - -/* - * A bridge has been allocated a range which is outside the range - * of its parent bridge, so it needs to be moved. - */ -static int __init -pci_relocate_bridge_resource(struct pci_bus *bus, int i) -{ - struct resource *res, *pr, *conflict; - unsigned long try, size; - int j; - struct pci_bus *parent = bus->parent; - - if (parent == NULL) { - /* shouldn't ever happen */ - printk(KERN_ERR "PCI: can't move host bridge resource\n"); - return -1; - } - res = bus->resource[i]; - if (res == NULL) - return -1; - pr = NULL; - for (j = 0; j < 4; j++) { - struct resource *r = parent->resource[j]; - if (!r) - continue; - if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) - continue; - if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) { - pr = r; - break; - } - if (res->flags & IORESOURCE_PREFETCH) - pr = r; - } - if (pr == NULL) - return -1; - size = res->end - res->start; - if (pr->start > pr->end || size > pr->end - pr->start) - return -1; - try = pr->end; - for (;;) { - res->start = try - size; - res->end = try; - if (probe_resource(bus->parent, pr, res, &conflict) == 0) - break; - if (conflict->start <= pr->start + size) - return -1; - try = conflict->start - 1; - } - if (request_resource(pr, res)) { - DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n", - (unsigned long long)res->start, - (unsigned long long)res->end); - return -1; /* "can't happen" */ - } - update_bridge_base(bus, i); - printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n", - bus->number, i, (unsigned long long)res->start, - (unsigned long long)res->end); - return 0; -} - -static int __init -probe_resource(struct pci_bus *parent, struct resource *pr, - struct resource *res, struct resource **conflict) -{ - struct pci_bus *bus; - struct pci_dev *dev; - struct resource *r; - int i; - - for (r = pr->child; r != NULL; r = r->sibling) { - if (r->end >= res->start && res->end >= r->start) { - *conflict = r; - return 1; - } - } - list_for_each_entry(bus, &parent->children, node) { - for (i = 0; i < 4; ++i) { - if ((r = bus->resource[i]) == NULL) - continue; - if (!r->flags || r->start > r->end || r == res) - continue; - if (pci_find_parent_resource(bus->self, r) != pr) - continue; - if (r->end >= res->start && res->end >= r->start) { - *conflict = r; - return 1; - } - } - } - list_for_each_entry(dev, &parent->devices, bus_list) { - for (i = 0; i < 6; ++i) { - r = &dev->resource[i]; - if (!r->flags || (r->flags & IORESOURCE_UNSET)) - continue; - if (pci_find_parent_resource(dev, r) != pr) - continue; - if (r->end >= res->start && res->end >= r->start) { - *conflict = r; - return 1; - } - } - } - return 0; -} - -static void __init -update_bridge_base(struct pci_bus *bus, int i) -{ - struct resource *res = bus->resource[i]; - u8 io_base_lo, io_limit_lo; - u16 mem_base, mem_limit; - u16 cmd; - unsigned long start, end, off; - struct pci_dev *dev = bus->self; - struct pci_controller *hose = dev->sysdata; - - if (!hose) { - printk("update_bridge_base: no hose?\n"); - return; - } - pci_read_config_word(dev, PCI_COMMAND, &cmd); - pci_write_config_word(dev, PCI_COMMAND, - cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); - if (res->flags & IORESOURCE_IO) { - off = (unsigned long) hose->io_base_virt - isa_io_base; - start = res->start - off; - end = res->end - off; - io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK; - io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK; - if (end > 0xffff) { - pci_write_config_word(dev, PCI_IO_BASE_UPPER16, - start >> 16); - pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, - end >> 16); - io_base_lo |= PCI_IO_RANGE_TYPE_32; - } else - io_base_lo |= PCI_IO_RANGE_TYPE_16; - pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo); - pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo); - - } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) - == IORESOURCE_MEM) { - off = hose->pci_mem_offset; - mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK; - mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK; - pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base); - pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit); - - } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) - == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) { - off = hose->pci_mem_offset; - mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK; - mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK; - pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base); - pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); - - } else { - DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n", - pci_name(dev), i, res->flags); - } - pci_write_config_word(dev, PCI_COMMAND, cmd); -} - -static inline void alloc_resource(struct pci_dev *dev, int idx) -{ - struct resource *pr, *r = &dev->resource[idx]; - - DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n", - pci_name(dev), idx, (unsigned long long)r->start, - (unsigned long long)r->end, r->flags); - pr = pci_find_parent_resource(dev, r); - if (!pr || request_resource(pr, r) < 0) { - printk(KERN_ERR "PCI: Cannot allocate resource region %d" - " of device %s\n", idx, pci_name(dev)); - if (pr) - DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n", - pr, (unsigned long long)pr->start, - (unsigned long long)pr->end, pr->flags); - /* We'll assign a new address later */ - r->flags |= IORESOURCE_UNSET; - r->end -= r->start; - r->start = 0; - } -} - -static void __init -pcibios_allocate_resources(int pass) -{ - struct pci_dev *dev = NULL; - int idx, disabled; - u16 command; - struct resource *r; - - for_each_pci_dev(dev) { - pci_read_config_word(dev, PCI_COMMAND, &command); - for (idx = 0; idx < 6; idx++) { - r = &dev->resource[idx]; - if (r->parent) /* Already allocated */ - continue; - if (!r->flags || (r->flags & IORESOURCE_UNSET)) - continue; /* Not assigned at all */ - if (r->flags & IORESOURCE_IO) - disabled = !(command & PCI_COMMAND_IO); - else - disabled = !(command & PCI_COMMAND_MEMORY); - if (pass == disabled) - alloc_resource(dev, idx); - } - if (pass) - continue; - r = &dev->resource[PCI_ROM_RESOURCE]; - if (r->flags & IORESOURCE_ROM_ENABLE) { - /* Turn the ROM off, leave the resource region, but keep it unregistered. */ - u32 reg; - DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); - r->flags &= ~IORESOURCE_ROM_ENABLE; - pci_read_config_dword(dev, dev->rom_base_reg, ®); - pci_write_config_dword(dev, dev->rom_base_reg, - reg & ~PCI_ROM_ADDRESS_ENABLE); - } - } -} - -static void __init -pcibios_assign_resources(void) -{ - struct pci_dev *dev = NULL; - int idx; - struct resource *r; - - for_each_pci_dev(dev) { - int class = dev->class >> 8; - - /* Don't touch classless devices and host bridges */ - if (!class || class == PCI_CLASS_BRIDGE_HOST) - continue; - - for (idx = 0; idx < 6; idx++) { - r = &dev->resource[idx]; - - /* - * We shall assign a new address to this resource, - * either because the BIOS (sic) forgot to do so - * or because we have decided the old address was - * unusable for some reason. - */ - if ((r->flags & IORESOURCE_UNSET) && r->end && - (!ppc_md.pcibios_enable_device_hook || - !ppc_md.pcibios_enable_device_hook(dev, 1))) { - r->flags &= ~IORESOURCE_UNSET; - pci_assign_resource(dev, idx); - } - } - -#if 0 /* don't assign ROMs */ - r = &dev->resource[PCI_ROM_RESOURCE]; - r->end -= r->start; - r->start = 0; - if (r->end) - pci_assign_resource(dev, PCI_ROM_RESOURCE); -#endif - } -} - - -static int next_controller_index; - -struct pci_controller * __init -pcibios_alloc_controller(void) -{ - struct pci_controller *hose; - - hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose)); - memset(hose, 0, sizeof(struct pci_controller)); - - *hose_tail = hose; - hose_tail = &hose->next; - - hose->index = next_controller_index++; - - return hose; -} - -void pcibios_make_OF_bus_map(void) -{ -} - -static int __init -pcibios_init(void) -{ - struct pci_controller *hose; - struct pci_bus *bus; - int next_busno; - - printk(KERN_INFO "PCI: Probing PCI hardware\n"); - - /* Scan all of the recorded PCI controllers. */ - for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { - if (pci_assign_all_buses) - hose->first_busno = next_busno; - hose->last_busno = 0xff; - bus = pci_scan_bus(hose->first_busno, hose->ops, hose); - hose->last_busno = bus->subordinate; - if (pci_assign_all_buses || next_busno <= hose->last_busno) - next_busno = hose->last_busno + pcibios_assign_bus_offset; - } - pci_bus_count = next_busno; - - /* OpenFirmware based machines need a map of OF bus - * numbers vs. kernel bus numbers since we may have to - * remap them. - */ - if (pci_assign_all_buses && have_of) - pcibios_make_OF_bus_map(); - - /* Do machine dependent PCI interrupt routing */ - if (ppc_md.pci_swizzle && ppc_md.pci_map_irq) - pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq); - - /* Call machine dependent fixup */ - if (ppc_md.pcibios_fixup) - ppc_md.pcibios_fixup(); - - /* Allocate and assign resources */ - pcibios_allocate_bus_resources(&pci_root_buses); - pcibios_allocate_resources(0); - pcibios_allocate_resources(1); - pcibios_assign_resources(); - - /* Call machine dependent post-init code */ - if (ppc_md.pcibios_after_init) - ppc_md.pcibios_after_init(); - - return 0; -} - -subsys_initcall(pcibios_init); - -unsigned char __init -common_swizzle(struct pci_dev *dev, unsigned char *pinp) -{ - struct pci_controller *hose = dev->sysdata; - - if (dev->bus->number != hose->first_busno) { - u8 pin = *pinp; - do { - pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); - /* Move up the chain of bridges. */ - dev = dev->bus->self; - } while (dev->bus->self); - *pinp = pin; - - /* The slot is the idsel of the last bridge. */ - } - return PCI_SLOT(dev->devfn); -} - -unsigned long resource_fixup(struct pci_dev * dev, struct resource * res, - unsigned long start, unsigned long size) -{ - return start; -} - -void __init pcibios_fixup_bus(struct pci_bus *bus) -{ - struct pci_controller *hose = (struct pci_controller *) bus->sysdata; - unsigned long io_offset; - struct resource *res; - int i; - - io_offset = (unsigned long)hose->io_base_virt - isa_io_base; - if (bus->parent == NULL) { - /* This is a host bridge - fill in its resources */ - hose->bus = bus; - - bus->resource[0] = res = &hose->io_resource; - if (!res->flags) { - if (io_offset) - printk(KERN_ERR "I/O resource not set for host" - " bridge %d\n", hose->index); - res->start = 0; - res->end = IO_SPACE_LIMIT; - res->flags = IORESOURCE_IO; - } - res->start += io_offset; - res->end += io_offset; - - for (i = 0; i < 3; ++i) { - res = &hose->mem_resources[i]; - if (!res->flags) { - if (i > 0) - continue; - printk(KERN_ERR "Memory resource not set for " - "host bridge %d\n", hose->index); - res->start = hose->pci_mem_offset; - res->end = ~0U; - res->flags = IORESOURCE_MEM; - } - bus->resource[i+1] = res; - } - } else { - /* This is a subordinate bridge */ - pci_read_bridge_bases(bus); - - for (i = 0; i < 4; ++i) { - if ((res = bus->resource[i]) == NULL) - continue; - if (!res->flags) - continue; - if (io_offset && (res->flags & IORESOURCE_IO)) { - res->start += io_offset; - res->end += io_offset; - } else if (hose->pci_mem_offset - && (res->flags & IORESOURCE_MEM)) { - res->start += hose->pci_mem_offset; - res->end += hose->pci_mem_offset; - } - } - } - - if (ppc_md.pcibios_fixup_bus) - ppc_md.pcibios_fixup_bus(bus); -} - -char __init *pcibios_setup(char *str) -{ - return str; -} - -/* the next one is stolen from the alpha port... */ -void __init -pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); - /* XXX FIXME - update OF device tree node interrupt property */ -} - -int pcibios_enable_device(struct pci_dev *dev, int mask) -{ - if (ppc_md.pcibios_enable_device_hook) - if (ppc_md.pcibios_enable_device_hook(dev, 0)) - return -EINVAL; - - return pci_enable_resources(dev, mask); -} - -struct pci_controller* -pci_bus_to_hose(int bus) -{ - struct pci_controller* hose = hose_head; - - for (; hose; hose = hose->next) - if (bus >= hose->first_busno && bus <= hose->last_busno) - return hose; - return NULL; -} - -void __iomem * -pci_bus_io_base(unsigned int bus) -{ - struct pci_controller *hose; - - hose = pci_bus_to_hose(bus); - if (!hose) - return NULL; - return hose->io_base_virt; -} - -unsigned long -pci_bus_io_base_phys(unsigned int bus) -{ - struct pci_controller *hose; - - hose = pci_bus_to_hose(bus); - if (!hose) - return 0; - return hose->io_base_phys; -} - -unsigned long -pci_bus_mem_base_phys(unsigned int bus) -{ - struct pci_controller *hose; - - hose = pci_bus_to_hose(bus); - if (!hose) - return 0; - return hose->pci_mem_offset; -} - -unsigned long -pci_resource_to_bus(struct pci_dev *pdev, struct resource *res) -{ - /* Hack alert again ! See comments in chrp_pci.c - */ - struct pci_controller* hose = - (struct pci_controller *)pdev->sysdata; - if (hose && res->flags & IORESOURCE_MEM) - return res->start - hose->pci_mem_offset; - /* We may want to do something with IOs here... */ - return res->start; -} - - -static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, - resource_size_t *offset, - enum pci_mmap_state mmap_state) -{ - struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - unsigned long io_offset = 0; - int i, res_bit; - - if (hose == 0) - return NULL; /* should never happen */ - - /* If memory, add on the PCI bridge address offset */ - if (mmap_state == pci_mmap_mem) { -#if 0 /* See comment in pci_resource_to_user() for why this is disabled */ - *offset += hose->pci_mem_offset; -#endif - res_bit = IORESOURCE_MEM; - } else { - io_offset = hose->io_base_virt - ___IO_BASE; - *offset += io_offset; - res_bit = IORESOURCE_IO; - } - - /* - * Check that the offset requested corresponds to one of the - * resources of the device. - */ - for (i = 0; i <= PCI_ROM_RESOURCE; i++) { - struct resource *rp = &dev->resource[i]; - int flags = rp->flags; - - /* treat ROM as memory (should be already) */ - if (i == PCI_ROM_RESOURCE) - flags |= IORESOURCE_MEM; - - /* Active and same type? */ - if ((flags & res_bit) == 0) - continue; - - /* In the range of this resource? */ - if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) - continue; - - /* found it! construct the final physical address */ - if (mmap_state == pci_mmap_io) - *offset += hose->io_base_phys - io_offset; - return rp; - } - - return NULL; -} - -/* - * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci - * device mapping. - */ -static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, - pgprot_t protection, - enum pci_mmap_state mmap_state, - int write_combine) -{ - unsigned long prot = pgprot_val(protection); - - /* Write combine is always 0 on non-memory space mappings. On - * memory space, if the user didn't pass 1, we check for a - * "prefetchable" resource. This is a bit hackish, but we use - * this to workaround the inability of /sysfs to provide a write - * combine bit - */ - if (mmap_state != pci_mmap_mem) - write_combine = 0; - else if (write_combine == 0) { - if (rp->flags & IORESOURCE_PREFETCH) - write_combine = 1; - } - - /* XXX would be nice to have a way to ask for write-through */ - prot |= _PAGE_NO_CACHE; - if (write_combine) - prot &= ~_PAGE_GUARDED; - else - prot |= _PAGE_GUARDED; - - printk("PCI map for %s:%llx, prot: %lx\n", pci_name(dev), - (unsigned long long)rp->start, prot); - - return __pgprot(prot); -} - -/* - * This one is used by /dev/mem and fbdev who have no clue about the - * PCI device, it tries to find the PCI device first and calls the - * above routine - */ -pgprot_t pci_phys_mem_access_prot(struct file *file, - unsigned long pfn, - unsigned long size, - pgprot_t protection) -{ - struct pci_dev *pdev = NULL; - struct resource *found = NULL; - unsigned long prot = pgprot_val(protection); - unsigned long offset = pfn << PAGE_SHIFT; - int i; - - if (page_is_ram(pfn)) - return prot; - - prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; - - for_each_pci_dev(pdev) { - for (i = 0; i <= PCI_ROM_RESOURCE; i++) { - struct resource *rp = &pdev->resource[i]; - int flags = rp->flags; - - /* Active and same type? */ - if ((flags & IORESOURCE_MEM) == 0) - continue; - /* In the range of this resource? */ - if (offset < (rp->start & PAGE_MASK) || - offset > rp->end) - continue; - found = rp; - break; - } - if (found) - break; - } - if (found) { - if (found->flags & IORESOURCE_PREFETCH) - prot &= ~_PAGE_GUARDED; - pci_dev_put(pdev); - } - - DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); - - return __pgprot(prot); -} - - -/* - * Perform the actual remap of the pages for a PCI device mapping, as - * appropriate for this architecture. The region in the process to map - * is described by vm_start and vm_end members of VMA, the base physical - * address is found in vm_pgoff. - * The pci device structure is provided so that architectures may make mapping - * decisions on a per-device or per-bus basis. - * - * Returns a negative error code on failure, zero on success. - */ -int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, - enum pci_mmap_state mmap_state, - int write_combine) -{ - resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT; - struct resource *rp; - int ret; - - rp = __pci_mmap_make_offset(dev, &offset, mmap_state); - if (rp == NULL) - return -EINVAL; - - vma->vm_pgoff = offset >> PAGE_SHIFT; - vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, - vma->vm_page_prot, - mmap_state, write_combine); - - ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, - vma->vm_end - vma->vm_start, vma->vm_page_prot); - - return ret; -} - -/* Obsolete functions. Should be removed once the symbios driver - * is fixed - */ -unsigned long -phys_to_bus(unsigned long pa) -{ - struct pci_controller *hose; - int i; - - for (hose = hose_head; hose; hose = hose->next) { - for (i = 0; i < 3; ++i) { - if (pa >= hose->mem_resources[i].start - && pa <= hose->mem_resources[i].end) { - /* - * XXX the hose->pci_mem_offset really - * only applies to mem_resources[0]. - * We need a way to store an offset for - * the others. -- paulus - */ - if (i == 0) - pa -= hose->pci_mem_offset; - return pa; - } - } - } - /* hmmm, didn't find it */ - return 0; -} - -unsigned long -pci_phys_to_bus(unsigned long pa, int busnr) -{ - struct pci_controller* hose = pci_bus_to_hose(busnr); - if (!hose) - return pa; - return pa - hose->pci_mem_offset; -} - -unsigned long -pci_bus_to_phys(unsigned int ba, int busnr) -{ - struct pci_controller* hose = pci_bus_to_hose(busnr); - if (!hose) - return ba; - return ba + hose->pci_mem_offset; -} - -/* Provide information on locations of various I/O regions in physical - * memory. Do this on a per-card basis so that we choose the right - * root bridge. - * Note that the returned IO or memory base is a physical address - */ - -long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) -{ - struct pci_controller* hose; - long result = -EOPNOTSUPP; - - hose = pci_bus_to_hose(bus); - if (!hose) - return -ENODEV; - - switch (which) { - case IOBASE_BRIDGE_NUMBER: - return (long)hose->first_busno; - case IOBASE_MEMORY: - return (long)hose->pci_mem_offset; - case IOBASE_IO: - return (long)hose->io_base_phys; - case IOBASE_ISA_IO: - return (long)isa_io_base; - case IOBASE_ISA_MEM: - return (long)isa_mem_base; - } - - return result; -} - -void pci_resource_to_user(const struct pci_dev *dev, int bar, - const struct resource *rsrc, - resource_size_t *start, resource_size_t *end) -{ - struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - resource_size_t offset = 0; - - if (hose == NULL) - return; - - if (rsrc->flags & IORESOURCE_IO) - offset = (unsigned long)hose->io_base_virt - _IO_BASE; - - /* We pass a fully fixed up address to userland for MMIO instead of - * a BAR value because X is lame and expects to be able to use that - * to pass to /dev/mem ! - * - * That means that we'll have potentially 64 bits values where some - * userland apps only expect 32 (like X itself since it thinks only - * Sparc has 64 bits MMIO) but if we don't do that, we break it on - * 32 bits CHRPs :-( - * - * Hopefully, the sysfs insterface is immune to that gunk. Once X - * has been fixed (and the fix spread enough), we can re-enable the - * 2 lines below and pass down a BAR value to userland. In that case - * we'll also have to re-enable the matching code in - * __pci_mmap_make_offset(). - * - * BenH. - */ -#if 0 - else if (rsrc->flags & IORESOURCE_MEM) - offset = hose->pci_mem_offset; -#endif - - *start = rsrc->start - offset; - *end = rsrc->end - offset; -} - -void __init pci_init_resource(struct resource *res, resource_size_t start, - resource_size_t end, int flags, char *name) -{ - res->start = start; - res->end = end; - res->flags = flags; - res->name = name; - res->parent = NULL; - res->sibling = NULL; - res->child = NULL; -} - -void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) -{ - resource_size_t start = pci_resource_start(dev, bar); - resource_size_t len = pci_resource_len(dev, bar); - unsigned long flags = pci_resource_flags(dev, bar); - - if (!len) - return NULL; - if (max && len > max) - len = max; - if (flags & IORESOURCE_IO) - return ioport_map(start, len); - if (flags & IORESOURCE_MEM) - /* Not checking IORESOURCE_CACHEABLE because PPC does - * not currently distinguish between ioremap and - * ioremap_nocache. - */ - return ioremap(start, len); - /* What? */ - return NULL; -} - -void pci_iounmap(struct pci_dev *dev, void __iomem *addr) -{ - /* Nothing to do */ -} -EXPORT_SYMBOL(pci_iomap); -EXPORT_SYMBOL(pci_iounmap); - -unsigned long pci_address_to_pio(phys_addr_t address) -{ - struct pci_controller* hose = hose_head; - - for (; hose; hose = hose->next) { - unsigned int size = hose->io_resource.end - - hose->io_resource.start + 1; - if (address >= hose->io_base_phys && - address < (hose->io_base_phys + size)) { - unsigned long base = - (unsigned long)hose->io_base_virt - _IO_BASE; - return base + (address - hose->io_base_phys); - } - } - return (unsigned int)-1; -} -EXPORT_SYMBOL(pci_address_to_pio); - -/* - * Null PCI config access functions, for the case when we can't - * find a hose. - */ -#define NULL_PCI_OP(rw, size, type) \ -static int \ -null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ -{ \ - return PCIBIOS_DEVICE_NOT_FOUND; \ -} - -static int -null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) -{ - return PCIBIOS_DEVICE_NOT_FOUND; -} - -static int -null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) -{ - return PCIBIOS_DEVICE_NOT_FOUND; -} - -static struct pci_ops null_pci_ops = -{ - null_read_config, - null_write_config -}; - -/* - * These functions are used early on before PCI scanning is done - * and all of the pci_dev and pci_bus structures have been created. - */ -static struct pci_bus * -fake_pci_bus(struct pci_controller *hose, int busnr) -{ - static struct pci_bus bus; - - if (hose == 0) { - hose = pci_bus_to_hose(busnr); - if (hose == 0) - printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); - } - bus.number = busnr; - bus.sysdata = hose; - bus.ops = hose? hose->ops: &null_pci_ops; - return &bus; -} - -#define EARLY_PCI_OP(rw, size, type) \ -int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ - int devfn, int offset, type value) \ -{ \ - return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ - devfn, offset, value); \ -} - -EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, word, u16 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, word, u16) -EARLY_PCI_OP(write, dword, u32) diff --git a/arch/ppc/kernel/ppc-stub.c b/arch/ppc/kernel/ppc-stub.c deleted file mode 100644 index 5f9ee7bb67ec..000000000000 --- a/arch/ppc/kernel/ppc-stub.c +++ /dev/null @@ -1,866 +0,0 @@ -/* - * ppc-stub.c: KGDB support for the Linux kernel. - * - * adapted from arch/sparc/kernel/sparc-stub.c for the PowerPC - * some stuff borrowed from Paul Mackerras' xmon - * Copyright (C) 1998 Michael AK Tesch (tesch@cs.wisc.edu) - * - * Modifications to run under Linux - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - * - * This file originally came from the gdb sources, and the - * copyright notices have been retained below. - */ - -/**************************************************************************** - - THIS SOFTWARE IS NOT COPYRIGHTED - - HP offers the following for use in the public domain. HP makes no - warranty with regard to the software or its performance and the - user accepts the software "AS IS" with all faults. - - HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD - TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES - OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - -****************************************************************************/ - -/**************************************************************************** - * Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $ - * - * Module name: remcom.c $ - * Revision: 1.34 $ - * Date: 91/03/09 12:29:49 $ - * Contributor: Lake Stevens Instrument Division$ - * - * Description: low level support for gdb debugger. $ - * - * Considerations: only works on target hardware $ - * - * Written by: Glenn Engel $ - * ModuleState: Experimental $ - * - * NOTES: See Below $ - * - * Modified for SPARC by Stu Grossman, Cygnus Support. - * - * This code has been extensively tested on the Fujitsu SPARClite demo board. - * - * To enable debugger support, two things need to happen. One, a - * call to set_debug_traps() is necessary in order to allow any breakpoints - * or error conditions to be properly intercepted and reported to gdb. - * Two, a breakpoint needs to be generated to begin communication. This - * is most easily accomplished by a call to breakpoint(). Breakpoint() - * simulates a breakpoint by executing a trap #1. - * - ************* - * - * The following gdb commands are supported: - * - * command function Return value - * - * g return the value of the CPU registers hex data or ENN - * G set the value of the CPU registers OK or ENN - * qOffsets Get section offsets. Reply is Text=xxx;Data=yyy;Bss=zzz - * - * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN - * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN - * - * c Resume at current address SNN ( signal NN) - * cAA..AA Continue at address AA..AA SNN - * - * s Step one instruction SNN - * sAA..AA Step one instruction from AA..AA SNN - * - * k kill - * - * ? What was the last sigval ? SNN (signal NN) - * - * bBB..BB Set baud rate to BB..BB OK or BNN, then sets - * baud rate - * - * All commands and responses are sent with a packet which includes a - * checksum. A packet consists of - * - * $#. - * - * where - * :: - * :: > - * - * When a packet is received, it is first acknowledged with either '+' or '-'. - * '+' indicates a successful transfer. '-' indicates a failed transfer. - * - * Example: - * - * Host: Reply: - * $m0,10#2a +$00010203040506070809101112131415#42 - * - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -void breakinst(void); - -/* - * BUFMAX defines the maximum number of characters in inbound/outbound buffers - * at least NUMREGBYTES*2 are needed for register packets - */ -#define BUFMAX 2048 -static char remcomInBuffer[BUFMAX]; -static char remcomOutBuffer[BUFMAX]; - -static int initialized; -static int kgdb_active; -static int kgdb_started; -static u_int fault_jmp_buf[100]; -static int kdebug; - - -static const char hexchars[]="0123456789abcdef"; - -/* Place where we save old trap entries for restoration - sparc*/ -/* struct tt_entry kgdb_savettable[256]; */ -/* typedef void (*trapfunc_t)(void); */ - -static void kgdb_fault_handler(struct pt_regs *regs); -static int handle_exception (struct pt_regs *regs); - -#if 0 -/* Install an exception handler for kgdb */ -static void exceptionHandler(int tnum, unsigned int *tfunc) -{ - /* We are dorking with a live trap table, all irqs off */ -} -#endif - -int -kgdb_setjmp(long *buf) -{ - asm ("mflr 0; stw 0,0(%0);" - "stw 1,4(%0); stw 2,8(%0);" - "mfcr 0; stw 0,12(%0);" - "stmw 13,16(%0)" - : : "r" (buf)); - /* XXX should save fp regs as well */ - return 0; -} -void -kgdb_longjmp(long *buf, int val) -{ - if (val == 0) - val = 1; - asm ("lmw 13,16(%0);" - "lwz 0,12(%0); mtcrf 0x38,0;" - "lwz 0,0(%0); lwz 1,4(%0); lwz 2,8(%0);" - "mtlr 0; mr 3,%1" - : : "r" (buf), "r" (val)); -} -/* Convert ch from a hex digit to an int */ -static int -hex(unsigned char ch) -{ - if (ch >= 'a' && ch <= 'f') - return ch-'a'+10; - if (ch >= '0' && ch <= '9') - return ch-'0'; - if (ch >= 'A' && ch <= 'F') - return ch-'A'+10; - return -1; -} - -/* Convert the memory pointed to by mem into hex, placing result in buf. - * Return a pointer to the last char put in buf (null), in case of mem fault, - * return 0. - */ -static unsigned char * -mem2hex(const char *mem, char *buf, int count) -{ - unsigned char ch; - unsigned short tmp_s; - unsigned long tmp_l; - - if (kgdb_setjmp((long*)fault_jmp_buf) == 0) { - debugger_fault_handler = kgdb_fault_handler; - - /* Accessing 16 bit and 32 bit objects in a single - ** load instruction is required to avoid bad side - ** effects for some IO registers. - */ - - if ((count == 2) && (((long)mem & 1) == 0)) { - tmp_s = *(unsigned short *)mem; - mem += 2; - *buf++ = hexchars[(tmp_s >> 12) & 0xf]; - *buf++ = hexchars[(tmp_s >> 8) & 0xf]; - *buf++ = hexchars[(tmp_s >> 4) & 0xf]; - *buf++ = hexchars[tmp_s & 0xf]; - - } else if ((count == 4) && (((long)mem & 3) == 0)) { - tmp_l = *(unsigned int *)mem; - mem += 4; - *buf++ = hexchars[(tmp_l >> 28) & 0xf]; - *buf++ = hexchars[(tmp_l >> 24) & 0xf]; - *buf++ = hexchars[(tmp_l >> 20) & 0xf]; - *buf++ = hexchars[(tmp_l >> 16) & 0xf]; - *buf++ = hexchars[(tmp_l >> 12) & 0xf]; - *buf++ = hexchars[(tmp_l >> 8) & 0xf]; - *buf++ = hexchars[(tmp_l >> 4) & 0xf]; - *buf++ = hexchars[tmp_l & 0xf]; - - } else { - while (count-- > 0) { - ch = *mem++; - *buf++ = hexchars[ch >> 4]; - *buf++ = hexchars[ch & 0xf]; - } - } - - } else { - /* error condition */ - } - debugger_fault_handler = NULL; - *buf = 0; - return buf; -} - -/* convert the hex array pointed to by buf into binary to be placed in mem - * return a pointer to the character AFTER the last byte written. -*/ -static char * -hex2mem(char *buf, char *mem, int count) -{ - unsigned char ch; - int i; - char *orig_mem; - unsigned short tmp_s; - unsigned long tmp_l; - - orig_mem = mem; - - if (kgdb_setjmp((long*)fault_jmp_buf) == 0) { - debugger_fault_handler = kgdb_fault_handler; - - /* Accessing 16 bit and 32 bit objects in a single - ** store instruction is required to avoid bad side - ** effects for some IO registers. - */ - - if ((count == 2) && (((long)mem & 1) == 0)) { - tmp_s = hex(*buf++) << 12; - tmp_s |= hex(*buf++) << 8; - tmp_s |= hex(*buf++) << 4; - tmp_s |= hex(*buf++); - - *(unsigned short *)mem = tmp_s; - mem += 2; - - } else if ((count == 4) && (((long)mem & 3) == 0)) { - tmp_l = hex(*buf++) << 28; - tmp_l |= hex(*buf++) << 24; - tmp_l |= hex(*buf++) << 20; - tmp_l |= hex(*buf++) << 16; - tmp_l |= hex(*buf++) << 12; - tmp_l |= hex(*buf++) << 8; - tmp_l |= hex(*buf++) << 4; - tmp_l |= hex(*buf++); - - *(unsigned long *)mem = tmp_l; - mem += 4; - - } else { - for (i=0; i# */ -static void -getpacket(char *buffer) -{ - unsigned char checksum; - unsigned char xmitcsum; - int i; - int count; - unsigned char ch; - - do { - /* wait around for the start character, ignore all other - * characters */ - while ((ch = (getDebugChar() & 0x7f)) != '$') ; - - checksum = 0; - xmitcsum = -1; - - count = 0; - - /* now, read until a # or end of buffer is found */ - while (count < BUFMAX) { - ch = getDebugChar() & 0x7f; - if (ch == '#') - break; - checksum = checksum + ch; - buffer[count] = ch; - count = count + 1; - } - - if (count >= BUFMAX) - continue; - - buffer[count] = 0; - - if (ch == '#') { - xmitcsum = hex(getDebugChar() & 0x7f) << 4; - xmitcsum |= hex(getDebugChar() & 0x7f); - if (checksum != xmitcsum) - putDebugChar('-'); /* failed checksum */ - else { - putDebugChar('+'); /* successful transfer */ - /* if a sequence char is present, reply the ID */ - if (buffer[2] == ':') { - putDebugChar(buffer[0]); - putDebugChar(buffer[1]); - /* remove sequence chars from buffer */ - count = strlen(buffer); - for (i=3; i <= count; i++) - buffer[i-3] = buffer[i]; - } - } - } - } while (checksum != xmitcsum); -} - -/* send the packet in buffer. */ -static void putpacket(unsigned char *buffer) -{ - unsigned char checksum; - int count; - unsigned char ch, recv; - - /* $#. */ - do { - putDebugChar('$'); - checksum = 0; - count = 0; - - while ((ch = buffer[count])) { - putDebugChar(ch); - checksum += ch; - count += 1; - } - - putDebugChar('#'); - putDebugChar(hexchars[checksum >> 4]); - putDebugChar(hexchars[checksum & 0xf]); - recv = getDebugChar(); - } while ((recv & 0x7f) != '+'); -} - -static void kgdb_flush_cache_all(void) -{ - flush_instruction_cache(); -} - -/* Set up exception handlers for tracing and breakpoints - * [could be called kgdb_init()] - */ -void set_debug_traps(void) -{ -#if 0 - unsigned char c; - - save_and_cli(flags); - - /* In case GDB is started before us, ack any packets (presumably - * "$?#xx") sitting there. - * - * I've found this code causes more problems than it solves, - * so that's why it's commented out. GDB seems to work fine - * now starting either before or after the kernel -bwb - */ - - while((c = getDebugChar()) != '$'); - while((c = getDebugChar()) != '#'); - c = getDebugChar(); /* eat first csum byte */ - c = getDebugChar(); /* eat second csum byte */ - putDebugChar('+'); /* ack it */ -#endif - debugger = kgdb; - debugger_bpt = kgdb_bpt; - debugger_sstep = kgdb_sstep; - debugger_iabr_match = kgdb_iabr_match; - debugger_dabr_match = kgdb_dabr_match; - - initialized = 1; -} - -static void kgdb_fault_handler(struct pt_regs *regs) -{ - kgdb_longjmp((long*)fault_jmp_buf, 1); -} - -int kgdb_bpt(struct pt_regs *regs) -{ - return handle_exception(regs); -} - -int kgdb_sstep(struct pt_regs *regs) -{ - return handle_exception(regs); -} - -void kgdb(struct pt_regs *regs) -{ - handle_exception(regs); -} - -int kgdb_iabr_match(struct pt_regs *regs) -{ - printk(KERN_ERR "kgdb doesn't support iabr, what?!?\n"); - return handle_exception(regs); -} - -int kgdb_dabr_match(struct pt_regs *regs) -{ - printk(KERN_ERR "kgdb doesn't support dabr, what?!?\n"); - return handle_exception(regs); -} - -/* Convert the hardware trap type code to a unix signal number. */ -/* - * This table contains the mapping between PowerPC hardware trap types, and - * signals, which are primarily what GDB understands. - */ -static struct hard_trap_info -{ - unsigned int tt; /* Trap type code for powerpc */ - unsigned char signo; /* Signal that we map this trap into */ -} hard_trap_info[] = { -#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) - { 0x100, SIGINT }, /* critical input interrupt */ - { 0x200, SIGSEGV }, /* machine check */ - { 0x300, SIGSEGV }, /* data storage */ - { 0x400, SIGBUS }, /* instruction storage */ - { 0x500, SIGINT }, /* interrupt */ - { 0x600, SIGBUS }, /* alignment */ - { 0x700, SIGILL }, /* program */ - { 0x800, SIGILL }, /* reserved */ - { 0x900, SIGILL }, /* reserved */ - { 0xa00, SIGILL }, /* reserved */ - { 0xb00, SIGILL }, /* reserved */ - { 0xc00, SIGCHLD }, /* syscall */ - { 0xd00, SIGILL }, /* reserved */ - { 0xe00, SIGILL }, /* reserved */ - { 0xf00, SIGILL }, /* reserved */ - /* - ** 0x1000 PIT - ** 0x1010 FIT - ** 0x1020 watchdog - ** 0x1100 data TLB miss - ** 0x1200 instruction TLB miss - */ - { 0x2002, SIGTRAP}, /* debug */ -#else - { 0x200, SIGSEGV }, /* machine check */ - { 0x300, SIGSEGV }, /* address error (store) */ - { 0x400, SIGBUS }, /* instruction bus error */ - { 0x500, SIGINT }, /* interrupt */ - { 0x600, SIGBUS }, /* alingment */ - { 0x700, SIGTRAP }, /* breakpoint trap */ - { 0x800, SIGFPE }, /* fpu unavail */ - { 0x900, SIGALRM }, /* decrementer */ - { 0xa00, SIGILL }, /* reserved */ - { 0xb00, SIGILL }, /* reserved */ - { 0xc00, SIGCHLD }, /* syscall */ - { 0xd00, SIGTRAP }, /* single-step/watch */ - { 0xe00, SIGFPE }, /* fp assist */ -#endif - { 0, 0} /* Must be last */ - -}; - -static int computeSignal(unsigned int tt) -{ - struct hard_trap_info *ht; - - for (ht = hard_trap_info; ht->tt && ht->signo; ht++) - if (ht->tt == tt) - return ht->signo; - - return SIGHUP; /* default for things we don't know about */ -} - -#define PC_REGNUM 64 -#define SP_REGNUM 1 - -/* - * This function does all command processing for interfacing to gdb. - */ -static int -handle_exception (struct pt_regs *regs) -{ - int sigval; - int addr; - int length; - char *ptr; - unsigned int msr; - - /* We don't handle user-mode breakpoints. */ - if (user_mode(regs)) - return 0; - - if (debugger_fault_handler) { - debugger_fault_handler(regs); - panic("kgdb longjump failed!\n"); - } - if (kgdb_active) { - printk(KERN_ERR "interrupt while in kgdb, returning\n"); - return 0; - } - - kgdb_active = 1; - kgdb_started = 1; - -#ifdef KGDB_DEBUG - printk("kgdb: entering handle_exception; trap [0x%x]\n", - (unsigned int)regs->trap); -#endif - - kgdb_interruptible(0); - lock_kernel(); - msr = mfmsr(); - mtmsr(msr & ~MSR_EE); /* disable interrupts */ - - if (regs->nip == (unsigned long)breakinst) { - /* Skip over breakpoint trap insn */ - regs->nip += 4; - } - - /* reply to host that an exception has occurred */ - sigval = computeSignal(regs->trap); - ptr = remcomOutBuffer; - - *ptr++ = 'T'; - *ptr++ = hexchars[sigval >> 4]; - *ptr++ = hexchars[sigval & 0xf]; - *ptr++ = hexchars[PC_REGNUM >> 4]; - *ptr++ = hexchars[PC_REGNUM & 0xf]; - *ptr++ = ':'; - ptr = mem2hex((char *)®s->nip, ptr, 4); - *ptr++ = ';'; - *ptr++ = hexchars[SP_REGNUM >> 4]; - *ptr++ = hexchars[SP_REGNUM & 0xf]; - *ptr++ = ':'; - ptr = mem2hex(((char *)regs) + SP_REGNUM*4, ptr, 4); - *ptr++ = ';'; - *ptr++ = 0; - - putpacket(remcomOutBuffer); - if (kdebug) - printk("remcomOutBuffer: %s\n", remcomOutBuffer); - - /* XXX We may want to add some features dealing with poking the - * XXX page tables, ... (look at sparc-stub.c for more info) - * XXX also required hacking to the gdb sources directly... - */ - - while (1) { - remcomOutBuffer[0] = 0; - - getpacket(remcomInBuffer); - switch (remcomInBuffer[0]) { - case '?': /* report most recent signal */ - remcomOutBuffer[0] = 'S'; - remcomOutBuffer[1] = hexchars[sigval >> 4]; - remcomOutBuffer[2] = hexchars[sigval & 0xf]; - remcomOutBuffer[3] = 0; - break; -#if 0 - case 'q': /* this screws up gdb for some reason...*/ - { - extern long _start, sdata, __bss_start; - - ptr = &remcomInBuffer[1]; - if (strncmp(ptr, "Offsets", 7) != 0) - break; - - ptr = remcomOutBuffer; - sprintf(ptr, "Text=%8.8x;Data=%8.8x;Bss=%8.8x", - &_start, &sdata, &__bss_start); - break; - } -#endif - case 'd': - /* toggle debug flag */ - kdebug ^= 1; - break; - - case 'g': /* return the value of the CPU registers. - * some of them are non-PowerPC names :( - * they are stored in gdb like: - * struct { - * u32 gpr[32]; - * f64 fpr[32]; - * u32 pc, ps, cnd, lr; (ps=msr) - * u32 cnt, xer, mq; - * } - */ - { - int i; - ptr = remcomOutBuffer; - /* General Purpose Regs */ - ptr = mem2hex((char *)regs, ptr, 32 * 4); - /* Floating Point Regs - FIXME */ - /*ptr = mem2hex((char *), ptr, 32 * 8);*/ - for(i=0; i<(32*8*2); i++) { /* 2chars/byte */ - ptr[i] = '0'; - } - ptr += 32*8*2; - /* pc, msr, cr, lr, ctr, xer, (mq is unused) */ - ptr = mem2hex((char *)®s->nip, ptr, 4); - ptr = mem2hex((char *)®s->msr, ptr, 4); - ptr = mem2hex((char *)®s->ccr, ptr, 4); - ptr = mem2hex((char *)®s->link, ptr, 4); - ptr = mem2hex((char *)®s->ctr, ptr, 4); - ptr = mem2hex((char *)®s->xer, ptr, 4); - } - break; - - case 'G': /* set the value of the CPU registers */ - { - ptr = &remcomInBuffer[1]; - - /* - * If the stack pointer has moved, you should pray. - * (cause only god can help you). - */ - - /* General Purpose Regs */ - hex2mem(ptr, (char *)regs, 32 * 4); - - /* Floating Point Regs - FIXME?? */ - /*ptr = hex2mem(ptr, ??, 32 * 8);*/ - ptr += 32*8*2; - - /* pc, msr, cr, lr, ctr, xer, (mq is unused) */ - ptr = hex2mem(ptr, (char *)®s->nip, 4); - ptr = hex2mem(ptr, (char *)®s->msr, 4); - ptr = hex2mem(ptr, (char *)®s->ccr, 4); - ptr = hex2mem(ptr, (char *)®s->link, 4); - ptr = hex2mem(ptr, (char *)®s->ctr, 4); - ptr = hex2mem(ptr, (char *)®s->xer, 4); - - strcpy(remcomOutBuffer,"OK"); - } - break; - case 'H': - /* don't do anything, yet, just acknowledge */ - hexToInt(&ptr, &addr); - strcpy(remcomOutBuffer,"OK"); - break; - - case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */ - /* Try to read %x,%x. */ - - ptr = &remcomInBuffer[1]; - - if (hexToInt(&ptr, &addr) && *ptr++ == ',' - && hexToInt(&ptr, &length)) { - if (mem2hex((char *)addr, remcomOutBuffer, - length)) - break; - strcpy(remcomOutBuffer, "E03"); - } else - strcpy(remcomOutBuffer, "E01"); - break; - - case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */ - /* Try to read '%x,%x:'. */ - - ptr = &remcomInBuffer[1]; - - if (hexToInt(&ptr, &addr) && *ptr++ == ',' - && hexToInt(&ptr, &length) - && *ptr++ == ':') { - if (hex2mem(ptr, (char *)addr, length)) - strcpy(remcomOutBuffer, "OK"); - else - strcpy(remcomOutBuffer, "E03"); - flush_icache_range(addr, addr+length); - } else - strcpy(remcomOutBuffer, "E02"); - break; - - - case 'k': /* kill the program, actually just continue */ - case 'c': /* cAA..AA Continue; address AA..AA optional */ - /* try to read optional parameter, pc unchanged if no parm */ - - ptr = &remcomInBuffer[1]; - if (hexToInt(&ptr, &addr)) - regs->nip = addr; - -/* Need to flush the instruction cache here, as we may have deposited a - * breakpoint, and the icache probably has no way of knowing that a data ref to - * some location may have changed something that is in the instruction cache. - */ - kgdb_flush_cache_all(); - mtmsr(msr); - - kgdb_interruptible(1); - unlock_kernel(); - kgdb_active = 0; - if (kdebug) { - printk("remcomInBuffer: %s\n", remcomInBuffer); - printk("remcomOutBuffer: %s\n", remcomOutBuffer); - } - return 1; - - case 's': - kgdb_flush_cache_all(); -#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) - mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC); - regs->msr |= MSR_DE; -#else - regs->msr |= MSR_SE; -#endif - unlock_kernel(); - kgdb_active = 0; - if (kdebug) { - printk("remcomInBuffer: %s\n", remcomInBuffer); - printk("remcomOutBuffer: %s\n", remcomOutBuffer); - } - return 1; - - case 'r': /* Reset (if user process..exit ???)*/ - panic("kgdb reset."); - break; - } /* switch */ - if (remcomOutBuffer[0] && kdebug) { - printk("remcomInBuffer: %s\n", remcomInBuffer); - printk("remcomOutBuffer: %s\n", remcomOutBuffer); - } - /* reply to the request */ - putpacket(remcomOutBuffer); - } /* while(1) */ -} - -/* This function will generate a breakpoint exception. It is used at the - beginning of a program to sync up with a debugger and can be used - otherwise as a quick means to stop program execution and "break" into - the debugger. */ - -void -breakpoint(void) -{ - if (!initialized) { - printk("breakpoint() called b4 kgdb init\n"); - return; - } - - asm(" .globl breakinst \n\ - breakinst: .long 0x7d821008"); -} - -#ifdef CONFIG_KGDB_CONSOLE -/* Output string in GDB O-packet format if GDB has connected. If nothing - output, returns 0 (caller must then handle output). */ -int -kgdb_output_string (const char* s, unsigned int count) -{ - char buffer[512]; - - if (!kgdb_started) - return 0; - - count = (count <= (sizeof(buffer) / 2 - 2)) - ? count : (sizeof(buffer) / 2 - 2); - - buffer[0] = 'O'; - mem2hex (s, &buffer[1], count); - putpacket(buffer); - - return 1; -} -#endif - -static void sysrq_handle_gdb(int key, struct pt_regs *pt_regs, - struct tty_struct *tty) -{ - printk("Entering GDB stub\n"); - breakpoint(); -} -static struct sysrq_key_op sysrq_gdb_op = { - .handler = sysrq_handle_gdb, - .help_msg = "Gdb", - .action_msg = "GDB", -}; - -static int gdb_register_sysrq(void) -{ - printk("Registering GDB sysrq handler\n"); - register_sysrq_key('g', &sysrq_gdb_op); - return 0; -} -module_init(gdb_register_sysrq); diff --git a/arch/ppc/kernel/ppc_htab.c b/arch/ppc/kernel/ppc_htab.c deleted file mode 100644 index 9ed36dd9cbff..000000000000 --- a/arch/ppc/kernel/ppc_htab.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * PowerPC hash table management proc entry. Will show information - * about the current hash table and will allow changes to it. - * - * Written by Cort Dougan (cort@cs.nmt.edu) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -static int ppc_htab_show(struct seq_file *m, void *v); -static ssize_t ppc_htab_write(struct file * file, const char __user * buffer, - size_t count, loff_t *ppos); -extern PTE *Hash, *Hash_end; -extern unsigned long Hash_size, Hash_mask; -extern unsigned long _SDR1; -extern unsigned long htab_reloads; -extern unsigned long htab_preloads; -extern unsigned long htab_evicts; -extern unsigned long pte_misses; -extern unsigned long pte_errors; -extern unsigned int primary_pteg_full; -extern unsigned int htab_hash_searches; - -static int ppc_htab_open(struct inode *inode, struct file *file) -{ - return single_open(file, ppc_htab_show, NULL); -} - -const struct file_operations ppc_htab_operations = { - .open = ppc_htab_open, - .read = seq_read, - .llseek = seq_lseek, - .write = ppc_htab_write, - .release = single_release, -}; - -static char *pmc1_lookup(unsigned long mmcr0) -{ - switch ( mmcr0 & (0x7f<<7) ) - { - case 0x0: - return "none"; - case MMCR0_PMC1_CYCLES: - return "cycles"; - case MMCR0_PMC1_ICACHEMISS: - return "ic miss"; - case MMCR0_PMC1_DTLB: - return "dtlb miss"; - default: - return "unknown"; - } -} - -static char *pmc2_lookup(unsigned long mmcr0) -{ - switch ( mmcr0 & 0x3f ) - { - case 0x0: - return "none"; - case MMCR0_PMC2_CYCLES: - return "cycles"; - case MMCR0_PMC2_DCACHEMISS: - return "dc miss"; - case MMCR0_PMC2_ITLB: - return "itlb miss"; - case MMCR0_PMC2_LOADMISSTIME: - return "load miss time"; - default: - return "unknown"; - } -} - -/* - * print some useful info about the hash table. This function - * is _REALLY_ slow (see the nested for loops below) but nothing - * in here should be really timing critical. -- Cort - */ -static int ppc_htab_show(struct seq_file *m, void *v) -{ - unsigned long mmcr0 = 0, pmc1 = 0, pmc2 = 0; -#if defined(CONFIG_PPC_STD_MMU) - unsigned int kptes = 0, uptes = 0; - PTE *ptr; -#endif /* CONFIG_PPC_STD_MMU */ - - if (cpu_has_feature(CPU_FTR_604_PERF_MON)) { - mmcr0 = mfspr(SPRN_MMCR0); - pmc1 = mfspr(SPRN_PMC1); - pmc2 = mfspr(SPRN_PMC2); - seq_printf(m, - "604 Performance Monitoring\n" - "MMCR0\t\t: %08lx %s%s ", - mmcr0, - ( mmcr0>>28 & 0x2 ) ? "(user mode counted)" : "", - ( mmcr0>>28 & 0x4 ) ? "(kernel mode counted)" : ""); - seq_printf(m, - "\nPMC1\t\t: %08lx (%s)\n" - "PMC2\t\t: %08lx (%s)\n", - pmc1, pmc1_lookup(mmcr0), - pmc2, pmc2_lookup(mmcr0)); - } - -#ifdef CONFIG_PPC_STD_MMU - /* if we don't have a htab */ - if ( Hash_size == 0 ) { - seq_printf(m, "No Hash Table used\n"); - return 0; - } - - for (ptr = Hash; ptr < Hash_end; ptr++) { - unsigned int mctx, vsid; - - if (!ptr->v) - continue; - /* undo the esid skew */ - vsid = ptr->vsid; - mctx = ((vsid - (vsid & 0xf) * 0x111) >> 4) & 0xfffff; - if (mctx == 0) - kptes++; - else - uptes++; - } - - seq_printf(m, - "PTE Hash Table Information\n" - "Size\t\t: %luKb\n" - "Buckets\t\t: %lu\n" - "Address\t\t: %08lx\n" - "Entries\t\t: %lu\n" - "User ptes\t: %u\n" - "Kernel ptes\t: %u\n" - "Percent full\t: %lu%%\n" - , (unsigned long)(Hash_size>>10), - (Hash_size/(sizeof(PTE)*8)), - (unsigned long)Hash, - Hash_size/sizeof(PTE) - , uptes, - kptes, - ((kptes+uptes)*100) / (Hash_size/sizeof(PTE)) - ); - - seq_printf(m, - "Reloads\t\t: %lu\n" - "Preloads\t: %lu\n" - "Searches\t: %u\n" - "Overflows\t: %u\n" - "Evicts\t\t: %lu\n", - htab_reloads, htab_preloads, htab_hash_searches, - primary_pteg_full, htab_evicts); -#endif /* CONFIG_PPC_STD_MMU */ - - seq_printf(m, - "Non-error misses: %lu\n" - "Error misses\t: %lu\n", - pte_misses, pte_errors); - return 0; -} - -/* - * Allow user to define performance counters and resize the hash table - */ -static ssize_t ppc_htab_write(struct file * file, const char __user * ubuffer, - size_t count, loff_t *ppos) -{ -#ifdef CONFIG_PPC_STD_MMU - unsigned long tmp; - char buffer[16]; - - if (!capable(CAP_SYS_ADMIN)) - return -EACCES; - if (strncpy_from_user(buffer, ubuffer, 15)) - return -EFAULT; - buffer[15] = 0; - - /* don't set the htab size for now */ - if ( !strncmp( buffer, "size ", 5) ) - return -EBUSY; - - if ( !strncmp( buffer, "reset", 5) ) - { - if (cpu_has_feature(CPU_FTR_604_PERF_MON)) { - /* reset PMC1 and PMC2 */ - mtspr(SPRN_PMC1, 0); - mtspr(SPRN_PMC2, 0); - } - htab_reloads = 0; - htab_evicts = 0; - pte_misses = 0; - pte_errors = 0; - } - - /* Everything below here requires the performance monitor feature. */ - if (!cpu_has_feature(CPU_FTR_604_PERF_MON)) - return count; - - /* turn off performance monitoring */ - if ( !strncmp( buffer, "off", 3) ) - { - mtspr(SPRN_MMCR0, 0); - mtspr(SPRN_PMC1, 0); - mtspr(SPRN_PMC2, 0); - } - - if ( !strncmp( buffer, "user", 4) ) - { - /* setup mmcr0 and clear the correct pmc */ - tmp = (mfspr(SPRN_MMCR0) & ~(0x60000000)) | 0x20000000; - mtspr(SPRN_MMCR0, tmp); - mtspr(SPRN_PMC1, 0); - mtspr(SPRN_PMC2, 0); - } - - if ( !strncmp( buffer, "kernel", 6) ) - { - /* setup mmcr0 and clear the correct pmc */ - tmp = (mfspr(SPRN_MMCR0) & ~(0x60000000)) | 0x40000000; - mtspr(SPRN_MMCR0, tmp); - mtspr(SPRN_PMC1, 0); - mtspr(SPRN_PMC2, 0); - } - - /* PMC1 values */ - if ( !strncmp( buffer, "dtlb", 4) ) - { - /* setup mmcr0 and clear the correct pmc */ - tmp = (mfspr(SPRN_MMCR0) & ~(0x7F << 7)) | MMCR0_PMC1_DTLB; - mtspr(SPRN_MMCR0, tmp); - mtspr(SPRN_PMC1, 0); - } - - if ( !strncmp( buffer, "ic miss", 7) ) - { - /* setup mmcr0 and clear the correct pmc */ - tmp = (mfspr(SPRN_MMCR0) & ~(0x7F<<7)) | MMCR0_PMC1_ICACHEMISS; - mtspr(SPRN_MMCR0, tmp); - mtspr(SPRN_PMC1, 0); - } - - /* PMC2 values */ - if ( !strncmp( buffer, "load miss time", 14) ) - { - /* setup mmcr0 and clear the correct pmc */ - asm volatile( - "mfspr %0,%1\n\t" /* get current mccr0 */ - "rlwinm %0,%0,0,0,31-6\n\t" /* clear bits [26-31] */ - "ori %0,%0,%2 \n\t" /* or in mmcr0 settings */ - "mtspr %1,%0 \n\t" /* set new mccr0 */ - "mtspr %3,%4 \n\t" /* reset the pmc */ - : "=r" (tmp) - : "i" (SPRN_MMCR0), - "i" (MMCR0_PMC2_LOADMISSTIME), - "i" (SPRN_PMC2), "r" (0) ); - } - - if ( !strncmp( buffer, "itlb", 4) ) - { - /* setup mmcr0 and clear the correct pmc */ - asm volatile( - "mfspr %0,%1\n\t" /* get current mccr0 */ - "rlwinm %0,%0,0,0,31-6\n\t" /* clear bits [26-31] */ - "ori %0,%0,%2 \n\t" /* or in mmcr0 settings */ - "mtspr %1,%0 \n\t" /* set new mccr0 */ - "mtspr %3,%4 \n\t" /* reset the pmc */ - : "=r" (tmp) - : "i" (SPRN_MMCR0), "i" (MMCR0_PMC2_ITLB), - "i" (SPRN_PMC2), "r" (0) ); - } - - if ( !strncmp( buffer, "dc miss", 7) ) - { - /* setup mmcr0 and clear the correct pmc */ - asm volatile( - "mfspr %0,%1\n\t" /* get current mccr0 */ - "rlwinm %0,%0,0,0,31-6\n\t" /* clear bits [26-31] */ - "ori %0,%0,%2 \n\t" /* or in mmcr0 settings */ - "mtspr %1,%0 \n\t" /* set new mccr0 */ - "mtspr %3,%4 \n\t" /* reset the pmc */ - : "=r" (tmp) - : "i" (SPRN_MMCR0), "i" (MMCR0_PMC2_DCACHEMISS), - "i" (SPRN_PMC2), "r" (0) ); - } - - return count; -#else /* CONFIG_PPC_STD_MMU */ - return 0; -#endif /* CONFIG_PPC_STD_MMU */ -} - -int proc_dol2crvec(ctl_table *table, int write, struct file *filp, - void __user *buffer_arg, size_t *lenp, loff_t *ppos) -{ - int vleft, first=1, len, left, val; - char __user *buffer = (char __user *) buffer_arg; - #define TMPBUFLEN 256 - char buf[TMPBUFLEN], *p; - static const char *sizestrings[4] = { - "2MB", "256KB", "512KB", "1MB" - }; - static const char *clockstrings[8] = { - "clock disabled", "+1 clock", "+1.5 clock", "reserved(3)", - "+2 clock", "+2.5 clock", "+3 clock", "reserved(7)" - }; - static const char *typestrings[4] = { - "flow-through burst SRAM", "reserved SRAM", - "pipelined burst SRAM", "pipelined late-write SRAM" - }; - static const char *holdstrings[4] = { - "0.5", "1.0", "(reserved2)", "(reserved3)" - }; - - if (!cpu_has_feature(CPU_FTR_L2CR)) - return -EFAULT; - - if ( /*!table->maxlen ||*/ (*ppos && !write)) { - *lenp = 0; - return 0; - } - - vleft = table->maxlen / sizeof(int); - left = *lenp; - - for (; left /*&& vleft--*/; first=0) { - if (write) { - while (left) { - char c; - if(get_user(c, buffer)) - return -EFAULT; - if (!isspace(c)) - break; - left--; - buffer++; - } - if (!left) - break; - len = left; - if (len > TMPBUFLEN-1) - len = TMPBUFLEN-1; - if(copy_from_user(buf, buffer, len)) - return -EFAULT; - buf[len] = 0; - p = buf; - if (*p < '0' || *p > '9') - break; - val = simple_strtoul(p, &p, 0); - len = p-buf; - if ((len < left) && *p && !isspace(*p)) - break; - buffer += len; - left -= len; - _set_L2CR(val); - } else { - p = buf; - if (!first) - *p++ = '\t'; - val = _get_L2CR(); - p += sprintf(p, "0x%08x: ", val); - p += sprintf(p, " %s", (val >> 31) & 1 ? "enabled" : - "disabled"); - p += sprintf(p, ", %sparity", (val>>30)&1 ? "" : "no "); - p += sprintf(p, ", %s", sizestrings[(val >> 28) & 3]); - p += sprintf(p, ", %s", clockstrings[(val >> 25) & 7]); - p += sprintf(p, ", %s", typestrings[(val >> 23) & 2]); - p += sprintf(p, "%s", (val>>22)&1 ? ", data only" : ""); - p += sprintf(p, "%s", (val>>20)&1 ? ", ZZ enabled": ""); - p += sprintf(p, ", %s", (val>>19)&1 ? "write-through" : - "copy-back"); - p += sprintf(p, "%s", (val>>18)&1 ? ", testing" : ""); - p += sprintf(p, ", %sns hold",holdstrings[(val>>16)&3]); - p += sprintf(p, "%s", (val>>15)&1 ? ", DLL slow" : ""); - p += sprintf(p, "%s", (val>>14)&1 ? ", diff clock" :""); - p += sprintf(p, "%s", (val>>13)&1 ? ", DLL bypass" :""); - - p += sprintf(p,"\n"); - - len = strlen(buf); - if (len > left) - len = left; - if (copy_to_user(buffer, buf, len)) - return -EFAULT; - left -= len; - buffer += len; - break; - } - } - - if (!write && !first && left) { - if(put_user('\n', (char __user *) buffer)) - return -EFAULT; - left--, buffer++; - } - if (write) { - char __user *s = (char __user *) buffer; - while (left) { - char c; - if(get_user(c, s++)) - return -EFAULT; - if (!isspace(c)) - break; - left--; - } - } - if (write && first) - return -EINVAL; - *lenp -= left; - *ppos += *lenp; - return 0; -} - -#ifdef CONFIG_SYSCTL -/* - * Register our sysctl. - */ -static ctl_table htab_ctl_table[]={ - { - .procname = "l2cr", - .mode = 0644, - .proc_handler = &proc_dol2crvec, - }, - {} -}; -static ctl_table htab_sysctl_root[] = { - { - .ctl_name = CTL_KERN, - .procname = "kernel", - .mode = 0555, - .child = htab_ctl_table, - }, - {} -}; - -static int __init -register_ppc_htab_sysctl(void) -{ - register_sysctl_table(htab_sysctl_root); - - return 0; -} - -__initcall(register_ppc_htab_sysctl); -#endif diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c deleted file mode 100644 index 5d529bcbeee9..000000000000 --- a/arch/ppc/kernel/ppc_ksyms.c +++ /dev/null @@ -1,258 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_8xx -#include -#endif - -extern void transfer_to_handler(void); -extern void do_IRQ(struct pt_regs *regs); -extern void machine_check_exception(struct pt_regs *regs); -extern void alignment_exception(struct pt_regs *regs); -extern void program_check_exception(struct pt_regs *regs); -extern void single_step_exception(struct pt_regs *regs); -extern int sys_sigreturn(struct pt_regs *regs); - -long long __ashrdi3(long long, int); -long long __ashldi3(long long, int); -long long __lshrdi3(long long, int); - -EXPORT_SYMBOL(empty_zero_page); -EXPORT_SYMBOL(clear_pages); -EXPORT_SYMBOL(clear_user_page); -EXPORT_SYMBOL(copy_page); -EXPORT_SYMBOL(transfer_to_handler); -EXPORT_SYMBOL(do_IRQ); -EXPORT_SYMBOL(machine_check_exception); -EXPORT_SYMBOL(alignment_exception); -EXPORT_SYMBOL(program_check_exception); -EXPORT_SYMBOL(single_step_exception); -EXPORT_SYMBOL(sys_sigreturn); -EXPORT_SYMBOL(ppc_n_lost_interrupts); - -EXPORT_SYMBOL(ISA_DMA_THRESHOLD); -EXPORT_SYMBOL(DMA_MODE_READ); -EXPORT_SYMBOL(DMA_MODE_WRITE); - -#if !defined(__INLINE_BITOPS) -EXPORT_SYMBOL(set_bit); -EXPORT_SYMBOL(clear_bit); -EXPORT_SYMBOL(change_bit); -EXPORT_SYMBOL(test_and_set_bit); -EXPORT_SYMBOL(test_and_clear_bit); -EXPORT_SYMBOL(test_and_change_bit); -#endif /* __INLINE_BITOPS */ - -EXPORT_SYMBOL(strcpy); -EXPORT_SYMBOL(strncpy); -EXPORT_SYMBOL(strcat); -EXPORT_SYMBOL(strlen); -EXPORT_SYMBOL(strcmp); -EXPORT_SYMBOL(strncmp); - -EXPORT_SYMBOL(csum_partial); -EXPORT_SYMBOL(csum_partial_copy_generic); -EXPORT_SYMBOL(ip_fast_csum); -EXPORT_SYMBOL(csum_tcpudp_magic); - -EXPORT_SYMBOL(__copy_tofrom_user); -EXPORT_SYMBOL(__clear_user); -EXPORT_SYMBOL(__strncpy_from_user); -EXPORT_SYMBOL(__strnlen_user); - -/* -EXPORT_SYMBOL(inb); -EXPORT_SYMBOL(inw); -EXPORT_SYMBOL(inl); -EXPORT_SYMBOL(outb); -EXPORT_SYMBOL(outw); -EXPORT_SYMBOL(outl); -EXPORT_SYMBOL(outsl);*/ - -EXPORT_SYMBOL(_insb); -EXPORT_SYMBOL(_outsb); -EXPORT_SYMBOL(_insw_ns); -EXPORT_SYMBOL(_outsw_ns); -EXPORT_SYMBOL(_insl_ns); -EXPORT_SYMBOL(_outsl_ns); -EXPORT_SYMBOL(iopa); -EXPORT_SYMBOL(ioremap); -#ifdef CONFIG_44x -EXPORT_SYMBOL(ioremap64); -#endif -EXPORT_SYMBOL(__ioremap); -EXPORT_SYMBOL(iounmap); -EXPORT_SYMBOL(ioremap_bot); /* aka VMALLOC_END */ - -#ifdef CONFIG_PCI -EXPORT_SYMBOL(isa_io_base); -EXPORT_SYMBOL(isa_mem_base); -EXPORT_SYMBOL(pci_dram_offset); -EXPORT_SYMBOL(pci_alloc_consistent); -EXPORT_SYMBOL(pci_free_consistent); -EXPORT_SYMBOL(pci_bus_io_base); -EXPORT_SYMBOL(pci_bus_io_base_phys); -EXPORT_SYMBOL(pci_bus_mem_base_phys); -EXPORT_SYMBOL(pci_bus_to_hose); -EXPORT_SYMBOL(pci_resource_to_bus); -EXPORT_SYMBOL(pci_phys_to_bus); -EXPORT_SYMBOL(pci_bus_to_phys); -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_NOT_COHERENT_CACHE -extern void flush_dcache_all(void); -EXPORT_SYMBOL(flush_dcache_all); -#endif - -EXPORT_SYMBOL(start_thread); -EXPORT_SYMBOL(kernel_thread); - -EXPORT_SYMBOL(flush_instruction_cache); -EXPORT_SYMBOL(giveup_fpu); -EXPORT_SYMBOL(__flush_icache_range); -EXPORT_SYMBOL(flush_dcache_range); -EXPORT_SYMBOL(flush_icache_user_range); -EXPORT_SYMBOL(flush_dcache_page); -EXPORT_SYMBOL(flush_tlb_kernel_range); -EXPORT_SYMBOL(flush_tlb_page); -EXPORT_SYMBOL(_tlbie); -#ifdef CONFIG_ALTIVEC -#ifndef CONFIG_SMP -EXPORT_SYMBOL(last_task_used_altivec); -#endif -EXPORT_SYMBOL(giveup_altivec); -#endif /* CONFIG_ALTIVEC */ -#ifdef CONFIG_SMP -EXPORT_SYMBOL(smp_call_function); -EXPORT_SYMBOL(smp_hw_index); -#endif - -EXPORT_SYMBOL(ppc_md); - -#ifdef CONFIG_ADB -EXPORT_SYMBOL(adb_request); -EXPORT_SYMBOL(adb_register); -EXPORT_SYMBOL(adb_unregister); -EXPORT_SYMBOL(adb_poll); -EXPORT_SYMBOL(adb_try_handler_change); -#endif /* CONFIG_ADB */ -#ifdef CONFIG_ADB_CUDA -EXPORT_SYMBOL(cuda_request); -EXPORT_SYMBOL(cuda_poll); -#endif /* CONFIG_ADB_CUDA */ -#if defined(CONFIG_BOOTX_TEXT) -EXPORT_SYMBOL(btext_update_display); -#endif -EXPORT_SYMBOL(to_tm); - -EXPORT_SYMBOL(pm_power_off); - -EXPORT_SYMBOL(__ashrdi3); -EXPORT_SYMBOL(__ashldi3); -EXPORT_SYMBOL(__lshrdi3); -EXPORT_SYMBOL(memcpy); -EXPORT_SYMBOL(cacheable_memcpy); -EXPORT_SYMBOL(memset); -EXPORT_SYMBOL(memmove); -EXPORT_SYMBOL(memcmp); -EXPORT_SYMBOL(memchr); - -#if defined(CONFIG_FB_VGA16_MODULE) -EXPORT_SYMBOL(screen_info); -#endif - -EXPORT_SYMBOL(__delay); -EXPORT_SYMBOL(timer_interrupt); -EXPORT_SYMBOL(irq_desc); -EXPORT_SYMBOL(tb_ticks_per_jiffy); -EXPORT_SYMBOL(console_drivers); -#ifdef CONFIG_XMON -EXPORT_SYMBOL(xmon); -EXPORT_SYMBOL(xmon_printf); -#endif - -#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) -extern void (*debugger)(struct pt_regs *regs); -extern int (*debugger_bpt)(struct pt_regs *regs); -extern int (*debugger_sstep)(struct pt_regs *regs); -extern int (*debugger_iabr_match)(struct pt_regs *regs); -extern int (*debugger_dabr_match)(struct pt_regs *regs); -extern void (*debugger_fault_handler)(struct pt_regs *regs); - -EXPORT_SYMBOL(debugger); -EXPORT_SYMBOL(debugger_bpt); -EXPORT_SYMBOL(debugger_sstep); -EXPORT_SYMBOL(debugger_iabr_match); -EXPORT_SYMBOL(debugger_dabr_match); -EXPORT_SYMBOL(debugger_fault_handler); -#endif - -#ifdef CONFIG_8xx -EXPORT_SYMBOL(cpm_install_handler); -EXPORT_SYMBOL(cpm_free_handler); -#endif /* CONFIG_8xx */ -#if defined(CONFIG_8xx) || defined(CONFIG_40x) -EXPORT_SYMBOL(__res); -#endif - -EXPORT_SYMBOL(next_mmu_context); -EXPORT_SYMBOL(set_context); -EXPORT_SYMBOL(disarm_decr); -#ifdef CONFIG_PPC_STD_MMU -extern long mol_trampoline; -EXPORT_SYMBOL(mol_trampoline); /* For MOL */ -EXPORT_SYMBOL(flush_hash_pages); /* For MOL */ -#ifdef CONFIG_SMP -extern int mmu_hash_lock; -EXPORT_SYMBOL(mmu_hash_lock); /* For MOL */ -#endif /* CONFIG_SMP */ -extern long *intercept_table; -EXPORT_SYMBOL(intercept_table); -#endif /* CONFIG_PPC_STD_MMU */ -#ifdef CONFIG_PPC_DCR_NATIVE -EXPORT_SYMBOL(__mtdcr); -EXPORT_SYMBOL(__mfdcr); -#endif diff --git a/arch/ppc/kernel/relocate_kernel.S b/arch/ppc/kernel/relocate_kernel.S deleted file mode 100644 index 9b2ad48e988c..000000000000 --- a/arch/ppc/kernel/relocate_kernel.S +++ /dev/null @@ -1,123 +0,0 @@ -/* - * relocate_kernel.S - put the kernel image in place to boot - * Copyright (C) 2002-2003 Eric Biederman - * - * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz - * - * This source code is licensed under the GNU General Public License, - * Version 2. See the file COPYING for more details. - */ - -#include -#include -#include - -#include - -#define PAGE_SIZE 4096 /* must be same value as in */ - - /* - * Must be relocatable PIC code callable as a C function. - */ - .globl relocate_new_kernel -relocate_new_kernel: - /* r3 = page_list */ - /* r4 = reboot_code_buffer */ - /* r5 = start_address */ - - li r0, 0 - - /* - * Set Machine Status Register to a known status, - * switch the MMU off and jump to 1: in a single step. - */ - - mr r8, r0 - ori r8, r8, MSR_RI|MSR_ME - mtspr SPRN_SRR1, r8 - addi r8, r4, 1f - relocate_new_kernel - mtspr SPRN_SRR0, r8 - sync - rfi - -1: - /* from this point address translation is turned off */ - /* and interrupts are disabled */ - - /* set a new stack at the bottom of our page... */ - /* (not really needed now) */ - addi r1, r4, KEXEC_CONTROL_CODE_SIZE - 8 /* for LR Save+Back Chain */ - stw r0, 0(r1) - - /* Do the copies */ - li r6, 0 /* checksum */ - mr r0, r3 - b 1f - -0: /* top, read another word for the indirection page */ - lwzu r0, 4(r3) - -1: - /* is it a destination page? (r8) */ - rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ - beq 2f - - rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ - b 0b - -2: /* is it an indirection page? (r3) */ - rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ - beq 2f - - rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ - subi r3, r3, 4 - b 0b - -2: /* are we done? */ - rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ - beq 2f - b 3f - -2: /* is it a source page? (r9) */ - rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ - beq 0b - - rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ - - li r7, PAGE_SIZE / 4 - mtctr r7 - subi r9, r9, 4 - subi r8, r8, 4 -9: - lwzu r0, 4(r9) /* do the copy */ - xor r6, r6, r0 - stwu r0, 4(r8) - dcbst 0, r8 - sync - icbi 0, r8 - bdnz 9b - - addi r9, r9, 4 - addi r8, r8, 4 - b 0b - -3: - - /* To be certain of avoiding problems with self-modifying code - * execute a serializing instruction here. - */ - isync - sync - - /* jump to the entry point, usually the setup routine */ - mtlr r5 - blrl - -1: b 1b - -relocate_new_kernel_end: - - .globl relocate_new_kernel_size -relocate_new_kernel_size: - .long relocate_new_kernel_end - relocate_new_kernel - diff --git a/arch/ppc/kernel/setup.c b/arch/ppc/kernel/setup.c deleted file mode 100644 index 51e8094f52d6..000000000000 --- a/arch/ppc/kernel/setup.c +++ /dev/null @@ -1,572 +0,0 @@ -/* - * Common prep boot and setup code. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define USES_PPC_SYS (defined(CONFIG_MPC10X_BRIDGE) || defined(CONFIG_8260) || \ - defined(CONFIG_PPC_MPC52xx)) - -#if USES_PPC_SYS -#include -#endif - -#if defined CONFIG_KGDB -#include -#endif - -extern void platform_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, unsigned long r7); -extern void reloc_got2(unsigned long offset); - -extern void ppc6xx_idle(void); -extern void power4_idle(void); - -extern boot_infos_t *boot_infos; - -/* Used with the BI_MEMSIZE bootinfo parameter to store the memory - size value reported by the boot loader. */ -unsigned long boot_mem_size; - -unsigned long ISA_DMA_THRESHOLD; -unsigned int DMA_MODE_READ; -unsigned int DMA_MODE_WRITE; - -#ifdef CONFIG_PPC_PREP -extern void prep_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, unsigned long r7); - -dev_t boot_dev; -#endif /* CONFIG_PPC_PREP */ - -int have_of; -EXPORT_SYMBOL(have_of); - -#ifdef __DO_IRQ_CANON -int ppc_do_canonicalize_irqs; -EXPORT_SYMBOL(ppc_do_canonicalize_irqs); -#endif - -#ifdef CONFIG_VGA_CONSOLE -unsigned long vgacon_remap_base; -#endif - -struct machdep_calls ppc_md; - -/* - * These are used in binfmt_elf.c to put aux entries on the stack - * for each elf executable being started. - */ -int dcache_bsize; -int icache_bsize; -int ucache_bsize; - -#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_FB_VGA16) || \ - defined(CONFIG_FB_VGA16_MODULE) || defined(CONFIG_FB_VESA) -struct screen_info screen_info = { - 0, 25, /* orig-x, orig-y */ - 0, /* unused */ - 0, /* orig-video-page */ - 0, /* orig-video-mode */ - 80, /* orig-video-cols */ - 0,0,0, /* ega_ax, ega_bx, ega_cx */ - 25, /* orig-video-lines */ - 1, /* orig-video-isVGA */ - 16 /* orig-video-points */ -}; -#endif /* CONFIG_VGA_CONSOLE || CONFIG_FB_VGA16 || CONFIG_FB_VESA */ - -void machine_restart(char *cmd) -{ -#ifdef CONFIG_NVRAM - nvram_sync(); -#endif - ppc_md.restart(cmd); -} - -static void ppc_generic_power_off(void) -{ - ppc_md.power_off(); -} - -void machine_halt(void) -{ -#ifdef CONFIG_NVRAM - nvram_sync(); -#endif - ppc_md.halt(); -} - -void (*pm_power_off)(void) = ppc_generic_power_off; - -void machine_power_off(void) -{ -#ifdef CONFIG_NVRAM - nvram_sync(); -#endif - if (pm_power_off) - pm_power_off(); - ppc_generic_power_off(); -} - -#ifdef CONFIG_TAU -extern u32 cpu_temp(unsigned long cpu); -extern u32 cpu_temp_both(unsigned long cpu); -#endif /* CONFIG_TAU */ - -int show_cpuinfo(struct seq_file *m, void *v) -{ - int i = (int) v - 1; - int err = 0; - unsigned int pvr; - unsigned short maj, min; - unsigned long lpj; - - if (i >= NR_CPUS) { - /* Show summary information */ -#ifdef CONFIG_SMP - unsigned long bogosum = 0; - for_each_online_cpu(i) - bogosum += cpu_data[i].loops_per_jiffy; - seq_printf(m, "total bogomips\t: %lu.%02lu\n", - bogosum/(500000/HZ), bogosum/(5000/HZ) % 100); -#endif /* CONFIG_SMP */ - - if (ppc_md.show_cpuinfo != NULL) - err = ppc_md.show_cpuinfo(m); - return err; - } - -#ifdef CONFIG_SMP - if (!cpu_online(i)) - return 0; - pvr = cpu_data[i].pvr; - lpj = cpu_data[i].loops_per_jiffy; -#else - pvr = mfspr(SPRN_PVR); - lpj = loops_per_jiffy; -#endif - - seq_printf(m, "processor\t: %d\n", i); - seq_printf(m, "cpu\t\t: "); - - if (cur_cpu_spec->pvr_mask) - seq_printf(m, "%s", cur_cpu_spec->cpu_name); - else - seq_printf(m, "unknown (%08x)", pvr); -#ifdef CONFIG_ALTIVEC - if (cur_cpu_spec->cpu_features & CPU_FTR_ALTIVEC) - seq_printf(m, ", altivec supported"); -#endif - seq_printf(m, "\n"); - -#ifdef CONFIG_TAU - if (cur_cpu_spec->cpu_features & CPU_FTR_TAU) { -#ifdef CONFIG_TAU_AVERAGE - /* more straightforward, but potentially misleading */ - seq_printf(m, "temperature \t: %u C (uncalibrated)\n", - cpu_temp(i)); -#else - /* show the actual temp sensor range */ - u32 temp; - temp = cpu_temp_both(i); - seq_printf(m, "temperature \t: %u-%u C (uncalibrated)\n", - temp & 0xff, temp >> 16); -#endif - } -#endif /* CONFIG_TAU */ - - if (ppc_md.show_percpuinfo != NULL) { - err = ppc_md.show_percpuinfo(m, i); - if (err) - return err; - } - - /* If we are a Freescale core do a simple check so - * we dont have to keep adding cases in the future */ - if ((PVR_VER(pvr) & 0x8000) == 0x8000) { - maj = PVR_MAJ(pvr); - min = PVR_MIN(pvr); - } else { - switch (PVR_VER(pvr)) { - case 0x0020: /* 403 family */ - maj = PVR_MAJ(pvr) + 1; - min = PVR_MIN(pvr); - break; - case 0x1008: /* 740P/750P ?? */ - maj = ((pvr >> 8) & 0xFF) - 1; - min = pvr & 0xFF; - break; - default: - maj = (pvr >> 8) & 0xFF; - min = pvr & 0xFF; - break; - } - } - - seq_printf(m, "revision\t: %hd.%hd (pvr %04x %04x)\n", - maj, min, PVR_VER(pvr), PVR_REV(pvr)); - - seq_printf(m, "bogomips\t: %lu.%02lu\n", - lpj / (500000/HZ), (lpj / (5000/HZ)) % 100); - -#if USES_PPC_SYS - if (cur_ppc_sys_spec->ppc_sys_name) - seq_printf(m, "chipset\t\t: %s\n", - cur_ppc_sys_spec->ppc_sys_name); -#endif - -#ifdef CONFIG_SMP - seq_printf(m, "\n"); -#endif - - return 0; -} - -static void *c_start(struct seq_file *m, loff_t *pos) -{ - int i = *pos; - - return i <= NR_CPUS? (void *) (i + 1): NULL; -} - -static void *c_next(struct seq_file *m, void *v, loff_t *pos) -{ - ++*pos; - return c_start(m, pos); -} - -static void c_stop(struct seq_file *m, void *v) -{ -} - -const struct seq_operations cpuinfo_op = { - .start =c_start, - .next = c_next, - .stop = c_stop, - .show = show_cpuinfo, -}; - -/* - * We're called here very early in the boot. We determine the machine - * type and call the appropriate low-level setup functions. - * -- Cort - * - * Note that the kernel may be running at an address which is different - * from the address that it was linked at, so we must use RELOC/PTRRELOC - * to access static data (including strings). -- paulus - */ -__init -unsigned long -early_init(int r3, int r4, int r5) -{ - unsigned long phys; - unsigned long offset = reloc_offset(); - struct cpu_spec *spec; - - /* Default */ - phys = offset + KERNELBASE; - - /* First zero the BSS -- use memset, some arches don't have - * caches on yet */ - memset_io(PTRRELOC(&__bss_start), 0, _end - __bss_start); - - /* - * Identify the CPU type and fix up code sections - * that depend on which cpu we have. - */ -#if defined(CONFIG_440EP) && defined(CONFIG_PPC_FPU) - /* We pass the virtual PVR here for 440EP as 440EP and 440GR have - * identical PVRs and there is no reliable way to check for the FPU - */ - spec = identify_cpu(offset, (mfspr(SPRN_PVR) | 0x8)); -#else - spec = identify_cpu(offset, mfspr(SPRN_PVR)); -#endif - do_feature_fixups(spec->cpu_features, - PTRRELOC(&__start___ftr_fixup), - PTRRELOC(&__stop___ftr_fixup)); - - return phys; -} - -#ifdef CONFIG_PPC_PREP -/* - * The PPC_PREP version of platform_init... - */ -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ -#ifdef CONFIG_BOOTX_TEXT - if (boot_text_mapped) { - btext_clearscreen(); - btext_welcome(); - } -#endif - - parse_bootinfo(find_bootinfo()); - - prep_init(r3, r4, r5, r6, r7); -} -#endif /* CONFIG_PPC_PREP */ - -struct bi_record *find_bootinfo(void) -{ - struct bi_record *rec; - - rec = (struct bi_record *)_ALIGN((ulong)__bss_start+(1<<20)-1,(1<<20)); - if ( rec->tag != BI_FIRST ) { - /* - * This 0x10000 offset is a terrible hack but it will go away when - * we have the bootloader handle all the relocation and - * prom calls -- Cort - */ - rec = (struct bi_record *)_ALIGN((ulong)__bss_start+0x10000+(1<<20)-1,(1<<20)); - if ( rec->tag != BI_FIRST ) - return NULL; - } - return rec; -} - -void parse_bootinfo(struct bi_record *rec) -{ - if (rec == NULL || rec->tag != BI_FIRST) - return; - while (rec->tag != BI_LAST) { - ulong *data = rec->data; - switch (rec->tag) { - case BI_CMD_LINE: - strlcpy(cmd_line, (void *)data, sizeof(cmd_line)); - break; -#ifdef CONFIG_BLK_DEV_INITRD - case BI_INITRD: - initrd_start = data[0] + KERNELBASE; - initrd_end = data[0] + data[1] + KERNELBASE; - break; -#endif /* CONFIG_BLK_DEV_INITRD */ - case BI_MEMSIZE: - boot_mem_size = data[0]; - break; - } - rec = (struct bi_record *)((ulong)rec + rec->size); - } -} - -/* - * Find out what kind of machine we're on and save any data we need - * from the early boot process (devtree is copied on pmac by prom_init()). - * This is called very early on the boot process, after a minimal - * MMU environment has been set up but before MMU_init is called. - */ -void __init -machine_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ -#ifdef CONFIG_CMDLINE - strlcpy(cmd_line, CONFIG_CMDLINE, sizeof(cmd_line)); -#endif /* CONFIG_CMDLINE */ - -#ifdef CONFIG_6xx - ppc_md.power_save = ppc6xx_idle; -#endif - - platform_init(r3, r4, r5, r6, r7); - - if (ppc_md.progress) - ppc_md.progress("id mach(): done", 0x200); -} -#ifdef CONFIG_BOOKE_WDT -/* Checks wdt=x and wdt_period=xx command-line option */ -int __init early_parse_wdt(char *p) -{ - if (p && strncmp(p, "0", 1) != 0) - booke_wdt_enabled = 1; - - return 0; -} -early_param("wdt", early_parse_wdt); - -int __init early_parse_wdt_period (char *p) -{ - if (p) - booke_wdt_period = simple_strtoul(p, NULL, 0); - - return 0; -} -early_param("wdt_period", early_parse_wdt_period); -#endif /* CONFIG_BOOKE_WDT */ - -/* Checks "l2cr=xxxx" command-line option */ -int __init ppc_setup_l2cr(char *str) -{ - if (cpu_has_feature(CPU_FTR_L2CR)) { - unsigned long val = simple_strtoul(str, NULL, 0); - printk(KERN_INFO "l2cr set to %lx\n", val); - _set_L2CR(0); /* force invalidate by disable cache */ - _set_L2CR(val); /* and enable it */ - } - return 1; -} -__setup("l2cr=", ppc_setup_l2cr); - -#ifdef CONFIG_GENERIC_NVRAM - -/* Generic nvram hooks used by drivers/char/gen_nvram.c */ -unsigned char nvram_read_byte(int addr) -{ - if (ppc_md.nvram_read_val) - return ppc_md.nvram_read_val(addr); - return 0xff; -} -EXPORT_SYMBOL(nvram_read_byte); - -void nvram_write_byte(unsigned char val, int addr) -{ - if (ppc_md.nvram_write_val) - ppc_md.nvram_write_val(addr, val); -} -EXPORT_SYMBOL(nvram_write_byte); - -void nvram_sync(void) -{ - if (ppc_md.nvram_sync) - ppc_md.nvram_sync(); -} -EXPORT_SYMBOL(nvram_sync); - -#endif /* CONFIG_NVRAM */ - -static struct cpu cpu_devices[NR_CPUS]; - -int __init ppc_init(void) -{ - int i; - - /* clear the progress line */ - if ( ppc_md.progress ) ppc_md.progress(" ", 0xffff); - - /* register CPU devices */ - for_each_possible_cpu(i) - register_cpu(&cpu_devices[i], i); - - /* call platform init */ - if (ppc_md.init != NULL) { - ppc_md.init(); - } - return 0; -} - -arch_initcall(ppc_init); - -/* Warning, IO base is not yet inited */ -void __init setup_arch(char **cmdline_p) -{ - extern char *klimit; - extern void do_init_bootmem(void); - - /* so udelay does something sensible, assume <= 1000 bogomips */ - loops_per_jiffy = 500000000 / HZ; - - if (ppc_md.init_early) - ppc_md.init_early(); - -#ifdef CONFIG_XMON - xmon_init(1); - if (strstr(cmd_line, "xmon")) - xmon(NULL); -#endif /* CONFIG_XMON */ - if ( ppc_md.progress ) ppc_md.progress("setup_arch: enter", 0x3eab); - -#if defined(CONFIG_KGDB) - if (ppc_md.kgdb_map_scc) - ppc_md.kgdb_map_scc(); - set_debug_traps(); - if (strstr(cmd_line, "gdb")) { - if (ppc_md.progress) - ppc_md.progress("setup_arch: kgdb breakpoint", 0x4000); - printk("kgdb breakpoint activated\n"); - breakpoint(); - } -#endif - - /* - * Set cache line size based on type of cpu as a default. - * Systems with OF can look in the properties on the cpu node(s) - * for a possibly more accurate value. - */ - if (! cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) { - dcache_bsize = cur_cpu_spec->dcache_bsize; - icache_bsize = cur_cpu_spec->icache_bsize; - ucache_bsize = 0; - } else - ucache_bsize = dcache_bsize = icache_bsize - = cur_cpu_spec->dcache_bsize; - - /* reboot on panic */ - panic_timeout = 180; - - init_mm.start_code = PAGE_OFFSET; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long) klimit; - - /* Save unparsed command line copy for /proc/cmdline */ - strlcpy(boot_command_line, cmd_line, COMMAND_LINE_SIZE); - *cmdline_p = cmd_line; - - parse_early_param(); - - /* set up the bootmem stuff with available memory */ - do_init_bootmem(); - if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab); - -#ifdef CONFIG_PPC_OCP - /* Initialize OCP device list */ - ocp_early_init(); - if ( ppc_md.progress ) ppc_md.progress("ocp: exit", 0x3eab); -#endif - -#ifdef CONFIG_DUMMY_CONSOLE - conswitchp = &dummy_con; -#endif - - ppc_md.setup_arch(); - if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); - - paging_init(); -} diff --git a/arch/ppc/kernel/smp-tbsync.c b/arch/ppc/kernel/smp-tbsync.c deleted file mode 100644 index d0cf3f86931d..000000000000 --- a/arch/ppc/kernel/smp-tbsync.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Smp timebase synchronization for ppc. - * - * Copyright (C) 2003 Samuel Rydh (samuel@ibrium.se) - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define NUM_ITER 300 - -enum { - kExit=0, kSetAndTest, kTest -}; - -static struct { - volatile int tbu; - volatile int tbl; - volatile int mark; - volatile int cmd; - volatile int handshake; - int filler[3]; - - volatile int ack; - int filler2[7]; - - volatile int race_result; -} *tbsync; - -static volatile int running; - -static void __devinit -enter_contest( int mark, int add ) -{ - while( (int)(get_tbl() - mark) < 0 ) - tbsync->race_result = add; -} - -void __devinit -smp_generic_take_timebase( void ) -{ - int cmd, tbl, tbu; - unsigned long flags; - - local_irq_save(flags); - while( !running ) - ; - rmb(); - - for( ;; ) { - tbsync->ack = 1; - while( !tbsync->handshake ) - ; - rmb(); - - cmd = tbsync->cmd; - tbl = tbsync->tbl; - tbu = tbsync->tbu; - tbsync->ack = 0; - if( cmd == kExit ) - break; - - if( cmd == kSetAndTest ) { - while( tbsync->handshake ) - ; - asm volatile ("mttbl %0" :: "r" (tbl) ); - asm volatile ("mttbu %0" :: "r" (tbu) ); - } else { - while( tbsync->handshake ) - ; - } - enter_contest( tbsync->mark, -1 ); - } - local_irq_restore(flags); -} - -static int __devinit -start_contest( int cmd, int offset, int num ) -{ - int i, tbu, tbl, mark, score=0; - - tbsync->cmd = cmd; - - local_irq_disable(); - for( i=-3; itbu = tbu = get_tbu(); - tbsync->tbl = tbl + offset; - tbsync->mark = mark = tbl + 400; - - wmb(); - - tbsync->handshake = 1; - while( tbsync->ack ) - ; - - while( (int)(get_tbl() - tbl) <= 0 ) - ; - tbsync->handshake = 0; - enter_contest( mark, 1 ); - - while( !tbsync->ack ) - ; - - if( tbsync->tbu != get_tbu() || ((tbsync->tbl ^ get_tbl()) & 0x80000000) ) - continue; - if( i++ > 0 ) - score += tbsync->race_result; - } - local_irq_enable(); - return score; -} - -void __devinit -smp_generic_give_timebase( void ) -{ - int i, score, score2, old, min=0, max=5000, offset=1000; - - printk("Synchronizing timebase\n"); - - /* if this fails then this kernel won't work anyway... */ - tbsync = kzalloc( sizeof(*tbsync), GFP_KERNEL ); - mb(); - running = 1; - - while( !tbsync->ack ) - ; - - /* binary search */ - for( old=-1 ; old != offset ; offset=(min+max)/2 ) { - score = start_contest( kSetAndTest, offset, NUM_ITER ); - - printk("score %d, offset %d\n", score, offset ); - - if( score > 0 ) - max = offset; - else - min = offset; - old = offset; - } - score = start_contest( kSetAndTest, min, NUM_ITER ); - score2 = start_contest( kSetAndTest, max, NUM_ITER ); - - printk( "Min %d (score %d), Max %d (score %d)\n", min, score, max, score2 ); - score = abs( score ); - score2 = abs( score2 ); - offset = (score < score2) ? min : max; - - /* guard against inaccurate mttb */ - for( i=0; i<10; i++ ) { - start_contest( kSetAndTest, offset, NUM_ITER/10 ); - - if( (score2=start_contest(kTest, offset, NUM_ITER)) < 0 ) - score2 = -score2; - if( score2 <= score || score2 < 20 ) - break; - } - printk("Final offset: %d (%d/%d)\n", offset, score2, NUM_ITER ); - - /* exiting */ - tbsync->cmd = kExit; - wmb(); - tbsync->handshake = 1; - while( tbsync->ack ) - ; - tbsync->handshake = 0; - kfree( tbsync ); - tbsync = NULL; - running = 0; - - /* all done */ - smp_tb_synchronized = 1; -} diff --git a/arch/ppc/kernel/smp.c b/arch/ppc/kernel/smp.c deleted file mode 100644 index 055998575cb4..000000000000 --- a/arch/ppc/kernel/smp.c +++ /dev/null @@ -1,414 +0,0 @@ -/* - * Smp support for ppc. - * - * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great - * deal of code from the sparc and intel versions. - * - * Copyright (C) 1999 Cort Dougan - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -volatile int smp_commenced; -int smp_tb_synchronized; -struct cpuinfo_PPC cpu_data[NR_CPUS]; -atomic_t ipi_recv; -atomic_t ipi_sent; -cpumask_t cpu_online_map; -cpumask_t cpu_possible_map; -int smp_hw_index[NR_CPUS]; -struct thread_info *secondary_ti; -static struct task_struct *idle_tasks[NR_CPUS]; - -EXPORT_SYMBOL(cpu_online_map); -EXPORT_SYMBOL(cpu_possible_map); - -/* SMP operations for this machine */ -struct smp_ops_t *smp_ops; - -/* all cpu mappings are 1-1 -- Cort */ -volatile unsigned long cpu_callin_map[NR_CPUS]; - -int start_secondary(void *); -void smp_call_function_interrupt(void); -static int __smp_call_function(void (*func) (void *info), void *info, - int wait, int target); - -/* Low level assembly function used to backup CPU 0 state */ -extern void __save_cpu_setup(void); - -/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers. - * - * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up - * in /proc/interrupts will be wrong!!! --Troy */ -#define PPC_MSG_CALL_FUNCTION 0 -#define PPC_MSG_RESCHEDULE 1 -#define PPC_MSG_INVALIDATE_TLB 2 -#define PPC_MSG_XMON_BREAK 3 - -static inline void -smp_message_pass(int target, int msg) -{ - if (smp_ops) { - atomic_inc(&ipi_sent); - smp_ops->message_pass(target, msg); - } -} - -/* - * Common functions - */ -void smp_message_recv(int msg) -{ - atomic_inc(&ipi_recv); - - switch( msg ) { - case PPC_MSG_CALL_FUNCTION: - smp_call_function_interrupt(); - break; - case PPC_MSG_RESCHEDULE: - set_need_resched(); - break; - case PPC_MSG_INVALIDATE_TLB: - _tlbia(); - break; -#ifdef CONFIG_XMON - case PPC_MSG_XMON_BREAK: - xmon(get_irq_regs()); - break; -#endif /* CONFIG_XMON */ - default: - printk("SMP %d: smp_message_recv(): unknown msg %d\n", - smp_processor_id(), msg); - break; - } -} - -/* - * 750's don't broadcast tlb invalidates so - * we have to emulate that behavior. - * -- Cort - */ -void smp_send_tlb_invalidate(int cpu) -{ - if ( PVR_VER(mfspr(SPRN_PVR)) == 8 ) - smp_message_pass(MSG_ALL_BUT_SELF, PPC_MSG_INVALIDATE_TLB); -} - -void smp_send_reschedule(int cpu) -{ - /* - * This is only used if `cpu' is running an idle task, - * so it will reschedule itself anyway... - * - * This isn't the case anymore since the other CPU could be - * sleeping and won't reschedule until the next interrupt (such - * as the timer). - * -- Cort - */ - /* This is only used if `cpu' is running an idle task, - so it will reschedule itself anyway... */ - smp_message_pass(cpu, PPC_MSG_RESCHEDULE); -} - -#ifdef CONFIG_XMON -void smp_send_xmon_break(int cpu) -{ - smp_message_pass(cpu, PPC_MSG_XMON_BREAK); -} -#endif /* CONFIG_XMON */ - -static void stop_this_cpu(void *dummy) -{ - local_irq_disable(); - while (1) - ; -} - -void smp_send_stop(void) -{ - smp_call_function(stop_this_cpu, NULL, 1, 0); -} - -/* - * Structure and data for smp_call_function(). This is designed to minimise - * static memory requirements. It also looks cleaner. - * Stolen from the i386 version. - */ -static DEFINE_SPINLOCK(call_lock); - -static struct call_data_struct { - void (*func) (void *info); - void *info; - atomic_t started; - atomic_t finished; - int wait; -} *call_data; - -/* - * this function sends a 'generic call function' IPI to all other CPUs - * in the system. - */ - -int smp_call_function(void (*func) (void *info), void *info, int nonatomic, - int wait) -/* - * [SUMMARY] Run a function on all other CPUs. - * The function to run. This must be fast and non-blocking. - * An arbitrary pointer to pass to the function. - * currently unused. - * If true, wait (atomically) until function has completed on other CPUs. - * [RETURNS] 0 on success, else a negative status code. Does not return until - * remote CPUs are nearly ready to execute <> or are or have executed. - * - * You must not call this function with disabled interrupts or from a - * hardware interrupt handler or from a bottom half handler. - */ -{ - /* FIXME: get cpu lock with hotplug cpus, or change this to - bitmask. --RR */ - if (num_online_cpus() <= 1) - return 0; - /* Can deadlock when called with interrupts disabled */ - WARN_ON(irqs_disabled()); - return __smp_call_function(func, info, wait, MSG_ALL_BUT_SELF); -} - -static int __smp_call_function(void (*func) (void *info), void *info, - int wait, int target) -{ - struct call_data_struct data; - int ret = -1; - int timeout; - int ncpus = 1; - - if (target == MSG_ALL_BUT_SELF) - ncpus = num_online_cpus() - 1; - else if (target == MSG_ALL) - ncpus = num_online_cpus(); - - data.func = func; - data.info = info; - atomic_set(&data.started, 0); - data.wait = wait; - if (wait) - atomic_set(&data.finished, 0); - - spin_lock(&call_lock); - call_data = &data; - /* Send a message to all other CPUs and wait for them to respond */ - smp_message_pass(target, PPC_MSG_CALL_FUNCTION); - - /* Wait for response */ - timeout = 1000000; - while (atomic_read(&data.started) != ncpus) { - if (--timeout == 0) { - printk("smp_call_function on cpu %d: other cpus not responding (%d)\n", - smp_processor_id(), atomic_read(&data.started)); - goto out; - } - barrier(); - udelay(1); - } - - if (wait) { - timeout = 1000000; - while (atomic_read(&data.finished) != ncpus) { - if (--timeout == 0) { - printk("smp_call_function on cpu %d: other cpus not finishing (%d/%d)\n", - smp_processor_id(), atomic_read(&data.finished), atomic_read(&data.started)); - goto out; - } - barrier(); - udelay(1); - } - } - ret = 0; - - out: - spin_unlock(&call_lock); - return ret; -} - -void smp_call_function_interrupt(void) -{ - void (*func) (void *info) = call_data->func; - void *info = call_data->info; - int wait = call_data->wait; - - /* - * Notify initiating CPU that I've grabbed the data and am - * about to execute the function - */ - atomic_inc(&call_data->started); - /* - * At this point the info structure may be out of scope unless wait==1 - */ - (*func)(info); - if (wait) - atomic_inc(&call_data->finished); -} - -static void __devinit smp_store_cpu_info(int id) -{ - struct cpuinfo_PPC *c = &cpu_data[id]; - - /* assume bogomips are same for everything */ - c->loops_per_jiffy = loops_per_jiffy; - c->pvr = mfspr(SPRN_PVR); -} - -void __init smp_prepare_cpus(unsigned int max_cpus) -{ - int num_cpus, i, cpu; - struct task_struct *p; - - /* Fixup boot cpu */ - smp_store_cpu_info(smp_processor_id()); - cpu_callin_map[smp_processor_id()] = 1; - - if (smp_ops == NULL) { - printk("SMP not supported on this machine.\n"); - return; - } - - /* Probe platform for CPUs: always linear. */ - num_cpus = smp_ops->probe(); - - if (num_cpus < 2) - smp_tb_synchronized = 1; - - for (i = 0; i < num_cpus; ++i) - cpu_set(i, cpu_possible_map); - - /* Backup CPU 0 state */ - __save_cpu_setup(); - - for_each_possible_cpu(cpu) { - if (cpu == smp_processor_id()) - continue; - /* create a process for the processor */ - p = fork_idle(cpu); - if (IS_ERR(p)) - panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p)); - task_thread_info(p)->cpu = cpu; - idle_tasks[cpu] = p; - } -} - -void __devinit smp_prepare_boot_cpu(void) -{ - cpu_set(smp_processor_id(), cpu_online_map); - cpu_set(smp_processor_id(), cpu_possible_map); -} - -int __init setup_profiling_timer(unsigned int multiplier) -{ - return 0; -} - -/* Processor coming up starts here */ -int __devinit start_secondary(void *unused) -{ - int cpu; - - atomic_inc(&init_mm.mm_count); - current->active_mm = &init_mm; - - cpu = smp_processor_id(); - smp_store_cpu_info(cpu); - set_dec(tb_ticks_per_jiffy); - preempt_disable(); - cpu_callin_map[cpu] = 1; - - printk("CPU %d done callin...\n", cpu); - smp_ops->setup_cpu(cpu); - printk("CPU %d done setup...\n", cpu); - smp_ops->take_timebase(); - printk("CPU %d done timebase take...\n", cpu); - - spin_lock(&call_lock); - cpu_set(cpu, cpu_online_map); - spin_unlock(&call_lock); - - local_irq_enable(); - - cpu_idle(); - return 0; -} - -int __cpu_up(unsigned int cpu) -{ - char buf[32]; - int c; - - secondary_ti = task_thread_info(idle_tasks[cpu]); - mb(); - - /* - * There was a cache flush loop here to flush the cache - * to memory for the first 8MB of RAM. The cache flush - * has been pushed into the kick_cpu function for those - * platforms that need it. - */ - - /* wake up cpu */ - smp_ops->kick_cpu(cpu); - - /* - * wait to see if the cpu made a callin (is actually up). - * use this value that I found through experimentation. - * -- Cort - */ - for (c = 1000; c && !cpu_callin_map[cpu]; c--) - udelay(100); - - if (!cpu_callin_map[cpu]) { - sprintf(buf, "didn't find cpu %u", cpu); - if (ppc_md.progress) ppc_md.progress(buf, 0x360+cpu); - printk("Processor %u is stuck.\n", cpu); - return -ENOENT; - } - - sprintf(buf, "found cpu %u", cpu); - if (ppc_md.progress) ppc_md.progress(buf, 0x350+cpu); - printk("Processor %d found.\n", cpu); - - smp_ops->give_timebase(); - - /* Wait until cpu puts itself in the online map */ - while (!cpu_online(cpu)) - cpu_relax(); - - return 0; -} - -void smp_cpus_done(unsigned int max_cpus) -{ - smp_ops->setup_cpu(0); -} diff --git a/arch/ppc/kernel/softemu8xx.c b/arch/ppc/kernel/softemu8xx.c deleted file mode 100644 index 9bbb6bf7b645..000000000000 --- a/arch/ppc/kernel/softemu8xx.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Software emulation of some PPC instructions for the 8xx core. - * - * Copyright (C) 1998 Dan Malek (dmalek@jlc.net) - * - * Software floating emuation for the MPC8xx processor. I did this mostly - * because it was easier than trying to get the libraries compiled for - * software floating point. The goal is still to get the libraries done, - * but I lost patience and needed some hacks to at least get init and - * shells running. The first problem is the setjmp/longjmp that save - * and restore the floating point registers. - * - * For this emulation, our working registers are found on the register - * save area. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -extern void -print_8xx_pte(struct mm_struct *mm, unsigned long addr); -extern int -get_8xx_pte(struct mm_struct *mm, unsigned long addr); - -/* Eventually we may need a look-up table, but this works for now. -*/ -#define LFS 48 -#define LFD 50 -#define LFDU 51 -#define STFD 54 -#define STFDU 55 -#define FMR 63 - -/* - * We return 0 on success, 1 on unimplemented instruction, and EFAULT - * if a load/store faulted. - */ -int -Soft_emulate_8xx(struct pt_regs *regs) -{ - uint inst, instword; - uint flreg, idxreg, disp; - uint retval; - signed short sdisp; - uint *ea, *ip; - - retval = 0; - - instword = *((uint *)regs->nip); - inst = instword >> 26; - - flreg = (instword >> 21) & 0x1f; - idxreg = (instword >> 16) & 0x1f; - disp = instword & 0xffff; - - ea = (uint *)(regs->gpr[idxreg] + disp); - ip = (uint *)¤t->thread.fpr[flreg]; - - switch ( inst ) - { - case LFD: - /* this is a 16 bit quantity that is sign extended - * so use a signed short here -- Cort - */ - sdisp = (instword & 0xffff); - ea = (uint *)(regs->gpr[idxreg] + sdisp); - if (copy_from_user(ip, ea, sizeof(double))) - retval = -EFAULT; - break; - - case LFDU: - if (copy_from_user(ip, ea, sizeof(double))) - retval = -EFAULT; - else - regs->gpr[idxreg] = (uint)ea; - break; - case LFS: - sdisp = (instword & 0xffff); - ea = (uint *)(regs->gpr[idxreg] + sdisp); - if (copy_from_user(ip, ea, sizeof(float))) - retval = -EFAULT; - break; - case STFD: - /* this is a 16 bit quantity that is sign extended - * so use a signed short here -- Cort - */ - sdisp = (instword & 0xffff); - ea = (uint *)(regs->gpr[idxreg] + sdisp); - if (copy_to_user(ea, ip, sizeof(double))) - retval = -EFAULT; - break; - - case STFDU: - if (copy_to_user(ea, ip, sizeof(double))) - retval = -EFAULT; - else - regs->gpr[idxreg] = (uint)ea; - break; - case FMR: - /* assume this is a fp move -- Cort */ - memcpy( ip, ¤t->thread.fpr[(instword>>11)&0x1f], - sizeof(double) ); - break; - default: - retval = 1; - printk("Bad emulation %s/%d\n" - " NIP: %08lx instruction: %08x opcode: %x " - "A: %x B: %x C: %x code: %x rc: %x\n", - current->comm,current->pid, - regs->nip, - instword,inst, - (instword>>16)&0x1f, - (instword>>11)&0x1f, - (instword>>6)&0x1f, - (instword>>1)&0x3ff, - instword&1); - { - int pa; - print_8xx_pte(current->mm,regs->nip); - pa = get_8xx_pte(current->mm,regs->nip) & PAGE_MASK; - pa |= (regs->nip & ~PAGE_MASK); - pa = (unsigned long)__va(pa); - printk("Kernel VA for NIP %x ", pa); - print_8xx_pte(current->mm,pa); - } - - } - - if (retval == 0) - regs->nip += 4; - return(retval); -} - diff --git a/arch/ppc/kernel/time.c b/arch/ppc/kernel/time.c deleted file mode 100644 index 18ee851e33e3..000000000000 --- a/arch/ppc/kernel/time.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * Common time routines among all ppc machines. - * - * Written by Cort Dougan (cort@cs.nmt.edu) to merge - * Paul Mackerras' version and mine for PReP and Pmac. - * MPC8xx/MBX changes by Dan Malek (dmalek@jlc.net). - * - * First round of bugfixes by Gabriel Paubert (paubert@iram.es) - * to make clock more stable (2.4.0-test5). The only thing - * that this code assumes is that the timebases have been synchronized - * by firmware on SMP and are never stopped (never do sleep - * on SMP then, nap and doze are OK). - * - * TODO (not necessarily in this file): - * - improve precision and reproducibility of timebase frequency - * measurement at boot time. - * - get rid of xtime_lock for gettimeofday (generic kernel problem - * to be implemented on all architectures for SMP scalability and - * eventually implementing gettimeofday without entering the kernel). - * - put all time/clock related variables in a single structure - * to minimize number of cache lines touched by gettimeofday() - * - for astronomical applications: add a new function to get - * non ambiguous timestamps even around leap seconds. This needs - * a new timestamp format and a good name. - * - * - * The following comment is partially obsolete (at least the long wait - * is no more a valid reason): - * Since the MPC8xx has a programmable interrupt timer, I decided to - * use that rather than the decrementer. Two reasons: 1.) the clock - * frequency is low, causing 2.) a long wait in the timer interrupt - * while ((d = get_dec()) == dval) - * loop. The MPC8xx can be driven from a variety of input clocks, - * so a number of assumptions have been made here because the kernel - * parameter HZ is a constant. We assume (correctly, today :-) that - * the MPC8xx on the MBX board is driven from a 32.768 kHz crystal. - * This is then divided by 4, providing a 8192 Hz clock into the PIT. - * Since it is not possible to get a nice 100 Hz clock out of this, without - * creating a software PLL, I have set HZ to 128. -- Dan - * - * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 - * "A Kernel Model for Precision Timekeeping" by Dave Mills - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -unsigned long disarm_decr[NR_CPUS]; - -extern struct timezone sys_tz; - -/* keep track of when we need to update the rtc */ -time_t last_rtc_update; - -/* The decrementer counts down by 128 every 128ns on a 601. */ -#define DECREMENTER_COUNT_601 (1000000000 / HZ) - -unsigned tb_ticks_per_jiffy; -unsigned tb_to_us; -unsigned tb_last_stamp; -unsigned long tb_to_ns_scale; - -/* used for timezone offset */ -static long timezone_offset; - -DEFINE_SPINLOCK(rtc_lock); - -EXPORT_SYMBOL(rtc_lock); - -/* Timer interrupt helper function */ -static inline int tb_delta(unsigned *jiffy_stamp) { - int delta; - if (__USE_RTC()) { - delta = get_rtcl(); - if (delta < *jiffy_stamp) *jiffy_stamp -= 1000000000; - delta -= *jiffy_stamp; - } else { - delta = get_tbl() - *jiffy_stamp; - } - return delta; -} - -#ifdef CONFIG_SMP -unsigned long profile_pc(struct pt_regs *regs) -{ - unsigned long pc = instruction_pointer(regs); - - if (in_lock_functions(pc)) - return regs->link; - - return pc; -} -EXPORT_SYMBOL(profile_pc); -#endif - -void wakeup_decrementer(void) -{ - set_dec(tb_ticks_per_jiffy); - /* No currently-supported powerbook has a 601, - * so use get_tbl, not native - */ - last_jiffy_stamp(0) = tb_last_stamp = get_tbl(); -} - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - * We set it up to overflow again in 1/HZ seconds. - */ -void timer_interrupt(struct pt_regs * regs) -{ - struct pt_regs *old_regs; - int next_dec; - unsigned long cpu = smp_processor_id(); - unsigned jiffy_stamp = last_jiffy_stamp(cpu); - extern void do_IRQ(struct pt_regs *); - - if (atomic_read(&ppc_n_lost_interrupts) != 0) - do_IRQ(regs); - - old_regs = set_irq_regs(regs); - irq_enter(); - - while ((next_dec = tb_ticks_per_jiffy - tb_delta(&jiffy_stamp)) <= 0) { - jiffy_stamp += tb_ticks_per_jiffy; - - profile_tick(CPU_PROFILING); - update_process_times(user_mode(regs)); - - if (smp_processor_id()) - continue; - - /* We are in an interrupt, no need to save/restore flags */ - write_seqlock(&xtime_lock); - tb_last_stamp = jiffy_stamp; - do_timer(1); - - /* - * update the rtc when needed, this should be performed on the - * right fraction of a second. Half or full second ? - * Full second works on mk48t59 clocks, others need testing. - * Note that this update is basically only used through - * the adjtimex system calls. Setting the HW clock in - * any other way is a /dev/rtc and userland business. - * This is still wrong by -0.5/+1.5 jiffies because of the - * timer interrupt resolution and possible delay, but here we - * hit a quantization limit which can only be solved by higher - * resolution timers and decoupling time management from timer - * interrupts. This is also wrong on the clocks - * which require being written at the half second boundary. - * We should have an rtc call that only sets the minutes and - * seconds like on Intel to avoid problems with non UTC clocks. - */ - if ( ppc_md.set_rtc_time && ntp_synced() && - xtime.tv_sec - last_rtc_update >= 659 && - abs((xtime.tv_nsec / 1000) - (1000000-1000000/HZ)) < 500000/HZ) { - if (ppc_md.set_rtc_time(xtime.tv_sec+1 + timezone_offset) == 0) - last_rtc_update = xtime.tv_sec+1; - else - /* Try again one minute later */ - last_rtc_update += 60; - } - write_sequnlock(&xtime_lock); - } - if ( !disarm_decr[smp_processor_id()] ) - set_dec(next_dec); - last_jiffy_stamp(cpu) = jiffy_stamp; - - if (ppc_md.heartbeat && !ppc_md.heartbeat_count--) - ppc_md.heartbeat(); - - irq_exit(); - set_irq_regs(old_regs); -} - -/* - * This version of gettimeofday has microsecond resolution. - */ -void do_gettimeofday(struct timeval *tv) -{ - unsigned long flags; - unsigned long seq; - unsigned delta, usec, sec; - - do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - sec = xtime.tv_sec; - usec = (xtime.tv_nsec / 1000); - delta = tb_ticks_since(tb_last_stamp); -#ifdef CONFIG_SMP - /* As long as timebases are not in sync, gettimeofday can only - * have jiffy resolution on SMP. - */ - if (!smp_tb_synchronized) - delta = 0; -#endif /* CONFIG_SMP */ - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - - usec += mulhwu(tb_to_us, delta); - while (usec >= 1000000) { - sec++; - usec -= 1000000; - } - tv->tv_sec = sec; - tv->tv_usec = usec; -} - -EXPORT_SYMBOL(do_gettimeofday); - -int do_settimeofday(struct timespec *tv) -{ - time_t wtm_sec, new_sec = tv->tv_sec; - long wtm_nsec, new_nsec = tv->tv_nsec; - unsigned long flags; - int tb_delta; - - if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) - return -EINVAL; - - write_seqlock_irqsave(&xtime_lock, flags); - /* Updating the RTC is not the job of this code. If the time is - * stepped under NTP, the RTC will be update after STA_UNSYNC - * is cleared. Tool like clock/hwclock either copy the RTC - * to the system time, in which case there is no point in writing - * to the RTC again, or write to the RTC but then they don't call - * settimeofday to perform this operation. Note also that - * we don't touch the decrementer since: - * a) it would lose timer interrupt synchronization on SMP - * (if it is working one day) - * b) it could make one jiffy spuriously shorter or longer - * which would introduce another source of uncertainty potentially - * harmful to relatively short timers. - */ - - /* This works perfectly on SMP only if the tb are in sync but - * guarantees an error < 1 jiffy even if they are off by eons, - * still reasonable when gettimeofday resolution is 1 jiffy. - */ - tb_delta = tb_ticks_since(last_jiffy_stamp(smp_processor_id())); - - new_nsec -= 1000 * mulhwu(tb_to_us, tb_delta); - - wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - new_sec); - wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - new_nsec); - - set_normalized_timespec(&xtime, new_sec, new_nsec); - set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - - /* In case of a large backwards jump in time with NTP, we want the - * clock to be updated as soon as the PLL is again in lock. - */ - last_rtc_update = new_sec - 658; - - ntp_clear(); - write_sequnlock_irqrestore(&xtime_lock, flags); - clock_was_set(); - return 0; -} - -EXPORT_SYMBOL(do_settimeofday); - -/* This function is only called on the boot processor */ -void __init time_init(void) -{ - time_t sec, old_sec; - unsigned old_stamp, stamp, elapsed; - - if (ppc_md.time_init != NULL) - timezone_offset = ppc_md.time_init(); - - if (__USE_RTC()) { - /* 601 processor: dec counts down by 128 every 128ns */ - tb_ticks_per_jiffy = DECREMENTER_COUNT_601; - /* mulhwu_scale_factor(1000000000, 1000000) is 0x418937 */ - tb_to_us = 0x418937; - } else { - ppc_md.calibrate_decr(); - tb_to_ns_scale = mulhwu(tb_to_us, 1000 << 10); - } - - /* Now that the decrementer is calibrated, it can be used in case the - * clock is stuck, but the fact that we have to handle the 601 - * makes things more complex. Repeatedly read the RTC until the - * next second boundary to try to achieve some precision. If there - * is no RTC, we still need to set tb_last_stamp and - * last_jiffy_stamp(cpu 0) to the current stamp. - */ - stamp = get_native_tbl(); - if (ppc_md.get_rtc_time) { - sec = ppc_md.get_rtc_time(); - elapsed = 0; - do { - old_stamp = stamp; - old_sec = sec; - stamp = get_native_tbl(); - if (__USE_RTC() && stamp < old_stamp) - old_stamp -= 1000000000; - elapsed += stamp - old_stamp; - sec = ppc_md.get_rtc_time(); - } while ( sec == old_sec && elapsed < 2*HZ*tb_ticks_per_jiffy); - if (sec==old_sec) - printk("Warning: real time clock seems stuck!\n"); - xtime.tv_sec = sec; - xtime.tv_nsec = 0; - /* No update now, we just read the time from the RTC ! */ - last_rtc_update = xtime.tv_sec; - } - last_jiffy_stamp(0) = tb_last_stamp = stamp; - - /* Not exact, but the timer interrupt takes care of this */ - set_dec(tb_ticks_per_jiffy); - - /* If platform provided a timezone (pmac), we correct the time */ - if (timezone_offset) { - sys_tz.tz_minuteswest = -timezone_offset / 60; - sys_tz.tz_dsttime = 0; - xtime.tv_sec -= timezone_offset; - } - set_normalized_timespec(&wall_to_monotonic, - -xtime.tv_sec, -xtime.tv_nsec); -} - -#define FEBRUARY 2 -#define STARTOFTIME 1970 -#define SECDAY 86400L -#define SECYR (SECDAY * 365) - -/* - * Note: this is wrong for 2100, but our signed 32-bit time_t will - * have overflowed long before that, so who cares. -- paulus - */ -#define leapyear(year) ((year) % 4 == 0) -#define days_in_year(a) (leapyear(a) ? 366 : 365) -#define days_in_month(a) (month_days[(a) - 1]) - -static int month_days[12] = { - 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 -}; - -void to_tm(int tim, struct rtc_time * tm) -{ - register int i; - register long hms, day, gday; - - gday = day = tim / SECDAY; - hms = tim % SECDAY; - - /* Hours, minutes, seconds are easy */ - tm->tm_hour = hms / 3600; - tm->tm_min = (hms % 3600) / 60; - tm->tm_sec = (hms % 3600) % 60; - - /* Number of years in days */ - for (i = STARTOFTIME; day >= days_in_year(i); i++) - day -= days_in_year(i); - tm->tm_year = i; - - /* Number of months in days left */ - if (leapyear(tm->tm_year)) - days_in_month(FEBRUARY) = 29; - for (i = 1; day >= days_in_month(i); i++) - day -= days_in_month(i); - days_in_month(FEBRUARY) = 28; - tm->tm_mon = i; - - /* Days are what is left over (+1) from all that. */ - tm->tm_mday = day + 1; - - /* - * Determine the day of week. Jan. 1, 1970 was a Thursday. - */ - tm->tm_wday = (gday + 4) % 7; -} - -/* Auxiliary function to compute scaling factors */ -/* Actually the choice of a timebase running at 1/4 the of the bus - * frequency giving resolution of a few tens of nanoseconds is quite nice. - * It makes this computation very precise (27-28 bits typically) which - * is optimistic considering the stability of most processor clock - * oscillators and the precision with which the timebase frequency - * is measured but does not harm. - */ -unsigned mulhwu_scale_factor(unsigned inscale, unsigned outscale) { - unsigned mlt=0, tmp, err; - /* No concern for performance, it's done once: use a stupid - * but safe and compact method to find the multiplier. - */ - for (tmp = 1U<<31; tmp != 0; tmp >>= 1) { - if (mulhwu(inscale, mlt|tmp) < outscale) mlt|=tmp; - } - /* We might still be off by 1 for the best approximation. - * A side effect of this is that if outscale is too large - * the returned value will be zero. - * Many corner cases have been checked and seem to work, - * some might have been forgotten in the test however. - */ - err = inscale*(mlt+1); - if (err <= inscale/2) mlt++; - return mlt; -} - -unsigned long long sched_clock(void) -{ - unsigned long lo, hi, hi2; - unsigned long long tb; - - if (!__USE_RTC()) { - do { - hi = get_tbu(); - lo = get_tbl(); - hi2 = get_tbu(); - } while (hi2 != hi); - tb = ((unsigned long long) hi << 32) | lo; - tb = (tb * tb_to_ns_scale) >> 10; - } else { - do { - hi = get_rtcu(); - lo = get_rtcl(); - hi2 = get_rtcu(); - } while (hi2 != hi); - tb = ((unsigned long long) hi) * 1000000000 + lo; - } - return tb; -} diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c deleted file mode 100644 index a467a429c2fe..000000000000 --- a/arch/ppc/kernel/traps.c +++ /dev/null @@ -1,826 +0,0 @@ -/* - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_XMON -extern int xmon_bpt(struct pt_regs *regs); -extern int xmon_sstep(struct pt_regs *regs); -extern int xmon_iabr_match(struct pt_regs *regs); -extern int xmon_dabr_match(struct pt_regs *regs); - -int (*debugger)(struct pt_regs *regs) = xmon; -int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt; -int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep; -int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match; -int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match; -void (*debugger_fault_handler)(struct pt_regs *regs); -#else -#ifdef CONFIG_KGDB -int (*debugger)(struct pt_regs *regs); -int (*debugger_bpt)(struct pt_regs *regs); -int (*debugger_sstep)(struct pt_regs *regs); -int (*debugger_iabr_match)(struct pt_regs *regs); -int (*debugger_dabr_match)(struct pt_regs *regs); -void (*debugger_fault_handler)(struct pt_regs *regs); -#else -#define debugger(regs) do { } while (0) -#define debugger_bpt(regs) 0 -#define debugger_sstep(regs) 0 -#define debugger_iabr_match(regs) 0 -#define debugger_dabr_match(regs) 0 -#define debugger_fault_handler ((void (*)(struct pt_regs *))0) -#endif -#endif - -/* - * Trap & Exception support - */ - -DEFINE_SPINLOCK(die_lock); - -int die(const char * str, struct pt_regs * fp, long err) -{ - static int die_counter; - int nl = 0; - console_verbose(); - spin_lock_irq(&die_lock); - printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); -#ifdef CONFIG_PREEMPT - printk("PREEMPT "); - nl = 1; -#endif -#ifdef CONFIG_SMP - printk("SMP NR_CPUS=%d ", NR_CPUS); - nl = 1; -#endif - if (nl) - printk("\n"); - show_regs(fp); - add_taint(TAINT_DIE); - spin_unlock_irq(&die_lock); - /* do_exit() should take care of panic'ing from an interrupt - * context so we don't handle it here - */ - do_exit(err); -} - -void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) -{ - siginfo_t info; - - if (!user_mode(regs)) { - debugger(regs); - die("Exception in kernel mode", regs, signr); - } - info.si_signo = signr; - info.si_errno = 0; - info.si_code = code; - info.si_addr = (void __user *) addr; - force_sig_info(signr, &info, current); - - /* - * Init gets no signals that it doesn't have a handler for. - * That's all very well, but if it has caused a synchronous - * exception and we ignore the resulting signal, it will just - * generate the same exception over and over again and we get - * nowhere. Better to kill it and let the kernel panic. - */ - if (is_global_init(current)) { - __sighandler_t handler; - - spin_lock_irq(¤t->sighand->siglock); - handler = current->sighand->action[signr-1].sa.sa_handler; - spin_unlock_irq(¤t->sighand->siglock); - if (handler == SIG_DFL) { - /* init has generated a synchronous exception - and it doesn't have a handler for the signal */ - printk(KERN_CRIT "init has generated signal %d " - "but has no handler for it\n", signr); - do_exit(signr); - } - } -} - -/* - * I/O accesses can cause machine checks on powermacs. - * Check if the NIP corresponds to the address of a sync - * instruction for which there is an entry in the exception - * table. - * Note that the 601 only takes a machine check on TEA - * (transfer error ack) signal assertion, and does not - * set any of the top 16 bits of SRR1. - * -- paulus. - */ -static inline int check_io_access(struct pt_regs *regs) -{ -#if defined CONFIG_8xx - unsigned long msr = regs->msr; - const struct exception_table_entry *entry; - unsigned int *nip = (unsigned int *)regs->nip; - - if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) - && (entry = search_exception_tables(regs->nip)) != NULL) { - /* - * Check that it's a sync instruction, or somewhere - * in the twi; isync; nop sequence that inb/inw/inl uses. - * As the address is in the exception table - * we should be able to read the instr there. - * For the debug message, we look at the preceding - * load or store. - */ - if (*nip == 0x60000000) /* nop */ - nip -= 2; - else if (*nip == 0x4c00012c) /* isync */ - --nip; - /* eieio from I/O string functions */ - else if ((*nip) == 0x7c0006ac || *(nip+1) == 0x7c0006ac) - nip += 2; - if (*nip == 0x7c0004ac || (*nip >> 26) == 3 || - (*(nip+1) >> 26) == 3) { - /* sync or twi */ - unsigned int rb; - - --nip; - rb = (*nip >> 11) & 0x1f; - printk(KERN_DEBUG "%s bad port %lx at %p\n", - (*nip & 0x100)? "OUT to": "IN from", - regs->gpr[rb] - _IO_BASE, nip); - regs->msr |= MSR_RI; - regs->nip = entry->fixup; - return 1; - } - } -#endif /* CONFIG_8xx */ - return 0; -} - -#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) -/* On 4xx, the reason for the machine check or program exception - is in the ESR. */ -#define get_reason(regs) ((regs)->dsisr) -#define get_mc_reason(regs) ((regs)->dsisr) -#define REASON_FP ESR_FP -#define REASON_ILLEGAL (ESR_PIL | ESR_PUO) -#define REASON_PRIVILEGED ESR_PPR -#define REASON_TRAP ESR_PTR - -/* single-step stuff */ -#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) -#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) - -#else -/* On non-4xx, the reason for the machine check or program - exception is in the MSR. */ -#define get_reason(regs) ((regs)->msr) -#define get_mc_reason(regs) ((regs)->msr) -#define REASON_FP 0x100000 -#define REASON_ILLEGAL 0x80000 -#define REASON_PRIVILEGED 0x40000 -#define REASON_TRAP 0x20000 - -#define single_stepping(regs) ((regs)->msr & MSR_SE) -#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) -#endif - -/* - * This is "fall-back" implementation for configurations - * which don't provide platform-specific machine check info - */ -void __attribute__ ((weak)) -platform_machine_check(struct pt_regs *regs) -{ -} - -#if defined(CONFIG_4xx) -int machine_check_4xx(struct pt_regs *regs) -{ - unsigned long reason = get_mc_reason(regs); - - if (reason & ESR_IMCP) { - printk("Instruction"); - mtspr(SPRN_ESR, reason & ~ESR_IMCP); - } else - printk("Data"); - printk(" machine check in kernel mode.\n"); - - return 0; -} - -int machine_check_440A(struct pt_regs *regs) -{ - unsigned long reason = get_mc_reason(regs); - - printk("Machine check in kernel mode.\n"); - if (reason & ESR_IMCP){ - printk("Instruction Synchronous Machine Check exception\n"); - mtspr(SPRN_ESR, reason & ~ESR_IMCP); - } - else { - u32 mcsr = mfspr(SPRN_MCSR); - if (mcsr & MCSR_IB) - printk("Instruction Read PLB Error\n"); - if (mcsr & MCSR_DRB) - printk("Data Read PLB Error\n"); - if (mcsr & MCSR_DWB) - printk("Data Write PLB Error\n"); - if (mcsr & MCSR_TLBP) - printk("TLB Parity Error\n"); - if (mcsr & MCSR_ICP){ - flush_instruction_cache(); - printk("I-Cache Parity Error\n"); - } - if (mcsr & MCSR_DCSP) - printk("D-Cache Search Parity Error\n"); - if (mcsr & MCSR_DCFP) - printk("D-Cache Flush Parity Error\n"); - if (mcsr & MCSR_IMPE) - printk("Machine Check exception is imprecise\n"); - - /* Clear MCSR */ - mtspr(SPRN_MCSR, mcsr); - } - return 0; -} -#else -int machine_check_generic(struct pt_regs *regs) -{ - unsigned long reason = get_mc_reason(regs); - - printk("Machine check in kernel mode.\n"); - printk("Caused by (from SRR1=%lx): ", reason); - switch (reason & 0x601F0000) { - case 0x80000: - printk("Machine check signal\n"); - break; - case 0: /* for 601 */ - case 0x40000: - case 0x140000: /* 7450 MSS error and TEA */ - printk("Transfer error ack signal\n"); - break; - case 0x20000: - printk("Data parity error signal\n"); - break; - case 0x10000: - printk("Address parity error signal\n"); - break; - case 0x20000000: - printk("L1 Data Cache error\n"); - break; - case 0x40000000: - printk("L1 Instruction Cache error\n"); - break; - case 0x00100000: - printk("L2 data cache parity error\n"); - break; - default: - printk("Unknown values in msr\n"); - } - return 0; -} -#endif /* everything else */ - -void machine_check_exception(struct pt_regs *regs) -{ - int recover = 0; - - if (cur_cpu_spec->machine_check) - recover = cur_cpu_spec->machine_check(regs); - if (recover > 0) - return; - - if (user_mode(regs)) { - regs->msr |= MSR_RI; - _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); - return; - } - -#if defined(CONFIG_8xx) && defined(CONFIG_PCI) - /* the qspan pci read routines can cause machine checks -- Cort */ - bad_page_fault(regs, regs->dar, SIGBUS); - return; -#endif - - if (debugger_fault_handler) { - debugger_fault_handler(regs); - regs->msr |= MSR_RI; - return; - } - - if (check_io_access(regs)) - return; - - /* - * Optional platform-provided routine to print out - * additional info, e.g. bus error registers. - */ - platform_machine_check(regs); - - debugger(regs); - die("machine check", regs, SIGBUS); -} - -void SMIException(struct pt_regs *regs) -{ - debugger(regs); -#if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB)) - show_regs(regs); - panic("System Management Interrupt"); -#endif -} - -void unknown_exception(struct pt_regs *regs) -{ - printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx %s\n", - regs->nip, regs->msr, regs->trap, print_tainted()); - _exception(SIGTRAP, regs, 0, 0); -} - -void instruction_breakpoint_exception(struct pt_regs *regs) -{ - if (debugger_iabr_match(regs)) - return; - _exception(SIGTRAP, regs, TRAP_BRKPT, 0); -} - -void RunModeException(struct pt_regs *regs) -{ - _exception(SIGTRAP, regs, 0, 0); -} - -/* Illegal instruction emulation support. Originally written to - * provide the PVR to user applications using the mfspr rd, PVR. - * Return non-zero if we can't emulate, or -EFAULT if the associated - * memory access caused an access fault. Return zero on success. - * - * There are a couple of ways to do this, either "decode" the instruction - * or directly match lots of bits. In this case, matching lots of - * bits is faster and easier. - * - */ -#define INST_MFSPR_PVR 0x7c1f42a6 -#define INST_MFSPR_PVR_MASK 0xfc1fffff - -#define INST_DCBA 0x7c0005ec -#define INST_DCBA_MASK 0x7c0007fe - -#define INST_MCRXR 0x7c000400 -#define INST_MCRXR_MASK 0x7c0007fe - -#define INST_STRING 0x7c00042a -#define INST_STRING_MASK 0x7c0007fe -#define INST_STRING_GEN_MASK 0x7c00067e -#define INST_LSWI 0x7c0004aa -#define INST_LSWX 0x7c00042a -#define INST_STSWI 0x7c0005aa -#define INST_STSWX 0x7c00052a - -static int emulate_string_inst(struct pt_regs *regs, u32 instword) -{ - u8 rT = (instword >> 21) & 0x1f; - u8 rA = (instword >> 16) & 0x1f; - u8 NB_RB = (instword >> 11) & 0x1f; - u32 num_bytes; - unsigned long EA; - int pos = 0; - - /* Early out if we are an invalid form of lswx */ - if ((instword & INST_STRING_MASK) == INST_LSWX) - if ((rT == rA) || (rT == NB_RB)) - return -EINVAL; - - EA = (rA == 0) ? 0 : regs->gpr[rA]; - - switch (instword & INST_STRING_MASK) { - case INST_LSWX: - case INST_STSWX: - EA += NB_RB; - num_bytes = regs->xer & 0x7f; - break; - case INST_LSWI: - case INST_STSWI: - num_bytes = (NB_RB == 0) ? 32 : NB_RB; - break; - default: - return -EINVAL; - } - - while (num_bytes != 0) - { - u8 val; - u32 shift = 8 * (3 - (pos & 0x3)); - - switch ((instword & INST_STRING_MASK)) { - case INST_LSWX: - case INST_LSWI: - if (get_user(val, (u8 __user *)EA)) - return -EFAULT; - /* first time updating this reg, - * zero it out */ - if (pos == 0) - regs->gpr[rT] = 0; - regs->gpr[rT] |= val << shift; - break; - case INST_STSWI: - case INST_STSWX: - val = regs->gpr[rT] >> shift; - if (put_user(val, (u8 __user *)EA)) - return -EFAULT; - break; - } - /* move EA to next address */ - EA += 1; - num_bytes--; - - /* manage our position within the register */ - if (++pos == 4) { - pos = 0; - if (++rT == 32) - rT = 0; - } - } - - return 0; -} - -static int emulate_instruction(struct pt_regs *regs) -{ - u32 instword; - u32 rd; - - if (!user_mode(regs)) - return -EINVAL; - CHECK_FULL_REGS(regs); - - if (get_user(instword, (u32 __user *)(regs->nip))) - return -EFAULT; - - /* Emulate the mfspr rD, PVR. - */ - if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { - rd = (instword >> 21) & 0x1f; - regs->gpr[rd] = mfspr(SPRN_PVR); - return 0; - } - - /* Emulating the dcba insn is just a no-op. */ - if ((instword & INST_DCBA_MASK) == INST_DCBA) - return 0; - - /* Emulate the mcrxr insn. */ - if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { - int shift = (instword >> 21) & 0x1c; - unsigned long msk = 0xf0000000UL >> shift; - - regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); - regs->xer &= ~0xf0000000UL; - return 0; - } - - /* Emulate load/store string insn. */ - if ((instword & INST_STRING_GEN_MASK) == INST_STRING) - return emulate_string_inst(regs, instword); - - return -EINVAL; -} - -/* - * After we have successfully emulated an instruction, we have to - * check if the instruction was being single-stepped, and if so, - * pretend we got a single-step exception. This was pointed out - * by Kumar Gala. -- paulus - */ -static void emulate_single_step(struct pt_regs *regs) -{ - if (single_stepping(regs)) { - clear_single_step(regs); - _exception(SIGTRAP, regs, TRAP_TRACE, 0); - } -} - -int is_valid_bugaddr(unsigned long addr) -{ - return addr >= PAGE_OFFSET; -} - -void program_check_exception(struct pt_regs *regs) -{ - unsigned int reason = get_reason(regs); - extern int do_mathemu(struct pt_regs *regs); - -#ifdef CONFIG_MATH_EMULATION - /* (reason & REASON_ILLEGAL) would be the obvious thing here, - * but there seems to be a hardware bug on the 405GP (RevD) - * that means ESR is sometimes set incorrectly - either to - * ESR_DST (!?) or 0. In the process of chasing this with the - * hardware people - not sure if it can happen on any illegal - * instruction or only on FP instructions, whether there is a - * pattern to occurrences etc. -dgibson 31/Mar/2003 */ - if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) { - emulate_single_step(regs); - return; - } -#endif /* CONFIG_MATH_EMULATION */ - - if (reason & REASON_FP) { - /* IEEE FP exception */ - int code = 0; - u32 fpscr; - - /* We must make sure the FP state is consistent with - * our MSR_FP in regs - */ - preempt_disable(); - if (regs->msr & MSR_FP) - giveup_fpu(current); - preempt_enable(); - - fpscr = current->thread.fpscr.val; - fpscr &= fpscr << 22; /* mask summary bits with enables */ - if (fpscr & FPSCR_VX) - code = FPE_FLTINV; - else if (fpscr & FPSCR_OX) - code = FPE_FLTOVF; - else if (fpscr & FPSCR_UX) - code = FPE_FLTUND; - else if (fpscr & FPSCR_ZX) - code = FPE_FLTDIV; - else if (fpscr & FPSCR_XX) - code = FPE_FLTRES; - _exception(SIGFPE, regs, code, regs->nip); - return; - } - - if (reason & REASON_TRAP) { - /* trap exception */ - if (debugger_bpt(regs)) - return; - - if (!(regs->msr & MSR_PR) && /* not user-mode */ - report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { - regs->nip += 4; - return; - } - _exception(SIGTRAP, regs, TRAP_BRKPT, 0); - return; - } - - /* Try to emulate it if we should. */ - if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { - switch (emulate_instruction(regs)) { - case 0: - regs->nip += 4; - emulate_single_step(regs); - return; - case -EFAULT: - _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); - return; - } - } - - if (reason & REASON_PRIVILEGED) - _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); - else - _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); -} - -void single_step_exception(struct pt_regs *regs) -{ - regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ - if (debugger_sstep(regs)) - return; - _exception(SIGTRAP, regs, TRAP_TRACE, 0); -} - -void alignment_exception(struct pt_regs *regs) -{ - int sig, code, fixed = 0; - - fixed = fix_alignment(regs); - if (fixed == 1) { - regs->nip += 4; /* skip over emulated instruction */ - emulate_single_step(regs); - return; - } - if (fixed == -EFAULT) { - sig = SIGSEGV; - code = SEGV_ACCERR; - } else { - sig = SIGBUS; - code = BUS_ADRALN; - } - if (user_mode(regs)) - _exception(sig, regs, code, regs->dar); - else - bad_page_fault(regs, regs->dar, sig); -} - -void StackOverflow(struct pt_regs *regs) -{ - printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", - current, regs->gpr[1]); - debugger(regs); - show_regs(regs); - panic("kernel stack overflow"); -} - -void nonrecoverable_exception(struct pt_regs *regs) -{ - printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", - regs->nip, regs->msr); - debugger(regs); - die("nonrecoverable exception", regs, SIGKILL); -} - -void trace_syscall(struct pt_regs *regs) -{ - printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", - current, current->pid, regs->nip, regs->link, regs->gpr[0], - regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); -} - -#ifdef CONFIG_8xx -void SoftwareEmulation(struct pt_regs *regs) -{ - extern int do_mathemu(struct pt_regs *); - extern int Soft_emulate_8xx(struct pt_regs *); - int errcode; - - CHECK_FULL_REGS(regs); - - if (!user_mode(regs)) { - debugger(regs); - die("Kernel Mode Software FPU Emulation", regs, SIGFPE); - } - -#ifdef CONFIG_MATH_EMULATION - errcode = do_mathemu(regs); -#else - errcode = Soft_emulate_8xx(regs); -#endif - if (errcode) { - if (errcode > 0) - _exception(SIGFPE, regs, 0, 0); - else if (errcode == -EFAULT) - _exception(SIGSEGV, regs, 0, 0); - else - _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); - } else - emulate_single_step(regs); -} -#endif /* CONFIG_8xx */ - -#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) - -void DebugException(struct pt_regs *regs, unsigned long debug_status) -{ - if (debug_status & DBSR_IC) { /* instruction completion */ - regs->msr &= ~MSR_DE; - if (user_mode(regs)) { - current->thread.dbcr0 &= ~DBCR0_IC; - } else { - /* Disable instruction completion */ - mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); - /* Clear the instruction completion event */ - mtspr(SPRN_DBSR, DBSR_IC); - if (debugger_sstep(regs)) - return; - } - _exception(SIGTRAP, regs, TRAP_TRACE, 0); - } -} -#endif /* CONFIG_4xx || CONFIG_BOOKE */ - -#if !defined(CONFIG_TAU_INT) -void TAUException(struct pt_regs *regs) -{ - printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", - regs->nip, regs->msr, regs->trap, print_tainted()); -} -#endif /* CONFIG_INT_TAU */ - -/* - * FP unavailable trap from kernel - print a message, but let - * the task use FP in the kernel until it returns to user mode. - */ -void kernel_fp_unavailable_exception(struct pt_regs *regs) -{ - regs->msr |= MSR_FP; - printk(KERN_ERR "floating point used in kernel (task=%p, pc=%lx)\n", - current, regs->nip); -} - -void altivec_unavailable_exception(struct pt_regs *regs) -{ - static int kernel_altivec_count; - -#ifndef CONFIG_ALTIVEC - if (user_mode(regs)) { - /* A user program has executed an altivec instruction, - but this kernel doesn't support altivec. */ - _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); - return; - } -#endif - /* The kernel has executed an altivec instruction without - first enabling altivec. Whinge but let it do it. */ - if (++kernel_altivec_count < 10) - printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n", - current, regs->nip); - regs->msr |= MSR_VEC; -} - -#ifdef CONFIG_ALTIVEC -void altivec_assist_exception(struct pt_regs *regs) -{ - int err; - - preempt_disable(); - if (regs->msr & MSR_VEC) - giveup_altivec(current); - preempt_enable(); - if (!user_mode(regs)) { - printk(KERN_ERR "altivec assist exception in kernel mode" - " at %lx\n", regs->nip); - debugger(regs); - die("altivec assist exception", regs, SIGFPE); - return; - } - - err = emulate_altivec(regs); - if (err == 0) { - regs->nip += 4; /* skip emulated instruction */ - emulate_single_step(regs); - return; - } - - if (err == -EFAULT) { - /* got an error reading the instruction */ - _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); - } else { - /* didn't recognize the instruction */ - /* XXX quick hack for now: set the non-Java bit in the VSCR */ - printk(KERN_ERR "unrecognized altivec instruction " - "in %s at %lx\n", current->comm, regs->nip); - current->thread.vscr.u[3] |= 0x10000; - } -} -#endif /* CONFIG_ALTIVEC */ - -#ifdef CONFIG_BOOKE_WDT -/* - * Default handler for a Watchdog exception, - * spins until a reboot occurs - */ -void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) -{ - /* Generic WatchdogHandler, implement your own */ - mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); - return; -} - -void WatchdogException(struct pt_regs *regs) -{ - printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); - WatchdogHandler(regs); -} -#endif - -void __init trap_init(void) -{ -} diff --git a/arch/ppc/kernel/vmlinux.lds.S b/arch/ppc/kernel/vmlinux.lds.S deleted file mode 100644 index 8a24bc47eb6c..000000000000 --- a/arch/ppc/kernel/vmlinux.lds.S +++ /dev/null @@ -1,164 +0,0 @@ -#include - -OUTPUT_ARCH(powerpc:common) -jiffies = jiffies_64 + 4; -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .gnu.hash : { *(.gnu.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } -/* .init : { *(.init) } =0*/ - .plt : { *(.plt) } - .text : - { - _text = .; - TEXT_TEXT - SCHED_TEXT - LOCK_TEXT - *(.fixup) - *(.got1) - __got2_start = .; - *(.got2) - __got2_end = .; - } - _etext = .; - PROVIDE (etext = .); - - RODATA - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - .fixup : { *(.fixup) } - - __ex_table : { - __start___ex_table = .; - *(__ex_table) - __stop___ex_table = .; - } - - __bug_table : { - __start___bug_table = .; - *(__bug_table) - __stop___bug_table = .; - } - - /* Read-write section, merged into data segment: */ - . = ALIGN(4096); - .data : - { - DATA_DATA - *(.data1) - *(.sdata) - *(.sdata2) - *(.got.plt) *(.got) - *(.dynamic) - CONSTRUCTORS - } - - . = ALIGN(4096); - __nosave_begin = .; - .data_nosave : { *(.data.nosave) } - . = ALIGN(4096); - __nosave_end = .; - - . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - - _edata = .; - PROVIDE (edata = .); - - . = ALIGN(8192); - .data.init_task : { *(.data.init_task) } - - NOTES - - . = ALIGN(4096); - __init_begin = .; - .init.text : { - _sinittext = .; - INIT_TEXT - _einittext = .; - } - /* .exit.text is discarded at runtime, not link time, - to deal with references from __bug_table */ - .exit.text : { EXIT_TEXT } - .init.data : { - INIT_DATA - __vtop_table_begin = .; - *(.vtop_fixup); - __vtop_table_end = .; - __ptov_table_begin = .; - *(.ptov_fixup); - __ptov_table_end = .; - } - . = ALIGN(16); - __setup_start = .; - .init.setup : { *(.init.setup) } - __setup_end = .; - __initcall_start = .; - .initcall.init : { - INITCALLS - } - __initcall_end = .; - - __con_initcall_start = .; - .con_initcall.init : { *(.con_initcall.init) } - __con_initcall_end = .; - - SECURITY_INIT - - __start___ftr_fixup = .; - __ftr_fixup : { *(__ftr_fixup) } - __stop___ftr_fixup = .; - - PERCPU(4096) - -#ifdef CONFIG_BLK_DEV_INITRD - . = ALIGN(4096); - __initramfs_start = .; - .init.ramfs : { *(.init.ramfs) } - __initramfs_end = .; -#endif - - . = ALIGN(4096); - __init_end = .; - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_stop = .; - - _end = . ; - PROVIDE (end = .); - - /* Sections to be discarded. */ - /DISCARD/ : { - *(.exitcall.exit) - EXIT_DATA - } -} diff --git a/arch/ppc/lib/Makefile b/arch/ppc/lib/Makefile deleted file mode 100644 index 095e661e79dd..000000000000 --- a/arch/ppc/lib/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for ppc-specific library files.. -# - -obj-y := checksum.o string.o div64.o diff --git a/arch/ppc/lib/checksum.S b/arch/ppc/lib/checksum.S deleted file mode 100644 index 7874e8a80455..000000000000 --- a/arch/ppc/lib/checksum.S +++ /dev/null @@ -1,225 +0,0 @@ -/* - * This file contains assembly-language implementations - * of IP-style 1's complement checksum routines. - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Severely hacked about by Paul Mackerras (paulus@cs.anu.edu.au). - */ - -#include -#include -#include -#include - - .text - -/* - * ip_fast_csum(buf, len) -- Optimized for IP header - * len is in words and is always >= 5. - */ -_GLOBAL(ip_fast_csum) - lwz r0,0(r3) - lwzu r5,4(r3) - addic. r4,r4,-2 - addc r0,r0,r5 - mtctr r4 - blelr- -1: lwzu r4,4(r3) - adde r0,r0,r4 - bdnz 1b - addze r0,r0 /* add in final carry */ - rlwinm r3,r0,16,0,31 /* fold two halves together */ - add r3,r0,r3 - not r3,r3 - srwi r3,r3,16 - blr - -/* - * Compute checksum of TCP or UDP pseudo-header: - * csum_tcpudp_magic(saddr, daddr, len, proto, sum) - */ -_GLOBAL(csum_tcpudp_magic) - rlwimi r5,r6,16,0,15 /* put proto in upper half of len */ - addc r0,r3,r4 /* add 4 32-bit words together */ - adde r0,r0,r5 - adde r0,r0,r7 - addze r0,r0 /* add in final carry */ - rlwinm r3,r0,16,0,31 /* fold two halves together */ - add r3,r0,r3 - not r3,r3 - srwi r3,r3,16 - blr - -/* - * computes the checksum of a memory block at buff, length len, - * and adds in "sum" (32-bit) - * - * csum_partial(buff, len, sum) - */ -_GLOBAL(csum_partial) - addic r0,r5,0 - subi r3,r3,4 - srwi. r6,r4,2 - beq 3f /* if we're doing < 4 bytes */ - andi. r5,r3,2 /* Align buffer to longword boundary */ - beq+ 1f - lhz r5,4(r3) /* do 2 bytes to get aligned */ - addi r3,r3,2 - subi r4,r4,2 - addc r0,r0,r5 - srwi. r6,r4,2 /* # words to do */ - beq 3f -1: mtctr r6 -2: lwzu r5,4(r3) /* the bdnz has zero overhead, so it should */ - adde r0,r0,r5 /* be unnecessary to unroll this loop */ - bdnz 2b - andi. r4,r4,3 -3: cmpwi 0,r4,2 - blt+ 4f - lhz r5,4(r3) - addi r3,r3,2 - subi r4,r4,2 - adde r0,r0,r5 -4: cmpwi 0,r4,1 - bne+ 5f - lbz r5,4(r3) - slwi r5,r5,8 /* Upper byte of word */ - adde r0,r0,r5 -5: addze r3,r0 /* add in final carry */ - blr - -/* - * Computes the checksum of a memory block at src, length len, - * and adds in "sum" (32-bit), while copying the block to dst. - * If an access exception occurs on src or dst, it stores -EFAULT - * to *src_err or *dst_err respectively, and (for an error on - * src) zeroes the rest of dst. - * - * csum_partial_copy_generic(src, dst, len, sum, src_err, dst_err) - */ -_GLOBAL(csum_partial_copy_generic) - addic r0,r6,0 - subi r3,r3,4 - subi r4,r4,4 - srwi. r6,r5,2 - beq 3f /* if we're doing < 4 bytes */ - andi. r9,r4,2 /* Align dst to longword boundary */ - beq+ 1f -81: lhz r6,4(r3) /* do 2 bytes to get aligned */ - addi r3,r3,2 - subi r5,r5,2 -91: sth r6,4(r4) - addi r4,r4,2 - addc r0,r0,r6 - srwi. r6,r5,2 /* # words to do */ - beq 3f -1: srwi. r6,r5,4 /* # groups of 4 words to do */ - beq 10f - mtctr r6 -71: lwz r6,4(r3) -72: lwz r9,8(r3) -73: lwz r10,12(r3) -74: lwzu r11,16(r3) - adde r0,r0,r6 -75: stw r6,4(r4) - adde r0,r0,r9 -76: stw r9,8(r4) - adde r0,r0,r10 -77: stw r10,12(r4) - adde r0,r0,r11 -78: stwu r11,16(r4) - bdnz 71b -10: rlwinm. r6,r5,30,30,31 /* # words left to do */ - beq 13f - mtctr r6 -82: lwzu r9,4(r3) -92: stwu r9,4(r4) - adde r0,r0,r9 - bdnz 82b -13: andi. r5,r5,3 -3: cmpwi 0,r5,2 - blt+ 4f -83: lhz r6,4(r3) - addi r3,r3,2 - subi r5,r5,2 -93: sth r6,4(r4) - addi r4,r4,2 - adde r0,r0,r6 -4: cmpwi 0,r5,1 - bne+ 5f -84: lbz r6,4(r3) -94: stb r6,4(r4) - slwi r6,r6,8 /* Upper byte of word */ - adde r0,r0,r6 -5: addze r3,r0 /* add in final carry */ - blr - -/* These shouldn't go in the fixup section, since that would - cause the ex_table addresses to get out of order. */ - -src_error_4: - mfctr r6 /* update # bytes remaining from ctr */ - rlwimi r5,r6,4,0,27 - b 79f -src_error_1: - li r6,0 - subi r5,r5,2 -95: sth r6,4(r4) - addi r4,r4,2 -79: srwi. r6,r5,2 - beq 3f - mtctr r6 -src_error_2: - li r6,0 -96: stwu r6,4(r4) - bdnz 96b -3: andi. r5,r5,3 - beq src_error -src_error_3: - li r6,0 - mtctr r5 - addi r4,r4,3 -97: stbu r6,1(r4) - bdnz 97b -src_error: - cmpwi 0,r7,0 - beq 1f - li r6,-EFAULT - stw r6,0(r7) -1: addze r3,r0 - blr - -dst_error: - cmpwi 0,r8,0 - beq 1f - li r6,-EFAULT - stw r6,0(r8) -1: addze r3,r0 - blr - -.section __ex_table,"a" - .long 81b,src_error_1 - .long 91b,dst_error - .long 71b,src_error_4 - .long 72b,src_error_4 - .long 73b,src_error_4 - .long 74b,src_error_4 - .long 75b,dst_error - .long 76b,dst_error - .long 77b,dst_error - .long 78b,dst_error - .long 82b,src_error_2 - .long 92b,dst_error - .long 83b,src_error_3 - .long 93b,dst_error - .long 84b,src_error_3 - .long 94b,dst_error - .long 95b,dst_error - .long 96b,dst_error - .long 97b,dst_error diff --git a/arch/ppc/lib/div64.S b/arch/ppc/lib/div64.S deleted file mode 100644 index 3527569e9926..000000000000 --- a/arch/ppc/lib/div64.S +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Divide a 64-bit unsigned number by a 32-bit unsigned number. - * This routine assumes that the top 32 bits of the dividend are - * non-zero to start with. - * On entry, r3 points to the dividend, which get overwritten with - * the 64-bit quotient, and r4 contains the divisor. - * On exit, r3 contains the remainder. - * - * Copyright (C) 2002 Paul Mackerras, IBM Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#include -#include - -_GLOBAL(__div64_32) - lwz r5,0(r3) # get the dividend into r5/r6 - lwz r6,4(r3) - cmplw r5,r4 - li r7,0 - li r8,0 - blt 1f - divwu r7,r5,r4 # if dividend.hi >= divisor, - mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor - subf. r5,r0,r5 # dividend.hi %= divisor - beq 3f -1: mr r11,r5 # here dividend.hi != 0 - andis. r0,r5,0xc000 - bne 2f - cntlzw r0,r5 # we are shifting the dividend right - li r10,-1 # to make it < 2^32, and shifting - srw r10,r10,r0 # the divisor right the same amount, - add r9,r4,r10 # rounding up (so the estimate cannot - andc r11,r6,r10 # ever be too large, only too small) - andc r9,r9,r10 - or r11,r5,r11 - rotlw r9,r9,r0 - rotlw r11,r11,r0 - divwu r11,r11,r9 # then we divide the shifted quantities -2: mullw r10,r11,r4 # to get an estimate of the quotient, - mulhwu r9,r11,r4 # multiply the estimate by the divisor, - subfc r6,r10,r6 # take the product from the divisor, - add r8,r8,r11 # and add the estimate to the accumulated - subfe. r5,r9,r5 # quotient - bne 1b -3: cmplw r6,r4 - blt 4f - divwu r0,r6,r4 # perform the remaining 32-bit division - mullw r10,r0,r4 # and get the remainder - add r8,r8,r0 - subf r6,r10,r6 -4: stw r7,0(r3) # return the quotient in *r3 - stw r8,4(r3) - mr r3,r6 # return the remainder in r3 - blr diff --git a/arch/ppc/lib/locks.c b/arch/ppc/lib/locks.c deleted file mode 100644 index ea4aee6b20e6..000000000000 --- a/arch/ppc/lib/locks.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Locks for smp ppc - * - * Written by Cort Dougan (cort@cs.nmt.edu) - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_DEBUG_SPINLOCK - -#undef INIT_STUCK -#define INIT_STUCK 200000000 /*0xffffffff*/ - -/* - * Try to acquire a spinlock. - * Only does the stwcx. if the load returned 0 - the Programming - * Environments Manual suggests not doing unnecessary stcwx.'s - * since they may inhibit forward progress by other CPUs in getting - * a lock. - */ -static inline unsigned long __spin_trylock(volatile unsigned long *lock) -{ - unsigned long ret; - - __asm__ __volatile__ ("\n\ -1: lwarx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne 2f\n" - PPC405_ERR77(0,%1) -" stwcx. %2,0,%1\n\ - bne- 1b\n\ - isync\n\ -2:" - : "=&r"(ret) - : "r"(lock), "r"(1) - : "cr0", "memory"); - - return ret; -} - -void _raw_spin_lock(spinlock_t *lock) -{ - int cpu = smp_processor_id(); - unsigned int stuck = INIT_STUCK; - while (__spin_trylock(&lock->lock)) { - while ((unsigned volatile long)lock->lock != 0) { - if (!--stuck) { - printk("_spin_lock(%p) CPU#%d NIP %p" - " holder: cpu %ld pc %08lX\n", - lock, cpu, __builtin_return_address(0), - lock->owner_cpu,lock->owner_pc); - stuck = INIT_STUCK; - /* steal the lock */ - /*xchg_u32((void *)&lock->lock,0);*/ - } - } - } - lock->owner_pc = (unsigned long)__builtin_return_address(0); - lock->owner_cpu = cpu; -} -EXPORT_SYMBOL(_raw_spin_lock); - -int _raw_spin_trylock(spinlock_t *lock) -{ - if (__spin_trylock(&lock->lock)) - return 0; - lock->owner_cpu = smp_processor_id(); - lock->owner_pc = (unsigned long)__builtin_return_address(0); - return 1; -} -EXPORT_SYMBOL(_raw_spin_trylock); - -void _raw_spin_unlock(spinlock_t *lp) -{ - if ( !lp->lock ) - printk("_spin_unlock(%p): no lock cpu %d curr PC %p %s/%d\n", - lp, smp_processor_id(), __builtin_return_address(0), - current->comm, current->pid); - if ( lp->owner_cpu != smp_processor_id() ) - printk("_spin_unlock(%p): cpu %d trying clear of cpu %d pc %lx val %lx\n", - lp, smp_processor_id(), (int)lp->owner_cpu, - lp->owner_pc,lp->lock); - lp->owner_pc = lp->owner_cpu = 0; - wmb(); - lp->lock = 0; -} -EXPORT_SYMBOL(_raw_spin_unlock); - -/* - * For rwlocks, zero is unlocked, -1 is write-locked, - * positive is read-locked. - */ -static __inline__ int __read_trylock(rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( -"2: lwarx %0,0,%1 # __read_trylock\n\ - addic. %0,%0,1\n\ - ble- 1f\n" - PPC405_ERR77(0,%1) -" stwcx. %0,0,%1\n\ - bne- 2b\n\ - isync\n\ -1:" - : "=&r"(tmp) - : "r"(&rw->lock) - : "cr0", "memory"); - - return tmp; -} - -int _raw_read_trylock(rwlock_t *rw) -{ - return __read_trylock(rw) > 0; -} -EXPORT_SYMBOL(_raw_read_trylock); - -void _raw_read_lock(rwlock_t *rw) -{ - unsigned int stuck; - - while (__read_trylock(rw) <= 0) { - stuck = INIT_STUCK; - while (!read_can_lock(rw)) { - if (--stuck == 0) { - printk("_read_lock(%p) CPU#%d lock %d\n", - rw, raw_smp_processor_id(), rw->lock); - stuck = INIT_STUCK; - } - } - } -} -EXPORT_SYMBOL(_raw_read_lock); - -void _raw_read_unlock(rwlock_t *rw) -{ - if ( rw->lock == 0 ) - printk("_read_unlock(): %s/%d (nip %08lX) lock %d\n", - current->comm,current->pid,current->thread.regs->nip, - rw->lock); - wmb(); - atomic_dec((atomic_t *) &(rw)->lock); -} -EXPORT_SYMBOL(_raw_read_unlock); - -void _raw_write_lock(rwlock_t *rw) -{ - unsigned int stuck; - - while (cmpxchg(&rw->lock, 0, -1) != 0) { - stuck = INIT_STUCK; - while (!write_can_lock(rw)) { - if (--stuck == 0) { - printk("write_lock(%p) CPU#%d lock %d)\n", - rw, raw_smp_processor_id(), rw->lock); - stuck = INIT_STUCK; - } - } - } - wmb(); -} -EXPORT_SYMBOL(_raw_write_lock); - -int _raw_write_trylock(rwlock_t *rw) -{ - if (cmpxchg(&rw->lock, 0, -1) != 0) - return 0; - wmb(); - return 1; -} -EXPORT_SYMBOL(_raw_write_trylock); - -void _raw_write_unlock(rwlock_t *rw) -{ - if (rw->lock >= 0) - printk("_write_lock(): %s/%d (nip %08lX) lock %d\n", - current->comm,current->pid,current->thread.regs->nip, - rw->lock); - wmb(); - rw->lock = 0; -} -EXPORT_SYMBOL(_raw_write_unlock); - -#endif diff --git a/arch/ppc/lib/string.S b/arch/ppc/lib/string.S deleted file mode 100644 index 927253bfc826..000000000000 --- a/arch/ppc/lib/string.S +++ /dev/null @@ -1,732 +0,0 @@ -/* - * String handling functions for PowerPC. - * - * Copyright (C) 1996 Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#include -#include -#include -#include - -#define COPY_16_BYTES \ - lwz r7,4(r4); \ - lwz r8,8(r4); \ - lwz r9,12(r4); \ - lwzu r10,16(r4); \ - stw r7,4(r6); \ - stw r8,8(r6); \ - stw r9,12(r6); \ - stwu r10,16(r6) - -#define COPY_16_BYTES_WITHEX(n) \ -8 ## n ## 0: \ - lwz r7,4(r4); \ -8 ## n ## 1: \ - lwz r8,8(r4); \ -8 ## n ## 2: \ - lwz r9,12(r4); \ -8 ## n ## 3: \ - lwzu r10,16(r4); \ -8 ## n ## 4: \ - stw r7,4(r6); \ -8 ## n ## 5: \ - stw r8,8(r6); \ -8 ## n ## 6: \ - stw r9,12(r6); \ -8 ## n ## 7: \ - stwu r10,16(r6) - -#define COPY_16_BYTES_EXCODE(n) \ -9 ## n ## 0: \ - addi r5,r5,-(16 * n); \ - b 104f; \ -9 ## n ## 1: \ - addi r5,r5,-(16 * n); \ - b 105f; \ -.section __ex_table,"a"; \ - .align 2; \ - .long 8 ## n ## 0b,9 ## n ## 0b; \ - .long 8 ## n ## 1b,9 ## n ## 0b; \ - .long 8 ## n ## 2b,9 ## n ## 0b; \ - .long 8 ## n ## 3b,9 ## n ## 0b; \ - .long 8 ## n ## 4b,9 ## n ## 1b; \ - .long 8 ## n ## 5b,9 ## n ## 1b; \ - .long 8 ## n ## 6b,9 ## n ## 1b; \ - .long 8 ## n ## 7b,9 ## n ## 1b; \ - .text - - .text - .stabs "arch/ppc/lib/",N_SO,0,0,0f - .stabs "string.S",N_SO,0,0,0f - -CACHELINE_BYTES = L1_CACHE_BYTES -LG_CACHELINE_BYTES = L1_CACHE_SHIFT -CACHELINE_MASK = (L1_CACHE_BYTES-1) - -_GLOBAL(strcpy) - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r5) - bne 1b - blr - -/* This clears out any unused part of the destination buffer, - just as the libc version does. -- paulus */ -_GLOBAL(strncpy) - cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r6) - bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */ - bnelr /* if we didn't hit a null char, we're done */ - mfctr r5 - cmpwi 0,r5,0 /* any space left in destination buffer? */ - beqlr /* we know r0 == 0 here */ -2: stbu r0,1(r6) /* clear it out if so */ - bdnz 2b - blr - -_GLOBAL(strcat) - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r5) - cmpwi 0,r0,0 - bne 1b - addi r5,r5,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r5) - bne 1b - blr - -_GLOBAL(strcmp) - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r5) - cmpwi 1,r3,0 - lbzu r0,1(r4) - subf. r3,r0,r3 - beqlr 1 - beq 1b - blr - -_GLOBAL(strncmp) - PPC_LCMPI r5,0 - beqlr - mtctr r5 - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r5) - cmpwi 1,r3,0 - lbzu r0,1(r4) - subf. r3,r0,r3 - beqlr 1 - bdnzt eq,1b - blr - -_GLOBAL(strlen) - addi r4,r3,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - bne 1b - subf r3,r3,r4 - blr - -/* - * Use dcbz on the complete cache lines in the destination - * to set them to zero. This requires that the destination - * area is cacheable. -- paulus - */ -_GLOBAL(cacheable_memzero) - mr r5,r4 - li r4,0 - addi r6,r3,-4 - cmplwi 0,r5,4 - blt 7f - stwu r4,4(r6) - beqlr - andi. r0,r6,3 - add r5,r0,r5 - subf r6,r0,r6 - clrlwi r7,r6,32-LG_CACHELINE_BYTES - add r8,r7,r5 - srwi r9,r8,LG_CACHELINE_BYTES - addic. r9,r9,-1 /* total number of complete cachelines */ - ble 2f - xori r0,r7,CACHELINE_MASK & ~3 - srwi. r0,r0,2 - beq 3f - mtctr r0 -4: stwu r4,4(r6) - bdnz 4b -3: mtctr r9 - li r7,4 -#if !defined(CONFIG_8xx) -10: dcbz r7,r6 -#else -10: stw r4, 4(r6) - stw r4, 8(r6) - stw r4, 12(r6) - stw r4, 16(r6) -#if CACHE_LINE_SIZE >= 32 - stw r4, 20(r6) - stw r4, 24(r6) - stw r4, 28(r6) - stw r4, 32(r6) -#endif /* CACHE_LINE_SIZE */ -#endif - addi r6,r6,CACHELINE_BYTES - bdnz 10b - clrlwi r5,r8,32-LG_CACHELINE_BYTES - addi r5,r5,4 -2: srwi r0,r5,2 - mtctr r0 - bdz 6f -1: stwu r4,4(r6) - bdnz 1b -6: andi. r5,r5,3 -7: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r6,3 -8: stbu r4,1(r6) - bdnz 8b - blr - -_GLOBAL(memset) - rlwimi r4,r4,8,16,23 - rlwimi r4,r4,16,0,15 - addi r6,r3,-4 - cmplwi 0,r5,4 - blt 7f - stwu r4,4(r6) - beqlr - andi. r0,r6,3 - add r5,r0,r5 - subf r6,r0,r6 - srwi r0,r5,2 - mtctr r0 - bdz 6f -1: stwu r4,4(r6) - bdnz 1b -6: andi. r5,r5,3 -7: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r6,3 -8: stbu r4,1(r6) - bdnz 8b - blr - -/* - * This version uses dcbz on the complete cache lines in the - * destination area to reduce memory traffic. This requires that - * the destination area is cacheable. - * We only use this version if the source and dest don't overlap. - * -- paulus. - */ -_GLOBAL(cacheable_memcpy) - add r7,r3,r5 /* test if the src & dst overlap */ - add r8,r4,r5 - cmplw 0,r4,r7 - cmplw 1,r3,r8 - crand 0,0,4 /* cr0.lt &= cr1.lt */ - blt memcpy /* if regions overlap */ - - addi r4,r4,-4 - addi r6,r3,-4 - neg r0,r3 - andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */ - beq 58f - - cmplw 0,r5,r0 /* is this more than total to do? */ - blt 63f /* if not much to do */ - andi. r8,r0,3 /* get it word-aligned first */ - subf r5,r0,r5 - mtctr r8 - beq+ 61f -70: lbz r9,4(r4) /* do some bytes */ - stb r9,4(r6) - addi r4,r4,1 - addi r6,r6,1 - bdnz 70b -61: srwi. r0,r0,2 - mtctr r0 - beq 58f -72: lwzu r9,4(r4) /* do some words */ - stwu r9,4(r6) - bdnz 72b - -58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */ - clrlwi r5,r5,32-LG_CACHELINE_BYTES - li r11,4 - mtctr r0 - beq 63f -53: -#if !defined(CONFIG_8xx) - dcbz r11,r6 -#endif - COPY_16_BYTES -#if L1_CACHE_BYTES >= 32 - COPY_16_BYTES -#if L1_CACHE_BYTES >= 64 - COPY_16_BYTES - COPY_16_BYTES -#if L1_CACHE_BYTES >= 128 - COPY_16_BYTES - COPY_16_BYTES - COPY_16_BYTES - COPY_16_BYTES -#endif -#endif -#endif - bdnz 53b - -63: srwi. r0,r5,2 - mtctr r0 - beq 64f -30: lwzu r0,4(r4) - stwu r0,4(r6) - bdnz 30b - -64: andi. r0,r5,3 - mtctr r0 - beq+ 65f -40: lbz r0,4(r4) - stb r0,4(r6) - addi r4,r4,1 - addi r6,r6,1 - bdnz 40b -65: blr - -_GLOBAL(memmove) - cmplw 0,r3,r4 - bgt backwards_memcpy - /* fall through */ - -_GLOBAL(memcpy) - srwi. r7,r5,3 - addi r6,r3,-4 - addi r4,r4,-4 - beq 2f /* if less than 8 bytes to do */ - andi. r0,r6,3 /* get dest word aligned */ - mtctr r7 - bne 5f -1: lwz r7,4(r4) - lwzu r8,8(r4) - stw r7,4(r6) - stwu r8,8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,4(r4) - addi r5,r5,-4 - stwu r0,4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r4,r4,3 - addi r6,r6,3 -4: lbzu r0,1(r4) - stbu r0,1(r6) - bdnz 4b - blr -5: subfic r0,r0,4 - mtctr r0 -6: lbz r7,4(r4) - addi r4,r4,1 - stb r7,4(r6) - addi r6,r6,1 - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - -_GLOBAL(backwards_memcpy) - rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ - add r6,r3,r5 - add r4,r4,r5 - beq 2f - andi. r0,r6,3 - mtctr r7 - bne 5f -1: lwz r7,-4(r4) - lwzu r8,-8(r4) - stw r7,-4(r6) - stwu r8,-8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,-4(r4) - subi r5,r5,4 - stwu r0,-4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 -4: lbzu r0,-1(r4) - stbu r0,-1(r6) - bdnz 4b - blr -5: mtctr r0 -6: lbzu r7,-1(r4) - stbu r7,-1(r6) - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - -_GLOBAL(memcmp) - cmpwi 0,r5,0 - ble- 2f - mtctr r5 - addi r6,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r6) - lbzu r0,1(r4) - subf. r3,r0,r3 - bdnzt 2,1b - blr -2: li r3,0 - blr - -_GLOBAL(memchr) - cmpwi 0,r5,0 - ble- 2f - mtctr r5 - addi r3,r3,-1 -1: lbzu r0,1(r3) - cmpw 0,r0,r4 - bdnzf 2,1b - beqlr -2: li r3,0 - blr - -_GLOBAL(__copy_tofrom_user) - addi r4,r4,-4 - addi r6,r3,-4 - neg r0,r3 - andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */ - beq 58f - - cmplw 0,r5,r0 /* is this more than total to do? */ - blt 63f /* if not much to do */ - andi. r8,r0,3 /* get it word-aligned first */ - mtctr r8 - beq+ 61f -70: lbz r9,4(r4) /* do some bytes */ -71: stb r9,4(r6) - addi r4,r4,1 - addi r6,r6,1 - bdnz 70b -61: subf r5,r0,r5 - srwi. r0,r0,2 - mtctr r0 - beq 58f -72: lwzu r9,4(r4) /* do some words */ -73: stwu r9,4(r6) - bdnz 72b - - .section __ex_table,"a" - .align 2 - .long 70b,100f - .long 71b,101f - .long 72b,102f - .long 73b,103f - .text - -58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */ - clrlwi r5,r5,32-LG_CACHELINE_BYTES - li r11,4 - beq 63f - -#ifdef CONFIG_8xx - /* Don't use prefetch on 8xx */ - mtctr r0 - li r0,0 -53: COPY_16_BYTES_WITHEX(0) - bdnz 53b - -#else /* not CONFIG_8xx */ - /* Here we decide how far ahead to prefetch the source */ - li r3,4 - cmpwi r0,1 - li r7,0 - ble 114f - li r7,1 -#if MAX_COPY_PREFETCH > 1 - /* Heuristically, for large transfers we prefetch - MAX_COPY_PREFETCH cachelines ahead. For small transfers - we prefetch 1 cacheline ahead. */ - cmpwi r0,MAX_COPY_PREFETCH - ble 112f - li r7,MAX_COPY_PREFETCH -112: mtctr r7 -111: dcbt r3,r4 - addi r3,r3,CACHELINE_BYTES - bdnz 111b -#else - dcbt r3,r4 - addi r3,r3,CACHELINE_BYTES -#endif /* MAX_COPY_PREFETCH > 1 */ - -114: subf r8,r7,r0 - mr r0,r7 - mtctr r8 - -53: dcbt r3,r4 -54: dcbz r11,r6 - .section __ex_table,"a" - .align 2 - .long 54b,105f - .text -/* the main body of the cacheline loop */ - COPY_16_BYTES_WITHEX(0) -#if L1_CACHE_BYTES >= 32 - COPY_16_BYTES_WITHEX(1) -#if L1_CACHE_BYTES >= 64 - COPY_16_BYTES_WITHEX(2) - COPY_16_BYTES_WITHEX(3) -#if L1_CACHE_BYTES >= 128 - COPY_16_BYTES_WITHEX(4) - COPY_16_BYTES_WITHEX(5) - COPY_16_BYTES_WITHEX(6) - COPY_16_BYTES_WITHEX(7) -#endif -#endif -#endif - bdnz 53b - cmpwi r0,0 - li r3,4 - li r7,0 - bne 114b -#endif /* CONFIG_8xx */ - -63: srwi. r0,r5,2 - mtctr r0 - beq 64f -30: lwzu r0,4(r4) -31: stwu r0,4(r6) - bdnz 30b - -64: andi. r0,r5,3 - mtctr r0 - beq+ 65f -40: lbz r0,4(r4) -41: stb r0,4(r6) - addi r4,r4,1 - addi r6,r6,1 - bdnz 40b -65: li r3,0 - blr - -/* read fault, initial single-byte copy */ -100: li r9,0 - b 90f -/* write fault, initial single-byte copy */ -101: li r9,1 -90: subf r5,r8,r5 - li r3,0 - b 99f -/* read fault, initial word copy */ -102: li r9,0 - b 91f -/* write fault, initial word copy */ -103: li r9,1 -91: li r3,2 - b 99f - -/* - * this stuff handles faults in the cacheline loop and branches to either - * 104f (if in read part) or 105f (if in write part), after updating r5 - */ - COPY_16_BYTES_EXCODE(0) -#if L1_CACHE_BYTES >= 32 - COPY_16_BYTES_EXCODE(1) -#if L1_CACHE_BYTES >= 64 - COPY_16_BYTES_EXCODE(2) - COPY_16_BYTES_EXCODE(3) -#if L1_CACHE_BYTES >= 128 - COPY_16_BYTES_EXCODE(4) - COPY_16_BYTES_EXCODE(5) - COPY_16_BYTES_EXCODE(6) - COPY_16_BYTES_EXCODE(7) -#endif -#endif -#endif - -/* read fault in cacheline loop */ -104: li r9,0 - b 92f -/* fault on dcbz (effectively a write fault) */ -/* or write fault in cacheline loop */ -105: li r9,1 -92: li r3,LG_CACHELINE_BYTES - mfctr r8 - add r0,r0,r8 - b 106f -/* read fault in final word loop */ -108: li r9,0 - b 93f -/* write fault in final word loop */ -109: li r9,1 -93: andi. r5,r5,3 - li r3,2 - b 99f -/* read fault in final byte loop */ -110: li r9,0 - b 94f -/* write fault in final byte loop */ -111: li r9,1 -94: li r5,0 - li r3,0 -/* - * At this stage the number of bytes not copied is - * r5 + (ctr << r3), and r9 is 0 for read or 1 for write. - */ -99: mfctr r0 -106: slw r3,r0,r3 - add. r3,r3,r5 - beq 120f /* shouldn't happen */ - cmpwi 0,r9,0 - bne 120f -/* for a read fault, first try to continue the copy one byte at a time */ - mtctr r3 -130: lbz r0,4(r4) -131: stb r0,4(r6) - addi r4,r4,1 - addi r6,r6,1 - bdnz 130b -/* then clear out the destination: r3 bytes starting at 4(r6) */ -132: mfctr r3 - srwi. r0,r3,2 - li r9,0 - mtctr r0 - beq 113f -112: stwu r9,4(r6) - bdnz 112b -113: andi. r0,r3,3 - mtctr r0 - beq 120f -114: stb r9,4(r6) - addi r6,r6,1 - bdnz 114b -120: blr - - .section __ex_table,"a" - .align 2 - .long 30b,108b - .long 31b,109b - .long 40b,110b - .long 41b,111b - .long 130b,132b - .long 131b,120b - .long 112b,120b - .long 114b,120b - .text - -_GLOBAL(__clear_user) - addi r6,r3,-4 - li r3,0 - li r5,0 - cmplwi 0,r4,4 - blt 7f - /* clear a single word */ -11: stwu r5,4(r6) - beqlr - /* clear word sized chunks */ - andi. r0,r6,3 - add r4,r0,r4 - subf r6,r0,r6 - srwi r0,r4,2 - andi. r4,r4,3 - mtctr r0 - bdz 7f -1: stwu r5,4(r6) - bdnz 1b - /* clear byte sized chunks */ -7: cmpwi 0,r4,0 - beqlr - mtctr r4 - addi r6,r6,3 -8: stbu r5,1(r6) - bdnz 8b - blr -90: mr r3,r4 - blr -91: mfctr r3 - slwi r3,r3,2 - add r3,r3,r4 - blr -92: mfctr r3 - blr - - .section __ex_table,"a" - .align 2 - .long 11b,90b - .long 1b,91b - .long 8b,92b - .text - -_GLOBAL(__strncpy_from_user) - addi r6,r3,-1 - addi r4,r4,-1 - cmpwi 0,r5,0 - beq 2f - mtctr r5 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r6) - bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */ - beq 3f -2: addi r6,r6,1 -3: subf r3,r3,r6 - blr -99: li r3,-EFAULT - blr - - .section __ex_table,"a" - .align 2 - .long 1b,99b - .text - -/* r3 = str, r4 = len (> 0), r5 = top (highest addr) */ -_GLOBAL(__strnlen_user) - addi r7,r3,-1 - subf r6,r7,r5 /* top+1 - str */ - cmplw 0,r4,r6 - bge 0f - mr r6,r4 -0: mtctr r6 /* ctr = min(len, top - str) */ -1: lbzu r0,1(r7) /* get next byte */ - cmpwi 0,r0,0 - bdnzf 2,1b /* loop if --ctr != 0 && byte != 0 */ - addi r7,r7,1 - subf r3,r3,r7 /* number of bytes we have looked at */ - beqlr /* return if we found a 0 byte */ - cmpw 0,r3,r4 /* did we look at all len bytes? */ - blt 99f /* if not, must have hit top */ - addi r3,r4,1 /* return len + 1 to indicate no null found */ - blr -99: li r3,0 /* bad address, return 0 */ - blr - - .section __ex_table,"a" - .align 2 - .long 1b,99b diff --git a/arch/ppc/mm/44x_mmu.c b/arch/ppc/mm/44x_mmu.c deleted file mode 100644 index fbb577a0d165..000000000000 --- a/arch/ppc/mm/44x_mmu.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Modifications by Matt Porter (mporter@mvista.com) to support - * PPC44x Book E processors. - * - * This file contains the routines for initializing the MMU - * on the 4xx series of chips. - * -- paulus - * - * Derived from arch/ppc/mm/init.c: - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) - * and Cort Dougan (PReP) (cort@cs.nmt.edu) - * Copyright (C) 1996 Paul Mackerras - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). - * - * Derived from "arch/i386/mm/init.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mmu_decl.h" - -extern char etext[], _stext[]; - -/* Used by the 44x TLB replacement exception handler. - * Just needed it declared someplace. - */ -unsigned int tlb_44x_index = 0; -unsigned int tlb_44x_hwater = PPC4XX_TLB_SIZE - 1 - PPC44x_EARLY_TLBS; -int icache_44x_need_flush; - -/* - * "Pins" a 256MB TLB entry in AS0 for kernel lowmem - */ -static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys) -{ - __asm__ __volatile__( - "tlbwe %2,%3,%4\n" - "tlbwe %1,%3,%5\n" - "tlbwe %0,%3,%6\n" - : - : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G), - "r" (phys), - "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M), - "r" (tlb_44x_hwater--), /* slot for this TLB entry */ - "i" (PPC44x_TLB_PAGEID), - "i" (PPC44x_TLB_XLAT), - "i" (PPC44x_TLB_ATTRIB)); -} - -void __init MMU_init_hw(void) -{ - flush_instruction_cache(); -} - -unsigned long __init mmu_mapin_ram(void) -{ - unsigned long addr; - - /* Pin in enough TLBs to cover any lowmem not covered by the - * initial 256M mapping established in head_44x.S */ - for (addr = PPC_PIN_SIZE; addr < total_lowmem; - addr += PPC_PIN_SIZE) - ppc44x_pin_tlb(addr + PAGE_OFFSET, addr); - - return total_lowmem; -} diff --git a/arch/ppc/mm/4xx_mmu.c b/arch/ppc/mm/4xx_mmu.c deleted file mode 100644 index ea785dbaac7c..000000000000 --- a/arch/ppc/mm/4xx_mmu.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file contains the routines for initializing the MMU - * on the 4xx series of chips. - * -- paulus - * - * Derived from arch/ppc/mm/init.c: - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) - * and Cort Dougan (PReP) (cort@cs.nmt.edu) - * Copyright (C) 1996 Paul Mackerras - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). - * - * Derived from "arch/i386/mm/init.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mmu_decl.h" - -extern int __map_without_ltlbs; -/* - * MMU_init_hw does the chip-specific initialization of the MMU hardware. - */ -void __init MMU_init_hw(void) -{ - /* - * The Zone Protection Register (ZPR) defines how protection will - * be applied to every page which is a member of a given zone. At - * present, we utilize only two of the 4xx's zones. - * The zone index bits (of ZSEL) in the PTE are used for software - * indicators, except the LSB. For user access, zone 1 is used, - * for kernel access, zone 0 is used. We set all but zone 1 - * to zero, allowing only kernel access as indicated in the PTE. - * For zone 1, we set a 01 binary (a value of 10 will not work) - * to allow user access as indicated in the PTE. This also allows - * kernel access as indicated in the PTE. - */ - - mtspr(SPRN_ZPR, 0x10000000); - - flush_instruction_cache(); - - /* - * Set up the real-mode cache parameters for the exception vector - * handlers (which are run in real-mode). - */ - - mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */ - - /* - * Cache instruction and data space where the exception - * vectors and the kernel live in real-mode. - */ - - mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */ - mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */ -} - -#define LARGE_PAGE_SIZE_16M (1<<24) -#define LARGE_PAGE_SIZE_4M (1<<22) - -unsigned long __init mmu_mapin_ram(void) -{ - unsigned long v, s; - phys_addr_t p; - - v = KERNELBASE; - p = PPC_MEMSTART; - s = total_lowmem; - - if (__map_without_ltlbs) - return 0; - - while (s >= LARGE_PAGE_SIZE_16M) { - pmd_t *pmdp; - unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE; - - pmdp = pmd_offset(pgd_offset_k(v), v); - pmd_val(*pmdp++) = val; - pmd_val(*pmdp++) = val; - pmd_val(*pmdp++) = val; - pmd_val(*pmdp++) = val; - - v += LARGE_PAGE_SIZE_16M; - p += LARGE_PAGE_SIZE_16M; - s -= LARGE_PAGE_SIZE_16M; - } - - while (s >= LARGE_PAGE_SIZE_4M) { - pmd_t *pmdp; - unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE; - - pmdp = pmd_offset(pgd_offset_k(v), v); - pmd_val(*pmdp) = val; - - v += LARGE_PAGE_SIZE_4M; - p += LARGE_PAGE_SIZE_4M; - s -= LARGE_PAGE_SIZE_4M; - } - - return total_lowmem - s; -} diff --git a/arch/ppc/mm/Makefile b/arch/ppc/mm/Makefile deleted file mode 100644 index 691ba2bae05d..000000000000 --- a/arch/ppc/mm/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile for the linux ppc-specific parts of the memory manager. -# - -obj-y := fault.o init.o mem_pieces.o \ - mmu_context.o pgtable.o - -obj-$(CONFIG_PPC_STD_MMU) += hashtable.o ppc_mmu.o tlb.o -obj-$(CONFIG_40x) += 4xx_mmu.o -obj-$(CONFIG_44x) += 44x_mmu.o diff --git a/arch/ppc/mm/fault.c b/arch/ppc/mm/fault.c deleted file mode 100644 index 36c0e7529edb..000000000000 --- a/arch/ppc/mm/fault.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * PowerPC version - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Derived from "arch/i386/mm/fault.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * Modified by Cort Dougan and Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) -extern void (*debugger)(struct pt_regs *); -extern void (*debugger_fault_handler)(struct pt_regs *); -extern int (*debugger_dabr_match)(struct pt_regs *); -int debugger_kernel_faults = 1; -#endif - -unsigned long htab_reloads; /* updated by hashtable.S:hash_page() */ -unsigned long htab_evicts; /* updated by hashtable.S:hash_page() */ -unsigned long htab_preloads; /* updated by hashtable.S:add_hash_page() */ -unsigned long pte_misses; /* updated by do_page_fault() */ -unsigned long pte_errors; /* updated by do_page_fault() */ -unsigned int probingmem; - -/* - * Check whether the instruction at regs->nip is a store using - * an update addressing form which will update r1. - */ -static int store_updates_sp(struct pt_regs *regs) -{ - unsigned int inst; - - if (get_user(inst, (unsigned int __user *)regs->nip)) - return 0; - /* check for 1 in the rA field */ - if (((inst >> 16) & 0x1f) != 1) - return 0; - /* check major opcode */ - switch (inst >> 26) { - case 37: /* stwu */ - case 39: /* stbu */ - case 45: /* sthu */ - case 53: /* stfsu */ - case 55: /* stfdu */ - return 1; - case 31: - /* check minor opcode */ - switch ((inst >> 1) & 0x3ff) { - case 183: /* stwux */ - case 247: /* stbux */ - case 439: /* sthux */ - case 695: /* stfsux */ - case 759: /* stfdux */ - return 1; - } - } - return 0; -} - -/* - * For 600- and 800-family processors, the error_code parameter is DSISR - * for a data fault, SRR1 for an instruction fault. For 400-family processors - * the error_code parameter is ESR for a data fault, 0 for an instruction - * fault. - */ -int do_page_fault(struct pt_regs *regs, unsigned long address, - unsigned long error_code) -{ - struct vm_area_struct * vma; - struct mm_struct *mm = current->mm; - siginfo_t info; - int code = SEGV_MAPERR; - int fault; -#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE) - int is_write = error_code & ESR_DST; -#else - int is_write = 0; - - /* - * Fortunately the bit assignments in SRR1 for an instruction - * fault and DSISR for a data fault are mostly the same for the - * bits we are interested in. But there are some bits which - * indicate errors in DSISR but can validly be set in SRR1. - */ - if (TRAP(regs) == 0x400) - error_code &= 0x48200000; - else - is_write = error_code & 0x02000000; -#endif /* CONFIG_4xx || CONFIG_BOOKE */ - -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) - if (debugger_fault_handler && TRAP(regs) == 0x300) { - debugger_fault_handler(regs); - return 0; - } -#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) - if (error_code & 0x00400000) { - /* DABR match */ - if (debugger_dabr_match(regs)) - return 0; - } -#endif /* !(CONFIG_4xx || CONFIG_BOOKE)*/ -#endif /* CONFIG_XMON || CONFIG_KGDB */ - - if (in_atomic() || mm == NULL) - return SIGSEGV; - - down_read(&mm->mmap_sem); - vma = find_vma(mm, address); - if (!vma) - goto bad_area; - if (vma->vm_start <= address) - goto good_area; - if (!(vma->vm_flags & VM_GROWSDOWN)) - goto bad_area; - if (!is_write) - goto bad_area; - - /* - * N.B. The rs6000/xcoff ABI allows programs to access up to - * a few hundred bytes below the stack pointer. - * The kernel signal delivery code writes up to about 1.5kB - * below the stack pointer (r1) before decrementing it. - * The exec code can write slightly over 640kB to the stack - * before setting the user r1. Thus we allow the stack to - * expand to 1MB without further checks. - */ - if (address + 0x100000 < vma->vm_end) { - /* get user regs even if this fault is in kernel mode */ - struct pt_regs *uregs = current->thread.regs; - if (uregs == NULL) - goto bad_area; - - /* - * A user-mode access to an address a long way below - * the stack pointer is only valid if the instruction - * is one which would update the stack pointer to the - * address accessed if the instruction completed, - * i.e. either stwu rs,n(r1) or stwux rs,r1,rb - * (or the byte, halfword, float or double forms). - * - * If we don't check this then any write to the area - * between the last mapped region and the stack will - * expand the stack rather than segfaulting. - */ - if (address + 2048 < uregs->gpr[1] - && (!user_mode(regs) || !store_updates_sp(regs))) - goto bad_area; - } - if (expand_stack(vma, address)) - goto bad_area; - -good_area: - code = SEGV_ACCERR; -#if defined(CONFIG_6xx) - if (error_code & 0x95700000) - /* an error such as lwarx to I/O controller space, - address matching DABR, eciwx, etc. */ - goto bad_area; -#endif /* CONFIG_6xx */ -#if defined(CONFIG_8xx) - /* The MPC8xx seems to always set 0x80000000, which is - * "undefined". Of those that can be set, this is the only - * one which seems bad. - */ - if (error_code & 0x10000000) - /* Guarded storage error. */ - goto bad_area; -#endif /* CONFIG_8xx */ - - /* a write */ - if (is_write) { - if (!(vma->vm_flags & VM_WRITE)) - goto bad_area; -#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) - /* an exec - 4xx/Book-E allows for per-page execute permission */ - } else if (TRAP(regs) == 0x400) { - pte_t *ptep; - pmd_t *pmdp; - -#if 0 - /* It would be nice to actually enforce the VM execute - permission on CPUs which can do so, but far too - much stuff in userspace doesn't get the permissions - right, so we let any page be executed for now. */ - if (! (vma->vm_flags & VM_EXEC)) - goto bad_area; -#endif - - /* Since 4xx/Book-E supports per-page execute permission, - * we lazily flush dcache to icache. */ - ptep = NULL; - if (get_pteptr(mm, address, &ptep, &pmdp)) { - spinlock_t *ptl = pte_lockptr(mm, pmdp); - spin_lock(ptl); - if (pte_present(*ptep)) { - struct page *page = pte_page(*ptep); - - if (!test_bit(PG_arch_1, &page->flags)) { - flush_dcache_icache_page(page); - set_bit(PG_arch_1, &page->flags); - } - pte_update(ptep, 0, _PAGE_HWEXEC); - _tlbie(address, mm->context.id); - pte_unmap_unlock(ptep, ptl); - up_read(&mm->mmap_sem); - return 0; - } - pte_unmap_unlock(ptep, ptl); - } -#endif - /* a read */ - } else { - /* protection fault */ - if (error_code & 0x08000000) - goto bad_area; - if (!(vma->vm_flags & (VM_READ | VM_EXEC | VM_WRITE))) - goto bad_area; - } - - /* - * If for any reason at all we couldn't handle the fault, - * make sure we exit gracefully rather than endlessly redo - * the fault. - */ - survive: - fault = handle_mm_fault(mm, vma, address, is_write); - if (unlikely(fault & VM_FAULT_ERROR)) { - if (fault & VM_FAULT_OOM) - goto out_of_memory; - else if (fault & VM_FAULT_SIGBUS) - goto do_sigbus; - BUG(); - } - if (fault & VM_FAULT_MAJOR) - current->maj_flt++; - else - current->min_flt++; - - up_read(&mm->mmap_sem); - /* - * keep track of tlb+htab misses that are good addrs but - * just need pte's created via handle_mm_fault() - * -- Cort - */ - pte_misses++; - return 0; - -bad_area: - up_read(&mm->mmap_sem); - pte_errors++; - - /* User mode accesses cause a SIGSEGV */ - if (user_mode(regs)) { - _exception(SIGSEGV, regs, code, address); - return 0; - } - - return SIGSEGV; - -/* - * We ran out of memory, or some other thing happened to us that made - * us unable to handle the page fault gracefully. - */ -out_of_memory: - up_read(&mm->mmap_sem); - if (is_global_init(current)) { - yield(); - down_read(&mm->mmap_sem); - goto survive; - } - printk("VM: killing process %s\n", current->comm); - if (user_mode(regs)) - do_group_exit(SIGKILL); - return SIGKILL; - -do_sigbus: - up_read(&mm->mmap_sem); - info.si_signo = SIGBUS; - info.si_errno = 0; - info.si_code = BUS_ADRERR; - info.si_addr = (void __user *)address; - force_sig_info (SIGBUS, &info, current); - if (!user_mode(regs)) - return SIGBUS; - return 0; -} - -/* - * bad_page_fault is called when we have a bad access from the kernel. - * It is called from the DSI and ISI handlers in head.S and from some - * of the procedures in traps.c. - */ -void -bad_page_fault(struct pt_regs *regs, unsigned long address, int sig) -{ - const struct exception_table_entry *entry; - - /* Are we prepared to handle this fault? */ - if ((entry = search_exception_tables(regs->nip)) != NULL) { - regs->nip = entry->fixup; - return; - } - - /* kernel has accessed a bad area */ -#if defined(CONFIG_XMON) || defined(CONFIG_KGDB) - if (debugger_kernel_faults) - debugger(regs); -#endif - die("kernel access of bad area", regs, sig); -} - -#ifdef CONFIG_8xx - -/* The pgtable.h claims some functions generically exist, but I - * can't find them...... - */ -pte_t *va_to_pte(unsigned long address) -{ - pgd_t *dir; - pmd_t *pmd; - pte_t *pte; - - if (address < TASK_SIZE) - return NULL; - - dir = pgd_offset(&init_mm, address); - if (dir) { - pmd = pmd_offset(dir, address & PAGE_MASK); - if (pmd && pmd_present(*pmd)) { - pte = pte_offset_kernel(pmd, address & PAGE_MASK); - if (pte && pte_present(*pte)) - return(pte); - } - } - return NULL; -} - -unsigned long va_to_phys(unsigned long address) -{ - pte_t *pte; - - pte = va_to_pte(address); - if (pte) - return(((unsigned long)(pte_val(*pte)) & PAGE_MASK) | (address & ~(PAGE_MASK))); - return (0); -} - -void -print_8xx_pte(struct mm_struct *mm, unsigned long addr) -{ - pgd_t * pgd; - pmd_t * pmd; - pte_t * pte; - - printk(" pte @ 0x%8lx: ", addr); - pgd = pgd_offset(mm, addr & PAGE_MASK); - if (pgd) { - pmd = pmd_offset(pgd, addr & PAGE_MASK); - if (pmd && pmd_present(*pmd)) { - pte = pte_offset_kernel(pmd, addr & PAGE_MASK); - if (pte) { - printk(" (0x%08lx)->(0x%08lx)->0x%08lx\n", - (long)pgd, (long)pte, (long)pte_val(*pte)); -#define pp ((long)pte_val(*pte)) - printk(" RPN: %05lx PP: %lx SPS: %lx SH: %lx " - "CI: %lx v: %lx\n", - pp>>12, /* rpn */ - (pp>>10)&3, /* pp */ - (pp>>3)&1, /* small */ - (pp>>2)&1, /* shared */ - (pp>>1)&1, /* cache inhibit */ - pp&1 /* valid */ - ); -#undef pp - } - else { - printk("no pte\n"); - } - } - else { - printk("no pmd\n"); - } - } - else { - printk("no pgd\n"); - } -} - -int -get_8xx_pte(struct mm_struct *mm, unsigned long addr) -{ - pgd_t * pgd; - pmd_t * pmd; - pte_t * pte; - int retval = 0; - - pgd = pgd_offset(mm, addr & PAGE_MASK); - if (pgd) { - pmd = pmd_offset(pgd, addr & PAGE_MASK); - if (pmd && pmd_present(*pmd)) { - pte = pte_offset_kernel(pmd, addr & PAGE_MASK); - if (pte) { - retval = (int)pte_val(*pte); - } - } - } - return(retval); -} -#endif /* CONFIG_8xx */ diff --git a/arch/ppc/mm/hashtable.S b/arch/ppc/mm/hashtable.S deleted file mode 100644 index 5f364dc50154..000000000000 --- a/arch/ppc/mm/hashtable.S +++ /dev/null @@ -1,617 +0,0 @@ -/* - * $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $ - * - * PowerPC version - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP - * Copyright (C) 1996 Cort Dougan - * Adapted for Power Macintosh by Paul Mackerras. - * Low-level exception handlers and MMU support - * rewritten by Paul Mackerras. - * Copyright (C) 1996 Paul Mackerras. - * - * This file contains low-level assembler routines for managing - * the PowerPC MMU hash table. (PPC 8xx processors don't use a - * hash table, so this file is not used on them.) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SMP - .section .bss - .align 2 - .globl mmu_hash_lock -mmu_hash_lock: - .space 4 -#endif /* CONFIG_SMP */ - -/* - * Sync CPUs with hash_page taking & releasing the hash - * table lock - */ -#ifdef CONFIG_SMP - .text -_GLOBAL(hash_page_sync) - lis r8,mmu_hash_lock@h - ori r8,r8,mmu_hash_lock@l - lis r0,0x0fff - b 10f -11: lwz r6,0(r8) - cmpwi 0,r6,0 - bne 11b -10: lwarx r6,0,r8 - cmpwi 0,r6,0 - bne- 11b - stwcx. r0,0,r8 - bne- 10b - isync - eieio - li r0,0 - stw r0,0(r8) - blr -#endif - -/* - * Load a PTE into the hash table, if possible. - * The address is in r4, and r3 contains an access flag: - * _PAGE_RW (0x400) if a write. - * r9 contains the SRR1 value, from which we use the MSR_PR bit. - * SPRG3 contains the physical address of the current task's thread. - * - * Returns to the caller if the access is illegal or there is no - * mapping for the address. Otherwise it places an appropriate PTE - * in the hash table and returns from the exception. - * Uses r0, r3 - r8, ctr, lr. - */ - .text -_GLOBAL(hash_page) - tophys(r7,0) /* gets -KERNELBASE into r7 */ -#ifdef CONFIG_SMP - addis r8,r7,mmu_hash_lock@h - ori r8,r8,mmu_hash_lock@l - lis r0,0x0fff - b 10f -11: lwz r6,0(r8) - cmpwi 0,r6,0 - bne 11b -10: lwarx r6,0,r8 - cmpwi 0,r6,0 - bne- 11b - stwcx. r0,0,r8 - bne- 10b - isync -#endif - /* Get PTE (linux-style) and check access */ - lis r0,KERNELBASE@h /* check if kernel address */ - cmplw 0,r4,r0 - mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */ - ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ - lwz r5,PGDIR(r8) /* virt page-table root */ - blt+ 112f /* assume user more likely */ - lis r5,swapper_pg_dir@ha /* if kernel address, use */ - addi r5,r5,swapper_pg_dir@l /* kernel page table */ - rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ -112: add r5,r5,r7 /* convert to phys addr */ - rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ - lwz r8,0(r5) /* get pmd entry */ - rlwinm. r8,r8,0,0,19 /* extract address of pte page */ -#ifdef CONFIG_SMP - beq- hash_page_out /* return if no mapping */ -#else - /* XXX it seems like the 601 will give a machine fault on the - rfi if its alignment is wrong (bottom 4 bits of address are - 8 or 0xc) and we have had a not-taken conditional branch - to the address following the rfi. */ - beqlr- -#endif - rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ - rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ - ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE - - /* - * Update the linux PTE atomically. We do the lwarx up-front - * because almost always, there won't be a permission violation - * and there won't already be an HPTE, and thus we will have - * to update the PTE to set _PAGE_HASHPTE. -- paulus. - */ -retry: - lwarx r6,0,r8 /* get linux-style pte */ - andc. r5,r3,r6 /* check access & ~permission */ -#ifdef CONFIG_SMP - bne- hash_page_out /* return if access not permitted */ -#else - bnelr- -#endif - or r5,r0,r6 /* set accessed/dirty bits */ - stwcx. r5,0,r8 /* attempt to update PTE */ - bne- retry /* retry if someone got there first */ - - mfsrin r3,r4 /* get segment reg for segment */ - mfctr r0 - stw r0,_CTR(r11) - bl create_hpte /* add the hash table entry */ - -/* - * htab_reloads counts the number of times we have to fault an - * HPTE into the hash table. This should only happen after a - * fork (because fork does a flush_tlb_mm) or a vmalloc or ioremap. - * Where a page is faulted into a process's address space, - * update_mmu_cache gets called to put the HPTE into the hash table - * and those are counted as preloads rather than reloads. - */ - addis r8,r7,htab_reloads@ha - lwz r3,htab_reloads@l(r8) - addi r3,r3,1 - stw r3,htab_reloads@l(r8) - -#ifdef CONFIG_SMP - eieio - addis r8,r7,mmu_hash_lock@ha - li r0,0 - stw r0,mmu_hash_lock@l(r8) -#endif - - /* Return from the exception */ - lwz r5,_CTR(r11) - mtctr r5 - lwz r0,GPR0(r11) - lwz r7,GPR7(r11) - lwz r8,GPR8(r11) - b fast_exception_return - -#ifdef CONFIG_SMP -hash_page_out: - eieio - addis r8,r7,mmu_hash_lock@ha - li r0,0 - stw r0,mmu_hash_lock@l(r8) - blr -#endif /* CONFIG_SMP */ - -/* - * Add an entry for a particular page to the hash table. - * - * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) - * - * We assume any necessary modifications to the pte (e.g. setting - * the accessed bit) have already been done and that there is actually - * a hash table in use (i.e. we're not on a 603). - */ -_GLOBAL(add_hash_page) - mflr r0 - stw r0,4(r1) - - /* Convert context and va to VSID */ - mulli r3,r3,897*16 /* multiply context by context skew */ - rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ - mulli r0,r0,0x111 /* multiply by ESID skew */ - add r3,r3,r0 /* note create_hpte trims to 24 bits */ - -#ifdef CONFIG_SMP - rlwinm r8,r1,0,0,18 /* use cpu number to make tag */ - lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */ - oris r8,r8,12 -#endif /* CONFIG_SMP */ - - /* - * We disable interrupts here, even on UP, because we don't - * want to race with hash_page, and because we want the - * _PAGE_HASHPTE bit to be a reliable indication of whether - * the HPTE exists (or at least whether one did once). - * We also turn off the MMU for data accesses so that we - * we can't take a hash table miss (assuming the code is - * covered by a BAT). -- paulus - */ - mfmsr r10 - SYNC - rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ - rlwinm r0,r0,0,28,26 /* clear MSR_DR */ - mtmsr r0 - SYNC_601 - isync - - tophys(r7,0) - -#ifdef CONFIG_SMP - addis r9,r7,mmu_hash_lock@ha - addi r9,r9,mmu_hash_lock@l -10: lwarx r0,0,r9 /* take the mmu_hash_lock */ - cmpi 0,r0,0 - bne- 11f - stwcx. r8,0,r9 - beq+ 12f -11: lwz r0,0(r9) - cmpi 0,r0,0 - beq 10b - b 11b -12: isync -#endif - - /* - * Fetch the linux pte and test and set _PAGE_HASHPTE atomically. - * If _PAGE_HASHPTE was already set, we don't replace the existing - * HPTE, so we just unlock and return. - */ - mr r8,r5 - rlwimi r8,r4,22,20,29 -1: lwarx r6,0,r8 - andi. r0,r6,_PAGE_HASHPTE - bne 9f /* if HASHPTE already set, done */ - ori r5,r6,_PAGE_HASHPTE - stwcx. r5,0,r8 - bne- 1b - - bl create_hpte - - addis r8,r7,htab_preloads@ha - lwz r3,htab_preloads@l(r8) - addi r3,r3,1 - stw r3,htab_preloads@l(r8) - -9: -#ifdef CONFIG_SMP - eieio - li r0,0 - stw r0,0(r9) /* clear mmu_hash_lock */ -#endif - - /* reenable interrupts and DR */ - mtmsr r10 - SYNC_601 - isync - - lwz r0,4(r1) - mtlr r0 - blr - -/* - * This routine adds a hardware PTE to the hash table. - * It is designed to be called with the MMU either on or off. - * r3 contains the VSID, r4 contains the virtual address, - * r5 contains the linux PTE, r6 contains the old value of the - * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the - * offset to be added to addresses (0 if the MMU is on, - * -KERNELBASE if it is off). - * On SMP, the caller should have the mmu_hash_lock held. - * We assume that the caller has (or will) set the _PAGE_HASHPTE - * bit in the linux PTE in memory. The value passed in r6 should - * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set - * this routine will skip the search for an existing HPTE. - * This procedure modifies r0, r3 - r6, r8, cr0. - * -- paulus. - * - * For speed, 4 of the instructions get patched once the size and - * physical address of the hash table are known. These definitions - * of Hash_base and Hash_bits below are just an example. - */ -Hash_base = 0xc0180000 -Hash_bits = 12 /* e.g. 256kB hash table */ -Hash_msk = (((1 << Hash_bits) - 1) * 64) - -/* defines for the PTE format for 32-bit PPCs */ -#define PTE_SIZE 8 -#define PTEG_SIZE 64 -#define LG_PTEG_SIZE 6 -#define LDPTEu lwzu -#define STPTE stw -#define CMPPTE cmpw -#define PTE_H 0x40 -#define PTE_V 0x80000000 -#define TST_V(r) rlwinm. r,r,0,0,0 -#define SET_V(r) oris r,r,PTE_V@h -#define CLR_V(r,t) rlwinm r,r,0,1,31 - -#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) -#define HASH_RIGHT 31-LG_PTEG_SIZE - -_GLOBAL(create_hpte) - /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ - rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */ - rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ - and r8,r8,r0 /* writable if _RW & _DIRTY */ - rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ - rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ - ori r8,r8,0xe14 /* clear out reserved bits and M */ - andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */ -BEGIN_FTR_SECTION - ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */ -END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT) - - /* Construct the high word of the PPC-style PTE (r5) */ - rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ - rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ - SET_V(r5) /* set V (valid) bit */ - - /* Get the address of the primary PTE group in the hash table (r3) */ -_GLOBAL(hash_page_patch_A) - addis r0,r7,Hash_base@h /* base address of hash table */ - rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ - rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ - xor r3,r3,r0 /* make primary hash */ - li r0,8 /* PTEs/group */ - - /* - * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search - * if it is clear, meaning that the HPTE isn't there already... - */ - andi. r6,r6,_PAGE_HASHPTE - beq+ 10f /* no PTE: go look for an empty slot */ - tlbie r4 - - addis r4,r7,htab_hash_searches@ha - lwz r6,htab_hash_searches@l(r4) - addi r6,r6,1 /* count how many searches we do */ - stw r6,htab_hash_searches@l(r4) - - /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ - mtctr r0 - addi r4,r3,-PTE_SIZE -1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */ - CMPPTE 0,r6,r5 - bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ - beq+ found_slot - - /* Search the secondary PTEG for a matching PTE */ - ori r5,r5,PTE_H /* set H (secondary hash) bit */ -_GLOBAL(hash_page_patch_B) - xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ - xori r4,r4,(-PTEG_SIZE & 0xffff) - addi r4,r4,-PTE_SIZE - mtctr r0 -2: LDPTEu r6,PTE_SIZE(r4) - CMPPTE 0,r6,r5 - bdnzf 2,2b - beq+ found_slot - xori r5,r5,PTE_H /* clear H bit again */ - - /* Search the primary PTEG for an empty slot */ -10: mtctr r0 - addi r4,r3,-PTE_SIZE /* search primary PTEG */ -1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */ - TST_V(r6) /* test valid bit */ - bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ - beq+ found_empty - - /* update counter of times that the primary PTEG is full */ - addis r4,r7,primary_pteg_full@ha - lwz r6,primary_pteg_full@l(r4) - addi r6,r6,1 - stw r6,primary_pteg_full@l(r4) - - /* Search the secondary PTEG for an empty slot */ - ori r5,r5,PTE_H /* set H (secondary hash) bit */ -_GLOBAL(hash_page_patch_C) - xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ - xori r4,r4,(-PTEG_SIZE & 0xffff) - addi r4,r4,-PTE_SIZE - mtctr r0 -2: LDPTEu r6,PTE_SIZE(r4) - TST_V(r6) - bdnzf 2,2b - beq+ found_empty - xori r5,r5,PTE_H /* clear H bit again */ - - /* - * Choose an arbitrary slot in the primary PTEG to overwrite. - * Since both the primary and secondary PTEGs are full, and we - * have no information that the PTEs in the primary PTEG are - * more important or useful than those in the secondary PTEG, - * and we know there is a definite (although small) speed - * advantage to putting the PTE in the primary PTEG, we always - * put the PTE in the primary PTEG. - */ - addis r4,r7,next_slot@ha - lwz r6,next_slot@l(r4) - addi r6,r6,PTE_SIZE - andi. r6,r6,7*PTE_SIZE - stw r6,next_slot@l(r4) - add r4,r3,r6 - - /* update counter of evicted pages */ - addis r6,r7,htab_evicts@ha - lwz r3,htab_evicts@l(r6) - addi r3,r3,1 - stw r3,htab_evicts@l(r6) - -#ifndef CONFIG_SMP - /* Store PTE in PTEG */ -found_empty: - STPTE r5,0(r4) -found_slot: - STPTE r8,PTE_SIZE/2(r4) - -#else /* CONFIG_SMP */ -/* - * Between the tlbie above and updating the hash table entry below, - * another CPU could read the hash table entry and put it in its TLB. - * There are 3 cases: - * 1. using an empty slot - * 2. updating an earlier entry to change permissions (i.e. enable write) - * 3. taking over the PTE for an unrelated address - * - * In each case it doesn't really matter if the other CPUs have the old - * PTE in their TLB. So we don't need to bother with another tlbie here, - * which is convenient as we've overwritten the register that had the - * address. :-) The tlbie above is mainly to make sure that this CPU comes - * and gets the new PTE from the hash table. - * - * We do however have to make sure that the PTE is never in an invalid - * state with the V bit set. - */ -found_empty: -found_slot: - CLR_V(r5,r0) /* clear V (valid) bit in PTE */ - STPTE r5,0(r4) - sync - TLBSYNC - STPTE r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ - sync - SET_V(r5) - STPTE r5,0(r4) /* finally set V bit in PTE */ -#endif /* CONFIG_SMP */ - - sync /* make sure pte updates get to memory */ - blr - - .section .bss - .align 2 -next_slot: - .space 4 - .globl primary_pteg_full -primary_pteg_full: - .space 4 - .globl htab_hash_searches -htab_hash_searches: - .space 4 - .previous - -/* - * Flush the entry for a particular page from the hash table. - * - * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, - * int count) - * - * We assume that there is a hash table in use (Hash != 0). - */ -_GLOBAL(flush_hash_pages) - tophys(r7,0) - - /* - * We disable interrupts here, even on UP, because we want - * the _PAGE_HASHPTE bit to be a reliable indication of - * whether the HPTE exists (or at least whether one did once). - * We also turn off the MMU for data accesses so that we - * we can't take a hash table miss (assuming the code is - * covered by a BAT). -- paulus - */ - mfmsr r10 - SYNC - rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ - rlwinm r0,r0,0,28,26 /* clear MSR_DR */ - mtmsr r0 - SYNC_601 - isync - - /* First find a PTE in the range that has _PAGE_HASHPTE set */ - rlwimi r5,r4,22,20,29 -1: lwz r0,0(r5) - cmpwi cr1,r6,1 - andi. r0,r0,_PAGE_HASHPTE - bne 2f - ble cr1,19f - addi r4,r4,0x1000 - addi r5,r5,4 - addi r6,r6,-1 - b 1b - - /* Convert context and va to VSID */ -2: mulli r3,r3,897*16 /* multiply context by context skew */ - rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ - mulli r0,r0,0x111 /* multiply by ESID skew */ - add r3,r3,r0 /* note code below trims to 24 bits */ - - /* Construct the high word of the PPC-style PTE (r11) */ - rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ - rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ - SET_V(r11) /* set V (valid) bit */ - -#ifdef CONFIG_SMP - addis r9,r7,mmu_hash_lock@ha - addi r9,r9,mmu_hash_lock@l - rlwinm r8,r1,0,0,18 - add r8,r8,r7 - lwz r8,TI_CPU(r8) - oris r8,r8,9 -10: lwarx r0,0,r9 - cmpi 0,r0,0 - bne- 11f - stwcx. r8,0,r9 - beq+ 12f -11: lwz r0,0(r9) - cmpi 0,r0,0 - beq 10b - b 11b -12: isync -#endif - - /* - * Check the _PAGE_HASHPTE bit in the linux PTE. If it is - * already clear, we're done (for this pte). If not, - * clear it (atomically) and proceed. -- paulus. - */ -33: lwarx r8,0,r5 /* fetch the pte */ - andi. r0,r8,_PAGE_HASHPTE - beq 8f /* done if HASHPTE is already clear */ - rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ - stwcx. r8,0,r5 /* update the pte */ - bne- 33b - - /* Get the address of the primary PTE group in the hash table (r3) */ -_GLOBAL(flush_hash_patch_A) - addis r8,r7,Hash_base@h /* base address of hash table */ - rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ - rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ - xor r8,r0,r8 /* make primary hash */ - - /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ - li r0,8 /* PTEs/group */ - mtctr r0 - addi r12,r8,-PTE_SIZE -1: LDPTEu r0,PTE_SIZE(r12) /* get next PTE */ - CMPPTE 0,r0,r11 - bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ - beq+ 3f - - /* Search the secondary PTEG for a matching PTE */ - ori r11,r11,PTE_H /* set H (secondary hash) bit */ - li r0,8 /* PTEs/group */ -_GLOBAL(flush_hash_patch_B) - xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ - xori r12,r12,(-PTEG_SIZE & 0xffff) - addi r12,r12,-PTE_SIZE - mtctr r0 -2: LDPTEu r0,PTE_SIZE(r12) - CMPPTE 0,r0,r11 - bdnzf 2,2b - xori r11,r11,PTE_H /* clear H again */ - bne- 4f /* should rarely fail to find it */ - -3: li r0,0 - STPTE r0,0(r12) /* invalidate entry */ -4: sync - tlbie r4 /* in hw tlb too */ - sync - -8: ble cr1,9f /* if all ptes checked */ -81: addi r6,r6,-1 - addi r5,r5,4 /* advance to next pte */ - addi r4,r4,0x1000 - lwz r0,0(r5) /* check next pte */ - cmpwi cr1,r6,1 - andi. r0,r0,_PAGE_HASHPTE - bne 33b - bgt cr1,81b - -9: -#ifdef CONFIG_SMP - TLBSYNC - li r0,0 - stw r0,0(r9) /* clear mmu_hash_lock */ -#endif - -19: mtmsr r10 - SYNC_601 - isync - blr diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c deleted file mode 100644 index 1a63711081b5..000000000000 --- a/arch/ppc/mm/init.c +++ /dev/null @@ -1,603 +0,0 @@ -/* - * PowerPC version - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) - * and Cort Dougan (PReP) (cort@cs.nmt.edu) - * Copyright (C) 1996 Paul Mackerras - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). - * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com) - * - * Derived from "arch/i386/mm/init.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mem_pieces.h" -#include "mmu_decl.h" - -#if defined(CONFIG_KERNEL_START_BOOL) || defined(CONFIG_LOWMEM_SIZE_BOOL) -/* The amount of lowmem must be within 0xF0000000 - KERNELBASE. */ -#if (CONFIG_LOWMEM_SIZE > (0xF0000000 - KERNELBASE)) -#error "You must adjust CONFIG_LOWMEM_SIZE or CONFIG_START_KERNEL" -#endif -#endif -#define MAX_LOW_MEM CONFIG_LOWMEM_SIZE - -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); - -unsigned long total_memory; -unsigned long total_lowmem; - -unsigned long ppc_memstart; -unsigned long ppc_memoffset = PAGE_OFFSET; - -int mem_init_done; -int init_bootmem_done; -int boot_mapsize; - -extern char _end[]; -extern char etext[], _stext[]; -extern char __init_begin, __init_end; - -#ifdef CONFIG_HIGHMEM -pte_t *kmap_pte; -pgprot_t kmap_prot; - -EXPORT_SYMBOL(kmap_prot); -EXPORT_SYMBOL(kmap_pte); -#endif - -void MMU_init(void); -void set_phys_avail(unsigned long total_ram); - -/* XXX should be in current.h -- paulus */ -extern struct task_struct *current_set[NR_CPUS]; - -char *klimit = _end; -struct mem_pieces phys_avail; - -/* - * this tells the system to map all of ram with the segregs - * (i.e. page tables) instead of the bats. - * -- Cort - */ -int __map_without_bats; -int __map_without_ltlbs; - -/* max amount of RAM to use */ -unsigned long __max_memory; -/* max amount of low RAM to map in */ -unsigned long __max_low_memory = MAX_LOW_MEM; - -void show_mem(void) -{ - int i,free = 0,total = 0,reserved = 0; - int shared = 0, cached = 0; - int highmem = 0; - - printk("Mem-info:\n"); - show_free_areas(); - i = max_mapnr; - while (i-- > 0) { - total++; - if (PageHighMem(mem_map+i)) - highmem++; - if (PageReserved(mem_map+i)) - reserved++; - else if (PageSwapCache(mem_map+i)) - cached++; - else if (!page_count(mem_map+i)) - free++; - else - shared += page_count(mem_map+i) - 1; - } - printk("%d pages of RAM\n",total); - printk("%d pages of HIGHMEM\n", highmem); - printk("%d free pages\n",free); - printk("%d reserved pages\n",reserved); - printk("%d pages shared\n",shared); - printk("%d pages swap cached\n",cached); -} - -/* Free up now-unused memory */ -static void free_sec(unsigned long start, unsigned long end, const char *name) -{ - unsigned long cnt = 0; - - while (start < end) { - ClearPageReserved(virt_to_page(start)); - init_page_count(virt_to_page(start)); - free_page(start); - cnt++; - start += PAGE_SIZE; - } - if (cnt) { - printk(" %ldk %s", cnt << (PAGE_SHIFT - 10), name); - totalram_pages += cnt; - } -} - -void free_initmem(void) -{ -#define FREESEC(TYPE) \ - free_sec((unsigned long)(&__ ## TYPE ## _begin), \ - (unsigned long)(&__ ## TYPE ## _end), \ - #TYPE); - - printk ("Freeing unused kernel memory:"); - FREESEC(init); - printk("\n"); - ppc_md.progress = NULL; -#undef FREESEC -} - -#ifdef CONFIG_BLK_DEV_INITRD -void free_initrd_mem(unsigned long start, unsigned long end) -{ - printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); - - for (; start < end; start += PAGE_SIZE) { - ClearPageReserved(virt_to_page(start)); - init_page_count(virt_to_page(start)); - free_page(start); - totalram_pages++; - } -} -#endif - -/* - * Check for command-line options that affect what MMU_init will do. - */ -void MMU_setup(void) -{ - /* Check for nobats option (used in mapin_ram). */ - if (strstr(cmd_line, "nobats")) { - __map_without_bats = 1; - } - - if (strstr(cmd_line, "noltlbs")) { - __map_without_ltlbs = 1; - } - - /* Look for mem= option on command line */ - if (strstr(cmd_line, "mem=")) { - char *p, *q; - unsigned long maxmem = 0; - - for (q = cmd_line; (p = strstr(q, "mem=")) != 0; ) { - q = p + 4; - if (p > cmd_line && p[-1] != ' ') - continue; - maxmem = simple_strtoul(q, &q, 0); - if (*q == 'k' || *q == 'K') { - maxmem <<= 10; - ++q; - } else if (*q == 'm' || *q == 'M') { - maxmem <<= 20; - ++q; - } - } - __max_memory = maxmem; - } -} - -/* - * MMU_init sets up the basic memory mappings for the kernel, - * including both RAM and possibly some I/O regions, - * and sets up the page tables and the MMU hardware ready to go. - */ -void __init MMU_init(void) -{ - if (ppc_md.progress) - ppc_md.progress("MMU:enter", 0x111); - - /* parse args from command line */ - MMU_setup(); - - /* - * Figure out how much memory we have, how much - * is lowmem, and how much is highmem. If we were - * passed the total memory size from the bootloader, - * just use it. - */ - if (boot_mem_size) - total_memory = boot_mem_size; - else - total_memory = ppc_md.find_end_of_memory(); - - if (__max_memory && total_memory > __max_memory) - total_memory = __max_memory; - total_lowmem = total_memory; - if (total_lowmem > __max_low_memory) { - total_lowmem = __max_low_memory; -#ifndef CONFIG_HIGHMEM - total_memory = total_lowmem; -#endif /* CONFIG_HIGHMEM */ - } - set_phys_avail(total_lowmem); - - /* Initialize the MMU hardware */ - if (ppc_md.progress) - ppc_md.progress("MMU:hw init", 0x300); - MMU_init_hw(); - - /* Map in all of RAM starting at KERNELBASE */ - if (ppc_md.progress) - ppc_md.progress("MMU:mapin", 0x301); - mapin_ram(); - -#ifdef CONFIG_HIGHMEM - ioremap_base = PKMAP_BASE; -#else - ioremap_base = 0xfe000000UL; /* for now, could be 0xfffff000 */ -#endif /* CONFIG_HIGHMEM */ - ioremap_bot = ioremap_base; - - /* Map in I/O resources */ - if (ppc_md.progress) - ppc_md.progress("MMU:setio", 0x302); - if (ppc_md.setup_io_mappings) - ppc_md.setup_io_mappings(); - - /* Initialize the context management stuff */ - mmu_context_init(); - - if (ppc_md.progress) - ppc_md.progress("MMU:exit", 0x211); - -#ifdef CONFIG_BOOTX_TEXT - /* By default, we are no longer mapped */ - boot_text_mapped = 0; - /* Must be done last, or ppc_md.progress will die. */ - map_boot_text(); -#endif -} - -/* This is only called until mem_init is done. */ -void __init *early_get_page(void) -{ - void *p; - - if (init_bootmem_done) { - p = alloc_bootmem_pages(PAGE_SIZE); - } else { - p = mem_pieces_find(PAGE_SIZE, PAGE_SIZE); - } - return p; -} - -/* - * Initialize the bootmem system and give it all the memory we - * have available. - */ -void __init do_init_bootmem(void) -{ - unsigned long start, size; - int i; - - /* - * Find an area to use for the bootmem bitmap. - * We look for the first area which is at least - * 128kB in length (128kB is enough for a bitmap - * for 4GB of memory, using 4kB pages), plus 1 page - * (in case the address isn't page-aligned). - */ - start = 0; - size = 0; - for (i = 0; i < phys_avail.n_regions; ++i) { - unsigned long a = phys_avail.regions[i].address; - unsigned long s = phys_avail.regions[i].size; - if (s <= size) - continue; - start = a; - size = s; - if (s >= 33 * PAGE_SIZE) - break; - } - start = PAGE_ALIGN(start); - - min_low_pfn = start >> PAGE_SHIFT; - max_low_pfn = (PPC_MEMSTART + total_lowmem) >> PAGE_SHIFT; - max_pfn = (PPC_MEMSTART + total_memory) >> PAGE_SHIFT; - boot_mapsize = init_bootmem_node(&contig_page_data, min_low_pfn, - PPC_MEMSTART >> PAGE_SHIFT, - max_low_pfn); - - /* remove the bootmem bitmap from the available memory */ - mem_pieces_remove(&phys_avail, start, boot_mapsize, 1); - - /* add everything in phys_avail into the bootmem map */ - for (i = 0; i < phys_avail.n_regions; ++i) - free_bootmem(phys_avail.regions[i].address, - phys_avail.regions[i].size); - - init_bootmem_done = 1; -} - -/* - * paging_init() sets up the page tables - in fact we've already done this. - */ -void __init paging_init(void) -{ - unsigned long start_pfn, end_pfn; - unsigned long max_zone_pfns[MAX_NR_ZONES]; -#ifdef CONFIG_HIGHMEM - map_page(PKMAP_BASE, 0, 0); /* XXX gross */ - pkmap_page_table = pte_offset_kernel(pmd_offset(pgd_offset_k - (PKMAP_BASE), PKMAP_BASE), PKMAP_BASE); - map_page(KMAP_FIX_BEGIN, 0, 0); /* XXX gross */ - kmap_pte = pte_offset_kernel(pmd_offset(pgd_offset_k - (KMAP_FIX_BEGIN), KMAP_FIX_BEGIN), KMAP_FIX_BEGIN); - kmap_prot = PAGE_KERNEL; -#endif /* CONFIG_HIGHMEM */ - /* All pages are DMA-able so we put them all in the DMA zone. */ - start_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT; - end_pfn = start_pfn + (total_memory >> PAGE_SHIFT); - add_active_range(0, start_pfn, end_pfn); - - memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); -#ifdef CONFIG_HIGHMEM - max_zone_pfns[ZONE_DMA] = total_lowmem >> PAGE_SHIFT; - max_zone_pfns[ZONE_HIGHMEM] = total_memory >> PAGE_SHIFT; -#else - max_zone_pfns[ZONE_DMA] = total_memory >> PAGE_SHIFT; -#endif /* CONFIG_HIGHMEM */ - free_area_init_nodes(max_zone_pfns); -} - -void __init mem_init(void) -{ - unsigned long addr; - int codepages = 0; - int datapages = 0; - int initpages = 0; -#ifdef CONFIG_HIGHMEM - unsigned long highmem_mapnr; - - highmem_mapnr = total_lowmem >> PAGE_SHIFT; -#endif /* CONFIG_HIGHMEM */ - max_mapnr = total_memory >> PAGE_SHIFT; - - high_memory = (void *) __va(PPC_MEMSTART + total_lowmem); - num_physpages = max_mapnr; /* RAM is assumed contiguous */ - - totalram_pages += free_all_bootmem(); - -#ifdef CONFIG_BLK_DEV_INITRD - /* if we are booted from BootX with an initial ramdisk, - make sure the ramdisk pages aren't reserved. */ - if (initrd_start) { - for (addr = initrd_start; addr < initrd_end; addr += PAGE_SIZE) - ClearPageReserved(virt_to_page(addr)); - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - for (addr = PAGE_OFFSET; addr < (unsigned long)high_memory; - addr += PAGE_SIZE) { - if (!PageReserved(virt_to_page(addr))) - continue; - if (addr < (ulong) etext) - codepages++; - else if (addr >= (unsigned long)&__init_begin - && addr < (unsigned long)&__init_end) - initpages++; - else if (addr < (ulong) klimit) - datapages++; - } - -#ifdef CONFIG_HIGHMEM - { - unsigned long pfn; - - for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) { - struct page *page = mem_map + pfn; - - ClearPageReserved(page); - init_page_count(page); - __free_page(page); - totalhigh_pages++; - } - totalram_pages += totalhigh_pages; - } -#endif /* CONFIG_HIGHMEM */ - - printk("Memory: %luk available (%dk kernel code, %dk data, %dk init, %ldk highmem)\n", - (unsigned long)nr_free_pages()<< (PAGE_SHIFT-10), - codepages<< (PAGE_SHIFT-10), datapages<< (PAGE_SHIFT-10), - initpages<< (PAGE_SHIFT-10), - (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); - - mem_init_done = 1; -} - -/* - * Set phys_avail to the amount of physical memory, - * less the kernel text/data/bss. - */ -void __init -set_phys_avail(unsigned long total_memory) -{ - unsigned long kstart, ksize; - - /* - * Initially, available physical memory is equivalent to all - * physical memory. - */ - - phys_avail.regions[0].address = PPC_MEMSTART; - phys_avail.regions[0].size = total_memory; - phys_avail.n_regions = 1; - - /* - * Map out the kernel text/data/bss from the available physical - * memory. - */ - - kstart = __pa(_stext); /* should be 0 */ - ksize = PAGE_ALIGN(klimit - _stext); - - mem_pieces_remove(&phys_avail, kstart, ksize, 0); - mem_pieces_remove(&phys_avail, 0, 0x4000, 0); - -#if defined(CONFIG_BLK_DEV_INITRD) - /* Remove the init RAM disk from the available memory. */ - if (initrd_start) { - mem_pieces_remove(&phys_avail, __pa(initrd_start), - initrd_end - initrd_start, 1); - } -#endif /* CONFIG_BLK_DEV_INITRD */ -} - -/* Mark some memory as reserved by removing it from phys_avail. */ -void __init reserve_phys_mem(unsigned long start, unsigned long size) -{ - mem_pieces_remove(&phys_avail, start, size, 1); -} - -/* - * This is called when a page has been modified by the kernel. - * It just marks the page as not i-cache clean. We do the i-cache - * flush later when the page is given to a user process, if necessary. - */ -void flush_dcache_page(struct page *page) -{ - clear_bit(PG_arch_1, &page->flags); -} - -void flush_dcache_icache_page(struct page *page) -{ -#ifdef CONFIG_BOOKE - void *start = kmap_atomic(page, KM_PPC_SYNC_ICACHE); - __flush_dcache_icache(start); - kunmap_atomic(start, KM_PPC_SYNC_ICACHE); -#elif defined(CONFIG_8xx) - /* On 8xx there is no need to kmap since highmem is not supported */ - __flush_dcache_icache(page_address(page)); -#else - __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT); -#endif - -} -void clear_user_page(void *page, unsigned long vaddr, struct page *pg) -{ - clear_page(page); - clear_bit(PG_arch_1, &pg->flags); -} - -void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, - struct page *pg) -{ - copy_page(vto, vfrom); - clear_bit(PG_arch_1, &pg->flags); -} - -void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, - unsigned long addr, int len) -{ - unsigned long maddr; - - maddr = (unsigned long) kmap(page) + (addr & ~PAGE_MASK); - flush_icache_range(maddr, maddr + len); - kunmap(page); -} - -/* - * This is called at the end of handling a user page fault, when the - * fault has been handled by updating a PTE in the linux page tables. - * We use it to preload an HPTE into the hash table corresponding to - * the updated linux PTE. - */ -void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, - pte_t pte) -{ - /* handle i-cache coherency */ - unsigned long pfn = pte_pfn(pte); - - if (pfn_valid(pfn)) { - struct page *page = pfn_to_page(pfn); -#ifdef CONFIG_8xx - /* On 8xx, the TLB handlers work in 2 stages: - * First, a zeroed entry is loaded by TLBMiss handler, - * which causes the TLBError handler to be triggered. - * That means the zeroed TLB has to be invalidated - * whenever a page miss occurs. - */ - _tlbie(address, 0 /* 8xx doesn't care about PID */); -#endif - if (!PageReserved(page) - && !test_bit(PG_arch_1, &page->flags)) { - if (vma->vm_mm == current->active_mm) - __flush_dcache_icache((void *) address); - else - flush_dcache_icache_page(page); - set_bit(PG_arch_1, &page->flags); - } - } - -#ifdef CONFIG_PPC_STD_MMU - /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ - if (Hash != 0 && pte_young(pte)) { - struct mm_struct *mm; - pmd_t *pmd; - - mm = (address < TASK_SIZE)? vma->vm_mm: &init_mm; - pmd = pmd_offset(pgd_offset(mm, address), address); - if (!pmd_none(*pmd)) - add_hash_page(mm->context.id, address, pmd_val(*pmd)); - } -#endif -} - -/* - * This is called by /dev/mem to know if a given address has to - * be mapped non-cacheable or not - */ -int page_is_ram(unsigned long pfn) -{ - return pfn < max_pfn; -} - -pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, - unsigned long size, pgprot_t vma_prot) -{ - if (ppc_md.phys_mem_access_prot) - return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot); - - if (!page_is_ram(pfn)) - vma_prot = __pgprot(pgprot_val(vma_prot) - | _PAGE_GUARDED | _PAGE_NO_CACHE); - return vma_prot; -} -EXPORT_SYMBOL(phys_mem_access_prot); diff --git a/arch/ppc/mm/mem_pieces.c b/arch/ppc/mm/mem_pieces.c deleted file mode 100644 index 6030a0ddfbb4..000000000000 --- a/arch/ppc/mm/mem_pieces.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 1996 Paul Mackerras - * Changes to accommodate Power Macintoshes. - * Cort Dougan - * Rewrites. - * Grant Erickson - * General rework and split from mm/init.c. - * - * Module name: mem_pieces.c - * - * Description: - * Routines and data structures for manipulating and representing - * phyiscal memory extents (i.e. address/length pairs). - * - */ - -#include -#include -#include -#include - -#include "mem_pieces.h" - -extern struct mem_pieces phys_avail; - -static void mem_pieces_print(struct mem_pieces *); - -/* - * Scan a region for a piece of a given size with the required alignment. - */ -void __init * -mem_pieces_find(unsigned int size, unsigned int align) -{ - int i; - unsigned a, e; - struct mem_pieces *mp = &phys_avail; - - for (i = 0; i < mp->n_regions; ++i) { - a = mp->regions[i].address; - e = a + mp->regions[i].size; - a = (a + align - 1) & -align; - if (a + size <= e) { - mem_pieces_remove(mp, a, size, 1); - return (void *) __va(a); - } - } - panic("Couldn't find %u bytes at %u alignment\n", size, align); - - return NULL; -} - -/* - * Remove some memory from an array of pieces - */ -void __init -mem_pieces_remove(struct mem_pieces *mp, unsigned int start, unsigned int size, - int must_exist) -{ - int i, j; - unsigned int end, rs, re; - struct reg_property *rp; - - end = start + size; - for (i = 0, rp = mp->regions; i < mp->n_regions; ++i, ++rp) { - if (end > rp->address && start < rp->address + rp->size) - break; - } - if (i >= mp->n_regions) { - if (must_exist) - printk("mem_pieces_remove: [%x,%x) not in any region\n", - start, end); - return; - } - for (; i < mp->n_regions && end > rp->address; ++i, ++rp) { - rs = rp->address; - re = rs + rp->size; - if (must_exist && (start < rs || end > re)) { - printk("mem_pieces_remove: bad overlap [%x,%x) with", - start, end); - mem_pieces_print(mp); - must_exist = 0; - } - if (start > rs) { - rp->size = start - rs; - if (end < re) { - /* need to split this entry */ - if (mp->n_regions >= MEM_PIECES_MAX) - panic("eek... mem_pieces overflow"); - for (j = mp->n_regions; j > i + 1; --j) - mp->regions[j] = mp->regions[j-1]; - ++mp->n_regions; - rp[1].address = end; - rp[1].size = re - end; - } - } else { - if (end < re) { - rp->address = end; - rp->size = re - end; - } else { - /* need to delete this entry */ - for (j = i; j < mp->n_regions - 1; ++j) - mp->regions[j] = mp->regions[j+1]; - --mp->n_regions; - --i; - --rp; - } - } - } -} - -static void __init -mem_pieces_print(struct mem_pieces *mp) -{ - int i; - - for (i = 0; i < mp->n_regions; ++i) - printk(" [%x, %x)", mp->regions[i].address, - mp->regions[i].address + mp->regions[i].size); - printk("\n"); -} - -void __init -mem_pieces_sort(struct mem_pieces *mp) -{ - unsigned long a, s; - int i, j; - - for (i = 1; i < mp->n_regions; ++i) { - a = mp->regions[i].address; - s = mp->regions[i].size; - for (j = i - 1; j >= 0; --j) { - if (a >= mp->regions[j].address) - break; - mp->regions[j+1] = mp->regions[j]; - } - mp->regions[j+1].address = a; - mp->regions[j+1].size = s; - } -} - -void __init -mem_pieces_coalesce(struct mem_pieces *mp) -{ - unsigned long a, s, ns; - int i, j, d; - - d = 0; - for (i = 0; i < mp->n_regions; i = j) { - a = mp->regions[i].address; - s = mp->regions[i].size; - for (j = i + 1; j < mp->n_regions - && mp->regions[j].address - a <= s; ++j) { - ns = mp->regions[j].address + mp->regions[j].size - a; - if (ns > s) - s = ns; - } - mp->regions[d].address = a; - mp->regions[d].size = s; - ++d; - } - mp->n_regions = d; -} diff --git a/arch/ppc/mm/mem_pieces.h b/arch/ppc/mm/mem_pieces.h deleted file mode 100644 index e2b700dc7f18..000000000000 --- a/arch/ppc/mm/mem_pieces.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 1996 Paul Mackerras - * Changes to accommodate Power Macintoshes. - * Cort Dougan - * Rewrites. - * Grant Erickson - * General rework and split from mm/init.c. - * - * Module name: mem_pieces.h - * - * Description: - * Routines and data structures for manipulating and representing - * phyiscal memory extents (i.e. address/length pairs). - * - */ - -#ifndef __MEM_PIECES_H__ -#define __MEM_PIECES_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Type Definitions */ - -#define MEM_PIECES_MAX 32 - -struct mem_pieces { - int n_regions; - struct reg_property regions[MEM_PIECES_MAX]; -}; - -/* Function Prototypes */ - -extern void *mem_pieces_find(unsigned int size, unsigned int align); -extern void mem_pieces_remove(struct mem_pieces *mp, unsigned int start, - unsigned int size, int must_exist); -extern void mem_pieces_coalesce(struct mem_pieces *mp); -extern void mem_pieces_sort(struct mem_pieces *mp); - -#ifdef __cplusplus -} -#endif - -#endif /* __MEM_PIECES_H__ */ diff --git a/arch/ppc/mm/mmu_context.c b/arch/ppc/mm/mmu_context.c deleted file mode 100644 index dacf45ced473..000000000000 --- a/arch/ppc/mm/mmu_context.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file contains the routines for handling the MMU on those - * PowerPC implementations where the MMU substantially follows the - * architecture specification. This includes the 6xx, 7xx, 7xxx, - * and 8260 implementations but excludes the 8xx and 4xx. - * -- paulus - * - * Derived from arch/ppc/mm/init.c: - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) - * and Cort Dougan (PReP) (cort@cs.nmt.edu) - * Copyright (C) 1996 Paul Mackerras - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). - * - * Derived from "arch/i386/mm/init.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include - -#include -#include - -unsigned long next_mmu_context; -unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1]; -#ifdef FEW_CONTEXTS -atomic_t nr_free_contexts; -struct mm_struct *context_mm[LAST_CONTEXT+1]; -void steal_context(void); -#endif /* FEW_CONTEXTS */ - -/* - * Initialize the context management stuff. - */ -void __init -mmu_context_init(void) -{ - /* - * Some processors have too few contexts to reserve one for - * init_mm, and require using context 0 for a normal task. - * Other processors reserve the use of context zero for the kernel. - * This code assumes FIRST_CONTEXT < 32. - */ - context_map[0] = (1 << FIRST_CONTEXT) - 1; - next_mmu_context = FIRST_CONTEXT; -#ifdef FEW_CONTEXTS - atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1); -#endif /* FEW_CONTEXTS */ -} - -#ifdef FEW_CONTEXTS -/* - * Steal a context from a task that has one at the moment. - * This is only used on 8xx and 4xx and we presently assume that - * they don't do SMP. If they do then this will have to check - * whether the MM we steal is in use. - * We also assume that this is only used on systems that don't - * use an MMU hash table - this is true for 8xx and 4xx. - * This isn't an LRU system, it just frees up each context in - * turn (sort-of pseudo-random replacement :). This would be the - * place to implement an LRU scheme if anyone was motivated to do it. - * -- paulus - */ -void -steal_context(void) -{ - struct mm_struct *mm; - - /* free up context `next_mmu_context' */ - /* if we shouldn't free context 0, don't... */ - if (next_mmu_context < FIRST_CONTEXT) - next_mmu_context = FIRST_CONTEXT; - mm = context_mm[next_mmu_context]; - flush_tlb_mm(mm); - destroy_context(mm); -} -#endif /* FEW_CONTEXTS */ diff --git a/arch/ppc/mm/mmu_decl.h b/arch/ppc/mm/mmu_decl.h deleted file mode 100644 index 5f813e386b87..000000000000 --- a/arch/ppc/mm/mmu_decl.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Declarations of procedures and variables shared between files - * in arch/ppc/mm/. - * - * Derived from arch/ppc/mm/init.c: - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) - * and Cort Dougan (PReP) (cort@cs.nmt.edu) - * Copyright (C) 1996 Paul Mackerras - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). - * - * Derived from "arch/i386/mm/init.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ -#include -#include - -extern void mapin_ram(void); -extern int map_page(unsigned long va, phys_addr_t pa, int flags); -extern void setbat(int index, unsigned long virt, unsigned long phys, - unsigned int size, int flags); -extern void reserve_phys_mem(unsigned long start, unsigned long size); -extern void settlbcam(int index, unsigned long virt, phys_addr_t phys, - unsigned int size, int flags, unsigned int pid); -extern void invalidate_tlbcam_entry(int index); - -extern int __map_without_bats; -extern unsigned long ioremap_base; -extern unsigned long ioremap_bot; -extern unsigned int rtas_data, rtas_size; - -extern unsigned long total_memory; -extern unsigned long total_lowmem; -extern int mem_init_done; - -extern PTE *Hash, *Hash_end; -extern unsigned long Hash_size, Hash_mask; - -extern unsigned int num_tlbcam_entries; - -/* ...and now those things that may be slightly different between processor - * architectures. -- Dan - */ -#if defined(CONFIG_8xx) -#define flush_HPTE(X, va, pg) _tlbie(va, 0 /* 8xx doesn't care about PID */) -#define MMU_init_hw() do { } while(0) -#define mmu_mapin_ram() (0UL) - -#elif defined(CONFIG_4xx) -#define flush_HPTE(pid, va, pg) _tlbie(va, pid) -extern void MMU_init_hw(void); -extern unsigned long mmu_mapin_ram(void); - -#else -/* anything except 4xx or 8xx */ -extern void MMU_init_hw(void); -extern unsigned long mmu_mapin_ram(void); - -/* Be careful....this needs to be updated if we ever encounter 603 SMPs, - * which includes all new 82xx processors. We need tlbie/tlbsync here - * in that case (I think). -- Dan. - */ -static inline void flush_HPTE(unsigned context, unsigned long va, - unsigned long pdval) -{ - if ((Hash != 0) && - cpu_has_feature(CPU_FTR_HPTE_TABLE)) - flush_hash_pages(0, va, pdval, 1); - else - _tlbie(va); -} -#endif diff --git a/arch/ppc/mm/pgtable.c b/arch/ppc/mm/pgtable.c deleted file mode 100644 index 03a79bff1271..000000000000 --- a/arch/ppc/mm/pgtable.c +++ /dev/null @@ -1,403 +0,0 @@ -/* - * This file contains the routines setting up the linux page tables. - * -- paulus - * - * Derived from arch/ppc/mm/init.c: - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) - * and Cort Dougan (PReP) (cort@cs.nmt.edu) - * Copyright (C) 1996 Paul Mackerras - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). - * - * Derived from "arch/i386/mm/init.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "mmu_decl.h" - -unsigned long ioremap_base; -unsigned long ioremap_bot; -int io_bat_index; - -#if defined(CONFIG_6xx) -#define HAVE_BATS 1 -#endif - -extern char etext[], _stext[]; - -#ifdef CONFIG_SMP -extern void hash_page_sync(void); -#endif - -#ifdef HAVE_BATS -extern unsigned long v_mapped_by_bats(unsigned long va); -extern unsigned long p_mapped_by_bats(unsigned long pa); -void setbat(int index, unsigned long virt, unsigned long phys, - unsigned int size, int flags); - -#else /* !HAVE_BATS */ -#define v_mapped_by_bats(x) (0UL) -#define p_mapped_by_bats(x) (0UL) -#endif /* HAVE_BATS */ - -#ifdef CONFIG_PTE_64BIT -/* 44x uses an 8kB pgdir because it has 8-byte Linux PTEs. */ -#define PGDIR_ORDER 1 -#else -#define PGDIR_ORDER 0 -#endif - -pgd_t *pgd_alloc(struct mm_struct *mm) -{ - pgd_t *ret; - - ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGDIR_ORDER); - return ret; -} - -void pgd_free(struct mm_struct *mm, pgd_t *pgd) -{ - free_pages((unsigned long)pgd, PGDIR_ORDER); -} - -__init_refok pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) -{ - pte_t *pte; - extern int mem_init_done; - extern void *early_get_page(void); - - if (mem_init_done) { - pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); - } else { - pte = (pte_t *)early_get_page(); - if (pte) - clear_page(pte); - } - return pte; -} - -pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) -{ - struct page *ptepage; - -#ifdef CONFIG_HIGHPTE - gfp_t flags = GFP_KERNEL | __GFP_HIGHMEM | __GFP_REPEAT; -#else - gfp_t flags = GFP_KERNEL | __GFP_REPEAT; -#endif - - ptepage = alloc_pages(flags, 0); - if (ptepage) { - clear_highpage(ptepage); - pgtable_page_ctor(ptepage); - } - return ptepage; -} - -void pte_free_kernel(struct mm_struct *mm, pte_t *pte) -{ -#ifdef CONFIG_SMP - hash_page_sync(); -#endif - free_page((unsigned long)pte); -} - -void pte_free(struct mm_struct *mm, pgtable_t ptepage) -{ -#ifdef CONFIG_SMP - hash_page_sync(); -#endif - pgtable_page_dtor(ptepage); - __free_page(ptepage); -} - -#ifndef CONFIG_PHYS_64BIT -void __iomem * -ioremap(phys_addr_t addr, unsigned long size) -{ - return __ioremap(addr, size, _PAGE_NO_CACHE); -} -#else /* CONFIG_PHYS_64BIT */ -void __iomem * -ioremap64(unsigned long long addr, unsigned long size) -{ - return __ioremap(addr, size, _PAGE_NO_CACHE); -} - -void __iomem * -ioremap(phys_addr_t addr, unsigned long size) -{ - phys_addr_t addr64 = fixup_bigphys_addr(addr, size); - - return ioremap64(addr64, size); -} -#endif /* CONFIG_PHYS_64BIT */ - -void __iomem * -__ioremap(phys_addr_t addr, unsigned long size, unsigned long flags) -{ - unsigned long v, i; - phys_addr_t p; - int err; - - /* - * Choose an address to map it to. - * Once the vmalloc system is running, we use it. - * Before then, we use space going down from ioremap_base - * (ioremap_bot records where we're up to). - */ - p = addr & PAGE_MASK; - size = PAGE_ALIGN(addr + size) - p; - - /* - * If the address lies within the first 16 MB, assume it's in ISA - * memory space - */ - if (p < 16*1024*1024) - p += _ISA_MEM_BASE; - - /* - * Don't allow anybody to remap normal RAM that we're using. - * mem_init() sets high_memory so only do the check after that. - */ - if ( mem_init_done && (p < virt_to_phys(high_memory)) ) - { - printk("__ioremap(): phys addr "PHYS_FMT" is RAM lr %p\n", p, - __builtin_return_address(0)); - return NULL; - } - - if (size == 0) - return NULL; - - /* - * Is it already mapped? Perhaps overlapped by a previous - * BAT mapping. If the whole area is mapped then we're done, - * otherwise remap it since we want to keep the virt addrs for - * each request contiguous. - * - * We make the assumption here that if the bottom and top - * of the range we want are mapped then it's mapped to the - * same virt address (and this is contiguous). - * -- Cort - */ - if ((v = p_mapped_by_bats(p)) /*&& p_mapped_by_bats(p+size-1)*/ ) - goto out; - - if (mem_init_done) { - struct vm_struct *area; - area = get_vm_area(size, VM_IOREMAP); - if (area == 0) - return NULL; - v = (unsigned long) area->addr; - } else { - v = (ioremap_bot -= size); - } - - if ((flags & _PAGE_PRESENT) == 0) - flags |= _PAGE_KERNEL; - if (flags & _PAGE_NO_CACHE) - flags |= _PAGE_GUARDED; - - /* - * Should check if it is a candidate for a BAT mapping - */ - - err = 0; - for (i = 0; i < size && err == 0; i += PAGE_SIZE) - err = map_page(v+i, p+i, flags); - if (err) { - if (mem_init_done) - vunmap((void *)v); - return NULL; - } - -out: - return (void __iomem *) (v + ((unsigned long)addr & ~PAGE_MASK)); -} - -void iounmap(volatile void __iomem *addr) -{ - /* - * If mapped by BATs then there is nothing to do. - * Calling vfree() generates a benign warning. - */ - if (v_mapped_by_bats((unsigned long)addr)) return; - - if (addr > high_memory && (unsigned long) addr < ioremap_bot) - vunmap((void *) (PAGE_MASK & (unsigned long)addr)); -} - -void __iomem *ioport_map(unsigned long port, unsigned int len) -{ - return (void __iomem *) (port + _IO_BASE); -} - -void ioport_unmap(void __iomem *addr) -{ - /* Nothing to do */ -} -EXPORT_SYMBOL(ioport_map); -EXPORT_SYMBOL(ioport_unmap); - -int -map_page(unsigned long va, phys_addr_t pa, int flags) -{ - pmd_t *pd; - pte_t *pg; - int err = -ENOMEM; - - /* Use upper 10 bits of VA to index the first level map */ - pd = pmd_offset(pgd_offset_k(va), va); - /* Use middle 10 bits of VA to index the second-level map */ - pg = pte_alloc_kernel(pd, va); - if (pg != 0) { - err = 0; - set_pte_at(&init_mm, va, pg, pfn_pte(pa >> PAGE_SHIFT, __pgprot(flags))); - if (mem_init_done) - flush_HPTE(0, va, pmd_val(*pd)); - } - return err; -} - -/* - * Map in all of physical memory starting at KERNELBASE. - */ -void __init mapin_ram(void) -{ - unsigned long v, p, s, f; - - s = mmu_mapin_ram(); - v = KERNELBASE + s; - p = PPC_MEMSTART + s; - for (; s < total_lowmem; s += PAGE_SIZE) { - if ((char *) v >= _stext && (char *) v < etext) - f = _PAGE_RAM_TEXT; - else - f = _PAGE_RAM; - map_page(v, p, f); - v += PAGE_SIZE; - p += PAGE_SIZE; - } -} - -/* is x a power of 4? */ -#define is_power_of_4(x) is_power_of_2(x) && (ffs(x) & 1) - -/* - * Set up a mapping for a block of I/O. - * virt, phys, size must all be page-aligned. - * This should only be called before ioremap is called. - */ -void __init io_block_mapping(unsigned long virt, phys_addr_t phys, - unsigned int size, int flags) -{ - int i; - - if (virt > KERNELBASE && virt < ioremap_bot) - ioremap_bot = ioremap_base = virt; - -#ifdef HAVE_BATS - /* - * Use a BAT for this if possible... - */ - if (io_bat_index < 2 && is_power_of_2(size) - && (virt & (size - 1)) == 0 && (phys & (size - 1)) == 0) { - setbat(io_bat_index, virt, phys, size, flags); - ++io_bat_index; - return; - } -#endif /* HAVE_BATS */ - - /* No BATs available, put it in the page tables. */ - for (i = 0; i < size; i += PAGE_SIZE) - map_page(virt + i, phys + i, flags); -} - -/* Scan the real Linux page tables and return a PTE pointer for - * a virtual address in a context. - * Returns true (1) if PTE was found, zero otherwise. The pointer to - * the PTE pointer is unmodified if PTE is not found. - */ -int -get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep, pmd_t **pmdp) -{ - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - int retval = 0; - - pgd = pgd_offset(mm, addr & PAGE_MASK); - if (pgd) { - pmd = pmd_offset(pgd, addr & PAGE_MASK); - if (pmd_present(*pmd)) { - pte = pte_offset_map(pmd, addr & PAGE_MASK); - if (pte) { - retval = 1; - *ptep = pte; - if (pmdp) - *pmdp = pmd; - /* XXX caller needs to do pte_unmap, yuck */ - } - } - } - return(retval); -} - -/* Find physical address for this virtual address. Normally used by - * I/O functions, but anyone can call it. - */ -unsigned long iopa(unsigned long addr) -{ - unsigned long pa; - - /* I don't know why this won't work on PMacs or CHRP. It - * appears there is some bug, or there is some implicit - * mapping done not properly represented by BATs or in page - * tables.......I am actively working on resolving this, but - * can't hold up other stuff. -- Dan - */ - pte_t *pte; - struct mm_struct *mm; - - /* Check the BATs */ - pa = v_mapped_by_bats(addr); - if (pa) - return pa; - - /* Allow mapping of user addresses (within the thread) - * for DMA if necessary. - */ - if (addr < TASK_SIZE) - mm = current->mm; - else - mm = &init_mm; - - pa = 0; - if (get_pteptr(mm, addr, &pte, NULL)) { - pa = (pte_val(*pte) & PAGE_MASK) | (addr & ~PAGE_MASK); - pte_unmap(pte); - } - - return(pa); -} - diff --git a/arch/ppc/mm/ppc_mmu.c b/arch/ppc/mm/ppc_mmu.c deleted file mode 100644 index 0c1dc155996a..000000000000 --- a/arch/ppc/mm/ppc_mmu.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * This file contains the routines for handling the MMU on those - * PowerPC implementations where the MMU substantially follows the - * architecture specification. This includes the 6xx, 7xx, 7xxx, - * and 8260 implementations but excludes the 8xx and 4xx. - * -- paulus - * - * Derived from arch/ppc/mm/init.c: - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) - * and Cort Dougan (PReP) (cort@cs.nmt.edu) - * Copyright (C) 1996 Paul Mackerras - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). - * - * Derived from "arch/i386/mm/init.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include "mmu_decl.h" -#include "mem_pieces.h" - -PTE *Hash, *Hash_end; -unsigned long Hash_size, Hash_mask; -unsigned long _SDR1; - -union ubat { /* BAT register values to be loaded */ - BAT bat; - u32 word[2]; -} BATS[4][2]; /* 4 pairs of IBAT, DBAT */ - -struct batrange { /* stores address ranges mapped by BATs */ - unsigned long start; - unsigned long limit; - unsigned long phys; -} bat_addrs[4]; - -/* - * Return PA for this VA if it is mapped by a BAT, or 0 - */ -unsigned long v_mapped_by_bats(unsigned long va) -{ - int b; - for (b = 0; b < 4; ++b) - if (va >= bat_addrs[b].start && va < bat_addrs[b].limit) - return bat_addrs[b].phys + (va - bat_addrs[b].start); - return 0; -} - -/* - * Return VA for a given PA or 0 if not mapped - */ -unsigned long p_mapped_by_bats(unsigned long pa) -{ - int b; - for (b = 0; b < 4; ++b) - if (pa >= bat_addrs[b].phys - && pa < (bat_addrs[b].limit-bat_addrs[b].start) - +bat_addrs[b].phys) - return bat_addrs[b].start+(pa-bat_addrs[b].phys); - return 0; -} - -unsigned long __init mmu_mapin_ram(void) -{ - unsigned long tot, bl, done; - unsigned long max_size = (256<<20); - unsigned long align; - - if (__map_without_bats) - return 0; - - /* Set up BAT2 and if necessary BAT3 to cover RAM. */ - - /* Make sure we don't map a block larger than the - smallest alignment of the physical address. */ - /* alignment of PPC_MEMSTART */ - align = ~(PPC_MEMSTART-1) & PPC_MEMSTART; - /* set BAT block size to MIN(max_size, align) */ - if (align && align < max_size) - max_size = align; - - tot = total_lowmem; - for (bl = 128<<10; bl < max_size; bl <<= 1) { - if (bl * 2 > tot) - break; - } - - setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM); - done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1; - if ((done < tot) && !bat_addrs[3].limit) { - /* use BAT3 to cover a bit more */ - tot -= done; - for (bl = 128<<10; bl < max_size; bl <<= 1) - if (bl * 2 > tot) - break; - setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM); - done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1; - } - - return done; -} - -/* - * Set up one of the I/D BAT (block address translation) register pairs. - * The parameters are not checked; in particular size must be a power - * of 2 between 128k and 256M. - */ -void __init setbat(int index, unsigned long virt, unsigned long phys, - unsigned int size, int flags) -{ - unsigned int bl; - int wimgxpp; - union ubat *bat = BATS[index]; - - if (((flags & _PAGE_NO_CACHE) == 0) && - cpu_has_feature(CPU_FTR_NEED_COHERENT)) - flags |= _PAGE_COHERENT; - - bl = (size >> 17) - 1; - if (PVR_VER(mfspr(SPRN_PVR)) != 1) { - /* 603, 604, etc. */ - /* Do DBAT first */ - wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE - | _PAGE_COHERENT | _PAGE_GUARDED); - wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX; - bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */ - bat[1].word[1] = phys | wimgxpp; -#ifndef CONFIG_KGDB /* want user access for breakpoints */ - if (flags & _PAGE_USER) -#endif - bat[1].bat.batu.vp = 1; - if (flags & _PAGE_GUARDED) { - /* G bit must be zero in IBATs */ - bat[0].word[0] = bat[0].word[1] = 0; - } else { - /* make IBAT same as DBAT */ - bat[0] = bat[1]; - } - } else { - /* 601 cpu */ - if (bl > BL_8M) - bl = BL_8M; - wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE - | _PAGE_COHERENT); - wimgxpp |= (flags & _PAGE_RW)? - ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX; - bat->word[0] = virt | wimgxpp | 4; /* Ks=0, Ku=1 */ - bat->word[1] = phys | bl | 0x40; /* V=1 */ - } - - bat_addrs[index].start = virt; - bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1; - bat_addrs[index].phys = phys; -} - -/* - * Initialize the hash table and patch the instructions in hashtable.S. - */ -void __init MMU_init_hw(void) -{ - unsigned int hmask, mb, mb2; - unsigned int n_hpteg, lg_n_hpteg; - - extern unsigned int hash_page_patch_A[]; - extern unsigned int hash_page_patch_B[], hash_page_patch_C[]; - extern unsigned int hash_page[]; - extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[]; - - if (!cpu_has_feature(CPU_FTR_HPTE_TABLE)) { - /* - * Put a blr (procedure return) instruction at the - * start of hash_page, since we can still get DSI - * exceptions on a 603. - */ - hash_page[0] = 0x4e800020; - flush_icache_range((unsigned long) &hash_page[0], - (unsigned long) &hash_page[1]); - return; - } - - if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105); - -#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */ -#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10) -#define MIN_N_HPTEG 1024 /* min 64kB hash table */ - - /* - * Allow 1 HPTE (1/8 HPTEG) for each page of memory. - * This is less than the recommended amount, but then - * Linux ain't AIX. - */ - n_hpteg = total_memory / (PAGE_SIZE * 8); - if (n_hpteg < MIN_N_HPTEG) - n_hpteg = MIN_N_HPTEG; - lg_n_hpteg = __ilog2(n_hpteg); - if (n_hpteg & (n_hpteg - 1)) { - ++lg_n_hpteg; /* round up if not power of 2 */ - n_hpteg = 1 << lg_n_hpteg; - } - Hash_size = n_hpteg << LG_HPTEG_SIZE; - - /* - * Find some memory for the hash table. - */ - if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322); - Hash = mem_pieces_find(Hash_size, Hash_size); - cacheable_memzero(Hash, Hash_size); - _SDR1 = __pa(Hash) | SDR1_LOW_BITS; - - Hash_end = (PTE *) ((unsigned long)Hash + Hash_size); - - printk("Total memory = %ldMB; using %ldkB for hash table (at %p)\n", - total_memory >> 20, Hash_size >> 10, Hash); - - - /* - * Patch up the instructions in hashtable.S:create_hpte - */ - if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345); - Hash_mask = n_hpteg - 1; - hmask = Hash_mask >> (16 - LG_HPTEG_SIZE); - mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg; - if (lg_n_hpteg > 16) - mb2 = 16 - LG_HPTEG_SIZE; - - hash_page_patch_A[0] = (hash_page_patch_A[0] & ~0xffff) - | ((unsigned int)(Hash) >> 16); - hash_page_patch_A[1] = (hash_page_patch_A[1] & ~0x7c0) | (mb << 6); - hash_page_patch_A[2] = (hash_page_patch_A[2] & ~0x7c0) | (mb2 << 6); - hash_page_patch_B[0] = (hash_page_patch_B[0] & ~0xffff) | hmask; - hash_page_patch_C[0] = (hash_page_patch_C[0] & ~0xffff) | hmask; - - /* - * Ensure that the locations we've patched have been written - * out from the data cache and invalidated in the instruction - * cache, on those machines with split caches. - */ - flush_icache_range((unsigned long) &hash_page_patch_A[0], - (unsigned long) &hash_page_patch_C[1]); - - /* - * Patch up the instructions in hashtable.S:flush_hash_page - */ - flush_hash_patch_A[0] = (flush_hash_patch_A[0] & ~0xffff) - | ((unsigned int)(Hash) >> 16); - flush_hash_patch_A[1] = (flush_hash_patch_A[1] & ~0x7c0) | (mb << 6); - flush_hash_patch_A[2] = (flush_hash_patch_A[2] & ~0x7c0) | (mb2 << 6); - flush_hash_patch_B[0] = (flush_hash_patch_B[0] & ~0xffff) | hmask; - flush_icache_range((unsigned long) &flush_hash_patch_A[0], - (unsigned long) &flush_hash_patch_B[1]); - - if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205); -} diff --git a/arch/ppc/mm/tlb.c b/arch/ppc/mm/tlb.c deleted file mode 100644 index 4ff260bc9dd1..000000000000 --- a/arch/ppc/mm/tlb.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * This file contains the routines for TLB flushing. - * On machines where the MMU uses a hash table to store virtual to - * physical translations, these routines flush entries from the - * hash table also. - * -- paulus - * - * Derived from arch/ppc/mm/init.c: - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) - * and Cort Dougan (PReP) (cort@cs.nmt.edu) - * Copyright (C) 1996 Paul Mackerras - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). - * - * Derived from "arch/i386/mm/init.c" - * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "mmu_decl.h" - -/* - * Called when unmapping pages to flush entries from the TLB/hash table. - */ -void flush_hash_entry(struct mm_struct *mm, pte_t *ptep, unsigned long addr) -{ - unsigned long ptephys; - - if (Hash != 0) { - ptephys = __pa(ptep) & PAGE_MASK; - flush_hash_pages(mm->context.id, addr, ptephys, 1); - } -} - -/* - * Called by ptep_set_access_flags, must flush on CPUs for which the - * DSI handler can't just "fixup" the TLB on a write fault - */ -void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr) -{ - if (Hash != 0) - return; - _tlbie(addr); -} - -/* - * Called at the end of a mmu_gather operation to make sure the - * TLB flush is completely done. - */ -void tlb_flush(struct mmu_gather *tlb) -{ - if (Hash == 0) { - /* - * 603 needs to flush the whole TLB here since - * it doesn't use a hash table. - */ - _tlbia(); - } -} - -/* - * TLB flushing: - * - * - flush_tlb_mm(mm) flushes the specified mm context TLB's - * - flush_tlb_page(vma, vmaddr) flushes one page - * - flush_tlb_range(vma, start, end) flushes a range of pages - * - flush_tlb_kernel_range(start, end) flushes kernel pages - * - * since the hardware hash table functions as an extension of the - * tlb as far as the linux tables are concerned, flush it too. - * -- Cort - */ - -/* - * 750 SMP is a Bad Idea because the 750 doesn't broadcast all - * the cache operations on the bus. Hence we need to use an IPI - * to get the other CPU(s) to invalidate their TLBs. - */ -#ifdef CONFIG_SMP_750 -#define FINISH_FLUSH smp_send_tlb_invalidate(0) -#else -#define FINISH_FLUSH do { } while (0) -#endif - -static void flush_range(struct mm_struct *mm, unsigned long start, - unsigned long end) -{ - pmd_t *pmd; - unsigned long pmd_end; - int count; - unsigned int ctx = mm->context.id; - - if (Hash == 0) { - _tlbia(); - return; - } - start &= PAGE_MASK; - if (start >= end) - return; - end = (end - 1) | ~PAGE_MASK; - pmd = pmd_offset(pgd_offset(mm, start), start); - for (;;) { - pmd_end = ((start + PGDIR_SIZE) & PGDIR_MASK) - 1; - if (pmd_end > end) - pmd_end = end; - if (!pmd_none(*pmd)) { - count = ((pmd_end - start) >> PAGE_SHIFT) + 1; - flush_hash_pages(ctx, start, pmd_val(*pmd), count); - } - if (pmd_end == end) - break; - start = pmd_end + 1; - ++pmd; - } -} - -/* - * Flush kernel TLB entries in the given range - */ -void flush_tlb_kernel_range(unsigned long start, unsigned long end) -{ - flush_range(&init_mm, start, end); - FINISH_FLUSH; -} - -/* - * Flush all the (user) entries for the address space described by mm. - */ -void flush_tlb_mm(struct mm_struct *mm) -{ - struct vm_area_struct *mp; - - if (Hash == 0) { - _tlbia(); - return; - } - - for (mp = mm->mmap; mp != NULL; mp = mp->vm_next) - flush_range(mp->vm_mm, mp->vm_start, mp->vm_end); - FINISH_FLUSH; -} - -void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) -{ - struct mm_struct *mm; - pmd_t *pmd; - - if (Hash == 0) { - _tlbie(vmaddr); - return; - } - mm = (vmaddr < TASK_SIZE)? vma->vm_mm: &init_mm; - pmd = pmd_offset(pgd_offset(mm, vmaddr), vmaddr); - if (!pmd_none(*pmd)) - flush_hash_pages(mm->context.id, vmaddr, pmd_val(*pmd), 1); - FINISH_FLUSH; -} - -/* - * For each address in the range, find the pte for the address - * and check _PAGE_HASHPTE bit; if it is set, find and destroy - * the corresponding HPTE. - */ -void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - flush_range(vma->vm_mm, start, end); - FINISH_FLUSH; -} diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig deleted file mode 100644 index 76551b679030..000000000000 --- a/arch/ppc/platforms/4xx/Kconfig +++ /dev/null @@ -1,285 +0,0 @@ -config 4xx - bool - depends on 40x || 44x - default y - -config WANT_EARLY_SERIAL - bool - select SERIAL_8250 - default n - -menu "IBM 4xx options" - depends on 4xx - -choice - prompt "Machine Type" - depends on 40x - default WALNUT - -config BUBINGA - bool "Bubinga" - select WANT_EARLY_SERIAL - help - This option enables support for the IBM 405EP evaluation board. - -config CPCI405 - bool "CPCI405" - help - This option enables support for the CPCI405 board. - -config EP405 - bool "EP405/EP405PC" - select EMBEDDEDBOOT - help - This option enables support for the EP405/EP405PC boards. - -config REDWOOD_5 - bool "Redwood-5" - help - This option enables support for the IBM STB04 evaluation board. - -config REDWOOD_6 - bool "Redwood-6" - help - This option enables support for the IBM STBx25xx evaluation board. - -config SYCAMORE - bool "Sycamore" - help - This option enables support for the IBM PPC405GPr evaluation board. - -config WALNUT - bool "Walnut" - help - This option enables support for the IBM PPC405GP evaluation board. - -config XILINX_ML300 - bool "Xilinx-ML300" - select XILINX_VIRTEX_II_PRO - select EMBEDDEDBOOT - help - This option enables support for the Xilinx ML300 evaluation board. - -config XILINX_ML403 - bool "Xilinx-ML403" - select XILINX_VIRTEX_4_FX - select EMBEDDEDBOOT - help - This option enables support for the Xilinx ML403 evaluation board. -endchoice - -choice - prompt "Machine Type" - depends on 44x - default EBONY - -config BAMBOO - bool "Bamboo" - select WANT_EARLY_SERIAL - help - This option enables support for the IBM PPC440EP evaluation board. - -config EBONY - bool "Ebony" - select WANT_EARLY_SERIAL - help - This option enables support for the IBM PPC440GP evaluation board. - -config LUAN - bool "Luan" - select WANT_EARLY_SERIAL - help - This option enables support for the IBM PPC440SP evaluation board. - -config YUCCA - bool "Yucca" - select WANT_EARLY_SERIAL - help - This option enables support for the AMCC PPC440SPe evaluation board. - -config OCOTEA - bool "Ocotea" - select WANT_EARLY_SERIAL - help - This option enables support for the IBM PPC440GX evaluation board. - -config TAISHAN - bool "Taishan" - select WANT_EARLY_SERIAL - help - This option enables support for the AMCC PPC440GX evaluation board. - -endchoice - -config EP405PC - bool "EP405PC Support" - depends on EP405 - - -# It's often necessary to know the specific 4xx processor type. -# Fortunately, it is impled (so far) from the board type, so we -# don't need to ask more redundant questions. -config NP405H - bool - depends on ASH - default y - -config 440EP - bool - depends on BAMBOO - select PPC_FPU - default y - -config 440GP - bool - depends on EBONY - default y - -config 440GX - bool - depends on OCOTEA || TAISHAN - default y - -config 440SP - bool - depends on LUAN - default y - -config 440SPE - bool - depends on YUCCA - default y - -config 440 - bool - depends on 440GP || 440SP || 440SPE || 440EP - default y - -config 440A - bool - depends on 440GX - default y - -config IBM440EP_ERR42 - bool - depends on 440EP - default y - -# All 405-based cores up until the 405GPR and 405EP have this errata. -config IBM405_ERR77 - bool - depends on 40x && !403GCX && !405GPR && !405EP - default y - -# All 40x-based cores, up until the 405GPR and 405EP have this errata. -config IBM405_ERR51 - bool - depends on 40x && !405GPR && !405EP - default y - -config BOOKE - bool - depends on 44x - default y - -config IBM_OCP - bool - depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT - default y - -config IBM_EMAC4 - bool - depends on 440GX || 440SP || 440SPE - default y - -config BIOS_FIXUP - bool - depends on BUBINGA || EP405 || SYCAMORE || WALNUT || CPCI405 - default y - -# OAK doesn't exist but wanted to keep this around for any future 403GCX boards -config 403GCX - bool - depends on OAK - default y - -config 405EP - bool - depends on BUBINGA - default y - -config 405GP - bool - depends on CPCI405 || EP405 || WALNUT - default y - -config 405GPR - bool - depends on SYCAMORE - default y - -config XILINX_VIRTEX_II_PRO - bool - select XILINX_VIRTEX - -config XILINX_VIRTEX_4_FX - bool - select XILINX_VIRTEX - -config XILINX_VIRTEX - bool - -config STB03xxx - bool - depends on REDWOOD_5 || REDWOOD_6 - default y - -config EMBEDDEDBOOT - bool - -config IBM_OPENBIOS - bool - depends on ASH || REDWOOD_5 || REDWOOD_6 - default y - -config PPC4xx_DMA - bool "PPC4xx DMA controller support" - depends on 4xx - -config PPC4xx_EDMA - bool - depends on !STB03xxx && PPC4xx_DMA - default y - -config PPC_GEN550 - bool - depends on 4xx - default y - -choice - prompt "TTYS0 device and default console" - depends on 40x - default UART0_TTYS0 - -config UART0_TTYS0 - bool "UART0" - -config UART0_TTYS1 - bool "UART1" - -endchoice - -config SERIAL_SICC - bool "SICC Serial port support" - depends on STB03xxx - -config UART1_DFLT_CONSOLE - bool - depends on SERIAL_SICC && UART0_TTYS1 - default y - -config SERIAL_SICC_CONSOLE - bool - depends on SERIAL_SICC && UART0_TTYS1 - default y -endmenu diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile deleted file mode 100644 index 723ad7985cc6..000000000000 --- a/arch/ppc/platforms/4xx/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# Makefile for the PowerPC 4xx linux kernel. - -obj-$(CONFIG_BAMBOO) += bamboo.o -obj-$(CONFIG_CPCI405) += cpci405.o -obj-$(CONFIG_EBONY) += ebony.o -obj-$(CONFIG_EP405) += ep405.o -obj-$(CONFIG_BUBINGA) += bubinga.o -obj-$(CONFIG_LUAN) += luan.o -obj-$(CONFIG_YUCCA) += yucca.o -obj-$(CONFIG_OCOTEA) += ocotea.o -obj-$(CONFIG_REDWOOD_5) += redwood5.o -obj-$(CONFIG_REDWOOD_6) += redwood6.o -obj-$(CONFIG_SYCAMORE) += sycamore.o -obj-$(CONFIG_TAISHAN) += taishan.o -obj-$(CONFIG_WALNUT) += walnut.o -obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o -obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o - -obj-$(CONFIG_405GP) += ibm405gp.o -obj-$(CONFIG_REDWOOD_5) += ibmstb4.o -obj-$(CONFIG_NP405H) += ibmnp405h.o -obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o -obj-$(CONFIG_440EP) += ibm440ep.o -obj-$(CONFIG_440GP) += ibm440gp.o -obj-$(CONFIG_440GX) += ibm440gx.o -obj-$(CONFIG_440SP) += ibm440sp.o -obj-$(CONFIG_440SPE) += ppc440spe.o -obj-$(CONFIG_405EP) += ibm405ep.o -obj-$(CONFIG_405GPR) += ibm405gpr.o - diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c deleted file mode 100644 index 01f20f4c14fe..000000000000 --- a/arch/ppc/platforms/4xx/bamboo.c +++ /dev/null @@ -1,442 +0,0 @@ -/* - * Bamboo board specific routines - * - * Wade Farnsworth - * Copyright 2004 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -extern bd_t __res; - -static struct ibm44x_clocks clocks __initdata; - -/* - * Bamboo external IRQ triggering/polarity settings - */ -unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */ -}; - -static void __init -bamboo_calibrate_decr(void) -{ - unsigned int freq; - - if (mfspr(SPRN_CCR1) & CCR1_TCS) - freq = BAMBOO_TMRCLK; - else - freq = clocks.cpu; - - ibm44x_calibrate_decr(freq); - -} - -static int -bamboo_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: IBM\n"); - seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n"); - - return 0; -} - -static inline int -bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */ - { 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */ - { 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */ - { 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */ - }; - - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -static void __init bamboo_set_emacdata(void) -{ - u8 * base_addr; - struct ocp_def *def; - struct ocp_func_emac_data *emacdata; - u8 val; - int mode; - u32 excluded = 0; - - base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16); - val = readb(base_addr); - iounmap((void *) base_addr); - if (BAMBOO_SEL_MII(val)) - mode = PHY_MODE_MII; - else if (BAMBOO_SEL_RMII(val)) - mode = PHY_MODE_RMII; - else - mode = PHY_MODE_SMII; - - /* - * SW2 on the Bamboo is used for ethernet configuration and is accessed - * via the CONFIG2 register in the FPGA. If the ANEG pin is set, - * overwrite the supported features with the settings in SW2. - * - * This is used as a workaround for the improperly biased RJ-45 sockets - * on the Rev. 0 Bamboo. By default only 10baseT is functional. - * Removing inductors L17 and L18 from the board allows 100baseT, but - * disables 10baseT. The Rev. 1 has no such limitations. - */ - - base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8); - val = readb(base_addr); - iounmap((void *) base_addr); - if (!BAMBOO_AUTONEGOTIATE(val)) { - excluded |= SUPPORTED_Autoneg; - if (BAMBOO_FORCE_100Mbps(val)) { - excluded |= SUPPORTED_10baseT_Full; - excluded |= SUPPORTED_10baseT_Half; - if (BAMBOO_FULL_DUPLEX_EN(val)) - excluded |= SUPPORTED_100baseT_Half; - else - excluded |= SUPPORTED_100baseT_Full; - } else { - excluded |= SUPPORTED_100baseT_Full; - excluded |= SUPPORTED_100baseT_Half; - if (BAMBOO_FULL_DUPLEX_EN(val)) - excluded |= SUPPORTED_10baseT_Half; - else - excluded |= SUPPORTED_10baseT_Full; - } - } - - /* Set mac_addr, phy mode and unsupported phy features for each EMAC */ - - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); - emacdata = def->additions; - memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); - emacdata->phy_mode = mode; - emacdata->phy_feat_exc = excluded; - - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1); - emacdata = def->additions; - memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); - emacdata->phy_mode = mode; - emacdata->phy_feat_exc = excluded; -} - -static int -bamboo_exclude_device(unsigned char bus, unsigned char devfn) -{ - return (bus == 0 && devfn == 0); -} - -#define PCI_READW(offset) \ - (readw((void *)((u32)pci_reg_base+offset))) - -#define PCI_WRITEW(value, offset) \ - (writew(value, (void *)((u32)pci_reg_base+offset))) - -#define PCI_WRITEL(value, offset) \ - (writel(value, (void *)((u32)pci_reg_base+offset))) - -static void __init -bamboo_setup_pci(void) -{ - void *pci_reg_base; - unsigned long memory_size; - memory_size = ppc_md.find_end_of_memory(); - - pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE); - - /* Enable PCI I/O, Mem, and Busmaster cycles */ - PCI_WRITEW(PCI_READW(PCI_COMMAND) | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER, PCI_COMMAND); - - /* Disable region first */ - PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA); - - /* PLB starting addr: 0x00000000A0000000 */ - PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA); - - /* PCI start addr, 0xA0000000 (PCI Address) */ - PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA); - PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA); - - /* Enable no pre-fetch, enable region */ - PCI_WRITEL(((0xffffffff - - (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01), - BAMBOO_PCIL0_PMM0MA); - - /* Disable region one */ - PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA); - PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA); - PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA); - PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA); - PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA); - - /* Disable region two */ - PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA); - PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA); - PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA); - PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA); - PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA); - - /* Now configure the PCI->PLB windows, we only use PTM1 - * - * For Inbound flow, set the window size to all available memory - * This is required because if size is smaller, - * then Eth/PCI DD would fail as PCI card not able to access - * the memory allocated by DD. - */ - - PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */ - PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */ - - memory_size = 1 << fls(memory_size - 1); - - /* Size low + Enabled */ - PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS); - - eieio(); - iounmap(pci_reg_base); -} - -static void __init -bamboo_setup_hose(void) -{ - unsigned int bar_response, bar; - struct pci_controller *hose; - - bamboo_setup_pci(); - - hose = pcibios_alloc_controller(); - - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET; - - pci_init_resource(&hose->io_resource, - BAMBOO_PCI_LOWER_IO, - BAMBOO_PCI_UPPER_IO, - IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource(&hose->mem_resources[0], - BAMBOO_PCI_LOWER_MEM, - BAMBOO_PCI_UPPER_MEM, - IORESOURCE_MEM, - "PCI host bridge"); - - ppc_md.pci_exclude_device = bamboo_exclude_device; - - hose->io_space.start = BAMBOO_PCI_LOWER_IO; - hose->io_space.end = BAMBOO_PCI_UPPER_IO; - hose->mem_space.start = BAMBOO_PCI_LOWER_MEM; - hose->mem_space.end = BAMBOO_PCI_UPPER_MEM; - isa_io_base = - (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE); - hose->io_base_virt = (void *)isa_io_base; - - setup_indirect_pci(hose, - BAMBOO_PCI_CFGA_PLB32, - BAMBOO_PCI_CFGD_PLB32); - hose->set_cfg_type = 1; - - /* Zero config bars */ - for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { - early_write_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - 0x00000000); - early_read_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - &bar_response); - } - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = bamboo_map_irq; -} - -TODC_ALLOC(); - -static void __init -bamboo_early_serial_map(void) -{ - struct uart_port port; - - /* Setup ioremapped serial port access */ - memset(&port, 0, sizeof(port)); - port.membase = ioremap64(PPC440EP_UART0_ADDR, 8); - port.irq = 0; - port.uartclk = clocks.uart0; - port.regshift = 0; - port.iotype = UPIO_MEM; - port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - port.line = 0; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 0 failed\n"); - } - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Configure debug serial access */ - gen550_init(0, &port); -#endif - - port.membase = ioremap64(PPC440EP_UART1_ADDR, 8); - port.irq = 1; - port.uartclk = clocks.uart1; - port.line = 1; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 1 failed\n"); - } - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Configure debug serial access */ - gen550_init(1, &port); -#endif - - port.membase = ioremap64(PPC440EP_UART2_ADDR, 8); - port.irq = 3; - port.uartclk = clocks.uart2; - port.line = 2; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 2 failed\n"); - } - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Configure debug serial access */ - gen550_init(2, &port); -#endif - - port.membase = ioremap64(PPC440EP_UART3_ADDR, 8); - port.irq = 4; - port.uartclk = clocks.uart3; - port.line = 3; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 3 failed\n"); - } -} - -static void __init -bamboo_setup_arch(void) -{ - - bamboo_set_emacdata(); - - ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); - ocp_sys_info.opb_bus_freq = clocks.opb; - - /* Setup TODC access */ - TODC_INIT(TODC_TYPE_DS1743, - 0, - 0, - ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE), - 8); - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - - /* Setup PCI host bridge */ - bamboo_setup_hose(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_HDA1; -#endif - - bamboo_early_serial_map(); - - /* Identify the system */ - printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n"); -} - -void __init platform_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, unsigned long r7) -{ - ibm44x_platform_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = bamboo_setup_arch; - ppc_md.show_cpuinfo = bamboo_show_cpuinfo; - ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ - - ppc_md.calibrate_decr = bamboo_calibrate_decr; - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; -#ifdef CONFIG_KGDB - ppc_md.early_serial_map = bamboo_early_serial_map; -#endif -} - diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h deleted file mode 100644 index dcd3d09a0a71..000000000000 --- a/arch/ppc/platforms/4xx/bamboo.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Bamboo board definitions - * - * Wade Farnsworth - * - * Copyright 2004 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_BAMBOO_H__ -#define __ASM_BAMBOO_H__ - -#include - -/* F/W TLB mapping used in bootloader glue to reset EMAC */ -#define PPC44x_EMAC0_MR0 0x0EF600E00 - -/* Location of MAC addresses in PIBS image */ -#define PIBS_FLASH_BASE 0xfff00000 -#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xc0400) -#define PIBS_MAC_SIZE 0x200 -#define PIBS_MAC_OFFSET 0x100 - -/* Default clock rate */ -#define BAMBOO_TMRCLK 25000000 - -/* RTC/NVRAM location */ -#define BAMBOO_RTC_ADDR 0x080000000ULL -#define BAMBOO_RTC_SIZE 0x2000 - -/* FPGA Registers */ -#define BAMBOO_FPGA_ADDR 0x080002000ULL - -#define BAMBOO_FPGA_CONFIG2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x1) -#define BAMBOO_FULL_DUPLEX_EN(x) (x & 0x08) -#define BAMBOO_FORCE_100Mbps(x) (x & 0x04) -#define BAMBOO_AUTONEGOTIATE(x) (x & 0x02) - -#define BAMBOO_FPGA_SETTING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x3) -#define BAMBOO_BOOT_SMALL_FLASH(x) (!(x & 0x80)) -#define BAMBOO_LARGE_FLASH_EN(x) (!(x & 0x40)) -#define BAMBOO_BOOT_NAND_FLASH(x) (!(x & 0x20)) - -#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4) -#define BAMBOO_SEL_MII(x) (x & 0x80) -#define BAMBOO_SEL_RMII(x) (x & 0x40) -#define BAMBOO_SEL_SMII(x) (x & 0x20) - -/* Flash */ -#define BAMBOO_SMALL_FLASH_LOW 0x087f00000ULL -#define BAMBOO_SMALL_FLASH_HIGH 0x0fff00000ULL -#define BAMBOO_SMALL_FLASH_SIZE 0x100000 -#define BAMBOO_LARGE_FLASH_LOW 0x087800000ULL -#define BAMBOO_LARGE_FLASH_HIGH1 0x0ff800000ULL -#define BAMBOO_LARGE_FLASH_HIGH2 0x0ffc00000ULL -#define BAMBOO_LARGE_FLASH_SIZE 0x400000 -#define BAMBOO_SRAM_LOW 0x087f00000ULL -#define BAMBOO_SRAM_HIGH1 0x0fff00000ULL -#define BAMBOO_SRAM_HIGH2 0x0ff800000ULL -#define BAMBOO_SRAM_SIZE 0x100000 -#define BAMBOO_NAND_FLASH_REG_ADDR 0x090000000ULL -#define BAMBOO_NAND_FLASH_REG_SIZE 0x2000 - -/* - * Serial port defines - */ -#define RS_TABLE_SIZE 4 - -#define UART0_IO_BASE 0xEF600300 -#define UART1_IO_BASE 0xEF600400 -#define UART2_IO_BASE 0xEF600500 -#define UART3_IO_BASE 0xEF600600 - -#define BASE_BAUD 33177600/3/16 -#define UART0_INT 0 -#define UART1_INT 1 -#define UART2_INT 3 -#define UART3_INT 4 - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (void*)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) \ - STD_UART_OP(2) \ - STD_UART_OP(3) - -/* PCI support */ -#define BAMBOO_PCI_CFGA_PLB32 0xeec00000 -#define BAMBOO_PCI_CFGD_PLB32 0xeec00004 - -#define BAMBOO_PCI_IO_BASE 0x00000000e8000000ULL -#define BAMBOO_PCI_IO_SIZE 0x00010000 -#define BAMBOO_PCI_MEM_OFFSET 0x00000000 -#define BAMBOO_PCI_PHY_MEM_BASE 0x00000000a0000000ULL - -#define BAMBOO_PCI_LOWER_IO 0x00000000 -#define BAMBOO_PCI_UPPER_IO 0x0000ffff -#define BAMBOO_PCI_LOWER_MEM 0xa0000000 -#define BAMBOO_PCI_UPPER_MEM 0xafffffff -#define BAMBOO_PCI_MEM_BASE 0xa0000000 - -#define BAMBOO_PCIL0_BASE 0x00000000ef400000ULL -#define BAMBOO_PCIL0_SIZE 0x40 - -#define BAMBOO_PCIL0_PMM0LA 0x000 -#define BAMBOO_PCIL0_PMM0MA 0x004 -#define BAMBOO_PCIL0_PMM0PCILA 0x008 -#define BAMBOO_PCIL0_PMM0PCIHA 0x00C -#define BAMBOO_PCIL0_PMM1LA 0x010 -#define BAMBOO_PCIL0_PMM1MA 0x014 -#define BAMBOO_PCIL0_PMM1PCILA 0x018 -#define BAMBOO_PCIL0_PMM1PCIHA 0x01C -#define BAMBOO_PCIL0_PMM2LA 0x020 -#define BAMBOO_PCIL0_PMM2MA 0x024 -#define BAMBOO_PCIL0_PMM2PCILA 0x028 -#define BAMBOO_PCIL0_PMM2PCIHA 0x02C -#define BAMBOO_PCIL0_PTM1MS 0x030 -#define BAMBOO_PCIL0_PTM1LA 0x034 -#define BAMBOO_PCIL0_PTM2MS 0x038 -#define BAMBOO_PCIL0_PTM2LA 0x03C - -#endif /* __ASM_BAMBOO_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c deleted file mode 100644 index cd696be55aca..000000000000 --- a/arch/ppc/platforms/4xx/bubinga.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Support for IBM PPC 405EP evaluation board (Bubinga). - * - * Author: SAW (IBM), derived from walnut.c. - * Maintained by MontaVista Software - * - * 2003 (c) MontaVista Softare Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -extern bd_t __res; - -void *bubinga_rtc_base; - -/* Some IRQs unique to the board - * Used by the generic 405 PCI setup functions in ppc4xx_pci.c - */ -int __init -ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */ - {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */ - {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */ - {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */ - }; - - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -}; - -/* The serial clock for the chip is an internal clock determined by - * different clock speeds/dividers. - * Calculate the proper input baud rate and setup the serial driver. - */ -static void __init -bubinga_early_serial_map(void) -{ - u32 uart_div; - int uart_clock; - struct uart_port port; - - /* Calculate the serial clock input frequency - * - * The base baud is the PLL OUTA (provided in the board info - * structure) divided by the external UART Divisor, divided - * by 16. - */ - uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV); - uart_clock = __res.bi_procfreq / uart_div; - - /* Setup serial port access */ - memset(&port, 0, sizeof(port)); - port.membase = (void*)ACTING_UART0_IO_BASE; - port.irq = ACTING_UART0_INT; - port.uartclk = uart_clock; - port.regshift = 0; - port.iotype = UPIO_MEM; - port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - port.line = 0; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 0 failed\n"); - } - - port.membase = (void*)ACTING_UART1_IO_BASE; - port.irq = ACTING_UART1_INT; - port.line = 1; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 1 failed\n"); - } -} - -void __init -bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) -{ -#ifdef CONFIG_PCI - - unsigned int bar_response, bar; - /* - * Expected PCI mapping: - * - * PLB addr PCI memory addr - * --------------------- --------------------- - * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff - * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff - * - * PLB addr PCI io addr - * --------------------- --------------------- - * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 - * - * The following code is simplified by assuming that the bootrom - * has been well behaved in following this mapping. - */ - -#ifdef DEBUG - int i; - - printk("ioremap PCLIO_BASE = 0x%x\n", pcip); - printk("PCI bridge regs before fixup \n"); - for (i = 0; i <= 3; i++) { - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); - } - printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); - printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); - printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); - printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); - -#endif - - /* added for IBM boot rom version 1.15 bios bar changes -AK */ - - /* Disable region first */ - out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); - /* PLB starting addr, PCI: 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].la), 0x80000000); - /* PCI start addr, 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); - /* 512MB range of PLB to PCI */ - out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); - /* Enable no pre-fetch, enable region */ - out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - - (PPC405_PCI_UPPER_MEM - - PPC405_PCI_MEM_BASE)) | 0x01)); - - /* Disable region one */ - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[1].la), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->ptm1ms), 0x00000001); - - /* Disable region two */ - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[2].la), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->ptm2ms), 0x00000000); - out_le32((void *) &(pcip->ptm2la), 0x00000000); - - /* Zero config bars */ - for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { - early_write_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - 0x00000000); - early_read_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - &bar_response); - DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", - hose->first_busno, PCI_SLOT(hose->first_busno), - PCI_FUNC(hose->first_busno), bar, bar_response); - } - /* end workaround */ - -#ifdef DEBUG - printk("PCI bridge regs after fixup \n"); - for (i = 0; i <= 3; i++) { - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); - } - printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); - printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); - printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); - printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); - -#endif -#endif -} - -void __init -bubinga_setup_arch(void) -{ - ppc4xx_setup_arch(); - - ibm_ocp_set_emac(0, 1); - - bubinga_early_serial_map(); - - /* RTC step for the evb405ep */ - bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR; - TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base, - bubinga_rtc_base, 8); - /* Identify the system */ - printk("IBM Bubinga port (MontaVista Software, Inc. )\n"); -} - -void __init -bubinga_map_io(void) -{ - ppc4xx_map_io(); - io_block_mapping(BUBINGA_RTC_VADDR, - BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = bubinga_setup_arch; - ppc_md.setup_io_mappings = bubinga_map_io; - -#ifdef CONFIG_GEN_RTC - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; -#endif -#ifdef CONFIG_KGDB - ppc_md.early_serial_map = bubinga_early_serial_map; -#endif -} - diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h deleted file mode 100644 index 5c408060eb35..000000000000 --- a/arch/ppc/platforms/4xx/bubinga.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Bubinga board definitions - * - * Copyright (c) 2005 DENX Software Engineering - * Stefan Roese - * - * Based on original work by - * SAW (IBM) - * 2003 (c) MontaVista Softare Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __BUBINGA_H__ -#define __BUBINGA_H__ - -#include -#include - -/* Memory map for the Bubinga board. - * Generic 4xx plus RTC. - */ - -#define BUBINGA_RTC_PADDR ((uint)0xf0000000) -#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR -#define BUBINGA_RTC_SIZE ((uint)8*1024) - -/* The UART clock is based off an internal clock - - * define BASE_BAUD based on the internal clock and divider(s). - * Since BASE_BAUD must be a constant, we will initialize it - * using clock/divider values which OpenBIOS initializes - * for typical configurations at various CPU speeds. - * The base baud is calculated as (FWDA / EXT UART DIV / 16) - */ -#define BASE_BAUD 0 - -/* Flash */ -#define PPC40x_FPGA_BASE 0xF0300000 -#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */ -#define PPC40x_FLASH_ONBD_N(x) (x & 0x02) -#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01) -#define PPC40x_FLASH_LOW 0xFFF00000 -#define PPC40x_FLASH_HIGH 0xFFF80000 -#define PPC40x_FLASH_SIZE 0x80000 - -#define PPC4xx_MACHINE_NAME "IBM Bubinga" - -#endif /* __BUBINGA_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c deleted file mode 100644 index 2e7e25dd84cb..000000000000 --- a/arch/ppc/platforms/4xx/cpci405.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Board setup routines for the esd CPCI-405 cPCI Board. - * - * Copyright 2001-2006 esd electronic system design - hannover germany - * - * Authors: Matthias Fuchs - * matthias.fuchs@esd-electronics.com - * Stefan Roese - * stefan.roese@esd-electronics.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_GEN_RTC -void *cpci405_nvram; -#endif - -extern bd_t __res; - -/* - * Some IRQs unique to CPCI-405. - */ -int __init -ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {28, 29, 30, 27}, /* IDSEL 15 - cPCI slot 8 */ - {29, 30, 27, 28}, /* IDSEL 16 - cPCI slot 7 */ - {30, 27, 28, 29}, /* IDSEL 17 - cPCI slot 6 */ - {27, 28, 29, 30}, /* IDSEL 18 - cPCI slot 5 */ - {28, 29, 30, 27}, /* IDSEL 19 - cPCI slot 4 */ - {29, 30, 27, 28}, /* IDSEL 20 - cPCI slot 3 */ - {30, 27, 28, 29}, /* IDSEL 21 - cPCI slot 2 */ - }; - const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -}; - -/* The serial clock for the chip is an internal clock determined by - * different clock speeds/dividers. - * Calculate the proper input baud rate and setup the serial driver. - */ -static void __init -cpci405_early_serial_map(void) -{ - u32 uart_div; - int uart_clock; - struct uart_port port; - - /* Calculate the serial clock input frequency - * - * The uart clock is the cpu frequency (provided in the board info - * structure) divided by the external UART Divisor. - */ - uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1; - uart_clock = __res.bi_procfreq / uart_div; - - /* Setup serial port access */ - memset(&port, 0, sizeof(port)); -#if defined(CONFIG_UART0_TTYS0) - port.membase = (void*)UART0_IO_BASE; - port.irq = UART0_INT; -#else - port.membase = (void*)UART1_IO_BASE; - port.irq = UART1_INT; -#endif - port.uartclk = uart_clock; - port.regshift = 0; - port.iotype = UPIO_MEM; - port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - port.line = 0; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 0 failed\n"); - } -#if defined(CONFIG_UART0_TTYS0) - port.membase = (void*)UART1_IO_BASE; - port.irq = UART1_INT; -#else - port.membase = (void*)UART0_IO_BASE; - port.irq = UART0_INT; -#endif - port.line = 1; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 1 failed\n"); - } -} - -void __init -cpci405_setup_arch(void) -{ - ppc4xx_setup_arch(); - - ibm_ocp_set_emac(0, 0); - - cpci405_early_serial_map(); - -#ifdef CONFIG_GEN_RTC - TODC_INIT(TODC_TYPE_MK48T35, - cpci405_nvram, cpci405_nvram, cpci405_nvram, 8); -#endif -} - -void __init -bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) -{ -#ifdef CONFIG_PCI - unsigned int bar_response, bar; - - /* Disable region first */ - out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); - /* PLB starting addr, PCI: 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].la), 0x80000000); - /* PCI start addr, 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); - /* 512MB range of PLB to PCI */ - out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); - /* Enable no pre-fetch, enable region */ - out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - - (PPC405_PCI_UPPER_MEM - - PPC405_PCI_MEM_BASE)) | 0x01)); - - /* Disable region one */ - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[1].la), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->ptm1ms), 0x00000001); - - /* Disable region two */ - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[2].la), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->ptm2ms), 0x00000000); - out_le32((void *) &(pcip->ptm2la), 0x00000000); - - /* Zero config bars */ - for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { - early_write_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - 0x00000000); - early_read_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - &bar_response); - } -#endif -} - -void __init -cpci405_map_io(void) -{ - ppc4xx_map_io(); - -#ifdef CONFIG_GEN_RTC - cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE); -#endif -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = cpci405_setup_arch; - ppc_md.setup_io_mappings = cpci405_map_io; - -#ifdef CONFIG_GEN_RTC - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; -#endif -} diff --git a/arch/ppc/platforms/4xx/cpci405.h b/arch/ppc/platforms/4xx/cpci405.h deleted file mode 100644 index a6c0a138b0d7..000000000000 --- a/arch/ppc/platforms/4xx/cpci405.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * CPCI-405 board specific definitions - * - * Copyright 2001-2006 esd electronic system design - hannover germany - * - * Authors: Matthias Fuchs - * matthias.fuchs@esd-electronics.com - * Stefan Roese - * stefan.roese@esd-electronics.com - */ - -#ifdef __KERNEL__ -#ifndef __CPCI405_H__ -#define __CPCI405_H__ - -#include -#include - -/* Map for the NVRAM space */ -#define CPCI405_NVRAM_PADDR ((uint)0xf0200000) -#define CPCI405_NVRAM_SIZE ((uint)32*1024) - -#define BASE_BAUD 0 - -#define PPC4xx_MACHINE_NAME "esd CPCI-405" - -#endif /* __CPCI405_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c deleted file mode 100644 index 8027a36fc5bb..000000000000 --- a/arch/ppc/platforms/4xx/ebony.c +++ /dev/null @@ -1,334 +0,0 @@ -/* - * Ebony board specific routines - * - * Matt Porter - * Copyright 2002-2005 MontaVista Software Inc. - * - * Eugene Surovegin or - * Copyright (c) 2003-2005 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -extern bd_t __res; - -static struct ibm44x_clocks clocks __initdata; - -/* - * Ebony external IRQ triggering/polarity settings - */ -unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */ -}; - -static void __init -ebony_calibrate_decr(void) -{ - unsigned int freq; - - /* - * Determine system clock speed - * - * If we are on Rev. B silicon, then use - * default external system clock. If we are - * on Rev. C silicon then errata forces us to - * use the internal clock. - */ - if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0) - freq = EBONY_440GP_RB_SYSCLK; - else - freq = EBONY_440GP_RC_SYSCLK; - - ibm44x_calibrate_decr(freq); -} - -static int -ebony_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: IBM\n"); - seq_printf(m, "machine\t\t: Ebony\n"); - - return 0; -} - -static inline int -ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */ - { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */ - { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */ - { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */ - }; - - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -#define PCIX_WRITEL(value, offset) \ - (writel(value, pcix_reg_base + offset)) - -/* - * FIXME: This is only here to "make it work". This will move - * to a ibm_pcix.c which will contain a generic IBM PCIX bridge - * configuration library. -Matt - */ -static void __init -ebony_setup_pcix(void) -{ - void __iomem *pcix_reg_base; - - pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); - - /* Disable all windows */ - PCIX_WRITEL(0, PCIX0_POM0SA); - PCIX_WRITEL(0, PCIX0_POM1SA); - PCIX_WRITEL(0, PCIX0_POM2SA); - PCIX_WRITEL(0, PCIX0_PIM0SA); - PCIX_WRITEL(0, PCIX0_PIM1SA); - PCIX_WRITEL(0, PCIX0_PIM2SA); - - /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ - PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); - PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); - PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); - PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); - PCIX_WRITEL(0x80000001, PCIX0_POM0SA); - - /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ - PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); - PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); - PCIX_WRITEL(0x80000007, PCIX0_PIM0SA); - - eieio(); -} - -static void __init -ebony_setup_hose(void) -{ - struct pci_controller *hose; - - /* Configure windows on the PCI-X host bridge */ - ebony_setup_pcix(); - - hose = pcibios_alloc_controller(); - - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET; - - pci_init_resource(&hose->io_resource, - EBONY_PCI_LOWER_IO, - EBONY_PCI_UPPER_IO, - IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource(&hose->mem_resources[0], - EBONY_PCI_LOWER_MEM, - EBONY_PCI_UPPER_MEM, - IORESOURCE_MEM, - "PCI host bridge"); - - hose->io_space.start = EBONY_PCI_LOWER_IO; - hose->io_space.end = EBONY_PCI_UPPER_IO; - hose->mem_space.start = EBONY_PCI_LOWER_MEM; - hose->mem_space.end = EBONY_PCI_UPPER_MEM; - hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE); - isa_io_base = (unsigned long)hose->io_base_virt; - - setup_indirect_pci(hose, - EBONY_PCI_CFGA_PLB32, - EBONY_PCI_CFGD_PLB32); - hose->set_cfg_type = 1; - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = ebony_map_irq; -} - -TODC_ALLOC(); - -static void __init -ebony_early_serial_map(void) -{ - struct uart_port port; - - /* Setup ioremapped serial port access */ - memset(&port, 0, sizeof(port)); - port.membase = ioremap64(PPC440GP_UART0_ADDR, 8); - port.irq = 0; - port.uartclk = clocks.uart0; - port.regshift = 0; - port.iotype = UPIO_MEM; - port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - port.line = 0; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 0 failed\n"); - } - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Configure debug serial access */ - gen550_init(0, &port); - - /* Purge TLB entry added in head_44x.S for early serial access */ - _tlbie(UART0_IO_BASE, 0); -#endif - - port.membase = ioremap64(PPC440GP_UART1_ADDR, 8); - port.irq = 1; - port.uartclk = clocks.uart1; - port.line = 1; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 1 failed\n"); - } - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Configure debug serial access */ - gen550_init(1, &port); -#endif -} - -static void __init -ebony_setup_arch(void) -{ - struct ocp_def *def; - struct ocp_func_emac_data *emacdata; - - /* Set mac_addr for each EMAC */ - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); - emacdata = def->additions; - emacdata->phy_map = 0x00000001; /* Skip 0x00 */ - emacdata->phy_mode = PHY_MODE_RMII; - memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); - - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1); - emacdata = def->additions; - emacdata->phy_map = 0x00000001; /* Skip 0x00 */ - emacdata->phy_mode = PHY_MODE_RMII; - memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); - - /* - * Determine various clocks. - * To be completely correct we should get SysClk - * from FPGA, because it can be changed by on-board switches - * --ebs - */ - ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200); - ocp_sys_info.opb_bus_freq = clocks.opb; - - /* Setup TODC access */ - TODC_INIT(TODC_TYPE_DS1743, - 0, - 0, - ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE), - 8); - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - - /* Setup PCI host bridge */ - ebony_setup_hose(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_HDA1; -#endif - - ebony_early_serial_map(); - - /* Identify the system */ - printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n"); -} - -void __init platform_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, unsigned long r7) -{ - ibm44x_platform_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = ebony_setup_arch; - ppc_md.show_cpuinfo = ebony_show_cpuinfo; - ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ - - ppc_md.calibrate_decr = ebony_calibrate_decr; - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; -#ifdef CONFIG_KGDB - ppc_md.early_serial_map = ebony_early_serial_map; -#endif -} - diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h deleted file mode 100644 index f40e33d39d76..000000000000 --- a/arch/ppc/platforms/4xx/ebony.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Ebony board definitions - * - * Matt Porter - * - * Copyright 2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_EBONY_H__ -#define __ASM_EBONY_H__ - -#include - -/* F/W TLB mapping used in bootloader glue to reset EMAC */ -#define PPC44x_EMAC0_MR0 0xE0000800 - -/* Where to find the MAC info */ -#define OPENBIOS_MAC_BASE 0xfffffe0c -#define OPENBIOS_MAC_OFFSET 0x0c - -/* Default clock rates for Rev. B and Rev. C silicon */ -#define EBONY_440GP_RB_SYSCLK 33000000 -#define EBONY_440GP_RC_SYSCLK 400000000 - -/* RTC/NVRAM location */ -#define EBONY_RTC_ADDR 0x0000000148000000ULL -#define EBONY_RTC_SIZE 0x2000 - -/* Flash */ -#define EBONY_FPGA_ADDR 0x0000000148300000ULL -#define EBONY_BOOT_SMALL_FLASH(x) (x & 0x20) -#define EBONY_ONBRD_FLASH_EN(x) (x & 0x02) -#define EBONY_FLASH_SEL(x) (x & 0x01) -#define EBONY_SMALL_FLASH_LOW1 0x00000001ff800000ULL -#define EBONY_SMALL_FLASH_LOW2 0x00000001ff880000ULL -#define EBONY_SMALL_FLASH_HIGH1 0x00000001fff00000ULL -#define EBONY_SMALL_FLASH_HIGH2 0x00000001fff80000ULL -#define EBONY_SMALL_FLASH_SIZE 0x80000 -#define EBONY_LARGE_FLASH_LOW 0x00000001ff800000ULL -#define EBONY_LARGE_FLASH_HIGH 0x00000001ffc00000ULL -#define EBONY_LARGE_FLASH_SIZE 0x400000 - -#define EBONY_SMALL_FLASH_BASE 0x00000001fff80000ULL -#define EBONY_LARGE_FLASH_BASE 0x00000001ff800000ULL - -/* - * Serial port defines - */ - -#if defined(__BOOTER__) -/* OpenBIOS defined UART mappings, used by bootloader shim */ -#define UART0_IO_BASE 0xE0000200 -#define UART1_IO_BASE 0xE0000300 -#else -/* head_44x.S created UART mapping, used before early_serial_setup. - * We cannot use default OpenBIOS UART mappings because they - * don't work for configurations with more than 512M RAM. --ebs - */ -#define UART0_IO_BASE 0xF0000200 -#define UART1_IO_BASE 0xF0000300 -#endif - -/* external Epson SG-615P */ -#define BASE_BAUD 691200 - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (void*)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) - -/* PCI support */ -#define EBONY_PCI_LOWER_IO 0x00000000 -#define EBONY_PCI_UPPER_IO 0x0000ffff -#define EBONY_PCI_LOWER_MEM 0x80002000 -#define EBONY_PCI_UPPER_MEM 0xffffefff - -#define EBONY_PCI_CFGREGS_BASE 0x000000020ec00000 -#define EBONY_PCI_CFGA_PLB32 0x0ec00000 -#define EBONY_PCI_CFGD_PLB32 0x0ec00004 - -#define EBONY_PCI_IO_BASE 0x0000000208000000ULL -#define EBONY_PCI_IO_SIZE 0x00010000 -#define EBONY_PCI_MEM_OFFSET 0x00000000 - -#endif /* __ASM_EBONY_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ep405.c b/arch/ppc/platforms/4xx/ep405.c deleted file mode 100644 index 5aa295022804..000000000000 --- a/arch/ppc/platforms/4xx/ep405.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Embedded Planet 405GP board - * http://www.embeddedplanet.com - * - * Author: Matthew Locke - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -u8 *ep405_bcsr; -u8 *ep405_nvram; - -static struct { - u8 cpld_xirq_select; - int pci_idsel; - int irq; -} ep405_devtable[] = { -#ifdef CONFIG_EP405PC - {0x07, 0x0E, 25}, /* EP405PC: USB */ -#endif -}; - -int __init -ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - int i; - - /* AFAICT this is only called a few times during PCI setup, so - performance is not critical */ - for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) { - if (idsel == ep405_devtable[i].pci_idsel) - return ep405_devtable[i].irq; - } - return -1; -}; - -void __init -ep405_setup_arch(void) -{ - ppc4xx_setup_arch(); - - ibm_ocp_set_emac(0, 0); - - if (__res.bi_nvramsize == 512*1024) { - /* FIXME: we should properly handle NVRTCs of different sizes */ - TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8); - } -} - -void __init -bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) -{ -#ifdef CONFIG_PCI - unsigned int bar_response, bar; - /* - * Expected PCI mapping: - * - * PLB addr PCI memory addr - * --------------------- --------------------- - * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff - * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff - * - * PLB addr PCI io addr - * --------------------- --------------------- - * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 - * - */ - - /* Disable region zero first */ - out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); - /* PLB starting addr, PCI: 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].la), 0x80000000); - /* PCI start addr, 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); - /* 512MB range of PLB to PCI */ - out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); - /* Enable no pre-fetch, enable region */ - out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - - (PPC405_PCI_UPPER_MEM - - PPC405_PCI_MEM_BASE)) | 0x01)); - - /* Disable region one */ - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[1].la), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->ptm1ms), 0x00000000); - - /* Disable region two */ - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[2].la), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->ptm2ms), 0x00000000); - - /* Configure PTM (PCI->PLB) region 1 */ - out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */ - /* Disable PTM region 2 */ - out_le32((void *) &(pcip->ptm2ms), 0x00000000); - - /* Zero config bars */ - for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { - early_write_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - 0x00000000); - early_read_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - &bar_response); - DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", - hose->first_busno, PCI_SLOT(hose->first_busno), - PCI_FUNC(hose->first_busno), bar, bar_response); - } - /* end workaround */ -#endif -} - -void __init -ep405_map_io(void) -{ - bd_t *bip = &__res; - - ppc4xx_map_io(); - - ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE); - - if (bip->bi_nvramsize > 0) { - ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize); - } -} - -void __init -ep405_init_IRQ(void) -{ - int i; - - ppc4xx_init_IRQ(); - - /* Workaround for a bug in the firmware it incorrectly sets - the IRQ polarities for XIRQ0 and XIRQ1 */ - mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */ - mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */ - - /* Activate the XIRQs from the CPLD */ - writeb(0xf0, ep405_bcsr+10); - - /* Set up IRQ routing */ - for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) { - if ( (ep405_devtable[i].irq >= 25) - && (ep405_devtable[i].irq) <= 31) { - writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5); - writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6); - } - } -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = ep405_setup_arch; - ppc_md.setup_io_mappings = ep405_map_io; - ppc_md.init_IRQ = ep405_init_IRQ; - - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; - - if (__res.bi_nvramsize == 512*1024) { - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - } else { - printk("EP405: NVRTC size is not 512k (not a DS1557). Not sure what to do with it\n"); - } -} diff --git a/arch/ppc/platforms/4xx/ep405.h b/arch/ppc/platforms/4xx/ep405.h deleted file mode 100644 index 9814fc431725..000000000000 --- a/arch/ppc/platforms/4xx/ep405.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Embedded Planet 405GP board - * http://www.embeddedplanet.com - * - * Author: Matthew Locke - * - * 2000 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_EP405_H__ -#define __ASM_EP405_H__ - -/* We have a 405GP core */ -#include - -#ifndef __ASSEMBLY__ - -#include - -typedef struct board_info { - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ - unsigned int bi_nvramsize; /* Size of the NVRAM/RTC */ -} bd_t; - -/* Some 4xx parts use a different timebase frequency from the internal clock. -*/ -#define bi_tbfreq bi_intfreq - -extern u8 *ep405_bcsr; -extern u8 *ep405_nvram; - -/* Map for the BCSR and NVRAM space */ -#define EP405_BCSR_PADDR ((uint)0xf4000000) -#define EP405_BCSR_SIZE ((uint)16) -#define EP405_NVRAM_PADDR ((uint)0xf4200000) - -/* serial defines */ -#define BASE_BAUD 399193 - -#define PPC4xx_MACHINE_NAME "Embedded Planet 405GP" - -#endif /* !__ASSEMBLY__ */ -#endif /* __ASM_EP405_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c deleted file mode 100644 index fb3630a1608d..000000000000 --- a/arch/ppc/platforms/4xx/ibm405ep.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Support for IBM PPC 405EP processors. - * - * Author: SAW (IBM), derived from ibmnp405l.c. - * Maintained by MontaVista Software - * - * 2003 (c) MontaVista Softare Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -static struct ocp_func_mal_data ibm405ep_mal0_def = { - .num_tx_chans = 4, /* Number of TX channels */ - .num_rx_chans = 2, /* Number of RX channels */ - .txeob_irq = 11, /* TX End Of Buffer IRQ */ - .rxeob_irq = 12, /* RX End Of Buffer IRQ */ - .txde_irq = 13, /* TX Descriptor Error IRQ */ - .rxde_irq = 14, /* RX Descriptor Error IRQ */ - .serr_irq = 10, /* MAL System Error IRQ */ - .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ -}; -OCP_SYSFS_MAL_DATA() - -static struct ocp_func_emac_data ibm405ep_emac0_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = -1, /* ZMII device index */ - .zmii_mux = 0, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 0, /* MAL rx channel number */ - .mal_tx_chan = 0, /* MAL tx channel number */ - .wol_irq = 9, /* WOL interrupt number */ - .mdio_idx = 0, /* MDIO via EMAC0 */ - .tah_idx = -1, /* No TAH */ -}; - -static struct ocp_func_emac_data ibm405ep_emac1_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = -1, /* ZMII device index */ - .zmii_mux = 0, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 1, /* MAL rx channel number */ - .mal_tx_chan = 2, /* MAL tx channel number */ - .wol_irq = 9, /* WOL interrupt number */ - .mdio_idx = 0, /* MDIO via EMAC0 */ - .tah_idx = -1, /* No TAH */ -}; -OCP_SYSFS_EMAC_DATA() - -static struct ocp_func_iic_data ibm405ep_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_OPB, - .index = 0, - .paddr = 0xEF600000, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = UART0_IO_BASE, - .irq = UART0_INT, - .pm = IBM_CPM_UART0 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = UART1_IO_BASE, - .irq = UART1_INT, - .pm = IBM_CPM_UART1 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .paddr = 0xEF600500, - .irq = 2, - .pm = IBM_CPM_IIC0, - .additions = &ibm405ep_iic0_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .paddr = 0xEF600700, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_MAL, - .paddr = OCP_PADDR_NA, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - .additions = &ibm405ep_mal0_def, - .show = &ocp_show_mal_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 0, - .paddr = EMAC0_BASE, - .irq = 15, - .pm = OCP_CPM_NA, - .additions = &ibm405ep_emac0_def, - .show = &ocp_show_emac_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 1, - .paddr = 0xEF600900, - .irq = 17, - .pm = OCP_CPM_NA, - .additions = &ibm405ep_emac1_def, - .show = &ocp_show_emac_data - }, - { .vendor = OCP_VENDOR_INVALID - } -}; - -/* Polarity and triggering settings for internal interrupt sources */ -struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { - { .polarity = 0xffff7f80, - .triggering = 0x00000000, - .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */ - } -}; diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h deleted file mode 100644 index 3ef20a547080..000000000000 --- a/arch/ppc/platforms/4xx/ibm405ep.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * IBM PPC 405EP processor defines. - * - * Author: SAW (IBM), derived from ibm405gp.h. - * Maintained by MontaVista Software - * - * 2003 (c) MontaVista Softare Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM405EP_H__ -#define __ASM_IBM405EP_H__ - - -/* ibm405.h at bottom of this file */ - -/* PCI - * PCI Bridge config reg definitions - * see 17-19 of manual - */ - -#define PPC405_PCI_CONFIG_ADDR 0xeec00000 -#define PPC405_PCI_CONFIG_DATA 0xeec00004 - -#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */ - /* setbat */ -#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */ -#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */ -#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */ - -#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */ -#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */ -#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */ -#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */ - -#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE - -#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE) -#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR -#define PPC4xx_PCI_IO_SIZE ((uint)64*1024) -#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR) -#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR -#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) -#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000) -#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR -#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) -#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000) -#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR -#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) - -/* serial port defines */ -#define RS_TABLE_SIZE 2 - -#define UART0_INT 0 -#define UART1_INT 1 - -#define PCIL0_BASE 0xEF400000 -#define UART0_IO_BASE 0xEF600300 -#define UART1_IO_BASE 0xEF600400 -#define EMAC0_BASE 0xEF600800 - -#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i] - -#if defined(CONFIG_UART0_TTYS0) -#define ACTING_UART0_IO_BASE UART0_IO_BASE -#define ACTING_UART1_IO_BASE UART1_IO_BASE -#define ACTING_UART0_INT UART0_INT -#define ACTING_UART1_INT UART1_INT -#else -#define ACTING_UART0_IO_BASE UART1_IO_BASE -#define ACTING_UART1_IO_BASE UART0_IO_BASE -#define ACTING_UART0_INT UART1_INT -#define ACTING_UART1_INT UART0_INT -#endif - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, ACTING_UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (u8 *)ACTING_UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#define SERIAL_DEBUG_IO_BASE ACTING_UART0_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) - -/* DCR defines */ -#define DCRN_CPMSR_BASE 0x0BA -#define DCRN_CPMFR_BASE 0x0B9 - -#define DCRN_CPC0_PLLMR0_BASE 0x0F0 -#define DCRN_CPC0_BOOT_BASE 0x0F1 -#define DCRN_CPC0_CR1_BASE 0x0F2 -#define DCRN_CPC0_EPRCSR_BASE 0x0F3 -#define DCRN_CPC0_PLLMR1_BASE 0x0F4 -#define DCRN_CPC0_UCR_BASE 0x0F5 -#define DCRN_CPC0_UCR_U0DIV 0x07F -#define DCRN_CPC0_SRR_BASE 0x0F6 -#define DCRN_CPC0_JTAGID_BASE 0x0F7 -#define DCRN_CPC0_SPARE_BASE 0x0F8 -#define DCRN_CPC0_PCI_BASE 0x0F9 - - -#define IBM_CPM_GPT 0x80000000 /* GPT interface */ -#define IBM_CPM_PCI 0x40000000 /* PCI bridge */ -#define IBM_CPM_UIC 0x00010000 /* Universal Int Controller */ -#define IBM_CPM_CPU 0x00008000 /* processor core */ -#define IBM_CPM_EBC 0x00002000 /* EBC controller */ -#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM memory controller */ -#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO */ -#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */ -#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */ -#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */ -#define IBM_CPM_DMA 0x00000040 /* DMA controller */ -#define IBM_CPM_IIC0 0x00000010 /* IIC interface */ -#define IBM_CPM_UART1 0x00000002 /* serial port 0 */ -#define IBM_CPM_UART0 0x00000001 /* serial port 1 */ -#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \ - | IBM_CPM_OPB | IBM_CPM_EBC \ - | IBM_CPM_SDRAM0 | IBM_CPM_PLB \ - | IBM_CPM_UIC | IBM_CPM_TMRCLK) -#define DCRN_DMA0_BASE 0x100 -#define DCRN_DMA1_BASE 0x108 -#define DCRN_DMA2_BASE 0x110 -#define DCRN_DMA3_BASE 0x118 -#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ -#define DCRN_DMASR_BASE 0x120 -#define DCRN_EBC_BASE 0x012 -#define DCRN_DCP0_BASE 0x014 -#define DCRN_MAL_BASE 0x180 -#define DCRN_OCM0_BASE 0x018 -#define DCRN_PLB0_BASE 0x084 -#define DCRN_PLLMR_BASE 0x0B0 -#define DCRN_POB0_BASE 0x0A0 -#define DCRN_SDRAM0_BASE 0x010 -#define DCRN_UIC0_BASE 0x0C0 -#define UIC0 DCRN_UIC0_BASE - -#include - -#endif /* __ASM_IBM405EP_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibm405gp.c b/arch/ppc/platforms/4xx/ibm405gp.c deleted file mode 100644 index 2ac67a2f0ba6..000000000000 --- a/arch/ppc/platforms/4xx/ibm405gp.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * - * Copyright 2000-2001 MontaVista Software Inc. - * Original author: Armin Kuster akuster@mvista.com - * - * Module name: ibm405gp.c - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct ocp_func_emac_data ibm405gp_emac0_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = -1, /* ZMII device index */ - .zmii_mux = 0, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 0, /* MAL rx channel number */ - .mal_tx_chan = 0, /* MAL tx channel number */ - .wol_irq = 9, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; -OCP_SYSFS_EMAC_DATA() - -static struct ocp_func_mal_data ibm405gp_mal0_def = { - .num_tx_chans = 1, /* Number of TX channels */ - .num_rx_chans = 1, /* Number of RX channels */ - .txeob_irq = 11, /* TX End Of Buffer IRQ */ - .rxeob_irq = 12, /* RX End Of Buffer IRQ */ - .txde_irq = 13, /* TX Descriptor Error IRQ */ - .rxde_irq = 14, /* RX Descriptor Error IRQ */ - .serr_irq = 10, /* MAL System Error IRQ */ - .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ -}; -OCP_SYSFS_MAL_DATA() - -static struct ocp_func_iic_data ibm405gp_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_OPB, - .index = 0, - .paddr = 0xEF600000, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = UART0_IO_BASE, - .irq = UART0_INT, - .pm = IBM_CPM_UART0 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = UART1_IO_BASE, - .irq = UART1_INT, - .pm = IBM_CPM_UART1 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .paddr = 0xEF600500, - .irq = 2, - .pm = IBM_CPM_IIC0, - .additions = &ibm405gp_iic0_def, - .show = &ocp_show_iic_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .paddr = 0xEF600700, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_MAL, - .paddr = OCP_PADDR_NA, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - .additions = &ibm405gp_mal0_def, - .show = &ocp_show_mal_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 0, - .paddr = EMAC0_BASE, - .irq = 15, - .pm = IBM_CPM_EMAC0, - .additions = &ibm405gp_emac0_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_INVALID - } -}; - -/* Polarity and triggering settings for internal interrupt sources */ -struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { - { .polarity = 0xffffff80, - .triggering = 0x10000000, - .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */ - } -}; diff --git a/arch/ppc/platforms/4xx/ibm405gp.h b/arch/ppc/platforms/4xx/ibm405gp.h deleted file mode 100644 index 9f15e5518719..000000000000 --- a/arch/ppc/platforms/4xx/ibm405gp.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Author: Armin Kuster akuster@mvista.com - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM405GP_H__ -#define __ASM_IBM405GP_H__ - - -/* ibm405.h at bottom of this file */ - -/* PCI - * PCI Bridge config reg definitions - * see 17-19 of manual - */ - -#define PPC405_PCI_CONFIG_ADDR 0xeec00000 -#define PPC405_PCI_CONFIG_DATA 0xeec00004 - -#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */ - /* setbat */ -#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */ -#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */ -#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */ - -#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */ -#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */ -#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */ -#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */ - -#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE - -#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE) -#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR -#define PPC4xx_PCI_IO_SIZE ((uint)64*1024) -#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR) -#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR -#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) -#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000) -#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR -#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) -#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000) -#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR -#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) - -/* serial port defines */ -#define RS_TABLE_SIZE 2 - -#define UART0_INT 0 -#define UART1_INT 1 - -#define PCIL0_BASE 0xEF400000 -#define UART0_IO_BASE 0xEF600300 -#define UART1_IO_BASE 0xEF600400 -#define EMAC0_BASE 0xEF600800 - -#define BD_EMAC_ADDR(e,i) bi_enetaddr[i] - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (u8 *)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#if defined(CONFIG_UART0_TTYS0) -#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) -#endif - -#if defined(CONFIG_UART0_TTYS1) -#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(1) \ - STD_UART_OP(0) -#endif - -/* DCR defines */ -#define DCRN_CHCR_BASE 0x0B1 -#define DCRN_CHPSR_BASE 0x0B4 -#define DCRN_CPMSR_BASE 0x0B8 -#define DCRN_CPMFR_BASE 0x0BA - -#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */ -#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */ -#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */ -#define CHR1_CETE 0x00800000 /* CPU external timer enable */ - -#define DCRN_CHPSR_BASE 0x0B4 -#define PSR_PLL_FWD_MASK 0xC0000000 -#define PSR_PLL_FDBACK_MASK 0x30000000 -#define PSR_PLL_TUNING_MASK 0x0E000000 -#define PSR_PLB_CPU_MASK 0x01800000 -#define PSR_OPB_PLB_MASK 0x00600000 -#define PSR_PCI_PLB_MASK 0x00180000 -#define PSR_EB_PLB_MASK 0x00060000 -#define PSR_ROM_WIDTH_MASK 0x00018000 -#define PSR_ROM_LOC 0x00004000 -#define PSR_PCI_ASYNC_EN 0x00001000 -#define PSR_PCI_ARBIT_EN 0x00000400 - -#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ -#define IBM_CPM_PCI 0x40000000 /* PCI bridge */ -#define IBM_CPM_CPU 0x20000000 /* processor core */ -#define IBM_CPM_DMA 0x10000000 /* DMA controller */ -#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */ -#define IBM_CPM_DCP 0x04000000 /* CodePack */ -#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */ -#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */ -#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */ -#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */ -#define IBM_CPM_UART0 0x00200000 /* serial port 0 */ -#define IBM_CPM_UART1 0x00100000 /* serial port 1 */ -#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */ -#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */ -#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */ -#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \ - | IBM_CPM_OPB | IBM_CPM_EBC \ - | IBM_CPM_SDRAM0 | IBM_CPM_PLB \ - | IBM_CPM_UIC | IBM_CPM_TMRCLK) - -#define DCRN_DMA0_BASE 0x100 -#define DCRN_DMA1_BASE 0x108 -#define DCRN_DMA2_BASE 0x110 -#define DCRN_DMA3_BASE 0x118 -#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ -#define DCRN_DMASR_BASE 0x120 -#define DCRN_EBC_BASE 0x012 -#define DCRN_DCP0_BASE 0x014 -#define DCRN_MAL_BASE 0x180 -#define DCRN_OCM0_BASE 0x018 -#define DCRN_PLB0_BASE 0x084 -#define DCRN_PLLMR_BASE 0x0B0 -#define DCRN_POB0_BASE 0x0A0 -#define DCRN_SDRAM0_BASE 0x010 -#define DCRN_UIC0_BASE 0x0C0 -#define UIC0 DCRN_UIC0_BASE - -#include - -#endif /* __ASM_IBM405GP_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c deleted file mode 100644 index 9f4dacffdbb3..000000000000 --- a/arch/ppc/platforms/4xx/ibm405gpr.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct ocp_func_emac_data ibm405gpr_emac0_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = -1, /* ZMII device index */ - .zmii_mux = 0, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 0, /* MAL rx channel number */ - .mal_tx_chan = 0, /* MAL tx channel number */ - .wol_irq = 9, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; -OCP_SYSFS_EMAC_DATA() - -static struct ocp_func_mal_data ibm405gpr_mal0_def = { - .num_tx_chans = 1, /* Number of TX channels */ - .num_rx_chans = 1, /* Number of RX channels */ - .txeob_irq = 11, /* TX End Of Buffer IRQ */ - .rxeob_irq = 12, /* RX End Of Buffer IRQ */ - .txde_irq = 13, /* TX Descriptor Error IRQ */ - .rxde_irq = 14, /* RX Descriptor Error IRQ */ - .serr_irq = 10, /* MAL System Error IRQ */ - .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ -}; -OCP_SYSFS_MAL_DATA() - -static struct ocp_func_iic_data ibm405gpr_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; - -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_OPB, - .index = 0, - .paddr = 0xEF600000, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = UART0_IO_BASE, - .irq = UART0_INT, - .pm = IBM_CPM_UART0 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = UART1_IO_BASE, - .irq = UART1_INT, - .pm = IBM_CPM_UART1 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .paddr = 0xEF600500, - .irq = 2, - .pm = IBM_CPM_IIC0, - .additions = &ibm405gpr_iic0_def, - .show = &ocp_show_iic_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .paddr = 0xEF600700, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_MAL, - .paddr = OCP_PADDR_NA, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - .additions = &ibm405gpr_mal0_def, - .show = &ocp_show_mal_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 0, - .paddr = EMAC0_BASE, - .irq = 15, - .pm = IBM_CPM_EMAC0, - .additions = &ibm405gpr_emac0_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_INVALID - } -}; - -/* Polarity and triggering settings for internal interrupt sources */ -struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { - { .polarity = 0xffffe000, - .triggering = 0x10000000, - .ext_irq_mask = 0x00001fff, /* IRQ7 - IRQ12, IRQ0 - IRQ6 */ - } -}; diff --git a/arch/ppc/platforms/4xx/ibm405gpr.h b/arch/ppc/platforms/4xx/ibm405gpr.h deleted file mode 100644 index 9e01f1515de3..000000000000 --- a/arch/ppc/platforms/4xx/ibm405gpr.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM405GPR_H__ -#define __ASM_IBM405GPR_H__ - - -/* ibm405.h at bottom of this file */ - -/* PCI - * PCI Bridge config reg definitions - * see 17-19 of manual - */ - -#define PPC405_PCI_CONFIG_ADDR 0xeec00000 -#define PPC405_PCI_CONFIG_DATA 0xeec00004 - -#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */ - /* setbat */ -#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */ -#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */ -#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */ - -#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */ -#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */ -#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */ -#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */ - -#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE - -#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE) -#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR -#define PPC4xx_PCI_IO_SIZE ((uint)64*1024) -#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR) -#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR -#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) -#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000) -#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR -#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) -#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000) -#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR -#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) - -/* serial port defines */ -#define RS_TABLE_SIZE 2 - -#define UART0_INT 0 -#define UART1_INT 1 - -#define PCIL0_BASE 0xEF400000 -#define UART0_IO_BASE 0xEF600300 -#define UART1_IO_BASE 0xEF600400 -#define EMAC0_BASE 0xEF600800 - -#define BD_EMAC_ADDR(e,i) bi_enetaddr[i] - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (u8 *)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#if defined(CONFIG_UART0_TTYS0) -#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) -#endif - -#if defined(CONFIG_UART0_TTYS1) -#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(1) \ - STD_UART_OP(0) -#endif - -/* DCR defines */ -#define DCRN_CHCR_BASE 0x0B1 -#define DCRN_CHPSR_BASE 0x0B4 -#define DCRN_CPMSR_BASE 0x0B8 -#define DCRN_CPMFR_BASE 0x0BA - -#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */ -#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */ -#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */ -#define CHR1_CETE 0x00800000 /* CPU external timer enable */ - -#define DCRN_CHPSR_BASE 0x0B4 -#define PSR_PLL_FWD_MASK 0xC0000000 -#define PSR_PLL_FDBACK_MASK 0x30000000 -#define PSR_PLL_TUNING_MASK 0x0E000000 -#define PSR_PLB_CPU_MASK 0x01800000 -#define PSR_OPB_PLB_MASK 0x00600000 -#define PSR_PCI_PLB_MASK 0x00180000 -#define PSR_EB_PLB_MASK 0x00060000 -#define PSR_ROM_WIDTH_MASK 0x00018000 -#define PSR_ROM_LOC 0x00004000 -#define PSR_PCI_ASYNC_EN 0x00001000 -#define PSR_PCI_ARBIT_EN 0x00000400 - -#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ -#define IBM_CPM_PCI 0x40000000 /* PCI bridge */ -#define IBM_CPM_CPU 0x20000000 /* processor core */ -#define IBM_CPM_DMA 0x10000000 /* DMA controller */ -#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */ -#define IBM_CPM_DCP 0x04000000 /* CodePack */ -#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */ -#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */ -#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */ -#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */ -#define IBM_CPM_UART0 0x00200000 /* serial port 0 */ -#define IBM_CPM_UART1 0x00100000 /* serial port 1 */ -#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */ -#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */ -#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */ -#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \ - | IBM_CPM_OPB | IBM_CPM_EBC \ - | IBM_CPM_SDRAM0 | IBM_CPM_PLB \ - | IBM_CPM_UIC | IBM_CPM_TMRCLK) - -#define DCRN_DMA0_BASE 0x100 -#define DCRN_DMA1_BASE 0x108 -#define DCRN_DMA2_BASE 0x110 -#define DCRN_DMA3_BASE 0x118 -#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ -#define DCRN_DMASR_BASE 0x120 -#define DCRN_EBC_BASE 0x012 -#define DCRN_DCP0_BASE 0x014 -#define DCRN_MAL_BASE 0x180 -#define DCRN_OCM0_BASE 0x018 -#define DCRN_PLB0_BASE 0x084 -#define DCRN_PLLMR_BASE 0x0B0 -#define DCRN_POB0_BASE 0x0A0 -#define DCRN_SDRAM0_BASE 0x010 -#define DCRN_UIC0_BASE 0x0C0 -#define UIC0 DCRN_UIC0_BASE - -#include - -#endif /* __ASM_IBM405GPR_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c deleted file mode 100644 index 0de91532aabb..000000000000 --- a/arch/ppc/platforms/4xx/ibm440ep.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * PPC440EP I/O descriptions - * - * Wade Farnsworth - * Copyright 2004 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include -#include - -static struct ocp_func_emac_data ibm440ep_emac0_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 0, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 0, /* MAL rx channel number */ - .mal_tx_chan = 0, /* MAL tx channel number */ - .wol_irq = 61, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; - -static struct ocp_func_emac_data ibm440ep_emac1_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 1, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 1, /* MAL rx channel number */ - .mal_tx_chan = 2, /* MAL tx channel number */ - .wol_irq = 63, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; -OCP_SYSFS_EMAC_DATA() - -static struct ocp_func_mal_data ibm440ep_mal0_def = { - .num_tx_chans = 4, /* Number of TX channels */ - .num_rx_chans = 2, /* Number of RX channels */ - .txeob_irq = 10, /* TX End Of Buffer IRQ */ - .rxeob_irq = 11, /* RX End Of Buffer IRQ */ - .txde_irq = 33, /* TX Descriptor Error IRQ */ - .rxde_irq = 34, /* RX Descriptor Error IRQ */ - .serr_irq = 32, /* MAL System Error IRQ */ - .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ -}; -OCP_SYSFS_MAL_DATA() - -static struct ocp_func_iic_data ibm440ep_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; - -static struct ocp_func_iic_data ibm440ep_iic1_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_OPB, - .index = 0, - .paddr = 0x0EF600000ULL, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = PPC440EP_UART0_ADDR, - .irq = UART0_INT, - .pm = IBM_CPM_UART0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = PPC440EP_UART1_ADDR, - .irq = UART1_INT, - .pm = IBM_CPM_UART1, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 2, - .paddr = PPC440EP_UART2_ADDR, - .irq = UART2_INT, - .pm = IBM_CPM_UART2, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 3, - .paddr = PPC440EP_UART3_ADDR, - .irq = UART3_INT, - .pm = IBM_CPM_UART3, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 0, - .paddr = 0x0EF600700ULL, - .irq = 2, - .pm = IBM_CPM_IIC0, - .additions = &ibm440ep_iic0_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 1, - .paddr = 0x0EF600800ULL, - .irq = 7, - .pm = IBM_CPM_IIC1, - .additions = &ibm440ep_iic1_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .index = 0, - .paddr = 0x0EF600B00ULL, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .index = 1, - .paddr = 0x0EF600C00ULL, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_MAL, - .paddr = OCP_PADDR_NA, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - .additions = &ibm440ep_mal0_def, - .show = &ocp_show_mal_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 0, - .paddr = 0x0EF600E00ULL, - .irq = 60, - .pm = OCP_CPM_NA, - .additions = &ibm440ep_emac0_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 1, - .paddr = 0x0EF600F00ULL, - .irq = 62, - .pm = OCP_CPM_NA, - .additions = &ibm440ep_emac1_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_ZMII, - .paddr = 0x0EF600D00ULL, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_INVALID - } -}; - -/* Polarity and triggering settings for internal interrupt sources */ -struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { - { .polarity = 0xffbffe03, - .triggering = 0x00000000, - .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */ - }, - { .polarity = 0xffffc6af, - .triggering = 0x06000140, - .ext_irq_mask = 0x00003800, /* IRQ7 - IRQ9 */ - }, -}; - -static struct resource usb_gadget_resources[] = { - [0] = { - .start = 0x050000100ULL, - .end = 0x05000017FULL, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 55, - .end = 55, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 dma_mask = 0xffffffffULL; - -static struct platform_device usb_gadget_device = { - .name = "musbhsfc", - .id = 0, - .num_resources = ARRAY_SIZE(usb_gadget_resources), - .resource = usb_gadget_resources, - .dev = { - .dma_mask = &dma_mask, - .coherent_dma_mask = 0xffffffffULL, - } -}; - -static struct platform_device *ibm440ep_devs[] __initdata = { - &usb_gadget_device, -}; - -static int __init -ibm440ep_platform_add_devices(void) -{ - return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs)); -} -arch_initcall(ibm440ep_platform_add_devices); - diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h deleted file mode 100644 index d92572727d20..000000000000 --- a/arch/ppc/platforms/4xx/ibm440ep.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * PPC440EP definitions - * - * Wade Farnsworth - * - * Copyright 2002 Roland Dreier - * Copyright 2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __PPC_PLATFORMS_IBM440EP_H -#define __PPC_PLATFORMS_IBM440EP_H - -#include - -/* UART */ -#define PPC440EP_UART0_ADDR 0x0EF600300 -#define PPC440EP_UART1_ADDR 0x0EF600400 -#define PPC440EP_UART2_ADDR 0x0EF600500 -#define PPC440EP_UART3_ADDR 0x0EF600600 -#define UART0_INT 0 -#define UART1_INT 1 -#define UART2_INT 3 -#define UART3_INT 4 - -/* Clock and Power Management */ -#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ -#define IBM_CPM_IIC1 0x40000000 /* IIC interface */ -#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ -#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */ -#define IBM_CPM_FPU 0x04000000 /* floating point unit */ -#define IBM_CPM_CPU 0x02000000 /* processor core */ -#define IBM_CPM_DMA 0x01000000 /* DMA controller */ -#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ -#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ -#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */ -#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ -#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ -#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */ -#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */ -#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */ -#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */ -#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ -#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ -#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ -#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ -#define IBM_CPM_UART0 0x00000200 /* serial port 0 */ -#define IBM_CPM_UART1 0x00000100 /* serial port 1 */ -#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ -#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ -#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */ -#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */ -#define IBM_CPM_UART2 0x00000008 /* serial port 2 */ -#define IBM_CPM_UART3 0x00000004 /* serial port 3 */ -#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */ -#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */ - -#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \ - | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \ - | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \ - | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \ - | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \ - | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1) - - -#endif /* __PPC_PLATFORMS_IBM440EP_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c deleted file mode 100644 index b67a72e5c6fe..000000000000 --- a/arch/ppc/platforms/4xx/ibm440gp.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * PPC440GP I/O descriptions - * - * Matt Porter - * Copyright 2002-2004 MontaVista Software Inc. - * - * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include - -static struct ocp_func_emac_data ibm440gp_emac0_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 0, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 0, /* MAL rx channel number */ - .mal_tx_chan = 0, /* MAL tx channel number */ - .wol_irq = 61, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; - -static struct ocp_func_emac_data ibm440gp_emac1_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 1, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 1, /* MAL rx channel number */ - .mal_tx_chan = 2, /* MAL tx channel number */ - .wol_irq = 63, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; -OCP_SYSFS_EMAC_DATA() - -static struct ocp_func_mal_data ibm440gp_mal0_def = { - .num_tx_chans = 4, /* Number of TX channels */ - .num_rx_chans = 2, /* Number of RX channels */ - .txeob_irq = 10, /* TX End Of Buffer IRQ */ - .rxeob_irq = 11, /* RX End Of Buffer IRQ */ - .txde_irq = 33, /* TX Descriptor Error IRQ */ - .rxde_irq = 34, /* RX Descriptor Error IRQ */ - .serr_irq = 32, /* MAL System Error IRQ */ - .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ -}; -OCP_SYSFS_MAL_DATA() - -static struct ocp_func_iic_data ibm440gp_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; - -static struct ocp_func_iic_data ibm440gp_iic1_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_OPB, - .index = 0, - .paddr = 0x0000000140000000ULL, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = PPC440GP_UART0_ADDR, - .irq = UART0_INT, - .pm = IBM_CPM_UART0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = PPC440GP_UART1_ADDR, - .irq = UART1_INT, - .pm = IBM_CPM_UART1, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 0, - .paddr = 0x0000000140000400ULL, - .irq = 2, - .pm = IBM_CPM_IIC0, - .additions = &ibm440gp_iic0_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 1, - .paddr = 0x0000000140000500ULL, - .irq = 3, - .pm = IBM_CPM_IIC1, - .additions = &ibm440gp_iic1_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .index = 0, - .paddr = 0x0000000140000700ULL, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_MAL, - .paddr = OCP_PADDR_NA, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - .additions = &ibm440gp_mal0_def, - .show = &ocp_show_mal_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 0, - .paddr = 0x0000000140000800ULL, - .irq = 60, - .pm = OCP_CPM_NA, - .additions = &ibm440gp_emac0_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 1, - .paddr = 0x0000000140000900ULL, - .irq = 62, - .pm = OCP_CPM_NA, - .additions = &ibm440gp_emac1_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_ZMII, - .paddr = 0x0000000140000780ULL, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_INVALID - } -}; - -/* Polarity and triggering settings for internal interrupt sources */ -struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { - { .polarity = 0xfffffe03, - .triggering = 0x01c00000, - .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */ - }, - { .polarity = 0xffffc0ff, - .triggering = 0x00ff8000, - .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */ - }, -}; diff --git a/arch/ppc/platforms/4xx/ibm440gp.h b/arch/ppc/platforms/4xx/ibm440gp.h deleted file mode 100644 index 391c90e1f5ea..000000000000 --- a/arch/ppc/platforms/4xx/ibm440gp.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * PPC440GP definitions - * - * Roland Dreier - * - * Copyright 2002 Roland Dreier - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This file contains code that was originally in the files ibm44x.h - * and ebony.h, which were written by Matt Porter of MontaVista Software Inc. - */ - -#ifdef __KERNEL__ -#ifndef __PPC_PLATFORMS_IBM440GP_H -#define __PPC_PLATFORMS_IBM440GP_H - - -/* UART */ -#define PPC440GP_UART0_ADDR 0x0000000140000200ULL -#define PPC440GP_UART1_ADDR 0x0000000140000300ULL -#define UART0_INT 0 -#define UART1_INT 1 - -/* Clock and Power Management */ -#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ -#define IBM_CPM_IIC1 0x40000000 /* IIC interface */ -#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ -#define IBM_CPM_CPU 0x02000000 /* processor core */ -#define IBM_CPM_DMA 0x01000000 /* DMA controller */ -#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ -#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ -#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ -#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ -#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ -#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ -#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ -#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ -#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ -#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ -#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ -#define IBM_CPM_UART0 0x00000200 /* serial port 0 */ -#define IBM_CPM_UART1 0x00000100 /* serial port 1 */ -#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ -#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ - -#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ - | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ - | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ - | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI) -/* - * Serial port defines - */ -#define RS_TABLE_SIZE 2 - -#include -#include - -#endif /* __PPC_PLATFORMS_IBM440GP_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c deleted file mode 100644 index 685abffcb6ce..000000000000 --- a/arch/ppc/platforms/4xx/ibm440gx.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * PPC440GX I/O descriptions - * - * Matt Porter - * Copyright 2002-2004 MontaVista Software Inc. - * - * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include - -static struct ocp_func_emac_data ibm440gx_emac0_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 0, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 0, /* MAL rx channel number */ - .mal_tx_chan = 0, /* MAL tx channel number */ - .wol_irq = 61, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; - -static struct ocp_func_emac_data ibm440gx_emac1_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 1, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 1, /* MAL rx channel number */ - .mal_tx_chan = 1, /* MAL tx channel number */ - .wol_irq = 63, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; - -static struct ocp_func_emac_data ibm440gx_emac2_def = { - .rgmii_idx = 0, /* RGMII device index */ - .rgmii_mux = 0, /* RGMII input of this EMAC */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 2, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 2, /* MAL rx channel number */ - .mal_tx_chan = 2, /* MAL tx channel number */ - .wol_irq = 65, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = 0, /* TAH device index */ -}; - -static struct ocp_func_emac_data ibm440gx_emac3_def = { - .rgmii_idx = 0, /* RGMII device index */ - .rgmii_mux = 1, /* RGMII input of this EMAC */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 3, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 3, /* MAL rx channel number */ - .mal_tx_chan = 3, /* MAL tx channel number */ - .wol_irq = 67, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = 1, /* TAH device index */ -}; -OCP_SYSFS_EMAC_DATA() - -static struct ocp_func_mal_data ibm440gx_mal0_def = { - .num_tx_chans = 4, /* Number of TX channels */ - .num_rx_chans = 4, /* Number of RX channels */ - .txeob_irq = 10, /* TX End Of Buffer IRQ */ - .rxeob_irq = 11, /* RX End Of Buffer IRQ */ - .txde_irq = 33, /* TX Descriptor Error IRQ */ - .rxde_irq = 34, /* RX Descriptor Error IRQ */ - .serr_irq = 32, /* MAL System Error IRQ */ - .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ -}; -OCP_SYSFS_MAL_DATA() - -static struct ocp_func_iic_data ibm440gx_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; - -static struct ocp_func_iic_data ibm440gx_iic1_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_OPB, - .index = 0, - .paddr = 0x0000000140000000ULL, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = PPC440GX_UART0_ADDR, - .irq = UART0_INT, - .pm = IBM_CPM_UART0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = PPC440GX_UART1_ADDR, - .irq = UART1_INT, - .pm = IBM_CPM_UART1, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 0, - .paddr = 0x0000000140000400ULL, - .irq = 2, - .pm = IBM_CPM_IIC0, - .additions = &ibm440gx_iic0_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 1, - .paddr = 0x0000000140000500ULL, - .irq = 3, - .pm = IBM_CPM_IIC1, - .additions = &ibm440gx_iic1_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .index = 0, - .paddr = 0x0000000140000700ULL, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_MAL, - .paddr = OCP_PADDR_NA, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - .additions = &ibm440gx_mal0_def, - .show = &ocp_show_mal_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 0, - .paddr = 0x0000000140000800ULL, - .irq = 60, - .pm = OCP_CPM_NA, - .additions = &ibm440gx_emac0_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 1, - .paddr = 0x0000000140000900ULL, - .irq = 62, - .pm = OCP_CPM_NA, - .additions = &ibm440gx_emac1_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 2, - .paddr = 0x0000000140000C00ULL, - .irq = 64, - .pm = OCP_CPM_NA, - .additions = &ibm440gx_emac2_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 3, - .paddr = 0x0000000140000E00ULL, - .irq = 66, - .pm = OCP_CPM_NA, - .additions = &ibm440gx_emac3_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_RGMII, - .paddr = 0x0000000140000790ULL, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_ZMII, - .paddr = 0x0000000140000780ULL, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_TAH, - .index = 0, - .paddr = 0x0000000140000b50ULL, - .irq = 68, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_TAH, - .index = 1, - .paddr = 0x0000000140000d50ULL, - .irq = 69, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_INVALID - } -}; - -/* Polarity and triggering settings for internal interrupt sources */ -struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { - { .polarity = 0xfffffe03, - .triggering = 0x01c00000, - .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */ - }, - { .polarity = 0xffffc0ff, - .triggering = 0x00ff8000, - .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */ - }, - { .polarity = 0xffff83ff, - .triggering = 0x000f83c0, - .ext_irq_mask = 0x00007c00, /* IRQ13 - IRQ17 */ - }, -}; diff --git a/arch/ppc/platforms/4xx/ibm440gx.h b/arch/ppc/platforms/4xx/ibm440gx.h deleted file mode 100644 index 599c4289b9c2..000000000000 --- a/arch/ppc/platforms/4xx/ibm440gx.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * PPC440GX definitions - * - * Matt Porter - * - * Copyright 2002 Roland Dreier - * Copyright 2003 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __PPC_PLATFORMS_IBM440GX_H -#define __PPC_PLATFORMS_IBM440GX_H - - -#include - -/* UART */ -#define PPC440GX_UART0_ADDR 0x0000000140000200ULL -#define PPC440GX_UART1_ADDR 0x0000000140000300ULL -#define UART0_INT 0 -#define UART1_INT 1 - -/* Clock and Power Management */ -#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ -#define IBM_CPM_IIC1 0x40000000 /* IIC interface */ -#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ -#define IBM_CPM_RGMII 0x10000000 /* RGMII */ -#define IBM_CPM_TAHOE0 0x08000000 /* TAHOE 0 */ -#define IBM_CPM_TAHOE1 0x04000000 /* TAHOE 1 */ -#define IBM_CPM_CPU 0x02000000 /* processor core */ -#define IBM_CPM_DMA 0x01000000 /* DMA controller */ -#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ -#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ -#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ -#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ -#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ -#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ -#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ -#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ -#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ -#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ -#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ -#define IBM_CPM_UART0 0x00000200 /* serial port 0 */ -#define IBM_CPM_UART1 0x00000100 /* serial port 1 */ -#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ -#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ -#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */ -#define IBM_CPM_EMAC1 0x00000010 /* EMAC 1 */ -#define IBM_CPM_EMAC2 0x00000008 /* EMAC 2 */ -#define IBM_CPM_EMAC3 0x00000004 /* EMAC 3 */ - -#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ - | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ - | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ - | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \ - | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \ - | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \ - | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 ) -/* - * Serial port defines - */ -#define RS_TABLE_SIZE 2 - -#endif /* __PPC_PLATFORMS_IBM440GX_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c deleted file mode 100644 index de8f7ac5623c..000000000000 --- a/arch/ppc/platforms/4xx/ibm440sp.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * PPC440SP I/O descriptions - * - * Matt Porter - * Copyright 2002-2005 MontaVista Software Inc. - * - * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include - -static struct ocp_func_emac_data ibm440sp_emac0_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = -1, /* No ZMII */ - .zmii_mux = -1, /* No ZMII */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 0, /* MAL rx channel number */ - .mal_tx_chan = 0, /* MAL tx channel number */ - .wol_irq = 61, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; -OCP_SYSFS_EMAC_DATA() - -static struct ocp_func_mal_data ibm440sp_mal0_def = { - .num_tx_chans = 1, /* Number of TX channels */ - .num_rx_chans = 1, /* Number of RX channels */ - .txeob_irq = 38, /* TX End Of Buffer IRQ */ - .rxeob_irq = 39, /* RX End Of Buffer IRQ */ - .txde_irq = 34, /* TX Descriptor Error IRQ */ - .rxde_irq = 35, /* RX Descriptor Error IRQ */ - .serr_irq = 33, /* MAL System Error IRQ */ - .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ -}; -OCP_SYSFS_MAL_DATA() - -static struct ocp_func_iic_data ibm440sp_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; - -static struct ocp_func_iic_data ibm440sp_iic1_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_OPB, - .index = 0, - .paddr = 0x0000000140000000ULL, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = PPC440SP_UART0_ADDR, - .irq = UART0_INT, - .pm = IBM_CPM_UART0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = PPC440SP_UART1_ADDR, - .irq = UART1_INT, - .pm = IBM_CPM_UART1, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 2, - .paddr = PPC440SP_UART2_ADDR, - .irq = UART2_INT, - .pm = IBM_CPM_UART2, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 0, - .paddr = 0x00000001f0000400ULL, - .irq = 2, - .pm = IBM_CPM_IIC0, - .additions = &ibm440sp_iic0_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 1, - .paddr = 0x00000001f0000500ULL, - .irq = 3, - .pm = IBM_CPM_IIC1, - .additions = &ibm440sp_iic1_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .index = 0, - .paddr = 0x00000001f0000700ULL, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_MAL, - .paddr = OCP_PADDR_NA, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - .additions = &ibm440sp_mal0_def, - .show = &ocp_show_mal_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 0, - .paddr = 0x00000001f0000800ULL, - .irq = 60, - .pm = OCP_CPM_NA, - .additions = &ibm440sp_emac0_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_INVALID - } -}; diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h deleted file mode 100644 index 2978682f1720..000000000000 --- a/arch/ppc/platforms/4xx/ibm440sp.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * PPC440SP definitions - * - * Matt Porter - * - * Copyright 2004-2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __PPC_PLATFORMS_IBM440SP_H -#define __PPC_PLATFORMS_IBM440SP_H - - -#include - -/* UART */ -#define PPC440SP_UART0_ADDR 0x00000001f0000200ULL -#define PPC440SP_UART1_ADDR 0x00000001f0000300ULL -#define PPC440SP_UART2_ADDR 0x00000001f0000600ULL -#define UART0_INT 0 -#define UART1_INT 1 -#define UART2_INT 2 - -/* Clock and Power Management */ -#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ -#define IBM_CPM_IIC1 0x40000000 /* IIC interface */ -#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ -#define IBM_CPM_CPU 0x02000000 /* processor core */ -#define IBM_CPM_DMA 0x01000000 /* DMA controller */ -#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ -#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ -#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ -#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ -#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ -#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ -#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ -#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ -#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ -#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ -#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ -#define IBM_CPM_UART0 0x00000200 /* serial port 0 */ -#define IBM_CPM_UART1 0x00000100 /* serial port 1 */ -#define IBM_CPM_UART2 0x00000100 /* serial port 1 */ -#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ -#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ -#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */ - -#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ - | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ - | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ - | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \ - | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \ - | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \ - | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 ) -#endif /* __PPC_PLATFORMS_IBM440SP_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c deleted file mode 100644 index 1afc3642e5b1..000000000000 --- a/arch/ppc/platforms/4xx/ibmnp405h.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include - -static struct ocp_func_emac_data ibmnp405h_emac0_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 0, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 0, /* MAL rx channel number */ - .mal_tx_chan = 0, /* MAL tx channel number */ - .wol_irq = 41, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; - -static struct ocp_func_emac_data ibmnp405h_emac1_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 1, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 1, /* MAL rx channel number */ - .mal_tx_chan = 2, /* MAL tx channel number */ - .wol_irq = 41, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; -static struct ocp_func_emac_data ibmnp405h_emac2_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 2, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 2, /* MAL rx channel number */ - .mal_tx_chan = 4, /* MAL tx channel number */ - .wol_irq = 41, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; -static struct ocp_func_emac_data ibmnp405h_emac3_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = 0, /* ZMII device index */ - .zmii_mux = 3, /* ZMII input of this EMAC */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 3, /* MAL rx channel number */ - .mal_tx_chan = 6, /* MAL tx channel number */ - .wol_irq = 41, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; -OCP_SYSFS_EMAC_DATA() - -static struct ocp_func_mal_data ibmnp405h_mal0_def = { - .num_tx_chans = 8, /* Number of TX channels */ - .num_rx_chans = 4, /* Number of RX channels */ - .txeob_irq = 17, /* TX End Of Buffer IRQ */ - .rxeob_irq = 18, /* RX End Of Buffer IRQ */ - .txde_irq = 46, /* TX Descriptor Error IRQ */ - .rxde_irq = 47, /* RX Descriptor Error IRQ */ - .serr_irq = 45, /* MAL System Error IRQ */ - .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ -}; -OCP_SYSFS_MAL_DATA() - -static struct ocp_func_iic_data ibmnp405h_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_OPB, - .index = 0, - .paddr = 0xEF600000, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = UART0_IO_BASE, - .irq = UART0_INT, - .pm = IBM_CPM_UART0 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = UART1_IO_BASE, - .irq = UART1_INT, - .pm = IBM_CPM_UART1 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .paddr = 0xEF600500, - .irq = 2, - .pm = IBM_CPM_IIC0, - .additions = &ibmnp405h_iic0_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .paddr = 0xEF600700, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0 - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_MAL, - .paddr = OCP_PADDR_NA, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - .additions = &ibmnp405h_mal0_def, - .show = &ocp_show_mal_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 0, - .paddr = EMAC0_BASE, - .irq = 37, - .pm = IBM_CPM_EMAC0, - .additions = &ibmnp405h_emac0_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 1, - .paddr = 0xEF600900, - .irq = 38, - .pm = IBM_CPM_EMAC1, - .additions = &ibmnp405h_emac1_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 2, - .paddr = 0xEF600a00, - .irq = 39, - .pm = IBM_CPM_EMAC2, - .additions = &ibmnp405h_emac2_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 3, - .paddr = 0xEF600b00, - .irq = 40, - .pm = IBM_CPM_EMAC3, - .additions = &ibmnp405h_emac3_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_ZMII, - .paddr = 0xEF600C10, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_INVALID - } -}; diff --git a/arch/ppc/platforms/4xx/ibmnp405h.h b/arch/ppc/platforms/4xx/ibmnp405h.h deleted file mode 100644 index 08a6a7791903..000000000000 --- a/arch/ppc/platforms/4xx/ibmnp405h.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBMNP405H_H__ -#define __ASM_IBMNP405H_H__ - - -/* ibm405.h at bottom of this file */ - -#define PPC405_PCI_CONFIG_ADDR 0xeec00000 -#define PPC405_PCI_CONFIG_DATA 0xeec00004 -#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */ - /* setbat */ -#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */ -#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */ -#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */ - -#define PPC405_PCI_LOWER_MEM 0x00000000 /* hose_a->mem_space.start */ -#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */ -#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */ -#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */ - -#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE - -#define PPC4xx_PCI_IO_ADDR ((uint)PPC405_PCI_PHY_IO_BASE) -#define PPC4xx_PCI_IO_SIZE ((uint)64*1024) -#define PPC4xx_PCI_CFG_ADDR ((uint)PPC405_PCI_CONFIG_ADDR) -#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) -#define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000) -#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) -#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000) -#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) - -/* serial port defines */ -#define RS_TABLE_SIZE 4 - -#define UART0_INT 0 -#define UART1_INT 1 -#define PCIL0_BASE 0xEF400000 -#define UART0_IO_BASE 0xEF600300 -#define UART1_IO_BASE 0xEF600400 -#define OPB0_BASE 0xEF600600 -#define EMAC0_BASE 0xEF600800 - -#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i] - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base:(u8 *) UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#if defined(CONFIG_UART0_TTYS0) -#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) -#endif - -#if defined(CONFIG_UART0_TTYS1) -#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(1) \ - STD_UART_OP(0) -#endif - -/* DCR defines */ -/* ------------------------------------------------------------------------- */ - -#define DCRN_CHCR_BASE 0x0F1 -#define DCRN_CHPSR_BASE 0x0B4 -#define DCRN_CPMSR_BASE 0x0BA -#define DCRN_CPMFR_BASE 0x0B9 -#define DCRN_CPMER_BASE 0x0B8 - -/* CPM Clocking & Power Management defines */ -#define IBM_CPM_PCI 0x40000000 /* PCI */ -#define IBM_CPM_EMAC2 0x20000000 /* EMAC 2 MII */ -#define IBM_CPM_EMAC3 0x04000000 /* EMAC 3 MII */ -#define IBM_CPM_EMAC0 0x00800000 /* EMAC 0 MII */ -#define IBM_CPM_EMAC1 0x00100000 /* EMAC 1 MII */ -#define IBM_CPM_EMMII 0 /* Shift value for MII */ -#define IBM_CPM_EMRX 1 /* Shift value for recv */ -#define IBM_CPM_EMTX 2 /* Shift value for MAC */ -#define IBM_CPM_UIC1 0x00020000 /* Universal Interrupt Controller */ -#define IBM_CPM_UIC0 0x00010000 /* Universal Interrupt Controller */ -#define IBM_CPM_CPU 0x00008000 /* processor core */ -#define IBM_CPM_EBC 0x00004000 /* ROM/SRAM peripheral controller */ -#define IBM_CPM_SDRAM0 0x00002000 /* SDRAM memory controller */ -#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO (??) */ -#define IBM_CPM_HDLC 0x00000800 /* HDCL */ -#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */ -#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */ -#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */ -#define IBM_CPM_DMA 0x00000040 /* DMA controller */ -#define IBM_CPM_IIC0 0x00000010 /* IIC interface */ -#define IBM_CPM_UART0 0x00000002 /* serial port 0 */ -#define IBM_CPM_UART1 0x00000001 /* serial port 1 */ -/* this is the default setting for devices put to sleep when booting */ - -#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \ - | IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB \ - | IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA \ - | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2 \ - | IBM_CPM_EMAC3 | IBM_CPM_PCI) - -#define DCRN_DMA0_BASE 0x100 -#define DCRN_DMA1_BASE 0x108 -#define DCRN_DMA2_BASE 0x110 -#define DCRN_DMA3_BASE 0x118 -#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ -#define DCRN_DMASR_BASE 0x120 -#define DCRN_EBC_BASE 0x012 -#define DCRN_DCP0_BASE 0x014 -#define DCRN_MAL_BASE 0x180 -#define DCRN_OCM0_BASE 0x018 -#define DCRN_PLB0_BASE 0x084 -#define DCRN_PLLMR_BASE 0x0B0 -#define DCRN_POB0_BASE 0x0A0 -#define DCRN_SDRAM0_BASE 0x010 -#define DCRN_UIC0_BASE 0x0C0 -#define DCRN_UIC1_BASE 0x0D0 -#define DCRN_CPC0_EPRCSR 0x0F3 - -#define UIC0_UIC1NC 0x00000002 - -#define CHR1_CETE 0x00000004 /* CPU external timer enable */ -#define UIC0 DCRN_UIC0_BASE -#define UIC1 DCRN_UIC1_BASE - -#undef NR_UICS -#define NR_UICS 2 - -/* EMAC DCRN's FIXME: armin */ -#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */ -#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */ -#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */ -#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */ -#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */ -#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */ -#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */ -#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */ - -#include - -#endif /* __ASM_IBMNP405H_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c deleted file mode 100644 index 799a2eccccc3..000000000000 --- a/arch/ppc/platforms/4xx/ibmstb4.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include - -static struct ocp_func_iic_data ibmstb4_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; - -static struct ocp_func_iic_data ibmstb4_iic1_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] __initdata = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = UART0_IO_BASE, - .irq = UART0_INT, - .pm = IBM_CPM_UART0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = UART1_IO_BASE, - .irq = UART1_INT, - .pm = IBM_CPM_UART1, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 2, - .paddr = UART2_IO_BASE, - .irq = UART2_INT, - .pm = IBM_CPM_UART2, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .paddr = IIC0_BASE, - .irq = IIC0_IRQ, - .pm = IBM_CPM_IIC0, - .additions = &ibmstb4_iic0_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .paddr = IIC1_BASE, - .irq = IIC1_IRQ, - .pm = IBM_CPM_IIC1, - .additions = &ibmstb4_iic1_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .paddr = GPIO0_BASE, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IDE, - .paddr = IDE0_BASE, - .irq = IDE0_IRQ, - .pm = OCP_CPM_NA, - }, - { .vendor = OCP_VENDOR_INVALID, - } -}; - -/* Polarity and triggering settings for internal interrupt sources */ -struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { - { .polarity = 0x7fffff01, - .triggering = 0x00000000, - .ext_irq_mask = 0x0000007e, /* IRQ0 - IRQ5 */ - } -}; - -static struct resource ohci_usb_resources[] = { - [0] = { - .start = USB0_BASE, - .end = USB0_BASE + USB0_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = USB0_IRQ, - .end = USB0_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 dma_mask = 0xffffffffULL; - -static struct platform_device ohci_usb_device = { - .name = "ppc-soc-ohci", - .id = 0, - .num_resources = ARRAY_SIZE(ohci_usb_resources), - .resource = ohci_usb_resources, - .dev = { - .dma_mask = &dma_mask, - .coherent_dma_mask = 0xffffffffULL, - } -}; - -static struct platform_device *ibmstb4_devs[] __initdata = { - &ohci_usb_device, -}; - -static int __init -ibmstb4_platform_add_devices(void) -{ - return platform_add_devices(ibmstb4_devs, ARRAY_SIZE(ibmstb4_devs)); -} -arch_initcall(ibmstb4_platform_add_devices); diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h deleted file mode 100644 index 31a08abaa4a2..000000000000 --- a/arch/ppc/platforms/4xx/ibmstb4.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBMSTB4_H__ -#define __ASM_IBMSTB4_H__ - - -/* serial port defines */ -#define STB04xxx_IO_BASE ((uint)0xe0000000) -#define PPC4xx_PCI_IO_ADDR STB04xxx_IO_BASE -#define PPC4xx_ONB_IO_PADDR STB04xxx_IO_BASE -#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000) -#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024) - -/* - * map STB04xxx internal i/o address (0x400x00xx) to an address - * which is below the 2GB limit... - * - * 4000 000x uart1 -> 0xe000 000x - * 4001 00xx ppu - * 4002 00xx smart card - * 4003 000x iic - * 4004 000x uart0 - * 4005 0xxx timer - * 4006 00xx gpio - * 4007 00xx smart card - * 400b 000x iic - * 400c 000x scp - * 400d 000x modem - * 400e 000x uart2 -*/ -#define STB04xxx_MAP_IO_ADDR(a) (((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000)) - -#define RS_TABLE_SIZE 3 -#define UART0_INT 20 - -#ifdef __BOOTER__ -#define UART0_IO_BASE 0x40040000 -#else -#define UART0_IO_BASE 0xe0040000 -#endif - -#define UART1_INT 21 - -#ifdef __BOOTER__ -#define UART1_IO_BASE 0x40000000 -#else -#define UART1_IO_BASE 0xe0000000 -#endif - -#define UART2_INT 31 -#ifdef __BOOTER__ -#define UART2_IO_BASE 0x400e0000 -#else -#define UART2_IO_BASE 0xe00e0000 -#endif - -#define IDE0_BASE 0x400F0000 -#define IDE0_SIZE 0x200 -#define IDE0_IRQ 25 -#define IIC0_BASE 0x40030000 -#define IIC1_BASE 0x400b0000 -#define OPB0_BASE 0x40000000 -#define GPIO0_BASE 0x40060000 - -#define USB0_BASE 0x40010000 -#define USB0_SIZE 0xA0 -#define USB0_IRQ 18 - -#define IIC_NUMS 2 -#define UART_NUMS 3 -#define IIC0_IRQ 9 -#define IIC1_IRQ 10 -#define IIC_OWN 0x55 -#define IIC_CLOCK 50 - -#define BD_EMAC_ADDR(e,i) bi_enetaddr[i] - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (u8 *)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#if defined(CONFIG_UART0_TTYS0) -#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) \ - STD_UART_OP(2) -#endif - -#if defined(CONFIG_UART0_TTYS1) -#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(1) \ - STD_UART_OP(0) \ - STD_UART_OP(2) -#endif - -#if defined(CONFIG_UART0_TTYS2) -#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(2) \ - STD_UART_OP(0) \ - STD_UART_OP(1) -#endif - -#define DCRN_BE_BASE 0x090 -#define DCRN_DMA0_BASE 0x0C0 -#define DCRN_DMA1_BASE 0x0C8 -#define DCRN_DMA2_BASE 0x0D0 -#define DCRN_DMA3_BASE 0x0D8 -#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ -#define DCRN_DMASR_BASE 0x0E0 -#define DCRN_PLB0_BASE 0x054 -#define DCRN_PLB1_BASE 0x064 -#define DCRN_POB0_BASE 0x0B0 -#define DCRN_SCCR_BASE 0x120 -#define DCRN_UIC0_BASE 0x040 -#define DCRN_BE_BASE 0x090 -#define DCRN_DMA0_BASE 0x0C0 -#define DCRN_DMA1_BASE 0x0C8 -#define DCRN_DMA2_BASE 0x0D0 -#define DCRN_DMA3_BASE 0x0D8 -#define DCRN_CIC_BASE 0x030 -#define DCRN_DMASR_BASE 0x0E0 -#define DCRN_EBIMC_BASE 0x070 -#define DCRN_DCRX_BASE 0x020 -#define DCRN_CPMFR_BASE 0x102 -#define DCRN_SCCR_BASE 0x120 -#define UIC0 DCRN_UIC0_BASE - -#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */ -#define IBM_CPM_USB0 0x40000000 /* IEEE-1284 */ -#define IBM_CPM_IIC1 0x20000000 /* IIC 1 interface */ -#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */ -#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */ -#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */ -#define IBM_CPM_SDRAM1 0x02000000 /* SDRAM 1 memory controller */ -#define IBM_CPM_DMA 0x01000000 /* DMA controller */ -#define IBM_CPM_DMA1 0x00800000 /* reserved */ -#define IBM_CPM_XPT1 0x00400000 /* reserved */ -#define IBM_CPM_XPT2 0x00200000 /* reserved */ -#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */ -#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */ -#define IBM_CPM_EPI 0x00040000 /* DCR Extension */ -#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */ -#define IBM_CPM_VID 0x00010000 /* reserved */ -#define IBM_CPM_SC1 0x00008000 /* Smart Card 1 */ -#define IBM_CPM_USBSDRA 0x00004000 /* SDRAM 0 memory controller */ -#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */ -#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */ -#define IBM_CPM_GPT 0x00000800 /* GPTPWM */ -#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */ -#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */ -#define IBM_CPM_TMRCLK 0x00000100 /* CPU timers */ -#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */ -#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */ -#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */ -#define IBM_CPM_UART2 0x00000008 /* Serial Control Port */ -#define IBM_CPM_DDIO 0x00000004 /* Descrambler */ -#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */ - -#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \ - | IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \ - | IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \ - | IBM_CPM_XPT27 | IBM_CPM_UIC ) - -#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ -#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */ -/* DCRN_BESR */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 - -#define CHR1_CETE 0x00800000 /* CPU external timer enable */ -#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ - -#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ -#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ -#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ -#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ -#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ -#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ -#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ -#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ -#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ - -#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ -#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ -#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ -#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ -#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ -#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ -#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ -#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ - -#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ -#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ -#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ -#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ -#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ -#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ -#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ -#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ -#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */ -#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */ -#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */ -#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */ -#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */ -#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */ -#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */ -#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */ -#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */ -#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */ -#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */ - -#include - -#endif /* __ASM_IBMSTB4_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ibmstbx25.c b/arch/ppc/platforms/4xx/ibmstbx25.c deleted file mode 100644 index 090ddcbecc5e..000000000000 --- a/arch/ppc/platforms/4xx/ibmstbx25.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include - -static struct ocp_func_iic_data ibmstbx25_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] __initdata = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = UART0_IO_BASE, - .irq = UART0_INT, - .pm = IBM_CPM_UART0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = UART1_IO_BASE, - .irq = UART1_INT, - .pm = IBM_CPM_UART1, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 2, - .paddr = UART2_IO_BASE, - .irq = UART2_INT, - .pm = IBM_CPM_UART2, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .paddr = IIC0_BASE, - .irq = IIC0_IRQ, - .pm = IBM_CPM_IIC0, - .additions = &ibmstbx25_iic0_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .paddr = GPIO0_BASE, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0, - }, - { .vendor = OCP_VENDOR_INVALID - } -}; - -/* Polarity and triggering settings for internal interrupt sources */ -struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { - { .polarity = 0xffff8f80, - .triggering = 0x00000000, - .ext_irq_mask = 0x0000707f, /* IRQ7 - IRQ9, IRQ0 - IRQ6 */ - } -}; diff --git a/arch/ppc/platforms/4xx/ibmstbx25.h b/arch/ppc/platforms/4xx/ibmstbx25.h deleted file mode 100644 index 31b63343e641..000000000000 --- a/arch/ppc/platforms/4xx/ibmstbx25.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBMSTBX25_H__ -#define __ASM_IBMSTBX25_H__ - - -/* serial port defines */ -#define STBx25xx_IO_BASE ((uint)0xe0000000) -#define PPC4xx_ONB_IO_PADDR STBx25xx_IO_BASE -#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000) -#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024) - -/* - * map STBxxxx internal i/o address (0x400x00xx) to an address - * which is below the 2GB limit... - * - * 4000 000x uart1 -> 0xe000 000x - * 4001 00xx uart2 - * 4002 00xx smart card - * 4003 000x iic - * 4004 000x uart0 - * 4005 0xxx timer - * 4006 00xx gpio - * 4007 00xx smart card - * 400b 000x iic - * 400c 000x scp - * 400d 000x modem - * 400e 000x uart2 -*/ -#define STBx25xx_MAP_IO_ADDR(a) (((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000)) - -#define RS_TABLE_SIZE 3 - -#define OPB_BASE_START 0x40000000 -#define EBIU_BASE_START 0xF0100000 -#define DCR_BASE_START 0x0000 - -#ifdef __BOOTER__ -#define UART1_IO_BASE 0x40000000 -#define UART2_IO_BASE 0x40010000 -#else -#define UART1_IO_BASE 0xe0000000 -#define UART2_IO_BASE 0xe0010000 -#endif -#define SC0_BASE 0x40020000 /* smart card #0 */ -#define IIC0_BASE 0x40030000 -#ifdef __BOOTER__ -#define UART0_IO_BASE 0x40040000 -#else -#define UART0_IO_BASE 0xe0040000 -#endif -#define SCC0_BASE 0x40040000 /* Serial 0 controller IrdA */ -#define GPT0_BASE 0x40050000 /* General purpose timers */ -#define GPIO0_BASE 0x40060000 -#define SC1_BASE 0x40070000 /* smart card #1 */ -#define SCP0_BASE 0x400C0000 /* Serial Controller Port */ -#define SSP0_BASE 0x400D0000 /* Sync serial port */ - -#define IDE0_BASE 0xf0100000 -#define REDWOOD_IDE_CTRL 0xf1100000 - -#define RTCFPC_IRQ 0 -#define XPORT_IRQ 1 -#define AUD_IRQ 2 -#define AID_IRQ 3 -#define DMA0 4 -#define DMA1_IRQ 5 -#define DMA2_IRQ 6 -#define DMA3_IRQ 7 -#define SC0_IRQ 8 -#define IIC0_IRQ 9 -#define IIR0_IRQ 10 -#define GPT0_IRQ 11 -#define GPT1_IRQ 12 -#define SCP0_IRQ 13 -#define SSP0_IRQ 14 -#define GPT2_IRQ 15 /* count down timer */ -#define SC1_IRQ 16 -/* IRQ 17 - 19 external */ -#define UART0_INT 20 -#define UART1_INT 21 -#define UART2_INT 22 -#define XPTDMA_IRQ 23 -#define DCRIDE_IRQ 24 -/* IRQ 25 - 30 external */ -#define IDE0_IRQ 26 - -#define IIC_NUMS 1 -#define UART_NUMS 3 -#define IIC_OWN 0x55 -#define IIC_CLOCK 50 - -#define BD_EMAC_ADDR(e,i) bi_enetaddr[i] - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (u8 *)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#if defined(CONFIG_UART0_TTYS0) -#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) \ - STD_UART_OP(2) -#endif - -#if defined(CONFIG_UART0_TTYS1) -#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(1) \ - STD_UART_OP(0) \ - STD_UART_OP(2) -#endif - -#if defined(CONFIG_UART0_TTYS2) -#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE -#define SERIAL_PORT_DFNS \ - STD_UART_OP(2) \ - STD_UART_OP(0) \ - STD_UART_OP(1) -#endif - -#define DCRN_BE_BASE 0x090 -#define DCRN_DMA0_BASE 0x0C0 -#define DCRN_DMA1_BASE 0x0C8 -#define DCRN_DMA2_BASE 0x0D0 -#define DCRN_DMA3_BASE 0x0D8 -#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ -#define DCRN_DMASR_BASE 0x0E0 -#define DCRN_PLB0_BASE 0x054 -#define DCRN_PLB1_BASE 0x064 -#define DCRN_POB0_BASE 0x0B0 -#define DCRN_SCCR_BASE 0x120 -#define DCRN_UIC0_BASE 0x040 -#define DCRN_BE_BASE 0x090 -#define DCRN_DMA0_BASE 0x0C0 -#define DCRN_DMA1_BASE 0x0C8 -#define DCRN_DMA2_BASE 0x0D0 -#define DCRN_DMA3_BASE 0x0D8 -#define DCRN_CIC_BASE 0x030 -#define DCRN_DMASR_BASE 0x0E0 -#define DCRN_EBIMC_BASE 0x070 -#define DCRN_DCRX_BASE 0x020 -#define DCRN_CPMFR_BASE 0x102 -#define DCRN_SCCR_BASE 0x120 -#define DCRN_RTCFP_BASE 0x310 - -#define UIC0 DCRN_UIC0_BASE - -#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */ -#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */ -#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */ -#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */ -#define IBM_CPM_IRR 0x02000000 /* Infrared receiver */ -#define IBM_CPM_DMA 0x01000000 /* DMA controller */ -#define IBM_CPM_UART2 0x00200000 /* Serial Control Port */ -#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */ -#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */ -#define IBM_PM_DCRIDE 0x00040000 /* DCR timeout & IDE line Mode clock */ -#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */ -#define IBM_CPM_VID 0x00010000 /* reserved */ -#define IBM_CPM_SC1 0x00008000 /* Smart Card 0 */ -#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */ -#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */ -#define IBM_CPM_GPT 0x00000800 /* GPTPWM */ -#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */ -#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */ -#define IBM_CPM_C405T 0x00000100 /* CPU timers */ -#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */ -#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */ -#define IBM_CPM_RTCFPC 0x00000020 /* Realtime clock and front panel */ -#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */ -#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */ -#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_DMA \ - | IBM_CPM_CBS | IBM_CPM_XPT0 | IBM_CPM_C405T \ - | IBM_CPM_XPT27 | IBM_CPM_UIC) - -#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ -#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */ -/* DCRN_BESR */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 - -#define CHR1_CETE 0x00800000 /* CPU external timer enable */ -#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ - -#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ -#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ -#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ -#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ -#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ -#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ -#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ -#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ -#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ - -#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ -#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ -#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ -#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ -#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ -#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ -#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ -#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ - -#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ -#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ -#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ -#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ -#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ -#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ -#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ -#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ -#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */ -#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */ -#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */ -#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */ -#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */ -#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */ -#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */ -#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */ -#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */ -#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */ -#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */ - -#define DCRN_RTC_FPC0_CNTL (DCRN_RTCFP_BASE + 0x00) /* RTC cntl */ -#define DCRN_RTC_FPC0_INT (DCRN_RTCFP_BASE + 0x01) /* RTC Interrupt */ -#define DCRN_RTC_FPC0_TIME (DCRN_RTCFP_BASE + 0x02) /* RTC time reg */ -#define DCRN_RTC_FPC0_ALRM (DCRN_RTCFP_BASE + 0x03) /* RTC Alarm reg */ -#define DCRN_RTC_FPC0_D1 (DCRN_RTCFP_BASE + 0x04) /* LED Data 1 */ -#define DCRN_RTC_FPC0_D2 (DCRN_RTCFP_BASE + 0x05) /* LED Data 2 */ -#define DCRN_RTC_FPC0_D3 (DCRN_RTCFP_BASE + 0x06) /* LED Data 3 */ -#define DCRN_RTC_FPC0_D4 (DCRN_RTCFP_BASE + 0x07) /* LED Data 4 */ -#define DCRN_RTC_FPC0_D5 (DCRN_RTCFP_BASE + 0x08) /* LED Data 5 */ -#define DCRN_RTC_FPC0_FCNTL (DCRN_RTCFP_BASE + 0x09) /* LED control */ -#define DCRN_RTC_FPC0_BRT (DCRN_RTCFP_BASE + 0x0A) /* Brightness cntl */ - -#include - -#endif /* __ASM_IBMSTBX25_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c deleted file mode 100644 index f6d8c2e8b6b7..000000000000 --- a/arch/ppc/platforms/4xx/luan.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Luan board specific routines - * - * Matt Porter - * - * Copyright 2004-2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -extern bd_t __res; - -static struct ibm44x_clocks clocks __initdata; - -static void __init -luan_calibrate_decr(void) -{ - unsigned int freq; - - if (mfspr(SPRN_CCR1) & CCR1_TCS) - freq = LUAN_TMR_CLK; - else - freq = clocks.cpu; - - ibm44x_calibrate_decr(freq); -} - -static int -luan_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: IBM\n"); - seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n"); - - return 0; -} - -static inline int -luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - - /* PCIX0 in adapter mode, no host interrupt routing */ - - /* PCIX1 */ - if (hose->index == 0) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 49, 49, 49, 49 }, /* IDSEL 1 - PCIX1 Slot 0 */ - { 49, 49, 49, 49 }, /* IDSEL 2 - PCIX1 Slot 1 */ - { 49, 49, 49, 49 }, /* IDSEL 3 - PCIX1 Slot 2 */ - { 49, 49, 49, 49 }, /* IDSEL 4 - PCIX1 Slot 3 */ - }; - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - /* PCIX2 */ - } else if (hose->index == 1) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 50, 50, 50, 50 }, /* IDSEL 1 - PCIX2 Slot 0 */ - { 50, 50, 50, 50 }, /* IDSEL 2 - PCIX2 Slot 1 */ - { 50, 50, 50, 50 }, /* IDSEL 3 - PCIX2 Slot 2 */ - { 50, 50, 50, 50 }, /* IDSEL 4 - PCIX2 Slot 3 */ - }; - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } - return -1; -} - -static void __init luan_set_emacdata(void) -{ - struct ocp_def *def; - struct ocp_func_emac_data *emacdata; - - /* Set phy_map, phy_mode, and mac_addr for the EMAC */ - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); - emacdata = def->additions; - emacdata->phy_map = 0x00000001; /* Skip 0x00 */ - emacdata->phy_mode = PHY_MODE_GMII; - memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); -} - -#define PCIX_READW(offset) \ - (readw((void *)((u32)pcix_reg_base+offset))) - -#define PCIX_WRITEW(value, offset) \ - (writew(value, (void *)((u32)pcix_reg_base+offset))) - -#define PCIX_WRITEL(value, offset) \ - (writel(value, (void *)((u32)pcix_reg_base+offset))) - -static void __init -luan_setup_pcix(void) -{ - int i; - void *pcix_reg_base; - - for (i=0;i<3;i++) { - pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE); - - /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ - PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); - - /* Disable all windows */ - PCIX_WRITEL(0, PCIX0_POM0SA); - PCIX_WRITEL(0, PCIX0_POM1SA); - PCIX_WRITEL(0, PCIX0_POM2SA); - PCIX_WRITEL(0, PCIX0_PIM0SA); - PCIX_WRITEL(0, PCIX0_PIM0SAH); - PCIX_WRITEL(0, PCIX0_PIM1SA); - PCIX_WRITEL(0, PCIX0_PIM2SA); - PCIX_WRITEL(0, PCIX0_PIM2SAH); - - /* - * Setup 512MB PLB->PCI outbound mem window - * (a_n000_0000->0_n000_0000) - * */ - PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH); - PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL); - PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); - PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL); - PCIX_WRITEL(0xe0000001, PCIX0_POM0SA); - - /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ - PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); - PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); - PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); - PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH); - - iounmap(pcix_reg_base); - } - - eieio(); -} - -static void __init -luan_setup_hose(struct pci_controller *hose, - int lower_mem, - int upper_mem, - int cfga, - int cfgd, - u64 pcix_io_base) -{ - char name[20]; - - sprintf(name, "PCIX%d host bridge", hose->index); - - hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET; - - pci_init_resource(&hose->io_resource, - LUAN_PCIX_LOWER_IO, - LUAN_PCIX_UPPER_IO, - IORESOURCE_IO, - name); - - pci_init_resource(&hose->mem_resources[0], - lower_mem, - upper_mem, - IORESOURCE_MEM, - name); - - hose->io_space.start = LUAN_PCIX_LOWER_IO; - hose->io_space.end = LUAN_PCIX_UPPER_IO; - hose->mem_space.start = lower_mem; - hose->mem_space.end = upper_mem; - hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE); - isa_io_base = (unsigned long) hose->io_base_virt; - - setup_indirect_pci(hose, cfga, cfgd); - hose->set_cfg_type = 1; -} - -static void __init -luan_setup_hoses(void) -{ - struct pci_controller *hose1, *hose2; - - /* Configure windows on the PCI-X host bridge */ - luan_setup_pcix(); - - /* Allocate hoses for PCIX1 and PCIX2 */ - hose1 = pcibios_alloc_controller(); - if (!hose1) - return; - - hose2 = pcibios_alloc_controller(); - if (!hose2) { - pcibios_free_controller(hose1); - return; - } - - /* Setup PCIX1 */ - hose1->first_busno = 0; - hose1->last_busno = 0xff; - - luan_setup_hose(hose1, - LUAN_PCIX1_LOWER_MEM, - LUAN_PCIX1_UPPER_MEM, - PCIX1_CFGA, - PCIX1_CFGD, - PCIX1_IO_BASE); - - hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); - - /* Setup PCIX2 */ - hose2->first_busno = hose1->last_busno + 1; - hose2->last_busno = 0xff; - - luan_setup_hose(hose2, - LUAN_PCIX2_LOWER_MEM, - LUAN_PCIX2_UPPER_MEM, - PCIX2_CFGA, - PCIX2_CFGD, - PCIX2_IO_BASE); - - hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = luan_map_irq; -} - -TODC_ALLOC(); - -static void __init -luan_early_serial_map(void) -{ - struct uart_port port; - - /* Setup ioremapped serial port access */ - memset(&port, 0, sizeof(port)); - port.membase = ioremap64(PPC440SP_UART0_ADDR, 8); - port.irq = UART0_INT; - port.uartclk = clocks.uart0; - port.regshift = 0; - port.iotype = UPIO_MEM; - port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - port.line = 0; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 0 failed\n"); - } - - port.membase = ioremap64(PPC440SP_UART1_ADDR, 8); - port.irq = UART1_INT; - port.uartclk = clocks.uart1; - port.line = 1; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 1 failed\n"); - } - - port.membase = ioremap64(PPC440SP_UART2_ADDR, 8); - port.irq = UART2_INT; - port.uartclk = BASE_BAUD; - port.line = 2; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 2 failed\n"); - } -} - -static void __init -luan_setup_arch(void) -{ - luan_set_emacdata(); - -#if !defined(CONFIG_BDI_SWITCH) - /* - * The Abatron BDI JTAG debugger does not tolerate others - * mucking with the debug registers. - */ - mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); -#endif - - /* - * Determine various clocks. - * To be completely correct we should get SysClk - * from FPGA, because it can be changed by on-board switches - * --ebs - */ - /* 440GX and 440SP clocking is the same -mdp */ - ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); - ocp_sys_info.opb_bus_freq = clocks.opb; - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - - /* Setup PCIXn host bridges */ - luan_setup_hoses(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_HDA1; -#endif - - luan_early_serial_map(); - - /* Identify the system */ - printk("Luan port (MontaVista Software, Inc. )\n"); -} - -void __init platform_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, unsigned long r7) -{ - ibm44x_platform_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = luan_setup_arch; - ppc_md.show_cpuinfo = luan_show_cpuinfo; - ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory; - ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ - - ppc_md.calibrate_decr = luan_calibrate_decr; -#ifdef CONFIG_KGDB - ppc_md.early_serial_map = luan_early_serial_map; -#endif -} diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h deleted file mode 100644 index 68dd46b0a5c4..000000000000 --- a/arch/ppc/platforms/4xx/luan.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Luan board definitions - * - * Matt Porter - * - * Copyright 2004-2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_LUAN_H__ -#define __ASM_LUAN_H__ - -#include - -/* F/W TLB mapping used in bootloader glue to reset EMAC */ -#define PPC44x_EMAC0_MR0 0xa0000800 - -/* Location of MAC addresses in PIBS image */ -#define PIBS_FLASH_BASE 0xffe00000 -#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400) - -/* External timer clock frequency */ -#define LUAN_TMR_CLK 25000000 - -/* Flash */ -#define LUAN_FPGA_REG_0 0x0000000148300000ULL -#define LUAN_BOOT_LARGE_FLASH(x) (x & 0x40) -#define LUAN_SMALL_FLASH_LOW 0x00000001ff900000ULL -#define LUAN_SMALL_FLASH_HIGH 0x00000001ffe00000ULL -#define LUAN_SMALL_FLASH_SIZE 0x100000 -#define LUAN_LARGE_FLASH_LOW 0x00000001ff800000ULL -#define LUAN_LARGE_FLASH_HIGH 0x00000001ffc00000ULL -#define LUAN_LARGE_FLASH_SIZE 0x400000 - -/* - * Serial port defines - */ -#define RS_TABLE_SIZE 3 - -/* PIBS defined UART mappings, used before early_serial_setup */ -#define UART0_IO_BASE 0xa0000200 -#define UART1_IO_BASE 0xa0000300 -#define UART2_IO_BASE 0xa0000600 - -#define BASE_BAUD 11059200 -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (void*)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) \ - STD_UART_OP(2) - -/* PCI support */ -#define LUAN_PCIX_LOWER_IO 0x00000000 -#define LUAN_PCIX_UPPER_IO 0x0000ffff -#define LUAN_PCIX0_LOWER_MEM 0x80000000 -#define LUAN_PCIX0_UPPER_MEM 0x9fffffff -#define LUAN_PCIX1_LOWER_MEM 0xa0000000 -#define LUAN_PCIX1_UPPER_MEM 0xbfffffff -#define LUAN_PCIX2_LOWER_MEM 0xc0000000 -#define LUAN_PCIX2_UPPER_MEM 0xdfffffff - -#define LUAN_PCIX_MEM_SIZE 0x20000000 -#define LUAN_PCIX_MEM_OFFSET 0x00000000 - -#endif /* __ASM_LUAN_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c deleted file mode 100644 index 308386ef6f77..000000000000 --- a/arch/ppc/platforms/4xx/ocotea.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Ocotea board specific routines - * - * Matt Porter - * - * Copyright 2003-2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -extern bd_t __res; - -static struct ibm44x_clocks clocks __initdata; - -static void __init -ocotea_calibrate_decr(void) -{ - unsigned int freq; - - if (mfspr(SPRN_CCR1) & CCR1_TCS) - freq = OCOTEA_TMR_CLK; - else - freq = clocks.cpu; - - ibm44x_calibrate_decr(freq); -} - -static int -ocotea_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: IBM\n"); - seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n"); - ibm440gx_show_cpuinfo(m); - return 0; -} - -static inline int -ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */ - { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */ - { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */ - { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */ - }; - - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -static void __init ocotea_set_emacdata(void) -{ - struct ocp_def *def; - struct ocp_func_emac_data *emacdata; - int i; - - /* - * Note: Current rev. board only operates in Group 4a - * mode, so we always set EMAC0-1 for SMII and EMAC2-3 - * for RGMII (though these could run in RTBI just the same). - * - * The FPGA reg 3 information isn't even suitable for - * determining the phy_mode, so if the board becomes - * usable in !4a, it will be necessary to parse an environment - * variable from the firmware or similar to properly configure - * the phy_map/phy_mode. - */ - /* Set phy_map, phy_mode, and mac_addr for each EMAC */ - for (i=0; i<4; i++) { - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); - emacdata = def->additions; - if (i < 2) { - emacdata->phy_map = 0x00000001; /* Skip 0x00 */ - emacdata->phy_mode = PHY_MODE_SMII; - } - else { - emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */ - emacdata->phy_mode = PHY_MODE_RGMII; - } - if (i == 0) - memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); - else if (i == 1) - memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); - else if (i == 2) - memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6); - else if (i == 3) - memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6); - } -} - -#define PCIX_READW(offset) \ - (readw(pcix_reg_base+offset)) - -#define PCIX_WRITEW(value, offset) \ - (writew(value, pcix_reg_base+offset)) - -#define PCIX_WRITEL(value, offset) \ - (writel(value, pcix_reg_base+offset)) - -/* - * FIXME: This is only here to "make it work". This will move - * to a ibm_pcix.c which will contain a generic IBM PCIX bridge - * configuration library. -Matt - */ -static void __init -ocotea_setup_pcix(void) -{ - void *pcix_reg_base; - - pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); - - /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ - PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); - - /* Disable all windows */ - PCIX_WRITEL(0, PCIX0_POM0SA); - PCIX_WRITEL(0, PCIX0_POM1SA); - PCIX_WRITEL(0, PCIX0_POM2SA); - PCIX_WRITEL(0, PCIX0_PIM0SA); - PCIX_WRITEL(0, PCIX0_PIM0SAH); - PCIX_WRITEL(0, PCIX0_PIM1SA); - PCIX_WRITEL(0, PCIX0_PIM2SA); - PCIX_WRITEL(0, PCIX0_PIM2SAH); - - /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ - PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); - PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); - PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); - PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); - PCIX_WRITEL(0x80000001, PCIX0_POM0SA); - - /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ - PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); - PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); - PCIX_WRITEL(0x80000007, PCIX0_PIM0SA); - - eieio(); -} - -static void __init -ocotea_setup_hose(void) -{ - struct pci_controller *hose; - - /* Configure windows on the PCI-X host bridge */ - ocotea_setup_pcix(); - - hose = pcibios_alloc_controller(); - - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET; - - pci_init_resource(&hose->io_resource, - OCOTEA_PCI_LOWER_IO, - OCOTEA_PCI_UPPER_IO, - IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource(&hose->mem_resources[0], - OCOTEA_PCI_LOWER_MEM, - OCOTEA_PCI_UPPER_MEM, - IORESOURCE_MEM, - "PCI host bridge"); - - hose->io_space.start = OCOTEA_PCI_LOWER_IO; - hose->io_space.end = OCOTEA_PCI_UPPER_IO; - hose->mem_space.start = OCOTEA_PCI_LOWER_MEM; - hose->mem_space.end = OCOTEA_PCI_UPPER_MEM; - hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE); - isa_io_base = (unsigned long) hose->io_base_virt; - - setup_indirect_pci(hose, - OCOTEA_PCI_CFGA_PLB32, - OCOTEA_PCI_CFGD_PLB32); - hose->set_cfg_type = 1; - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = ocotea_map_irq; -} - - -TODC_ALLOC(); - -static void __init -ocotea_early_serial_map(void) -{ - struct uart_port port; - - /* Setup ioremapped serial port access */ - memset(&port, 0, sizeof(port)); - port.membase = ioremap64(PPC440GX_UART0_ADDR, 8); - port.irq = UART0_INT; - port.uartclk = clocks.uart0; - port.regshift = 0; - port.iotype = UPIO_MEM; - port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - port.line = 0; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 0 failed\n"); - } - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Configure debug serial access */ - gen550_init(0, &port); - - /* Purge TLB entry added in head_44x.S for early serial access */ - _tlbie(UART0_IO_BASE, 0); -#endif - - port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); - port.irq = UART1_INT; - port.uartclk = clocks.uart1; - port.line = 1; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 1 failed\n"); - } - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Configure debug serial access */ - gen550_init(1, &port); -#endif -} - -static void __init -ocotea_setup_arch(void) -{ - ocotea_set_emacdata(); - - ibm440gx_tah_enable(); - - /* - * Determine various clocks. - * To be completely correct we should get SysClk - * from FPGA, because it can be changed by on-board switches - * --ebs - */ - ibm440gx_get_clocks(&clocks, 33300000, 6 * 1843200); - ocp_sys_info.opb_bus_freq = clocks.opb; - - /* Setup TODC access */ - TODC_INIT(TODC_TYPE_DS1743, - 0, - 0, - ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE), - 8); - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - - /* Setup PCI host bridge */ - ocotea_setup_hose(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_HDA1; -#endif - - ocotea_early_serial_map(); - - /* Identify the system */ - printk("IBM Ocotea port (MontaVista Software, Inc. )\n"); -} - -static void __init ocotea_init(void) -{ - ibm440gx_l2c_setup(&clocks); -} - -void __init platform_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, unsigned long r7) -{ - ibm440gx_platform_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = ocotea_setup_arch; - ppc_md.show_cpuinfo = ocotea_show_cpuinfo; - ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ - - ppc_md.calibrate_decr = ocotea_calibrate_decr; - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; -#ifdef CONFIG_KGDB - ppc_md.early_serial_map = ocotea_early_serial_map; -#endif - ppc_md.init = ocotea_init; -} diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h deleted file mode 100644 index 89730ce2322c..000000000000 --- a/arch/ppc/platforms/4xx/ocotea.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Ocotea board definitions - * - * Matt Porter - * - * Copyright 2003-2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_OCOTEA_H__ -#define __ASM_OCOTEA_H__ - -#include - -/* F/W TLB mapping used in bootloader glue to reset EMAC */ -#define PPC44x_EMAC0_MR0 0xe0000800 - -/* Location of MAC addresses in PIBS image */ -#define PIBS_FLASH_BASE 0xfff00000 -#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xb0500) -#define PIBS_MAC_SIZE 0x200 -#define PIBS_MAC_OFFSET 0x100 - -/* External timer clock frequency */ -#define OCOTEA_TMR_CLK 25000000 - -/* RTC/NVRAM location */ -#define OCOTEA_RTC_ADDR 0x0000000148000000ULL -#define OCOTEA_RTC_SIZE 0x2000 - -/* Flash */ -#define OCOTEA_FPGA_REG_0 0x0000000148300000ULL -#define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40) -#define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL -#define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL -#define OCOTEA_SMALL_FLASH_SIZE 0x100000 -#define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL -#define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL -#define OCOTEA_LARGE_FLASH_SIZE 0x400000 - -/* FPGA_REG_3 (Ethernet Groups) */ -#define OCOTEA_FPGA_REG_3 0x0000000148300003ULL - -/* - * Serial port defines - */ -#define RS_TABLE_SIZE 2 - -#if defined(__BOOTER__) -/* OpenBIOS defined UART mappings, used by bootloader shim */ -#define UART0_IO_BASE 0xE0000200 -#define UART1_IO_BASE 0xE0000300 -#else -/* head_44x.S created UART mapping, used before early_serial_setup. - * We cannot use default OpenBIOS UART mappings because they - * don't work for configurations with more than 512M RAM. --ebs - */ -#define UART0_IO_BASE 0xF0000200 -#define UART1_IO_BASE 0xF0000300 -#endif - -#define BASE_BAUD 11059200/16 -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (void*)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) - -/* PCI support */ -#define OCOTEA_PCI_LOWER_IO 0x00000000 -#define OCOTEA_PCI_UPPER_IO 0x0000ffff -#define OCOTEA_PCI_LOWER_MEM 0x80000000 -#define OCOTEA_PCI_UPPER_MEM 0xffffefff - -#define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL -#define OCOTEA_PCI_CFGA_PLB32 0x0ec00000 -#define OCOTEA_PCI_CFGD_PLB32 0x0ec00004 - -#define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL -#define OCOTEA_PCI_IO_SIZE 0x00010000 -#define OCOTEA_PCI_MEM_OFFSET 0x00000000 - -#endif /* __ASM_OCOTEA_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c deleted file mode 100644 index 1be5d1c8e266..000000000000 --- a/arch/ppc/platforms/4xx/ppc440spe.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * PPC440SPe I/O descriptions - * - * Roland Dreier - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * - * Matt Porter - * Copyright 2002-2005 MontaVista Software Inc. - * - * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include - -static struct ocp_func_emac_data ppc440spe_emac0_def = { - .rgmii_idx = -1, /* No RGMII */ - .rgmii_mux = -1, /* No RGMII */ - .zmii_idx = -1, /* No ZMII */ - .zmii_mux = -1, /* No ZMII */ - .mal_idx = 0, /* MAL device index */ - .mal_rx_chan = 0, /* MAL rx channel number */ - .mal_tx_chan = 0, /* MAL tx channel number */ - .wol_irq = 61, /* WOL interrupt number */ - .mdio_idx = -1, /* No shared MDIO */ - .tah_idx = -1, /* No TAH */ -}; -OCP_SYSFS_EMAC_DATA() - -static struct ocp_func_mal_data ppc440spe_mal0_def = { - .num_tx_chans = 1, /* Number of TX channels */ - .num_rx_chans = 1, /* Number of RX channels */ - .txeob_irq = 38, /* TX End Of Buffer IRQ */ - .rxeob_irq = 39, /* RX End Of Buffer IRQ */ - .txde_irq = 34, /* TX Descriptor Error IRQ */ - .rxde_irq = 35, /* RX Descriptor Error IRQ */ - .serr_irq = 33, /* MAL System Error IRQ */ - .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ -}; -OCP_SYSFS_MAL_DATA() - -static struct ocp_func_iic_data ppc440spe_iic0_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; - -static struct ocp_func_iic_data ppc440spe_iic1_def = { - .fast_mode = 0, /* Use standad mode (100Khz) */ -}; -OCP_SYSFS_IIC_DATA() - -struct ocp_def core_ocp[] = { - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = PPC440SPE_UART0_ADDR, - .irq = UART0_INT, - .pm = IBM_CPM_UART0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = PPC440SPE_UART1_ADDR, - .irq = UART1_INT, - .pm = IBM_CPM_UART1, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_16550, - .index = 2, - .paddr = PPC440SPE_UART2_ADDR, - .irq = UART2_INT, - .pm = IBM_CPM_UART2, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 0, - .paddr = 0x00000004f0000400ULL, - .irq = 2, - .pm = IBM_CPM_IIC0, - .additions = &ppc440spe_iic0_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_IIC, - .index = 1, - .paddr = 0x00000004f0000500ULL, - .irq = 3, - .pm = IBM_CPM_IIC1, - .additions = &ppc440spe_iic1_def, - .show = &ocp_show_iic_data - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_GPIO, - .index = 0, - .paddr = 0x00000004f0000700ULL, - .irq = OCP_IRQ_NA, - .pm = IBM_CPM_GPIO0, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_MAL, - .paddr = OCP_PADDR_NA, - .irq = OCP_IRQ_NA, - .pm = OCP_CPM_NA, - .additions = &ppc440spe_mal0_def, - .show = &ocp_show_mal_data, - }, - { .vendor = OCP_VENDOR_IBM, - .function = OCP_FUNC_EMAC, - .index = 0, - .paddr = 0x00000004f0000800ULL, - .irq = 60, - .pm = OCP_CPM_NA, - .additions = &ppc440spe_emac0_def, - .show = &ocp_show_emac_data, - }, - { .vendor = OCP_VENDOR_INVALID - } -}; - -/* Polarity and triggering settings for internal interrupt sources */ -struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { - { .polarity = 0xffffffff, - .triggering = 0x010f0004, - .ext_irq_mask = 0x00000000, - }, - { .polarity = 0xffffffff, - .triggering = 0x001f8040, - .ext_irq_mask = 0x00007c30, /* IRQ6 - IRQ7, IRQ8 - IRQ12 */ - }, - { .polarity = 0xffffffff, - .triggering = 0x00000000, - .ext_irq_mask = 0x000000fc, /* IRQ0 - IRQ5 */ - }, - { .polarity = 0xffffffff, - .triggering = 0x00000000, - .ext_irq_mask = 0x00000000, - }, -}; diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h deleted file mode 100644 index f1e867c4c9fc..000000000000 --- a/arch/ppc/platforms/4xx/ppc440spe.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * PPC440SPe definitions - * - * Roland Dreier - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * - * Matt Porter - * Copyright 2004-2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __PPC_PLATFORMS_PPC440SPE_H -#define __PPC_PLATFORMS_PPC440SPE_H - - -#include - -/* UART */ -#define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL -#define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL -#define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL -#define UART0_INT 0 -#define UART1_INT 1 -#define UART2_INT 37 - -/* Clock and Power Management */ -#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ -#define IBM_CPM_IIC1 0x40000000 /* IIC interface */ -#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ -#define IBM_CPM_CPU 0x02000000 /* processor core */ -#define IBM_CPM_DMA 0x01000000 /* DMA controller */ -#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ -#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ -#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ -#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ -#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ -#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ -#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ -#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ -#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ -#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ -#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ -#define IBM_CPM_UART0 0x00000200 /* serial port 0 */ -#define IBM_CPM_UART1 0x00000100 /* serial port 1 */ -#define IBM_CPM_UART2 0x00000100 /* serial port 1 */ -#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ -#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ -#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */ - -#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ - | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ - | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ - | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \ - | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \ - | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \ - | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 ) -#endif /* __PPC_PLATFORMS_PPC440SP_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c deleted file mode 100644 index edf4d37d1a52..000000000000 --- a/arch/ppc/platforms/4xx/redwood5.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Support for the IBM redwood5 eval board file - * - * Author: Armin Kuster - * - * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * Define external IRQ senses and polarities. - */ -unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */ -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = SMC91111_BASE_ADDR, - .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SMC91111_IRQ, - .end = SMC91111_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct platform_device *redwood5_devs[] __initdata = { - &smc91x_device, -}; - -static int __init -redwood5_platform_add_devices(void) -{ - return platform_add_devices(redwood5_devs, ARRAY_SIZE(redwood5_devs)); -} - -void __init -redwood5_setup_arch(void) -{ - ppc4xx_setup_arch(); - -#ifdef CONFIG_DEBUG_BRINGUP - printk("\n"); - printk("machine\t: %s\n", PPC4xx_MACHINE_NAME); - printk("\n"); - printk("bi_s_version\t %s\n", bip->bi_s_version); - printk("bi_r_version\t %s\n", bip->bi_r_version); - printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,bip->bi_memsize/(1024*1000)); - printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0, - bip->bi_enetaddr[0], bip->bi_enetaddr[1], - bip->bi_enetaddr[2], bip->bi_enetaddr[3], - bip->bi_enetaddr[4], bip->bi_enetaddr[5]); - - printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n", - bip->bi_intfreq, bip->bi_intfreq/ 1000000); - - printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n", - bip->bi_busfreq, bip->bi_busfreq / 1000000 ); - printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n", - bip->bi_tbfreq, bip->bi_tbfreq/1000000); - - printk("\n"); -#endif - device_initcall(redwood5_platform_add_devices); -} - -void __init -redwood5_map_io(void) -{ - int i; - - ppc4xx_map_io(); - for (i = 0; i < 16; i++) { - unsigned long v, p; - - /* 0x400x0000 -> 0xe00x0000 */ - p = 0x40000000 | (i << 16); - v = STB04xxx_IO_BASE | (i << 16); - - io_block_mapping(v, p, PAGE_SIZE, - _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) | _PAGE_GUARDED); - } - - -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = redwood5_setup_arch; - ppc_md.setup_io_mappings = redwood5_map_io; -} diff --git a/arch/ppc/platforms/4xx/redwood5.h b/arch/ppc/platforms/4xx/redwood5.h deleted file mode 100644 index 49edd4818970..000000000000 --- a/arch/ppc/platforms/4xx/redwood5.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Macros, definitions, and data structures specific to the IBM PowerPC - * STB03xxx "Redwood" evaluation board. - * - * Author: Armin Kuster - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_REDWOOD5_H__ -#define __ASM_REDWOOD5_H__ - -/* Redwood5 has an STB04xxx core */ -#include - -#ifndef __ASSEMBLY__ -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned int bi_dummy; /* field shouldn't exist */ - unsigned char bi_enetaddr[6]; /* Ethernet MAC address */ - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* Bus speed, in Hz */ - unsigned int bi_tbfreq; /* Software timebase freq */ -} bd_t; -#endif /* !__ASSEMBLY__ */ - - -#define SMC91111_BASE_ADDR 0xf2000300 -#define SMC91111_REG_SIZE 16 -#define SMC91111_IRQ 28 - -#ifdef MAX_HWIFS -#undef MAX_HWIFS -#endif -#define MAX_HWIFS 1 - -#define _IO_BASE 0 -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 - -#define BASE_BAUD (378000000 / 18 / 16) - -#define PPC4xx_MACHINE_NAME "IBM Redwood5" - -#endif /* __ASM_REDWOOD5_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c deleted file mode 100644 index 006e29f83a1a..000000000000 --- a/arch/ppc/platforms/4xx/redwood6.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Define external IRQ senses and polarities. - */ -unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */ -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = SMC91111_BASE_ADDR, - .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SMC91111_IRQ, - .end = SMC91111_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct platform_device *redwood6_devs[] __initdata = { - &smc91x_device, -}; - -static int __init -redwood6_platform_add_devices(void) -{ - return platform_add_devices(redwood6_devs, ARRAY_SIZE(redwood6_devs)); -} - - -void __init -redwood6_setup_arch(void) -{ -#ifdef CONFIG_IDE - void *xilinx, *xilinx_1, *xilinx_2; - unsigned short us_reg5; -#endif - - ppc4xx_setup_arch(); - -#ifdef CONFIG_IDE - xilinx = (unsigned long) ioremap(IDE_XLINUX_MUX_BASE, 0x10); - /* init xilinx control registers - enable ide mux, clear reset bit */ - if (!xilinx) { - printk(KERN_CRIT - "redwood6_setup_arch() xilinxi ioremap failed\n"); - return; - } - xilinx_1 = xilinx + 0xa; - xilinx_2 = xilinx + 0xe; - - us_reg5 = readb(xilinx_1); - writeb(0x01d1, xilinx_1); - writeb(0x0008, xilinx_2); - - udelay(10 * 1000); - - writeb(0x01d1, xilinx_1); - writeb(0x0008, xilinx_2); -#endif - -#ifdef DEBUG_BRINGUP - bd_t *bip = (bd_t *) __res; - printk("\n"); - printk("machine\t: %s\n", PPC4xx_MACHINE_NAME); - printk("\n"); - printk("bi_s_version\t %s\n", bip->bi_s_version); - printk("bi_r_version\t %s\n", bip->bi_r_version); - printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize, - bip->bi_memsize / (1024 * 1000)); - printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0, - bip->bi_enetaddr[0], bip->bi_enetaddr[1], bip->bi_enetaddr[2], - bip->bi_enetaddr[3], bip->bi_enetaddr[4], bip->bi_enetaddr[5]); - - printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n", - bip->bi_intfreq, bip->bi_intfreq / 1000000); - - printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n", - bip->bi_busfreq, bip->bi_busfreq / 1000000); - printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n", - bip->bi_tbfreq, bip->bi_tbfreq / 1000000); - - printk("\n"); -#endif - - /* Identify the system */ - printk(KERN_INFO "IBM Redwood6 (STBx25XX) Platform\n"); - printk(KERN_INFO - "Port by MontaVista Software, Inc. (source@mvista.com)\n"); - - device_initcall(redwood6_platform_add_devices); -} - -void __init -redwood6_map_io(void) -{ - int i; - - ppc4xx_map_io(); - for (i = 0; i < 16; i++) { - unsigned long v, p; - - /* 0x400x0000 -> 0xe00x0000 */ - p = 0x40000000 | (i << 16); - v = STBx25xx_IO_BASE | (i << 16); - - io_block_mapping(v, p, PAGE_SIZE, - _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) | - _PAGE_GUARDED); - } -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = redwood6_setup_arch; - ppc_md.setup_io_mappings = redwood6_map_io; -} diff --git a/arch/ppc/platforms/4xx/redwood6.h b/arch/ppc/platforms/4xx/redwood6.h deleted file mode 100644 index 1edcbe5c51c7..000000000000 --- a/arch/ppc/platforms/4xx/redwood6.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Macros, definitions, and data structures specific to the IBM PowerPC - * STBx25xx "Redwood6" evaluation board. - * - * Author: Armin Kuster - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_REDWOOD5_H__ -#define __ASM_REDWOOD5_H__ - -/* Redwood6 has an STBx25xx core */ -#include - -#ifndef __ASSEMBLY__ -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned int bi_dummy; /* field shouldn't exist */ - unsigned char bi_enetaddr[6]; /* Ethernet MAC address */ - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* Bus speed, in Hz */ - unsigned int bi_tbfreq; /* Software timebase freq */ -} bd_t; -#endif /* !__ASSEMBLY__ */ - -#define SMC91111_BASE_ADDR 0xf2030300 -#define SMC91111_REG_SIZE 16 -#define SMC91111_IRQ 27 -#define IDE_XLINUX_MUX_BASE 0xf2040000 -#define IDE_DMA_ADDR 0xfce00000 - -#ifdef MAX_HWIFS -#undef MAX_HWIFS -#endif -#define MAX_HWIFS 1 - -#define _IO_BASE 0 -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 - -#define BASE_BAUD (378000000 / 18 / 16) - -#define PPC4xx_MACHINE_NAME "IBM Redwood6" - -#endif /* __ASM_REDWOOD5_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c deleted file mode 100644 index 8689f3e8ef3a..000000000000 --- a/arch/ppc/platforms/4xx/sycamore.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Architecture- / platform-specific boot-time initialization code for - * IBM PowerPC 4xx based boards. - * - * Author: Armin Kuster - * - * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -void *kb_cs; -void *kb_data; -void *sycamore_rtc_base; - -/* - * Define external IRQ senses and polarities. - */ -unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 10 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 11 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 12 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */ -}; - - -/* Some IRQs unique to Sycamore. - * Used by the generic 405 PCI setup functions in ppc4xx_pci.c - */ -int __init -ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */ - {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */ - {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */ - {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */ - }; - - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -}; - -void __init -sycamore_setup_arch(void) -{ - void *fpga_brdc; - unsigned char fpga_brdc_data; - void *fpga_enable; - void *fpga_polarity; - void *fpga_status; - void *fpga_trigger; - - ppc4xx_setup_arch(); - - ibm_ocp_set_emac(0, 0); - - kb_data = ioremap(SYCAMORE_PS2_BASE, 8); - if (!kb_data) { - printk(KERN_CRIT - "sycamore_setup_arch() kb_data ioremap failed\n"); - return; - } - - kb_cs = kb_data + 1; - - fpga_status = ioremap(PPC40x_FPGA_BASE, 8); - if (!fpga_status) { - printk(KERN_CRIT - "sycamore_setup_arch() fpga_status ioremap failed\n"); - return; - } - - fpga_enable = fpga_status + 1; - fpga_polarity = fpga_status + 2; - fpga_trigger = fpga_status + 3; - fpga_brdc = fpga_status + 4; - - /* split the keyboard and mouse interrupts */ - fpga_brdc_data = readb(fpga_brdc); - fpga_brdc_data |= 0x80; - writeb(fpga_brdc_data, fpga_brdc); - - writeb(0x3, fpga_enable); - - writeb(0x3, fpga_polarity); - - writeb(0x3, fpga_trigger); - - /* RTC step for the sycamore */ - sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR; - TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base, - sycamore_rtc_base, 8); - - /* Identify the system */ - printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n"); - printk(KERN_INFO - "Port by MontaVista Software, Inc. (source@mvista.com)\n"); -} - -void __init -bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) -{ -#ifdef CONFIG_PCI - unsigned int bar_response, bar; - /* - * Expected PCI mapping: - * - * PLB addr PCI memory addr - * --------------------- --------------------- - * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff - * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff - * - * PLB addr PCI io addr - * --------------------- --------------------- - * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 - * - * The following code is simplified by assuming that the bootrom - * has been well behaved in following this mapping. - */ - -#ifdef DEBUG - int i; - - printk("ioremap PCLIO_BASE = 0x%x\n", pcip); - printk("PCI bridge regs before fixup \n"); - for (i = 0; i <= 3; i++) { - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); - } - printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); - printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); - printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); - printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); - -#endif - - /* added for IBM boot rom version 1.15 bios bar changes -AK */ - - /* Disable region first */ - out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); - /* PLB starting addr, PCI: 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].la), 0x80000000); - /* PCI start addr, 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); - /* 512MB range of PLB to PCI */ - out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); - /* Enable no pre-fetch, enable region */ - out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - - (PPC405_PCI_UPPER_MEM - - PPC405_PCI_MEM_BASE)) | 0x01)); - - /* Enable inbound region one - 1GB size */ - out_le32((void *) &(pcip->ptm1ms), 0xc0000001); - - /* Disable outbound region one */ - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[1].la), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - - /* Disable inbound region two */ - out_le32((void *) &(pcip->ptm2ms), 0x00000000); - - /* Disable outbound region two */ - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[2].la), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - - /* Zero config bars */ - for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { - early_write_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - 0x00000000); - early_read_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - &bar_response); - DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", - hose->first_busno, PCI_SLOT(hose->first_busno), - PCI_FUNC(hose->first_busno), bar, bar_response); - } - /* end workaround */ - -#ifdef DEBUG - printk("PCI bridge regs after fixup \n"); - for (i = 0; i <= 3; i++) { - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); - } - printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); - printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); - printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); - printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); - -#endif -#endif - -} - -void __init -sycamore_map_io(void) -{ - ppc4xx_map_io(); - io_block_mapping(SYCAMORE_RTC_VADDR, - SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = sycamore_setup_arch; - ppc_md.setup_io_mappings = sycamore_map_io; - -#ifdef CONFIG_GEN_RTC - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; -#endif -} diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h deleted file mode 100644 index 69b169eac053..000000000000 --- a/arch/ppc/platforms/4xx/sycamore.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Sycamore board definitions - * - * Copyright (c) 2005 DENX Software Engineering - * Stefan Roese - * - * Based on original work by - * Armin Kuster - * 2000 (c) MontaVista, Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_SYCAMORE_H__ -#define __ASM_SYCAMORE_H__ - -#include -#include - -/* Memory map for the IBM "Sycamore" 405GPr evaluation board. - * Generic 4xx plus RTC. - */ - -#define SYCAMORE_RTC_PADDR ((uint)0xf0000000) -#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR -#define SYCAMORE_RTC_SIZE ((uint)8*1024) - -#define BASE_BAUD 691200 - -#define SYCAMORE_PS2_BASE 0xF0100000 - -/* Flash */ -#define PPC40x_FPGA_BASE 0xF0300000 -#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */ -#define PPC40x_FLASH_ONBD_N(x) (x & 0x02) -#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01) -#define PPC40x_FLASH_LOW 0xFFF00000 -#define PPC40x_FLASH_HIGH 0xFFF80000 -#define PPC40x_FLASH_SIZE 0x80000 - -#define PPC4xx_MACHINE_NAME "IBM Sycamore" - -#endif /* __ASM_SYCAMORE_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c deleted file mode 100644 index 115694275083..000000000000 --- a/arch/ppc/platforms/4xx/taishan.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * arch/ppc/platforms/4xx/taishan.c - * - * AMCC Taishan board specific routines - * - * Copyright 2007 DENX Software Engineering, Stefan Roese - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -extern bd_t __res; - -static struct ibm44x_clocks clocks __initdata; - -/* - * NOR FLASH configuration (using mtd physmap driver) - */ - -/* start will be added dynamically, end is always fixed */ -static struct resource taishan_nor_resource = { - .start = TAISHAN_FLASH_ADDR, - .end = 0x1ffffffffULL, - .flags = IORESOURCE_MEM, -}; - -#define RW_PART0_OF 0 -#define RW_PART0_SZ 0x180000 -#define RW_PART1_SZ 0x200000 -/* Partition 2 will be autosized dynamically... */ -#define RW_PART3_SZ 0x80000 -#define RW_PART4_SZ 0x40000 - -static struct mtd_partition taishan_nor_parts[] = { - { - .name = "kernel", - .offset = 0, - .size = RW_PART0_SZ - }, - { - .name = "root", - .offset = MTDPART_OFS_APPEND, - .size = RW_PART1_SZ, - }, - { - .name = "user", - .offset = MTDPART_OFS_APPEND, -/* .size = RW_PART2_SZ */ /* will be adjusted dynamically */ - }, - { - .name = "env", - .offset = MTDPART_OFS_APPEND, - .size = RW_PART3_SZ, - }, - { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = RW_PART4_SZ, - } -}; - -static struct physmap_flash_data taishan_nor_data = { - .width = 4, - .parts = taishan_nor_parts, - .nr_parts = ARRAY_SIZE(taishan_nor_parts), -}; - -static struct platform_device taishan_nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &taishan_nor_data, - }, - .num_resources = 1, - .resource = &taishan_nor_resource, -}; - -static int taishan_setup_flash(void) -{ - /* - * Adjust partition 2 to flash size - */ - taishan_nor_parts[2].size = __res.bi_flashsize - - RW_PART0_SZ - RW_PART1_SZ - RW_PART3_SZ - RW_PART4_SZ; - - platform_device_register(&taishan_nor_device); - - return 0; -} -arch_initcall(taishan_setup_flash); - -static void __init -taishan_calibrate_decr(void) -{ - unsigned int freq; - - if (mfspr(SPRN_CCR1) & CCR1_TCS) - freq = TAISHAN_TMR_CLK; - else - freq = clocks.cpu; - - ibm44x_calibrate_decr(freq); -} - -static int -taishan_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: AMCC\n"); - seq_printf(m, "machine\t\t: PPC440GX EVB (Taishan)\n"); - ibm440gx_show_cpuinfo(m); - return 0; -} - -static inline int -taishan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 23, 24, 25, 26 }, /* IDSEL 1 - PCI Slot 0 */ - { 24, 25, 26, 23 }, /* IDSEL 2 - PCI Slot 1 */ - }; - - const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -static void __init taishan_set_emacdata(void) -{ - struct ocp_def *def; - struct ocp_func_emac_data *emacdata; - int i; - - /* Set phy_map, phy_mode, and mac_addr for each EMAC */ - for (i=2; i<4; i++) { - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); - emacdata = def->additions; - if (i < 2) { - emacdata->phy_map = 0x00000001; /* Skip 0x00 */ - emacdata->phy_mode = PHY_MODE_SMII; - } else { - emacdata->phy_map = 0x00000001; /* Skip 0x00 */ - emacdata->phy_mode = PHY_MODE_RGMII; - } - if (i == 0) - memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6); - else if (i == 1) - memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6); - else if (i == 2) - memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); - else if (i == 3) - memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); - } -} - -#define PCIX_READW(offset) \ - (readw(pcix_reg_base+offset)) - -#define PCIX_WRITEW(value, offset) \ - (writew(value, pcix_reg_base+offset)) - -#define PCIX_WRITEL(value, offset) \ - (writel(value, pcix_reg_base+offset)) - -/* - * FIXME: This is only here to "make it work". This will move - * to a ibm_pcix.c which will contain a generic IBM PCIX bridge - * configuration library. -Matt - */ -static void __init -taishan_setup_pcix(void) -{ - void *pcix_reg_base; - - pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); - - /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ - PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); - - /* Disable all windows */ - PCIX_WRITEL(0, PCIX0_POM0SA); - PCIX_WRITEL(0, PCIX0_POM1SA); - PCIX_WRITEL(0, PCIX0_POM2SA); - PCIX_WRITEL(0, PCIX0_PIM0SA); - PCIX_WRITEL(0, PCIX0_PIM0SAH); - PCIX_WRITEL(0, PCIX0_PIM1SA); - PCIX_WRITEL(0, PCIX0_PIM2SA); - PCIX_WRITEL(0, PCIX0_PIM2SAH); - - /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ - PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); - PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); - PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); - PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); - PCIX_WRITEL(0x80000001, PCIX0_POM0SA); - - /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ - PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); - PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); - PCIX_WRITEL(0x80000007, PCIX0_PIM0SA); - PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH); - - iounmap(pcix_reg_base); - - eieio(); -} - -static void __init -taishan_setup_hose(void) -{ - struct pci_controller *hose; - - /* Configure windows on the PCI-X host bridge */ - taishan_setup_pcix(); - - hose = pcibios_alloc_controller(); - - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - hose->pci_mem_offset = TAISHAN_PCI_MEM_OFFSET; - - pci_init_resource(&hose->io_resource, - TAISHAN_PCI_LOWER_IO, - TAISHAN_PCI_UPPER_IO, - IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource(&hose->mem_resources[0], - TAISHAN_PCI_LOWER_MEM, - TAISHAN_PCI_UPPER_MEM, - IORESOURCE_MEM, - "PCI host bridge"); - - hose->io_space.start = TAISHAN_PCI_LOWER_IO; - hose->io_space.end = TAISHAN_PCI_UPPER_IO; - hose->mem_space.start = TAISHAN_PCI_LOWER_MEM; - hose->mem_space.end = TAISHAN_PCI_UPPER_MEM; - hose->io_base_virt = ioremap64(TAISHAN_PCI_IO_BASE, TAISHAN_PCI_IO_SIZE); - isa_io_base = (unsigned long) hose->io_base_virt; - - setup_indirect_pci(hose, - TAISHAN_PCI_CFGA_PLB32, - TAISHAN_PCI_CFGD_PLB32); - hose->set_cfg_type = 1; - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = taishan_map_irq; -} - - -static void __init -taishan_early_serial_map(void) -{ - struct uart_port port; - - /* Setup ioremapped serial port access */ - memset(&port, 0, sizeof(port)); - port.membase = ioremap64(PPC440GX_UART0_ADDR, 8); - port.irq = UART0_INT; - port.uartclk = clocks.uart0; - port.regshift = 0; - port.iotype = UPIO_MEM; - port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - port.line = 0; - - if (early_serial_setup(&port) != 0) - printk("Early serial init of port 0 failed\n"); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Configure debug serial access */ - gen550_init(0, &port); - - /* Purge TLB entry added in head_44x.S for early serial access */ - _tlbie(UART0_IO_BASE, 0); -#endif - - port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); - port.irq = UART1_INT; - port.uartclk = clocks.uart1; - port.line = 1; - - if (early_serial_setup(&port) != 0) - printk("Early serial init of port 1 failed\n"); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Configure debug serial access */ - gen550_init(1, &port); -#endif -} - -static void __init -taishan_setup_arch(void) -{ - taishan_set_emacdata(); - - ibm440gx_tah_enable(); - - /* - * Determine various clocks. - * To be completely correct we should get SysClk - * from FPGA, because it can be changed by on-board switches - * --ebs - */ - ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); - ocp_sys_info.opb_bus_freq = clocks.opb; - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - - /* Setup PCI host bridge */ - taishan_setup_hose(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_HDA1; -#endif - - taishan_early_serial_map(); - - /* Identify the system */ - printk("AMCC PowerPC 440GX Taishan Platform\n"); -} - -static void __init taishan_init(void) -{ - ibm440gx_l2c_setup(&clocks); -} - -void __init platform_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, unsigned long r7) -{ - ibm44x_platform_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = taishan_setup_arch; - ppc_md.show_cpuinfo = taishan_show_cpuinfo; - ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ - - ppc_md.calibrate_decr = taishan_calibrate_decr; - -#ifdef CONFIG_KGDB - ppc_md.early_serial_map = taishan_early_serial_map; -#endif - ppc_md.init = taishan_init; -} - diff --git a/arch/ppc/platforms/4xx/taishan.h b/arch/ppc/platforms/4xx/taishan.h deleted file mode 100644 index ea7561a80457..000000000000 --- a/arch/ppc/platforms/4xx/taishan.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * arch/ppc/platforms/4xx/taishan.h - * - * AMCC Taishan board definitions - * - * Copyright 2007 DENX Software Engineering, Stefan Roese - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_TAISHAN_H__ -#define __ASM_TAISHAN_H__ - -#include - -/* External timer clock frequency */ -#define TAISHAN_TMR_CLK 25000000 - -/* Flash */ -#define TAISHAN_FPGA_ADDR 0x0000000141000000ULL -#define TAISHAN_LCM_ADDR 0x0000000142000000ULL -#define TAISHAN_FLASH_ADDR 0x00000001fc000000ULL -#define TAISHAN_FLASH_SIZE 0x4000000 - -/* - * Serial port defines - */ -#define RS_TABLE_SIZE 2 - -/* head_44x.S created UART mapping, used before early_serial_setup. - * We cannot use default OpenBIOS UART mappings because they - * don't work for configurations with more than 512M RAM. --ebs - */ -#define UART0_IO_BASE 0xF0000200 -#define UART1_IO_BASE 0xF0000300 - -#define BASE_BAUD 11059200/16 -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (void*)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) - -/* PCI support */ -#define TAISHAN_PCI_LOWER_IO 0x00000000 -#define TAISHAN_PCI_UPPER_IO 0x0000ffff -#define TAISHAN_PCI_LOWER_MEM 0x80000000 -#define TAISHAN_PCI_UPPER_MEM 0xffffefff - -#define TAISHAN_PCI_CFGA_PLB32 0x0ec00000 -#define TAISHAN_PCI_CFGD_PLB32 0x0ec00004 - -#define TAISHAN_PCI_IO_BASE 0x0000000208000000ULL -#define TAISHAN_PCI_IO_SIZE 0x00010000 -#define TAISHAN_PCI_MEM_OFFSET 0x00000000 - -#endif /* __ASM_TAISHAN_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h deleted file mode 100644 index 738280420be5..000000000000 --- a/arch/ppc/platforms/4xx/virtex.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Basic Virtex platform defines, included by - * - * 2005-2007 (c) Secret Lab Technologies Ltd. - * 2002-2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_VIRTEX_H__ -#define __ASM_VIRTEX_H__ - -#include -#include - -/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */ -#if !defined(BASE_BAUD) - #define BASE_BAUD (0) /* dummy value; not used */ -#endif - -#ifndef __ASSEMBLY__ -extern const char* virtex_machine_name; -#define PPC4xx_MACHINE_NAME (virtex_machine_name) -#endif /* !__ASSEMBLY__ */ - -/* We don't need anything mapped. Size of zero will accomplish that. */ -#define PPC4xx_ONB_IO_PADDR 0u -#define PPC4xx_ONB_IO_VADDR 0u -#define PPC4xx_ONB_IO_SIZE 0u - -#endif /* __ASM_VIRTEX_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c deleted file mode 100644 index 2f9772340854..000000000000 --- a/arch/ppc/platforms/4xx/walnut.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Architecture- / platform-specific boot-time initialization code for - * IBM PowerPC 4xx based boards. Adapted from original - * code by Gary Thomas, Cort Dougan , and Dan Malek - * . - * - * Copyright(c) 1999-2000 Grant Erickson - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -void *kb_cs; -void *kb_data; -void *walnut_rtc_base; - -/* Some IRQs unique to Walnut. - * Used by the generic 405 PCI setup functions in ppc4xx_pci.c - */ -int __init -ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */ - {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */ - {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */ - {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */ - }; - - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -}; - -void __init -walnut_setup_arch(void) -{ - - void *fpga_brdc; - unsigned char fpga_brdc_data; - void *fpga_enable; - void *fpga_polarity; - void *fpga_status; - void *fpga_trigger; - - ppc4xx_setup_arch(); - - ibm_ocp_set_emac(0, 0); - - kb_data = ioremap(WALNUT_PS2_BASE, 8); - if (!kb_data) { - printk(KERN_CRIT - "walnut_setup_arch() kb_data ioremap failed\n"); - return; - } - - kb_cs = kb_data + 1; - - fpga_status = ioremap(PPC40x_FPGA_BASE, 8); - if (!fpga_status) { - printk(KERN_CRIT - "walnut_setup_arch() fpga_status ioremap failed\n"); - return; - } - - fpga_enable = fpga_status + 1; - fpga_polarity = fpga_status + 2; - fpga_trigger = fpga_status + 3; - fpga_brdc = fpga_status + 4; - - /* split the keyboard and mouse interrupts */ - fpga_brdc_data = readb(fpga_brdc); - fpga_brdc_data |= 0x80; - writeb(fpga_brdc_data, fpga_brdc); - - writeb(0x3, fpga_enable); - - writeb(0x3, fpga_polarity); - - writeb(0x3, fpga_trigger); - - /* RTC step for the walnut */ - walnut_rtc_base = (void *) WALNUT_RTC_VADDR; - TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base, - walnut_rtc_base, 8); - /* Identify the system */ - printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n"); -} - -void __init -bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) -{ -#ifdef CONFIG_PCI - unsigned int bar_response, bar; - /* - * Expected PCI mapping: - * - * PLB addr PCI memory addr - * --------------------- --------------------- - * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff - * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff - * - * PLB addr PCI io addr - * --------------------- --------------------- - * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 - * - * The following code is simplified by assuming that the bootrom - * has been well behaved in following this mapping. - */ - -#ifdef DEBUG - int i; - - printk("ioremap PCLIO_BASE = 0x%x\n", pcip); - printk("PCI bridge regs before fixup \n"); - for (i = 0; i <= 3; i++) { - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); - } - printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); - printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); - printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); - printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); - -#endif - - /* added for IBM boot rom version 1.15 bios bar changes -AK */ - - /* Disable region first */ - out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); - /* PLB starting addr, PCI: 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].la), 0x80000000); - /* PCI start addr, 0x80000000 */ - out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); - /* 512MB range of PLB to PCI */ - out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); - /* Enable no pre-fetch, enable region */ - out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - - (PPC405_PCI_UPPER_MEM - - PPC405_PCI_MEM_BASE)) | 0x01)); - - /* Disable region one */ - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[1].la), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); - out_le32((void *) &(pcip->ptm1ms), 0x00000000); - - /* Disable region two */ - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->pmm[2].la), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); - out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); - out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); - out_le32((void *) &(pcip->ptm2ms), 0x00000000); - - /* Zero config bars */ - for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { - early_write_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - 0x00000000); - early_read_config_dword(hose, hose->first_busno, - PCI_FUNC(hose->first_busno), bar, - &bar_response); - DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", - hose->first_busno, PCI_SLOT(hose->first_busno), - PCI_FUNC(hose->first_busno), bar, bar_response); - } - /* end work around */ - -#ifdef DEBUG - printk("PCI bridge regs after fixup \n"); - for (i = 0; i <= 3; i++) { - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); - printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); - } - printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); - printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); - printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); - printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); - -#endif -#endif -} - -void __init -walnut_map_io(void) -{ - ppc4xx_map_io(); - io_block_mapping(WALNUT_RTC_VADDR, - WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = walnut_setup_arch; - ppc_md.setup_io_mappings = walnut_map_io; - -#ifdef CONFIG_GEN_RTC - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; -#endif -} diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h deleted file mode 100644 index d9c4eb788940..000000000000 --- a/arch/ppc/platforms/4xx/walnut.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Walnut board definitions - * - * Copyright (c) 2005 DENX Software Engineering - * Stefan Roese - * - * Based on original work by - * Copyright (c) 1999 Grant Erickson - * Frank Rowand - * Debbie Chu - * 2000 (c) MontaVista, Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_WALNUT_H__ -#define __ASM_WALNUT_H__ - -#include -#include - -/* Memory map for the IBM "Walnut" 405GP evaluation board. - * Generic 4xx plus RTC. - */ - -#define WALNUT_RTC_PADDR ((uint)0xf0000000) -#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR -#define WALNUT_RTC_SIZE ((uint)8*1024) - -#define BASE_BAUD 691200 - -#define WALNUT_PS2_BASE 0xF0100000 - -/* Flash */ -#define PPC40x_FPGA_BASE 0xF0300000 -#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */ -#define PPC40x_FLASH_ONBD_N(x) (x & 0x02) -#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01) -#define PPC40x_FLASH_LOW 0xFFF00000 -#define PPC40x_FLASH_HIGH 0xFFF80000 -#define PPC40x_FLASH_SIZE 0x80000 -#define WALNUT_FPGA_BASE PPC40x_FPGA_BASE - -#define PPC4xx_MACHINE_NAME "IBM Walnut" - -#endif /* __ASM_WALNUT_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c deleted file mode 100644 index 6e522fefc26f..000000000000 --- a/arch/ppc/platforms/4xx/xilinx_ml300.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Xilinx ML300 evaluation board initialization - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/* - * As an overview of how the following functions (platform_init, - * ml300_map_io, ml300_setup_arch and ml300_init_IRQ) fit into the - * kernel startup procedure, here's a call tree: - * - * start_here arch/ppc/kernel/head_4xx.S - * early_init arch/ppc/kernel/setup.c - * machine_init arch/ppc/kernel/setup.c - * platform_init this file - * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c - * parse_bootinfo - * find_bootinfo - * "setup some default ppc_md pointers" - * MMU_init arch/ppc/mm/init.c - * *ppc_md.setup_io_mappings == ml300_map_io this file - * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c - * start_kernel init/main.c - * setup_arch arch/ppc/kernel/setup.c - * #if defined(CONFIG_KGDB) - * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc - * #endif - * *ppc_md.setup_arch == ml300_setup_arch this file - * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c - * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c - * init_IRQ arch/ppc/kernel/irq.c - * *ppc_md.init_IRQ == ml300_init_IRQ this file - * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c - * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c - */ - -const char* virtex_machine_name = "ML300 Reference Design"; - -#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) -static volatile unsigned *powerdown_base = - (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR; - -static void -xilinx_power_off(void) -{ - local_irq_disable(); - out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE); - while (1) ; -} -#endif - -void __init -ml300_map_io(void) -{ - ppc4xx_map_io(); - -#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) - powerdown_base = ioremap((unsigned long) powerdown_base, - XPAR_POWER_0_POWERDOWN_HIGHADDR - - XPAR_POWER_0_POWERDOWN_BASEADDR + 1); -#endif -} - -void __init -ml300_setup_arch(void) -{ - virtex_early_serial_map(); - ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ - - /* Identify the system */ - printk(KERN_INFO "Xilinx ML300 Reference System (Virtex-II Pro)\n"); -} - -/* Called after board_setup_irq from ppc4xx_init_IRQ(). */ -void __init -ml300_init_irq(void) -{ - ppc4xx_init_IRQ(); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = ml300_setup_arch; - ppc_md.setup_io_mappings = ml300_map_io; - ppc_md.init_IRQ = ml300_init_irq; - -#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) - ppc_md.power_off = xilinx_power_off; -#endif - -#ifdef CONFIG_KGDB - ppc_md.early_serial_map = virtex_early_serial_map; -#endif -} - diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c deleted file mode 100644 index bc3ace3762e7..000000000000 --- a/arch/ppc/platforms/4xx/xilinx_ml403.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Xilinx ML403 evaluation board initialization - * - * Author: Grant Likely - * - * 2005-2007 (c) Secret Lab Technologies Ltd. - * 2002-2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/* - * As an overview of how the following functions (platform_init, - * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the - * kernel startup procedure, here's a call tree: - * - * start_here arch/ppc/kernel/head_4xx.S - * early_init arch/ppc/kernel/setup.c - * machine_init arch/ppc/kernel/setup.c - * platform_init this file - * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c - * parse_bootinfo - * find_bootinfo - * "setup some default ppc_md pointers" - * MMU_init arch/ppc/mm/init.c - * *ppc_md.setup_io_mappings == ml403_map_io this file - * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c - * start_kernel init/main.c - * setup_arch arch/ppc/kernel/setup.c - * #if defined(CONFIG_KGDB) - * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc - * #endif - * *ppc_md.setup_arch == ml403_setup_arch this file - * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c - * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c - * init_IRQ arch/ppc/kernel/irq.c - * *ppc_md.init_IRQ == ml403_init_IRQ this file - * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c - * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c - */ - -const char* virtex_machine_name = "ML403 Reference Design"; - -#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) -static volatile unsigned *powerdown_base = - (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR; - -static void -xilinx_power_off(void) -{ - local_irq_disable(); - out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE); - while (1) ; -} -#endif - -void __init -ml403_map_io(void) -{ - ppc4xx_map_io(); - -#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) - powerdown_base = ioremap((unsigned long) powerdown_base, - XPAR_POWER_0_POWERDOWN_HIGHADDR - - XPAR_POWER_0_POWERDOWN_BASEADDR + 1); -#endif -} - -void __init -ml403_setup_arch(void) -{ - virtex_early_serial_map(); - ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ - - /* Identify the system */ - printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n"); -} - -/* Called after board_setup_irq from ppc4xx_init_IRQ(). */ -void __init -ml403_init_irq(void) -{ - ppc4xx_init_IRQ(); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - ppc4xx_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = ml403_setup_arch; - ppc_md.setup_io_mappings = ml403_map_io; - ppc_md.init_IRQ = ml403_init_irq; - -#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) - ppc_md.power_off = xilinx_power_off; -#endif - -#ifdef CONFIG_KGDB - ppc_md.early_serial_map = virtex_early_serial_map; -#endif -} - diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h deleted file mode 100644 index 650888b00fb0..000000000000 --- a/arch/ppc/platforms/4xx/xparameters/xparameters.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * arch/ppc/platforms/4xx/xparameters/xparameters.h - * - * This file includes the correct xparameters.h for the CONFIG'ed board plus - * fixups to translate board specific XPAR values to a common set of names - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms - * of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - - -#if defined(CONFIG_XILINX_ML300) - #include "xparameters_ml300.h" - #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \ - XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR - #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \ - XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR -#elif defined(CONFIG_XILINX_ML403) - #include "xparameters_ml403.h" - #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \ - XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR - #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \ - XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR -#else - /* Add other board xparameter includes here before the #else */ - #error No xparameters_*.h file included -#endif - -#ifndef SERIAL_PORT_DFNS - /* zImage serial port definitions */ - #define RS_TABLE_SIZE 1 - #define SERIAL_PORT_DFNS { \ - .baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \ - .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \ - .flags = ASYNC_BOOT_AUTOCONF, \ - .iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM, \ - }, -#endif - -/* - * A few reasonable defaults for the #defines which could be missing depending - * on the IP version or variant (e.g. OPB vs PLB) - */ - -#ifndef XPAR_EMAC_0_CAM_EXIST -#define XPAR_EMAC_0_CAM_EXIST 0 -#endif -#ifndef XPAR_EMAC_0_JUMBO_EXIST -#define XPAR_EMAC_0_JUMBO_EXIST 0 -#endif -#ifndef XPAR_EMAC_0_TX_DRE_TYPE -#define XPAR_EMAC_0_TX_DRE_TYPE 0 -#endif -#ifndef XPAR_EMAC_0_RX_DRE_TYPE -#define XPAR_EMAC_0_RX_DRE_TYPE 0 -#endif -#ifndef XPAR_EMAC_0_TX_INCLUDE_CSUM -#define XPAR_EMAC_0_TX_INCLUDE_CSUM 0 -#endif -#ifndef XPAR_EMAC_0_RX_INCLUDE_CSUM -#define XPAR_EMAC_0_RX_INCLUDE_CSUM 0 -#endif - -#ifndef XPAR_EMAC_1_CAM_EXIST -#define XPAR_EMAC_1_CAM_EXIST 0 -#endif -#ifndef XPAR_EMAC_1_JUMBO_EXIST -#define XPAR_EMAC_1_JUMBO_EXIST 0 -#endif -#ifndef XPAR_EMAC_1_TX_DRE_TYPE -#define XPAR_EMAC_1_TX_DRE_TYPE 0 -#endif -#ifndef XPAR_EMAC_1_RX_DRE_TYPE -#define XPAR_EMAC_1_RX_DRE_TYPE 0 -#endif -#ifndef XPAR_EMAC_1_TX_INCLUDE_CSUM -#define XPAR_EMAC_1_TX_INCLUDE_CSUM 0 -#endif -#ifndef XPAR_EMAC_1_RX_INCLUDE_CSUM -#define XPAR_EMAC_1_RX_INCLUDE_CSUM 0 -#endif - -#ifndef XPAR_GPIO_0_IS_DUAL -#define XPAR_GPIO_0_IS_DUAL 0 -#endif -#ifndef XPAR_GPIO_1_IS_DUAL -#define XPAR_GPIO_1_IS_DUAL 0 -#endif -#ifndef XPAR_GPIO_2_IS_DUAL -#define XPAR_GPIO_2_IS_DUAL 0 -#endif -#ifndef XPAR_GPIO_3_IS_DUAL -#define XPAR_GPIO_3_IS_DUAL 0 -#endif -#ifndef XPAR_GPIO_4_IS_DUAL -#define XPAR_GPIO_4_IS_DUAL 0 -#endif - diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h deleted file mode 100644 index 97e3f4d4bd54..000000000000 --- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h +++ /dev/null @@ -1,310 +0,0 @@ -/******************************************************************* -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -* Description: Driver parameters -* -*******************************************************************/ - -#define XPAR_XPCI_NUM_INSTANCES 1 -#define XPAR_XPCI_CLOCK_HZ 33333333 -#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0 -#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000 -#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF -#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000 -#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004 -#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000 -#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000 -#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF -#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000 -#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF - -/******************************************************************/ - -#define XPAR_XEMAC_NUM_INSTANCES 1 -#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 -#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF -#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 -#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 -#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 -#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 - -/******************************************************************/ - -#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0 -#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000 -#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7) -#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1 -#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8) -#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F) -#define XPAR_XGPIO_NUM_INSTANCES 2 - -/******************************************************************/ - -#define XPAR_XIIC_NUM_INSTANCES 1 -#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 -#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF -#define XPAR_OPB_IIC_0_DEVICE_ID 0 -#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 - -/******************************************************************/ - -#define XPAR_XUARTNS550_NUM_INSTANCES 2 -#define XPAR_XUARTNS550_CLOCK_HZ 100000000 -#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 -#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF -#define XPAR_OPB_UART16550_0_DEVICE_ID 0 -#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000 -#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF -#define XPAR_OPB_UART16550_1_DEVICE_ID 1 - -/******************************************************************/ - -#define XPAR_XSPI_NUM_INSTANCES 1 -#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000 -#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F -#define XPAR_OPB_SPI_0_DEVICE_ID 0 -#define XPAR_OPB_SPI_0_FIFO_EXIST 1 -#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0 -#define XPAR_OPB_SPI_0_NUM_SS_BITS 1 - -/******************************************************************/ - -#define XPAR_XPS2_NUM_INSTANCES 2 -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) - -/******************************************************************/ - -#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1 -#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000 -#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007 -#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0 - -/******************************************************************/ - -#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 -#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF -#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000 -#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF -#define XPAR_PLB_DDR_0_BASEADDR 0x00000000 -#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF - -/******************************************************************/ - -#define XPAR_XINTC_HAS_IPR 1 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18 -#define XPAR_XINTC_USE_DCR 0 -#define XPAR_XINTC_NUM_INSTANCES 1 -#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0 -#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF -#define XPAR_DCR_INTC_0_DEVICE_ID 0 -#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000 - -/******************************************************************/ - -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0 -#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1 -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2 -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3 -#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4 -#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5 -#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6 -#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7 -#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 -#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9 -#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10 -#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11 -#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12 -#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13 -#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14 -#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15 -#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16 -#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17 - -/******************************************************************/ - -#define XPAR_XTFT_NUM_INSTANCES 1 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 -#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 - -/******************************************************************/ - -#define XPAR_XSYSACE_MEM_WIDTH 8 -#define XPAR_XSYSACE_NUM_INSTANCES 1 -#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 -#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF -#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 -#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8 - -/******************************************************************/ - -#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 - -/******************************************************************/ - -/******************************************************************/ - -/* Linux Redefines */ - -/******************************************************************/ - -#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) -#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ -#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID -#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000) -#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR -#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ -#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID - -/******************************************************************/ - -#define XPAR_GPIO_0_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_0 -#define XPAR_GPIO_0_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_0 -#define XPAR_GPIO_0_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 -#define XPAR_GPIO_1_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_1 -#define XPAR_GPIO_1_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_1 -#define XPAR_GPIO_1_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 - -/******************************************************************/ - -#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR -#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR -#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR -#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR -#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR -#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_INTC_0_BASEADDR XPAR_DCR_INTC_0_BASEADDR -#define XPAR_INTC_0_HIGHADDR XPAR_DCR_INTC_0_HIGHADDR -#define XPAR_INTC_0_KIND_OF_INTR XPAR_DCR_INTC_0_KIND_OF_INTR -#define XPAR_INTC_0_DEVICE_ID XPAR_DCR_INTC_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR -#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR -#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR -#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR -#define XPAR_INTC_0_UARTNS550_1_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR -#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR -#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR -#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR -#define XPAR_INTC_0_TOUCHSCREEN_0_VEC_ID XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR -#define XPAR_INTC_0_PCI_0_VEC_ID_A XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR -#define XPAR_INTC_0_PCI_0_VEC_ID_B XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR -#define XPAR_INTC_0_PCI_0_VEC_ID_C XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR -#define XPAR_INTC_0_PCI_0_VEC_ID_D XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR - -/******************************************************************/ - -#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR -#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR -#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT -#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST -#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST -#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_SPI_0_BASEADDR XPAR_OPB_SPI_0_BASEADDR -#define XPAR_SPI_0_HIGHADDR XPAR_OPB_SPI_0_HIGHADDR -#define XPAR_SPI_0_DEVICE_ID XPAR_OPB_SPI_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_TOUCHSCREEN_0_BASEADDR XPAR_OPB_TSD_REF_0_BASEADDR -#define XPAR_TOUCHSCREEN_0_HIGHADDR XPAR_OPB_TSD_REF_0_HIGHADDR -#define XPAR_TOUCHSCREEN_0_DEVICE_ID XPAR_OPB_TSD_REF_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR - -/******************************************************************/ - -#define XPAR_PCI_0_BASEADDR XPAR_OPB_PCI_REF_0_BASEADDR -#define XPAR_PCI_0_HIGHADDR XPAR_OPB_PCI_REF_0_HIGHADDR -#define XPAR_PCI_0_CONFIG_ADDR XPAR_OPB_PCI_REF_0_CONFIG_ADDR -#define XPAR_PCI_0_CONFIG_DATA XPAR_OPB_PCI_REF_0_CONFIG_DATA -#define XPAR_PCI_0_LCONFIG_ADDR XPAR_OPB_PCI_REF_0_LCONFIG_ADDR -#define XPAR_PCI_0_MEM_BASEADDR XPAR_OPB_PCI_REF_0_MEM_BASEADDR -#define XPAR_PCI_0_MEM_HIGHADDR XPAR_OPB_PCI_REF_0_MEM_HIGHADDR -#define XPAR_PCI_0_IO_BASEADDR XPAR_OPB_PCI_REF_0_IO_BASEADDR -#define XPAR_PCI_0_IO_HIGHADDR XPAR_OPB_PCI_REF_0_IO_HIGHADDR -#define XPAR_PCI_0_CLOCK_FREQ_HZ XPAR_XPCI_CLOCK_HZ -#define XPAR_PCI_0_DEVICE_ID XPAR_OPB_PCI_REF_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 -#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 -#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 -#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 -#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 -#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 - -/******************************************************************/ - -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ -#define XPAR_DDR_0_SIZE 0x08000000 - -/******************************************************************/ - -#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 -#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF -#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 - -/******************************************************************/ - -#define XPAR_POWER_0_POWERDOWN_BASEADDR 0x90000004 -#define XPAR_POWER_0_POWERDOWN_HIGHADDR 0x90000007 -#define XPAR_POWER_0_POWERDOWN_VALUE 0xFF - -/******************************************************************/ diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h deleted file mode 100644 index 5cacdcb3964d..000000000000 --- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h +++ /dev/null @@ -1,243 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1 -* DO NOT EDIT. -* -* Copyright (c) 2005 Xilinx, Inc. All rights reserved. -* -* Description: Driver parameters -* -*******************************************************************/ - -#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000 -#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF - -/******************************************************************/ - -#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000 -#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF -#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000 -#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF -#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 -#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF -#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000 -#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF -#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000 -#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF - -/******************************************************************/ - -#define XPAR_XEMAC_NUM_INSTANCES 1 -#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 -#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF -#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 -#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 -#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 -#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 - -/******************************************************************/ - -#define XPAR_XUARTNS550_NUM_INSTANCES 1 -#define XPAR_XUARTNS550_CLOCK_HZ 100000000 -#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 -#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF -#define XPAR_OPB_UART16550_0_DEVICE_ID 0 - -/******************************************************************/ - -#define XPAR_XGPIO_NUM_INSTANCES 3 -#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000 -#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF -#define XPAR_OPB_GPIO_0_DEVICE_ID 0 -#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0 -#define XPAR_OPB_GPIO_0_IS_DUAL 1 -#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000 -#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF -#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1 -#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0 -#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1 -#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000 -#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF -#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2 -#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0 -#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0 - -/******************************************************************/ - -#define XPAR_XPS2_NUM_INSTANCES 2 -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) - -/******************************************************************/ - -#define XPAR_XIIC_NUM_INSTANCES 1 -#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 -#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF -#define XPAR_OPB_IIC_0_DEVICE_ID 0 -#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 -#define XPAR_OPB_IIC_0_GPO_WIDTH 1 - -/******************************************************************/ - -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10 -#define XPAR_XINTC_HAS_IPR 1 -#define XPAR_XINTC_USE_DCR 0 -#define XPAR_XINTC_NUM_INSTANCES 1 -#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0 -#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF -#define XPAR_OPB_INTC_0_DEVICE_ID 0 -#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000 - -/******************************************************************/ - -#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0 -#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF -#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID -#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001 -#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0 -#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002 -#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1 -#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004 -#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2 -#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008 -#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3 -#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010 -#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4 -#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020 -#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5 -#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040 -#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6 -#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080 -#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7 -#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100 -#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 -#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200 -#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9 - -/******************************************************************/ - -#define XPAR_XTFT_NUM_INSTANCES 1 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 -#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 - -/******************************************************************/ - -#define XPAR_XSYSACE_MEM_WIDTH 16 -#define XPAR_XSYSACE_NUM_INSTANCES 1 -#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 -#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF -#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 -#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16 - -/******************************************************************/ - -#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 - -/******************************************************************/ - - -/******************************************************************/ - -/* Linux Redefines */ - -/******************************************************************/ - -#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) -#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ -#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR -#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR -#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR -#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR -#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR -#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR -#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR -#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR -#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR - -/******************************************************************/ - -#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR - -/******************************************************************/ - -#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR -#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR -#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT -#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST -#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST -#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0 -#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0 -#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0 -#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1 -#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1 -#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1 -#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0 -#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0 -#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0 -#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1 -#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1 -#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1 -#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR -#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR -#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 -#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 -#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 -#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 -#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 -#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 - -/******************************************************************/ - -#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR -#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR -#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR -#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR -#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR -#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ -#define XPAR_DDR_0_SIZE 0x4000000 - -/******************************************************************/ - -#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 -#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF -#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 - -/******************************************************************/ - -#define XPAR_PCI_0_CLOCK_FREQ_HZ 0 - -/******************************************************************/ - diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c deleted file mode 100644 index f6cfd44281fc..000000000000 --- a/arch/ppc/platforms/4xx/yucca.c +++ /dev/null @@ -1,393 +0,0 @@ -/* - * Yucca board specific routines - * - * Roland Dreier (based on luan.c by Matt Porter) - * - * Copyright 2004-2005 MontaVista Software Inc. - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -extern bd_t __res; - -static struct ibm44x_clocks clocks __initdata; - -static void __init -yucca_calibrate_decr(void) -{ - unsigned int freq; - - if (mfspr(SPRN_CCR1) & CCR1_TCS) - freq = YUCCA_TMR_CLK; - else - freq = clocks.cpu; - - ibm44x_calibrate_decr(freq); -} - -static int -yucca_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: AMCC\n"); - seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n"); - - return 0; -} - -static enum { - HOSE_UNKNOWN, - HOSE_PCIX, - HOSE_PCIE0, - HOSE_PCIE1, - HOSE_PCIE2 -} hose_type[4]; - -static inline int -yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - - if (hose_type[hose->index] == HOSE_PCIX) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */ - }; - const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } else if (hose_type[hose->index] == HOSE_PCIE0) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 96, 97, 98, 99 }, - }; - const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } else if (hose_type[hose->index] == HOSE_PCIE1) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 100, 101, 102, 103 }, - }; - const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } else if (hose_type[hose->index] == HOSE_PCIE2) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 104, 105, 106, 107 }, - }; - const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } - return -1; -} - -static void __init yucca_set_emacdata(void) -{ - struct ocp_def *def; - struct ocp_func_emac_data *emacdata; - - /* Set phy_map, phy_mode, and mac_addr for the EMAC */ - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); - emacdata = def->additions; - emacdata->phy_map = 0x00000001; /* Skip 0x00 */ - emacdata->phy_mode = PHY_MODE_GMII; - memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); -} - -static int __init yucca_pcie_card_present(int port) -{ - void __iomem *pcie_fpga_base; - u16 reg; - - pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE); - reg = in_be16(pcie_fpga_base + FPGA_REG1C); - iounmap(pcie_fpga_base); - - switch(port) { - case 0: return !(reg & FPGA_REG1C_PE0_PRSNT); - case 1: return !(reg & FPGA_REG1C_PE1_PRSNT); - case 2: return !(reg & FPGA_REG1C_PE2_PRSNT); - default: return 0; - } -} - -/* - * For the given slot, set rootpoint mode, send power to the slot, - * turn on the green LED and turn off the yellow LED, enable the clock - * and turn off reset. - */ -static void __init yucca_setup_pcie_fpga_rootpoint(int port) -{ - void __iomem *pcie_reg_fpga_base; - u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; - - pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE); - - switch(port) { - case 0: - rootpoint = FPGA_REG1C_PE0_ROOTPOINT; - endpoint = 0; - power = FPGA_REG1A_PE0_PWRON; - green_led = FPGA_REG1A_PE0_GLED; - clock = FPGA_REG1A_PE0_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE0_YLED; - reset_off = FPGA_REG1C_PE0_PERST; - break; - case 1: - rootpoint = 0; - endpoint = FPGA_REG1C_PE1_ENDPOINT; - power = FPGA_REG1A_PE1_PWRON; - green_led = FPGA_REG1A_PE1_GLED; - clock = FPGA_REG1A_PE1_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE1_YLED; - reset_off = FPGA_REG1C_PE1_PERST; - break; - case 2: - rootpoint = 0; - endpoint = FPGA_REG1C_PE2_ENDPOINT; - power = FPGA_REG1A_PE2_PWRON; - green_led = FPGA_REG1A_PE2_GLED; - clock = FPGA_REG1A_PE2_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE2_YLED; - reset_off = FPGA_REG1C_PE2_PERST; - break; - - default: - iounmap(pcie_reg_fpga_base); - return; - } - - out_be16(pcie_reg_fpga_base + FPGA_REG1A, - ~(power | clock | green_led) & - (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A))); - out_be16(pcie_reg_fpga_base + FPGA_REG1C, - ~(endpoint | reset_off) & - (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C))); - - /* - * Leave device in reset for a while after powering on the - * slot to give it a chance to initialize. - */ - mdelay(250); - - out_be16(pcie_reg_fpga_base + FPGA_REG1C, - reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C)); - - iounmap(pcie_reg_fpga_base); -} - -static void __init -yucca_setup_hoses(void) -{ - struct pci_controller *hose; - char name[20]; - int i; - - if (0 && ppc440spe_init_pcie()) { - printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n"); - return; - } - - for (i = 0; i <= 2; ++i) { - if (!yucca_pcie_card_present(i)) - continue; - - printk(KERN_INFO "PCIE%d: card present\n", i); - yucca_setup_pcie_fpga_rootpoint(i); - if (ppc440spe_init_pcie_rootport(i)) { - printk(KERN_WARNING "PCIE%d: initialization failed\n", i); - continue; - } - - hose = pcibios_alloc_controller(); - if (!hose) - return; - - sprintf(name, "PCIE%d host bridge", i); - pci_init_resource(&hose->io_resource, - YUCCA_PCIX_LOWER_IO, - YUCCA_PCIX_UPPER_IO, - IORESOURCE_IO, - name); - - hose->mem_space.start = YUCCA_PCIE_LOWER_MEM + - i * YUCCA_PCIE_MEM_SIZE; - hose->mem_space.end = hose->mem_space.start + - YUCCA_PCIE_MEM_SIZE - 1; - - pci_init_resource(&hose->mem_resources[0], - hose->mem_space.start, - hose->mem_space.end, - IORESOURCE_MEM, - name); - - hose->first_busno = 0; - hose->last_busno = 15; - hose_type[hose->index] = HOSE_PCIE0 + i; - - ppc440spe_setup_pcie(hose, i); - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - } - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = yucca_map_irq; -} - -TODC_ALLOC(); - -static void __init -yucca_early_serial_map(void) -{ - struct uart_port port; - - /* Setup ioremapped serial port access */ - memset(&port, 0, sizeof(port)); - port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8); - port.irq = UART0_INT; - port.uartclk = clocks.uart0; - port.regshift = 0; - port.iotype = UPIO_MEM; - port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - port.line = 0; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 0 failed\n"); - } - - port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8); - port.irq = UART1_INT; - port.uartclk = clocks.uart1; - port.line = 1; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 1 failed\n"); - } - - port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8); - port.irq = UART2_INT; - port.uartclk = BASE_BAUD; - port.line = 2; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port 2 failed\n"); - } -} - -static void __init -yucca_setup_arch(void) -{ - yucca_set_emacdata(); - -#if !defined(CONFIG_BDI_SWITCH) - /* - * The Abatron BDI JTAG debugger does not tolerate others - * mucking with the debug registers. - */ - mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); -#endif - - /* - * Determine various clocks. - * To be completely correct we should get SysClk - * from FPGA, because it can be changed by on-board switches - * --ebs - */ - /* 440GX and 440SPe clocking is the same - rd */ - ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); - ocp_sys_info.opb_bus_freq = clocks.opb; - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - - /* Setup PCIXn host bridges */ - yucca_setup_hoses(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_HDA1; -#endif - - yucca_early_serial_map(); - - /* Identify the system */ - printk("Yucca port (Roland Dreier )\n"); -} - -void __init platform_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, unsigned long r7) -{ - ibm44x_platform_init(r3, r4, r5, r6, r7); - - ppc_md.setup_arch = yucca_setup_arch; - ppc_md.show_cpuinfo = yucca_show_cpuinfo; - ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory; - ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ - - ppc_md.calibrate_decr = yucca_calibrate_decr; -#ifdef CONFIG_KGDB - ppc_md.early_serial_map = yucca_early_serial_map; -#endif -} diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h deleted file mode 100644 index bc9684e66a84..000000000000 --- a/arch/ppc/platforms/4xx/yucca.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Yucca board definitions - * - * Roland Dreier (based on luan.h by Matt Porter) - * - * Copyright 2004-2005 MontaVista Software Inc. - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_YUCCA_H__ -#define __ASM_YUCCA_H__ - -#include - -/* F/W TLB mapping used in bootloader glue to reset EMAC */ -#define PPC44x_EMAC0_MR0 0xa0000800 - -/* Location of MAC addresses in PIBS image */ -#define PIBS_FLASH_BASE 0xffe00000 -#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400) - -/* External timer clock frequency */ -#define YUCCA_TMR_CLK 25000000 - -/* - * FPGA registers - */ -#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL -#define YUCCA_FPGA_REG_SIZE 0x24 - -#define FPGA_REG1A 0x1a - -#define FPGA_REG1A_PE0_GLED 0x8000 -#define FPGA_REG1A_PE1_GLED 0x4000 -#define FPGA_REG1A_PE2_GLED 0x2000 -#define FPGA_REG1A_PE0_YLED 0x1000 -#define FPGA_REG1A_PE1_YLED 0x0800 -#define FPGA_REG1A_PE2_YLED 0x0400 -#define FPGA_REG1A_PE0_PWRON 0x0200 -#define FPGA_REG1A_PE1_PWRON 0x0100 -#define FPGA_REG1A_PE2_PWRON 0x0080 -#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040 -#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020 -#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010 -#define FPGA_REG1A_PE_SPREAD0 0x0008 -#define FPGA_REG1A_PE_SPREAD1 0x0004 -#define FPGA_REG1A_PE_SELSOURCE_0 0x0002 -#define FPGA_REG1A_PE_SELSOURCE_1 0x0001 - -#define FPGA_REG1C 0x1c - -#define FPGA_REG1C_PE0_ROOTPOINT 0x8000 -#define FPGA_REG1C_PE1_ENDPOINT 0x4000 -#define FPGA_REG1C_PE2_ENDPOINT 0x2000 -#define FPGA_REG1C_PE0_PRSNT 0x1000 -#define FPGA_REG1C_PE1_PRSNT 0x0800 -#define FPGA_REG1C_PE2_PRSNT 0x0400 -#define FPGA_REG1C_PE0_WAKE 0x0080 -#define FPGA_REG1C_PE1_WAKE 0x0040 -#define FPGA_REG1C_PE2_WAKE 0x0020 -#define FPGA_REG1C_PE0_PERST 0x0010 -#define FPGA_REG1C_PE1_PERST 0x0008 -#define FPGA_REG1C_PE2_PERST 0x0004 - -/* - * Serial port defines - */ -#define RS_TABLE_SIZE 3 - -/* PIBS defined UART mappings, used before early_serial_setup */ -#define UART0_IO_BASE 0xa0000200 -#define UART1_IO_BASE 0xa0000300 -#define UART2_IO_BASE 0xa0000600 - -#define BASE_BAUD 11059200 -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - iomem_base: (void*)UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) \ - STD_UART_OP(2) - -/* PCI support */ -#define YUCCA_PCIX_LOWER_IO 0x00000000 -#define YUCCA_PCIX_UPPER_IO 0x0000ffff -#define YUCCA_PCIX_LOWER_MEM 0x80000000 -#define YUCCA_PCIX_UPPER_MEM 0x8fffffff -#define YUCCA_PCIE_LOWER_MEM 0x90000000 -#define YUCCA_PCIE_MEM_SIZE 0x10000000 - -#define YUCCA_PCIX_MEM_SIZE 0x10000000 -#define YUCCA_PCIX_MEM_OFFSET 0x00000000 -#define YUCCA_PCIE_MEM_SIZE 0x10000000 -#define YUCCA_PCIE_MEM_OFFSET 0x00000000 - -#endif /* __ASM_YUCCA_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile deleted file mode 100644 index 6260231987cb..000000000000 --- a/arch/ppc/platforms/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o -obj-$(CONFIG_PREP_RESIDUAL) += residual.o -obj-$(CONFIG_TQM8260) += tqm8260_setup.o -obj-$(CONFIG_CPCI690) += cpci690.o -obj-$(CONFIG_EV64260) += ev64260.o -obj-$(CONFIG_CHESTNUT) += chestnut.o -obj-$(CONFIG_LOPEC) += lopec.o -obj-$(CONFIG_KATANA) += katana.o -obj-$(CONFIG_HDPU) += hdpu.o -obj-$(CONFIG_MVME5100) += mvme5100.o -obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o -obj-$(CONFIG_POWERPMC250) += powerpmc250.o -obj-$(CONFIG_PPLUS) += pplus.o -obj-$(CONFIG_PRPMC750) += prpmc750.o -obj-$(CONFIG_PRPMC800) += prpmc800.o -obj-$(CONFIG_RADSTONE_PPC7D) += radstone_ppc7d.o -obj-$(CONFIG_SANDPOINT) += sandpoint.o -obj-$(CONFIG_SBC82xx) += sbc82xx.o -obj-$(CONFIG_SPRUCE) += spruce.o -obj-$(CONFIG_LITE5200) += lite5200.o -obj-$(CONFIG_EV64360) += ev64360.o diff --git a/arch/ppc/platforms/bseip.h b/arch/ppc/platforms/bseip.h deleted file mode 100644 index 691f4a52b0a5..000000000000 --- a/arch/ppc/platforms/bseip.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Bright Star Engineering ip-Engine board. Copied from the MBX stuff. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ -#ifndef __MACH_BSEIP_DEFS -#define __MACH_BSEIP_DEFS - -#ifndef __ASSEMBLY__ -/* A Board Information structure that is given to a program when - * prom starts it up. - */ -typedef struct bd_info { - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in Hz */ - unsigned char bi_enetaddr[6]; - unsigned int bi_baudrate; -} bd_t; - -extern bd_t m8xx_board_info; - -/* Memory map is configured by the PROM startup. - * All we need to get started is the IMMR. - */ -#define IMAP_ADDR ((uint)0xff000000) -#define IMAP_SIZE ((uint)(64 * 1024)) -#define PCMCIA_MEM_ADDR ((uint)0x04000000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) -#endif /* !__ASSEMBLY__ */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif diff --git a/arch/ppc/platforms/ccm.h b/arch/ppc/platforms/ccm.h deleted file mode 100644 index 69000b1c7a4c..000000000000 --- a/arch/ppc/platforms/ccm.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Siemens Card Controller Module specific definitions - * - * Copyright (C) 2001-2002 Wolfgang Denk (wd@denx.de) - */ - -#ifndef __MACH_CCM_H -#define __MACH_CCM_H - - -#include - -#define CCM_IMMR_BASE 0xF0000000 /* phys. addr of IMMR */ -#define CCM_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR CCM_IMMR_BASE /* physical base address of IMMR area */ -#define IMAP_SIZE CCM_IMAP_SIZE /* mapped size of IMMR area */ - -#define FEC_INTERRUPT 13 /* = SIU_LEVEL6 */ -#define DEC_INTERRUPT 11 /* = SIU_LEVEL5 */ -#define CPM_INTERRUPT 9 /* = SIU_LEVEL4 */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* __MACH_CCM_H */ diff --git a/arch/ppc/platforms/chestnut.c b/arch/ppc/platforms/chestnut.c deleted file mode 100644 index 27c140f218ed..000000000000 --- a/arch/ppc/platforms/chestnut.c +++ /dev/null @@ -1,574 +0,0 @@ -/* - * Board setup routines for IBM Chestnut - * - * Author: - * - * <2004> (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void __iomem *sram_base; /* Virtual addr of Internal SRAM */ -static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */ - -static mv64x60_handle_t bh; - -extern void gen550_progress(char *, unsigned short); -extern void gen550_init(int, struct uart_port *); -extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh); - -#define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \ - BIT(MV64x60_CPU2DEV_1_WIN) | \ - BIT(MV64x60_CPU2DEV_2_WIN) | \ - BIT(MV64x60_CPU2DEV_3_WIN) | \ - BIT(MV64x60_CPU2BOOT_WIN)) -/************************************************************************** - * FUNCTION: chestnut_calibrate_decr - * - * DESCRIPTION: initialize decrementer interrupt frequency (used as system - * timer) - * - ****/ -static void __init -chestnut_calibrate_decr(void) -{ - ulong freq; - - freq = CHESTNUT_BUS_SPEED / 4; - - printk("time_init: decrementer frequency = %lu.%.6lu MHz\n", - freq/1000000, freq%1000000); - - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); -} - -static int -chestnut_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: IBM\n"); - seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n"); - - return 0; -} - -/************************************************************************** - * FUNCTION: chestnut_find_end_of_memory - * - * DESCRIPTION: ppc_md memory size callback - * - ****/ -unsigned long __init -chestnut_find_end_of_memory(void) -{ - static int mem_size = 0; - - if (mem_size == 0) { - mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, - MV64x60_TYPE_MV64460); - } - return mem_size; -} - -#if defined(CONFIG_SERIAL_8250) -static void __init -chestnut_early_serial_map(void) -{ - struct uart_port port; - - /* Setup serial port access */ - memset(&port, 0, sizeof(port)); - port.uartclk = BASE_BAUD * 16; - port.irq = UART0_INT; - port.flags = STD_COM_FLAGS | UPF_IOREMAP; - port.iotype = UPIO_MEM; - port.mapbase = CHESTNUT_UART0_IO_BASE; - port.regshift = 0; - - if (early_serial_setup(&port) != 0) - printk("Early serial init of port 0 failed\n"); - - /* Assume early_serial_setup() doesn't modify serial_req */ - port.line = 1; - port.irq = UART1_INT; - port.mapbase = CHESTNUT_UART1_IO_BASE; - - if (early_serial_setup(&port) != 0) - printk("Early serial init of port 1 failed\n"); -} -#endif - -/************************************************************************** - * FUNCTION: chestnut_map_irq - * - * DESCRIPTION: 0 return since PCI IRQs not needed - * - ****/ -static int __init -chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = { - {CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ, - CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ}, - {CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ, - CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ}, - {CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ, - CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ}, - {CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ, - CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ}, - }; - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - - return PCI_IRQ_TABLE_LOOKUP; -} - - -/************************************************************************** - * FUNCTION: chestnut_setup_bridge - * - * DESCRIPTION: initalize board-specific settings on the MV64360 - * - ****/ -static void __init -chestnut_setup_bridge(void) -{ - struct mv64x60_setup_info si; - int i; - - if ( ppc_md.progress ) - ppc_md.progress("chestnut_setup_bridge: enter", 0); - - memset(&si, 0, sizeof(si)); - - si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; - - /* setup only PCI bus 0 (bus 1 not used) */ - si.pci_0.enable_bus = 1; - si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR; - si.pci_0.pci_io.pci_base_hi = 0; - si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR; - si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE; - si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */ - si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR; - si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR; - si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR; - si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE; - si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */ - si.pci_0.pci_cmd_bits = 0; - si.pci_0.latency_timer = 0x80; - - for (i=0; ifirst_busno = 0; - bh.hose_a->last_busno = 0xff; - bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); -} - -void __init -chestnut_setup_peripherals(void) -{ - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, - CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, - CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, - CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); - cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, - CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, - CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, - CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - -#ifdef CONFIG_NOT_COHERENT_CACHE - mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0); -#else - mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); -#endif - sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); - memset(sram_base, 0, MV64360_SRAM_SIZE); - - /* - * Configure MPP pins for PCI DMA - * - * PCI Slot GNT pin REQ pin - * 0 MPP16 MPP17 - * 1 MPP18 MPP19 - * 2 MPP20 MPP21 - * 3 MPP22 MPP23 - */ - mv64x60_write(&bh, MV64x60_MPP_CNTL_2, - (0x1 << 0) | /* MPPSel16 PCI0_GNT[0] */ - (0x1 << 4) | /* MPPSel17 PCI0_REQ[0] */ - (0x1 << 8) | /* MPPSel18 PCI0_GNT[1] */ - (0x1 << 12) | /* MPPSel19 PCI0_REQ[1] */ - (0x1 << 16) | /* MPPSel20 PCI0_GNT[2] */ - (0x1 << 20) | /* MPPSel21 PCI0_REQ[2] */ - (0x1 << 24) | /* MPPSel22 PCI0_GNT[3] */ - (0x1 << 28)); /* MPPSel23 PCI0_REQ[3] */ - /* - * Set unused MPP pins for output, as per schematic note - * - * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06 - * MPP09, MPP10, MPP13, MPP14, MPP15 - */ - mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0, - (0xf << 4) | /* MPPSel01 GPIO[1] */ - (0xf << 8) | /* MPPSel02 GPIO[2] */ - (0xf << 16) | /* MPPSel04 GPIO[4] */ - (0xf << 20) | /* MPPSel05 GPIO[5] */ - (0xf << 24)); /* MPPSel06 GPIO[6] */ - mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, - (0xf << 4) | /* MPPSel09 GPIO[9] */ - (0xf << 8) | /* MPPSel10 GPIO[10] */ - (0xf << 20) | /* MPPSel13 GPIO[13] */ - (0xf << 24) | /* MPPSel14 GPIO[14] */ - (0xf << 28)); /* MPPSel15 GPIO[15] */ - mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */ - BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | - BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15)); - - /* - * Configure the following MPP pins to indicate a level - * triggered interrupt - * - * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset) - * MPP25 - UART A (high) - * MPP26 - UART B (high) - * MPP28 - PCI Slot 3 (low) - * MPP29 - PCI Slot 2 (low) - * MPP30 - PCI Slot 1 (low) - * MPP31 - PCI Slot 0 (low) - */ - mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, - BIT(3) | BIT(2) | BIT(1) | BIT(0) | /* MPP 24 */ - BIT(7) | BIT(6) | BIT(5) | BIT(4) | /* MPP 25 */ - BIT(11) | BIT(10) | BIT(9) | BIT(8) | /* MPP 26 */ - BIT(19) | BIT(18) | BIT(17) | BIT(16) | /* MPP 28 */ - BIT(23) | BIT(22) | BIT(21) | BIT(20) | /* MPP 29 */ - BIT(27) | BIT(26) | BIT(25) | BIT(24) | /* MPP 30 */ - BIT(31) | BIT(30) | BIT(29) | BIT(28)); /* MPP 31 */ - - /* - * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low), - * 31 (low) interrupt polarity input signal and level triggered - */ - mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26)); - mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, - BIT(28) | BIT(29) | BIT(30) | BIT(31)); - mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, - BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) | - BIT(31)); - - /* Config GPP interrupt controller to respond to level trigger */ - mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10)); - - /* - * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0 - */ - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, - ~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) | - BIT(31))); - mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, - BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) | - BIT(31)); - - /* - * Dismiss and then enable interrupt on CPU #0 high cause register - * BIT27 summarizes GPP interrupts 24-31 - */ - mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27)); - - if (ppc_md.progress) - ppc_md.progress("chestnut_setup_bridge: exit", 0); -} - -/************************************************************************** - * FUNCTION: chestnut_setup_arch - * - * DESCRIPTION: ppc_md machine configuration callback - * - ****/ -static void __init -chestnut_setup_arch(void) -{ - if (ppc_md.progress) - ppc_md.progress("chestnut_setup_arch: enter", 0); - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000 / HZ; - - /* if the time base value is greater than bus freq/4 (the TB and - * decrementer tick rate) + signed integer rollover value, we - * can spend a fair amount of time waiting for the rollover to - * happen. To get around this, initialize the time base register - * to a "safe" value. - */ - set_tb(0, 0); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - /* - * Set up the L2CR register. - */ - _set_L2CR(_get_L2CR() | L2CR_L2E); - - chestnut_setup_bridge(); - chestnut_setup_peripherals(); - -#ifdef CONFIG_DUMMY_CONSOLE - conswitchp = &dummy_con; -#endif - -#if defined(CONFIG_SERIAL_8250) - chestnut_early_serial_map(); -#endif - - /* Identify the system */ - printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n"); - printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc." - " (source@mvista.com)\n"); - - if (ppc_md.progress) - ppc_md.progress("chestnut_setup_arch: exit", 0); -} - -#ifdef CONFIG_MTD_PHYSMAP -static struct mtd_partition ptbl; - -static int __init -chestnut_setup_mtd(void) -{ - memset(&ptbl, 0, sizeof(ptbl)); - - ptbl.name = "User FS"; - ptbl.size = CHESTNUT_32BIT_SIZE; - - physmap_map.size = CHESTNUT_32BIT_SIZE; - physmap_set_partitions(&ptbl, 1); - return 0; -} - -arch_initcall(chestnut_setup_mtd); -#endif - -/************************************************************************** - * FUNCTION: chestnut_restart - * - * DESCRIPTION: ppc_md machine reset callback - * reset the board via the CPLD command register - * - ****/ -static void -chestnut_restart(char *cmd) -{ - volatile ulong i = 10000000; - - local_irq_disable(); - - /* - * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work - * - * MPP24 - board reset - */ - writeb(0x1, cpld_base + 3); - - /* GPP pin tied to MPP earlier */ - mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24)); - - while (i-- > 0); - panic("restart failed\n"); -} - -static void -chestnut_halt(void) -{ - local_irq_disable(); - for (;;); - /* NOTREACHED */ -} - -static void -chestnut_power_off(void) -{ - chestnut_halt(); - /* NOTREACHED */ -} - -/************************************************************************** - * FUNCTION: chestnut_map_io - * - * DESCRIPTION: configure fixed memory-mapped IO - * - ****/ -static void __init -chestnut_map_io(void) -{ -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000, - _PAGE_IO); -#endif -} - -/************************************************************************** - * FUNCTION: chestnut_set_bat - * - * DESCRIPTION: configures a (temporary) bat mapping for early access to - * device I/O - * - ****/ -static __inline__ void -chestnut_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT3U, 0xf0001ffe); - mtspr(SPRN_DBAT3L, 0xf000002a); - mb(); -} - -/************************************************************************** - * FUNCTION: platform_init - * - * DESCRIPTION: main entry point for configuring board-specific machine - * callbacks - * - ****/ -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* Copy the kernel command line arguments to a safe place. */ - - if (r6) { - *(char *) (r7 + KERNELBASE) = 0; - strcpy(cmd_line, (char *) (r6 + KERNELBASE)); - } - - isa_mem_base = 0; - - ppc_md.setup_arch = chestnut_setup_arch; - ppc_md.show_cpuinfo = chestnut_show_cpuinfo; - ppc_md.init_IRQ = mv64360_init_irq; - ppc_md.get_irq = mv64360_get_irq; - ppc_md.init = NULL; - - ppc_md.find_end_of_memory = chestnut_find_end_of_memory; - ppc_md.setup_io_mappings = chestnut_map_io; - - ppc_md.restart = chestnut_restart; - ppc_md.power_off = chestnut_power_off; - ppc_md.halt = chestnut_halt; - - ppc_md.time_init = NULL; - ppc_md.set_rtc_time = NULL; - ppc_md.get_rtc_time = NULL; - ppc_md.calibrate_decr = chestnut_calibrate_decr; - - ppc_md.nvram_read_val = NULL; - ppc_md.nvram_write_val = NULL; - - ppc_md.heartbeat = NULL; - - bh.p_base = CONFIG_MV64X60_NEW_BASE; - - chestnut_set_bat(); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) - ppc_md.progress = gen550_progress; -#endif -#if defined(CONFIG_KGDB) - ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; -#endif - - if (ppc_md.progress) - ppc_md.progress("chestnut_init(): exit", 0); -} diff --git a/arch/ppc/platforms/chestnut.h b/arch/ppc/platforms/chestnut.h deleted file mode 100644 index e00fd9f8bbd0..000000000000 --- a/arch/ppc/platforms/chestnut.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Definitions for IBM 750FXGX Eval (Chestnut) - * - * Author: - * - * Based on Artesyn Katana code done by Tim Montgomery - * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il - * Based on code done by Mark A. Greer - * - * <2004> (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * This is the CPU physical memory map (windows must be at least 1MB and start - * on a boundary that is a multiple of the window size): - * - * Seems on the IBM 750FXGX Eval board, the MV64460 Registers can be in - * only 2 places per switch U17 0x14000000 or 0xf1000000 easily - chose to - * implement at 0xf1000000 only at this time - * - * 0xfff00000-0xffffffff - 8 Flash - * 0xffe00000-0xffefffff - BOOT SRAM - * 0xffd00000-0xffd00004 - CPLD - * 0xffc00000-0xffc0000f - UART - * 0xffb00000-0xffb07fff - FRAM - * 0xff840000-0xffafffff - *** HOLE *** - * 0xff800000-0xff83ffff - MV64460 Integrated SRAM - * 0xfe000000-0xff8fffff - *** HOLE *** - * 0xfc000000-0xfdffffff - 32bit Flash - * 0xf1010000-0xfbffffff - *** HOLE *** - * 0xf1000000-0xf100ffff - MV64460 Registers - */ - -#ifndef __PPC_PLATFORMS_CHESTNUT_H__ -#define __PPC_PLATFORMS_CHESTNUT_H__ - -#define CHESTNUT_BOOT_8BIT_BASE 0xfff00000 -#define CHESTNUT_BOOT_8BIT_SIZE_ACTUAL (1024*1024) -#define CHESTNUT_BOOT_SRAM_BASE 0xffe00000 -#define CHESTNUT_BOOT_SRAM_SIZE_ACTUAL (1024*1024) -#define CHESTNUT_CPLD_BASE 0xffd00000 -#define CHESTNUT_CPLD_SIZE_ACTUAL 5 -#define CHESTNUT_CPLD_REG3 (CHESTNUT_CPLD_BASE+3) -#define CHESTNUT_UART_BASE 0xffc00000 -#define CHESTNUT_UART_SIZE_ACTUAL 16 -#define CHESTNUT_FRAM_BASE 0xffb00000 -#define CHESTNUT_FRAM_SIZE_ACTUAL (32*1024) -#define CHESTNUT_INTERNAL_SRAM_BASE 0xff800000 -#define CHESTNUT_32BIT_BASE 0xfc000000 -#define CHESTNUT_32BIT_SIZE (32*1024*1024) - -#define CHESTNUT_BOOT_8BIT_SIZE max(MV64360_WINDOW_SIZE_MIN, \ - CHESTNUT_BOOT_8BIT_SIZE_ACTUAL) -#define CHESTNUT_BOOT_SRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \ - CHESTNUT_BOOT_SRAM_SIZE_ACTUAL) -#define CHESTNUT_CPLD_SIZE max(MV64360_WINDOW_SIZE_MIN, \ - CHESTNUT_CPLD_SIZE_ACTUAL) -#define CHESTNUT_UART_SIZE max(MV64360_WINDOW_SIZE_MIN, \ - CHESTNUT_UART_SIZE_ACTUAL) -#define CHESTNUT_FRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \ - CHESTNUT_FRAM_SIZE_ACTUAL) - -#define CHESTNUT_BUS_SPEED 200000000 -#define CHESTNUT_PIBS_DATABASE 0xf0000 /* from PIBS src code */ - -#define KATANA_ETH0_PHY_ADDR 12 -#define KATANA_ETH1_PHY_ADDR 11 -#define KATANA_ETH2_PHY_ADDR 4 - -#define CHESTNUT_ETH_TX_QUEUE_SIZE 800 -#define CHESTNUT_ETH_RX_QUEUE_SIZE 400 - -/* - * PCI windows - */ - -#define CHESTNUT_PCI0_MEM_PROC_ADDR 0x80000000 -#define CHESTNUT_PCI0_MEM_PCI_HI_ADDR 0x00000000 -#define CHESTNUT_PCI0_MEM_PCI_LO_ADDR 0x80000000 -#define CHESTNUT_PCI0_MEM_SIZE 0x10000000 -#define CHESTNUT_PCI0_IO_PROC_ADDR 0xa0000000 -#define CHESTNUT_PCI0_IO_PCI_ADDR 0x00000000 -#define CHESTNUT_PCI0_IO_SIZE 0x01000000 - -/* - * Board-specific IRQ info - */ -#define CHESTNUT_PCI_SLOT0_IRQ (64 + 31) -#define CHESTNUT_PCI_SLOT1_IRQ (64 + 30) -#define CHESTNUT_PCI_SLOT2_IRQ (64 + 29) -#define CHESTNUT_PCI_SLOT3_IRQ (64 + 28) - -/* serial port definitions */ -#define CHESTNUT_UART0_IO_BASE (CHESTNUT_UART_BASE + 8) -#define CHESTNUT_UART1_IO_BASE CHESTNUT_UART_BASE - -#define UART0_INT (64 + 25) -#define UART1_INT (64 + 26) - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 2 -#endif - -/* Rate for the 3.6864 Mhz clock for the onboard serial chip */ -#define BASE_BAUD (3686400 / 16) - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST) -#endif - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, STD_COM_FLAGS, \ - iomem_base: (u8 *)CHESTNUT_UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) - -#endif /* __PPC_PLATFORMS_CHESTNUT_H__ */ diff --git a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c deleted file mode 100644 index 07f672d58767..000000000000 --- a/arch/ppc/platforms/cpci690.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Board setup routines for the Force CPCI690 board. - * - * Author: Mark A. Greer - * - * 2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This programr - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define BOARD_VENDOR "Force" -#define BOARD_MACHINE "CPCI690" - -/* Set IDE controllers into Native mode? */ -#define SET_PCI_IDE_NATIVE - -static struct mv64x60_handle bh; -static void __iomem *cpci690_br_base; - -TODC_ALLOC(); - -static int __init -cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - - if (hose->index == 0) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 90, 91, 88, 89 }, /* IDSEL 30/20 - Sentinel */ - }; - - const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } else { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 93, 94, 95, 92 }, /* IDSEL 28/18 - PMC slot 2 */ - { 0, 0, 0, 0 }, /* IDSEL 29/19 - Not used */ - { 94, 95, 92, 93 }, /* IDSEL 30/20 - PMC slot 1 */ - }; - - const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } -} - -#define GB (1024UL * 1024UL * 1024UL) - -static u32 -cpci690_get_bus_freq(void) -{ - if (boot_mem_size >= (1*GB)) /* bus speed based on mem size */ - return 100000000; - else - return 133333333; -} - -static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */ - 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/ - 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/ -}; - -static int -cpci690_get_cpu_freq(void) -{ - unsigned long pll_cfg; - - pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27; - return cpci690_get_bus_freq() * cpu_750xx[pll_cfg]/2; -} - -static void __init -cpci690_setup_bridge(void) -{ - struct mv64x60_setup_info si; - int i; - - memset(&si, 0, sizeof(si)); - - si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; - - si.pci_0.enable_bus = 1; - si.pci_0.pci_io.cpu_base = CPCI690_PCI0_IO_START_PROC_ADDR; - si.pci_0.pci_io.pci_base_hi = 0; - si.pci_0.pci_io.pci_base_lo = CPCI690_PCI0_IO_START_PCI_ADDR; - si.pci_0.pci_io.size = CPCI690_PCI0_IO_SIZE; - si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_0.pci_mem[0].cpu_base = CPCI690_PCI0_MEM_START_PROC_ADDR; - si.pci_0.pci_mem[0].pci_base_hi = CPCI690_PCI0_MEM_START_PCI_HI_ADDR; - si.pci_0.pci_mem[0].pci_base_lo = CPCI690_PCI0_MEM_START_PCI_LO_ADDR; - si.pci_0.pci_mem[0].size = CPCI690_PCI0_MEM_SIZE; - si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_0.pci_cmd_bits = 0; - si.pci_0.latency_timer = 0x80; - - si.pci_1.enable_bus = 1; - si.pci_1.pci_io.cpu_base = CPCI690_PCI1_IO_START_PROC_ADDR; - si.pci_1.pci_io.pci_base_hi = 0; - si.pci_1.pci_io.pci_base_lo = CPCI690_PCI1_IO_START_PCI_ADDR; - si.pci_1.pci_io.size = CPCI690_PCI1_IO_SIZE; - si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_mem[0].cpu_base = CPCI690_PCI1_MEM_START_PROC_ADDR; - si.pci_1.pci_mem[0].pci_base_hi = CPCI690_PCI1_MEM_START_PCI_HI_ADDR; - si.pci_1.pci_mem[0].pci_base_lo = CPCI690_PCI1_MEM_START_PCI_LO_ADDR; - si.pci_1.pci_mem[0].size = CPCI690_PCI1_MEM_SIZE; - si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_cmd_bits = 0; - si.pci_1.latency_timer = 0x80; - - for (i=0; ifirst_busno = 0; - bh.hose_a->last_busno = 0xff; - bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); - - bh.hose_b->first_busno = bh.hose_a->last_busno + 1; - mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno); - bh.hose_b->last_busno = 0xff; - bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, - bh.hose_b->first_busno); -} - -static void __init -cpci690_setup_peripherals(void) -{ - /* Set up windows to CPLD, RTC/TODC, IPMI. */ - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE, - CPCI690_BR_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); - cpci690_br_base = ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE, - CPCI690_TODC_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); - TODC_INIT(TODC_TYPE_MK48T35, 0, 0, - ioremap(CPCI690_TODC_BASE, CPCI690_TODC_SIZE), 8); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CPCI690_IPMI_BASE, - CPCI690_IPMI_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); - - mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31)); - mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31)); - - mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */ - - /* - * Turn off timer/counters. Not turning off watchdog timer because - * can't read its reg on the 64260A so don't know if we'll be enabling - * or disabling. - */ - mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, - ((1<<0) | (1<<8) | (1<<16) | (1<<24))); - mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL, - ((1<<0) | (1<<8) | (1<<16) | (1<<24))); - - /* - * Set MPSC Multiplex RMII - * NOTE: ethernet driver modifies bit 0 and 1 - */ - mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102); - -#define GPP_EXTERNAL_INTERRUPTS \ - ((1<<24) | (1<<25) | (1<<26) | (1<<27) | \ - (1<<28) | (1<<29) | (1<<30) | (1<<31)) - /* PCI interrupts are inputs */ - mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS); - /* PCI interrupts are active low */ - mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS); - - /* Clear any pending interrupts for these inputs and enable them. */ - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS); - mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS); - - /* Route MPP interrupt inputs to GPP */ - mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000); - mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000); -} - -static void __init -cpci690_setup_arch(void) -{ - if (ppc_md.progress) - ppc_md.progress("cpci690_setup_arch: enter", 0); -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - if (ppc_md.progress) - ppc_md.progress("cpci690_setup_arch: Enabling L2 cache", 0); - - /* Enable L2 and L3 caches (if 745x) */ - _set_L2CR(_get_L2CR() | L2CR_L2E); - _set_L3CR(_get_L3CR() | L3CR_L3E); - - if (ppc_md.progress) - ppc_md.progress("cpci690_setup_arch: Initializing bridge", 0); - - cpci690_setup_bridge(); /* set up PCI bridge(s) */ - cpci690_setup_peripherals(); /* set up chip selects/GPP/MPP etc */ - - if (ppc_md.progress) - ppc_md.progress("cpci690_setup_arch: bridge init complete", 0); - - printk(KERN_INFO "%s %s port (C) 2003 MontaVista Software, Inc. " - "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE); - - if (ppc_md.progress) - ppc_md.progress("cpci690_setup_arch: exit", 0); -} - -/* Platform device data fixup routines. */ -#if defined(CONFIG_SERIAL_MPSC) -static void __init -cpci690_fixup_mpsc_pdata(struct platform_device *pdev) -{ - struct mpsc_pdata *pdata; - - pdata = (struct mpsc_pdata *)pdev->dev.platform_data; - - pdata->max_idle = 40; - pdata->default_baud = CPCI690_MPSC_BAUD; - pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC; - pdata->brg_clk_freq = cpci690_get_bus_freq(); -} - -static int -cpci690_platform_notify(struct device *dev) -{ - static struct { - char *bus_id; - void ((*rtn)(struct platform_device *pdev)); - } dev_map[] = { - { MPSC_CTLR_NAME ".0", cpci690_fixup_mpsc_pdata }, - { MPSC_CTLR_NAME ".1", cpci690_fixup_mpsc_pdata }, - }; - struct platform_device *pdev; - int i; - - if (dev && dev->bus_id) - for (i=0; ibus_id, dev_map[i].bus_id, - BUS_ID_SIZE)) { - - pdev = container_of(dev, - struct platform_device, dev); - dev_map[i].rtn(pdev); - } - - return 0; -} -#endif - -static void -cpci690_reset_board(void) -{ - u32 i = 10000; - - local_irq_disable(); - out_8((cpci690_br_base + CPCI690_BR_SW_RESET), 0x11); - - while (i != 0) i++; - panic("restart failed\n"); -} - -static void -cpci690_restart(char *cmd) -{ - cpci690_reset_board(); -} - -static void -cpci690_halt(void) -{ - while (1); - /* NOTREACHED */ -} - -static void -cpci690_power_off(void) -{ - cpci690_halt(); - /* NOTREACHED */ -} - -static int -cpci690_show_cpuinfo(struct seq_file *m) -{ - char *s; - - seq_printf(m, "cpu MHz\t\t: %d\n", - (cpci690_get_cpu_freq() + 500000) / 1000000); - seq_printf(m, "bus MHz\t\t: %d\n", - (cpci690_get_bus_freq() + 500000) / 1000000); - seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n"); - seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n"); - seq_printf(m, "FPGA Revision\t: %d\n", - in_8(cpci690_br_base + CPCI690_BR_MEM_CTLR) >> 5); - - switch(bh.type) { - case MV64x60_TYPE_GT64260A: - s = "gt64260a"; - break; - case MV64x60_TYPE_GT64260B: - s = "gt64260b"; - break; - case MV64x60_TYPE_MV64360: - s = "mv64360"; - break; - case MV64x60_TYPE_MV64460: - s = "mv64460"; - break; - default: - s = "Unknown"; - } - seq_printf(m, "bridge type\t: %s\n", s); - seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev); -#if defined(CONFIG_NOT_COHERENT_CACHE) - seq_printf(m, "coherency\t: %s\n", "off"); -#else - seq_printf(m, "coherency\t: %s\n", "on"); -#endif - - return 0; -} - -static void __init -cpci690_calibrate_decr(void) -{ - ulong freq; - - freq = cpci690_get_bus_freq() / 4; - - printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", - freq/1000000, freq%1000000); - - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); -} - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) -static void __init -cpci690_map_io(void) -{ - io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE, - 128 * 1024, _PAGE_IO); -} -#endif - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - -#ifdef CONFIG_BLK_DEV_INITRD - /* take care of initrd if we have one */ - if (r4) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - isa_mem_base = 0; - - ppc_md.setup_arch = cpci690_setup_arch; - ppc_md.show_cpuinfo = cpci690_show_cpuinfo; - ppc_md.init_IRQ = gt64260_init_irq; - ppc_md.get_irq = gt64260_get_irq; - ppc_md.restart = cpci690_restart; - ppc_md.power_off = cpci690_power_off; - ppc_md.halt = cpci690_halt; - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; - ppc_md.calibrate_decr = cpci690_calibrate_decr; - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) - ppc_md.setup_io_mappings = cpci690_map_io; -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = mv64x60_mpsc_progress; - mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ -#endif /* defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) */ - -#if defined(CONFIG_SERIAL_MPSC) - platform_notify = cpci690_platform_notify; -#endif -} diff --git a/arch/ppc/platforms/cpci690.h b/arch/ppc/platforms/cpci690.h deleted file mode 100644 index 0fa5a4c31b67..000000000000 --- a/arch/ppc/platforms/cpci690.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Definitions for Force CPCI690 - * - * Author: Mark A. Greer - * - * 2003 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * The GT64260 has 2 PCI buses each with 1 window from the CPU bus to - * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. - */ - -#ifndef __PPC_PLATFORMS_CPCI690_H -#define __PPC_PLATFORMS_CPCI690_H - -/* - * Define bd_t to pass in the MAC addresses used by the GT64260's enet ctlrs. - */ -#define CPCI690_BI_MAGIC 0xFE8765DC - -typedef struct board_info { - u32 bi_magic; - u8 bi_enetaddr[3][6]; -} bd_t; - -/* PCI bus Resource setup */ -#define CPCI690_PCI0_MEM_START_PROC_ADDR 0x80000000 -#define CPCI690_PCI0_MEM_START_PCI_HI_ADDR 0x00000000 -#define CPCI690_PCI0_MEM_START_PCI_LO_ADDR 0x80000000 -#define CPCI690_PCI0_MEM_SIZE 0x10000000 -#define CPCI690_PCI0_IO_START_PROC_ADDR 0xa0000000 -#define CPCI690_PCI0_IO_START_PCI_ADDR 0x00000000 -#define CPCI690_PCI0_IO_SIZE 0x01000000 - -#define CPCI690_PCI1_MEM_START_PROC_ADDR 0x90000000 -#define CPCI690_PCI1_MEM_START_PCI_HI_ADDR 0x00000000 -#define CPCI690_PCI1_MEM_START_PCI_LO_ADDR 0x90000000 -#define CPCI690_PCI1_MEM_SIZE 0x10000000 -#define CPCI690_PCI1_IO_START_PROC_ADDR 0xa1000000 -#define CPCI690_PCI1_IO_START_PCI_ADDR 0x01000000 -#define CPCI690_PCI1_IO_SIZE 0x01000000 - -/* Board Registers */ -#define CPCI690_BR_BASE 0xf0000000 -#define CPCI690_BR_SIZE_ACTUAL 0x8 -#define CPCI690_BR_SIZE max(GT64260_WINDOW_SIZE_MIN, \ - CPCI690_BR_SIZE_ACTUAL) -#define CPCI690_BR_LED_CNTL 0x00 -#define CPCI690_BR_SW_RESET 0x01 -#define CPCI690_BR_MISC_STATUS 0x02 -#define CPCI690_BR_SWITCH_STATUS 0x03 -#define CPCI690_BR_MEM_CTLR 0x04 -#define CPCI690_BR_LAST_RESET_1 0x05 -#define CPCI690_BR_LAST_RESET_2 0x06 - -#define CPCI690_TODC_BASE 0xf0100000 -#define CPCI690_TODC_SIZE_ACTUAL 0x8000 /* Size or NVRAM + RTC */ -#define CPCI690_TODC_SIZE max(GT64260_WINDOW_SIZE_MIN, \ - CPCI690_TODC_SIZE_ACTUAL) -#define CPCI690_MAC_OFFSET 0x7c10 /* MAC in RTC NVRAM */ - -#define CPCI690_IPMI_BASE 0xf0200000 -#define CPCI690_IPMI_SIZE_ACTUAL 0x10 /* 16 bytes of IPMI */ -#define CPCI690_IPMI_SIZE max(GT64260_WINDOW_SIZE_MIN, \ - CPCI690_IPMI_SIZE_ACTUAL) - -#define CPCI690_MPSC_BAUD 9600 -#define CPCI690_MPSC_CLK_SRC 8 /* TCLK */ - -#endif /* __PPC_PLATFORMS_CPCI690_H */ diff --git a/arch/ppc/platforms/est8260.h b/arch/ppc/platforms/est8260.h deleted file mode 100644 index adba68ecf57b..000000000000 --- a/arch/ppc/platforms/est8260.h +++ /dev/null @@ -1,35 +0,0 @@ -/* Board information for the EST8260, which should be generic for - * all 8260 boards. The IMMR is now given to us so the hard define - * will soon be removed. All of the clock values are computed from - * the configuration SCMR and the Power-On-Reset word. - */ -#ifndef __EST8260_PLATFORM -#define __EST8260_PLATFORM - -#define CPM_MAP_ADDR ((uint)0xf0000000) - -#define BOOTROM_RESTART_ADDR ((uint)0xff000104) - -/* For our show_cpuinfo hooks. */ -#define CPUINFO_VENDOR "EST Corporation" -#define CPUINFO_MACHINE "SBC8260 PowerPC" - -/* A Board Information structure that is given to a program when - * prom starts it up. - */ -typedef struct bd_info { - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in MHz */ - unsigned int bi_cpmfreq; /* CPM Freq, in MHz */ - unsigned int bi_brgfreq; /* BRG Freq, in MHz */ - unsigned int bi_vco; /* VCO Out from PLL */ - unsigned int bi_baudrate; /* Default console baud rate */ - unsigned int bi_immr; /* IMMR when called from boot rom */ - unsigned char bi_enetaddr[6]; -} bd_t; - -extern bd_t m8xx_board_info; - -#endif /* __EST8260_PLATFORM */ diff --git a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c deleted file mode 100644 index f522b31c46d7..000000000000 --- a/arch/ppc/platforms/ev64260.c +++ /dev/null @@ -1,649 +0,0 @@ -/* - * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board. - * - * Author: Mark A. Greer - * - * 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * The EV-64260-BP port is the result of hard work from many people from - * many companies. In particular, employees of Marvell/Galileo, Mission - * Critical Linux, Xyterra, and MontaVista Software were heavily involved. - * - * Note: I have not been able to get *all* PCI slots to work reliably - * at 66 MHz. I recommend setting jumpers J15 & J16 to short pins 1&2 - * so that 33 MHz is used. --MAG - * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK. - * At 100MHz, they are solid. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if !defined(CONFIG_SERIAL_MPSC_CONSOLE) -#include -#include -#include -#include -#else -#include -#endif -#include -#include -#include -#include -#include - -#include - -#define BOARD_VENDOR "Marvell/Galileo" -#define BOARD_MACHINE "EV-64260-BP" - -static struct mv64x60_handle bh; - -#if !defined(CONFIG_SERIAL_MPSC_CONSOLE) -extern void gen550_progress(char *, unsigned short); -extern void gen550_init(int, struct uart_port *); -#endif - -static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */ - 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 -}; -static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */ - { 1, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 }, - { 0, 30, 0, 2, 0, 26, 0, 18, 0, 22, 20, 24, 28, 32, 0, 0 } -}; - - -TODC_ALLOC(); - -static int -ev64260_get_bus_speed(void) -{ - return 100000000; -} - -static int -ev64260_get_cpu_speed(void) -{ - unsigned long pvr, hid1, pll_ext; - - pvr = PVR_VER(mfspr(SPRN_PVR)); - - if (pvr != PVR_VER(PVR_7450)) { - hid1 = mfspr(SPRN_HID1) >> 28; - return ev64260_get_bus_speed() * cpu_7xx[hid1]/2; - } - else { - hid1 = (mfspr(SPRN_HID1) & 0x0001e000) >> 13; - pll_ext = 0; /* No way to read; must get from schematic */ - return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2; - } -} - -unsigned long __init -ev64260_find_end_of_memory(void) -{ - return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, - MV64x60_TYPE_GT64260A); -} - -/* - * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing. - * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first - * PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ). - * This is the most IRQs you can get from one bus with this board, though. - */ -static int __init -ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - - if (hose->index == 0) { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */ - {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */ - }; - - const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } - else { - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */ - { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */ - }; - - const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } -} - -static void __init -ev64260_setup_peripherals(void) -{ - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, - EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, - EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, - EV64260_TODC_BASE, EV64260_TODC_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, - EV64260_UART_BASE, EV64260_UART_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, - EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); - - TODC_INIT(TODC_TYPE_DS1501, 0, 0, - ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8); - - mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29))); - mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27)); - - if (ev64260_get_bus_speed() > 100000000) - mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23)); - - mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3))); - mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3))); - - /* - * Enabling of PCI internal-vs-external arbitration - * is a platform- and errata-dependent decision. - */ - if (bh.type == MV64x60_TYPE_GT64260A ) { - mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31)); - mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31)); - } - - mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */ - - /* - * Turn off timer/counters. Not turning off watchdog timer because - * can't read its reg on the 64260A so don't know if we'll be enabling - * or disabling. - */ - mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, - ((1<<0) | (1<<8) | (1<<16) | (1<<24))); - mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL, - ((1<<0) | (1<<8) | (1<<16) | (1<<24))); - - /* - * Set MPSC Multiplex RMII - * NOTE: ethernet driver modifies bit 0 and 1 - */ - mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102); - - /* - * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260 - * bridge as interrupt inputs (via the General Purpose Ports (GPP) - * register). Need to route the MPP inputs to the GPP and set the - * polarity correctly. - * - * In MPP Control 2 Register - * MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0 - * MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0 - */ - mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) ); - - /* - * In MPP Control 3 Register - * MPP 26 -> GPP 26 (RTC INT) bits 8-11 -> 0 - * MPP 27 -> GPP 27 (PCI 0 INTA) bits 12-15 -> 0 - * MPP 29 -> GPP 29 (PCI 1 INTA) bits 20-23 -> 0 - */ - mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20)); - -#define GPP_EXTERNAL_INTERRUPTS \ - ((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29)) - /* DUART & PCI interrupts are inputs */ - mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS); - /* DUART & PCI interrupts are active low */ - mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS); - - /* Clear any pending interrupts for these inputs and enable them. */ - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS); - mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS); - - return; -} - -static void __init -ev64260_setup_bridge(void) -{ - struct mv64x60_setup_info si; - int i; - - memset(&si, 0, sizeof(si)); - - si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; - - si.pci_0.enable_bus = 1; - si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE; - si.pci_0.pci_io.pci_base_hi = 0; - si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE; - si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE; - si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE; - si.pci_0.pci_mem[0].pci_base_hi = 0; - si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE; - si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE; - si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_0.pci_cmd_bits = 0; - si.pci_0.latency_timer = 0x8; - - si.pci_1.enable_bus = 1; - si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE; - si.pci_1.pci_io.pci_base_hi = 0; - si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE; - si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE; - si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE; - si.pci_1.pci_mem[0].pci_base_hi = 0; - si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE; - si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE; - si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_cmd_bits = 0; - si.pci_1.latency_timer = 0x8; - - for (i=0; ifirst_busno = 0; - bh.hose_a->last_busno = 0xff; - bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); - - bh.hose_b->first_busno = bh.hose_a->last_busno + 1; - mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno); - bh.hose_b->last_busno = 0xff; - bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, - bh.hose_b->first_busno); - - return; -} - -#if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE) -static void __init -ev64260_early_serial_map(void) -{ - struct uart_port port; - static char first_time = 1; - - if (first_time) { - memset(&port, 0, sizeof(port)); - - port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE); - port.irq = EV64260_UART_0_IRQ; - port.uartclk = BASE_BAUD * 16; - port.regshift = 2; - port.iotype = UPIO_MEM; - port.flags = STD_COM_FLAGS; - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - gen550_init(0, &port); -#endif - - if (early_serial_setup(&port) != 0) - printk(KERN_WARNING "Early serial init of port 0 " - "failed\n"); - - first_time = 0; - } - - return; -} -#elif defined(CONFIG_SERIAL_MPSC_CONSOLE) -static void __init -ev64260_early_serial_map(void) -{ -} -#endif - -static void __init -ev64260_setup_arch(void) -{ - if (ppc_md.progress) - ppc_md.progress("ev64260_setup_arch: enter", 0); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - if (ppc_md.progress) - ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0); - - /* Enable L2 and L3 caches (if 745x) */ - _set_L2CR(_get_L2CR() | L2CR_L2E); - _set_L3CR(_get_L3CR() | L3CR_L3E); - - if (ppc_md.progress) - ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0); - - ev64260_setup_bridge(); /* set up PCI bridge(s) */ - ev64260_setup_peripherals(); /* set up chip selects/GPP/MPP etc */ - - if (ppc_md.progress) - ppc_md.progress("ev64260_setup_arch: bridge init complete", 0); - -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE) - ev64260_early_serial_map(); -#endif - - printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc. " - "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE); - - if (ppc_md.progress) - ppc_md.progress("ev64260_setup_arch: exit", 0); - - return; -} - -/* Platform device data fixup routines. */ -#if defined(CONFIG_SERIAL_MPSC) -static void __init -ev64260_fixup_mpsc_pdata(struct platform_device *pdev) -{ - struct mpsc_pdata *pdata; - - pdata = (struct mpsc_pdata *)pdev->dev.platform_data; - - pdata->max_idle = 40; - pdata->default_baud = EV64260_DEFAULT_BAUD; - pdata->brg_clk_src = EV64260_MPSC_CLK_SRC; - pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ; - - return; -} - -static int -ev64260_platform_notify(struct device *dev) -{ - static struct { - char *bus_id; - void ((*rtn)(struct platform_device *pdev)); - } dev_map[] = { - { MPSC_CTLR_NAME ".0", ev64260_fixup_mpsc_pdata }, - { MPSC_CTLR_NAME ".1", ev64260_fixup_mpsc_pdata }, - }; - struct platform_device *pdev; - int i; - - if (dev && dev->bus_id) - for (i=0; ibus_id, dev_map[i].bus_id, - BUS_ID_SIZE)) { - - pdev = container_of(dev, - struct platform_device, dev); - dev_map[i].rtn(pdev); - } - - return 0; -} -#endif - -static void -ev64260_reset_board(void *addr) -{ - local_irq_disable(); - - /* disable and invalidate the L2 cache */ - _set_L2CR(0); - _set_L2CR(0x200000); - - /* flush and disable L1 I/D cache */ - __asm__ __volatile__ - ("mfspr 3,1008\n\t" - "ori 5,5,0xcc00\n\t" - "ori 4,3,0xc00\n\t" - "andc 5,3,5\n\t" - "sync\n\t" - "mtspr 1008,4\n\t" - "isync\n\t" - "sync\n\t" - "mtspr 1008,5\n\t" - "isync\n\t" - "sync\n\t"); - - /* unmap any other random cs's that might overlap with bootcs */ - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0); - bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0); - bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0); - bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0); - bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); - - /* map bootrom back in to gt @ reset defaults */ - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, - 0xff800000, 8*1024*1024, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - - /* move reg base back to default, setup default pci0 */ - mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE, - (1<<24) | CONFIG_MV64X60_BASE >> 20); - - /* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped - * via BAT or MMU, and MSR IR/DR is ON */ - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ - /* NOTE: assumes reset vector is at 0xfff00100 */ - __asm__ __volatile__ - ("mtspr 26, %0\n\t" - "li 4,(1<<6)\n\t" - "mtspr 27,4\n\t" - "rfi\n\t" - :: "r" (addr):"r4"); - - return; -} - -static void -ev64260_restart(char *cmd) -{ - volatile ulong i = 10000000; - - ev64260_reset_board((void *)0xfff00100); - - while (i-- > 0); - panic("restart failed\n"); -} - -static void -ev64260_halt(void) -{ - local_irq_disable(); - while (1); - /* NOTREACHED */ -} - -static void -ev64260_power_off(void) -{ - ev64260_halt(); - /* NOTREACHED */ -} - -static int -ev64260_show_cpuinfo(struct seq_file *m) -{ - uint pvid; - - pvid = mfspr(SPRN_PVR); - seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n"); - seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n"); - seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000); - seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000); - - return 0; -} - -/* DS1501 RTC has too much variation to use RTC for calibration */ -static void __init -ev64260_calibrate_decr(void) -{ - ulong freq; - - freq = ev64260_get_bus_speed()/4; - - printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", - freq/1000000, freq%1000000); - - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); - - return; -} - -/* - * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space. - */ -static __inline__ void -ev64260_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT1U, 0xfb0001fe); - mtspr(SPRN_DBAT1L, 0xfb00002a); - mb(); - - return; -} - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) -static void __init -ev64260_map_io(void) -{ - io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO); -} -#endif - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ -#ifdef CONFIG_BLK_DEV_INITRD - extern int initrd_below_start_ok; - - initrd_start=initrd_end=0; - initrd_below_start_ok=0; -#endif /* CONFIG_BLK_DEV_INITRD */ - - parse_bootinfo(find_bootinfo()); - - isa_mem_base = 0; - isa_io_base = EV64260_PCI0_IO_CPU_BASE; - pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE; - - loops_per_jiffy = ev64260_get_cpu_speed() / HZ; - - ppc_md.setup_arch = ev64260_setup_arch; - ppc_md.show_cpuinfo = ev64260_show_cpuinfo; - ppc_md.init_IRQ = gt64260_init_irq; - ppc_md.get_irq = gt64260_get_irq; - - ppc_md.restart = ev64260_restart; - ppc_md.power_off = ev64260_power_off; - ppc_md.halt = ev64260_halt; - - ppc_md.find_end_of_memory = ev64260_find_end_of_memory; - - ppc_md.init = NULL; - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; - ppc_md.calibrate_decr = ev64260_calibrate_decr; - - bh.p_base = CONFIG_MV64X60_NEW_BASE; - - ev64260_set_bat(); - -#ifdef CONFIG_SERIAL_8250 -#if defined(CONFIG_SERIAL_TEXT_DEBUG) - ppc_md.setup_io_mappings = ev64260_map_io; - ppc_md.progress = gen550_progress; -#endif -#if defined(CONFIG_KGDB) - ppc_md.setup_io_mappings = ev64260_map_io; - ppc_md.early_serial_map = ev64260_early_serial_map; -#endif -#elif defined(CONFIG_SERIAL_MPSC_CONSOLE) -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.setup_io_mappings = ev64260_map_io; - ppc_md.progress = mv64x60_mpsc_progress; - mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ -#ifdef CONFIG_KGDB - ppc_md.setup_io_mappings = ev64260_map_io; - ppc_md.early_serial_map = ev64260_early_serial_map; -#endif /* CONFIG_KGDB */ - -#endif - -#if defined(CONFIG_SERIAL_MPSC) - platform_notify = ev64260_platform_notify; -#endif - - return; -} diff --git a/arch/ppc/platforms/ev64260.h b/arch/ppc/platforms/ev64260.h deleted file mode 100644 index 44d90d56745a..000000000000 --- a/arch/ppc/platforms/ev64260.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Definitions for Marvell/Galileo EV-64260-BP Evaluation Board. - * - * Author: Mark A. Greer - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * The MV64x60 has 2 PCI buses each with 1 window from the CPU bus to - * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. - * We'll only use one PCI MEM window on each PCI bus. - * - * This is the CPU physical memory map (windows must be at least 1MB and start - * on a boundary that is a multiple of the window size): - * - * 0xfc000000-0xffffffff - External FLASH on device module - * 0xfbf00000-0xfbffffff - Embedded (on board) FLASH - * 0xfbe00000-0xfbefffff - GT64260 Registers (preferably) - * but really a config option - * 0xfbd00000-0xfbdfffff - External SRAM on device module - * 0xfbc00000-0xfbcfffff - TODC chip on device module - * 0xfbb00000-0xfbbfffff - External UART on device module - * 0xa2000000-0xfbafffff - - * 0xa1000000-0xa1ffffff - PCI 1 I/O (defined in gt64260.h) - * 0xa0000000-0xa0ffffff - PCI 0 I/O (defined in gt64260.h) - * 0x90000000-0x9fffffff - PCI 1 MEM (defined in gt64260.h) - * 0x80000000-0x8fffffff - PCI 0 MEM (defined in gt64260.h) - */ - -#ifndef __PPC_PLATFORMS_EV64260_H -#define __PPC_PLATFORMS_EV64260_H - -/* PCI mappings */ -#define EV64260_PCI0_IO_CPU_BASE 0xa0000000 -#define EV64260_PCI0_IO_PCI_BASE 0x00000000 -#define EV64260_PCI0_IO_SIZE 0x01000000 - -#define EV64260_PCI0_MEM_CPU_BASE 0x80000000 -#define EV64260_PCI0_MEM_PCI_BASE 0x80000000 -#define EV64260_PCI0_MEM_SIZE 0x10000000 - -#define EV64260_PCI1_IO_CPU_BASE (EV64260_PCI0_IO_CPU_BASE + \ - EV64260_PCI0_IO_SIZE) -#define EV64260_PCI1_IO_PCI_BASE (EV64260_PCI0_IO_PCI_BASE + \ - EV64260_PCI0_IO_SIZE) -#define EV64260_PCI1_IO_SIZE 0x01000000 - -#define EV64260_PCI1_MEM_CPU_BASE (EV64260_PCI0_MEM_CPU_BASE + \ - EV64260_PCI0_MEM_SIZE) -#define EV64260_PCI1_MEM_PCI_BASE (EV64260_PCI0_MEM_PCI_BASE + \ - EV64260_PCI0_MEM_SIZE) -#define EV64260_PCI1_MEM_SIZE 0x10000000 - -/* CPU Physical Memory Map setup (other than PCI) */ -#define EV64260_EXT_FLASH_BASE 0xfc000000 -#define EV64260_EMB_FLASH_BASE 0xfbf00000 -#define EV64260_EXT_SRAM_BASE 0xfbd00000 -#define EV64260_TODC_BASE 0xfbc00000 -#define EV64260_UART_BASE 0xfbb00000 - -#define EV64260_EXT_FLASH_SIZE_ACTUAL 0x04000000 /* <= 64MB Extern FLASH */ -#define EV64260_EMB_FLASH_SIZE_ACTUAL 0x00080000 /* 512KB of Embed FLASH */ -#define EV64260_EXT_SRAM_SIZE_ACTUAL 0x00100000 /* 1MB SDRAM */ -#define EV64260_TODC_SIZE_ACTUAL 0x00000020 /* 32 bytes for TODC */ -#define EV64260_UART_SIZE_ACTUAL 0x00000040 /* 64 bytes for DUART */ - -#define EV64260_EXT_FLASH_SIZE max(GT64260_WINDOW_SIZE_MIN, \ - EV64260_EXT_FLASH_SIZE_ACTUAL) -#define EV64260_EMB_FLASH_SIZE max(GT64260_WINDOW_SIZE_MIN, \ - EV64260_EMB_FLASH_SIZE_ACTUAL) -#define EV64260_EXT_SRAM_SIZE max(GT64260_WINDOW_SIZE_MIN, \ - EV64260_EXT_SRAM_SIZE_ACTUAL) -#define EV64260_TODC_SIZE max(GT64260_WINDOW_SIZE_MIN, \ - EV64260_TODC_SIZE_ACTUAL) -/* Assembler in bootwrapper blows up if 'max' is used */ -#define EV64260_UART_SIZE GT64260_WINDOW_SIZE_MIN -#define EV64260_UART_END ((EV64260_UART_BASE + \ - EV64260_UART_SIZE - 1) & 0xfff00000) - -/* Board-specific IRQ info */ -#define EV64260_UART_0_IRQ 85 -#define EV64260_UART_1_IRQ 86 -#define EV64260_PCI_0_IRQ 91 -#define EV64260_PCI_1_IRQ 93 - -/* Serial port setup */ -#define EV64260_DEFAULT_BAUD 115200 - -#if defined(CONFIG_SERIAL_MPSC_CONSOLE) -#define SERIAL_PORT_DFNS - -#define EV64260_MPSC_CLK_SRC 8 /* TCLK */ -#define EV64260_MPSC_CLK_FREQ 100000000 /* 100MHz clk */ -#else -#define EV64260_SERIAL_0 (EV64260_UART_BASE + 0x20) -#define EV64260_SERIAL_1 EV64260_UART_BASE - -#define BASE_BAUD (EV64260_DEFAULT_BAUD * 2) - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 2 -#endif - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST) -#endif - -/* Required for bootloader's ns16550.c code */ -#define STD_SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, EV64260_SERIAL_0, EV64260_UART_0_IRQ, STD_COM_FLAGS, \ - iomem_base: (u8 *)EV64260_SERIAL_0, /* ttyS0 */ \ - iomem_reg_shift: 2, \ - io_type: SERIAL_IO_MEM }, - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DFNS -#endif -#endif /* __PPC_PLATFORMS_EV64260_H */ diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c deleted file mode 100644 index 6765676a5c6b..000000000000 --- a/arch/ppc/platforms/ev64360.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Board setup routines for the Marvell EV-64360-BP Evaluation Board. - * - * Author: Lee Nicks - * - * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il - * Based on code done by - Mark A. Greer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define BOARD_VENDOR "Marvell" -#define BOARD_MACHINE "EV-64360-BP" - -static struct mv64x60_handle bh; -static void __iomem *sram_base; - -static u32 ev64360_flash_size_0; -static u32 ev64360_flash_size_1; - -static u32 ev64360_bus_frequency; - -unsigned char __res[sizeof(bd_t)]; - -TODC_ALLOC(); - -static int __init -ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - return 0; -} - -static void __init -ev64360_setup_bridge(void) -{ - struct mv64x60_setup_info si; - int i; - - memset(&si, 0, sizeof(si)); - - si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; - - #ifdef CONFIG_PCI - si.pci_1.enable_bus = 1; - si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR; - si.pci_1.pci_io.pci_base_hi = 0; - si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR; - si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE; - si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR; - si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR; - si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR; - si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE; - si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_cmd_bits = 0; - si.pci_1.latency_timer = 0x80; - #else - si.pci_0.enable_bus = 0; - si.pci_1.enable_bus = 0; - #endif - - for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { -#if defined(CONFIG_NOT_COHERENT_CACHE) - si.cpu_prot_options[i] = 0; - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; - - si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_NONE | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; -#else - si.cpu_prot_options[i] = 0; - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */ - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */ - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */ - - si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_WB | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; -#endif - } - - if (mv64x60_init(&bh, &si)) - printk(KERN_WARNING "Bridge initialization failed.\n"); - - #ifdef CONFIG_PCI - pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */ - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = ev64360_map_irq; - ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; - - mv64x60_set_bus(&bh, 1, 0); - bh.hose_b->first_busno = 0; - bh.hose_b->last_busno = 0xff; - #endif -} - -/* Bridge & platform setup routines */ -void __init -ev64360_intr_setup(void) -{ - /* MPP 8, 9, and 10 */ - mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff); - - /* - * Define GPP 8,9,and 10 interrupt polarity as active low - * input signal and level triggered - */ - mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700); - mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700); - - /* Config GPP intr ctlr to respond to level trigger */ - mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10)); - - /* Erranum FEr PCI-#8 */ - mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9)); - mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9)); - - /* - * Dismiss and then enable interrupt on GPP interrupt cause - * for CPU #0 - */ - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700); - mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700); - - /* - * Dismiss and then enable interrupt on CPU #0 high cause reg - * BIT25 summarizes GPP interrupts 8-15 - */ - mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25)); -} - -void __init -ev64360_setup_peripherals(void) -{ - u32 base; - - /* Set up window for boot CS */ - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, - EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - - /* We only use the 32-bit flash */ - mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base, - &ev64360_flash_size_0); - ev64360_flash_size_1 = 0; - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, - EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); - - TODC_INIT(TODC_TYPE_DS1501, 0, 0, - ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, - EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); - - /* Set up Enet->SRAM window */ - mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, - EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2); - bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); - - /* Give enet r/w access to memory region */ - mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1))); - mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1))); - mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1))); - - mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3)); - mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, - ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24))); - -#if defined(CONFIG_NOT_COHERENT_CACHE) - mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000); -#else - mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); -#endif - - /* - * Setting the SRAM to 0. Note that this generates parity errors on - * internal data path in SRAM since it's first time accessing it - * while after reset it's not configured. - */ - memset(sram_base, 0, MV64360_SRAM_SIZE); - - /* set up PCI interrupt controller */ - ev64360_intr_setup(); -} - -static void __init -ev64360_setup_arch(void) -{ - if (ppc_md.progress) - ppc_md.progress("ev64360_setup_arch: enter", 0); - - set_tb(0, 0); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - /* - * Set up the L2CR register. - */ - _set_L2CR(L2CR_L2E | L2CR_L2PE); - - if (ppc_md.progress) - ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0); - - ev64360_setup_bridge(); - ev64360_setup_peripherals(); - ev64360_bus_frequency = ev64360_bus_freq(); - - printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks " - "(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE); - if (ppc_md.progress) - ppc_md.progress("ev64360_setup_arch: exit", 0); -} - -/* Platform device data fixup routines. */ -#if defined(CONFIG_SERIAL_MPSC) -static void __init -ev64360_fixup_mpsc_pdata(struct platform_device *pdev) -{ - struct mpsc_pdata *pdata; - - pdata = (struct mpsc_pdata *)pdev->dev.platform_data; - - pdata->max_idle = 40; - pdata->default_baud = EV64360_DEFAULT_BAUD; - pdata->brg_clk_src = EV64360_MPSC_CLK_SRC; - /* - * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts, - * TCLK == SysCLK but on 64460, they are separate pins. - * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz. - */ - pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX); -} -#endif - -#if defined(CONFIG_MV643XX_ETH) -static void __init -ev64360_fixup_eth_pdata(struct platform_device *pdev) -{ - struct mv643xx_eth_platform_data *eth_pd; - static u16 phy_addr[] = { - EV64360_ETH0_PHY_ADDR, - EV64360_ETH1_PHY_ADDR, - EV64360_ETH2_PHY_ADDR, - }; - - eth_pd = pdev->dev.platform_data; - eth_pd->force_phy_addr = 1; - eth_pd->phy_addr = phy_addr[pdev->id]; - eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE; - eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE; -} -#endif - -static int -ev64360_platform_notify(struct device *dev) -{ - static struct { - char *bus_id; - void ((*rtn)(struct platform_device *pdev)); - } dev_map[] = { -#if defined(CONFIG_SERIAL_MPSC) - { MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata }, - { MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata }, -#endif -#if defined(CONFIG_MV643XX_ETH) - { MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata }, - { MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata }, - { MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata }, -#endif - }; - struct platform_device *pdev; - int i; - - if (dev && dev->bus_id) - for (i=0; ibus_id, dev_map[i].bus_id, - BUS_ID_SIZE)) { - - pdev = container_of(dev, - struct platform_device, dev); - dev_map[i].rtn(pdev); - } - - return 0; -} - -#ifdef CONFIG_MTD_PHYSMAP - -#ifndef MB -#define MB (1 << 20) -#endif - -/* - * MTD Layout. - * - * FLASH Amount: 0xff000000 - 0xffffffff - * ------------- ----------------------- - * Reserved: 0xff000000 - 0xff03ffff - * JFFS2 file system: 0xff040000 - 0xffefffff - * U-boot: 0xfff00000 - 0xffffffff - */ -static int __init -ev64360_setup_mtd(void) -{ - u32 size; - int ptbl_entries; - static struct mtd_partition *ptbl; - - size = ev64360_flash_size_0 + ev64360_flash_size_1; - if (!size) - return -ENOMEM; - - ptbl_entries = 3; - - if ((ptbl = kzalloc(ptbl_entries * sizeof(struct mtd_partition), - GFP_KERNEL)) == NULL) { - - printk(KERN_WARNING "Can't alloc MTD partition table\n"); - return -ENOMEM; - } - - ptbl[0].name = "reserved"; - ptbl[0].offset = 0; - ptbl[0].size = EV64360_MTD_RESERVED_SIZE; - ptbl[1].name = "jffs2"; - ptbl[1].offset = EV64360_MTD_RESERVED_SIZE; - ptbl[1].size = EV64360_MTD_JFFS2_SIZE; - ptbl[2].name = "U-BOOT"; - ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE; - ptbl[2].size = EV64360_MTD_UBOOT_SIZE; - - physmap_map.size = size; - physmap_set_partitions(ptbl, ptbl_entries); - return 0; -} - -arch_initcall(ev64360_setup_mtd); -#endif - -static void -ev64360_restart(char *cmd) -{ - ulong i = 0xffffffff; - volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000); - - /* issue hard reset */ - rtc_base[0xf] = 0x80; - rtc_base[0xc] = 0x00; - rtc_base[0xd] = 0x01; - rtc_base[0xf] = 0x83; - - while (i-- > 0) ; - panic("restart failed\n"); -} - -static void -ev64360_halt(void) -{ - while (1) ; - /* NOTREACHED */ -} - -static void -ev64360_power_off(void) -{ - ev64360_halt(); - /* NOTREACHED */ -} - -static int -ev64360_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n"); - seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n"); - seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000); - - return 0; -} - -static void __init -ev64360_calibrate_decr(void) -{ - u32 freq; - - freq = ev64360_bus_frequency / 4; - - printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", - (long)freq / 1000000, (long)freq % 1000000); - - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); -} - -unsigned long __init -ev64360_find_end_of_memory(void) -{ - return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, - MV64x60_TYPE_MV64360); -} - -static inline void -ev64360_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT2U, 0xf0001ffe); - mtspr(SPRN_DBAT2L, 0xf000002a); - mb(); -} - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) -static void __init -ev64360_map_io(void) -{ - io_block_mapping(CONFIG_MV64X60_NEW_BASE, \ - CONFIG_MV64X60_NEW_BASE, \ - 0x00020000, _PAGE_IO); -} -#endif - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) - * are non-zero, then we should use the board info from the bd_t - * structure and the cmdline pointed to by r6 instead of the - * information from birecs, if any. Otherwise, use the information - * from birecs as discovered by the preceding call to - * parse_bootinfo(). This rule should work with both PPCBoot, which - * uses a bd_t board info structure, and the kernel boot wrapper, - * which uses birecs. - */ - if (r3 && r6) { - /* copy board info structure */ - memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); - /* copy command line */ - *(char *)(r7+KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6+KERNELBASE)); - } - #ifdef CONFIG_ISA - isa_mem_base = 0; - #endif - - ppc_md.setup_arch = ev64360_setup_arch; - ppc_md.show_cpuinfo = ev64360_show_cpuinfo; - ppc_md.init_IRQ = mv64360_init_irq; - ppc_md.get_irq = mv64360_get_irq; - ppc_md.restart = ev64360_restart; - ppc_md.power_off = ev64360_power_off; - ppc_md.halt = ev64360_halt; - ppc_md.find_end_of_memory = ev64360_find_end_of_memory; - ppc_md.init = NULL; - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; - ppc_md.calibrate_decr = ev64360_calibrate_decr; - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) - ppc_md.setup_io_mappings = ev64360_map_io; - ppc_md.progress = mv64x60_mpsc_progress; - mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); -#endif - -#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) - platform_notify = ev64360_platform_notify; -#endif - - ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */ -} diff --git a/arch/ppc/platforms/ev64360.h b/arch/ppc/platforms/ev64360.h deleted file mode 100644 index b30f4722690a..000000000000 --- a/arch/ppc/platforms/ev64360.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Definitions for Marvell EV-64360-BP Evaluation Board. - * - * Author: Lee Nicks - * - * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il - * Based on code done by Mark A. Greer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to - * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. - * We'll only use one PCI MEM window on each PCI bus. - * - * This is the CPU physical memory map (windows must be at least 64KB and start - * on a boundary that is a multiple of the window size): - * - * 0x42000000-0x4203ffff - Internal SRAM - * 0xf1000000-0xf100ffff - MV64360 Registers (CONFIG_MV64X60_NEW_BASE) - * 0xfc800000-0xfcffffff - RTC - * 0xff000000-0xffffffff - Boot window, 16 MB flash - * 0xc0000000-0xc3ffffff - PCI I/O (second hose) - * 0x80000000-0xbfffffff - PCI MEM (second hose) - */ - -#ifndef __PPC_PLATFORMS_EV64360_H -#define __PPC_PLATFORMS_EV64360_H - -/* CPU Physical Memory Map setup. */ -#define EV64360_BOOT_WINDOW_BASE 0xff000000 -#define EV64360_BOOT_WINDOW_SIZE 0x01000000 /* 16 MB */ -#define EV64360_INTERNAL_SRAM_BASE 0x42000000 -#define EV64360_RTC_WINDOW_BASE 0xfc800000 -#define EV64360_RTC_WINDOW_SIZE 0x00800000 /* 8 MB */ - -#define EV64360_PCI1_MEM_START_PROC_ADDR 0x80000000 -#define EV64360_PCI1_MEM_START_PCI_HI_ADDR 0x00000000 -#define EV64360_PCI1_MEM_START_PCI_LO_ADDR 0x80000000 -#define EV64360_PCI1_MEM_SIZE 0x40000000 /* 1 GB */ -#define EV64360_PCI1_IO_START_PROC_ADDR 0xc0000000 -#define EV64360_PCI1_IO_START_PCI_ADDR 0x00000000 -#define EV64360_PCI1_IO_SIZE 0x04000000 /* 64 MB */ - -#define EV64360_DEFAULT_BAUD 115200 -#define EV64360_MPSC_CLK_SRC 8 /* TCLK */ -#define EV64360_MPSC_CLK_FREQ 133333333 - -#define EV64360_MTD_RESERVED_SIZE 0x40000 -#define EV64360_MTD_JFFS2_SIZE 0xec0000 -#define EV64360_MTD_UBOOT_SIZE 0x100000 - -#define EV64360_ETH0_PHY_ADDR 8 -#define EV64360_ETH1_PHY_ADDR 9 -#define EV64360_ETH2_PHY_ADDR 10 - -#define EV64360_ETH_TX_QUEUE_SIZE 800 -#define EV64360_ETH_RX_QUEUE_SIZE 400 - -#define EV64360_ETH_PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -#define EV64360_ETH_PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -#define EV64360_ETH_PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT - -#define EV64360_ETH_PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ATTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_9700BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX - -static inline u32 -ev64360_bus_freq(void) -{ - return 133333333; -} - -#endif /* __PPC_PLATFORMS_EV64360_H */ diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h deleted file mode 100644 index 5219366667b3..000000000000 --- a/arch/ppc/platforms/fads.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Added MPC86XADS support. - * The MPC86xADS manual says the board "is compatible with the MPC8xxFADS - * for SW point of view". This is 99% correct. - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * 2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_FADS_H__ -#define __ASM_FADS_H__ - - -#include - -/* Memory map is configured by the PROM startup. - * I tried to follow the FADS manual, although the startup PROM - * dictates this and we simply have to move some of the physical - * addresses for Linux. - */ -#define BCSR_ADDR ((uint)0xff010000) - -/* PHY link change interrupt */ -#define PHY_INTERRUPT SIU_IRQ2 - -#define BCSR_SIZE ((uint)(64 * 1024)) -#define BCSR0 ((uint)(BCSR_ADDR + 0x00)) -#define BCSR1 ((uint)(BCSR_ADDR + 0x04)) -#define BCSR2 ((uint)(BCSR_ADDR + 0x08)) -#define BCSR3 ((uint)(BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint)(BCSR_ADDR + 0x10)) - -#define IMAP_ADDR ((uint)0xff000000) -#define IMAP_SIZE ((uint)(64 * 1024)) - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -/* Bits of interest in the BCSRs. - */ -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDAEN ((uint)0x10000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP0 ((uint)0x00200000) -#define BCSR1_PCCVPP1 ((uint)0x00100000) -#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) -#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1) - -#define BCSR4_ETHLOOP ((uint)0x80000000) /* EEST Loopback */ -#define BCSR4_EEFDX ((uint)0x40000000) /* EEST FDX enable */ -#define BCSR4_FETH_EN ((uint)0x08000000) /* PHY enable */ -#define BCSR4_FETHCFG0 ((uint)0x04000000) /* PHY autoneg mode */ -#define BCSR4_FETHCFG1 ((uint)0x00400000) /* PHY autoneg mode */ -#define BCSR4_FETHFDE ((uint)0x02000000) /* PHY FDX advertise */ -#define BCSR4_FETHRST ((uint)0x00200000) /* PHY Reset */ - -/* IO_BASE definition for pcmcia. - */ -#define _IO_BASE 0x80000000 -#define _IO_BASE_SIZE 0x1000 - -#ifdef CONFIG_IDE -#define MAX_HWIFS 1 -#endif - -/* Interrupt level assignments. - */ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -/* We don't use the 8259. - */ -#define NR_8259_INTS 0 - -/* CPM Ethernet through SCC1 or SCC2 */ - -#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1) /* Probably 860 variant */ -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - * TCLK - CLK1, RCLK - CLK2. - */ -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00001000) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002c) -#endif /* CONFIG_SCC1_ENET */ - -#ifdef CONFIG_SCC2_ENET /* Probably 823/850 variant */ -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - * TCLK - CLK1, RCLK - CLK2. - */ -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -/* Control bits in the SICR to route TCLK and RCLK to - * SCC2. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) -#endif /* CONFIG_SCC2_ENET */ - -#endif /* __ASM_FADS_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c deleted file mode 100644 index 904b518c152e..000000000000 --- a/arch/ppc/platforms/hdpu.c +++ /dev/null @@ -1,1015 +0,0 @@ -/* - * Board setup routines for the Sky Computers HDPU Compute Blade. - * - * Written by Brian Waite - * - * Based on code done by - Mark A. Greer - * Rabeeh Khoury - rabeeh@galileo.co.il - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define BOARD_VENDOR "Sky Computers" -#define BOARD_MACHINE "HDPU-CB-A" - -bd_t ppcboot_bd; -int ppcboot_bd_valid = 0; - -static mv64x60_handle_t bh; - -extern char cmd_line[]; - -unsigned long hdpu_find_end_of_memory(void); -void hdpu_mpsc_progress(char *s, unsigned short hex); -void hdpu_heartbeat(void); - -static void parse_bootinfo(unsigned long r3, - unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7); -static void hdpu_set_l1pe(void); -static void hdpu_cpustate_set(unsigned char new_state); -#ifdef CONFIG_SMP -static DEFINE_SPINLOCK(timebase_lock); -static unsigned int timebase_upper = 0, timebase_lower = 0; -extern int smp_tb_synchronized; - -void __devinit hdpu_tben_give(void); -void __devinit hdpu_tben_take(void); -#endif - -static int __init -hdpu_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - - if (hose->index == 0) { - static char pci_irq_table[][4] = { - {HDPU_PCI_0_IRQ, 0, 0, 0}, - {HDPU_PCI_0_IRQ, 0, 0, 0}, - }; - - const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } else { - static char pci_irq_table[][4] = { - {HDPU_PCI_1_IRQ, 0, 0, 0}, - }; - - const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; - } -} - -static void __init hdpu_intr_setup(void) -{ - mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, - (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | - (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) | - (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) | - (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) | - (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29))); - - /* XXXX Erranum FEr PCI-#8 */ - mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1 << 5) | (1 << 9)); - mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1 << 5) | (1 << 9)); - - /* - * Dismiss and then enable interrupt on GPP interrupt cause - * for CPU #0 - */ - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~((1 << 8) | (1 << 13))); - mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1 << 8) | (1 << 13)); - - /* - * Dismiss and then enable interrupt on CPU #0 high cause reg - * BIT25 summarizes GPP interrupts 8-15 - */ - mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1 << 25)); -} - -static void __init hdpu_setup_peripherals(void) -{ - unsigned int val; - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, - HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, - HDPU_TBEN_BASE, HDPU_TBEN_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, - HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, - HDPU_INTERNAL_SRAM_BASE, - HDPU_INTERNAL_SRAM_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - - bh.ci->disable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, 0, 0, 0); - - mv64x60_clr_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, (1 << 3)); - mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3)); - mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, - ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24))); - - /* Enable pipelining */ - mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13)); - /* Enable Snoop Pipelining */ - mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24)); - - /* - * Change DRAM read buffer assignment. - * Assign read buffer 0 dedicated only for CPU, - * and the rest read buffer 1. - */ - val = mv64x60_read(&bh, MV64360_SDRAM_CONFIG); - val = val & 0x03ffffff; - val = val | 0xf8000000; - mv64x60_write(&bh, MV64360_SDRAM_CONFIG, val); - - /* - * Configure internal SRAM - - * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set - * Parity enabled. - * Parity error propagation - * Arbitration not parked for CPU only - * Other bits are reserved. - */ -#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT - mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); -#else - mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0); -#endif - - hdpu_intr_setup(); -} - -static void __init hdpu_setup_bridge(void) -{ - struct mv64x60_setup_info si; - int i; - - memset(&si, 0, sizeof(si)); - - si.phys_reg_base = HDPU_BRIDGE_REG_BASE; - si.pci_0.enable_bus = 1; - si.pci_0.pci_io.cpu_base = HDPU_PCI0_IO_START_PROC_ADDR; - si.pci_0.pci_io.pci_base_hi = 0; - si.pci_0.pci_io.pci_base_lo = HDPU_PCI0_IO_START_PCI_ADDR; - si.pci_0.pci_io.size = HDPU_PCI0_IO_SIZE; - si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_0.pci_mem[0].cpu_base = HDPU_PCI0_MEM_START_PROC_ADDR; - si.pci_0.pci_mem[0].pci_base_hi = HDPU_PCI0_MEM_START_PCI_HI_ADDR; - si.pci_0.pci_mem[0].pci_base_lo = HDPU_PCI0_MEM_START_PCI_LO_ADDR; - si.pci_0.pci_mem[0].size = HDPU_PCI0_MEM_SIZE; - si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_0.pci_cmd_bits = 0; - si.pci_0.latency_timer = 0x80; - - si.pci_1.enable_bus = 1; - si.pci_1.pci_io.cpu_base = HDPU_PCI1_IO_START_PROC_ADDR; - si.pci_1.pci_io.pci_base_hi = 0; - si.pci_1.pci_io.pci_base_lo = HDPU_PCI1_IO_START_PCI_ADDR; - si.pci_1.pci_io.size = HDPU_PCI1_IO_SIZE; - si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_mem[0].cpu_base = HDPU_PCI1_MEM_START_PROC_ADDR; - si.pci_1.pci_mem[0].pci_base_hi = HDPU_PCI1_MEM_START_PCI_HI_ADDR; - si.pci_1.pci_mem[0].pci_base_lo = HDPU_PCI1_MEM_START_PCI_LO_ADDR; - si.pci_1.pci_mem[0].size = HDPU_PCI1_MEM_SIZE; - si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_cmd_bits = 0; - si.pci_1.latency_timer = 0x80; - - for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { -#if defined(CONFIG_NOT_COHERENT_CACHE) - si.cpu_prot_options[i] = 0; - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; - - si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_NONE | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; - - si.pci_0.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_NONE | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; - -#else - si.cpu_prot_options[i] = 0; - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; /* errata */ - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; /* errata */ - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; /* errata */ - - si.pci_0.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_WB | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; - - si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_WB | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; -#endif - } - - hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI); - - /* Lookup PCI host bridges */ - mv64x60_init(&bh, &si); - pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */ - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = hdpu_map_irq; - - mv64x60_set_bus(&bh, 0, 0); - bh.hose_a->first_busno = 0; - bh.hose_a->last_busno = 0xff; - bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); - - bh.hose_b->first_busno = bh.hose_a->last_busno + 1; - mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno); - bh.hose_b->last_busno = 0xff; - bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, - bh.hose_b->first_busno); - - ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; - - hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG); - /* - * Enabling of PCI internal-vs-external arbitration - * is a platform- and errata-dependent decision. - */ - return; -} - -#if defined(CONFIG_SERIAL_MPSC_CONSOLE) -static void __init hdpu_early_serial_map(void) -{ -#ifdef CONFIG_KGDB - static char first_time = 1; - -#if defined(CONFIG_KGDB_TTYS0) -#define KGDB_PORT 0 -#elif defined(CONFIG_KGDB_TTYS1) -#define KGDB_PORT 1 -#else -#error "Invalid kgdb_tty port" -#endif - - if (first_time) { - gt_early_mpsc_init(KGDB_PORT, - B9600 | CS8 | CREAD | HUPCL | CLOCAL); - first_time = 0; - } - - return; -#endif -} -#endif - -static void hdpu_init2(void) -{ - return; -} - -#if defined(CONFIG_MV643XX_ETH) -static void __init hdpu_fixup_eth_pdata(struct platform_device *pd) -{ - - struct mv643xx_eth_platform_data *eth_pd; - eth_pd = pd->dev.platform_data; - - eth_pd->force_phy_addr = 1; - eth_pd->phy_addr = pd->id; - eth_pd->speed = SPEED_100; - eth_pd->duplex = DUPLEX_FULL; - eth_pd->tx_queue_size = 400; - eth_pd->rx_queue_size = 800; -} -#endif - -static void __init hdpu_fixup_mpsc_pdata(struct platform_device *pd) -{ - - struct mpsc_pdata *pdata; - - pdata = (struct mpsc_pdata *)pd->dev.platform_data; - - pdata->max_idle = 40; - if (ppcboot_bd_valid) - pdata->default_baud = ppcboot_bd.bi_baudrate; - else - pdata->default_baud = HDPU_DEFAULT_BAUD; - pdata->brg_clk_src = HDPU_MPSC_CLK_SRC; - pdata->brg_clk_freq = HDPU_MPSC_CLK_FREQ; -} - -#if defined(CONFIG_HDPU_FEATURES) -static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd) -{ - struct platform_device *pds[1]; - pds[0] = pd; - mv64x60_pd_fixup(&bh, pds, 1); -} -#endif - -static int hdpu_platform_notify(struct device *dev) -{ - static struct { - char *bus_id; - void ((*rtn) (struct platform_device * pdev)); - } dev_map[] = { - { - MPSC_CTLR_NAME ".0", hdpu_fixup_mpsc_pdata}, -#if defined(CONFIG_MV643XX_ETH) - { - MV643XX_ETH_NAME ".0", hdpu_fixup_eth_pdata}, -#endif -#if defined(CONFIG_HDPU_FEATURES) - { - HDPU_CPUSTATE_NAME ".0", hdpu_fixup_cpustate_pdata}, -#endif - }; - struct platform_device *pdev; - int i; - - if (dev && dev->bus_id) - for (i = 0; i < ARRAY_SIZE(dev_map); i++) - if (!strncmp(dev->bus_id, dev_map[i].bus_id, - BUS_ID_SIZE)) { - - pdev = container_of(dev, - struct platform_device, - dev); - dev_map[i].rtn(pdev); - } - - return 0; -} - -static void __init hdpu_setup_arch(void) -{ - if (ppc_md.progress) - ppc_md.progress("hdpu_setup_arch: enter", 0); -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - ppc_md.heartbeat = hdpu_heartbeat; - - ppc_md.heartbeat_reset = HZ; - ppc_md.heartbeat_count = 1; - - if (ppc_md.progress) - ppc_md.progress("hdpu_setup_arch: Enabling L2 cache", 0); - - /* Enable L1 Parity Bits */ - hdpu_set_l1pe(); - - /* Enable L2 and L3 caches (if 745x) */ - _set_L2CR(0x80080000); - - if (ppc_md.progress) - ppc_md.progress("hdpu_setup_arch: enter", 0); - - hdpu_setup_bridge(); - - hdpu_setup_peripherals(); - -#ifdef CONFIG_SERIAL_MPSC_CONSOLE - hdpu_early_serial_map(); -#endif - - printk("SKY HDPU Compute Blade \n"); - - if (ppc_md.progress) - ppc_md.progress("hdpu_setup_arch: exit", 0); - - hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_OK); - return; -} -static void __init hdpu_init_irq(void) -{ - mv64360_init_irq(); -} - -static void __init hdpu_set_l1pe() -{ - unsigned long ictrl; - asm volatile ("mfspr %0, 1011":"=r" (ictrl):); - ictrl |= ICTRL_EICE | ICTRL_EDC | ICTRL_EICP; - asm volatile ("mtspr 1011, %0"::"r" (ictrl)); -} - -/* - * Set BAT 1 to map 0xf1000000 to end of physical memory space. - */ -static __inline__ void hdpu_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT1U, 0xf10001fe); - mtspr(SPRN_DBAT1L, 0xf100002a); - mb(); - - return; -} - -unsigned long __init hdpu_find_end_of_memory(void) -{ - return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, - MV64x60_TYPE_MV64360); -} - -static void hdpu_reset_board(void) -{ - volatile int infinite = 1; - - hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_RESET); - - local_irq_disable(); - - /* Clear all the LEDs */ - mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) | - (1 << 5) | (1 << 6))); - - /* disable and invalidate the L2 cache */ - _set_L2CR(0); - _set_L2CR(0x200000); - - /* flush and disable L1 I/D cache */ - __asm__ __volatile__ - ("\n" - "mfspr 3,1008\n" - "ori 5,5,0xcc00\n" - "ori 4,3,0xc00\n" - "andc 5,3,5\n" - "sync\n" - "mtspr 1008,4\n" - "isync\n" "sync\n" "mtspr 1008,5\n" "isync\n" "sync\n"); - - /* Hit the reset bit */ - mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 3)); - - while (infinite) - infinite = infinite; - - return; -} - -static void hdpu_restart(char *cmd) -{ - volatile ulong i = 10000000; - - hdpu_reset_board(); - - while (i-- > 0) ; - panic("restart failed\n"); -} - -static void hdpu_halt(void) -{ - local_irq_disable(); - - hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_HALT); - - /* Clear all the LEDs */ - mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) | (1 << 5) | - (1 << 6))); - while (1) ; - /* NOTREACHED */ -} - -static void hdpu_power_off(void) -{ - hdpu_halt(); - /* NOTREACHED */ -} - -static int hdpu_show_cpuinfo(struct seq_file *m) -{ - uint pvid; - - pvid = mfspr(SPRN_PVR); - seq_printf(m, "vendor\t\t: Sky Computers\n"); - seq_printf(m, "machine\t\t: HDPU Compute Blade\n"); - seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n", - pvid, (pvid & (1 << 15) ? "IBM" : "Motorola")); - - return 0; -} - -static void __init hdpu_calibrate_decr(void) -{ - ulong freq; - - if (ppcboot_bd_valid) - freq = ppcboot_bd.bi_busfreq / 4; - else - freq = 133000000; - - printk("time_init: decrementer frequency = %lu.%.6lu MHz\n", - freq / 1000000, freq % 1000000); - - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); - - return; -} - -static void parse_bootinfo(unsigned long r3, - unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - bd_t *bd = NULL; - char *cmdline_start = NULL; - int cmdline_len = 0; - - if (r3) { - if ((r3 & 0xf0000000) == 0) - r3 += KERNELBASE; - if ((r3 & 0xf0000000) == KERNELBASE) { - bd = (void *)r3; - - memcpy(&ppcboot_bd, bd, sizeof(ppcboot_bd)); - ppcboot_bd_valid = 1; - } - } -#ifdef CONFIG_BLK_DEV_INITRD - if (r4 && r5 && r5 > r4) { - if ((r4 & 0xf0000000) == 0) - r4 += KERNELBASE; - if ((r5 & 0xf0000000) == 0) - r5 += KERNELBASE; - if ((r4 & 0xf0000000) == KERNELBASE) { - initrd_start = r4; - initrd_end = r5; - initrd_below_start_ok = 1; - } - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - if (r6 && r7 && r7 > r6) { - if ((r6 & 0xf0000000) == 0) - r6 += KERNELBASE; - if ((r7 & 0xf0000000) == 0) - r7 += KERNELBASE; - if ((r6 & 0xf0000000) == KERNELBASE) { - cmdline_start = (void *)r6; - cmdline_len = (r7 - r6); - strncpy(cmd_line, cmdline_start, cmdline_len); - } - } -} - -void hdpu_heartbeat(void) -{ - if (mv64x60_read(&bh, MV64x60_GPP_VALUE) & (1 << 5)) - mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 5)); - else - mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, (1 << 5)); - - ppc_md.heartbeat_count = ppc_md.heartbeat_reset; - -} - -static void __init hdpu_map_io(void) -{ - io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO); -} - -#ifdef CONFIG_SMP -char hdpu_smp0[] = "SMP Cpu #0"; -char hdpu_smp1[] = "SMP Cpu #1"; - -static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id) -{ - volatile unsigned int doorbell; - - doorbell = mv64x60_read(&bh, MV64360_CPU0_DOORBELL); - - /* Ack the doorbell interrupts */ - mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, doorbell); - - if (doorbell & 1) { - smp_message_recv(0); - } - if (doorbell & 2) { - smp_message_recv(1); - } - if (doorbell & 4) { - smp_message_recv(2); - } - if (doorbell & 8) { - smp_message_recv(3); - } - return IRQ_HANDLED; -} - -static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id) -{ - volatile unsigned int doorbell; - - doorbell = mv64x60_read(&bh, MV64360_CPU1_DOORBELL); - - /* Ack the doorbell interrupts */ - mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, doorbell); - - if (doorbell & 1) { - smp_message_recv(0); - } - if (doorbell & 2) { - smp_message_recv(1); - } - if (doorbell & 4) { - smp_message_recv(2); - } - if (doorbell & 8) { - smp_message_recv(3); - } - return IRQ_HANDLED; -} - -static void smp_hdpu_CPU_two(void) -{ - __asm__ __volatile__ - ("\n" - "lis 3,0x0000\n" - "ori 3,3,0x00c0\n" - "mtspr 26, 3\n" "li 4,0\n" "mtspr 27,4\n" "rfi"); - -} - -static int smp_hdpu_probe(void) -{ - int *cpu_count_reg; - int num_cpus = 0; - - cpu_count_reg = ioremap(HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE); - if (cpu_count_reg) { - num_cpus = (*cpu_count_reg >> 20) & 0x3; - iounmap(cpu_count_reg); - } - - /* Validate the bits in the CPLD. If we could not map the reg, return 2. - * If the register reported 0 or 3, return 2. - * Older CPLD revisions set these bits to all ones (val = 3). - */ - if ((num_cpus < 1) || (num_cpus > 2)) { - printk - ("Unable to determine the number of processors %d . deafulting to 2.\n", - num_cpus); - num_cpus = 2; - } - return num_cpus; -} - -static void -smp_hdpu_message_pass(int target, int msg) -{ - if (msg > 0x3) { - printk("SMP %d: smp_message_pass: unknown msg %d\n", - smp_processor_id(), msg); - return; - } - switch (target) { - case MSG_ALL: - mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg); - mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg); - break; - case MSG_ALL_BUT_SELF: - if (smp_processor_id()) - mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg); - else - mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg); - break; - default: - if (target == 0) - mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg); - else - mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg); - break; - } -} - -static void smp_hdpu_kick_cpu(int nr) -{ - volatile unsigned int *bootaddr; - - if (ppc_md.progress) - ppc_md.progress("smp_hdpu_kick_cpu", 0); - - hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_CPU1_KICK); - - /* Disable BootCS. Must also reduce the windows size to zero. */ - bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 0, 0, 0); - - bootaddr = ioremap(HDPU_INTERNAL_SRAM_BASE, HDPU_INTERNAL_SRAM_SIZE); - if (!bootaddr) { - if (ppc_md.progress) - ppc_md.progress("smp_hdpu_kick_cpu: ioremap failed", 0); - return; - } - - memcpy((void *)(bootaddr + 0x40), (void *)&smp_hdpu_CPU_two, 0x20); - - /* map SRAM to 0xfff00000 */ - bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, - 0xfff00000, HDPU_INTERNAL_SRAM_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - - /* Enable CPU1 arbitration */ - mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1 << 9)); - - /* - * Wait 100mSecond until other CPU has reached __secondary_start. - * When it reaches, it is permittable to rever the SRAM mapping etc... - */ - mdelay(100); - *(unsigned long *)KERNELBASE = nr; - asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory"); - - iounmap(bootaddr); - - /* Set up window for internal sram (256KByte insize) */ - bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, - HDPU_INTERNAL_SRAM_BASE, - HDPU_INTERNAL_SRAM_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - /* - * Set up windows for embedded FLASH (using boot CS window). - */ - - bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, - HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); -} - -static void smp_hdpu_setup_cpu(int cpu_nr) -{ - if (cpu_nr == 0) { - if (ppc_md.progress) - ppc_md.progress("smp_hdpu_setup_cpu 0", 0); - mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff); - mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff); - request_irq(60, hdpu_smp_cpu0_int_handler, - IRQF_DISABLED, hdpu_smp0, 0); - } - - if (cpu_nr == 1) { - if (ppc_md.progress) - ppc_md.progress("smp_hdpu_setup_cpu 1", 0); - - hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | - CPUSTATE_KERNEL_CPU1_OK); - - /* Enable L1 Parity Bits */ - hdpu_set_l1pe(); - - /* Enable L2 cache */ - _set_L2CR(0); - _set_L2CR(0x80080000); - - mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0); - mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff); - request_irq(28, hdpu_smp_cpu1_int_handler, - IRQF_DISABLED, hdpu_smp1, 0); - } - -} - -void __devinit hdpu_tben_give() -{ - volatile unsigned long *val = 0; - - /* By writing 0 to the TBEN_BASE, the timebases is frozen */ - val = ioremap(HDPU_TBEN_BASE, 4); - *val = 0; - mb(); - - spin_lock(&timebase_lock); - timebase_upper = get_tbu(); - timebase_lower = get_tbl(); - spin_unlock(&timebase_lock); - - while (timebase_upper || timebase_lower) - barrier(); - - /* By writing 1 to the TBEN_BASE, the timebases is thawed */ - *val = 1; - mb(); - - iounmap(val); - -} - -void __devinit hdpu_tben_take() -{ - while (!(timebase_upper || timebase_lower)) - barrier(); - - spin_lock(&timebase_lock); - set_tb(timebase_upper, timebase_lower); - timebase_upper = 0; - timebase_lower = 0; - spin_unlock(&timebase_lock); -} - -static struct smp_ops_t hdpu_smp_ops = { - .message_pass = smp_hdpu_message_pass, - .probe = smp_hdpu_probe, - .kick_cpu = smp_hdpu_kick_cpu, - .setup_cpu = smp_hdpu_setup_cpu, - .give_timebase = hdpu_tben_give, - .take_timebase = hdpu_tben_take, -}; -#endif /* CONFIG_SMP */ - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(r3, r4, r5, r6, r7); - - isa_mem_base = 0; - - ppc_md.setup_arch = hdpu_setup_arch; - ppc_md.init = hdpu_init2; - ppc_md.show_cpuinfo = hdpu_show_cpuinfo; - ppc_md.init_IRQ = hdpu_init_irq; - ppc_md.get_irq = mv64360_get_irq; - ppc_md.restart = hdpu_restart; - ppc_md.power_off = hdpu_power_off; - ppc_md.halt = hdpu_halt; - ppc_md.find_end_of_memory = hdpu_find_end_of_memory; - ppc_md.calibrate_decr = hdpu_calibrate_decr; - ppc_md.setup_io_mappings = hdpu_map_io; - - bh.p_base = CONFIG_MV64X60_NEW_BASE; - bh.v_base = (unsigned long *)bh.p_base; - - hdpu_set_bat(); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) - ppc_md.progress = hdpu_mpsc_progress; /* embedded UART */ - mv64x60_progress_init(bh.p_base); -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ - -#ifdef CONFIG_SMP - smp_ops = &hdpu_smp_ops; -#endif /* CONFIG_SMP */ - -#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) - platform_notify = hdpu_platform_notify; -#endif - return; -} - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) -/* SMP safe version of the serial text debug routine. Uses Semaphore 0 */ -void hdpu_mpsc_progress(char *s, unsigned short hex) -{ - while (mv64x60_read(&bh, MV64360_WHO_AM_I) != - mv64x60_read(&bh, MV64360_SEMAPHORE_0)) { - } - mv64x60_mpsc_progress(s, hex); - mv64x60_write(&bh, MV64360_SEMAPHORE_0, 0xff); -} -#endif - -static void hdpu_cpustate_set(unsigned char new_state) -{ - unsigned int state = (new_state << 21); - mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (0xff << 21)); - mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, state); -} - -#ifdef CONFIG_MTD_PHYSMAP -static struct mtd_partition hdpu_partitions[] = { - { - .name = "Root FS", - .size = 0x03400000, - .offset = 0, - .mask_flags = 0, - },{ - .name = "User FS", - .size = 0x00800000, - .offset = 0x03400000, - .mask_flags = 0, - },{ - .name = "Kernel Image", - .size = 0x002C0000, - .offset = 0x03C00000, - .mask_flags = 0, - },{ - .name = "bootEnv", - .size = 0x00040000, - .offset = 0x03EC0000, - .mask_flags = 0, - },{ - .name = "bootROM", - .size = 0x00100000, - .offset = 0x03F00000, - .mask_flags = 0, - } -}; - -static int __init hdpu_setup_mtd(void) -{ - - physmap_set_partitions(hdpu_partitions, 5); - return 0; -} - -arch_initcall(hdpu_setup_mtd); -#endif - -#ifdef CONFIG_HDPU_FEATURES - -static struct resource hdpu_cpustate_resources[] = { - [0] = { - .name = "addr base", - .start = MV64x60_GPP_VALUE_SET, - .end = MV64x60_GPP_VALUE_CLR + 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource hdpu_nexus_resources[] = { - [0] = { - .name = "nexus register", - .start = HDPU_NEXUS_ID_BASE, - .end = HDPU_NEXUS_ID_BASE + HDPU_NEXUS_ID_SIZE, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device hdpu_cpustate_device = { - .name = HDPU_CPUSTATE_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(hdpu_cpustate_resources), - .resource = hdpu_cpustate_resources, -}; - -static struct platform_device hdpu_nexus_device = { - .name = HDPU_NEXUS_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(hdpu_nexus_resources), - .resource = hdpu_nexus_resources, -}; - -static int __init hdpu_add_pds(void) -{ - platform_device_register(&hdpu_cpustate_device); - platform_device_register(&hdpu_nexus_device); - return 0; -} - -arch_initcall(hdpu_add_pds); -#endif diff --git a/arch/ppc/platforms/hdpu.h b/arch/ppc/platforms/hdpu.h deleted file mode 100644 index f9e020b6970c..000000000000 --- a/arch/ppc/platforms/hdpu.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Definitions for Sky Computers HDPU board. - * - * Brian Waite - * - * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il - * Based on code done by Mark A. Greer - * Based on code done by Tim Montgomery - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to - * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. - * We'll only use one PCI MEM window on each PCI bus. - * - * This is the CPU physical memory map (windows must be at least 64K and start - * on a boundary that is a multiple of the window size): - * - * 0x80000000-0x8fffffff - PCI 0 MEM - * 0xa0000000-0xafffffff - PCI 1 MEM - * 0xc0000000-0xc0ffffff - PCI 0 I/O - * 0xc1000000-0xc1ffffff - PCI 1 I/O - - * 0xf1000000-0xf100ffff - MV64360 Registers - * 0xf1010000-0xfb9fffff - HOLE - * 0xfbfa0000-0xfbfaffff - TBEN - * 0xfbf00000-0xfbfbffff - NEXUS - * 0xfbfc0000-0xfbffffff - Internal SRAM - * 0xfc000000-0xffffffff - Boot window - */ - -#ifndef __PPC_PLATFORMS_HDPU_H -#define __PPC_PLATFORMS_HDPU_H - -/* CPU Physical Memory Map setup. */ -#define HDPU_BRIDGE_REG_BASE 0xf1000000 - -#define HDPU_TBEN_BASE 0xfbfa0000 -#define HDPU_TBEN_SIZE 0x00010000 -#define HDPU_NEXUS_ID_BASE 0xfbfb0000 -#define HDPU_NEXUS_ID_SIZE 0x00010000 -#define HDPU_INTERNAL_SRAM_BASE 0xfbfc0000 -#define HDPU_INTERNAL_SRAM_SIZE 0x00040000 -#define HDPU_EMB_FLASH_BASE 0xfc000000 -#define HDPU_EMB_FLASH_SIZE 0x04000000 - -/* PCI Mappings */ - -#define HDPU_PCI0_MEM_START_PROC_ADDR 0x80000000 -#define HDPU_PCI0_MEM_START_PCI_HI_ADDR 0x00000000 -#define HDPU_PCI0_MEM_START_PCI_LO_ADDR HDPU_PCI0_MEM_START_PROC_ADDR -#define HDPU_PCI0_MEM_SIZE 0x10000000 - -#define HDPU_PCI1_MEM_START_PROC_ADDR 0xc0000000 -#define HDPU_PCI1_MEM_START_PCI_HI_ADDR 0x00000000 -#define HDPU_PCI1_MEM_START_PCI_LO_ADDR HDPU_PCI1_MEM_START_PROC_ADDR -#define HDPU_PCI1_MEM_SIZE 0x20000000 - -#define HDPU_PCI0_IO_START_PROC_ADDR 0xc0000000 -#define HDPU_PCI0_IO_START_PCI_ADDR 0x00000000 -#define HDPU_PCI0_IO_SIZE 0x01000000 - -#define HDPU_PCI1_IO_START_PROC_ADDR 0xc1000000 -#define HDPU_PCI1_IO_START_PCI_ADDR 0x01000000 -#define HDPU_PCI1_IO_SIZE 0x01000000 - -#define HDPU_DEFAULT_BAUD 115200 -#define HDPU_MPSC_CLK_SRC 8 /* TCLK */ -#define HDPU_MPSC_CLK_FREQ 133000000 /* 133 Mhz */ - -#define HDPU_PCI_0_IRQ (8+64) -#define HDPU_PCI_1_IRQ (13+64) - -#endif /* __PPC_PLATFORMS_HDPU_H */ diff --git a/arch/ppc/platforms/hermes.h b/arch/ppc/platforms/hermes.h deleted file mode 100644 index de91afff8ca1..000000000000 --- a/arch/ppc/platforms/hermes.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Multidata HERMES-PRO ( / SL ) board specific definitions - * - * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de) - */ - -#ifndef __MACH_HERMES_H -#define __MACH_HERMES_H - - -#include - -#define HERMES_IMMR_BASE 0xFF000000 /* phys. addr of IMMR */ -#define HERMES_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR HERMES_IMMR_BASE /* physical base address of IMMR area */ -#define IMAP_SIZE HERMES_IMAP_SIZE /* mapped size of IMMR area */ - -#define FEC_INTERRUPT 9 /* = SIU_LEVEL4 */ -#define CPM_INTERRUPT 11 /* = SIU_LEVEL5 (was: SIU_LEVEL2) */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* __MACH_HERMES_H */ diff --git a/arch/ppc/platforms/ip860.h b/arch/ppc/platforms/ip860.h deleted file mode 100644 index 2f1f86ce1447..000000000000 --- a/arch/ppc/platforms/ip860.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * MicroSys IP860 VMEBus board specific definitions - * - * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de) - */ - -#ifndef __MACH_IP860_H -#define __MACH_IP860_H - - -#include - -#define IP860_IMMR_BASE 0xF1000000 /* phys. addr of IMMR */ -#define IP860_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR IP860_IMMR_BASE /* physical base address of IMMR area */ -#define IMAP_SIZE IP860_IMAP_SIZE /* mapped size of IMMR area */ - -/* - * MPC8xx Chip Select Usage - */ -#define IP860_BOOT_CS 0 /* Boot (VMEBus or Flash) Chip Select 0 */ -#define IP860_FLASH_CS 1 /* Flash is on Chip Select 1 */ -#define IP860_SDRAM_CS 2 /* SDRAM is on Chip Select 2 */ -#define IP860_SRAM_CS 3 /* SRAM is on Chip Select 3 */ -#define IP860_BCSR_CS 4 /* BCSR is on Chip Select 4 */ -#define IP860_IP_CS 5 /* IP Slots are on Chip Select 5 */ -#define IP860_VME_STD_CS 6 /* VME Standard I/O is on Chip Select 6 */ -#define IP860_VME_SHORT_CS 7 /* VME Short I/O is on Chip Select 7 */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* __MACH_IP860_H */ diff --git a/arch/ppc/platforms/ivms8.h b/arch/ppc/platforms/ivms8.h deleted file mode 100644 index 9109e684ad9b..000000000000 --- a/arch/ppc/platforms/ivms8.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Speech Design Integrated Voicemail board specific definitions - * - IVMS8 (small, 8 channels) - * - IVML24 (large, 24 channels) - * - * In 2.5 when we force a new bootloader, we can merge these two, and add - * in _MACH_'s for them. -- Tom - * - * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de) - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IVMS8_H__ -#define __ASM_IVMS8_H__ - - -#include - -#define IVMS_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */ -#define IVMS_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR IVMS_IMMR_BASE /* phys. base address of IMMR area */ -#define IMAP_SIZE IVMS_IMAP_SIZE /* mapped size of IMMR area */ - -#define PCMCIA_MEM_ADDR ((uint)0xFE100000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define FEC_INTERRUPT 9 /* = SIU_LEVEL4 */ -#define IDE0_INTERRUPT 10 /* = IRQ5 */ -#define CPM_INTERRUPT 11 /* = SIU_LEVEL5 (was: SIU_LEVEL2) */ -#define PHY_INTERRUPT 12 /* = IRQ6 */ - -/* override the default number of IDE hardware interfaces */ -#define MAX_HWIFS 1 - -/* - * Definitions for IDE0 Interface - */ -#define IDE0_BASE_OFFSET 0x0000 /* Offset in PCMCIA memory */ -#define IDE0_DATA_REG_OFFSET 0x0000 -#define IDE0_ERROR_REG_OFFSET 0x0081 -#define IDE0_NSECTOR_REG_OFFSET 0x0082 -#define IDE0_SECTOR_REG_OFFSET 0x0083 -#define IDE0_LCYL_REG_OFFSET 0x0084 -#define IDE0_HCYL_REG_OFFSET 0x0085 -#define IDE0_SELECT_REG_OFFSET 0x0086 -#define IDE0_STATUS_REG_OFFSET 0x0087 -#define IDE0_CONTROL_REG_OFFSET 0x0106 -#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */ - -/* We don't use the 8259. */ -#define NR_8259_INTS 0 - -#endif /* __ASM_IVMS8_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c deleted file mode 100644 index fe6e88cdb1cd..000000000000 --- a/arch/ppc/platforms/katana.c +++ /dev/null @@ -1,902 +0,0 @@ -/* - * Board setup routines for the Artesyn Katana cPCI boards. - * - * Author: Tim Montgomery - * Maintained by: Mark A. Greer - * - * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il - * Based on code done by - Mark A. Greer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -/* - * Supports the Artesyn 750i, 752i, and 3750. The 752i is virtually identical - * to the 750i except that it has an mv64460 bridge. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct mv64x60_handle bh; -static katana_id_t katana_id; -static void __iomem *cpld_base; -static void __iomem *sram_base; -static u32 katana_flash_size_0; -static u32 katana_flash_size_1; -static u32 katana_bus_frequency; -static struct pci_controller katana_hose_a; - -unsigned char __res[sizeof(bd_t)]; - -/* PCI Interrupt routing */ -static int __init -katana_irq_lookup_750i(unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - /* IDSEL 4 (PMC 1) */ - { KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i, - KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i }, - /* IDSEL 5 (PMC 2) */ - { KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i, - KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i }, - /* IDSEL 6 (T8110) */ - {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 }, - /* IDSEL 7 (unused) */ - {0, 0, 0, 0 }, - /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */ - {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 }, - }; - const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4; - - return PCI_IRQ_TABLE_LOOKUP; -} - -static int __init -katana_irq_lookup_3750(unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */ - { KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/ - { KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/ - }; - const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4; - - return PCI_IRQ_TABLE_LOOKUP; -} - -static int __init -katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - switch (katana_id) { - case KATANA_ID_750I: - case KATANA_ID_752I: - return katana_irq_lookup_750i(idsel, pin); - - case KATANA_ID_3750: - return katana_irq_lookup_3750(idsel, pin); - - default: - printk(KERN_ERR "Bogus board ID\n"); - return 0; - } -} - -/* Board info retrieval routines */ -void __init -katana_get_board_id(void) -{ - switch (in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)) { - case KATANA_PRODUCT_ID_3750: - katana_id = KATANA_ID_3750; - break; - - case KATANA_PRODUCT_ID_750i: - katana_id = KATANA_ID_750I; - break; - - case KATANA_PRODUCT_ID_752i: - katana_id = KATANA_ID_752I; - break; - - default: - printk(KERN_ERR "Unsupported board\n"); - } -} - -int __init -katana_get_proc_num(void) -{ - u16 val; - u8 save_exclude; - static int proc = -1; - static u8 first_time = 1; - - if (first_time) { - if (katana_id != KATANA_ID_3750) - proc = 0; - else { - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - - early_read_config_word(bh.hose_b, 0, - PCI_DEVFN(0,0), PCI_DEVICE_ID, &val); - - mv64x60_pci_exclude_bridge = save_exclude; - - switch(val) { - case PCI_DEVICE_ID_KATANA_3750_PROC0: - proc = 0; - break; - - case PCI_DEVICE_ID_KATANA_3750_PROC1: - proc = 1; - break; - - case PCI_DEVICE_ID_KATANA_3750_PROC2: - proc = 2; - break; - - default: - printk(KERN_ERR "Bogus Device ID\n"); - } - } - - first_time = 0; - } - - return proc; -} - -static inline int -katana_is_monarch(void) -{ - return in_8(cpld_base + KATANA_CPLD_BD_CFG_3) & - KATANA_CPLD_BD_CFG_3_MONARCH; -} - -static void __init -katana_setup_bridge(void) -{ - struct pci_controller hose; - struct mv64x60_setup_info si; - void __iomem *vaddr; - int i; - u32 v; - u16 val, type; - u8 save_exclude; - - /* - * Some versions of the Katana firmware mistakenly change the vendor - * & device id fields in the bridge's pci device (visible via pci - * config accesses). This breaks mv64x60_init() because those values - * are used to identify the type of bridge that's there. Artesyn - * claims that the subsystem vendor/device id's will have the correct - * Marvell values so this code puts back the correct values from there. - */ - memset(&hose, 0, sizeof(hose)); - vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE); - setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR, - vaddr + MV64x60_PCI0_CONFIG_DATA); - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - - early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val); - - if (val != PCI_VENDOR_ID_MARVELL) { - early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), - PCI_SUBSYSTEM_VENDOR_ID, &val); - early_write_config_word(&hose, 0, PCI_DEVFN(0, 0), - PCI_VENDOR_ID, val); - early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), - PCI_SUBSYSTEM_ID, &val); - early_write_config_word(&hose, 0, PCI_DEVFN(0, 0), - PCI_DEVICE_ID, val); - } - - /* - * While we're in here, set the hotswap register correctly. - * Turn off blue LED; mask ENUM#, clear insertion & extraction bits. - */ - early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0), - MV64360_PCICFG_CPCI_HOTSWAP, &v); - v &= ~(1<<19); - v |= ((1<<17) | (1<<22) | (1<<23)); - early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0), - MV64360_PCICFG_CPCI_HOTSWAP, v); - - /* While we're at it, grab the bridge type for later */ - early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type); - - mv64x60_pci_exclude_bridge = save_exclude; - iounmap(vaddr); - - memset(&si, 0, sizeof(si)); - - si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; - - si.pci_1.enable_bus = 1; - si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR; - si.pci_1.pci_io.pci_base_hi = 0; - si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR; - si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE; - si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR; - si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR; - si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR; - si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE; - si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_cmd_bits = 0; - si.pci_1.latency_timer = 0x80; - - for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { -#if defined(CONFIG_NOT_COHERENT_CACHE) - si.cpu_prot_options[i] = 0; - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; - - si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_NONE | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; -#else - si.cpu_prot_options[i] = 0; - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; - - si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_WB | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | - ((type == PCI_DEVICE_ID_MARVELL_MV64360) ? - MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES : - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES); -#endif - } - - /* Lookup PCI host bridges */ - if (mv64x60_init(&bh, &si)) - printk(KERN_WARNING "Bridge initialization failed.\n"); - - pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */ - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = katana_map_irq; - ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; - - mv64x60_set_bus(&bh, 1, 0); - bh.hose_b->first_busno = 0; - bh.hose_b->last_busno = 0xff; - - /* - * Need to access hotswap reg which is in the pci config area of the - * bridge's hose 0. Note that pcibios_alloc_controller() can't be used - * to alloc hose_a b/c that would make hose 0 known to the generic - * pci code which we don't want. - */ - bh.hose_a = &katana_hose_a; - setup_indirect_pci_nomap(bh.hose_a, - bh.v_base + MV64x60_PCI0_CONFIG_ADDR, - bh.v_base + MV64x60_PCI0_CONFIG_DATA); -} - -/* Bridge & platform setup routines */ -void __init -katana_intr_setup(void) -{ - if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */ - mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15); - - /* MPP 8, 9, and 10 */ - mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff); - - /* MPP 14 */ - if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) - mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000); - - /* - * Define GPP 8,9,and 10 interrupt polarity as active low - * input signal and level triggered - */ - mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700); - mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700); - - if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) { - mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14)); - mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14)); - } - - /* Config GPP intr ctlr to respond to level trigger */ - mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10)); - - if (bh.type == MV64x60_TYPE_MV64360) { - /* Erratum FEr PCI-#9 */ - mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, - (1<<4) | (1<<5) | (1<<6) | (1<<7)); - mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9)); - } else { - mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7)); - mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, - (1<<4) | (1<<5) | (1<<8) | (1<<9)); - } - - /* - * Dismiss and then enable interrupt on GPP interrupt cause - * for CPU #0 - */ - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700); - mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700); - - if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) { - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14)); - mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14)); - } - - /* - * Dismiss and then enable interrupt on CPU #0 high cause reg - * BIT25 summarizes GPP interrupts 8-15 - */ - mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25)); -} - -void __init -katana_setup_peripherals(void) -{ - u32 base; - - /* Set up windows for boot CS, soldered & socketed flash, and CPLD */ - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, - KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - - /* Assume firmware set up window sizes correctly for dev 0 & 1 */ - mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base, - &katana_flash_size_0); - - if (katana_flash_size_0 > 0) { - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, - KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); - } - - mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base, - &katana_flash_size_1); - - if (katana_flash_size_1 > 0) { - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, - (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0), - katana_flash_size_1, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); - } - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, - KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, - KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); - cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, - KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); - - /* Set up Enet->SRAM window */ - mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, - KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2); - bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); - - /* Give enet r/w access to memory region */ - mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1))); - mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1))); - mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1))); - - mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3)); - mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, - ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24))); - - /* Must wait until window set up before retrieving board id */ - katana_get_board_id(); - - /* Enumerate pci bus (must know board id before getting proc number) */ - if (katana_get_proc_num() == 0) - bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0); - -#if defined(CONFIG_NOT_COHERENT_CACHE) - mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000); -#else - mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); -#endif - - /* - * Setting the SRAM to 0. Note that this generates parity errors on - * internal data path in SRAM since it's first time accessing it - * while after reset it's not configured. - */ - memset(sram_base, 0, MV64360_SRAM_SIZE); - - /* Only processor zero [on 3750] is an PCI interrupt controller */ - if (katana_get_proc_num() == 0) - katana_intr_setup(); -} - -static void __init -katana_enable_ipmi(void) -{ - u8 reset_out; - - /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */ - reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT); - reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL; - out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out); -} - -static void __init -katana_setup_arch(void) -{ - if (ppc_md.progress) - ppc_md.progress("katana_setup_arch: enter", 0); - - set_tb(0, 0); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - /* - * Set up the L2CR register. - * - * 750FX has only L2E, L2PE (bits 2-8 are reserved) - * DD2.0 has bug that requires the L2 to be in WRT mode - * avoid dirty data in cache - */ - if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) { - printk(KERN_INFO "DD2.0 detected. Setting L2 cache" - "to Writethrough mode\n"); - _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT); - } else - _set_L2CR(L2CR_L2E | L2CR_L2PE); - - if (ppc_md.progress) - ppc_md.progress("katana_setup_arch: calling setup_bridge", 0); - - katana_setup_bridge(); - katana_setup_peripherals(); - katana_enable_ipmi(); - - katana_bus_frequency = katana_bus_freq(cpld_base); - - printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n"); - if (ppc_md.progress) - ppc_md.progress("katana_setup_arch: exit", 0); -} - -void -katana_fixup_resources(struct pci_dev *dev) -{ - u16 v16; - - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES>>2); - - pci_read_config_word(dev, PCI_COMMAND, &v16); - v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK; - pci_write_config_word(dev, PCI_COMMAND, v16); -} - -static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */ - 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/ - 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/ -}; - -static int -katana_get_cpu_freq(void) -{ - unsigned long pll_cfg; - - pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27; - return katana_bus_frequency * cpu_750xx[pll_cfg]/2; -} - -/* Platform device data fixup routines. */ -#if defined(CONFIG_SERIAL_MPSC) -static void __init -katana_fixup_mpsc_pdata(struct platform_device *pdev) -{ - struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data; - bd_t *bdp = (bd_t *)__res; - - if (bdp->bi_baudrate) - pdata->default_baud = bdp->bi_baudrate; - else - pdata->default_baud = KATANA_DEFAULT_BAUD; - - pdata->max_idle = 40; - pdata->brg_clk_src = KATANA_MPSC_CLK_SRC; - /* - * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts, - * TCLK == SysCLK but on 64460, they are separate pins. - * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz. - */ - pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX); -} -#endif - -#if defined(CONFIG_MV643XX_ETH) -static void __init -katana_fixup_eth_pdata(struct platform_device *pdev) -{ - struct mv643xx_eth_platform_data *eth_pd; - static u16 phy_addr[] = { - KATANA_ETH0_PHY_ADDR, - KATANA_ETH1_PHY_ADDR, - KATANA_ETH2_PHY_ADDR, - }; - - eth_pd = pdev->dev.platform_data; - eth_pd->force_phy_addr = 1; - eth_pd->phy_addr = phy_addr[pdev->id]; - eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE; - eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE; -} -#endif - -#if defined(CONFIG_SYSFS) -static void __init -katana_fixup_mv64xxx_pdata(struct platform_device *pdev) -{ - struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *) - pdev->dev.platform_data; - - /* Katana supports the mv64xxx hotswap register */ - pdata->hs_reg_valid = 1; -} -#endif - -static int -katana_platform_notify(struct device *dev) -{ - static struct { - char *bus_id; - void ((*rtn)(struct platform_device *pdev)); - } dev_map[] = { -#if defined(CONFIG_SERIAL_MPSC) - { MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata }, - { MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata }, -#endif -#if defined(CONFIG_MV643XX_ETH) - { MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata }, - { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata }, - { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata }, -#endif -#if defined(CONFIG_SYSFS) - { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata }, -#endif - }; - struct platform_device *pdev; - int i; - - if (dev && dev->bus_id) - for (i=0; ibus_id, dev_map[i].bus_id, - BUS_ID_SIZE)) { - pdev = container_of(dev, - struct platform_device, dev); - dev_map[i].rtn(pdev); - } - - return 0; -} - -#ifdef CONFIG_MTD_PHYSMAP - -#ifndef MB -#define MB (1 << 20) -#endif - -/* - * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB. - * - * FLASH Amount: 128 64 32 16 - * ------------- --- -- -- -- - * Monitor: 1 1 1 1 - * Primary Kernel: 1.5 1.5 1.5 1.5 - * Primary fs: 30 30 - * Secondary Kernel: 1.5 1.5 N/A N/A - * Secondary fs: N/A N/A - * User: - */ -static int __init -katana_setup_mtd(void) -{ - u32 size; - int ptbl_entries; - static struct mtd_partition *ptbl; - - size = katana_flash_size_0 + katana_flash_size_1; - if (!size) - return -ENOMEM; - - ptbl_entries = (size >= (64*MB)) ? 6 : 4; - - if ((ptbl = kcalloc(ptbl_entries, sizeof(struct mtd_partition), - GFP_KERNEL)) == NULL) { - printk(KERN_WARNING "Can't alloc MTD partition table\n"); - return -ENOMEM; - } - - ptbl[0].name = "Monitor"; - ptbl[0].size = KATANA_MTD_MONITOR_SIZE; - ptbl[1].name = "Primary Kernel"; - ptbl[1].offset = MTDPART_OFS_NXTBLK; - ptbl[1].size = 0x00180000; /* 1.5 MB */ - ptbl[2].name = "Primary Filesystem"; - ptbl[2].offset = MTDPART_OFS_APPEND; - ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */ - ptbl[ptbl_entries-1].name = "User FLASH"; - ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE; - ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL; - - if (size >= (64*MB)) { - ptbl[2].size = 30*MB; - ptbl[3].name = "Secondary Kernel"; - ptbl[3].offset = MTDPART_OFS_NXTBLK; - ptbl[3].size = 0x00180000; /* 1.5 MB */ - ptbl[4].name = "Secondary Filesystem"; - ptbl[4].offset = MTDPART_OFS_APPEND; - ptbl[4].size = MTDPART_SIZ_FULL; - } - - physmap_map.size = size; - physmap_set_partitions(ptbl, ptbl_entries); - return 0; -} -arch_initcall(katana_setup_mtd); -#endif - -static void -katana_restart(char *cmd) -{ - ulong i = 10000000; - - /* issue hard reset to the reset command register */ - out_8(cpld_base + KATANA_CPLD_RST_CMD, KATANA_CPLD_RST_CMD_HR); - - while (i-- > 0) ; - panic("restart failed\n"); -} - -static void -katana_halt(void) -{ - u8 v; - - /* Turn on blue LED to indicate its okay to remove */ - if (katana_id == KATANA_ID_750I) { - u32 v; - u8 save_exclude; - - /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */ - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0), - MV64360_PCICFG_CPCI_HOTSWAP, &v); - v &= 0xff; - v |= (1 << 19); - early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0), - MV64360_PCICFG_CPCI_HOTSWAP, v); - mv64x60_pci_exclude_bridge = save_exclude; - } else if (katana_id == KATANA_ID_752I) { - v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF); - v |= HSL_PLD_HOT_SWAP_LED_BIT; - out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v); - } - - while (1) ; - /* NOTREACHED */ -} - -static void -katana_power_off(void) -{ - katana_halt(); - /* NOTREACHED */ -} - -static int -katana_show_cpuinfo(struct seq_file *m) -{ - char *s; - - seq_printf(m, "cpu freq\t: %dMHz\n", - (katana_get_cpu_freq() + 500000) / 1000000); - seq_printf(m, "bus freq\t: %ldMHz\n", - ((long)katana_bus_frequency + 500000) / 1000000); - seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n"); - - seq_printf(m, "board\t\t: "); - switch (katana_id) { - case KATANA_ID_3750: - seq_printf(m, "Katana 3750"); - break; - - case KATANA_ID_750I: - seq_printf(m, "Katana 750i"); - break; - - case KATANA_ID_752I: - seq_printf(m, "Katana 752i"); - break; - - default: - seq_printf(m, "Unknown"); - break; - } - seq_printf(m, " (product id: 0x%x)\n", - in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)); - - seq_printf(m, "pci mode\t: %sMonarch\n", - katana_is_monarch()? "" : "Non-"); - seq_printf(m, "hardware rev\t: 0x%x\n", - in_8(cpld_base+KATANA_CPLD_HARDWARE_VER)); - seq_printf(m, "pld rev\t\t: 0x%x\n", - in_8(cpld_base + KATANA_CPLD_PLD_VER)); - - switch(bh.type) { - case MV64x60_TYPE_GT64260A: - s = "gt64260a"; - break; - case MV64x60_TYPE_GT64260B: - s = "gt64260b"; - break; - case MV64x60_TYPE_MV64360: - s = "mv64360"; - break; - case MV64x60_TYPE_MV64460: - s = "mv64460"; - break; - default: - s = "Unknown"; - } - seq_printf(m, "bridge type\t: %s\n", s); - seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev); -#if defined(CONFIG_NOT_COHERENT_CACHE) - seq_printf(m, "coherency\t: %s\n", "off"); -#else - seq_printf(m, "coherency\t: %s\n", "on"); -#endif - - return 0; -} - -static void __init -katana_calibrate_decr(void) -{ - u32 freq; - - freq = katana_bus_frequency / 4; - - printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", - (long)freq / 1000000, (long)freq % 1000000); - - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); -} - -/* - * The katana supports both uImage and zImage. If uImage, get the mem size - * from the bd info. If zImage, the bootwrapper adds a BI_MEMSIZE entry in - * the bi_rec data which is sucked out and put into boot_mem_size by - * parse_bootinfo(). MMU_init() will then use the boot_mem_size for the mem - * size and not call this routine. The only way this will fail is when a uImage - * is used but the fw doesn't pass in a valid bi_memsize. This should never - * happen, though. - */ -unsigned long __init -katana_find_end_of_memory(void) -{ - bd_t *bdp = (bd_t *)__res; - return bdp->bi_memsize; -} - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) -static void __init -katana_map_io(void) -{ - io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO); -} -#endif - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) - * are non-zero, then we should use the board info from the bd_t - * structure and the cmdline pointed to by r6 instead of the - * information from birecs, if any. Otherwise, use the information - * from birecs as discovered by the preceding call to - * parse_bootinfo(). This rule should work with both PPCBoot, which - * uses a bd_t board info structure, and the kernel boot wrapper, - * which uses birecs. - */ - if (r3 && r6) { - /* copy board info structure */ - memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t)); - /* copy command line */ - *(char *)(r7+KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6+KERNELBASE)); - } - -#ifdef CONFIG_BLK_DEV_INITRD - /* take care of initrd if we have one */ - if (r4) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - isa_mem_base = 0; - - ppc_md.setup_arch = katana_setup_arch; - ppc_md.pcibios_fixup_resources = katana_fixup_resources; - ppc_md.show_cpuinfo = katana_show_cpuinfo; - ppc_md.init_IRQ = mv64360_init_irq; - ppc_md.get_irq = mv64360_get_irq; - ppc_md.restart = katana_restart; - ppc_md.power_off = katana_power_off; - ppc_md.halt = katana_halt; - ppc_md.find_end_of_memory = katana_find_end_of_memory; - ppc_md.calibrate_decr = katana_calibrate_decr; - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) - ppc_md.setup_io_mappings = katana_map_io; - ppc_md.progress = mv64x60_mpsc_progress; - mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); -#endif - -#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) - platform_notify = katana_platform_notify; -#endif -} diff --git a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h deleted file mode 100644 index 0a9b036526b1..000000000000 --- a/arch/ppc/platforms/katana.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Definitions for Artesyn Katana750i/3750 board. - * - * Author: Tim Montgomery - * Maintained by: Mark A. Greer - * - * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il - * Based on code done by Mark A. Greer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to - * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. - * We'll only use one PCI MEM window on each PCI bus. - * - * This is the CPU physical memory map (windows must be at least 64 KB and start - * on a boundary that is a multiple of the window size): - * - * 0xff800000-0xffffffff - Boot window - * 0xf8400000-0xf843ffff - Internal SRAM - * 0xf8200000-0xf83fffff - CPLD - * 0xf8100000-0xf810ffff - MV64360 Registers (CONFIG_MV64X60_NEW_BASE) - * 0xf8000000-0xf80fffff - Socketed FLASH - * 0xe0000000-0xefffffff - Soldered FLASH - * 0xc0000000-0xc3ffffff - PCI I/O (second hose) - * 0x80000000-0xbfffffff - PCI MEM (second hose) - */ - -#ifndef __PPC_PLATFORMS_KATANA_H -#define __PPC_PLATFORMS_KATANA_H - -/* CPU Physical Memory Map setup. */ -#define KATANA_BOOT_WINDOW_BASE 0xff800000 -#define KATANA_BOOT_WINDOW_SIZE 0x00800000 /* 8 MB */ -#define KATANA_INTERNAL_SRAM_BASE 0xf8400000 -#define KATANA_CPLD_BASE 0xf8200000 -#define KATANA_CPLD_SIZE 0x00200000 /* 2 MB */ -#define KATANA_SOCKET_BASE 0xf8000000 -#define KATANA_SOCKETED_FLASH_SIZE 0x00100000 /* 1 MB */ -#define KATANA_SOLDERED_FLASH_BASE 0xe0000000 -#define KATANA_SOLDERED_FLASH_SIZE 0x10000000 /* 256 MB */ - -#define KATANA_PCI1_MEM_START_PROC_ADDR 0x80000000 -#define KATANA_PCI1_MEM_START_PCI_HI_ADDR 0x00000000 -#define KATANA_PCI1_MEM_START_PCI_LO_ADDR 0x80000000 -#define KATANA_PCI1_MEM_SIZE 0x40000000 /* 1 GB */ -#define KATANA_PCI1_IO_START_PROC_ADDR 0xc0000000 -#define KATANA_PCI1_IO_START_PCI_ADDR 0x00000000 -#define KATANA_PCI1_IO_SIZE 0x04000000 /* 64 MB */ - -/* Board-specific IRQ info */ -#define KATANA_PCI_INTA_IRQ_3750 (64+8) -#define KATANA_PCI_INTB_IRQ_3750 (64+9) -#define KATANA_PCI_INTC_IRQ_3750 (64+10) - -#define KATANA_PCI_INTA_IRQ_750i (64+8) -#define KATANA_PCI_INTB_IRQ_750i (64+9) -#define KATANA_PCI_INTC_IRQ_750i (64+10) -#define KATANA_PCI_INTD_IRQ_750i (64+14) - -#define KATANA_CPLD_RST_EVENT 0x00000000 -#define KATANA_CPLD_RST_CMD 0x00001000 -#define KATANA_CPLD_PCI_ERR_INT_EN 0x00002000 -#define KATANA_CPLD_PCI_ERR_INT_PEND 0x00003000 -#define KATANA_CPLD_PRODUCT_ID 0x00004000 -#define KATANA_CPLD_EREADY 0x00005000 - -#define KATANA_CPLD_HARDWARE_VER 0x00007000 -#define KATANA_CPLD_PLD_VER 0x00008000 -#define KATANA_CPLD_BD_CFG_0 0x00009000 -#define KATANA_CPLD_BD_CFG_1 0x0000a000 -#define KATANA_CPLD_BD_CFG_3 0x0000c000 -#define KATANA_CPLD_LED 0x0000d000 -#define KATANA_CPLD_RESET_OUT 0x0000e000 - -#define KATANA_CPLD_RST_EVENT_INITACT 0x80 -#define KATANA_CPLD_RST_EVENT_SW 0x40 -#define KATANA_CPLD_RST_EVENT_WD 0x20 -#define KATANA_CPLD_RST_EVENT_COPS 0x10 -#define KATANA_CPLD_RST_EVENT_COPH 0x08 -#define KATANA_CPLD_RST_EVENT_CPCI 0x02 -#define KATANA_CPLD_RST_EVENT_FP 0x01 - -#define KATANA_CPLD_RST_CMD_SCL 0x80 -#define KATANA_CPLD_RST_CMD_SDA 0x40 -#define KATANA_CPLD_RST_CMD_I2C 0x10 -#define KATANA_CPLD_RST_CMD_FR 0x08 -#define KATANA_CPLD_RST_CMD_SR 0x04 -#define KATANA_CPLD_RST_CMD_HR 0x01 - -#define KATANA_CPLD_BD_CFG_0_SYSCLK_MASK 0xc0 -#define KATANA_CPLD_BD_CFG_0_SYSCLK_200 0x00 -#define KATANA_CPLD_BD_CFG_0_SYSCLK_166 0x80 -#define KATANA_CPLD_BD_CFG_0_SYSCLK_133 0xc0 -#define KATANA_CPLD_BD_CFG_0_SYSCLK_100 0x40 - -#define KATANA_CPLD_BD_CFG_1_FL_BANK_MASK 0x03 -#define KATANA_CPLD_BD_CFG_1_FL_BANK_16MB 0x00 -#define KATANA_CPLD_BD_CFG_1_FL_BANK_32MB 0x01 -#define KATANA_CPLD_BD_CFG_1_FL_BANK_64MB 0x02 -#define KATANA_CPLD_BD_CFG_1_FL_BANK_128MB 0x03 - -#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_MASK 0x04 -#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_ONE 0x00 -#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_TWO 0x04 - -#define KATANA_CPLD_BD_CFG_3_MONARCH 0x04 - -#define KATANA_CPLD_RESET_OUT_PORTSEL 0x80 -#define KATANA_CPLD_RESET_OUT_WD 0x20 -#define KATANA_CPLD_RESET_OUT_COPH 0x08 -#define KATANA_CPLD_RESET_OUT_PCI_RST_PCI 0x02 -#define KATANA_CPLD_RESET_OUT_PCI_RST_FP 0x01 - -#define KATANA_MBOX_RESET_REQUEST 0xC83A -#define KATANA_MBOX_RESET_ACK 0xE430 -#define KATANA_MBOX_RESET_DONE 0x32E5 - -#define HSL_PLD_BASE 0x00010000 -#define HSL_PLD_J4SGA_REG_OFF 0 -#define HSL_PLD_J4GA_REG_OFF 1 -#define HSL_PLD_J2GA_REG_OFF 2 -#define HSL_PLD_HOT_SWAP_OFF 6 -#define HSL_PLD_HOT_SWAP_LED_BIT 0x1 -#define GA_MASK 0x1f -#define HSL_PLD_SIZE 0x1000 -#define K3750_GPP_GEO_ADDR_PINS 0xf8000000 -#define K3750_GPP_GEO_ADDR_SHIFT 27 - -#define K3750_GPP_EVENT_PROC_0 (1 << 21) -#define K3750_GPP_EVENT_PROC_1_2 (1 << 2) - -#define PCI_VENDOR_ID_ARTESYN 0x1223 -#define PCI_DEVICE_ID_KATANA_3750_PROC0 0x0041 -#define PCI_DEVICE_ID_KATANA_3750_PROC1 0x0042 -#define PCI_DEVICE_ID_KATANA_3750_PROC2 0x0043 - -#define COPROC_MEM_FUNCTION 0 -#define COPROC_MEM_BAR 0 -#define COPROC_REGS_FUNCTION 0 -#define COPROC_REGS_BAR 4 -#define COPROC_FLASH_FUNCTION 2 -#define COPROC_FLASH_BAR 4 - -#define KATANA_IPMB_LOCAL_I2C_ADDR 0x08 - -#define KATANA_DEFAULT_BAUD 9600 -#define KATANA_MPSC_CLK_SRC 8 /* TCLK */ - -#define KATANA_MTD_MONITOR_SIZE (1 << 20) /* 1 MB */ - -#define KATANA_ETH0_PHY_ADDR 12 -#define KATANA_ETH1_PHY_ADDR 11 -#define KATANA_ETH2_PHY_ADDR 4 - -#define KATANA_PRODUCT_ID_3750 0x01 -#define KATANA_PRODUCT_ID_750i 0x02 -#define KATANA_PRODUCT_ID_752i 0x04 - -#define KATANA_ETH_TX_QUEUE_SIZE 800 -#define KATANA_ETH_RX_QUEUE_SIZE 400 - -#define KATANA_ETH_PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -#define KATANA_ETH_PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -#define KATANA_ETH_PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT - -#define KATANA_ETH_PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ATTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_9700BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX - -#ifndef __ASSEMBLY__ - -typedef enum { - KATANA_ID_3750, - KATANA_ID_750I, - KATANA_ID_752I, - KATANA_ID_MAX -} katana_id_t; - -#endif - -static inline u32 -katana_bus_freq(void __iomem *cpld_base) -{ - u8 bd_cfg_0; - - bd_cfg_0 = in_8(cpld_base + KATANA_CPLD_BD_CFG_0); - - switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) { - case KATANA_CPLD_BD_CFG_0_SYSCLK_200: - return 200000000; - break; - - case KATANA_CPLD_BD_CFG_0_SYSCLK_166: - return 166666666; - break; - - case KATANA_CPLD_BD_CFG_0_SYSCLK_133: - return 133333333; - break; - - case KATANA_CPLD_BD_CFG_0_SYSCLK_100: - return 100000000; - break; - - default: - return 133333333; - break; - } -} - -#endif /* __PPC_PLATFORMS_KATANA_H */ diff --git a/arch/ppc/platforms/lantec.h b/arch/ppc/platforms/lantec.h deleted file mode 100644 index 5e5eb6d0f6aa..000000000000 --- a/arch/ppc/platforms/lantec.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * LANTEC board specific definitions - * - * Copyright (c) 2001 Wolfgang Denk (wd@denx.de) - */ - -#ifndef __MACH_LANTEC_H -#define __MACH_LANTEC_H - - -#include - -#define IMAP_ADDR 0xFFF00000 /* physical base address of IMMR area */ -#define IMAP_SIZE (64 * 1024) /* mapped size of IMMR area */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* __MACH_LANTEC_H */ diff --git a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c deleted file mode 100644 index b9e9db63f65b..000000000000 --- a/arch/ppc/platforms/lite5200.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Platform support file for the Freescale LITE5200 based on MPC52xx. - * A maximum of this file should be moved to syslib/mpc52xx_????? - * so that new platform based on MPC52xx need a minimal platform file - * ( avoid code duplication ) - * - * - * Maintainer : Sylvain Munaut - * - * Based on the 2.4 code written by Kent Borg, - * Dale Farnsworth and - * Wolfgang Denk - * - * Copyright 2004-2005 Sylvain Munaut - * Copyright 2003 Motorola Inc. - * Copyright 2003 MontaVista Software Inc. - * Copyright 2003 DENX Software Engineering (wd@denx.de) - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - - -extern int powersave_nap; - -/* Board data given by U-Boot */ -bd_t __res; -EXPORT_SYMBOL(__res); /* For modules */ - - -/* ======================================================================== */ -/* Platform specific code */ -/* ======================================================================== */ - -/* Supported PSC function in "preference" order */ -struct mpc52xx_psc_func mpc52xx_psc_functions[] = { - { .id = 0, - .func = "uart", - }, - { .id = -1, /* End entry */ - .func = NULL, - } - }; - - -static int -lite5200_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "machine\t\t: Freescale LITE5200\n"); - return 0; -} - -#ifdef CONFIG_PCI -#ifdef CONFIG_LITE5200B -static int -lite5200_map_irq(struct pci_dev *dev, unsigned char idsel, - unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {MPC52xx_IRQ0, MPC52xx_IRQ1, MPC52xx_IRQ2, MPC52xx_IRQ3}, - {MPC52xx_IRQ1, MPC52xx_IRQ2, MPC52xx_IRQ3, MPC52xx_IRQ0}, - }; - - const long min_idsel = 24, max_idsel = 25, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} -#else /* Original Lite */ -static int -lite5200_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - return (pin == 1) && (idsel==24) ? MPC52xx_IRQ0 : -1; -} -#endif -#endif - -static void __init -lite5200_setup_cpu(void) -{ - struct mpc52xx_gpio __iomem *gpio; - struct mpc52xx_intr __iomem *intr; - - u32 port_config; - u32 intr_ctrl; - - /* Map zones */ - gpio = ioremap(MPC52xx_PA(MPC52xx_GPIO_OFFSET), MPC52xx_GPIO_SIZE); - intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE); - - if (!gpio || !intr) { - printk(KERN_ERR __FILE__ ": " - "Error while mapping GPIO/INTR during " - "lite5200_setup_cpu\n"); - goto unmap_regs; - } - - /* Get port mux config */ - port_config = in_be32(&gpio->port_config); - - /* 48Mhz internal, pin is GPIO */ - port_config &= ~0x00800000; - - /* USB port */ - port_config &= ~0x00007000; /* Differential mode - USB1 only */ - port_config |= 0x00001000; - - /* ATA CS is on csb_4/5 */ - port_config &= ~0x03000000; - port_config |= 0x01000000; - - /* Commit port config */ - out_be32(&gpio->port_config, port_config); - - /* IRQ[0-3] setup */ - intr_ctrl = in_be32(&intr->ctrl); - intr_ctrl &= ~0x00ff0000; -#ifdef CONFIG_LITE5200B - /* IRQ[0-3] Level Active Low */ - intr_ctrl |= 0x00ff0000; -#else - /* IRQ0 Level Active Low - * IRQ[1-3] Level Active High */ - intr_ctrl |= 0x00c00000; -#endif - out_be32(&intr->ctrl, intr_ctrl); - - /* Unmap reg zone */ -unmap_regs: - if (gpio) iounmap(gpio); - if (intr) iounmap(intr); -} - -static void __init -lite5200_setup_arch(void) -{ - /* CPU & Port mux setup */ - mpc52xx_setup_cpu(); /* Generic */ - lite5200_setup_cpu(); /* Platform specific */ - -#ifdef CONFIG_PCI - /* PCI Bridge setup */ - mpc52xx_find_bridges(); -#endif -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - /* Generic MPC52xx platform initialization */ - /* TODO Create one and move a max of stuff in it. - Put this init in the syslib */ - - struct bi_record *bootinfo = find_bootinfo(); - - if (bootinfo) - parse_bootinfo(bootinfo); - else { - /* Load the bd_t board info structure */ - if (r3) - memcpy((void*)&__res,(void*)(r3+KERNELBASE), - sizeof(bd_t)); - -#ifdef CONFIG_BLK_DEV_INITRD - /* Load the initrd */ - if (r4) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif - - /* Load the command line */ - if (r6) { - *(char *)(r7+KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6+KERNELBASE)); - } - } - - /* PPC Sys identification */ - identify_ppc_sys_by_id(mfspr(SPRN_SVR)); - - /* BAT setup */ - mpc52xx_set_bat(); - - /* No ISA bus by default */ -#ifdef CONFIG_PCI - isa_io_base = 0; - isa_mem_base = 0; -#endif - - /* Powersave */ - /* This is provided as an example on how to do it. But you - need to be aware that NAP disable bus snoop and that may - be required for some devices to work properly, like USB ... */ - /* powersave_nap = 1; */ - - - /* Setup the ppc_md struct */ - ppc_md.setup_arch = lite5200_setup_arch; - ppc_md.show_cpuinfo = lite5200_show_cpuinfo; - ppc_md.show_percpuinfo = NULL; - ppc_md.init_IRQ = mpc52xx_init_irq; - ppc_md.get_irq = mpc52xx_get_irq; - -#ifdef CONFIG_PCI - ppc_md.pci_map_irq = lite5200_map_irq; -#endif - - ppc_md.find_end_of_memory = mpc52xx_find_end_of_memory; - ppc_md.setup_io_mappings = mpc52xx_map_io; - - ppc_md.restart = mpc52xx_restart; - ppc_md.power_off = mpc52xx_power_off; - ppc_md.halt = mpc52xx_halt; - - /* No time keeper on the LITE5200 */ - ppc_md.time_init = NULL; - ppc_md.get_rtc_time = NULL; - ppc_md.set_rtc_time = NULL; - - ppc_md.calibrate_decr = mpc52xx_calibrate_decr; -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = mpc52xx_progress; -#endif -} - diff --git a/arch/ppc/platforms/lite5200.h b/arch/ppc/platforms/lite5200.h deleted file mode 100644 index 852a18e24d0b..000000000000 --- a/arch/ppc/platforms/lite5200.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Definitions for Freescale LITE5200 : MPC52xx Standard Development - * Platform board support - * - * Maintainer : Sylvain Munaut - * - * Copyright (C) 2004 Sylvain Munaut - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef __PLATFORMS_LITE5200_H__ -#define __PLATFORMS_LITE5200_H__ - -/* Serial port used for low-level debug */ -#define MPC52xx_PF_CONSOLE_PORT 1 /* PSC1 */ - - -#endif /* __PLATFORMS_LITE5200_H__ */ diff --git a/arch/ppc/platforms/lopec.c b/arch/ppc/platforms/lopec.c deleted file mode 100644 index 1e3aa6e9b6c7..000000000000 --- a/arch/ppc/platforms/lopec.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Setup routines for the Motorola LoPEC. - * - * Author: Dan Cox - * Maintainer: Tom Rini - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Define all of the IRQ senses and polarities. Taken from the - * LoPEC Programmer's Reference Guide. - */ -static u_char lopec_openpic_initsenses[16] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 4 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 5 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 6 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 7 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 8 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 9 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 10 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 11 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 12 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 13 */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ 14 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* IRQ 15 */ -}; - -static inline int __init -lopec_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - int irq; - static char pci_irq_table[][4] = { - {16, 0, 0, 0}, /* ID 11 - Winbond */ - {22, 0, 0, 0}, /* ID 12 - SCSI */ - {0, 0, 0, 0}, /* ID 13 - nothing */ - {17, 0, 0, 0}, /* ID 14 - 82559 Ethernet */ - {27, 0, 0, 0}, /* ID 15 - USB */ - {23, 0, 0, 0}, /* ID 16 - PMC slot 1 */ - {24, 0, 0, 0}, /* ID 17 - PMC slot 2 */ - {25, 0, 0, 0}, /* ID 18 - PCI slot */ - {0, 0, 0, 0}, /* ID 19 - nothing */ - {0, 0, 0, 0}, /* ID 20 - nothing */ - {0, 0, 0, 0}, /* ID 21 - nothing */ - {0, 0, 0, 0}, /* ID 22 - nothing */ - {0, 0, 0, 0}, /* ID 23 - nothing */ - {0, 0, 0, 0}, /* ID 24 - PMC slot 1b */ - {0, 0, 0, 0}, /* ID 25 - nothing */ - {0, 0, 0, 0} /* ID 26 - PMC Slot 2b */ - }; - const long min_idsel = 11, max_idsel = 26, irqs_per_slot = 4; - - irq = PCI_IRQ_TABLE_LOOKUP; - if (!irq) - return 0; - - return irq; -} - -static void __init -lopec_setup_winbond_83553(struct pci_controller *hose) -{ - int devfn; - - devfn = PCI_DEVFN(11,0); - - /* IDE interrupt routing (primary 14, secondary 15) */ - early_write_config_byte(hose, 0, devfn, 0x43, 0xef); - /* PCI interrupt routing */ - early_write_config_word(hose, 0, devfn, 0x44, 0x0000); - - /* ISA-PCI address decoder */ - early_write_config_byte(hose, 0, devfn, 0x48, 0xf0); - - /* RTC, kb, not used in PPC */ - early_write_config_byte(hose, 0, devfn, 0x4d, 0x00); - early_write_config_byte(hose, 0, devfn, 0x4e, 0x04); - devfn = PCI_DEVFN(11, 1); - early_write_config_byte(hose, 0, devfn, 0x09, 0x8f); - early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011); -} - -static void __init -lopec_find_bridges(void) -{ - struct pci_controller *hose; - - hose = pcibios_alloc_controller(); - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - if (mpc10x_bridge_init(hose, MPC10X_MEM_MAP_B, MPC10X_MEM_MAP_B, - MPC10X_MAPB_EUMB_BASE) == 0) { - - hose->mem_resources[0].end = 0xffffffff; - lopec_setup_winbond_83553(hose); - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = lopec_map_irq; - } -} - -static int -lopec_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "machine\t\t: Motorola LoPEC\n"); - return 0; -} - -static void -lopec_restart(char *cmd) -{ -#define LOPEC_SYSSTAT1 0xffe00000 - /* force a hard reset, if possible */ - unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1); - reg |= 0x80; - *((unsigned char *) LOPEC_SYSSTAT1) = reg; - - local_irq_disable(); - while(1); -#undef LOPEC_SYSSTAT1 -} - -static void -lopec_halt(void) -{ - local_irq_disable(); - while(1); -} - -static void -lopec_power_off(void) -{ - lopec_halt(); -} - -static void __init -lopec_init_IRQ(void) -{ - int i; - - /* - * Provide the open_pic code with the correct table of interrupts. - */ - OpenPIC_InitSenses = lopec_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses); - - mpc10x_set_openpic(); - - /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */ - openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", - &i8259_irq); - - /* - * The EPIC allows for a read in the range of 0xFEF00000 -> - * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction. - */ - i8259_init(0xfef00000, 0); -} - -static int __init -lopec_request_io(void) -{ - outb(0x00, 0x4d0); - outb(0xc0, 0x4d1); - - request_region(0x00, 0x20, "dma1"); - request_region(0x20, 0x20, "pic1"); - request_region(0x40, 0x20, "timer"); - request_region(0x80, 0x10, "dma page reg"); - request_region(0xa0, 0x20, "pic2"); - request_region(0xc0, 0x20, "dma2"); - - return 0; -} - -device_initcall(lopec_request_io); - -static void __init -lopec_map_io(void) -{ - io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO); - io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO); -} - -/* - * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1. - */ -static __inline__ void -lopec_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT1U, 0xf8000ffe); - mtspr(SPRN_DBAT1L, 0xf800002a); - mb(); -} - -TODC_ALLOC(); - -static void __init -lopec_setup_arch(void) -{ - - TODC_INIT(TODC_TYPE_MK48T37, 0, 0, - ioremap(0xffe80000, 0x8000), 8); - - loops_per_jiffy = 100000000/HZ; - - lopec_find_bridges(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#elif defined(CONFIG_ROOT_NFS) - ROOT_DEV = Root_NFS; -#elif defined(CONFIG_BLK_DEV_IDEDISK) - ROOT_DEV = Root_HDA1; -#else - ROOT_DEV = Root_SDA1; -#endif - -#ifdef CONFIG_PPCBUG_NVRAM - /* Read in NVRAM data */ - init_prep_nvram(); - - /* if no bootargs, look in NVRAM */ - if ( cmd_line[0] == '\0' ) { - char *bootargs; - bootargs = prep_nvram_get_var("bootargs"); - if (bootargs != NULL) { - strcpy(cmd_line, bootargs); - /* again.. */ - strcpy(boot_command_line, cmd_line); - } - } -#endif -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - lopec_set_bat(); - - isa_io_base = MPC10X_MAPB_ISA_IO_BASE; - isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE; - pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET; - ISA_DMA_THRESHOLD = 0x00ffffff; - DMA_MODE_READ = 0x44; - DMA_MODE_WRITE = 0x48; - ppc_do_canonicalize_irqs = 1; - - ppc_md.setup_arch = lopec_setup_arch; - ppc_md.show_cpuinfo = lopec_show_cpuinfo; - ppc_md.init_IRQ = lopec_init_IRQ; - ppc_md.get_irq = openpic_get_irq; - - ppc_md.restart = lopec_restart; - ppc_md.power_off = lopec_power_off; - ppc_md.halt = lopec_halt; - - ppc_md.setup_io_mappings = lopec_map_io; - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.calibrate_decr = todc_calibrate_decr; - - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; - -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif -} diff --git a/arch/ppc/platforms/lopec.h b/arch/ppc/platforms/lopec.h deleted file mode 100644 index d597b6878693..000000000000 --- a/arch/ppc/platforms/lopec.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * arch/ppc/platforms/lopec.h - * - * Definitions for Motorola LoPEC board. - * - * Author: Dan Cox - * danc@mvista.com (or, alternately, source@mvista.com) - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __H_LOPEC_SERIAL -#define __H_LOPEC_SERIAL - -#define RS_TABLE_SIZE 3 - -#define BASE_BAUD (1843200 / 16) - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST) -#endif - -#define SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, 0xffe10000, 29, STD_COM_FLAGS, \ - iomem_base: (u8 *) 0xffe10000, \ - io_type: SERIAL_IO_MEM }, \ - { 0, BASE_BAUD, 0xffe11000, 20, STD_COM_FLAGS, \ - iomem_base: (u8 *) 0xffe11000, \ - io_type: SERIAL_IO_MEM }, \ - { 0, BASE_BAUD, 0xffe12000, 21, STD_COM_FLAGS, \ - iomem_base: (u8 *) 0xffe12000, \ - io_type: SERIAL_IO_MEM } - -#endif diff --git a/arch/ppc/platforms/lwmon.h b/arch/ppc/platforms/lwmon.h deleted file mode 100644 index e63f3b07a5db..000000000000 --- a/arch/ppc/platforms/lwmon.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Liebherr LWMON board specific definitions - * - * Copyright (c) 2001 Wolfgang Denk (wd@denx.de) - */ - -#ifndef __MACH_LWMON_H -#define __MACH_LWMON_H - - -#include - -#define IMAP_ADDR 0xFFF00000 /* physical base address of IMMR area */ -#define IMAP_SIZE (64 * 1024) /* mapped size of IMMR area */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define PCMCIA_MEM_SIZE ( 64 << 20 ) - -#define MAX_HWIFS 1 /* overwrite default in include/asm-ppc/ide.h */ - -/* - * Definitions for IDE0 Interface - */ -#define IDE0_BASE_OFFSET 0 -#define IDE0_DATA_REG_OFFSET (PCMCIA_MEM_SIZE + 0x320) -#define IDE0_ERROR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 1) -#define IDE0_NSECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 2) -#define IDE0_SECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 3) -#define IDE0_LCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 4) -#define IDE0_HCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 5) -#define IDE0_SELECT_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 6) -#define IDE0_STATUS_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 7) -#define IDE0_CONTROL_REG_OFFSET 0x0106 -#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */ - -#define IDE0_INTERRUPT 13 - -/* - * Definitions for I2C devices - */ -#define I2C_ADDR_AUDIO 0x28 /* Audio volume control */ -#define I2C_ADDR_SYSMON 0x2E /* LM87 System Monitor */ -#define I2C_ADDR_RTC 0x51 /* PCF8563 RTC */ -#define I2C_ADDR_POWER_A 0x52 /* PCMCIA/USB power switch, channel A */ -#define I2C_ADDR_POWER_B 0x53 /* PCMCIA/USB power switch, channel B */ -#define I2C_ADDR_KEYBD 0x56 /* PIC LWE keyboard */ -#define I2C_ADDR_PICIO 0x57 /* PIC IO Expander */ -#define I2C_ADDR_EEPROM 0x58 /* EEPROM AT24C164 */ - - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* __MACH_LWMON_H */ diff --git a/arch/ppc/platforms/mbx.h b/arch/ppc/platforms/mbx.h deleted file mode 100644 index 1cf36fa3592d..000000000000 --- a/arch/ppc/platforms/mbx.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola MBX boards. This was originally created for the - * MBX860, and probably needs revisions for other boards (like the 821). - * When this file gets out of control, we can split it up into more - * meaningful pieces. - * - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - */ -#ifdef __KERNEL__ -#ifndef __MACH_MBX_DEFS -#define __MACH_MBX_DEFS - -#ifndef __ASSEMBLY__ -/* A Board Information structure that is given to a program when - * EPPC-Bug starts it up. - */ -typedef struct bd_info { - unsigned int bi_tag; /* Should be 0x42444944 "BDID" */ - unsigned int bi_size; /* Size of this structure */ - unsigned int bi_revision; /* revision of this structure */ - unsigned int bi_bdate; /* EPPCbug date, i.e. 0x11061997 */ - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in Hz */ - unsigned int bi_clun; /* Boot device controller */ - unsigned int bi_dlun; /* Boot device logical dev */ - - /* These fields are not part of the board information structure - * provided by the boot rom. They are filled in by embed_config.c - * so we have the information consistent with other platforms. - */ - unsigned char bi_enetaddr[6]; - unsigned int bi_baudrate; -} bd_t; - -/* Memory map for the MBX as configured by EPPC-Bug. We could reprogram - * The SIU and PCI bridge, and try to use larger MMU pages, but the - * performance gain is not measurable and it certainly complicates the - * generic MMU model. - * - * In a effort to minimize memory usage for embedded applications, any - * PCI driver or ISA driver must request or map the region required by - * the device. For convenience (and since we can map up to 4 Mbytes with - * a single page table page), the MMU initialization will map the - * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI - * Bridge CSRs 1:1 into the kernel address space. - */ -#define PCI_ISA_IO_ADDR ((unsigned)0x80000000) -#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024)) -#define PCI_IDE_ADDR ((unsigned)0x81000000) -#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000) -#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024)) -#define PCMCIA_MEM_ADDR ((uint)0xe0000000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024 * 1024)) -#define PCMCIA_DMA_ADDR ((uint)0xe4000000) -#define PCMCIA_DMA_SIZE ((uint)(64 * 1024 * 1024)) -#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000) -#define PCMCIA_ATTRB_SIZE ((uint)(64 * 1024 * 1024)) -#define PCMCIA_IO_ADDR ((uint)0xec000000) -#define PCMCIA_IO_SIZE ((uint)(64 * 1024 * 1024)) -#define NVRAM_ADDR ((uint)0xfa000000) -#define NVRAM_SIZE ((uint)(1 * 1024 * 1024)) -#define MBX_CSR_ADDR ((uint)0xfa100000) -#define MBX_CSR_SIZE ((uint)(1 * 1024 * 1024)) -#define IMAP_ADDR ((uint)0xfa200000) -#define IMAP_SIZE ((uint)(64 * 1024)) -#define PCI_CSR_ADDR ((uint)0xfa210000) -#define PCI_CSR_SIZE ((uint)(64 * 1024)) - -/* Map additional physical space into well known virtual addresses. Due - * to virtual address mapping, these physical addresses are not accessible - * in a 1:1 virtual to physical mapping. - */ -#define ISA_IO_VIRT_ADDR ((uint)0xfa220000) -#define ISA_IO_VIRT_SIZE ((uint)64 * 1024) - -/* Interrupt assignments. - * These are defined (and fixed) by the MBX hardware implementation. - */ -#define POWER_FAIL_INT SIU_IRQ0 /* Power fail */ -#define TEMP_HILO_INT SIU_IRQ1 /* Temperature sensor */ -#define QSPAN_INT SIU_IRQ2 /* PCI Bridge (DMA CTLR?) */ -#define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */ -#define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */ -#define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */ - -/* CPM Ethernet through SCCx. - * - * Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. The TCLK and RCLK seem unique - * to the MBX860 board. Any two of the four available clocks could be - * used, and the MPC860 cookbook manual has an example using different - * clock pins. - */ -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PC_ENET_TENA ((ushort)0x0001) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) - -/* The MBX uses the 8259. -*/ -#define NR_8259_INTS 16 - -#endif /* !__ASSEMBLY__ */ -#endif /* __MACH_MBX_DEFS */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c deleted file mode 100644 index 62370f4a5a0f..000000000000 --- a/arch/ppc/platforms/mpc866ads_setup.c +++ /dev/null @@ -1,413 +0,0 @@ -/*arch/ppc/platforms/mpc866ads_setup.c - * - * Platform setup for the Freescale mpc866ads board - * - * Vitaly Bordug - * - * Copyright 2005-2006 MontaVista Software Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern unsigned char __res[]; - -static void setup_fec1_ioports(struct fs_platform_info*); -static void setup_scc1_ioports(struct fs_platform_info*); -static void setup_smc1_ioports(struct fs_uart_platform_info*); -static void setup_smc2_ioports(struct fs_uart_platform_info*); - -static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata; - -static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata; - -static struct fs_platform_info mpc8xx_enet_pdata[] = { - [fsid_fec1] = { - .rx_ring = 128, - .tx_ring = 16, - .rx_copybreak = 240, - - .use_napi = 1, - .napi_weight = 17, - - .init_ioports = setup_fec1_ioports, - - .bus_id = "0:0f", - .has_phy = 1, - }, - [fsid_scc1] = { - .rx_ring = 64, - .tx_ring = 8, - .rx_copybreak = 240, - .use_napi = 1, - .napi_weight = 17, - - - .init_ioports = setup_scc1_ioports, - - .bus_id = "fixed@100:1", - }, -}; - -static struct fs_uart_platform_info mpc866_uart_pdata[] = { - [fsid_smc1_uart] = { - .brg = 1, - .fs_no = fsid_smc1_uart, - .init_ioports = setup_smc1_ioports, - .tx_num_fifo = 4, - .tx_buf_size = 32, - .rx_num_fifo = 4, - .rx_buf_size = 32, - }, - [fsid_smc2_uart] = { - .brg = 2, - .fs_no = fsid_smc2_uart, - .init_ioports = setup_smc2_ioports, - .tx_num_fifo = 4, - .tx_buf_size = 32, - .rx_num_fifo = 4, - .rx_buf_size = 32, - }, -}; - -void __init board_init(void) -{ - volatile cpm8xx_t *cp = cpmp; - unsigned *bcsr_io; - - bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); - - if (bcsr_io == NULL) { - printk(KERN_CRIT "Could not remap BCSR1\n"); - return; - } - -#ifdef CONFIG_SERIAL_CPM_SMC1 - cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */ - clrbits32(bcsr_io,(0x80000000 >> 7)); - cp->cp_smc[0].smc_smcm |= (SMCM_RX | SMCM_TX); - cp->cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); -#else - setbits32(bcsr_io,(0x80000000 >> 7)); - - cp->cp_pbpar &= ~(0x000000c0); - cp->cp_pbdir |= 0x000000c0; - cp->cp_smc[0].smc_smcmr = 0; - cp->cp_smc[0].smc_smce = 0; -#endif - -#ifdef CONFIG_SERIAL_CPM_SMC2 - cp->cp_simode &= ~(0xe0000000 >> 1); - cp->cp_simode |= (0x20000000 >> 1); /* brg2 */ - clrbits32(bcsr_io,(0x80000000 >> 13)); - cp->cp_smc[1].smc_smcm |= (SMCM_RX | SMCM_TX); - cp->cp_smc[1].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); -#else - clrbits32(bcsr_io,(0x80000000 >> 13)); - cp->cp_pbpar &= ~(0x00000c00); - cp->cp_pbdir |= 0x00000c00; - cp->cp_smc[1].smc_smcmr = 0; - cp->cp_smc[1].smc_smce = 0; -#endif - iounmap(bcsr_io); -} - -static void setup_fec1_ioports(struct fs_platform_info* pdata) -{ - immap_t *immap = (immap_t *) IMAP_ADDR; - - setbits16(&immap->im_ioport.iop_pdpar, 0x1fff); - setbits16(&immap->im_ioport.iop_pddir, 0x1fff); -} - -static void setup_scc1_ioports(struct fs_platform_info* pdata) -{ - immap_t *immap = (immap_t *) IMAP_ADDR; - unsigned *bcsr_io; - - bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); - - if (bcsr_io == NULL) { - printk(KERN_CRIT "Could not remap BCSR1\n"); - return; - } - - /* Enable the PHY. - */ - clrbits32(bcsr_io,BCSR1_ETHEN); - - /* Configure port A pins for Txd and Rxd. - */ - /* Disable receive and transmit in case EPPC-Bug started it. - */ - setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD); - clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD); - clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD); - - /* Configure port C pins to enable CLSN and RENA. - */ - clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); - clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); - setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); - /* Configure port A for TCLK and RCLK. - */ - setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK); - clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK); - clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA); - clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA); - - /* Configure Serial Interface clock routing. - * First, clear all SCC bits to zero, then set the ones we want. - */ - clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK); - setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT); - - /* In the original SCC enet driver the following code is placed at - the end of the initialization */ - setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA); - setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA); - -} - -static void setup_smc1_ioports(struct fs_uart_platform_info* pdata) -{ - immap_t *immap = (immap_t *) IMAP_ADDR; - unsigned *bcsr_io; - unsigned int iobits = 0x000000c0; - - bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); - - if (bcsr_io == NULL) { - printk(KERN_CRIT "Could not remap BCSR1\n"); - return; - } - - clrbits32(bcsr_io,BCSR1_RS232EN_1); - iounmap(bcsr_io); - - setbits32(&immap->im_cpm.cp_pbpar, iobits); - clrbits32(&immap->im_cpm.cp_pbdir, iobits); - clrbits16(&immap->im_cpm.cp_pbodr, iobits); - -} - -static void setup_smc2_ioports(struct fs_uart_platform_info* pdata) -{ - immap_t *immap = (immap_t *) IMAP_ADDR; - unsigned *bcsr_io; - unsigned int iobits = 0x00000c00; - - bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); - - if (bcsr_io == NULL) { - printk(KERN_CRIT "Could not remap BCSR1\n"); - return; - } - - clrbits32(bcsr_io,BCSR1_RS232EN_2); - - iounmap(bcsr_io); - -#ifndef CONFIG_SERIAL_CPM_ALT_SMC2 - setbits32(&immap->im_cpm.cp_pbpar, iobits); - clrbits32(&immap->im_cpm.cp_pbdir, iobits); - clrbits16(&immap->im_cpm.cp_pbodr, iobits); -#else - setbits16(&immap->im_ioport.iop_papar, iobits); - clrbits16(&immap->im_ioport.iop_padir, iobits); - clrbits16(&immap->im_ioport.iop_paodr, iobits); -#endif - -} - -static int ma_count = 0; - -static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) -{ - struct fs_platform_info *fpi; - - volatile cpm8xx_t *cp; - bd_t *bd = (bd_t *) __res; - char *e; - int i; - - /* Get pointer to Communication Processor */ - cp = cpmp; - - if(fs_no >= ARRAY_SIZE(mpc8xx_enet_pdata)) { - printk(KERN_ERR"No network-suitable #%d device on bus", fs_no); - return; - } - - - fpi = &mpc8xx_enet_pdata[fs_no]; - fpi->fs_no = fs_no; - pdev->dev.platform_data = fpi; - - e = (unsigned char *)&bd->bi_enetaddr; - for (i = 0; i < 6; i++) - fpi->macaddr[i] = *e++; - - fpi->macaddr[5] += ma_count++; -} - -static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev, - int idx) -{ - /* This is for FEC devices only */ - if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec"))) - return; - mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1); -} - -static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev, - int idx) -{ - /* This is for SCC devices only */ - if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc"))) - return; - - mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); -} - -static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev, - int idx) -{ - bd_t *bd = (bd_t *) __res; - struct fs_uart_platform_info *pinfo; - int num = ARRAY_SIZE(mpc866_uart_pdata); - - int id = fs_uart_id_smc2fsid(idx); - - /* no need to alter anything if console */ - if ((id < num) && (!pdev->dev.platform_data)) { - pinfo = &mpc866_uart_pdata[id]; - pinfo->uart_clk = bd->bi_intfreq; - pdev->dev.platform_data = pinfo; - } -} - -static int mpc866ads_platform_notify(struct device *dev) -{ - static const struct platform_notify_dev_map dev_map[] = { - { - .bus_id = "fsl-cpm-fec", - .rtn = mpc866ads_fixup_fec_enet_pdata, - }, - { - .bus_id = "fsl-cpm-scc", - .rtn = mpc866ads_fixup_scc_enet_pdata, - }, - { - .bus_id = "fsl-cpm-smc:uart", - .rtn = mpc866ads_fixup_uart_pdata - }, - { - .bus_id = NULL - } - }; - - platform_notify_map(dev_map,dev); - - return 0; -} - -int __init mpc866ads_init(void) -{ - bd_t *bd = (bd_t *) __res; - struct fs_mii_fec_platform_info* fmpi; - - printk(KERN_NOTICE "mpc866ads: Init\n"); - - platform_notify = mpc866ads_platform_notify; - - ppc_sys_device_initfunc(); - ppc_sys_device_disable_all(); - -#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC1 - ppc_sys_device_enable(MPC8xx_CPM_SCC1); -#endif - ppc_sys_device_enable(MPC8xx_CPM_FEC1); - - ppc_sys_device_enable(MPC8xx_MDIO_FEC); - - fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data = - &mpc8xx_mdio_fec_pdata; - - fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1; - /* No PHY interrupt line here */ - fmpi->irq[0xf] = PHY_POLL; - -/* Since either of the uarts could be used as console, they need to ready */ -#ifdef CONFIG_SERIAL_CPM_SMC1 - ppc_sys_device_enable(MPC8xx_CPM_SMC1); - ppc_sys_device_setfunc(MPC8xx_CPM_SMC1, PPC_SYS_FUNC_UART); -#endif - -#ifdef CONFIG_SERIAL_CPM_SMC2 - ppc_sys_device_enable(MPC8xx_CPM_SMC2); - ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART); -#endif - ppc_sys_device_enable(MPC8xx_MDIO_FEC); - - fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data = - &mpc8xx_mdio_fec_pdata; - - fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1; - /* No PHY interrupt line here */ - fmpi->irq[0xf] = PHY_POLL; - - return 0; -} - -/* - To prevent confusion, console selection is gross: - by 0 assumed SMC1 and by 1 assumed SMC2 - */ -struct platform_device* early_uart_get_pdev(int index) -{ - bd_t *bd = (bd_t *) __res; - struct fs_uart_platform_info *pinfo; - - struct platform_device* pdev = NULL; - if(index) { /*assume SMC2 here*/ - pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC2]; - pinfo = &mpc866_uart_pdata[1]; - } else { /*over SMC1*/ - pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC1]; - pinfo = &mpc866_uart_pdata[0]; - } - - pinfo->uart_clk = bd->bi_intfreq; - pdev->dev.platform_data = pinfo; - ppc_sys_fixup_mem_resource(pdev, IMAP_ADDR); - return NULL; -} - -arch_initcall(mpc866ads_init); diff --git a/arch/ppc/platforms/mvme5100.c b/arch/ppc/platforms/mvme5100.c deleted file mode 100644 index 053b54ac88f2..000000000000 --- a/arch/ppc/platforms/mvme5100.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Board setup routines for the Motorola MVME5100. - * - * Author: Matt Porter - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -static u_char mvme5100_openpic_initsenses[16] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* i8259 cascade */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* TL16C550 UART 1,2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet1 front panel or P2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Hawk Watchdog 1,2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* DS1621 thermal alarm */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT0# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT1# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT2# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT3# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTA#, PMC2 INTB# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTB#, PMC2 INTC# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTC#, PMC2 INTD# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTD#, PMC2 INTA# */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet 2 (front panel) */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Abort Switch */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* RTC Alarm */ -}; - -static inline int -mvme5100_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - int irq; - - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 0, 0, 0, 0 }, /* IDSEL 11 - Winbond */ - { 0, 0, 0, 0 }, /* IDSEL 12 - unused */ - { 21, 22, 23, 24 }, /* IDSEL 13 - Universe II */ - { 18, 0, 0, 0 }, /* IDSEL 14 - Enet 1 */ - { 0, 0, 0, 0 }, /* IDSEL 15 - unused */ - { 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */ - { 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */ - { 0, 0, 0, 0 }, /* IDSEL 18 - unused */ - { 29, 0, 0, 0 }, /* IDSEL 19 - Enet 2 */ - { 0, 0, 0, 0 }, /* IDSEL 20 - PMCSPAN */ - }; - - const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4; - irq = PCI_IRQ_TABLE_LOOKUP; - /* If lookup is zero, always return 0 */ - if (!irq) - return 0; - else -#ifdef CONFIG_MVME5100_IPMC761_PRESENT - /* If IPMC761 present, return table value */ - return irq; -#else - /* If IPMC761 not present, we don't have an i8259 so adjust */ - return (irq - NUM_8259_INTERRUPTS); -#endif -} - -static void -mvme5100_pcibios_fixup_resources(struct pci_dev *dev) -{ - int i; - - if ((dev->vendor == PCI_VENDOR_ID_MOTOROLA) && - (dev->device == PCI_DEVICE_ID_MOTOROLA_HAWK)) - for (i=0; iresource[i].start = 0; - dev->resource[i].end = 0; - } -} - -static void __init -mvme5100_setup_bridge(void) -{ - struct pci_controller* hose; - - hose = pcibios_alloc_controller(); - - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - hose->pci_mem_offset = MVME5100_PCI_MEM_OFFSET; - - pci_init_resource(&hose->io_resource, MVME5100_PCI_LOWER_IO, - MVME5100_PCI_UPPER_IO, IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource(&hose->mem_resources[0], MVME5100_PCI_LOWER_MEM, - MVME5100_PCI_UPPER_MEM, IORESOURCE_MEM, - "PCI host bridge"); - - hose->io_space.start = MVME5100_PCI_LOWER_IO; - hose->io_space.end = MVME5100_PCI_UPPER_IO; - hose->mem_space.start = MVME5100_PCI_LOWER_MEM; - hose->mem_space.end = MVME5100_PCI_UPPER_MEM; - hose->io_base_virt = (void *)MVME5100_ISA_IO_BASE; - - /* Use indirect method of Hawk */ - setup_indirect_pci(hose, MVME5100_PCI_CONFIG_ADDR, - MVME5100_PCI_CONFIG_DATA); - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pcibios_fixup_resources = mvme5100_pcibios_fixup_resources; - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = mvme5100_map_irq; -} - -static void __init -mvme5100_setup_arch(void) -{ - if ( ppc_md.progress ) - ppc_md.progress("mvme5100_setup_arch: enter", 0); - - loops_per_jiffy = 50000000 / HZ; - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - if ( ppc_md.progress ) - ppc_md.progress("mvme5100_setup_arch: find_bridges", 0); - - /* Setup PCI host bridge */ - mvme5100_setup_bridge(); - - /* Find and map our OpenPIC */ - hawk_mpic_init(MVME5100_PCI_MEM_OFFSET); - OpenPIC_InitSenses = mvme5100_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(mvme5100_openpic_initsenses); - - printk("MVME5100 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n"); - - if ( ppc_md.progress ) - ppc_md.progress("mvme5100_setup_arch: exit", 0); - - return; -} - -static void __init -mvme5100_init2(void) -{ -#ifdef CONFIG_MVME5100_IPMC761_PRESENT - request_region(0x00,0x20,"dma1"); - request_region(0x20,0x20,"pic1"); - request_region(0x40,0x20,"timer"); - request_region(0x80,0x10,"dma page reg"); - request_region(0xa0,0x20,"pic2"); - request_region(0xc0,0x20,"dma2"); -#endif - return; -} - -/* - * Interrupt setup and service. - * Have MPIC on HAWK and cascaded 8259s on Winbond cascaded to MPIC. - */ -static void __init -mvme5100_init_IRQ(void) -{ -#ifdef CONFIG_MVME5100_IPMC761_PRESENT - int i; -#endif - - if ( ppc_md.progress ) - ppc_md.progress("init_irq: enter", 0); - - openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000); -#ifdef CONFIG_MVME5100_IPMC761_PRESENT - openpic_init(NUM_8259_INTERRUPTS); - openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", - &i8259_irq); - - i8259_init(0, 0); -#else - openpic_init(0); -#endif - - if ( ppc_md.progress ) - ppc_md.progress("init_irq: exit", 0); - - return; -} - -/* - * Set BAT 3 to map 0xf0000000 to end of physical memory space. - */ -static __inline__ void -mvme5100_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT1U, 0xf0001ffe); - mtspr(SPRN_DBAT1L, 0xf000002a); - mb(); -} - -static unsigned long __init -mvme5100_find_end_of_memory(void) -{ - return hawk_get_mem_size(MVME5100_HAWK_SMC_BASE); -} - -static void __init -mvme5100_map_io(void) -{ - io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO); - ioremap_base = 0xfe000000; -} - -static void -mvme5100_reset_board(void) -{ - local_irq_disable(); - - /* Set exception prefix high - to the firmware */ - _nmask_and_or_msr(0, MSR_IP); - - out_8((u_char *)MVME5100_BOARD_MODRST_REG, 0x01); - - return; -} - -static void -mvme5100_restart(char *cmd) -{ - volatile ulong i = 10000000; - - mvme5100_reset_board(); - - while (i-- > 0); - panic("restart failed\n"); -} - -static void -mvme5100_halt(void) -{ - local_irq_disable(); - while (1); -} - -static void -mvme5100_power_off(void) -{ - mvme5100_halt(); -} - -static int -mvme5100_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: Motorola\n"); - seq_printf(m, "machine\t\t: MVME5100\n"); - - return 0; -} - -TODC_ALLOC(); - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - mvme5100_set_bat(); - - isa_io_base = MVME5100_ISA_IO_BASE; - isa_mem_base = MVME5100_ISA_MEM_BASE; - pci_dram_offset = MVME5100_PCI_DRAM_OFFSET; - - ppc_md.setup_arch = mvme5100_setup_arch; - ppc_md.show_cpuinfo = mvme5100_show_cpuinfo; - ppc_md.init_IRQ = mvme5100_init_IRQ; - ppc_md.get_irq = openpic_get_irq; - ppc_md.init = mvme5100_init2; - - ppc_md.restart = mvme5100_restart; - ppc_md.power_off = mvme5100_power_off; - ppc_md.halt = mvme5100_halt; - - ppc_md.find_end_of_memory = mvme5100_find_end_of_memory; - ppc_md.setup_io_mappings = mvme5100_map_io; - - TODC_INIT(TODC_TYPE_MK48T37, MVME5100_NVRAM_AS0, MVME5100_NVRAM_AS1, - MVME5100_NVRAM_DATA, 8); - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.calibrate_decr = todc_calibrate_decr; - - ppc_md.nvram_read_val = todc_m48txx_read_val; - ppc_md.nvram_write_val = todc_m48txx_write_val; -} diff --git a/arch/ppc/platforms/mvme5100.h b/arch/ppc/platforms/mvme5100.h deleted file mode 100644 index fbb5495165c7..000000000000 --- a/arch/ppc/platforms/mvme5100.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * arch/ppc/platforms/mvme5100.h - * - * Definitions for Motorola MVME5100. - * - * Author: Matt Porter - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_MVME5100_H__ -#define __ASM_MVME5100_H__ - -#define MVME5100_HAWK_SMC_BASE 0xfef80000 - -#define MVME5100_PCI_CONFIG_ADDR 0xfe000cf8 -#define MVME5100_PCI_CONFIG_DATA 0xfe000cfc - -#define MVME5100_PCI_IO_BASE 0xfe000000 -#define MVME5100_PCI_MEM_BASE 0x80000000 - -#define MVME5100_PCI_MEM_OFFSET 0x00000000 - -#define MVME5100_PCI_DRAM_OFFSET 0x00000000 -#define MVME5100_ISA_MEM_BASE 0x00000000 -#define MVME5100_ISA_IO_BASE MVME5100_PCI_IO_BASE - -#define MVME5100_PCI_LOWER_MEM 0x80000000 -#define MVME5100_PCI_UPPER_MEM 0xf3f7ffff -#define MVME5100_PCI_LOWER_IO 0x00000000 -#define MVME5100_PCI_UPPER_IO 0x0077ffff - -/* MVME5100 board register addresses. */ -#define MVME5100_BOARD_STATUS_REG 0xfef88080 -#define MVME5100_BOARD_MODFAIL_REG 0xfef88090 -#define MVME5100_BOARD_MODRST_REG 0xfef880a0 -#define MVME5100_BOARD_TBEN_REG 0xfef880c0 -#define MVME5100_BOARD_SW_READ_REG 0xfef880e0 -#define MVME5100_BOARD_GEO_ADDR_REG 0xfef880e8 -#define MVME5100_BOARD_EXT_FEATURE1_REG 0xfef880f0 -#define MVME5100_BOARD_EXT_FEATURE2_REG 0xfef88100 - -/* Define the NVRAM/RTC address strobe & data registers */ -#define MVME5100_PHYS_NVRAM_AS0 0xfef880c8 -#define MVME5100_PHYS_NVRAM_AS1 0xfef880d0 -#define MVME5100_PHYS_NVRAM_DATA 0xfef880d8 - -#define MVME5100_NVRAM_AS0 (MVME5100_PHYS_NVRAM_AS0 - MVME5100_ISA_IO_BASE) -#define MVME5100_NVRAM_AS1 (MVME5100_PHYS_NVRAM_AS1 - MVME5100_ISA_IO_BASE) -#define MVME5100_NVRAM_DATA (MVME5100_PHYS_NVRAM_DATA - MVME5100_ISA_IO_BASE) - -/* UART clock, addresses, and irq */ -#define MVME5100_BASE_BAUD 1843200 -#define MVME5100_SERIAL_1 0xfef88000 -#define MVME5100_SERIAL_2 0xfef88200 -#ifdef CONFIG_MVME5100_IPMC761_PRESENT -#define MVME5100_SERIAL_IRQ 17 -#else -#define MVME5100_SERIAL_IRQ 1 -#endif - -#define RS_TABLE_SIZE 4 - -#define BASE_BAUD ( MVME5100_BASE_BAUD / 16 ) - -#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF - -/* All UART IRQs are wire-OR'd to one MPIC IRQ */ -#define STD_SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, MVME5100_SERIAL_1, \ - MVME5100_SERIAL_IRQ, \ - STD_COM_FLAGS, /* ttyS0 */ \ - iomem_base: (unsigned char *)MVME5100_SERIAL_1, \ - iomem_reg_shift: 4, \ - io_type: SERIAL_IO_MEM }, \ - { 0, BASE_BAUD, MVME5100_SERIAL_2, \ - MVME5100_SERIAL_IRQ, \ - STD_COM_FLAGS, /* ttyS1 */ \ - iomem_base: (unsigned char *)MVME5100_SERIAL_2, \ - iomem_reg_shift: 4, \ - io_type: SERIAL_IO_MEM }, - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DFNS - -#endif /* __ASM_MVME5100_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/pal4.h b/arch/ppc/platforms/pal4.h deleted file mode 100644 index 8569c423d887..000000000000 --- a/arch/ppc/platforms/pal4.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Definitions for SBS Palomar IV board - * - * Author: Dan Cox - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __PPC_PLATFORMS_PAL4_H -#define __PPC_PLATFORMS_PAL4_H - -#define PAL4_NVRAM 0xfffc0000 -#define PAL4_NVRAM_SIZE 0x8000 - -#define PAL4_DRAM 0xfff80000 -#define PAL4_DRAM_BR_MASK 0xc0 -#define PAL4_DRAM_BR_SHIFT 6 -#define PAL4_DRAM_RESET 0x10 -#define PAL4_DRAM_EREADY 0x40 - -#define PAL4_MISC 0xfff80004 -#define PAL4_MISC_FB_MASK 0xc0 -#define PAL4_MISC_FLASH 0x20 /* StratFlash mapping: 1->0xff80, 0->0xfff0 */ -#define PAL4_MISC_MISC 0x08 -#define PAL4_MISC_BITF 0x02 -#define PAL4_MISC_NVKS 0x01 - -#define PAL4_L2 0xfff80008 -#define PAL4_L2_MASK 0x07 - -#define PAL4_PLDR 0xfff8000c - -/* Only two Ethernet devices on the board... */ -#define PAL4_ETH 31 -#define PAL4_INTA 20 - -#endif /* __PPC_PLATFORMS_PAL4_H */ diff --git a/arch/ppc/platforms/pal4_pci.c b/arch/ppc/platforms/pal4_pci.c deleted file mode 100644 index d81ae1c7e1cf..000000000000 --- a/arch/ppc/platforms/pal4_pci.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * PCI support for SBS Palomar IV - * - * Author: Dan Cox - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "pal4.h" - -/* not much to this.... */ -static inline int __init -pal4_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - if (idsel == 9) - return PAL4_ETH; - else - return PAL4_INTA + (idsel - 3); -} - -void __init -pal4_find_bridges(void) -{ - struct pci_controller *hose; - - hose = pcibios_alloc_controller(); - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - hose->pci_mem_offset = 0; - - /* Could snatch these from the CPC700.... */ - pci_init_resource(&hose->io_resource, - 0x0, - 0x03ffffff, - IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource(&hose->mem_resources[0], - 0x90000000, - 0x9fffffff, - IORESOURCE_MEM, - "PCI host bridge"); - - hose->io_space.start = 0x00800000; - hose->io_space.end = 0x03ffffff; - hose->mem_space.start = 0x90000000; - hose->mem_space.end = 0x9fffffff; - hose->io_base_virt = (void *) 0xf8000000; - - setup_indirect_pci(hose, CPC700_PCI_CONFIG_ADDR, - CPC700_PCI_CONFIG_DATA); - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = pal4_map_irq; -} diff --git a/arch/ppc/platforms/pal4_serial.h b/arch/ppc/platforms/pal4_serial.h deleted file mode 100644 index a75343224cfd..000000000000 --- a/arch/ppc/platforms/pal4_serial.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Definitions for SBS PalomarIV serial support - * - * Author: Dan Cox - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __PPC_PAL4_SERIAL_H -#define __PPC_PAL4_SERIAL_H - -#define CPC700_SERIAL_1 0xff600300 -#define CPC700_SERIAL_2 0xff600400 - -#define RS_TABLE_SIZE 2 -#define BASE_BAUD (33333333 / 4 / 16) - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF) -#endif - -#define SERIAL_PORT_DFNS \ - {0, BASE_BAUD, CPC700_SERIAL_1, 3, STD_COM_FLAGS, \ - iomem_base: (unsigned char *) CPC700_SERIAL_1, \ - io_type: SERIAL_IO_MEM}, /* ttyS0 */ \ - {0, BASE_BAUD, CPC700_SERIAL_2, 4, STD_COM_FLAGS, \ - iomem_base: (unsigned char *) CPC700_SERIAL_2, \ - io_type: SERIAL_IO_MEM} - -#endif diff --git a/arch/ppc/platforms/pal4_setup.c b/arch/ppc/platforms/pal4_setup.c deleted file mode 100644 index 3da47d9ec7a2..000000000000 --- a/arch/ppc/platforms/pal4_setup.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Board setup routines for the SBS PalomarIV. - * - * Author: Dan Cox - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "pal4.h" - -extern void pal4_find_bridges(void); - -unsigned int cpc700_irq_assigns[][2] = { - {1, 1}, /* IRQ 0: ECC correctable error */ - {1, 1}, /* IRQ 1: PCI write to memory range */ - {0, 1}, /* IRQ 2: PCI write to command register */ - {0, 1}, /* IRQ 3: UART 0 */ - {0, 1}, /* IRQ 4: UART 1 */ - {0, 1}, /* IRQ 5: ICC 0 */ - {0, 1}, /* IRQ 6: ICC 1 */ - {0, 1}, /* IRQ 7: GPT compare 0 */ - {0, 1}, /* IRQ 8: GPT compare 1 */ - {0, 1}, /* IRQ 9: GPT compare 2 */ - {0, 1}, /* IRQ 10: GPT compare 3 */ - {0, 1}, /* IRQ 11: GPT compare 4 */ - {0, 1}, /* IRQ 12: GPT capture 0 */ - {0, 1}, /* IRQ 13: GPT capture 1 */ - {0, 1}, /* IRQ 14: GPT capture 2 */ - {0, 1}, /* IRQ 15: GPT capture 3 */ - {0, 1}, /* IRQ 16: GPT capture 4 */ - {0, 0}, /* IRQ 17: reserved */ - {0, 0}, /* IRQ 18: reserved */ - {0, 0}, /* IRQ 19: reserved */ - {0, 0}, /* IRQ 20: reserved */ - {0, 1}, /* IRQ 21: Ethernet */ - {0, 0}, /* IRQ 22: reserved */ - {0, 0}, /* IRQ 23: reserved */ - {0, 0}, /* IRQ 24: resreved */ - {0, 0}, /* IRQ 25: reserved */ - {0, 0}, /* IRQ 26: reserved */ - {0, 0}, /* IRQ 27: reserved */ - {0, 0}, /* IRQ 28: reserved */ - {0, 0}, /* IRQ 29: reserved */ - {0, 0}, /* IRQ 30: reserved */ - {0, 0}, /* IRQ 31: reserved */ -}; - -static int -pal4_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "board\t\t: SBS Palomar IV\n"); - - return 0; -} - -static void -pal4_restart(char *cmd) -{ - local_irq_disable(); - __asm__ __volatile__("lis 3,0xfff0\n \ - ori 3,3,0x100\n \ - mtspr 26,3\n \ - li 3,0\n \ - mtspr 27,3\n \ - rfi"); - - for(;;); -} - -static void -pal4_power_off(void) -{ - local_irq_disable(); - for(;;); -} - -static void -pal4_halt(void) -{ - pal4_power_off(); -} - -TODC_ALLOC(); - -static void __init -pal4_setup_arch(void) -{ - unsigned long l2; - - TODC_INIT(TODC_TYPE_MK48T37, 0, 0, - ioremap(PAL4_NVRAM, PAL4_NVRAM_SIZE), 8); - - pal4_find_bridges(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif - ROOT_DEV = Root_NFS; - - /* The L2 gets disabled in the bootloader, but all the proper - bits should be present from the fw, so just re-enable it */ - l2 = _get_L2CR(); - if (!(l2 & L2CR_L2E)) { - /* presume that it was initially set if the size is - still present. */ - if (l2 ^ L2CR_L2SIZ_MASK) - _set_L2CR(l2 | L2CR_L2E); - else - printk("L2 not set by firmware; left disabled.\n"); - } -} - -static void __init -pal4_map_io(void) -{ - io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - isa_io_base = 0 /*PAL4_ISA_IO_BASE*/; - pci_dram_offset = 0 /*PAL4_PCI_SYS_MEM_BASE*/; - - ppc_md.setup_arch = pal4_setup_arch; - ppc_md.show_cpuinfo = pal4_show_cpuinfo; - - ppc_md.setup_io_mappings = pal4_map_io; - - ppc_md.init_IRQ = cpc700_init_IRQ; - ppc_md.get_irq = cpc700_get_irq; - - ppc_md.restart = pal4_restart; - ppc_md.halt = pal4_halt; - ppc_md.power_off = pal4_power_off; - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.calibrate_decr = todc_calibrate_decr; - - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; -} - diff --git a/arch/ppc/platforms/pcu_e.h b/arch/ppc/platforms/pcu_e.h deleted file mode 100644 index a2c03a22875e..000000000000 --- a/arch/ppc/platforms/pcu_e.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Siemens PCU E board specific definitions - * - * Copyright (c) 2001 Wolfgang Denk (wd@denx.de) - */ - -#ifndef __MACH_PCU_E_H -#define __MACH_PCU_E_H - - -#include - -#define PCU_E_IMMR_BASE 0xFE000000 /* phys. addr of IMMR */ -#define PCU_E_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR PCU_E_IMMR_BASE /* physical base address of IMMR area */ -#define IMAP_SIZE PCU_E_IMAP_SIZE /* mapped size of IMMR area */ - -#define FEC_INTERRUPT 15 /* = SIU_LEVEL7 */ -#define DEC_INTERRUPT 13 /* = SIU_LEVEL6 */ -#define CPM_INTERRUPT 11 /* = SIU_LEVEL5 (was: SIU_LEVEL2) */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* __MACH_PCU_E_H */ diff --git a/arch/ppc/platforms/powerpmc250.c b/arch/ppc/platforms/powerpmc250.c deleted file mode 100644 index 162dc85ff7be..000000000000 --- a/arch/ppc/platforms/powerpmc250.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Board setup routines for Force PowerPMC-250 Processor PMC - * - * Author: Troy Benjegerdes - * Borrowed heavily from prpmc750_*.c by - * Matt Porter - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void powerpmc250_find_bridges(void); -extern unsigned long loops_per_jiffy; - -static u_char powerpmc250_openpic_initsenses[] __initdata = -{ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, /* PMC INTA (also MPC107 output interrupt INTA) */ - 1, /* PMC INTB (also I82559 Ethernet controller) */ - 1, /* PMC INTC */ - 1, /* PMC INTD */ - 0, /* DUART interrupt (active high) */ -}; - -static int -powerpmc250_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m,"machine\t\t: Force PowerPMC250\n"); - - return 0; -} - -static void __init -powerpmc250_setup_arch(void) -{ - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - - /* Lookup PCI host bridges */ - powerpmc250_find_bridges(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - printk("Force PowerPMC250 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n"); -} - -#if 0 -/* - * Compute the PrPMC750's bus speed using the baud clock as a - * reference. - */ -unsigned long __init powerpmc250_get_bus_speed(void) -{ - unsigned long tbl_start, tbl_end; - unsigned long current_state, old_state, bus_speed; - unsigned char lcr, dll, dlm; - int baud_divisor, count; - - /* Read the UART's baud clock divisor */ - lcr = readb(PRPMC750_SERIAL_0_LCR); - writeb(lcr | UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR); - dll = readb(PRPMC750_SERIAL_0_DLL); - dlm = readb(PRPMC750_SERIAL_0_DLM); - writeb(lcr & ~UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR); - baud_divisor = (dlm << 8) | dll; - - /* - * Use the baud clock divisor and base baud clock - * to determine the baud rate and use that as - * the number of baud clock edges we use for - * the time base sample. Make it half the baud - * rate. - */ - count = PRPMC750_BASE_BAUD / (baud_divisor * 16); - - /* Find the first edge of the baud clock */ - old_state = readb(PRPMC750_STATUS_REG) & PRPMC750_BAUDOUT_MASK; - do { - current_state = readb(PRPMC750_STATUS_REG) & - PRPMC750_BAUDOUT_MASK; - } while(old_state == current_state); - - old_state = current_state; - - /* Get the starting time base value */ - tbl_start = get_tbl(); - - /* - * Loop until we have found a number of edges equal - * to half the count (half the baud rate) - */ - do { - do { - current_state = readb(PRPMC750_STATUS_REG) & - PRPMC750_BAUDOUT_MASK; - } while(old_state == current_state); - old_state = current_state; - } while (--count); - - /* Get the ending time base value */ - tbl_end = get_tbl(); - - /* Compute bus speed */ - bus_speed = (tbl_end-tbl_start)*128; - - return bus_speed; -} -#endif - -static void __init -powerpmc250_calibrate_decr(void) -{ - unsigned long freq; - int divisor = 4; - - //freq = powerpmc250_get_bus_speed(); -#warning hardcoded bus freq - freq = 100000000; - - tb_ticks_per_jiffy = freq / (HZ * divisor); - tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000); -} - -static void -powerpmc250_restart(char *cmd) -{ - local_irq_disable(); - /* Hard reset */ - writeb(0x11, 0xfe000332); - while(1); -} - -static void -powerpmc250_halt(void) -{ - local_irq_disable(); - while (1); -} - -static void -powerpmc250_power_off(void) -{ - powerpmc250_halt(); -} - -static void __init -powerpmc250_init_IRQ(void) -{ - - OpenPIC_InitSenses = powerpmc250_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(powerpmc250_openpic_initsenses); - mpc10x_set_openpic(); -} - -/* - * Set BAT 3 to map 0xf0000000 to end of physical memory space. - */ -static __inline__ void -powerpmc250_set_bat(void) -{ - unsigned long bat3u, bat3l; - static int mapping_set = 0; - - if (!mapping_set) - { - __asm__ __volatile__( - " lis %0,0xf000\n \ - ori %1,%0,0x002a\n \ - ori %0,%0,0x1ffe\n \ - mtspr 0x21e,%0\n \ - mtspr 0x21f,%1\n \ - isync\n \ - sync " - : "=r" (bat3u), "=r" (bat3l)); - - mapping_set = 1; - } - return; -} - -static unsigned long __init -powerpmc250_find_end_of_memory(void) -{ - /* Cover I/O space with a BAT */ - /* yuck, better hope your ram size is a power of 2 -- paulus */ - powerpmc250_set_bat(); - - return mpc10x_get_mem_size(MPC10X_MEM_MAP_B); -} - -static void __init -powerpmc250_map_io(void) -{ - io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - -#ifdef CONFIG_BLK_DEV_INITRD - if ( r4 ) - { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif - - /* Copy cmd_line parameters */ - if ( r6) - { - *(char *)(r7 + KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6 + KERNELBASE)); - } - - isa_io_base = MPC10X_MAPB_ISA_IO_BASE; - isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE; - pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET; - - ppc_md.setup_arch = powerpmc250_setup_arch; - ppc_md.show_cpuinfo = powerpmc250_show_cpuinfo; - ppc_md.init_IRQ = powerpmc250_init_IRQ; - ppc_md.get_irq = openpic_get_irq; - - ppc_md.find_end_of_memory = powerpmc250_find_end_of_memory; - ppc_md.setup_io_mappings = powerpmc250_map_io; - - ppc_md.restart = powerpmc250_restart; - ppc_md.power_off = powerpmc250_power_off; - ppc_md.halt = powerpmc250_halt; - - /* PowerPMC250 has no timekeeper part */ - ppc_md.time_init = NULL; - ppc_md.get_rtc_time = NULL; - ppc_md.set_rtc_time = NULL; - ppc_md.calibrate_decr = powerpmc250_calibrate_decr; -} - - -/* - * (This used to be arch/ppc/platforms/powerpmc250_pci.c) - * - * PCI support for Force PowerPMC250 - * - */ - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -static inline int __init -powerpmc250_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {17, 0, 0, 0}, /* Device 11 - 82559 */ - {0, 0, 0, 0}, /* 12 */ - {0, 0, 0, 0}, /* 13 */ - {0, 0, 0, 0}, /* 14 */ - {0, 0, 0, 0}, /* 15 */ - {16, 17, 18, 19}, /* Device 16 - PMC A1?? */ - }; - const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -}; - -static int -powerpmc250_exclude_device(u_char bus, u_char devfn) -{ - /* - * While doing PCI Scan the MPC107 will 'detect' itself as - * device on the PCI Bus, will create an incorrect response and - * later will respond incorrectly to Configuration read coming - * from another device. - * - * The work around is that when doing a PCI Scan one - * should skip its own device number in the scan. - * - * The top IDsel is AD13 and the middle is AD14. - * - * -- Note from force - */ - - if ((bus == 0) && (PCI_SLOT(devfn) == 13 || PCI_SLOT(devfn) == 14)) { - return PCIBIOS_DEVICE_NOT_FOUND; - } - else { - return PCIBIOS_SUCCESSFUL; - } -} - -void __init -powerpmc250_find_bridges(void) -{ - struct pci_controller* hose; - - hose = pcibios_alloc_controller(); - if (!hose){ - printk("Can't allocate PCI 'hose' structure!!!\n"); - return; - } - - hose->first_busno = 0; - hose->last_busno = 0xff; - - if (mpc10x_bridge_init(hose, - MPC10X_MEM_MAP_B, - MPC10X_MEM_MAP_B, - MPC10X_MAPB_EUMB_BASE) == 0) { - - hose->mem_resources[0].end = 0xffffffff; - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - /* ppc_md.pcibios_fixup = pcore_pcibios_fixup; */ - ppc_md.pci_swizzle = common_swizzle; - - ppc_md.pci_exclude_device = powerpmc250_exclude_device; - ppc_md.pci_map_irq = powerpmc250_map_irq; - } else { - if (ppc_md.progress) - ppc_md.progress("Bridge init failed", 0x100); - printk("Host bridge init failed\n"); - } - -} diff --git a/arch/ppc/platforms/powerpmc250.h b/arch/ppc/platforms/powerpmc250.h deleted file mode 100644 index d33ad8dc0439..000000000000 --- a/arch/ppc/platforms/powerpmc250.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * arch/ppc/platforms/powerpmc250.h - * - * Definitions for Force PowerPMC-250 board support - * - * Author: Troy Benjegerdes - * - * Borrowed heavily from prpmc750.h by Matt Porter - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __ASMPPC_POWERPMC250_H -#define __ASMPPC_POWERPMC250_H - -#define POWERPMC250_PCI_CONFIG_ADDR 0x80000cf8 -#define POWERPMC250_PCI_CONFIG_DATA 0x80000cfc - -#define POWERPMC250_PCI_PHY_MEM_BASE 0xc0000000 -#define POWERPMC250_PCI_MEM_BASE 0xf0000000 -#define POWERPMC250_PCI_IO_BASE 0x80000000 - -#define POWERPMC250_ISA_IO_BASE POWERPMC250_PCI_IO_BASE -#define POWERPMC250_ISA_MEM_BASE POWERPMC250_PCI_MEM_BASE -#define POWERPMC250_PCI_MEM_OFFSET POWERPMC250_PCI_PHY_MEM_BASE - -#define POWERPMC250_SYS_MEM_BASE 0x80000000 - -#define POWERPMC250_HAWK_SMC_BASE 0xfef80000 - -#define POWERPMC250_BASE_BAUD 12288000 -#define POWERPMC250_SERIAL 0xff000000 -#define POWERPMC250_SERIAL_IRQ 20 - -/* UART Defines. */ -#define RS_TABLE_SIZE 1 - -#define BASE_BAUD (POWERPMC250_BASE_BAUD / 16) - -#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF - -#define SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, POWERPMC250_SERIAL, POWERPMC250_SERIAL_IRQ, \ - STD_COM_FLAGS, /* ttyS0 */ \ - iomem_base: (u8 *)POWERPMC250_SERIAL, \ - iomem_reg_shift: 0, \ - io_type: SERIAL_IO_MEM } - -#endif /* __ASMPPC_POWERPMC250_H */ diff --git a/arch/ppc/platforms/pplus.c b/arch/ppc/platforms/pplus.c deleted file mode 100644 index cbcac85c7a78..000000000000 --- a/arch/ppc/platforms/pplus.c +++ /dev/null @@ -1,844 +0,0 @@ -/* - * Board and PCI setup routines for MCG PowerPlus - * - * Author: Randy Vinson - * - * Derived from original PowerPlus PReP work by - * Cort Dougan, Johnnie Peters, Matt Porter, and - * Troy Benjegerdes. - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pplus.h" - -#undef DUMP_DBATS - -TODC_ALLOC(); - -extern void pplus_setup_hose(void); -extern void pplus_set_VIA_IDE_native(void); - -extern unsigned long loops_per_jiffy; -unsigned char *Motherboard_map_name; - -/* Tables for known hardware */ - -/* Motorola Mesquite */ -static inline int -mesquite_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * MPIC interrupts for various IDSEL values (MPIC IRQ0 = - * Linux IRQ16 (to leave room for ISA IRQs at 0-15). - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */ - { 0, 0, 0, 0}, /* IDSEL 15 - unused */ - {19, 19, 19, 19}, /* IDSEL 16 - PMC Slot 1 */ - { 0, 0, 0, 0}, /* IDSEL 17 - unused */ - { 0, 0, 0, 0}, /* IDSEL 18 - unused */ - { 0, 0, 0, 0}, /* IDSEL 19 - unused */ - {24, 25, 26, 27}, /* IDSEL 20 - P2P bridge (to cPCI 1) */ - { 0, 0, 0, 0}, /* IDSEL 21 - unused */ - {28, 29, 30, 31} /* IDSEL 22 - P2P bridge (to cPCI 2) */ - }; - - const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -/* Motorola Sitka */ -static inline int -sitka_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * MPIC interrupts for various IDSEL values (MPIC IRQ0 = - * Linux IRQ16 (to leave room for ISA IRQs at 0-15). - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */ - { 0, 0, 0, 0}, /* IDSEL 15 - unused */ - {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */ - {28, 25, 26, 27}, /* IDSEL 17 - PMC Slot 2 */ - { 0, 0, 0, 0}, /* IDSEL 18 - unused */ - { 0, 0, 0, 0}, /* IDSEL 19 - unused */ - {20, 0, 0, 0} /* IDSEL 20 - P2P bridge (to cPCI) */ - }; - - const long min_idsel = 14, max_idsel = 20, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -/* Motorola MTX */ -static inline int -MTX_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * MPIC interrupts for various IDSEL values (MPIC IRQ0 = - * Linux IRQ16 (to leave room for ISA IRQs at 0-15). - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {19, 0, 0, 0}, /* IDSEL 12 - SCSI */ - { 0, 0, 0, 0}, /* IDSEL 13 - unused */ - {18, 0, 0, 0}, /* IDSEL 14 - Enet */ - { 0, 0, 0, 0}, /* IDSEL 15 - unused */ - {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */ - {26, 27, 28, 25}, /* IDSEL 17 - PMC Slot 2 */ - {27, 28, 25, 26} /* IDSEL 18 - PCI Slot 3 */ - }; - - const long min_idsel = 12, max_idsel = 18, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -/* Motorola MTX Plus */ -/* Secondary bus interrupt routing is not supported yet */ -static inline int -MTXplus_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * MPIC interrupts for various IDSEL values (MPIC IRQ0 = - * Linux IRQ16 (to leave room for ISA IRQs at 0-15). - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {19, 0, 0, 0}, /* IDSEL 12 - SCSI */ - { 0, 0, 0, 0}, /* IDSEL 13 - unused */ - {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */ - { 0, 0, 0, 0}, /* IDSEL 15 - unused */ - {25, 26, 27, 28}, /* IDSEL 16 - PCI Slot 1P */ - {26, 27, 28, 25}, /* IDSEL 17 - PCI Slot 2P */ - {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */ - {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */ - { 0, 0, 0, 0} /* IDSEL 20 - P2P Bridge */ - }; - - const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -static inline int -Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - /* 2600 - * Raven 31 - * ISA 11 - * SCSI 12 - IRQ3 - * Univ 13 - * eth 14 - IRQ2 - * VGA 15 - IRQ4 - * PMC1 16 - IRQ9,10,11,12 = PMC1 A-D - * PMC2 17 - IRQ12,9,10,11 = A-D - * SCSI2 18 - IRQ11 - * eth2 19 - IRQ10 - * PCIX 20 - IRQ9,10,11,12 = PCI A-D - */ - - /* 2400 - * Hawk 31 - * ISA 11 - * Univ 13 - * eth 14 - IRQ2 - * PMC1 16 - IRQ9,10,11,12 = PMC A-D - * PMC2 17 - IRQ12,9,10,11 = PMC A-D - * PCIX 20 - IRQ9,10,11,12 = PMC A-D - */ - - /* 2300 - * Raven 31 - * ISA 11 - * Univ 13 - * eth 14 - IRQ2 - * PMC1 16 - 9,10,11,12 = A-D - * PMC2 17 - 9,10,11,12 = B,C,D,A - */ - - static char pci_irq_table[][4] = - /* - * MPIC interrupts for various IDSEL values (MPIC IRQ0 = - * Linux IRQ16 (to leave room for ISA IRQs at 0-15). - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {19, 0, 0, 0}, /* IDSEL 12 - SCSI */ - { 0, 0, 0, 0}, /* IDSEL 13 - Universe PCI - VME */ - {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */ - { 0, 0, 0, 0}, /* IDSEL 15 - unused */ - {25, 26, 27, 28}, /* IDSEL 16 - PCI/PMC Slot 1P */ - {28, 25, 26, 27}, /* IDSEL 17 - PCI/PMC Slot 2P */ - {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */ - {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */ - {25, 26, 27, 28} /* IDSEL 20 - P2P Bridge */ - }; - - const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -#define MOTOROLA_CPUTYPE_REG 0x800 -#define MOTOROLA_BASETYPE_REG 0x803 -#define MPIC_RAVEN_ID 0x48010000 -#define MPIC_HAWK_ID 0x48030000 -#define MOT_PROC2_BIT 0x800 - -static u_char pplus_openpic_initsenses[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_FALCN_ECC_ERR */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_ETHERNET */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_GRAPHICS */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), -}; - -int mot_entry = -1; -int prep_keybd_present = 1; -int mot_multi = 0; - -struct brd_info { - /* 0x100 mask assumes for Raven and Hawk boards that the level/edge - * are set */ - int cpu_type; - /* 0x200 if this board has a Hawk chip. */ - int base_type; - /* or'ed with 0x80 if this board should be checked for multi CPU */ - int max_cpu; - const char *name; - int (*map_irq) (struct pci_dev *, unsigned char, unsigned char); -}; -struct brd_info mot_info[] = { - {0x300, 0x00, 0x00, "MVME 2400", Genesis2_map_irq}, - {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", mesquite_map_irq}, - {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", sitka_map_irq}, - {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", mesquite_map_irq}, - {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_map_irq}, - {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_map_irq}, - {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_map_irq}, - {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_map_irq}, - {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_map_irq}, - {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_map_irq}, - {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_map_irq}, - {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_map_irq}, - {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_map_irq}, - {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_map_irq}, - {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_map_irq}, - {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_map_irq}, - {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_map_irq}, - {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_map_irq}, - {0x000, 0x00, 0x00, "", NULL} -}; - -void __init pplus_set_board_type(void) -{ - unsigned char cpu_type; - unsigned char base_mod; - int entry; - unsigned short devid; - unsigned long *ProcInfo = NULL; - - cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0; - base_mod = inb(MOTOROLA_BASETYPE_REG); - early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid); - - for (entry = 0; mot_info[entry].cpu_type != 0; entry++) { - /* Check for Hawk chip */ - if (mot_info[entry].cpu_type & 0x200) { - if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK) - continue; - } else { - /* store the system config register for later use. */ - ProcInfo = - (unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4); - - /* Check non hawk boards */ - if ((mot_info[entry].cpu_type & 0xff) != cpu_type) - continue; - - if (mot_info[entry].base_type == 0) { - mot_entry = entry; - break; - } - - if (mot_info[entry].base_type != base_mod) - continue; - } - - if (!(mot_info[entry].max_cpu & 0x80)) { - mot_entry = entry; - break; - } - - /* processor 1 not present and max processor zero indicated */ - if ((*ProcInfo & MOT_PROC2_BIT) - && !(mot_info[entry].max_cpu & 0x7f)) { - mot_entry = entry; - break; - } - - /* processor 1 present and max processor zero indicated */ - if (!(*ProcInfo & MOT_PROC2_BIT) - && (mot_info[entry].max_cpu & 0x7f)) { - mot_entry = entry; - break; - } - - /* Indicate to system if this is a multiprocessor board */ - if (!(*ProcInfo & MOT_PROC2_BIT)) - mot_multi = 1; - } - - if (mot_entry == -1) - /* No particular cpu type found - assume Mesquite (MCP750) */ - mot_entry = 1; - - Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name; - ppc_md.pci_map_irq = mot_info[mot_entry].map_irq; -} -void __init pplus_pib_init(void) -{ - unsigned char reg; - unsigned short short_reg; - - struct pci_dev *dev = NULL; - - /* - * Perform specific configuration for the Via Tech or - * or Winbond PCI-ISA-Bridge part. - */ - if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C586_1, dev))) { - /* - * PPCBUG does not set the enable bits - * for the IDE device. Force them on here. - */ - pci_read_config_byte(dev, 0x40, ®); - - reg |= 0x03; /* IDE: Chip Enable Bits */ - pci_write_config_byte(dev, 0x40, reg); - } - - if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C586_2, - dev)) && (dev->devfn = 0x5a)) { - /* Force correct USB interrupt */ - dev->irq = 11; - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - } - - if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND, - PCI_DEVICE_ID_WINBOND_83C553, dev))) { - /* Clear PCI Interrupt Routing Control Register. */ - short_reg = 0x0000; - pci_write_config_word(dev, 0x44, short_reg); - /* Route IDE interrupts to IRQ 14 */ - reg = 0xEE; - pci_write_config_byte(dev, 0x43, reg); - } - - if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND, - PCI_DEVICE_ID_WINBOND_82C105, dev))) { - /* - * Disable LEGIRQ mode so PCI INTS are routed - * directly to the 8259 and enable both channels - */ - pci_write_config_dword(dev, 0x40, 0x10ff0033); - - /* Force correct IDE interrupt */ - dev->irq = 14; - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - } - pci_dev_put(dev); -} - -void __init pplus_set_VIA_IDE_legacy(void) -{ - unsigned short vend, dev; - - early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend); - early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev); - - if ((vend == PCI_VENDOR_ID_VIA) && - (dev == PCI_DEVICE_ID_VIA_82C586_1)) { - unsigned char temp; - - /* put back original "standard" port base addresses */ - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_0, 0x1f1); - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_1, 0x3f5); - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_2, 0x171); - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_3, 0x375); - early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1), - PCI_BASE_ADDRESS_4, 0xcc01); - - /* put into legacy mode */ - early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, - &temp); - temp &= ~0x05; - early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, - temp); - } -} - -void pplus_set_VIA_IDE_native(void) -{ - unsigned short vend, dev; - - early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend); - early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev); - - if ((vend == PCI_VENDOR_ID_VIA) && - (dev == PCI_DEVICE_ID_VIA_82C586_1)) { - unsigned char temp; - - /* put into native mode */ - early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, - &temp); - temp |= 0x05; - early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG, - temp); - } -} - -void __init pplus_pcibios_fixup(void) -{ - - unsigned char reg; - unsigned short devid; - unsigned char base_mod; - - printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n", - Motherboard_map_name); - - /* Setup the Winbond or Via PIB */ - pplus_pib_init(); - - /* Set up floppy in PS/2 mode */ - outb(0x09, SIO_CONFIG_RA); - reg = inb(SIO_CONFIG_RD); - reg = (reg & 0x3F) | 0x40; - outb(reg, SIO_CONFIG_RD); - outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */ - - /* This is a hack. If this is a 2300 or 2400 mot board then there is - * no keyboard controller and we have to indicate that. - */ - - early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid); - base_mod = inb(MOTOROLA_BASETYPE_REG); - if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) || - (base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1)) - prep_keybd_present = 0; -} - -void __init pplus_find_bridges(void) -{ - struct pci_controller *hose; - - hose = pcibios_alloc_controller(); - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - hose->pci_mem_offset = PREP_ISA_MEM_BASE; - hose->io_base_virt = (void *)PREP_ISA_IO_BASE; - - pci_init_resource(&hose->io_resource, PPLUS_PCI_IO_START, - PPLUS_PCI_IO_END, IORESOURCE_IO, "PCI host bridge"); - pci_init_resource(&hose->mem_resources[0], PPLUS_PROC_PCI_MEM_START, - PPLUS_PROC_PCI_MEM_END, IORESOURCE_MEM, - "PCI host bridge"); - - hose->io_space.start = PPLUS_PCI_IO_START; - hose->io_space.end = PPLUS_PCI_IO_END; - hose->mem_space.start = PPLUS_PCI_MEM_START; - hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE; - - if (hawk_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START, - PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE, - PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END, - PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1) - != 0) { - printk(KERN_CRIT "Could not initialize host bridge\n"); - - } - - pplus_set_VIA_IDE_legacy(); - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pcibios_fixup = pplus_pcibios_fixup; - ppc_md.pci_swizzle = common_swizzle; -} - -static int pplus_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: Motorola MCG\n"); - seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name); - - return 0; -} - -static void __init pplus_setup_arch(void) -{ - struct pci_controller *hose; - - if (ppc_md.progress) - ppc_md.progress("pplus_setup_arch: enter", 0); - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000; - - if (ppc_md.progress) - ppc_md.progress("pplus_setup_arch: find_bridges", 0); - - /* Setup PCI host bridge */ - pplus_find_bridges(); - - hose = pci_bus_to_hose(0); - isa_io_base = (ulong) hose->io_base_virt; - - if (ppc_md.progress) - ppc_md.progress("pplus_setup_arch: set_board_type", 0); - - pplus_set_board_type(); - - /* Enable L2. Assume we don't need to flush -- Cort */ - *(unsigned char *)(PPLUS_L2_CONTROL_REG) |= 3; - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - printk(KERN_INFO "Motorola PowerPlus Platform\n"); - printk(KERN_INFO - "Port by MontaVista Software, Inc. (source@mvista.com)\n"); - -#ifdef CONFIG_VGA_CONSOLE - /* remap the VGA memory */ - vgacon_remap_base = (unsigned long)ioremap(PPLUS_ISA_MEM_BASE, - 0x08000000); - conswitchp = &vga_con; -#endif -#ifdef CONFIG_PPCBUG_NVRAM - /* Read in NVRAM data */ - init_prep_nvram(); - - /* if no bootargs, look in NVRAM */ - if (cmd_line[0] == '\0') { - char *bootargs; - bootargs = prep_nvram_get_var("bootargs"); - if (bootargs != NULL) { - strcpy(cmd_line, bootargs); - /* again.. */ - strcpy(boot_command_line, cmd_line); - } - } -#endif - if (ppc_md.progress) - ppc_md.progress("pplus_setup_arch: exit", 0); -} - -static void pplus_restart(char *cmd) -{ - unsigned long i = 10000; - - local_irq_disable(); - - /* set VIA IDE controller into native mode */ - pplus_set_VIA_IDE_native(); - - /* set exception prefix high - to the prom */ - _nmask_and_or_msr(0, MSR_IP); - - /* make sure bit 0 (reset) is a 0 */ - outb(inb(0x92) & ~1L, 0x92); - /* signal a reset to system control port A - soft reset */ - outb(inb(0x92) | 1, 0x92); - - while (i != 0) - i++; - panic("restart failed\n"); -} - -static void pplus_halt(void) -{ - /* set exception prefix high - to the prom */ - _nmask_and_or_msr(MSR_EE, MSR_IP); - - /* make sure bit 0 (reset) is a 0 */ - outb(inb(0x92) & ~1L, 0x92); - /* signal a reset to system control port A - soft reset */ - outb(inb(0x92) | 1, 0x92); - - while (1) ; - /* - * Not reached - */ -} - -static void pplus_power_off(void) -{ - pplus_halt(); -} - -static void __init pplus_init_IRQ(void) -{ - int i; - - if (ppc_md.progress) - ppc_md.progress("init_irq: enter", 0); - - OpenPIC_InitSenses = pplus_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses); - - if (OpenPIC_Addr != NULL) { - - openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000); - openpic_init(NUM_8259_INTERRUPTS); - openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", - i8259_irq); - ppc_md.get_irq = openpic_get_irq; - } - - i8259_init(0, 0); - - if (ppc_md.progress) - ppc_md.progress("init_irq: exit", 0); -} - -#ifdef CONFIG_SMP -/* PowerPlus (MTX) support */ -static int __init smp_pplus_probe(void) -{ - extern int mot_multi; - - if (mot_multi) { - openpic_request_IPIs(); - smp_hw_index[1] = 1; - return 2; - } - - return 1; -} - -static void __init smp_pplus_kick_cpu(int nr) -{ - *(unsigned long *)KERNELBASE = nr; - asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory"); - printk(KERN_INFO "CPU1 reset, waiting\n"); -} - -static void __init smp_pplus_setup_cpu(int cpu_nr) -{ - if (OpenPIC_Addr) - do_openpic_setup_cpu(); -} - -static struct smp_ops_t pplus_smp_ops = { - smp_openpic_message_pass, - smp_pplus_probe, - smp_pplus_kick_cpu, - smp_pplus_setup_cpu, - .give_timebase = smp_generic_give_timebase, - .take_timebase = smp_generic_take_timebase, -}; -#endif /* CONFIG_SMP */ - -#ifdef DUMP_DBATS -static void print_dbat(int idx, u32 bat) -{ - - char str[64]; - - sprintf(str, "DBAT%c%c = 0x%08x\n", - (char)((idx - DBAT0U) / 2) + '0', (idx & 1) ? 'L' : 'U', bat); - ppc_md.progress(str, 0); -} - -#define DUMP_DBAT(x) \ - do { \ - u32 __temp = mfspr(x);\ - print_dbat(x, __temp); \ - } while (0) - -static void dump_dbats(void) -{ - if (ppc_md.progress) { - DUMP_DBAT(DBAT0U); - DUMP_DBAT(DBAT0L); - DUMP_DBAT(DBAT1U); - DUMP_DBAT(DBAT1L); - DUMP_DBAT(DBAT2U); - DUMP_DBAT(DBAT2L); - DUMP_DBAT(DBAT3U); - DUMP_DBAT(DBAT3L); - } -} -#endif - -static unsigned long __init pplus_find_end_of_memory(void) -{ - unsigned long total; - - if (ppc_md.progress) - ppc_md.progress("pplus_find_end_of_memory", 0); - -#ifdef DUMP_DBATS - dump_dbats(); -#endif - - total = hawk_get_mem_size(PPLUS_HAWK_SMC_BASE); - return (total); -} - -static void __init pplus_map_io(void) -{ - io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000, - _PAGE_IO); - io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO); -} - -static void __init pplus_init2(void) -{ -#ifdef CONFIG_NVRAM - request_region(PREP_NVRAM_AS0, 0x8, "nvram"); -#endif - request_region(0x20, 0x20, "pic1"); - request_region(0xa0, 0x20, "pic2"); - request_region(0x00, 0x20, "dma1"); - request_region(0x40, 0x20, "timer"); - request_region(0x80, 0x10, "dma page reg"); - request_region(0xc0, 0x20, "dma2"); -} - -/* - * Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3 - * to 0xf0000000 to access Falcon/Raven or Hawk registers - */ -static __inline__ void pplus_set_bat(void) -{ - /* wait for all outstanding memory accesses to complete */ - mb(); - - /* setup DBATs */ - mtspr(SPRN_DBAT2U, 0x80001ffe); - mtspr(SPRN_DBAT2L, 0x8000002a); - mtspr(SPRN_DBAT3U, 0xf0001ffe); - mtspr(SPRN_DBAT3L, 0xf000002a); - - /* wait for updates */ - mb(); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* Map in board regs, etc. */ - pplus_set_bat(); - - isa_io_base = PREP_ISA_IO_BASE; - isa_mem_base = PREP_ISA_MEM_BASE; - pci_dram_offset = PREP_PCI_DRAM_OFFSET; - ISA_DMA_THRESHOLD = 0x00ffffff; - DMA_MODE_READ = 0x44; - DMA_MODE_WRITE = 0x48; - ppc_do_canonicalize_irqs = 1; - - ppc_md.setup_arch = pplus_setup_arch; - ppc_md.show_cpuinfo = pplus_show_cpuinfo; - ppc_md.init_IRQ = pplus_init_IRQ; - /* this gets changed later on if we have an OpenPIC -- Cort */ - ppc_md.get_irq = i8259_irq; - ppc_md.init = pplus_init2; - - ppc_md.restart = pplus_restart; - ppc_md.power_off = pplus_power_off; - ppc_md.halt = pplus_halt; - - TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1, - PREP_NVRAM_DATA, 8); - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.calibrate_decr = todc_calibrate_decr; - ppc_md.nvram_read_val = todc_m48txx_read_val; - ppc_md.nvram_write_val = todc_m48txx_write_val; - - ppc_md.find_end_of_memory = pplus_find_end_of_memory; - ppc_md.setup_io_mappings = pplus_map_io; - -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ -#ifdef CONFIG_KGDB - ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; -#endif -#ifdef CONFIG_SMP - smp_ops = &pplus_smp_ops; -#endif /* CONFIG_SMP */ -} diff --git a/arch/ppc/platforms/pplus.h b/arch/ppc/platforms/pplus.h deleted file mode 100644 index a4bbaa8d858f..000000000000 --- a/arch/ppc/platforms/pplus.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. - * - * Author: Mark A. Greerinclude/asm-ppc/hawk.h - * mgreer@mvista.com - * - * Modified by Randy Vinson (rvinson@mvista.com) - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __PPC_PPLUS_H -#define __PPC_PPLUS_H - -#include - -/* - * Due to limitations imposed by legacy hardware (primarily IDE controllers), - * the PPLUS boards operate using a PReP address map. - * - * From Processor (physical) -> PCI: - * PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB) - * PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB) - * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area - * - * From PCI -> Processor (physical): - * System Memory: 0x80000000 -> 0x00000000 - */ - -#define PPLUS_ISA_MEM_BASE PREP_ISA_MEM_BASE -#define PPLUS_ISA_IO_BASE PREP_ISA_IO_BASE - -/* PCI Memory space mapping info */ -#define PPLUS_PCI_MEM_SIZE 0x30000000U -#define PPLUS_PROC_PCI_MEM_START PPLUS_ISA_MEM_BASE -#define PPLUS_PROC_PCI_MEM_END (PPLUS_PROC_PCI_MEM_START + \ - PPLUS_PCI_MEM_SIZE - 1) -#define PPLUS_PCI_MEM_START 0x00000000U -#define PPLUS_PCI_MEM_END (PPLUS_PCI_MEM_START + \ - PPLUS_PCI_MEM_SIZE - 1) - -/* PCI I/O space mapping info */ -#define PPLUS_PCI_IO_SIZE 0x10000000U -#define PPLUS_PROC_PCI_IO_START PPLUS_ISA_IO_BASE -#define PPLUS_PROC_PCI_IO_END (PPLUS_PROC_PCI_IO_START + \ - PPLUS_PCI_IO_SIZE - 1) -#define PPLUS_PCI_IO_START 0x00000000U -#define PPLUS_PCI_IO_END (PPLUS_PCI_IO_START + \ - PPLUS_PCI_IO_SIZE - 1) -/* System memory mapping info */ -#define PPLUS_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET -#define PPLUS_PCI_PHY_MEM_OFFSET (PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START) - -/* Define base addresses for important sets of registers */ -#define PPLUS_HAWK_SMC_BASE 0xfef80000U -#define PPLUS_HAWK_PPC_REG_BASE 0xfeff0000U -#define PPLUS_SYS_CONFIG_REG 0xfef80400U -#define PPLUS_L2_CONTROL_REG 0x8000081cU - -#define PPLUS_VGA_MEM_BASE 0xf0000000U - -#endif /* __PPC_PPLUS_H */ diff --git a/arch/ppc/platforms/prep_pci.c b/arch/ppc/platforms/prep_pci.c deleted file mode 100644 index 8ed433e2a5c7..000000000000 --- a/arch/ppc/platforms/prep_pci.c +++ /dev/null @@ -1,1339 +0,0 @@ -/* - * PReP pci functions. - * Originally by Gary Thomas - * rewritten and updated by Cort Dougan (cort@cs.nmt.edu) - * - * The motherboard routes/maps will disappear shortly. -- Cort - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void (*setup_ibm_pci)(char *irq_lo, char *irq_hi); - -/* Which PCI interrupt line does a given device [slot] use? */ -/* Note: This really should be two dimensional based in slot/pin used */ -static unsigned char *Motherboard_map; -unsigned char *Motherboard_map_name; - -/* How is the 82378 PIRQ mapping setup? */ -static unsigned char *Motherboard_routes; - -static void (*Motherboard_non0)(struct pci_dev *); - -static void Powerplus_Map_Non0(struct pci_dev *); - -/* Used for Motorola to store system config register */ -static unsigned long *ProcInfo; - -/* Tables for known hardware */ - -/* Motorola PowerStackII - Utah */ -static char Utah_pci_IRQ_map[23] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 5, /* Slot 2 - SCSI - NCR825A */ - 0, /* Slot 3 - unused */ - 3, /* Slot 4 - Ethernet - DEC2114x */ - 0, /* Slot 5 - unused */ - 2, /* Slot 6 - PCI Card slot #1 */ - 3, /* Slot 7 - PCI Card slot #2 */ - 5, /* Slot 8 - PCI Card slot #3 */ - 5, /* Slot 9 - PCI Bridge */ - /* added here in case we ever support PCI bridges */ - /* Secondary PCI bus cards are at slot-9,6 & slot-9,7 */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 5, /* Slot 12 - SCSI - NCR825A */ - 0, /* Slot 13 - unused */ - 3, /* Slot 14 - enet */ - 0, /* Slot 15 - unused */ - 2, /* Slot 16 - unused */ - 3, /* Slot 17 - unused */ - 5, /* Slot 18 - unused */ - 0, /* Slot 19 - unused */ - 0, /* Slot 20 - unused */ - 0, /* Slot 21 - unused */ - 0, /* Slot 22 - unused */ -}; - -static char Utah_pci_IRQ_routes[] = -{ - 0, /* Line 0 - Unused */ - 9, /* Line 1 */ - 10, /* Line 2 */ - 11, /* Line 3 */ - 14, /* Line 4 */ - 15, /* Line 5 */ -}; - -/* Motorola PowerStackII - Omaha */ -/* no integrated SCSI or ethernet */ -static char Omaha_pci_IRQ_map[23] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 3, /* Slot 2 - Winbond EIDE */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 1, /* Slot 6 - PCI slot 1 */ - 2, /* Slot 7 - PCI slot 2 */ - 3, /* Slot 8 - PCI slot 3 */ - 4, /* Slot 9 - PCI slot 4 */ /* needs indirect access */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 0, /* Slot 12 - unused */ - 0, /* Slot 13 - unused */ - 0, /* Slot 14 - unused */ - 0, /* Slot 15 - unused */ - 1, /* Slot 16 - PCI slot 1 */ - 2, /* Slot 17 - PCI slot 2 */ - 3, /* Slot 18 - PCI slot 3 */ - 4, /* Slot 19 - PCI slot 4 */ /* needs indirect access */ - 0, - 0, - 0, -}; - -static char Omaha_pci_IRQ_routes[] = -{ - 0, /* Line 0 - Unused */ - 9, /* Line 1 */ - 11, /* Line 2 */ - 14, /* Line 3 */ - 15 /* Line 4 */ -}; - -/* Motorola PowerStack */ -static char Blackhawk_pci_IRQ_map[19] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 3, /* Slot 12 - SCSI */ - 0, /* Slot 13 - unused */ - 1, /* Slot 14 - Ethernet */ - 0, /* Slot 15 - unused */ - 1, /* Slot P7 */ - 2, /* Slot P6 */ - 3, /* Slot P5 */ -}; - -static char Blackhawk_pci_IRQ_routes[] = -{ - 0, /* Line 0 - Unused */ - 9, /* Line 1 */ - 11, /* Line 2 */ - 15, /* Line 3 */ - 15 /* Line 4 */ -}; - -/* Motorola Mesquite */ -static char Mesquite_pci_IRQ_map[23] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 0, /* Slot 12 - unused */ - 0, /* Slot 13 - unused */ - 2, /* Slot 14 - Ethernet */ - 0, /* Slot 15 - unused */ - 3, /* Slot 16 - PMC */ - 0, /* Slot 17 - unused */ - 0, /* Slot 18 - unused */ - 0, /* Slot 19 - unused */ - 0, /* Slot 20 - unused */ - 0, /* Slot 21 - unused */ - 0, /* Slot 22 - unused */ -}; - -/* Motorola Sitka */ -static char Sitka_pci_IRQ_map[21] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 0, /* Slot 12 - unused */ - 0, /* Slot 13 - unused */ - 2, /* Slot 14 - Ethernet */ - 0, /* Slot 15 - unused */ - 9, /* Slot 16 - PMC 1 */ - 12, /* Slot 17 - PMC 2 */ - 0, /* Slot 18 - unused */ - 0, /* Slot 19 - unused */ - 4, /* Slot 20 - NT P2P bridge */ -}; - -/* Motorola MTX */ -static char MTX_pci_IRQ_map[23] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 3, /* Slot 12 - SCSI */ - 0, /* Slot 13 - unused */ - 2, /* Slot 14 - Ethernet */ - 0, /* Slot 15 - unused */ - 9, /* Slot 16 - PCI/PMC slot 1 */ - 10, /* Slot 17 - PCI/PMC slot 2 */ - 11, /* Slot 18 - PCI slot 3 */ - 0, /* Slot 19 - unused */ - 0, /* Slot 20 - unused */ - 0, /* Slot 21 - unused */ - 0, /* Slot 22 - unused */ -}; - -/* Motorola MTX Plus */ -/* Secondary bus interrupt routing is not supported yet */ -static char MTXplus_pci_IRQ_map[23] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 3, /* Slot 12 - SCSI */ - 0, /* Slot 13 - unused */ - 2, /* Slot 14 - Ethernet 1 */ - 0, /* Slot 15 - unused */ - 9, /* Slot 16 - PCI slot 1P */ - 10, /* Slot 17 - PCI slot 2P */ - 11, /* Slot 18 - PCI slot 3P */ - 10, /* Slot 19 - Ethernet 2 */ - 0, /* Slot 20 - P2P Bridge */ - 0, /* Slot 21 - unused */ - 0, /* Slot 22 - unused */ -}; - -static char Raven_pci_IRQ_routes[] = -{ - 0, /* This is a dummy structure */ -}; - -/* Motorola MVME16xx */ -static char Genesis_pci_IRQ_map[16] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 3, /* Slot 12 - SCSI */ - 0, /* Slot 13 - unused */ - 1, /* Slot 14 - Ethernet */ - 0, /* Slot 15 - unused */ -}; - -static char Genesis_pci_IRQ_routes[] = -{ - 0, /* Line 0 - Unused */ - 10, /* Line 1 */ - 11, /* Line 2 */ - 14, /* Line 3 */ - 15 /* Line 4 */ -}; - -static char Genesis2_pci_IRQ_map[23] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - IDE */ - 3, /* Slot 12 - SCSI */ - 5, /* Slot 13 - Universe PCI - VME Bridge */ - 2, /* Slot 14 - Ethernet */ - 0, /* Slot 15 - unused */ - 9, /* Slot 16 - PMC 1 */ - 12, /* Slot 17 - pci */ - 11, /* Slot 18 - pci */ - 10, /* Slot 19 - pci */ - 0, /* Slot 20 - pci */ - 0, /* Slot 21 - unused */ - 0, /* Slot 22 - unused */ -}; - -/* Motorola Series-E */ -static char Comet_pci_IRQ_map[23] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 3, /* Slot 12 - SCSI */ - 0, /* Slot 13 - unused */ - 1, /* Slot 14 - Ethernet */ - 0, /* Slot 15 - unused */ - 1, /* Slot 16 - PCI slot 1 */ - 2, /* Slot 17 - PCI slot 2 */ - 3, /* Slot 18 - PCI slot 3 */ - 4, /* Slot 19 - PCI bridge */ - 0, - 0, - 0, -}; - -static char Comet_pci_IRQ_routes[] = -{ - 0, /* Line 0 - Unused */ - 10, /* Line 1 */ - 11, /* Line 2 */ - 14, /* Line 3 */ - 15 /* Line 4 */ -}; - -/* Motorola Series-EX */ -static char Comet2_pci_IRQ_map[23] = -{ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 3, /* Slot 2 - SCSI - NCR825A */ - 0, /* Slot 3 - unused */ - 1, /* Slot 4 - Ethernet - DEC2104X */ - 0, /* Slot 5 - unused */ - 1, /* Slot 6 - PCI slot 1 */ - 2, /* Slot 7 - PCI slot 2 */ - 3, /* Slot 8 - PCI slot 3 */ - 4, /* Slot 9 - PCI bridge */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 3, /* Slot 12 - SCSI - NCR825A */ - 0, /* Slot 13 - unused */ - 1, /* Slot 14 - Ethernet - DEC2104X */ - 0, /* Slot 15 - unused */ - 1, /* Slot 16 - PCI slot 1 */ - 2, /* Slot 17 - PCI slot 2 */ - 3, /* Slot 18 - PCI slot 3 */ - 4, /* Slot 19 - PCI bridge */ - 0, - 0, - 0, -}; - -static char Comet2_pci_IRQ_routes[] = -{ - 0, /* Line 0 - Unused */ - 10, /* Line 1 */ - 11, /* Line 2 */ - 14, /* Line 3 */ - 15, /* Line 4 */ -}; - -/* - * ibm 830 (and 850?). - * This is actually based on the Carolina motherboard - * -- Cort - */ -static char ibm8xx_pci_IRQ_map[23] = { - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - FireCoral */ - 4, /* Slot 12 - Ethernet PCIINTD# */ - 2, /* Slot 13 - PCI Slot #2 */ - 2, /* Slot 14 - S3 Video PCIINTD# */ - 0, /* Slot 15 - onboard SCSI (INDI) [1] */ - 3, /* Slot 16 - NCR58C810 RS6000 Only PCIINTC# */ - 0, /* Slot 17 - unused */ - 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */ - 0, /* Slot 19 - unused */ - 0, /* Slot 20 - unused */ - 0, /* Slot 21 - unused */ - 2, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */ -}; - -static char ibm8xx_pci_IRQ_routes[] = { - 0, /* Line 0 - unused */ - 15, /* Line 1 */ - 15, /* Line 2 */ - 15, /* Line 3 */ - 15, /* Line 4 */ -}; - -/* - * a 6015 ibm board - * -- Cort - */ -static char ibm6015_pci_IRQ_map[23] = { - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - */ - 1, /* Slot 12 - SCSI */ - 2, /* Slot 13 - */ - 2, /* Slot 14 - */ - 1, /* Slot 15 - */ - 1, /* Slot 16 - */ - 0, /* Slot 17 - */ - 2, /* Slot 18 - */ - 0, /* Slot 19 - */ - 0, /* Slot 20 - */ - 0, /* Slot 21 - */ - 2, /* Slot 22 - */ -}; - -static char ibm6015_pci_IRQ_routes[] = { - 0, /* Line 0 - unused */ - 13, /* Line 1 */ - 15, /* Line 2 */ - 15, /* Line 3 */ - 15, /* Line 4 */ -}; - - -/* IBM Nobis and Thinkpad 850 */ -static char Nobis_pci_IRQ_map[23] ={ - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - unused */ - 3, /* Slot 12 - SCSI */ - 0, /* Slot 13 - unused */ - 0, /* Slot 14 - unused */ - 0, /* Slot 15 - unused */ -}; - -static char Nobis_pci_IRQ_routes[] = { - 0, /* Line 0 - Unused */ - 13, /* Line 1 */ - 13, /* Line 2 */ - 13, /* Line 3 */ - 13 /* Line 4 */ -}; - -/* - * IBM RS/6000 43p/140 -- paulus - * XXX we should get all this from the residual data - */ -static char ibm43p_pci_IRQ_map[23] = { - 0, /* Slot 0 - unused */ - 0, /* Slot 1 - unused */ - 0, /* Slot 2 - unused */ - 0, /* Slot 3 - unused */ - 0, /* Slot 4 - unused */ - 0, /* Slot 5 - unused */ - 0, /* Slot 6 - unused */ - 0, /* Slot 7 - unused */ - 0, /* Slot 8 - unused */ - 0, /* Slot 9 - unused */ - 0, /* Slot 10 - unused */ - 0, /* Slot 11 - FireCoral ISA bridge */ - 6, /* Slot 12 - Ethernet */ - 0, /* Slot 13 - openpic */ - 0, /* Slot 14 - unused */ - 0, /* Slot 15 - unused */ - 7, /* Slot 16 - NCR58C825a onboard scsi */ - 0, /* Slot 17 - unused */ - 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */ - 0, /* Slot 19 - unused */ - 0, /* Slot 20 - unused */ - 0, /* Slot 21 - unused */ - 1, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */ -}; - -static char ibm43p_pci_IRQ_routes[] = { - 0, /* Line 0 - unused */ - 15, /* Line 1 */ - 15, /* Line 2 */ - 15, /* Line 3 */ - 15, /* Line 4 */ -}; - -/* Motorola PowerPlus architecture PCI IRQ tables */ -/* Interrupt line values for INTA-D on primary/secondary MPIC inputs */ - -struct powerplus_irq_list -{ - unsigned char primary[4]; /* INT A-D */ - unsigned char secondary[4]; /* INT A-D */ -}; - -/* - * For standard PowerPlus boards, bus 0 PCI INTs A-D are routed to - * OpenPIC inputs 9-12. PCI INTs A-D from the on board P2P bridge - * are routed to OpenPIC inputs 5-8. These values are offset by - * 16 in the table to reflect the Linux kernel interrupt value. - */ -struct powerplus_irq_list Powerplus_pci_IRQ_list = -{ - {25, 26, 27, 28}, - {21, 22, 23, 24} -}; - -/* - * For the MCP750 (system slot board), cPCI INTs A-D are routed to - * OpenPIC inputs 8-11 and the PMC INTs A-D are routed to OpenPIC - * input 3. On a hot swap MCP750, the companion card PCI INTs A-D - * are routed to OpenPIC inputs 12-15. These values are offset by - * 16 in the table to reflect the Linux kernel interrupt value. - */ -struct powerplus_irq_list Mesquite_pci_IRQ_list = -{ - {24, 25, 26, 27}, - {28, 29, 30, 31} -}; - -/* - * This table represents the standard PCI swizzle defined in the - * PCI bus specification. - */ -static unsigned char prep_pci_intpins[4][4] = -{ - { 1, 2, 3, 4}, /* Buses 0, 4, 8, ... */ - { 2, 3, 4, 1}, /* Buses 1, 5, 9, ... */ - { 3, 4, 1, 2}, /* Buses 2, 6, 10 ... */ - { 4, 1, 2, 3}, /* Buses 3, 7, 11 ... */ -}; - -/* We have to turn on LEVEL mode for changed IRQs */ -/* All PCI IRQs need to be level mode, so this should be something - * other than hard-coded as well... IRQs are individually mappable - * to either edge or level. - */ - -/* - * 8259 edge/level control definitions - */ -#define ISA8259_M_ELCR 0x4d0 -#define ISA8259_S_ELCR 0x4d1 - -#define ELCRS_INT15_LVL 0x80 -#define ELCRS_INT14_LVL 0x40 -#define ELCRS_INT12_LVL 0x10 -#define ELCRS_INT11_LVL 0x08 -#define ELCRS_INT10_LVL 0x04 -#define ELCRS_INT9_LVL 0x02 -#define ELCRS_INT8_LVL 0x01 -#define ELCRM_INT7_LVL 0x80 -#define ELCRM_INT5_LVL 0x20 - -#if 0 -/* - * PCI config space access. - */ -#define CFGADDR(dev) ((1<<(dev>>3)) | ((dev&7)<<8)) -#define DEVNO(dev) (dev>>3) - -#define MIN_DEVNR 11 -#define MAX_DEVNR 22 - -static int -prep_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) -{ - struct pci_controller *hose = bus->sysdata; - volatile void __iomem *cfg_data; - - if (bus->number != 0 || DEVNO(devfn) < MIN_DEVNR - || DEVNO(devfn) > MAX_DEVNR) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - cfg_data = hose->cfg_data + CFGADDR(devfn) + offset; - switch (len) { - case 1: - *val = in_8(cfg_data); - break; - case 2: - *val = in_le16(cfg_data); - break; - default: - *val = in_le32(cfg_data); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static int -prep_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) -{ - struct pci_controller *hose = bus->sysdata; - volatile void __iomem *cfg_data; - - if (bus->number != 0 || DEVNO(devfn) < MIN_DEVNR - || DEVNO(devfn) > MAX_DEVNR) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - cfg_data = hose->cfg_data + CFGADDR(devfn) + offset; - switch (len) { - case 1: - out_8(cfg_data, val); - break; - case 2: - out_le16(cfg_data, val); - break; - default: - out_le32(cfg_data, val); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops prep_pci_ops = -{ - prep_read_config, - prep_write_config -}; -#endif - -#define MOTOROLA_CPUTYPE_REG 0x800 -#define MOTOROLA_BASETYPE_REG 0x803 -#define MPIC_RAVEN_ID 0x48010000 -#define MPIC_HAWK_ID 0x48030000 -#define MOT_PROC2_BIT 0x800 - -static u_char prep_openpic_initsenses[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */ - (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_FALCN_ECC_ERR */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_ETHERNET */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_GRAPHICS */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */ -}; - -#define MOT_RAVEN_PRESENT 0x1 -#define MOT_HAWK_PRESENT 0x2 - -int mot_entry = -1; -int prep_keybd_present = 1; -int MotMPIC; -int mot_multi; - -int __init -raven_init(void) -{ - unsigned int devid; - unsigned int pci_membase; - unsigned char base_mod; - - /* Check to see if the Raven chip exists. */ - if ( _prep_type != _PREP_Motorola) { - OpenPIC_Addr = NULL; - return 0; - } - - /* Check to see if this board is a type that might have a Raven. */ - if ((inb(MOTOROLA_CPUTYPE_REG) & 0xF0) != 0xE0) { - OpenPIC_Addr = NULL; - return 0; - } - - /* Check the first PCI device to see if it is a Raven. */ - early_read_config_dword(NULL, 0, 0, PCI_VENDOR_ID, &devid); - - switch (devid & 0xffff0000) { - case MPIC_RAVEN_ID: - MotMPIC = MOT_RAVEN_PRESENT; - break; - case MPIC_HAWK_ID: - MotMPIC = MOT_HAWK_PRESENT; - break; - default: - OpenPIC_Addr = NULL; - return 0; - } - - - /* Read the memory base register. */ - early_read_config_dword(NULL, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase); - - if (pci_membase == 0) { - OpenPIC_Addr = NULL; - return 0; - } - - /* Map the Raven MPIC registers to virtual memory. */ - OpenPIC_Addr = ioremap(pci_membase+0xC0000000, 0x22000); - - OpenPIC_InitSenses = prep_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses); - - ppc_md.get_irq = openpic_get_irq; - - /* If raven is present on Motorola store the system config register - * for later use. - */ - ProcInfo = (unsigned long *)ioremap(0xfef80400, 4); - - /* Indicate to system if this is a multiprocessor board */ - if (!(*ProcInfo & MOT_PROC2_BIT)) { - mot_multi = 1; - } - - /* This is a hack. If this is a 2300 or 2400 mot board then there is - * no keyboard controller and we have to indicate that. - */ - base_mod = inb(MOTOROLA_BASETYPE_REG); - if ((MotMPIC == MOT_HAWK_PRESENT) || (base_mod == 0xF9) || - (base_mod == 0xFA) || (base_mod == 0xE1)) - prep_keybd_present = 0; - - return 1; -} - -struct mot_info { - int cpu_type; /* 0x100 mask assumes for Raven and Hawk boards that the level/edge are set */ - /* 0x200 if this board has a Hawk chip. */ - int base_type; - int max_cpu; /* ored with 0x80 if this board should be checked for multi CPU */ - const char *name; - unsigned char *map; - unsigned char *routes; - void (*map_non0_bus)(struct pci_dev *); /* For boards with more than bus 0 devices. */ - struct powerplus_irq_list *pci_irq_list; /* List of PCI MPIC inputs */ - unsigned char secondary_bridge_devfn; /* devfn of secondary bus transparent bridge */ -} mot_info[] = { - {0x300, 0x00, 0x00, "MVME 2400", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x010, 0x00, 0x00, "Genesis", Genesis_pci_IRQ_map, Genesis_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, - {0x020, 0x00, 0x00, "Powerstack (Series E)", Comet_pci_IRQ_map, Comet_pci_IRQ_routes, NULL, NULL, 0x00}, - {0x040, 0x00, 0x00, "Blackhawk (Powerstack)", Blackhawk_pci_IRQ_map, Blackhawk_pci_IRQ_routes, NULL, NULL, 0x00}, - {0x050, 0x00, 0x00, "Omaha (PowerStack II Pro3000)", Omaha_pci_IRQ_map, Omaha_pci_IRQ_routes, NULL, NULL, 0x00}, - {0x060, 0x00, 0x00, "Utah (Powerstack II Pro4000)", Utah_pci_IRQ_map, Utah_pci_IRQ_routes, NULL, NULL, 0x00}, - {0x0A0, 0x00, 0x00, "Powerstack (Series EX)", Comet2_pci_IRQ_map, Comet2_pci_IRQ_routes, NULL, NULL, 0x00}, - {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xFF}, - {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", Sitka_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xC0}, - {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0}, - {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0}, - {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, - {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, - {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, - {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, - {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, - {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x1E0, 0xFF, 0x00, "MVME 1600-001 or 1600-011", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, - {0x000, 0x00, 0x00, "", NULL, NULL, NULL, NULL, 0x00} -}; - -void __init -ibm_prep_init(void) -{ - if (have_residual_data) { - u32 addr, real_addr, len, offset; - PPC_DEVICE *mpic; - PnP_TAG_PACKET *pkt; - - /* Use the PReP residual data to determine if an OpenPIC is - * present. If so, get the large vendor packet which will - * tell us the base address and length in memory. - * If we are successful, ioremap the memory area and set - * OpenPIC_Addr (this indicates that the OpenPIC was found). - */ - mpic = residual_find_device(-1, NULL, SystemPeripheral, - ProgrammableInterruptController, MPIC, 0); - if (!mpic) - return; - - pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap + - mpic->AllocatedOffset, 9, 0); - - if (!pkt) - return; - -#define p pkt->L4_Pack.L4_Data.L4_PPCPack - if (p.PPCData[1] == 32) { - switch (p.PPCData[0]) { - case 1: offset = PREP_ISA_IO_BASE; break; - case 2: offset = PREP_ISA_MEM_BASE; break; - default: return; /* Not I/O or memory?? */ - } - } - else - return; /* Not a 32-bit address */ - - real_addr = ld_le32((unsigned int *) (p.PPCData + 4)); - if (real_addr == 0xffffffff) - return; - - /* Adjust address to be as seen by CPU */ - addr = real_addr + offset; - - len = ld_le32((unsigned int *) (p.PPCData + 12)); - if (!len) - return; -#undef p - OpenPIC_Addr = ioremap(addr, len); - ppc_md.get_irq = openpic_get_irq; - - OpenPIC_InitSenses = prep_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses); - - printk(KERN_INFO "MPIC at 0x%08x (0x%08x), length 0x%08x " - "mapped to 0x%p\n", addr, real_addr, len, OpenPIC_Addr); - } -} - -static void __init -ibm43p_pci_map_non0(struct pci_dev *dev) -{ - unsigned char intpin; - static unsigned char bridge_intrs[4] = { 3, 4, 5, 8 }; - - if (dev == NULL) - return; - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin); - if (intpin < 1 || intpin > 4) - return; - intpin = (PCI_SLOT(dev->devfn) + intpin - 1) & 3; - dev->irq = openpic_to_irq(bridge_intrs[intpin]); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); -} - -void __init -prep_residual_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) -{ - if (have_residual_data) { - Motherboard_map_name = res->VitalProductData.PrintableModel; - Motherboard_map = NULL; - Motherboard_routes = NULL; - residual_irq_mask(irq_edge_mask_lo, irq_edge_mask_hi); - } -} - -void __init -prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) -{ - Motherboard_map_name = "IBM 6015/7020 (Sandalfoot/Sandalbow)"; - Motherboard_map = ibm6015_pci_IRQ_map; - Motherboard_routes = ibm6015_pci_IRQ_routes; - *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ - *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */ -} - -void __init -prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) -{ - Motherboard_map_name = "IBM Thinkpad 850/860"; - Motherboard_map = Nobis_pci_IRQ_map; - Motherboard_routes = Nobis_pci_IRQ_routes; - *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ - *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */ -} - -void __init -prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) -{ - Motherboard_map_name = "IBM 7248, PowerSeries 830/850 (Carolina)"; - Motherboard_map = ibm8xx_pci_IRQ_map; - Motherboard_routes = ibm8xx_pci_IRQ_routes; - *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ - *irq_edge_mask_hi = 0xA4; /* IRQs 10, 13, 15 level-triggered */ -} - -void __init -prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) -{ - Motherboard_map_name = "IBM 43P-140 (Tiger1)"; - Motherboard_map = ibm43p_pci_IRQ_map; - Motherboard_routes = ibm43p_pci_IRQ_routes; - Motherboard_non0 = ibm43p_pci_map_non0; - *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ - *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */ -} - -void __init -prep_route_pci_interrupts(void) -{ - unsigned char *ibc_pirq = (unsigned char *)0x80800860; - unsigned char *ibc_pcicon = (unsigned char *)0x80800840; - int i; - - if ( _prep_type == _PREP_Motorola) - { - unsigned short irq_mode; - unsigned char cpu_type; - unsigned char base_mod; - int entry; - - cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0; - base_mod = inb(MOTOROLA_BASETYPE_REG); - - for (entry = 0; mot_info[entry].cpu_type != 0; entry++) { - if (mot_info[entry].cpu_type & 0x200) { /* Check for Hawk chip */ - if (!(MotMPIC & MOT_HAWK_PRESENT)) - continue; - } else { /* Check non hawk boards */ - if ((mot_info[entry].cpu_type & 0xff) != cpu_type) - continue; - - if (mot_info[entry].base_type == 0) { - mot_entry = entry; - break; - } - - if (mot_info[entry].base_type != base_mod) - continue; - } - - if (!(mot_info[entry].max_cpu & 0x80)) { - mot_entry = entry; - break; - } - - /* processor 1 not present and max processor zero indicated */ - if ((*ProcInfo & MOT_PROC2_BIT) && !(mot_info[entry].max_cpu & 0x7f)) { - mot_entry = entry; - break; - } - - /* processor 1 present and max processor zero indicated */ - if (!(*ProcInfo & MOT_PROC2_BIT) && (mot_info[entry].max_cpu & 0x7f)) { - mot_entry = entry; - break; - } - } - - if (mot_entry == -1) /* No particular cpu type found - assume Blackhawk */ - mot_entry = 3; - - Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name; - Motherboard_map = mot_info[mot_entry].map; - Motherboard_routes = mot_info[mot_entry].routes; - Motherboard_non0 = mot_info[mot_entry].map_non0_bus; - - if (!(mot_info[entry].cpu_type & 0x100)) { - /* AJF adjust level/edge control according to routes */ - irq_mode = 0; - for (i = 1; i <= 4; i++) - irq_mode |= ( 1 << Motherboard_routes[i] ); - outb( irq_mode & 0xff, 0x4d0 ); - outb( (irq_mode >> 8) & 0xff, 0x4d1 ); - } - } else if ( _prep_type == _PREP_IBM ) { - unsigned char irq_edge_mask_lo, irq_edge_mask_hi; - unsigned short irq_edge_mask; - int i; - - setup_ibm_pci(&irq_edge_mask_lo, &irq_edge_mask_hi); - - outb(inb(0x04d0)|irq_edge_mask_lo, 0x4d0); /* primary 8259 */ - outb(inb(0x04d1)|irq_edge_mask_hi, 0x4d1); /* cascaded 8259 */ - - irq_edge_mask = (irq_edge_mask_hi << 8) | irq_edge_mask_lo; - for (i = 0; i < 16; ++i, irq_edge_mask >>= 1) - if (irq_edge_mask & 1) - irq_desc[i].status |= IRQ_LEVEL; - } else { - printk("No known machine pci routing!\n"); - return; - } - - /* Set up mapping from slots */ - if (Motherboard_routes) { - for (i = 1; i <= 4; i++) - ibc_pirq[i-1] = Motherboard_routes[i]; - - /* Enable PCI interrupts */ - *ibc_pcicon |= 0x20; - } -} - -void __init -prep_pib_init(void) -{ - unsigned char reg; - unsigned short short_reg; - - struct pci_dev *dev = NULL; - - if (( _prep_type == _PREP_Motorola) && (OpenPIC_Addr)) { - /* - * Perform specific configuration for the Via Tech or - * or Winbond PCI-ISA-Bridge part. - */ - if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C586_1, dev))) { - /* - * PPCBUG does not set the enable bits - * for the IDE device. Force them on here. - */ - pci_read_config_byte(dev, 0x40, ®); - - reg |= 0x03; /* IDE: Chip Enable Bits */ - pci_write_config_byte(dev, 0x40, reg); - } - if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C586_2, - dev)) && (dev->devfn = 0x5a)) { - /* Force correct USB interrupt */ - dev->irq = 11; - pci_write_config_byte(dev, - PCI_INTERRUPT_LINE, - dev->irq); - } - if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND, - PCI_DEVICE_ID_WINBOND_83C553, dev))) { - /* Clear PCI Interrupt Routing Control Register. */ - short_reg = 0x0000; - pci_write_config_word(dev, 0x44, short_reg); - if (OpenPIC_Addr){ - /* Route IDE interrupts to IRQ 14 */ - reg = 0xEE; - pci_write_config_byte(dev, 0x43, reg); - } - } - } - - if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND, - PCI_DEVICE_ID_WINBOND_82C105, dev))){ - if (OpenPIC_Addr){ - /* - * Disable LEGIRQ mode so PCI INTS are routed - * directly to the 8259 and enable both channels - */ - pci_write_config_dword(dev, 0x40, 0x10ff0033); - - /* Force correct IDE interrupt */ - dev->irq = 14; - pci_write_config_byte(dev, - PCI_INTERRUPT_LINE, - dev->irq); - } else { - /* Enable LEGIRQ for PCI INT -> 8259 IRQ routing */ - pci_write_config_dword(dev, 0x40, 0x10ff08a1); - } - } - pci_dev_put(dev); -} - -static void __init -Powerplus_Map_Non0(struct pci_dev *dev) -{ - struct pci_bus *pbus; /* Parent bus structure pointer */ - struct pci_dev *tdev = dev; /* Temporary device structure */ - unsigned int devnum; /* Accumulated device number */ - unsigned char intline; /* Linux interrupt value */ - unsigned char intpin; /* PCI interrupt pin */ - - /* Check for valid PCI dev pointer */ - if (dev == NULL) return; - - /* Initialize bridge IDSEL variable */ - devnum = PCI_SLOT(tdev->devfn); - - /* Read the interrupt pin of the device and adjust for indexing */ - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin); - - /* If device doesn't request an interrupt, return */ - if ( (intpin < 1) || (intpin > 4) ) - return; - - intpin--; - - /* - * Walk up to bus 0, adjusting the interrupt pin for the standard - * PCI bus swizzle. - */ - do { - intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1; - pbus = tdev->bus; /* up one level */ - tdev = pbus->self; - devnum = PCI_SLOT(tdev->devfn); - } while(tdev->bus->number); - - /* Use the primary interrupt inputs by default */ - intline = mot_info[mot_entry].pci_irq_list->primary[intpin]; - - /* - * If the board has secondary interrupt inputs, walk the bus and - * note the devfn of the bridge from bus 0. If it is the same as - * the devfn of the bus bridge with secondary inputs, use those. - * Otherwise, assume it's a PMC site and get the interrupt line - * value from the interrupt routing table. - */ - if (mot_info[mot_entry].secondary_bridge_devfn) { - pbus = dev->bus; - - while (pbus->primary != 0) - pbus = pbus->parent; - - if ((pbus->self)->devfn != 0xA0) { - if ((pbus->self)->devfn == mot_info[mot_entry].secondary_bridge_devfn) - intline = mot_info[mot_entry].pci_irq_list->secondary[intpin]; - else { - if ((char *)(mot_info[mot_entry].map) == (char *)Mesquite_pci_IRQ_map) - intline = mot_info[mot_entry].map[((pbus->self)->devfn)/8] + 16; - else { - int i; - for (i=0;i<3;i++) - intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1; - intline = mot_info[mot_entry].pci_irq_list->primary[intpin]; - } - } - } - } - - /* Write calculated interrupt value to header and device list */ - dev->irq = intline; - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, (u8)dev->irq); -} - -void __init -prep_pcibios_fixup(void) -{ - struct pci_dev *dev = NULL; - int irq; - int have_openpic = (OpenPIC_Addr != NULL); - - prep_route_pci_interrupts(); - - printk("Setting PCI interrupts for a \"%s\"\n", Motherboard_map_name); - - /* Iterate through all the PCI devices, setting the IRQ */ - for_each_pci_dev(dev) { - /* - * If we have residual data, then this is easy: query the - * residual data for the IRQ line allocated to the device. - * This works the same whether we have an OpenPic or not. - */ - if (have_residual_data) { - irq = residual_pcidev_irq(dev); - dev->irq = have_openpic ? openpic_to_irq(irq) : irq; - } - /* - * If we don't have residual data, then we need to use - * tables to determine the IRQ. The table organisation - * is different depending on whether there is an OpenPIC - * or not. The tables are only used for bus 0, so check - * this first. - */ - else if (dev->bus->number == 0) { - irq = Motherboard_map[PCI_SLOT(dev->devfn)]; - dev->irq = have_openpic ? openpic_to_irq(irq) - : Motherboard_routes[irq]; - } - /* - * Finally, if we don't have residual data and the bus is - * non-zero, use the callback (if provided) - */ - else { - if (Motherboard_non0 != NULL) - Motherboard_non0(dev); - - continue; - } - - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - } - - /* Setup the Winbond or Via PIB - prep_pib_init() is coded for - * the non-openpic case, but it breaks (at least) the Utah - * (Powerstack II Pro4000), so only call it if we have an - * openpic. - */ - if (have_openpic) - prep_pib_init(); -} - -static void __init -prep_pcibios_after_init(void) -{ -#if 0 - struct pci_dev *dev; - - /* If there is a WD 90C, reset the IO BAR to 0x0 (it started that - * way, but the PCI layer relocated it because it thought 0x0 was - * invalid for a BAR). - * If you don't do this, the card's VGA base will be +0xc0000 - * instead of 0xc0000. vgacon.c (for example) is completely unaware of - * this little quirk. - */ - dev = pci_get_device(PCI_VENDOR_ID_WD, PCI_DEVICE_ID_WD_90C, NULL); - if (dev) { - dev->resource[1].end -= dev->resource[1].start; - dev->resource[1].start = 0; - /* tell the hardware */ - pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x0); - pci_dev_put(dev); - } -#endif -} - -static void __init -prep_init_resource(struct resource *res, unsigned long start, - unsigned long end, int flags) -{ - res->flags = flags; - res->start = start; - res->end = end; - res->name = "PCI host bridge"; - res->parent = NULL; - res->sibling = NULL; - res->child = NULL; -} - -void __init -prep_find_bridges(void) -{ - struct pci_controller* hose; - - hose = pcibios_alloc_controller(); - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - hose->pci_mem_offset = PREP_ISA_MEM_BASE; - hose->io_base_phys = PREP_ISA_IO_BASE; - hose->io_base_virt = ioremap(PREP_ISA_IO_BASE, 0x800000); - prep_init_resource(&hose->io_resource, 0, 0x007fffff, IORESOURCE_IO); - prep_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfeffffff, - IORESOURCE_MEM); - setup_indirect_pci(hose, PREP_ISA_IO_BASE + 0xcf8, - PREP_ISA_IO_BASE + 0xcfc); - - printk("PReP architecture\n"); - - if (have_residual_data) { - PPC_DEVICE *hostbridge; - - hostbridge = residual_find_device(PROCESSORDEVICE, NULL, - BridgeController, PCIBridge, -1, 0); - if (hostbridge && - ((hostbridge->DeviceId.Interface == PCIBridgeIndirect) || - (hostbridge->DeviceId.Interface == PCIBridgeRS6K))) { - PnP_TAG_PACKET * pkt; - pkt = PnP_find_large_vendor_packet( - res->DevicePnPHeap+hostbridge->AllocatedOffset, - 3, 0); - if(pkt) { -#define p pkt->L4_Pack.L4_Data.L4_PPCPack - setup_indirect_pci(hose, - ld_le32((unsigned *) (p.PPCData)), - ld_le32((unsigned *) (p.PPCData+8))); -#undef p - } else - setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc); - } - } - - ppc_md.pcibios_fixup = prep_pcibios_fixup; - ppc_md.pcibios_after_init = prep_pcibios_after_init; -} diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c deleted file mode 100644 index 465b658c927d..000000000000 --- a/arch/ppc/platforms/prep_setup.c +++ /dev/null @@ -1,1043 +0,0 @@ -/* - * Copyright (C) 1995 Linus Torvalds - * Adapted from 'alpha' version by Gary Thomas - * Modified by Cort Dougan (cort@cs.nmt.edu) - * - * Support for PReP (Motorola MTX/MVME) - * by Troy Benjegerdes (hozer@drgw.net) - */ - -/* - * bootup setup stuff.. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* prep registers for L2 */ -#define CACHECRBA 0x80000823 /* Cache configuration register address */ -#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ -#define L2CACHE_512KB 0x00 /* 512KB */ -#define L2CACHE_256KB 0x01 /* 256KB */ -#define L2CACHE_1MB 0x02 /* 1MB */ -#define L2CACHE_NONE 0x03 /* NONE */ -#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ - -TODC_ALLOC(); - -extern unsigned char prep_nvram_read_val(int addr); -extern void prep_nvram_write_val(int addr, - unsigned char val); -extern unsigned char rs_nvram_read_val(int addr); -extern void rs_nvram_write_val(int addr, - unsigned char val); -extern void ibm_prep_init(void); - -extern void prep_find_bridges(void); - -int _prep_type; - -extern void prep_residual_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi); -extern void prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi); -extern void prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi); -extern void prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi); -extern void prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi); - - -#define cached_21 (((char *)(ppc_cached_irq_mask))[3]) -#define cached_A1 (((char *)(ppc_cached_irq_mask))[2]) - -extern PTE *Hash, *Hash_end; -extern unsigned long Hash_size, Hash_mask; -extern int probingmem; -extern unsigned long loops_per_jiffy; - -/* useful ISA ports */ -#define PREP_SYSCTL 0x81c -/* present in the IBM reference design; possibly identical in Mot boxes: */ -#define PREP_IBM_SIMM_ID 0x803 /* SIMM size: 32 or 8 MiB */ -#define PREP_IBM_SIMM_PRESENCE 0x804 -#define PREP_IBM_EQUIPMENT 0x80c -#define PREP_IBM_L2INFO 0x80d -#define PREP_IBM_PM1 0x82a /* power management register 1 */ -#define PREP_IBM_PLANAR 0x852 /* planar ID - identifies the motherboard */ -#define PREP_IBM_DISP 0x8c0 /* 4-digit LED display */ - -/* Equipment Present Register masks: */ -#define PREP_IBM_EQUIPMENT_RESERVED 0x80 -#define PREP_IBM_EQUIPMENT_SCSIFUSE 0x40 -#define PREP_IBM_EQUIPMENT_L2_COPYBACK 0x08 -#define PREP_IBM_EQUIPMENT_L2_256 0x04 -#define PREP_IBM_EQUIPMENT_CPU 0x02 -#define PREP_IBM_EQUIPMENT_L2 0x01 - -/* planar ID values: */ -/* Sandalfoot/Sandalbow (6015/7020) */ -#define PREP_IBM_SANDALFOOT 0xfc -/* Woodfield, Thinkpad 850/860 (6042/7249) */ -#define PREP_IBM_THINKPAD 0xff /* planar ID unimplemented */ -/* PowerSeries 830/850 (6050/6070) */ -#define PREP_IBM_CAROLINA_IDE_0 0xf0 -#define PREP_IBM_CAROLINA_IDE_1 0xf1 -#define PREP_IBM_CAROLINA_IDE_2 0xf2 -#define PREP_IBM_CAROLINA_IDE_3 0xf3 -/* 7248-43P */ -#define PREP_IBM_CAROLINA_SCSI_0 0xf4 -#define PREP_IBM_CAROLINA_SCSI_1 0xf5 -#define PREP_IBM_CAROLINA_SCSI_2 0xf6 -#define PREP_IBM_CAROLINA_SCSI_3 0xf7 /* missing from Carolina Tech Spec */ -/* Tiger1 (7043-140) */ -#define PREP_IBM_TIGER1_133 0xd1 -#define PREP_IBM_TIGER1_166 0xd2 -#define PREP_IBM_TIGER1_180 0xd3 -#define PREP_IBM_TIGER1_xxx 0xd4 /* unknown, but probably exists */ -#define PREP_IBM_TIGER1_333 0xd5 /* missing from Tiger Tech Spec */ - -/* setup_ibm_pci: - * set Motherboard_map_name, Motherboard_map, Motherboard_routes. - * return 8259 edge/level masks. - */ -void (*setup_ibm_pci)(char *irq_lo, char *irq_hi); - -extern char *Motherboard_map_name; /* for use in *_cpuinfo */ - -/* - * As found in the PReP reference implementation. - * Used by Thinkpad, Sandalfoot (6015/7020), and all Motorola PReP. - */ -static void __init -prep_gen_enable_l2(void) -{ - outb(inb(PREP_SYSCTL) | 0x3, PREP_SYSCTL); -} - -/* Used by Carolina and Tiger1 */ -static void __init -prep_carolina_enable_l2(void) -{ - outb(inb(PREP_SYSCTL) | 0xc0, PREP_SYSCTL); -} - -/* cpuinfo code common to all IBM PReP */ -static void -prep_ibm_cpuinfo(struct seq_file *m) -{ - unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT); - - seq_printf(m, "machine\t\t: PReP %s\n", Motherboard_map_name); - - seq_printf(m, "upgrade cpu\t: "); - if (equip_reg & PREP_IBM_EQUIPMENT_CPU) { - seq_printf(m, "not "); - } - seq_printf(m, "present\n"); - - /* print info about the SCSI fuse */ - seq_printf(m, "scsi fuse\t: "); - if (equip_reg & PREP_IBM_EQUIPMENT_SCSIFUSE) - seq_printf(m, "ok"); - else - seq_printf(m, "bad"); - seq_printf(m, "\n"); - - /* print info about SIMMs */ - if (have_residual_data) { - int i; - seq_printf(m, "simms\t\t: "); - for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) { - if (res->Memories[i].SIMMSize != 0) - seq_printf(m, "%d:%ldMiB ", i, - (res->Memories[i].SIMMSize > 1024) ? - res->Memories[i].SIMMSize>>20 : - res->Memories[i].SIMMSize); - } - seq_printf(m, "\n"); - } -} - -static int -prep_gen_cpuinfo(struct seq_file *m) -{ - prep_ibm_cpuinfo(m); - return 0; -} - -static int -prep_sandalfoot_cpuinfo(struct seq_file *m) -{ - unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT); - - prep_ibm_cpuinfo(m); - - /* report amount and type of L2 cache present */ - seq_printf(m, "L2 cache\t: "); - if (equip_reg & PREP_IBM_EQUIPMENT_L2) { - seq_printf(m, "not present"); - } else { - if (equip_reg & PREP_IBM_EQUIPMENT_L2_256) - seq_printf(m, "256KiB"); - else - seq_printf(m, "unknown size"); - - if (equip_reg & PREP_IBM_EQUIPMENT_L2_COPYBACK) - seq_printf(m, ", copy-back"); - else - seq_printf(m, ", write-through"); - } - seq_printf(m, "\n"); - - return 0; -} - -static int -prep_thinkpad_cpuinfo(struct seq_file *m) -{ - unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT); - char *cpubus_speed, *pci_speed; - - prep_ibm_cpuinfo(m); - - /* report amount and type of L2 cache present */ - seq_printf(m, "l2 cache\t: "); - if ((equip_reg & 0x1) == 0) { - switch ((equip_reg & 0xc) >> 2) { - case 0x0: - seq_printf(m, "128KiB look-aside 2-way write-through\n"); - break; - case 0x1: - seq_printf(m, "512KiB look-aside direct-mapped write-back\n"); - break; - case 0x2: - seq_printf(m, "256KiB look-aside 2-way write-through\n"); - break; - case 0x3: - seq_printf(m, "256KiB look-aside direct-mapped write-back\n"); - break; - } - } else { - seq_printf(m, "not present\n"); - } - - /* report bus speeds because we can */ - if ((equip_reg & 0x80) == 0) { - switch ((equip_reg & 0x30) >> 4) { - case 0x1: - cpubus_speed = "50"; - pci_speed = "25"; - break; - case 0x3: - cpubus_speed = "66"; - pci_speed = "33"; - break; - default: - cpubus_speed = "unknown"; - pci_speed = "unknown"; - break; - } - } else { - switch ((equip_reg & 0x30) >> 4) { - case 0x1: - cpubus_speed = "25"; - pci_speed = "25"; - break; - case 0x2: - cpubus_speed = "60"; - pci_speed = "30"; - break; - case 0x3: - cpubus_speed = "33"; - pci_speed = "33"; - break; - default: - cpubus_speed = "unknown"; - pci_speed = "unknown"; - break; - } - } - seq_printf(m, "60x bus\t\t: %sMHz\n", cpubus_speed); - seq_printf(m, "pci bus\t\t: %sMHz\n", pci_speed); - - return 0; -} - -static int -prep_carolina_cpuinfo(struct seq_file *m) -{ - unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT); - - prep_ibm_cpuinfo(m); - - /* report amount and type of L2 cache present */ - seq_printf(m, "l2 cache\t: "); - if ((equip_reg & 0x1) == 0) { - unsigned int l2_reg = inb(PREP_IBM_L2INFO); - - /* L2 size */ - if ((l2_reg & 0x60) == 0) - seq_printf(m, "256KiB"); - else if ((l2_reg & 0x60) == 0x20) - seq_printf(m, "512KiB"); - else - seq_printf(m, "unknown size"); - - /* L2 type */ - if ((l2_reg & 0x3) == 0) - seq_printf(m, ", async"); - else if ((l2_reg & 0x3) == 1) - seq_printf(m, ", sync"); - else - seq_printf(m, ", unknown type"); - - seq_printf(m, "\n"); - } else { - seq_printf(m, "not present\n"); - } - - return 0; -} - -static int -prep_tiger1_cpuinfo(struct seq_file *m) -{ - unsigned int l2_reg = inb(PREP_IBM_L2INFO); - - prep_ibm_cpuinfo(m); - - /* report amount and type of L2 cache present */ - seq_printf(m, "l2 cache\t: "); - if ((l2_reg & 0xf) == 0xf) { - seq_printf(m, "not present\n"); - } else { - if (l2_reg & 0x8) - seq_printf(m, "async, "); - else - seq_printf(m, "sync burst, "); - - if (l2_reg & 0x4) - seq_printf(m, "parity, "); - else - seq_printf(m, "no parity, "); - - switch (l2_reg & 0x3) { - case 0x0: - seq_printf(m, "256KiB\n"); - break; - case 0x1: - seq_printf(m, "512KiB\n"); - break; - case 0x2: - seq_printf(m, "1MiB\n"); - break; - default: - seq_printf(m, "unknown size\n"); - break; - } - } - - return 0; -} - - -/* Used by all Motorola PReP */ -static int -prep_mot_cpuinfo(struct seq_file *m) -{ - unsigned int cachew = *((unsigned char *)CACHECRBA); - - seq_printf(m, "machine\t\t: PReP %s\n", Motherboard_map_name); - - /* report amount and type of L2 cache present */ - seq_printf(m, "l2 cache\t: "); - switch (cachew & L2CACHE_MASK) { - case L2CACHE_512KB: - seq_printf(m, "512KiB"); - break; - case L2CACHE_256KB: - seq_printf(m, "256KiB"); - break; - case L2CACHE_1MB: - seq_printf(m, "1MiB"); - break; - case L2CACHE_NONE: - seq_printf(m, "none\n"); - goto no_l2; - break; - default: - seq_printf(m, "%x\n", cachew); - } - - seq_printf(m, ", parity %s", - (cachew & L2CACHE_PARITY)? "enabled" : "disabled"); - - seq_printf(m, " SRAM:"); - - switch ( ((cachew & 0xf0) >> 4) & ~(0x3) ) { - case 1: seq_printf(m, "synchronous, parity, flow-through\n"); - break; - case 2: seq_printf(m, "asynchronous, no parity\n"); - break; - case 3: seq_printf(m, "asynchronous, parity\n"); - break; - default:seq_printf(m, "synchronous, pipelined, no parity\n"); - break; - } - -no_l2: - /* print info about SIMMs */ - if (have_residual_data) { - int i; - seq_printf(m, "simms\t\t: "); - for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) { - if (res->Memories[i].SIMMSize != 0) - seq_printf(m, "%d:%ldM ", i, - (res->Memories[i].SIMMSize > 1024) ? - res->Memories[i].SIMMSize>>20 : - res->Memories[i].SIMMSize); - } - seq_printf(m, "\n"); - } - - return 0; -} - -static void -prep_restart(char *cmd) -{ -#define PREP_SP92 0x92 /* Special Port 92 */ - local_irq_disable(); /* no interrupts */ - - /* set exception prefix high - to the prom */ - _nmask_and_or_msr(0, MSR_IP); - - /* make sure bit 0 (reset) is a 0 */ - outb( inb(PREP_SP92) & ~1L , PREP_SP92); - /* signal a reset to system control port A - soft reset */ - outb( inb(PREP_SP92) | 1 , PREP_SP92); - - while ( 1 ) ; - /* not reached */ -#undef PREP_SP92 -} - -static void -prep_halt(void) -{ - local_irq_disable(); /* no interrupts */ - - /* set exception prefix high - to the prom */ - _nmask_and_or_msr(0, MSR_IP); - - while ( 1 ) ; - /* not reached */ -} - -/* Carrera is the power manager in the Thinkpads. Unfortunately not much is - * known about it, so we can't power down. - */ -static void -prep_carrera_poweroff(void) -{ - prep_halt(); -} - -/* - * On most IBM PReP's, power management is handled by a Signetics 87c750 - * behind the Utah component on the ISA bus. To access the 750 you must write - * a series of nibbles to port 0x82a (decoded by the Utah). This is described - * somewhat in the IBM Carolina Technical Specification. - * -Hollis - */ -static void -utah_sig87c750_setbit(unsigned int bytenum, unsigned int bitnum, int value) -{ - /* - * byte1: 0 0 0 1 0 d a5 a4 - * byte2: 0 0 0 1 a3 a2 a1 a0 - * - * d = the bit's value, enabled or disabled - * (a5 a4 a3) = the byte number, minus 20 - * (a2 a1 a0) = the bit number - * - * example: set the 5th bit of byte 21 (21.5) - * a5 a4 a3 = 001 (byte 1) - * a2 a1 a0 = 101 (bit 5) - * - * byte1 = 0001 0100 (0x14) - * byte2 = 0001 1101 (0x1d) - */ - unsigned char byte1=0x10, byte2=0x10; - - /* the 750's '20.0' is accessed as '0.0' through Utah (which adds 20) */ - bytenum -= 20; - - byte1 |= (!!value) << 2; /* set d */ - byte1 |= (bytenum >> 1) & 0x3; /* set a5, a4 */ - - byte2 |= (bytenum & 0x1) << 3; /* set a3 */ - byte2 |= bitnum & 0x7; /* set a2, a1, a0 */ - - outb(byte1, PREP_IBM_PM1); /* first nibble */ - mb(); - udelay(100); /* important: let controller recover */ - - outb(byte2, PREP_IBM_PM1); /* second nibble */ - mb(); - udelay(100); /* important: let controller recover */ -} - -static void -prep_sig750_poweroff(void) -{ - /* tweak the power manager found in most IBM PRePs (except Thinkpads) */ - - local_irq_disable(); - /* set exception prefix high - to the prom */ - _nmask_and_or_msr(0, MSR_IP); - - utah_sig87c750_setbit(21, 5, 1); /* set bit 21.5, "PMEXEC_OFF" */ - - while (1) ; - /* not reached */ -} - -static int -prep_show_percpuinfo(struct seq_file *m, int i) -{ - /* PREP's without residual data will give incorrect values here */ - seq_printf(m, "clock\t\t: "); - if (have_residual_data) - seq_printf(m, "%ldMHz\n", - (res->VitalProductData.ProcessorHz > 1024) ? - res->VitalProductData.ProcessorHz / 1000000 : - res->VitalProductData.ProcessorHz); - else - seq_printf(m, "???\n"); - - return 0; -} - -/* - * Fill out screen_info according to the residual data. This allows us to use - * at least vesafb. - */ -static void __init -prep_init_vesa(void) -{ -#if (defined(CONFIG_FB_VGA16) || defined(CONFIG_FB_VGA16_MODULE) || \ - defined(CONFIG_FB_VESA)) - PPC_DEVICE *vgadev = NULL; - - if (have_residual_data) - vgadev = residual_find_device(~0, NULL, DisplayController, - SVGAController, -1, 0); - - if (vgadev != NULL) { - PnP_TAG_PACKET *pkt; - - pkt = PnP_find_large_vendor_packet( - (unsigned char *)&res->DevicePnPHeap[vgadev->AllocatedOffset], - 0x04, 0); /* 0x04 = Display Tag */ - if (pkt != NULL) { - unsigned char *ptr = (unsigned char *)pkt; - - if (ptr[4]) { - /* graphics mode */ - screen_info.orig_video_isVGA = VIDEO_TYPE_VLFB; - - screen_info.lfb_depth = ptr[4] * 8; - - screen_info.lfb_width = swab16(*(short *)(ptr+6)); - screen_info.lfb_height = swab16(*(short *)(ptr+8)); - screen_info.lfb_linelength = swab16(*(short *)(ptr+10)); - - screen_info.lfb_base = swab32(*(long *)(ptr+12)); - screen_info.lfb_size = swab32(*(long *)(ptr+20)) / 65536; - } - } - } -#endif -} - -/* - * Set DBAT 2 to access 0x80000000 so early progress messages will work - */ -static __inline__ void -prep_set_bat(void) -{ - /* wait for all outstanding memory access to complete */ - mb(); - - /* setup DBATs */ - mtspr(SPRN_DBAT2U, 0x80001ffe); - mtspr(SPRN_DBAT2L, 0x8000002a); - - /* wait for updates */ - mb(); -} - -/* - * IBM 3-digit status LED - */ -static unsigned int ibm_statusled_base; - -static void -ibm_statusled_progress(char *s, unsigned short hex); - -static int -ibm_statusled_panic(struct notifier_block *dummy1, unsigned long dummy2, - void * dummy3) -{ - ibm_statusled_progress(NULL, 0x505); /* SOS */ - return NOTIFY_DONE; -} - -static struct notifier_block ibm_statusled_block = { - ibm_statusled_panic, - NULL, - INT_MAX /* try to do it first */ -}; - -static void -ibm_statusled_progress(char *s, unsigned short hex) -{ - static int notifier_installed; - /* - * Progress uses 4 digits and we have only 3. So, we map 0xffff to - * 0xfff for display switch off. Out of range values are mapped to - * 0xeff, as I'm told 0xf00 and above are reserved for hardware codes. - * Install the panic notifier when the display is first switched off. - */ - if (hex == 0xffff) { - hex = 0xfff; - if (!notifier_installed) { - ++notifier_installed; - atomic_notifier_chain_register(&panic_notifier_list, - &ibm_statusled_block); - } - } - else - if (hex > 0xfff) - hex = 0xeff; - - mb(); - outw(hex, ibm_statusled_base); -} - -static void __init -ibm_statusled_init(void) -{ - /* - * The IBM 3-digit LED display is specified in the residual data - * as an operator panel device, type "System Status LED". Find - * that device and determine its address. We validate all the - * other parameters on the off-chance another, similar device - * exists. - */ - if (have_residual_data) { - PPC_DEVICE *led; - PnP_TAG_PACKET *pkt; - - led = residual_find_device(~0, NULL, SystemPeripheral, - OperatorPanel, SystemStatusLED, 0); - if (!led) - return; - - pkt = PnP_find_packet((unsigned char *) - &res->DevicePnPHeap[led->AllocatedOffset], S8_Packet, 0); - if (!pkt) - return; - - if (pkt->S8_Pack.IOInfo != ISAAddr16bit) - return; - if (*(unsigned short *)pkt->S8_Pack.RangeMin != - *(unsigned short *)pkt->S8_Pack.RangeMax) - return; - if (pkt->S8_Pack.IOAlign != 2) - return; - if (pkt->S8_Pack.IONum != 2) - return; - - ibm_statusled_base = ld_le16((unsigned short *) - (pkt->S8_Pack.RangeMin)); - ppc_md.progress = ibm_statusled_progress; - } -} - -static void __init -prep_setup_arch(void) -{ - unsigned char reg; - int is_ide=0; - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000; - - /* Lookup PCI host bridges */ - prep_find_bridges(); - - /* Set up floppy in PS/2 mode */ - outb(0x09, SIO_CONFIG_RA); - reg = inb(SIO_CONFIG_RD); - reg = (reg & 0x3F) | 0x40; - outb(reg, SIO_CONFIG_RD); - outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */ - - switch ( _prep_type ) - { - case _PREP_IBM: - reg = inb(PREP_IBM_PLANAR); - printk(KERN_INFO "IBM planar ID: %02x", reg); - switch (reg) { - case PREP_IBM_SANDALFOOT: - prep_gen_enable_l2(); - setup_ibm_pci = prep_sandalfoot_setup_pci; - ppc_md.power_off = prep_sig750_poweroff; - ppc_md.show_cpuinfo = prep_sandalfoot_cpuinfo; - break; - case PREP_IBM_THINKPAD: - prep_gen_enable_l2(); - setup_ibm_pci = prep_thinkpad_setup_pci; - ppc_md.power_off = prep_carrera_poweroff; - ppc_md.show_cpuinfo = prep_thinkpad_cpuinfo; - break; - default: - if (have_residual_data) { - prep_gen_enable_l2(); - setup_ibm_pci = prep_residual_setup_pci; - ppc_md.power_off = prep_halt; - ppc_md.show_cpuinfo = prep_gen_cpuinfo; - break; - } - else - printk(" - unknown! Assuming Carolina"); - /* fall through */ - case PREP_IBM_CAROLINA_IDE_0: - case PREP_IBM_CAROLINA_IDE_1: - case PREP_IBM_CAROLINA_IDE_2: - case PREP_IBM_CAROLINA_IDE_3: - is_ide = 1; - case PREP_IBM_CAROLINA_SCSI_0: - case PREP_IBM_CAROLINA_SCSI_1: - case PREP_IBM_CAROLINA_SCSI_2: - case PREP_IBM_CAROLINA_SCSI_3: - prep_carolina_enable_l2(); - setup_ibm_pci = prep_carolina_setup_pci; - ppc_md.power_off = prep_sig750_poweroff; - ppc_md.show_cpuinfo = prep_carolina_cpuinfo; - break; - case PREP_IBM_TIGER1_133: - case PREP_IBM_TIGER1_166: - case PREP_IBM_TIGER1_180: - case PREP_IBM_TIGER1_xxx: - case PREP_IBM_TIGER1_333: - prep_carolina_enable_l2(); - setup_ibm_pci = prep_tiger1_setup_pci; - ppc_md.power_off = prep_sig750_poweroff; - ppc_md.show_cpuinfo = prep_tiger1_cpuinfo; - break; - } - printk("\n"); - - /* default root device */ - if (is_ide) - ROOT_DEV = MKDEV(IDE0_MAJOR, 3); - else - ROOT_DEV = MKDEV(SCSI_DISK0_MAJOR, 3); - - break; - case _PREP_Motorola: - prep_gen_enable_l2(); - ppc_md.power_off = prep_halt; - ppc_md.show_cpuinfo = prep_mot_cpuinfo; - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - break; - } - - /* Read in NVRAM data */ - init_prep_nvram(); - - /* if no bootargs, look in NVRAM */ - if ( cmd_line[0] == '\0' ) { - char *bootargs; - bootargs = prep_nvram_get_var("bootargs"); - if (bootargs != NULL) { - strcpy(cmd_line, bootargs); - /* again.. */ - strcpy(boot_command_line, cmd_line); - } - } - - prep_init_vesa(); - - switch (_prep_type) { - case _PREP_Motorola: - raven_init(); - break; - case _PREP_IBM: - ibm_prep_init(); - break; - } - -#ifdef CONFIG_VGA_CONSOLE - /* vgacon.c needs to know where we mapped IO memory in io_block_mapping() */ - vgacon_remap_base = 0xf0000000; - conswitchp = &vga_con; -#endif -} - -/* - * First, see if we can get this information from the residual data. - * This is important on some IBM PReP systems. If we cannot, we let the - * TODC code handle doing this. - */ -static void __init -prep_calibrate_decr(void) -{ - if (have_residual_data) { - unsigned long freq, divisor = 4; - - if ( res->VitalProductData.ProcessorBusHz ) { - freq = res->VitalProductData.ProcessorBusHz; - printk("time_init: decrementer frequency = %lu.%.6lu MHz\n", - (freq/divisor)/1000000, - (freq/divisor)%1000000); - tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000); - tb_ticks_per_jiffy = freq / HZ / divisor; - } - } - else - todc_calibrate_decr(); -} - -static void __init -prep_init_IRQ(void) -{ - unsigned int pci_viddid, pci_did; - - if (OpenPIC_Addr != NULL) { - openpic_init(NUM_8259_INTERRUPTS); - /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */ - openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", - i8259_irq); - } - - if (have_residual_data) { - i8259_init(residual_isapic_addr(), 0); - return; - } - - /* If we have a Raven PCI bridge or a Hawk PCI bridge / Memory - * controller, we poll (as they have a different int-ack address). */ - early_read_config_dword(NULL, 0, 0, PCI_VENDOR_ID, &pci_viddid); - pci_did = (pci_viddid & 0xffff0000) >> 16; - if (((pci_viddid & 0xffff) == PCI_VENDOR_ID_MOTOROLA) - && ((pci_did == PCI_DEVICE_ID_MOTOROLA_RAVEN) - || (pci_did == PCI_DEVICE_ID_MOTOROLA_HAWK))) - i8259_init(0, 0); - else - /* PCI interrupt ack address given in section 6.1.8 of the - * PReP specification. */ - i8259_init(MPC10X_MAPA_PCI_INTACK_ADDR, 0); -} - -#ifdef CONFIG_SMP -/* PReP (MTX) support */ -static int __init -smp_prep_probe(void) -{ - extern int mot_multi; - - if (mot_multi) { - openpic_request_IPIs(); - smp_hw_index[1] = 1; - return 2; - } - - return 1; -} - -static void __init -smp_prep_kick_cpu(int nr) -{ - *(unsigned long *)KERNELBASE = nr; - asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory"); - printk("CPU1 released, waiting\n"); -} - -static void __init -smp_prep_setup_cpu(int cpu_nr) -{ - if (OpenPIC_Addr) - do_openpic_setup_cpu(); -} - -static struct smp_ops_t prep_smp_ops = { - smp_openpic_message_pass, - smp_prep_probe, - smp_prep_kick_cpu, - smp_prep_setup_cpu, - .give_timebase = smp_generic_give_timebase, - .take_timebase = smp_generic_take_timebase, -}; -#endif /* CONFIG_SMP */ - -/* - * Setup the bat mappings we're going to load that cover - * the io areas. RAM was mapped by mapin_ram(). - * -- Cort - */ -static void __init -prep_map_io(void) -{ - io_block_mapping(0x80000000, PREP_ISA_IO_BASE, 0x10000000, _PAGE_IO); - io_block_mapping(0xf0000000, PREP_ISA_MEM_BASE, 0x08000000, _PAGE_IO); -} - -static int __init -prep_request_io(void) -{ -#ifdef CONFIG_NVRAM - request_region(PREP_NVRAM_AS0, 0x8, "nvram"); -#endif - request_region(0x00,0x20,"dma1"); - request_region(0x40,0x20,"timer"); - request_region(0x80,0x10,"dma page reg"); - request_region(0xc0,0x20,"dma2"); - - return 0; -} - -device_initcall(prep_request_io); - -void __init -prep_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ -#ifdef CONFIG_PREP_RESIDUAL - /* make a copy of residual data */ - if ( r3 ) { - memcpy((void *)res,(void *)(r3+KERNELBASE), - sizeof(RESIDUAL)); - } -#endif - - isa_io_base = PREP_ISA_IO_BASE; - isa_mem_base = PREP_ISA_MEM_BASE; - pci_dram_offset = PREP_PCI_DRAM_OFFSET; - ISA_DMA_THRESHOLD = 0x00ffffff; - DMA_MODE_READ = 0x44; - DMA_MODE_WRITE = 0x48; - ppc_do_canonicalize_irqs = 1; - - /* figure out what kind of prep workstation we are */ - if (have_residual_data) { - if ( !strncmp(res->VitalProductData.PrintableModel,"IBM",3) ) - _prep_type = _PREP_IBM; - else - _prep_type = _PREP_Motorola; - } - else { - /* assume motorola if no residual (netboot?) */ - _prep_type = _PREP_Motorola; - } - -#ifdef CONFIG_PREP_RESIDUAL - /* Switch off all residual data processing if the user requests it */ - if (strstr(cmd_line, "noresidual") != NULL) - res = NULL; -#endif - - /* Initialise progress early to get maximum benefit */ - prep_set_bat(); - ibm_statusled_init(); - - ppc_md.setup_arch = prep_setup_arch; - ppc_md.show_percpuinfo = prep_show_percpuinfo; - ppc_md.show_cpuinfo = NULL; /* set in prep_setup_arch() */ - ppc_md.init_IRQ = prep_init_IRQ; - /* this gets changed later on if we have an OpenPIC -- Cort */ - ppc_md.get_irq = i8259_irq; - - ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; - - ppc_md.restart = prep_restart; - ppc_md.power_off = NULL; /* set in prep_setup_arch() */ - ppc_md.halt = prep_halt; - - ppc_md.nvram_read_val = prep_nvram_read_val; - ppc_md.nvram_write_val = prep_nvram_write_val; - - ppc_md.time_init = todc_time_init; - if (_prep_type == _PREP_IBM) { - ppc_md.rtc_read_val = todc_mc146818_read_val; - ppc_md.rtc_write_val = todc_mc146818_write_val; - TODC_INIT(TODC_TYPE_MC146818, RTC_PORT(0), NULL, RTC_PORT(1), - 8); - } else { - TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1, - PREP_NVRAM_DATA, 8); - } - - ppc_md.calibrate_decr = prep_calibrate_decr; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - - ppc_md.setup_io_mappings = prep_map_io; - -#ifdef CONFIG_SMP - smp_ops = &prep_smp_ops; -#endif /* CONFIG_SMP */ -} diff --git a/arch/ppc/platforms/prpmc750.c b/arch/ppc/platforms/prpmc750.c deleted file mode 100644 index 93bd593cf957..000000000000 --- a/arch/ppc/platforms/prpmc750.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board setup routines for Motorola PrPMC750 - * - * Author: Matt Porter - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "prpmc750.h" - -extern unsigned long loops_per_jiffy; - -extern void gen550_progress(char *, unsigned short); - -static u_char prpmc750_openpic_initsenses[] __initdata = -{ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HOSTINT0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UART */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_DEBUGINT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HAWK_WDT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UNUSED */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_ABORT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HOSTINT1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HOSTINT2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HOSTINT3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_PMC_INTA */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_PMC_INTB */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_PMC_INTC */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_PMC_INTD */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UNUSED */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UNUSED */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UNUSED */ -}; - -/* - * Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier - * Combined irq tables. Only Base has IDSEL 14, only Carrier has 21 and 22. - */ -static inline int -prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */ - {0, 0, 0, 0}, /* IDSEL 15 - unused */ - {10, 11, 12, 9}, /* IDSEL 16 - PMC A1, PMC1 */ - {10, 11, 12, 9}, /* IDSEL 17 - PrPMC-A-B, PMC2-B */ - {11, 12, 9, 10}, /* IDSEL 18 - PMC A1-B, PMC1-B */ - {0, 0, 0, 0}, /* IDSEL 19 - unused */ - {9, 10, 11, 12}, /* IDSEL 20 - P2P Bridge */ - {11, 12, 9, 10}, /* IDSEL 21 - PMC A2, carrier */ - {12, 9, 10, 11}, /* IDSEL 22 - PMC A2-B, carrier */ - }; - const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -}; - -static void __init prpmc750_pcibios_fixup(void) -{ - struct pci_dev *dev; - unsigned short wtmp; - - /* - * Kludge to clean up after PPC6BUG which doesn't - * configure the CL5446 VGA card. Also the - * resource subsystem doesn't fixup the - * PCI mem resources on the CL5446. - */ - if ((dev = pci_get_device(PCI_VENDOR_ID_CIRRUS, - PCI_DEVICE_ID_CIRRUS_5446, 0))) { - dev->resource[0].start += PRPMC750_PCI_PHY_MEM_OFFSET; - dev->resource[0].end += PRPMC750_PCI_PHY_MEM_OFFSET; - pci_read_config_word(dev, PCI_COMMAND, &wtmp); - pci_write_config_word(dev, PCI_COMMAND, wtmp | 3); - /* Enable Color mode in MISC reg */ - outb(0x03, 0x3c2); - /* Select DRAM config reg */ - outb(0x0f, 0x3c4); - /* Set proper DRAM config */ - outb(0xdf, 0x3c5); - pci_dev_put(dev); - } -} - -void __init prpmc750_find_bridges(void) -{ - struct pci_controller *hose; - - hose = pcibios_alloc_controller(); - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - hose->io_base_virt = (void *)PRPMC750_ISA_IO_BASE; - hose->pci_mem_offset = PRPMC750_PCI_PHY_MEM_OFFSET; - - pci_init_resource(&hose->io_resource, - PRPMC750_PCI_IO_START, - PRPMC750_PCI_IO_END, - IORESOURCE_IO, "PCI host bridge"); - - pci_init_resource(&hose->mem_resources[0], - PRPMC750_PROC_PCI_MEM_START, - PRPMC750_PROC_PCI_MEM_END, - IORESOURCE_MEM, "PCI host bridge"); - - hose->io_space.start = PRPMC750_PCI_IO_START; - hose->io_space.end = PRPMC750_PCI_IO_END; - hose->mem_space.start = PRPMC750_PCI_MEM_START; - hose->mem_space.end = PRPMC750_PCI_MEM_END - HAWK_MPIC_SIZE; - - if (hawk_init(hose, PRPMC750_HAWK_PPC_REG_BASE, - PRPMC750_PROC_PCI_MEM_START, - PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE, - PRPMC750_PROC_PCI_IO_START, PRPMC750_PROC_PCI_IO_END, - PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1) - != 0) { - printk(KERN_CRIT "Could not initialize host bridge\n"); - } - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pcibios_fixup = prpmc750_pcibios_fixup; - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = prpmc_map_irq; -} -static int prpmc750_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "machine\t\t: PrPMC750\n"); - - return 0; -} - -static void __init prpmc750_setup_arch(void) -{ - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000 / HZ; - - /* Lookup PCI host bridges */ - prpmc750_find_bridges(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - OpenPIC_InitSenses = prpmc750_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(prpmc750_openpic_initsenses); - - printk(KERN_INFO "Port by MontaVista Software, Inc. " - "(source@mvista.com)\n"); -} - -/* - * Compute the PrPMC750's bus speed using the baud clock as a - * reference. - */ -static unsigned long __init prpmc750_get_bus_speed(void) -{ - unsigned long tbl_start, tbl_end; - unsigned long current_state, old_state, bus_speed; - unsigned char lcr, dll, dlm; - int baud_divisor, count; - - /* Read the UART's baud clock divisor */ - lcr = readb(PRPMC750_SERIAL_0_LCR); - writeb(lcr | UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR); - dll = readb(PRPMC750_SERIAL_0_DLL); - dlm = readb(PRPMC750_SERIAL_0_DLM); - writeb(lcr & ~UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR); - baud_divisor = (dlm << 8) | dll; - - /* - * Use the baud clock divisor and base baud clock - * to determine the baud rate and use that as - * the number of baud clock edges we use for - * the time base sample. Make it half the baud - * rate. - */ - count = PRPMC750_BASE_BAUD / (baud_divisor * 16); - - /* Find the first edge of the baud clock */ - old_state = readb(PRPMC750_STATUS_REG) & PRPMC750_BAUDOUT_MASK; - do { - current_state = readb(PRPMC750_STATUS_REG) & - PRPMC750_BAUDOUT_MASK; - } while (old_state == current_state); - - old_state = current_state; - - /* Get the starting time base value */ - tbl_start = get_tbl(); - - /* - * Loop until we have found a number of edges equal - * to half the count (half the baud rate) - */ - do { - do { - current_state = readb(PRPMC750_STATUS_REG) & - PRPMC750_BAUDOUT_MASK; - } while (old_state == current_state); - old_state = current_state; - } while (--count); - - /* Get the ending time base value */ - tbl_end = get_tbl(); - - /* Compute bus speed */ - bus_speed = (tbl_end - tbl_start) * 128; - - return bus_speed; -} - -static void __init prpmc750_calibrate_decr(void) -{ - unsigned long freq; - int divisor = 4; - - freq = prpmc750_get_bus_speed(); - - tb_ticks_per_jiffy = freq / (HZ * divisor); - tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); -} - -static void prpmc750_restart(char *cmd) -{ - local_irq_disable(); - writeb(PRPMC750_MODRST_MASK, PRPMC750_MODRST_REG); - while (1) ; -} - -static void prpmc750_halt(void) -{ - local_irq_disable(); - while (1) ; -} - -static void prpmc750_power_off(void) -{ - prpmc750_halt(); -} - -static void __init prpmc750_init_IRQ(void) -{ - openpic_init(0); -} - -/* - * Set BAT 3 to map 0xf0000000 to end of physical memory space. - */ -static __inline__ void prpmc750_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT1U, 0xf0001ffe); - mtspr(SPRN_DBAT1L, 0xf000002a); - mb(); -} - -/* - * We need to read the Falcon/Hawk memory controller - * to properly determine this value - */ -static unsigned long __init prpmc750_find_end_of_memory(void) -{ - /* Read the memory size from the Hawk SMC */ - return hawk_get_mem_size(PRPMC750_HAWK_SMC_BASE); -} - -static void __init prpmc750_map_io(void) -{ - io_block_mapping(PRPMC750_ISA_IO_BASE, PRPMC750_ISA_IO_BASE, - 0x10000000, _PAGE_IO); -#if 0 - io_block_mapping(0xf0000000, 0xc0000000, 0x08000000, _PAGE_IO); -#endif - io_block_mapping(0xf8000000, 0xf8000000, 0x08000000, _PAGE_IO); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* Cover the Hawk registers with a BAT */ - prpmc750_set_bat(); - - isa_io_base = PRPMC750_ISA_IO_BASE; - isa_mem_base = PRPMC750_ISA_MEM_BASE; - pci_dram_offset = PRPMC750_PCI_DRAM_OFFSET; - - ppc_md.setup_arch = prpmc750_setup_arch; - ppc_md.show_cpuinfo = prpmc750_show_cpuinfo; - ppc_md.init_IRQ = prpmc750_init_IRQ; - ppc_md.get_irq = openpic_get_irq; - - ppc_md.find_end_of_memory = prpmc750_find_end_of_memory; - ppc_md.setup_io_mappings = prpmc750_map_io; - - ppc_md.restart = prpmc750_restart; - ppc_md.power_off = prpmc750_power_off; - ppc_md.halt = prpmc750_halt; - - /* PrPMC750 has no timekeeper part */ - ppc_md.time_init = NULL; - ppc_md.get_rtc_time = NULL; - ppc_md.set_rtc_time = NULL; - ppc_md.calibrate_decr = prpmc750_calibrate_decr; - -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ -} diff --git a/arch/ppc/platforms/prpmc750.h b/arch/ppc/platforms/prpmc750.h deleted file mode 100644 index c4dcff09d7ca..000000000000 --- a/arch/ppc/platforms/prpmc750.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * arch/ppc/platforms/prpmc750.h - * - * Definitions for Motorola PrPMC750 board support - * - * Author: Matt Porter - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_PRPMC750_H__ -#define __ASM_PRPMC750_H__ - -/* - * Due to limitations imposed by legacy hardware (primarily IDE controllers), - * the PrPMC750 carrier board operates using a PReP address map. - * - * From Processor (physical) -> PCI: - * PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB) - * PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB) - * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area - * - * From PCI -> Processor (physical): - * System Memory: 0x80000000 -> 0x00000000 - */ - -#define PRPMC750_ISA_IO_BASE PREP_ISA_IO_BASE -#define PRPMC750_ISA_MEM_BASE PREP_ISA_MEM_BASE - -/* PCI Memory space mapping info */ -#define PRPMC750_PCI_MEM_SIZE 0x30000000U -#define PRPMC750_PROC_PCI_MEM_START PRPMC750_ISA_MEM_BASE -#define PRPMC750_PROC_PCI_MEM_END (PRPMC750_PROC_PCI_MEM_START + \ - PRPMC750_PCI_MEM_SIZE - 1) -#define PRPMC750_PCI_MEM_START 0x00000000U -#define PRPMC750_PCI_MEM_END (PRPMC750_PCI_MEM_START + \ - PRPMC750_PCI_MEM_SIZE - 1) - -/* PCI I/O space mapping info */ -#define PRPMC750_PCI_IO_SIZE 0x10000000U -#define PRPMC750_PROC_PCI_IO_START PRPMC750_ISA_IO_BASE -#define PRPMC750_PROC_PCI_IO_END (PRPMC750_PROC_PCI_IO_START + \ - PRPMC750_PCI_IO_SIZE - 1) -#define PRPMC750_PCI_IO_START 0x00000000U -#define PRPMC750_PCI_IO_END (PRPMC750_PCI_IO_START + \ - PRPMC750_PCI_IO_SIZE - 1) - -/* System memory mapping info */ -#define PRPMC750_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET -#define PRPMC750_PCI_PHY_MEM_OFFSET (PRPMC750_ISA_MEM_BASE-PRPMC750_PCI_MEM_START) - -/* Register address definitions */ -#define PRPMC750_HAWK_SMC_BASE 0xfef80000U -#define PRPMC750_HAWK_PPC_REG_BASE 0xfeff0000U - -#define PRPMC750_BASE_BAUD 1843200 -#define PRPMC750_SERIAL_0 0xfef88000 -#define PRPMC750_SERIAL_0_DLL (PRPMC750_SERIAL_0 + (UART_DLL << 4)) -#define PRPMC750_SERIAL_0_DLM (PRPMC750_SERIAL_0 + (UART_DLM << 4)) -#define PRPMC750_SERIAL_0_LCR (PRPMC750_SERIAL_0 + (UART_LCR << 4)) - -#define PRPMC750_STATUS_REG 0xfef88080 -#define PRPMC750_BAUDOUT_MASK 0x02 -#define PRPMC750_MONARCH_MASK 0x01 - -#define PRPMC750_MODRST_REG 0xfef880a0 -#define PRPMC750_MODRST_MASK 0x01 - -#define PRPMC750_PIRQ_REG 0xfef880b0 -#define PRPMC750_SEL1_MASK 0x02 -#define PRPMC750_SEL0_MASK 0x01 - -#define PRPMC750_TBEN_REG 0xfef880c0 -#define PRPMC750_TBEN_MASK 0x01 - -/* UART Defines. */ -#define RS_TABLE_SIZE 4 - -/* Rate for the 1.8432 Mhz clock for the onboard serial chip */ -#define BASE_BAUD (PRPMC750_BASE_BAUD / 16) - -#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF - -#define SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, PRPMC750_SERIAL_0, 1, STD_COM_FLAGS, \ - iomem_base: (unsigned char *)PRPMC750_SERIAL_0, \ - iomem_reg_shift: 4, \ - io_type: SERIAL_IO_MEM } /* ttyS0 */ - -#endif /* __ASM_PRPMC750_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/prpmc800.c b/arch/ppc/platforms/prpmc800.c deleted file mode 100644 index 5bcda7f92cd0..000000000000 --- a/arch/ppc/platforms/prpmc800.c +++ /dev/null @@ -1,472 +0,0 @@ -/* - * Author: Dale Farnsworth - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "prpmc800.h" - -#define HARRIER_REVI_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_REVI_OFF) -#define HARRIER_UCTL_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_UCTL_OFF) -#define HARRIER_MISC_CSR_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_MISC_CSR_OFF) -#define HARRIER_IFEVP_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEVP_OFF) -#define HARRIER_IFEDE_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEDE_OFF) -#define HARRIER_FEEN_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEEN_OFF) -#define HARRIER_FEMA_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEMA_OFF) - -#define HARRIER_VENI_REG (PRPMC800_HARRIER_XCSR_BASE + HARRIER_VENI_OFF) -#define HARRIER_MISC_CSR (PRPMC800_HARRIER_XCSR_BASE + \ - HARRIER_MISC_CSR_OFF) - -#define MONARCH (monarch != 0) -#define NON_MONARCH (monarch == 0) - -extern int mpic_init(void); -extern unsigned long loops_per_jiffy; -extern void gen550_progress(char *, unsigned short); - -static int monarch = 0; -static int found_self = 0; -static int self = 0; - -static u_char prpmc800_openpic_initsenses[] __initdata = -{ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT0 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_DEBUGINT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HARRIER_WDT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTA */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTB */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTC */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTD */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HARRIER_INT (UARTS, ABORT, DMA) */ -}; - -/* - * Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier - * Combined irq tables. Only Base has IDSEL 14, only Carrier has 21 and 22. - */ -static inline int -prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */ - {0, 0, 0, 0}, /* IDSEL 15 - unused */ - {10, 11, 12, 9}, /* IDSEL 16 - PMC A1, PMC1 */ - {10, 11, 12, 9}, /* IDSEL 17 - PrPMC-A-B, PMC2-B */ - {11, 12, 9, 10}, /* IDSEL 18 - PMC A1-B, PMC1-B */ - {0, 0, 0, 0}, /* IDSEL 19 - unused */ - {9, 10, 11, 12}, /* IDSEL 20 - P2P Bridge */ - {11, 12, 9, 10}, /* IDSEL 21 - PMC A2, carrier */ - {12, 9, 10, 11}, /* IDSEL 22 - PMC A2-B, carrier */ - }; - const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -}; - -static int -prpmc_read_config_dword(struct pci_controller *hose, u8 bus, u8 devfn, - int offset, u32 * val) -{ - /* paranoia */ - if ((hose == NULL) || - (hose->cfg_addr == NULL) || (hose->cfg_data == NULL)) - return PCIBIOS_DEVICE_NOT_FOUND; - - out_be32(hose->cfg_addr, ((offset & 0xfc) << 24) | (devfn << 16) - | ((bus - hose->bus_offset) << 8) | 0x80); - *val = in_le32((u32 *) (hose->cfg_data + (offset & 3))); - - return PCIBIOS_SUCCESSFUL; -} - -#define HARRIER_PCI_VEND_DEV_ID (PCI_VENDOR_ID_MOTOROLA | \ - (PCI_DEVICE_ID_MOTOROLA_HARRIER << 16)) -static int prpmc_self(u8 bus, u8 devfn) -{ - /* - * Harriers always view themselves as being on bus 0. If we're not - * looking at bus 0, we're not going to find ourselves. - */ - if (bus != 0) - return PCIBIOS_DEVICE_NOT_FOUND; - else { - int result; - int val; - struct pci_controller *hose; - - hose = pci_bus_to_hose(bus); - - /* See if target device is a Harrier */ - result = prpmc_read_config_dword(hose, bus, devfn, - PCI_VENDOR_ID, &val); - if ((result != PCIBIOS_SUCCESSFUL) || - (val != HARRIER_PCI_VEND_DEV_ID)) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* - * LBA bit is set if target Harrier == initiating Harrier - * (i.e. if we are reading our own PCI header). - */ - result = prpmc_read_config_dword(hose, bus, devfn, - HARRIER_LBA_OFF, &val); - if ((result != PCIBIOS_SUCCESSFUL) || - ((val & HARRIER_LBA_MSK) != HARRIER_LBA_MSK)) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* It's us, save our location for later */ - self = devfn; - found_self = 1; - return PCIBIOS_SUCCESSFUL; - } -} - -static int prpmc_exclude_device(u8 bus, u8 devfn) -{ - /* - * Monarch is allowed to access all PCI devices. Non-monarch is - * only allowed to access its own Harrier. - */ - - if (MONARCH) - return PCIBIOS_SUCCESSFUL; - if (found_self) - if ((bus == 0) && (devfn == self)) - return PCIBIOS_SUCCESSFUL; - else - return PCIBIOS_DEVICE_NOT_FOUND; - else - return prpmc_self(bus, devfn); -} - -void __init prpmc800_find_bridges(void) -{ - struct pci_controller *hose; - int host_bridge; - - hose = pcibios_alloc_controller(); - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - ppc_md.pci_exclude_device = prpmc_exclude_device; - ppc_md.pcibios_fixup = NULL; - ppc_md.pcibios_fixup_bus = NULL; - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = prpmc_map_irq; - - setup_indirect_pci(hose, - PRPMC800_PCI_CONFIG_ADDR, PRPMC800_PCI_CONFIG_DATA); - - /* Get host bridge vendor/dev id */ - - host_bridge = in_be32((uint *) (HARRIER_VENI_REG)); - - if (host_bridge != HARRIER_VEND_DEV_ID) { - printk(KERN_CRIT "Host bridge 0x%x not supported\n", - host_bridge); - return; - } - - monarch = in_be32((uint *) HARRIER_MISC_CSR) & HARRIER_SYSCON; - - printk(KERN_INFO "Running as %s.\n", - MONARCH ? "Monarch" : "Non-Monarch"); - - hose->io_space.start = PRPMC800_PCI_IO_START; - hose->io_space.end = PRPMC800_PCI_IO_END; - hose->io_base_virt = (void *)PRPMC800_ISA_IO_BASE; - hose->pci_mem_offset = PRPMC800_PCI_PHY_MEM_OFFSET; - - pci_init_resource(&hose->io_resource, - PRPMC800_PCI_IO_START, PRPMC800_PCI_IO_END, - IORESOURCE_IO, "PCI host bridge"); - - if (MONARCH) { - hose->mem_space.start = PRPMC800_PCI_MEM_START; - hose->mem_space.end = PRPMC800_PCI_MEM_END; - - pci_init_resource(&hose->mem_resources[0], - PRPMC800_PCI_MEM_START, - PRPMC800_PCI_MEM_END, - IORESOURCE_MEM, "PCI host bridge"); - - if (harrier_init(hose, - PRPMC800_HARRIER_XCSR_BASE, - PRPMC800_PROC_PCI_MEM_START, - PRPMC800_PROC_PCI_MEM_END, - PRPMC800_PROC_PCI_IO_START, - PRPMC800_PROC_PCI_IO_END, - PRPMC800_HARRIER_MPIC_BASE) != 0) - printk(KERN_CRIT "Could not initialize HARRIER " - "bridge\n"); - - harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE); - harrier_wait_eready(PRPMC800_HARRIER_XCSR_BASE); - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - } else { - pci_init_resource(&hose->mem_resources[0], - PRPMC800_NM_PCI_MEM_START, - PRPMC800_NM_PCI_MEM_END, - IORESOURCE_MEM, "PCI host bridge"); - - hose->mem_space.start = PRPMC800_NM_PCI_MEM_START; - hose->mem_space.end = PRPMC800_NM_PCI_MEM_END; - - if (harrier_init(hose, - PRPMC800_HARRIER_XCSR_BASE, - PRPMC800_NM_PROC_PCI_MEM_START, - PRPMC800_NM_PROC_PCI_MEM_END, - PRPMC800_PROC_PCI_IO_START, - PRPMC800_PROC_PCI_IO_END, - PRPMC800_HARRIER_MPIC_BASE) != 0) - printk(KERN_CRIT "Could not initialize HARRIER " - "bridge\n"); - - harrier_setup_nonmonarch(PRPMC800_HARRIER_XCSR_BASE, - HARRIER_ITSZ_1MB); - harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE); - } -} - -static int prpmc800_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "machine\t\t: PrPMC800\n"); - - return 0; -} - -static void __init prpmc800_setup_arch(void) -{ - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000 / HZ; - - /* Lookup PCI host bridges */ - prpmc800_find_bridges(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA2; -#endif - - printk(KERN_INFO "Port by MontaVista Software, Inc. " - "(source@mvista.com)\n"); -} - -/* - * Compute the PrPMC800's tbl frequency using the baud clock as a reference. - */ -static void __init prpmc800_calibrate_decr(void) -{ - unsigned long tbl_start, tbl_end; - unsigned long current_state, old_state, tb_ticks_per_second; - unsigned int count; - unsigned int harrier_revision; - - harrier_revision = readb(HARRIER_REVI_REG); - if (harrier_revision < 2) { - /* XTAL64 was broken in harrier revision 1 */ - printk(KERN_INFO "time_init: Harrier revision %d, assuming " - "100 Mhz bus\n", harrier_revision); - tb_ticks_per_second = 100000000 / 4; - tb_ticks_per_jiffy = tb_ticks_per_second / HZ; - tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000); - return; - } - - /* - * The XTAL64 bit oscillates at the 1/64 the base baud clock - * Set count to XTAL64 cycles per second. Since we'll count - * half-cycles, we'll reach the count in half a second. - */ - count = PRPMC800_BASE_BAUD / 64; - - /* Find the first edge of the baud clock */ - old_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK; - do { - current_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK; - } while (old_state == current_state); - - old_state = current_state; - - /* Get the starting time base value */ - tbl_start = get_tbl(); - - /* - * Loop until we have found a number of edges (half-cycles) - * equal to the count (half a second) - */ - do { - do { - current_state = readb(HARRIER_UCTL_REG) & - HARRIER_XTAL64_MASK; - } while (old_state == current_state); - old_state = current_state; - } while (--count); - - /* Get the ending time base value */ - tbl_end = get_tbl(); - - /* We only counted for half a second, so double to get ticks/second */ - tb_ticks_per_second = (tbl_end - tbl_start) * 2; - tb_ticks_per_jiffy = tb_ticks_per_second / HZ; - tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000); -} - -static void prpmc800_restart(char *cmd) -{ - ulong temp; - - local_irq_disable(); - temp = in_be32((uint *) HARRIER_MISC_CSR_REG); - temp |= HARRIER_RSTOUT; - out_be32((uint *) HARRIER_MISC_CSR_REG, temp); - while (1) ; -} - -static void prpmc800_halt(void) -{ - local_irq_disable(); - while (1) ; -} - -static void prpmc800_power_off(void) -{ - prpmc800_halt(); -} - -static void __init prpmc800_init_IRQ(void) -{ - OpenPIC_InitSenses = prpmc800_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(prpmc800_openpic_initsenses); - - /* Setup external interrupt sources. */ - openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000); - /* Setup internal UART interrupt source. */ - openpic_set_sources(16, 1, OpenPIC_Addr + 0x10200); - - /* Do the MPIC initialization based on the above settings. */ - openpic_init(0); - - /* enable functional exceptions for uarts and abort */ - out_8((u8 *) HARRIER_FEEN_REG, (HARRIER_FE_UA0 | HARRIER_FE_UA1)); - out_8((u8 *) HARRIER_FEMA_REG, ~(HARRIER_FE_UA0 | HARRIER_FE_UA1)); -} - -/* - * Set BAT 3 to map 0xf0000000 to end of physical memory space. - */ -static __inline__ void prpmc800_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT1U, 0xf0001ffe); - mtspr(SPRN_DBAT1L, 0xf000002a); - mb(); -} - -/* - * We need to read the Harrier memory controller - * to properly determine this value - */ -static unsigned long __init prpmc800_find_end_of_memory(void) -{ - /* Read the memory size from the Harrier XCSR */ - return harrier_get_mem_size(PRPMC800_HARRIER_XCSR_BASE); -} - -static void __init prpmc800_map_io(void) -{ - io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO); - io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - prpmc800_set_bat(); - - isa_io_base = PRPMC800_ISA_IO_BASE; - isa_mem_base = PRPMC800_ISA_MEM_BASE; - pci_dram_offset = PRPMC800_PCI_DRAM_OFFSET; - - ppc_md.setup_arch = prpmc800_setup_arch; - ppc_md.show_cpuinfo = prpmc800_show_cpuinfo; - ppc_md.init_IRQ = prpmc800_init_IRQ; - ppc_md.get_irq = openpic_get_irq; - - ppc_md.find_end_of_memory = prpmc800_find_end_of_memory; - ppc_md.setup_io_mappings = prpmc800_map_io; - - ppc_md.restart = prpmc800_restart; - ppc_md.power_off = prpmc800_power_off; - ppc_md.halt = prpmc800_halt; - - /* PrPMC800 has no timekeeper part */ - ppc_md.time_init = NULL; - ppc_md.get_rtc_time = NULL; - ppc_md.set_rtc_time = NULL; - ppc_md.calibrate_decr = prpmc800_calibrate_decr; -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#else /* !CONFIG_SERIAL_TEXT_DEBUG */ - ppc_md.progress = NULL; -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ -} diff --git a/arch/ppc/platforms/prpmc800.h b/arch/ppc/platforms/prpmc800.h deleted file mode 100644 index 26f604e05cfa..000000000000 --- a/arch/ppc/platforms/prpmc800.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * arch/ppc/platforms/prpmc800.h - * - * Definitions for Motorola PrPMC800 board support - * - * Author: Dale Farnsworth - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - /* - * From Processor to PCI: - * PCI Mem Space: 0x80000000 - 0xa0000000 -> 0x80000000 - 0xa0000000 (512 MB) - * PCI I/O Space: 0xfe400000 - 0xfeef0000 -> 0x00000000 - 0x00b00000 (11 MB) - * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area - * - * From PCI to Processor: - * System Memory: 0x00000000 -> 0x00000000 - */ - -#ifndef __ASMPPC_PRPMC800_H -#define __ASMPPC_PRPMC800_H - -#define PRPMC800_PCI_CONFIG_ADDR 0xfe000cf8 -#define PRPMC800_PCI_CONFIG_DATA 0xfe000cfc - -#define PRPMC800_PROC_PCI_IO_START 0xfe400000U -#define PRPMC800_PROC_PCI_IO_END 0xfeefffffU -#define PRPMC800_PCI_IO_START 0x00000000U -#define PRPMC800_PCI_IO_END 0x00afffffU - -#define PRPMC800_PROC_PCI_MEM_START 0x80000000U -#define PRPMC800_PROC_PCI_MEM_END 0x9fffffffU -#define PRPMC800_PCI_MEM_START 0x80000000U -#define PRPMC800_PCI_MEM_END 0x9fffffffU - -#define PRPMC800_NM_PROC_PCI_MEM_START 0x40000000U -#define PRPMC800_NM_PROC_PCI_MEM_END 0xdfffffffU -#define PRPMC800_NM_PCI_MEM_START 0x40000000U -#define PRPMC800_NM_PCI_MEM_END 0xdfffffffU - -#define PRPMC800_PCI_DRAM_OFFSET 0x00000000U -#define PRPMC800_PCI_PHY_MEM_OFFSET 0x00000000U - -#define PRPMC800_ISA_IO_BASE PRPMC800_PROC_PCI_IO_START -#define PRPMC800_ISA_MEM_BASE 0x00000000U - -#define PRPMC800_HARRIER_XCSR_BASE HARRIER_DEFAULT_XCSR_BASE -#define PRPMC800_HARRIER_MPIC_BASE 0xff000000 - -#define PRPMC800_SERIAL_1 0xfeff00c0 - -#define PRPMC800_BASE_BAUD 1843200 - -/* - * interrupt vector number and priority for harrier internal interrupt - * sources - */ -#define PRPMC800_INT_IRQ 16 -#define PRPMC800_INT_PRI 15 - -/* UART Defines. */ -#define RS_TABLE_SIZE 4 - -/* Rate for the 1.8432 Mhz clock for the onboard serial chip */ -#define BASE_BAUD (PRPMC800_BASE_BAUD / 16) - -#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF - -/* UARTS are at IRQ 16 */ -#define STD_SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, PRPMC800_SERIAL_1, 16, STD_COM_FLAGS, /* ttyS0 */\ - iomem_base: (unsigned char *)PRPMC800_SERIAL_1, \ - iomem_reg_shift: 0, \ - io_type: SERIAL_IO_MEM }, - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DFNS - -#endif /* __ASMPPC_PRPMC800_H */ diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c deleted file mode 100644 index f1dee1e87809..000000000000 --- a/arch/ppc/platforms/radstone_ppc7d.c +++ /dev/null @@ -1,1492 +0,0 @@ -/* - * Board setup routines for the Radstone PPC7D boards. - * - * Author: James Chapman - * - * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il - * Based on code done by - Mark A. Greer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* Radstone PPC7D boards are rugged VME boards with PPC 7447A CPUs, - * Discovery-II, dual gigabit ethernet, dual PMC, USB, keyboard/mouse, - * 4 serial ports, 2 high speed serial ports (MPSCs) and optional - * SCSI / VGA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /* for linux/serial_core.h */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "radstone_ppc7d.h" - -#undef DEBUG - -#define PPC7D_RST_PIN 17 /* GPP17 */ - -extern u32 mv64360_irq_base; -extern spinlock_t rtc_lock; - -static struct mv64x60_handle bh; -static int ppc7d_has_alma; - -extern void gen550_progress(char *, unsigned short); -extern void gen550_init(int, struct uart_port *); - -/* FIXME - move to h file */ -extern int ds1337_do_command(int id, int cmd, void *arg); -#define DS1337_GET_DATE 0 -#define DS1337_SET_DATE 1 - -/* residual data */ -unsigned char __res[sizeof(bd_t)]; - -/***************************************************************************** - * Serial port code - *****************************************************************************/ - -#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG) -static void __init ppc7d_early_serial_map(void) -{ -#if defined(CONFIG_SERIAL_MPSC_CONSOLE) - mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); -#elif defined(CONFIG_SERIAL_8250) - struct uart_port serial_req; - - /* Setup serial port access */ - memset(&serial_req, 0, sizeof(serial_req)); - serial_req.uartclk = UART_CLK; - serial_req.irq = 4; - serial_req.flags = STD_COM_FLAGS; - serial_req.iotype = UPIO_MEM; - serial_req.membase = (u_char *) PPC7D_SERIAL_0; - - gen550_init(0, &serial_req); - if (early_serial_setup(&serial_req) != 0) - printk(KERN_ERR "Early serial init of port 0 failed\n"); - - /* Assume early_serial_setup() doesn't modify serial_req */ - serial_req.line = 1; - serial_req.irq = 3; - serial_req.membase = (u_char *) PPC7D_SERIAL_1; - - gen550_init(1, &serial_req); - if (early_serial_setup(&serial_req) != 0) - printk(KERN_ERR "Early serial init of port 1 failed\n"); -#else -#error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX -#endif -} -#endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */ - -/***************************************************************************** - * Low-level board support code - *****************************************************************************/ - -static unsigned long __init ppc7d_find_end_of_memory(void) -{ - bd_t *bp = (bd_t *) __res; - - if (bp->bi_memsize) - return bp->bi_memsize; - - return (256 * 1024 * 1024); -} - -static void __init ppc7d_map_io(void) -{ - /* remove temporary mapping */ - mtspr(SPRN_DBAT3U, 0x00000000); - mtspr(SPRN_DBAT3L, 0x00000000); - - io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO); - io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO); -} - -static void ppc7d_restart(char *cmd) -{ - u32 data; - - /* Disable GPP17 interrupt */ - data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); - data &= ~(1 << PPC7D_RST_PIN); - mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data); - - /* Configure MPP17 as GPP */ - data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2); - data &= ~(0x0000000f << 4); - mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data); - - /* Enable pin GPP17 for output */ - data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL); - data |= (1 << PPC7D_RST_PIN); - mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data); - - /* Toggle GPP9 pin to reset the board */ - mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, 1 << PPC7D_RST_PIN); - mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, 1 << PPC7D_RST_PIN); - - for (;;) ; /* Spin until reset happens */ - /* NOTREACHED */ -} - -static void ppc7d_power_off(void) -{ - u32 data; - - local_irq_disable(); - - /* Ensure that internal MV643XX watchdog is disabled. - * The Disco watchdog uses MPP17 on this hardware. - */ - data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2); - data &= ~(0x0000000f << 4); - mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data); - - data = mv64x60_read(&bh, MV64x60_WDT_WDC); - if (data & 0x80000000) { - mv64x60_write(&bh, MV64x60_WDT_WDC, 1 << 24); - mv64x60_write(&bh, MV64x60_WDT_WDC, 2 << 24); - } - - for (;;) ; /* No way to shut power off with software */ - /* NOTREACHED */ -} - -static void ppc7d_halt(void) -{ - ppc7d_power_off(); - /* NOTREACHED */ -} - -static unsigned long ppc7d_led_no_pulse; - -static int __init ppc7d_led_pulse_disable(char *str) -{ - ppc7d_led_no_pulse = 1; - return 1; -} - -/* This kernel option disables the heartbeat pulsing of a board LED */ -__setup("ledoff", ppc7d_led_pulse_disable); - -static void ppc7d_heartbeat(void) -{ - u32 data32; - u8 data8; - static int max706_wdog = 0; - - /* Unfortunately we can't access the LED control registers - * during early init because they're on the CPLD which is the - * other side of a PCI bridge which goes unreachable during - * PCI scan. So write the LEDs only if the MV64360 watchdog is - * enabled (i.e. userspace apps are running so kernel is up).. - */ - data32 = mv64x60_read(&bh, MV64x60_WDT_WDC); - if (data32 & 0x80000000) { - /* Enable MAX706 watchdog if not done already */ - if (!max706_wdog) { - outb(3, PPC7D_CPLD_RESET); - max706_wdog = 1; - } - - /* Hit the MAX706 watchdog */ - outb(0, PPC7D_CPLD_WATCHDOG_TRIG); - - /* Pulse LED DS219 if not disabled */ - if (!ppc7d_led_no_pulse) { - static int led_on = 0; - - data8 = inb(PPC7D_CPLD_LEDS); - if (led_on) - data8 &= ~PPC7D_CPLD_LEDS_DS219_MASK; - else - data8 |= PPC7D_CPLD_LEDS_DS219_MASK; - - outb(data8, PPC7D_CPLD_LEDS); - led_on = !led_on; - } - } - ppc_md.heartbeat_count = ppc_md.heartbeat_reset; -} - -static int ppc7d_show_cpuinfo(struct seq_file *m) -{ - u8 val; - u8 val1, val2; - static int flash_sizes[4] = { 64, 32, 0, 16 }; - static int flash_banks[4] = { 4, 3, 2, 1 }; - static int sdram_bank_sizes[4] = { 128, 256, 512, 1 }; - int sdram_num_banks = 2; - static char *pci_modes[] = { "PCI33", "PCI66", - "Unknown", "Unknown", - "PCIX33", "PCIX66", - "PCIX100", "PCIX133" - }; - - seq_printf(m, "vendor\t\t: Radstone Technology\n"); - seq_printf(m, "machine\t\t: PPC7D\n"); - - val = inb(PPC7D_CPLD_BOARD_REVISION); - val1 = (val & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5; - val2 = (val & PPC7D_CPLD_BOARD_REVISION_LETTER_MASK); - seq_printf(m, "revision\t: %hd%c%c\n", - val1, - (val2 <= 0x18) ? 'A' + val2 : 'Y', - (val2 > 0x18) ? 'A' + (val2 - 0x19) : ' '); - - val = inb(PPC7D_CPLD_MOTHERBOARD_TYPE); - val1 = val & PPC7D_CPLD_MB_TYPE_PLL_MASK; - val2 = val & (PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK | - PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK); - seq_printf(m, "bus speed\t: %dMHz\n", - (val1 == PPC7D_CPLD_MB_TYPE_PLL_133) ? 133 : - (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 : - (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0); - - val = inb(PPC7D_CPLD_MEM_CONFIG); - if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--; - - val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND); - val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6; - seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c", - sdram_num_banks, - sdram_bank_sizes[val1], - (sdram_bank_sizes[val1] < 128) ? 'G' : 'M', - sdram_num_banks * sdram_bank_sizes[val1], - (sdram_bank_sizes[val1] < 128) ? 'G' : 'M'); - if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) { - seq_printf(m, " [ECC %sabled]", - (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" : - "dis"); - } - seq_printf(m, "\n"); - - val1 = (val & PPC7D_CPLD_FLASH_DEV_SIZE_MASK); - val2 = (val & PPC7D_CPLD_FLASH_BANK_NUM_MASK) >> 2; - seq_printf(m, "FLASH\t\t: %d banks of %dM, total %dM\n", - flash_banks[val2], flash_sizes[val1], - flash_banks[val2] * flash_sizes[val1]); - - val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL); - val1 = inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT); - seq_printf(m, " write links\t: %s%s%s%s\n", - (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "WRITE " : "", - (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "BOOT " : "", - (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "USER " : "", - (val & (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK | - PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK | - PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK)) == - 0 ? "NONE" : ""); - seq_printf(m, " write sector h/w enables: %s%s%s%s%s\n", - (val & PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK) ? "RECOVERY " : - "", - (val & PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK) ? "BOOT " : "", - (val & PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK) ? "USER " : "", - (val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ? "NVRAM " : - "", - (((val & - (PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK | - PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK | - PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK)) == 0) - && ((val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) == - 0)) ? "NONE" : ""); - val1 = - inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT) & - (PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK | - PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK); - seq_printf(m, " software sector enables: %s%s%s\n", - (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK) ? "SYSBOOT " - : "", - (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK) ? "USER " : "", - (val1 == 0) ? "NONE " : ""); - - seq_printf(m, "Boot options\t: %s%s%s%s\n", - (val & PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK) ? - "ALTERNATE " : "", - (val & PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK) ? "VME " : - "", - (val & PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK) ? "RECOVERY " - : "", - ((val & - (PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK | - PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK | - PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK)) == - 0) ? "NONE" : ""); - - val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_1); - seq_printf(m, "Fitted modules\t: %s%s%s%s\n", - (val & PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK) ? "" : "PMC1 ", - (val & PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK) ? "" : "PMC2 ", - (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) ? "AFIX " : "", - ((val & (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK | - PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK | - PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK)) == - (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK | - PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK)) ? "NONE" : ""); - - if (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) { - static const char *ids[] = { - "unknown", - "1553 (Dual Channel)", - "1553 (Single Channel)", - "8-bit SCSI + VGA", - "16-bit SCSI + VGA", - "1553 (Single Channel with sideband)", - "1553 (Dual Channel with sideband)", - NULL - }; - u8 id = __raw_readb((void *)PPC7D_AFIX_REG_BASE + 0x03); - seq_printf(m, "AFIX module\t: 0x%hx [%s]\n", id, - id < 7 ? ids[id] : "unknown"); - } - - val = inb(PPC7D_CPLD_PCI_CONFIG); - val1 = (val & PPC7D_CPLD_PCI_CONFIG_PCI0_MASK) >> 4; - val2 = (val & PPC7D_CPLD_PCI_CONFIG_PCI1_MASK); - seq_printf(m, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n", - pci_modes[val1], pci_modes[val2]); - - val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2); - seq_printf(m, "PMC1\t\t: %s\nPMC2\t\t: %s\n", - (val & PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK) ? "3.3v" : "5v", - (val & PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK) ? "3.3v" : "5v"); - seq_printf(m, "PMC power source: %s\n", - (val & PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK) ? "VME" : - "internal"); - - val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4); - val2 = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2); - seq_printf(m, "Fit options\t: %s%s%s%s%s%s%s\n", - (val & PPC7D_CPLD_EQPT_PRES_4_LPT_MASK) ? "LPT " : "", - (val & PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED) ? "PS2 " : "", - (val & PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED) ? "USB2 " : "", - (val2 & PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK) ? "VME " : "", - (val2 & PPC7D_CPLD_EQPT_PRES_2_COM36_MASK) ? "COM3-6 " : "", - (val2 & PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK) ? "eth0 " : "", - (val2 & PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK) ? "eth1 " : - ""); - - val = inb(PPC7D_CPLD_ID_LINK); - val1 = val & (PPC7D_CPLD_ID_LINK_E6_MASK | - PPC7D_CPLD_ID_LINK_E7_MASK | - PPC7D_CPLD_ID_LINK_E12_MASK | - PPC7D_CPLD_ID_LINK_E13_MASK); - - val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL) & - (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK | - PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK | - PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK); - - seq_printf(m, "Board links present: %s%s%s%s%s%s%s%s\n", - (val1 & PPC7D_CPLD_ID_LINK_E6_MASK) ? "E6 " : "", - (val1 & PPC7D_CPLD_ID_LINK_E7_MASK) ? "E7 " : "", - (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "E9 " : "", - (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "E10 " : "", - (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "E11 " : "", - (val1 & PPC7D_CPLD_ID_LINK_E12_MASK) ? "E12 " : "", - (val1 & PPC7D_CPLD_ID_LINK_E13_MASK) ? "E13 " : "", - ((val == 0) && (val1 == 0)) ? "NONE" : ""); - - val = inb(PPC7D_CPLD_WDOG_RESETSW_MASK); - seq_printf(m, "Front panel reset switch: %sabled\n", - (val & PPC7D_CPLD_WDOG_RESETSW_MASK) ? "dis" : "en"); - - return 0; -} - -static void __init ppc7d_calibrate_decr(void) -{ - ulong freq; - - freq = 100000000 / 4; - - pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n", - freq / 1000000, freq % 1000000); - - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); -} - -/***************************************************************************** - * Interrupt stuff - *****************************************************************************/ - -static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id) -{ - u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE); - if (temp & (1 << 28)) { - i8259_irq(); - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28))); - return IRQ_HANDLED; - } - - return IRQ_NONE; -} - -/* - * Each interrupt cause is assigned an IRQ number. - * Southbridge has 16*2 (two 8259's) interrupts. - * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32). - * If multiple interrupts are pending, get_irq() returns the - * lowest pending irq number first. - * - * - * IRQ # Source Trig Active - * ============================================================= - * - * Southbridge - * ----------- - * IRQ # Source Trig - * ============================================================= - * 0 ISA High Resolution Counter Edge - * 1 Keyboard Edge - * 2 Cascade From (IRQ 8-15) Edge - * 3 Com 2 (Uart 2) Edge - * 4 Com 1 (Uart 1) Edge - * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level - * 6 GPIO Level - * 7 LPT Edge - * 8 RTC Alarm Edge - * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level - * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level - * 11 USB2 Level - * 12 Mouse Edge - * 13 Reserved internally by Ali M1535+ - * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level - * 15 COM 5/6 Level - * - * 16..112 Discovery-II... - * - * MPP28 Southbridge Edge High - * - * - * Interrupts are cascaded through to the Discovery-II. - * - * PCI --- - * \ - * CPLD --> ALI1535 -------> DISCOVERY-II - * INTF MPP28 - */ -static void __init ppc7d_init_irq(void) -{ - int irq; - - pr_debug("%s\n", __func__); - i8259_init(0, 0); - mv64360_init_irq(); - - /* IRQs 5,6,9,10,11,14,15 are level sensitive */ - irq_desc[5].status |= IRQ_LEVEL; - irq_desc[6].status |= IRQ_LEVEL; - irq_desc[9].status |= IRQ_LEVEL; - irq_desc[10].status |= IRQ_LEVEL; - irq_desc[11].status |= IRQ_LEVEL; - irq_desc[14].status |= IRQ_LEVEL; - irq_desc[15].status |= IRQ_LEVEL; - - /* GPP28 is edge triggered */ - irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL; -} - -static u32 ppc7d_irq_canonicalize(u32 irq) -{ - if ((irq >= 16) && (irq < (16 + 96))) - irq -= 16; - - return irq; -} - -static int ppc7d_get_irq(void) -{ - int irq; - - irq = mv64360_get_irq(); - if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28)) - irq = i8259_irq(); - return irq; -} - -/* - * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level - * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level - * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level - * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level - */ -static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel, - unsigned char pin) -{ - static const char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {10, 14, 5, 9}, /* IDSEL 10 - PMC2 / AFIX IRQW */ - {9, 10, 14, 5}, /* IDSEL 11 - PMC1 / AFIX IRQX */ - {5, 9, 10, 14}, /* IDSEL 12 - AFIX IRQY */ - {14, 5, 9, 10}, /* IDSEL 13 - AFIX IRQZ */ - }; - const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4; - - pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __func__, - dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin); - - return PCI_IRQ_TABLE_LOOKUP; -} - -void __init ppc7d_intr_setup(void) -{ - u32 data; - - /* - * Define GPP 28 interrupt polarity as active high - * input signal and level triggered - */ - data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL); - data &= ~(1 << 28); - mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data); - data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL); - data &= ~(1 << 28); - mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data); - - /* Config GPP intr ctlr to respond to level trigger */ - data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL); - data |= (1 << 10); - mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data); - - /* XXXX Erranum FEr PCI-#8 */ - data = mv64x60_read(&bh, MV64x60_PCI0_CMD); - data &= ~((1 << 5) | (1 << 9)); - mv64x60_write(&bh, MV64x60_PCI0_CMD, data); - data = mv64x60_read(&bh, MV64x60_PCI1_CMD); - data &= ~((1 << 5) | (1 << 9)); - mv64x60_write(&bh, MV64x60_PCI1_CMD, data); - - /* - * Dismiss and then enable interrupt on GPP interrupt cause - * for CPU #0 - */ - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28)); - data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); - data |= (1 << 28); - mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data); - - /* - * Dismiss and then enable interrupt on CPU #0 high cause reg - * BIT27 summarizes GPP interrupts 23-31 - */ - mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27)); - data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI); - data |= (1 << 27); - mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data); -} - -/***************************************************************************** - * Platform device data fixup routines. - *****************************************************************************/ - -#if defined(CONFIG_SERIAL_MPSC) -static void __init ppc7d_fixup_mpsc_pdata(struct platform_device *pdev) -{ - struct mpsc_pdata *pdata; - - pdata = (struct mpsc_pdata *)pdev->dev.platform_data; - - pdata->max_idle = 40; - pdata->default_baud = PPC7D_DEFAULT_BAUD; - pdata->brg_clk_src = PPC7D_MPSC_CLK_SRC; - pdata->brg_clk_freq = PPC7D_MPSC_CLK_FREQ; - - return; -} -#endif - -#if defined(CONFIG_MV643XX_ETH) -static void __init ppc7d_fixup_eth_pdata(struct platform_device *pdev) -{ - struct mv643xx_eth_platform_data *eth_pd; - static u16 phy_addr[] = { - PPC7D_ETH0_PHY_ADDR, - PPC7D_ETH1_PHY_ADDR, - PPC7D_ETH2_PHY_ADDR, - }; - int i; - - eth_pd = pdev->dev.platform_data; - eth_pd->force_phy_addr = 1; - eth_pd->phy_addr = phy_addr[pdev->id]; - eth_pd->tx_queue_size = PPC7D_ETH_TX_QUEUE_SIZE; - eth_pd->rx_queue_size = PPC7D_ETH_RX_QUEUE_SIZE; - - /* Adjust IRQ by mv64360_irq_base */ - for (i = 0; i < pdev->num_resources; i++) { - struct resource *r = &pdev->resource[i]; - - if (r->flags & IORESOURCE_IRQ) { - r->start += mv64360_irq_base; - r->end += mv64360_irq_base; - pr_debug("%s, uses IRQ %d\n", pdev->name, - (int)r->start); - } - } - -} -#endif - -#if defined(CONFIG_I2C_MV64XXX) -static void __init -ppc7d_fixup_i2c_pdata(struct platform_device *pdev) -{ - struct mv64xxx_i2c_pdata *pdata; - int i; - - pdata = pdev->dev.platform_data; - if (pdata == NULL) { - pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); - if (pdata == NULL) - return; - - pdev->dev.platform_data = pdata; - } - - /* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */ - pdata->freq_m = 8; - pdata->freq_n = 3; - pdata->timeout = 500; - pdata->retries = 3; - - /* Adjust IRQ by mv64360_irq_base */ - for (i = 0; i < pdev->num_resources; i++) { - struct resource *r = &pdev->resource[i]; - - if (r->flags & IORESOURCE_IRQ) { - r->start += mv64360_irq_base; - r->end += mv64360_irq_base; - pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start); - } - } -} -#endif - -static int ppc7d_platform_notify(struct device *dev) -{ - static struct { - char *bus_id; - void ((*rtn) (struct platform_device * pdev)); - } dev_map[] = { -#if defined(CONFIG_SERIAL_MPSC) - { MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata }, - { MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata }, -#endif -#if defined(CONFIG_MV643XX_ETH) - { MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata }, - { MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata }, - { MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata }, -#endif -#if defined(CONFIG_I2C_MV64XXX) - { MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata }, -#endif - }; - struct platform_device *pdev; - int i; - - if (dev && dev->bus_id) - for (i = 0; i < ARRAY_SIZE(dev_map); i++) - if (!strncmp(dev->bus_id, dev_map[i].bus_id, - BUS_ID_SIZE)) { - - pdev = container_of(dev, - struct platform_device, - dev); - dev_map[i].rtn(pdev); - } - - return 0; -} - -/***************************************************************************** - * PCI device fixups. - * These aren't really fixups per se. They are used to init devices as they - * are found during PCI scan. - * - * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI - * scan in order to find other devices on its secondary side. - *****************************************************************************/ - -static void __init ppc7d_fixup_hb8(struct pci_dev *dev) -{ - u16 val16; - - if (dev->bus->number == 0) { - pr_debug("PCI: HB8 init\n"); - - pci_write_config_byte(dev, 0x1c, - ((PPC7D_PCI0_IO_START_PCI_ADDR & 0xf000) - >> 8) | 0x01); - pci_write_config_byte(dev, 0x1d, - (((PPC7D_PCI0_IO_START_PCI_ADDR + - PPC7D_PCI0_IO_SIZE - - 1) & 0xf000) >> 8) | 0x01); - pci_write_config_word(dev, 0x30, - PPC7D_PCI0_IO_START_PCI_ADDR >> 16); - pci_write_config_word(dev, 0x32, - ((PPC7D_PCI0_IO_START_PCI_ADDR + - PPC7D_PCI0_IO_SIZE - - 1) >> 16) & 0xffff); - - pci_write_config_word(dev, 0x20, - PPC7D_PCI0_MEM0_START_PCI_LO_ADDR >> 16); - pci_write_config_word(dev, 0x22, - ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + - PPC7D_PCI0_MEM0_SIZE - - 1) >> 16) & 0xffff); - pci_write_config_word(dev, 0x24, 0); - pci_write_config_word(dev, 0x26, 0); - pci_write_config_dword(dev, 0x28, 0); - pci_write_config_dword(dev, 0x2c, 0); - - pci_read_config_word(dev, 0x3e, &val16); - val16 |= ((1 << 5) | (1 << 1)); /* signal master aborts and - * SERR to primary - */ - val16 &= ~(1 << 2); /* ISA disable, so all ISA - * ports forwarded to secondary - */ - pci_write_config_word(dev, 0x3e, val16); - } -} - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0028, ppc7d_fixup_hb8); - -/* This should perhaps be a separate driver as we're actually initializing - * the chip for this board here. It's hardly a fixup... - */ -static void __init ppc7d_fixup_ali1535(struct pci_dev *dev) -{ - pr_debug("PCI: ALI1535 init\n"); - - if (dev->bus->number == 1) { - /* Configure the ISA Port Settings */ - pci_write_config_byte(dev, 0x43, 0x00); - - /* Disable PCI Interrupt polling mode */ - pci_write_config_byte(dev, 0x45, 0x00); - - /* Multifunction pin select INTFJ -> INTF */ - pci_write_config_byte(dev, 0x78, 0x00); - - /* Set PCI INT -> IRQ Routing control in for external - * pins south bridge. - */ - pci_write_config_byte(dev, 0x48, 0x31); /* [7-4] INT B -> IRQ10 - * [3-0] INT A -> IRQ9 - */ - pci_write_config_byte(dev, 0x49, 0x5D); /* [7-4] INT D -> IRQ5 - * [3-0] INT C -> IRQ14 - */ - - /* PPC7D setup */ - /* NEC USB device on IRQ 11 (INTE) - INTF disabled */ - pci_write_config_byte(dev, 0x4A, 0x09); - - /* GPIO on IRQ 6 */ - pci_write_config_byte(dev, 0x76, 0x07); - - /* SIRQ I (COMS 5/6) use IRQ line 15. - * Positive (not subtractive) address decode. - */ - pci_write_config_byte(dev, 0x44, 0x0f); - - /* SIRQ II disabled */ - pci_write_config_byte(dev, 0x75, 0x0); - - /* On board USB and RTC disabled */ - pci_write_config_word(dev, 0x52, (1 << 14)); - pci_write_config_byte(dev, 0x74, 0x00); - - /* On board IDE disabled */ - pci_write_config_byte(dev, 0x58, 0x00); - - /* Decode 32-bit addresses */ - pci_write_config_byte(dev, 0x5b, 0); - - /* Disable docking IO */ - pci_write_config_word(dev, 0x5c, 0x0000); - - /* Disable modem, enable sound */ - pci_write_config_byte(dev, 0x77, (1 << 6)); - - /* Disable hot-docking mode */ - pci_write_config_byte(dev, 0x7d, 0x00); - } -} - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1533, ppc7d_fixup_ali1535); - -static int ppc7d_pci_exclude_device(u8 bus, u8 devfn) -{ - /* Early versions of this board were fitted with IBM ALMA - * PCI-VME bridge chips. The PCI config space of these devices - * was not set up correctly and causes PCI scan problems. - */ - if ((bus == 1) && (PCI_SLOT(devfn) == 4) && ppc7d_has_alma) - return PCIBIOS_DEVICE_NOT_FOUND; - - return mv64x60_pci_exclude_device(bus, devfn); -} - -/* This hook is called when each PCI bus is probed. - */ -static void ppc7d_pci_fixup_bus(struct pci_bus *bus) -{ - pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n", - bus->number, - bus->resource[0] ? bus->resource[0]->start : 0, - bus->resource[0] ? bus->resource[0]->end : 0, - bus->resource[1] ? bus->resource[1]->start : 0, - bus->resource[1] ? bus->resource[1]->end : 0, - bus->resource[2] ? bus->resource[2]->start : 0, - bus->resource[2] ? bus->resource[2]->end : 0, - bus->resource[3] ? bus->resource[3]->start : 0, - bus->resource[3] ? bus->resource[3]->end : 0); - - if ((bus->number == 1) && (bus->resource[2] != NULL)) { - /* Hide PCI window 2 of Bus 1 which is used only to - * map legacy ISA memory space. - */ - bus->resource[2]->start = 0; - bus->resource[2]->end = 0; - bus->resource[2]->flags = 0; - } -} - -/***************************************************************************** - * Board device setup code - *****************************************************************************/ - -void __init ppc7d_setup_peripherals(void) -{ - u32 val32; - - /* Set up windows for boot CS */ - mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, - PPC7D_BOOT_WINDOW_BASE, PPC7D_BOOT_WINDOW_SIZE, - 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); - - /* Boot firmware configures the following DevCS addresses. - * DevCS0 - board control/status - * DevCS1 - test registers - * DevCS2 - AFIX port/address registers (for identifying) - * DevCS3 - FLASH - * - * We don't use DevCS0, DevCS1. - */ - val32 = mv64x60_read(&bh, MV64360_CPU_BAR_ENABLE); - val32 |= ((1 << 4) | (1 << 5)); - mv64x60_write(&bh, MV64360_CPU_BAR_ENABLE, val32); - mv64x60_write(&bh, MV64x60_CPU2DEV_0_BASE, 0); - mv64x60_write(&bh, MV64x60_CPU2DEV_0_SIZE, 0); - mv64x60_write(&bh, MV64x60_CPU2DEV_1_BASE, 0); - mv64x60_write(&bh, MV64x60_CPU2DEV_1_SIZE, 0); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, - PPC7D_AFIX_REG_BASE, PPC7D_AFIX_REG_SIZE, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, - PPC7D_FLASH_BASE, PPC7D_FLASH_SIZE_ACTUAL, 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); - - mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, - PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, - 0); - bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); - - /* Set up Enet->SRAM window */ - mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, - PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, - 0x2); - bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); - - /* Give enet r/w access to memory region */ - val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_0); - val32 |= (0x3 << (4 << 1)); - mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_0, val32); - val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_1); - val32 |= (0x3 << (4 << 1)); - mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_1, val32); - val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_2); - val32 |= (0x3 << (4 << 1)); - mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_2, val32); - - val32 = mv64x60_read(&bh, MV64x60_TIMR_CNTR_0_3_CNTL); - val32 &= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)); - mv64x60_write(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, val32); - - /* Enumerate pci bus. - * - * We scan PCI#0 first (the bus with the HB8 and other - * on-board peripherals). We must configure the 64360 before - * each scan, according to the bus number assignments. Busses - * are assigned incrementally, starting at 0. PCI#0 is - * usually assigned bus#0, the secondary side of the HB8 gets - * bus#1 and PCI#1 (second PMC site) gets bus#2. However, if - * any PMC card has a PCI bridge, these bus assignments will - * change. - */ - - /* Turn off PCI retries */ - val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG); - val32 |= (1 << 17); - mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32); - - /* Scan PCI#0 */ - mv64x60_set_bus(&bh, 0, 0); - bh.hose_a->first_busno = 0; - bh.hose_a->last_busno = 0xff; - bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0); - printk(KERN_INFO "PCI#0: first=%d last=%d\n", - bh.hose_a->first_busno, bh.hose_a->last_busno); - - /* Scan PCI#1 */ - bh.hose_b->first_busno = bh.hose_a->last_busno + 1; - mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno); - bh.hose_b->last_busno = 0xff; - bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, - bh.hose_b->first_busno); - printk(KERN_INFO "PCI#1: first=%d last=%d\n", - bh.hose_b->first_busno, bh.hose_b->last_busno); - - /* Turn on PCI retries */ - val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG); - val32 &= ~(1 << 17); - mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32); - - /* Setup interrupts */ - ppc7d_intr_setup(); -} - -static void __init ppc7d_setup_bridge(void) -{ - struct mv64x60_setup_info si; - int i; - u32 temp; - - mv64360_irq_base = 16; /* first 16 intrs are 2 x 8259's */ - - memset(&si, 0, sizeof(si)); - - si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; - - si.pci_0.enable_bus = 1; - si.pci_0.pci_io.cpu_base = PPC7D_PCI0_IO_START_PROC_ADDR; - si.pci_0.pci_io.pci_base_hi = 0; - si.pci_0.pci_io.pci_base_lo = PPC7D_PCI0_IO_START_PCI_ADDR; - si.pci_0.pci_io.size = PPC7D_PCI0_IO_SIZE; - si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_0.pci_mem[0].cpu_base = PPC7D_PCI0_MEM0_START_PROC_ADDR; - si.pci_0.pci_mem[0].pci_base_hi = PPC7D_PCI0_MEM0_START_PCI_HI_ADDR; - si.pci_0.pci_mem[0].pci_base_lo = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR; - si.pci_0.pci_mem[0].size = PPC7D_PCI0_MEM0_SIZE; - si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_0.pci_mem[1].cpu_base = PPC7D_PCI0_MEM1_START_PROC_ADDR; - si.pci_0.pci_mem[1].pci_base_hi = PPC7D_PCI0_MEM1_START_PCI_HI_ADDR; - si.pci_0.pci_mem[1].pci_base_lo = PPC7D_PCI0_MEM1_START_PCI_LO_ADDR; - si.pci_0.pci_mem[1].size = PPC7D_PCI0_MEM1_SIZE; - si.pci_0.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_0.pci_cmd_bits = 0; - si.pci_0.latency_timer = 0x80; - - si.pci_1.enable_bus = 1; - si.pci_1.pci_io.cpu_base = PPC7D_PCI1_IO_START_PROC_ADDR; - si.pci_1.pci_io.pci_base_hi = 0; - si.pci_1.pci_io.pci_base_lo = PPC7D_PCI1_IO_START_PCI_ADDR; - si.pci_1.pci_io.size = PPC7D_PCI1_IO_SIZE; - si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_mem[0].cpu_base = PPC7D_PCI1_MEM0_START_PROC_ADDR; - si.pci_1.pci_mem[0].pci_base_hi = PPC7D_PCI1_MEM0_START_PCI_HI_ADDR; - si.pci_1.pci_mem[0].pci_base_lo = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR; - si.pci_1.pci_mem[0].size = PPC7D_PCI1_MEM0_SIZE; - si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_mem[1].cpu_base = PPC7D_PCI1_MEM1_START_PROC_ADDR; - si.pci_1.pci_mem[1].pci_base_hi = PPC7D_PCI1_MEM1_START_PCI_HI_ADDR; - si.pci_1.pci_mem[1].pci_base_lo = PPC7D_PCI1_MEM1_START_PCI_LO_ADDR; - si.pci_1.pci_mem[1].size = PPC7D_PCI1_MEM1_SIZE; - si.pci_1.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE; - si.pci_1.pci_cmd_bits = 0; - si.pci_1.latency_timer = 0x80; - - /* Don't clear the SRAM window since we use it for debug */ - si.window_preserve_mask_32_lo = (1 << MV64x60_CPU2SRAM_WIN); - - printk(KERN_INFO "PCI: MV64360 PCI#0 IO at %x, size %x\n", - si.pci_0.pci_io.cpu_base, si.pci_0.pci_io.size); - printk(KERN_INFO "PCI: MV64360 PCI#1 IO at %x, size %x\n", - si.pci_1.pci_io.cpu_base, si.pci_1.pci_io.size); - - for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { -#if defined(CONFIG_NOT_COHERENT_CACHE) - si.cpu_prot_options[i] = 0; - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; - - si.pci_0.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_NONE | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; - - si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_NONE | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; -#else - si.cpu_prot_options[i] = 0; - /* All PPC7D hardware uses B0 or newer MV64360 silicon which - * does not have snoop bugs. - */ - si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; - si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; - si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; - - si.pci_0.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_WB | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; - - si.pci_1.acc_cntl_options[i] = - MV64360_PCI_ACC_CNTL_SNOOP_WB | - MV64360_PCI_ACC_CNTL_SWAP_NONE | - MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | - MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; -#endif - } - - /* Lookup PCI host bridges */ - if (mv64x60_init(&bh, &si)) - printk(KERN_ERR "MV64360 initialization failed.\n"); - - pr_debug("MV64360 regs @ %lx/%p\n", bh.p_base, bh.v_base); - - /* Enable WB Cache coherency on SRAM */ - temp = mv64x60_read(&bh, MV64360_SRAM_CONFIG); - pr_debug("SRAM_CONFIG: %x\n", temp); -#if defined(CONFIG_NOT_COHERENT_CACHE) - mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp & ~0x2); -#else - mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp | 0x2); -#endif - /* If system operates with internal bus arbiter (CPU master - * control bit8) clear AACK Delay bit [25] in CPU - * configuration register. - */ - temp = mv64x60_read(&bh, MV64x60_CPU_MASTER_CNTL); - if (temp & (1 << 8)) { - temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG); - mv64x60_write(&bh, MV64x60_CPU_CONFIG, (temp & ~(1 << 25))); - } - - /* Data and address parity is enabled */ - temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG); - mv64x60_write(&bh, MV64x60_CPU_CONFIG, - (temp | (1 << 26) | (1 << 19))); - - pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */ - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = ppc7d_map_irq; - ppc_md.pci_exclude_device = ppc7d_pci_exclude_device; - - mv64x60_set_bus(&bh, 0, 0); - bh.hose_a->first_busno = 0; - bh.hose_a->last_busno = 0xff; - bh.hose_a->mem_space.start = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR; - bh.hose_a->mem_space.end = - PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + PPC7D_PCI0_MEM0_SIZE; - - /* These will be set later, as a result of PCI0 scan */ - bh.hose_b->first_busno = 0; - bh.hose_b->last_busno = 0xff; - bh.hose_b->mem_space.start = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR; - bh.hose_b->mem_space.end = - PPC7D_PCI1_MEM0_START_PCI_LO_ADDR + PPC7D_PCI1_MEM0_SIZE; - - pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n", - mv64x60_read(&bh, 0x48), mv64x60_read(&bh, 0x50), - mv64x60_read(&bh, 0xf0)); -} - -static void __init ppc7d_setup_arch(void) -{ - int port; - - loops_per_jiffy = 100000000 / HZ; - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_HDA1; -#endif - - if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) || - (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)) - /* 745x is different. We only want to pass along enable. */ - _set_L2CR(L2CR_L2E); - else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR) - /* All modules have 1MB of L2. We also assume that an - * L2 divisor of 3 will work. - */ - _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3 - | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); - - if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR) - /* No L3 cache */ - _set_L3CR(0); - -#ifdef CONFIG_DUMMY_CONSOLE - conswitchp = &dummy_con; -#endif - - /* Lookup PCI host bridges */ - if (ppc_md.progress) - ppc_md.progress("ppc7d_setup_arch: calling setup_bridge", 0); - - ppc7d_setup_bridge(); - ppc7d_setup_peripherals(); - - /* Disable ethernet. It might have been setup by the bootrom */ - for (port = 0; port < 3; port++) - mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port), - 0x0000ff00); - - /* Clear queue pointers to ensure they are all initialized, - * otherwise since queues 1-7 are unused, they have random - * pointers which look strange in register dumps. Don't bother - * with queue 0 since it will be initialized later. - */ - for (port = 0; port < 3; port++) { - mv64x60_write(&bh, - MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port), - 0x00000000); - mv64x60_write(&bh, - MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port), - 0x00000000); - mv64x60_write(&bh, - MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port), - 0x00000000); - mv64x60_write(&bh, - MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port), - 0x00000000); - mv64x60_write(&bh, - MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port), - 0x00000000); - mv64x60_write(&bh, - MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port), - 0x00000000); - mv64x60_write(&bh, - MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port), - 0x00000000); - } - - printk(KERN_INFO "Radstone Technology PPC7D\n"); - if (ppc_md.progress) - ppc_md.progress("ppc7d_setup_arch: exit", 0); - -} - -/* Real Time Clock support. - * PPC7D has a DS1337 accessed by I2C. - */ -static ulong ppc7d_get_rtc_time(void) -{ - struct rtc_time tm; - int result; - - spin_lock(&rtc_lock); - result = ds1337_do_command(0, DS1337_GET_DATE, &tm); - spin_unlock(&rtc_lock); - - if (result == 0) - result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); - - return result; -} - -static int ppc7d_set_rtc_time(unsigned long nowtime) -{ - struct rtc_time tm; - int result; - - spin_lock(&rtc_lock); - to_tm(nowtime, &tm); - result = ds1337_do_command(0, DS1337_SET_DATE, &tm); - spin_unlock(&rtc_lock); - - return result; -} - -/* This kernel command line parameter can be used to have the target - * wait for a JTAG debugger to attach. Of course, a JTAG debugger - * with hardware breakpoint support can have the target stop at any - * location during init, but this is a convenience feature that makes - * it easier in the common case of loading the code using the ppcboot - * bootloader.. - */ -static unsigned long ppc7d_wait_debugger; - -static int __init ppc7d_waitdbg(char *str) -{ - ppc7d_wait_debugger = 1; - return 1; -} - -__setup("waitdbg", ppc7d_waitdbg); - -/* Second phase board init, called after other (architecture common) - * low-level services have been initialized. - */ -static void ppc7d_init2(void) -{ - unsigned long flags; - u32 data; - u8 data8; - - pr_debug("%s: enter\n", __func__); - - /* Wait for debugger? */ - if (ppc7d_wait_debugger) { - printk("Waiting for debugger...\n"); - - while (readl(&ppc7d_wait_debugger)) ; - } - - /* Hook up i8259 interrupt which is connected to GPP28 */ - request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr, - IRQF_DISABLED, "I8259 (GPP28) interrupt", (void *)0); - - /* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */ - spin_lock_irqsave(&mv64x60_lock, flags); - data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2); - data &= ~(0x0000000f << 0); - data |= (0x00000004 << 0); - data &= ~(0x0000000f << 4); - data |= (0x00000004 << 4); - mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data); - spin_unlock_irqrestore(&mv64x60_lock, flags); - - /* All LEDs off */ - data8 = inb(PPC7D_CPLD_LEDS); - data8 &= ~0x08; - data8 |= 0x07; - outb(data8, PPC7D_CPLD_LEDS); - - /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */ - ppc_md.set_rtc_time = ppc7d_set_rtc_time; - ppc_md.get_rtc_time = ppc7d_get_rtc_time; - - pr_debug("%s: exit\n", __func__); -} - -/* Called from machine_init(), early, before any of the __init functions - * have run. We must init software-configurable pins before other functions - * such as interrupt controllers are initialised. - */ -void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - u8 val8; - u8 rev_num; - - /* Map 0xe0000000-0xffffffff early because we need access to SRAM - * and the ISA memory space (for serial port) here. This mapping - * is redone properly in ppc7d_map_io() later. - */ - mtspr(SPRN_DBAT3U, 0xe0003fff); - mtspr(SPRN_DBAT3L, 0xe000002a); - - /* - * Zero SRAM. Note that this generates parity errors on - * internal data path in SRAM if it's first time accessing it - * after reset. - * - * We do this ASAP to avoid parity errors when reading - * uninitialized SRAM. - */ - memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE); - - pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n", - r3, r4, r5, r6, r7); - - parse_bootinfo(find_bootinfo()); - - /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) - * are non-zero, then we should use the board info from the bd_t - * structure and the cmdline pointed to by r6 instead of the - * information from birecs, if any. Otherwise, use the information - * from birecs as discovered by the preceding call to - * parse_bootinfo(). This rule should work with both PPCBoot, which - * uses a bd_t board info structure, and the kernel boot wrapper, - * which uses birecs. - */ - if (r3 && r6) { - bd_t *bp = (bd_t *) __res; - - /* copy board info structure */ - memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t)); - /* copy command line */ - *(char *)(r7 + KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6 + KERNELBASE)); - - printk(KERN_INFO "Board info data:-\n"); - printk(KERN_INFO " Internal freq: %lu MHz, bus freq: %lu MHz\n", - bp->bi_intfreq, bp->bi_busfreq); - printk(KERN_INFO " Memory: %lx, size %lx\n", bp->bi_memstart, - bp->bi_memsize); - printk(KERN_INFO " Console baudrate: %lu\n", bp->bi_baudrate); - printk(KERN_INFO " Ethernet address: " - "%02x:%02x:%02x:%02x:%02x:%02x\n", - bp->bi_enetaddr[0], bp->bi_enetaddr[1], - bp->bi_enetaddr[2], bp->bi_enetaddr[3], - bp->bi_enetaddr[4], bp->bi_enetaddr[5]); - } -#ifdef CONFIG_BLK_DEV_INITRD - /* take care of initrd if we have one */ - if (r4) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end); - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - /* Map in board regs, etc. */ - isa_io_base = 0xe8000000; - isa_mem_base = 0xe8000000; - pci_dram_offset = 0x00000000; - ISA_DMA_THRESHOLD = 0x00ffffff; - DMA_MODE_READ = 0x44; - DMA_MODE_WRITE = 0x48; - - ppc_md.setup_arch = ppc7d_setup_arch; - ppc_md.init = ppc7d_init2; - ppc_md.show_cpuinfo = ppc7d_show_cpuinfo; - /* XXX this is broken... */ - ppc_md.irq_canonicalize = ppc7d_irq_canonicalize; - ppc_md.init_IRQ = ppc7d_init_irq; - ppc_md.get_irq = ppc7d_get_irq; - - ppc_md.restart = ppc7d_restart; - ppc_md.power_off = ppc7d_power_off; - ppc_md.halt = ppc7d_halt; - - ppc_md.find_end_of_memory = ppc7d_find_end_of_memory; - ppc_md.setup_io_mappings = ppc7d_map_io; - - ppc_md.time_init = NULL; - ppc_md.set_rtc_time = NULL; - ppc_md.get_rtc_time = NULL; - ppc_md.calibrate_decr = ppc7d_calibrate_decr; - ppc_md.nvram_read_val = NULL; - ppc_md.nvram_write_val = NULL; - - ppc_md.heartbeat = ppc7d_heartbeat; - ppc_md.heartbeat_reset = HZ; - ppc_md.heartbeat_count = ppc_md.heartbeat_reset; - - ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus; - -#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \ - defined(CONFIG_I2C_MV64XXX) - platform_notify = ppc7d_platform_notify; -#endif - -#ifdef CONFIG_SERIAL_MPSC - /* On PPC7D, we must configure MPSC support via CPLD control - * registers. - */ - outb(PPC7D_CPLD_RTS_COM4_SCLK | - PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS); - outb(PPC7D_CPLD_COMS_COM3_TCLKEN | - PPC7D_CPLD_COMS_COM3_TXEN | - PPC7D_CPLD_COMS_COM4_TCLKEN | - PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS); -#endif /* CONFIG_SERIAL_MPSC */ - -#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG) - ppc7d_early_serial_map(); -#ifdef CONFIG_SERIAL_TEXT_DEBUG -#if defined(CONFIG_SERIAL_MPSC_CONSOLE) - ppc_md.progress = mv64x60_mpsc_progress; -#elif defined(CONFIG_SERIAL_8250) - ppc_md.progress = gen550_progress; -#else -#error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX -#endif /* CONFIG_SERIAL_8250 */ -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ -#endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */ - - /* Enable write access to user flash. This is necessary for - * flash probe. - */ - val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT); - writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED & - PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK), - (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT); - - /* Determine if this board has IBM ALMA VME devices */ - val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION); - rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5; - if (rev_num <= 1) - ppc7d_has_alma = 1; - -#ifdef DEBUG - console_printk[0] = 8; -#endif -} diff --git a/arch/ppc/platforms/radstone_ppc7d.h b/arch/ppc/platforms/radstone_ppc7d.h deleted file mode 100644 index 2bb093a0c03e..000000000000 --- a/arch/ppc/platforms/radstone_ppc7d.h +++ /dev/null @@ -1,433 +0,0 @@ -/* - * Board definitions for the Radstone PPC7D boards. - * - * Author: James Chapman - * - * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il - * Based on code done by - Mark A. Greer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to - * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. - * We'll only use one PCI MEM window on each PCI bus. - * - * This is the CPU physical memory map (windows must be at least 1MB - * and start on a boundary that is a multiple of the window size): - * - * 0xff800000-0xffffffff - Boot window - * 0xff000000-0xff000fff - AFIX registers (DevCS2) - * 0xfef00000-0xfef0ffff - Internal MV64x60 registers - * 0xfef40000-0xfef7ffff - Internal SRAM - * 0xfef00000-0xfef0ffff - MV64360 Registers - * 0x70000000-0x7fffffff - soldered flash (DevCS3) - * 0xe8000000-0xe9ffffff - PCI I/O - * 0x80000000-0xbfffffff - PCI MEM - */ - -#ifndef __PPC_PLATFORMS_PPC7D_H -#define __PPC_PLATFORMS_PPC7D_H - -#include - -/***************************************************************************** - * CPU Physical Memory Map setup. - *****************************************************************************/ - -#define PPC7D_BOOT_WINDOW_BASE 0xff800000 -#define PPC7D_AFIX_REG_BASE 0xff000000 -#define PPC7D_INTERNAL_SRAM_BASE 0xfef40000 -#define PPC7D_FLASH_BASE 0x70000000 - -#define PPC7D_BOOT_WINDOW_SIZE_ACTUAL 0x00800000 /* 8MB */ -#define PPC7D_FLASH_SIZE_ACTUAL 0x10000000 /* 256MB */ - -#define PPC7D_BOOT_WINDOW_SIZE max(MV64360_WINDOW_SIZE_MIN, \ - PPC7D_BOOT_WINDOW_SIZE_ACTUAL) -#define PPC7D_FLASH_SIZE max(MV64360_WINDOW_SIZE_MIN, \ - PPC7D_FLASH_SIZE_ACTUAL) -#define PPC7D_AFIX_REG_SIZE max(MV64360_WINDOW_SIZE_MIN, 0xff) - - -#define PPC7D_PCI0_MEM0_START_PROC_ADDR 0x80000000UL -#define PPC7D_PCI0_MEM0_START_PCI_HI_ADDR 0x00000000UL -#define PPC7D_PCI0_MEM0_START_PCI_LO_ADDR 0x80000000UL -#define PPC7D_PCI0_MEM0_SIZE 0x20000000UL -#define PPC7D_PCI0_MEM1_START_PROC_ADDR 0xe8010000UL -#define PPC7D_PCI0_MEM1_START_PCI_HI_ADDR 0x00000000UL -#define PPC7D_PCI0_MEM1_START_PCI_LO_ADDR 0x00000000UL -#define PPC7D_PCI0_MEM1_SIZE 0x000f0000UL -#define PPC7D_PCI0_IO_START_PROC_ADDR 0xe8000000UL -#define PPC7D_PCI0_IO_START_PCI_ADDR 0x00000000UL -#define PPC7D_PCI0_IO_SIZE 0x00010000UL - -#define PPC7D_PCI1_MEM0_START_PROC_ADDR 0xa0000000UL -#define PPC7D_PCI1_MEM0_START_PCI_HI_ADDR 0x00000000UL -#define PPC7D_PCI1_MEM0_START_PCI_LO_ADDR 0xa0000000UL -#define PPC7D_PCI1_MEM0_SIZE 0x20000000UL -#define PPC7D_PCI1_MEM1_START_PROC_ADDR 0xe9800000UL -#define PPC7D_PCI1_MEM1_START_PCI_HI_ADDR 0x00000000UL -#define PPC7D_PCI1_MEM1_START_PCI_LO_ADDR 0x00000000UL -#define PPC7D_PCI1_MEM1_SIZE 0x00800000UL -#define PPC7D_PCI1_IO_START_PROC_ADDR 0xe9000000UL -#define PPC7D_PCI1_IO_START_PCI_ADDR 0x00000000UL -#define PPC7D_PCI1_IO_SIZE 0x00010000UL - -#define PPC7D_DEFAULT_BAUD 9600 -#define PPC7D_MPSC_CLK_SRC 8 /* TCLK */ -#define PPC7D_MPSC_CLK_FREQ 133333333 /* 133.3333... MHz */ - -#define PPC7D_ETH0_PHY_ADDR 8 -#define PPC7D_ETH1_PHY_ADDR 9 -#define PPC7D_ETH2_PHY_ADDR 0 - -#define PPC7D_ETH_TX_QUEUE_SIZE 400 -#define PPC7D_ETH_RX_QUEUE_SIZE 400 - -#define PPC7D_ETH_PORT_CONFIG_VALUE \ - MV64340_ETH_UNICAST_NORMAL_MODE | \ - MV64340_ETH_DEFAULT_RX_QUEUE_0 | \ - MV64340_ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - MV64340_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - MV64340_ETH_RECEIVE_BC_IF_IP | \ - MV64340_ETH_RECEIVE_BC_IF_ARP | \ - MV64340_ETH_CAPTURE_TCP_FRAMES_DIS | \ - MV64340_ETH_CAPTURE_UDP_FRAMES_DIS | \ - MV64340_ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - MV64340_ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - MV64340_ETH_DEFAULT_RX_BPDU_QUEUE_0 - -#define PPC7D_ETH_PORT_CONFIG_EXTEND_VALUE \ - MV64340_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - MV64340_ETH_PARTITION_DISABLE - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -#define PPC7D_ETH_PORT_SDMA_CONFIG_VALUE \ - MV64340_ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - MV64340_ETH_TX_BURST_SIZE_4_64BIT - -#define PPC7D_ETH_PORT_SERIAL_CONTROL_VALUE \ - MV64340_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - MV64340_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - MV64340_ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - MV64340_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MV64340_ETH_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) | \ - MV64340_ETH_DO_NOT_FORCE_LINK_FAIL | \ - MV64340_ETH_RETRANSMIT_16_ATTEMPTS | \ - MV64340_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - MV64340_ETH_DTE_ADV_0 | \ - MV64340_ETH_DISABLE_AUTO_NEG_BYPASS | \ - MV64340_ETH_AUTO_NEG_NO_CHANGE | \ - MV64340_ETH_MAX_RX_PACKET_9700BYTE | \ - MV64340_ETH_CLR_EXT_LOOPBACK | \ - MV64340_ETH_SET_FULL_DUPLEX_MODE | \ - MV64340_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX - -/***************************************************************************** - * Serial defines. - *****************************************************************************/ - -#define PPC7D_SERIAL_0 0xe80003f8 -#define PPC7D_SERIAL_1 0xe80002f8 - -#define RS_TABLE_SIZE 2 - -/* Rate for the 1.8432 Mhz clock for the onboard serial chip */ -#define UART_CLK 1843200 -#define BASE_BAUD ( UART_CLK / 16 ) - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF) -#endif - -#define STD_SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, PPC7D_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \ - iomem_base: (u8 *)PPC7D_SERIAL_0, \ - io_type: SERIAL_IO_MEM, }, \ - { 0, BASE_BAUD, PPC7D_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \ - iomem_base: (u8 *)PPC7D_SERIAL_1, \ - io_type: SERIAL_IO_MEM }, - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DFNS - -/***************************************************************************** - * CPLD defines. - * - * Register map:- - * - * 0000 to 000F South Bridge DMA 1 Control - * 0020 and 0021 South Bridge Interrupt 1 Control - * 0040 to 0043 South Bridge Counter Control - * 0060 Keyboard - * 0061 South Bridge NMI Status and Control - * 0064 Keyboard - * 0071 and 0072 RTC R/W - * 0078 to 007B South Bridge BIOS Timer - * 0080 to 0090 South Bridge DMA Pages - * 00A0 and 00A1 South Bridge Interrupt 2 Control - * 00C0 to 00DE South Bridge DMA 2 Control - * 02E8 to 02EF COM6 R/W - * 02F8 to 02FF South Bridge COM2 R/W - * 03E8 to 03EF COM5 R/W - * 03F8 to 03FF South Bridge COM1 R/W - * 040A South Bridge DMA Scatter/Gather RO - * 040B DMA 1 Extended Mode WO - * 0410 to 043F South Bridge DMA Scatter/Gather - * 0481 to 048B South Bridge DMA High Pages - * 04D0 and 04D1 South Bridge Edge/Level Control - * 04D6 DMA 2 Extended Mode WO - * 0804 Memory Configuration RO - * 0806 Memory Configuration Extend RO - * 0808 SCSI Activity LED R/W - * 080C Equipment Present 1 RO - * 080E Equipment Present 2 RO - * 0810 Equipment Present 3 RO - * 0812 Equipment Present 4 RO - * 0818 Key Lock RO - * 0820 LEDS R/W - * 0824 COMs R/W - * 0826 RTS R/W - * 0828 Reset R/W - * 082C Watchdog Trig R/W - * 082E Interrupt R/W - * 0830 Interrupt Status RO - * 0832 PCI configuration RO - * 0854 Board Revision RO - * 0858 Extended ID RO - * 0864 ID Link RO - * 0866 Motherboard Type RO - * 0868 FLASH Write control RO - * 086A Software FLASH write protect R/W - * 086E FLASH Control R/W - *****************************************************************************/ - -#define PPC7D_CPLD_MEM_CONFIG 0x0804 -#define PPC7D_CPLD_MEM_CONFIG_EXTEND 0x0806 -#define PPC7D_CPLD_SCSI_ACTIVITY_LED 0x0808 -#define PPC7D_CPLD_EQUIPMENT_PRESENT_1 0x080C -#define PPC7D_CPLD_EQUIPMENT_PRESENT_2 0x080E -#define PPC7D_CPLD_EQUIPMENT_PRESENT_3 0x0810 -#define PPC7D_CPLD_EQUIPMENT_PRESENT_4 0x0812 -#define PPC7D_CPLD_KEY_LOCK 0x0818 -#define PPC7D_CPLD_LEDS 0x0820 -#define PPC7D_CPLD_COMS 0x0824 -#define PPC7D_CPLD_RTS 0x0826 -#define PPC7D_CPLD_RESET 0x0828 -#define PPC7D_CPLD_WATCHDOG_TRIG 0x082C -#define PPC7D_CPLD_INTR 0x082E -#define PPC7D_CPLD_INTR_STATUS 0x0830 -#define PPC7D_CPLD_PCI_CONFIG 0x0832 -#define PPC7D_CPLD_BOARD_REVISION 0x0854 -#define PPC7D_CPLD_EXTENDED_ID 0x0858 -#define PPC7D_CPLD_ID_LINK 0x0864 -#define PPC7D_CPLD_MOTHERBOARD_TYPE 0x0866 -#define PPC7D_CPLD_FLASH_WRITE_CNTL 0x0868 -#define PPC7D_CPLD_SW_FLASH_WRITE_PROTECT 0x086A -#define PPC7D_CPLD_FLASH_CNTL 0x086E - -/* MEMORY_CONFIG_EXTEND */ -#define PPC7D_CPLD_SDRAM_BANK_NUM_MASK 0x02 -#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0 -#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0 -#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40 -#define PPC7D_CPLD_SDRAM_BANK_SIZE_512M 0x80 -#define PPC7D_CPLD_SDRAM_BANK_SIZE_1G 0xc0 -#define PPC7D_CPLD_FLASH_DEV_SIZE_MASK 0x03 -#define PPC7D_CPLD_FLASH_BANK_NUM_MASK 0x0c -#define PPC7D_CPLD_FLASH_DEV_SIZE_64M 0 -#define PPC7D_CPLD_FLASH_DEV_SIZE_32M 1 -#define PPC7D_CPLD_FLASH_DEV_SIZE_16M 3 -#define PPC7D_CPLD_FLASH_BANK_NUM_4 0x00 -#define PPC7D_CPLD_FLASH_BANK_NUM_3 0x04 -#define PPC7D_CPLD_FLASH_BANK_NUM_2 0x08 -#define PPC7D_CPLD_FLASH_BANK_NUM_1 0x0c - -/* SCSI_LED */ -#define PPC7D_CPLD_SCSI_ACTIVITY_LED_OFF 0 -#define PPC7D_CPLD_SCSI_ACTIVITY_LED_ON 1 - -/* EQUIPMENT_PRESENT_1 */ -#define PPC7D_CPLD_EQPT_PRES_1_FITTED 0 -#define PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK (0x80 >> 2) -#define PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK (0x80 >> 3) -#define PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK (0x80 >> 4) - -/* EQUIPMENT_PRESENT_2 */ -#define PPC7D_CPLD_EQPT_PRES_2_FITTED !0 -#define PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK (0x80 >> 0) -#define PPC7D_CPLD_EQPT_PRES_2_COM36_MASK (0x80 >> 2) -#define PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK (0x80 >> 3) -#define PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK (0x80 >> 4) - -/* EQUIPMENT_PRESENT_3 */ -#define PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK (0x80 >> 3) -#define PPC7D_CPLD_EQPT_PRES_3_PMC2_5V (0 >> 3) -#define PPC7D_CPLD_EQPT_PRES_3_PMC2_3V (0x80 >> 3) -#define PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK (0x80 >> 4) -#define PPC7D_CPLD_EQPT_PRES_3_PMC1_5V (0 >> 4) -#define PPC7D_CPLD_EQPT_PRES_3_PMC1_3V (0x80 >> 4) -#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK (0x80 >> 5) -#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_INTER (0 >> 5) -#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_VME (0x80 >> 5) - -/* EQUIPMENT_PRESENT_4 */ -#define PPC7D_CPLD_EQPT_PRES_4_LPT_MASK (0x80 >> 2) -#define PPC7D_CPLD_EQPT_PRES_4_LPT_FITTED (0x80 >> 2) -#define PPC7D_CPLD_EQPT_PRES_4_PS2_USB2_MASK (0xc0 >> 6) -#define PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED (0x40 >> 6) -#define PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED (0x80 >> 6) - -/* CPLD_LEDS */ -#define PPC7D_CPLD_LEDS_ON (!0) -#define PPC7D_CPLD_LEDS_OFF (0) -#define PPC7D_CPLD_LEDS_NVRAM_PAGE_MASK (0xc0 >> 2) -#define PPC7D_CPLD_LEDS_DS201_MASK (0x80 >> 4) -#define PPC7D_CPLD_LEDS_DS219_MASK (0x80 >> 5) -#define PPC7D_CPLD_LEDS_DS220_MASK (0x80 >> 6) -#define PPC7D_CPLD_LEDS_DS221_MASK (0x80 >> 7) - -/* CPLD_COMS */ -#define PPC7D_CPLD_COMS_COM3_TCLKEN (0x80 >> 0) -#define PPC7D_CPLD_COMS_COM3_RTCLKEN (0x80 >> 1) -#define PPC7D_CPLD_COMS_COM3_MODE_MASK (0x80 >> 2) -#define PPC7D_CPLD_COMS_COM3_MODE_RS232 (0) -#define PPC7D_CPLD_COMS_COM3_MODE_RS422 (0x80 >> 2) -#define PPC7D_CPLD_COMS_COM3_TXEN (0x80 >> 3) -#define PPC7D_CPLD_COMS_COM4_TCLKEN (0x80 >> 4) -#define PPC7D_CPLD_COMS_COM4_RTCLKEN (0x80 >> 5) -#define PPC7D_CPLD_COMS_COM4_MODE_MASK (0x80 >> 6) -#define PPC7D_CPLD_COMS_COM4_MODE_RS232 (0) -#define PPC7D_CPLD_COMS_COM4_MODE_RS422 (0x80 >> 6) -#define PPC7D_CPLD_COMS_COM4_TXEN (0x80 >> 7) - -/* CPLD_RTS */ -#define PPC7D_CPLD_RTS_COM36_LOOPBACK (0x80 >> 0) -#define PPC7D_CPLD_RTS_COM4_SCLK (0x80 >> 1) -#define PPC7D_CPLD_RTS_COM3_TXFUNC_MASK (0xc0 >> 2) -#define PPC7D_CPLD_RTS_COM3_TXFUNC_DISABLED (0 >> 2) -#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED (0x80 >> 2) -#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3 (0xc0 >> 2) -#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3S (0xc0 >> 2) -#define PPC7D_CPLD_RTS_COM56_MODE_MASK (0x80 >> 4) -#define PPC7D_CPLD_RTS_COM56_MODE_RS232 (0) -#define PPC7D_CPLD_RTS_COM56_MODE_RS422 (0x80 >> 4) -#define PPC7D_CPLD_RTS_COM56_ENABLE_MASK (0x80 >> 5) -#define PPC7D_CPLD_RTS_COM56_DISABLED (0) -#define PPC7D_CPLD_RTS_COM56_ENABLED (0x80 >> 5) -#define PPC7D_CPLD_RTS_COM4_TXFUNC_MASK (0xc0 >> 6) -#define PPC7D_CPLD_RTS_COM4_TXFUNC_DISABLED (0 >> 6) -#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED (0x80 >> 6) -#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3 (0x40 >> 6) -#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3S (0x40 >> 6) - -/* WATCHDOG_TRIG */ -#define PPC7D_CPLD_WDOG_CAUSE_MASK (0x80 >> 0) -#define PPC7D_CPLD_WDOG_CAUSE_NORMAL_RESET (0 >> 0) -#define PPC7D_CPLD_WDOG_CAUSE_WATCHDOG (0x80 >> 0) -#define PPC7D_CPLD_WDOG_ENABLE_MASK (0x80 >> 6) -#define PPC7D_CPLD_WDOG_ENABLE_OFF (0 >> 6) -#define PPC7D_CPLD_WDOG_ENABLE_ON (0x80 >> 6) -#define PPC7D_CPLD_WDOG_RESETSW_MASK (0x80 >> 7) -#define PPC7D_CPLD_WDOG_RESETSW_OFF (0 >> 7) -#define PPC7D_CPLD_WDOG_RESETSW_ON (0x80 >> 7) - -/* Interrupt mask and status bits */ -#define PPC7D_CPLD_INTR_TEMP_MASK (0x80 >> 0) -#define PPC7D_CPLD_INTR_HB8_MASK (0x80 >> 1) -#define PPC7D_CPLD_INTR_PHY1_MASK (0x80 >> 2) -#define PPC7D_CPLD_INTR_PHY0_MASK (0x80 >> 3) -#define PPC7D_CPLD_INTR_ISANMI_MASK (0x80 >> 5) -#define PPC7D_CPLD_INTR_CRITTEMP_MASK (0x80 >> 6) - -/* CPLD_INTR */ -#define PPC7D_CPLD_INTR_ENABLE_OFF (0) -#define PPC7D_CPLD_INTR_ENABLE_ON (!0) - -/* CPLD_INTR_STATUS */ -#define PPC7D_CPLD_INTR_STATUS_OFF (0) -#define PPC7D_CPLD_INTR_STATUS_ON (!0) - -/* CPLD_PCI_CONFIG */ -#define PPC7D_CPLD_PCI_CONFIG_PCI0_MASK 0x70 -#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI33 0x00 -#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI66 0x10 -#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX33 0x40 -#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX66 0x50 -#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX100 0x60 -#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX133 0x70 -#define PPC7D_CPLD_PCI_CONFIG_PCI1_MASK 0x07 -#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI33 0x00 -#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI66 0x01 -#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX33 0x04 -#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX66 0x05 -#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX100 0x06 -#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX133 0x07 - -/* CPLD_BOARD_REVISION */ -#define PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK 0xe0 -#define PPC7D_CPLD_BOARD_REVISION_LETTER_MASK 0x1f - -/* CPLD_EXTENDED_ID */ -#define PPC7D_CPLD_EXTENDED_ID_PPC7D 0x18 - -/* CPLD_ID_LINK */ -#define PPC7D_CPLD_ID_LINK_VME64_GAP_MASK (0x80 >> 2) -#define PPC7D_CPLD_ID_LINK_VME64_GA4_MASK (0x80 >> 3) -#define PPC7D_CPLD_ID_LINK_E13_MASK (0x80 >> 4) -#define PPC7D_CPLD_ID_LINK_E12_MASK (0x80 >> 5) -#define PPC7D_CPLD_ID_LINK_E7_MASK (0x80 >> 6) -#define PPC7D_CPLD_ID_LINK_E6_MASK (0x80 >> 7) - -/* CPLD_MOTHERBOARD_TYPE */ -#define PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK (0x80 >> 0) -#define PPC7D_CPLD_MB_TYPE_ECC_ENABLED (0x80 >> 0) -#define PPC7D_CPLD_MB_TYPE_ECC_DISABLED (0 >> 0) -#define PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK (0x80 >> 3) -#define PPC7D_CPLD_MB_TYPE_PLL_MASK 0x0c -#define PPC7D_CPLD_MB_TYPE_PLL_133 0x00 -#define PPC7D_CPLD_MB_TYPE_PLL_100 0x08 -#define PPC7D_CPLD_MB_TYPE_PLL_64 0x04 -#define PPC7D_CPLD_MB_TYPE_HW_ID_MASK 0x03 - -/* CPLD_FLASH_WRITE_CNTL */ -#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK (0x80 >> 0) -#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_FITTED (0x80 >> 0) -#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK (0x80 >> 2) -#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_FITTED (0x80 >> 2) -#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK (0x80 >> 3) -#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_FITTED (0x80 >> 3) -#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK (0x80 >> 5) -#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_ENABLED (0x80 >> 5) -#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK (0x80 >> 6) -#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_ENABLED (0x80 >> 6) -#define PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK (0x80 >> 7) -#define PPD7D_CPLD_FLASH_CNTL_USER_WR_ENABLED (0x80 >> 7) - -/* CPLD_SW_FLASH_WRITE_PROTECT */ -#define PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED (!0) -#define PPC7D_CPLD_SW_FLASH_WRPROT_DISABLED (0) -#define PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK (0x80 >> 6) -#define PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK (0x80 >> 7) - -/* CPLD_FLASH_WRITE_CNTL */ -#define PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK (0x80 >> 0) -#define PPC7D_CPLD_FLASH_CNTL_NVRAM_DISABLED (0 >> 0) -#define PPC7D_CPLD_FLASH_CNTL_NVRAM_ENABLED (0x80 >> 0) -#define PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK (0x80 >> 1) -#define PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK (0x80 >> 2) -#define PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK (0x80 >> 3) - - -#endif /* __PPC_PLATFORMS_PPC7D_H */ diff --git a/arch/ppc/platforms/residual.c b/arch/ppc/platforms/residual.c deleted file mode 100644 index d687b0f8763b..000000000000 --- a/arch/ppc/platforms/residual.c +++ /dev/null @@ -1,1034 +0,0 @@ -/* - * Code to deal with the PReP residual data. - * - * Written by: Cort Dougan (cort@cs.nmt.edu) - * Improved _greatly_ and rewritten by Gabriel Paubert (paubert@iram.es) - * - * This file is based on the following documentation: - * - * IBM Power Personal Systems Architecture - * Residual Data - * Document Number: PPS-AR-FW0001 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - - -unsigned char __res[sizeof(RESIDUAL)] = {0,}; -RESIDUAL *res = (RESIDUAL *)&__res; - -char * PnP_BASE_TYPES[] __initdata = { - "Reserved", - "MassStorageDevice", - "NetworkInterfaceController", - "DisplayController", - "MultimediaController", - "MemoryController", - "BridgeController", - "CommunicationsDevice", - "SystemPeripheral", - "InputDevice", - "ServiceProcessor" - }; - -/* Device Sub Type Codes */ - -unsigned char * PnP_SUB_TYPES[] __initdata = { - "\001\000SCSIController", - "\001\001IDEController", - "\001\002FloppyController", - "\001\003IPIController", - "\001\200OtherMassStorageController", - "\002\000EthernetController", - "\002\001TokenRingController", - "\002\002FDDIController", - "\002\0x80OtherNetworkController", - "\003\000VGAController", - "\003\001SVGAController", - "\003\002XGAController", - "\003\200OtherDisplayController", - "\004\000VideoController", - "\004\001AudioController", - "\004\200OtherMultimediaController", - "\005\000RAM", - "\005\001FLASH", - "\005\200OtherMemoryDevice", - "\006\000HostProcessorBridge", - "\006\001ISABridge", - "\006\002EISABridge", - "\006\003MicroChannelBridge", - "\006\004PCIBridge", - "\006\005PCMCIABridge", - "\006\006VMEBridge", - "\006\200OtherBridgeDevice", - "\007\000RS232Device", - "\007\001ATCompatibleParallelPort", - "\007\200OtherCommunicationsDevice", - "\010\000ProgrammableInterruptController", - "\010\001DMAController", - "\010\002SystemTimer", - "\010\003RealTimeClock", - "\010\004L2Cache", - "\010\005NVRAM", - "\010\006PowerManagement", - "\010\007CMOS", - "\010\010OperatorPanel", - "\010\011ServiceProcessorClass1", - "\010\012ServiceProcessorClass2", - "\010\013ServiceProcessorClass3", - "\010\014GraphicAssist", - "\010\017SystemPlanar", - "\010\200OtherSystemPeripheral", - "\011\000KeyboardController", - "\011\001Digitizer", - "\011\002MouseController", - "\011\003TabletController", - "\011\0x80OtherInputController", - "\012\000GeneralMemoryController", - NULL -}; - -/* Device Interface Type Codes */ - -unsigned char * PnP_INTERFACES[] __initdata = { - "\000\000\000General", - "\001\000\000GeneralSCSI", - "\001\001\000GeneralIDE", - "\001\001\001ATACompatible", - - "\001\002\000GeneralFloppy", - "\001\002\001Compatible765", - "\001\002\002NS398_Floppy", /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - "\001\002\003NS26E_Floppy", /* Ports 26E and 26F */ - "\001\002\004NS15C_Floppy", /* Ports 15C and 15D */ - "\001\002\005NS2E_Floppy", /* Ports 2E and 2F */ - "\001\002\006CHRP_Floppy", /* CHRP Floppy in PR*P system */ - - "\001\003\000GeneralIPI", - - "\002\000\000GeneralEther", - "\002\001\000GeneralToken", - "\002\002\000GeneralFDDI", - - "\003\000\000GeneralVGA", - "\003\001\000GeneralSVGA", - "\003\002\000GeneralXGA", - - "\004\000\000GeneralVideo", - "\004\001\000GeneralAudio", - "\004\001\001CS4232Audio", /* CS 4232 Plug 'n Play Configured */ - - "\005\000\000GeneralRAM", - /* This one is obviously wrong ! */ - "\005\000\000PCIMemoryController", /* PCI Config Method */ - "\005\000\001RS6KMemoryController", /* RS6K Config Method */ - "\005\001\000GeneralFLASH", - - "\006\000\000GeneralHostBridge", - "\006\001\000GeneralISABridge", - "\006\002\000GeneralEISABridge", - "\006\003\000GeneralMCABridge", - /* GeneralPCIBridge = 0, */ - "\006\004\000PCIBridgeDirect", - "\006\004\001PCIBridgeIndirect", - "\006\004\002PCIBridgeRS6K", - "\006\005\000GeneralPCMCIABridge", - "\006\006\000GeneralVMEBridge", - - "\007\000\000GeneralRS232", - "\007\000\001COMx", - "\007\000\002Compatible16450", - "\007\000\003Compatible16550", - "\007\000\004NS398SerPort", /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - "\007\000\005NS26ESerPort", /* Ports 26E and 26F */ - "\007\000\006NS15CSerPort", /* Ports 15C and 15D */ - "\007\000\007NS2ESerPort", /* Ports 2E and 2F */ - - "\007\001\000GeneralParPort", - "\007\001\001LPTx", - "\007\001\002NS398ParPort", /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - "\007\001\003NS26EParPort", /* Ports 26E and 26F */ - "\007\001\004NS15CParPort", /* Ports 15C and 15D */ - "\007\001\005NS2EParPort", /* Ports 2E and 2F */ - - "\010\000\000GeneralPIC", - "\010\000\001ISA_PIC", - "\010\000\002EISA_PIC", - "\010\000\003MPIC", - "\010\000\004RS6K_PIC", - - "\010\001\000GeneralDMA", - "\010\001\001ISA_DMA", - "\010\001\002EISA_DMA", - - "\010\002\000GeneralTimer", - "\010\002\001ISA_Timer", - "\010\002\002EISA_Timer", - "\010\003\000GeneralRTC", - "\010\003\001ISA_RTC", - - "\010\004\001StoreThruOnly", - "\010\004\002StoreInEnabled", - "\010\004\003RS6KL2Cache", - - "\010\005\000IndirectNVRAM", /* Indirectly addressed */ - "\010\005\001DirectNVRAM", /* Memory Mapped */ - "\010\005\002IndirectNVRAM24", /* Indirectly addressed - 24 bit */ - - "\010\006\000GeneralPowerManagement", - "\010\006\001EPOWPowerManagement", - "\010\006\002PowerControl", // d1378 - - "\010\007\000GeneralCMOS", - - "\010\010\000GeneralOPPanel", - "\010\010\001HarddiskLight", - "\010\010\002CDROMLight", - "\010\010\003PowerLight", - "\010\010\004KeyLock", - "\010\010\005ANDisplay", /* AlphaNumeric Display */ - "\010\010\006SystemStatusLED", /* 3 digit 7 segment LED */ - "\010\010\007CHRP_SystemStatusLED", /* CHRP LEDs in PR*P system */ - - "\010\011\000GeneralServiceProcessor", - "\010\012\000GeneralServiceProcessor", - "\010\013\000GeneralServiceProcessor", - - "\010\014\001TransferData", - "\010\014\002IGMC32", - "\010\014\003IGMC64", - - "\010\017\000GeneralSystemPlanar", /* 10/5/95 */ - NULL - }; - -static const unsigned char __init *PnP_SUB_TYPE_STR(unsigned char BaseType, - unsigned char SubType) { - unsigned char ** s=PnP_SUB_TYPES; - while (*s && !((*s)[0]==BaseType - && (*s)[1]==SubType)) s++; - if (*s) return *s+2; - else return("Unknown !"); -}; - -static const unsigned char __init *PnP_INTERFACE_STR(unsigned char BaseType, - unsigned char SubType, - unsigned char Interface) { - unsigned char ** s=PnP_INTERFACES; - while (*s && !((*s)[0]==BaseType - && (*s)[1]==SubType - && (*s)[2]==Interface)) s++; - if (*s) return *s+3; - else return NULL; -}; - -static void __init printsmallvendor(PnP_TAG_PACKET *pkt, int size) { - int i, c; - char decomp[4]; -#define p pkt->S14_Pack.S14_Data.S14_PPCPack - switch(p.Type) { - case 1: - /* Decompress first 3 chars */ - c = *(unsigned short *)p.PPCData; - decomp[0]='A'-1+((c>>10)&0x1F); - decomp[1]='A'-1+((c>>5)&0x1F); - decomp[2]='A'-1+(c&0x1F); - decomp[3]=0; - printk(" Chip identification: %s%4.4X\n", - decomp, ld_le16((unsigned short *)(p.PPCData+2))); - break; - default: - printk(" Small vendor item type 0x%2.2x, data (hex): ", - p.Type); - for(i=0; iS1_Pack.Tag)) { - case PnPVersion: - printk(" PnPversion 0x%x.%x\n", - pkt->S1_Pack.Version[0], /* How to interpret version ? */ - pkt->S1_Pack.Version[1]); - break; -// case Logicaldevice: - break; -// case CompatibleDevice: - break; - case IRQFormat: -#define p pkt->S4_Pack - printk(" IRQ Mask 0x%4.4x, %s %s sensitive\n", - ld_le16((unsigned short *)p.IRQMask), - intlevel[(size>3) ? !(p.IRQInfo&0x05) : 0], - intsense[(size>3) ? !(p.IRQInfo&0x03) : 0]); -#undef p - break; - case DMAFormat: -#define p pkt->S5_Pack - printk(" DMA channel mask 0x%2.2x, info 0x%2.2x\n", - p.DMAMask, p.DMAInfo); -#undef p - break; - case StartDepFunc: - printk("Start dependent function:\n"); - break; - case EndDepFunc: - printk("End dependent function\n"); - break; - case IOPort: -#define p pkt->S8_Pack - printk(" Variable (%d decoded bits) I/O port\n" - " from 0x%4.4x to 0x%4.4x, alignment %d, %d ports\n", - p.IOInfo&ISAAddr16bit?16:10, - ld_le16((unsigned short *)p.RangeMin), - ld_le16((unsigned short *)p.RangeMax), - p.IOAlign, p.IONum); -#undef p - break; - case FixedIOPort: -#define p pkt->S9_Pack - printk(" Fixed (10 decoded bits) I/O port from %3.3x to %3.3x\n", - (p.Range[1]<<8)|p.Range[0], - ((p.Range[1]<<8)|p.Range[0])+p.IONum-1); -#undef p - break; - case Res1: - case Res2: - case Res3: - printk(" Undefined packet type %d!\n", - tag_small_item_name(pkt->S1_Pack.Tag)); - break; - case SmallVendorItem: - printsmallvendor(pkt,size); - break; - default: - printk(" Type 0x2.2x%d, size=%d\n", - pkt->S1_Pack.Tag, size); - break; - } -} - -static void __init printlargevendor(PnP_TAG_PACKET * pkt, int size) { - static const unsigned char * addrtype[] = {"I/O", "Memory", "System"}; - static const unsigned char * inttype[] = {"8259", "MPIC", "RS6k BUID %d"}; - static const unsigned char * convtype[] = {"Bus Memory", "Bus I/O", "DMA"}; - static const unsigned char * transtype[] = {"direct", "mapped", "direct-store segment"}; - static const unsigned char * L2type[] = {"WriteThru", "CopyBack"}; - static const unsigned char * L2assoc[] = {"DirectMapped", "2-way set"}; - - int i; - char tmpstr[30], *t; -#define p pkt->L4_Pack.L4_Data.L4_PPCPack - switch(p.Type) { - case 2: - printk(" %d K %s %s L2 cache, %d/%d bytes line/sector size\n", - ld_le32((unsigned int *)p.PPCData), - L2type[p.PPCData[10]-1], - L2assoc[p.PPCData[4]-1], - ld_le16((unsigned short *)p.PPCData+3), - ld_le16((unsigned short *)p.PPCData+4)); - break; - case 3: - printk(" PCI Bridge parameters\n" - " ConfigBaseAddress %0x\n" - " ConfigBaseData %0x\n" - " Bus number %d\n", - ld_le32((unsigned int *)p.PPCData), - ld_le32((unsigned int *)(p.PPCData+8)), - p.PPCData[16]); - for(i=20; iS1_Pack.Tag)) { - case LargeVendorItem: - printlargevendor(pkt, size); - break; - default: - printk(" Type 0x2.2x%d, size=%d\n", - pkt->S1_Pack.Tag, size); - break; - } -} - -static void __init printpackets(PnP_TAG_PACKET * pkt, const char * cat) -{ - if (pkt->S1_Pack.Tag== END_TAG) { - printk(" No packets describing %s resources.\n", cat); - return; - } - printk( " Packets describing %s resources:\n",cat); - do { - int size; - if (tag_type(pkt->S1_Pack.Tag)) { - size= 3 + - pkt->L1_Pack.Count0 + - pkt->L1_Pack.Count1*256; - printlargepacket(pkt, size); - } else { - size=tag_small_count(pkt->S1_Pack.Tag)+1; - printsmallpacket(pkt, size); - } - pkt = (PnP_TAG_PACKET *)((unsigned char *) pkt + size); - } while (pkt->S1_Pack.Tag != END_TAG); -} - -void __init print_residual_device_info(void) -{ - int i; - PPC_DEVICE *dev; -#define did dev->DeviceId - - /* make sure we have residual data first */ - if (!have_residual_data) - return; - - printk("Residual: %ld devices\n", res->ActualNumDevices); - for ( i = 0; - i < res->ActualNumDevices ; - i++) - { - char decomp[4], sn[20]; - const char * s; - dev = &res->Devices[i]; - s = PnP_INTERFACE_STR(did.BaseType, did.SubType, - did.Interface); - if(!s) { - sprintf(sn, "interface %d", did.Interface); - s=sn; - } - if ( did.BusId & PCIDEVICE ) - printk("PCI Device, Bus %d, DevFunc 0x%x:", - dev->BusAccess.PCIAccess.BusNumber, - dev->BusAccess.PCIAccess.DevFuncNumber); - if ( did.BusId & PNPISADEVICE ) printk("PNPISA Device:"); - if ( did.BusId & ISADEVICE ) - printk("ISA Device, Slot %d, LogicalDev %d:", - dev->BusAccess.ISAAccess.SlotNumber, - dev->BusAccess.ISAAccess.LogicalDevNumber); - if ( did.BusId & EISADEVICE ) printk("EISA Device:"); - if ( did.BusId & PROCESSORDEVICE ) - printk("ProcBus Device, Bus %d, BUID %d: ", - dev->BusAccess.ProcBusAccess.BusNumber, - dev->BusAccess.ProcBusAccess.BUID); - if ( did.BusId & PCMCIADEVICE ) printk("PCMCIA "); - if ( did.BusId & VMEDEVICE ) printk("VME "); - if ( did.BusId & MCADEVICE ) printk("MCA "); - if ( did.BusId & MXDEVICE ) printk("MX "); - /* Decompress first 3 chars */ - decomp[0]='A'-1+((did.DevId>>26)&0x1F); - decomp[1]='A'-1+((did.DevId>>21)&0x1F); - decomp[2]='A'-1+((did.DevId>>16)&0x1F); - decomp[3]=0; - printk(" %s%4.4lX, %s, %s, %s\n", - decomp, did.DevId&0xffff, - PnP_BASE_TYPES[did.BaseType], - PnP_SUB_TYPE_STR(did.BaseType,did.SubType), - s); - if ( dev->AllocatedOffset ) - printpackets( (union _PnP_TAG_PACKET *) - &res->DevicePnPHeap[dev->AllocatedOffset], - "allocated"); - if ( dev->PossibleOffset ) - printpackets( (union _PnP_TAG_PACKET *) - &res->DevicePnPHeap[dev->PossibleOffset], - "possible"); - if ( dev->CompatibleOffset ) - printpackets( (union _PnP_TAG_PACKET *) - &res->DevicePnPHeap[dev->CompatibleOffset], - "compatible"); - } -} - - -#if 0 -static void __init printVPD(void) { -#define vpd res->VitalProductData - int ps=vpd.PageSize, i, j; - static const char* Usage[]={ - "FirmwareStack", "FirmwareHeap", "FirmwareCode", "BootImage", - "Free", "Unpopulated", "ISAAddr", "PCIConfig", - "IOMemory", "SystemIO", "SystemRegs", "PCIAddr", - "UnPopSystemRom", "SystemROM", "ResumeBlock", "Other" - }; - static const unsigned char *FWMan[]={ - "IBM", "Motorola", "FirmWorks", "Bull" - }; - static const unsigned char *FWFlags[]={ - "Conventional", "OpenFirmware", "Diagnostics", "LowDebug", - "MultiBoot", "LowClient", "Hex41", "FAT", - "ISO9660", "SCSI_ID_Override", "Tape_Boot", "FW_Boot_Path" - }; - static const unsigned char *ESM[]={ - "Port92", "PCIConfigA8", "FF001030", "????????" - }; - static const unsigned char *SIOM[]={ - "Port850", "????????", "PCIConfigA8", "????????" - }; - - printk("Model: %s\n",vpd.PrintableModel); - printk("Serial: %s\n", vpd.Serial); - printk("FirmwareSupplier: %s\n", FWMan[vpd.FirmwareSupplier]); - printk("FirmwareFlags:"); - for(j=0; j<12; j++) { - if (vpd.FirmwareSupports & (1<2 ? 2 : vpd.EndianSwitchMethod]); - printk("SpreadIOMethod: %s\n", - SIOM[vpd.SpreadIOMethod>3 ? 3 : vpd.SpreadIOMethod]); - printk("Processor/Bus frequencies (Hz): %ld/%ld\n", - vpd.ProcessorHz, vpd.ProcessorBusHz); - printk("Time Base Divisor: %ld\n", vpd.TimeBaseDivisor); - printk("WordWidth, PageSize: %ld, %d\n", vpd.WordWidth, ps); - printk("Cache sector size, Lock granularity: %ld, %ld\n", - vpd.CoherenceBlockSize, vpd.GranuleSize); - for (i=0; iActualNumMemSegs; i++) { - int mask=res->Segs[i].Usage, first, j; - printk("%8.8lx-%8.8lx ", - res->Segs[i].BasePage*ps, - (res->Segs[i].PageCount+res->Segs[i].BasePage)*ps-1); - for(j=15, first=1; j>=0; j--) { - if (mask&(1<DeviceId - - /* make sure we have residual data first */ - if (!have_residual_data) - return; - printk("Residual: %ld devices\n", res->ActualNumDevices); - for ( i = 0; - i < res->ActualNumDevices ; - i++) - { - dev = &res->Devices[i]; - /* - * pci devices - */ - if ( did.BusId & PCIDEVICE ) - { - printk("PCI Device:"); - /* unknown vendor */ - if ( !strncmp( "Unknown", pci_strvendor(did.DevId>>16), 7) ) - printk(" id %08lx types %d/%d", did.DevId, - did.BaseType, did.SubType); - /* known vendor */ - else - printk(" %s %s", - pci_strvendor(did.DevId>>16), - pci_strdev(did.DevId>>16, - did.DevId&0xffff) - ); - - if ( did.BusId & PNPISADEVICE ) - { - printk(" pnp:"); - /* get pnp info on the device */ - pkt = (union _PnP_TAG_PACKET *) - &res->DevicePnPHeap[dev->AllocatedOffset]; - for (; pkt->S1_Pack.Tag != DF_END_TAG; - pkt++ ) - { - if ( (pkt->S1_Pack.Tag == S4_Packet) || - (pkt->S1_Pack.Tag == S4_Packet_flags) ) - printk(" irq %02x%02x", - pkt->S4_Pack.IRQMask[0], - pkt->S4_Pack.IRQMask[1]); - } - } - printk("\n"); - continue; - } - /* - * isa devices - */ - if ( did.BusId & ISADEVICE ) - { - printk("ISA Device: basetype: %d subtype: %d", - did.BaseType, did.SubType); - printk("\n"); - continue; - } - /* - * eisa devices - */ - if ( did.BusId & EISADEVICE ) - { - printk("EISA Device: basetype: %d subtype: %d", - did.BaseType, did.SubType); - printk("\n"); - continue; - } - /* - * proc bus devices - */ - if ( did.BusId & PROCESSORDEVICE ) - { - printk("ProcBus Device: basetype: %d subtype: %d", - did.BaseType, did.SubType); - printk("\n"); - continue; - } - /* - * pcmcia devices - */ - if ( did.BusId & PCMCIADEVICE ) - { - printk("PCMCIA Device: basetype: %d subtype: %d", - did.BaseType, did.SubType); - printk("\n"); - continue; - } - printk("Unknown bus access device: busid %lx\n", - did.BusId); - } -} -#endif - -/* Returns the device index in the residual data, - any of the search items may be set as -1 for wildcard, - DevID number field (second halfword) is big endian ! - - Examples: - - search for the Interrupt controller (8259 type), 2 methods: - 1) i8259 = residual_find_device(~0, - NULL, - SystemPeripheral, - ProgrammableInterruptController, - ISA_PIC, - 0); - 2) i8259 = residual_find_device(~0, "PNP0000", -1, -1, -1, 0) - - - search for the first two serial devices, whatever their type) - iserial1 = residual_find_device(~0,NULL, - CommunicationsDevice, - RS232Device, - -1, 0) - iserial2 = residual_find_device(~0,NULL, - CommunicationsDevice, - RS232Device, - -1, 1) - - but search for typical COM1 and COM2 is not easy due to the - fact that the interface may be anything and the name "PNP0500" or - "PNP0501". Quite bad. - -*/ - -/* devid are easier to uncompress than to compress, so to minimize bloat -in this rarely used area we unencode and compare */ - -/* in residual data number is big endian in the device table and -little endian in the heap, so we use two parameters to avoid writing -two very similar functions */ - -static int __init same_DevID(unsigned short vendor, - unsigned short Number, - char * str) -{ - static unsigned const char hexdigit[]="0123456789ABCDEF"; - if (strlen(str)!=7) return 0; - if ( ( ((vendor>>10)&0x1f)+'A'-1 == str[0]) && - ( ((vendor>>5)&0x1f)+'A'-1 == str[1]) && - ( (vendor&0x1f)+'A'-1 == str[2]) && - (hexdigit[(Number>>12)&0x0f] == str[3]) && - (hexdigit[(Number>>8)&0x0f] == str[4]) && - (hexdigit[(Number>>4)&0x0f] == str[5]) && - (hexdigit[Number&0x0f] == str[6]) ) return 1; - return 0; -} - -PPC_DEVICE __init *residual_find_device(unsigned long BusMask, - unsigned char * DevID, - int BaseType, - int SubType, - int Interface, - int n) -{ - int i; - if (!have_residual_data) return NULL; - for (i=0; iActualNumDevices; i++) { -#define Dev res->Devices[i].DeviceId - if ( (Dev.BusId&BusMask) && - (BaseType==-1 || Dev.BaseType==BaseType) && - (SubType==-1 || Dev.SubType==SubType) && - (Interface==-1 || Dev.Interface==Interface) && - (DevID==NULL || same_DevID((Dev.DevId>>16)&0xffff, - Dev.DevId&0xffff, DevID)) && - !(n--) ) return res->Devices+i; -#undef Dev - } - return NULL; -} - -PPC_DEVICE __init *residual_find_device_id(unsigned long BusMask, - unsigned short DevID, - int BaseType, - int SubType, - int Interface, - int n) -{ - int i; - if (!have_residual_data) return NULL; - for (i=0; iActualNumDevices; i++) { -#define Dev res->Devices[i].DeviceId - if ( (Dev.BusId&BusMask) && - (BaseType==-1 || Dev.BaseType==BaseType) && - (SubType==-1 || Dev.SubType==SubType) && - (Interface==-1 || Dev.Interface==Interface) && - (DevID==0xffff || (Dev.DevId&0xffff) == DevID) && - !(n--) ) return res->Devices+i; -#undef Dev - } - return NULL; -} - -static int __init -residual_scan_pcibridge(PnP_TAG_PACKET * pkt, struct pci_dev *dev) -{ - int irq = -1; - -#define data pkt->L4_Pack.L4_Data.L4_PPCPack.PPCData - if (dev->bus->number == data[16]) { - int i, size; - - size = 3 + ld_le16((u_short *) (&pkt->L4_Pack.Count0)); - for (i = 20; i < size - 4; i += 12) { - unsigned char pin; - int line_irq; - - if (dev->devfn != data[i + 1]) - continue; - - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); - if (pin) { - line_irq = ld_le16((unsigned short *) - (&data[i + 4 + 2 * (pin - 1)])); - irq = (line_irq == 0xffff) ? 0 - : line_irq & 0x7fff; - } else - irq = 0; - - break; - } - } -#undef data - - return irq; -} - -int __init -residual_pcidev_irq(struct pci_dev *dev) -{ - int i = 0; - int irq = -1; - PPC_DEVICE *bridge; - - while ((bridge = residual_find_device - (-1, NULL, BridgeController, PCIBridge, -1, i++))) { - - PnP_TAG_PACKET *pkt; - if (bridge->AllocatedOffset) { - pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap + - bridge->AllocatedOffset, 3, 0); - if (!pkt) - continue; - - irq = residual_scan_pcibridge(pkt, dev); - if (irq != -1) - break; - } - } - - return (irq < 0) ? 0 : irq; -} - -void __init residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi) -{ - PPC_DEVICE *dev; - int i = 0; - unsigned short irq_mask = 0x000; /* default to edge */ - - while ((dev = residual_find_device(-1, NULL, -1, -1, -1, i++))) { - PnP_TAG_PACKET *pkt; - unsigned short mask; - int size; - int offset = dev->AllocatedOffset; - - if (!offset) - continue; - - pkt = PnP_find_packet(res->DevicePnPHeap + offset, - IRQFormat, 0); - if (!pkt) - continue; - - size = tag_small_count(pkt->S1_Pack.Tag) + 1; - mask = ld_le16((unsigned short *)pkt->S4_Pack.IRQMask); - if (size > 3 && (pkt->S4_Pack.IRQInfo & 0x0c)) - irq_mask |= mask; - } - - *irq_edge_mask_lo = irq_mask & 0xff; - *irq_edge_mask_hi = irq_mask >> 8; -} - -unsigned int __init residual_isapic_addr(void) -{ - PPC_DEVICE *isapic; - PnP_TAG_PACKET *pkt; - unsigned int addr; - - isapic = residual_find_device(~0, NULL, SystemPeripheral, - ProgrammableInterruptController, - ISA_PIC, 0); - if (!isapic) - goto unknown; - - pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap + - isapic->AllocatedOffset, 9, 0); - if (!pkt) - goto unknown; - -#define p pkt->L4_Pack.L4_Data.L4_PPCPack - /* Must be 32-bit system address */ - if (!((p.PPCData[0] == 3) && (p.PPCData[1] == 32))) - goto unknown; - - /* It doesn't seem to work where length != 1 (what can I say? :-/ ) */ - if (ld_le32((unsigned int *)(p.PPCData + 12)) != 1) - goto unknown; - - addr = ld_le32((unsigned int *) (p.PPCData + 4)); -#undef p - return addr; -unknown: - return 0; -} - -PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, - unsigned packet_tag, - int n) -{ - unsigned mask, masked_tag, size; - if(!p) return NULL; - if (tag_type(packet_tag)) mask=0xff; else mask=0xF8; - masked_tag = packet_tag&mask; - for(; *p != END_TAG; p+=size) { - if ((*p & mask) == masked_tag && !(n--)) - return (PnP_TAG_PACKET *) p; - if (tag_type(*p)) - size=ld_le16((unsigned short *)(p+1))+3; - else - size=tag_small_count(*p)+1; - } - return NULL; /* not found */ -} - -PnP_TAG_PACKET __init *PnP_find_small_vendor_packet(unsigned char *p, - unsigned packet_type, - int n) -{ - int next=0; - while (p) { - p = (unsigned char *) PnP_find_packet(p, 0x70, next); - if (p && p[1]==packet_type && !(n--)) - return (PnP_TAG_PACKET *) p; - next = 1; - }; - return NULL; /* not found */ -} - -PnP_TAG_PACKET __init *PnP_find_large_vendor_packet(unsigned char *p, - unsigned packet_type, - int n) -{ - int next=0; - while (p) { - p = (unsigned char *) PnP_find_packet(p, 0x84, next); - if (p && p[3]==packet_type && !(n--)) - return (PnP_TAG_PACKET *) p; - next = 1; - }; - return NULL; /* not found */ -} - -#ifdef CONFIG_PROC_PREPRESIDUAL -static int proc_prep_residual_read(char * buf, char ** start, off_t off, - int count, int *eof, void *data) -{ - int n; - - n = res->ResidualLength - off; - if (n < 0) { - *eof = 1; - n = 0; - } - else { - if (n > count) - n = count; - else - *eof = 1; - - memcpy(buf, (char *)res + off, n); - *start = buf; - } - - return n; -} - -int __init -proc_prep_residual_init(void) -{ - if (have_residual_data) - create_proc_read_entry("residual", S_IRUGO, NULL, - proc_prep_residual_read, NULL); - return 0; -} - -__initcall(proc_prep_residual_init); -#endif diff --git a/arch/ppc/platforms/rpx8260.h b/arch/ppc/platforms/rpx8260.h deleted file mode 100644 index 843494a50ef3..000000000000 --- a/arch/ppc/platforms/rpx8260.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Embedded Planet RPX6 (or RPX Super) MPC8260 board. - * Copied from the RPX-Classic and SBS8260 stuff. - * - * Copyright (c) 2001 Dan Malek - */ -#ifdef __KERNEL__ -#ifndef __ASM_PLATFORMS_RPX8260_H__ -#define __ASM_PLATFORMS_RPX8260_H__ - -/* A Board Information structure that is given to a program when - * prom starts it up. - */ -typedef struct bd_info { - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_nvsize; /* NVRAM size in bytes (can be 0) */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in MHz */ - unsigned int bi_cpmfreq; /* CPM Freq, in MHz */ - unsigned int bi_brgfreq; /* BRG Freq, in MHz */ - unsigned int bi_vco; /* VCO Out from PLL */ - unsigned int bi_baudrate; /* Default console baud rate */ - unsigned int bi_immr; /* IMMR when called from boot rom */ - unsigned char bi_enetaddr[6]; -} bd_t; - -extern bd_t m8xx_board_info; - -/* Memory map is configured by the PROM startup. - * We just map a few things we need. The CSR is actually 4 byte-wide - * registers that can be accessed as 8-, 16-, or 32-bit values. - */ -#define CPM_MAP_ADDR ((uint)0xf0000000) -#define RPX_CSR_ADDR ((uint)0xfa000000) -#define RPX_CSR_SIZE ((uint)(512 * 1024)) -#define RPX_NVRTC_ADDR ((uint)0xfa080000) -#define RPX_NVRTC_SIZE ((uint)(512 * 1024)) - -/* The RPX6 has 16, byte wide control/status registers. - * Not all are used (yet). - */ -extern volatile u_char *rpx6_csr_addr; - -/* Things of interest in the CSR. -*/ -#define BCSR0_ID_MASK ((u_char)0xf0) /* Read only */ -#define BCSR0_SWITCH_MASK ((u_char)0x0f) /* Read only */ -#define BCSR1_XCVR_SMC1 ((u_char)0x80) -#define BCSR1_XCVR_SMC2 ((u_char)0x40) -#define BCSR2_FLASH_WENABLE ((u_char)0x20) -#define BCSR2_NVRAM_ENABLE ((u_char)0x10) -#define BCSR2_ALT_IRQ2 ((u_char)0x08) -#define BCSR2_ALT_IRQ3 ((u_char)0x04) -#define BCSR2_PRST ((u_char)0x02) /* Force reset */ -#define BCSR2_ENPRST ((u_char)0x01) /* Enable POR */ -#define BCSR3_MODCLK_MASK ((u_char)0xe0) -#define BCSR3_ENCLKHDR ((u_char)0x10) -#define BCSR3_LED5 ((u_char)0x04) /* 0 == on */ -#define BCSR3_LED6 ((u_char)0x02) /* 0 == on */ -#define BCSR3_LED7 ((u_char)0x01) /* 0 == on */ -#define BCSR4_EN_PHY ((u_char)0x80) /* Enable PHY */ -#define BCSR4_EN_MII ((u_char)0x40) /* Enable PHY */ -#define BCSR4_MII_READ ((u_char)0x04) -#define BCSR4_MII_MDC ((u_char)0x02) -#define BCSR4_MII_MDIO ((u_char)0x01) -#define BCSR13_FETH_IRQMASK ((u_char)0xf0) -#define BCSR15_FETH_IRQ ((u_char)0x20) - -#define PHY_INTERRUPT SIU_INT_IRQ7 - -/* For our show_cpuinfo hooks. */ -#define CPUINFO_VENDOR "Embedded Planet" -#define CPUINFO_MACHINE "EP8260 PowerPC" - -/* Warm reset vector. */ -#define BOOTROM_RESTART_ADDR ((uint)0xfff00104) - -#endif /* __ASM_PLATFORMS_RPX8260_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/rpxclassic.h b/arch/ppc/platforms/rpxclassic.h deleted file mode 100644 index a3c1118e5b09..000000000000 --- a/arch/ppc/platforms/rpxclassic.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the RPCG RPX-Classic board. Copied from the RPX-Lite stuff. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ -#ifdef __KERNEL__ -#ifndef __MACH_RPX_DEFS -#define __MACH_RPX_DEFS - - -#ifndef __ASSEMBLY__ -/* A Board Information structure that is given to a program when - * prom starts it up. - */ -typedef struct bd_info { - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in Hz */ - unsigned char bi_enetaddr[6]; - unsigned int bi_baudrate; -} bd_t; - -extern bd_t m8xx_board_info; - -/* Memory map is configured by the PROM startup. - * We just map a few things we need. The CSR is actually 4 byte-wide - * registers that can be accessed as 8-, 16-, or 32-bit values. - */ -#define PCI_ISA_IO_ADDR ((unsigned)0x80000000) -#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024)) -#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000) -#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024)) -#define RPX_CSR_ADDR ((uint)0xfa400000) -#define RPX_CSR_SIZE ((uint)(4 * 1024)) -#define IMAP_ADDR ((uint)0xfa200000) -#define IMAP_SIZE ((uint)(64 * 1024)) -#define PCI_CSR_ADDR ((uint)0x80000000) -#define PCI_CSR_SIZE ((uint)(64 * 1024)) -#define PCMCIA_MEM_ADDR ((uint)0xe0000000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) -#define PCMCIA_IO_ADDR ((uint)0xe4000000) -#define PCMCIA_IO_SIZE ((uint)(4 * 1024)) -#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000) -#define PCMCIA_ATTRB_SIZE ((uint)(4 * 1024)) - -/* Things of interest in the CSR. -*/ -#define BCSR0_ETHEN ((uint)0x80000000) -#define BCSR0_ETHLPBK ((uint)0x40000000) -#define BCSR0_COLTESTDIS ((uint)0x20000000) -#define BCSR0_FULLDPLXDIS ((uint)0x10000000) -#define BCSR0_ENFLSHSEL ((uint)0x04000000) -#define BCSR0_FLASH_SEL ((uint)0x02000000) -#define BCSR0_ENMONXCVR ((uint)0x01000000) - -#define BCSR0_PCMCIAVOLT ((uint)0x000f0000) /* CLLF */ -#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000) /* CLLF */ -#define BCSR0_PCMCIA5VOLT ((uint)0x00060000) /* CLLF */ - -#define BCSR1_IPB5SEL ((uint)0x00100000) -#define BCSR1_PCVCTL4 ((uint)0x00080000) -#define BCSR1_PCVCTL5 ((uint)0x00040000) -#define BCSR1_PCVCTL6 ((uint)0x00020000) -#define BCSR1_PCVCTL7 ((uint)0x00010000) - -#define BCSR2_EN232XCVR ((uint)0x00008000) -#define BCSR2_QSPACESEL ((uint)0x00004000) -#define BCSR2_FETHLEDMODE ((uint)0x00000800) /* CLLF */ - -/* define IO_BASE for pcmcia, CLLF only */ -#if !defined(CONFIG_PCI) -#define _IO_BASE 0x80000000 -#define _IO_BASE_SIZE 0x1000 - -/* for pcmcia sandisk */ -#ifdef CONFIG_IDE -# define MAX_HWIFS 1 -#endif -#endif - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - - -/* CPM Ethernet through SCCx. - * - * Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00001000) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) - -/* We don't use the 8259. -*/ - -#define NR_8259_INTS 0 - -#endif /* !__ASSEMBLY__ */ -#endif /* __MACH_RPX_DEFS */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/rpxlite.h b/arch/ppc/platforms/rpxlite.h deleted file mode 100644 index b615501d55fc..000000000000 --- a/arch/ppc/platforms/rpxlite.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the RPCG RPX-Lite board. Copied from the MBX stuff. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ -#ifdef __KERNEL__ -#ifndef __MACH_RPX_DEFS -#define __MACH_RPX_DEFS - - -#ifndef __ASSEMBLY__ -/* A Board Information structure that is given to a program when - * prom starts it up. - */ -typedef struct bd_info { - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in Hz */ - unsigned char bi_enetaddr[6]; - unsigned int bi_baudrate; -} bd_t; - -extern bd_t m8xx_board_info; - -/* Memory map is configured by the PROM startup. - * We just map a few things we need. The CSR is actually 4 byte-wide - * registers that can be accessed as 8-, 16-, or 32-bit values. - */ -#define RPX_CSR_ADDR ((uint)0xfa400000) -#define RPX_CSR_SIZE ((uint)(4 * 1024)) -#define IMAP_ADDR ((uint)0xfa200000) -#define IMAP_SIZE ((uint)(64 * 1024)) -#define PCMCIA_MEM_ADDR ((uint)0x04000000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) -#define PCMCIA_IO_ADDR ((uint)0x04400000) -#define PCMCIA_IO_SIZE ((uint)(4 * 1024)) - -/* Things of interest in the CSR. -*/ -#define BCSR0_ETHEN ((uint)0x80000000) -#define BCSR0_ETHLPBK ((uint)0x40000000) -#define BCSR0_COLTESTDIS ((uint)0x20000000) -#define BCSR0_FULLDPLXDIS ((uint)0x10000000) -#define BCSR0_LEDOFF ((uint)0x08000000) -#define BCSR0_USBDISABLE ((uint)0x04000000) -#define BCSR0_USBHISPEED ((uint)0x02000000) -#define BCSR0_USBPWREN ((uint)0x01000000) -#define BCSR0_PCMCIAVOLT ((uint)0x000f0000) -#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000) -#define BCSR0_PCMCIA5VOLT ((uint)0x00060000) - -#define BCSR1_IPB5SEL ((uint)0x00100000) -#define BCSR1_PCVCTL4 ((uint)0x00080000) -#define BCSR1_PCVCTL5 ((uint)0x00040000) -#define BCSR1_PCVCTL6 ((uint)0x00020000) -#define BCSR1_PCVCTL7 ((uint)0x00010000) - -/* define IO_BASE for pcmcia */ -#define _IO_BASE 0x80000000 -#define _IO_BASE_SIZE 0x1000 - -#ifdef CONFIG_IDE -# define MAX_HWIFS 1 -#endif - -/* CPM Ethernet through SCCx. - * - * This ENET stuff is for the MPC850 with ethernet on SCC2. Some of - * this may be unique to the RPX-Lite configuration. - * Note TENA is on Port B. - */ -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003d00) - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* !__ASSEMBLY__ */ -#endif /* __MACH_RPX_DEFS */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/sandpoint.c b/arch/ppc/platforms/sandpoint.c deleted file mode 100644 index b4897bdb742a..000000000000 --- a/arch/ppc/platforms/sandpoint.c +++ /dev/null @@ -1,651 +0,0 @@ -/* - * Board setup routines for the Motorola SPS Sandpoint Test Platform. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2000-2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * This file adds support for the Motorola SPS Sandpoint Test Platform. - * These boards have a PPMC slot for the processor so any combination - * of cpu and host bridge can be attached. This port is for an 8240 PPMC - * module from Motorola SPS and other closely related cpu/host bridge - * combinations (e.g., 750/755/7400 with MPC107 host bridge). - * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2 - * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a - * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr), - * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V - * but are really 5V). - * - * The firmware on the sandpoint is called DINK (not my acronym :). This port - * depends on DINK to do some basic initialization (e.g., initialize the memory - * ctlr) and to ensure that the processor is using MAP B (CHRP map). - * - * The switch settings for the Sandpoint board MUST be as follows: - * S3: down - * S4: up - * S5: up - * S6: down - * - * 'down' is in the direction from the PCI slots towards the PPMC slot; - * 'up' is in the direction from the PPMC slot towards the PCI slots. - * Be careful, the way the sandpoint board is installed in XT chasses will - * make the directions reversed. - * - * Since Motorola listened to our suggestions for improvement, we now have - * the Sandpoint X3 board. All of the PCI slots are available, it uses - * the serial interrupt interface (just a hardware thing we need to - * configure properly). - * - * Use the default X3 switch settings. The interrupts are then: - * EPIC Source - * 0 SIOINT (8259, active low) - * 1 PCI #1 - * 2 PCI #2 - * 3 PCI #3 - * 4 PCI #4 - * 7 Winbond INTC (IDE interrupt) - * 8 Winbond INTD (IDE interrupt) - * - * - * Motorola has finally released a version of DINK32 that correctly - * (seemingly) initializes the memory controller correctly, regardless - * of the amount of memory in the system. Once a method of determining - * what version of DINK initializes the system for us, if applicable, is - * found, we can hopefully stop hardcoding 32MB of RAM. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /* for linux/serial_core.h */ -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "sandpoint.h" - -/* Set non-zero if an X2 Sandpoint detected. */ -static int sandpoint_is_x2; - -unsigned char __res[sizeof(bd_t)]; - -static void sandpoint_halt(void); -static void sandpoint_probe_type(void); - -/* - * Define all of the IRQ senses and polarities. Taken from the - * Sandpoint X3 User's manual. - */ -static u_char sandpoint_openpic_initsenses[] __initdata = { - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */ -}; - -/* - * Motorola SPS Sandpoint interrupt routing. - */ -static inline int -x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 16, 0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */ - { 0, 0, 0, 0 }, /* IDSEL 12 - unused */ - { 18, 21, 20, 19 }, /* IDSEL 13 - PCI slot 1 */ - { 19, 18, 21, 20 }, /* IDSEL 14 - PCI slot 2 */ - { 20, 19, 18, 21 }, /* IDSEL 15 - PCI slot 3 */ - { 21, 20, 19, 18 }, /* IDSEL 16 - PCI slot 4 */ - }; - - const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -static inline int -x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { 18, 0, 0, 0 }, /* IDSEL 11 - i8259 on Windbond */ - { 0, 0, 0, 0 }, /* IDSEL 12 - unused */ - { 16, 17, 18, 19 }, /* IDSEL 13 - PCI slot 1 */ - { 17, 18, 19, 16 }, /* IDSEL 14 - PCI slot 2 */ - { 18, 19, 16, 17 }, /* IDSEL 15 - PCI slot 3 */ - { 19, 16, 17, 18 }, /* IDSEL 16 - PCI slot 4 */ - }; - - const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -static void __init -sandpoint_setup_winbond_83553(struct pci_controller *hose) -{ - int devfn; - - /* - * Route IDE interrupts directly to the 8259's IRQ 14 & 15. - * We can't route the IDE interrupt to PCI INTC# or INTD# because those - * woule interfere with the PMC's INTC# and INTD# lines. - */ - /* - * Winbond Fcn 0 - */ - devfn = PCI_DEVFN(11,0); - - early_write_config_byte(hose, - 0, - devfn, - 0x43, /* IDE Interrupt Routing Control */ - 0xef); - early_write_config_word(hose, - 0, - devfn, - 0x44, /* PCI Interrupt Routing Control */ - 0x0000); - - /* Want ISA memory cycles to be forwarded to PCI bus */ - early_write_config_byte(hose, - 0, - devfn, - 0x48, /* ISA-to-PCI Addr Decoder Control */ - 0xf0); - - /* Enable Port 92. */ - early_write_config_byte(hose, - 0, - devfn, - 0x4e, /* AT System Control Register */ - 0x06); - /* - * Winbond Fcn 1 - */ - devfn = PCI_DEVFN(11,1); - - /* Put IDE controller into native mode. */ - early_write_config_byte(hose, - 0, - devfn, - 0x09, /* Programming interface Register */ - 0x8f); - - /* Init IRQ routing, enable both ports, disable fast 16 */ - early_write_config_dword(hose, - 0, - devfn, - 0x40, /* IDE Control/Status Register */ - 0x00ff0011); - return; -} - -/* On the sandpoint X2, we must avoid sending configuration cycles to - * device #12 (IDSEL addr = AD12). - */ -static int -x2_exclude_device(u_char bus, u_char devfn) -{ - if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL)) - return PCIBIOS_DEVICE_NOT_FOUND; - else - return PCIBIOS_SUCCESSFUL; -} - -static void __init -sandpoint_find_bridges(void) -{ - struct pci_controller *hose; - - hose = pcibios_alloc_controller(); - - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - if (mpc10x_bridge_init(hose, - MPC10X_MEM_MAP_B, - MPC10X_MEM_MAP_B, - MPC10X_MAPB_EUMB_BASE) == 0) { - - /* Do early winbond init, then scan PCI bus */ - sandpoint_setup_winbond_83553(hose); - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pcibios_fixup = NULL; - ppc_md.pcibios_fixup_bus = NULL; - ppc_md.pci_swizzle = common_swizzle; - if (sandpoint_is_x2) { - ppc_md.pci_map_irq = x2_map_irq; - ppc_md.pci_exclude_device = x2_exclude_device; - } else - ppc_md.pci_map_irq = x3_map_irq; - } - else { - if (ppc_md.progress) - ppc_md.progress("Bridge init failed", 0x100); - printk("Host bridge init failed\n"); - } - - return; -} - -static void __init -sandpoint_setup_arch(void) -{ - /* Probe for Sandpoint model */ - sandpoint_probe_type(); - if (sandpoint_is_x2) - epic_serial_mode = 0; - - loops_per_jiffy = 100000000 / HZ; - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_HDA1; -#endif - - /* Lookup PCI host bridges */ - sandpoint_find_bridges(); - - if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0) - { - bd_t *bp = (bd_t *)__res; - struct plat_serial8250_port *pdata; - - pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0); - if (pdata) - { - pdata[0].uartclk = bp->bi_busfreq; - } - -#ifdef CONFIG_SANDPOINT_ENABLE_UART1 - pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1); - if (pdata) - { - pdata[0].uartclk = bp->bi_busfreq; - } -#else - ppc_sys_device_remove(MPC10X_UART1); -#endif - } - - printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n"); - printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n"); - - /* DINK32 12.3 and below do not correctly enable any caches. - * We will do this now with good known values. Future versions - * of DINK32 are supposed to get this correct. - */ - if (cpu_has_feature(CPU_FTR_SPEC7450)) - /* 745x is different. We only want to pass along enable. */ - _set_L2CR(L2CR_L2E); - else if (cpu_has_feature(CPU_FTR_L2CR)) - /* All modules have 1MB of L2. We also assume that an - * L2 divisor of 3 will work. - */ - _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3 - | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); -#if 0 - /* Untested right now. */ - if (cpu_has_feature(CPU_FTR_L3CR)) { - /* Magic value. */ - _set_L3CR(0x8f032000); - } -#endif -} - -#define SANDPOINT_87308_CFG_ADDR 0x15c -#define SANDPOINT_87308_CFG_DATA 0x15d - -#define SANDPOINT_87308_CFG_INB(addr, byte) { \ - outb((addr), SANDPOINT_87308_CFG_ADDR); \ - (byte) = inb(SANDPOINT_87308_CFG_DATA); \ -} - -#define SANDPOINT_87308_CFG_OUTB(addr, byte) { \ - outb((addr), SANDPOINT_87308_CFG_ADDR); \ - outb((byte), SANDPOINT_87308_CFG_DATA); \ -} - -#define SANDPOINT_87308_SELECT_DEV(dev_num) { \ - SANDPOINT_87308_CFG_OUTB(0x07, (dev_num)); \ -} - -#define SANDPOINT_87308_DEV_ENABLE(dev_num) { \ - SANDPOINT_87308_SELECT_DEV(dev_num); \ - SANDPOINT_87308_CFG_OUTB(0x30, 0x01); \ -} - -/* - * To probe the Sandpoint type, we need to check for a connection between GPIO - * pins 6 and 7 on the NS87308 SuperIO. - */ -static void __init sandpoint_probe_type(void) -{ - u8 x; - /* First, ensure that the GPIO pins are enabled. */ - SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */ - SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */ - SANDPOINT_87308_CFG_OUTB(0x61, 0x00); - SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */ - - /* Now, set pin 7 to output and pin 6 to input. */ - outb((inb(0x701) | 0x80) & 0xbf, 0x701); - /* Set push-pull output */ - outb(inb(0x702) | 0x80, 0x702); - /* Set pull-up on input */ - outb(inb(0x703) | 0x40, 0x703); - /* Set output high and check */ - x = inb(0x700); - outb(x | 0x80, 0x700); - x = inb(0x700); - sandpoint_is_x2 = ! (x & 0x40); - if (ppc_md.progress && sandpoint_is_x2) - ppc_md.progress("High output says X2", 0); - /* Set output low and check */ - outb(x & 0x7f, 0x700); - sandpoint_is_x2 |= inb(0x700) & 0x40; - if (ppc_md.progress && sandpoint_is_x2) - ppc_md.progress("Low output says X2", 0); - if (ppc_md.progress && ! sandpoint_is_x2) - ppc_md.progress("Sandpoint is X3", 0); -} - -/* - * Fix IDE interrupts. - */ -static int __init -sandpoint_fix_winbond_83553(void) -{ - /* Make some 8259 interrupt level sensitive */ - outb(0xe0, 0x4d0); - outb(0xde, 0x4d1); - - return 0; -} - -arch_initcall(sandpoint_fix_winbond_83553); - -/* - * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip. - */ -static int __init -sandpoint_setup_natl_87308(void) -{ - u_char reg; - - /* - * Enable all the devices on the Super I/O chip. - */ - SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */ - SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */ - SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */ - SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */ - SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */ - SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */ - SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */ - SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */ - SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */ - SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */ - SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */ - - /* Set up floppy in PS/2 mode */ - outb(0x09, SIO_CONFIG_RA); - reg = inb(SIO_CONFIG_RD); - reg = (reg & 0x3F) | 0x40; - outb(reg, SIO_CONFIG_RD); - outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */ - - return 0; -} - -arch_initcall(sandpoint_setup_natl_87308); - -static int __init -sandpoint_request_io(void) -{ - request_region(0x00,0x20,"dma1"); - request_region(0x20,0x20,"pic1"); - request_region(0x40,0x20,"timer"); - request_region(0x80,0x10,"dma page reg"); - request_region(0xa0,0x20,"pic2"); - request_region(0xc0,0x20,"dma2"); - - return 0; -} - -arch_initcall(sandpoint_request_io); - -/* - * Interrupt setup and service. Interrupts on the Sandpoint come - * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO). - * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4, - * IDE is on EPIC 7 and 8. - */ -static void __init -sandpoint_init_IRQ(void) -{ - int i; - - OpenPIC_InitSenses = sandpoint_openpic_initsenses; - OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses); - - mpc10x_set_openpic(); - openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade", - i8259_irq); - - /* - * The EPIC allows for a read in the range of 0xFEF00000 -> - * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction. - */ - i8259_init(0xfef00000, 0); -} - -static unsigned long __init -sandpoint_find_end_of_memory(void) -{ - bd_t *bp = (bd_t *)__res; - - if (bp->bi_memsize) - return bp->bi_memsize; - - /* DINK32 13.0 correctly initializes things, so iff you use - * this you _should_ be able to change this instead of a - * hardcoded value. */ -#if 0 - return mpc10x_get_mem_size(MPC10X_MEM_MAP_B); -#else - return 32*1024*1024; -#endif -} - -static void __init -sandpoint_map_io(void) -{ - io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO); -} - -static void -sandpoint_restart(char *cmd) -{ - local_irq_disable(); - - /* Set exception prefix high - to the firmware */ - _nmask_and_or_msr(0, MSR_IP); - - /* Reset system via Port 92 */ - outb(0x00, 0x92); - outb(0x01, 0x92); - for(;;); /* Spin until reset happens */ -} - -static void -sandpoint_power_off(void) -{ - local_irq_disable(); - for(;;); /* No way to shut power off with software */ - /* NOTREACHED */ -} - -static void -sandpoint_halt(void) -{ - sandpoint_power_off(); - /* NOTREACHED */ -} - -static int -sandpoint_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: Motorola SPS\n"); - seq_printf(m, "machine\t\t: Sandpoint\n"); - - return 0; -} - -/* - * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1. - */ -static __inline__ void -sandpoint_set_bat(void) -{ - unsigned long bat3u, bat3l; - - __asm__ __volatile__( - " lis %0,0xf800\n \ - ori %1,%0,0x002a\n \ - ori %0,%0,0x0ffe\n \ - mtspr 0x21e,%0\n \ - mtspr 0x21f,%1\n \ - isync\n \ - sync " - : "=r" (bat3u), "=r" (bat3l)); -} - -TODC_ALLOC(); - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) - * are non-zero, then we should use the board info from the bd_t - * structure and the cmdline pointed to by r6 instead of the - * information from birecs, if any. Otherwise, use the information - * from birecs as discovered by the preceding call to - * parse_bootinfo(). This rule should work with both PPCBoot, which - * uses a bd_t board info structure, and the kernel boot wrapper, - * which uses birecs. - */ - if (r3 && r6) { - /* copy board info structure */ - memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); - /* copy command line */ - *(char *)(r7+KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6+KERNELBASE)); - } - -#ifdef CONFIG_BLK_DEV_INITRD - /* take care of initrd if we have one */ - if (r4) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - /* Map in board regs, etc. */ - sandpoint_set_bat(); - - isa_io_base = MPC10X_MAPB_ISA_IO_BASE; - isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE; - pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET; - ISA_DMA_THRESHOLD = 0x00ffffff; - DMA_MODE_READ = 0x44; - DMA_MODE_WRITE = 0x48; - ppc_do_canonicalize_irqs = 1; - - ppc_md.setup_arch = sandpoint_setup_arch; - ppc_md.show_cpuinfo = sandpoint_show_cpuinfo; - ppc_md.init_IRQ = sandpoint_init_IRQ; - ppc_md.get_irq = openpic_get_irq; - - ppc_md.restart = sandpoint_restart; - ppc_md.power_off = sandpoint_power_off; - ppc_md.halt = sandpoint_halt; - - ppc_md.find_end_of_memory = sandpoint_find_end_of_memory; - ppc_md.setup_io_mappings = sandpoint_map_io; - - TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8); - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.calibrate_decr = todc_calibrate_decr; - - ppc_md.nvram_read_val = todc_mc146818_read_val; - ppc_md.nvram_write_val = todc_mc146818_write_val; - -#ifdef CONFIG_KGDB - ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; -#endif -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif -} diff --git a/arch/ppc/platforms/sandpoint.h b/arch/ppc/platforms/sandpoint.h deleted file mode 100644 index ed83759e4044..000000000000 --- a/arch/ppc/platforms/sandpoint.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Definitions for Motorola SPS Sandpoint Test Platform - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2000-2003 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * Sandpoint uses the CHRP map (Map B). - */ - -#ifndef __PPC_PLATFORMS_SANDPOINT_H -#define __PPC_PLATFORMS_SANDPOINT_H - -#include - -#if 0 -/* The Sandpoint X3 allows the IDE interrupt to be directly connected - * from the Windbond (PCI INTC or INTD) to the serial EPIC. Someday - * we should try this, but it was easier to use the existing 83c553 - * initialization than change it to route the different interrupts :-). - * -- Dan - */ -#define SANDPOINT_IDE_INT0 23 /* EPIC 7 */ -#define SANDPOINT_IDE_INT1 24 /* EPIC 8 */ -#endif - -/* - * The sandpoint boards have processor modules that either have an 8240 or - * an MPC107 host bridge on them. These bridges have an IDSEL line that allows - * them to respond to PCI transactions as if they were a normal PCI devices. - * However, the processor on the processor side of the bridge can not reach - * out onto the PCI bus and then select the bridge or bad things will happen - * (documented in the 8240 and 107 manuals). - * Because of this, we always skip the bridge PCI device when accessing the - * PCI bus. The PCI slot that the bridge occupies is defined by the macro - * below. - */ -#define SANDPOINT_HOST_BRIDGE_IDSEL 12 - -/* - * Serial defines. - */ -#define SANDPOINT_SERIAL_0 0xfe0003f8 -#define SANDPOINT_SERIAL_1 0xfe0002f8 - -#define RS_TABLE_SIZE 2 - -/* Rate for the 1.8432 Mhz clock for the onboard serial chip */ -#define BASE_BAUD ( 1843200 / 16 ) -#define UART_CLK 1843200 - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF) -#endif - -#define STD_SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, SANDPOINT_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \ - iomem_base: (u8 *)SANDPOINT_SERIAL_0, \ - io_type: SERIAL_IO_MEM }, \ - { 0, BASE_BAUD, SANDPOINT_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \ - iomem_base: (u8 *)SANDPOINT_SERIAL_1, \ - io_type: SERIAL_IO_MEM }, - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DFNS - -#endif /* __PPC_PLATFORMS_SANDPOINT_H */ diff --git a/arch/ppc/platforms/sbc82xx.c b/arch/ppc/platforms/sbc82xx.c deleted file mode 100644 index 24f6e0694ac1..000000000000 --- a/arch/ppc/platforms/sbc82xx.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * SBC82XX platform support - * - * Author: Guy Streeter - * - * Derived from: est8260_setup.c by Allen Curtis, ONZ - * - * Copyright 2004 Red Hat, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -static void (*callback_init_IRQ)(void); - -extern unsigned char __res[sizeof(bd_t)]; - -#ifdef CONFIG_GEN_RTC -TODC_ALLOC(); - -/* - * Timer init happens before mem_init but after paging init, so we cannot - * directly use ioremap() at that time. - * late_time_init() is call after paging init. - */ - -static void sbc82xx_time_init(void) -{ - volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl; - - /* Set up CS11 for RTC chip */ - mc->memc_br11=0; - mc->memc_or11=0xffff0836; - mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801; - - TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0); - - todc_info->nvram_data = - (unsigned int)ioremap(todc_info->nvram_data, 0x2000); - BUG_ON(!todc_info->nvram_data); - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; - todc_time_init(); -} -#endif /* CONFIG_GEN_RTC */ - -static volatile char *sbc82xx_i8259_map; -static char sbc82xx_i8259_mask = 0xff; -static DEFINE_SPINLOCK(sbc82xx_i8259_lock); - -static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr) -{ - unsigned long flags; - - irq_nr -= NR_SIU_INTS; - - spin_lock_irqsave(&sbc82xx_i8259_lock, flags); - sbc82xx_i8259_mask |= 1 << irq_nr; - (void) sbc82xx_i8259_map[1]; /* Dummy read */ - sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; - sbc82xx_i8259_map[0] = 0x20; /* OCW2: Non-specific EOI */ - spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags); -} - -static void sbc82xx_i8259_mask_irq(unsigned int irq_nr) -{ - unsigned long flags; - - irq_nr -= NR_SIU_INTS; - - spin_lock_irqsave(&sbc82xx_i8259_lock, flags); - sbc82xx_i8259_mask |= 1 << irq_nr; - sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; - spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags); -} - -static void sbc82xx_i8259_unmask_irq(unsigned int irq_nr) -{ - unsigned long flags; - - irq_nr -= NR_SIU_INTS; - - spin_lock_irqsave(&sbc82xx_i8259_lock, flags); - sbc82xx_i8259_mask &= ~(1 << irq_nr); - sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; - spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags); -} - -static void sbc82xx_i8259_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) - && irq_desc[irq].action) - sbc82xx_i8259_unmask_irq(irq); -} - - -struct hw_interrupt_type sbc82xx_i8259_ic = { - .typename = " i8259 ", - .enable = sbc82xx_i8259_unmask_irq, - .disable = sbc82xx_i8259_mask_irq, - .ack = sbc82xx_i8259_mask_and_ack_irq, - .end = sbc82xx_i8259_end_irq, -}; - -static irqreturn_t sbc82xx_i8259_demux(int dummy, void *dev_id) -{ - int irq; - - spin_lock(&sbc82xx_i8259_lock); - - sbc82xx_i8259_map[0] = 0x0c; /* OCW3: Read IR register on RD# pulse */ - irq = sbc82xx_i8259_map[0] & 7; /* Read IRR */ - - if (irq == 7) { - /* Possible spurious interrupt */ - int isr; - sbc82xx_i8259_map[0] = 0x0b; /* OCW3: Read IS register on RD# pulse */ - isr = sbc82xx_i8259_map[0]; /* Read ISR */ - - if (!(isr & 0x80)) { - printk(KERN_INFO "Spurious i8259 interrupt\n"); - return IRQ_HANDLED; - } - } - __do_IRQ(NR_SIU_INTS + irq); - return IRQ_HANDLED; -} - -static struct irqaction sbc82xx_i8259_irqaction = { - .handler = sbc82xx_i8259_demux, - .flags = IRQF_DISABLED, - .mask = CPU_MASK_NONE, - .name = "i8259 demux", -}; - -void __init sbc82xx_init_IRQ(void) -{ - volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl; - volatile intctl_cpm2_t *ic = &cpm2_immr->im_intctl; - int i; - - callback_init_IRQ(); - - /* u-boot doesn't always set the board up correctly */ - mc->memc_br5 = 0; - mc->memc_or5 = 0xfff00856; - mc->memc_br5 = 0x22000801; - - sbc82xx_i8259_map = ioremap(0x22008000, 2); - if (!sbc82xx_i8259_map) { - printk(KERN_CRIT "Mapping i8259 interrupt controller failed\n"); - return; - } - - /* Set up the interrupt handlers for the i8259 IRQs */ - for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) { - irq_desc[i].chip = &sbc82xx_i8259_ic; - irq_desc[i].status |= IRQ_LEVEL; - } - - /* make IRQ6 level sensitive */ - ic->ic_siexr &= ~(1 << (14 - (SIU_INT_IRQ6 - SIU_INT_IRQ1))); - irq_desc[SIU_INT_IRQ6].status |= IRQ_LEVEL; - - /* Initialise the i8259 */ - sbc82xx_i8259_map[0] = 0x1b; /* ICW1: Level, no cascade, ICW4 */ - sbc82xx_i8259_map[1] = 0x00; /* ICW2: vector base */ - /* No ICW3 (no cascade) */ - sbc82xx_i8259_map[1] = 0x01; /* ICW4: 8086 mode, normal EOI */ - - sbc82xx_i8259_map[0] = 0x0b; /* OCW3: Read IS register on RD# pulse */ - - sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; /* Set interrupt mask */ - - /* Request cascade IRQ */ - if (setup_irq(SIU_INT_IRQ6, &sbc82xx_i8259_irqaction)) { - printk("Installation of i8259 IRQ demultiplexer failed.\n"); - } -} - -static int sbc82xx_pci_map_irq(struct pci_dev *dev, unsigned char idsel, - unsigned char pin) -{ - static char pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 16 - PMC slot */ - { SBC82xx_PC_IRQA, SBC82xx_PC_IRQB, -1, -1 }, /* IDSEL 17 - CardBus */ - { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 18 - PCI-X bridge */ - }; - - const long min_idsel = 16, max_idsel = 18, irqs_per_slot = 4; - - return PCI_IRQ_TABLE_LOOKUP; -} - -static void __devinit quirk_sbc8260_cardbus(struct pci_dev *pdev) -{ - uint32_t ctrl; - - if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(17, 0)) - return; - - printk(KERN_INFO "Setting up CardBus controller\n"); - - /* Set P2CCLK bit in System Control Register */ - pci_read_config_dword(pdev, 0x80, &ctrl); - ctrl |= (1<<27); - pci_write_config_dword(pdev, 0x80, ctrl); - - /* Set MFUNC up for PCI IRQ routing via INTA and INTB, and LEDs. */ - pci_write_config_dword(pdev, 0x8c, 0x00c01d22); - -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, quirk_sbc8260_cardbus); - -void __init -m82xx_board_init(void) -{ - /* u-boot may be using one of the FCC Ethernet devices. - Use the MAC address to the SCC. */ - __res[offsetof(bd_t, bi_enetaddr[5])] &= ~3; - - /* Anything special for this platform */ - callback_init_IRQ = ppc_md.init_IRQ; - - ppc_md.init_IRQ = sbc82xx_init_IRQ; - ppc_md.pci_map_irq = sbc82xx_pci_map_irq; -#ifdef CONFIG_GEN_RTC - ppc_md.time_init = NULL; - ppc_md.get_rtc_time = NULL; - ppc_md.set_rtc_time = NULL; - ppc_md.nvram_read_val = NULL; - ppc_md.nvram_write_val = NULL; - late_time_init = sbc82xx_time_init; -#endif /* CONFIG_GEN_RTC */ -} diff --git a/arch/ppc/platforms/sbc82xx.h b/arch/ppc/platforms/sbc82xx.h deleted file mode 100644 index e4042d4995f6..000000000000 --- a/arch/ppc/platforms/sbc82xx.h +++ /dev/null @@ -1,36 +0,0 @@ -/* Board information for the SBCPowerQUICCII, which should be generic for - * all 8260 boards. The IMMR is now given to us so the hard define - * will soon be removed. All of the clock values are computed from - * the configuration SCMR and the Power-On-Reset word. - */ - -#ifndef __PPC_SBC82xx_H__ -#define __PPC_SBC82xx_H__ - -#include - -#define CPM_MAP_ADDR 0xf0000000 - -#define SBC82xx_TODC_NVRAM_ADDR 0xd0000000 - -#define SBC82xx_MACADDR_NVRAM_FCC1 0x220000c9 /* JP6B */ -#define SBC82xx_MACADDR_NVRAM_SCC1 0x220000cf /* JP6A */ -#define SBC82xx_MACADDR_NVRAM_FCC2 0x220000d5 /* JP7A */ -#define SBC82xx_MACADDR_NVRAM_FCC3 0x220000db /* JP7B */ - -/* For our show_cpuinfo hooks. */ -#define CPUINFO_VENDOR "Wind River" -#define CPUINFO_MACHINE "SBC PowerQUICC II" - -#define BOOTROM_RESTART_ADDR ((uint)0x40000104) - -#define SBC82xx_PC_IRQA (NR_SIU_INTS+0) -#define SBC82xx_PC_IRQB (NR_SIU_INTS+1) -#define SBC82xx_MPC185_IRQ (NR_SIU_INTS+2) -#define SBC82xx_ATM_IRQ (NR_SIU_INTS+3) -#define SBC82xx_PIRQA (NR_SIU_INTS+4) -#define SBC82xx_PIRQB (NR_SIU_INTS+5) -#define SBC82xx_PIRQC (NR_SIU_INTS+6) -#define SBC82xx_PIRQD (NR_SIU_INTS+7) - -#endif /* __PPC_SBC82xx_H__ */ diff --git a/arch/ppc/platforms/sbs8260.h b/arch/ppc/platforms/sbs8260.h deleted file mode 100644 index d51427a0f0d4..000000000000 --- a/arch/ppc/platforms/sbs8260.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __ASSEMBLY__ -/* Board information for various SBS 8260 cards, which should be generic for - * all 8260 boards. The IMMR is now given to us so the hard define - * will soon be removed. All of the clock values are computed from - * the configuration SCMR and the Power-On-Reset word. - */ - -#define CPM_MAP_ADDR ((uint)0xfe000000) - - -/* A Board Information structure that is given to a program when - * prom starts it up. - */ -typedef struct bd_info { - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in MHz */ - unsigned int bi_cpmfreq; /* CPM Freq, in MHz */ - unsigned int bi_brgfreq; /* BRG Freq, in MHz */ - unsigned int bi_vco; /* VCO Out from PLL */ - unsigned int bi_baudrate; /* Default console baud rate */ - unsigned int bi_immr; /* IMMR when called from boot rom */ - unsigned char bi_enetaddr[6]; -} bd_t; - -extern bd_t m8xx_board_info; -#endif /* !__ASSEMBLY__ */ diff --git a/arch/ppc/platforms/spruce.c b/arch/ppc/platforms/spruce.c deleted file mode 100644 index a344134f14b8..000000000000 --- a/arch/ppc/platforms/spruce.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Board and PCI setup routines for IBM Spruce - * - * Author: MontaVista Software - * - * 2000-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "spruce.h" - -static inline int -spruce_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - {23, 24, 25, 26}, /* IDSEL 1 - PCI slot 3 */ - {24, 25, 26, 23}, /* IDSEL 2 - PCI slot 2 */ - {25, 26, 23, 24}, /* IDSEL 3 - PCI slot 1 */ - {26, 23, 24, 25}, /* IDSEL 4 - PCI slot 0 */ - }; - - const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -static void __init -spruce_setup_hose(void) -{ - struct pci_controller *hose; - - /* Setup hose */ - hose = pcibios_alloc_controller(); - if (!hose) - return; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_init_resource(&hose->io_resource, - SPRUCE_PCI_LOWER_IO, - SPRUCE_PCI_UPPER_IO, - IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource(&hose->mem_resources[0], - SPRUCE_PCI_LOWER_MEM, - SPRUCE_PCI_UPPER_MEM, - IORESOURCE_MEM, - "PCI host bridge"); - - hose->io_space.start = SPRUCE_PCI_LOWER_IO; - hose->io_space.end = SPRUCE_PCI_UPPER_IO; - hose->mem_space.start = SPRUCE_PCI_LOWER_MEM; - hose->mem_space.end = SPRUCE_PCI_UPPER_MEM; - hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE; - - setup_indirect_pci(hose, - SPRUCE_PCI_CONFIG_ADDR, - SPRUCE_PCI_CONFIG_DATA); - - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = spruce_map_irq; -} - -/* - * CPC700 PIC interrupt programming table - * - * First entry is the sensitivity (level/edge), second is the polarity. - */ -unsigned int cpc700_irq_assigns[32][2] = { - { 1, 1 }, /* IRQ 0: ECC Correctable Error - rising edge */ - { 1, 1 }, /* IRQ 1: PCI Write Mem Range - rising edge */ - { 0, 1 }, /* IRQ 2: PCI Write Command Reg - active high */ - { 0, 1 }, /* IRQ 3: UART 0 - active high */ - { 0, 1 }, /* IRQ 4: UART 1 - active high */ - { 0, 1 }, /* IRQ 5: ICC 0 - active high */ - { 0, 1 }, /* IRQ 6: ICC 1 - active high */ - { 0, 1 }, /* IRQ 7: GPT Compare 0 - active high */ - { 0, 1 }, /* IRQ 8: GPT Compare 1 - active high */ - { 0, 1 }, /* IRQ 9: GPT Compare 2 - active high */ - { 0, 1 }, /* IRQ 10: GPT Compare 3 - active high */ - { 0, 1 }, /* IRQ 11: GPT Compare 4 - active high */ - { 0, 1 }, /* IRQ 12: GPT Capture 0 - active high */ - { 0, 1 }, /* IRQ 13: GPT Capture 1 - active high */ - { 0, 1 }, /* IRQ 14: GPT Capture 2 - active high */ - { 0, 1 }, /* IRQ 15: GPT Capture 3 - active high */ - { 0, 1 }, /* IRQ 16: GPT Capture 4 - active high */ - { 0, 0 }, /* IRQ 17: Reserved */ - { 0, 0 }, /* IRQ 18: Reserved */ - { 0, 0 }, /* IRQ 19: Reserved */ - { 0, 1 }, /* IRQ 20: FPGA EXT_IRQ0 - active high */ - { 1, 1 }, /* IRQ 21: Mouse - rising edge */ - { 1, 1 }, /* IRQ 22: Keyboard - rising edge */ - { 0, 0 }, /* IRQ 23: PCI Slot 3 - active low */ - { 0, 0 }, /* IRQ 24: PCI Slot 2 - active low */ - { 0, 0 }, /* IRQ 25: PCI Slot 1 - active low */ - { 0, 0 }, /* IRQ 26: PCI Slot 0 - active low */ -}; - -static void __init -spruce_calibrate_decr(void) -{ - int freq, divisor = 4; - - /* determine processor bus speed */ - freq = SPRUCE_BUS_SPEED; - tb_ticks_per_jiffy = freq / HZ / divisor; - tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000); -} - -static int -spruce_show_cpuinfo(struct seq_file *m) -{ - seq_printf(m, "vendor\t\t: IBM\n"); - seq_printf(m, "machine\t\t: Spruce\n"); - - return 0; -} - -static void __init -spruce_early_serial_map(void) -{ - u32 uart_clk; - struct uart_port serial_req; - - if (SPRUCE_UARTCLK_IS_33M(readb(SPRUCE_FPGA_REG_A))) - uart_clk = SPRUCE_BAUD_33M * 16; - else - uart_clk = SPRUCE_BAUD_30M * 16; - - /* Setup serial port access */ - memset(&serial_req, 0, sizeof(serial_req)); - serial_req.uartclk = uart_clk; - serial_req.irq = UART0_INT; - serial_req.flags = UPF_BOOT_AUTOCONF; - serial_req.iotype = UPIO_MEM; - serial_req.membase = (u_char *)UART0_IO_BASE; - serial_req.regshift = 0; - -#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG) - gen550_init(0, &serial_req); -#endif -#ifdef CONFIG_SERIAL_8250 - if (early_serial_setup(&serial_req) != 0) - printk("Early serial init of port 0 failed\n"); -#endif - - /* Assume early_serial_setup() doesn't modify serial_req */ - serial_req.line = 1; - serial_req.irq = UART1_INT; - serial_req.membase = (u_char *)UART1_IO_BASE; - -#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG) - gen550_init(1, &serial_req); -#endif -#ifdef CONFIG_SERIAL_8250 - if (early_serial_setup(&serial_req) != 0) - printk("Early serial init of port 1 failed\n"); -#endif -} - -TODC_ALLOC(); - -static void __init -spruce_setup_arch(void) -{ - /* Setup TODC access */ - TODC_INIT(TODC_TYPE_DS1643, 0, 0, SPRUCE_RTC_BASE_ADDR, 8); - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000 / HZ; - - /* Setup PCI host bridge */ - spruce_setup_hose(); - -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif -#ifdef CONFIG_ROOT_NFS - ROOT_DEV = Root_NFS; -#else - ROOT_DEV = Root_SDA1; -#endif - - /* Identify the system */ - printk(KERN_INFO "System Identification: IBM Spruce\n"); - printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n"); -} - -static void -spruce_restart(char *cmd) -{ - local_irq_disable(); - - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ - __asm__ __volatile__ - ("\n\ - lis 3,0xfff0 \n\ - ori 3,3,0x0100 \n\ - mtspr 26,3 \n\ - li 3,0 \n\ - mtspr 27,3 \n\ - rfi \n\ - "); - for(;;); -} - -static void -spruce_power_off(void) -{ - for(;;); -} - -static void -spruce_halt(void) -{ - spruce_restart(NULL); -} - -static void __init -spruce_map_io(void) -{ - io_block_mapping(SPRUCE_PCI_IO_BASE, SPRUCE_PCI_PHY_IO_BASE, - 0x08000000, _PAGE_IO); -} - -/* - * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1. - */ -static __inline__ void -spruce_set_bat(void) -{ - mb(); - mtspr(SPRN_DBAT1U, 0xf8000ffe); - mtspr(SPRN_DBAT1L, 0xf800002a); - mb(); -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* Map in board regs, etc. */ - spruce_set_bat(); - - isa_io_base = SPRUCE_ISA_IO_BASE; - pci_dram_offset = SPRUCE_PCI_SYS_MEM_BASE; - - ppc_md.setup_arch = spruce_setup_arch; - ppc_md.show_cpuinfo = spruce_show_cpuinfo; - ppc_md.init_IRQ = cpc700_init_IRQ; - ppc_md.get_irq = cpc700_get_irq; - - ppc_md.setup_io_mappings = spruce_map_io; - - ppc_md.restart = spruce_restart; - ppc_md.power_off = spruce_power_off; - ppc_md.halt = spruce_halt; - - ppc_md.time_init = todc_time_init; - ppc_md.set_rtc_time = todc_set_rtc_time; - ppc_md.get_rtc_time = todc_get_rtc_time; - ppc_md.calibrate_decr = spruce_calibrate_decr; - - ppc_md.nvram_read_val = todc_direct_read_val; - ppc_md.nvram_write_val = todc_direct_write_val; - - spruce_early_serial_map(); - -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ -#ifdef CONFIG_KGDB - ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; -#endif -} diff --git a/arch/ppc/platforms/spruce.h b/arch/ppc/platforms/spruce.h deleted file mode 100644 index f1f96f1de72a..000000000000 --- a/arch/ppc/platforms/spruce.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * arch/ppc/platforms/spruce.h - * - * Definitions for IBM Spruce reference board support - * - * Authors: Matt Porter and Johnnie Peters - * mporter@mvista.com - * jpeters@mvista.com - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_SPRUCE_H__ -#define __ASM_SPRUCE_H__ - -#define SPRUCE_PCI_CONFIG_ADDR 0xfec00000 -#define SPRUCE_PCI_CONFIG_DATA 0xfec00004 - -#define SPRUCE_PCI_PHY_IO_BASE 0xf8000000 -#define SPRUCE_PCI_IO_BASE SPRUCE_PCI_PHY_IO_BASE - -#define SPRUCE_PCI_SYS_MEM_BASE 0x00000000 - -#define SPRUCE_PCI_LOWER_MEM 0x80000000 -#define SPRUCE_PCI_UPPER_MEM 0x9fffffff -#define SPRUCE_PCI_LOWER_IO 0x00000000 -#define SPRUCE_PCI_UPPER_IO 0x03ffffff - -#define SPRUCE_ISA_IO_BASE SPRUCE_PCI_IO_BASE - -#define SPRUCE_MEM_SIZE 0x04000000 -#define SPRUCE_BUS_SPEED 66666667 - -#define SPRUCE_NVRAM_BASE_ADDR 0xff800000 -#define SPRUCE_RTC_BASE_ADDR SPRUCE_NVRAM_BASE_ADDR - -/* - * Serial port defines - */ -#define SPRUCE_FPGA_REG_A 0xff820000 -#define SPRUCE_UARTCLK_33M 0x02 -#define SPRUCE_UARTCLK_IS_33M(reg) (reg & SPRUCE_UARTCLK_33M) - -#define UART0_IO_BASE 0xff600300 -#define UART1_IO_BASE 0xff600400 - -#define RS_TABLE_SIZE 2 - -#define SPRUCE_BAUD_33M (33000000/64) -#define SPRUCE_BAUD_30M (30000000/64) -#define BASE_BAUD SPRUCE_BAUD_33M - -#define UART0_INT 3 -#define UART1_INT 4 - -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, UART##num##_INT, \ - ASYNC_BOOT_AUTOCONF, \ - iomem_base: (unsigned char *) UART##num##_IO_BASE, \ - io_type: SERIAL_IO_MEM}, - -#define SERIAL_PORT_DFNS \ - STD_UART_OP(0) \ - STD_UART_OP(1) - -#endif /* __ASM_SPRUCE_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/tqm8260.h b/arch/ppc/platforms/tqm8260.h deleted file mode 100644 index 7f8c9a6928f8..000000000000 --- a/arch/ppc/platforms/tqm8260.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * TQM8260 board specific definitions - * - * Copyright (c) 2001 Wolfgang Denk (wd@denx.de) - */ - -#ifndef __TQM8260_PLATFORM -#define __TQM8260_PLATFORM - - -#include - -#define CPM_MAP_ADDR ((uint)0xFFF00000) -#define PHY_INTERRUPT 25 - -/* For our show_cpuinfo hooks. */ -#define CPUINFO_VENDOR "IN2 Systems" -#define CPUINFO_MACHINE "TQM8260 PowerPC" - -#define BOOTROM_RESTART_ADDR ((uint)0x40000104) - -#endif /* __TQM8260_PLATFORM */ diff --git a/arch/ppc/platforms/tqm8260_setup.c b/arch/ppc/platforms/tqm8260_setup.c deleted file mode 100644 index b766339f44ac..000000000000 --- a/arch/ppc/platforms/tqm8260_setup.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * TQM8260 platform support - * - * Author: Allen Curtis - * Derived from: m8260_setup.c by Dan Malek, MVista - * - * Copyright 2002 Ones and Zeros, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include - -#include -#include -#include - -static int -tqm8260_set_rtc_time(unsigned long time) -{ - ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt = time; - ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcntsc = 0x3; - - return(0); -} - -static unsigned long -tqm8260_get_rtc_time(void) -{ - return ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt; -} - -void __init -m82xx_board_init(void) -{ - /* Anything special for this platform */ - ppc_md.set_rtc_time = tqm8260_set_rtc_time; - ppc_md.get_rtc_time = tqm8260_get_rtc_time; -} diff --git a/arch/ppc/platforms/tqm8xx.h b/arch/ppc/platforms/tqm8xx.h deleted file mode 100644 index 662131d0eb39..000000000000 --- a/arch/ppc/platforms/tqm8xx.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * TQM8xx(L) board specific definitions - * - * Copyright (c) 1999-2002 Wolfgang Denk (wd@denx.de) - */ - -#ifdef __KERNEL__ -#ifndef __MACH_TQM8xx_H -#define __MACH_TQM8xx_H - - -#include - -#ifndef __ASSEMBLY__ -#define TQM_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */ -#define TQM_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR TQM_IMMR_BASE /* physical base address of IMMR area */ -#define IMAP_SIZE TQM_IMAP_SIZE /* mapped size of IMMR area */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define PCMCIA_MEM_SIZE ( 64 << 20 ) - -#ifndef CONFIG_KUP4K -# define MAX_HWIFS 1 /* overwrite default in include/asm-ppc/ide.h */ - -#else /* CONFIG_KUP4K */ - -# define MAX_HWIFS 2 /* overwrite default in include/asm-ppc/ide.h */ -# ifndef __ASSEMBLY__ -# include -static __inline__ void ide_led(int on) -{ - volatile immap_t *immap = (immap_t *)IMAP_ADDR; - - if (on) { - immap->im_ioport.iop_padat &= ~0x80; - } else { - immap->im_ioport.iop_padat |= 0x80; - } -} -# endif /* __ASSEMBLY__ */ -# define IDE_LED(x) ide_led((x)) -#endif /* CONFIG_KUP4K */ - -/* - * Definitions for IDE0 Interface - */ -#define IDE0_BASE_OFFSET 0 -#define IDE0_DATA_REG_OFFSET (PCMCIA_MEM_SIZE + 0x320) -#define IDE0_ERROR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 1) -#define IDE0_NSECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 2) -#define IDE0_SECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 3) -#define IDE0_LCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 4) -#define IDE0_HCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 5) -#define IDE0_SELECT_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 6) -#define IDE0_STATUS_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 7) -#define IDE0_CONTROL_REG_OFFSET 0x0106 -#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */ - -/* define IO_BASE for PCMCIA */ -#define _IO_BASE 0x80000000 -#define _IO_BASE_SIZE (64<<10) - -#define FEC_INTERRUPT 9 /* = SIU_LEVEL4 */ -#define PHY_INTERRUPT 12 /* = IRQ6 */ -#define IDE0_INTERRUPT 13 - -#ifdef CONFIG_IDE -#endif - -/*----------------------------------------------------------------------- - * CPM Ethernet through SCCx. - *----------------------------------------------------------------------- - * - */ - -/*** TQM823L, TQM850L ***********************************************/ - -#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) -#endif /* CONFIG_TQM823L, CONFIG_TQM850L */ - -/*** TQM860L ********************************************************/ - -#ifdef CONFIG_TQM860L -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x00000026) -#endif /* CONFIG_TQM860L */ - -/*** FPS850L *********************************************************/ - -#ifdef CONFIG_FPS850L -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) -#endif /* CONFIG_FPS850L */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* !__ASSEMBLY__ */ -#endif /* __MACH_TQM8xx_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile deleted file mode 100644 index 52ddebe6c6d1..000000000000 --- a/arch/ppc/syslib/Makefile +++ /dev/null @@ -1,96 +0,0 @@ -# -# Makefile for the linux kernel. -# - -CFLAGS_prom_init.o += -fPIC -CFLAGS_btext.o += -fPIC - -wdt-mpc8xx-$(CONFIG_8xx_WDT) += m8xx_wdt.o - -obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o -obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o -obj-$(CONFIG_PPC_OCP) += ocp.o -obj-$(CONFIG_IBM_OCP) += ibm_ocp.o -obj-$(CONFIG_44x) += ibm44x_common.o -obj-$(CONFIG_440EP) += ibm440gx_common.o -obj-$(CONFIG_440GP) += ibm440gp_common.o -obj-$(CONFIG_440GX) += ibm440gx_common.o -obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o -obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o -ifeq ($(CONFIG_4xx),y) -ifeq ($(CONFIG_XILINX_VIRTEX),y) -obj-$(CONFIG_40x) += xilinx_pic.o -obj-y += virtex_devices.o -else -ifeq ($(CONFIG_403),y) -obj-$(CONFIG_40x) += ppc403_pic.o -else -obj-$(CONFIG_40x) += ppc4xx_pic.o -endif -endif -obj-$(CONFIG_44x) += ppc4xx_pic.o -obj-$(CONFIG_40x) += ppc4xx_setup.o -obj-$(CONFIG_GEN_RTC) += todc_time.o -obj-$(CONFIG_PPC4xx_DMA) += ppc4xx_dma.o -obj-$(CONFIG_PPC4xx_EDMA) += ppc4xx_sgdma.o -ifeq ($(CONFIG_40x),y) -obj-$(CONFIG_PCI) += pci_auto.o ppc405_pci.o -endif -endif -obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \ - ppc_sys.o mpc8xx_devices.o mpc8xx_sys.o -obj-$(CONFIG_PCI_QSPAN) += qspan_pci.o -obj-$(CONFIG_PPC_PREP) += open_pic.o todc_time.o -obj-$(CONFIG_BAMBOO) += pci_auto.o todc_time.o -obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o -obj-$(CONFIG_EBONY) += pci_auto.o todc_time.o -obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o -obj-$(CONFIG_EV64360) += todc_time.o -obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o -obj-$(CONFIG_GT64260) += gt64260_pic.o -obj-$(CONFIG_LOPEC) += pci_auto.o todc_time.o -obj-$(CONFIG_HDPU) += pci_auto.o -obj-$(CONFIG_LUAN) += pci_auto.o todc_time.o -obj-$(CONFIG_YUCCA) += pci_auto.o todc_time.o -obj-$(CONFIG_KATANA) += pci_auto.o -obj-$(CONFIG_MV64360) += mv64360_pic.o -obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o -obj-$(CONFIG_MVME5100) += open_pic.o todc_time.o \ - pci_auto.o hawk_common.o -obj-$(CONFIG_OCOTEA) += pci_auto.o todc_time.o -obj-$(CONFIG_PAL4) += cpc700_pic.o -obj-$(CONFIG_POWERPMC250) += pci_auto.o -obj-$(CONFIG_PPLUS) += hawk_common.o open_pic.o \ - todc_time.o pci_auto.o -obj-$(CONFIG_PRPMC750) += open_pic.o pci_auto.o \ - hawk_common.o -obj-$(CONFIG_HARRIER) += harrier.o -obj-$(CONFIG_PRPMC800) += open_pic.o pci_auto.o -obj-$(CONFIG_RADSTONE_PPC7D) += pci_auto.o -obj-$(CONFIG_SANDPOINT) += pci_auto.o todc_time.o -obj-$(CONFIG_SBC82xx) += todc_time.o -obj-$(CONFIG_SPRUCE) += cpc700_pic.o pci_auto.o \ - todc_time.o -obj-$(CONFIG_TAISHAN) += pci_auto.o -obj-$(CONFIG_8260) += m8260_setup.o pq2_devices.o pq2_sys.o \ - ppc_sys.o -obj-$(CONFIG_PCI_8260) += m82xx_pci.o pci_auto.o -obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o -obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o -ifeq ($(CONFIG_PPC_GEN550),y) -obj-$(CONFIG_KGDB) += gen550_kgdb.o gen550_dbg.o -obj-$(CONFIG_SERIAL_TEXT_DEBUG) += gen550_dbg.o -endif -ifeq ($(CONFIG_SERIAL_MPSC_CONSOLE),y) -obj-$(CONFIG_SERIAL_TEXT_DEBUG) += mv64x60_dbg.o -endif -obj-$(CONFIG_BOOTX_TEXT) += btext.o -obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o ppc_sys.o -obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o -obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ - mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o -ifeq ($(CONFIG_PPC_MPC52xx),y) -obj-$(CONFIG_PCI) += mpc52xx_pci.o -endif - -obj-$(CONFIG_PPC_I8259) += i8259.o diff --git a/arch/ppc/syslib/btext.c b/arch/ppc/syslib/btext.c deleted file mode 100644 index d11667046f21..000000000000 --- a/arch/ppc/syslib/btext.c +++ /dev/null @@ -1,860 +0,0 @@ -/* - * Procedures for drawing on the screen early on in the boot process. - * - * Benjamin Herrenschmidt - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define NO_SCROLL - -#ifndef NO_SCROLL -static void scrollscreen(void); -#endif - -static void draw_byte(unsigned char c, long locX, long locY); -static void draw_byte_32(unsigned char *bits, unsigned long *base, int rb); -static void draw_byte_16(unsigned char *bits, unsigned long *base, int rb); -static void draw_byte_8(unsigned char *bits, unsigned long *base, int rb); - -static int g_loc_X; -static int g_loc_Y; -static int g_max_loc_X; -static int g_max_loc_Y; - -unsigned long disp_BAT[2] __initdata = {0, 0}; - -#define cmapsz (16*256) - -static unsigned char vga_font[cmapsz]; - -int boot_text_mapped; -int force_printk_to_btext = 0; - -boot_infos_t disp_bi; - -extern char *klimit; - -/* - * Powermac can use btext_* after boot for xmon, - * chrp only uses it during early boot. - */ -#ifdef CONFIG_XMON -#define BTEXT -#define BTDATA -#else -#define BTEXT __init -#define BTDATA __initdata -#endif /* CONFIG_XMON */ - -/* - * This is called only when we are booted via BootX. - */ -void __init -btext_init(boot_infos_t *bi) -{ - g_loc_X = 0; - g_loc_Y = 0; - g_max_loc_X = (bi->dispDeviceRect[2] - bi->dispDeviceRect[0]) / 8; - g_max_loc_Y = (bi->dispDeviceRect[3] - bi->dispDeviceRect[1]) / 16; - disp_bi = *bi; - boot_text_mapped = 1; -} - -void __init -btext_welcome(void) -{ - unsigned long flags; - unsigned long pvr; - boot_infos_t* bi = &disp_bi; - - btext_drawstring("Welcome to Linux, kernel " UTS_RELEASE "\n"); - btext_drawstring("\nlinked at : 0x"); - btext_drawhex(KERNELBASE); - btext_drawstring("\nframe buffer at : 0x"); - btext_drawhex((unsigned long)bi->dispDeviceBase); - btext_drawstring(" (phys), 0x"); - btext_drawhex((unsigned long)bi->logicalDisplayBase); - btext_drawstring(" (log)"); - btext_drawstring("\nklimit : 0x"); - btext_drawhex((unsigned long)klimit); - btext_drawstring("\nMSR : 0x"); - __asm__ __volatile__ ("mfmsr %0" : "=r" (flags)); - btext_drawhex(flags); - __asm__ __volatile__ ("mfspr %0, 287" : "=r" (pvr)); - pvr >>= 16; - if (pvr > 1) { - btext_drawstring("\nHID0 : 0x"); - __asm__ __volatile__ ("mfspr %0, 1008" : "=r" (flags)); - btext_drawhex(flags); - } - if (pvr == 8 || pvr == 12 || pvr == 0x800c) { - btext_drawstring("\nICTC : 0x"); - __asm__ __volatile__ ("mfspr %0, 1019" : "=r" (flags)); - btext_drawhex(flags); - } - btext_drawstring("\n\n"); -} - -/* Calc BAT values for mapping the display and store them - * in disp_BAT. Those values are then used from head.S to map - * the display during identify_machine() and MMU_Init() - * - * The display is mapped to virtual address 0xD0000000, rather - * than 1:1, because some some CHRP machines put the frame buffer - * in the region starting at 0xC0000000 (KERNELBASE). - * This mapping is temporary and will disappear as soon as the - * setup done by MMU_Init() is applied. - * - * For now, we align the BAT and then map 8Mb on 601 and 16Mb - * on other PPCs. This may cause trouble if the framebuffer - * is really badly aligned, but I didn't encounter this case - * yet. - */ -void __init -btext_prepare_BAT(void) -{ - boot_infos_t* bi = &disp_bi; - unsigned long vaddr = KERNELBASE + 0x10000000; - unsigned long addr; - unsigned long lowbits; - - addr = (unsigned long)bi->dispDeviceBase; - if (!addr) { - boot_text_mapped = 0; - return; - } - if (PVR_VER(mfspr(SPRN_PVR)) != 1) { - /* 603, 604, G3, G4, ... */ - lowbits = addr & ~0xFF000000UL; - addr &= 0xFF000000UL; - disp_BAT[0] = vaddr | (BL_16M<<2) | 2; - disp_BAT[1] = addr | (_PAGE_NO_CACHE | _PAGE_GUARDED | BPP_RW); - } else { - /* 601 */ - lowbits = addr & ~0xFF800000UL; - addr &= 0xFF800000UL; - disp_BAT[0] = vaddr | (_PAGE_NO_CACHE | PP_RWXX) | 4; - disp_BAT[1] = addr | BL_8M | 0x40; - } - bi->logicalDisplayBase = (void *) (vaddr + lowbits); -} - -/* This function will enable the early boot text when doing OF booting. This - * way, xmon output should work too - */ -void __init -btext_setup_display(int width, int height, int depth, int pitch, - unsigned long address) -{ - boot_infos_t* bi = &disp_bi; - - g_loc_X = 0; - g_loc_Y = 0; - g_max_loc_X = width / 8; - g_max_loc_Y = height / 16; - bi->logicalDisplayBase = (unsigned char *)address; - bi->dispDeviceBase = (unsigned char *)address; - bi->dispDeviceRowBytes = pitch; - bi->dispDeviceDepth = depth; - bi->dispDeviceRect[0] = bi->dispDeviceRect[1] = 0; - bi->dispDeviceRect[2] = width; - bi->dispDeviceRect[3] = height; - boot_text_mapped = 1; -} - -/* Here's a small text engine to use during early boot - * or for debugging purposes - * - * todo: - * - * - build some kind of vgacon with it to enable early printk - * - move to a separate file - * - add a few video driver hooks to keep in sync with display - * changes. - */ - -void -map_boot_text(void) -{ - unsigned long base, offset, size; - boot_infos_t *bi = &disp_bi; - unsigned char *vbase; - - /* By default, we are no longer mapped */ - boot_text_mapped = 0; - if (bi->dispDeviceBase == 0) - return; - base = ((unsigned long) bi->dispDeviceBase) & 0xFFFFF000UL; - offset = ((unsigned long) bi->dispDeviceBase) - base; - size = bi->dispDeviceRowBytes * bi->dispDeviceRect[3] + offset - + bi->dispDeviceRect[0]; - vbase = ioremap(base, size); - if (vbase == 0) - return; - bi->logicalDisplayBase = vbase + offset; - boot_text_mapped = 1; -} - -/* Calc the base address of a given point (x,y) */ -static unsigned char * BTEXT -calc_base(boot_infos_t *bi, int x, int y) -{ - unsigned char *base; - - base = bi->logicalDisplayBase; - if (base == 0) - base = bi->dispDeviceBase; - base += (x + bi->dispDeviceRect[0]) * (bi->dispDeviceDepth >> 3); - base += (y + bi->dispDeviceRect[1]) * bi->dispDeviceRowBytes; - return base; -} - -/* Adjust the display to a new resolution */ -void -btext_update_display(unsigned long phys, int width, int height, - int depth, int pitch) -{ - boot_infos_t *bi = &disp_bi; - - if (bi->dispDeviceBase == 0) - return; - - /* check it's the same frame buffer (within 256MB) */ - if ((phys ^ (unsigned long)bi->dispDeviceBase) & 0xf0000000) - return; - - bi->dispDeviceBase = (__u8 *) phys; - bi->dispDeviceRect[0] = 0; - bi->dispDeviceRect[1] = 0; - bi->dispDeviceRect[2] = width; - bi->dispDeviceRect[3] = height; - bi->dispDeviceDepth = depth; - bi->dispDeviceRowBytes = pitch; - if (boot_text_mapped) { - iounmap(bi->logicalDisplayBase); - boot_text_mapped = 0; - } - map_boot_text(); - g_loc_X = 0; - g_loc_Y = 0; - g_max_loc_X = width / 8; - g_max_loc_Y = height / 16; -} - -void BTEXT btext_clearscreen(void) -{ - boot_infos_t* bi = &disp_bi; - unsigned long *base = (unsigned long *)calc_base(bi, 0, 0); - unsigned long width = ((bi->dispDeviceRect[2] - bi->dispDeviceRect[0]) * - (bi->dispDeviceDepth >> 3)) >> 2; - int i,j; - - for (i=0; i<(bi->dispDeviceRect[3] - bi->dispDeviceRect[1]); i++) - { - unsigned long *ptr = base; - for(j=width; j; --j) - *(ptr++) = 0; - base += (bi->dispDeviceRowBytes >> 2); - } -} - -__inline__ void dcbst(const void* addr) -{ - __asm__ __volatile__ ("dcbst 0,%0" :: "r" (addr)); -} - -void BTEXT btext_flushscreen(void) -{ - boot_infos_t* bi = &disp_bi; - unsigned long *base = (unsigned long *)calc_base(bi, 0, 0); - unsigned long width = ((bi->dispDeviceRect[2] - bi->dispDeviceRect[0]) * - (bi->dispDeviceDepth >> 3)) >> 2; - int i,j; - - for (i=0; i<(bi->dispDeviceRect[3] - bi->dispDeviceRect[1]); i++) - { - unsigned long *ptr = base; - for(j=width; j>0; j-=8) { - dcbst(ptr); - ptr += 8; - } - base += (bi->dispDeviceRowBytes >> 2); - } -} - -#ifndef NO_SCROLL -static BTEXT void -scrollscreen(void) -{ - boot_infos_t* bi = &disp_bi; - unsigned long *src = (unsigned long *)calc_base(bi,0,16); - unsigned long *dst = (unsigned long *)calc_base(bi,0,0); - unsigned long width = ((bi->dispDeviceRect[2] - bi->dispDeviceRect[0]) * - (bi->dispDeviceDepth >> 3)) >> 2; - int i,j; - -#ifdef CONFIG_ADB_PMU - pmu_suspend(); /* PMU will not shut us down ! */ -#endif - for (i=0; i<(bi->dispDeviceRect[3] - bi->dispDeviceRect[1] - 16); i++) - { - unsigned long *src_ptr = src; - unsigned long *dst_ptr = dst; - for(j=width; j; --j) - *(dst_ptr++) = *(src_ptr++); - src += (bi->dispDeviceRowBytes >> 2); - dst += (bi->dispDeviceRowBytes >> 2); - } - for (i=0; i<16; i++) - { - unsigned long *dst_ptr = dst; - for(j=width; j; --j) - *(dst_ptr++) = 0; - dst += (bi->dispDeviceRowBytes >> 2); - } -#ifdef CONFIG_ADB_PMU - pmu_resume(); /* PMU will not shut us down ! */ -#endif -} -#endif /* ndef NO_SCROLL */ - -void BTEXT btext_drawchar(char c) -{ - int cline = 0, x; - - if (!boot_text_mapped) - return; - - switch (c) { - case '\b': - if (g_loc_X > 0) - --g_loc_X; - break; - case '\t': - g_loc_X = (g_loc_X & -8) + 8; - break; - case '\r': - g_loc_X = 0; - break; - case '\n': - g_loc_X = 0; - g_loc_Y++; - cline = 1; - break; - default: - draw_byte(c, g_loc_X++, g_loc_Y); - } - if (g_loc_X >= g_max_loc_X) { - g_loc_X = 0; - g_loc_Y++; - cline = 1; - } -#ifndef NO_SCROLL - while (g_loc_Y >= g_max_loc_Y) { - scrollscreen(); - g_loc_Y--; - } -#else - /* wrap around from bottom to top of screen so we don't - waste time scrolling each line. -- paulus. */ - if (g_loc_Y >= g_max_loc_Y) - g_loc_Y = 0; - if (cline) { - for (x = 0; x < g_max_loc_X; ++x) - draw_byte(' ', x, g_loc_Y); - } -#endif -} - -void BTEXT -btext_drawstring(const char *c) -{ - if (!boot_text_mapped) - return; - while (*c) - btext_drawchar(*c++); -} - -void BTEXT -btext_drawhex(unsigned long v) -{ - static char hex_table[] = "0123456789abcdef"; - - if (!boot_text_mapped) - return; - btext_drawchar(hex_table[(v >> 28) & 0x0000000FUL]); - btext_drawchar(hex_table[(v >> 24) & 0x0000000FUL]); - btext_drawchar(hex_table[(v >> 20) & 0x0000000FUL]); - btext_drawchar(hex_table[(v >> 16) & 0x0000000FUL]); - btext_drawchar(hex_table[(v >> 12) & 0x0000000FUL]); - btext_drawchar(hex_table[(v >> 8) & 0x0000000FUL]); - btext_drawchar(hex_table[(v >> 4) & 0x0000000FUL]); - btext_drawchar(hex_table[(v >> 0) & 0x0000000FUL]); - btext_drawchar(' '); -} - -static void BTEXT -draw_byte(unsigned char c, long locX, long locY) -{ - boot_infos_t* bi = &disp_bi; - unsigned char *base = calc_base(bi, locX << 3, locY << 4); - unsigned char *font = &vga_font[((unsigned long)c) * 16]; - int rb = bi->dispDeviceRowBytes; - - switch(bi->dispDeviceDepth) { - case 24: - case 32: - draw_byte_32(font, (unsigned long *)base, rb); - break; - case 15: - case 16: - draw_byte_16(font, (unsigned long *)base, rb); - break; - case 8: - draw_byte_8(font, (unsigned long *)base, rb); - break; - } -} - -static unsigned long expand_bits_8[16] BTDATA = { - 0x00000000, - 0x000000ff, - 0x0000ff00, - 0x0000ffff, - 0x00ff0000, - 0x00ff00ff, - 0x00ffff00, - 0x00ffffff, - 0xff000000, - 0xff0000ff, - 0xff00ff00, - 0xff00ffff, - 0xffff0000, - 0xffff00ff, - 0xffffff00, - 0xffffffff -}; - -static unsigned long expand_bits_16[4] BTDATA = { - 0x00000000, - 0x0000ffff, - 0xffff0000, - 0xffffffff -}; - - -static void BTEXT -draw_byte_32(unsigned char *font, unsigned long *base, int rb) -{ - int l, bits; - int fg = 0xFFFFFFFFUL; - int bg = 0x00000000UL; - - for (l = 0; l < 16; ++l) - { - bits = *font++; - base[0] = (-(bits >> 7) & fg) ^ bg; - base[1] = (-((bits >> 6) & 1) & fg) ^ bg; - base[2] = (-((bits >> 5) & 1) & fg) ^ bg; - base[3] = (-((bits >> 4) & 1) & fg) ^ bg; - base[4] = (-((bits >> 3) & 1) & fg) ^ bg; - base[5] = (-((bits >> 2) & 1) & fg) ^ bg; - base[6] = (-((bits >> 1) & 1) & fg) ^ bg; - base[7] = (-(bits & 1) & fg) ^ bg; - base = (unsigned long *) ((char *)base + rb); - } -} - -static void BTEXT -draw_byte_16(unsigned char *font, unsigned long *base, int rb) -{ - int l, bits; - int fg = 0xFFFFFFFFUL; - int bg = 0x00000000UL; - unsigned long *eb = expand_bits_16; - - for (l = 0; l < 16; ++l) - { - bits = *font++; - base[0] = (eb[bits >> 6] & fg) ^ bg; - base[1] = (eb[(bits >> 4) & 3] & fg) ^ bg; - base[2] = (eb[(bits >> 2) & 3] & fg) ^ bg; - base[3] = (eb[bits & 3] & fg) ^ bg; - base = (unsigned long *) ((char *)base + rb); - } -} - -static void BTEXT -draw_byte_8(unsigned char *font, unsigned long *base, int rb) -{ - int l, bits; - int fg = 0x0F0F0F0FUL; - int bg = 0x00000000UL; - unsigned long *eb = expand_bits_8; - - for (l = 0; l < 16; ++l) - { - bits = *font++; - base[0] = (eb[bits >> 4] & fg) ^ bg; - base[1] = (eb[bits & 0xf] & fg) ^ bg; - base = (unsigned long *) ((char *)base + rb); - } -} - -static unsigned char vga_font[cmapsz] BTDATA = { -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x81, 0xa5, 0x81, 0x81, 0xbd, -0x99, 0x81, 0x81, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0xff, -0xdb, 0xff, 0xff, 0xc3, 0xe7, 0xff, 0xff, 0x7e, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x6c, 0xfe, 0xfe, 0xfe, 0xfe, 0x7c, 0x38, 0x10, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x7c, 0xfe, -0x7c, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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Greer - * mgreer@mvista.com - * - * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * This file contains the defines and macros for the IBM CPC700 host bridge, - * memory controller, PIC, UARTs, IIC, and Timers. - */ - -#ifndef __PPC_SYSLIB_CPC700_H__ -#define __PPC_SYSLIB_CPC700_H__ - -#include -#include -#include - -/* XXX no barriers? not even any volatiles? -- paulus */ -#define CPC700_OUT_32(a,d) (*(u_int *)a = d) -#define CPC700_IN_32(a) (*(u_int *)a) - -/* - * PCI Section - */ -#define CPC700_PCI_CONFIG_ADDR 0xfec00000 -#define CPC700_PCI_CONFIG_DATA 0xfec00004 - -/* CPU -> PCI memory window 0 */ -#define CPC700_PMM0_LOCAL 0xff400000 /* CPU physical addr */ -#define CPC700_PMM0_MASK_ATTR 0xff400004 /* size and attrs */ -#define CPC700_PMM0_PCI_LOW 0xff400008 /* PCI addr, low word */ -#define CPC700_PMM0_PCI_HIGH 0xff40000c /* PCI addr, high wd */ -/* CPU -> PCI memory window 1 */ -#define CPC700_PMM1_LOCAL 0xff400010 -#define CPC700_PMM1_MASK_ATTR 0xff400014 -#define CPC700_PMM1_PCI_LOW 0xff400018 -#define CPC700_PMM1_PCI_HIGH 0xff40001c -/* CPU -> PCI memory window 2 */ -#define CPC700_PMM2_LOCAL 0xff400020 -#define CPC700_PMM2_MASK_ATTR 0xff400024 -#define CPC700_PMM2_PCI_LOW 0xff400028 -#define CPC700_PMM2_PCI_HIGH 0xff40002c -/* PCI memory -> CPU window 1 */ -#define CPC700_PTM1_MEMSIZE 0xff400030 /* window size */ -#define CPC700_PTM1_LOCAL 0xff400034 /* CPU phys addr */ -/* PCI memory -> CPU window 2 */ -#define CPC700_PTM2_MEMSIZE 0xff400038 /* size and enable */ -#define CPC700_PTM2_LOCAL 0xff40003c - -/* - * PIC Section - * - * IBM calls the CPC700's programmable interrupt controller the Universal - * Interrupt Controller or UIC. - */ - -/* - * UIC Register Addresses. - */ -#define CPC700_UIC_UICSR 0xff500880 /* Status Reg (Rd/Clr)*/ -#define CPC700_UIC_UICSRS 0xff500884 /* Status Reg (Set) */ -#define CPC700_UIC_UICER 0xff500888 /* Enable Reg */ -#define CPC700_UIC_UICCR 0xff50088c /* Critical Reg */ -#define CPC700_UIC_UICPR 0xff500890 /* Polarity Reg */ -#define CPC700_UIC_UICTR 0xff500894 /* Trigger Reg */ -#define CPC700_UIC_UICMSR 0xff500898 /* Masked Status Reg */ -#define CPC700_UIC_UICVR 0xff50089c /* Vector Reg */ -#define CPC700_UIC_UICVCR 0xff5008a0 /* Vector Config Reg */ - -#define CPC700_UIC_UICER_ENABLE 0x00000001 /* Enable an IRQ */ - -#define CPC700_UIC_UICVCR_31_HI 0x00000000 /* IRQ 31 hi priority */ -#define CPC700_UIC_UICVCR_0_HI 0x00000001 /* IRQ 0 hi priority */ -#define CPC700_UIC_UICVCR_BASE_MASK 0xfffffffc -#define CPC700_UIC_UICVCR_ORDER_MASK 0x00000001 - -/* Specify value of a bit for an IRQ. */ -#define CPC700_UIC_IRQ_BIT(i) ((0x00000001) << (31 - (i))) - -/* - * UIC Exports... - */ -extern struct hw_interrupt_type cpc700_pic; -extern unsigned int cpc700_irq_assigns[32][2]; - -extern void __init cpc700_init_IRQ(void); -extern int cpc700_get_irq(void); - -#endif /* __PPC_SYSLIB_CPC700_H__ */ diff --git a/arch/ppc/syslib/cpc700_pic.c b/arch/ppc/syslib/cpc700_pic.c deleted file mode 100644 index d48e8f45c050..000000000000 --- a/arch/ppc/syslib/cpc700_pic.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Interrupt controller support for IBM Spruce - * - * Authors: Mark Greer, Matt Porter, and Johnnie Peters - * mgreer@mvista.com - * mporter@mvista.com - * jpeters@mvista.com - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "cpc700.h" - -static void -cpc700_unmask_irq(unsigned int irq) -{ - unsigned int tr_bits; - - /* - * IRQ 31 is largest IRQ supported. - * IRQs 17-19 are reserved. - */ - if ((irq <= 31) && ((irq < 17) || (irq > 19))) { - tr_bits = CPC700_IN_32(CPC700_UIC_UICTR); - - if ((tr_bits & (1 << (31 - irq))) == 0) { - /* level trigger interrupt, clear bit in status - * register */ - CPC700_OUT_32(CPC700_UIC_UICSR, 1 << (31 - irq)); - } - - /* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */ - ppc_cached_irq_mask[0] |= CPC700_UIC_IRQ_BIT(irq); - - CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]); - } - return; -} - -static void -cpc700_mask_irq(unsigned int irq) -{ - /* - * IRQ 31 is largest IRQ supported. - * IRQs 17-19 are reserved. - */ - if ((irq <= 31) && ((irq < 17) || (irq > 19))) { - /* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */ - ppc_cached_irq_mask[0] &= - ~CPC700_UIC_IRQ_BIT(irq); - - CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]); - } - return; -} - -static void -cpc700_mask_and_ack_irq(unsigned int irq) -{ - u_int bit; - - /* - * IRQ 31 is largest IRQ supported. - * IRQs 17-19 are reserved. - */ - if ((irq <= 31) && ((irq < 17) || (irq > 19))) { - /* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */ - bit = CPC700_UIC_IRQ_BIT(irq); - - ppc_cached_irq_mask[0] &= ~bit; - CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]); - CPC700_OUT_32(CPC700_UIC_UICSR, bit); /* Write 1 clears IRQ */ - } - return; -} - -static struct hw_interrupt_type cpc700_pic = { - .typename = "CPC700 PIC", - .enable = cpc700_unmask_irq, - .disable = cpc700_mask_irq, - .ack = cpc700_mask_and_ack_irq, -}; - -__init static void -cpc700_pic_init_irq(unsigned int irq) -{ - unsigned int tmp; - - /* Set interrupt sense */ - tmp = CPC700_IN_32(CPC700_UIC_UICTR); - if (cpc700_irq_assigns[irq][0] == 0) { - tmp &= ~CPC700_UIC_IRQ_BIT(irq); - } else { - tmp |= CPC700_UIC_IRQ_BIT(irq); - } - CPC700_OUT_32(CPC700_UIC_UICTR, tmp); - - /* Set interrupt polarity */ - tmp = CPC700_IN_32(CPC700_UIC_UICPR); - if (cpc700_irq_assigns[irq][1]) { - tmp |= CPC700_UIC_IRQ_BIT(irq); - } else { - tmp &= ~CPC700_UIC_IRQ_BIT(irq); - } - CPC700_OUT_32(CPC700_UIC_UICPR, tmp); - - /* Set interrupt critical */ - tmp = CPC700_IN_32(CPC700_UIC_UICCR); - tmp |= CPC700_UIC_IRQ_BIT(irq); - CPC700_OUT_32(CPC700_UIC_UICCR, tmp); - - return; -} - -__init void -cpc700_init_IRQ(void) -{ - int i; - - ppc_cached_irq_mask[0] = 0; - CPC700_OUT_32(CPC700_UIC_UICER, 0x00000000); /* Disable all irq's */ - CPC700_OUT_32(CPC700_UIC_UICSR, 0xffffffff); /* Clear cur intrs */ - CPC700_OUT_32(CPC700_UIC_UICCR, 0xffffffff); /* Gen INT not MCP */ - CPC700_OUT_32(CPC700_UIC_UICPR, 0x00000000); /* Active low */ - CPC700_OUT_32(CPC700_UIC_UICTR, 0x00000000); /* Level Sensitive */ - CPC700_OUT_32(CPC700_UIC_UICVR, CPC700_UIC_UICVCR_0_HI); - /* IRQ 0 is highest */ - - for (i = 0; i < 17; i++) { - irq_desc[i].chip = &cpc700_pic; - cpc700_pic_init_irq(i); - } - - for (i = 20; i < 32; i++) { - irq_desc[i].chip = &cpc700_pic; - cpc700_pic_init_irq(i); - } - - return; -} - - - -/* - * Find the highest IRQ that generating an interrupt, if any. - */ -int -cpc700_get_irq(void) -{ - int irq = 0; - u_int irq_status, irq_test = 1; - - irq_status = CPC700_IN_32(CPC700_UIC_UICMSR); - - do - { - if (irq_status & irq_test) - break; - irq++; - irq_test <<= 1; - } while (irq < NR_IRQS); - - - if (irq == NR_IRQS) - irq = 33; - - return (31 - irq); -} diff --git a/arch/ppc/syslib/cpm2_common.c b/arch/ppc/syslib/cpm2_common.c deleted file mode 100644 index 6cd859d7721f..000000000000 --- a/arch/ppc/syslib/cpm2_common.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * General Purpose functions for the global management of the - * 8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) - * 2.3.99 Updates - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void cpm2_dpinit(void); -cpm_cpm2_t *cpmp; /* Pointer to comm processor space */ - -/* We allocate this here because it is used almost exclusively for - * the communication processor devices. - */ -cpm2_map_t *cpm2_immr; - -#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount - of space for CPM as it is larger - than on PQ2 */ - -void -cpm2_reset(void) -{ - cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE); - - /* Reclaim the DP memory for our use. - */ - cpm2_dpinit(); - - /* Tell everyone where the comm processor resides. - */ - cpmp = &cpm2_immr->im_cpm; -} - -/* Set a baud rate generator. This needs lots of work. There are - * eight BRGs, which can be connected to the CPM channels or output - * as clocks. The BRGs are in two different block of internal - * memory mapped space. - * The baud rate clock is the system clock divided by something. - * It was set up long ago during the initial boot phase and is - * is given to us. - * Baud rate clocks are zero-based in the driver code (as that maps - * to port numbers). Documentation uses 1-based numbering. - */ -#define BRG_INT_CLK (((bd_t *)__res)->bi_brgfreq) -#define BRG_UART_CLK (BRG_INT_CLK/16) - -/* This function is used by UARTS, or anything else that uses a 16x - * oversampled clock. - */ -void -cpm_setbrg(uint brg, uint rate) -{ - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - if (brg < 4) { - bp = (uint *)&cpm2_immr->im_brgc1; - } - else { - bp = (uint *)&cpm2_immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN; -} - -/* This function is used to set high speed synchronous baud rate - * clocks. - */ -void -cpm2_fastbrg(uint brg, uint rate, int div16) -{ - volatile uint *bp; - - if (brg < 4) { - bp = (uint *)&cpm2_immr->im_brgc1; - } - else { - bp = (uint *)&cpm2_immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN; - if (div16) - *bp |= CPM_BRG_DIV16; -} - -/* - * dpalloc / dpfree bits. - */ -static spinlock_t cpm_dpmem_lock; -/* 16 blocks should be enough to satisfy all requests - * until the memory subsystem goes up... */ -static rh_block_t cpm_boot_dpmem_rh_block[16]; -static rh_info_t cpm_dpmem_info; - -static void cpm2_dpinit(void) -{ - spin_lock_init(&cpm_dpmem_lock); - - /* initialize the info header */ - rh_init(&cpm_dpmem_info, 1, - sizeof(cpm_boot_dpmem_rh_block) / - sizeof(cpm_boot_dpmem_rh_block[0]), - cpm_boot_dpmem_rh_block); - - /* Attach the usable dpmem area */ - /* XXX: This is actually crap. CPM_DATAONLY_BASE and - * CPM_DATAONLY_SIZE is only a subset of the available dpram. It - * varies with the processor and the microcode patches activated. - * But the following should be at least safe. - */ - rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE); -} - -/* This function returns an index into the DPRAM area. - */ -unsigned long cpm_dpalloc(uint size, uint align) -{ - unsigned long start; - unsigned long flags; - - spin_lock_irqsave(&cpm_dpmem_lock, flags); - cpm_dpmem_info.alignment = align; - start = rh_alloc(&cpm_dpmem_info, size, "commproc"); - spin_unlock_irqrestore(&cpm_dpmem_lock, flags); - - return start; -} -EXPORT_SYMBOL(cpm_dpalloc); - -int cpm_dpfree(unsigned long offset) -{ - int ret; - unsigned long flags; - - spin_lock_irqsave(&cpm_dpmem_lock, flags); - ret = rh_free(&cpm_dpmem_info, offset); - spin_unlock_irqrestore(&cpm_dpmem_lock, flags); - - return ret; -} -EXPORT_SYMBOL(cpm_dpfree); - -/* not sure if this is ever needed */ -unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align) -{ - unsigned long start; - unsigned long flags; - - spin_lock_irqsave(&cpm_dpmem_lock, flags); - cpm_dpmem_info.alignment = align; - start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc"); - spin_unlock_irqrestore(&cpm_dpmem_lock, flags); - - return start; -} -EXPORT_SYMBOL(cpm_dpalloc_fixed); - -void cpm_dpdump(void) -{ - rh_dump(&cpm_dpmem_info); -} -EXPORT_SYMBOL(cpm_dpdump); - -void *cpm_dpram_addr(unsigned long offset) -{ - return (void *)&cpm2_immr->im_dprambase[offset]; -} -EXPORT_SYMBOL(cpm_dpram_addr); diff --git a/arch/ppc/syslib/cpm2_pic.c b/arch/ppc/syslib/cpm2_pic.c deleted file mode 100644 index fb2d5842641a..000000000000 --- a/arch/ppc/syslib/cpm2_pic.c +++ /dev/null @@ -1,177 +0,0 @@ -/* The CPM2 internal interrupt controller. It is usually - * the only interrupt controller. - * There are two 32-bit registers (high/low) for up to 64 - * possible interrupts. - * - * Now, the fun starts.....Interrupt Numbers DO NOT MAP - * in a simple arithmetic fashion to mask or pending registers. - * That is, interrupt 4 does not map to bit position 4. - * We create two tables, indexed by vector number, to indicate - * which register to use and which bit in the register to use. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#include "cpm2_pic.h" - -static u_char irq_to_siureg[] = { - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -/* bit numbers do not match the docs, these are precomputed so the bit for - * a given irq is (1 << irq_to_siubit[irq]) */ -static u_char irq_to_siubit[] = { - 0, 15, 14, 13, 12, 11, 10, 9, - 8, 7, 6, 5, 4, 3, 2, 1, - 2, 1, 0, 14, 13, 12, 11, 10, - 9, 8, 7, 6, 5, 4, 3, 0, - 31, 30, 29, 28, 27, 26, 25, 24, - 23, 22, 21, 20, 19, 18, 17, 16, - 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, -}; - -static void cpm2_mask_irq(unsigned int irq_nr) -{ - int bit, word; - volatile uint *simr; - - irq_nr -= CPM_IRQ_OFFSET; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(cpm2_immr->im_intctl.ic_simrh); - ppc_cached_irq_mask[word] &= ~(1 << bit); - simr[word] = ppc_cached_irq_mask[word]; -} - -static void cpm2_unmask_irq(unsigned int irq_nr) -{ - int bit, word; - volatile uint *simr; - - irq_nr -= CPM_IRQ_OFFSET; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(cpm2_immr->im_intctl.ic_simrh); - ppc_cached_irq_mask[word] |= 1 << bit; - simr[word] = ppc_cached_irq_mask[word]; -} - -static void cpm2_mask_and_ack(unsigned int irq_nr) -{ - int bit, word; - volatile uint *simr, *sipnr; - - irq_nr -= CPM_IRQ_OFFSET; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(cpm2_immr->im_intctl.ic_simrh); - sipnr = &(cpm2_immr->im_intctl.ic_sipnrh); - ppc_cached_irq_mask[word] &= ~(1 << bit); - simr[word] = ppc_cached_irq_mask[word]; - sipnr[word] = 1 << bit; -} - -static void cpm2_end_irq(unsigned int irq_nr) -{ - int bit, word; - volatile uint *simr; - - if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)) - && irq_desc[irq_nr].action) { - - irq_nr -= CPM_IRQ_OFFSET; - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(cpm2_immr->im_intctl.ic_simrh); - ppc_cached_irq_mask[word] |= 1 << bit; - simr[word] = ppc_cached_irq_mask[word]; - /* - * Work around large numbers of spurious IRQs on PowerPC 82xx - * systems. - */ - mb(); - } -} - -static struct hw_interrupt_type cpm2_pic = { - .typename = " CPM2 SIU ", - .enable = cpm2_unmask_irq, - .disable = cpm2_mask_irq, - .ack = cpm2_mask_and_ack, - .end = cpm2_end_irq, -}; - -int cpm2_get_irq(void) -{ - int irq; - unsigned long bits; - - /* For CPM2, read the SIVEC register and shift the bits down - * to get the irq number. */ - bits = cpm2_immr->im_intctl.ic_sivec; - irq = bits >> 26; - - if (irq == 0) - return(-1); - return irq+CPM_IRQ_OFFSET; -} - -void cpm2_init_IRQ(void) -{ - int i; - - /* Clear the CPM IRQ controller, in case it has any bits set - * from the bootloader - */ - - /* Mask out everything */ - cpm2_immr->im_intctl.ic_simrh = 0x00000000; - cpm2_immr->im_intctl.ic_simrl = 0x00000000; - wmb(); - - /* Ack everything */ - cpm2_immr->im_intctl.ic_sipnrh = 0xffffffff; - cpm2_immr->im_intctl.ic_sipnrl = 0xffffffff; - wmb(); - - /* Dummy read of the vector */ - i = cpm2_immr->im_intctl.ic_sivec; - rmb(); - - /* Initialize the default interrupt mapping priorities, - * in case the boot rom changed something on us. - */ - cpm2_immr->im_intctl.ic_sicr = 0; - cpm2_immr->im_intctl.ic_scprrh = 0x05309770; - cpm2_immr->im_intctl.ic_scprrl = 0x05309770; - - - /* Enable chaining to OpenPIC, and make everything level - */ - for (i = 0; i < NR_CPM_INTS; i++) { - irq_desc[i+CPM_IRQ_OFFSET].chip = &cpm2_pic; - irq_desc[i+CPM_IRQ_OFFSET].status |= IRQ_LEVEL; - } -} diff --git a/arch/ppc/syslib/cpm2_pic.h b/arch/ppc/syslib/cpm2_pic.h deleted file mode 100644 index 467339337a78..000000000000 --- a/arch/ppc/syslib/cpm2_pic.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _PPC_KERNEL_CPM2_H -#define _PPC_KERNEL_CPM2_H - -extern int cpm2_get_irq(void); - -extern void cpm2_init_IRQ(void); - -#endif /* _PPC_KERNEL_CPM2_H */ diff --git a/arch/ppc/syslib/gen550.h b/arch/ppc/syslib/gen550.h deleted file mode 100644 index 5254d3cdbca6..000000000000 --- a/arch/ppc/syslib/gen550.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * gen550 prototypes - * - * Matt Porter - * - * 2004 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -extern void gen550_progress(char *, unsigned short); -extern void gen550_init(int, struct uart_port *); -extern void gen550_kgdb_map_scc(void); diff --git a/arch/ppc/syslib/gen550_dbg.c b/arch/ppc/syslib/gen550_dbg.c deleted file mode 100644 index 9293f5c59099..000000000000 --- a/arch/ppc/syslib/gen550_dbg.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * A library of polled 16550 serial routines. These are intended to - * be used to support progress messages, xmon, kgdb, etc. on a - * variety of platforms. - * - * Adapted from lots of code ripped from the arch/ppc/boot/ polled - * 16550 support. - * - * Author: Matt Porter - * - * 2002-2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include /* For linux/serial_core.h */ -#include -#include -#include -#include -#include -#include - -#define SERIAL_BAUD 9600 - -/* SERIAL_PORT_DFNS is defined in */ -#ifndef SERIAL_PORT_DFNS -#define SERIAL_PORT_DFNS -#endif - -static struct serial_state rs_table[RS_TABLE_SIZE] = { - SERIAL_PORT_DFNS /* defined in */ -}; - -static void (*serial_outb)(unsigned long, unsigned char); -static unsigned long (*serial_inb)(unsigned long); - -static int shift; - -unsigned long direct_inb(unsigned long addr) -{ - return readb((void __iomem *)addr); -} - -void direct_outb(unsigned long addr, unsigned char val) -{ - writeb(val, (void __iomem *)addr); -} - -unsigned long io_inb(unsigned long port) -{ - return inb(port); -} - -void io_outb(unsigned long port, unsigned char val) -{ - outb(val, port); -} - -unsigned long serial_init(int chan, void *ignored) -{ - unsigned long com_port; - unsigned char lcr, dlm; - - /* We need to find out which type io we're expecting. If it's - * 'SERIAL_IO_PORT', we get an offset from the isa_io_base. - * If it's 'SERIAL_IO_MEM', we can the exact location. -- Tom */ - switch (rs_table[chan].io_type) { - case SERIAL_IO_PORT: - com_port = rs_table[chan].port; - serial_outb = io_outb; - serial_inb = io_inb; - break; - case SERIAL_IO_MEM: - com_port = (unsigned long)rs_table[chan].iomem_base; - serial_outb = direct_outb; - serial_inb = direct_inb; - break; - default: - /* We can't deal with it. */ - return -1; - } - - /* How far apart the registers are. */ - shift = rs_table[chan].iomem_reg_shift; - - /* save the LCR */ - lcr = serial_inb(com_port + (UART_LCR << shift)); - - /* Access baud rate */ - serial_outb(com_port + (UART_LCR << shift), UART_LCR_DLAB); - dlm = serial_inb(com_port + (UART_DLM << shift)); - - /* - * Test if serial port is unconfigured - * We assume that no-one uses less than 110 baud or - * less than 7 bits per character these days. - * -- paulus. - */ - if ((dlm <= 4) && (lcr & 2)) { - /* port is configured, put the old LCR back */ - serial_outb(com_port + (UART_LCR << shift), lcr); - } - else { - /* Input clock. */ - serial_outb(com_port + (UART_DLL << shift), - (rs_table[chan].baud_base / SERIAL_BAUD) & 0xFF); - serial_outb(com_port + (UART_DLM << shift), - (rs_table[chan].baud_base / SERIAL_BAUD) >> 8); - /* 8 data, 1 stop, no parity */ - serial_outb(com_port + (UART_LCR << shift), 0x03); - /* RTS/DTR */ - serial_outb(com_port + (UART_MCR << shift), 0x03); - - /* Clear & enable FIFOs */ - serial_outb(com_port + (UART_FCR << shift), 0x07); - } - - return (com_port); -} - -void -serial_putc(unsigned long com_port, unsigned char c) -{ - while ((serial_inb(com_port + (UART_LSR << shift)) & UART_LSR_THRE) == 0) - ; - serial_outb(com_port, c); -} - -unsigned char -serial_getc(unsigned long com_port) -{ - while ((serial_inb(com_port + (UART_LSR << shift)) & UART_LSR_DR) == 0) - ; - return serial_inb(com_port); -} - -int -serial_tstc(unsigned long com_port) -{ - return ((serial_inb(com_port + (UART_LSR << shift)) & UART_LSR_DR) != 0); -} - -void -serial_close(unsigned long com_port) -{ -} - -void -gen550_init(int i, struct uart_port *serial_req) -{ - rs_table[i].io_type = serial_req->iotype; - rs_table[i].port = serial_req->iobase; - rs_table[i].iomem_base = serial_req->membase; - rs_table[i].iomem_reg_shift = serial_req->regshift; - rs_table[i].baud_base = serial_req->uartclk ? serial_req->uartclk / 16 : BASE_BAUD; -} - -#ifdef CONFIG_SERIAL_TEXT_DEBUG -void -gen550_progress(char *s, unsigned short hex) -{ - volatile unsigned int progress_debugport; - volatile char c; - - progress_debugport = serial_init(0, NULL); - - serial_putc(progress_debugport, '\r'); - - while ((c = *s++) != 0) - serial_putc(progress_debugport, c); - - serial_putc(progress_debugport, '\n'); - serial_putc(progress_debugport, '\r'); -} -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ diff --git a/arch/ppc/syslib/gen550_kgdb.c b/arch/ppc/syslib/gen550_kgdb.c deleted file mode 100644 index 987cc0414e6e..000000000000 --- a/arch/ppc/syslib/gen550_kgdb.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Generic 16550 kgdb support intended to be useful on a variety - * of platforms. To enable this support, it is necessary to set - * the CONFIG_GEN550 option. Any virtual mapping of the serial - * port(s) to be used can be accomplished by setting - * ppc_md.early_serial_map to a platform-specific mapping function. - * - * Adapted from ppc4xx_kgdb.c. - * - * Author: Matt Porter - * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include - -#include - -extern unsigned long serial_init(int, void *); -extern unsigned long serial_getc(unsigned long); -extern unsigned long serial_putc(unsigned long, unsigned char); - -#if defined(CONFIG_KGDB_TTYS0) -#define KGDB_PORT 0 -#elif defined(CONFIG_KGDB_TTYS1) -#define KGDB_PORT 1 -#elif defined(CONFIG_KGDB_TTYS2) -#define KGDB_PORT 2 -#elif defined(CONFIG_KGDB_TTYS3) -#define KGDB_PORT 3 -#else -#error "invalid kgdb_tty port" -#endif - -static volatile unsigned int kgdb_debugport; - -void putDebugChar(unsigned char c) -{ - if (kgdb_debugport == 0) - kgdb_debugport = serial_init(KGDB_PORT, NULL); - - serial_putc(kgdb_debugport, c); -} - -int getDebugChar(void) -{ - if (kgdb_debugport == 0) - kgdb_debugport = serial_init(KGDB_PORT, NULL); - - return(serial_getc(kgdb_debugport)); -} - -void kgdb_interruptible(int enable) -{ - return; -} - -void putDebugString(char* str) -{ - while (*str != '\0') { - putDebugChar(*str); - str++; - } - putDebugChar('\r'); - return; -} - -/* - * Note: gen550_init() must be called already on the port we are going - * to use. - */ -void -gen550_kgdb_map_scc(void) -{ - printk(KERN_DEBUG "kgdb init\n"); - if (ppc_md.early_serial_map) - ppc_md.early_serial_map(); - kgdb_debugport = serial_init(KGDB_PORT, NULL); -} diff --git a/arch/ppc/syslib/gt64260_pic.c b/arch/ppc/syslib/gt64260_pic.c deleted file mode 100644 index 3b4fcca5d1e1..000000000000 --- a/arch/ppc/syslib/gt64260_pic.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Interrupt controller support for Galileo's GT64260. - * - * Author: Chris Zankel - * Modified by: Mark A. Greer - * - * Based on sources from Rabeeh Khoury / Galileo Technology - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * This file contains the specific functions to support the GT64260 - * interrupt controller. - * - * The GT64260 has two main interrupt registers (high and low) that - * summarizes the interrupts generated by the units of the GT64260. - * Each bit is assigned to an interrupt number, where the low register - * are assigned from IRQ0 to IRQ31 and the high cause register - * from IRQ32 to IRQ63 - * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0) - * to IRQ95 (GPP31). - * get_irq() returns the lowest interrupt number that is currently asserted. - * - * Note: - * - This driver does not initialize the GPP when used as an interrupt - * input. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define CPU_INTR_STR "gt64260 cpu interface error" -#define PCI0_INTR_STR "gt64260 pci 0 error" -#define PCI1_INTR_STR "gt64260 pci 1 error" - -/* ========================== forward declaration ========================== */ - -static void gt64260_unmask_irq(unsigned int); -static void gt64260_mask_irq(unsigned int); - -/* ========================== local declarations =========================== */ - -struct hw_interrupt_type gt64260_pic = { - .typename = " gt64260_pic ", - .enable = gt64260_unmask_irq, - .disable = gt64260_mask_irq, - .ack = gt64260_mask_irq, - .end = gt64260_unmask_irq, -}; - -u32 gt64260_irq_base = 0; /* GT64260 handles the next 96 IRQs from here */ - -static struct mv64x60_handle bh; - -/* gt64260_init_irq() - * - * This function initializes the interrupt controller. It assigns - * all interrupts from IRQ0 to IRQ95 to the gt64260 interrupt controller. - * - * Note: - * We register all GPP inputs as interrupt source, but disable them. - */ -void __init -gt64260_init_irq(void) -{ - int i; - - if (ppc_md.progress) - ppc_md.progress("gt64260_init_irq: enter", 0x0); - - bh.v_base = mv64x60_get_bridge_vbase(); - - ppc_cached_irq_mask[0] = 0; - ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */ - ppc_cached_irq_mask[2] = 0; - - /* disable all interrupts and clear current interrupts */ - mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]); - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0); - mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, ppc_cached_irq_mask[0]); - mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, ppc_cached_irq_mask[1]); - - /* use the gt64260 for all (possible) interrupt sources */ - for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++) - irq_desc[i].chip = >64260_pic; - - if (ppc_md.progress) - ppc_md.progress("gt64260_init_irq: exit", 0x0); -} - -/* - * gt64260_get_irq() - * - * This function returns the lowest interrupt number of all interrupts that - * are currently asserted. - * - * Output Variable(s): - * None. - * - * Returns: - * int or -2 (bogus interrupt) - */ -int -gt64260_get_irq(void) -{ - int irq; - int irq_gpp; - - irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_LO); - irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]); - - if (irq == -1) { - irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_HI); - irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]); - - if (irq == -1) - irq = -2; /* bogus interrupt, should never happen */ - else { - if (irq >= 24) { - irq_gpp = mv64x60_read(&bh, - MV64x60_GPP_INTR_CAUSE); - irq_gpp = __ilog2(irq_gpp & - ppc_cached_irq_mask[2]); - - if (irq_gpp == -1) - irq = -2; - else { - irq = irq_gpp + 64; - mv64x60_write(&bh, - MV64x60_GPP_INTR_CAUSE, - ~(1 << (irq - 64))); - } - } else - irq += 32; - } - } - - (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE); - - if (irq < 0) - return (irq); - else - return (gt64260_irq_base + irq); -} - -/* gt64260_unmask_irq() - * - * This function enables an interrupt. - * - * Input Variable(s): - * unsigned int interrupt number (IRQ0...IRQ95). - * - * Output Variable(s): - * None. - * - * Returns: - * void - */ -static void -gt64260_unmask_irq(unsigned int irq) -{ - irq -= gt64260_irq_base; - - if (irq > 31) - if (irq > 63) /* unmask GPP irq */ - mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, - ppc_cached_irq_mask[2] |= (1 << (irq - 64))); - else /* mask high interrupt register */ - mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, - ppc_cached_irq_mask[1] |= (1 << (irq - 32))); - else /* mask low interrupt register */ - mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, - ppc_cached_irq_mask[0] |= (1 << irq)); - - (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); - return; -} - -/* gt64260_mask_irq() - * - * This function disables the requested interrupt. - * - * Input Variable(s): - * unsigned int interrupt number (IRQ0...IRQ95). - * - * Output Variable(s): - * None. - * - * Returns: - * void - */ -static void -gt64260_mask_irq(unsigned int irq) -{ - irq -= gt64260_irq_base; - - if (irq > 31) - if (irq > 63) /* mask GPP irq */ - mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, - ppc_cached_irq_mask[2] &= ~(1 << (irq - 64))); - else /* mask high interrupt register */ - mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, - ppc_cached_irq_mask[1] &= ~(1 << (irq - 32))); - else /* mask low interrupt register */ - mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, - ppc_cached_irq_mask[0] &= ~(1 << irq)); - - (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); - return; -} - -static irqreturn_t -gt64260_cpu_error_int_handler(int irq, void *dev_id) -{ - printk(KERN_ERR "gt64260_cpu_error_int_handler: %s 0x%08x\n", - "Error on CPU interface - Cause regiser", - mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE)); - printk(KERN_ERR "\tCPU error register dump:\n"); - printk(KERN_ERR "\tAddress low 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO)); - printk(KERN_ERR "\tAddress high 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI)); - printk(KERN_ERR "\tData low 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO)); - printk(KERN_ERR "\tData high 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI)); - printk(KERN_ERR "\tParity 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY)); - mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0); - return IRQ_HANDLED; -} - -static irqreturn_t -gt64260_pci_error_int_handler(int irq, void *dev_id) -{ - u32 val; - unsigned int pci_bus = (unsigned int)dev_id; - - if (pci_bus == 0) { /* Error on PCI 0 */ - val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE); - printk(KERN_ERR "%s: Error in PCI %d Interface\n", - "gt64260_pci_error_int_handler", pci_bus); - printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus); - printk(KERN_ERR "\tCause register 0x%08x\n", val); - printk(KERN_ERR "\tAddress Low 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO)); - printk(KERN_ERR "\tAddress High 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI)); - printk(KERN_ERR "\tAttribute 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO)); - printk(KERN_ERR "\tCommand 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD)); - mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val); - } - if (pci_bus == 1) { /* Error on PCI 1 */ - val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE); - printk(KERN_ERR "%s: Error in PCI %d Interface\n", - "gt64260_pci_error_int_handler", pci_bus); - printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus); - printk(KERN_ERR "\tCause register 0x%08x\n", val); - printk(KERN_ERR "\tAddress Low 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO)); - printk(KERN_ERR "\tAddress High 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI)); - printk(KERN_ERR "\tAttribute 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO)); - printk(KERN_ERR "\tCommand 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD)); - mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val); - } - return IRQ_HANDLED; -} - -static int __init -gt64260_register_hdlrs(void) -{ - int rc; - - /* Register CPU interface error interrupt handler */ - if ((rc = request_irq(MV64x60_IRQ_CPU_ERR, - gt64260_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, 0))) - printk(KERN_WARNING "Can't register cpu error handler: %d", rc); - - mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); - mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000fe); - - /* Register PCI 0 error interrupt handler */ - if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler, - IRQF_DISABLED, PCI0_INTR_STR, (void *)0))) - printk(KERN_WARNING "Can't register pci 0 error handler: %d", - rc); - - mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0); - mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0x003c0c24); - - /* Register PCI 1 error interrupt handler */ - if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler, - IRQF_DISABLED, PCI1_INTR_STR, (void *)1))) - printk(KERN_WARNING "Can't register pci 1 error handler: %d", - rc); - - mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0); - mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0x003c0c24); - - return 0; -} - -arch_initcall(gt64260_register_hdlrs); diff --git a/arch/ppc/syslib/harrier.c b/arch/ppc/syslib/harrier.c deleted file mode 100644 index 45b797b3a336..000000000000 --- a/arch/ppc/syslib/harrier.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Motorola MCG Harrier northbridge/memory controller support - * - * Author: Dale Farnsworth - * dale.farnsworth@mvista.com - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/* define defaults for inbound windows */ -#define HARRIER_ITAT_DEFAULT (HARRIER_ITAT_ENA | \ - HARRIER_ITAT_MEM | \ - HARRIER_ITAT_WPE | \ - HARRIER_ITAT_GBL) - -#define HARRIER_MPAT_DEFAULT (HARRIER_ITAT_ENA | \ - HARRIER_ITAT_MEM | \ - HARRIER_ITAT_WPE | \ - HARRIER_ITAT_GBL) - -/* - * Initialize the inbound window size on a non-monarch harrier. - */ -void __init harrier_setup_nonmonarch(uint ppc_reg_base, uint in0_size) -{ - u16 temps; - u32 temp; - - if (in0_size > HARRIER_ITSZ_2GB) { - printk - ("harrier_setup_nonmonarch: Invalid window size code %d\n", - in0_size); - return; - } - - /* Clear the PCI memory enable bit. If we don't, then when the - * inbound windows are enabled below, the corresponding BARs will be - * "live" and start answering to PCI memory reads from their default - * addresses (0x0), which overlap with system RAM. - */ - temps = in_le16((u16 *) (ppc_reg_base + - HARRIER_XCSR_CONFIG(PCI_COMMAND))); - temps &= ~(PCI_COMMAND_MEMORY); - out_le16((u16 *) (ppc_reg_base + HARRIER_XCSR_CONFIG(PCI_COMMAND)), - temps); - - /* Setup a non-prefetchable inbound window */ - out_le32((u32 *) (ppc_reg_base + - HARRIER_XCSR_CONFIG(HARRIER_ITSZ0_OFF)), in0_size); - - temp = in_le32((u32 *) (ppc_reg_base + - HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF))); - temp &= ~HARRIER_ITAT_PRE; - temp |= HARRIER_ITAT_DEFAULT; - out_le32((u32 *) (ppc_reg_base + - HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)), temp); - - /* Enable the message passing block */ - temp = in_le32((u32 *) (ppc_reg_base + - HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF))); - temp |= HARRIER_MPAT_DEFAULT; - out_le32((u32 *) (ppc_reg_base + - HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)), temp); -} - -void __init harrier_release_eready(uint ppc_reg_base) -{ - ulong temp; - - /* - * Set EREADY to allow the line to be pulled up after everyone is - * ready. - */ - temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF)); - temp |= HARRIER_EREADY; - out_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF), temp); -} - -void __init harrier_wait_eready(uint ppc_reg_base) -{ - ulong temp; - - /* - * Poll the ERDYS line until it goes high to indicate that all - * non-monarch PrPMCs are ready for bus enumeration (or that there are - * no PrPMCs present). - */ - - /* FIXME: Add a timeout of some kind to prevent endless waits. */ - do { - - temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF)); - - } while (!(temp & HARRIER_ERDYS)); -} - -/* - * Initialize the Motorola MCG Harrier host bridge. - * - * This means setting up the PPC bus to PCI memory and I/O space mappings, - * setting the PCI memory space address of the MPIC (mapped straight - * through), and ioremap'ing the mpic registers. - * 'OpenPIC_Addr' will be set correctly by this routine. - * This routine will not change the PCI_CONFIG_ADDR or PCI_CONFIG_DATA - * addresses and assumes that the mapping of PCI memory space back to system - * memory is set up correctly by PPCBug. - */ -int __init -harrier_init(struct pci_controller *hose, - uint ppc_reg_base, - ulong processor_pci_mem_start, - ulong processor_pci_mem_end, - ulong processor_pci_io_start, - ulong processor_pci_io_end, ulong processor_mpic_base) -{ - uint addr, offset; - - /* - * Some sanity checks... - */ - if (((processor_pci_mem_start & 0xffff0000) != processor_pci_mem_start) - || ((processor_pci_io_start & 0xffff0000) != - processor_pci_io_start)) { - printk("harrier_init: %s\n", - "PPC to PCI mappings must start on 64 KB boundaries"); - return -1; - } - - if (((processor_pci_mem_end & 0x0000ffff) != 0x0000ffff) || - ((processor_pci_io_end & 0x0000ffff) != 0x0000ffff)) { - printk("harrier_init: PPC to PCI mappings %s\n", - "must end just before a 64 KB boundaries"); - return -1; - } - - if (((processor_pci_mem_end - processor_pci_mem_start) != - (hose->mem_space.end - hose->mem_space.start)) || - ((processor_pci_io_end - processor_pci_io_start) != - (hose->io_space.end - hose->io_space.start))) { - printk("harrier_init: %s\n", - "PPC and PCI memory or I/O space sizes don't match"); - return -1; - } - - if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) { - printk("harrier_init: %s\n", - "MPIC address must start on 256 KB boundary"); - return -1; - } - - if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) { - printk("harrier_init: %s\n", - "pci_dram_offset must be multiple of 64 KB"); - return -1; - } - - /* - * Program the OTAD/OTOF registers to set up the PCI Mem & I/O - * space mappings. These are the mappings going from the processor to - * the PCI bus. - * - * Note: Don't need to 'AND' start/end addresses with 0xffff0000 - * because sanity check above ensures that they are properly - * aligned. - */ - - /* Set up PPC->PCI Mem mapping */ - addr = processor_pci_mem_start | (processor_pci_mem_end >> 16); -#ifdef CONFIG_HARRIER_STORE_GATHERING - offset = (hose->mem_space.start - processor_pci_mem_start) | 0x9a; -#else - offset = (hose->mem_space.start - processor_pci_mem_start) | 0x92; -#endif - out_be32((uint *) (ppc_reg_base + HARRIER_OTAD0_OFF), addr); - out_be32((uint *) (ppc_reg_base + HARRIER_OTOF0_OFF), offset); - - /* Set up PPC->PCI I/O mapping -- Contiguous I/O space */ - addr = processor_pci_io_start | (processor_pci_io_end >> 16); - offset = (hose->io_space.start - processor_pci_io_start) | 0x80; - out_be32((uint *) (ppc_reg_base + HARRIER_OTAD1_OFF), addr); - out_be32((uint *) (ppc_reg_base + HARRIER_OTOF1_OFF), offset); - - /* Enable MPIC */ - OpenPIC_Addr = (void *)processor_mpic_base; - addr = (processor_mpic_base >> 16) | 1; - out_be16((ushort *) (ppc_reg_base + HARRIER_MBAR_OFF), addr); - out_8((u_char *) (ppc_reg_base + HARRIER_MPIC_CSR_OFF), - HARRIER_MPIC_OPI_ENABLE); - - return 0; -} - -/* - * Find the amount of RAM present. - * This assumes that PPCBug has initialized the memory controller (SMC) - * on the Harrier correctly (i.e., it does no sanity checking). - * It also assumes that the memory base registers are set to configure the - * memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc. - * however, RAM base registers can be skipped (e.g. A, B, C are set, - * D is skipped but E is set is okay). - */ -#define MB (1024*1024UL) - -static uint harrier_size_table[] __initdata = { - 0 * MB, /* 0 ==> 0 MB */ - 32 * MB, /* 1 ==> 32 MB */ - 64 * MB, /* 2 ==> 64 MB */ - 64 * MB, /* 3 ==> 64 MB */ - 128 * MB, /* 4 ==> 128 MB */ - 128 * MB, /* 5 ==> 128 MB */ - 128 * MB, /* 6 ==> 128 MB */ - 256 * MB, /* 7 ==> 256 MB */ - 256 * MB, /* 8 ==> 256 MB */ - 256 * MB, /* 9 ==> 256 MB */ - 512 * MB, /* a ==> 512 MB */ - 512 * MB, /* b ==> 512 MB */ - 512 * MB, /* c ==> 512 MB */ - 1024 * MB, /* d ==> 1024 MB */ - 1024 * MB, /* e ==> 1024 MB */ - 2048 * MB, /* f ==> 2048 MB */ -}; - -/* - * *** WARNING: You MUST have a BAT set up to map in the XCSR regs *** - * - * Read the memory controller's registers to determine the amount of system - * memory. Assumes that the memory controller registers are already mapped - * into virtual memory--too early to use ioremap(). - */ -unsigned long __init harrier_get_mem_size(uint xcsr_base) -{ - ulong last_addr; - int i; - uint vend_dev_id; - uint *size_table; - uint val; - uint *csrp; - uint size; - int size_table_entries; - - vend_dev_id = in_be32((uint *) xcsr_base + PCI_VENDOR_ID); - - if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) { - printk("harrier_get_mem_size: %s (0x%x)\n", - "Not a Motorola Memory Controller", vend_dev_id); - return 0; - } - - vend_dev_id &= 0x0000ffff; - - if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HARRIER) { - size_table = harrier_size_table; - size_table_entries = sizeof(harrier_size_table) / - sizeof(harrier_size_table[0]); - } else { - printk("harrier_get_mem_size: %s (0x%x)\n", - "Not a Harrier", vend_dev_id); - return 0; - } - - last_addr = 0; - - csrp = (uint *) (xcsr_base + HARRIER_SDBA_OFF); - for (i = 0; i < 8; i++) { - val = in_be32(csrp++); - - if (val & 0x100) { /* If enabled */ - size = val >> HARRIER_SDB_SIZE_SHIFT; - size &= HARRIER_SDB_SIZE_MASK; - if (size >= size_table_entries) { - break; /* Register not set correctly */ - } - size = size_table[size]; - - val &= ~(size - 1); - val += size; - - if (val > last_addr) { - last_addr = val; - } - } - } - - return last_addr; -} diff --git a/arch/ppc/syslib/hawk_common.c b/arch/ppc/syslib/hawk_common.c deleted file mode 100644 index 86821d8753ed..000000000000 --- a/arch/ppc/syslib/hawk_common.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Common Motorola PowerPlus Platform--really Falcon/Raven or HAWK. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/* - * The Falcon/Raven and HAWK has 4 sets of registers: - * 1) PPC Registers which define the mappings from PPC bus to PCI bus, - * etc. - * 2) PCI Registers which define the mappings from PCI bus to PPC bus and the - * MPIC base address. - * 3) MPIC registers. - * 4) System Memory Controller (SMC) registers. - */ - -/* - * Initialize the Motorola MCG Raven or HAWK host bridge. - * - * This means setting up the PPC bus to PCI memory and I/O space mappings, - * setting the PCI memory space address of the MPIC (mapped straight - * through), and ioremap'ing the mpic registers. - * This routine will set the PCI_CONFIG_ADDR or PCI_CONFIG_DATA - * addresses based on the PCI I/O address that is passed in. - * 'OpenPIC_Addr' will be set correctly by this routine. - */ -int __init -hawk_init(struct pci_controller *hose, - uint ppc_reg_base, - ulong processor_pci_mem_start, - ulong processor_pci_mem_end, - ulong processor_pci_io_start, - ulong processor_pci_io_end, - ulong processor_mpic_base) -{ - uint addr, offset; - - /* - * Some sanity checks... - */ - if (((processor_pci_mem_start&0xffff0000) != processor_pci_mem_start) || - ((processor_pci_io_start &0xffff0000) != processor_pci_io_start)) { - printk("hawk_init: %s\n", - "PPC to PCI mappings must start on 64 KB boundaries"); - return -1; - } - - if (((processor_pci_mem_end &0x0000ffff) != 0x0000ffff) || - ((processor_pci_io_end &0x0000ffff) != 0x0000ffff)) { - printk("hawk_init: PPC to PCI mappings %s\n", - "must end just before a 64 KB boundaries"); - return -1; - } - - if (((processor_pci_mem_end - processor_pci_mem_start) != - (hose->mem_space.end - hose->mem_space.start)) || - ((processor_pci_io_end - processor_pci_io_start) != - (hose->io_space.end - hose->io_space.start))) { - printk("hawk_init: %s\n", - "PPC and PCI memory or I/O space sizes don't match"); - return -1; - } - - if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) { - printk("hawk_init: %s\n", - "MPIC address must start on 256 MB boundary"); - return -1; - } - - if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) { - printk("hawk_init: %s\n", - "pci_dram_offset must be multiple of 64 KB"); - return -1; - } - - /* - * Disable previous PPC->PCI mappings. - */ - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), 0x00000000); - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), 0x00000000); - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF2_OFF), 0x00000000); - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), 0x00000000); - - /* - * Program the XSADD/XSOFF registers to set up the PCI Mem & I/O - * space mappings. These are the mappings going from the processor to - * the PCI bus. - * - * Note: Don't need to 'AND' start/end addresses with 0xffff0000 - * because sanity check above ensures that they are properly - * aligned. - */ - - /* Set up PPC->PCI Mem mapping */ - addr = processor_pci_mem_start | (processor_pci_mem_end >> 16); - offset = (hose->mem_space.start - processor_pci_mem_start) | 0xd2; - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD0_OFF), addr); - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), offset); - - /* Set up PPC->MPIC mapping on the bridge */ - addr = processor_mpic_base | - (((processor_mpic_base + HAWK_MPIC_SIZE) >> 16) - 1); - /* No write posting for this PCI Mem space */ - offset = (hose->mem_space.start - processor_pci_mem_start) | 0xc2; - - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD1_OFF), addr); - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), offset); - - /* Set up PPC->PCI I/O mapping -- Contiguous I/O space */ - addr = processor_pci_io_start | (processor_pci_io_end >> 16); - offset = (hose->io_space.start - processor_pci_io_start) | 0xc0; - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD3_OFF), addr); - out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), offset); - - hose->io_base_virt = (void *)ioremap(processor_pci_io_start, - (processor_pci_io_end - processor_pci_io_start + 1)); - - /* - * Set up the indirect method of accessing PCI config space. - * The PCI config addr/data pair based on start addr of PCI I/O space. - */ - setup_indirect_pci(hose, - processor_pci_io_start + HAWK_PCI_CONFIG_ADDR_OFF, - processor_pci_io_start + HAWK_PCI_CONFIG_DATA_OFF); - - /* - * Disable previous PCI->PPC mappings. - */ - - /* XXXX Put in mappings from PCI bus to processor bus XXXX */ - - /* - * Disable MPIC response to PCI I/O space (BAR 0). - * Make MPIC respond to PCI Mem space at specified address. - * (BAR 1). - */ - early_write_config_dword(hose, - 0, - PCI_DEVFN(0,0), - PCI_BASE_ADDRESS_0, - 0x00000000 | 0x1); - - early_write_config_dword(hose, - 0, - PCI_DEVFN(0,0), - PCI_BASE_ADDRESS_1, - (processor_mpic_base - - processor_pci_mem_start + - hose->mem_space.start) | 0x0); - - /* Map MPIC into virtual memory */ - OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE); - - return 0; -} - -/* - * Find the amount of RAM present. - * This assumes that PPCBug has initialized the memory controller (SMC) - * on the Falcon/HAWK correctly (i.e., it does no sanity checking). - * It also assumes that the memory base registers are set to configure the - * memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc. - * however, RAM base registers can be skipped (e.g. A, B, C are set, - * D is skipped but E is set is okay). - */ -#define MB (1024*1024) - -static uint reg_offset_table[] __initdata = { - HAWK_SMC_RAM_A_SIZE_REG_OFF, - HAWK_SMC_RAM_B_SIZE_REG_OFF, - HAWK_SMC_RAM_C_SIZE_REG_OFF, - HAWK_SMC_RAM_D_SIZE_REG_OFF, - HAWK_SMC_RAM_E_SIZE_REG_OFF, - HAWK_SMC_RAM_F_SIZE_REG_OFF, - HAWK_SMC_RAM_G_SIZE_REG_OFF, - HAWK_SMC_RAM_H_SIZE_REG_OFF -}; - -static uint falcon_size_table[] __initdata = { - 0 * MB, /* 0 ==> 0 MB */ - 16 * MB, /* 1 ==> 16 MB */ - 32 * MB, /* 2 ==> 32 MB */ - 64 * MB, /* 3 ==> 64 MB */ - 128 * MB, /* 4 ==> 128 MB */ - 256 * MB, /* 5 ==> 256 MB */ - 1024 * MB, /* 6 ==> 1024 MB (1 GB) */ -}; - -static uint hawk_size_table[] __initdata = { - 0 * MB, /* 0 ==> 0 MB */ - 32 * MB, /* 1 ==> 32 MB */ - 64 * MB, /* 2 ==> 64 MB */ - 64 * MB, /* 3 ==> 64 MB */ - 128 * MB, /* 4 ==> 128 MB */ - 128 * MB, /* 5 ==> 128 MB */ - 128 * MB, /* 6 ==> 128 MB */ - 256 * MB, /* 7 ==> 256 MB */ - 256 * MB, /* 8 ==> 256 MB */ - 512 * MB, /* 9 ==> 512 MB */ -}; - -/* - * *** WARNING: You MUST have a BAT set up to map in the SMC regs *** - * - * Read the memory controller's registers to determine the amount of system - * memory. Assumes that the memory controller registers are already mapped - * into virtual memory--too early to use ioremap(). - */ -unsigned long __init -hawk_get_mem_size(uint smc_base) -{ - unsigned long total; - int i, size_table_entries, reg_limit; - uint vend_dev_id; - uint *size_table; - u_char val; - - - vend_dev_id = in_be32((uint *)smc_base + PCI_VENDOR_ID); - - if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) { - printk("hawk_get_mem_size: %s (0x%x)\n", - "Not a Motorola Memory Controller", vend_dev_id); - return 0; - } - - vend_dev_id &= 0x0000ffff; - - if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_FALCON) { - size_table = falcon_size_table; - size_table_entries = sizeof(falcon_size_table) / - sizeof(falcon_size_table[0]); - - reg_limit = FALCON_SMC_REG_COUNT; - } - else if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HAWK) { - size_table = hawk_size_table; - size_table_entries = sizeof(hawk_size_table) / - sizeof(hawk_size_table[0]); - reg_limit = HAWK_SMC_REG_COUNT; - } - else { - printk("hawk_get_mem_size: %s (0x%x)\n", - "Not a Falcon or HAWK", vend_dev_id); - return 0; - } - - total = 0; - - /* Check every reg because PPCBug may skip some */ - for (i=0; i -#include -#include -#include -#include - -static volatile void __iomem *pci_intack; /* RO, gives us the irq vector */ - -static unsigned char cached_8259[2] = { 0xff, 0xff }; -#define cached_A1 (cached_8259[0]) -#define cached_21 (cached_8259[1]) - -static DEFINE_SPINLOCK(i8259_lock); - -static int i8259_pic_irq_offset; - -/* - * Acknowledge the IRQ using either the PCI host bridge's interrupt - * acknowledge feature or poll. How i8259_init() is called determines - * which is called. It should be noted that polling is broken on some - * IBM and Motorola PReP boxes so we must use the int-ack feature on them. - */ -int i8259_irq(void) -{ - int irq; - - spin_lock(&i8259_lock); - - /* Either int-ack or poll for the IRQ */ - if (pci_intack) - irq = readb(pci_intack); - else { - /* Perform an interrupt acknowledge cycle on controller 1. */ - outb(0x0C, 0x20); /* prepare for poll */ - irq = inb(0x20) & 7; - if (irq == 2 ) { - /* - * Interrupt is cascaded so perform interrupt - * acknowledge on controller 2. - */ - outb(0x0C, 0xA0); /* prepare for poll */ - irq = (inb(0xA0) & 7) + 8; - } - } - - if (irq == 7) { - /* - * This may be a spurious interrupt. - * - * Read the interrupt status register (ISR). If the most - * significant bit is not set then there is no valid - * interrupt. - */ - if (!pci_intack) - outb(0x0B, 0x20); /* ISR register */ - if(~inb(0x20) & 0x80) - irq = -1; - } - - spin_unlock(&i8259_lock); - return irq + i8259_pic_irq_offset; -} - -static void i8259_mask_and_ack_irq(unsigned int irq_nr) -{ - unsigned long flags; - - spin_lock_irqsave(&i8259_lock, flags); - irq_nr -= i8259_pic_irq_offset; - if (irq_nr > 7) { - cached_A1 |= 1 << (irq_nr-8); - inb(0xA1); /* DUMMY */ - outb(cached_A1, 0xA1); - outb(0x20, 0xA0); /* Non-specific EOI */ - outb(0x20, 0x20); /* Non-specific EOI to cascade */ - } else { - cached_21 |= 1 << irq_nr; - inb(0x21); /* DUMMY */ - outb(cached_21, 0x21); - outb(0x20, 0x20); /* Non-specific EOI */ - } - spin_unlock_irqrestore(&i8259_lock, flags); -} - -static void i8259_set_irq_mask(int irq_nr) -{ - outb(cached_A1,0xA1); - outb(cached_21,0x21); -} - -static void i8259_mask_irq(unsigned int irq_nr) -{ - unsigned long flags; - - spin_lock_irqsave(&i8259_lock, flags); - irq_nr -= i8259_pic_irq_offset; - if (irq_nr < 8) - cached_21 |= 1 << irq_nr; - else - cached_A1 |= 1 << (irq_nr-8); - i8259_set_irq_mask(irq_nr); - spin_unlock_irqrestore(&i8259_lock, flags); -} - -static void i8259_unmask_irq(unsigned int irq_nr) -{ - unsigned long flags; - - spin_lock_irqsave(&i8259_lock, flags); - irq_nr -= i8259_pic_irq_offset; - if (irq_nr < 8) - cached_21 &= ~(1 << irq_nr); - else - cached_A1 &= ~(1 << (irq_nr-8)); - i8259_set_irq_mask(irq_nr); - spin_unlock_irqrestore(&i8259_lock, flags); -} - -static struct irq_chip i8259_pic = { - .typename = " i8259 ", - .mask = i8259_mask_irq, - .disable = i8259_mask_irq, - .unmask = i8259_unmask_irq, - .mask_ack = i8259_mask_and_ack_irq, -}; - -static struct resource pic1_iores = { - .name = "8259 (master)", - .start = 0x20, - .end = 0x21, - .flags = IORESOURCE_BUSY, -}; - -static struct resource pic2_iores = { - .name = "8259 (slave)", - .start = 0xa0, - .end = 0xa1, - .flags = IORESOURCE_BUSY, -}; - -static struct resource pic_edgectrl_iores = { - .name = "8259 edge control", - .start = 0x4d0, - .end = 0x4d1, - .flags = IORESOURCE_BUSY, -}; - -static struct irqaction i8259_irqaction = { - .handler = no_action, - .flags = IRQF_DISABLED, - .mask = CPU_MASK_NONE, - .name = "82c59 secondary cascade", -}; - -/* - * i8259_init() - * intack_addr - PCI interrupt acknowledge (real) address which will return - * the active irq from the 8259 - */ -void __init i8259_init(unsigned long intack_addr, int offset) -{ - unsigned long flags; - int i; - - spin_lock_irqsave(&i8259_lock, flags); - i8259_pic_irq_offset = offset; - - /* init master interrupt controller */ - outb(0x11, 0x20); /* Start init sequence */ - outb(0x00, 0x21); /* Vector base */ - outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */ - outb(0x01, 0x21); /* Select 8086 mode */ - - /* init slave interrupt controller */ - outb(0x11, 0xA0); /* Start init sequence */ - outb(0x08, 0xA1); /* Vector base */ - outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */ - outb(0x01, 0xA1); /* Select 8086 mode */ - - /* always read ISR */ - outb(0x0B, 0x20); - outb(0x0B, 0xA0); - - /* Mask all interrupts */ - outb(cached_A1, 0xA1); - outb(cached_21, 0x21); - - spin_unlock_irqrestore(&i8259_lock, flags); - - for (i = 0; i < NUM_ISA_INTERRUPTS; ++i) { - set_irq_chip_and_handler(offset + i, &i8259_pic, - handle_level_irq); - irq_desc[offset + i].status |= IRQ_LEVEL; - } - - /* reserve our resources */ - setup_irq(offset + 2, &i8259_irqaction); - request_resource(&ioport_resource, &pic1_iores); - request_resource(&ioport_resource, &pic2_iores); - request_resource(&ioport_resource, &pic_edgectrl_iores); - - if (intack_addr != 0) - pci_intack = ioremap(intack_addr, 1); - -} diff --git a/arch/ppc/syslib/ibm440gp_common.c b/arch/ppc/syslib/ibm440gp_common.c deleted file mode 100644 index a3927ec9b5d7..000000000000 --- a/arch/ppc/syslib/ibm440gp_common.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * PPC440GP system library - * - * Matt Porter - * Copyright 2002-2003 MontaVista Software Inc. - * - * Eugene Surovegin or - * Copyright (c) 2003 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include - -/* - * Calculate 440GP clocks - */ -void __init ibm440gp_get_clocks(struct ibm44x_clocks* p, - unsigned int sys_clk, - unsigned int ser_clk) -{ - u32 cpc0_sys0 = mfdcr(DCRN_CPC0_SYS0); - u32 cpc0_cr0 = mfdcr(DCRN_CPC0_CR0); - u32 opdv = ((cpc0_sys0 >> 10) & 0x3) + 1; - u32 epdv = ((cpc0_sys0 >> 8) & 0x3) + 1; - - if (cpc0_sys0 & 0x2){ - /* Bypass system PLL */ - p->cpu = p->plb = sys_clk; - } - else { - u32 fbdv, fwdva, fwdvb, m, vco; - - fbdv = (cpc0_sys0 >> 18) & 0x0f; - if (!fbdv) - fbdv = 16; - - fwdva = 8 - ((cpc0_sys0 >> 15) & 0x7); - fwdvb = 8 - ((cpc0_sys0 >> 12) & 0x7); - - /* Feedback path */ - if (cpc0_sys0 & 0x00000080){ - /* PerClk */ - m = fwdvb * opdv * epdv; - } - else { - /* CPU clock */ - m = fbdv * fwdva; - } - vco = sys_clk * m; - p->cpu = vco / fwdva; - p->plb = vco / fwdvb; - } - - p->opb = p->plb / opdv; - p->ebc = p->opb / epdv; - - if (cpc0_cr0 & 0x00400000){ - /* External UART clock */ - p->uart0 = p->uart1 = ser_clk; - } - else { - /* Internal UART clock */ - u32 uart_div = ((cpc0_cr0 >> 16) & 0x1f) + 1; - p->uart0 = p->uart1 = p->plb / uart_div; - } -} diff --git a/arch/ppc/syslib/ibm440gp_common.h b/arch/ppc/syslib/ibm440gp_common.h deleted file mode 100644 index 94d7835038ad..000000000000 --- a/arch/ppc/syslib/ibm440gp_common.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * PPC440GP system library - * - * Eugene Surovegin or - * Copyright (c) 2003 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#ifdef __KERNEL__ -#ifndef __PPC_SYSLIB_IBM440GP_COMMON_H -#define __PPC_SYSLIB_IBM440GP_COMMON_H - -#ifndef __ASSEMBLY__ - -#include -#include - -/* - * Please, refer to the Figure 13.1 in 440GP user manual - * - * if internal UART clock is used, ser_clk is ignored - */ -void ibm440gp_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk, - unsigned int ser_clk) __init; - -#endif /* __ASSEMBLY__ */ -#endif /* __PPC_SYSLIB_IBM440GP_COMMON_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c deleted file mode 100644 index 6ad52f4a26e1..000000000000 --- a/arch/ppc/syslib/ibm440gx_common.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * PPC440GX system library - * - * Eugene Surovegin or - * Copyright (c) 2003 - 2006 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include -#include - -/* - * Calculate 440GX clocks - */ -static inline u32 __fix_zero(u32 v, u32 def){ - return v ? v : def; -} - -void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk, - unsigned int ser_clk) -{ - u32 pllc = CPR_READ(DCRN_CPR_PLLC); - u32 plld = CPR_READ(DCRN_CPR_PLLD); - u32 uart0 = SDR_READ(DCRN_SDR_UART0); - u32 uart1 = SDR_READ(DCRN_SDR_UART1); -#ifdef CONFIG_440EP - u32 uart2 = SDR_READ(DCRN_SDR_UART2); - u32 uart3 = SDR_READ(DCRN_SDR_UART3); -#endif - - /* Dividers */ - u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32); - u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16); - u32 fwdvb = __fix_zero((plld >> 8) & 7, 8); - u32 lfbdv = __fix_zero(plld & 0x3f, 64); - u32 pradv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMAD) >> 24) & 7, 8); - u32 prbdv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMBD) >> 24) & 7, 8); - u32 opbdv0 = __fix_zero((CPR_READ(DCRN_CPR_OPBD) >> 24) & 3, 4); - u32 perdv0 = __fix_zero((CPR_READ(DCRN_CPR_PERD) >> 24) & 3, 4); - - /* Input clocks for primary dividers */ - u32 clk_a, clk_b; - - if (pllc & 0x40000000){ - u32 m; - - /* Feedback path */ - switch ((pllc >> 24) & 7){ - case 0: - /* PLLOUTx */ - m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv; - break; - case 1: - /* CPU */ - m = fwdva * pradv0; - break; - case 5: - /* PERClk */ - m = fwdvb * prbdv0 * opbdv0 * perdv0; - break; - default: - printk(KERN_EMERG "invalid PLL feedback source\n"); - goto bypass; - } - m *= fbdv; - p->vco = sys_clk * m; - clk_a = p->vco / fwdva; - clk_b = p->vco / fwdvb; - } - else { -bypass: - /* Bypass system PLL */ - p->vco = 0; - clk_a = clk_b = sys_clk; - } - - p->cpu = clk_a / pradv0; - p->plb = clk_b / prbdv0; - p->opb = p->plb / opbdv0; - p->ebc = p->opb / perdv0; - - /* UARTs clock */ - if (uart0 & 0x00800000) - p->uart0 = ser_clk; - else - p->uart0 = p->plb / __fix_zero(uart0 & 0xff, 256); - - if (uart1 & 0x00800000) - p->uart1 = ser_clk; - else - p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256); -#ifdef CONFIG_440EP - if (uart2 & 0x00800000) - p->uart2 = ser_clk; - else - p->uart2 = p->plb / __fix_zero(uart2 & 0xff, 256); - - if (uart3 & 0x00800000) - p->uart3 = ser_clk; - else - p->uart3 = p->plb / __fix_zero(uart3 & 0xff, 256); -#endif -} - -/* Issue L2C diagnostic command */ -static inline u32 l2c_diag(u32 addr) -{ - mtdcr(DCRN_L2C0_ADDR, addr); - mtdcr(DCRN_L2C0_CMD, L2C_CMD_DIAG); - while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ; - return mfdcr(DCRN_L2C0_DATA); -} - -static irqreturn_t l2c_error_handler(int irq, void* dev) -{ - u32 sr = mfdcr(DCRN_L2C0_SR); - if (sr & L2C_SR_CPE){ - /* Read cache trapped address */ - u32 addr = l2c_diag(0x42000000); - printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n", addr); - } - if (sr & L2C_SR_TPE){ - /* Read tag trapped address */ - u32 addr = l2c_diag(0x82000000) >> 16; - printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n", addr); - } - - /* Clear parity errors */ - if (sr & (L2C_SR_CPE | L2C_SR_TPE)){ - mtdcr(DCRN_L2C0_ADDR, 0); - mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE); - } else - printk(KERN_EMERG "L2C: LRU error\n"); - - return IRQ_HANDLED; -} - -/* Enable L2 cache */ -void __init ibm440gx_l2c_enable(void){ - u32 r; - unsigned long flags; - - /* Install error handler */ - if (request_irq(87, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0){ - printk(KERN_ERR "Cannot install L2C error handler, cache is not enabled\n"); - return; - } - - local_irq_save(flags); - asm volatile ("sync" ::: "memory"); - - /* Disable SRAM */ - mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); - mtdcr(DCRN_SRAM0_SB0CR, mfdcr(DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); - mtdcr(DCRN_SRAM0_SB1CR, mfdcr(DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); - mtdcr(DCRN_SRAM0_SB2CR, mfdcr(DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK); - mtdcr(DCRN_SRAM0_SB3CR, mfdcr(DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK); - - /* Enable L2_MODE without ICU/DCU */ - r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK); - r |= L2C_CFG_L2M | L2C_CFG_SS_256; - mtdcr(DCRN_L2C0_CFG, r); - - mtdcr(DCRN_L2C0_ADDR, 0); - - /* Hardware Clear Command */ - mtdcr(DCRN_L2C0_CMD, L2C_CMD_HCC); - while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ; - - /* Clear Cache Parity and Tag Errors */ - mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE); - - /* Enable 64G snoop region starting at 0 */ - r = mfdcr(DCRN_L2C0_SNP0) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK); - r |= L2C_SNP_SSR_32G | L2C_SNP_ESR; - mtdcr(DCRN_L2C0_SNP0, r); - - r = mfdcr(DCRN_L2C0_SNP1) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK); - r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR; - mtdcr(DCRN_L2C0_SNP1, r); - - asm volatile ("sync" ::: "memory"); - - /* Enable ICU/DCU ports */ - r = mfdcr(DCRN_L2C0_CFG); - r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM | L2C_CFG_TPEI - | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM); - r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN - | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM; - mtdcr(DCRN_L2C0_CFG, r); - - asm volatile ("sync; isync" ::: "memory"); - local_irq_restore(flags); -} - -/* Disable L2 cache */ -void __init ibm440gx_l2c_disable(void){ - u32 r; - unsigned long flags; - - local_irq_save(flags); - asm volatile ("sync" ::: "memory"); - - /* Disable L2C mode */ - r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_L2M | L2C_CFG_ICU | L2C_CFG_DCU); - mtdcr(DCRN_L2C0_CFG, r); - - /* Enable SRAM */ - mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) | SRAM_DPC_ENABLE); - mtdcr(DCRN_SRAM0_SB0CR, - SRAM_SBCR_BAS0 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW); - mtdcr(DCRN_SRAM0_SB1CR, - SRAM_SBCR_BAS1 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW); - mtdcr(DCRN_SRAM0_SB2CR, - SRAM_SBCR_BAS2 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW); - mtdcr(DCRN_SRAM0_SB3CR, - SRAM_SBCR_BAS3 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW); - - asm volatile ("sync; isync" ::: "memory"); - local_irq_restore(flags); -} - -void __init ibm440gx_l2c_setup(struct ibm44x_clocks* p) -{ - /* Disable L2C on rev.A, rev.B and 800MHz version of rev.C, - enable it on all other revisions - */ - if (strcmp(cur_cpu_spec->cpu_name, "440GX Rev. A") == 0 || - strcmp(cur_cpu_spec->cpu_name, "440GX Rev. B") == 0 - || (strcmp(cur_cpu_spec->cpu_name, "440GX Rev. C") - == 0 && p->cpu > 667000000)) - ibm440gx_l2c_disable(); - else - ibm440gx_l2c_enable(); -} - -int __init ibm440gx_get_eth_grp(void) -{ - return (SDR_READ(DCRN_SDR_PFC1) & DCRN_SDR_PFC1_EPS) >> DCRN_SDR_PFC1_EPS_SHIFT; -} - -void __init ibm440gx_set_eth_grp(int group) -{ - SDR_WRITE(DCRN_SDR_PFC1, (SDR_READ(DCRN_SDR_PFC1) & ~DCRN_SDR_PFC1_EPS) | (group << DCRN_SDR_PFC1_EPS_SHIFT)); -} - -void __init ibm440gx_tah_enable(void) -{ - /* Enable TAH0 and TAH1 */ - SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) & - ~DCRN_SDR_MFR_TAH0); - SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) & - ~DCRN_SDR_MFR_TAH1); -} - -int ibm440gx_show_cpuinfo(struct seq_file *m){ - - u32 l2c_cfg = mfdcr(DCRN_L2C0_CFG); - const char* s; - if (l2c_cfg & L2C_CFG_L2M){ - switch (l2c_cfg & (L2C_CFG_ICU | L2C_CFG_DCU)){ - case L2C_CFG_ICU: s = "I-Cache only"; break; - case L2C_CFG_DCU: s = "D-Cache only"; break; - default: s = "I-Cache/D-Cache"; break; - } - } - else - s = "disabled"; - - seq_printf(m, "L2-Cache\t: %s (0x%08x 0x%08x)\n", s, - l2c_cfg, mfdcr(DCRN_L2C0_SR)); - - return 0; -} - -void __init ibm440gx_platform_init(unsigned long r3, unsigned long r4, - unsigned long r5, unsigned long r6, - unsigned long r7) -{ - /* Erratum 440_43 workaround, disable L1 cache parity checking */ - if (!strcmp(cur_cpu_spec->cpu_name, "440GX Rev. C") || - !strcmp(cur_cpu_spec->cpu_name, "440GX Rev. F")) - mtspr(SPRN_CCR1, mfspr(SPRN_CCR1) | CCR1_DPC); - - ibm44x_platform_init(r3, r4, r5, r6, r7); -} diff --git a/arch/ppc/syslib/ibm440gx_common.h b/arch/ppc/syslib/ibm440gx_common.h deleted file mode 100644 index 8d6f203e7a1d..000000000000 --- a/arch/ppc/syslib/ibm440gx_common.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * PPC440GX system library - * - * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#ifdef __KERNEL__ -#ifndef __PPC_SYSLIB_IBM440GX_COMMON_H -#define __PPC_SYSLIB_IBM440GX_COMMON_H - -#ifndef __ASSEMBLY__ - -#include -#include -#include - -/* - * Please, refer to the Figure 14.1 in 440GX user manual - * - * if internal UART clock is used, ser_clk is ignored - */ -void ibm440gx_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk, - unsigned int ser_clk) __init; - -/* common 440GX platform init */ -void ibm440gx_platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) __init; - -/* Enable L2 cache */ -void ibm440gx_l2c_enable(void) __init; - -/* Disable L2 cache */ -void ibm440gx_l2c_disable(void) __init; - -/* Enable/disable L2 cache for a particular chip revision */ -void ibm440gx_l2c_setup(struct ibm44x_clocks*) __init; - -/* Get Ethernet Group */ -int ibm440gx_get_eth_grp(void) __init; - -/* Set Ethernet Group */ -void ibm440gx_set_eth_grp(int group) __init; - -/* Enable TAH devices */ -void ibm440gx_tah_enable(void) __init; - -/* Add L2C info to /proc/cpuinfo */ -int ibm440gx_show_cpuinfo(struct seq_file*); - -#endif /* __ASSEMBLY__ */ -#endif /* __PPC_SYSLIB_IBM440GX_COMMON_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/syslib/ibm440sp_common.c b/arch/ppc/syslib/ibm440sp_common.c deleted file mode 100644 index 571f8bcf78e6..000000000000 --- a/arch/ppc/syslib/ibm440sp_common.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * PPC440SP/PPC440SPe system library - * - * Matt Porter - * Copyright 2002-2005 MontaVista Software Inc. - * - * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include - -#include -#include -#include -#include -#include -#include - -/* - * Read the 440SP memory controller to get size of system memory. - */ -unsigned long __init ibm440sp_find_end_of_memory(void) -{ - u32 i; - u32 mem_size = 0; - - /* Read two bank sizes and sum */ - for (i=0; i< MQ0_NUM_BANKS; i++) - switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) { - case MQ0_CONFIG_SIZE_8M: - mem_size += PPC44x_MEM_SIZE_8M; - break; - case MQ0_CONFIG_SIZE_16M: - mem_size += PPC44x_MEM_SIZE_16M; - break; - case MQ0_CONFIG_SIZE_32M: - mem_size += PPC44x_MEM_SIZE_32M; - break; - case MQ0_CONFIG_SIZE_64M: - mem_size += PPC44x_MEM_SIZE_64M; - break; - case MQ0_CONFIG_SIZE_128M: - mem_size += PPC44x_MEM_SIZE_128M; - break; - case MQ0_CONFIG_SIZE_256M: - mem_size += PPC44x_MEM_SIZE_256M; - break; - case MQ0_CONFIG_SIZE_512M: - mem_size += PPC44x_MEM_SIZE_512M; - break; - case MQ0_CONFIG_SIZE_1G: - mem_size += PPC44x_MEM_SIZE_1G; - break; - case MQ0_CONFIG_SIZE_2G: - mem_size += PPC44x_MEM_SIZE_2G; - break; - default: - break; - } - return mem_size; -} diff --git a/arch/ppc/syslib/ibm440sp_common.h b/arch/ppc/syslib/ibm440sp_common.h deleted file mode 100644 index 8077bf8ed118..000000000000 --- a/arch/ppc/syslib/ibm440sp_common.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * PPC440SP system library - * - * Matt Porter - * Copyright 2004-2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#ifdef __KERNEL__ -#ifndef __PPC_SYSLIB_IBM440SP_COMMON_H -#define __PPC_SYSLIB_IBM440SP_COMMON_H - -#ifndef __ASSEMBLY__ - -extern unsigned long __init ibm440sp_find_end_of_memory(void); - -#endif /* __ASSEMBLY__ */ -#endif /* __PPC_SYSLIB_IBM440SP_COMMON_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/syslib/ibm44x_common.c b/arch/ppc/syslib/ibm44x_common.c deleted file mode 100644 index 01f99b4a6649..000000000000 --- a/arch/ppc/syslib/ibm44x_common.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * PPC44x system library - * - * Matt Porter - * Copyright 2002-2005 MontaVista Software Inc. - * - * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* Global Variables */ -bd_t __res; - -phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size) -{ - phys_addr_t page_4gb = 0; - - /* - * Trap the least significant 32-bit portions of an - * address in the 440's 36-bit address space. Fix - * them up with the appropriate ERPN - */ - if ((addr >= PPC44x_IO_LO) && (addr <= PPC44x_IO_HI)) - page_4gb = PPC44x_IO_PAGE; - else if ((addr >= PPC44x_PCI0CFG_LO) && (addr <= PPC44x_PCI0CFG_HI)) - page_4gb = PPC44x_PCICFG_PAGE; -#ifdef CONFIG_440SP - else if ((addr >= PPC44x_PCI1CFG_LO) && (addr <= PPC44x_PCI1CFG_HI)) - page_4gb = PPC44x_PCICFG_PAGE; - else if ((addr >= PPC44x_PCI2CFG_LO) && (addr <= PPC44x_PCI2CFG_HI)) - page_4gb = PPC44x_PCICFG_PAGE; -#endif - else if ((addr >= PPC44x_PCIMEM_LO) && (addr <= PPC44x_PCIMEM_HI)) - page_4gb = PPC44x_PCIMEM_PAGE; - - return (page_4gb | addr); -}; -EXPORT_SYMBOL(fixup_bigphys_addr); - -void __init ibm44x_calibrate_decr(unsigned int freq) -{ - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); - - /* Set the time base to zero */ - mtspr(SPRN_TBWL, 0); - mtspr(SPRN_TBWU, 0); - - /* Clear any pending timer interrupts */ - mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS); - - /* Enable decrementer interrupt */ - mtspr(SPRN_TCR, TCR_DIE); -} - -extern void abort(void); - -static void ibm44x_restart(char *cmd) -{ - local_irq_disable(); - abort(); -} - -static void ibm44x_power_off(void) -{ - local_irq_disable(); - for(;;); -} - -static void ibm44x_halt(void) -{ - local_irq_disable(); - for(;;); -} - -/* - * Read the 44x memory controller to get size of system memory. - */ -static unsigned long __init ibm44x_find_end_of_memory(void) -{ - u32 i, bank_config; - u32 mem_size = 0; - - for (i=0; i<4; i++) - { - switch (i) - { - case 0: - mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR); - break; - case 1: - mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR); - break; - case 2: - mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR); - break; - case 3: - mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR); - break; - } - - bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); - - if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE)) - continue; - switch (SDRAM_CONFIG_BANK_SIZE(bank_config)) - { - case SDRAM_CONFIG_SIZE_8M: - mem_size += PPC44x_MEM_SIZE_8M; - break; - case SDRAM_CONFIG_SIZE_16M: - mem_size += PPC44x_MEM_SIZE_16M; - break; - case SDRAM_CONFIG_SIZE_32M: - mem_size += PPC44x_MEM_SIZE_32M; - break; - case SDRAM_CONFIG_SIZE_64M: - mem_size += PPC44x_MEM_SIZE_64M; - break; - case SDRAM_CONFIG_SIZE_128M: - mem_size += PPC44x_MEM_SIZE_128M; - break; - case SDRAM_CONFIG_SIZE_256M: - mem_size += PPC44x_MEM_SIZE_256M; - break; - case SDRAM_CONFIG_SIZE_512M: - mem_size += PPC44x_MEM_SIZE_512M; - break; - } - } - return mem_size; -} - -void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* - * If we were passed in a board information, copy it into the - * residual data area. - */ - if (r3) - __res = *(bd_t *)(r3 + KERNELBASE); - -#if defined(CONFIG_BLK_DEV_INITRD) - /* - * If the init RAM disk has been configured in, and there's a valid - * starting address for it, set it up. - */ - if (r4) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - /* Copy the kernel command line arguments to a safe place. */ - - if (r6) { - *(char *) (r7 + KERNELBASE) = 0; - strcpy(cmd_line, (char *) (r6 + KERNELBASE)); - } - - ppc_md.init_IRQ = ppc4xx_pic_init; - ppc_md.find_end_of_memory = ibm44x_find_end_of_memory; - ppc_md.restart = ibm44x_restart; - ppc_md.power_off = ibm44x_power_off; - ppc_md.halt = ibm44x_halt; - -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ -#ifdef CONFIG_KGDB - ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; -#endif - - /* - * The Abatron BDI JTAG debugger does not tolerate others - * mucking with the debug registers. - */ -#if !defined(CONFIG_BDI_SWITCH) - /* Enable internal debug mode */ - mtspr(SPRN_DBCR0, (DBCR0_IDM)); - - /* Clear any residual debug events */ - mtspr(SPRN_DBSR, 0xffffffff); -#endif -} - -/* Called from machine_check_exception */ -void platform_machine_check(struct pt_regs *regs) -{ -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) - printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n", - mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL), - mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH), - mfdcr(DCRN_PLB0_BESRL)); - printk("PLB1: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n", - mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL), - mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH), - mfdcr(DCRN_PLB1_BESRL)); -#else - printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n", - mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL), - mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR)); -#endif - printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n", - mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL), - mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1)); - printk("OPB0: BEAR=0x%08x%08x BSTAT=0x%08x\n", - mfdcr(DCRN_OPB0_BEARH), mfdcr(DCRN_OPB0_BEARL), - mfdcr(DCRN_OPB0_BSTAT)); -} diff --git a/arch/ppc/syslib/ibm44x_common.h b/arch/ppc/syslib/ibm44x_common.h deleted file mode 100644 index f179db8634e0..000000000000 --- a/arch/ppc/syslib/ibm44x_common.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * PPC44x system library - * - * Eugene Surovegin or - * Copyright (c) 2003, 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#ifdef __KERNEL__ -#ifndef __PPC_SYSLIB_IBM44x_COMMON_H -#define __PPC_SYSLIB_IBM44x_COMMON_H - -#ifndef __ASSEMBLY__ - -/* - * All clocks are in Hz - */ -struct ibm44x_clocks { - unsigned int vco; /* VCO, 0 if system PLL is bypassed */ - unsigned int cpu; /* CPUCoreClk */ - unsigned int plb; /* PLBClk */ - unsigned int opb; /* OPBClk */ - unsigned int ebc; /* PerClk */ - unsigned int uart0; - unsigned int uart1; -#ifdef CONFIG_440EP - unsigned int uart2; - unsigned int uart3; -#endif -}; - -/* common 44x platform init */ -void ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) __init; - -/* initialize decrementer and tick-related variables */ -void ibm44x_calibrate_decr(unsigned int freq) __init; - -#endif /* __ASSEMBLY__ */ -#endif /* __PPC_SYSLIB_IBM44x_COMMON_H */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/syslib/ibm_ocp.c b/arch/ppc/syslib/ibm_ocp.c deleted file mode 100644 index 2ee176610e7c..000000000000 --- a/arch/ppc/syslib/ibm_ocp.c +++ /dev/null @@ -1,10 +0,0 @@ -#include -#include -#include - -struct ocp_sys_info_data ocp_sys_info = { - .opb_bus_freq = 50000000, /* OPB Bus Frequency (Hz) */ - .ebc_bus_freq = 33333333, /* EBC Bus Frequency (Hz) */ -}; - -EXPORT_SYMBOL(ocp_sys_info); diff --git a/arch/ppc/syslib/indirect_pci.c b/arch/ppc/syslib/indirect_pci.c deleted file mode 100644 index 83b323a7d029..000000000000 --- a/arch/ppc/syslib/indirect_pci.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Support for indirect PCI bridges. - * - * Copyright (C) 1998 Gabriel Paubert. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_PPC_INDIRECT_PCI_BE -#define PCI_CFG_OUT out_be32 -#else -#define PCI_CFG_OUT out_le32 -#endif - -static int -indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) -{ - struct pci_controller *hose = bus->sysdata; - volatile void __iomem *cfg_data; - u8 cfg_type = 0; - - if (ppc_md.pci_exclude_device) - if (ppc_md.pci_exclude_device(bus->number, devfn)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (hose->set_cfg_type) - if (bus->number != hose->first_busno) - cfg_type = 1; - - PCI_CFG_OUT(hose->cfg_addr, - (0x80000000 | ((bus->number - hose->bus_offset) << 16) - | (devfn << 8) | ((offset & 0xfc) | cfg_type))); - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - cfg_data = hose->cfg_data + (offset & 3); - switch (len) { - case 1: - *val = in_8(cfg_data); - break; - case 2: - *val = in_le16(cfg_data); - break; - default: - *val = in_le32(cfg_data); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static int -indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) -{ - struct pci_controller *hose = bus->sysdata; - volatile void __iomem *cfg_data; - u8 cfg_type = 0; - - if (ppc_md.pci_exclude_device) - if (ppc_md.pci_exclude_device(bus->number, devfn)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (hose->set_cfg_type) - if (bus->number != hose->first_busno) - cfg_type = 1; - - PCI_CFG_OUT(hose->cfg_addr, - (0x80000000 | ((bus->number - hose->bus_offset) << 16) - | (devfn << 8) | ((offset & 0xfc) | cfg_type))); - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - cfg_data = hose->cfg_data + (offset & 3); - switch (len) { - case 1: - out_8(cfg_data, val); - break; - case 2: - out_le16(cfg_data, val); - break; - default: - out_le32(cfg_data, val); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops indirect_pci_ops = -{ - indirect_read_config, - indirect_write_config -}; - -void __init -setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr, - void __iomem * cfg_data) -{ - hose->cfg_addr = cfg_addr; - hose->cfg_data = cfg_data; - hose->ops = &indirect_pci_ops; -} - -void __init -setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) -{ - unsigned long base = cfg_addr & PAGE_MASK; - void __iomem *mbase, *addr, *data; - - mbase = ioremap(base, PAGE_SIZE); - addr = mbase + (cfg_addr & ~PAGE_MASK); - if ((cfg_data & PAGE_MASK) != base) - mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); - data = mbase + (cfg_data & ~PAGE_MASK); - setup_indirect_pci_nomap(hose, addr, data); -} diff --git a/arch/ppc/syslib/m8260_pci_erratum9.c b/arch/ppc/syslib/m8260_pci_erratum9.c deleted file mode 100644 index ebb8c8f8f30c..000000000000 --- a/arch/ppc/syslib/m8260_pci_erratum9.c +++ /dev/null @@ -1,455 +0,0 @@ -/* - * Workaround for device erratum PCI 9. - * See Motorola's "XPC826xA Family Device Errata Reference." - * The erratum applies to all 8260 family Hip4 processors. It is scheduled - * to be fixed in HiP4 Rev C. Erratum PCI 9 states that a simultaneous PCI - * inbound write transaction and PCI outbound read transaction can result in a - * bus deadlock. The suggested workaround is to use the IDMA controller to - * perform all reads from PCI configuration, memory, and I/O space. - * - * Author: andy_lowe@mvista.com - * - * 2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "m82xx_pci.h" - -#ifdef CONFIG_8260_PCI9 -/*#include */ /* included in asm/io.h */ - -#define IDMA_XFER_BUF_SIZE 64 /* size of the IDMA transfer buffer */ - -/* define a structure for the IDMA dpram usage */ -typedef struct idma_dpram_s { - idma_t pram; /* IDMA parameter RAM */ - u_char xfer_buf[IDMA_XFER_BUF_SIZE]; /* IDMA transfer buffer */ - idma_bd_t bd; /* buffer descriptor */ -} idma_dpram_t; - -/* define offsets relative to start of IDMA dpram */ -#define IDMA_XFER_BUF_OFFSET (sizeof(idma_t)) -#define IDMA_BD_OFFSET (sizeof(idma_t) + IDMA_XFER_BUF_SIZE) - -/* define globals */ -static volatile idma_dpram_t *idma_dpram; - -/* Exactly one of CONFIG_8260_PCI9_IDMAn must be defined, - * where n is 1, 2, 3, or 4. This selects the IDMA channel used for - * the PCI9 workaround. - */ -#ifdef CONFIG_8260_PCI9_IDMA1 -#define IDMA_CHAN 0 -#define PROFF_IDMA PROFF_IDMA1_BASE -#define IDMA_PAGE CPM_CR_IDMA1_PAGE -#define IDMA_SBLOCK CPM_CR_IDMA1_SBLOCK -#endif -#ifdef CONFIG_8260_PCI9_IDMA2 -#define IDMA_CHAN 1 -#define PROFF_IDMA PROFF_IDMA2_BASE -#define IDMA_PAGE CPM_CR_IDMA2_PAGE -#define IDMA_SBLOCK CPM_CR_IDMA2_SBLOCK -#endif -#ifdef CONFIG_8260_PCI9_IDMA3 -#define IDMA_CHAN 2 -#define PROFF_IDMA PROFF_IDMA3_BASE -#define IDMA_PAGE CPM_CR_IDMA3_PAGE -#define IDMA_SBLOCK CPM_CR_IDMA3_SBLOCK -#endif -#ifdef CONFIG_8260_PCI9_IDMA4 -#define IDMA_CHAN 3 -#define PROFF_IDMA PROFF_IDMA4_BASE -#define IDMA_PAGE CPM_CR_IDMA4_PAGE -#define IDMA_SBLOCK CPM_CR_IDMA4_SBLOCK -#endif - -void idma_pci9_init(void) -{ - uint dpram_offset; - volatile idma_t *pram; - volatile im_idma_t *idma_reg; - volatile cpm2_map_t *immap = cpm2_immr; - - /* allocate IDMA dpram */ - dpram_offset = cpm_dpalloc(sizeof(idma_dpram_t), 64); - idma_dpram = cpm_dpram_addr(dpram_offset); - - /* initialize the IDMA parameter RAM */ - memset((void *)idma_dpram, 0, sizeof(idma_dpram_t)); - pram = &idma_dpram->pram; - pram->ibase = dpram_offset + IDMA_BD_OFFSET; - pram->dpr_buf = dpram_offset + IDMA_XFER_BUF_OFFSET; - pram->ss_max = 32; - pram->dts = 32; - - /* initialize the IDMA_BASE pointer to the IDMA parameter RAM */ - *((ushort *) &immap->im_dprambase[PROFF_IDMA]) = dpram_offset; - - /* initialize the IDMA registers */ - idma_reg = (volatile im_idma_t *) &immap->im_sdma.sdma_idsr1; - idma_reg[IDMA_CHAN].idmr = 0; /* mask all IDMA interrupts */ - idma_reg[IDMA_CHAN].idsr = 0xff; /* clear all event flags */ - - printk(KERN_WARNING - "Using IDMA%d for MPC8260 device erratum PCI 9 workaround\n", - IDMA_CHAN + 1); - - return; -} - -/* Use the IDMA controller to transfer data from I/O memory to local RAM. - * The src address must be a physical address suitable for use by the DMA - * controller with no translation. The dst address must be a kernel virtual - * address. The dst address is translated to a physical address via - * virt_to_phys(). - * The sinc argument specifies whether or not the source address is incremented - * by the DMA controller. The source address is incremented if and only if sinc - * is non-zero. The destination address is always incremented since the - * destination is always host RAM. - */ -static void -idma_pci9_read(u8 *dst, u8 *src, int bytes, int unit_size, int sinc) -{ - unsigned long flags; - volatile idma_t *pram = &idma_dpram->pram; - volatile idma_bd_t *bd = &idma_dpram->bd; - volatile cpm2_map_t *immap = cpm2_immr; - - local_irq_save(flags); - - /* initialize IDMA parameter RAM for this transfer */ - if (sinc) - pram->dcm = IDMA_DCM_DMA_WRAP_64 | IDMA_DCM_SINC - | IDMA_DCM_DINC | IDMA_DCM_SD_MEM2MEM; - else - pram->dcm = IDMA_DCM_DMA_WRAP_64 | IDMA_DCM_DINC - | IDMA_DCM_SD_MEM2MEM; - pram->ibdptr = pram->ibase; - pram->sts = unit_size; - pram->istate = 0; - - /* initialize the buffer descriptor */ - bd->dst = virt_to_phys(dst); - bd->src = (uint) src; - bd->len = bytes; - bd->flags = IDMA_BD_V | IDMA_BD_W | IDMA_BD_I | IDMA_BD_L | IDMA_BD_DGBL - | IDMA_BD_DBO_BE | IDMA_BD_SBO_BE | IDMA_BD_SDTB; - - /* issue the START_IDMA command to the CP */ - while (immap->im_cpm.cp_cpcr & CPM_CR_FLG); - immap->im_cpm.cp_cpcr = mk_cr_cmd(IDMA_PAGE, IDMA_SBLOCK, 0, - CPM_CR_START_IDMA) | CPM_CR_FLG; - while (immap->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* wait for transfer to complete */ - while(bd->flags & IDMA_BD_V); - - local_irq_restore(flags); - - return; -} - -/* Use the IDMA controller to transfer data from I/O memory to local RAM. - * The dst address must be a physical address suitable for use by the DMA - * controller with no translation. The src address must be a kernel virtual - * address. The src address is translated to a physical address via - * virt_to_phys(). - * The dinc argument specifies whether or not the dest address is incremented - * by the DMA controller. The source address is incremented if and only if sinc - * is non-zero. The source address is always incremented since the - * source is always host RAM. - */ -static void -idma_pci9_write(u8 *dst, u8 *src, int bytes, int unit_size, int dinc) -{ - unsigned long flags; - volatile idma_t *pram = &idma_dpram->pram; - volatile idma_bd_t *bd = &idma_dpram->bd; - volatile cpm2_map_t *immap = cpm2_immr; - - local_irq_save(flags); - - /* initialize IDMA parameter RAM for this transfer */ - if (dinc) - pram->dcm = IDMA_DCM_DMA_WRAP_64 | IDMA_DCM_SINC - | IDMA_DCM_DINC | IDMA_DCM_SD_MEM2MEM; - else - pram->dcm = IDMA_DCM_DMA_WRAP_64 | IDMA_DCM_SINC - | IDMA_DCM_SD_MEM2MEM; - pram->ibdptr = pram->ibase; - pram->sts = unit_size; - pram->istate = 0; - - /* initialize the buffer descriptor */ - bd->dst = (uint) dst; - bd->src = virt_to_phys(src); - bd->len = bytes; - bd->flags = IDMA_BD_V | IDMA_BD_W | IDMA_BD_I | IDMA_BD_L | IDMA_BD_DGBL - | IDMA_BD_DBO_BE | IDMA_BD_SBO_BE | IDMA_BD_SDTB; - - /* issue the START_IDMA command to the CP */ - while (immap->im_cpm.cp_cpcr & CPM_CR_FLG); - immap->im_cpm.cp_cpcr = mk_cr_cmd(IDMA_PAGE, IDMA_SBLOCK, 0, - CPM_CR_START_IDMA) | CPM_CR_FLG; - while (immap->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* wait for transfer to complete */ - while(bd->flags & IDMA_BD_V); - - local_irq_restore(flags); - - return; -} - -/* Same as idma_pci9_read, but 16-bit little-endian byte swapping is performed - * if the unit_size is 2, and 32-bit little-endian byte swapping is performed if - * the unit_size is 4. - */ -static void -idma_pci9_read_le(u8 *dst, u8 *src, int bytes, int unit_size, int sinc) -{ - int i; - u8 *p; - - idma_pci9_read(dst, src, bytes, unit_size, sinc); - switch(unit_size) { - case 2: - for (i = 0, p = dst; i < bytes; i += 2, p += 2) - swab16s((u16 *) p); - break; - case 4: - for (i = 0, p = dst; i < bytes; i += 4, p += 4) - swab32s((u32 *) p); - break; - default: - break; - } -} -EXPORT_SYMBOL(idma_pci9_init); -EXPORT_SYMBOL(idma_pci9_read); -EXPORT_SYMBOL(idma_pci9_read_le); - -static inline int is_pci_mem(unsigned long addr) -{ - if (addr >= M82xx_PCI_LOWER_MMIO && - addr <= M82xx_PCI_UPPER_MMIO) - return 1; - if (addr >= M82xx_PCI_LOWER_MEM && - addr <= M82xx_PCI_UPPER_MEM) - return 1; - return 0; -} - -#define is_pci_mem(pa) ( (pa > 0x80000000) && (pa < 0xc0000000)) -int readb(volatile unsigned char *addr) -{ - u8 val; - unsigned long pa = iopa((unsigned long) addr); - - if (!is_pci_mem(pa)) - return in_8(addr); - - idma_pci9_read((u8 *)&val, (u8 *)pa, sizeof(val), sizeof(val), 0); - return val; -} - -int readw(volatile unsigned short *addr) -{ - u16 val; - unsigned long pa = iopa((unsigned long) addr); - - if (!is_pci_mem(pa)) - return in_le16(addr); - - idma_pci9_read((u8 *)&val, (u8 *)pa, sizeof(val), sizeof(val), 0); - return swab16(val); -} - -unsigned readl(volatile unsigned *addr) -{ - u32 val; - unsigned long pa = iopa((unsigned long) addr); - - if (!is_pci_mem(pa)) - return in_le32(addr); - - idma_pci9_read((u8 *)&val, (u8 *)pa, sizeof(val), sizeof(val), 0); - return swab32(val); -} - -int inb(unsigned port) -{ - u8 val; - u8 *addr = (u8 *)(port + _IO_BASE); - - idma_pci9_read((u8 *)&val, (u8 *)addr, sizeof(val), sizeof(val), 0); - return val; -} - -int inw(unsigned port) -{ - u16 val; - u8 *addr = (u8 *)(port + _IO_BASE); - - idma_pci9_read((u8 *)&val, (u8 *)addr, sizeof(val), sizeof(val), 0); - return swab16(val); -} - -unsigned inl(unsigned port) -{ - u32 val; - u8 *addr = (u8 *)(port + _IO_BASE); - - idma_pci9_read((u8 *)&val, (u8 *)addr, sizeof(val), sizeof(val), 0); - return swab32(val); -} - -void insb(unsigned port, void *buf, int ns) -{ - u8 *addr = (u8 *)(port + _IO_BASE); - - idma_pci9_read((u8 *)buf, (u8 *)addr, ns*sizeof(u8), sizeof(u8), 0); -} - -void insw(unsigned port, void *buf, int ns) -{ - u8 *addr = (u8 *)(port + _IO_BASE); - - idma_pci9_read((u8 *)buf, (u8 *)addr, ns*sizeof(u16), sizeof(u16), 0); -} - -void insl(unsigned port, void *buf, int nl) -{ - u8 *addr = (u8 *)(port + _IO_BASE); - - idma_pci9_read((u8 *)buf, (u8 *)addr, nl*sizeof(u32), sizeof(u32), 0); -} - -void *memcpy_fromio(void *dest, unsigned long src, size_t count) -{ - unsigned long pa = iopa((unsigned long) src); - - if (is_pci_mem(pa)) - idma_pci9_read((u8 *)dest, (u8 *)pa, count, 32, 1); - else - memcpy(dest, (void *)src, count); - return dest; -} - -EXPORT_SYMBOL(readb); -EXPORT_SYMBOL(readw); -EXPORT_SYMBOL(readl); -EXPORT_SYMBOL(inb); -EXPORT_SYMBOL(inw); -EXPORT_SYMBOL(inl); -EXPORT_SYMBOL(insb); -EXPORT_SYMBOL(insw); -EXPORT_SYMBOL(insl); -EXPORT_SYMBOL(memcpy_fromio); - -#endif /* ifdef CONFIG_8260_PCI9 */ - -/* Indirect PCI routines adapted from arch/ppc/kernel/indirect_pci.c. - * Copyright (C) 1998 Gabriel Paubert. - */ -#ifndef CONFIG_8260_PCI9 -#define cfg_read(val, addr, type, op) *val = op((type)(addr)) -#else -#define cfg_read(val, addr, type, op) \ - idma_pci9_read_le((u8*)(val),(u8*)(addr),sizeof(*(val)),sizeof(*(val)),0) -#endif - -#define cfg_write(val, addr, type, op) op((type *)(addr), (val)) - -static int indirect_write_config(struct pci_bus *pbus, unsigned int devfn, int where, - int size, u32 value) -{ - struct pci_controller *hose = pbus->sysdata; - u8 cfg_type = 0; - if (ppc_md.pci_exclude_device) - if (ppc_md.pci_exclude_device(pbus->number, devfn)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (hose->set_cfg_type) - if (pbus->number != hose->first_busno) - cfg_type = 1; - - out_be32(hose->cfg_addr, - (((where & 0xfc) | cfg_type) << 24) | (devfn << 16) - | ((pbus->number - hose->bus_offset) << 8) | 0x80); - - switch (size) - { - case 1: - cfg_write(value, hose->cfg_data + (where & 3), u8, out_8); - break; - case 2: - cfg_write(value, hose->cfg_data + (where & 2), u16, out_le16); - break; - case 4: - cfg_write(value, hose->cfg_data + (where & 0), u32, out_le32); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static int indirect_read_config(struct pci_bus *pbus, unsigned int devfn, int where, - int size, u32 *value) -{ - struct pci_controller *hose = pbus->sysdata; - u8 cfg_type = 0; - if (ppc_md.pci_exclude_device) - if (ppc_md.pci_exclude_device(pbus->number, devfn)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (hose->set_cfg_type) - if (pbus->number != hose->first_busno) - cfg_type = 1; - - out_be32(hose->cfg_addr, - (((where & 0xfc) | cfg_type) << 24) | (devfn << 16) - | ((pbus->number - hose->bus_offset) << 8) | 0x80); - - switch (size) - { - case 1: - cfg_read(value, hose->cfg_data + (where & 3), u8 *, in_8); - break; - case 2: - cfg_read(value, hose->cfg_data + (where & 2), u16 *, in_le16); - break; - case 4: - cfg_read(value, hose->cfg_data + (where & 0), u32 *, in_le32); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops indirect_pci_ops = -{ - .read = indirect_read_config, - .write = indirect_write_config, -}; - -void -setup_m8260_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) -{ - hose->ops = &indirect_pci_ops; - hose->cfg_addr = (unsigned int *) ioremap(cfg_addr, 4); - hose->cfg_data = (unsigned char *) ioremap(cfg_data, 4); -} diff --git a/arch/ppc/syslib/m8260_setup.c b/arch/ppc/syslib/m8260_setup.c deleted file mode 100644 index b40583724de3..000000000000 --- a/arch/ppc/syslib/m8260_setup.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (C) 1995 Linus Torvalds - * Adapted from 'alpha' version by Gary Thomas - * Modified by Cort Dougan (cort@cs.nmt.edu) - * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net) - * Further modified for generic 8xx and 8260 by Dan. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpm2_pic.h" - -unsigned char __res[sizeof(bd_t)]; - -extern void pq2_find_bridges(void); -extern void pq2pci_init_irq(void); -extern void idma_pci9_init(void); - -/* Place-holder for board-specific init */ -void __attribute__ ((weak)) __init -m82xx_board_setup(void) -{ -} - -static void __init -m8260_setup_arch(void) -{ - /* Print out Vendor and Machine info. */ - printk(KERN_INFO "%s %s port\n", CPUINFO_VENDOR, CPUINFO_MACHINE); - - /* Reset the Communication Processor Module. */ - cpm2_reset(); -#ifdef CONFIG_8260_PCI9 - /* Initialise IDMA for PCI erratum workaround */ - idma_pci9_init(); -#endif -#ifdef CONFIG_PCI_8260 - pq2_find_bridges(); -#endif -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - ROOT_DEV = Root_RAM0; -#endif - - identify_ppc_sys_by_name_and_id(BOARD_CHIP_NAME, - in_be32((void *)CPM_MAP_ADDR + CPM_IMMR_OFFSET)); - - m82xx_board_setup(); -} - -/* The decrementer counts at the system (internal) clock frequency - * divided by four. - */ -static void __init -m8260_calibrate_decr(void) -{ - bd_t *binfo = (bd_t *)__res; - int freq, divisor; - - freq = binfo->bi_busfreq; - divisor = 4; - tb_ticks_per_jiffy = freq / HZ / divisor; - tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); -} - -/* The 8260 has an internal 1-second timer update register that - * we should use for this purpose. - */ -static uint rtc_time; - -static int -m8260_set_rtc_time(unsigned long time) -{ - rtc_time = time; - - return(0); -} - -static unsigned long -m8260_get_rtc_time(void) -{ - /* Get time from the RTC. - */ - return((unsigned long)rtc_time); -} - -#ifndef BOOTROM_RESTART_ADDR -#warning "Using default BOOTROM_RESTART_ADDR!" -#define BOOTROM_RESTART_ADDR 0xff000104 -#endif - -static void -m8260_restart(char *cmd) -{ - extern void m8260_gorom(bd_t *bi, uint addr); - uint startaddr; - - /* Most boot roms have a warmstart as the second instruction - * of the reset vector. If that doesn't work for you, change this - * or the reboot program to send a proper address. - */ - startaddr = BOOTROM_RESTART_ADDR; - if (cmd != NULL) { - if (!strncmp(cmd, "startaddr=", 10)) - startaddr = simple_strtoul(&cmd[10], NULL, 0); - } - - m8260_gorom((void*)__pa(__res), startaddr); -} - -static void -m8260_halt(void) -{ - local_irq_disable(); - while (1); -} - -static void -m8260_power_off(void) -{ - m8260_halt(); -} - -static int -m8260_show_cpuinfo(struct seq_file *m) -{ - bd_t *bp = (bd_t *)__res; - - seq_printf(m, "vendor\t\t: %s\n" - "machine\t\t: %s\n" - "\n" - "mem size\t\t: 0x%08lx\n" - "console baud\t\t: %ld\n" - "\n" - "core clock\t: %lu MHz\n" - "CPM clock\t: %lu MHz\n" - "bus clock\t: %lu MHz\n", - CPUINFO_VENDOR, CPUINFO_MACHINE, bp->bi_memsize, - bp->bi_baudrate, bp->bi_intfreq / 1000000, - bp->bi_cpmfreq / 1000000, bp->bi_busfreq / 1000000); - return 0; -} - -/* Initialize the internal interrupt controller. The number of - * interrupts supported can vary with the processor type, and the - * 8260 family can have up to 64. - * External interrupts can be either edge or level triggered, and - * need to be initialized by the appropriate driver. - */ -static void __init -m8260_init_IRQ(void) -{ - cpm2_init_IRQ(); - - /* Initialize the default interrupt mapping priorities, - * in case the boot rom changed something on us. - */ - cpm2_immr->im_intctl.ic_siprr = 0x05309770; -} - -/* - * Same hack as 8xx - */ -static unsigned long __init -m8260_find_end_of_memory(void) -{ - bd_t *binfo = (bd_t *)__res; - - return binfo->bi_memsize; -} - -/* Map the IMMR, plus anything else we can cover - * in that upper space according to the memory controller - * chip select mapping. Grab another bunch of space - * below that for stuff we can't cover in the upper. - */ -static void __init -m8260_map_io(void) -{ - uint addr; - - /* Map IMMR region to a 256MB BAT */ - addr = (cpm2_immr != NULL) ? (uint)cpm2_immr : CPM_MAP_ADDR; - io_block_mapping(addr, addr, 0x10000000, _PAGE_IO); - - /* Map I/O region to a 256MB BAT */ - io_block_mapping(IO_VIRT_ADDR, IO_PHYS_ADDR, 0x10000000, _PAGE_IO); -} - -/* Place-holder for board-specific ppc_md hooking */ -void __attribute__ ((weak)) __init -m82xx_board_init(void) -{ -} - -/* Inputs: - * r3 - Optional pointer to a board information structure. - * r4 - Optional pointer to the physical starting address of the init RAM - * disk. - * r5 - Optional pointer to the physical ending address of the init RAM - * disk. - * r6 - Optional pointer to the physical starting address of any kernel - * command-line parameters. - * r7 - Optional pointer to the physical ending address of any kernel - * command-line parameters. - */ -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - if ( r3 ) - memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); - -#ifdef CONFIG_BLK_DEV_INITRD - /* take care of initrd if we have one */ - if ( r4 ) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - /* take care of cmd line */ - if ( r6 ) { - *(char *)(r7+KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6+KERNELBASE)); - } - - ppc_md.setup_arch = m8260_setup_arch; - ppc_md.show_cpuinfo = m8260_show_cpuinfo; - ppc_md.init_IRQ = m8260_init_IRQ; - ppc_md.get_irq = cpm2_get_irq; - - ppc_md.restart = m8260_restart; - ppc_md.power_off = m8260_power_off; - ppc_md.halt = m8260_halt; - - ppc_md.set_rtc_time = m8260_set_rtc_time; - ppc_md.get_rtc_time = m8260_get_rtc_time; - ppc_md.calibrate_decr = m8260_calibrate_decr; - - ppc_md.find_end_of_memory = m8260_find_end_of_memory; - ppc_md.setup_io_mappings = m8260_map_io; - - /* Call back for board-specific settings and overrides. */ - m82xx_board_init(); -} diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c deleted file mode 100644 index 657a1c25a2ab..000000000000 --- a/arch/ppc/syslib/m82xx_pci.c +++ /dev/null @@ -1,346 +0,0 @@ -/* - * - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 Red Hat, Inc. - * - * 2005 (c) MontaVista Software, Inc. - * Vitaly Bordug - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "m82xx_pci.h" - -/* - * Interrupt routing - */ - -static inline int -pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -{ - static char pci_irq_table[][4] = - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - { - { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */ - { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */ - { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */ - }; - - const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4; - return PCI_IRQ_TABLE_LOOKUP; -} - -static void -pq2pci_mask_irq(unsigned int irq) -{ - int bit = irq - NR_CPM_INTS; - - *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit)); - return; -} - -static void -pq2pci_unmask_irq(unsigned int irq) -{ - int bit = irq - NR_CPM_INTS; - - *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit)); - return; -} - -static void -pq2pci_mask_and_ack(unsigned int irq) -{ - int bit = irq - NR_CPM_INTS; - - *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit)); - return; -} - -static void -pq2pci_end_irq(unsigned int irq) -{ - int bit = irq - NR_CPM_INTS; - - *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit)); - return; -} - -struct hw_interrupt_type pq2pci_ic = { - "PQ2 PCI", - NULL, - NULL, - pq2pci_unmask_irq, - pq2pci_mask_irq, - pq2pci_mask_and_ack, - pq2pci_end_irq, - 0 -}; - -static irqreturn_t -pq2pci_irq_demux(int irq, void *dev_id) -{ - unsigned long stat, mask, pend; - int bit; - - for(;;) { - stat = *(volatile unsigned long *) PCI_INT_STAT_REG; - mask = *(volatile unsigned long *) PCI_INT_MASK_REG; - pend = stat & ~mask & 0xf0000000; - if (!pend) - break; - for (bit = 0; pend != 0; ++bit, pend <<= 1) { - if (pend & 0x80000000) - __do_IRQ(NR_CPM_INTS + bit); - } - } - - return IRQ_HANDLED; -} - -static struct irqaction pq2pci_irqaction = { - .handler = pq2pci_irq_demux, - .flags = IRQF_DISABLED, - .mask = CPU_MASK_NONE, - .name = "PQ2 PCI cascade", -}; - - -void -pq2pci_init_irq(void) -{ - int irq; - volatile cpm2_map_t *immap = cpm2_immr; - for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++) - irq_desc[irq].chip = &pq2pci_ic; - - /* make PCI IRQ level sensitive */ - immap->im_intctl.ic_siexr &= - ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1))); - - /* mask all PCI interrupts */ - *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000; - - /* install the demultiplexer for the PCI cascade interrupt */ - setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction); - return; -} - -static int -pq2pci_exclude_device(u_char bus, u_char devfn) -{ - return PCIBIOS_SUCCESSFUL; -} - -/* PCI bus configuration registers. - */ -static void -pq2ads_setup_pci(struct pci_controller *hose) -{ - __u32 val; - volatile cpm2_map_t *immap = cpm2_immr; - bd_t* binfo = (bd_t*) __res; - u32 sccr = immap->im_clkrst.car_sccr; - uint pci_div,freq,time; - /* PCI int lowest prio */ - /* Each 4 bits is a device bus request and the MS 4bits - is highest priority */ - /* Bus 4bit value - --- ---------- - CPM high 0b0000 - CPM middle 0b0001 - CPM low 0b0010 - PCI request 0b0011 - Reserved 0b0100 - Reserved 0b0101 - Internal Core 0b0110 - External Master 1 0b0111 - External Master 2 0b1000 - External Master 3 0b1001 - The rest are reserved - */ - immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893; - /* park bus on core */ - immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE; - /* - * Set up master windows that allow the CPU to access PCI space. These - * windows are set up using the two SIU PCIBR registers. - */ - - immap->im_memctl.memc_pcimsk0 = M82xx_PCI_PRIM_WND_SIZE; - immap->im_memctl.memc_pcibr0 = M82xx_PCI_PRIM_WND_BASE | PCIBR_ENABLE; - -#ifdef M82xx_PCI_SEC_WND_SIZE - immap->im_memctl.memc_pcimsk1 = M82xx_PCI_SEC_WND_SIZE; - immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE; -#endif - - /* Enable PCI */ - immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN); - - pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) * - ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1); - freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div)); - time = (int)66666666/freq; - - /* due to PCI Local Bus spec, some devices needs to wait such a long - time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */ - printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq, - (time==1) ? "0.5 seconds":"1 second" ); - - { - int i; - for(i=0;i<(500*time);i++) - udelay(1000); - } - - /* setup ATU registers */ - immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO | - ((~(M82xx_PCI_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT)); - immap->im_pci.pci_potar0 = cpu_to_le32(M82xx_PCI_LOWER_IO >> POTA_ADDR_SHIFT); - immap->im_pci.pci_pobar0 = cpu_to_le32(M82xx_PCI_IO_BASE >> POTA_ADDR_SHIFT); - - /* Set-up non-prefetchable window */ - immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(M82xx_PCI_MMIO_SIZE-1U)) >> POTA_ADDR_SHIFT)); - immap->im_pci.pci_potar1 = cpu_to_le32(M82xx_PCI_LOWER_MMIO >> POTA_ADDR_SHIFT); - immap->im_pci.pci_pobar1 = cpu_to_le32((M82xx_PCI_LOWER_MMIO - M82xx_PCI_MMIO_OFFSET) >> POTA_ADDR_SHIFT); - - /* Set-up prefetchable window */ - immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN | - (~(M82xx_PCI_MEM_SIZE-1U) >> POTA_ADDR_SHIFT)); - immap->im_pci.pci_potar2 = cpu_to_le32(M82xx_PCI_LOWER_MEM >> POTA_ADDR_SHIFT); - immap->im_pci.pci_pobar2 = cpu_to_le32((M82xx_PCI_LOWER_MEM - M82xx_PCI_MEM_OFFSET) >> POTA_ADDR_SHIFT); - - /* Inbound transactions from PCI memory space */ - immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN | - ((~(M82xx_PCI_SLAVE_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT)); - immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT); - immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT); - - /* park bus on PCI */ - immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; - - /* Enable bus mastering and inbound memory transactions */ - early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val); - val &= 0xffff0000; - val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER; - early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val); - -} - -void __init pq2_find_bridges(void) -{ - extern int pci_assign_all_buses; - struct pci_controller * hose; - int host_bridge; - - pci_assign_all_buses = 1; - - hose = pcibios_alloc_controller(); - - if (!hose) - return; - - ppc_md.pci_swizzle = common_swizzle; - - hose->first_busno = 0; - hose->bus_offset = 0; - hose->last_busno = 0xff; - - setup_m8260_indirect_pci(hose, - (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr, - (unsigned long)&cpm2_immr->im_pci.pci_cfg_data); - - /* Make sure it is a supported bridge */ - early_read_config_dword(hose, - 0, - PCI_DEVFN(0,0), - PCI_VENDOR_ID, - &host_bridge); - switch (host_bridge) { - case PCI_DEVICE_ID_MPC8265: - break; - case PCI_DEVICE_ID_MPC8272: - break; - default: - printk("Attempting to use unrecognized host bridge ID" - " 0x%08x.\n", host_bridge); - break; - } - - pq2ads_setup_pci(hose); - - hose->io_space.start = M82xx_PCI_LOWER_IO; - hose->io_space.end = M82xx_PCI_UPPER_IO; - hose->mem_space.start = M82xx_PCI_LOWER_MEM; - hose->mem_space.end = M82xx_PCI_UPPER_MMIO; - hose->pci_mem_offset = M82xx_PCI_MEM_OFFSET; - - isa_io_base = - (unsigned long) ioremap(M82xx_PCI_IO_BASE, - M82xx_PCI_IO_SIZE); - hose->io_base_virt = (void *) isa_io_base; - - /* setup resources */ - pci_init_resource(&hose->mem_resources[0], - M82xx_PCI_LOWER_MEM, - M82xx_PCI_UPPER_MEM, - IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory"); - - pci_init_resource(&hose->mem_resources[1], - M82xx_PCI_LOWER_MMIO, - M82xx_PCI_UPPER_MMIO, - IORESOURCE_MEM, "PCI memory"); - - pci_init_resource(&hose->io_resource, - M82xx_PCI_LOWER_IO, - M82xx_PCI_UPPER_IO, - IORESOURCE_IO | 1, "PCI I/O"); - - ppc_md.pci_exclude_device = pq2pci_exclude_device; - hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); - - ppc_md.pci_map_irq = pq2pci_map_irq; - ppc_md.pcibios_fixup = NULL; - ppc_md.pcibios_fixup_bus = NULL; - -} diff --git a/arch/ppc/syslib/m82xx_pci.h b/arch/ppc/syslib/m82xx_pci.h deleted file mode 100644 index 924f73f8e595..000000000000 --- a/arch/ppc/syslib/m82xx_pci.h +++ /dev/null @@ -1,92 +0,0 @@ - -#ifndef _PPC_KERNEL_M82XX_PCI_H -#define _PPC_KERNEL_M82XX_PCI_H - -#include -/* - * Local->PCI map (from CPU) controlled by - * MPC826x master window - * - * 0xF6000000 - 0xF7FFFFFF IO space - * 0x80000000 - 0xBFFFFFFF CPU2PCI memory space PCIBR0 - * - * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1) - * 0xA0000000 - 0xBFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2) - * 0xF6000000 - 0xF7FFFFFF 32-bit PCI IO (Outbound ATU #3) - * - * PCI->Local map (from PCI) - * MPC826x slave window controlled by - * - * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1) - */ - -/* - * Slave window that allows PCI masters to access MPC826x local memory. - * This window is set up using the first set of Inbound ATU registers - */ - -#ifndef M82xx_PCI_SLAVE_MEM_LOCAL -#define M82xx_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart) -#define M82xx_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart) -#define M82xx_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize) -#endif - -/* - * This is the window that allows the CPU to access PCI address space. - * It will be setup with the SIU PCIBR0 register. All three PCI master - * windows, which allow the CPU to access PCI prefetch, non prefetch, - * and IO space (see below), must all fit within this window. - */ - -#ifndef M82xx_PCI_LOWER_MEM -#define M82xx_PCI_LOWER_MEM 0x80000000 -#define M82xx_PCI_UPPER_MEM 0x9fffffff -#define M82xx_PCI_MEM_OFFSET 0x00000000 -#define M82xx_PCI_MEM_SIZE 0x20000000 -#endif - -#ifndef M82xx_PCI_LOWER_MMIO -#define M82xx_PCI_LOWER_MMIO 0xa0000000 -#define M82xx_PCI_UPPER_MMIO 0xafffffff -#define M82xx_PCI_MMIO_OFFSET 0x00000000 -#define M82xx_PCI_MMIO_SIZE 0x20000000 -#endif - -#ifndef M82xx_PCI_LOWER_IO -#define M82xx_PCI_LOWER_IO 0x00000000 -#define M82xx_PCI_UPPER_IO 0x01ffffff -#define M82xx_PCI_IO_BASE 0xf6000000 -#define M82xx_PCI_IO_SIZE 0x02000000 -#endif - -#ifndef M82xx_PCI_PRIM_WND_SIZE -#define M82xx_PCI_PRIM_WND_SIZE ~(M82xx_PCI_IO_SIZE - 1U) -#define M82xx_PCI_PRIM_WND_BASE (M82xx_PCI_IO_BASE) -#endif - -#ifndef M82xx_PCI_SEC_WND_SIZE -#define M82xx_PCI_SEC_WND_SIZE ~(M82xx_PCI_MEM_SIZE + M82xx_PCI_MMIO_SIZE - 1U) -#define M82xx_PCI_SEC_WND_BASE (M82xx_PCI_LOWER_MEM) -#endif - -#ifndef POTA_ADDR_SHIFT -#define POTA_ADDR_SHIFT 12 -#endif - -#ifndef PITA_ADDR_SHIFT -#define PITA_ADDR_SHIFT 12 -#endif - -#ifndef _IO_BASE -#define _IO_BASE isa_io_base -#endif - -#ifdef CONFIG_8260_PCI9 -struct pci_controller; -extern void setup_m8260_indirect_pci(struct pci_controller* hose, - u32 cfg_addr, u32 cfg_data); -#else -#define setup_m8260_indirect_pci setup_indirect_pci -#endif - -#endif /* _PPC_KERNEL_M8260_PCI_H */ diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c deleted file mode 100644 index 18da720fc1b0..000000000000 --- a/arch/ppc/syslib/m8xx_setup.c +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (C) 1995 Linus Torvalds - * Adapted from 'alpha' version by Gary Thomas - * Modified by Cort Dougan (cort@cs.nmt.edu) - * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net) - * Further modified for generic 8xx by Dan. - */ - -/* - * bootup setup stuff.. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP) -#include -#include -#include -#include -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ppc8xx_pic.h" - -#ifdef CONFIG_MTD_PHYSMAP -#define MPC8xxADS_BANK_WIDTH 4 -#endif - -#define MPC8xxADS_U_BOOT_SIZE 0x80000 -#define MPC8xxADS_FREE_AREA_OFFSET MPC8xxADS_U_BOOT_SIZE - -#if defined(CONFIG_MTD_PARTITIONS) - /* - NOTE: bank width and interleave relative to the installed flash - should have been chosen within MTD_CFI_GEOMETRY options. - */ -static struct mtd_partition mpc8xxads_partitions[] = { - { - .name = "bootloader", - .size = MPC8xxADS_U_BOOT_SIZE, - .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - .name = "User FS", - .offset = MPC8xxADS_FREE_AREA_OFFSET - } -}; - -#define mpc8xxads_part_num ARRAY_SIZE(mpc8xxads_partitions) - -#endif - -static int m8xx_set_rtc_time(unsigned long time); -static unsigned long m8xx_get_rtc_time(void); -void m8xx_calibrate_decr(void); - -unsigned char __res[sizeof(bd_t)]; - -extern unsigned long find_available_memory(void); -extern void m8xx_cpm_reset(void); -extern void m8xx_wdt_handler_install(bd_t *bp); -extern void rpxfb_alloc_pages(void); -extern void cpm_interrupt_init(void); - -void __attribute__ ((weak)) -board_init(void) -{ -} - -void __init -m8xx_setup_arch(void) -{ -#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP) - bd_t *binfo = (bd_t *)__res; -#endif - - /* Reset the Communication Processor Module. - */ - m8xx_cpm_reset(); - -#ifdef CONFIG_FB_RPX - rpxfb_alloc_pages(); -#endif - -#ifdef notdef - ROOT_DEV = Root_HDA1; /* hda1 */ -#endif - -#ifdef CONFIG_BLK_DEV_INITRD -#if 0 - ROOT_DEV = Root_FD0; /* floppy */ - rd_prompt = 1; - rd_doload = 1; - rd_image_start = 0; -#endif -#if 0 /* XXX this may need to be updated for the new bootmem stuff, - or possibly just deleted (see set_phys_avail() in init.c). - - paulus. */ - /* initrd_start and size are setup by boot/head.S and kernel/head.S */ - if ( initrd_start ) - { - if (initrd_end > *memory_end_p) - { - printk("initrd extends beyond end of memory " - "(0x%08lx > 0x%08lx)\ndisabling initrd\n", - initrd_end,*memory_end_p); - initrd_start = 0; - } - } -#endif -#endif - - board_init(); -} - -void -abort(void) -{ -#ifdef CONFIG_XMON - xmon(0); -#endif - machine_restart(NULL); - - /* not reached */ - for (;;); -} - -/* A place holder for time base interrupts, if they are ever enabled. */ -irqreturn_t timebase_interrupt(int irq, void * dev) -{ - printk ("timebase_interrupt()\n"); - - return IRQ_HANDLED; -} - -static struct irqaction tbint_irqaction = { - .handler = timebase_interrupt, - .mask = CPU_MASK_NONE, - .name = "tbint", -}; - -/* per-board overridable init_internal_rtc() function. */ -void __init __attribute__ ((weak)) -init_internal_rtc(void) -{ - /* Disable the RTC one second and alarm interrupts. */ - clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE)); - - /* Enable the RTC */ - setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE)); - -} - -/* The decrementer counts at the system (internal) clock frequency divided by - * sixteen, or external oscillator divided by four. We force the processor - * to use system clock divided by sixteen. - */ -void __init m8xx_calibrate_decr(void) -{ - bd_t *binfo = (bd_t *)__res; - int freq, fp, divisor; - - /* Unlock the SCCR. */ - out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, ~KAPWR_KEY); - out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY); - - /* Force all 8xx processors to use divide by 16 processor clock. */ - setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000); - /* Processor frequency is MHz. - * The value 'fp' is the number of decrementer ticks per second. - */ - fp = binfo->bi_intfreq / 16; - freq = fp*60; /* try to make freq/1e6 an integer */ - divisor = 60; - printk("Decrementer Frequency = %d/%d\n", freq, divisor); - tb_ticks_per_jiffy = freq / HZ / divisor; - tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); - - /* Perform some more timer/timebase initialization. This used - * to be done elsewhere, but other changes caused it to get - * called more than once....that is a bad thing. - * - * First, unlock all of the registers we are going to modify. - * To protect them from corruption during power down, registers - * that are maintained by keep alive power are "locked". To - * modify these registers we have to write the key value to - * the key location associated with the register. - * Some boards power up with these unlocked, while others - * are locked. Writing anything (including the unlock code?) - * to the unlocked registers will lock them again. So, here - * we guarantee the registers are locked, then we unlock them - * for our use. - */ - out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, ~KAPWR_KEY); - out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, ~KAPWR_KEY); - out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, ~KAPWR_KEY); - out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, KAPWR_KEY); - out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY); - out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY); - - init_internal_rtc(); - - /* Enabling the decrementer also enables the timebase interrupts - * (or from the other point of view, to get decrementer interrupts - * we have to enable the timebase). The decrementer interrupt - * is wired into the vector table, nothing to do here for that. - */ - out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_tbscr, (mk_int_int_mask(DEC_INTERRUPT) << 8) | (TBSCR_TBF | TBSCR_TBE)); - - if (setup_irq(DEC_INTERRUPT, &tbint_irqaction)) - panic("Could not allocate timer IRQ!"); - -#ifdef CONFIG_8xx_WDT - /* Install watchdog timer handler early because it might be - * already enabled by the bootloader - */ - m8xx_wdt_handler_install(binfo); -#endif -} - -/* The RTC on the MPC8xx is an internal register. - * We want to protect this during power down, so we need to unlock, - * modify, and re-lock. - */ -static int -m8xx_set_rtc_time(unsigned long time) -{ - out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, KAPWR_KEY); - out_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc, time); - out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, ~KAPWR_KEY); - return(0); -} - -static unsigned long -m8xx_get_rtc_time(void) -{ - /* Get time from the RTC. */ - return (unsigned long) in_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc); -} - -static void -m8xx_restart(char *cmd) -{ - __volatile__ unsigned char dummy; - - local_irq_disable(); - - setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080); - /* Clear the ME bit in MSR to cause checkstop on machine check - */ - mtmsr(mfmsr() & ~0x1000); - - dummy = in_8(&((immap_t *)IMAP_ADDR)->im_clkrst.res[0]); - printk("Restart failed\n"); - while(1); -} - -static void -m8xx_power_off(void) -{ - m8xx_restart(NULL); -} - -static void -m8xx_halt(void) -{ - m8xx_restart(NULL); -} - - -static int -m8xx_show_percpuinfo(struct seq_file *m, int i) -{ - bd_t *bp; - - bp = (bd_t *)__res; - - seq_printf(m, "clock\t\t: %uMHz\n" - "bus clock\t: %uMHz\n", - bp->bi_intfreq / 1000000, - bp->bi_busfreq / 1000000); - - return 0; -} - -#ifdef CONFIG_PCI -static struct irqaction mbx_i8259_irqaction = { - .handler = mbx_i8259_action, - .mask = CPU_MASK_NONE, - .name = "i8259 cascade", -}; -#endif - -/* Initialize the internal interrupt controller. The number of - * interrupts supported can vary with the processor type, and the - * 82xx family can have up to 64. - * External interrupts can be either edge or level triggered, and - * need to be initialized by the appropriate driver. - */ -static void __init -m8xx_init_IRQ(void) -{ - int i; - - for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++) - irq_desc[i].chip = &ppc8xx_pic; - - cpm_interrupt_init(); - -#if defined(CONFIG_PCI) - for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++) - irq_desc[i].chip = &i8259_pic; - - i8259_pic_irq_offset = I8259_IRQ_OFFSET; - i8259_init(0); - - /* The i8259 cascade interrupt must be level sensitive. */ - - clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT)); - if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction)) - enable_irq(ISA_BRIDGE_INT); -#endif /* CONFIG_PCI */ -} - -/* -------------------------------------------------------------------- */ - -/* - * This is a big hack right now, but it may turn into something real - * someday. - * - * For the 8xx boards (at this time anyway), there is nothing to initialize - * associated the PROM. Rather than include all of the prom.c - * functions in the image just to get prom_init, all we really need right - * now is the initialization of the physical memory region. - */ -static unsigned long __init -m8xx_find_end_of_memory(void) -{ - bd_t *binfo; - extern unsigned char __res[]; - - binfo = (bd_t *)__res; - - return binfo->bi_memsize; -} - -/* - * Now map in some of the I/O space that is generically needed - * or shared with multiple devices. - * All of this fits into the same 4Mbyte region, so it only - * requires one page table page. (or at least it used to -- paulus) - */ -static void __init -m8xx_map_io(void) -{ - io_block_mapping(IMAP_ADDR, IMAP_ADDR, IMAP_SIZE, _PAGE_IO); -#ifdef CONFIG_MBX - io_block_mapping(NVRAM_ADDR, NVRAM_ADDR, NVRAM_SIZE, _PAGE_IO); - io_block_mapping(MBX_CSR_ADDR, MBX_CSR_ADDR, MBX_CSR_SIZE, _PAGE_IO); - io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO); - - /* Map some of the PCI/ISA I/O space to get the IDE interface. - */ - io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO); - io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO); -#endif -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) - io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO); -#if !defined(CONFIG_PCI) - io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO); -#endif -#endif -#if defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX) - io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO); -#endif -#ifdef CONFIG_FADS - io_block_mapping(BCSR_ADDR, BCSR_ADDR, BCSR_SIZE, _PAGE_IO); -#endif -#ifdef CONFIG_PCI - io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO); -#endif -#if defined(CONFIG_NETTA) - io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO); -#endif -} - -void __init -platform_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - if ( r3 ) - memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); - -#ifdef CONFIG_PCI - m8xx_setup_pci_ptrs(); -#endif - -#ifdef CONFIG_BLK_DEV_INITRD - /* take care of initrd if we have one */ - if ( r4 ) - { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - /* take care of cmd line */ - if ( r6 ) - { - *(char *)(r7+KERNELBASE) = 0; - strcpy(cmd_line, (char *)(r6+KERNELBASE)); - } - - identify_ppc_sys_by_name(BOARD_CHIP_NAME); - - ppc_md.setup_arch = m8xx_setup_arch; - ppc_md.show_percpuinfo = m8xx_show_percpuinfo; - ppc_md.init_IRQ = m8xx_init_IRQ; - ppc_md.get_irq = m8xx_get_irq; - ppc_md.init = NULL; - - ppc_md.restart = m8xx_restart; - ppc_md.power_off = m8xx_power_off; - ppc_md.halt = m8xx_halt; - - ppc_md.time_init = NULL; - ppc_md.set_rtc_time = m8xx_set_rtc_time; - ppc_md.get_rtc_time = m8xx_get_rtc_time; - ppc_md.calibrate_decr = m8xx_calibrate_decr; - - ppc_md.find_end_of_memory = m8xx_find_end_of_memory; - ppc_md.setup_io_mappings = m8xx_map_io; -} diff --git a/arch/ppc/syslib/m8xx_wdt.c b/arch/ppc/syslib/m8xx_wdt.c deleted file mode 100644 index fffac8cbeb51..000000000000 --- a/arch/ppc/syslib/m8xx_wdt.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * m8xx_wdt.c - MPC8xx watchdog driver - * - * Author: Florian Schirmer - * - * 2002 (c) Florian Schirmer This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static int wdt_timeout; -int m8xx_has_internal_rtc = 0; - -static irqreturn_t m8xx_wdt_interrupt(int, void *); -static struct irqaction m8xx_wdt_irqaction = { - .handler = m8xx_wdt_interrupt, - .name = "watchdog", -}; - -void m8xx_wdt_reset(void) -{ - volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR; - - out_be16(&imap->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */ - out_be16(&imap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */ -} - -static irqreturn_t m8xx_wdt_interrupt(int irq, void *dev) -{ - volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR; - - m8xx_wdt_reset(); - - setbits16(&imap->im_sit.sit_piscr, PISCR_PS); - return IRQ_HANDLED; -} - -#define SYPCR_SWP 0x1 -#define SYPCR_SWE 0x4 - - -void __init m8xx_wdt_install_irq(volatile immap_t *imap, bd_t *binfo) -{ - u32 pitc; - u32 pitrtclk; - - /* - * Fire trigger if half of the wdt ticked down - */ - - if (imap->im_sit.sit_rtcsc & RTCSC_38K) - pitrtclk = 9600; - else - pitrtclk = 8192; - - if ((wdt_timeout) > (UINT_MAX / pitrtclk)) - pitc = wdt_timeout / binfo->bi_intfreq * pitrtclk / 2; - else - pitc = pitrtclk * wdt_timeout / binfo->bi_intfreq / 2; - - out_be32(&imap->im_sit.sit_pitc, pitc << 16); - - out_be16(&imap->im_sit.sit_piscr, (mk_int_int_mask(PIT_INTERRUPT) << 8) | PISCR_PIE | PISCR_PTE); - - if (setup_irq(PIT_INTERRUPT, &m8xx_wdt_irqaction)) - panic("m8xx_wdt: error setting up the watchdog irq!"); - - printk(KERN_NOTICE - "m8xx_wdt: keep-alive trigger installed (PITC: 0x%04X)\n", pitc); - -} - -static void m8xx_wdt_timer_func(unsigned long data); - -static struct timer_list m8xx_wdt_timer = - TIMER_INITIALIZER(m8xx_wdt_timer_func, 0, 0); - -void m8xx_wdt_stop_timer(void) -{ - del_timer(&m8xx_wdt_timer); -} - -void m8xx_wdt_install_timer(void) -{ - m8xx_wdt_timer.expires = jiffies + (HZ/2); - add_timer(&m8xx_wdt_timer); -} - -static void m8xx_wdt_timer_func(unsigned long data) -{ - m8xx_wdt_reset(); - m8xx_wdt_install_timer(); -} - -void __init m8xx_wdt_handler_install(bd_t * binfo) -{ - volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR; - u32 sypcr; - - sypcr = in_be32(&imap->im_siu_conf.sc_sypcr); - - if (!(sypcr & SYPCR_SWE)) { - printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n", - sypcr); - return; - } - - m8xx_wdt_reset(); - - printk(KERN_NOTICE - "m8xx_wdt: active wdt found (SWTC: 0x%04X, SWP: 0x%01X)\n", - (sypcr >> 16), sypcr & SYPCR_SWP); - - wdt_timeout = (sypcr >> 16) & 0xFFFF; - - if (!wdt_timeout) - wdt_timeout = 0xFFFF; - - if (sypcr & SYPCR_SWP) - wdt_timeout *= 2048; - - m8xx_has_internal_rtc = in_be16(&imap->im_sit.sit_rtcsc) & RTCSC_RTE; - - /* if the internal RTC is off use a kernel timer */ - if (!m8xx_has_internal_rtc) { - if (wdt_timeout < (binfo->bi_intfreq/HZ)) - printk(KERN_ERR "m8xx_wdt: timeout too short for ktimer!\n"); - m8xx_wdt_install_timer(); - } else - m8xx_wdt_install_irq(imap, binfo); - - wdt_timeout /= binfo->bi_intfreq; -} - -int m8xx_wdt_get_timeout(void) -{ - return wdt_timeout; -} diff --git a/arch/ppc/syslib/m8xx_wdt.h b/arch/ppc/syslib/m8xx_wdt.h deleted file mode 100644 index e75835f0012b..000000000000 --- a/arch/ppc/syslib/m8xx_wdt.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Author: Florian Schirmer - * - * 2002 (c) Florian Schirmer This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef _PPC_SYSLIB_M8XX_WDT_H -#define _PPC_SYSLIB_M8XX_WDT_H - -extern int m8xx_has_internal_rtc; - -extern void m8xx_wdt_handler_install(bd_t * binfo); -extern int m8xx_wdt_get_timeout(void); -extern void m8xx_wdt_reset(void); -extern void m8xx_wdt_install_timer(void); -extern void m8xx_wdt_stop_timer(void); - -#endif /* _PPC_SYSLIB_M8XX_WDT_H */ diff --git a/arch/ppc/syslib/mpc10x_common.c b/arch/ppc/syslib/mpc10x_common.c deleted file mode 100644 index 437a294527a9..000000000000 --- a/arch/ppc/syslib/mpc10x_common.c +++ /dev/null @@ -1,654 +0,0 @@ -/* - * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge, - * Mem ctlr, EPIC, etc. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * *** WARNING - A BAT MUST be set to access the PCI config addr/data regs *** - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_MPC10X_OPENPIC -#ifdef CONFIG_EPIC_SERIAL_MODE -#define EPIC_IRQ_BASE (epic_serial_mode ? 16 : 5) -#else -#define EPIC_IRQ_BASE 5 -#endif -#define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS) -#define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS) -#define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS) -#define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS) -#define MPC10X_UART1_IRQ (EPIC_IRQ_BASE + 5 + NUM_8259_INTERRUPTS) -#else -#define MPC10X_I2C_IRQ -1 -#define MPC10X_DMA0_IRQ -1 -#define MPC10X_DMA1_IRQ -1 -#define MPC10X_UART0_IRQ -1 -#define MPC10X_UART1_IRQ -1 -#endif - -static struct fsl_i2c_platform_data mpc10x_i2c_pdata = { - .device_flags = 0, -}; - -static struct plat_serial8250_port serial_plat_uart0[] = { - [0] = { - .mapbase = 0x4500, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { }, -}; -static struct plat_serial8250_port serial_plat_uart1[] = { - [0] = { - .mapbase = 0x4600, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { }, -}; - -struct platform_device ppc_sys_platform_devices[] = { - [MPC10X_IIC1] = { - .name = "fsl-i2c", - .id = 1, - .dev.platform_data = &mpc10x_i2c_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC10X_EUMB_I2C_OFFSET, - .end = MPC10X_EUMB_I2C_OFFSET + - MPC10X_EUMB_I2C_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .flags = IORESOURCE_IRQ - }, - }, - }, - [MPC10X_DMA0] = { - .name = "fsl-dma", - .id = 0, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC10X_EUMB_DMA_OFFSET + 0x10, - .end = MPC10X_EUMB_DMA_OFFSET + 0x1f, - .flags = IORESOURCE_MEM, - }, - { - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC10X_DMA1] = { - .name = "fsl-dma", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC10X_EUMB_DMA_OFFSET + 0x20, - .end = MPC10X_EUMB_DMA_OFFSET + 0x2f, - .flags = IORESOURCE_MEM, - }, - { - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC10X_DMA1] = { - .name = "fsl-dma", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC10X_EUMB_DMA_OFFSET + 0x20, - .end = MPC10X_EUMB_DMA_OFFSET + 0x2f, - .flags = IORESOURCE_MEM, - }, - { - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC10X_UART0] = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = serial_plat_uart0, - }, - [MPC10X_UART1] = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev.platform_data = serial_plat_uart1, - }, - -}; - -/* We use the PCI ID to match on */ -struct ppc_sys_spec *cur_ppc_sys_spec; -struct ppc_sys_spec ppc_sys_specs[] = { - { - .ppc_sys_name = "8245", - .mask = 0xFFFFFFFF, - .value = MPC10X_BRIDGE_8245, - .num_devices = 5, - .device_list = (enum ppc_sys_devices[]) - { - MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_UART0, MPC10X_UART1, - }, - }, - { - .ppc_sys_name = "8240", - .mask = 0xFFFFFFFF, - .value = MPC10X_BRIDGE_8240, - .num_devices = 3, - .device_list = (enum ppc_sys_devices[]) - { - MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, - }, - }, - { - .ppc_sys_name = "107", - .mask = 0xFFFFFFFF, - .value = MPC10X_BRIDGE_107, - .num_devices = 3, - .device_list = (enum ppc_sys_devices[]) - { - MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, - }, - }, - { /* default match */ - .ppc_sys_name = "", - .mask = 0x00000000, - .value = 0x00000000, - }, -}; - -/* - * mach_mpc10x_fixup: This function enables DUART mode if it detects - * if it detects two UARTS in the platform device entries. - */ -static int __init mach_mpc10x_fixup(struct platform_device *pdev) -{ - if (strncmp (pdev->name, "serial8250", 10) == 0 && pdev->id == 1) - writeb(readb(serial_plat_uart1[0].membase + 0x11) | 0x1, - serial_plat_uart1[0].membase + 0x11); - return 0; -} - -static int __init mach_mpc10x_init(void) -{ - ppc_sys_device_fixup = mach_mpc10x_fixup; - return 0; -} -postcore_initcall(mach_mpc10x_init); - -/* Set resources to match bridge memory map */ -void __init -mpc10x_bridge_set_resources(int map, struct pci_controller *hose) -{ - - switch (map) { - case MPC10X_MEM_MAP_A: - pci_init_resource(&hose->io_resource, - 0x00000000, - 0x3f7fffff, - IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource (&hose->mem_resources[0], - 0xc0000000, - 0xfeffffff, - IORESOURCE_MEM, - "PCI host bridge"); - break; - case MPC10X_MEM_MAP_B: - pci_init_resource(&hose->io_resource, - 0x00000000, - 0x00bfffff, - IORESOURCE_IO, - "PCI host bridge"); - - pci_init_resource (&hose->mem_resources[0], - 0x80000000, - 0xfcffffff, - IORESOURCE_MEM, - "PCI host bridge"); - break; - default: - printk("mpc10x_bridge_set_resources: " - "Invalid map specified\n"); - if (ppc_md.progress) - ppc_md.progress("mpc10x:exit1", 0x100); - } -} - -/* - * Do some initialization and put the EUMB registers at the specified address - * (also map the EPIC registers into virtual space--OpenPIC_Addr will be set). - * - * The EPIC is not on the 106, only the 8240 and 107. - */ -int __init -mpc10x_bridge_init(struct pci_controller *hose, - uint current_map, - uint new_map, - uint phys_eumb_base) -{ - int host_bridge, picr1, picr1_bit, i; - ulong pci_config_addr, pci_config_data; - u_char pir, byte; - - if (ppc_md.progress) ppc_md.progress("mpc10x:enter", 0x100); - - /* Set up for current map so we can get at config regs */ - switch (current_map) { - case MPC10X_MEM_MAP_A: - setup_indirect_pci(hose, - MPC10X_MAPA_CNFG_ADDR, - MPC10X_MAPA_CNFG_DATA); - break; - case MPC10X_MEM_MAP_B: - setup_indirect_pci(hose, - MPC10X_MAPB_CNFG_ADDR, - MPC10X_MAPB_CNFG_DATA); - break; - default: - printk("mpc10x_bridge_init: %s\n", - "Invalid current map specified"); - if (ppc_md.progress) - ppc_md.progress("mpc10x:exit1", 0x100); - return -1; - } - - /* Make sure it's a supported bridge */ - early_read_config_dword(hose, - 0, - PCI_DEVFN(0,0), - PCI_VENDOR_ID, - &host_bridge); - - switch (host_bridge) { - case MPC10X_BRIDGE_106: - case MPC10X_BRIDGE_8240: - case MPC10X_BRIDGE_107: - case MPC10X_BRIDGE_8245: - break; - default: - if (ppc_md.progress) - ppc_md.progress("mpc10x:exit2", 0x100); - return -1; - } - - switch (new_map) { - case MPC10X_MEM_MAP_A: - MPC10X_SETUP_HOSE(hose, A); - pci_config_addr = MPC10X_MAPA_CNFG_ADDR; - pci_config_data = MPC10X_MAPA_CNFG_DATA; - picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_A; - break; - case MPC10X_MEM_MAP_B: - MPC10X_SETUP_HOSE(hose, B); - pci_config_addr = MPC10X_MAPB_CNFG_ADDR; - pci_config_data = MPC10X_MAPB_CNFG_DATA; - picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_B; - break; - default: - printk("mpc10x_bridge_init: %s\n", - "Invalid new map specified"); - if (ppc_md.progress) - ppc_md.progress("mpc10x:exit3", 0x100); - return -1; - } - - /* Make bridge use the 'new_map', if not already usng it */ - if (current_map != new_map) { - early_read_config_dword(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_PICR1_REG, - &picr1); - - picr1 = (picr1 & ~MPC10X_CFG_PICR1_ADDR_MAP_MASK) | - picr1_bit; - - early_write_config_dword(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_PICR1_REG, - picr1); - - asm volatile("sync"); - - /* Undo old mappings & map in new cfg data/addr regs */ - iounmap((void *)hose->cfg_addr); - iounmap((void *)hose->cfg_data); - - setup_indirect_pci(hose, - pci_config_addr, - pci_config_data); - } - - /* Setup resources to match map */ - mpc10x_bridge_set_resources(new_map, hose); - - /* - * Want processor accesses of 0xFDxxxxxx to be mapped - * to PCI memory space at 0x00000000. Do not want - * host bridge to respond to PCI memory accesses of - * 0xFDxxxxxx. Do not want host bridge to respond - * to PCI memory addresses 0xFD000000-0xFDFFFFFF; - * want processor accesses from 0x000A0000-0x000BFFFF - * to be forwarded to system memory. - * - * Only valid if not in agent mode and using MAP B. - */ - if (new_map == MPC10X_MEM_MAP_B) { - early_read_config_byte(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_MAPB_OPTIONS_REG, - &byte); - - byte &= ~(MPC10X_CFG_MAPB_OPTIONS_PFAE | - MPC10X_CFG_MAPB_OPTIONS_PCICH | - MPC10X_CFG_MAPB_OPTIONS_PROCCH); - - if (host_bridge != MPC10X_BRIDGE_106) { - byte |= MPC10X_CFG_MAPB_OPTIONS_CFAE; - } - - early_write_config_byte(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_MAPB_OPTIONS_REG, - byte); - } - - if (host_bridge != MPC10X_BRIDGE_106) { - early_read_config_byte(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_PIR_REG, - &pir); - - if (pir != MPC10X_CFG_PIR_HOST_BRIDGE) { - printk("Host bridge in Agent mode\n"); - /* Read or Set LMBAR & PCSRBAR? */ - } - - /* Set base addr of the 8240/107 EUMB. */ - early_write_config_dword(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_EUMBBAR, - phys_eumb_base); -#ifdef CONFIG_MPC10X_OPENPIC - /* Map EPIC register part of EUMB into vitual memory - PCORE - uses an i8259 instead of EPIC. */ - OpenPIC_Addr = - ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET, - MPC10X_EUMB_EPIC_SIZE); -#endif - } - -#ifdef CONFIG_MPC10X_STORE_GATHERING - mpc10x_enable_store_gathering(hose); -#else - mpc10x_disable_store_gathering(hose); -#endif - - /* setup platform devices for MPC10x bridges */ - identify_ppc_sys_by_id (host_bridge); - - for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) { - unsigned int dev_id = cur_ppc_sys_spec->device_list[i]; - ppc_sys_fixup_mem_resource(&ppc_sys_platform_devices[dev_id], - phys_eumb_base); - } - - /* IRQs are determined at runtime */ - ppc_sys_platform_devices[MPC10X_IIC1].resource[1].start = MPC10X_I2C_IRQ; - ppc_sys_platform_devices[MPC10X_IIC1].resource[1].end = MPC10X_I2C_IRQ; - ppc_sys_platform_devices[MPC10X_DMA0].resource[1].start = MPC10X_DMA0_IRQ; - ppc_sys_platform_devices[MPC10X_DMA0].resource[1].end = MPC10X_DMA0_IRQ; - ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ; - ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ; - - serial_plat_uart0[0].mapbase += phys_eumb_base; - serial_plat_uart0[0].irq = MPC10X_UART0_IRQ; - serial_plat_uart0[0].membase = ioremap(serial_plat_uart0[0].mapbase, 0x100); - - serial_plat_uart1[0].mapbase += phys_eumb_base; - serial_plat_uart1[0].irq = MPC10X_UART1_IRQ; - serial_plat_uart1[0].membase = ioremap(serial_plat_uart1[0].mapbase, 0x100); - - /* - * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative - * PCI reads may return stale data so turn off. - */ - if ((host_bridge == MPC10X_BRIDGE_8240) - || (host_bridge == MPC10X_BRIDGE_8245) - || (host_bridge == MPC10X_BRIDGE_107)) { - - early_read_config_dword(hose, 0, PCI_DEVFN(0,0), - MPC10X_CFG_PICR1_REG, &picr1); - - picr1 &= ~MPC10X_CFG_PICR1_SPEC_PCI_RD; - - early_write_config_dword(hose, 0, PCI_DEVFN(0,0), - MPC10X_CFG_PICR1_REG, picr1); - } - - /* - * 8241/8245 erratum 28: PCI reads from local memory may return - * stale data. Workaround by setting PICR2[0] to disable copyback - * optimization. Oddly, the latest available user manual for the - * 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd. - */ - if (host_bridge == MPC10X_BRIDGE_8245) { - u32 picr2; - - early_read_config_dword(hose, 0, PCI_DEVFN(0,0), - MPC10X_CFG_PICR2_REG, &picr2); - - picr2 |= MPC10X_CFG_PICR2_COPYBACK_OPT; - - early_write_config_dword(hose, 0, PCI_DEVFN(0,0), - MPC10X_CFG_PICR2_REG, picr2); - } - - if (ppc_md.progress) ppc_md.progress("mpc10x:exit", 0x100); - return 0; -} - -/* - * Need to make our own PCI config space access macros because - * mpc10x_get_mem_size() is called before the data structures are set up for - * the 'early_xxx' and 'indirect_xxx' routines to work. - * Assumes bus 0. - */ -#define MPC10X_CFG_read(val, addr, type, op) *val = op((type)(addr)) -#define MPC10X_CFG_write(val, addr, type, op) op((type *)(addr), (val)) - -#define MPC10X_PCI_OP(rw, size, type, op, mask) \ -static void \ -mpc10x_##rw##_config_##size(uint *cfg_addr, uint *cfg_data, int devfn, int offset, type val) \ -{ \ - out_be32(cfg_addr, \ - ((offset & 0xfc) << 24) | (devfn << 16) \ - | (0 << 8) | 0x80); \ - MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op); \ - return; \ -} - -MPC10X_PCI_OP(read, byte, u8 *, in_8, 3) -MPC10X_PCI_OP(read, dword, u32 *, in_le32, 0) -#if 0 /* Not used */ -MPC10X_PCI_OP(write, byte, u8, out_8, 3) -MPC10X_PCI_OP(read, word, u16 *, in_le16, 2) -MPC10X_PCI_OP(write, word, u16, out_le16, 2) -MPC10X_PCI_OP(write, dword, u32, out_le32, 0) -#endif - -/* - * Read the memory controller registers to determine the amount of memory in - * the system. This assumes that the firmware has correctly set up the memory - * controller registers. - */ -unsigned long __init -mpc10x_get_mem_size(uint mem_map) -{ - uint *config_addr, *config_data, val; - ulong start, end, total, offset; - int i; - u_char bank_enables; - - switch (mem_map) { - case MPC10X_MEM_MAP_A: - config_addr = (uint *)MPC10X_MAPA_CNFG_ADDR; - config_data = (uint *)MPC10X_MAPA_CNFG_DATA; - break; - case MPC10X_MEM_MAP_B: - config_addr = (uint *)MPC10X_MAPB_CNFG_ADDR; - config_data = (uint *)MPC10X_MAPB_CNFG_DATA; - break; - default: - return 0; - } - - mpc10x_read_config_byte(config_addr, - config_data, - PCI_DEVFN(0,0), - MPC10X_MCTLR_MEM_BANK_ENABLES, - &bank_enables); - - total = 0; - - for (i=0; i<8; i++) { - if (bank_enables & (1 << i)) { - offset = MPC10X_MCTLR_MEM_START_1 + ((i > 3) ? 4 : 0); - mpc10x_read_config_dword(config_addr, - config_data, - PCI_DEVFN(0,0), - offset, - &val); - start = (val >> ((i & 3) << 3)) & 0xff; - - offset = MPC10X_MCTLR_EXT_MEM_START_1 + ((i>3) ? 4 : 0); - mpc10x_read_config_dword(config_addr, - config_data, - PCI_DEVFN(0,0), - offset, - &val); - val = (val >> ((i & 3) << 3)) & 0x03; - start = (val << 28) | (start << 20); - - offset = MPC10X_MCTLR_MEM_END_1 + ((i > 3) ? 4 : 0); - mpc10x_read_config_dword(config_addr, - config_data, - PCI_DEVFN(0,0), - offset, - &val); - end = (val >> ((i & 3) << 3)) & 0xff; - - offset = MPC10X_MCTLR_EXT_MEM_END_1 + ((i > 3) ? 4 : 0); - mpc10x_read_config_dword(config_addr, - config_data, - PCI_DEVFN(0,0), - offset, - &val); - val = (val >> ((i & 3) << 3)) & 0x03; - end = (val << 28) | (end << 20) | 0xfffff; - - total += (end - start + 1); - } - } - - return total; -} - -int __init -mpc10x_enable_store_gathering(struct pci_controller *hose) -{ - uint picr1; - - early_read_config_dword(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_PICR1_REG, - &picr1); - - picr1 |= MPC10X_CFG_PICR1_ST_GATH_EN; - - early_write_config_dword(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_PICR1_REG, - picr1); - - return 0; -} - -int __init -mpc10x_disable_store_gathering(struct pci_controller *hose) -{ - uint picr1; - - early_read_config_dword(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_PICR1_REG, - &picr1); - - picr1 &= ~MPC10X_CFG_PICR1_ST_GATH_EN; - - early_write_config_dword(hose, - 0, - PCI_DEVFN(0,0), - MPC10X_CFG_PICR1_REG, - picr1); - - return 0; -} - -#ifdef CONFIG_MPC10X_OPENPIC -void __init mpc10x_set_openpic(void) -{ - /* Map external IRQs */ - openpic_set_sources(0, EPIC_IRQ_BASE, OpenPIC_Addr + 0x10200); - /* Skip reserved space and map i2c and DMA Ch[01] */ - openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020); - /* Skip reserved space and map Message Unit Interrupt (I2O) */ - openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0); - /* Skip reserved space and map Serial Interrupts */ - openpic_set_sources(EPIC_IRQ_BASE + 4, 2, OpenPIC_Addr + 0x11120); - - openpic_init(NUM_8259_INTERRUPTS); -} -#endif diff --git a/arch/ppc/syslib/mpc52xx_devices.c b/arch/ppc/syslib/mpc52xx_devices.c deleted file mode 100644 index 7487539a4e92..000000000000 --- a/arch/ppc/syslib/mpc52xx_devices.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Freescale MPC52xx device descriptions - * - * - * Maintainer : Sylvain Munaut - * - * Copyright (C) 2005 Sylvain Munaut - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include - - -static u64 mpc52xx_dma_mask = 0xffffffffULL; - -static struct fsl_i2c_platform_data mpc52xx_fsl_i2c_pdata = { - .device_flags = FSL_I2C_DEV_CLOCK_5200, -}; - - -/* We use relative offsets for IORESOURCE_MEM to be independent from the - * MBAR location at compile time - */ - -/* TODO Add the BestComm initiator channel to the device definitions, - possibly using IORESOURCE_DMA. But that's when BestComm is ready ... */ - -struct platform_device ppc_sys_platform_devices[] = { - [MPC52xx_MSCAN1] = { - .name = "mpc52xx-mscan", - .id = 0, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x0900, - .end = 0x097f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_MSCAN1_IRQ, - .end = MPC52xx_MSCAN1_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_MSCAN2] = { - .name = "mpc52xx-mscan", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x0980, - .end = 0x09ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_MSCAN2_IRQ, - .end = MPC52xx_MSCAN2_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_SPI] = { - .name = "mpc52xx-spi", - .id = -1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .start = 0x0f00, - .end = 0x0f1f, - .flags = IORESOURCE_MEM, - }, - { - .name = "modf", - .start = MPC52xx_SPI_MODF_IRQ, - .end = MPC52xx_SPI_MODF_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "spif", - .start = MPC52xx_SPI_SPIF_IRQ, - .end = MPC52xx_SPI_SPIF_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_USB] = { - .name = "ppc-soc-ohci", - .id = -1, - .num_resources = 2, - .dev.dma_mask = &mpc52xx_dma_mask, - .dev.coherent_dma_mask = 0xffffffffULL, - .resource = (struct resource[]) { - { - .start = 0x1000, - .end = 0x10ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_USB_IRQ, - .end = MPC52xx_USB_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_BDLC] = { - .name = "mpc52xx-bdlc", - .id = -1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x1300, - .end = 0x130f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_BDLC_IRQ, - .end = MPC52xx_BDLC_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_PSC1] = { - .name = "mpc52xx-psc", - .id = 0, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x2000, - .end = 0x209f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_PSC1_IRQ, - .end = MPC52xx_PSC1_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_PSC2] = { - .name = "mpc52xx-psc", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x2200, - .end = 0x229f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_PSC2_IRQ, - .end = MPC52xx_PSC2_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_PSC3] = { - .name = "mpc52xx-psc", - .id = 2, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x2400, - .end = 0x249f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_PSC3_IRQ, - .end = MPC52xx_PSC3_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_PSC4] = { - .name = "mpc52xx-psc", - .id = 3, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x2600, - .end = 0x269f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_PSC4_IRQ, - .end = MPC52xx_PSC4_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_PSC5] = { - .name = "mpc52xx-psc", - .id = 4, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x2800, - .end = 0x289f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_PSC5_IRQ, - .end = MPC52xx_PSC5_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_PSC6] = { - .name = "mpc52xx-psc", - .id = 5, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x2c00, - .end = 0x2c9f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_PSC6_IRQ, - .end = MPC52xx_PSC6_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_FEC] = { - .name = "mpc52xx-fec", - .id = -1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x3000, - .end = 0x33ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_FEC_IRQ, - .end = MPC52xx_FEC_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_ATA] = { - .name = "mpc52xx-ata", - .id = -1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x3a00, - .end = 0x3aff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_ATA_IRQ, - .end = MPC52xx_ATA_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_I2C1] = { - .name = "fsl-i2c", - .id = 0, - .dev.platform_data = &mpc52xx_fsl_i2c_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x3d00, - .end = 0x3d1f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_I2C1_IRQ, - .end = MPC52xx_I2C1_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC52xx_I2C2] = { - .name = "fsl-i2c", - .id = 1, - .dev.platform_data = &mpc52xx_fsl_i2c_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x3d40, - .end = 0x3d5f, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC52xx_I2C2_IRQ, - .end = MPC52xx_I2C2_IRQ, - .flags = IORESOURCE_IRQ, - }, - }, - }, -}; - - -static int __init mach_mpc52xx_fixup(struct platform_device *pdev) -{ - ppc_sys_fixup_mem_resource(pdev, MPC52xx_MBAR); - return 0; -} - -static int __init mach_mpc52xx_init(void) -{ - ppc_sys_device_fixup = mach_mpc52xx_fixup; - return 0; -} - -postcore_initcall(mach_mpc52xx_init); diff --git a/arch/ppc/syslib/mpc52xx_pci.c b/arch/ppc/syslib/mpc52xx_pci.c deleted file mode 100644 index 20a0eac0dc3a..000000000000 --- a/arch/ppc/syslib/mpc52xx_pci.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * PCI code for the Freescale MPC52xx embedded CPU. - * - * - * Maintainer : Sylvain Munaut - * - * Copyright (C) 2004 Sylvain Munaut - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - - -#include - -#include -#include "mpc52xx_pci.h" - -#include -#include - - -/* This macro is defined to activate the workaround for the bug - 435 of the MPC5200 (L25R). With it activated, we don't do any - 32 bits configuration access during type-1 cycles */ -#define MPC5200_BUG_435_WORKAROUND - - -static int -mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int offset, int len, u32 *val) -{ - struct pci_controller *hose = bus->sysdata; - u32 value; - - if (ppc_md.pci_exclude_device) - if (ppc_md.pci_exclude_device(bus->number, devfn)) - return PCIBIOS_DEVICE_NOT_FOUND; - - out_be32(hose->cfg_addr, - (1 << 31) | - ((bus->number - hose->bus_offset) << 16) | - (devfn << 8) | - (offset & 0xfc)); - mb(); - -#ifdef MPC5200_BUG_435_WORKAROUND - if (bus->number != hose->bus_offset) { - switch (len) { - case 1: - value = in_8(((u8 __iomem *)hose->cfg_data) + (offset & 3)); - break; - case 2: - value = in_le16(((u16 __iomem *)hose->cfg_data) + ((offset>>1) & 1)); - break; - - default: - value = in_le16((u16 __iomem *)hose->cfg_data) | - (in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16); - break; - } - } - else -#endif - { - value = in_le32(hose->cfg_data); - - if (len != 4) { - value >>= ((offset & 0x3) << 3); - value &= 0xffffffff >> (32 - (len << 3)); - } - } - - *val = value; - - out_be32(hose->cfg_addr, 0); - mb(); - - return PCIBIOS_SUCCESSFUL; -} - -static int -mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, - int offset, int len, u32 val) -{ - struct pci_controller *hose = bus->sysdata; - u32 value, mask; - - if (ppc_md.pci_exclude_device) - if (ppc_md.pci_exclude_device(bus->number, devfn)) - return PCIBIOS_DEVICE_NOT_FOUND; - - out_be32(hose->cfg_addr, - (1 << 31) | - ((bus->number - hose->bus_offset) << 16) | - (devfn << 8) | - (offset & 0xfc)); - mb(); - -#ifdef MPC5200_BUG_435_WORKAROUND - if (bus->number != hose->bus_offset) { - switch (len) { - case 1: - out_8(((u8 __iomem *)hose->cfg_data) + - (offset & 3), val); - break; - case 2: - out_le16(((u16 __iomem *)hose->cfg_data) + - ((offset>>1) & 1), val); - break; - - default: - out_le16((u16 __iomem *)hose->cfg_data, - (u16)val); - out_le16(((u16 __iomem *)hose->cfg_data) + 1, - (u16)(val>>16)); - break; - } - } - else -#endif - { - if (len != 4) { - value = in_le32(hose->cfg_data); - - offset = (offset & 0x3) << 3; - mask = (0xffffffff >> (32 - (len << 3))); - mask <<= offset; - - value &= ~mask; - val = value | ((val << offset) & mask); - } - - out_le32(hose->cfg_data, val); - } - mb(); - - out_be32(hose->cfg_addr, 0); - mb(); - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops mpc52xx_pci_ops = { - .read = mpc52xx_pci_read_config, - .write = mpc52xx_pci_write_config -}; - - -static void __init -mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs) -{ - u32 tmp; - - /* Setup control regs */ - tmp = in_be32(&pci_regs->scr); - tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - out_be32(&pci_regs->scr, tmp); - - /* Setup windows */ - out_be32(&pci_regs->iw0btar, MPC52xx_PCI_IWBTAR_TRANSLATION( - MPC52xx_PCI_MEM_START + MPC52xx_PCI_MEM_OFFSET, - MPC52xx_PCI_MEM_START, - MPC52xx_PCI_MEM_SIZE )); - - out_be32(&pci_regs->iw1btar, MPC52xx_PCI_IWBTAR_TRANSLATION( - MPC52xx_PCI_MMIO_START + MPC52xx_PCI_MEM_OFFSET, - MPC52xx_PCI_MMIO_START, - MPC52xx_PCI_MMIO_SIZE )); - - out_be32(&pci_regs->iw2btar, MPC52xx_PCI_IWBTAR_TRANSLATION( - MPC52xx_PCI_IO_BASE, - MPC52xx_PCI_IO_START, - MPC52xx_PCI_IO_SIZE )); - - out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK( - ( MPC52xx_PCI_IWCR_ENABLE | /* iw0btar */ - MPC52xx_PCI_IWCR_READ_MULTI | - MPC52xx_PCI_IWCR_MEM ), - ( MPC52xx_PCI_IWCR_ENABLE | /* iw1btar */ - MPC52xx_PCI_IWCR_READ | - MPC52xx_PCI_IWCR_MEM ), - ( MPC52xx_PCI_IWCR_ENABLE | /* iw2btar */ - MPC52xx_PCI_IWCR_IO ) - )); - - - out_be32(&pci_regs->tbatr0, - MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO ); - out_be32(&pci_regs->tbatr1, - MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM ); - - out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD); - - /* Reset the exteral bus ( internal PCI controller is NOT resetted ) */ - /* Not necessary and can be a bad thing if for example the bootloader - is displaying a splash screen or ... Just left here for - documentation purpose if anyone need it */ - tmp = in_be32(&pci_regs->gscr); -#if 0 - out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR); - udelay(50); -#endif - out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR); -} - -static void -mpc52xx_pci_fixup_resources(struct pci_dev *dev) -{ - int i; - - /* We don't rely on boot loader for PCI and resets all - devices */ - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - struct resource *res = &dev->resource[i]; - if (res->end > res->start) { /* Only valid resources */ - res->end -= res->start; - res->start = 0; - res->flags |= IORESOURCE_UNSET; - } - } - - /* The PCI Host bridge of MPC52xx has a prefetch memory resource - fixed to 1Gb. Doesn't fit in the resource system so we remove it */ - if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) && - ( dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200 - || dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200B) ) { - struct resource *res = &dev->resource[1]; - res->start = res->end = res->flags = 0; - } -} - -void __init -mpc52xx_find_bridges(void) -{ - struct mpc52xx_pci __iomem *pci_regs; - struct pci_controller *hose; - - pci_assign_all_buses = 1; - - pci_regs = ioremap(MPC52xx_PA(MPC52xx_PCI_OFFSET), MPC52xx_PCI_SIZE); - if (!pci_regs) - return; - - hose = pcibios_alloc_controller(); - if (!hose) { - iounmap(pci_regs); - return; - } - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources; - - hose->first_busno = 0; - hose->last_busno = 0xff; - hose->bus_offset = 0; - hose->ops = &mpc52xx_pci_ops; - - mpc52xx_pci_setup(pci_regs); - - hose->pci_mem_offset = MPC52xx_PCI_MEM_OFFSET; - - hose->io_base_virt = ioremap(MPC52xx_PCI_IO_BASE, MPC52xx_PCI_IO_SIZE); - isa_io_base = (unsigned long) hose->io_base_virt; - - hose->cfg_addr = &pci_regs->car; - hose->cfg_data = hose->io_base_virt; - - /* Setup resources */ - pci_init_resource(&hose->mem_resources[0], - MPC52xx_PCI_MEM_START, - MPC52xx_PCI_MEM_STOP, - IORESOURCE_MEM|IORESOURCE_PREFETCH, - "PCI prefetchable memory"); - - pci_init_resource(&hose->mem_resources[1], - MPC52xx_PCI_MMIO_START, - MPC52xx_PCI_MMIO_STOP, - IORESOURCE_MEM, - "PCI memory"); - - pci_init_resource(&hose->io_resource, - MPC52xx_PCI_IO_START, - MPC52xx_PCI_IO_STOP, - IORESOURCE_IO, - "PCI I/O"); - -} diff --git a/arch/ppc/syslib/mpc52xx_pci.h b/arch/ppc/syslib/mpc52xx_pci.h deleted file mode 100644 index 77d47dbba85e..000000000000 --- a/arch/ppc/syslib/mpc52xx_pci.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * PCI Include file the Freescale MPC52xx embedded cpu chips - * - * - * Maintainer : Sylvain Munaut - * - * Inspired from code written by Dale Farnsworth - * for the 2.4 kernel. - * - * Copyright (C) 2004 Sylvain Munaut - * Copyright (C) 2003 MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef __SYSLIB_MPC52xx_PCI_H__ -#define __SYSLIB_MPC52xx_PCI_H__ - -/* ======================================================================== */ -/* PCI windows config */ -/* ======================================================================== */ - -/* - * Master windows : MPC52xx -> PCI - * - * 0x80000000 -> 0x9FFFFFFF PCI Mem prefetchable IW0BTAR - * 0xA0000000 -> 0xAFFFFFFF PCI Mem IW1BTAR - * 0xB0000000 -> 0xB0FFFFFF PCI IO IW2BTAR - * - * Slave windows : PCI -> MPC52xx - * - * 0xF0000000 -> 0xF003FFFF MPC52xx MBAR TBATR0 - * 0x00000000 -> 0x3FFFFFFF MPC52xx local memory TBATR1 - */ - -#define MPC52xx_PCI_MEM_OFFSET 0x00000000 /* Offset for MEM MMIO */ - -#define MPC52xx_PCI_MEM_START 0x80000000 -#define MPC52xx_PCI_MEM_SIZE 0x20000000 -#define MPC52xx_PCI_MEM_STOP (MPC52xx_PCI_MEM_START+MPC52xx_PCI_MEM_SIZE-1) - -#define MPC52xx_PCI_MMIO_START 0xa0000000 -#define MPC52xx_PCI_MMIO_SIZE 0x10000000 -#define MPC52xx_PCI_MMIO_STOP (MPC52xx_PCI_MMIO_START+MPC52xx_PCI_MMIO_SIZE-1) - -#define MPC52xx_PCI_IO_BASE 0xb0000000 - -#define MPC52xx_PCI_IO_START 0x00000000 -#define MPC52xx_PCI_IO_SIZE 0x01000000 -#define MPC52xx_PCI_IO_STOP (MPC52xx_PCI_IO_START+MPC52xx_PCI_IO_SIZE-1) - - -#define MPC52xx_PCI_TARGET_IO MPC52xx_MBAR -#define MPC52xx_PCI_TARGET_MEM 0x00000000 - - -/* ======================================================================== */ -/* Structures mapping & Defines for PCI Unit */ -/* ======================================================================== */ - -#define MPC52xx_PCI_GSCR_BM 0x40000000 -#define MPC52xx_PCI_GSCR_PE 0x20000000 -#define MPC52xx_PCI_GSCR_SE 0x10000000 -#define MPC52xx_PCI_GSCR_XLB2PCI_MASK 0x07000000 -#define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT 24 -#define MPC52xx_PCI_GSCR_IPG2PCI_MASK 0x00070000 -#define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT 16 -#define MPC52xx_PCI_GSCR_BME 0x00004000 -#define MPC52xx_PCI_GSCR_PEE 0x00002000 -#define MPC52xx_PCI_GSCR_SEE 0x00001000 -#define MPC52xx_PCI_GSCR_PR 0x00000001 - - -#define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size) \ - ( ( (proc_ad) & 0xff000000 ) | \ - ( (((size) - 1) >> 8) & 0x00ff0000 ) | \ - ( ((pci_ad) >> 16) & 0x0000ff00 ) ) - -#define MPC52xx_PCI_IWCR_PACK(win0,win1,win2) (((win0) << 24) | \ - ((win1) << 16) | \ - ((win2) << 8)) - -#define MPC52xx_PCI_IWCR_DISABLE 0x0 -#define MPC52xx_PCI_IWCR_ENABLE 0x1 -#define MPC52xx_PCI_IWCR_READ 0x0 -#define MPC52xx_PCI_IWCR_READ_LINE 0x2 -#define MPC52xx_PCI_IWCR_READ_MULTI 0x4 -#define MPC52xx_PCI_IWCR_MEM 0x0 -#define MPC52xx_PCI_IWCR_IO 0x8 - -#define MPC52xx_PCI_TCR_P 0x01000000 -#define MPC52xx_PCI_TCR_LD 0x00010000 - -#define MPC52xx_PCI_TBATR_DISABLE 0x0 -#define MPC52xx_PCI_TBATR_ENABLE 0x1 - - -#ifndef __ASSEMBLY__ - -struct mpc52xx_pci { - u32 idr; /* PCI + 0x00 */ - u32 scr; /* PCI + 0x04 */ - u32 ccrir; /* PCI + 0x08 */ - u32 cr1; /* PCI + 0x0C */ - u32 bar0; /* PCI + 0x10 */ - u32 bar1; /* PCI + 0x14 */ - u8 reserved1[16]; /* PCI + 0x18 */ - u32 ccpr; /* PCI + 0x28 */ - u32 sid; /* PCI + 0x2C */ - u32 erbar; /* PCI + 0x30 */ - u32 cpr; /* PCI + 0x34 */ - u8 reserved2[4]; /* PCI + 0x38 */ - u32 cr2; /* PCI + 0x3C */ - u8 reserved3[32]; /* PCI + 0x40 */ - u32 gscr; /* PCI + 0x60 */ - u32 tbatr0; /* PCI + 0x64 */ - u32 tbatr1; /* PCI + 0x68 */ - u32 tcr; /* PCI + 0x6C */ - u32 iw0btar; /* PCI + 0x70 */ - u32 iw1btar; /* PCI + 0x74 */ - u32 iw2btar; /* PCI + 0x78 */ - u8 reserved4[4]; /* PCI + 0x7C */ - u32 iwcr; /* PCI + 0x80 */ - u32 icr; /* PCI + 0x84 */ - u32 isr; /* PCI + 0x88 */ - u32 arb; /* PCI + 0x8C */ - u8 reserved5[104]; /* PCI + 0x90 */ - u32 car; /* PCI + 0xF8 */ - u8 reserved6[4]; /* PCI + 0xFC */ -}; - -#endif /* __ASSEMBLY__ */ - - -#endif /* __SYSLIB_MPC52xx_PCI_H__ */ diff --git a/arch/ppc/syslib/mpc52xx_pic.c b/arch/ppc/syslib/mpc52xx_pic.c deleted file mode 100644 index f58149c03b0f..000000000000 --- a/arch/ppc/syslib/mpc52xx_pic.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Programmable Interrupt Controller functions for the Freescale MPC52xx - * embedded CPU. - * - * - * Maintainer : Sylvain Munaut - * - * Based on (well, mostly copied from) the code from the 2.4 kernel by - * Dale Farnsworth and Kent Borg. - * - * Copyright (C) 2004 Sylvain Munaut - * Copyright (C) 2003 Montavista Software, Inc - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - - -static struct mpc52xx_intr __iomem *intr; -static struct mpc52xx_sdma __iomem *sdma; - -static void -mpc52xx_ic_disable(unsigned int irq) -{ - u32 val; - - if (irq == MPC52xx_IRQ0) { - val = in_be32(&intr->ctrl); - val &= ~(1 << 11); - out_be32(&intr->ctrl, val); - } - else if (irq < MPC52xx_IRQ1) { - BUG(); - } - else if (irq <= MPC52xx_IRQ3) { - val = in_be32(&intr->ctrl); - val &= ~(1 << (10 - (irq - MPC52xx_IRQ1))); - out_be32(&intr->ctrl, val); - } - else if (irq < MPC52xx_SDMA_IRQ_BASE) { - val = in_be32(&intr->main_mask); - val |= 1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE)); - out_be32(&intr->main_mask, val); - } - else if (irq < MPC52xx_PERP_IRQ_BASE) { - val = in_be32(&sdma->IntMask); - val |= 1 << (irq - MPC52xx_SDMA_IRQ_BASE); - out_be32(&sdma->IntMask, val); - } - else { - val = in_be32(&intr->per_mask); - val |= 1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE)); - out_be32(&intr->per_mask, val); - } -} - -static void -mpc52xx_ic_enable(unsigned int irq) -{ - u32 val; - - if (irq == MPC52xx_IRQ0) { - val = in_be32(&intr->ctrl); - val |= 1 << 11; - out_be32(&intr->ctrl, val); - } - else if (irq < MPC52xx_IRQ1) { - BUG(); - } - else if (irq <= MPC52xx_IRQ3) { - val = in_be32(&intr->ctrl); - val |= 1 << (10 - (irq - MPC52xx_IRQ1)); - out_be32(&intr->ctrl, val); - } - else if (irq < MPC52xx_SDMA_IRQ_BASE) { - val = in_be32(&intr->main_mask); - val &= ~(1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE))); - out_be32(&intr->main_mask, val); - } - else if (irq < MPC52xx_PERP_IRQ_BASE) { - val = in_be32(&sdma->IntMask); - val &= ~(1 << (irq - MPC52xx_SDMA_IRQ_BASE)); - out_be32(&sdma->IntMask, val); - } - else { - val = in_be32(&intr->per_mask); - val &= ~(1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE))); - out_be32(&intr->per_mask, val); - } -} - -static void -mpc52xx_ic_ack(unsigned int irq) -{ - u32 val; - - /* - * Only some irqs are reset here, others in interrupting hardware. - */ - - switch (irq) { - case MPC52xx_IRQ0: - val = in_be32(&intr->ctrl); - val |= 0x08000000; - out_be32(&intr->ctrl, val); - break; - case MPC52xx_CCS_IRQ: - val = in_be32(&intr->enc_status); - val |= 0x00000400; - out_be32(&intr->enc_status, val); - break; - case MPC52xx_IRQ1: - val = in_be32(&intr->ctrl); - val |= 0x04000000; - out_be32(&intr->ctrl, val); - break; - case MPC52xx_IRQ2: - val = in_be32(&intr->ctrl); - val |= 0x02000000; - out_be32(&intr->ctrl, val); - break; - case MPC52xx_IRQ3: - val = in_be32(&intr->ctrl); - val |= 0x01000000; - out_be32(&intr->ctrl, val); - break; - default: - if (irq >= MPC52xx_SDMA_IRQ_BASE - && irq < (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)) { - out_be32(&sdma->IntPend, - 1 << (irq - MPC52xx_SDMA_IRQ_BASE)); - } - break; - } -} - -static void -mpc52xx_ic_disable_and_ack(unsigned int irq) -{ - mpc52xx_ic_disable(irq); - mpc52xx_ic_ack(irq); -} - -static void -mpc52xx_ic_end(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - mpc52xx_ic_enable(irq); -} - -static struct hw_interrupt_type mpc52xx_ic = { - .typename = " MPC52xx ", - .enable = mpc52xx_ic_enable, - .disable = mpc52xx_ic_disable, - .ack = mpc52xx_ic_disable_and_ack, - .end = mpc52xx_ic_end, -}; - -void __init -mpc52xx_init_irq(void) -{ - int i; - u32 intr_ctrl; - - /* Remap the necessary zones */ - intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE); - sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE); - - if ((intr==NULL) || (sdma==NULL)) - panic("Can't ioremap PIC/SDMA register for init_irq !"); - - /* Disable all interrupt sources. */ - out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ - out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ - out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */ - out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */ - intr_ctrl = in_be32(&intr->ctrl); - intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */ - intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */ - 0x00001000 | /* MEE master external enable */ - 0x00000000 | /* 0 means disable IRQ 0-3 */ - 0x00000001; /* CEb route critical normally */ - out_be32(&intr->ctrl, intr_ctrl); - - /* Zero a bunch of the priority settings. */ - out_be32(&intr->per_pri1, 0); - out_be32(&intr->per_pri2, 0); - out_be32(&intr->per_pri3, 0); - out_be32(&intr->main_pri1, 0); - out_be32(&intr->main_pri2, 0); - - /* Initialize irq_desc[i].chip's with mpc52xx_ic. */ - for (i = 0; i < NR_IRQS; i++) { - irq_desc[i].chip = &mpc52xx_ic; - irq_desc[i].status = IRQ_LEVEL; - } - - #define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03) - for (i=0 ; i<4 ; i++) { - int mode; - mode = IRQn_MODE(intr_ctrl,i); - if ((mode == 0x1) || (mode == 0x2)) - irq_desc[i?MPC52xx_IRQ1+i-1:MPC52xx_IRQ0].status = 0; - } -} - -int -mpc52xx_get_irq(void) -{ - u32 status; - int irq = -1; - - status = in_be32(&intr->enc_status); - - if (status & 0x00000400) { /* critical */ - irq = (status >> 8) & 0x3; - if (irq == 2) /* high priority peripheral */ - goto peripheral; - irq += MPC52xx_CRIT_IRQ_BASE; - } - else if (status & 0x00200000) { /* main */ - irq = (status >> 16) & 0x1f; - if (irq == 4) /* low priority peripheral */ - goto peripheral; - irq += MPC52xx_MAIN_IRQ_BASE; - } - else if (status & 0x20000000) { /* peripheral */ -peripheral: - irq = (status >> 24) & 0x1f; - if (irq == 0) { /* bestcomm */ - status = in_be32(&sdma->IntPend); - irq = ffs(status) + MPC52xx_SDMA_IRQ_BASE-1; - } - else - irq += MPC52xx_PERP_IRQ_BASE; - } - - return irq; -} - diff --git a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c deleted file mode 100644 index ab0cf4ced9e5..000000000000 --- a/arch/ppc/syslib/mpc52xx_setup.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Common code for the boards based on Freescale MPC52xx embedded CPU. - * - * - * Maintainer : Sylvain Munaut - * - * Support for other bootloaders than UBoot by Dale Farnsworth - * - * - * Copyright (C) 2004 Sylvain Munaut - * Copyright (C) 2003 Montavista Software, Inc - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - - -#include -#include -#include -#include -#include -#include -#include - -#include - -extern bd_t __res; - -static int core_mult[] = { /* CPU Frequency multiplier, taken */ - 0, 0, 0, 10, 20, 20, 25, 45, /* from the datasheet used to compute */ - 30, 55, 40, 50, 0, 60, 35, 0, /* CPU frequency from XLB freq and */ - 30, 25, 65, 10, 70, 20, 75, 45, /* external jumper config */ - 0, 55, 40, 50, 80, 60, 35, 0 -}; - -void -mpc52xx_restart(char *cmd) -{ - struct mpc52xx_gpt __iomem *gpt0 = MPC52xx_VA(MPC52xx_GPTx_OFFSET(0)); - - local_irq_disable(); - - /* Turn on the watchdog and wait for it to expire. It effectively - does a reset */ - out_be32(&gpt0->count, 0x000000ff); - out_be32(&gpt0->mode, 0x00009004); - - while (1); -} - -void -mpc52xx_halt(void) -{ - local_irq_disable(); - - while (1); -} - -void -mpc52xx_power_off(void) -{ - /* By default we don't have any way of shut down. - If a specific board wants to, it can set the power down - code to any hardware implementation dependent code */ - mpc52xx_halt(); -} - - -void __init -mpc52xx_set_bat(void) -{ - /* Set BAT 2 to map the 0xf0000000 area */ - /* This mapping is used during mpc52xx_progress, - * mpc52xx_find_end_of_memory, and UARTs/GPIO access for debug - */ - mb(); - mtspr(SPRN_DBAT2U, 0xf0001ffe); - mtspr(SPRN_DBAT2L, 0xf000002a); - mb(); -} - -void __init -mpc52xx_map_io(void) -{ - /* Here we map the MBAR and the whole upper zone. MBAR is only - 64k but we can't map only 64k with BATs. Map the whole - 0xf0000000 range is ok and helps eventual lpb devices placed there */ - io_block_mapping( - MPC52xx_MBAR_VIRT, MPC52xx_MBAR, 0x10000000, _PAGE_IO); -} - - -#ifdef CONFIG_SERIAL_TEXT_DEBUG -#ifndef MPC52xx_PF_CONSOLE_PORT -#error "mpc52xx PSC for console not selected" -#endif - -static void -mpc52xx_psc_putc(struct mpc52xx_psc __iomem *psc, unsigned char c) -{ - while (!(in_be16(&psc->mpc52xx_psc_status) & - MPC52xx_PSC_SR_TXRDY)); - out_8(&psc->mpc52xx_psc_buffer_8, c); -} - -void -mpc52xx_progress(char *s, unsigned short hex) -{ - char c; - struct mpc52xx_psc __iomem *psc; - - psc = MPC52xx_VA(MPC52xx_PSCx_OFFSET(MPC52xx_PF_CONSOLE_PORT)); - - while ((c = *s++) != 0) { - if (c == '\n') - mpc52xx_psc_putc(psc, '\r'); - mpc52xx_psc_putc(psc, c); - } - - mpc52xx_psc_putc(psc, '\r'); - mpc52xx_psc_putc(psc, '\n'); -} - -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ - - -unsigned long __init -mpc52xx_find_end_of_memory(void) -{ - u32 ramsize = __res.bi_memsize; - - /* - * if bootloader passed a memsize, just use it - * else get size from sdram config registers - */ - if (ramsize == 0) { - struct mpc52xx_mmap_ctl __iomem *mmap_ctl; - u32 sdram_config_0, sdram_config_1; - - /* Temp BAT2 mapping active when this is called ! */ - mmap_ctl = MPC52xx_VA(MPC52xx_MMAP_CTL_OFFSET); - - sdram_config_0 = in_be32(&mmap_ctl->sdram0); - sdram_config_1 = in_be32(&mmap_ctl->sdram1); - - if ((sdram_config_0 & 0x1f) >= 0x13) - ramsize = 1 << ((sdram_config_0 & 0xf) + 17); - - if (((sdram_config_1 & 0x1f) >= 0x13) && - ((sdram_config_1 & 0xfff00000) == ramsize)) - ramsize += 1 << ((sdram_config_1 & 0xf) + 17); - } - - return ramsize; -} - -void __init -mpc52xx_calibrate_decr(void) -{ - int current_time, previous_time; - int tbl_start, tbl_end; - unsigned int xlbfreq, cpufreq, ipbfreq, pcifreq, divisor; - - xlbfreq = __res.bi_busfreq; - /* if bootloader didn't pass bus frequencies, calculate them */ - if (xlbfreq == 0) { - /* Get RTC & Clock manager modules */ - struct mpc52xx_rtc __iomem *rtc; - struct mpc52xx_cdm __iomem *cdm; - - rtc = ioremap(MPC52xx_PA(MPC52xx_RTC_OFFSET), MPC52xx_RTC_SIZE); - cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE); - - if ((rtc==NULL) || (cdm==NULL)) - panic("Can't ioremap RTC/CDM while computing bus freq"); - - /* Count bus clock during 1/64 sec */ - out_be32(&rtc->dividers, 0x8f1f0000); /* Set RTC 64x faster */ - previous_time = in_be32(&rtc->time); - while ((current_time = in_be32(&rtc->time)) == previous_time) ; - tbl_start = get_tbl(); - previous_time = current_time; - while ((current_time = in_be32(&rtc->time)) == previous_time) ; - tbl_end = get_tbl(); - out_be32(&rtc->dividers, 0xffff0000); /* Restore RTC */ - - /* Compute all frequency from that & CDM settings */ - xlbfreq = (tbl_end - tbl_start) << 8; - cpufreq = (xlbfreq * core_mult[in_be32(&cdm->rstcfg)&0x1f])/10; - ipbfreq = (in_8(&cdm->ipb_clk_sel) & 1) ? - xlbfreq / 2 : xlbfreq; - switch (in_8(&cdm->pci_clk_sel) & 3) { - case 0: - pcifreq = ipbfreq; - break; - case 1: - pcifreq = ipbfreq / 2; - break; - default: - pcifreq = xlbfreq / 4; - break; - } - __res.bi_busfreq = xlbfreq; - __res.bi_intfreq = cpufreq; - __res.bi_ipbfreq = ipbfreq; - __res.bi_pcifreq = pcifreq; - - /* Release mapping */ - iounmap(rtc); - iounmap(cdm); - } - - divisor = 4; - - tb_ticks_per_jiffy = xlbfreq / HZ / divisor; - tb_to_us = mulhwu_scale_factor(xlbfreq / divisor, 1000000); -} - - -void __init -mpc52xx_setup_cpu(void) -{ - struct mpc52xx_cdm __iomem *cdm; - struct mpc52xx_xlb __iomem *xlb; - - /* Map zones */ - cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE); - xlb = ioremap(MPC52xx_PA(MPC52xx_XLB_OFFSET), MPC52xx_XLB_SIZE); - - if (!cdm || !xlb) { - printk(KERN_ERR __FILE__ ": " - "Error while mapping CDM/XLB during " - "mpc52xx_setup_cpu\n"); - goto unmap_regs; - } - - /* Use internal 48 Mhz */ - out_8(&cdm->ext_48mhz_en, 0x00); - out_8(&cdm->fd_enable, 0x01); - if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */ - out_be16(&cdm->fd_counters, 0x0001); - else - out_be16(&cdm->fd_counters, 0x5555); - - /* Configure the XLB Arbiter priorities */ - out_be32(&xlb->master_pri_enable, 0xff); - out_be32(&xlb->master_priority, 0x11111111); - - /* Enable ram snooping for 1GB window */ - out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_SNOOP); - out_be32(&xlb->snoop_window, MPC52xx_PCI_TARGET_MEM | 0x1d); - - /* Disable XLB pipelining */ - /* (cfr errata 292. We could do this only just before ATA PIO - transaction and re-enable it after ...) */ - out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); - - /* Unmap reg zone */ -unmap_regs: - if (cdm) iounmap(cdm); - if (xlb) iounmap(xlb); -} - - -int mpc52xx_match_psc_function(int psc_idx, const char *func) -{ - struct mpc52xx_psc_func *cf = mpc52xx_psc_functions; - - while ((cf->id != -1) && (cf->func != NULL)) { - if ((cf->id == psc_idx) && !strcmp(cf->func,func)) - return 1; - cf++; - } - - return 0; -} - -int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv) -{ - static DEFINE_SPINLOCK(lock); - struct mpc52xx_cdm __iomem *cdm; - unsigned long flags; - u16 mclken_div; - u16 __iomem *reg; - u32 mask; - - cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE); - if (!cdm) { - printk(KERN_ERR __FILE__ ": Error mapping CDM\n"); - return -ENODEV; - } - - mclken_div = 0x8000 | (clkdiv & 0x1FF); - switch (psc_id) { - case 1: reg = &cdm->mclken_div_psc1; mask = 0x20; break; - case 2: reg = &cdm->mclken_div_psc2; mask = 0x40; break; - case 3: reg = &cdm->mclken_div_psc3; mask = 0x80; break; - case 6: reg = &cdm->mclken_div_psc6; mask = 0x10; break; - default: - return -ENODEV; - } - - /* Set the rate and enable the clock */ - spin_lock_irqsave(&lock, flags); - out_be16(reg, mclken_div); - out_be32(&cdm->clk_enables, in_be32(&cdm->clk_enables) | mask); - spin_unlock_irqrestore(&lock, flags); - - iounmap(cdm); - return 0; -} diff --git a/arch/ppc/syslib/mpc52xx_sys.c b/arch/ppc/syslib/mpc52xx_sys.c deleted file mode 100644 index b4e6f978f057..000000000000 --- a/arch/ppc/syslib/mpc52xx_sys.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Freescale MPC52xx system descriptions - * - * - * Maintainer : Sylvain Munaut - * - * Copyright (C) 2005 Sylvain Munaut - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -struct ppc_sys_spec *cur_ppc_sys_spec; -struct ppc_sys_spec ppc_sys_specs[] = { - { - .ppc_sys_name = "5200", - .mask = 0xffff0000, - .value = 0x80110000, - .num_devices = 15, - .device_list = (enum ppc_sys_devices[]) - { - MPC52xx_MSCAN1, MPC52xx_MSCAN2, MPC52xx_SPI, - MPC52xx_USB, MPC52xx_BDLC, MPC52xx_PSC1, MPC52xx_PSC2, - MPC52xx_PSC3, MPC52xx_PSC4, MPC52xx_PSC5, MPC52xx_PSC6, - MPC52xx_FEC, MPC52xx_ATA, MPC52xx_I2C1, MPC52xx_I2C2, - }, - }, - { /* default match */ - .ppc_sys_name = "", - .mask = 0x00000000, - .value = 0x00000000, - }, -}; diff --git a/arch/ppc/syslib/mpc8xx_devices.c b/arch/ppc/syslib/mpc8xx_devices.c deleted file mode 100644 index 80804eee5795..000000000000 --- a/arch/ppc/syslib/mpc8xx_devices.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * MPC8xx Device descriptions - * - * Maintainer: Kumar Gala - * - * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* We use offsets for IORESOURCE_MEM to do not set dependencies at compile time. - * They will get fixed up by mach_mpc8xx_fixup - */ - -struct platform_device ppc_sys_platform_devices[] = { - [MPC8xx_CPM_FEC1] = { - .name = "fsl-cpm-fec", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0xe00, - .end = 0xe88, - .flags = IORESOURCE_MEM, - }, - { - .name = "interrupt", - .start = MPC8xx_INT_FEC1, - .end = MPC8xx_INT_FEC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC8xx_CPM_FEC2] = { - .name = "fsl-cpm-fec", - .id = 2, - .num_resources = 2, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0x1e00, - .end = 0x1e88, - .flags = IORESOURCE_MEM, - }, - { - .name = "interrupt", - .start = MPC8xx_INT_FEC2, - .end = MPC8xx_INT_FEC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC8xx_CPM_SCC1] = { - .name = "fsl-cpm-scc", - .id = 1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0xa00, - .end = 0xa18, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x3c00, - .end = 0x3c7f, - .flags = IORESOURCE_MEM, - }, - { - .name = "interrupt", - .start = MPC8xx_INT_SCC1, - .end = MPC8xx_INT_SCC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC8xx_CPM_SCC2] = { - .name = "fsl-cpm-scc", - .id = 2, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0xa20, - .end = 0xa38, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x3d00, - .end = 0x3d7f, - .flags = IORESOURCE_MEM, - }, - - { - .name = "interrupt", - .start = MPC8xx_INT_SCC2, - .end = MPC8xx_INT_SCC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC8xx_CPM_SCC3] = { - .name = "fsl-cpm-scc", - .id = 3, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0xa40, - .end = 0xa58, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x3e00, - .end = 0x3e7f, - .flags = IORESOURCE_MEM, - }, - - { - .name = "interrupt", - .start = MPC8xx_INT_SCC3, - .end = MPC8xx_INT_SCC3, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC8xx_CPM_SCC4] = { - .name = "fsl-cpm-scc", - .id = 4, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0xa60, - .end = 0xa78, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x3f00, - .end = 0x3f7f, - .flags = IORESOURCE_MEM, - }, - - { - .name = "interrupt", - .start = MPC8xx_INT_SCC4, - .end = MPC8xx_INT_SCC4, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC8xx_CPM_SMC1] = { - .name = "fsl-cpm-smc", - .id = 1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0xa80, - .end = 0xa8f, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x3e80, - .end = 0x3ebf, - .flags = IORESOURCE_MEM, - }, - { - .name = "interrupt", - .start = MPC8xx_INT_SMC1, - .end = MPC8xx_INT_SMC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC8xx_CPM_SMC2] = { - .name = "fsl-cpm-smc", - .id = 2, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0xa90, - .end = 0xa9f, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x3f80, - .end = 0x3fbf, - .flags = IORESOURCE_MEM, - - }, - { - .name = "interrupt", - .start = MPC8xx_INT_SMC2, - .end = MPC8xx_INT_SMC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - - [MPC8xx_MDIO_FEC] = { - .name = "fsl-cpm-fec-mdio", - .id = 0, - .num_resources = 0, - - }, - -}; - -static int __init mach_mpc8xx_fixup(struct platform_device *pdev) -{ - ppc_sys_fixup_mem_resource (pdev, IMAP_ADDR); - return 0; -} - -static int __init mach_mpc8xx_init(void) -{ - ppc_sys_device_fixup = mach_mpc8xx_fixup; - return 0; -} - -postcore_initcall(mach_mpc8xx_init); diff --git a/arch/ppc/syslib/mpc8xx_sys.c b/arch/ppc/syslib/mpc8xx_sys.c deleted file mode 100644 index 18ba1d7ff9f1..000000000000 --- a/arch/ppc/syslib/mpc8xx_sys.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * MPC8xx System descriptions - * - * Maintainer: Kumar Gala - * - * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include - -struct ppc_sys_spec *cur_ppc_sys_spec; -struct ppc_sys_spec ppc_sys_specs[] = { - { - .ppc_sys_name = "MPC86X", - .mask = 0xFFFFFFFF, - .value = 0x00000000, - .num_devices = 8, - .device_list = (enum ppc_sys_devices[]) - { - MPC8xx_CPM_FEC1, - MPC8xx_CPM_SCC1, - MPC8xx_CPM_SCC2, - MPC8xx_CPM_SCC3, - MPC8xx_CPM_SCC4, - MPC8xx_CPM_SMC1, - MPC8xx_CPM_SMC2, - MPC8xx_MDIO_FEC, - }, - }, - { - .ppc_sys_name = "MPC885", - .mask = 0xFFFFFFFF, - .value = 0x00000000, - .num_devices = 9, - .device_list = (enum ppc_sys_devices[]) - { - MPC8xx_CPM_FEC1, - MPC8xx_CPM_FEC2, - MPC8xx_CPM_SCC1, - MPC8xx_CPM_SCC2, - MPC8xx_CPM_SCC3, - MPC8xx_CPM_SCC4, - MPC8xx_CPM_SMC1, - MPC8xx_CPM_SMC2, - MPC8xx_MDIO_FEC, - }, - }, - { /* default match */ - .ppc_sys_name = "", - .mask = 0x00000000, - .value = 0x00000000, - }, -}; diff --git a/arch/ppc/syslib/mv64360_pic.c b/arch/ppc/syslib/mv64360_pic.c deleted file mode 100644 index 2dd2dc5cd404..000000000000 --- a/arch/ppc/syslib/mv64360_pic.c +++ /dev/null @@ -1,423 +0,0 @@ -/* - * Interrupt controller support for Marvell's MV64360. - * - * Author: Rabeeh Khoury - * Based on MV64360 PIC written by - * Chris Zankel - * Mark A. Greer - * - * Copyright 2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * This file contains the specific functions to support the MV64360 - * interrupt controller. - * - * The MV64360 has two main interrupt registers (high and low) that - * summarizes the interrupts generated by the units of the MV64360. - * Each bit is assigned to an interrupt number, where the low register - * are assigned from IRQ0 to IRQ31 and the high cause register - * from IRQ32 to IRQ63 - * The GPP (General Purpose Pins) interrupts are assigned from IRQ64 (GPP0) - * to IRQ95 (GPP31). - * get_irq() returns the lowest interrupt number that is currently asserted. - * - * Note: - * - This driver does not initialize the GPP when used as an interrupt - * input. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_IRQ_ALL_CPUS -#error "The mv64360 does not support distribution of IRQs on all CPUs" -#endif -/* ========================== forward declaration ========================== */ - -static void mv64360_unmask_irq(unsigned int); -static void mv64360_mask_irq(unsigned int); -static irqreturn_t mv64360_cpu_error_int_handler(int, void *); -static irqreturn_t mv64360_sram_error_int_handler(int, void *); -static irqreturn_t mv64360_pci_error_int_handler(int, void *); - -/* ========================== local declarations =========================== */ - -struct hw_interrupt_type mv64360_pic = { - .typename = " mv64360 ", - .enable = mv64360_unmask_irq, - .disable = mv64360_mask_irq, - .ack = mv64360_mask_irq, - .end = mv64360_unmask_irq, -}; - -#define CPU_INTR_STR "mv64360 cpu interface error" -#define SRAM_INTR_STR "mv64360 internal sram error" -#define PCI0_INTR_STR "mv64360 pci 0 error" -#define PCI1_INTR_STR "mv64360 pci 1 error" - -static struct mv64x60_handle bh; - -u32 mv64360_irq_base = 0; /* MV64360 handles the next 96 IRQs from here */ - -/* mv64360_init_irq() - * - * This function initializes the interrupt controller. It assigns - * all interrupts from IRQ0 to IRQ95 to the mv64360 interrupt controller. - * - * Input Variable(s): - * None. - * - * Outpu. Variable(s): - * None. - * - * Returns: - * void - * - * Note: - * We register all GPP inputs as interrupt source, but disable them. - */ -void __init -mv64360_init_irq(void) -{ - int i; - - if (ppc_md.progress) - ppc_md.progress("mv64360_init_irq: enter", 0x0); - - bh.v_base = mv64x60_get_bridge_vbase(); - - ppc_cached_irq_mask[0] = 0; - ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */ - ppc_cached_irq_mask[2] = 0; - - /* disable all interrupts and clear current interrupts */ - mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0); - mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]); - mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO,ppc_cached_irq_mask[0]); - mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI,ppc_cached_irq_mask[1]); - - /* All interrupts are level interrupts */ - for (i = mv64360_irq_base; i < (mv64360_irq_base + 96); i++) { - irq_desc[i].status |= IRQ_LEVEL; - irq_desc[i].chip = &mv64360_pic; - } - - if (ppc_md.progress) - ppc_md.progress("mv64360_init_irq: exit", 0x0); -} - -/* mv64360_get_irq() - * - * This function returns the lowest interrupt number of all interrupts that - * are currently asserted. - * - * Output Variable(s): - * None. - * - * Returns: - * int or -2 (bogus interrupt) - * - */ -int -mv64360_get_irq(void) -{ - int irq; - int irq_gpp; - -#ifdef CONFIG_SMP - /* - * Second CPU gets only doorbell (message) interrupts. - * The doorbell interrupt is BIT28 in the main interrupt low cause reg. - */ - int cpu_nr = smp_processor_id(); - if (cpu_nr == 1) { - if (!(mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO) & - (1 << MV64x60_IRQ_DOORBELL))) - return -1; - return mv64360_irq_base + MV64x60_IRQ_DOORBELL; - } -#endif - - irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO); - irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]); - - if (irq == -1) { - irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_HI); - irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]); - - if (irq == -1) - irq = -2; /* bogus interrupt, should never happen */ - else { - if ((irq >= 24) && (irq < MV64x60_IRQ_DOORBELL)) { - irq_gpp = mv64x60_read(&bh, - MV64x60_GPP_INTR_CAUSE); - irq_gpp = __ilog2(irq_gpp & - ppc_cached_irq_mask[2]); - - if (irq_gpp == -1) - irq = -2; - else { - irq = irq_gpp + 64; - mv64x60_write(&bh, - MV64x60_GPP_INTR_CAUSE, - ~(1 << (irq - 64))); - } - } - else - irq += 32; - } - } - - (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE); - - if (irq < 0) - return (irq); - else - return (mv64360_irq_base + irq); -} - -/* mv64360_unmask_irq() - * - * This function enables an interrupt. - * - * Input Variable(s): - * unsigned int interrupt number (IRQ0...IRQ95). - * - * Output Variable(s): - * None. - * - * Returns: - * void - */ -static void -mv64360_unmask_irq(unsigned int irq) -{ -#ifdef CONFIG_SMP - /* second CPU gets only doorbell interrupts */ - if ((irq - mv64360_irq_base) == MV64x60_IRQ_DOORBELL) { - mv64x60_set_bits(&bh, MV64360_IC_CPU1_INTR_MASK_LO, - (1 << MV64x60_IRQ_DOORBELL)); - return; - } -#endif - irq -= mv64360_irq_base; - - if (irq > 31) { - if (irq > 63) /* unmask GPP irq */ - mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, - ppc_cached_irq_mask[2] |= (1 << (irq - 64))); - else /* mask high interrupt register */ - mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, - ppc_cached_irq_mask[1] |= (1 << (irq - 32))); - } - else /* mask low interrupt register */ - mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO, - ppc_cached_irq_mask[0] |= (1 << irq)); - - (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); - return; -} - -/* mv64360_mask_irq() - * - * This function disables the requested interrupt. - * - * Input Variable(s): - * unsigned int interrupt number (IRQ0...IRQ95). - * - * Output Variable(s): - * None. - * - * Returns: - * void - */ -static void -mv64360_mask_irq(unsigned int irq) -{ -#ifdef CONFIG_SMP - if ((irq - mv64360_irq_base) == MV64x60_IRQ_DOORBELL) { - mv64x60_clr_bits(&bh, MV64360_IC_CPU1_INTR_MASK_LO, - (1 << MV64x60_IRQ_DOORBELL)); - return; - } -#endif - irq -= mv64360_irq_base; - - if (irq > 31) { - if (irq > 63) /* mask GPP irq */ - mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, - ppc_cached_irq_mask[2] &= ~(1 << (irq - 64))); - else /* mask high interrupt register */ - mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, - ppc_cached_irq_mask[1] &= ~(1 << (irq - 32))); - } - else /* mask low interrupt register */ - mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO, - ppc_cached_irq_mask[0] &= ~(1 << irq)); - - (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); - return; -} - -static irqreturn_t -mv64360_cpu_error_int_handler(int irq, void *dev_id) -{ - printk(KERN_ERR "mv64360_cpu_error_int_handler: %s 0x%08x\n", - "Error on CPU interface - Cause regiser", - mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE)); - printk(KERN_ERR "\tCPU error register dump:\n"); - printk(KERN_ERR "\tAddress low 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO)); - printk(KERN_ERR "\tAddress high 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI)); - printk(KERN_ERR "\tData low 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO)); - printk(KERN_ERR "\tData high 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI)); - printk(KERN_ERR "\tParity 0x%08x\n", - mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY)); - mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0); - return IRQ_HANDLED; -} - -static irqreturn_t -mv64360_sram_error_int_handler(int irq, void *dev_id) -{ - printk(KERN_ERR "mv64360_sram_error_int_handler: %s 0x%08x\n", - "Error in internal SRAM - Cause register", - mv64x60_read(&bh, MV64360_SRAM_ERR_CAUSE)); - printk(KERN_ERR "\tSRAM error register dump:\n"); - printk(KERN_ERR "\tAddress Low 0x%08x\n", - mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_LO)); - printk(KERN_ERR "\tAddress High 0x%08x\n", - mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_HI)); - printk(KERN_ERR "\tData Low 0x%08x\n", - mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_LO)); - printk(KERN_ERR "\tData High 0x%08x\n", - mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_HI)); - printk(KERN_ERR "\tParity 0x%08x\n", - mv64x60_read(&bh, MV64360_SRAM_ERR_PARITY)); - mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0); - return IRQ_HANDLED; -} - -static irqreturn_t -mv64360_pci_error_int_handler(int irq, void *dev_id) -{ - u32 val; - unsigned int pci_bus = (unsigned int)dev_id; - - if (pci_bus == 0) { /* Error on PCI 0 */ - val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE); - printk(KERN_ERR "%s: Error in PCI %d Interface\n", - "mv64360_pci_error_int_handler", pci_bus); - printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus); - printk(KERN_ERR "\tCause register 0x%08x\n", val); - printk(KERN_ERR "\tAddress Low 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO)); - printk(KERN_ERR "\tAddress High 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI)); - printk(KERN_ERR "\tAttribute 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO)); - printk(KERN_ERR "\tCommand 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD)); - mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val); - } - if (pci_bus == 1) { /* Error on PCI 1 */ - val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE); - printk(KERN_ERR "%s: Error in PCI %d Interface\n", - "mv64360_pci_error_int_handler", pci_bus); - printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus); - printk(KERN_ERR "\tCause register 0x%08x\n", val); - printk(KERN_ERR "\tAddress Low 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO)); - printk(KERN_ERR "\tAddress High 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI)); - printk(KERN_ERR "\tAttribute 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO)); - printk(KERN_ERR "\tCommand 0x%08x\n", - mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD)); - mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val); - } - return IRQ_HANDLED; -} - -/* - * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of - * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as - * well. IOW, don't set bit 0. - */ -#define MV64360_PCI0_ERR_MASK_VAL 0x00a50c24 - -static int __init -mv64360_register_hdlrs(void) -{ - int rc; - - /* Clear old errors and register CPU interface error intr handler */ - mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0); - if ((rc = request_irq(MV64x60_IRQ_CPU_ERR + mv64360_irq_base, - mv64360_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, NULL))) - printk(KERN_WARNING "Can't register cpu error handler: %d", rc); - - mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); - mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000ff); - - /* Clear old errors and register internal SRAM error intr handler */ - mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0); - if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR + mv64360_irq_base, - mv64360_sram_error_int_handler,IRQF_DISABLED,SRAM_INTR_STR, NULL))) - printk(KERN_WARNING "Can't register SRAM error handler: %d",rc); - - /* Clear old errors and register PCI 0 error intr handler */ - mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0); - if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base, - mv64360_pci_error_int_handler, - IRQF_DISABLED, PCI0_INTR_STR, (void *)0))) - printk(KERN_WARNING "Can't register pci 0 error handler: %d", - rc); - - mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0); - mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL); - - /* Erratum FEr PCI-#16 says to clear bit 0 of PCI SERRn Mask reg. */ - mv64x60_write(&bh, MV64x60_PCI0_ERR_SERR_MASK, - mv64x60_read(&bh, MV64x60_PCI0_ERR_SERR_MASK) & ~0x1UL); - - /* Clear old errors and register PCI 1 error intr handler */ - mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0); - if ((rc = request_irq(MV64360_IRQ_PCI1 + mv64360_irq_base, - mv64360_pci_error_int_handler, - IRQF_DISABLED, PCI1_INTR_STR, (void *)1))) - printk(KERN_WARNING "Can't register pci 1 error handler: %d", - rc); - - mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0); - mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL); - - /* Erratum FEr PCI-#16 says to clear bit 0 of PCI Intr Mask reg. */ - mv64x60_write(&bh, MV64x60_PCI1_ERR_SERR_MASK, - mv64x60_read(&bh, MV64x60_PCI1_ERR_SERR_MASK) & ~0x1UL); - - return 0; -} - -arch_initcall(mv64360_register_hdlrs); diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c deleted file mode 100644 index 418f3053de52..000000000000 --- a/arch/ppc/syslib/mv64x60.c +++ /dev/null @@ -1,2485 +0,0 @@ -/* - * Common routines for the Marvell/Galileo Discovery line of host bridges - * (gt64260, mv64360, mv64460, ...). - * - * Author: Mark A. Greer - * - * 2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -u8 mv64x60_pci_exclude_bridge = 1; -DEFINE_SPINLOCK(mv64x60_lock); - -static phys_addr_t mv64x60_bridge_pbase; -static void __iomem *mv64x60_bridge_vbase; -static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID; -static u32 mv64x60_bridge_rev; -#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) -static struct pci_controller sysfs_hose_a; -#endif - -static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits); -static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits); -static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, - u32 window, u32 base); -static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh, - struct pci_controller *hose, u32 bus, u32 base); -static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window); -static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window); -static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window); -static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window); -static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window); -static void gt64260_disable_all_windows(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si); -static void gt64260a_chip_specific_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si); -static void gt64260b_chip_specific_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si); - -static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits); -static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits); -static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, - u32 window, u32 base); -static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh, - struct pci_controller *hose, u32 bus, u32 base); -static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window); -static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window); -static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window); -static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window); -static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window); -static void mv64360_disable_all_windows(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si); -static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); -static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base); -static void mv64360_chip_specific_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si); -static void mv64460_chip_specific_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si); - - -/* - * Define tables that have the chip-specific info for each type of - * Marvell bridge chip. - */ -static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */ - .translate_size = gt64260_translate_size, - .untranslate_size = gt64260_untranslate_size, - .set_pci2mem_window = gt64260_set_pci2mem_window, - .set_pci2regs_window = gt64260_set_pci2regs_window, - .is_enabled_32bit = gt64260_is_enabled_32bit, - .enable_window_32bit = gt64260_enable_window_32bit, - .disable_window_32bit = gt64260_disable_window_32bit, - .enable_window_64bit = gt64260_enable_window_64bit, - .disable_window_64bit = gt64260_disable_window_64bit, - .disable_all_windows = gt64260_disable_all_windows, - .chip_specific_init = gt64260a_chip_specific_init, - .window_tab_32bit = gt64260_32bit_windows, - .window_tab_64bit = gt64260_64bit_windows, -}; - -static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */ - .translate_size = gt64260_translate_size, - .untranslate_size = gt64260_untranslate_size, - .set_pci2mem_window = gt64260_set_pci2mem_window, - .set_pci2regs_window = gt64260_set_pci2regs_window, - .is_enabled_32bit = gt64260_is_enabled_32bit, - .enable_window_32bit = gt64260_enable_window_32bit, - .disable_window_32bit = gt64260_disable_window_32bit, - .enable_window_64bit = gt64260_enable_window_64bit, - .disable_window_64bit = gt64260_disable_window_64bit, - .disable_all_windows = gt64260_disable_all_windows, - .chip_specific_init = gt64260b_chip_specific_init, - .window_tab_32bit = gt64260_32bit_windows, - .window_tab_64bit = gt64260_64bit_windows, -}; - -static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */ - .translate_size = mv64360_translate_size, - .untranslate_size = mv64360_untranslate_size, - .set_pci2mem_window = mv64360_set_pci2mem_window, - .set_pci2regs_window = mv64360_set_pci2regs_window, - .is_enabled_32bit = mv64360_is_enabled_32bit, - .enable_window_32bit = mv64360_enable_window_32bit, - .disable_window_32bit = mv64360_disable_window_32bit, - .enable_window_64bit = mv64360_enable_window_64bit, - .disable_window_64bit = mv64360_disable_window_64bit, - .disable_all_windows = mv64360_disable_all_windows, - .config_io2mem_windows = mv64360_config_io2mem_windows, - .set_mpsc2regs_window = mv64360_set_mpsc2regs_window, - .chip_specific_init = mv64360_chip_specific_init, - .window_tab_32bit = mv64360_32bit_windows, - .window_tab_64bit = mv64360_64bit_windows, -}; - -static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */ - .translate_size = mv64360_translate_size, - .untranslate_size = mv64360_untranslate_size, - .set_pci2mem_window = mv64360_set_pci2mem_window, - .set_pci2regs_window = mv64360_set_pci2regs_window, - .is_enabled_32bit = mv64360_is_enabled_32bit, - .enable_window_32bit = mv64360_enable_window_32bit, - .disable_window_32bit = mv64360_disable_window_32bit, - .enable_window_64bit = mv64360_enable_window_64bit, - .disable_window_64bit = mv64360_disable_window_64bit, - .disable_all_windows = mv64360_disable_all_windows, - .config_io2mem_windows = mv64360_config_io2mem_windows, - .set_mpsc2regs_window = mv64360_set_mpsc2regs_window, - .chip_specific_init = mv64460_chip_specific_init, - .window_tab_32bit = mv64360_32bit_windows, - .window_tab_64bit = mv64360_64bit_windows, -}; - -/* - ***************************************************************************** - * - * Platform Device Definitions - * - ***************************************************************************** - */ -#ifdef CONFIG_SERIAL_MPSC -static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = { - .mrr_val = 0x3ffffe38, - .rcrr_val = 0, - .tcrr_val = 0, - .intr_cause_val = 0, - .intr_mask_val = 0, -}; - -static struct resource mv64x60_mpsc_shared_resources[] = { - /* Do not change the order of the IORESOURCE_MEM resources */ - [0] = { - .name = "mpsc routing base", - .start = MV64x60_MPSC_ROUTING_OFFSET, - .end = MV64x60_MPSC_ROUTING_OFFSET + - MPSC_ROUTING_REG_BLOCK_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "sdma intr base", - .start = MV64x60_SDMA_INTR_OFFSET, - .end = MV64x60_SDMA_INTR_OFFSET + - MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mpsc_shared_device = { /* Shared device */ - .name = MPSC_SHARED_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv64x60_mpsc_shared_resources), - .resource = mv64x60_mpsc_shared_resources, - .dev = { - .platform_data = &mv64x60_mpsc_shared_pdata, - }, -}; - -static struct mpsc_pdata mv64x60_mpsc0_pdata = { - .mirror_regs = 0, - .cache_mgmt = 0, - .max_idle = 0, - .default_baud = 9600, - .default_bits = 8, - .default_parity = 'n', - .default_flow = 'n', - .chr_1_val = 0x00000000, - .chr_2_val = 0x00000000, - .chr_10_val = 0x00000003, - .mpcr_val = 0, - .bcr_val = 0, - .brg_can_tune = 0, - .brg_clk_src = 8, /* Default to TCLK */ - .brg_clk_freq = 100000000, /* Default to 100 MHz */ -}; - -static struct resource mv64x60_mpsc0_resources[] = { - /* Do not change the order of the IORESOURCE_MEM resources */ - [0] = { - .name = "mpsc 0 base", - .start = MV64x60_MPSC_0_OFFSET, - .end = MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "sdma 0 base", - .start = MV64x60_SDMA_0_OFFSET, - .end = MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .name = "brg 0 base", - .start = MV64x60_BRG_0_OFFSET, - .end = MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [3] = { - .name = "sdma 0 irq", - .start = MV64x60_IRQ_SDMA_0, - .end = MV64x60_IRQ_SDMA_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mpsc0_device = { - .name = MPSC_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv64x60_mpsc0_resources), - .resource = mv64x60_mpsc0_resources, - .dev = { - .platform_data = &mv64x60_mpsc0_pdata, - }, -}; - -static struct mpsc_pdata mv64x60_mpsc1_pdata = { - .mirror_regs = 0, - .cache_mgmt = 0, - .max_idle = 0, - .default_baud = 9600, - .default_bits = 8, - .default_parity = 'n', - .default_flow = 'n', - .chr_1_val = 0x00000000, - .chr_1_val = 0x00000000, - .chr_2_val = 0x00000000, - .chr_10_val = 0x00000003, - .mpcr_val = 0, - .bcr_val = 0, - .brg_can_tune = 0, - .brg_clk_src = 8, /* Default to TCLK */ - .brg_clk_freq = 100000000, /* Default to 100 MHz */ -}; - -static struct resource mv64x60_mpsc1_resources[] = { - /* Do not change the order of the IORESOURCE_MEM resources */ - [0] = { - .name = "mpsc 1 base", - .start = MV64x60_MPSC_1_OFFSET, - .end = MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "sdma 1 base", - .start = MV64x60_SDMA_1_OFFSET, - .end = MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .name = "brg 1 base", - .start = MV64x60_BRG_1_OFFSET, - .end = MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [3] = { - .name = "sdma 1 irq", - .start = MV64360_IRQ_SDMA_1, - .end = MV64360_IRQ_SDMA_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mpsc1_device = { - .name = MPSC_CTLR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(mv64x60_mpsc1_resources), - .resource = mv64x60_mpsc1_resources, - .dev = { - .platform_data = &mv64x60_mpsc1_pdata, - }, -}; -#endif - -#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) -static struct resource mv64x60_eth_shared_resources[] = { - [0] = { - .name = "ethernet shared base", - .start = MV643XX_ETH_SHARED_REGS, - .end = MV643XX_ETH_SHARED_REGS + - MV643XX_ETH_SHARED_REGS_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv64x60_eth_shared_device = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv64x60_eth_shared_resources), - .resource = mv64x60_eth_shared_resources, -}; - -#ifdef CONFIG_MV643XX_ETH_0 -static struct resource mv64x60_eth0_resources[] = { - [0] = { - .name = "eth0 irq", - .start = MV64x60_IRQ_ETH_0, - .end = MV64x60_IRQ_ETH_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv643xx_eth_platform_data eth0_pd = { - .shared = &mv64x60_eth_shared_device; - .port_number = 0, -}; - -static struct platform_device eth0_device = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv64x60_eth0_resources), - .resource = mv64x60_eth0_resources, - .dev = { - .platform_data = ð0_pd, - }, -}; -#endif - -#ifdef CONFIG_MV643XX_ETH_1 -static struct resource mv64x60_eth1_resources[] = { - [0] = { - .name = "eth1 irq", - .start = MV64x60_IRQ_ETH_1, - .end = MV64x60_IRQ_ETH_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv643xx_eth_platform_data eth1_pd = { - .shared = &mv64x60_eth_shared_device; - .port_number = 1, -}; - -static struct platform_device eth1_device = { - .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(mv64x60_eth1_resources), - .resource = mv64x60_eth1_resources, - .dev = { - .platform_data = ð1_pd, - }, -}; -#endif - -#ifdef CONFIG_MV643XX_ETH_2 -static struct resource mv64x60_eth2_resources[] = { - [0] = { - .name = "eth2 irq", - .start = MV64x60_IRQ_ETH_2, - .end = MV64x60_IRQ_ETH_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv643xx_eth_platform_data eth2_pd = { - .shared = &mv64x60_eth_shared_device; - .port_number = 2, -}; - -static struct platform_device eth2_device = { - .name = MV643XX_ETH_NAME, - .id = 2, - .num_resources = ARRAY_SIZE(mv64x60_eth2_resources), - .resource = mv64x60_eth2_resources, - .dev = { - .platform_data = ð2_pd, - }, -}; -#endif -#endif - -#ifdef CONFIG_I2C_MV64XXX -static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = { - .freq_m = 8, - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource mv64xxx_i2c_resources[] = { - /* Do not change the order of the IORESOURCE_MEM resources */ - [0] = { - .name = "mv64xxx i2c base", - .start = MV64XXX_I2C_OFFSET, - .end = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "mv64xxx i2c irq", - .start = MV64x60_IRQ_I2C, - .end = MV64x60_IRQ_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_device = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv64xxx_i2c_resources), - .resource = mv64xxx_i2c_resources, - .dev = { - .platform_data = &mv64xxx_i2c_pdata, - }, -}; -#endif - -#ifdef CONFIG_WATCHDOG -static struct mv64x60_wdt_pdata mv64x60_wdt_pdata = { - .timeout = 10, /* default watchdog expiry in seconds */ - .bus_clk = 133, /* default bus clock in MHz */ -}; - -static struct resource mv64x60_wdt_resources[] = { - [0] = { - .name = "mv64x60 wdt base", - .start = MV64x60_WDT_WDC, - .end = MV64x60_WDT_WDC + 8 - 1, /* two 32-bit registers */ - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device wdt_device = { - .name = MV64x60_WDT_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv64x60_wdt_resources), - .resource = mv64x60_wdt_resources, - .dev = { - .platform_data = &mv64x60_wdt_pdata, - }, -}; -#endif - -#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) -static struct mv64xxx_pdata mv64xxx_pdata = { - .hs_reg_valid = 0, -}; - -static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */ - .name = MV64XXX_DEV_NAME, - .id = 0, - .dev = { - .platform_data = &mv64xxx_pdata, - }, -}; -#endif - -static struct platform_device *mv64x60_pd_devs[] __initdata = { -#ifdef CONFIG_SERIAL_MPSC - &mpsc_shared_device, - &mpsc0_device, - &mpsc1_device, -#endif -#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) - &mv64x60_eth_shared_device, -#endif -#ifdef CONFIG_MV643XX_ETH_0 - ð0_device, -#endif -#ifdef CONFIG_MV643XX_ETH_1 - ð1_device, -#endif -#ifdef CONFIG_MV643XX_ETH_2 - ð2_device, -#endif -#ifdef CONFIG_I2C_MV64XXX - &i2c_device, -#endif -#ifdef CONFIG_MV64X60_WDT - &wdt_device, -#endif -#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) - &mv64xxx_device, -#endif -}; - -/* - ***************************************************************************** - * - * Bridge Initialization Routines - * - ***************************************************************************** - */ -/* - * mv64x60_init() - * - * Initialize the bridge based on setting passed in via 'si'. The bridge - * handle, 'bh', will be set so that it can be used to make subsequent - * calls to routines in this file. - */ -int __init -mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si) -{ - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]; - - if (ppc_md.progress) - ppc_md.progress("mv64x60 initialization", 0x0); - - spin_lock_init(&mv64x60_lock); - mv64x60_early_init(bh, si); - - if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) { - iounmap(bh->v_base); - bh->v_base = 0; - if (ppc_md.progress) - ppc_md.progress("mv64x60_init: Can't determine chip",0); - return -1; - } - - bh->ci->disable_all_windows(bh, si); - mv64x60_get_mem_windows(bh, mem_windows); - mv64x60_config_cpu2mem_windows(bh, si, mem_windows); - - if (bh->ci->config_io2mem_windows) - bh->ci->config_io2mem_windows(bh, si, mem_windows); - if (bh->ci->set_mpsc2regs_window) - bh->ci->set_mpsc2regs_window(bh, si->phys_reg_base); - - if (si->pci_1.enable_bus) { - bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base, - si->pci_1.pci_io.size); - isa_io_base = bh->io_base_b; - } - - if (si->pci_0.enable_bus) { - bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base, - si->pci_0.pci_io.size); - isa_io_base = bh->io_base_a; - - mv64x60_alloc_hose(bh, MV64x60_PCI0_CONFIG_ADDR, - MV64x60_PCI0_CONFIG_DATA, &bh->hose_a); - mv64x60_config_resources(bh->hose_a, &si->pci_0, bh->io_base_a); - mv64x60_config_pci_params(bh->hose_a, &si->pci_0); - - mv64x60_config_cpu2pci_windows(bh, &si->pci_0, 0); - mv64x60_config_pci2mem_windows(bh, bh->hose_a, &si->pci_0, 0, - mem_windows); - bh->ci->set_pci2regs_window(bh, bh->hose_a, 0, - si->phys_reg_base); - } - - if (si->pci_1.enable_bus) { - mv64x60_alloc_hose(bh, MV64x60_PCI1_CONFIG_ADDR, - MV64x60_PCI1_CONFIG_DATA, &bh->hose_b); - mv64x60_config_resources(bh->hose_b, &si->pci_1, bh->io_base_b); - mv64x60_config_pci_params(bh->hose_b, &si->pci_1); - - mv64x60_config_cpu2pci_windows(bh, &si->pci_1, 1); - mv64x60_config_pci2mem_windows(bh, bh->hose_b, &si->pci_1, 1, - mem_windows); - bh->ci->set_pci2regs_window(bh, bh->hose_b, 1, - si->phys_reg_base); - } - - bh->ci->chip_specific_init(bh, si); - mv64x60_pd_fixup(bh, mv64x60_pd_devs, ARRAY_SIZE(mv64x60_pd_devs)); - - return 0; -} - -/* - * mv64x60_early_init() - * - * Do some bridge work that must take place before we start messing with - * the bridge for real. - */ -void __init -mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si) -{ - struct pci_controller hose_a, hose_b; - - memset(bh, 0, sizeof(*bh)); - - bh->p_base = si->phys_reg_base; - bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE); - - mv64x60_bridge_pbase = bh->p_base; - mv64x60_bridge_vbase = bh->v_base; - - /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */ - bh->pci_mode_a = mv64x60_read(bh, MV64x60_PCI0_MODE) & - MV64x60_PCIMODE_MASK; - bh->pci_mode_b = mv64x60_read(bh, MV64x60_PCI1_MODE) & - MV64x60_PCIMODE_MASK; - - /* Need temporary hose structs to call mv64x60_set_bus() */ - memset(&hose_a, 0, sizeof(hose_a)); - memset(&hose_b, 0, sizeof(hose_b)); - setup_indirect_pci_nomap(&hose_a, bh->v_base + MV64x60_PCI0_CONFIG_ADDR, - bh->v_base + MV64x60_PCI0_CONFIG_DATA); - setup_indirect_pci_nomap(&hose_b, bh->v_base + MV64x60_PCI1_CONFIG_ADDR, - bh->v_base + MV64x60_PCI1_CONFIG_DATA); - bh->hose_a = &hose_a; - bh->hose_b = &hose_b; - -#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) - /* Save a copy of hose_a for sysfs functions -- hack */ - memcpy(&sysfs_hose_a, &hose_a, sizeof(hose_a)); -#endif - - mv64x60_set_bus(bh, 0, 0); - mv64x60_set_bus(bh, 1, 0); - - bh->hose_a = NULL; - bh->hose_b = NULL; - - /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */ - mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001); - mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001); - - /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */ - mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12)); - mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27)); - - mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff); - mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff); -} - -/* - ***************************************************************************** - * - * Window Config Routines - * - ***************************************************************************** - */ -/* - * mv64x60_get_32bit_window() - * - * Determine the base address and size of a 32-bit window on the bridge. - */ -void __init -mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window, - u32 *base, u32 *size) -{ - u32 val, base_reg, size_reg, base_bits, size_bits; - u32 (*get_from_field)(u32 val, u32 num_bits); - - base_reg = bh->ci->window_tab_32bit[window].base_reg; - - if (base_reg != 0) { - size_reg = bh->ci->window_tab_32bit[window].size_reg; - base_bits = bh->ci->window_tab_32bit[window].base_bits; - size_bits = bh->ci->window_tab_32bit[window].size_bits; - get_from_field= bh->ci->window_tab_32bit[window].get_from_field; - - val = mv64x60_read(bh, base_reg); - *base = get_from_field(val, base_bits); - - if (size_reg != 0) { - val = mv64x60_read(bh, size_reg); - val = get_from_field(val, size_bits); - *size = bh->ci->untranslate_size(*base, val, size_bits); - } else - *size = 0; - } else { - *base = 0; - *size = 0; - } - - pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n", - window, *base, *size); -} - -/* - * mv64x60_set_32bit_window() - * - * Set the base address and size of a 32-bit window on the bridge. - */ -void __init -mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, - u32 base, u32 size, u32 other_bits) -{ - u32 val, base_reg, size_reg, base_bits, size_bits; - u32 (*map_to_field)(u32 val, u32 num_bits); - - pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n", - window, base, size, other_bits); - - base_reg = bh->ci->window_tab_32bit[window].base_reg; - - if (base_reg != 0) { - size_reg = bh->ci->window_tab_32bit[window].size_reg; - base_bits = bh->ci->window_tab_32bit[window].base_bits; - size_bits = bh->ci->window_tab_32bit[window].size_bits; - map_to_field = bh->ci->window_tab_32bit[window].map_to_field; - - val = map_to_field(base, base_bits) | other_bits; - mv64x60_write(bh, base_reg, val); - - if (size_reg != 0) { - val = bh->ci->translate_size(base, size, size_bits); - val = map_to_field(val, size_bits); - mv64x60_write(bh, size_reg, val); - } - - (void)mv64x60_read(bh, base_reg); /* Flush FIFO */ - } -} - -/* - * mv64x60_get_64bit_window() - * - * Determine the base address and size of a 64-bit window on the bridge. - */ -void __init -mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, - u32 *base_hi, u32 *base_lo, u32 *size) -{ - u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits; - u32 (*get_from_field)(u32 val, u32 num_bits); - - base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg; - - if (base_lo_reg != 0) { - size_reg = bh->ci->window_tab_64bit[window].size_reg; - base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits; - size_bits = bh->ci->window_tab_64bit[window].size_bits; - get_from_field= bh->ci->window_tab_64bit[window].get_from_field; - - *base_hi = mv64x60_read(bh, - bh->ci->window_tab_64bit[window].base_hi_reg); - - val = mv64x60_read(bh, base_lo_reg); - *base_lo = get_from_field(val, base_lo_bits); - - if (size_reg != 0) { - val = mv64x60_read(bh, size_reg); - val = get_from_field(val, size_bits); - *size = bh->ci->untranslate_size(*base_lo, val, - size_bits); - } else - *size = 0; - } else { - *base_hi = 0; - *base_lo = 0; - *size = 0; - } - - pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, " - "size: 0x%x\n", window, *base_hi, *base_lo, *size); -} - -/* - * mv64x60_set_64bit_window() - * - * Set the base address and size of a 64-bit window on the bridge. - */ -void __init -mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window, - u32 base_hi, u32 base_lo, u32 size, u32 other_bits) -{ - u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits; - u32 (*map_to_field)(u32 val, u32 num_bits); - - pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, " - "size: 0x%x, other: 0x%x\n", - window, base_hi, base_lo, size, other_bits); - - base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg; - - if (base_lo_reg != 0) { - size_reg = bh->ci->window_tab_64bit[window].size_reg; - base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits; - size_bits = bh->ci->window_tab_64bit[window].size_bits; - map_to_field = bh->ci->window_tab_64bit[window].map_to_field; - - mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg, - base_hi); - - val = map_to_field(base_lo, base_lo_bits) | other_bits; - mv64x60_write(bh, base_lo_reg, val); - - if (size_reg != 0) { - val = bh->ci->translate_size(base_lo, size, size_bits); - val = map_to_field(val, size_bits); - mv64x60_write(bh, size_reg, val); - } - - (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */ - } -} - -/* - * mv64x60_mask() - * - * Take the high-order 'num_bits' of 'val' & mask off low bits. - */ -u32 __init -mv64x60_mask(u32 val, u32 num_bits) -{ - return val & (0xffffffff << (32 - num_bits)); -} - -/* - * mv64x60_shift_left() - * - * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB). - */ -u32 __init -mv64x60_shift_left(u32 val, u32 num_bits) -{ - return val << (32 - num_bits); -} - -/* - * mv64x60_shift_right() - * - * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB). - */ -u32 __init -mv64x60_shift_right(u32 val, u32 num_bits) -{ - return val >> (32 - num_bits); -} - -/* - ***************************************************************************** - * - * Chip Identification Routines - * - ***************************************************************************** - */ -/* - * mv64x60_get_type() - * - * Determine the type of bridge chip we have. - */ -int __init -mv64x60_get_type(struct mv64x60_handle *bh) -{ - struct pci_controller hose; - u16 val; - u8 save_exclude; - - memset(&hose, 0, sizeof(hose)); - setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR, - bh->v_base + MV64x60_PCI0_CONFIG_DATA); - - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - /* Sanity check of bridge's Vendor ID */ - early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val); - - if (val != PCI_VENDOR_ID_MARVELL) { - mv64x60_pci_exclude_bridge = save_exclude; - return -1; - } - - /* Get the revision of the chip */ - early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION, - &val); - bh->rev = (u32)(val & 0xff); - - /* Figure out the type of Marvell bridge it is */ - early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val); - mv64x60_pci_exclude_bridge = save_exclude; - - switch (val) { - case PCI_DEVICE_ID_MARVELL_GT64260: - switch (bh->rev) { - case GT64260_REV_A: - bh->type = MV64x60_TYPE_GT64260A; - break; - - default: - printk(KERN_WARNING "Unsupported GT64260 rev %04x\n", - bh->rev); - /* Assume its similar to a 'B' rev and fallthru */ - case GT64260_REV_B: - bh->type = MV64x60_TYPE_GT64260B; - break; - } - break; - - case PCI_DEVICE_ID_MARVELL_MV64360: - /* Marvell won't tell me how to distinguish a 64361 & 64362 */ - bh->type = MV64x60_TYPE_MV64360; - break; - - case PCI_DEVICE_ID_MARVELL_MV64460: - bh->type = MV64x60_TYPE_MV64460; - break; - - default: - printk(KERN_ERR "Unknown Marvell bridge type %04x\n", val); - return -1; - } - - /* Hang onto bridge type & rev for PIC code */ - mv64x60_bridge_type = bh->type; - mv64x60_bridge_rev = bh->rev; - - return 0; -} - -/* - * mv64x60_setup_for_chip() - * - * Set 'bh' to use the proper set of routine for the bridge chip that we have. - */ -int __init -mv64x60_setup_for_chip(struct mv64x60_handle *bh) -{ - int rc = 0; - - /* Set up chip-specific info based on the chip/bridge type */ - switch(bh->type) { - case MV64x60_TYPE_GT64260A: - bh->ci = >64260a_ci; - break; - - case MV64x60_TYPE_GT64260B: - bh->ci = >64260b_ci; - break; - - case MV64x60_TYPE_MV64360: - bh->ci = &mv64360_ci; - break; - - case MV64x60_TYPE_MV64460: - bh->ci = &mv64460_ci; - break; - - case MV64x60_TYPE_INVALID: - default: - if (ppc_md.progress) - ppc_md.progress("mv64x60: Unsupported bridge", 0x0); - printk(KERN_ERR "mv64x60: Unsupported bridge\n"); - rc = -1; - } - - return rc; -} - -/* - * mv64x60_get_bridge_vbase() - * - * Return the virtual address of the bridge's registers. - */ -void __iomem * -mv64x60_get_bridge_vbase(void) -{ - return mv64x60_bridge_vbase; -} - -/* - * mv64x60_get_bridge_type() - * - * Return the type of bridge on the platform. - */ -u32 -mv64x60_get_bridge_type(void) -{ - return mv64x60_bridge_type; -} - -/* - * mv64x60_get_bridge_rev() - * - * Return the revision of the bridge on the platform. - */ -u32 -mv64x60_get_bridge_rev(void) -{ - return mv64x60_bridge_rev; -} - -/* - ***************************************************************************** - * - * System Memory Window Related Routines - * - ***************************************************************************** - */ -/* - * mv64x60_get_mem_size() - * - * Calculate the amount of memory that the memory controller is set up for. - * This should only be used by board-specific code if there is no other - * way to determine the amount of memory in the system. - */ -u32 __init -mv64x60_get_mem_size(u32 bridge_base, u32 chip_type) -{ - struct mv64x60_handle bh; - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]; - u32 rc = 0; - - memset(&bh, 0, sizeof(bh)); - - bh.type = chip_type; - bh.v_base = (void *)bridge_base; - - if (!mv64x60_setup_for_chip(&bh)) { - mv64x60_get_mem_windows(&bh, mem_windows); - rc = mv64x60_calc_mem_size(&bh, mem_windows); - } - - return rc; -} - -/* - * mv64x60_get_mem_windows() - * - * Get the values in the memory controller & return in the 'mem_windows' array. - */ -void __init -mv64x60_get_mem_windows(struct mv64x60_handle *bh, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) -{ - u32 i, win; - - for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++) - if (bh->ci->is_enabled_32bit(bh, win)) - mv64x60_get_32bit_window(bh, win, - &mem_windows[i][0], &mem_windows[i][1]); - else { - mem_windows[i][0] = 0; - mem_windows[i][1] = 0; - } -} - -/* - * mv64x60_calc_mem_size() - * - * Using the memory controller register values in 'mem_windows', determine - * how much memory it is set up for. - */ -u32 __init -mv64x60_calc_mem_size(struct mv64x60_handle *bh, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) -{ - u32 i, total = 0; - - for (i=0; iSystem MEM, PCI Config Routines - * - ***************************************************************************** - */ -/* - * mv64x60_config_cpu2mem_windows() - * - * Configure CPU->Memory windows on the bridge. - */ -static u32 prot_tab[] __initdata = { - MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN, - MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN -}; - -static u32 cpu_snoop_tab[] __initdata = { - MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN, - MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN -}; - -void __init -mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) -{ - u32 i, win; - - /* Set CPU protection & snoop windows */ - for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++) - if (bh->ci->is_enabled_32bit(bh, win)) { - mv64x60_set_32bit_window(bh, prot_tab[i], - mem_windows[i][0], mem_windows[i][1], - si->cpu_prot_options[i]); - bh->ci->enable_window_32bit(bh, prot_tab[i]); - - if (bh->ci->window_tab_32bit[cpu_snoop_tab[i]]. - base_reg != 0) { - mv64x60_set_32bit_window(bh, cpu_snoop_tab[i], - mem_windows[i][0], mem_windows[i][1], - si->cpu_snoop_options[i]); - bh->ci->enable_window_32bit(bh, - cpu_snoop_tab[i]); - } - - } -} - -/* - * mv64x60_config_cpu2pci_windows() - * - * Configure the CPU->PCI windows for one of the PCI buses. - */ -static u32 win_tab[2][4] __initdata = { - { MV64x60_CPU2PCI0_IO_WIN, MV64x60_CPU2PCI0_MEM_0_WIN, - MV64x60_CPU2PCI0_MEM_1_WIN, MV64x60_CPU2PCI0_MEM_2_WIN }, - { MV64x60_CPU2PCI1_IO_WIN, MV64x60_CPU2PCI1_MEM_0_WIN, - MV64x60_CPU2PCI1_MEM_1_WIN, MV64x60_CPU2PCI1_MEM_2_WIN }, -}; - -static u32 remap_tab[2][4] __initdata = { - { MV64x60_CPU2PCI0_IO_REMAP_WIN, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN, - MV64x60_CPU2PCI0_MEM_1_REMAP_WIN, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN }, - { MV64x60_CPU2PCI1_IO_REMAP_WIN, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN, - MV64x60_CPU2PCI1_MEM_1_REMAP_WIN, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN } -}; - -void __init -mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, - struct mv64x60_pci_info *pi, u32 bus) -{ - int i; - - if (pi->pci_io.size > 0) { - mv64x60_set_32bit_window(bh, win_tab[bus][0], - pi->pci_io.cpu_base, pi->pci_io.size, pi->pci_io.swap); - mv64x60_set_32bit_window(bh, remap_tab[bus][0], - pi->pci_io.pci_base_lo, 0, 0); - bh->ci->enable_window_32bit(bh, win_tab[bus][0]); - } else /* Actually, the window should already be disabled */ - bh->ci->disable_window_32bit(bh, win_tab[bus][0]); - - for (i=0; i<3; i++) - if (pi->pci_mem[i].size > 0) { - mv64x60_set_32bit_window(bh, win_tab[bus][i+1], - pi->pci_mem[i].cpu_base, pi->pci_mem[i].size, - pi->pci_mem[i].swap); - mv64x60_set_64bit_window(bh, remap_tab[bus][i+1], - pi->pci_mem[i].pci_base_hi, - pi->pci_mem[i].pci_base_lo, 0, 0); - bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]); - } else /* Actually, the window should already be disabled */ - bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]); -} - -/* - ***************************************************************************** - * - * PCI->System MEM Config Routines - * - ***************************************************************************** - */ -/* - * mv64x60_config_pci2mem_windows() - * - * Configure the PCI->Memory windows on the bridge. - */ -static u32 pci_acc_tab[2][4] __initdata = { - { MV64x60_PCI02MEM_ACC_CNTL_0_WIN, MV64x60_PCI02MEM_ACC_CNTL_1_WIN, - MV64x60_PCI02MEM_ACC_CNTL_2_WIN, MV64x60_PCI02MEM_ACC_CNTL_3_WIN }, - { MV64x60_PCI12MEM_ACC_CNTL_0_WIN, MV64x60_PCI12MEM_ACC_CNTL_1_WIN, - MV64x60_PCI12MEM_ACC_CNTL_2_WIN, MV64x60_PCI12MEM_ACC_CNTL_3_WIN } -}; - -static u32 pci_snoop_tab[2][4] __initdata = { - { MV64x60_PCI02MEM_SNOOP_0_WIN, MV64x60_PCI02MEM_SNOOP_1_WIN, - MV64x60_PCI02MEM_SNOOP_2_WIN, MV64x60_PCI02MEM_SNOOP_3_WIN }, - { MV64x60_PCI12MEM_SNOOP_0_WIN, MV64x60_PCI12MEM_SNOOP_1_WIN, - MV64x60_PCI12MEM_SNOOP_2_WIN, MV64x60_PCI12MEM_SNOOP_3_WIN } -}; - -static u32 pci_size_tab[2][4] __initdata = { - { MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE, - MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE }, - { MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE, - MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE } -}; - -void __init -mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh, - struct pci_controller *hose, struct mv64x60_pci_info *pi, - u32 bus, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) -{ - u32 i, win; - - /* - * Set the access control, snoop, BAR size, and window base addresses. - * PCI->MEM windows base addresses will match exactly what the - * CPU->MEM windows are. - */ - for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++) - if (bh->ci->is_enabled_32bit(bh, win)) { - mv64x60_set_64bit_window(bh, - pci_acc_tab[bus][i], 0, - mem_windows[i][0], mem_windows[i][1], - pi->acc_cntl_options[i]); - bh->ci->enable_window_64bit(bh, pci_acc_tab[bus][i]); - - if (bh->ci->window_tab_64bit[ - pci_snoop_tab[bus][i]].base_lo_reg != 0) { - - mv64x60_set_64bit_window(bh, - pci_snoop_tab[bus][i], 0, - mem_windows[i][0], mem_windows[i][1], - pi->snoop_options[i]); - bh->ci->enable_window_64bit(bh, - pci_snoop_tab[bus][i]); - } - - bh->ci->set_pci2mem_window(hose, bus, i, - mem_windows[i][0]); - mv64x60_write(bh, pci_size_tab[bus][i], - mv64x60_mask(mem_windows[i][1] - 1, 20)); - - /* Enable the window */ - mv64x60_clr_bits(bh, ((bus == 0) ? - MV64x60_PCI0_BAR_ENABLE : - MV64x60_PCI1_BAR_ENABLE), (1 << i)); - } -} - -/* - ***************************************************************************** - * - * Hose & Resource Alloc/Init Routines - * - ***************************************************************************** - */ -/* - * mv64x60_alloc_hoses() - * - * Allocate the PCI hose structures for the bridge's PCI buses. - */ -void __init -mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data, - struct pci_controller **hose) -{ - *hose = pcibios_alloc_controller(); - setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr, - bh->v_base + cfg_data); -} - -/* - * mv64x60_config_resources() - * - * Calculate the offsets, etc. for the hose structures to reflect all of - * the address remapping that happens as you go from CPU->PCI and PCI->MEM. - */ -void __init -mv64x60_config_resources(struct pci_controller *hose, - struct mv64x60_pci_info *pi, u32 io_base) -{ - int i; - /* 2 hoses; 4 resources/hose; string <= 64 bytes */ - static char s[2][4][64]; - - if (pi->pci_io.size != 0) { - sprintf(s[hose->index][0], "PCI hose %d I/O Space", - hose->index); - pci_init_resource(&hose->io_resource, io_base - isa_io_base, - io_base - isa_io_base + pi->pci_io.size - 1, - IORESOURCE_IO, s[hose->index][0]); - hose->io_space.start = pi->pci_io.pci_base_lo; - hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1; - hose->io_base_phys = pi->pci_io.cpu_base; - hose->io_base_virt = (void *)isa_io_base; - } - - for (i=0; i<3; i++) - if (pi->pci_mem[i].size != 0) { - sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d", - hose->index, i); - pci_init_resource(&hose->mem_resources[i], - pi->pci_mem[i].cpu_base, - pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1, - IORESOURCE_MEM, s[hose->index][i+1]); - } - - hose->mem_space.end = pi->pci_mem[0].pci_base_lo + - pi->pci_mem[0].size - 1; - hose->pci_mem_offset = pi->pci_mem[0].cpu_base - - pi->pci_mem[0].pci_base_lo; -} - -/* - * mv64x60_config_pci_params() - * - * Configure a hose's PCI config space parameters. - */ -void __init -mv64x60_config_pci_params(struct pci_controller *hose, - struct mv64x60_pci_info *pi) -{ - u32 devfn; - u16 u16_val; - u8 save_exclude; - - devfn = PCI_DEVFN(0,0); - - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - - /* Set class code to indicate host bridge */ - u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */ - early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val); - - /* Enable bridge to be PCI master & respond to PCI MEM cycles */ - early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val); - u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK); - u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val); - - /* Set latency timer, cache line size, clear BIST */ - u16_val = (pi->latency_timer << 8) | (L1_CACHE_BYTES >> 2); - early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val); - - mv64x60_pci_exclude_bridge = save_exclude; -} - -/* - ***************************************************************************** - * - * PCI Related Routine - * - ***************************************************************************** - */ -/* - * mv64x60_set_bus() - * - * Set the bus number for the hose directly under the bridge. - */ -void __init -mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus) -{ - struct pci_controller *hose; - u32 pci_mode, p2p_cfg, pci_cfg_offset, val; - u8 save_exclude; - - if (bus == 0) { - pci_mode = bh->pci_mode_a; - p2p_cfg = MV64x60_PCI0_P2P_CONFIG; - pci_cfg_offset = 0x64; - hose = bh->hose_a; - } else { - pci_mode = bh->pci_mode_b; - p2p_cfg = MV64x60_PCI1_P2P_CONFIG; - pci_cfg_offset = 0xe4; - hose = bh->hose_b; - } - - child_bus &= 0xff; - val = mv64x60_read(bh, p2p_cfg); - - if (pci_mode == MV64x60_PCIMODE_CONVENTIONAL) { - val &= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */ - val |= (child_bus << 16) | 0xff; - mv64x60_write(bh, p2p_cfg, val); - (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */ - } else { /* PCI-X */ - /* - * Need to use the current bus/dev number (that's in the - * P2P CONFIG reg) to access the bridge's pci config space. - */ - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - early_write_config_dword(hose, (val & 0x00ff0000) >> 16, - PCI_DEVFN(((val & 0x1f000000) >> 24), 0), - pci_cfg_offset, child_bus << 8); - mv64x60_pci_exclude_bridge = save_exclude; - } -} - -/* - * mv64x60_pci_exclude_device() - * - * This routine is used to make the bridge not appear when the - * PCI subsystem is accessing PCI devices (in PCI config space). - */ -int -mv64x60_pci_exclude_device(u8 bus, u8 devfn) -{ - struct pci_controller *hose; - - hose = pci_bus_to_hose(bus); - - /* Skip slot 0 on both hoses */ - if ((mv64x60_pci_exclude_bridge == 1) && (PCI_SLOT(devfn) == 0) && - (hose->first_busno == bus)) - - return PCIBIOS_DEVICE_NOT_FOUND; - else - return PCIBIOS_SUCCESSFUL; -} /* mv64x60_pci_exclude_device() */ - -/* - ***************************************************************************** - * - * Platform Device Routines - * - ***************************************************************************** - */ - -/* - * mv64x60_pd_fixup() - * - * Need to add the base addr of where the bridge's regs are mapped in the - * physical addr space so drivers can ioremap() them. - */ -void __init -mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[], - u32 entries) -{ - struct resource *r; - u32 i, j; - - for (i=0; istart += bh->p_base; - r->end += bh->p_base; - j++; - } - } -} - -/* - * mv64x60_add_pds() - * - * Add the mv64x60 platform devices to the list of platform devices. - */ -static int __init -mv64x60_add_pds(void) -{ - return platform_add_devices(mv64x60_pd_devs, - ARRAY_SIZE(mv64x60_pd_devs)); -} -arch_initcall(mv64x60_add_pds); - -/* - ***************************************************************************** - * - * GT64260-Specific Routines - * - ***************************************************************************** - */ -/* - * gt64260_translate_size() - * - * On the GT64260, the size register is really the "top" address of the window. - */ -static u32 __init -gt64260_translate_size(u32 base, u32 size, u32 num_bits) -{ - return base + mv64x60_mask(size - 1, num_bits); -} - -/* - * gt64260_untranslate_size() - * - * Translate the top address of a window into a window size. - */ -static u32 __init -gt64260_untranslate_size(u32 base, u32 size, u32 num_bits) -{ - if (size >= base) - size = size - base + (1 << (32 - num_bits)); - else - size = 0; - - return size; -} - -/* - * gt64260_set_pci2mem_window() - * - * The PCI->MEM window registers are actually in PCI config space so need - * to set them by setting the correct config space BARs. - */ -static u32 gt64260_reg_addrs[2][4] __initdata = { - { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c } -}; - -static void __init -gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window, - u32 base) -{ - u8 save_exclude; - - pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window, - hose->index, base); - - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - early_write_config_dword(hose, 0, PCI_DEVFN(0, 0), - gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8); - mv64x60_pci_exclude_bridge = save_exclude; -} - -/* - * gt64260_set_pci2regs_window() - * - * Set where the bridge's registers appear in PCI MEM space. - */ -static u32 gt64260_offset[2] __initdata = {0x20, 0xa0}; - -static void __init -gt64260_set_pci2regs_window(struct mv64x60_handle *bh, - struct pci_controller *hose, u32 bus, u32 base) -{ - u8 save_exclude; - - pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index, - base); - - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus], - (base << 16)); - mv64x60_pci_exclude_bridge = save_exclude; -} - -/* - * gt64260_is_enabled_32bit() - * - * On a GT64260, a window is enabled iff its top address is >= to its base - * address. - */ -static u32 __init -gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window) -{ - u32 rc = 0; - - if ((gt64260_32bit_windows[window].base_reg != 0) && - (gt64260_32bit_windows[window].size_reg != 0) && - ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) & - ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >= - (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) & - ((1 << gt64260_32bit_windows[window].base_bits) - 1)))) - - rc = 1; - - return rc; -} - -/* - * gt64260_enable_window_32bit() - * - * On the GT64260, a window is enabled iff the top address is >= to the base - * address of the window. Since the window has already been configured by - * the time this routine is called, we have nothing to do here. - */ -static void __init -gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window) -{ - pr_debug("enable 32bit window: %d\n", window); -} - -/* - * gt64260_disable_window_32bit() - * - * On a GT64260, you disable a window by setting its top address to be less - * than its base address. - */ -static void __init -gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window) -{ - pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n", - window, gt64260_32bit_windows[window].base_reg, - gt64260_32bit_windows[window].size_reg); - - if ((gt64260_32bit_windows[window].base_reg != 0) && - (gt64260_32bit_windows[window].size_reg != 0)) { - - /* To disable, make bottom reg higher than top reg */ - mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff); - mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0); - } -} - -/* - * gt64260_enable_window_64bit() - * - * On the GT64260, a window is enabled iff the top address is >= to the base - * address of the window. Since the window has already been configured by - * the time this routine is called, we have nothing to do here. - */ -static void __init -gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window) -{ - pr_debug("enable 64bit window: %d\n", window); -} - -/* - * gt64260_disable_window_64bit() - * - * On a GT64260, you disable a window by setting its top address to be less - * than its base address. - */ -static void __init -gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window) -{ - pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n", - window, gt64260_64bit_windows[window].base_lo_reg, - gt64260_64bit_windows[window].size_reg); - - if ((gt64260_64bit_windows[window].base_lo_reg != 0) && - (gt64260_64bit_windows[window].size_reg != 0)) { - - /* To disable, make bottom reg higher than top reg */ - mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg, - 0xfff); - mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0); - mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0); - } -} - -/* - * gt64260_disable_all_windows() - * - * The GT64260 has several windows that aren't represented in the table of - * windows at the top of this file. This routine turns all of them off - * except for the memory controller windows, of course. - */ -static void __init -gt64260_disable_all_windows(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si) -{ - u32 i, preserve; - - /* Disable 32bit windows (don't disable cpu->mem windows) */ - for (i=MV64x60_CPU2DEV_0_WIN; iwindow_preserve_mask_32_lo & (1 << i); - else - preserve = si->window_preserve_mask_32_hi & (1<<(i-32)); - - if (!preserve) - gt64260_disable_window_32bit(bh, i); - } - - /* Disable 64bit windows */ - for (i=0; iwindow_preserve_mask_64 & (1<MEM access cntl wins not in gt64260_64bit_windows[] */ - mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff); - mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0); - mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0); - mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff); - mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0); - mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0); - mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff); - mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0); - mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0); - mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff); - mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0); - mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0); - - mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff); - mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0); - mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0); - mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff); - mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0); - mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0); - mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff); - mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0); - mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0); - mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff); - mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0); - mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0); - - /* Disable all PCI-> windows */ - mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07fffdff); - mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07fffdff); - - /* - * Some firmwares enable a bunch of intr sources - * for the PCI INT output pins. - */ - mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_LO, 0); - mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_HI, 0); - mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_LO, 0); - mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_HI, 0); - mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_LO, 0); - mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_HI, 0); - mv64x60_write(bh, GT64260_IC_CPU_INT_0_MASK, 0); - mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0); - mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0); - mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0); -} - -/* - * gt64260a_chip_specific_init() - * - * Implement errata workarounds for the GT64260A. - */ -static void __init -gt64260a_chip_specific_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si) -{ -#ifdef CONFIG_SERIAL_MPSC - struct resource *r; -#endif -#if !defined(CONFIG_NOT_COHERENT_CACHE) - u32 val; - u8 save_exclude; -#endif - - if (si->pci_0.enable_bus) - mv64x60_set_bits(bh, MV64x60_PCI0_CMD, - ((1<<4) | (1<<5) | (1<<9) | (1<<13))); - - if (si->pci_1.enable_bus) - mv64x60_set_bits(bh, MV64x60_PCI1_CMD, - ((1<<4) | (1<<5) | (1<<9) | (1<<13))); - - /* - * Dave Wilhardt found that bit 4 in the PCI Command registers must - * be set if you are using cache coherency. - */ -#if !defined(CONFIG_NOT_COHERENT_CACHE) - /* Res #MEM-4 -- cpu read buffer to buffer 1 */ - if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40) - mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26)); - - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - if (si->pci_0.enable_bus) { - early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0), - PCI_COMMAND, &val); - val |= PCI_COMMAND_INVALIDATE; - early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0), - PCI_COMMAND, val); - } - - if (si->pci_1.enable_bus) { - early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0), - PCI_COMMAND, &val); - val |= PCI_COMMAND_INVALIDATE; - early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0), - PCI_COMMAND, val); - } - mv64x60_pci_exclude_bridge = save_exclude; -#endif - - /* Disable buffer/descriptor snooping */ - mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30)); - mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30)); - -#ifdef CONFIG_SERIAL_MPSC - mv64x60_mpsc0_pdata.mirror_regs = 1; - mv64x60_mpsc0_pdata.cache_mgmt = 1; - mv64x60_mpsc1_pdata.mirror_regs = 1; - mv64x60_mpsc1_pdata.cache_mgmt = 1; - - if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0)) - != NULL) { - r->start = MV64x60_IRQ_SDMA_0; - r->end = MV64x60_IRQ_SDMA_0; - } -#endif -} - -/* - * gt64260b_chip_specific_init() - * - * Implement errata workarounds for the GT64260B. - */ -static void __init -gt64260b_chip_specific_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si) -{ -#ifdef CONFIG_SERIAL_MPSC - struct resource *r; -#endif -#if !defined(CONFIG_NOT_COHERENT_CACHE) - u32 val; - u8 save_exclude; -#endif - - if (si->pci_0.enable_bus) - mv64x60_set_bits(bh, MV64x60_PCI0_CMD, - ((1<<4) | (1<<5) | (1<<9) | (1<<13))); - - if (si->pci_1.enable_bus) - mv64x60_set_bits(bh, MV64x60_PCI1_CMD, - ((1<<4) | (1<<5) | (1<<9) | (1<<13))); - - /* - * Dave Wilhardt found that bit 4 in the PCI Command registers must - * be set if you are using cache coherency. - */ -#if !defined(CONFIG_NOT_COHERENT_CACHE) - mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf); - - /* Res #MEM-4 -- cpu read buffer to buffer 1 */ - if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40) - mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26)); - - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - if (si->pci_0.enable_bus) { - early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0), - PCI_COMMAND, &val); - val |= PCI_COMMAND_INVALIDATE; - early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0), - PCI_COMMAND, val); - } - - if (si->pci_1.enable_bus) { - early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0), - PCI_COMMAND, &val); - val |= PCI_COMMAND_INVALIDATE; - early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0), - PCI_COMMAND, val); - } - mv64x60_pci_exclude_bridge = save_exclude; -#endif - - /* Disable buffer/descriptor snooping */ - mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30)); - mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30)); - -#ifdef CONFIG_SERIAL_MPSC - /* - * The 64260B is not supposed to have the bug where the MPSC & ENET - * can't access cache coherent regions. However, testing has shown - * that the MPSC, at least, still has this bug. - */ - mv64x60_mpsc0_pdata.cache_mgmt = 1; - mv64x60_mpsc1_pdata.cache_mgmt = 1; - - if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0)) - != NULL) { - r->start = MV64x60_IRQ_SDMA_0; - r->end = MV64x60_IRQ_SDMA_0; - } -#endif -} - -/* - ***************************************************************************** - * - * MV64360-Specific Routines - * - ***************************************************************************** - */ -/* - * mv64360_translate_size() - * - * On the MV64360, the size register is set similar to the size you get - * from a pci config space BAR register. That is, programmed from LSB to MSB - * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the - * assumption that the size is a power of 2. - */ -static u32 __init -mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits) -{ - return mv64x60_mask(size - 1, num_bits); -} - -/* - * mv64360_untranslate_size() - * - * Translate the size register value of a window into a window size. - */ -static u32 __init -mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits) -{ - if (size > 0) { - size >>= (32 - num_bits); - size++; - size <<= (32 - num_bits); - } - - return size; -} - -/* - * mv64360_set_pci2mem_window() - * - * The PCI->MEM window registers are actually in PCI config space so need - * to set them by setting the correct config space BARs. - */ -struct { - u32 fcn; - u32 base_hi_bar; - u32 base_lo_bar; -} static mv64360_reg_addrs[2][4] __initdata = { - {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 }, - { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }}, - {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 }, - { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }} -}; - -static void __init -mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window, - u32 base) -{ - u8 save_exclude; - - pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window, - hose->index, base); - - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - early_write_config_dword(hose, 0, - PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn), - mv64360_reg_addrs[bus][window].base_hi_bar, 0); - early_write_config_dword(hose, 0, - PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn), - mv64360_reg_addrs[bus][window].base_lo_bar, - mv64x60_mask(base,20) | 0xc); - mv64x60_pci_exclude_bridge = save_exclude; -} - -/* - * mv64360_set_pci2regs_window() - * - * Set where the bridge's registers appear in PCI MEM space. - */ -static u32 mv64360_offset[2][2] __initdata = {{0x20, 0x24}, {0xa0, 0xa4}}; - -static void __init -mv64360_set_pci2regs_window(struct mv64x60_handle *bh, - struct pci_controller *hose, u32 bus, u32 base) -{ - u8 save_exclude; - - pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index, - base); - - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - early_write_config_dword(hose, 0, PCI_DEVFN(0,0), - mv64360_offset[bus][0], (base << 16)); - early_write_config_dword(hose, 0, PCI_DEVFN(0,0), - mv64360_offset[bus][1], 0); - mv64x60_pci_exclude_bridge = save_exclude; -} - -/* - * mv64360_is_enabled_32bit() - * - * On a MV64360, a window is enabled by either clearing a bit in the - * CPU BAR Enable reg or setting a bit in the window's base reg. - * Note that this doesn't work for windows on the PCI slave side but we don't - * check those so its okay. - */ -static u32 __init -mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window) -{ - u32 extra, rc = 0; - - if (((mv64360_32bit_windows[window].base_reg != 0) && - (mv64360_32bit_windows[window].size_reg != 0)) || - (window == MV64x60_CPU2SRAM_WIN)) { - - extra = mv64360_32bit_windows[window].extra; - - switch (extra & MV64x60_EXTRA_MASK) { - case MV64x60_EXTRA_CPUWIN_ENAB: - rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) & - (1 << (extra & 0x1f))) == 0; - break; - - case MV64x60_EXTRA_CPUPROT_ENAB: - rc = (mv64x60_read(bh, - mv64360_32bit_windows[window].base_reg) & - (1 << (extra & 0x1f))) != 0; - break; - - case MV64x60_EXTRA_ENET_ENAB: - rc = (mv64x60_read(bh, MV64360_ENET2MEM_BAR_ENABLE) & - (1 << (extra & 0x7))) == 0; - break; - - case MV64x60_EXTRA_MPSC_ENAB: - rc = (mv64x60_read(bh, MV64360_MPSC2MEM_BAR_ENABLE) & - (1 << (extra & 0x3))) == 0; - break; - - case MV64x60_EXTRA_IDMA_ENAB: - rc = (mv64x60_read(bh, MV64360_IDMA2MEM_BAR_ENABLE) & - (1 << (extra & 0x7))) == 0; - break; - - default: - printk(KERN_ERR "mv64360_is_enabled: %s\n", - "32bit table corrupted"); - } - } - - return rc; -} - -/* - * mv64360_enable_window_32bit() - * - * On a MV64360, a window is enabled by either clearing a bit in the - * CPU BAR Enable reg or setting a bit in the window's base reg. - */ -static void __init -mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window) -{ - u32 extra; - - pr_debug("enable 32bit window: %d\n", window); - - if (((mv64360_32bit_windows[window].base_reg != 0) && - (mv64360_32bit_windows[window].size_reg != 0)) || - (window == MV64x60_CPU2SRAM_WIN)) { - - extra = mv64360_32bit_windows[window].extra; - - switch (extra & MV64x60_EXTRA_MASK) { - case MV64x60_EXTRA_CPUWIN_ENAB: - mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE, - (1 << (extra & 0x1f))); - break; - - case MV64x60_EXTRA_CPUPROT_ENAB: - mv64x60_set_bits(bh, - mv64360_32bit_windows[window].base_reg, - (1 << (extra & 0x1f))); - break; - - case MV64x60_EXTRA_ENET_ENAB: - mv64x60_clr_bits(bh, MV64360_ENET2MEM_BAR_ENABLE, - (1 << (extra & 0x7))); - break; - - case MV64x60_EXTRA_MPSC_ENAB: - mv64x60_clr_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE, - (1 << (extra & 0x3))); - break; - - case MV64x60_EXTRA_IDMA_ENAB: - mv64x60_clr_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE, - (1 << (extra & 0x7))); - break; - - default: - printk(KERN_ERR "mv64360_enable: %s\n", - "32bit table corrupted"); - } - } -} - -/* - * mv64360_disable_window_32bit() - * - * On a MV64360, a window is disabled by either setting a bit in the - * CPU BAR Enable reg or clearing a bit in the window's base reg. - */ -static void __init -mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window) -{ - u32 extra; - - pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n", - window, mv64360_32bit_windows[window].base_reg, - mv64360_32bit_windows[window].size_reg); - - if (((mv64360_32bit_windows[window].base_reg != 0) && - (mv64360_32bit_windows[window].size_reg != 0)) || - (window == MV64x60_CPU2SRAM_WIN)) { - - extra = mv64360_32bit_windows[window].extra; - - switch (extra & MV64x60_EXTRA_MASK) { - case MV64x60_EXTRA_CPUWIN_ENAB: - mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE, - (1 << (extra & 0x1f))); - break; - - case MV64x60_EXTRA_CPUPROT_ENAB: - mv64x60_clr_bits(bh, - mv64360_32bit_windows[window].base_reg, - (1 << (extra & 0x1f))); - break; - - case MV64x60_EXTRA_ENET_ENAB: - mv64x60_set_bits(bh, MV64360_ENET2MEM_BAR_ENABLE, - (1 << (extra & 0x7))); - break; - - case MV64x60_EXTRA_MPSC_ENAB: - mv64x60_set_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE, - (1 << (extra & 0x3))); - break; - - case MV64x60_EXTRA_IDMA_ENAB: - mv64x60_set_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE, - (1 << (extra & 0x7))); - break; - - default: - printk(KERN_ERR "mv64360_disable: %s\n", - "32bit table corrupted"); - } - } -} - -/* - * mv64360_enable_window_64bit() - * - * On the MV64360, a 64-bit window is enabled by setting a bit in the window's - * base reg. - */ -static void __init -mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window) -{ - pr_debug("enable 64bit window: %d\n", window); - - if ((mv64360_64bit_windows[window].base_lo_reg!= 0) && - (mv64360_64bit_windows[window].size_reg != 0)) { - - if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK) - == MV64x60_EXTRA_PCIACC_ENAB) - mv64x60_set_bits(bh, - mv64360_64bit_windows[window].base_lo_reg, - (1 << (mv64360_64bit_windows[window].extra & - 0x1f))); - else - printk(KERN_ERR "mv64360_enable: %s\n", - "64bit table corrupted"); - } -} - -/* - * mv64360_disable_window_64bit() - * - * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's - * base reg. - */ -static void __init -mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window) -{ - pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n", - window, mv64360_64bit_windows[window].base_lo_reg, - mv64360_64bit_windows[window].size_reg); - - if ((mv64360_64bit_windows[window].base_lo_reg != 0) && - (mv64360_64bit_windows[window].size_reg != 0)) { - if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK) - == MV64x60_EXTRA_PCIACC_ENAB) - mv64x60_clr_bits(bh, - mv64360_64bit_windows[window].base_lo_reg, - (1 << (mv64360_64bit_windows[window].extra & - 0x1f))); - else - printk(KERN_ERR "mv64360_disable: %s\n", - "64bit table corrupted"); - } -} - -/* - * mv64360_disable_all_windows() - * - * The MV64360 has a few windows that aren't represented in the table of - * windows at the top of this file. This routine turns all of them off - * except for the memory controller windows, of course. - */ -static void __init -mv64360_disable_all_windows(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si) -{ - u32 preserve, i; - - /* Disable 32bit windows (don't disable cpu->mem windows) */ - for (i=MV64x60_CPU2DEV_0_WIN; iwindow_preserve_mask_32_lo & (1 << i); - else - preserve = si->window_preserve_mask_32_hi & (1<<(i-32)); - - if (!preserve) - mv64360_disable_window_32bit(bh, i); - } - - /* Disable 64bit windows */ - for (i=0; iwindow_preserve_mask_64 & (1<MEM access cntl wins not in mv64360_64bit_windows[] */ - mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0); - mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0); - mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0); - mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0); - - /* Disable all PCI-> windows */ - mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff); - mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff); -} - -/* - * mv64360_config_io2mem_windows() - * - * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that - * must be set up so that the respective ctlr can access system memory. - */ -static u32 enet_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = { - MV64x60_ENET2MEM_0_WIN, MV64x60_ENET2MEM_1_WIN, - MV64x60_ENET2MEM_2_WIN, MV64x60_ENET2MEM_3_WIN, -}; - -static u32 mpsc_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = { - MV64x60_MPSC2MEM_0_WIN, MV64x60_MPSC2MEM_1_WIN, - MV64x60_MPSC2MEM_2_WIN, MV64x60_MPSC2MEM_3_WIN, -}; - -static u32 idma_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = { - MV64x60_IDMA2MEM_0_WIN, MV64x60_IDMA2MEM_1_WIN, - MV64x60_IDMA2MEM_2_WIN, MV64x60_IDMA2MEM_3_WIN, -}; - -static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] __initdata = - { 0xe, 0xd, 0xb, 0x7 }; - -static void __init -mv64360_config_io2mem_windows(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) -{ - u32 i, win; - - pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n"); - - mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_0, 0); - mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_1, 0); - mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_2, 0); - - mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_0, 0); - mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_1, 0); - - mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_0, 0); - mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_1, 0); - mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_2, 0); - mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_3, 0); - - /* Assume that mem ctlr has no more windows than embedded I/O ctlr */ - for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++) - if (bh->ci->is_enabled_32bit(bh, win)) { - mv64x60_set_32bit_window(bh, enet_tab[i], - mem_windows[i][0], mem_windows[i][1], - (dram_selects[i] << 8) | - (si->enet_options[i] & 0x3000)); - bh->ci->enable_window_32bit(bh, enet_tab[i]); - - /* Give enet r/w access to memory region */ - mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_0, - (0x3 << (i << 1))); - mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_1, - (0x3 << (i << 1))); - mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_2, - (0x3 << (i << 1))); - - mv64x60_set_32bit_window(bh, mpsc_tab[i], - mem_windows[i][0], mem_windows[i][1], - (dram_selects[i] << 8) | - (si->mpsc_options[i] & 0x3000)); - bh->ci->enable_window_32bit(bh, mpsc_tab[i]); - - /* Give mpsc r/w access to memory region */ - mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_0, - (0x3 << (i << 1))); - mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_1, - (0x3 << (i << 1))); - - mv64x60_set_32bit_window(bh, idma_tab[i], - mem_windows[i][0], mem_windows[i][1], - (dram_selects[i] << 8) | - (si->idma_options[i] & 0x3000)); - bh->ci->enable_window_32bit(bh, idma_tab[i]); - - /* Give idma r/w access to memory region */ - mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_0, - (0x3 << (i << 1))); - mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_1, - (0x3 << (i << 1))); - mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_2, - (0x3 << (i << 1))); - mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3, - (0x3 << (i << 1))); - } -} - -/* - * mv64360_set_mpsc2regs_window() - * - * MPSC has a window to the bridge's internal registers. Call this routine - * to change that window so it doesn't conflict with the windows mapping the - * mpsc to system memory. - */ -static void __init -mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base) -{ - pr_debug("set mpsc->internal regs, base: 0x%x\n", base); - mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000); -} - -/* - * mv64360_chip_specific_init() - * - * Implement errata workarounds for the MV64360. - */ -static void __init -mv64360_chip_specific_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si) -{ -#if !defined(CONFIG_NOT_COHERENT_CACHE) - mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24)); -#endif -#ifdef CONFIG_SERIAL_MPSC - mv64x60_mpsc0_pdata.brg_can_tune = 1; - mv64x60_mpsc0_pdata.cache_mgmt = 1; - mv64x60_mpsc1_pdata.brg_can_tune = 1; - mv64x60_mpsc1_pdata.cache_mgmt = 1; -#endif -} - -/* - * mv64460_chip_specific_init() - * - * Implement errata workarounds for the MV64460. - */ -static void __init -mv64460_chip_specific_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si) -{ -#if !defined(CONFIG_NOT_COHERENT_CACHE) - mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24) | (1<<25)); - mv64x60_set_bits(bh, MV64460_D_UNIT_MMASK, (1<<1) | (1<<4)); -#endif -#ifdef CONFIG_SERIAL_MPSC - mv64x60_mpsc0_pdata.brg_can_tune = 1; - mv64x60_mpsc0_pdata.cache_mgmt = 1; - mv64x60_mpsc1_pdata.brg_can_tune = 1; - mv64x60_mpsc1_pdata.cache_mgmt = 1; -#endif -} - - -#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) -/* Export the hotswap register via sysfs for enum event monitoring */ -#define VAL_LEN_MAX 11 /* 32-bit hex or dec stringified number + '\n' */ - -static DEFINE_MUTEX(mv64xxx_hs_lock); - -static ssize_t -mv64xxx_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, size_t count) -{ - u32 v; - u8 save_exclude; - - if (off > 0) - return 0; - if (count < VAL_LEN_MAX) - return -EINVAL; - - if (mutex_lock_interruptible(&mv64xxx_hs_lock)) - return -ERESTARTSYS; - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - early_read_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0), - MV64360_PCICFG_CPCI_HOTSWAP, &v); - mv64x60_pci_exclude_bridge = save_exclude; - mutex_unlock(&mv64xxx_hs_lock); - - return sprintf(buf, "0x%08x\n", v); -} - -static ssize_t -mv64xxx_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, size_t count) -{ - u32 v; - u8 save_exclude; - - if (off > 0) - return 0; - if (count <= 0) - return -EINVAL; - - if (sscanf(buf, "%i", &v) == 1) { - if (mutex_lock_interruptible(&mv64xxx_hs_lock)) - return -ERESTARTSYS; - save_exclude = mv64x60_pci_exclude_bridge; - mv64x60_pci_exclude_bridge = 0; - early_write_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0), - MV64360_PCICFG_CPCI_HOTSWAP, v); - mv64x60_pci_exclude_bridge = save_exclude; - mutex_unlock(&mv64xxx_hs_lock); - } - else - count = -EINVAL; - - return count; -} - -static struct bin_attribute mv64xxx_hs_reg_attr = { /* Hotswap register */ - .attr = { - .name = "hs_reg", - .mode = S_IRUGO | S_IWUSR, - }, - .size = VAL_LEN_MAX, - .read = mv64xxx_hs_reg_read, - .write = mv64xxx_hs_reg_write, -}; - -/* Provide sysfs file indicating if this platform supports the hs_reg */ -static ssize_t -mv64xxx_hs_reg_valid_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct platform_device *pdev; - struct mv64xxx_pdata *pdp; - u32 v; - - pdev = container_of(dev, struct platform_device, dev); - pdp = (struct mv64xxx_pdata *)pdev->dev.platform_data; - - if (mutex_lock_interruptible(&mv64xxx_hs_lock)) - return -ERESTARTSYS; - v = pdp->hs_reg_valid; - mutex_unlock(&mv64xxx_hs_lock); - - return sprintf(buf, "%i\n", v); -} -static DEVICE_ATTR(hs_reg_valid, S_IRUGO, mv64xxx_hs_reg_valid_show, NULL); - -static int __init -mv64xxx_sysfs_init(void) -{ - sysfs_create_bin_file(&mv64xxx_device.dev.kobj, &mv64xxx_hs_reg_attr); - sysfs_create_file(&mv64xxx_device.dev.kobj,&dev_attr_hs_reg_valid.attr); - return 0; -} -subsys_initcall(mv64xxx_sysfs_init); -#endif diff --git a/arch/ppc/syslib/mv64x60_dbg.c b/arch/ppc/syslib/mv64x60_dbg.c deleted file mode 100644 index e1876261e5dc..000000000000 --- a/arch/ppc/syslib/mv64x60_dbg.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * KGDB and progress routines for the Marvell/Galileo MV64x60 (Discovery). - * - * Author: Mark A. Greer - * - * 2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - ***************************************************************************** - * - * Low-level MPSC/UART I/O routines - * - ***************************************************************************** - */ - - -#include -#include -#include -#include - - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) - -#define MPSC_CHR_1 0x000c -#define MPSC_CHR_2 0x0010 - -static struct mv64x60_handle mv64x60_dbg_bh; - -void -mv64x60_progress_init(u32 base) -{ - mv64x60_dbg_bh.v_base = base; - return; -} - -static void -mv64x60_polled_putc(int chan, char c) -{ - u32 offset; - - if (chan == 0) - offset = 0x8000; - else - offset = 0x9000; - - mv64x60_write(&mv64x60_dbg_bh, offset + MPSC_CHR_1, (u32)c); - mv64x60_write(&mv64x60_dbg_bh, offset + MPSC_CHR_2, 0x200); - udelay(2000); -} - -void -mv64x60_mpsc_progress(char *s, unsigned short hex) -{ - volatile char c; - - mv64x60_polled_putc(0, '\r'); - - while ((c = *s++) != 0) - mv64x60_polled_putc(0, c); - - mv64x60_polled_putc(0, '\n'); - mv64x60_polled_putc(0, '\r'); - - return; -} -#endif /* CONFIG_SERIAL_TEXT_DEBUG */ - - -#if defined(CONFIG_KGDB) - -#if defined(CONFIG_KGDB_TTYS0) -#define KGDB_PORT 0 -#elif defined(CONFIG_KGDB_TTYS1) -#define KGDB_PORT 1 -#else -#error "Invalid kgdb_tty port" -#endif - -void -putDebugChar(unsigned char c) -{ - mv64x60_polled_putc(KGDB_PORT, (char)c); -} - -int -getDebugChar(void) -{ - unsigned char c; - - while (!mv64x60_polled_getc(KGDB_PORT, &c)); - return (int)c; -} - -void -putDebugString(char* str) -{ - while (*str != '\0') { - putDebugChar(*str); - str++; - } - putDebugChar('\r'); - return; -} - -void -kgdb_interruptible(int enable) -{ -} - -void -kgdb_map_scc(void) -{ - if (ppc_md.early_serial_map) - ppc_md.early_serial_map(); -} -#endif /* CONFIG_KGDB */ diff --git a/arch/ppc/syslib/mv64x60_win.c b/arch/ppc/syslib/mv64x60_win.c deleted file mode 100644 index 4bf1ad17bf1a..000000000000 --- a/arch/ppc/syslib/mv64x60_win.c +++ /dev/null @@ -1,1165 +0,0 @@ -/* - * Tables with info on how to manipulate the 32 & 64 bit windows on the - * various types of Marvell bridge chips. - * - * Author: Mark A. Greer - * - * 2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -/* - ***************************************************************************** - * - * Tables describing how to set up windows on each type of bridge - * - ***************************************************************************** - */ -struct mv64x60_32bit_window - gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT] __initdata = { - /* CPU->MEM Windows */ - [MV64x60_CPU2MEM_0_WIN] = { - .base_reg = MV64x60_CPU2MEM_0_BASE, - .size_reg = MV64x60_CPU2MEM_0_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2MEM_1_WIN] = { - .base_reg = MV64x60_CPU2MEM_1_BASE, - .size_reg = MV64x60_CPU2MEM_1_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2MEM_2_WIN] = { - .base_reg = MV64x60_CPU2MEM_2_BASE, - .size_reg = MV64x60_CPU2MEM_2_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2MEM_3_WIN] = { - .base_reg = MV64x60_CPU2MEM_3_BASE, - .size_reg = MV64x60_CPU2MEM_3_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU->Device Windows */ - [MV64x60_CPU2DEV_0_WIN] = { - .base_reg = MV64x60_CPU2DEV_0_BASE, - .size_reg = MV64x60_CPU2DEV_0_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2DEV_1_WIN] = { - .base_reg = MV64x60_CPU2DEV_1_BASE, - .size_reg = MV64x60_CPU2DEV_1_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2DEV_2_WIN] = { - .base_reg = MV64x60_CPU2DEV_2_BASE, - .size_reg = MV64x60_CPU2DEV_2_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2DEV_3_WIN] = { - .base_reg = MV64x60_CPU2DEV_3_BASE, - .size_reg = MV64x60_CPU2DEV_3_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU->Boot Window */ - [MV64x60_CPU2BOOT_WIN] = { - .base_reg = MV64x60_CPU2BOOT_0_BASE, - .size_reg = MV64x60_CPU2BOOT_0_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU->PCI 0 Windows */ - [MV64x60_CPU2PCI0_IO_WIN] = { - .base_reg = MV64x60_CPU2PCI0_IO_BASE, - .size_reg = MV64x60_CPU2PCI0_IO_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_0_WIN] = { - .base_reg = MV64x60_CPU2PCI0_MEM_0_BASE, - .size_reg = MV64x60_CPU2PCI0_MEM_0_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_1_WIN] = { - .base_reg = MV64x60_CPU2PCI0_MEM_1_BASE, - .size_reg = MV64x60_CPU2PCI0_MEM_1_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_2_WIN] = { - .base_reg = MV64x60_CPU2PCI0_MEM_2_BASE, - .size_reg = MV64x60_CPU2PCI0_MEM_2_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_3_WIN] = { - .base_reg = MV64x60_CPU2PCI0_MEM_3_BASE, - .size_reg = MV64x60_CPU2PCI0_MEM_3_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU->PCI 1 Windows */ - [MV64x60_CPU2PCI1_IO_WIN] = { - .base_reg = MV64x60_CPU2PCI1_IO_BASE, - .size_reg = MV64x60_CPU2PCI1_IO_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_0_WIN] = { - .base_reg = MV64x60_CPU2PCI1_MEM_0_BASE, - .size_reg = MV64x60_CPU2PCI1_MEM_0_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_1_WIN] = { - .base_reg = MV64x60_CPU2PCI1_MEM_1_BASE, - .size_reg = MV64x60_CPU2PCI1_MEM_1_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_2_WIN] = { - .base_reg = MV64x60_CPU2PCI1_MEM_2_BASE, - .size_reg = MV64x60_CPU2PCI1_MEM_2_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_3_WIN] = { - .base_reg = MV64x60_CPU2PCI1_MEM_3_BASE, - .size_reg = MV64x60_CPU2PCI1_MEM_3_SIZE, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU->SRAM Window (64260 has no integrated SRAM) */ - /* CPU->PCI 0 Remap I/O Window */ - [MV64x60_CPU2PCI0_IO_REMAP_WIN] = { - .base_reg = MV64x60_CPU2PCI0_IO_REMAP, - .size_reg = 0, - .base_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU->PCI 1 Remap I/O Window */ - [MV64x60_CPU2PCI1_IO_REMAP_WIN] = { - .base_reg = MV64x60_CPU2PCI1_IO_REMAP, - .size_reg = 0, - .base_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU Memory Protection Windows */ - [MV64x60_CPU_PROT_0_WIN] = { - .base_reg = MV64x60_CPU_PROT_BASE_0, - .size_reg = MV64x60_CPU_PROT_SIZE_0, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU_PROT_1_WIN] = { - .base_reg = MV64x60_CPU_PROT_BASE_1, - .size_reg = MV64x60_CPU_PROT_SIZE_1, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU_PROT_2_WIN] = { - .base_reg = MV64x60_CPU_PROT_BASE_2, - .size_reg = MV64x60_CPU_PROT_SIZE_2, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU_PROT_3_WIN] = { - .base_reg = MV64x60_CPU_PROT_BASE_3, - .size_reg = MV64x60_CPU_PROT_SIZE_3, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU Snoop Windows */ - [MV64x60_CPU_SNOOP_0_WIN] = { - .base_reg = GT64260_CPU_SNOOP_BASE_0, - .size_reg = GT64260_CPU_SNOOP_SIZE_0, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU_SNOOP_1_WIN] = { - .base_reg = GT64260_CPU_SNOOP_BASE_1, - .size_reg = GT64260_CPU_SNOOP_SIZE_1, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU_SNOOP_2_WIN] = { - .base_reg = GT64260_CPU_SNOOP_BASE_2, - .size_reg = GT64260_CPU_SNOOP_SIZE_2, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU_SNOOP_3_WIN] = { - .base_reg = GT64260_CPU_SNOOP_BASE_3, - .size_reg = GT64260_CPU_SNOOP_SIZE_3, - .base_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* PCI 0->System Memory Remap Windows */ - [MV64x60_PCI02MEM_REMAP_0_WIN] = { - .base_reg = MV64x60_PCI0_SLAVE_MEM_0_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI02MEM_REMAP_1_WIN] = { - .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI02MEM_REMAP_2_WIN] = { - .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI02MEM_REMAP_3_WIN] = { - .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - /* PCI 1->System Memory Remap Windows */ - [MV64x60_PCI12MEM_REMAP_0_WIN] = { - .base_reg = MV64x60_PCI1_SLAVE_MEM_0_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI12MEM_REMAP_1_WIN] = { - .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI12MEM_REMAP_2_WIN] = { - .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI12MEM_REMAP_3_WIN] = { - .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - /* ENET->SRAM Window (64260 doesn't have separate windows) */ - /* MPSC->SRAM Window (64260 doesn't have separate windows) */ - /* IDMA->SRAM Window (64260 doesn't have separate windows) */ -}; - -struct mv64x60_64bit_window - gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT] __initdata = { - /* CPU->PCI 0 MEM Remap Windows */ - [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU->PCI 1 MEM Remap Windows */ - [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 12, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* PCI 0->MEM Access Control Windows */ - [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = { - .base_hi_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_HI, - .base_lo_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_LO, - .size_reg = MV64x60_PCI0_ACC_CNTL_0_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = { - .base_hi_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_HI, - .base_lo_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_LO, - .size_reg = MV64x60_PCI0_ACC_CNTL_1_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = { - .base_hi_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_HI, - .base_lo_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_LO, - .size_reg = MV64x60_PCI0_ACC_CNTL_2_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = { - .base_hi_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_HI, - .base_lo_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_LO, - .size_reg = MV64x60_PCI0_ACC_CNTL_3_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* PCI 1->MEM Access Control Windows */ - [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = { - .base_hi_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_HI, - .base_lo_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_LO, - .size_reg = MV64x60_PCI1_ACC_CNTL_0_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = { - .base_hi_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_HI, - .base_lo_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_LO, - .size_reg = MV64x60_PCI1_ACC_CNTL_1_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = { - .base_hi_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_HI, - .base_lo_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_LO, - .size_reg = MV64x60_PCI1_ACC_CNTL_2_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = { - .base_hi_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_HI, - .base_lo_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_LO, - .size_reg = MV64x60_PCI1_ACC_CNTL_3_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* PCI 0->MEM Snoop Windows */ - [MV64x60_PCI02MEM_SNOOP_0_WIN] = { - .base_hi_reg = GT64260_PCI0_SNOOP_0_BASE_HI, - .base_lo_reg = GT64260_PCI0_SNOOP_0_BASE_LO, - .size_reg = GT64260_PCI0_SNOOP_0_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI02MEM_SNOOP_1_WIN] = { - .base_hi_reg = GT64260_PCI0_SNOOP_1_BASE_HI, - .base_lo_reg = GT64260_PCI0_SNOOP_1_BASE_LO, - .size_reg = GT64260_PCI0_SNOOP_1_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI02MEM_SNOOP_2_WIN] = { - .base_hi_reg = GT64260_PCI0_SNOOP_2_BASE_HI, - .base_lo_reg = GT64260_PCI0_SNOOP_2_BASE_LO, - .size_reg = GT64260_PCI0_SNOOP_2_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI02MEM_SNOOP_3_WIN] = { - .base_hi_reg = GT64260_PCI0_SNOOP_3_BASE_HI, - .base_lo_reg = GT64260_PCI0_SNOOP_3_BASE_LO, - .size_reg = GT64260_PCI0_SNOOP_3_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* PCI 1->MEM Snoop Windows */ - [MV64x60_PCI12MEM_SNOOP_0_WIN] = { - .base_hi_reg = GT64260_PCI1_SNOOP_0_BASE_HI, - .base_lo_reg = GT64260_PCI1_SNOOP_0_BASE_LO, - .size_reg = GT64260_PCI1_SNOOP_0_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI12MEM_SNOOP_1_WIN] = { - .base_hi_reg = GT64260_PCI1_SNOOP_1_BASE_HI, - .base_lo_reg = GT64260_PCI1_SNOOP_1_BASE_LO, - .size_reg = GT64260_PCI1_SNOOP_1_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI12MEM_SNOOP_2_WIN] = { - .base_hi_reg = GT64260_PCI1_SNOOP_2_BASE_HI, - .base_lo_reg = GT64260_PCI1_SNOOP_2_BASE_LO, - .size_reg = GT64260_PCI1_SNOOP_2_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_PCI12MEM_SNOOP_3_WIN] = { - .base_hi_reg = GT64260_PCI1_SNOOP_3_BASE_HI, - .base_lo_reg = GT64260_PCI1_SNOOP_3_BASE_LO, - .size_reg = GT64260_PCI1_SNOOP_3_SIZE, - .base_lo_bits = 12, - .size_bits = 12, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, -}; - -struct mv64x60_32bit_window - mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT] __initdata = { - /* CPU->MEM Windows */ - [MV64x60_CPU2MEM_0_WIN] = { - .base_reg = MV64x60_CPU2MEM_0_BASE, - .size_reg = MV64x60_CPU2MEM_0_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 0 }, - [MV64x60_CPU2MEM_1_WIN] = { - .base_reg = MV64x60_CPU2MEM_1_BASE, - .size_reg = MV64x60_CPU2MEM_1_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 1 }, - [MV64x60_CPU2MEM_2_WIN] = { - .base_reg = MV64x60_CPU2MEM_2_BASE, - .size_reg = MV64x60_CPU2MEM_2_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 2 }, - [MV64x60_CPU2MEM_3_WIN] = { - .base_reg = MV64x60_CPU2MEM_3_BASE, - .size_reg = MV64x60_CPU2MEM_3_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 3 }, - /* CPU->Device Windows */ - [MV64x60_CPU2DEV_0_WIN] = { - .base_reg = MV64x60_CPU2DEV_0_BASE, - .size_reg = MV64x60_CPU2DEV_0_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 4 }, - [MV64x60_CPU2DEV_1_WIN] = { - .base_reg = MV64x60_CPU2DEV_1_BASE, - .size_reg = MV64x60_CPU2DEV_1_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 5 }, - [MV64x60_CPU2DEV_2_WIN] = { - .base_reg = MV64x60_CPU2DEV_2_BASE, - .size_reg = MV64x60_CPU2DEV_2_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 6 }, - [MV64x60_CPU2DEV_3_WIN] = { - .base_reg = MV64x60_CPU2DEV_3_BASE, - .size_reg = MV64x60_CPU2DEV_3_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 7 }, - /* CPU->Boot Window */ - [MV64x60_CPU2BOOT_WIN] = { - .base_reg = MV64x60_CPU2BOOT_0_BASE, - .size_reg = MV64x60_CPU2BOOT_0_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 8 }, - /* CPU->PCI 0 Windows */ - [MV64x60_CPU2PCI0_IO_WIN] = { - .base_reg = MV64x60_CPU2PCI0_IO_BASE, - .size_reg = MV64x60_CPU2PCI0_IO_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 9 }, - [MV64x60_CPU2PCI0_MEM_0_WIN] = { - .base_reg = MV64x60_CPU2PCI0_MEM_0_BASE, - .size_reg = MV64x60_CPU2PCI0_MEM_0_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 10 }, - [MV64x60_CPU2PCI0_MEM_1_WIN] = { - .base_reg = MV64x60_CPU2PCI0_MEM_1_BASE, - .size_reg = MV64x60_CPU2PCI0_MEM_1_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 11 }, - [MV64x60_CPU2PCI0_MEM_2_WIN] = { - .base_reg = MV64x60_CPU2PCI0_MEM_2_BASE, - .size_reg = MV64x60_CPU2PCI0_MEM_2_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 12 }, - [MV64x60_CPU2PCI0_MEM_3_WIN] = { - .base_reg = MV64x60_CPU2PCI0_MEM_3_BASE, - .size_reg = MV64x60_CPU2PCI0_MEM_3_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 13 }, - /* CPU->PCI 1 Windows */ - [MV64x60_CPU2PCI1_IO_WIN] = { - .base_reg = MV64x60_CPU2PCI1_IO_BASE, - .size_reg = MV64x60_CPU2PCI1_IO_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 14 }, - [MV64x60_CPU2PCI1_MEM_0_WIN] = { - .base_reg = MV64x60_CPU2PCI1_MEM_0_BASE, - .size_reg = MV64x60_CPU2PCI1_MEM_0_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 15 }, - [MV64x60_CPU2PCI1_MEM_1_WIN] = { - .base_reg = MV64x60_CPU2PCI1_MEM_1_BASE, - .size_reg = MV64x60_CPU2PCI1_MEM_1_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 16 }, - [MV64x60_CPU2PCI1_MEM_2_WIN] = { - .base_reg = MV64x60_CPU2PCI1_MEM_2_BASE, - .size_reg = MV64x60_CPU2PCI1_MEM_2_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 17 }, - [MV64x60_CPU2PCI1_MEM_3_WIN] = { - .base_reg = MV64x60_CPU2PCI1_MEM_3_BASE, - .size_reg = MV64x60_CPU2PCI1_MEM_3_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 18 }, - /* CPU->SRAM Window */ - [MV64x60_CPU2SRAM_WIN] = { - .base_reg = MV64360_CPU2SRAM_BASE, - .size_reg = 0, - .base_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUWIN_ENAB | 19 }, - /* CPU->PCI 0 Remap I/O Window */ - [MV64x60_CPU2PCI0_IO_REMAP_WIN] = { - .base_reg = MV64x60_CPU2PCI0_IO_REMAP, - .size_reg = 0, - .base_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU->PCI 1 Remap I/O Window */ - [MV64x60_CPU2PCI1_IO_REMAP_WIN] = { - .base_reg = MV64x60_CPU2PCI1_IO_REMAP, - .size_reg = 0, - .base_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU Memory Protection Windows */ - [MV64x60_CPU_PROT_0_WIN] = { - .base_reg = MV64x60_CPU_PROT_BASE_0, - .size_reg = MV64x60_CPU_PROT_SIZE_0, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 }, - [MV64x60_CPU_PROT_1_WIN] = { - .base_reg = MV64x60_CPU_PROT_BASE_1, - .size_reg = MV64x60_CPU_PROT_SIZE_1, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 }, - [MV64x60_CPU_PROT_2_WIN] = { - .base_reg = MV64x60_CPU_PROT_BASE_2, - .size_reg = MV64x60_CPU_PROT_SIZE_2, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 }, - [MV64x60_CPU_PROT_3_WIN] = { - .base_reg = MV64x60_CPU_PROT_BASE_3, - .size_reg = MV64x60_CPU_PROT_SIZE_3, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 }, - /* CPU Snoop Windows -- don't exist on 64360 */ - /* PCI 0->System Memory Remap Windows */ - [MV64x60_PCI02MEM_REMAP_0_WIN] = { - .base_reg = MV64x60_PCI0_SLAVE_MEM_0_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI02MEM_REMAP_1_WIN] = { - .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI02MEM_REMAP_2_WIN] = { - .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI02MEM_REMAP_3_WIN] = { - .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - /* PCI 1->System Memory Remap Windows */ - [MV64x60_PCI12MEM_REMAP_0_WIN] = { - .base_reg = MV64x60_PCI1_SLAVE_MEM_0_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI12MEM_REMAP_1_WIN] = { - .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI12MEM_REMAP_2_WIN] = { - .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - [MV64x60_PCI12MEM_REMAP_3_WIN] = { - .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, - .size_reg = 0, - .base_bits = 20, - .size_bits = 0, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = 0 }, - /* ENET->System Memory Windows */ - [MV64x60_ENET2MEM_0_WIN] = { - .base_reg = MV64360_ENET2MEM_0_BASE, - .size_reg = MV64360_ENET2MEM_0_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_ENET_ENAB | 0 }, - [MV64x60_ENET2MEM_1_WIN] = { - .base_reg = MV64360_ENET2MEM_1_BASE, - .size_reg = MV64360_ENET2MEM_1_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_ENET_ENAB | 1 }, - [MV64x60_ENET2MEM_2_WIN] = { - .base_reg = MV64360_ENET2MEM_2_BASE, - .size_reg = MV64360_ENET2MEM_2_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_ENET_ENAB | 2 }, - [MV64x60_ENET2MEM_3_WIN] = { - .base_reg = MV64360_ENET2MEM_3_BASE, - .size_reg = MV64360_ENET2MEM_3_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_ENET_ENAB | 3 }, - [MV64x60_ENET2MEM_4_WIN] = { - .base_reg = MV64360_ENET2MEM_4_BASE, - .size_reg = MV64360_ENET2MEM_4_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_ENET_ENAB | 4 }, - [MV64x60_ENET2MEM_5_WIN] = { - .base_reg = MV64360_ENET2MEM_5_BASE, - .size_reg = MV64360_ENET2MEM_5_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_ENET_ENAB | 5 }, - /* MPSC->System Memory Windows */ - [MV64x60_MPSC2MEM_0_WIN] = { - .base_reg = MV64360_MPSC2MEM_0_BASE, - .size_reg = MV64360_MPSC2MEM_0_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_MPSC_ENAB | 0 }, - [MV64x60_MPSC2MEM_1_WIN] = { - .base_reg = MV64360_MPSC2MEM_1_BASE, - .size_reg = MV64360_MPSC2MEM_1_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_MPSC_ENAB | 1 }, - [MV64x60_MPSC2MEM_2_WIN] = { - .base_reg = MV64360_MPSC2MEM_2_BASE, - .size_reg = MV64360_MPSC2MEM_2_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_MPSC_ENAB | 2 }, - [MV64x60_MPSC2MEM_3_WIN] = { - .base_reg = MV64360_MPSC2MEM_3_BASE, - .size_reg = MV64360_MPSC2MEM_3_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_MPSC_ENAB | 3 }, - /* IDMA->System Memory Windows */ - [MV64x60_IDMA2MEM_0_WIN] = { - .base_reg = MV64360_IDMA2MEM_0_BASE, - .size_reg = MV64360_IDMA2MEM_0_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_IDMA_ENAB | 0 }, - [MV64x60_IDMA2MEM_1_WIN] = { - .base_reg = MV64360_IDMA2MEM_1_BASE, - .size_reg = MV64360_IDMA2MEM_1_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_IDMA_ENAB | 1 }, - [MV64x60_IDMA2MEM_2_WIN] = { - .base_reg = MV64360_IDMA2MEM_2_BASE, - .size_reg = MV64360_IDMA2MEM_2_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_IDMA_ENAB | 2 }, - [MV64x60_IDMA2MEM_3_WIN] = { - .base_reg = MV64360_IDMA2MEM_3_BASE, - .size_reg = MV64360_IDMA2MEM_3_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_IDMA_ENAB | 3 }, - [MV64x60_IDMA2MEM_4_WIN] = { - .base_reg = MV64360_IDMA2MEM_4_BASE, - .size_reg = MV64360_IDMA2MEM_4_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_IDMA_ENAB | 4 }, - [MV64x60_IDMA2MEM_5_WIN] = { - .base_reg = MV64360_IDMA2MEM_5_BASE, - .size_reg = MV64360_IDMA2MEM_5_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_IDMA_ENAB | 5 }, - [MV64x60_IDMA2MEM_6_WIN] = { - .base_reg = MV64360_IDMA2MEM_6_BASE, - .size_reg = MV64360_IDMA2MEM_6_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_IDMA_ENAB | 6 }, - [MV64x60_IDMA2MEM_7_WIN] = { - .base_reg = MV64360_IDMA2MEM_7_BASE, - .size_reg = MV64360_IDMA2MEM_7_SIZE, - .base_bits = 16, - .size_bits = 16, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_IDMA_ENAB | 7 }, -}; - -struct mv64x60_64bit_window - mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT] __initdata = { - /* CPU->PCI 0 MEM Remap Windows */ - [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* CPU->PCI 1 MEM Remap Windows */ - [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = { - .base_hi_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_HI, - .base_lo_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_LO, - .size_reg = 0, - .base_lo_bits = 16, - .size_bits = 0, - .get_from_field = mv64x60_shift_left, - .map_to_field = mv64x60_shift_right, - .extra = 0 }, - /* PCI 0->MEM Access Control Windows */ - [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = { - .base_hi_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_HI, - .base_lo_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_LO, - .size_reg = MV64x60_PCI0_ACC_CNTL_0_SIZE, - .base_lo_bits = 20, - .size_bits = 20, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, - [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = { - .base_hi_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_HI, - .base_lo_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_LO, - .size_reg = MV64x60_PCI0_ACC_CNTL_1_SIZE, - .base_lo_bits = 20, - .size_bits = 20, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, - [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = { - .base_hi_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_HI, - .base_lo_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_LO, - .size_reg = MV64x60_PCI0_ACC_CNTL_2_SIZE, - .base_lo_bits = 20, - .size_bits = 20, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, - [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = { - .base_hi_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_HI, - .base_lo_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_LO, - .size_reg = MV64x60_PCI0_ACC_CNTL_3_SIZE, - .base_lo_bits = 20, - .size_bits = 20, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, - /* PCI 1->MEM Access Control Windows */ - [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = { - .base_hi_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_HI, - .base_lo_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_LO, - .size_reg = MV64x60_PCI1_ACC_CNTL_0_SIZE, - .base_lo_bits = 20, - .size_bits = 20, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, - [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = { - .base_hi_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_HI, - .base_lo_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_LO, - .size_reg = MV64x60_PCI1_ACC_CNTL_1_SIZE, - .base_lo_bits = 20, - .size_bits = 20, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, - [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = { - .base_hi_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_HI, - .base_lo_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_LO, - .size_reg = MV64x60_PCI1_ACC_CNTL_2_SIZE, - .base_lo_bits = 20, - .size_bits = 20, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, - [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = { - .base_hi_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_HI, - .base_lo_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_LO, - .size_reg = MV64x60_PCI1_ACC_CNTL_3_SIZE, - .base_lo_bits = 20, - .size_bits = 20, - .get_from_field = mv64x60_mask, - .map_to_field = mv64x60_mask, - .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, - /* PCI 0->MEM Snoop Windows -- don't exist on 64360 */ - /* PCI 1->MEM Snoop Windows -- don't exist on 64360 */ -}; diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c deleted file mode 100644 index a6fb7dcfa738..000000000000 --- a/arch/ppc/syslib/ocp.c +++ /dev/null @@ -1,482 +0,0 @@ -/* - * ocp.c - * - * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) - * Mipsys - France - * - * Derived from work (c) Armin Kuster akuster@pacbell.net - * - * Additional support and port to 2.6 LDM/sysfs by - * Matt Porter - * Copyright 2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * OCP (On Chip Peripheral) is a software emulated "bus" with a - * pseudo discovery method for dumb peripherals. Usually these type - * of peripherals are found on embedded SoC (System On a Chip) - * processors or highly integrated system controllers that have - * a host bridge and many peripherals. Common examples where - * this is already used include the PPC4xx, MPC52xx, - * and MV64xxx parts. - * - * This subsystem creates a standard OCP bus type within the - * device model. The devices on the OCP bus are seeded by an - * an initial OCP device array created by the arch-specific - * Device entries can be added/removed/modified through OCP - * helper functions to accommodate system and board-specific - * parameters commonly found in embedded systems. OCP also - * provides a standard method for devices to describe extended - * attributes about themselves to the system. A standard access - * method allows OCP drivers to obtain the information, both - * SoC-specific and system/board-specific, needed for operation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -//#define DBG(x) printk x -#define DBG(x) - -extern int mem_init_done; - -extern struct ocp_def core_ocp[]; /* Static list of devices, provided by - CPU core */ - -LIST_HEAD(ocp_devices); /* List of all OCP devices */ -DECLARE_RWSEM(ocp_devices_sem); /* Global semaphores for those lists */ - -static int ocp_inited; - -/* Sysfs support */ -#define OCP_DEF_ATTR(field, format_string) \ -static ssize_t \ -show_##field(struct device *dev, struct device_attribute *attr, char *buf) \ -{ \ - struct ocp_device *odev = to_ocp_dev(dev); \ - \ - return sprintf(buf, format_string, odev->def->field); \ -} \ -static DEVICE_ATTR(field, S_IRUGO, show_##field, NULL); - -OCP_DEF_ATTR(vendor, "0x%04x\n"); -OCP_DEF_ATTR(function, "0x%04x\n"); -OCP_DEF_ATTR(index, "0x%04x\n"); -#ifdef CONFIG_PTE_64BIT -OCP_DEF_ATTR(paddr, "0x%016Lx\n"); -#else -OCP_DEF_ATTR(paddr, "0x%08lx\n"); -#endif -OCP_DEF_ATTR(irq, "%d\n"); -OCP_DEF_ATTR(pm, "%lu\n"); - -void ocp_create_sysfs_dev_files(struct ocp_device *odev) -{ - struct device *dev = &odev->dev; - - /* Current OCP device def attributes */ - device_create_file(dev, &dev_attr_vendor); - device_create_file(dev, &dev_attr_function); - device_create_file(dev, &dev_attr_index); - device_create_file(dev, &dev_attr_paddr); - device_create_file(dev, &dev_attr_irq); - device_create_file(dev, &dev_attr_pm); - /* Current OCP device additions attributes */ - if (odev->def->additions && odev->def->show) - odev->def->show(dev); -} - -/** - * ocp_device_match - Match one driver to one device - * @drv: driver to match - * @dev: device to match - * - * This function returns 0 if the driver and device don't match - */ -static int -ocp_device_match(struct device *dev, struct device_driver *drv) -{ - struct ocp_device *ocp_dev = to_ocp_dev(dev); - struct ocp_driver *ocp_drv = to_ocp_drv(drv); - const struct ocp_device_id *ids = ocp_drv->id_table; - - if (!ids) - return 0; - - while (ids->vendor || ids->function) { - if ((ids->vendor == OCP_ANY_ID - || ids->vendor == ocp_dev->def->vendor) - && (ids->function == OCP_ANY_ID - || ids->function == ocp_dev->def->function)) - return 1; - ids++; - } - return 0; -} - -static int -ocp_device_probe(struct device *dev) -{ - int error = 0; - struct ocp_driver *drv; - struct ocp_device *ocp_dev; - - drv = to_ocp_drv(dev->driver); - ocp_dev = to_ocp_dev(dev); - - if (drv->probe) { - error = drv->probe(ocp_dev); - if (error >= 0) { - ocp_dev->driver = drv; - error = 0; - } - } - return error; -} - -static int -ocp_device_remove(struct device *dev) -{ - struct ocp_device *ocp_dev = to_ocp_dev(dev); - - if (ocp_dev->driver) { - if (ocp_dev->driver->remove) - ocp_dev->driver->remove(ocp_dev); - ocp_dev->driver = NULL; - } - return 0; -} - -static int -ocp_device_suspend(struct device *dev, pm_message_t state) -{ - struct ocp_device *ocp_dev = to_ocp_dev(dev); - struct ocp_driver *ocp_drv = to_ocp_drv(dev->driver); - - if (dev->driver && ocp_drv->suspend) - return ocp_drv->suspend(ocp_dev, state); - return 0; -} - -static int -ocp_device_resume(struct device *dev) -{ - struct ocp_device *ocp_dev = to_ocp_dev(dev); - struct ocp_driver *ocp_drv = to_ocp_drv(dev->driver); - - if (dev->driver && ocp_drv->resume) - return ocp_drv->resume(ocp_dev); - return 0; -} - -struct bus_type ocp_bus_type = { - .name = "ocp", - .match = ocp_device_match, - .probe = ocp_device_probe, - .remove = ocp_device_remove, - .suspend = ocp_device_suspend, - .resume = ocp_device_resume, -}; - -/** - * ocp_register_driver - Register an OCP driver - * @drv: pointer to statically defined ocp_driver structure - * - * The driver's probe() callback is called either recursively - * by this function or upon later call of ocp_driver_init - * - * NOTE: Detection of devices is a 2 pass step on this implementation, - * hotswap isn't supported. First, all OCP devices are put in the device - * list, _then_ all drivers are probed on each match. - */ -int -ocp_register_driver(struct ocp_driver *drv) -{ - /* initialize common driver fields */ - drv->driver.name = drv->name; - drv->driver.bus = &ocp_bus_type; - - /* register with core */ - return driver_register(&drv->driver); -} - -/** - * ocp_unregister_driver - Unregister an OCP driver - * @drv: pointer to statically defined ocp_driver structure - * - * The driver's remove() callback is called recursively - * by this function for any device already registered - */ -void -ocp_unregister_driver(struct ocp_driver *drv) -{ - DBG(("ocp: ocp_unregister_driver(%s)...\n", drv->name)); - - driver_unregister(&drv->driver); - - DBG(("ocp: ocp_unregister_driver(%s)... done.\n", drv->name)); -} - -/* Core of ocp_find_device(). Caller must hold ocp_devices_sem */ -static struct ocp_device * -__ocp_find_device(unsigned int vendor, unsigned int function, int index) -{ - struct list_head *entry; - struct ocp_device *dev, *found = NULL; - - DBG(("ocp: __ocp_find_device(vendor: %x, function: %x, index: %d)...\n", vendor, function, index)); - - list_for_each(entry, &ocp_devices) { - dev = list_entry(entry, struct ocp_device, link); - if (vendor != OCP_ANY_ID && vendor != dev->def->vendor) - continue; - if (function != OCP_ANY_ID && function != dev->def->function) - continue; - if (index != OCP_ANY_INDEX && index != dev->def->index) - continue; - found = dev; - break; - } - - DBG(("ocp: __ocp_find_device(vendor: %x, function: %x, index: %d)... done\n", vendor, function, index)); - - return found; -} - -/** - * ocp_find_device - Find a device by function & index - * @vendor: vendor ID of the device (or OCP_ANY_ID) - * @function: function code of the device (or OCP_ANY_ID) - * @idx: index of the device (or OCP_ANY_INDEX) - * - * This function allows a lookup of a given function by it's - * index, it's typically used to find the MAL or ZMII associated - * with an EMAC or similar horrors. - * You can pass vendor, though you usually want OCP_ANY_ID there... - */ -struct ocp_device * -ocp_find_device(unsigned int vendor, unsigned int function, int index) -{ - struct ocp_device *dev; - - down_read(&ocp_devices_sem); - dev = __ocp_find_device(vendor, function, index); - up_read(&ocp_devices_sem); - - return dev; -} - -/** - * ocp_get_one_device - Find a def by function & index - * @vendor: vendor ID of the device (or OCP_ANY_ID) - * @function: function code of the device (or OCP_ANY_ID) - * @idx: index of the device (or OCP_ANY_INDEX) - * - * This function allows a lookup of a given ocp_def by it's - * vendor, function, and index. The main purpose for is to - * allow modification of the def before binding to the driver - */ -struct ocp_def * -ocp_get_one_device(unsigned int vendor, unsigned int function, int index) -{ - struct ocp_device *dev; - struct ocp_def *found = NULL; - - DBG(("ocp: ocp_get_one_device(vendor: %x, function: %x, index: %d)...\n", - vendor, function, index)); - - dev = ocp_find_device(vendor, function, index); - - if (dev) - found = dev->def; - - DBG(("ocp: ocp_get_one_device(vendor: %x, function: %x, index: %d)... done.\n", - vendor, function, index)); - - return found; -} - -/** - * ocp_add_one_device - Add a device - * @def: static device definition structure - * - * This function adds a device definition to the - * device list. It may only be called before - * ocp_driver_init() and will return an error - * otherwise. - */ -int -ocp_add_one_device(struct ocp_def *def) -{ - struct ocp_device *dev; - - DBG(("ocp: ocp_add_one_device()...\n")); - - /* Can't be called after ocp driver init */ - if (ocp_inited) - return 1; - - if (mem_init_done) - dev = kmalloc(sizeof(*dev), GFP_KERNEL); - else - dev = alloc_bootmem(sizeof(*dev)); - - if (dev == NULL) - return 1; - memset(dev, 0, sizeof(*dev)); - dev->def = def; - dev->current_state = 4; - sprintf(dev->name, "OCP device %04x:%04x:%04x", - dev->def->vendor, dev->def->function, dev->def->index); - down_write(&ocp_devices_sem); - list_add_tail(&dev->link, &ocp_devices); - up_write(&ocp_devices_sem); - - DBG(("ocp: ocp_add_one_device()...done\n")); - - return 0; -} - -/** - * ocp_remove_one_device - Remove a device by function & index - * @vendor: vendor ID of the device (or OCP_ANY_ID) - * @function: function code of the device (or OCP_ANY_ID) - * @idx: index of the device (or OCP_ANY_INDEX) - * - * This function allows removal of a given function by its - * index. It may only be called before ocp_driver_init() - * and will return an error otherwise. - */ -int -ocp_remove_one_device(unsigned int vendor, unsigned int function, int index) -{ - struct ocp_device *dev; - - DBG(("ocp: ocp_remove_one_device(vendor: %x, function: %x, index: %d)...\n", vendor, function, index)); - - /* Can't be called after ocp driver init */ - if (ocp_inited) - return 1; - - down_write(&ocp_devices_sem); - dev = __ocp_find_device(vendor, function, index); - list_del(&dev->link); - up_write(&ocp_devices_sem); - - DBG(("ocp: ocp_remove_one_device(vendor: %x, function: %x, index: %d)... done.\n", vendor, function, index)); - - return 0; -} - -/** - * ocp_for_each_device - Iterate over OCP devices - * @callback: routine to execute for each ocp device. - * @arg: user data to be passed to callback routine. - * - * This routine holds the ocp_device semaphore, so the - * callback routine cannot modify the ocp_device list. - */ -void -ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg) -{ - struct list_head *entry; - - if (callback) { - down_read(&ocp_devices_sem); - list_for_each(entry, &ocp_devices) - callback(list_entry(entry, struct ocp_device, link), - arg); - up_read(&ocp_devices_sem); - } -} - -/** - * ocp_early_init - Init OCP device management - * - * This function builds the list of devices before setup_arch. - * This allows platform code to modify the device lists before - * they are bound to drivers (changes to paddr, removing devices - * etc) - */ -int __init -ocp_early_init(void) -{ - struct ocp_def *def; - - DBG(("ocp: ocp_early_init()...\n")); - - /* Fill the devices list */ - for (def = core_ocp; def->vendor != OCP_VENDOR_INVALID; def++) - ocp_add_one_device(def); - - DBG(("ocp: ocp_early_init()... done.\n")); - - return 0; -} - -/** - * ocp_driver_init - Init OCP device management - * - * This function is meant to be called via OCP bus registration. - */ -static int __init -ocp_driver_init(void) -{ - int ret = 0, index = 0; - struct device *ocp_bus; - struct list_head *entry; - struct ocp_device *dev; - - if (ocp_inited) - return ret; - ocp_inited = 1; - - DBG(("ocp: ocp_driver_init()...\n")); - - /* Allocate/register primary OCP bus */ - ocp_bus = kzalloc(sizeof(struct device), GFP_KERNEL); - if (ocp_bus == NULL) - return 1; - strcpy(ocp_bus->bus_id, "ocp"); - - bus_register(&ocp_bus_type); - - device_register(ocp_bus); - - /* Put each OCP device into global device list */ - list_for_each(entry, &ocp_devices) { - dev = list_entry(entry, struct ocp_device, link); - sprintf(dev->dev.bus_id, "%2.2x", index); - dev->dev.parent = ocp_bus; - dev->dev.bus = &ocp_bus_type; - device_register(&dev->dev); - ocp_create_sysfs_dev_files(dev); - index++; - } - - DBG(("ocp: ocp_driver_init()... done.\n")); - - return 0; -} - -postcore_initcall(ocp_driver_init); - -EXPORT_SYMBOL(ocp_bus_type); -EXPORT_SYMBOL(ocp_find_device); -EXPORT_SYMBOL(ocp_register_driver); -EXPORT_SYMBOL(ocp_unregister_driver); diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c deleted file mode 100644 index 67dffe27b5c3..000000000000 --- a/arch/ppc/syslib/open_pic.c +++ /dev/null @@ -1,1087 +0,0 @@ -/* - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "open_pic_defs.h" - -#if defined(CONFIG_PRPMC800) -#define OPENPIC_BIG_ENDIAN -#endif - -void __iomem *OpenPIC_Addr; -static volatile struct OpenPIC __iomem *OpenPIC = NULL; - -/* - * We define OpenPIC_InitSenses table thusly: - * bit 0x1: sense, 0 for edge and 1 for level. - * bit 0x2: polarity, 0 for negative, 1 for positive. - */ -u_int OpenPIC_NumInitSenses __initdata = 0; -u_char *OpenPIC_InitSenses __initdata = NULL; -extern int use_of_interrupt_tree; - -static u_int NumProcessors; -static u_int NumSources; -static int open_pic_irq_offset; -static volatile OpenPIC_Source __iomem *ISR[NR_IRQS]; -static int openpic_cascade_irq = -1; -static int (*openpic_cascade_fn)(void); - -/* Global Operations */ -static void openpic_disable_8259_pass_through(void); -static void openpic_set_spurious(u_int vector); - -#ifdef CONFIG_SMP -/* Interprocessor Interrupts */ -static void openpic_initipi(u_int ipi, u_int pri, u_int vector); -static irqreturn_t openpic_ipi_action(int cpl, void *dev_id); -#endif - -/* Timer Interrupts */ -static void openpic_inittimer(u_int timer, u_int pri, u_int vector); -static void openpic_maptimer(u_int timer, cpumask_t cpumask); - -/* Interrupt Sources */ -static void openpic_enable_irq(u_int irq); -static void openpic_disable_irq(u_int irq); -static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity, - int is_level); -static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask); - -/* - * These functions are not used but the code is kept here - * for completeness and future reference. - */ -#ifdef notused -static void openpic_enable_8259_pass_through(void); -static u_int openpic_get_spurious(void); -static void openpic_set_sense(u_int irq, int sense); -#endif /* notused */ - -/* - * Description of the openpic for the higher-level irq code - */ -static void openpic_end_irq(unsigned int irq_nr); -static void openpic_ack_irq(unsigned int irq_nr); -static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask); - -struct hw_interrupt_type open_pic = { - .typename = " OpenPIC ", - .enable = openpic_enable_irq, - .disable = openpic_disable_irq, - .ack = openpic_ack_irq, - .end = openpic_end_irq, - .set_affinity = openpic_set_affinity, -}; - -#ifdef CONFIG_SMP -static void openpic_end_ipi(unsigned int irq_nr); -static void openpic_ack_ipi(unsigned int irq_nr); -static void openpic_enable_ipi(unsigned int irq_nr); -static void openpic_disable_ipi(unsigned int irq_nr); - -struct hw_interrupt_type open_pic_ipi = { - .typename = " OpenPIC ", - .enable = openpic_enable_ipi, - .disable = openpic_disable_ipi, - .ack = openpic_ack_ipi, - .end = openpic_end_ipi, -}; -#endif /* CONFIG_SMP */ - -/* - * Accesses to the current processor's openpic registers - */ -#ifdef CONFIG_SMP -#define THIS_CPU Processor[cpu] -#define DECL_THIS_CPU int cpu = smp_hw_index[smp_processor_id()] -#define CHECK_THIS_CPU check_arg_cpu(cpu) -#else -#define THIS_CPU Processor[0] -#define DECL_THIS_CPU -#define CHECK_THIS_CPU -#endif /* CONFIG_SMP */ - -#if 1 -#define check_arg_ipi(ipi) \ - if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \ - printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi); -#define check_arg_timer(timer) \ - if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \ - printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer); -#define check_arg_vec(vec) \ - if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \ - printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec); -#define check_arg_pri(pri) \ - if (pri < 0 || pri >= OPENPIC_NUM_PRI) \ - printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri); -/* - * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's - * data has probably been corrupted and we're going to panic or deadlock later - * anyway --Troy - */ -#define check_arg_irq(irq) \ - if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \ - || ISR[irq - open_pic_irq_offset] == 0) { \ - printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \ - dump_stack(); } -#define check_arg_cpu(cpu) \ - if (cpu < 0 || cpu >= NumProcessors){ \ - printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \ - dump_stack(); } -#else -#define check_arg_ipi(ipi) do {} while (0) -#define check_arg_timer(timer) do {} while (0) -#define check_arg_vec(vec) do {} while (0) -#define check_arg_pri(pri) do {} while (0) -#define check_arg_irq(irq) do {} while (0) -#define check_arg_cpu(cpu) do {} while (0) -#endif - -u_int openpic_read(volatile u_int __iomem *addr) -{ - u_int val; - -#ifdef OPENPIC_BIG_ENDIAN - val = in_be32(addr); -#else - val = in_le32(addr); -#endif - return val; -} - -static inline void openpic_write(volatile u_int __iomem *addr, u_int val) -{ -#ifdef OPENPIC_BIG_ENDIAN - out_be32(addr, val); -#else - out_le32(addr, val); -#endif -} - -static inline u_int openpic_readfield(volatile u_int __iomem *addr, u_int mask) -{ - u_int val = openpic_read(addr); - return val & mask; -} - -inline void openpic_writefield(volatile u_int __iomem *addr, u_int mask, - u_int field) -{ - u_int val = openpic_read(addr); - openpic_write(addr, (val & ~mask) | (field & mask)); -} - -static inline void openpic_clearfield(volatile u_int __iomem *addr, u_int mask) -{ - openpic_writefield(addr, mask, 0); -} - -static inline void openpic_setfield(volatile u_int __iomem *addr, u_int mask) -{ - openpic_writefield(addr, mask, mask); -} - -static void openpic_safe_writefield(volatile u_int __iomem *addr, u_int mask, - u_int field) -{ - openpic_setfield(addr, OPENPIC_MASK); - while (openpic_read(addr) & OPENPIC_ACTIVITY); - openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK); -} - -#ifdef CONFIG_SMP -/* yes this is right ... bug, feature, you decide! -- tgall */ -u_int openpic_read_IPI(volatile u_int __iomem * addr) -{ - u_int val = 0; -#if defined(OPENPIC_BIG_ENDIAN) - val = in_be32(addr); -#else - val = in_le32(addr); -#endif - return val; -} - -/* because of the power3 be / le above, this is needed */ -inline void openpic_writefield_IPI(volatile u_int __iomem * addr, u_int mask, u_int field) -{ - u_int val = openpic_read_IPI(addr); - openpic_write(addr, (val & ~mask) | (field & mask)); -} - -static inline void openpic_clearfield_IPI(volatile u_int __iomem *addr, u_int mask) -{ - openpic_writefield_IPI(addr, mask, 0); -} - -static inline void openpic_setfield_IPI(volatile u_int __iomem *addr, u_int mask) -{ - openpic_writefield_IPI(addr, mask, mask); -} - -static void openpic_safe_writefield_IPI(volatile u_int __iomem *addr, u_int mask, u_int field) -{ - openpic_setfield_IPI(addr, OPENPIC_MASK); - - /* wait until it's not in use */ - /* BenH: Is this code really enough ? I would rather check the result - * and eventually retry ... - */ - while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY); - - openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK); -} -#endif /* CONFIG_SMP */ - -#ifdef CONFIG_EPIC_SERIAL_MODE -/* On platforms that may use EPIC serial mode, the default is enabled. */ -int epic_serial_mode = 1; - -static void __init openpic_eicr_set_clk(u_int clkval) -{ - openpic_writefield(&OpenPIC->Global.Global_Configuration1, - OPENPIC_EICR_S_CLK_MASK, (clkval << 28)); -} - -static void __init openpic_enable_sie(void) -{ - openpic_setfield(&OpenPIC->Global.Global_Configuration1, - OPENPIC_EICR_SIE); -} -#endif - -#if defined(CONFIG_EPIC_SERIAL_MODE) -static void openpic_reset(void) -{ - openpic_setfield(&OpenPIC->Global.Global_Configuration0, - OPENPIC_CONFIG_RESET); - while (openpic_readfield(&OpenPIC->Global.Global_Configuration0, - OPENPIC_CONFIG_RESET)) - mb(); -} -#endif - -void __init openpic_set_sources(int first_irq, int num_irqs, void __iomem *first_ISR) -{ - volatile OpenPIC_Source __iomem *src = first_ISR; - int i, last_irq; - - last_irq = first_irq + num_irqs; - if (last_irq > NumSources) - NumSources = last_irq; - if (src == 0) - src = &((struct OpenPIC __iomem *)OpenPIC_Addr)->Source[first_irq]; - for (i = first_irq; i < last_irq; ++i, ++src) - ISR[i] = src; -} - -/* - * The `offset' parameter defines where the interrupts handled by the - * OpenPIC start in the space of interrupt numbers that the kernel knows - * about. In other words, the OpenPIC's IRQ0 is numbered `offset' in the - * kernel's interrupt numbering scheme. - * We assume there is only one OpenPIC. - */ -void __init openpic_init(int offset) -{ - u_int t, i; - u_int timerfreq; - const char *version; - - if (!OpenPIC_Addr) { - printk("No OpenPIC found !\n"); - return; - } - OpenPIC = (volatile struct OpenPIC __iomem *)OpenPIC_Addr; - -#ifdef CONFIG_EPIC_SERIAL_MODE - /* Have to start from ground zero. - */ - openpic_reset(); -#endif - - if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122); - - t = openpic_read(&OpenPIC->Global.Feature_Reporting0); - switch (t & OPENPIC_FEATURE_VERSION_MASK) { - case 1: - version = "1.0"; - break; - case 2: - version = "1.2"; - break; - case 3: - version = "1.3"; - break; - default: - version = "?"; - break; - } - NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >> - OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1; - if (NumSources == 0) - openpic_set_sources(0, - ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >> - OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1, - NULL); - printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n", - version, NumProcessors, NumSources, OpenPIC); - timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency); - if (timerfreq) - printk("OpenPIC timer frequency is %d.%06d MHz\n", - timerfreq / 1000000, timerfreq % 1000000); - - open_pic_irq_offset = offset; - - /* Initialize timer interrupts */ - if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba); - for (i = 0; i < OPENPIC_NUM_TIMERS; i++) { - /* Disabled, Priority 0 */ - openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset); - /* No processor */ - openpic_maptimer(i, CPU_MASK_NONE); - } - -#ifdef CONFIG_SMP - /* Initialize IPI interrupts */ - if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb); - for (i = 0; i < OPENPIC_NUM_IPI; i++) { - /* Disabled, increased priorities 10..13 */ - openpic_initipi(i, OPENPIC_PRIORITY_IPI_BASE+i, - OPENPIC_VEC_IPI+i+offset); - /* IPIs are per-CPU */ - irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU; - irq_desc[OPENPIC_VEC_IPI+i+offset].chip = &open_pic_ipi; - } -#endif - - /* Initialize external interrupts */ - if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc); - - openpic_set_priority(0xf); - - /* Init all external sources, including possibly the cascade. */ - for (i = 0; i < NumSources; i++) { - int sense; - - if (ISR[i] == 0) - continue; - - /* the bootloader may have left it enabled (bad !) */ - openpic_disable_irq(i+offset); - - sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE); - - if (sense & IRQ_SENSE_MASK) - irq_desc[i+offset].status = IRQ_LEVEL; - - /* Enabled, Default priority */ - openpic_initirq(i, OPENPIC_PRIORITY_DEFAULT, i+offset, - (sense & IRQ_POLARITY_MASK), - (sense & IRQ_SENSE_MASK)); - /* Processor 0 */ - openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE); - } - - /* Init descriptors */ - for (i = offset; i < NumSources + offset; i++) - irq_desc[i].chip = &open_pic; - - /* Initialize the spurious interrupt */ - if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd); - openpic_set_spurious(OPENPIC_VEC_SPURIOUS); - openpic_disable_8259_pass_through(); -#ifdef CONFIG_EPIC_SERIAL_MODE - if (epic_serial_mode) { - openpic_eicr_set_clk(7); /* Slowest value until we know better */ - openpic_enable_sie(); - } -#endif - openpic_set_priority(0); - - if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222); -} - -#ifdef notused -static void openpic_enable_8259_pass_through(void) -{ - openpic_clearfield(&OpenPIC->Global.Global_Configuration0, - OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); -} -#endif /* notused */ - -static void openpic_disable_8259_pass_through(void) -{ - openpic_setfield(&OpenPIC->Global.Global_Configuration0, - OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); -} - -/* - * Find out the current interrupt - */ -u_int openpic_irq(void) -{ - u_int vec; - DECL_THIS_CPU; - - CHECK_THIS_CPU; - vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge, - OPENPIC_VECTOR_MASK); - return vec; -} - -void openpic_eoi(void) -{ - DECL_THIS_CPU; - - CHECK_THIS_CPU; - openpic_write(&OpenPIC->THIS_CPU.EOI, 0); - /* Handle PCI write posting */ - (void)openpic_read(&OpenPIC->THIS_CPU.EOI); -} - -u_int openpic_get_priority(void) -{ - DECL_THIS_CPU; - - CHECK_THIS_CPU; - return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority, - OPENPIC_CURRENT_TASK_PRIORITY_MASK); -} - -void openpic_set_priority(u_int pri) -{ - DECL_THIS_CPU; - - CHECK_THIS_CPU; - check_arg_pri(pri); - openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority, - OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri); -} - -/* - * Get/set the spurious vector - */ -#ifdef notused -static u_int openpic_get_spurious(void) -{ - return openpic_readfield(&OpenPIC->Global.Spurious_Vector, - OPENPIC_VECTOR_MASK); -} -#endif /* notused */ - -static void openpic_set_spurious(u_int vec) -{ - check_arg_vec(vec); - openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK, - vec); -} - -#ifdef CONFIG_SMP -/* - * Convert a cpu mask from logical to physical cpu numbers. - */ -static inline cpumask_t physmask(cpumask_t cpumask) -{ - int i; - cpumask_t mask = CPU_MASK_NONE; - - cpus_and(cpumask, cpu_online_map, cpumask); - - for (i = 0; i < NR_CPUS; i++) - if (cpu_isset(i, cpumask)) - cpu_set(smp_hw_index[i], mask); - - return mask; -} -#else -#define physmask(cpumask) (cpumask) -#endif - -void openpic_reset_processor_phys(u_int mask) -{ - openpic_write(&OpenPIC->Global.Processor_Initialization, mask); -} - -#if defined(CONFIG_SMP) || defined(CONFIG_PM) -static DEFINE_SPINLOCK(openpic_setup_lock); -#endif - -#ifdef CONFIG_SMP -/* - * Initialize an interprocessor interrupt (and disable it) - * - * ipi: OpenPIC interprocessor interrupt number - * pri: interrupt source priority - * vec: the vector it will produce - */ -static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec) -{ - check_arg_ipi(ipi); - check_arg_pri(pri); - check_arg_vec(vec); - openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi), - OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, - (pri << OPENPIC_PRIORITY_SHIFT) | vec); -} - -/* - * Send an IPI to one or more CPUs - * - * Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI) - * and not a system-wide interrupt number - */ -void openpic_cause_IPI(u_int ipi, cpumask_t cpumask) -{ - DECL_THIS_CPU; - - CHECK_THIS_CPU; - check_arg_ipi(ipi); - openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi), - cpus_addr(physmask(cpumask))[0]); -} - -void openpic_request_IPIs(void) -{ - int i; - - /* - * Make sure this matches what is defined in smp.c for - * smp_message_{pass|recv}() or what shows up in - * /proc/interrupts will be wrong!!! --Troy */ - - if (OpenPIC == NULL) - return; - - /* - * IPIs are marked IRQF_DISABLED as they must run with irqs - * disabled - */ - request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset, - openpic_ipi_action, IRQF_DISABLED, - "IPI0 (call function)", NULL); - request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1, - openpic_ipi_action, IRQF_DISABLED, - "IPI1 (reschedule)", NULL); - request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2, - openpic_ipi_action, IRQF_DISABLED, - "IPI2 (invalidate tlb)", NULL); - request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3, - openpic_ipi_action, IRQF_DISABLED, - "IPI3 (xmon break)", NULL); - - for ( i = 0; i < OPENPIC_NUM_IPI ; i++ ) - openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i); -} - -/* - * Do per-cpu setup for SMP systems. - * - * Get IPI's working and start taking interrupts. - * -- Cort - */ - -void __devinit do_openpic_setup_cpu(void) -{ -#ifdef CONFIG_IRQ_ALL_CPUS - int i; - cpumask_t msk = CPU_MASK_NONE; -#endif - spin_lock(&openpic_setup_lock); - -#ifdef CONFIG_IRQ_ALL_CPUS - cpu_set(smp_hw_index[smp_processor_id()], msk); - - /* let the openpic know we want intrs. default affinity - * is 0xffffffff until changed via /proc - * That's how it's done on x86. If we want it differently, then - * we should make sure we also change the default values of - * irq_desc[].affinity in irq.c. - */ - for (i = 0; i < NumSources; i++) - openpic_mapirq(i, msk, CPU_MASK_ALL); -#endif /* CONFIG_IRQ_ALL_CPUS */ - openpic_set_priority(0); - - spin_unlock(&openpic_setup_lock); -} -#endif /* CONFIG_SMP */ - -/* - * Initialize a timer interrupt (and disable it) - * - * timer: OpenPIC timer number - * pri: interrupt source priority - * vec: the vector it will produce - */ -static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec) -{ - check_arg_timer(timer); - check_arg_pri(pri); - check_arg_vec(vec); - openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority, - OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, - (pri << OPENPIC_PRIORITY_SHIFT) | vec); -} - -/* - * Map a timer interrupt to one or more CPUs - */ -static void __init openpic_maptimer(u_int timer, cpumask_t cpumask) -{ - cpumask_t phys = physmask(cpumask); - check_arg_timer(timer); - openpic_write(&OpenPIC->Global.Timer[timer].Destination, - cpus_addr(phys)[0]); -} - -/* - * Change the priority of an interrupt - */ -void __init -openpic_set_irq_priority(u_int irq, u_int pri) -{ - check_arg_irq(irq); - openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority, - OPENPIC_PRIORITY_MASK, - pri << OPENPIC_PRIORITY_SHIFT); -} - -/* - * Initalize the interrupt source which will generate an NMI. - * This raises the interrupt's priority from 8 to 9. - * - * irq: The logical IRQ which generates an NMI. - */ -void __init -openpic_init_nmi_irq(u_int irq) -{ - check_arg_irq(irq); - openpic_set_irq_priority(irq, OPENPIC_PRIORITY_NMI); -} - -/* - * - * All functions below take an offset'ed irq argument - * - */ - -/* - * Hookup a cascade to the OpenPIC. - */ - -static struct irqaction openpic_cascade_irqaction = { - .handler = no_action, - .flags = IRQF_DISABLED, - .mask = CPU_MASK_NONE, -}; - -void __init -openpic_hookup_cascade(u_int irq, char *name, - int (*cascade_fn)(void)) -{ - openpic_cascade_irq = irq; - openpic_cascade_fn = cascade_fn; - - if (setup_irq(irq, &openpic_cascade_irqaction)) - printk("Unable to get OpenPIC IRQ %d for cascade\n", - irq - open_pic_irq_offset); -} - -/* - * Enable/disable an external interrupt source - * - * Externally called, irq is an offseted system-wide interrupt number - */ -static void openpic_enable_irq(u_int irq) -{ - volatile u_int __iomem *vpp; - - check_arg_irq(irq); - vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority; - openpic_clearfield(vpp, OPENPIC_MASK); - /* make sure mask gets to controller before we return to user */ - do { - mb(); /* sync is probably useless here */ - } while (openpic_readfield(vpp, OPENPIC_MASK)); -} - -static void openpic_disable_irq(u_int irq) -{ - volatile u_int __iomem *vpp; - u32 vp; - - check_arg_irq(irq); - vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority; - openpic_setfield(vpp, OPENPIC_MASK); - /* make sure mask gets to controller before we return to user */ - do { - mb(); /* sync is probably useless here */ - vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY); - } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK)); -} - -#ifdef CONFIG_SMP -/* - * Enable/disable an IPI interrupt source - * - * Externally called, irq is an offseted system-wide interrupt number - */ -void openpic_enable_ipi(u_int irq) -{ - irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset); - check_arg_ipi(irq); - openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK); - -} - -void openpic_disable_ipi(u_int irq) -{ - irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset); - check_arg_ipi(irq); - openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK); -} -#endif - -/* - * Initialize an interrupt source (and disable it!) - * - * irq: OpenPIC interrupt number - * pri: interrupt source priority - * vec: the vector it will produce - * pol: polarity (1 for positive, 0 for negative) - * sense: 1 for level, 0 for edge - */ -static void __init -openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense) -{ - openpic_safe_writefield(&ISR[irq]->Vector_Priority, - OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | - OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK, - (pri << OPENPIC_PRIORITY_SHIFT) | vec | - (pol ? OPENPIC_POLARITY_POSITIVE : - OPENPIC_POLARITY_NEGATIVE) | - (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE)); -} - -/* - * Map an interrupt source to one or more CPUs - */ -static void openpic_mapirq(u_int irq, cpumask_t physmask, cpumask_t keepmask) -{ - if (ISR[irq] == 0) - return; - if (!cpus_empty(keepmask)) { - cpumask_t irqdest = { .bits[0] = openpic_read(&ISR[irq]->Destination) }; - cpus_and(irqdest, irqdest, keepmask); - cpus_or(physmask, physmask, irqdest); - } - openpic_write(&ISR[irq]->Destination, cpus_addr(physmask)[0]); -} - -#ifdef notused -/* - * Set the sense for an interrupt source (and disable it!) - * - * sense: 1 for level, 0 for edge - */ -static void openpic_set_sense(u_int irq, int sense) -{ - if (ISR[irq] != 0) - openpic_safe_writefield(&ISR[irq]->Vector_Priority, - OPENPIC_SENSE_LEVEL, - (sense ? OPENPIC_SENSE_LEVEL : 0)); -} -#endif /* notused */ - -/* No spinlocks, should not be necessary with the OpenPIC - * (1 register = 1 interrupt and we have the desc lock). - */ -static void openpic_ack_irq(unsigned int irq_nr) -{ -#ifdef __SLOW_VERSION__ - openpic_disable_irq(irq_nr); - openpic_eoi(); -#else - if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0) - openpic_eoi(); -#endif -} - -static void openpic_end_irq(unsigned int irq_nr) -{ -#ifdef __SLOW_VERSION__ - if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)) - && irq_desc[irq_nr].action) - openpic_enable_irq(irq_nr); -#else - if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0) - openpic_eoi(); -#endif -} - -static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask) -{ - openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), CPU_MASK_NONE); -} - -#ifdef CONFIG_SMP -static void openpic_ack_ipi(unsigned int irq_nr) -{ - openpic_eoi(); -} - -static void openpic_end_ipi(unsigned int irq_nr) -{ -} - -static irqreturn_t openpic_ipi_action(int cpl, void *dev_id) -{ - smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset); - return IRQ_HANDLED; -} - -#endif /* CONFIG_SMP */ - -int -openpic_get_irq(void) -{ - int irq = openpic_irq(); - - /* - * Check for the cascade interrupt and call the cascaded - * interrupt controller function (usually i8259_irq) if so. - * This should move to irq.c eventually. -- paulus - */ - if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) { - int cirq = openpic_cascade_fn(); - - /* Allow for the cascade being shared with other devices */ - if (cirq != -1) { - irq = cirq; - openpic_eoi(); - } - } else if (irq == OPENPIC_VEC_SPURIOUS) - irq = -1; - return irq; -} - -#ifdef CONFIG_SMP -void -smp_openpic_message_pass(int target, int msg) -{ - cpumask_t mask = CPU_MASK_ALL; - /* make sure we're sending something that translates to an IPI */ - if (msg > 0x3) { - printk("SMP %d: smp_message_pass: unknown msg %d\n", - smp_processor_id(), msg); - return; - } - switch (target) { - case MSG_ALL: - openpic_cause_IPI(msg, mask); - break; - case MSG_ALL_BUT_SELF: - cpu_clear(smp_processor_id(), mask); - openpic_cause_IPI(msg, mask); - break; - default: - openpic_cause_IPI(msg, cpumask_of_cpu(target)); - break; - } -} -#endif /* CONFIG_SMP */ - -#ifdef CONFIG_PM - -/* - * We implement the IRQ controller as a sysdev and put it - * to sleep at powerdown stage (the callback is named suspend, - * but it's old semantics, for the Device Model, it's really - * powerdown). The possible problem is that another sysdev that - * happens to be suspend after this one will have interrupts off, - * that may be an issue... For now, this isn't an issue on pmac - * though... - */ - -static u32 save_ipi_vp[OPENPIC_NUM_IPI]; -static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES]; -static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES]; -static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS]; -static int openpic_suspend_count; - -static void openpic_cached_enable_irq(u_int irq) -{ - check_arg_irq(irq); - save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK; -} - -static void openpic_cached_disable_irq(u_int irq) -{ - check_arg_irq(irq); - save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK; -} - -/* WARNING: Can be called directly by the cpufreq code with NULL parameter, - * we need something better to deal with that... Maybe switch to S1 for - * cpufreq changes - */ -int openpic_suspend(struct sys_device *sysdev, pm_message_t state) -{ - int i; - unsigned long flags; - - spin_lock_irqsave(&openpic_setup_lock, flags); - - if (openpic_suspend_count++ > 0) { - spin_unlock_irqrestore(&openpic_setup_lock, flags); - return 0; - } - - openpic_set_priority(0xf); - - open_pic.enable = openpic_cached_enable_irq; - open_pic.disable = openpic_cached_disable_irq; - - for (i=0; iProcessor[i].Current_Task_Priority); - openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority, - OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf); - } - - for (i=0; iGlobal.IPI_Vector_Priority(i)); - for (i=0; iVector_Priority) & ~OPENPIC_ACTIVITY; - save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination); - } - - spin_unlock_irqrestore(&openpic_setup_lock, flags); - - return 0; -} - -/* WARNING: Can be called directly by the cpufreq code with NULL parameter, - * we need something better to deal with that... Maybe switch to S1 for - * cpufreq changes - */ -int openpic_resume(struct sys_device *sysdev) -{ - int i; - unsigned long flags; - u32 vppmask = OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | - OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK | - OPENPIC_MASK; - - spin_lock_irqsave(&openpic_setup_lock, flags); - - if ((--openpic_suspend_count) > 0) { - spin_unlock_irqrestore(&openpic_setup_lock, flags); - return 0; - } - - /* OpenPIC sometimes seem to need some time to be fully back up... */ - do { - openpic_set_spurious(OPENPIC_VEC_SPURIOUS); - } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK) - != OPENPIC_VEC_SPURIOUS); - - openpic_disable_8259_pass_through(); - - for (i=0; iGlobal.IPI_Vector_Priority(i), - save_ipi_vp[i]); - for (i=0; iDestination, save_irq_src_dest[i]); - openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]); - /* make sure mask gets to controller before we return to user */ - do { - openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]); - } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask) - != (save_irq_src_vp[i] & vppmask)); - } - for (i=0; iProcessor[i].Current_Task_Priority, - save_cpu_task_pri[i]); - - open_pic.enable = openpic_enable_irq; - open_pic.disable = openpic_disable_irq; - - openpic_set_priority(0); - - spin_unlock_irqrestore(&openpic_setup_lock, flags); - - return 0; -} - -#endif /* CONFIG_PM */ - -static struct sysdev_class openpic_sysclass = { - .name = "openpic", -}; - -static struct sys_device device_openpic = { - .id = 0, - .cls = &openpic_sysclass, -}; - -static struct sysdev_driver driver_openpic = { -#ifdef CONFIG_PM - .suspend = &openpic_suspend, - .resume = &openpic_resume, -#endif /* CONFIG_PM */ -}; - -static int __init init_openpic_sysfs(void) -{ - int rc; - - if (!OpenPIC_Addr) - return -ENODEV; - printk(KERN_DEBUG "Registering openpic with sysfs...\n"); - rc = sysdev_class_register(&openpic_sysclass); - if (rc) { - printk(KERN_ERR "Failed registering openpic sys class\n"); - return -ENODEV; - } - rc = sysdev_register(&device_openpic); - if (rc) { - printk(KERN_ERR "Failed registering openpic sys device\n"); - return -ENODEV; - } - rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic); - if (rc) { - printk(KERN_ERR "Failed registering openpic sys driver\n"); - return -ENODEV; - } - return 0; -} - -subsys_initcall(init_openpic_sysfs); - diff --git a/arch/ppc/syslib/open_pic2.c b/arch/ppc/syslib/open_pic2.c deleted file mode 100644 index 449075a04798..000000000000 --- a/arch/ppc/syslib/open_pic2.c +++ /dev/null @@ -1,710 +0,0 @@ -/* - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * This is a duplicate of open_pic.c that deals with U3s MPIC on - * G5 PowerMacs. It's the same file except it's using big endian - * register accesses - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "open_pic_defs.h" - -void *OpenPIC2_Addr; -static volatile struct OpenPIC *OpenPIC2 = NULL; -/* - * We define OpenPIC_InitSenses table thusly: - * bit 0x1: sense, 0 for edge and 1 for level. - * bit 0x2: polarity, 0 for negative, 1 for positive. - */ -extern u_int OpenPIC_NumInitSenses; -extern u_char *OpenPIC_InitSenses; -extern int use_of_interrupt_tree; - -static u_int NumProcessors; -static u_int NumSources; -static int open_pic2_irq_offset; -static volatile OpenPIC_Source *ISR[NR_IRQS]; - -/* Global Operations */ -static void openpic2_disable_8259_pass_through(void); -static void openpic2_set_priority(u_int pri); -static void openpic2_set_spurious(u_int vector); - -/* Timer Interrupts */ -static void openpic2_inittimer(u_int timer, u_int pri, u_int vector); -static void openpic2_maptimer(u_int timer, u_int cpumask); - -/* Interrupt Sources */ -static void openpic2_enable_irq(u_int irq); -static void openpic2_disable_irq(u_int irq); -static void openpic2_initirq(u_int irq, u_int pri, u_int vector, int polarity, - int is_level); -static void openpic2_mapirq(u_int irq, u_int cpumask, u_int keepmask); - -/* - * These functions are not used but the code is kept here - * for completeness and future reference. - */ -static void openpic2_reset(void); -#ifdef notused -static void openpic2_enable_8259_pass_through(void); -static u_int openpic2_get_priority(void); -static u_int openpic2_get_spurious(void); -static void openpic2_set_sense(u_int irq, int sense); -#endif /* notused */ - -/* - * Description of the openpic for the higher-level irq code - */ -static void openpic2_end_irq(unsigned int irq_nr); -static void openpic2_ack_irq(unsigned int irq_nr); - -struct hw_interrupt_type open_pic2 = { - .typename = " OpenPIC2 ", - .enable = openpic2_enable_irq, - .disable = openpic2_disable_irq, - .ack = openpic2_ack_irq, - .end = openpic2_end_irq, -}; - -/* - * Accesses to the current processor's openpic registers - * On cascaded controller, this is only CPU 0 - */ -#define THIS_CPU Processor[0] -#define DECL_THIS_CPU -#define CHECK_THIS_CPU - -#if 1 -#define check_arg_ipi(ipi) \ - if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \ - printk("open_pic.c:%d: illegal ipi %d\n", __LINE__, ipi); -#define check_arg_timer(timer) \ - if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \ - printk("open_pic.c:%d: illegal timer %d\n", __LINE__, timer); -#define check_arg_vec(vec) \ - if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \ - printk("open_pic.c:%d: illegal vector %d\n", __LINE__, vec); -#define check_arg_pri(pri) \ - if (pri < 0 || pri >= OPENPIC_NUM_PRI) \ - printk("open_pic.c:%d: illegal priority %d\n", __LINE__, pri); -/* - * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's - * data has probably been corrupted and we're going to panic or deadlock later - * anyway --Troy - */ -extern unsigned long* _get_SP(void); -#define check_arg_irq(irq) \ - if (irq < open_pic2_irq_offset || irq >= NumSources+open_pic2_irq_offset \ - || ISR[irq - open_pic2_irq_offset] == 0) { \ - printk("open_pic.c:%d: illegal irq %d\n", __LINE__, irq); \ - /*print_backtrace(_get_SP());*/ } -#define check_arg_cpu(cpu) \ - if (cpu < 0 || cpu >= NumProcessors){ \ - printk("open_pic2.c:%d: illegal cpu %d\n", __LINE__, cpu); \ - /*print_backtrace(_get_SP());*/ } -#else -#define check_arg_ipi(ipi) do {} while (0) -#define check_arg_timer(timer) do {} while (0) -#define check_arg_vec(vec) do {} while (0) -#define check_arg_pri(pri) do {} while (0) -#define check_arg_irq(irq) do {} while (0) -#define check_arg_cpu(cpu) do {} while (0) -#endif - -static u_int openpic2_read(volatile u_int *addr) -{ - u_int val; - - val = in_be32(addr); - return val; -} - -static inline void openpic2_write(volatile u_int *addr, u_int val) -{ - out_be32(addr, val); -} - -static inline u_int openpic2_readfield(volatile u_int *addr, u_int mask) -{ - u_int val = openpic2_read(addr); - return val & mask; -} - -inline void openpic2_writefield(volatile u_int *addr, u_int mask, - u_int field) -{ - u_int val = openpic2_read(addr); - openpic2_write(addr, (val & ~mask) | (field & mask)); -} - -static inline void openpic2_clearfield(volatile u_int *addr, u_int mask) -{ - openpic2_writefield(addr, mask, 0); -} - -static inline void openpic2_setfield(volatile u_int *addr, u_int mask) -{ - openpic2_writefield(addr, mask, mask); -} - -static void openpic2_safe_writefield(volatile u_int *addr, u_int mask, - u_int field) -{ - openpic2_setfield(addr, OPENPIC_MASK); - while (openpic2_read(addr) & OPENPIC_ACTIVITY); - openpic2_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK); -} - -static void openpic2_reset(void) -{ - openpic2_setfield(&OpenPIC2->Global.Global_Configuration0, - OPENPIC_CONFIG_RESET); - while (openpic2_readfield(&OpenPIC2->Global.Global_Configuration0, - OPENPIC_CONFIG_RESET)) - mb(); -} - -void __init openpic2_set_sources(int first_irq, int num_irqs, void *first_ISR) -{ - volatile OpenPIC_Source *src = first_ISR; - int i, last_irq; - - last_irq = first_irq + num_irqs; - if (last_irq > NumSources) - NumSources = last_irq; - if (src == 0) - src = &((struct OpenPIC *)OpenPIC2_Addr)->Source[first_irq]; - for (i = first_irq; i < last_irq; ++i, ++src) - ISR[i] = src; -} - -/* - * The `offset' parameter defines where the interrupts handled by the - * OpenPIC start in the space of interrupt numbers that the kernel knows - * about. In other words, the OpenPIC's IRQ0 is numbered `offset' in the - * kernel's interrupt numbering scheme. - * We assume there is only one OpenPIC. - */ -void __init openpic2_init(int offset) -{ - u_int t, i; - u_int timerfreq; - const char *version; - - if (!OpenPIC2_Addr) { - printk("No OpenPIC2 found !\n"); - return; - } - OpenPIC2 = (volatile struct OpenPIC *)OpenPIC2_Addr; - - if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122); - - t = openpic2_read(&OpenPIC2->Global.Feature_Reporting0); - switch (t & OPENPIC_FEATURE_VERSION_MASK) { - case 1: - version = "1.0"; - break; - case 2: - version = "1.2"; - break; - case 3: - version = "1.3"; - break; - default: - version = "?"; - break; - } - NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >> - OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1; - if (NumSources == 0) - openpic2_set_sources(0, - ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >> - OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1, - NULL); - printk("OpenPIC (2) Version %s (%d CPUs and %d IRQ sources) at %p\n", - version, NumProcessors, NumSources, OpenPIC2); - timerfreq = openpic2_read(&OpenPIC2->Global.Timer_Frequency); - if (timerfreq) - printk("OpenPIC timer frequency is %d.%06d MHz\n", - timerfreq / 1000000, timerfreq % 1000000); - - open_pic2_irq_offset = offset; - - /* Initialize timer interrupts */ - if ( ppc_md.progress ) ppc_md.progress("openpic2: timer",0x3ba); - for (i = 0; i < OPENPIC_NUM_TIMERS; i++) { - /* Disabled, Priority 0 */ - openpic2_inittimer(i, 0, OPENPIC2_VEC_TIMER+i+offset); - /* No processor */ - openpic2_maptimer(i, 0); - } - - /* Initialize external interrupts */ - if (ppc_md.progress) ppc_md.progress("openpic2: external",0x3bc); - - openpic2_set_priority(0xf); - - /* Init all external sources, including possibly the cascade. */ - for (i = 0; i < NumSources; i++) { - int sense; - - if (ISR[i] == 0) - continue; - - /* the bootloader may have left it enabled (bad !) */ - openpic2_disable_irq(i+offset); - - sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE); - - if (sense & IRQ_SENSE_MASK) - irq_desc[i+offset].status = IRQ_LEVEL; - - /* Enabled, Priority 8 */ - openpic2_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK), - (sense & IRQ_SENSE_MASK)); - /* Processor 0 */ - openpic2_mapirq(i, 1<<0, 0); - } - - /* Init descriptors */ - for (i = offset; i < NumSources + offset; i++) - irq_desc[i].chip = &open_pic2; - - /* Initialize the spurious interrupt */ - if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd); - openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+offset); - - openpic2_disable_8259_pass_through(); - openpic2_set_priority(0); - - if (ppc_md.progress) ppc_md.progress("openpic2: exit",0x222); -} - -#ifdef notused -static void openpic2_enable_8259_pass_through(void) -{ - openpic2_clearfield(&OpenPIC2->Global.Global_Configuration0, - OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); -} -#endif /* notused */ - -/* This can't be __init, it is used in openpic_sleep_restore_intrs */ -static void openpic2_disable_8259_pass_through(void) -{ - openpic2_setfield(&OpenPIC2->Global.Global_Configuration0, - OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); -} - -/* - * Find out the current interrupt - */ -u_int openpic2_irq(void) -{ - u_int vec; - DECL_THIS_CPU; - - CHECK_THIS_CPU; - vec = openpic2_readfield(&OpenPIC2->THIS_CPU.Interrupt_Acknowledge, - OPENPIC_VECTOR_MASK); - return vec; -} - -void openpic2_eoi(void) -{ - DECL_THIS_CPU; - - CHECK_THIS_CPU; - openpic2_write(&OpenPIC2->THIS_CPU.EOI, 0); - /* Handle PCI write posting */ - (void)openpic2_read(&OpenPIC2->THIS_CPU.EOI); -} - -#ifdef notused -static u_int openpic2_get_priority(void) -{ - DECL_THIS_CPU; - - CHECK_THIS_CPU; - return openpic2_readfield(&OpenPIC2->THIS_CPU.Current_Task_Priority, - OPENPIC_CURRENT_TASK_PRIORITY_MASK); -} -#endif /* notused */ - -static void __init openpic2_set_priority(u_int pri) -{ - DECL_THIS_CPU; - - CHECK_THIS_CPU; - check_arg_pri(pri); - openpic2_writefield(&OpenPIC2->THIS_CPU.Current_Task_Priority, - OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri); -} - -/* - * Get/set the spurious vector - */ -#ifdef notused -static u_int openpic2_get_spurious(void) -{ - return openpic2_readfield(&OpenPIC2->Global.Spurious_Vector, - OPENPIC_VECTOR_MASK); -} -#endif /* notused */ - -/* This can't be __init, it is used in openpic_sleep_restore_intrs */ -static void openpic2_set_spurious(u_int vec) -{ - check_arg_vec(vec); - openpic2_writefield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK, - vec); -} - -static DEFINE_SPINLOCK(openpic2_setup_lock); - -/* - * Initialize a timer interrupt (and disable it) - * - * timer: OpenPIC timer number - * pri: interrupt source priority - * vec: the vector it will produce - */ -static void __init openpic2_inittimer(u_int timer, u_int pri, u_int vec) -{ - check_arg_timer(timer); - check_arg_pri(pri); - check_arg_vec(vec); - openpic2_safe_writefield(&OpenPIC2->Global.Timer[timer].Vector_Priority, - OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, - (pri << OPENPIC_PRIORITY_SHIFT) | vec); -} - -/* - * Map a timer interrupt to one or more CPUs - */ -static void __init openpic2_maptimer(u_int timer, u_int cpumask) -{ - check_arg_timer(timer); - openpic2_write(&OpenPIC2->Global.Timer[timer].Destination, - cpumask); -} - -/* - * Initalize the interrupt source which will generate an NMI. - * This raises the interrupt's priority from 8 to 9. - * - * irq: The logical IRQ which generates an NMI. - */ -void __init -openpic2_init_nmi_irq(u_int irq) -{ - check_arg_irq(irq); - openpic2_safe_writefield(&ISR[irq - open_pic2_irq_offset]->Vector_Priority, - OPENPIC_PRIORITY_MASK, - 9 << OPENPIC_PRIORITY_SHIFT); -} - -/* - * - * All functions below take an offset'ed irq argument - * - */ - - -/* - * Enable/disable an external interrupt source - * - * Externally called, irq is an offseted system-wide interrupt number - */ -static void openpic2_enable_irq(u_int irq) -{ - volatile u_int *vpp; - - check_arg_irq(irq); - vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority; - openpic2_clearfield(vpp, OPENPIC_MASK); - /* make sure mask gets to controller before we return to user */ - do { - mb(); /* sync is probably useless here */ - } while (openpic2_readfield(vpp, OPENPIC_MASK)); -} - -static void openpic2_disable_irq(u_int irq) -{ - volatile u_int *vpp; - u32 vp; - - check_arg_irq(irq); - vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority; - openpic2_setfield(vpp, OPENPIC_MASK); - /* make sure mask gets to controller before we return to user */ - do { - mb(); /* sync is probably useless here */ - vp = openpic2_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY); - } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK)); -} - - -/* - * Initialize an interrupt source (and disable it!) - * - * irq: OpenPIC interrupt number - * pri: interrupt source priority - * vec: the vector it will produce - * pol: polarity (1 for positive, 0 for negative) - * sense: 1 for level, 0 for edge - */ -static void __init -openpic2_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense) -{ - openpic2_safe_writefield(&ISR[irq]->Vector_Priority, - OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | - OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK, - (pri << OPENPIC_PRIORITY_SHIFT) | vec | - (pol ? OPENPIC_POLARITY_POSITIVE : - OPENPIC_POLARITY_NEGATIVE) | - (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE)); -} - -/* - * Map an interrupt source to one or more CPUs - */ -static void openpic2_mapirq(u_int irq, u_int physmask, u_int keepmask) -{ - if (ISR[irq] == 0) - return; - if (keepmask != 0) - physmask |= openpic2_read(&ISR[irq]->Destination) & keepmask; - openpic2_write(&ISR[irq]->Destination, physmask); -} - -#ifdef notused -/* - * Set the sense for an interrupt source (and disable it!) - * - * sense: 1 for level, 0 for edge - */ -static void openpic2_set_sense(u_int irq, int sense) -{ - if (ISR[irq] != 0) - openpic2_safe_writefield(&ISR[irq]->Vector_Priority, - OPENPIC_SENSE_LEVEL, - (sense ? OPENPIC_SENSE_LEVEL : 0)); -} -#endif /* notused */ - -/* No spinlocks, should not be necessary with the OpenPIC - * (1 register = 1 interrupt and we have the desc lock). - */ -static void openpic2_ack_irq(unsigned int irq_nr) -{ - openpic2_disable_irq(irq_nr); - openpic2_eoi(); -} - -static void openpic2_end_irq(unsigned int irq_nr) -{ - if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - openpic2_enable_irq(irq_nr); -} - -int -openpic2_get_irq(void) -{ - int irq = openpic2_irq(); - - if (irq == (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset)) - irq = -1; - return irq; -} - -#ifdef CONFIG_PM - -/* - * We implement the IRQ controller as a sysdev and put it - * to sleep at powerdown stage (the callback is named suspend, - * but it's old semantics, for the Device Model, it's really - * powerdown). The possible problem is that another sysdev that - * happens to be suspend after this one will have interrupts off, - * that may be an issue... For now, this isn't an issue on pmac - * though... - */ - -static u32 save_ipi_vp[OPENPIC_NUM_IPI]; -static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES]; -static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES]; -static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS]; -static int openpic_suspend_count; - -static void openpic2_cached_enable_irq(u_int irq) -{ - check_arg_irq(irq); - save_irq_src_vp[irq - open_pic2_irq_offset] &= ~OPENPIC_MASK; -} - -static void openpic2_cached_disable_irq(u_int irq) -{ - check_arg_irq(irq); - save_irq_src_vp[irq - open_pic2_irq_offset] |= OPENPIC_MASK; -} - -/* WARNING: Can be called directly by the cpufreq code with NULL parameter, - * we need something better to deal with that... Maybe switch to S1 for - * cpufreq changes - */ -int openpic2_suspend(struct sys_device *sysdev, pm_message_t state) -{ - int i; - unsigned long flags; - - spin_lock_irqsave(&openpic2_setup_lock, flags); - - if (openpic_suspend_count++ > 0) { - spin_unlock_irqrestore(&openpic2_setup_lock, flags); - return 0; - } - - open_pic2.enable = openpic2_cached_enable_irq; - open_pic2.disable = openpic2_cached_disable_irq; - - for (i=0; iProcessor[i].Current_Task_Priority); - openpic2_writefield(&OpenPIC2->Processor[i].Current_Task_Priority, - OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf); - } - - for (i=0; iGlobal.IPI_Vector_Priority(i)); - for (i=0; iVector_Priority) & ~OPENPIC_ACTIVITY; - save_irq_src_dest[i] = openpic2_read(&ISR[i]->Destination); - } - - spin_unlock_irqrestore(&openpic2_setup_lock, flags); - - return 0; -} - -/* WARNING: Can be called directly by the cpufreq code with NULL parameter, - * we need something better to deal with that... Maybe switch to S1 for - * cpufreq changes - */ -int openpic2_resume(struct sys_device *sysdev) -{ - int i; - unsigned long flags; - u32 vppmask = OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | - OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK | - OPENPIC_MASK; - - spin_lock_irqsave(&openpic2_setup_lock, flags); - - if ((--openpic_suspend_count) > 0) { - spin_unlock_irqrestore(&openpic2_setup_lock, flags); - return 0; - } - - openpic2_reset(); - - /* OpenPIC sometimes seem to need some time to be fully back up... */ - do { - openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+open_pic2_irq_offset); - } while(openpic2_readfield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK) - != (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset)); - - openpic2_disable_8259_pass_through(); - - for (i=0; iGlobal.IPI_Vector_Priority(i), - save_ipi_vp[i]); - for (i=0; iDestination, save_irq_src_dest[i]); - openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]); - /* make sure mask gets to controller before we return to user */ - do { - openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]); - } while (openpic2_readfield(&ISR[i]->Vector_Priority, vppmask) - != (save_irq_src_vp[i] & vppmask)); - } - for (i=0; iProcessor[i].Current_Task_Priority, - save_cpu_task_pri[i]); - - open_pic2.enable = openpic2_enable_irq; - open_pic2.disable = openpic2_disable_irq; - - spin_unlock_irqrestore(&openpic2_setup_lock, flags); - - return 0; -} - -#endif /* CONFIG_PM */ - -/* HACK ALERT */ -static struct sysdev_class openpic2_sysclass = { - .name = "openpic2", -}; - -static struct sys_device device_openpic2 = { - .id = 0, - .cls = &openpic2_sysclass, -}; - -static struct sysdev_driver driver_openpic2 = { -#ifdef CONFIG_PM - .suspend = &openpic2_suspend, - .resume = &openpic2_resume, -#endif /* CONFIG_PM */ -}; - -static int __init init_openpic2_sysfs(void) -{ - int rc; - - if (!OpenPIC2_Addr) - return -ENODEV; - printk(KERN_DEBUG "Registering openpic2 with sysfs...\n"); - rc = sysdev_class_register(&openpic2_sysclass); - if (rc) { - printk(KERN_ERR "Failed registering openpic sys class\n"); - return -ENODEV; - } - rc = sysdev_register(&device_openpic2); - if (rc) { - printk(KERN_ERR "Failed registering openpic sys device\n"); - return -ENODEV; - } - rc = sysdev_driver_register(&openpic2_sysclass, &driver_openpic2); - if (rc) { - printk(KERN_ERR "Failed registering openpic sys driver\n"); - return -ENODEV; - } - return 0; -} - -subsys_initcall(init_openpic2_sysfs); - diff --git a/arch/ppc/syslib/open_pic_defs.h b/arch/ppc/syslib/open_pic_defs.h deleted file mode 100644 index 3a25de7cb572..000000000000 --- a/arch/ppc/syslib/open_pic_defs.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is based on the following documentation: - * - * The Open Programmable Interrupt Controller (PIC) - * Register Interface Specification Revision 1.2 - * - * Issue Date: October 1995 - * - * Issued jointly by Advanced Micro Devices and Cyrix Corporation - * - * AMD is a registered trademark of Advanced Micro Devices, Inc. - * Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc. - * All Rights Reserved. - * - * To receive a copy of this documentation, send an email to openpic@amd.com. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _LINUX_OPENPIC_H -#define _LINUX_OPENPIC_H - -#ifdef __KERNEL__ - - /* - * OpenPIC supports up to 2048 interrupt sources and up to 32 processors - */ - -#define OPENPIC_MAX_SOURCES 2048 -#define OPENPIC_MAX_PROCESSORS 32 -#define OPENPIC_MAX_ISU 16 - -#define OPENPIC_NUM_TIMERS 4 -#define OPENPIC_NUM_IPI 4 -#define OPENPIC_NUM_PRI 16 -#define OPENPIC_NUM_VECTORS 256 - - - - /* - * OpenPIC Registers are 32 bits and aligned on 128 bit boundaries - */ - -typedef struct _OpenPIC_Reg { - u_int Reg; /* Little endian! */ - char Pad[0xc]; -} OpenPIC_Reg; - - - /* - * Per Processor Registers - */ - -typedef struct _OpenPIC_Processor { - /* - * Private Shadow Registers (for SLiC backwards compatibility) - */ - u_int IPI0_Dispatch_Shadow; /* Write Only */ - char Pad1[0x4]; - u_int IPI0_Vector_Priority_Shadow; /* Read/Write */ - char Pad2[0x34]; - /* - * Interprocessor Interrupt Command Ports - */ - OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */ - /* - * Current Task Priority Register - */ - OpenPIC_Reg _Current_Task_Priority; /* Read/Write */ - char Pad3[0x10]; - /* - * Interrupt Acknowledge Register - */ - OpenPIC_Reg _Interrupt_Acknowledge; /* Read Only */ - /* - * End of Interrupt (EOI) Register - */ - OpenPIC_Reg _EOI; /* Read/Write */ - char Pad5[0xf40]; -} OpenPIC_Processor; - - - /* - * Timer Registers - */ - -typedef struct _OpenPIC_Timer { - OpenPIC_Reg _Current_Count; /* Read Only */ - OpenPIC_Reg _Base_Count; /* Read/Write */ - OpenPIC_Reg _Vector_Priority; /* Read/Write */ - OpenPIC_Reg _Destination; /* Read/Write */ -} OpenPIC_Timer; - - - /* - * Global Registers - */ - -typedef struct _OpenPIC_Global { - /* - * Feature Reporting Registers - */ - OpenPIC_Reg _Feature_Reporting0; /* Read Only */ - OpenPIC_Reg _Feature_Reporting1; /* Future Expansion */ - /* - * Global Configuration Registers - */ - OpenPIC_Reg _Global_Configuration0; /* Read/Write */ - OpenPIC_Reg _Global_Configuration1; /* Future Expansion */ - /* - * Vendor Specific Registers - */ - OpenPIC_Reg _Vendor_Specific[4]; - /* - * Vendor Identification Register - */ - OpenPIC_Reg _Vendor_Identification; /* Read Only */ - /* - * Processor Initialization Register - */ - OpenPIC_Reg _Processor_Initialization; /* Read/Write */ - /* - * IPI Vector/Priority Registers - */ - OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI]; /* Read/Write */ - /* - * Spurious Vector Register - */ - OpenPIC_Reg _Spurious_Vector; /* Read/Write */ - /* - * Global Timer Registers - */ - OpenPIC_Reg _Timer_Frequency; /* Read/Write */ - OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS]; - char Pad1[0xee00]; -} OpenPIC_Global; - - - /* - * Interrupt Source Registers - */ - -typedef struct _OpenPIC_Source { - OpenPIC_Reg _Vector_Priority; /* Read/Write */ - OpenPIC_Reg _Destination; /* Read/Write */ -} OpenPIC_Source, *OpenPIC_SourcePtr; - - - /* - * OpenPIC Register Map - */ - -struct OpenPIC { - char Pad1[0x1000]; - /* - * Global Registers - */ - OpenPIC_Global Global; - /* - * Interrupt Source Configuration Registers - */ - OpenPIC_Source Source[OPENPIC_MAX_SOURCES]; - /* - * Per Processor Registers - */ - OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS]; -}; - - /* - * Current Task Priority Register - */ - -#define OPENPIC_CURRENT_TASK_PRIORITY_MASK 0x0000000f - - /* - * Who Am I Register - */ - -#define OPENPIC_WHO_AM_I_ID_MASK 0x0000001f - - /* - * Feature Reporting Register 0 - */ - -#define OPENPIC_FEATURE_LAST_SOURCE_MASK 0x07ff0000 -#define OPENPIC_FEATURE_LAST_SOURCE_SHIFT 16 -#define OPENPIC_FEATURE_LAST_PROCESSOR_MASK 0x00001f00 -#define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT 8 -#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff - - /* - * Global Configuration Register 0 - */ - -#define OPENPIC_CONFIG_RESET 0x80000000 -#define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000 -#define OPENPIC_CONFIG_BASE_MASK 0x000fffff - - /* - * Global Configuration Register 1 - * This is the EICR on EPICs. - */ - -#define OPENPIC_EICR_S_CLK_MASK 0x70000000 -#define OPENPIC_EICR_SIE 0x08000000 - - /* - * Vendor Identification Register - */ - -#define OPENPIC_VENDOR_ID_STEPPING_MASK 0x00ff0000 -#define OPENPIC_VENDOR_ID_STEPPING_SHIFT 16 -#define OPENPIC_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 -#define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT 8 -#define OPENPIC_VENDOR_ID_VENDOR_ID_MASK 0x000000ff - - /* - * Vector/Priority Registers - */ - -#define OPENPIC_MASK 0x80000000 -#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ -#define OPENPIC_PRIORITY_MASK 0x000f0000 -#define OPENPIC_PRIORITY_SHIFT 16 -#define OPENPIC_VECTOR_MASK 0x000000ff - - - /* - * Interrupt Source Registers - */ - -#define OPENPIC_POLARITY_POSITIVE 0x00800000 -#define OPENPIC_POLARITY_NEGATIVE 0x00000000 -#define OPENPIC_POLARITY_MASK 0x00800000 -#define OPENPIC_SENSE_LEVEL 0x00400000 -#define OPENPIC_SENSE_EDGE 0x00000000 -#define OPENPIC_SENSE_MASK 0x00400000 - - - /* - * Timer Registers - */ - -#define OPENPIC_COUNT_MASK 0x7fffffff -#define OPENPIC_TIMER_TOGGLE 0x80000000 -#define OPENPIC_TIMER_COUNT_INHIBIT 0x80000000 - - - /* - * Aliases to make life simpler - */ - -/* Per Processor Registers */ -#define IPI_Dispatch(i) _IPI_Dispatch[i].Reg -#define Current_Task_Priority _Current_Task_Priority.Reg -#define Interrupt_Acknowledge _Interrupt_Acknowledge.Reg -#define EOI _EOI.Reg - -/* Global Registers */ -#define Feature_Reporting0 _Feature_Reporting0.Reg -#define Feature_Reporting1 _Feature_Reporting1.Reg -#define Global_Configuration0 _Global_Configuration0.Reg -#define Global_Configuration1 _Global_Configuration1.Reg -#define Vendor_Specific(i) _Vendor_Specific[i].Reg -#define Vendor_Identification _Vendor_Identification.Reg -#define Processor_Initialization _Processor_Initialization.Reg -#define IPI_Vector_Priority(i) _IPI_Vector_Priority[i].Reg -#define Spurious_Vector _Spurious_Vector.Reg -#define Timer_Frequency _Timer_Frequency.Reg - -/* Timer Registers */ -#define Current_Count _Current_Count.Reg -#define Base_Count _Base_Count.Reg -#define Vector_Priority _Vector_Priority.Reg -#define Destination _Destination.Reg - -/* Interrupt Source Registers */ -#define Vector_Priority _Vector_Priority.Reg -#define Destination _Destination.Reg - -#endif /* __KERNEL__ */ - -#endif /* _LINUX_OPENPIC_H */ diff --git a/arch/ppc/syslib/pci_auto.c b/arch/ppc/syslib/pci_auto.c deleted file mode 100644 index ee20a86fcc4b..000000000000 --- a/arch/ppc/syslib/pci_auto.c +++ /dev/null @@ -1,515 +0,0 @@ -/* - * PCI autoconfiguration library - * - * Author: Matt Porter - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * The CardBus support is very preliminary. Preallocating space is - * the way to go but will require some change in card services to - * make it useful. Eventually this will ensure that we can put - * multiple CB bridges behind multiple P2P bridges. For now, at - * least it ensures that we place the CB bridge BAR and assigned - * initial bus numbers. I definitely need to do something about - * the lack of 16-bit I/O support. -MDP - */ - -#include -#include -#include - -#include - -#define PCIAUTO_IDE_MODE_MASK 0x05 - -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -static int pciauto_upper_iospc; -static int pciauto_upper_memspc; - -void __init pciauto_setup_bars(struct pci_controller *hose, - int current_bus, - int pci_devfn, - int bar_limit) -{ - int bar_response, bar_size, bar_value; - int bar, addr_mask; - int * upper_limit; - int found_mem64 = 0; - - DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n", - current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) ); - - for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) { - /* Tickle the BAR and get the response */ - early_write_config_dword(hose, - current_bus, - pci_devfn, - bar, - 0xffffffff); - early_read_config_dword(hose, - current_bus, - pci_devfn, - bar, - &bar_response); - - /* If BAR is not implemented go to the next BAR */ - if (!bar_response) - continue; - - /* Check the BAR type and set our address mask */ - if (bar_response & PCI_BASE_ADDRESS_SPACE) { - addr_mask = PCI_BASE_ADDRESS_IO_MASK; - upper_limit = &pciauto_upper_iospc; - DBG("PCI Autoconfig: BAR 0x%x, I/O, ", bar); - } else { - if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == - PCI_BASE_ADDRESS_MEM_TYPE_64) - found_mem64 = 1; - - addr_mask = PCI_BASE_ADDRESS_MEM_MASK; - upper_limit = &pciauto_upper_memspc; - DBG("PCI Autoconfig: BAR 0x%x, Mem ", bar); - } - - /* Calculate requested size */ - bar_size = ~(bar_response & addr_mask) + 1; - - /* Allocate a base address */ - bar_value = (*upper_limit - bar_size) & ~(bar_size - 1); - - /* Write it out and update our limit */ - early_write_config_dword(hose, - current_bus, - pci_devfn, - bar, - bar_value); - - *upper_limit = bar_value; - - /* - * If we are a 64-bit decoder then increment to the - * upper 32 bits of the bar and force it to locate - * in the lower 4GB of memory. - */ - if (found_mem64) { - bar += 4; - early_write_config_dword(hose, - current_bus, - pci_devfn, - bar, - 0x00000000); - found_mem64 = 0; - } - - DBG("size=0x%x, address=0x%x\n", - bar_size, bar_value); - } - -} - -void __init pciauto_prescan_setup_bridge(struct pci_controller *hose, - int current_bus, - int pci_devfn, - int sub_bus, - int *iosave, - int *memsave) -{ - /* Configure bus number registers */ - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_PRIMARY_BUS, - current_bus); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_SECONDARY_BUS, - sub_bus + 1); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_SUBORDINATE_BUS, - 0xff); - - /* Round memory allocator to 1MB boundary */ - pciauto_upper_memspc &= ~(0x100000 - 1); - *memsave = pciauto_upper_memspc; - - /* Round I/O allocator to 4KB boundary */ - pciauto_upper_iospc &= ~(0x1000 - 1); - *iosave = pciauto_upper_iospc; - - /* Set up memory and I/O filter limits, assume 32-bit I/O space */ - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_MEMORY_LIMIT, - ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_IO_LIMIT, - ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8); - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_IO_LIMIT_UPPER16, - ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16); - - /* Zero upper 32 bits of prefetchable base/limit */ - early_write_config_dword(hose, - current_bus, - pci_devfn, - PCI_PREF_BASE_UPPER32, - 0); - early_write_config_dword(hose, - current_bus, - pci_devfn, - PCI_PREF_LIMIT_UPPER32, - 0); -} - -void __init pciauto_postscan_setup_bridge(struct pci_controller *hose, - int current_bus, - int pci_devfn, - int sub_bus, - int *iosave, - int *memsave) -{ - int cmdstat; - - /* Configure bus number registers */ - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_SUBORDINATE_BUS, - sub_bus); - - /* - * Round memory allocator to 1MB boundary. - * If no space used, allocate minimum. - */ - pciauto_upper_memspc &= ~(0x100000 - 1); - if (*memsave == pciauto_upper_memspc) - pciauto_upper_memspc -= 0x00100000; - - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_MEMORY_BASE, - pciauto_upper_memspc >> 16); - - /* Allocate 1MB for pre-fretch */ - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_PREF_MEMORY_LIMIT, - ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16); - - pciauto_upper_memspc -= 0x100000; - - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_PREF_MEMORY_BASE, - pciauto_upper_memspc >> 16); - - /* Round I/O allocator to 4KB boundary */ - pciauto_upper_iospc &= ~(0x1000 - 1); - if (*iosave == pciauto_upper_iospc) - pciauto_upper_iospc -= 0x1000; - - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_IO_BASE, - (pciauto_upper_iospc & 0x0000f000) >> 8); - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_IO_BASE_UPPER16, - pciauto_upper_iospc >> 16); - - /* Enable memory and I/O accesses, enable bus master */ - early_read_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - &cmdstat); - early_write_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - cmdstat | - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); -} - -void __init pciauto_prescan_setup_cardbus_bridge(struct pci_controller *hose, - int current_bus, - int pci_devfn, - int sub_bus, - int *iosave, - int *memsave) -{ - /* Configure bus number registers */ - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_PRIMARY_BUS, - current_bus); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_SECONDARY_BUS, - sub_bus + 1); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_SUBORDINATE_BUS, - 0xff); - - /* Round memory allocator to 4KB boundary */ - pciauto_upper_memspc &= ~(0x1000 - 1); - *memsave = pciauto_upper_memspc; - - /* Round I/O allocator to 4 byte boundary */ - pciauto_upper_iospc &= ~(0x4 - 1); - *iosave = pciauto_upper_iospc; - - /* Set up memory and I/O filter limits, assume 32-bit I/O space */ - early_write_config_dword(hose, - current_bus, - pci_devfn, - 0x20, - pciauto_upper_memspc - 1); - early_write_config_dword(hose, - current_bus, - pci_devfn, - 0x30, - pciauto_upper_iospc - 1); -} - -void __init pciauto_postscan_setup_cardbus_bridge(struct pci_controller *hose, - int current_bus, - int pci_devfn, - int sub_bus, - int *iosave, - int *memsave) -{ - int cmdstat; - - /* - * Configure subordinate bus number. The PCI subsystem - * bus scan will renumber buses (reserving three additional - * for this PCI<->CardBus bridge for the case where a CardBus - * adapter contains a P2P or CB2CB bridge. - */ - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_SUBORDINATE_BUS, - sub_bus); - - /* - * Reserve an additional 4MB for mem space and 16KB for - * I/O space. This should cover any additional space - * requirement of unusual CardBus devices with - * additional bridges that can consume more address space. - * - * Although pcmcia-cs currently will reprogram bridge - * windows, the goal is to add an option to leave them - * alone and use the bridge window ranges as the regions - * that are searched for free resources upon hot-insertion - * of a device. This will allow a PCI<->CardBus bridge - * configured by this routine to happily live behind a - * P2P bridge in a system. - */ - pciauto_upper_memspc -= 0x00400000; - pciauto_upper_iospc -= 0x00004000; - - /* Round memory allocator to 4KB boundary */ - pciauto_upper_memspc &= ~(0x1000 - 1); - - early_write_config_dword(hose, - current_bus, - pci_devfn, - 0x1c, - pciauto_upper_memspc); - - /* Round I/O allocator to 4 byte boundary */ - pciauto_upper_iospc &= ~(0x4 - 1); - early_write_config_dword(hose, - current_bus, - pci_devfn, - 0x2c, - pciauto_upper_iospc); - - /* Enable memory and I/O accesses, enable bus master */ - early_read_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - &cmdstat); - early_write_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - cmdstat | - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); -} - -int __init pciauto_bus_scan(struct pci_controller *hose, int current_bus) -{ - int sub_bus, pci_devfn, pci_class, cmdstat, found_multi = 0; - unsigned short vid; - unsigned char header_type; - - /* - * Fetch our I/O and memory space upper boundaries used - * to allocated base addresses on this hose. - */ - if (current_bus == hose->first_busno) { - pciauto_upper_iospc = hose->io_space.end + 1; - pciauto_upper_memspc = hose->mem_space.end + 1; - } - - sub_bus = current_bus; - - for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { - /* Skip our host bridge */ - if ( (current_bus == hose->first_busno) && (pci_devfn == 0) ) - continue; - - if (PCI_FUNC(pci_devfn) && !found_multi) - continue; - - /* If config space read fails from this device, move on */ - if (early_read_config_byte(hose, - current_bus, - pci_devfn, - PCI_HEADER_TYPE, - &header_type)) - continue; - - if (!PCI_FUNC(pci_devfn)) - found_multi = header_type & 0x80; - - early_read_config_word(hose, - current_bus, - pci_devfn, - PCI_VENDOR_ID, - &vid); - - if (vid != 0xffff) { - early_read_config_dword(hose, - current_bus, - pci_devfn, - PCI_CLASS_REVISION, &pci_class); - if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) { - int iosave, memsave; - - DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn)); - /* Allocate PCI I/O and/or memory space */ - pciauto_setup_bars(hose, - current_bus, - pci_devfn, - PCI_BASE_ADDRESS_1); - - pciauto_prescan_setup_bridge(hose, - current_bus, - pci_devfn, - sub_bus, - &iosave, - &memsave); - sub_bus = pciauto_bus_scan(hose, sub_bus+1); - pciauto_postscan_setup_bridge(hose, - current_bus, - pci_devfn, - sub_bus, - &iosave, - &memsave); - } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) { - int iosave, memsave; - - DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn)); - /* Place CardBus Socket/ExCA registers */ - pciauto_setup_bars(hose, - current_bus, - pci_devfn, - PCI_BASE_ADDRESS_0); - - pciauto_prescan_setup_cardbus_bridge(hose, - current_bus, - pci_devfn, - sub_bus, - &iosave, - &memsave); - sub_bus = pciauto_bus_scan(hose, sub_bus+1); - pciauto_postscan_setup_cardbus_bridge(hose, - current_bus, - pci_devfn, - sub_bus, - &iosave, - &memsave); - } else { - if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) { - unsigned char prg_iface; - - early_read_config_byte(hose, - current_bus, - pci_devfn, - PCI_CLASS_PROG, - &prg_iface); - if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { - DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n"); - continue; - } - } - /* Allocate PCI I/O and/or memory space */ - pciauto_setup_bars(hose, - current_bus, - pci_devfn, - PCI_BASE_ADDRESS_5); - - /* - * Enable some standard settings - */ - early_read_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - &cmdstat); - early_write_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - cmdstat | - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_LATENCY_TIMER, - 0x80); - } - } - } - return sub_bus; -} diff --git a/arch/ppc/syslib/ppc403_pic.c b/arch/ppc/syslib/ppc403_pic.c deleted file mode 100644 index c3b7b8bfbcfe..000000000000 --- a/arch/ppc/syslib/ppc403_pic.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * - * Copyright (c) 1999 Grant Erickson - * - * Module name: ppc403_pic.c - * - * Description: - * Interrupt controller driver for PowerPC 403-based processors. - */ - -/* - * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has - * 32 possible interrupts, a majority of which are not implemented on - * all cores. There are six configurable, external interrupt pins and - * there are eight internal interrupts for the on-chip serial port - * (SPU), DMA controller, and JTAG controller. - * - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* Function Prototypes */ - -static void ppc403_aic_enable(unsigned int irq); -static void ppc403_aic_disable(unsigned int irq); -static void ppc403_aic_disable_and_ack(unsigned int irq); - -static struct hw_interrupt_type ppc403_aic = { - .typename = "403GC AIC", - .enable = ppc403_aic_enable, - .disable = ppc403_aic_disable, - .ack = ppc403_aic_disable_and_ack, -}; - -int -ppc403_pic_get_irq(void) -{ - int irq; - unsigned long bits; - - /* - * Only report the status of those interrupts that are actually - * enabled. - */ - - bits = mfdcr(DCRN_EXISR) & mfdcr(DCRN_EXIER); - - /* - * Walk through the interrupts from highest priority to lowest, and - * report the first pending interrupt found. - * We want PPC, not C bit numbering, so just subtract the ffs() - * result from 32. - */ - irq = 32 - ffs(bits); - - if (irq == NR_AIC_IRQS) - irq = -1; - - return (irq); -} - -static void -ppc403_aic_enable(unsigned int irq) -{ - int bit, word; - - bit = irq & 0x1f; - word = irq >> 5; - - ppc_cached_irq_mask[word] |= (1 << (31 - bit)); - mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]); -} - -static void -ppc403_aic_disable(unsigned int irq) -{ - int bit, word; - - bit = irq & 0x1f; - word = irq >> 5; - - ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]); -} - -static void -ppc403_aic_disable_and_ack(unsigned int irq) -{ - int bit, word; - - bit = irq & 0x1f; - word = irq >> 5; - - ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]); - mtdcr(DCRN_EXISR, (1 << (31 - bit))); -} - -void __init -ppc4xx_pic_init(void) -{ - int i; - - /* - * Disable all external interrupts until they are - * explicitly requested. - */ - ppc_cached_irq_mask[0] = 0; - - mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]); - - ppc_md.get_irq = ppc403_pic_get_irq; - - for (i = 0; i < NR_IRQS; i++) - irq_desc[i].chip = &ppc403_aic; -} diff --git a/arch/ppc/syslib/ppc405_pci.c b/arch/ppc/syslib/ppc405_pci.c deleted file mode 100644 index 9e9035693bfa..000000000000 --- a/arch/ppc/syslib/ppc405_pci.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Authors: Frank Rowand , - * Debbie Chu , or source@mvista.com - * Further modifications by Armin Kuster - * - * 2000 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Based on arch/ppc/kernel/indirect.c, Copyright (C) 1998 Gabriel Paubert. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -extern void bios_fixup(struct pci_controller *, struct pcil0_regs *); -extern int ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, - unsigned char pin); - -void -ppc405_pcibios_fixup_resources(struct pci_dev *dev) -{ - int i; - unsigned long max_host_addr; - unsigned long min_host_addr; - struct resource *res; - - /* - * openbios puts some graphics cards in the same range as the host - * controller uses to map to SDRAM. Fix it. - */ - - min_host_addr = 0; - max_host_addr = PPC405_PCI_MEM_BASE - 1; - - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - res = dev->resource + i; - if (!res->start) - continue; - if ((res->flags & IORESOURCE_MEM) && - (((res->start >= min_host_addr) - && (res->start <= max_host_addr)) - || ((res->end >= min_host_addr) - && (res->end <= max_host_addr)) - || ((res->start < min_host_addr) - && (res->end > max_host_addr)) - ) - ) { - - /* force pcibios_assign_resources() to assign a new address */ - res->end -= res->start; - res->start = 0; - } - } -} - -static int -ppc4xx_exclude_device(unsigned char bus, unsigned char devfn) -{ - /* We prevent us from seeing ourselves to avoid having - * the kernel try to remap our BAR #1 and fuck up bus - * master from external PCI devices - */ - return (bus == 0 && devfn == 0); -} - -void -ppc4xx_find_bridges(void) -{ - struct pci_controller *hose_a; - struct pcil0_regs *pcip; - unsigned int tmp_addr; - unsigned int tmp_size; - unsigned int reg_index; - unsigned int new_pmm_max = 0; - unsigned int new_pmm_min = 0; - - isa_io_base = 0; - isa_mem_base = 0; - pci_dram_offset = 0; - - /* Setup PCI32 hose */ - hose_a = pcibios_alloc_controller(); - if (!hose_a) - return; - setup_indirect_pci(hose_a, PPC405_PCI_CONFIG_ADDR, - PPC405_PCI_CONFIG_DATA); - - pcip = ioremap(PPC4xx_PCI_LCFG_PADDR, PAGE_SIZE); - if (pcip != NULL) { - -#if defined(CONFIG_BIOS_FIXUP) - bios_fixup(hose_a, pcip); -#endif - new_pmm_min = 0xffffffff; - for (reg_index = 0; reg_index < 3; reg_index++) { - tmp_size = in_le32(&pcip->pmm[reg_index].ma); // mask & attrs - /* test the enable bit */ - if ((tmp_size & 0x1) == 0) - continue; - tmp_addr = in_le32(&pcip->pmm[reg_index].pcila); // PCI addr - if (tmp_addr < PPC405_PCI_PHY_MEM_BASE) { - printk(KERN_DEBUG - "Disabling mapping to PCI mem addr 0x%8.8x\n", - tmp_addr); - out_le32(&pcip->pmm[reg_index].ma, tmp_size & ~1); // *_PMMOMA - continue; - } - tmp_addr = in_le32(&pcip->pmm[reg_index].la); // *_PMMOLA - if (tmp_addr < new_pmm_min) - new_pmm_min = tmp_addr; - tmp_addr = tmp_addr + - (0xffffffff - (tmp_size & 0xffffc000)); - if (tmp_addr > PPC405_PCI_UPPER_MEM) { - new_pmm_max = tmp_addr; // PPC405_PCI_UPPER_MEM - } else { - new_pmm_max = PPC405_PCI_UPPER_MEM; - } - - } // for - - iounmap(pcip); - } - - hose_a->first_busno = 0; - hose_a->last_busno = 0xff; - hose_a->pci_mem_offset = 0; - - /* Setup bridge memory/IO ranges & resources - * TODO: Handle firmware setting up a legacy ISA mem base - */ - hose_a->io_space.start = PPC405_PCI_LOWER_IO; - hose_a->io_space.end = PPC405_PCI_UPPER_IO; - hose_a->mem_space.start = new_pmm_min; - hose_a->mem_space.end = new_pmm_max; - hose_a->io_base_phys = PPC405_PCI_PHY_IO_BASE; - hose_a->io_base_virt = ioremap(hose_a->io_base_phys, 0x10000); - hose_a->io_resource.start = 0; - hose_a->io_resource.end = PPC405_PCI_UPPER_IO - PPC405_PCI_LOWER_IO; - hose_a->io_resource.flags = IORESOURCE_IO; - hose_a->io_resource.name = "PCI I/O"; - hose_a->mem_resources[0].start = new_pmm_min; - hose_a->mem_resources[0].end = new_pmm_max; - hose_a->mem_resources[0].flags = IORESOURCE_MEM; - hose_a->mem_resources[0].name = "PCI Memory"; - isa_io_base = (int) hose_a->io_base_virt; - isa_mem_base = 0; /* ISA not implemented */ - ISA_DMA_THRESHOLD = 0x00ffffff; /* ??? ISA not implemented */ - - /* Scan busses & initial setup by pci_auto */ - hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); - hose_a->last_busno = 0; - - /* Setup ppc_md */ - ppc_md.pcibios_fixup = NULL; - ppc_md.pci_exclude_device = ppc4xx_exclude_device; - ppc_md.pcibios_fixup_resources = ppc405_pcibios_fixup_resources; - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = ppc405_map_irq; -} diff --git a/arch/ppc/syslib/ppc440spe_pcie.c b/arch/ppc/syslib/ppc440spe_pcie.c deleted file mode 100644 index dd5d4b958c31..000000000000 --- a/arch/ppc/syslib/ppc440spe_pcie.c +++ /dev/null @@ -1,441 +0,0 @@ -/* - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * Roland Dreier - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include "ppc440spe_pcie.h" - -static int -pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) -{ - struct pci_controller *hose = bus->sysdata; - - if (PCI_SLOT(devfn) != 1) - return PCIBIOS_DEVICE_NOT_FOUND; - - offset += devfn << 12; - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - switch (len) { - case 1: - *val = in_8(hose->cfg_data + offset); - break; - case 2: - *val = in_le16(hose->cfg_data + offset); - break; - default: - *val = in_le32(hose->cfg_data + offset); - break; - } - - if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset); - - return PCIBIOS_SUCCESSFUL; -} - -static int -pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) -{ - struct pci_controller *hose = bus->sysdata; - - if (PCI_SLOT(devfn) != 1) - return PCIBIOS_DEVICE_NOT_FOUND; - - offset += devfn << 12; - - switch (len) { - case 1: - out_8(hose->cfg_data + offset, val); - break; - case 2: - out_le16(hose->cfg_data + offset, val); - break; - default: - out_le32(hose->cfg_data + offset, val); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops pcie_pci_ops = -{ - .read = pcie_read_config, - .write = pcie_write_config -}; - -enum { - PTYPE_ENDPOINT = 0x0, - PTYPE_LEGACY_ENDPOINT = 0x1, - PTYPE_ROOT_PORT = 0x4, - - LNKW_X1 = 0x1, - LNKW_X4 = 0x4, - LNKW_X8 = 0x8 -}; - -static void check_error(void) -{ - u32 valPE0, valPE1, valPE2; - - /* SDR0_PEGPLLLCT1 reset */ - if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { - printk(KERN_INFO "PCIE: SDR0_PEGPLLLCT1 reset error 0x%8x\n", valPE0); - } - - valPE0 = SDR_READ(PESDR0_RCSSET); - valPE1 = SDR_READ(PESDR1_RCSSET); - valPE2 = SDR_READ(PESDR2_RCSSET); - - /* SDR0_PExRCSSET rstgu */ - if ( !(valPE0 & 0x01000000) || - !(valPE1 & 0x01000000) || - !(valPE2 & 0x01000000)) { - printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n"); - } - - /* SDR0_PExRCSSET rstdl */ - if ( !(valPE0 & 0x00010000) || - !(valPE1 & 0x00010000) || - !(valPE2 & 0x00010000)) { - printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n"); - } - - /* SDR0_PExRCSSET rstpyn */ - if ( (valPE0 & 0x00001000) || - (valPE1 & 0x00001000) || - (valPE2 & 0x00001000)) { - printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n"); - } - - /* SDR0_PExRCSSET hldplb */ - if ( (valPE0 & 0x10000000) || - (valPE1 & 0x10000000) || - (valPE2 & 0x10000000)) { - printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n"); - } - - /* SDR0_PExRCSSET rdy */ - if ( (valPE0 & 0x00100000) || - (valPE1 & 0x00100000) || - (valPE2 & 0x00100000)) { - printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n"); - } - - /* SDR0_PExRCSSET shutdown */ - if ( (valPE0 & 0x00000100) || - (valPE1 & 0x00000100) || - (valPE2 & 0x00000100)) { - printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n"); - } -} - -/* - * Initialize PCI Express core as described in User Manual section 27.12.1 - */ -int ppc440spe_init_pcie(void) -{ - /* Set PLL clock receiver to LVPECL */ - SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); - - check_error(); - - printk(KERN_INFO "PCIE initialization OK\n"); - - if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) - printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", - SDR_READ(PESDR0_PLLLCT2)); - - /* De-assert reset of PCIe PLL, wait for lock */ - SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); - udelay(3); - - return 0; -} - -int ppc440spe_init_pcie_rootport(int port) -{ - static int core_init; - void __iomem *utl_base; - u32 val = 0; - int i; - - if (!core_init) { - ++core_init; - i = ppc440spe_init_pcie(); - if (i) - return i; - } - - /* - * Initialize various parts of the PCI Express core for our port: - * - * - Set as a root port and enable max width - * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). - * - Set up UTL configuration. - * - Increase SERDES drive strength to levels suggested by AMCC. - * - De-assert RSTPYN, RSTDL and RSTGU. - */ - switch (port) { - case 0: - SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); - - SDR_WRITE(PESDR0_UTLSET1, 0x21222222); - SDR_WRITE(PESDR0_UTLSET2, 0x11000000); - - SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); - - SDR_WRITE(PESDR0_RCSSET, - (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 1: - SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); - - SDR_WRITE(PESDR1_UTLSET1, 0x21222222); - SDR_WRITE(PESDR1_UTLSET2, 0x11000000); - - SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); - - SDR_WRITE(PESDR1_RCSSET, - (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 2: - SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); - - SDR_WRITE(PESDR2_UTLSET1, 0x21222222); - SDR_WRITE(PESDR2_UTLSET2, 0x11000000); - - SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); - - SDR_WRITE(PESDR2_RCSSET, - (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - } - - mdelay(1000); - - switch (port) { - case 0: val = SDR_READ(PESDR0_RCSSTS); break; - case 1: val = SDR_READ(PESDR1_RCSSTS); break; - case 2: val = SDR_READ(PESDR2_RCSSTS); break; - } - - if (!(val & (1 << 20))) - printk(KERN_INFO "PCIE%d: PGRST inactive\n", port); - else - printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val); - - switch (port) { - case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break; - case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break; - case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break; - } - - /* - * Map UTL registers at 0xc_1000_0n00 - */ - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); - mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); - break; - - case 1: - mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); - mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); - break; - - case 2: - mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); - mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); - } - - utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100); - - /* - * Set buffer allocations and then assert VRB and TXE. - */ - out_be32(utl_base + PEUTL_OUTTR, 0x08000000); - out_be32(utl_base + PEUTL_INTR, 0x02000000); - out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); - out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); - out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); - out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); - out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); - out_be32(utl_base + PEUTL_PCTL, 0x80800066); - - iounmap(utl_base); - - /* - * We map PCI Express configuration access into the 512MB regions - * PCIE0: 0xc_4000_0000 - * PCIE1: 0xc_8000_0000 - * PCIE2: 0xc_c000_0000 - */ - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); - mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ - break; - - case 1: - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); - mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ - break; - - case 2: - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); - mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ - break; - } - - /* - * Check for VC0 active and assert RDY. - */ - switch (port) { - case 0: - if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) - printk(KERN_WARNING "PCIE0: VC0 not active\n"); - SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); - break; - case 1: - if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) - printk(KERN_WARNING "PCIE0: VC0 not active\n"); - SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); - break; - case 2: - if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) - printk(KERN_WARNING "PCIE0: VC0 not active\n"); - SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); - break; - } - -#if 0 - /* Dump all config regs */ - for (i = 0x300; i <= 0x320; ++i) - printk("[%04x] 0x%08x\n", i, SDR_READ(i)); - for (i = 0x340; i <= 0x353; ++i) - printk("[%04x] 0x%08x\n", i, SDR_READ(i)); - for (i = 0x370; i <= 0x383; ++i) - printk("[%04x] 0x%08x\n", i, SDR_READ(i)); - for (i = 0x3a0; i <= 0x3a2; ++i) - printk("[%04x] 0x%08x\n", i, SDR_READ(i)); - for (i = 0x3c0; i <= 0x3c3; ++i) - printk("[%04x] 0x%08x\n", i, SDR_READ(i)); -#endif - - mdelay(100); - - return 0; -} - -void ppc440spe_setup_pcie(struct pci_controller *hose, int port) -{ - void __iomem *mbase; - - /* - * Map 16MB, which is enough for 4 bits of bus # - */ - hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000, - 1 << 24); - hose->ops = &pcie_pci_ops; - - /* - * Set bus numbers on our root port - */ - mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096); - out_8(mbase + PCI_PRIMARY_BUS, 0); - out_8(mbase + PCI_SECONDARY_BUS, 0); - - /* - * Set up outbound translation to hose->mem_space from PLB - * addresses at an offset of 0xd_0000_0000. We set the low - * bits of the mask to 11 to turn off splitting into 8 - * subregions and to enable the outbound translation. - */ - out_le32(mbase + PECFG_POM0LAH, 0); - out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start); - - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(hose->mem_space.end - hose->mem_space.start) | 3); - break; - case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(hose->mem_space.end - hose->mem_space.start) | 3); - - break; - case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(hose->mem_space.end - hose->mem_space.start) | 3); - break; - } - - /* Set up 16GB inbound memory window at 0 */ - out_le32(mbase + PCI_BASE_ADDRESS_0, 0); - out_le32(mbase + PCI_BASE_ADDRESS_1, 0); - out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); - out_le32(mbase + PECFG_BAR0LMPA, 0); - out_le32(mbase + PECFG_PIM0LAL, 0); - out_le32(mbase + PECFG_PIM0LAH, 0); - out_le32(mbase + PECFG_PIMEN, 0x1); - - /* Enable I/O, Mem, and Busmaster cycles */ - out_le16(mbase + PCI_COMMAND, - in_le16(mbase + PCI_COMMAND) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - iounmap(mbase); -} diff --git a/arch/ppc/syslib/ppc440spe_pcie.h b/arch/ppc/syslib/ppc440spe_pcie.h deleted file mode 100644 index 55b765ad3272..000000000000 --- a/arch/ppc/syslib/ppc440spe_pcie.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * Roland Dreier - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __PPC_SYSLIB_PPC440SPE_PCIE_H -#define __PPC_SYSLIB_PPC440SPE_PCIE_H - -#define DCRN_SDR0_CFGADDR 0x00e -#define DCRN_SDR0_CFGDATA 0x00f - -#define DCRN_PCIE0_BASE 0x100 -#define DCRN_PCIE1_BASE 0x120 -#define DCRN_PCIE2_BASE 0x140 -#define PCIE0 DCRN_PCIE0_BASE -#define PCIE1 DCRN_PCIE1_BASE -#define PCIE2 DCRN_PCIE2_BASE - -#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) -#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) -#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) -#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) -#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) -#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) -#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) -#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) -#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) -#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) -#define DCRN_PEGPL_REGBAH(base) (base + 0x12) -#define DCRN_PEGPL_REGBAL(base) (base + 0x13) -#define DCRN_PEGPL_REGMSK(base) (base + 0x14) -#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) - -/* - * System DCRs (SDRs) - */ -#define PESDR0_PLLLCT1 0x03a0 -#define PESDR0_PLLLCT2 0x03a1 -#define PESDR0_PLLLCT3 0x03a2 - -#define PESDR0_UTLSET1 0x0300 -#define PESDR0_UTLSET2 0x0301 -#define PESDR0_DLPSET 0x0302 -#define PESDR0_LOOP 0x0303 -#define PESDR0_RCSSET 0x0304 -#define PESDR0_RCSSTS 0x0305 -#define PESDR0_HSSL0SET1 0x0306 -#define PESDR0_HSSL0SET2 0x0307 -#define PESDR0_HSSL0STS 0x0308 -#define PESDR0_HSSL1SET1 0x0309 -#define PESDR0_HSSL1SET2 0x030a -#define PESDR0_HSSL1STS 0x030b -#define PESDR0_HSSL2SET1 0x030c -#define PESDR0_HSSL2SET2 0x030d -#define PESDR0_HSSL2STS 0x030e -#define PESDR0_HSSL3SET1 0x030f -#define PESDR0_HSSL3SET2 0x0310 -#define PESDR0_HSSL3STS 0x0311 -#define PESDR0_HSSL4SET1 0x0312 -#define PESDR0_HSSL4SET2 0x0313 -#define PESDR0_HSSL4STS 0x0314 -#define PESDR0_HSSL5SET1 0x0315 -#define PESDR0_HSSL5SET2 0x0316 -#define PESDR0_HSSL5STS 0x0317 -#define PESDR0_HSSL6SET1 0x0318 -#define PESDR0_HSSL6SET2 0x0319 -#define PESDR0_HSSL6STS 0x031a -#define PESDR0_HSSL7SET1 0x031b -#define PESDR0_HSSL7SET2 0x031c -#define PESDR0_HSSL7STS 0x031d -#define PESDR0_HSSCTLSET 0x031e -#define PESDR0_LANE_ABCD 0x031f -#define PESDR0_LANE_EFGH 0x0320 - -#define PESDR1_UTLSET1 0x0340 -#define PESDR1_UTLSET2 0x0341 -#define PESDR1_DLPSET 0x0342 -#define PESDR1_LOOP 0x0343 -#define PESDR1_RCSSET 0x0344 -#define PESDR1_RCSSTS 0x0345 -#define PESDR1_HSSL0SET1 0x0346 -#define PESDR1_HSSL0SET2 0x0347 -#define PESDR1_HSSL0STS 0x0348 -#define PESDR1_HSSL1SET1 0x0349 -#define PESDR1_HSSL1SET2 0x034a -#define PESDR1_HSSL1STS 0x034b -#define PESDR1_HSSL2SET1 0x034c -#define PESDR1_HSSL2SET2 0x034d -#define PESDR1_HSSL2STS 0x034e -#define PESDR1_HSSL3SET1 0x034f -#define PESDR1_HSSL3SET2 0x0350 -#define PESDR1_HSSL3STS 0x0351 -#define PESDR1_HSSCTLSET 0x0352 -#define PESDR1_LANE_ABCD 0x0353 - -#define PESDR2_UTLSET1 0x0370 -#define PESDR2_UTLSET2 0x0371 -#define PESDR2_DLPSET 0x0372 -#define PESDR2_LOOP 0x0373 -#define PESDR2_RCSSET 0x0374 -#define PESDR2_RCSSTS 0x0375 -#define PESDR2_HSSL0SET1 0x0376 -#define PESDR2_HSSL0SET2 0x0377 -#define PESDR2_HSSL0STS 0x0378 -#define PESDR2_HSSL1SET1 0x0379 -#define PESDR2_HSSL1SET2 0x037a -#define PESDR2_HSSL1STS 0x037b -#define PESDR2_HSSL2SET1 0x037c -#define PESDR2_HSSL2SET2 0x037d -#define PESDR2_HSSL2STS 0x037e -#define PESDR2_HSSL3SET1 0x037f -#define PESDR2_HSSL3SET2 0x0380 -#define PESDR2_HSSL3STS 0x0381 -#define PESDR2_HSSCTLSET 0x0382 -#define PESDR2_LANE_ABCD 0x0383 - -/* - * UTL register offsets - */ -#define PEUTL_PBBSZ 0x20 -#define PEUTL_OPDBSZ 0x68 -#define PEUTL_IPHBSZ 0x70 -#define PEUTL_IPDBSZ 0x78 -#define PEUTL_OUTTR 0x90 -#define PEUTL_INTR 0x98 -#define PEUTL_PCTL 0xa0 -#define PEUTL_RCIRQEN 0xb8 - -/* - * Config space register offsets - */ -#define PECFG_BAR0LMPA 0x210 -#define PECFG_BAR0HMPA 0x214 -#define PECFG_PIMEN 0x33c -#define PECFG_PIM0LAL 0x340 -#define PECFG_PIM0LAH 0x344 -#define PECFG_POM0LAL 0x380 -#define PECFG_POM0LAH 0x384 - -int ppc440spe_init_pcie(void); -int ppc440spe_init_pcie_rootport(int port); -void ppc440spe_setup_pcie(struct pci_controller *hose, int port); - -#endif /* __PPC_SYSLIB_PPC440SPE_PCIE_H */ diff --git a/arch/ppc/syslib/ppc4xx_dma.c b/arch/ppc/syslib/ppc4xx_dma.c deleted file mode 100644 index bd301868996b..000000000000 --- a/arch/ppc/syslib/ppc4xx_dma.c +++ /dev/null @@ -1,710 +0,0 @@ -/* - * IBM PPC4xx DMA engine core library - * - * Copyright 2000-2004 MontaVista Software Inc. - * - * Cleaned up and converted to new DCR access - * Matt Porter - * - * Original code by Armin Kuster - * and Pete Popov - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -ppc_dma_ch_t dma_channels[MAX_PPC4xx_DMA_CHANNELS]; - -int -ppc4xx_get_dma_status(void) -{ - return (mfdcr(DCRN_DMASR)); -} - -void -ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr) -{ - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("set_src_addr: bad channel: %d\n", dmanr); - return; - } - -#ifdef PPC4xx_DMA_64BIT - mtdcr(DCRN_DMASAH0 + dmanr*2, (u32)(src_addr >> 32)); -#else - mtdcr(DCRN_DMASA0 + dmanr*2, (u32)src_addr); -#endif -} - -void -ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr) -{ - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("set_dst_addr: bad channel: %d\n", dmanr); - return; - } - -#ifdef PPC4xx_DMA_64BIT - mtdcr(DCRN_DMADAH0 + dmanr*2, (u32)(dst_addr >> 32)); -#else - mtdcr(DCRN_DMADA0 + dmanr*2, (u32)dst_addr); -#endif -} - -void -ppc4xx_enable_dma(unsigned int dmanr) -{ - unsigned int control; - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - unsigned int status_bits[] = { DMA_CS0 | DMA_TS0 | DMA_CH0_ERR, - DMA_CS1 | DMA_TS1 | DMA_CH1_ERR, - DMA_CS2 | DMA_TS2 | DMA_CH2_ERR, - DMA_CS3 | DMA_TS3 | DMA_CH3_ERR}; - - if (p_dma_ch->in_use) { - printk("enable_dma: channel %d in use\n", dmanr); - return; - } - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("enable_dma: bad channel: %d\n", dmanr); - return; - } - - if (p_dma_ch->mode == DMA_MODE_READ) { - /* peripheral to memory */ - ppc4xx_set_src_addr(dmanr, 0); - ppc4xx_set_dst_addr(dmanr, p_dma_ch->addr); - } else if (p_dma_ch->mode == DMA_MODE_WRITE) { - /* memory to peripheral */ - ppc4xx_set_src_addr(dmanr, p_dma_ch->addr); - ppc4xx_set_dst_addr(dmanr, 0); - } - - /* for other xfer modes, the addresses are already set */ - control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8)); - - control &= ~(DMA_TM_MASK | DMA_TD); /* clear all mode bits */ - if (p_dma_ch->mode == DMA_MODE_MM) { - /* software initiated memory to memory */ - control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE; - } - - mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control); - - /* - * Clear the CS, TS, RI bits for the channel from DMASR. This - * has been observed to happen correctly only after the mode and - * ETD/DCE bits in DMACRx are set above. Must do this before - * enabling the channel. - */ - - mtdcr(DCRN_DMASR, status_bits[dmanr]); - - /* - * For device-paced transfers, Terminal Count Enable apparently - * must be on, and this must be turned on after the mode, etc. - * bits are cleared above (at least on Redwood-6). - */ - - if ((p_dma_ch->mode == DMA_MODE_MM_DEVATDST) || - (p_dma_ch->mode == DMA_MODE_MM_DEVATSRC)) - control |= DMA_TCE_ENABLE; - - /* - * Now enable the channel. - */ - - control |= (p_dma_ch->mode | DMA_CE_ENABLE); - - mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control); - - p_dma_ch->in_use = 1; -} - -void -ppc4xx_disable_dma(unsigned int dmanr) -{ - unsigned int control; - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - - if (!p_dma_ch->in_use) { - printk("disable_dma: channel %d not in use\n", dmanr); - return; - } - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("disable_dma: bad channel: %d\n", dmanr); - return; - } - - control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8)); - control &= ~DMA_CE_ENABLE; - mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control); - - p_dma_ch->in_use = 0; -} - -/* - * Sets the dma mode for single DMA transfers only. - * For scatter/gather transfers, the mode is passed to the - * alloc_dma_handle() function as one of the parameters. - * - * The mode is simply saved and used later. This allows - * the driver to call set_dma_mode() and set_dma_addr() in - * any order. - * - * Valid mode values are: - * - * DMA_MODE_READ peripheral to memory - * DMA_MODE_WRITE memory to peripheral - * DMA_MODE_MM memory to memory - * DMA_MODE_MM_DEVATSRC device-paced memory to memory, device at src - * DMA_MODE_MM_DEVATDST device-paced memory to memory, device at dst - */ -int -ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode) -{ - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("set_dma_mode: bad channel 0x%x\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - p_dma_ch->mode = mode; - - return DMA_STATUS_GOOD; -} - -/* - * Sets the DMA Count register. Note that 'count' is in bytes. - * However, the DMA Count register counts the number of "transfers", - * where each transfer is equal to the bus width. Thus, count - * MUST be a multiple of the bus width. - */ -void -ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count) -{ - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - -#ifdef DEBUG_4xxDMA - { - int error = 0; - switch (p_dma_ch->pwidth) { - case PW_8: - break; - case PW_16: - if (count & 0x1) - error = 1; - break; - case PW_32: - if (count & 0x3) - error = 1; - break; - case PW_64: - if (count & 0x7) - error = 1; - break; - default: - printk("set_dma_count: invalid bus width: 0x%x\n", - p_dma_ch->pwidth); - return; - } - if (error) - printk - ("Warning: set_dma_count count 0x%x bus width %d\n", - count, p_dma_ch->pwidth); - } -#endif - - count = count >> p_dma_ch->shift; - - mtdcr(DCRN_DMACT0 + (dmanr * 0x8), count); -} - -/* - * Returns the number of bytes left to be transferred. - * After a DMA transfer, this should return zero. - * Reading this while a DMA transfer is still in progress will return - * unpredictable results. - */ -int -ppc4xx_get_dma_residue(unsigned int dmanr) -{ - unsigned int count; - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_get_dma_residue: bad channel 0x%x\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - count = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)); - - return (count << p_dma_ch->shift); -} - -/* - * Sets the DMA address for a memory to peripheral or peripheral - * to memory transfer. The address is just saved in the channel - * structure for now and used later in enable_dma(). - */ -void -ppc4xx_set_dma_addr(unsigned int dmanr, phys_addr_t addr) -{ - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_set_dma_addr: bad channel: %d\n", dmanr); - return; - } - -#ifdef DEBUG_4xxDMA - { - int error = 0; - switch (p_dma_ch->pwidth) { - case PW_8: - break; - case PW_16: - if ((unsigned) addr & 0x1) - error = 1; - break; - case PW_32: - if ((unsigned) addr & 0x3) - error = 1; - break; - case PW_64: - if ((unsigned) addr & 0x7) - error = 1; - break; - default: - printk("ppc4xx_set_dma_addr: invalid bus width: 0x%x\n", - p_dma_ch->pwidth); - return; - } - if (error) - printk("Warning: ppc4xx_set_dma_addr addr 0x%x bus width %d\n", - addr, p_dma_ch->pwidth); - } -#endif - - /* save dma address and program it later after we know the xfer mode */ - p_dma_ch->addr = addr; -} - -/* - * Sets both DMA addresses for a memory to memory transfer. - * For memory to peripheral or peripheral to memory transfers - * the function set_dma_addr() should be used instead. - */ -void -ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr, - phys_addr_t dst_dma_addr) -{ - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_set_dma_addr2: bad channel: %d\n", dmanr); - return; - } - -#ifdef DEBUG_4xxDMA - { - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - int error = 0; - switch (p_dma_ch->pwidth) { - case PW_8: - break; - case PW_16: - if (((unsigned) src_dma_addr & 0x1) || - ((unsigned) dst_dma_addr & 0x1) - ) - error = 1; - break; - case PW_32: - if (((unsigned) src_dma_addr & 0x3) || - ((unsigned) dst_dma_addr & 0x3) - ) - error = 1; - break; - case PW_64: - if (((unsigned) src_dma_addr & 0x7) || - ((unsigned) dst_dma_addr & 0x7) - ) - error = 1; - break; - default: - printk("ppc4xx_set_dma_addr2: invalid bus width: 0x%x\n", - p_dma_ch->pwidth); - return; - } - if (error) - printk - ("Warning: ppc4xx_set_dma_addr2 src 0x%x dst 0x%x bus width %d\n", - src_dma_addr, dst_dma_addr, p_dma_ch->pwidth); - } -#endif - - ppc4xx_set_src_addr(dmanr, src_dma_addr); - ppc4xx_set_dst_addr(dmanr, dst_dma_addr); -} - -/* - * Enables the channel interrupt. - * - * If performing a scatter/gatter transfer, this function - * MUST be called before calling alloc_dma_handle() and building - * the sgl list. Otherwise, interrupts will not be enabled, if - * they were previously disabled. - */ -int -ppc4xx_enable_dma_interrupt(unsigned int dmanr) -{ - unsigned int control; - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_enable_dma_interrupt: bad channel: %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - p_dma_ch->int_enable = 1; - - control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8)); - control |= DMA_CIE_ENABLE; /* Channel Interrupt Enable */ - mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control); - - return DMA_STATUS_GOOD; -} - -/* - * Disables the channel interrupt. - * - * If performing a scatter/gatter transfer, this function - * MUST be called before calling alloc_dma_handle() and building - * the sgl list. Otherwise, interrupts will not be disabled, if - * they were previously enabled. - */ -int -ppc4xx_disable_dma_interrupt(unsigned int dmanr) -{ - unsigned int control; - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_disable_dma_interrupt: bad channel: %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - p_dma_ch->int_enable = 0; - - control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8)); - control &= ~DMA_CIE_ENABLE; /* Channel Interrupt Enable */ - mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control); - - return DMA_STATUS_GOOD; -} - -/* - * Configures a DMA channel, including the peripheral bus width, if a - * peripheral is attached to the channel, the polarity of the DMAReq and - * DMAAck signals, etc. This information should really be setup by the boot - * code, since most likely the configuration won't change dynamically. - * If the kernel has to call this function, it's recommended that it's - * called from platform specific init code. The driver should not need to - * call this function. - */ -int -ppc4xx_init_dma_channel(unsigned int dmanr, ppc_dma_ch_t * p_init) -{ - unsigned int polarity; - uint32_t control = 0; - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - - DMA_MODE_READ = (unsigned long) DMA_TD; /* Peripheral to Memory */ - DMA_MODE_WRITE = 0; /* Memory to Peripheral */ - - if (!p_init) { - printk("ppc4xx_init_dma_channel: NULL p_init\n"); - return DMA_STATUS_NULL_POINTER; - } - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_init_dma_channel: bad channel %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - -#if DCRN_POL > 0 - polarity = mfdcr(DCRN_POL); -#else - polarity = 0; -#endif - - /* Setup the control register based on the values passed to - * us in p_init. Then, over-write the control register with this - * new value. - */ - control |= SET_DMA_CONTROL; - - /* clear all polarity signals and then "or" in new signal levels */ - polarity &= ~GET_DMA_POLARITY(dmanr); - polarity |= p_init->polarity; -#if DCRN_POL > 0 - mtdcr(DCRN_POL, polarity); -#endif - mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control); - - /* save these values in our dma channel structure */ - memcpy(p_dma_ch, p_init, sizeof (ppc_dma_ch_t)); - - /* - * The peripheral width values written in the control register are: - * PW_8 0 - * PW_16 1 - * PW_32 2 - * PW_64 3 - * - * Since the DMA count register takes the number of "transfers", - * we need to divide the count sent to us in certain - * functions by the appropriate number. It so happens that our - * right shift value is equal to the peripheral width value. - */ - p_dma_ch->shift = p_init->pwidth; - - /* - * Save the control word for easy access. - */ - p_dma_ch->control = control; - - mtdcr(DCRN_DMASR, 0xffffffff); /* clear status register */ - return DMA_STATUS_GOOD; -} - -/* - * This function returns the channel configuration. - */ -int -ppc4xx_get_channel_config(unsigned int dmanr, ppc_dma_ch_t * p_dma_ch) -{ - unsigned int polarity; - unsigned int control; - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_get_channel_config: bad channel %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - memcpy(p_dma_ch, &dma_channels[dmanr], sizeof (ppc_dma_ch_t)); - -#if DCRN_POL > 0 - polarity = mfdcr(DCRN_POL); -#else - polarity = 0; -#endif - - p_dma_ch->polarity = polarity & GET_DMA_POLARITY(dmanr); - control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8)); - - p_dma_ch->cp = GET_DMA_PRIORITY(control); - p_dma_ch->pwidth = GET_DMA_PW(control); - p_dma_ch->psc = GET_DMA_PSC(control); - p_dma_ch->pwc = GET_DMA_PWC(control); - p_dma_ch->phc = GET_DMA_PHC(control); - p_dma_ch->ce = GET_DMA_CE_ENABLE(control); - p_dma_ch->int_enable = GET_DMA_CIE_ENABLE(control); - p_dma_ch->shift = GET_DMA_PW(control); - -#ifdef CONFIG_PPC4xx_EDMA - p_dma_ch->pf = GET_DMA_PREFETCH(control); -#else - p_dma_ch->ch_enable = GET_DMA_CH(control); - p_dma_ch->ece_enable = GET_DMA_ECE(control); - p_dma_ch->tcd_disable = GET_DMA_TCD(control); -#endif - return DMA_STATUS_GOOD; -} - -/* - * Sets the priority for the DMA channel dmanr. - * Since this is setup by the hardware init function, this function - * can be used to dynamically change the priority of a channel. - * - * Acceptable priorities: - * - * PRIORITY_LOW - * PRIORITY_MID_LOW - * PRIORITY_MID_HIGH - * PRIORITY_HIGH - * - */ -int -ppc4xx_set_channel_priority(unsigned int dmanr, unsigned int priority) -{ - unsigned int control; - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_set_channel_priority: bad channel %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - if ((priority != PRIORITY_LOW) && - (priority != PRIORITY_MID_LOW) && - (priority != PRIORITY_MID_HIGH) && (priority != PRIORITY_HIGH)) { - printk("ppc4xx_set_channel_priority: bad priority: 0x%x\n", priority); - } - - control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8)); - control |= SET_DMA_PRIORITY(priority); - mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control); - - return DMA_STATUS_GOOD; -} - -/* - * Returns the width of the peripheral attached to this channel. This assumes - * that someone who knows the hardware configuration, boot code or some other - * init code, already set the width. - * - * The return value is one of: - * PW_8 - * PW_16 - * PW_32 - * PW_64 - * - * The function returns 0 on error. - */ -unsigned int -ppc4xx_get_peripheral_width(unsigned int dmanr) -{ - unsigned int control; - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_get_peripheral_width: bad channel %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8)); - - return (GET_DMA_PW(control)); -} - -/* - * Clears the channel status bits - */ -int -ppc4xx_clr_dma_status(unsigned int dmanr) -{ - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk(KERN_ERR "ppc4xx_clr_dma_status: bad channel: %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - mtdcr(DCRN_DMASR, ((u32)DMA_CH0_ERR | (u32)DMA_CS0 | (u32)DMA_TS0) >> dmanr); - return DMA_STATUS_GOOD; -} - -#ifdef CONFIG_PPC4xx_EDMA -/* - * Enables the burst on the channel (BTEN bit in the control/count register) - * Note: - * For scatter/gather dma, this function MUST be called before the - * ppc4xx_alloc_dma_handle() func as the chan count register is copied into the - * sgl list and used as each sgl element is added. - */ -int -ppc4xx_enable_burst(unsigned int dmanr) -{ - unsigned int ctc; - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk(KERN_ERR "ppc4xx_enable_burst: bad channel: %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) | DMA_CTC_BTEN; - mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc); - return DMA_STATUS_GOOD; -} -/* - * Disables the burst on the channel (BTEN bit in the control/count register) - * Note: - * For scatter/gather dma, this function MUST be called before the - * ppc4xx_alloc_dma_handle() func as the chan count register is copied into the - * sgl list and used as each sgl element is added. - */ -int -ppc4xx_disable_burst(unsigned int dmanr) -{ - unsigned int ctc; - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk(KERN_ERR "ppc4xx_disable_burst: bad channel: %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BTEN; - mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc); - return DMA_STATUS_GOOD; -} -/* - * Sets the burst size (number of peripheral widths) for the channel - * (BSIZ bits in the control/count register)) - * must be one of: - * DMA_CTC_BSIZ_2 - * DMA_CTC_BSIZ_4 - * DMA_CTC_BSIZ_8 - * DMA_CTC_BSIZ_16 - * Note: - * For scatter/gather dma, this function MUST be called before the - * ppc4xx_alloc_dma_handle() func as the chan count register is copied into the - * sgl list and used as each sgl element is added. - */ -int -ppc4xx_set_burst_size(unsigned int dmanr, unsigned int bsize) -{ - unsigned int ctc; - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk(KERN_ERR "ppc4xx_set_burst_size: bad channel: %d\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BSIZ_MSK; - ctc |= (bsize & DMA_CTC_BSIZ_MSK); - mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc); - return DMA_STATUS_GOOD; -} - -EXPORT_SYMBOL(ppc4xx_enable_burst); -EXPORT_SYMBOL(ppc4xx_disable_burst); -EXPORT_SYMBOL(ppc4xx_set_burst_size); -#endif /* CONFIG_PPC4xx_EDMA */ - -EXPORT_SYMBOL(ppc4xx_init_dma_channel); -EXPORT_SYMBOL(ppc4xx_get_channel_config); -EXPORT_SYMBOL(ppc4xx_set_channel_priority); -EXPORT_SYMBOL(ppc4xx_get_peripheral_width); -EXPORT_SYMBOL(dma_channels); -EXPORT_SYMBOL(ppc4xx_set_src_addr); -EXPORT_SYMBOL(ppc4xx_set_dst_addr); -EXPORT_SYMBOL(ppc4xx_set_dma_addr); -EXPORT_SYMBOL(ppc4xx_set_dma_addr2); -EXPORT_SYMBOL(ppc4xx_enable_dma); -EXPORT_SYMBOL(ppc4xx_disable_dma); -EXPORT_SYMBOL(ppc4xx_set_dma_mode); -EXPORT_SYMBOL(ppc4xx_set_dma_count); -EXPORT_SYMBOL(ppc4xx_get_dma_residue); -EXPORT_SYMBOL(ppc4xx_enable_dma_interrupt); -EXPORT_SYMBOL(ppc4xx_disable_dma_interrupt); -EXPORT_SYMBOL(ppc4xx_get_dma_status); -EXPORT_SYMBOL(ppc4xx_clr_dma_status); - diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c deleted file mode 100644 index ee0da4b4b993..000000000000 --- a/arch/ppc/syslib/ppc4xx_pic.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Interrupt controller driver for PowerPC 4xx-based processors. - * - * Eugene Surovegin or - * Copyright (c) 2004, 2005 Zultys Technologies - * - * Based on original code by - * Copyright (c) 1999 Grant Erickson - * Armin Custer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. -*/ -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* See comment in include/arch-ppc/ppc4xx_pic.h - * for more info about these two variables - */ -extern struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[NR_UICS] - __attribute__ ((weak)); -extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak)); - -#define IRQ_MASK_UIC0(irq) (1 << (31 - (irq))) -#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f))) -#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq) -#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq) -#define IRQ_MASK_UIC3(irq) IRQ_MASK_UICx(irq) - -#define UIC_HANDLERS(n) \ -static void ppc4xx_uic##n##_enable(unsigned int irq) \ -{ \ - u32 mask = IRQ_MASK_UIC##n(irq); \ - if (irq_desc[irq].status & IRQ_LEVEL) \ - mtdcr(DCRN_UIC_SR(UIC##n), mask); \ - ppc_cached_irq_mask[n] |= mask; \ - mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \ -} \ - \ -static void ppc4xx_uic##n##_disable(unsigned int irq) \ -{ \ - ppc_cached_irq_mask[n] &= ~IRQ_MASK_UIC##n(irq); \ - mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \ - ACK_UIC##n##_PARENT \ -} \ - \ -static void ppc4xx_uic##n##_ack(unsigned int irq) \ -{ \ - u32 mask = IRQ_MASK_UIC##n(irq); \ - ppc_cached_irq_mask[n] &= ~mask; \ - mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \ - mtdcr(DCRN_UIC_SR(UIC##n), mask); \ - ACK_UIC##n##_PARENT \ -} \ - \ -static void ppc4xx_uic##n##_end(unsigned int irq) \ -{ \ - unsigned int status = irq_desc[irq].status; \ - u32 mask = IRQ_MASK_UIC##n(irq); \ - if (status & IRQ_LEVEL) { \ - mtdcr(DCRN_UIC_SR(UIC##n), mask); \ - ACK_UIC##n##_PARENT \ - } \ - if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) { \ - ppc_cached_irq_mask[n] |= mask; \ - mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \ - } \ -} - -#define DECLARE_UIC(n) \ -{ \ - .typename = "UIC"#n, \ - .enable = ppc4xx_uic##n##_enable, \ - .disable = ppc4xx_uic##n##_disable, \ - .ack = ppc4xx_uic##n##_ack, \ - .end = ppc4xx_uic##n##_end, \ -} \ - -#if NR_UICS == 4 -#define ACK_UIC0_PARENT -#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC); -#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC); -#define ACK_UIC3_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC3NC); -UIC_HANDLERS(0); -UIC_HANDLERS(1); -UIC_HANDLERS(2); -UIC_HANDLERS(3); - -static int ppc4xx_pic_get_irq(void) -{ - u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0)); - if (uic0 & UIC0_UIC1NC) - return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1))); - else if (uic0 & UIC0_UIC2NC) - return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2))); - else if (uic0 & UIC0_UIC3NC) - return 128 - ffs(mfdcr(DCRN_UIC_MSR(UIC3))); - else - return uic0 ? 32 - ffs(uic0) : -1; -} - -static void __init ppc4xx_pic_impl_init(void) -{ - /* Enable cascade interrupts in UIC0 */ - ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC; - mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC); - mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]); -} - -#elif NR_UICS == 3 -#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC); -#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC); -#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC); -UIC_HANDLERS(0); -UIC_HANDLERS(1); -UIC_HANDLERS(2); - -static int ppc4xx_pic_get_irq(void) -{ - u32 uicb = mfdcr(DCRN_UIC_MSR(UICB)); - if (uicb & UICB_UIC0NC) - return 32 - ffs(mfdcr(DCRN_UIC_MSR(UIC0))); - else if (uicb & UICB_UIC1NC) - return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1))); - else if (uicb & UICB_UIC2NC) - return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2))); - else - return -1; -} - -static void __init ppc4xx_pic_impl_init(void) -{ -#if defined(CONFIG_440GX) - /* Disable 440GP compatibility mode if it was enabled in firmware */ - SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~DCRN_SDR_MFR_PCM); -#endif - /* Configure Base UIC */ - mtdcr(DCRN_UIC_CR(UICB), 0); - mtdcr(DCRN_UIC_TR(UICB), 0); - mtdcr(DCRN_UIC_PR(UICB), 0xffffffff); - mtdcr(DCRN_UIC_SR(UICB), 0xffffffff); - mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC); -} - -#elif NR_UICS == 2 -#define ACK_UIC0_PARENT -#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC); -UIC_HANDLERS(0); -UIC_HANDLERS(1); - -static int ppc4xx_pic_get_irq(void) -{ - u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0)); - if (uic0 & UIC0_UIC1NC) - return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1))); - else - return uic0 ? 32 - ffs(uic0) : -1; -} - -static void __init ppc4xx_pic_impl_init(void) -{ - /* Enable cascade interrupt in UIC0 */ - ppc_cached_irq_mask[0] |= UIC0_UIC1NC; - mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC); - mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]); -} - -#elif NR_UICS == 1 -#define ACK_UIC0_PARENT -UIC_HANDLERS(0); - -static int ppc4xx_pic_get_irq(void) -{ - u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0)); - return uic0 ? 32 - ffs(uic0) : -1; -} - -static inline void ppc4xx_pic_impl_init(void) -{ -} -#endif - -static struct ppc4xx_uic_impl { - struct hw_interrupt_type decl; - int base; /* Base DCR number */ -} __uic[] = { - { .decl = DECLARE_UIC(0), .base = UIC0 }, -#if NR_UICS > 1 - { .decl = DECLARE_UIC(1), .base = UIC1 }, -#if NR_UICS > 2 - { .decl = DECLARE_UIC(2), .base = UIC2 }, -#if NR_UICS > 3 - { .decl = DECLARE_UIC(3), .base = UIC3 }, -#endif -#endif -#endif -}; - -static inline int is_level_sensitive(int irq) -{ - u32 tr = mfdcr(DCRN_UIC_TR(__uic[irq >> 5].base)); - return (tr & IRQ_MASK_UICx(irq)) == 0; -} - -void __init ppc4xx_pic_init(void) -{ - int i; - unsigned char *eirqs = ppc4xx_uic_ext_irq_cfg; - - for (i = 0; i < NR_UICS; ++i) { - int base = __uic[i].base; - - /* Disable everything by default */ - ppc_cached_irq_mask[i] = 0; - mtdcr(DCRN_UIC_ER(base), 0); - - /* We don't use critical interrupts */ - mtdcr(DCRN_UIC_CR(base), 0); - - /* Configure polarity and triggering */ - if (ppc4xx_core_uic_cfg) { - struct ppc4xx_uic_settings *p = ppc4xx_core_uic_cfg + i; - u32 mask = p->ext_irq_mask; - u32 pr = mfdcr(DCRN_UIC_PR(base)) & mask; - u32 tr = mfdcr(DCRN_UIC_TR(base)) & mask; - - /* "Fixed" interrupts (on-chip devices) */ - pr |= p->polarity & ~mask; - tr |= p->triggering & ~mask; - - /* Merge external IRQs settings if board port - * provided them - */ - if (eirqs && mask) { - pr &= ~mask; - tr &= ~mask; - while (mask) { - /* Extract current external IRQ mask */ - u32 eirq_mask = 1 << __ilog2(mask); - - if (!(*eirqs & IRQ_SENSE_LEVEL)) - tr |= eirq_mask; - - if (*eirqs & IRQ_POLARITY_POSITIVE) - pr |= eirq_mask; - - mask &= ~eirq_mask; - ++eirqs; - } - } - mtdcr(DCRN_UIC_PR(base), pr); - mtdcr(DCRN_UIC_TR(base), tr); - } - - /* ACK any pending interrupts to prevent false - * triggering after first enable - */ - mtdcr(DCRN_UIC_SR(base), 0xffffffff); - } - - /* Perform optional implementation specific setup - * (e.g. enable cascade interrupts for multi-UIC configurations) - */ - ppc4xx_pic_impl_init(); - - /* Attach low-level handlers */ - for (i = 0; i < (NR_UICS << 5); ++i) { - irq_desc[i].chip = &__uic[i >> 5].decl; - if (is_level_sensitive(i)) - irq_desc[i].status |= IRQ_LEVEL; - } - - ppc_md.get_irq = ppc4xx_pic_get_irq; -} diff --git a/arch/ppc/syslib/ppc4xx_setup.c b/arch/ppc/syslib/ppc4xx_setup.c deleted file mode 100644 index 353d746b47e1..000000000000 --- a/arch/ppc/syslib/ppc4xx_setup.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * - * Copyright (c) 1999-2000 Grant Erickson - * - * Copyright 2000-2001 MontaVista Software Inc. - * Completed implementation. - * Author: MontaVista Software, Inc. - * Frank Rowand - * Debbie Chu - * Further modifications by Armin Kuster - * - * Module name: ppc4xx_setup.c - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* Function Prototypes */ -extern void abort(void); -extern void ppc4xx_find_bridges(void); - -/* Global Variables */ -bd_t __res; - -void __init -ppc4xx_setup_arch(void) -{ -#if !defined(CONFIG_BDI_SWITCH) - /* - * The Abatron BDI JTAG debugger does not tolerate others - * mucking with the debug registers. - */ - mtspr(SPRN_DBCR0, (DBCR0_IDM)); - mtspr(SPRN_DBSR, 0xffffffff); -#endif - - /* Setup PCI host bridges */ -#ifdef CONFIG_PCI - ppc4xx_find_bridges(); -#endif -} - -/* - * This routine pretty-prints the platform's internal CPU clock - * frequencies into the buffer for usage in /proc/cpuinfo. - */ - -static int -ppc4xx_show_percpuinfo(struct seq_file *m, int i) -{ - seq_printf(m, "clock\t\t: %ldMHz\n", (long)__res.bi_intfreq / 1000000); - - return 0; -} - -/* - * This routine pretty-prints the platform's internal bus clock - * frequencies into the buffer for usage in /proc/cpuinfo. - */ -static int -ppc4xx_show_cpuinfo(struct seq_file *m) -{ - bd_t *bip = &__res; - - seq_printf(m, "machine\t\t: %s\n", PPC4xx_MACHINE_NAME); - seq_printf(m, "plb bus clock\t: %ldMHz\n", - (long) bip->bi_busfreq / 1000000); -#ifdef CONFIG_PCI - seq_printf(m, "pci bus clock\t: %dMHz\n", - bip->bi_pci_busfreq / 1000000); -#endif - - return 0; -} - -/* - * Return the virtual address representing the top of physical RAM. - */ -static unsigned long __init -ppc4xx_find_end_of_memory(void) -{ - return ((unsigned long) __res.bi_memsize); -} - -void __init -ppc4xx_map_io(void) -{ - io_block_mapping(PPC4xx_ONB_IO_VADDR, - PPC4xx_ONB_IO_PADDR, PPC4xx_ONB_IO_SIZE, _PAGE_IO); -#ifdef CONFIG_PCI - io_block_mapping(PPC4xx_PCI_IO_VADDR, - PPC4xx_PCI_IO_PADDR, PPC4xx_PCI_IO_SIZE, _PAGE_IO); - io_block_mapping(PPC4xx_PCI_CFG_VADDR, - PPC4xx_PCI_CFG_PADDR, PPC4xx_PCI_CFG_SIZE, _PAGE_IO); - io_block_mapping(PPC4xx_PCI_LCFG_VADDR, - PPC4xx_PCI_LCFG_PADDR, PPC4xx_PCI_LCFG_SIZE, _PAGE_IO); -#endif -} - -void __init -ppc4xx_init_IRQ(void) -{ - ppc4xx_pic_init(); -} - -static void -ppc4xx_restart(char *cmd) -{ - printk("%s\n", cmd); - abort(); -} - -static void -ppc4xx_power_off(void) -{ - printk("System Halted\n"); - local_irq_disable(); - while (1) ; -} - -static void -ppc4xx_halt(void) -{ - printk("System Halted\n"); - local_irq_disable(); - while (1) ; -} - -/* - * This routine retrieves the internal processor frequency from the board - * information structure, sets up the kernel timer decrementer based on - * that value, enables the 4xx programmable interval timer (PIT) and sets - * it up for auto-reload. - */ -static void __init -ppc4xx_calibrate_decr(void) -{ - unsigned int freq; - bd_t *bip = &__res; - -#if defined(CONFIG_WALNUT) || defined(CONFIG_SYCAMORE) - /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */ - mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE); -#endif - freq = bip->bi_tbfreq; - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); - - /* Set the time base to zero. - ** At 200 Mhz, time base will rollover in ~2925 years. - */ - - mtspr(SPRN_TBWL, 0); - mtspr(SPRN_TBWU, 0); - - /* Clear any pending timer interrupts */ - - mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS); - mtspr(SPRN_TCR, TCR_PIE | TCR_ARE); - - /* Set the PIT reload value and just let it run. */ - mtspr(SPRN_PIT, tb_ticks_per_jiffy); -} - -TODC_ALLOC(); - -/* - * Input(s): - * r3 - Optional pointer to a board information structure. - * r4 - Optional pointer to the physical starting address of the init RAM - * disk. - * r5 - Optional pointer to the physical ending address of the init RAM - * disk. - * r6 - Optional pointer to the physical starting address of any kernel - * command-line parameters. - * r7 - Optional pointer to the physical ending address of any kernel - * command-line parameters. - */ -void __init -ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - parse_bootinfo(find_bootinfo()); - - /* - * If we were passed in a board information, copy it into the - * residual data area. - */ - if (r3) - __res = *(bd_t *)(r3 + KERNELBASE); - -#if defined(CONFIG_BLK_DEV_INITRD) - /* - * If the init RAM disk has been configured in, and there's a valid - * starting address for it, set it up. - */ - if (r4) { - initrd_start = r4 + KERNELBASE; - initrd_end = r5 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - /* Copy the kernel command line arguments to a safe place. */ - - if (r6) { - *(char *) (r7 + KERNELBASE) = 0; - strcpy(cmd_line, (char *) (r6 + KERNELBASE)); - } - - /* Initialize machine-dependent vectors */ - - ppc_md.setup_arch = ppc4xx_setup_arch; - ppc_md.show_percpuinfo = ppc4xx_show_percpuinfo; - ppc_md.show_cpuinfo = ppc4xx_show_cpuinfo; - ppc_md.init_IRQ = ppc4xx_init_IRQ; - - ppc_md.restart = ppc4xx_restart; - ppc_md.power_off = ppc4xx_power_off; - ppc_md.halt = ppc4xx_halt; - - ppc_md.calibrate_decr = ppc4xx_calibrate_decr; - - ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory; - ppc_md.setup_io_mappings = ppc4xx_map_io; - -#ifdef CONFIG_SERIAL_TEXT_DEBUG - ppc_md.progress = gen550_progress; -#endif -} - -/* Called from machine_check_exception */ -void platform_machine_check(struct pt_regs *regs) -{ -#if defined(DCRN_PLB0_BEAR) - printk("PLB0: BEAR= 0x%08x ACR= 0x%08x BESR= 0x%08x\n", - mfdcr(DCRN_PLB0_BEAR), mfdcr(DCRN_PLB0_ACR), - mfdcr(DCRN_PLB0_BESR)); -#endif -#if defined(DCRN_POB0_BEAR) - printk("PLB0 to OPB: BEAR= 0x%08x BESR0= 0x%08x BESR1= 0x%08x\n", - mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_POB0_BESR0), - mfdcr(DCRN_POB0_BESR1)); -#endif - -} diff --git a/arch/ppc/syslib/ppc4xx_sgdma.c b/arch/ppc/syslib/ppc4xx_sgdma.c deleted file mode 100644 index c4b369b50f9c..000000000000 --- a/arch/ppc/syslib/ppc4xx_sgdma.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * IBM PPC4xx DMA engine scatter/gather library - * - * Copyright 2002-2003 MontaVista Software Inc. - * - * Cleaned up and converted to new DCR access - * Matt Porter - * - * Original code by Armin Kuster - * and Pete Popov - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -void -ppc4xx_set_sg_addr(int dmanr, phys_addr_t sg_addr) -{ - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_set_sg_addr: bad channel: %d\n", dmanr); - return; - } - -#ifdef PPC4xx_DMA_64BIT - mtdcr(DCRN_ASGH0 + (dmanr * 0x8), (u32)(sg_addr >> 32)); -#endif - mtdcr(DCRN_ASG0 + (dmanr * 0x8), (u32)sg_addr); -} - -/* - * Add a new sgl descriptor to the end of a scatter/gather list - * which was created by alloc_dma_handle(). - * - * For a memory to memory transfer, both dma addresses must be - * valid. For a peripheral to memory transfer, one of the addresses - * must be set to NULL, depending on the direction of the transfer: - * memory to peripheral: set dst_addr to NULL, - * peripheral to memory: set src_addr to NULL. - */ -int -ppc4xx_add_dma_sgl(sgl_handle_t handle, phys_addr_t src_addr, phys_addr_t dst_addr, - unsigned int count) -{ - sgl_list_info_t *psgl = (sgl_list_info_t *) handle; - ppc_dma_ch_t *p_dma_ch; - - if (!handle) { - printk("ppc4xx_add_dma_sgl: null handle\n"); - return DMA_STATUS_BAD_HANDLE; - } - - if (psgl->dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_add_dma_sgl: bad channel: %d\n", psgl->dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - p_dma_ch = &dma_channels[psgl->dmanr]; - -#ifdef DEBUG_4xxDMA - { - int error = 0; - unsigned int aligned = - (unsigned) src_addr | (unsigned) dst_addr | count; - switch (p_dma_ch->pwidth) { - case PW_8: - break; - case PW_16: - if (aligned & 0x1) - error = 1; - break; - case PW_32: - if (aligned & 0x3) - error = 1; - break; - case PW_64: - if (aligned & 0x7) - error = 1; - break; - default: - printk("ppc4xx_add_dma_sgl: invalid bus width: 0x%x\n", - p_dma_ch->pwidth); - return DMA_STATUS_GENERAL_ERROR; - } - if (error) - printk - ("Alignment warning: ppc4xx_add_dma_sgl src 0x%x dst 0x%x count 0x%x bus width var %d\n", - src_addr, dst_addr, count, p_dma_ch->pwidth); - - } -#endif - - if ((unsigned) (psgl->ptail + 1) >= ((unsigned) psgl + SGL_LIST_SIZE)) { - printk("sgl handle out of memory \n"); - return DMA_STATUS_OUT_OF_MEMORY; - } - - if (!psgl->ptail) { - psgl->phead = (ppc_sgl_t *) - ((unsigned) psgl + sizeof (sgl_list_info_t)); - psgl->phead_dma = psgl->dma_addr + sizeof(sgl_list_info_t); - psgl->ptail = psgl->phead; - psgl->ptail_dma = psgl->phead_dma; - } else { - if(p_dma_ch->int_on_final_sg) { - /* mask out all dma interrupts, except error, on tail - before adding new tail. */ - psgl->ptail->control_count &= - ~(SG_TCI_ENABLE | SG_ETI_ENABLE); - } - psgl->ptail->next = psgl->ptail_dma + sizeof(ppc_sgl_t); - psgl->ptail++; - psgl->ptail_dma += sizeof(ppc_sgl_t); - } - - psgl->ptail->control = psgl->control; - psgl->ptail->src_addr = src_addr; - psgl->ptail->dst_addr = dst_addr; - psgl->ptail->control_count = (count >> p_dma_ch->shift) | - psgl->sgl_control; - psgl->ptail->next = (uint32_t) NULL; - - return DMA_STATUS_GOOD; -} - -/* - * Enable (start) the DMA described by the sgl handle. - */ -void -ppc4xx_enable_dma_sgl(sgl_handle_t handle) -{ - sgl_list_info_t *psgl = (sgl_list_info_t *) handle; - ppc_dma_ch_t *p_dma_ch; - uint32_t sg_command; - - if (!handle) { - printk("ppc4xx_enable_dma_sgl: null handle\n"); - return; - } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) { - printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n", - psgl->dmanr); - return; - } else if (!psgl->phead) { - printk("ppc4xx_enable_dma_sgl: sg list empty\n"); - return; - } - - p_dma_ch = &dma_channels[psgl->dmanr]; - psgl->ptail->control_count &= ~SG_LINK; /* make this the last dscrptr */ - sg_command = mfdcr(DCRN_ASGC); - - ppc4xx_set_sg_addr(psgl->dmanr, psgl->phead_dma); - - sg_command |= SSG_ENABLE(psgl->dmanr); - - mtdcr(DCRN_ASGC, sg_command); /* start transfer */ -} - -/* - * Halt an active scatter/gather DMA operation. - */ -void -ppc4xx_disable_dma_sgl(sgl_handle_t handle) -{ - sgl_list_info_t *psgl = (sgl_list_info_t *) handle; - uint32_t sg_command; - - if (!handle) { - printk("ppc4xx_enable_dma_sgl: null handle\n"); - return; - } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) { - printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n", - psgl->dmanr); - return; - } - - sg_command = mfdcr(DCRN_ASGC); - sg_command &= ~SSG_ENABLE(psgl->dmanr); - mtdcr(DCRN_ASGC, sg_command); /* stop transfer */ -} - -/* - * Returns number of bytes left to be transferred from the entire sgl list. - * *src_addr and *dst_addr get set to the source/destination address of - * the sgl descriptor where the DMA stopped. - * - * An sgl transfer must NOT be active when this function is called. - */ -int -ppc4xx_get_dma_sgl_residue(sgl_handle_t handle, phys_addr_t * src_addr, - phys_addr_t * dst_addr) -{ - sgl_list_info_t *psgl = (sgl_list_info_t *) handle; - ppc_dma_ch_t *p_dma_ch; - ppc_sgl_t *pnext, *sgl_addr; - uint32_t count_left; - - if (!handle) { - printk("ppc4xx_get_dma_sgl_residue: null handle\n"); - return DMA_STATUS_BAD_HANDLE; - } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) { - printk("ppc4xx_get_dma_sgl_residue: bad channel in handle %d\n", - psgl->dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - sgl_addr = (ppc_sgl_t *) __va(mfdcr(DCRN_ASG0 + (psgl->dmanr * 0x8))); - count_left = mfdcr(DCRN_DMACT0 + (psgl->dmanr * 0x8)) & SG_COUNT_MASK; - - if (!sgl_addr) { - printk("ppc4xx_get_dma_sgl_residue: sgl addr register is null\n"); - goto error; - } - - pnext = psgl->phead; - while (pnext && - ((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE) && - (pnext != sgl_addr)) - ) { - pnext++; - } - - if (pnext == sgl_addr) { /* found the sgl descriptor */ - - *src_addr = pnext->src_addr; - *dst_addr = pnext->dst_addr; - - /* - * Now search the remaining descriptors and add their count. - * We already have the remaining count from this descriptor in - * count_left. - */ - pnext++; - - while ((pnext != psgl->ptail) && - ((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE)) - ) { - count_left += pnext->control_count & SG_COUNT_MASK; - } - - if (pnext != psgl->ptail) { /* should never happen */ - printk - ("ppc4xx_get_dma_sgl_residue error (1) psgl->ptail 0x%x handle 0x%x\n", - (unsigned int) psgl->ptail, (unsigned int) handle); - goto error; - } - - /* success */ - p_dma_ch = &dma_channels[psgl->dmanr]; - return (count_left << p_dma_ch->shift); /* count in bytes */ - - } else { - /* this shouldn't happen */ - printk - ("get_dma_sgl_residue, unable to match current address 0x%x, handle 0x%x\n", - (unsigned int) sgl_addr, (unsigned int) handle); - - } - - error: - *src_addr = (phys_addr_t) NULL; - *dst_addr = (phys_addr_t) NULL; - return 0; -} - -/* - * Returns the address(es) of the buffer(s) contained in the head element of - * the scatter/gather list. The element is removed from the scatter/gather - * list and the next element becomes the head. - * - * This function should only be called when the DMA is not active. - */ -int -ppc4xx_delete_dma_sgl_element(sgl_handle_t handle, phys_addr_t * src_dma_addr, - phys_addr_t * dst_dma_addr) -{ - sgl_list_info_t *psgl = (sgl_list_info_t *) handle; - - if (!handle) { - printk("ppc4xx_delete_sgl_element: null handle\n"); - return DMA_STATUS_BAD_HANDLE; - } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) { - printk("ppc4xx_delete_sgl_element: bad channel in handle %d\n", - psgl->dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - if (!psgl->phead) { - printk("ppc4xx_delete_sgl_element: sgl list empty\n"); - *src_dma_addr = (phys_addr_t) NULL; - *dst_dma_addr = (phys_addr_t) NULL; - return DMA_STATUS_SGL_LIST_EMPTY; - } - - *src_dma_addr = (phys_addr_t) psgl->phead->src_addr; - *dst_dma_addr = (phys_addr_t) psgl->phead->dst_addr; - - if (psgl->phead == psgl->ptail) { - /* last descriptor on the list */ - psgl->phead = NULL; - psgl->ptail = NULL; - } else { - psgl->phead++; - psgl->phead_dma += sizeof(ppc_sgl_t); - } - - return DMA_STATUS_GOOD; -} - - -/* - * Create a scatter/gather list handle. This is simply a structure which - * describes a scatter/gather list. - * - * A handle is returned in "handle" which the driver should save in order to - * be able to access this list later. A chunk of memory will be allocated - * to be used by the API for internal management purposes, including managing - * the sg list and allocating memory for the sgl descriptors. One page should - * be more than enough for that purpose. Perhaps it's a bit wasteful to use - * a whole page for a single sg list, but most likely there will be only one - * sg list per channel. - * - * Interrupt notes: - * Each sgl descriptor has a copy of the DMA control word which the DMA engine - * loads in the control register. The control word has a "global" interrupt - * enable bit for that channel. Interrupts are further qualified by a few bits - * in the sgl descriptor count register. In order to setup an sgl, we have to - * know ahead of time whether or not interrupts will be enabled at the completion - * of the transfers. Thus, enable_dma_interrupt()/disable_dma_interrupt() MUST - * be called before calling alloc_dma_handle(). If the interrupt mode will never - * change after powerup, then enable_dma_interrupt()/disable_dma_interrupt() - * do not have to be called -- interrupts will be enabled or disabled based - * on how the channel was configured after powerup by the hw_init_dma_channel() - * function. Each sgl descriptor will be setup to interrupt if an error occurs; - * however, only the last descriptor will be setup to interrupt. Thus, an - * interrupt will occur (if interrupts are enabled) only after the complete - * sgl transfer is done. - */ -int -ppc4xx_alloc_dma_handle(sgl_handle_t * phandle, unsigned int mode, unsigned int dmanr) -{ - sgl_list_info_t *psgl=NULL; - dma_addr_t dma_addr; - ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; - uint32_t sg_command; - uint32_t ctc_settings; - void *ret; - - if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { - printk("ppc4xx_alloc_dma_handle: invalid channel 0x%x\n", dmanr); - return DMA_STATUS_BAD_CHANNEL; - } - - if (!phandle) { - printk("ppc4xx_alloc_dma_handle: null handle pointer\n"); - return DMA_STATUS_NULL_POINTER; - } - - /* Get a page of memory, which is zeroed out by consistent_alloc() */ - ret = dma_alloc_coherent(NULL, DMA_PPC4xx_SIZE, &dma_addr, GFP_KERNEL); - if (ret != NULL) { - memset(ret, 0, DMA_PPC4xx_SIZE); - psgl = (sgl_list_info_t *) ret; - } - - if (psgl == NULL) { - *phandle = (sgl_handle_t) NULL; - return DMA_STATUS_OUT_OF_MEMORY; - } - - psgl->dma_addr = dma_addr; - psgl->dmanr = dmanr; - - /* - * Modify and save the control word. These words will be - * written to each sgl descriptor. The DMA engine then - * loads this control word into the control register - * every time it reads a new descriptor. - */ - psgl->control = p_dma_ch->control; - /* Clear all mode bits */ - psgl->control &= ~(DMA_TM_MASK | DMA_TD); - /* Save control word and mode */ - psgl->control |= (mode | DMA_CE_ENABLE); - - /* In MM mode, we must set ETD/TCE */ - if (mode == DMA_MODE_MM) - psgl->control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE; - - if (p_dma_ch->int_enable) { - /* Enable channel interrupt */ - psgl->control |= DMA_CIE_ENABLE; - } else { - psgl->control &= ~DMA_CIE_ENABLE; - } - - sg_command = mfdcr(DCRN_ASGC); - sg_command |= SSG_MASK_ENABLE(dmanr); - - /* Enable SGL control access */ - mtdcr(DCRN_ASGC, sg_command); - psgl->sgl_control = SG_ERI_ENABLE | SG_LINK; - - /* keep control count register settings */ - ctc_settings = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) - & (DMA_CTC_BSIZ_MSK | DMA_CTC_BTEN); /*burst mode settings*/ - psgl->sgl_control |= ctc_settings; - - if (p_dma_ch->int_enable) { - if (p_dma_ch->tce_enable) - psgl->sgl_control |= SG_TCI_ENABLE; - else - psgl->sgl_control |= SG_ETI_ENABLE; - } - - *phandle = (sgl_handle_t) psgl; - return DMA_STATUS_GOOD; -} - -/* - * Destroy a scatter/gather list handle that was created by alloc_dma_handle(). - * The list must be empty (contain no elements). - */ -void -ppc4xx_free_dma_handle(sgl_handle_t handle) -{ - sgl_list_info_t *psgl = (sgl_list_info_t *) handle; - - if (!handle) { - printk("ppc4xx_free_dma_handle: got NULL\n"); - return; - } else if (psgl->phead) { - printk("ppc4xx_free_dma_handle: list not empty\n"); - return; - } else if (!psgl->dma_addr) { /* should never happen */ - printk("ppc4xx_free_dma_handle: no dma address\n"); - return; - } - - dma_free_coherent(NULL, DMA_PPC4xx_SIZE, (void *) psgl, 0); -} - -EXPORT_SYMBOL(ppc4xx_alloc_dma_handle); -EXPORT_SYMBOL(ppc4xx_free_dma_handle); -EXPORT_SYMBOL(ppc4xx_add_dma_sgl); -EXPORT_SYMBOL(ppc4xx_delete_dma_sgl_element); -EXPORT_SYMBOL(ppc4xx_enable_dma_sgl); -EXPORT_SYMBOL(ppc4xx_disable_dma_sgl); -EXPORT_SYMBOL(ppc4xx_get_dma_sgl_residue); diff --git a/arch/ppc/syslib/ppc8xx_pic.c b/arch/ppc/syslib/ppc8xx_pic.c deleted file mode 100644 index bce9a75c80e3..000000000000 --- a/arch/ppc/syslib/ppc8xx_pic.c +++ /dev/null @@ -1,126 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ppc8xx_pic.h" - -extern int cpm_get_irq(void); - -/* The 8xx internal interrupt controller. It is usually - * the only interrupt controller. Some boards, like the MBX and - * Sandpoint have the 8259 as a secondary controller. Depending - * upon the processor type, the internal controller can have as - * few as 16 interrupts or as many as 64. We could use the - * "clear_bit()" and "set_bit()" functions like other platforms, - * but they are overkill for us. - */ - -static void m8xx_mask_irq(unsigned int irq_nr) -{ - int bit, word; - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] &= ~(1 << (31-bit)); - out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]); -} - -static void m8xx_unmask_irq(unsigned int irq_nr) -{ - int bit, word; - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] |= (1 << (31-bit)); - out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]); -} - -static void m8xx_end_irq(unsigned int irq_nr) -{ - if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)) - && irq_desc[irq_nr].action) { - int bit, word; - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] |= (1 << (31-bit)); - out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]); - } -} - - -static void m8xx_mask_and_ack(unsigned int irq_nr) -{ - int bit, word; - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] &= ~(1 << (31-bit)); - out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]); - out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend, 1 << (31-bit)); -} - -struct hw_interrupt_type ppc8xx_pic = { - .typename = " 8xx SIU ", - .enable = m8xx_unmask_irq, - .disable = m8xx_mask_irq, - .ack = m8xx_mask_and_ack, - .end = m8xx_end_irq, -}; - -/* - * We either return a valid interrupt or -1 if there is nothing pending - */ -int -m8xx_get_irq(struct pt_regs *regs) -{ - int irq; - - /* For MPC8xx, read the SIVEC register and shift the bits down - * to get the irq number. - */ - irq = in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec) >> 26; - - /* - * When we read the sivec without an interrupt to process, we will - * get back SIU_LEVEL7. In this case, return -1 - */ - if (irq == CPM_INTERRUPT) - irq = CPM_IRQ_OFFSET + cpm_get_irq(); -#if defined(CONFIG_PCI) - else if (irq == ISA_BRIDGE_INT) { - int isa_irq; - - if ((isa_irq = i8259_poll(regs)) >= 0) - irq = I8259_IRQ_OFFSET + isa_irq; - } -#endif /* CONFIG_PCI */ - else if (irq == SIU_LEVEL7) - irq = -1; - - return irq; -} - -#if defined(CONFIG_MBX) && defined(CONFIG_PCI) -/* Only the MBX uses the external 8259. This allows us to catch standard - * drivers that may mess up the internal interrupt controllers, and also - * allow them to run without modification on the MBX. - */ -void mbx_i8259_action(int irq, void *dev_id, struct pt_regs *regs) -{ - /* This interrupt handler never actually gets called. It is - * installed only to unmask the 8259 cascade interrupt in the SIU - * and to make the 8259 cascade interrupt visible in /proc/interrupts. - */ -} -#endif /* CONFIG_PCI */ diff --git a/arch/ppc/syslib/ppc8xx_pic.h b/arch/ppc/syslib/ppc8xx_pic.h deleted file mode 100644 index 53bcd97ef7f5..000000000000 --- a/arch/ppc/syslib/ppc8xx_pic.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _PPC_KERNEL_PPC8xx_H -#define _PPC_KERNEL_PPC8xx_H - -#include -#include - -extern struct hw_interrupt_type ppc8xx_pic; - -void m8xx_do_IRQ(struct pt_regs *regs, - int cpu); -int m8xx_get_irq(struct pt_regs *regs); - -#ifdef CONFIG_MBX -#include -#include -void mbx_i8259_action(int cpl, void *dev_id, struct pt_regs *regs); -#endif - -#endif /* _PPC_KERNEL_PPC8xx_H */ diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c deleted file mode 100644 index 837183c24dfc..000000000000 --- a/arch/ppc/syslib/ppc_sys.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * PPC System library functions - * - * Maintainer: Kumar Gala - * - * Copyright 2005 Freescale Semiconductor Inc. - * Copyright 2005 MontaVista, Inc. by Vitaly Bordug - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include - -int (*ppc_sys_device_fixup) (struct platform_device * pdev); - -static int ppc_sys_inited; -static int ppc_sys_func_inited; - -static const char *ppc_sys_func_names[] = { - [PPC_SYS_FUNC_DUMMY] = "dummy", - [PPC_SYS_FUNC_ETH] = "eth", - [PPC_SYS_FUNC_UART] = "uart", - [PPC_SYS_FUNC_HLDC] = "hldc", - [PPC_SYS_FUNC_USB] = "usb", - [PPC_SYS_FUNC_IRDA] = "irda", -}; - -void __init identify_ppc_sys_by_id(u32 id) -{ - unsigned int i = 0; - while (1) { - if ((ppc_sys_specs[i].mask & id) == ppc_sys_specs[i].value) - break; - i++; - } - - cur_ppc_sys_spec = &ppc_sys_specs[i]; - - return; -} - -void __init identify_ppc_sys_by_name(char *name) -{ - unsigned int i = 0; - while (ppc_sys_specs[i].ppc_sys_name[0]) { - if (!strcmp(ppc_sys_specs[i].ppc_sys_name, name)) - break; - i++; - } - cur_ppc_sys_spec = &ppc_sys_specs[i]; - - return; -} - -static int __init count_sys_specs(void) -{ - int i = 0; - while (ppc_sys_specs[i].ppc_sys_name[0]) - i++; - return i; -} - -static int __init find_chip_by_name_and_id(char *name, u32 id) -{ - int ret = -1; - unsigned int i = 0; - unsigned int j = 0; - unsigned int dups = 0; - - unsigned char matched[count_sys_specs()]; - - while (ppc_sys_specs[i].ppc_sys_name[0]) { - if (!strcmp(ppc_sys_specs[i].ppc_sys_name, name)) - matched[j++] = i; - i++; - } - - ret = i; - - if (j != 0) { - for (i = 0; i < j; i++) { - if ((ppc_sys_specs[matched[i]].mask & id) == - ppc_sys_specs[matched[i]].value) { - ret = matched[i]; - dups++; - } - } - ret = (dups == 1) ? ret : (-1 * dups); - } - return ret; -} - -void __init identify_ppc_sys_by_name_and_id(char *name, u32 id) -{ - int i = find_chip_by_name_and_id(name, id); - BUG_ON(i < 0); - cur_ppc_sys_spec = &ppc_sys_specs[i]; -} - -/* Update all memory resources by paddr, call before platform_device_register */ -void __init -ppc_sys_fixup_mem_resource(struct platform_device *pdev, phys_addr_t paddr) -{ - int i; - for (i = 0; i < pdev->num_resources; i++) { - struct resource *r = &pdev->resource[i]; - if (((r->flags & IORESOURCE_MEM) == IORESOURCE_MEM) && - ((r->flags & PPC_SYS_IORESOURCE_FIXUPPED) != PPC_SYS_IORESOURCE_FIXUPPED)) { - r->start += paddr; - r->end += paddr; - r->flags |= PPC_SYS_IORESOURCE_FIXUPPED; - } - } -} - -/* Get platform_data pointer out of platform device, call before platform_device_register */ -void *__init ppc_sys_get_pdata(enum ppc_sys_devices dev) -{ - return ppc_sys_platform_devices[dev].dev.platform_data; -} - -void ppc_sys_device_remove(enum ppc_sys_devices dev) -{ - unsigned int i; - - if (ppc_sys_inited) { - platform_device_unregister(&ppc_sys_platform_devices[dev]); - } else { - if (cur_ppc_sys_spec == NULL) - return; - for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) - if (cur_ppc_sys_spec->device_list[i] == dev) - cur_ppc_sys_spec->device_list[i] = -1; - } -} - -/* Platform-notify mapping - * Helper function for BSP code to assign board-specific platfom-divice bits - */ - -void platform_notify_map(const struct platform_notify_dev_map *map, - struct device *dev) -{ - struct platform_device *pdev; - int len, idx; - const char *s; - - /* do nothing if no device or no bus_id */ - if (!dev || !dev->bus_id) - return; - - /* call per device map */ - while (map->bus_id != NULL) { - idx = -1; - s = strrchr(dev->bus_id, '.'); - if (s != NULL) { - idx = (int)simple_strtol(s + 1, NULL, 10); - len = s - dev->bus_id; - } else { - s = dev->bus_id; - len = strlen(dev->bus_id); - } - - if (!strncmp(dev->bus_id, map->bus_id, len)) { - pdev = container_of(dev, struct platform_device, dev); - map->rtn(pdev, idx); - } - map++; - } -} - -/* - Function assignment stuff. - Intended to work as follows: - the device name defined in foo_devices.c will be concatenated with :"func", - where func is string map of respective function from platfom_device_func enum - - The PPC_SYS_FUNC_DUMMY function is intended to remove all assignments, making the device to appear - in platform bus with unmodified name. - */ - -/* - Here we'll replace .name pointers with fixed-length strings - Hereby, this should be called *before* any func stuff triggeded. - */ -void ppc_sys_device_initfunc(void) -{ - int i; - const char *name; - static char new_names[NUM_PPC_SYS_DEVS][BUS_ID_SIZE]; - enum ppc_sys_devices cur_dev; - - /* If inited yet, do nothing */ - if (ppc_sys_func_inited) - return; - - for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) { - if ((cur_dev = cur_ppc_sys_spec->device_list[i]) < 0) - continue; - - if (ppc_sys_platform_devices[cur_dev].name) { - /*backup name */ - name = ppc_sys_platform_devices[cur_dev].name; - strlcpy(new_names[i], name, BUS_ID_SIZE); - ppc_sys_platform_devices[cur_dev].name = new_names[i]; - } - } - - ppc_sys_func_inited = 1; -} - -/*The "engine" of the func stuff. Here we either concat specified function string description - to the name, or remove it if PPC_SYS_FUNC_DUMMY parameter is passed here*/ -void ppc_sys_device_setfunc(enum ppc_sys_devices dev, - enum platform_device_func func) -{ - char *s; - char *name = (char *)ppc_sys_platform_devices[dev].name; - char tmp[BUS_ID_SIZE]; - - if (!ppc_sys_func_inited) { - printk(KERN_ERR "Unable to alter function - not inited!\n"); - return; - } - - if (ppc_sys_inited) { - platform_device_unregister(&ppc_sys_platform_devices[dev]); - } - - if ((s = (char *)strchr(name, ':')) != NULL) { /* reassign */ - /* Either change the name after ':' or remove func modifications */ - if (func != PPC_SYS_FUNC_DUMMY) - strlcpy(s + 1, ppc_sys_func_names[func], BUS_ID_SIZE); - else - *s = 0; - } else if (func != PPC_SYS_FUNC_DUMMY) { - /* do assignment if it is not just "clear" request */ - sprintf(tmp, "%s:%s", name, ppc_sys_func_names[func]); - strlcpy(name, tmp, BUS_ID_SIZE); - } - - if (ppc_sys_inited) { - platform_device_register(&ppc_sys_platform_devices[dev]); - } -} - -void ppc_sys_device_disable(enum ppc_sys_devices dev) -{ - BUG_ON(cur_ppc_sys_spec == NULL); - - /*Check if it is enabled*/ - if(!(cur_ppc_sys_spec->config[dev] & PPC_SYS_CONFIG_DISABLED)) { - if (ppc_sys_inited) { - platform_device_unregister(&ppc_sys_platform_devices[dev]); - } - cur_ppc_sys_spec->config[dev] |= PPC_SYS_CONFIG_DISABLED; - } -} - -void ppc_sys_device_enable(enum ppc_sys_devices dev) -{ - BUG_ON(cur_ppc_sys_spec == NULL); - - /*Check if it is disabled*/ - if(cur_ppc_sys_spec->config[dev] & PPC_SYS_CONFIG_DISABLED) { - if (ppc_sys_inited) { - platform_device_register(&ppc_sys_platform_devices[dev]); - } - cur_ppc_sys_spec->config[dev] &= ~PPC_SYS_CONFIG_DISABLED; - } - -} - -void ppc_sys_device_enable_all(void) -{ - enum ppc_sys_devices cur_dev; - int i; - - for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) { - cur_dev = cur_ppc_sys_spec->device_list[i]; - ppc_sys_device_enable(cur_dev); - } -} - -void ppc_sys_device_disable_all(void) -{ - enum ppc_sys_devices cur_dev; - int i; - - for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) { - cur_dev = cur_ppc_sys_spec->device_list[i]; - ppc_sys_device_disable(cur_dev); - } -} - - -static int __init ppc_sys_init(void) -{ - unsigned int i, dev_id, ret = 0; - - BUG_ON(cur_ppc_sys_spec == NULL); - - for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) { - dev_id = cur_ppc_sys_spec->device_list[i]; - if ((dev_id != -1) && - !(cur_ppc_sys_spec->config[dev_id] & PPC_SYS_CONFIG_DISABLED)) { - if (ppc_sys_device_fixup != NULL) - ppc_sys_device_fixup(&ppc_sys_platform_devices - [dev_id]); - if (platform_device_register - (&ppc_sys_platform_devices[dev_id])) { - ret = 1; - printk(KERN_ERR - "unable to register device %d\n", - dev_id); - } - } - } - - ppc_sys_inited = 1; - return ret; -} - -subsys_initcall(ppc_sys_init); diff --git a/arch/ppc/syslib/pq2_devices.c b/arch/ppc/syslib/pq2_devices.c deleted file mode 100644 index fefbc217a56d..000000000000 --- a/arch/ppc/syslib/pq2_devices.c +++ /dev/null @@ -1,393 +0,0 @@ -/* - * PQ2 Device descriptions - * - * Maintainer: Kumar Gala - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include - -struct platform_device ppc_sys_platform_devices[] = { - [MPC82xx_CPM_FCC1] = { - .name = "fsl-cpm-fcc", - .id = 1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "fcc_regs", - .start = 0x11300, - .end = 0x1131f, - .flags = IORESOURCE_MEM, - }, - { - .name = "fcc_pram", - .start = 0x8400, - .end = 0x84ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_FCC1, - .end = SIU_INT_FCC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_FCC2] = { - .name = "fsl-cpm-fcc", - .id = 2, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "fcc_regs", - .start = 0x11320, - .end = 0x1133f, - .flags = IORESOURCE_MEM, - }, - { - .name = "fcc_pram", - .start = 0x8500, - .end = 0x85ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_FCC2, - .end = SIU_INT_FCC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_FCC3] = { - .name = "fsl-cpm-fcc", - .id = 3, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "fcc_regs", - .start = 0x11340, - .end = 0x1135f, - .flags = IORESOURCE_MEM, - }, - { - .name = "fcc_pram", - .start = 0x8600, - .end = 0x86ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_FCC3, - .end = SIU_INT_FCC3, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_I2C] = { - .name = "fsl-cpm-i2c", - .id = 1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "i2c_mem", - .start = 0x11860, - .end = 0x118BF, - .flags = IORESOURCE_MEM, - }, - { - .name = "i2c_pram", - .start = 0x8afc, - .end = 0x8afd, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_I2C, - .end = SIU_INT_I2C, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_SCC1] = { - .name = "fsl-cpm-scc", - .id = 1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0x11A00, - .end = 0x11A1F, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x8000, - .end = 0x80ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SCC1, - .end = SIU_INT_SCC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_SCC2] = { - .name = "fsl-cpm-scc", - .id = 2, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0x11A20, - .end = 0x11A3F, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x8100, - .end = 0x81ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SCC2, - .end = SIU_INT_SCC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_SCC3] = { - .name = "fsl-cpm-scc", - .id = 3, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0x11A40, - .end = 0x11A5F, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x8200, - .end = 0x82ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SCC3, - .end = SIU_INT_SCC3, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_SCC4] = { - .name = "fsl-cpm-scc", - .id = 4, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "regs", - .start = 0x11A60, - .end = 0x11A7F, - .flags = IORESOURCE_MEM, - }, - { - .name = "pram", - .start = 0x8300, - .end = 0x83ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SCC4, - .end = SIU_INT_SCC4, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_SPI] = { - .name = "fsl-cpm-spi", - .id = 1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "spi_mem", - .start = 0x11AA0, - .end = 0x11AFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "spi_pram", - .start = 0x89fc, - .end = 0x89fd, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SPI, - .end = SIU_INT_SPI, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_MCC1] = { - .name = "fsl-cpm-mcc", - .id = 1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "mcc_mem", - .start = 0x11B30, - .end = 0x11B3F, - .flags = IORESOURCE_MEM, - }, - { - .name = "mcc_pram", - .start = 0x8700, - .end = 0x877f, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_MCC1, - .end = SIU_INT_MCC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_MCC2] = { - .name = "fsl-cpm-mcc", - .id = 2, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "mcc_mem", - .start = 0x11B50, - .end = 0x11B5F, - .flags = IORESOURCE_MEM, - }, - { - .name = "mcc_pram", - .start = 0x8800, - .end = 0x887f, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_MCC2, - .end = SIU_INT_MCC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_SMC1] = { - .name = "fsl-cpm-smc", - .id = 1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "smc_mem", - .start = 0x11A80, - .end = 0x11A8F, - .flags = IORESOURCE_MEM, - }, - { - .name = "smc_pram", - .start = 0x87fc, - .end = 0x87fd, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SMC1, - .end = SIU_INT_SMC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_SMC2] = { - .name = "fsl-cpm-smc", - .id = 2, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "smc_mem", - .start = 0x11A90, - .end = 0x11A9F, - .flags = IORESOURCE_MEM, - }, - { - .name = "smc_pram", - .start = 0x88fc, - .end = 0x88fd, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SMC2, - .end = SIU_INT_SMC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC82xx_CPM_USB] = { - .name = "fsl-cpm-usb", - .id = 1, - .num_resources = 3, - .resource = (struct resource[]) { - { - .name = "usb_mem", - .start = 0x11b60, - .end = 0x11b78, - .flags = IORESOURCE_MEM, - }, - { - .name = "usb_pram", - .start = 0x8b00, - .end = 0x8bff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_USB, - .end = SIU_INT_USB, - .flags = IORESOURCE_IRQ, - }, - - }, - }, - [MPC82xx_SEC1] = { - .name = "fsl-sec", - .id = 1, - .num_resources = 1, - .resource = (struct resource[]) { - { - .name = "sec_mem", - .start = 0x40000, - .end = 0x52fff, - .flags = IORESOURCE_MEM, - }, - }, - }, - [MPC82xx_MDIO_BB] = { - .name = "fsl-bb-mdio", - .id = 0, - .num_resources = 0, - }, -}; - -static int __init mach_mpc82xx_fixup(struct platform_device *pdev) -{ - ppc_sys_fixup_mem_resource(pdev, CPM_MAP_ADDR); - return 0; -} - -static int __init mach_mpc82xx_init(void) -{ - if (ppc_md.progress) - ppc_md.progress("mach_mpc82xx_init:enter", 0); - ppc_sys_device_fixup = mach_mpc82xx_fixup; - return 0; -} - -postcore_initcall(mach_mpc82xx_init); diff --git a/arch/ppc/syslib/pq2_sys.c b/arch/ppc/syslib/pq2_sys.c deleted file mode 100644 index 9c85300846c7..000000000000 --- a/arch/ppc/syslib/pq2_sys.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * PQ2 System descriptions - * - * Maintainer: Kumar Gala - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include - -#include - -struct ppc_sys_spec *cur_ppc_sys_spec; -struct ppc_sys_spec ppc_sys_specs[] = { - /* below is a list of the 8260 family of processors */ - { - .ppc_sys_name = "8250", - .mask = 0x0000ff00, - .value = 0x00000000, - .num_devices = 12, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, - MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC2, MPC82xx_CPM_SMC1, - MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, - } - }, - { - .ppc_sys_name = "8255", - .mask = 0x0000ff00, - .value = 0x00000000, - .num_devices = 11, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, - MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4, - MPC82xx_CPM_MCC2, MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, - MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, - } - }, - { - .ppc_sys_name = "8260", - .mask = 0x0000ff00, - .value = 0x00000000, - .num_devices = 13, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, - MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2, - MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, - MPC82xx_CPM_I2C, - } - }, - { - .ppc_sys_name = "8264", - .mask = 0x0000ff00, - .value = 0x00000000, - .num_devices = 13, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, - MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2, - MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, - MPC82xx_CPM_I2C, - } - }, - { - .ppc_sys_name = "8265", - .mask = 0x0000ff00, - .value = 0x00000000, - .num_devices = 13, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, - MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2, - MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, - MPC82xx_CPM_I2C, - } - }, - { - .ppc_sys_name = "8266", - .mask = 0x0000ff00, - .value = 0x00000000, - .num_devices = 13, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, - MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2, - MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, - MPC82xx_CPM_I2C, - } - }, - /* below is a list of the 8272 family of processors */ - { - .ppc_sys_name = "8247", - .mask = 0x0000ff00, - .value = 0x00000d00, - .num_devices = 10, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, - MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1, - MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, - MPC82xx_CPM_USB, - }, - }, - { - .ppc_sys_name = "8248", - .mask = 0x0000ff00, - .value = 0x00000c00, - .num_devices = 12, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, - MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4, - MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, - MPC82xx_CPM_I2C, MPC82xx_CPM_USB, MPC82xx_SEC1, - }, - }, - { - .ppc_sys_name = "8271", - .mask = 0x0000ff00, - .value = 0x00000d00, - .num_devices = 10, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, - MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1, - MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, - MPC82xx_CPM_USB, - }, - }, - { - .ppc_sys_name = "8272", - .mask = 0x0000ff00, - .value = 0x00000c00, - .num_devices = 13, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, - MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4, - MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, - MPC82xx_CPM_I2C, MPC82xx_CPM_USB, MPC82xx_SEC1, - MPC82xx_MDIO_BB, - }, - }, - /* below is a list of the 8280 family of processors */ - { - .ppc_sys_name = "8270", - .mask = 0x0000ff00, - .value = 0x00000a00, - .num_devices = 12, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, - MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC2, MPC82xx_CPM_SMC1, - MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, - }, - }, - { - .ppc_sys_name = "8275", - .mask = 0x0000ff00, - .value = 0x00000a00, - .num_devices = 12, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, - MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC2, MPC82xx_CPM_SMC1, - MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, - }, - }, - { - .ppc_sys_name = "8280", - .mask = 0x0000ff00, - .value = 0x00000a00, - .num_devices = 13, - .device_list = (enum ppc_sys_devices[]) - { - MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, - MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2, - MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, - MPC82xx_CPM_I2C, - }, - }, - { - /* default match */ - .ppc_sys_name = "", - .mask = 0x00000000, - .value = 0x00000000, - }, -}; diff --git a/arch/ppc/syslib/prep_nvram.c b/arch/ppc/syslib/prep_nvram.c deleted file mode 100644 index 474dccbc4a8a..000000000000 --- a/arch/ppc/syslib/prep_nvram.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) 1998 Corey Minyard - * - * This reads the NvRAM on PReP compliant machines (generally from IBM or - * Motorola). Motorola kept the format of NvRAM in their ROM, PPCBUG, the - * same, long after they had stopped producing PReP compliant machines. So - * this code is useful in those cases as well. - * - */ -#include -#include -#include -#include - -#include -#include -#include -#include - -static char nvramData[MAX_PREP_NVRAM]; -static NVRAM_MAP *nvram=(NVRAM_MAP *)&nvramData[0]; - -unsigned char prep_nvram_read_val(int addr) -{ - outb(addr, PREP_NVRAM_AS0); - outb(addr>>8, PREP_NVRAM_AS1); - return inb(PREP_NVRAM_DATA); -} - -void prep_nvram_write_val(int addr, - unsigned char val) -{ - outb(addr, PREP_NVRAM_AS0); - outb(addr>>8, PREP_NVRAM_AS1); - outb(val, PREP_NVRAM_DATA); -} - -void __init init_prep_nvram(void) -{ - unsigned char *nvp; - int i; - int nvramSize; - - /* - * The following could fail if the NvRAM were corrupt but - * we expect the boot firmware to have checked its checksum - * before boot - */ - nvp = (char *) &nvram->Header; - for (i=0; iHeader.GEAddress+nvram->Header.GELength; - if(nvramSize>MAX_PREP_NVRAM) - { - /* - * NvRAM is too large - */ - nvram->Header.GELength=0; - return; - } - - /* - * Read the remainder of the PReP NvRAM - */ - nvp = (char *) &nvram->GEArea[0]; - for (i=sizeof(HEADER); iGEArea)) < nvram->Header.GELength) - && (*cp == '\0')) - { - cp++; - } - - if ((cp - ((char *) nvram->GEArea)) < nvram->Header.GELength) { - return cp; - } else { - return NULL; - } -} diff --git a/arch/ppc/syslib/qspan_pci.c b/arch/ppc/syslib/qspan_pci.c deleted file mode 100644 index 7a97c7440b30..000000000000 --- a/arch/ppc/syslib/qspan_pci.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - * QSpan pci routines. - * Most 8xx boards use the QSpan PCI bridge. The config address register - * is located 0x500 from the base of the bridge control/status registers. - * The data register is located at 0x504. - * This is a two step operation. First, the address register is written, - * then the data register is read/written as required. - * I don't know what to do about interrupts (yet). - * - * The RPX Classic implementation shares a chip select for normal - * PCI access and QSpan control register addresses. The selection is - * further selected by a bit setting in a board control register. - * Although it should happen, we disable interrupts during this operation - * to make sure some driver doesn't accidentally access the PCI while - * we have switched the chip select. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - - -/* - * This blows...... - * When reading the configuration space, if something does not respond - * the bus times out and we get a machine check interrupt. So, the - * good ol' exception tables come to mind to trap it and return some - * value. - * - * On an error we just return a -1, since that is what the caller wants - * returned if nothing is present. I copied this from __get_user_asm, - * with the only difference of returning -1 instead of EFAULT. - * There is an associated hack in the machine check trap code. - * - * The QSPAN is also a big endian device, that is it makes the PCI - * look big endian to us. This presents a problem for the Linux PCI - * functions, which assume little endian. For example, we see the - * first 32-bit word like this: - * ------------------------ - * | Device ID | Vendor ID | - * ------------------------ - * If we read/write as a double word, that's OK. But in our world, - * when read as a word, device ID is at location 0, not location 2 as - * the little endian PCI would believe. We have to switch bits in - * the PCI addresses given to us to get the data to/from the correct - * byte lanes. - * - * The QSPAN only supports 4 bits of "slot" in the dev_fn instead of 5. - * It always forces the MS bit to zero. Therefore, dev_fn values - * greater than 128 are returned as "no device found" errors. - * - * The QSPAN can only perform long word (32-bit) configuration cycles. - * The "offset" must have the two LS bits set to zero. Read operations - * require we read the entire word and then sort out what should be - * returned. Write operations other than long word require that we - * read the long word, update the proper word or byte, then write the - * entire long word back. - * - * PCI Bridge hack. We assume (correctly) that bus 0 is the primary - * PCI bus from the QSPAN. If we are called with a bus number other - * than zero, we create a Type 1 configuration access that a downstream - * PCI bridge will interpret. - */ - -#define __get_qspan_pci_config(x, addr, op) \ - __asm__ __volatile__( \ - "1: "op" %0,0(%1)\n" \ - " eieio\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r"(x) : "r"(addr) : " %0") - -#define QS_CONFIG_ADDR ((volatile uint *)(PCI_CSR_ADDR + 0x500)) -#define QS_CONFIG_DATA ((volatile uint *)(PCI_CSR_ADDR + 0x504)) - -#define mk_config_addr(bus, dev, offset) \ - (((bus)<<16) | ((dev)<<8) | (offset & 0xfc)) - -#define mk_config_type1(bus, dev, offset) \ - mk_config_addr(bus, dev, offset) | 1; - -static DEFINE_SPINLOCK(pcibios_lock); - -int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned char *val) -{ - uint temp; - u_char *cp; -#ifdef CONFIG_RPXCLASSIC - unsigned long flags; -#endif - - if ((bus > 7) || (dev_fn > 127)) { - *val = 0xff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - -#ifdef CONFIG_RPXCLASSIC - /* disable interrupts */ - spin_lock_irqsave(&pcibios_lock, flags); - *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; - eieio(); -#endif - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - __get_qspan_pci_config(temp, QS_CONFIG_DATA, "lwz"); - -#ifdef CONFIG_RPXCLASSIC - *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; - eieio(); - spin_unlock_irqrestore(&pcibios_lock, flags); -#endif - - offset ^= 0x03; - cp = ((u_char *)&temp) + (offset & 0x03); - *val = *cp; - return PCIBIOS_SUCCESSFUL; -} - -int qspan_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned short *val) -{ - uint temp; - ushort *sp; -#ifdef CONFIG_RPXCLASSIC - unsigned long flags; -#endif - - if ((bus > 7) || (dev_fn > 127)) { - *val = 0xffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - -#ifdef CONFIG_RPXCLASSIC - /* disable interrupts */ - spin_lock_irqsave(&pcibios_lock, flags); - *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; - eieio(); -#endif - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - __get_qspan_pci_config(temp, QS_CONFIG_DATA, "lwz"); - offset ^= 0x02; - -#ifdef CONFIG_RPXCLASSIC - *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; - eieio(); - spin_unlock_irqrestore(&pcibios_lock, flags); -#endif - - sp = ((ushort *)&temp) + ((offset >> 1) & 1); - *val = *sp; - return PCIBIOS_SUCCESSFUL; -} - -int qspan_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned int *val) -{ -#ifdef CONFIG_RPXCLASSIC - unsigned long flags; -#endif - - if ((bus > 7) || (dev_fn > 127)) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - -#ifdef CONFIG_RPXCLASSIC - /* disable interrupts */ - spin_lock_irqsave(&pcibios_lock, flags); - *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; - eieio(); -#endif - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - __get_qspan_pci_config(*val, QS_CONFIG_DATA, "lwz"); - -#ifdef CONFIG_RPXCLASSIC - *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; - eieio(); - spin_unlock_irqrestore(&pcibios_lock, flags); -#endif - - return PCIBIOS_SUCCESSFUL; -} - -int qspan_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned char val) -{ - uint temp; - u_char *cp; -#ifdef CONFIG_RPXCLASSIC - unsigned long flags; -#endif - - if ((bus > 7) || (dev_fn > 127)) - return PCIBIOS_DEVICE_NOT_FOUND; - - qspan_pcibios_read_config_dword(bus, dev_fn, offset, &temp); - - offset ^= 0x03; - cp = ((u_char *)&temp) + (offset & 0x03); - *cp = val; - -#ifdef CONFIG_RPXCLASSIC - /* disable interrupts */ - spin_lock_irqsave(&pcibios_lock, flags); - *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; - eieio(); -#endif - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - *QS_CONFIG_DATA = temp; - -#ifdef CONFIG_RPXCLASSIC - *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; - eieio(); - spin_unlock_irqrestore(&pcibios_lock, flags); -#endif - - return PCIBIOS_SUCCESSFUL; -} - -int qspan_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned short val) -{ - uint temp; - ushort *sp; -#ifdef CONFIG_RPXCLASSIC - unsigned long flags; -#endif - - if ((bus > 7) || (dev_fn > 127)) - return PCIBIOS_DEVICE_NOT_FOUND; - - qspan_pcibios_read_config_dword(bus, dev_fn, offset, &temp); - - offset ^= 0x02; - sp = ((ushort *)&temp) + ((offset >> 1) & 1); - *sp = val; - -#ifdef CONFIG_RPXCLASSIC - /* disable interrupts */ - spin_lock_irqsave(&pcibios_lock, flags); - *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; - eieio(); -#endif - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - *QS_CONFIG_DATA = temp; - -#ifdef CONFIG_RPXCLASSIC - *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; - eieio(); - spin_unlock_irqrestore(&pcibios_lock, flags); -#endif - - return PCIBIOS_SUCCESSFUL; -} - -int qspan_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn, - unsigned char offset, unsigned int val) -{ -#ifdef CONFIG_RPXCLASSIC - unsigned long flags; -#endif - - if ((bus > 7) || (dev_fn > 127)) - return PCIBIOS_DEVICE_NOT_FOUND; - -#ifdef CONFIG_RPXCLASSIC - /* disable interrupts */ - spin_lock_irqsave(&pcibios_lock, flags); - *((uint *)RPX_CSR_ADDR) &= ~BCSR2_QSPACESEL; - eieio(); -#endif - - if (bus == 0) - *QS_CONFIG_ADDR = mk_config_addr(bus, dev_fn, offset); - else - *QS_CONFIG_ADDR = mk_config_type1(bus, dev_fn, offset); - *(unsigned int *)QS_CONFIG_DATA = val; - -#ifdef CONFIG_RPXCLASSIC - *((uint *)RPX_CSR_ADDR) |= BCSR2_QSPACESEL; - eieio(); - spin_unlock_irqrestore(&pcibios_lock, flags); -#endif - - return PCIBIOS_SUCCESSFUL; -} - -int qspan_pcibios_find_device(unsigned short vendor, unsigned short dev_id, - unsigned short index, unsigned char *bus_ptr, - unsigned char *dev_fn_ptr) -{ - int num, devfn; - unsigned int x, vendev; - - if (vendor == 0xffff) - return PCIBIOS_BAD_VENDOR_ID; - vendev = (dev_id << 16) + vendor; - num = 0; - for (devfn = 0; devfn < 32; devfn++) { - qspan_pcibios_read_config_dword(0, devfn<<3, PCI_VENDOR_ID, &x); - if (x == vendev) { - if (index == num) { - *bus_ptr = 0; - *dev_fn_ptr = devfn<<3; - return PCIBIOS_SUCCESSFUL; - } - ++num; - } - } - return PCIBIOS_DEVICE_NOT_FOUND; -} - -int qspan_pcibios_find_class(unsigned int class_code, unsigned short index, - unsigned char *bus_ptr, unsigned char *dev_fn_ptr) -{ - int devnr, x, num; - - num = 0; - for (devnr = 0; devnr < 32; devnr++) { - qspan_pcibios_read_config_dword(0, devnr<<3, PCI_CLASS_REVISION, &x); - if ((x>>8) == class_code) { - if (index == num) { - *bus_ptr = 0; - *dev_fn_ptr = devnr<<3; - return PCIBIOS_SUCCESSFUL; - } - ++num; - } - } - return PCIBIOS_DEVICE_NOT_FOUND; -} - -void __init -m8xx_pcibios_fixup(void) -{ - /* Lots to do here, all board and configuration specific. */ -} - -void __init -m8xx_setup_pci_ptrs(void) -{ - set_config_access_method(qspan); - - ppc_md.pcibios_fixup = m8xx_pcibios_fixup; -} - diff --git a/arch/ppc/syslib/todc_time.c b/arch/ppc/syslib/todc_time.c deleted file mode 100644 index a8168b8e5683..000000000000 --- a/arch/ppc/syslib/todc_time.c +++ /dev/null @@ -1,511 +0,0 @@ -/* - * Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818 - * Real Time Clocks/Timekeepers. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * Depending on the hardware on your board and your board design, the - * RTC/NVRAM may be accessed either directly (like normal memory) or via - * address/data registers. If your board uses the direct method, set - * 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and - * 'nvram_as1' NULL. If your board uses address/data regs to access nvram, - * set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the - * address of the upper byte (leave NULL if using mc146818), and set - * 'nvram_data' to the address of the 8-bit data register. - * - * In order to break the assumption that the RTC and NVRAM are accessed by - * the same mechanism, you need to explicitly set 'ppc_md.rtc_read_val' and - * 'ppc_md.rtc_write_val', otherwise the values of 'ppc_md.rtc_read_val' - * and 'ppc_md.rtc_write_val' will be used. - * - * Note: Even though the documentation for the various RTC chips say that it - * take up to a second before it starts updating once the 'R' bit is - * cleared, they always seem to update even though we bang on it many - * times a second. This is true, except for the Dallas Semi 1746/1747 - * (possibly others). Those chips seem to have a real problem whenever - * we set the 'R' bit before reading them, they basically stop counting. - * --MAG - */ - -/* - * 'todc_info' should be initialized in your *_setup.c file to - * point to a fully initialized 'todc_info_t' structure. - * This structure holds all the register offsets for your particular - * TODC/RTC chip. - * TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you. - */ - -#ifdef RTC_FREQ_SELECT -#undef RTC_FREQ_SELECT -#define RTC_FREQ_SELECT control_b /* Register A */ -#endif - -#ifdef RTC_CONTROL -#undef RTC_CONTROL -#define RTC_CONTROL control_a /* Register B */ -#endif - -#ifdef RTC_INTR_FLAGS -#undef RTC_INTR_FLAGS -#define RTC_INTR_FLAGS watchdog /* Register C */ -#endif - -#ifdef RTC_VALID -#undef RTC_VALID -#define RTC_VALID interrupts /* Register D */ -#endif - -/* Access routines when RTC accessed directly (like normal memory) */ -u_char -todc_direct_read_val(int addr) -{ - return readb((void __iomem *)(todc_info->nvram_data + addr)); -} - -void -todc_direct_write_val(int addr, unsigned char val) -{ - writeb(val, (void __iomem *)(todc_info->nvram_data + addr)); - return; -} - -/* Access routines for accessing m48txx type chips via addr/data regs */ -u_char -todc_m48txx_read_val(int addr) -{ - outb(addr, todc_info->nvram_as0); - outb(addr>>todc_info->as0_bits, todc_info->nvram_as1); - return inb(todc_info->nvram_data); -} - -void -todc_m48txx_write_val(int addr, unsigned char val) -{ - outb(addr, todc_info->nvram_as0); - outb(addr>>todc_info->as0_bits, todc_info->nvram_as1); - outb(val, todc_info->nvram_data); - return; -} - -/* Access routines for accessing mc146818 type chips via addr/data regs */ -u_char -todc_mc146818_read_val(int addr) -{ - outb_p(addr, todc_info->nvram_as0); - return inb_p(todc_info->nvram_data); -} - -void -todc_mc146818_write_val(int addr, unsigned char val) -{ - outb_p(addr, todc_info->nvram_as0); - outb_p(val, todc_info->nvram_data); -} - - -/* - * Routines to make RTC chips with NVRAM buried behind an addr/data pair - * have the NVRAM and clock regs appear at the same level. - * The NVRAM will appear to start at addr 0 and the clock regs will appear - * to start immediately after the NVRAM (actually, start at offset - * todc_info->nvram_size). - */ -static inline u_char -todc_read_val(int addr) -{ - u_char val; - - if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) { - if (addr < todc_info->nvram_size) { /* NVRAM */ - ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr); - val = ppc_md.rtc_read_val(todc_info->nvram_data_reg); - } - else { /* Clock Reg */ - addr -= todc_info->nvram_size; - val = ppc_md.rtc_read_val(addr); - } - } - else { - val = ppc_md.rtc_read_val(addr); - } - - return val; -} - -static inline void -todc_write_val(int addr, u_char val) -{ - if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) { - if (addr < todc_info->nvram_size) { /* NVRAM */ - ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr); - ppc_md.rtc_write_val(todc_info->nvram_data_reg, val); - } - else { /* Clock Reg */ - addr -= todc_info->nvram_size; - ppc_md.rtc_write_val(addr, val); - } - } - else { - ppc_md.rtc_write_val(addr, val); - } -} - -/* - * TODC routines - * - * There is some ugly stuff in that there are assumptions for the mc146818. - * - * Assumptions: - * - todc_info->control_a has the offset as mc146818 Register B reg - * - todc_info->control_b has the offset as mc146818 Register A reg - * - m48txx control reg's write enable or 'W' bit is same as - * mc146818 Register B 'SET' bit (i.e., 0x80) - * - * These assumptions were made to make the code simpler. - */ -long __init -todc_time_init(void) -{ - u_char cntl_b; - - if (!ppc_md.rtc_read_val) - ppc_md.rtc_read_val = ppc_md.nvram_read_val; - if (!ppc_md.rtc_write_val) - ppc_md.rtc_write_val = ppc_md.nvram_write_val; - - cntl_b = todc_read_val(todc_info->control_b); - - if (todc_info->rtc_type == TODC_TYPE_MC146818) { - if ((cntl_b & 0x70) != 0x20) { - printk(KERN_INFO "TODC %s %s\n", - "real-time-clock was stopped.", - "Now starting..."); - cntl_b &= ~0x70; - cntl_b |= 0x20; - } - - todc_write_val(todc_info->control_b, cntl_b); - } else if (todc_info->rtc_type == TODC_TYPE_DS17285) { - u_char mode; - - mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A); - /* Make sure countdown clear is not set */ - mode &= ~0x40; - /* Enable oscillator, extended register set */ - mode |= 0x30; - todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode); - - } else if (todc_info->rtc_type == TODC_TYPE_DS1501) { - u_char month; - - todc_info->enable_read = TODC_DS1501_CNTL_B_TE; - todc_info->enable_write = TODC_DS1501_CNTL_B_TE; - - month = todc_read_val(todc_info->month); - - if ((month & 0x80) == 0x80) { - printk(KERN_INFO "TODC %s %s\n", - "real-time-clock was stopped.", - "Now starting..."); - month &= ~0x80; - todc_write_val(todc_info->month, month); - } - - cntl_b &= ~TODC_DS1501_CNTL_B_TE; - todc_write_val(todc_info->control_b, cntl_b); - } else { /* must be a m48txx type */ - u_char cntl_a; - - todc_info->enable_read = TODC_MK48TXX_CNTL_A_R; - todc_info->enable_write = TODC_MK48TXX_CNTL_A_W; - - cntl_a = todc_read_val(todc_info->control_a); - - /* Check & clear STOP bit in control B register */ - if (cntl_b & TODC_MK48TXX_DAY_CB) { - printk(KERN_INFO "TODC %s %s\n", - "real-time-clock was stopped.", - "Now starting..."); - - cntl_a |= todc_info->enable_write; - cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */ - - todc_write_val(todc_info->control_a, cntl_a); - todc_write_val(todc_info->control_b, cntl_b); - } - - /* Make sure READ & WRITE bits are cleared. */ - cntl_a &= ~(todc_info->enable_write | - todc_info->enable_read); - todc_write_val(todc_info->control_a, cntl_a); - } - - return 0; -} - -/* - * There is some ugly stuff in that there are assumptions that for a mc146818, - * the todc_info->control_a has the offset of the mc146818 Register B reg and - * that the register'ss 'SET' bit is the same as the m48txx's write enable - * bit in the control register of the m48txx (i.e., 0x80). - * - * It was done to make the code look simpler. - */ -ulong -todc_get_rtc_time(void) -{ - uint year = 0, mon = 0, day = 0, hour = 0, min = 0, sec = 0; - uint limit, i; - u_char save_control, uip = 0; - - spin_lock(&rtc_lock); - save_control = todc_read_val(todc_info->control_a); - - if (todc_info->rtc_type != TODC_TYPE_MC146818) { - limit = 1; - - switch (todc_info->rtc_type) { - case TODC_TYPE_DS1553: - case TODC_TYPE_DS1557: - case TODC_TYPE_DS1743: - case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */ - case TODC_TYPE_DS1747: - case TODC_TYPE_DS17285: - break; - default: - todc_write_val(todc_info->control_a, - (save_control | todc_info->enable_read)); - } - } - else { - limit = 100000000; - } - - for (i=0; irtc_type == TODC_TYPE_MC146818) { - uip = todc_read_val(todc_info->RTC_FREQ_SELECT); - } - - sec = todc_read_val(todc_info->seconds) & 0x7f; - min = todc_read_val(todc_info->minutes) & 0x7f; - hour = todc_read_val(todc_info->hours) & 0x3f; - day = todc_read_val(todc_info->day_of_month) & 0x3f; - mon = todc_read_val(todc_info->month) & 0x1f; - year = todc_read_val(todc_info->year) & 0xff; - - if (todc_info->rtc_type == TODC_TYPE_MC146818) { - uip |= todc_read_val(todc_info->RTC_FREQ_SELECT); - if ((uip & RTC_UIP) == 0) break; - } - } - - if (todc_info->rtc_type != TODC_TYPE_MC146818) { - switch (todc_info->rtc_type) { - case TODC_TYPE_DS1553: - case TODC_TYPE_DS1557: - case TODC_TYPE_DS1743: - case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */ - case TODC_TYPE_DS1747: - case TODC_TYPE_DS17285: - break; - default: - save_control &= ~(todc_info->enable_read); - todc_write_val(todc_info->control_a, - save_control); - } - } - spin_unlock(&rtc_lock); - - if ((todc_info->rtc_type != TODC_TYPE_MC146818) || - ((save_control & RTC_DM_BINARY) == 0) || - RTC_ALWAYS_BCD) { - - BCD_TO_BIN(sec); - BCD_TO_BIN(min); - BCD_TO_BIN(hour); - BCD_TO_BIN(day); - BCD_TO_BIN(mon); - BCD_TO_BIN(year); - } - - year = year + 1900; - if (year < 1970) { - year += 100; - } - - return mktime(year, mon, day, hour, min, sec); -} - -int -todc_set_rtc_time(unsigned long nowtime) -{ - struct rtc_time tm; - u_char save_control, save_freq_select = 0; - - spin_lock(&rtc_lock); - to_tm(nowtime, &tm); - - save_control = todc_read_val(todc_info->control_a); - - /* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */ - todc_write_val(todc_info->control_a, - (save_control | todc_info->enable_write)); - save_control &= ~(todc_info->enable_write); /* in case it was set */ - - if (todc_info->rtc_type == TODC_TYPE_MC146818) { - save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT); - todc_write_val(todc_info->RTC_FREQ_SELECT, - save_freq_select | RTC_DIV_RESET2); - } - - - tm.tm_year = (tm.tm_year - 1900) % 100; - - if ((todc_info->rtc_type != TODC_TYPE_MC146818) || - ((save_control & RTC_DM_BINARY) == 0) || - RTC_ALWAYS_BCD) { - - BIN_TO_BCD(tm.tm_sec); - BIN_TO_BCD(tm.tm_min); - BIN_TO_BCD(tm.tm_hour); - BIN_TO_BCD(tm.tm_mon); - BIN_TO_BCD(tm.tm_mday); - BIN_TO_BCD(tm.tm_year); - } - - todc_write_val(todc_info->seconds, tm.tm_sec); - todc_write_val(todc_info->minutes, tm.tm_min); - todc_write_val(todc_info->hours, tm.tm_hour); - todc_write_val(todc_info->month, tm.tm_mon); - todc_write_val(todc_info->day_of_month, tm.tm_mday); - todc_write_val(todc_info->year, tm.tm_year); - - todc_write_val(todc_info->control_a, save_control); - - if (todc_info->rtc_type == TODC_TYPE_MC146818) { - todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select); - } - spin_unlock(&rtc_lock); - - return 0; -} - -/* - * Manipulates read bit to reliably read seconds at a high rate. - */ -static unsigned char __init todc_read_timereg(int addr) -{ - unsigned char save_control = 0, val; - - switch (todc_info->rtc_type) { - case TODC_TYPE_DS1553: - case TODC_TYPE_DS1557: - case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */ - case TODC_TYPE_DS1747: - case TODC_TYPE_DS17285: - case TODC_TYPE_MC146818: - break; - default: - save_control = todc_read_val(todc_info->control_a); - todc_write_val(todc_info->control_a, - (save_control | todc_info->enable_read)); - } - val = todc_read_val(addr); - - switch (todc_info->rtc_type) { - case TODC_TYPE_DS1553: - case TODC_TYPE_DS1557: - case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */ - case TODC_TYPE_DS1747: - case TODC_TYPE_DS17285: - case TODC_TYPE_MC146818: - break; - default: - save_control &= ~(todc_info->enable_read); - todc_write_val(todc_info->control_a, save_control); - } - - return val; -} - -/* - * This was taken from prep_setup.c - * Use the NVRAM RTC to time a second to calibrate the decrementer. - */ -void __init -todc_calibrate_decr(void) -{ - ulong freq; - ulong tbl, tbu; - long i, loop_count; - u_char sec; - - todc_time_init(); - - /* - * Actually this is bad for precision, we should have a loop in - * which we only read the seconds counter. todc_read_val writes - * the address bytes on every call and this takes a lot of time. - * Perhaps an nvram_wait_change method returning a time - * stamp with a loop count as parameter would be the solution. - */ - /* - * Need to make sure the tbl doesn't roll over so if tbu increments - * during this test, we need to do it again. - */ - loop_count = 0; - - sec = todc_read_timereg(todc_info->seconds) & 0x7f; - - do { - tbu = get_tbu(); - - for (i = 0 ; i < 10000000 ; i++) {/* may take up to 1 second */ - tbl = get_tbl(); - - if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) { - break; - } - } - - sec = todc_read_timereg(todc_info->seconds) & 0x7f; - - for (i = 0 ; i < 10000000 ; i++) { /* Should take 1 second */ - freq = get_tbl(); - - if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) { - break; - } - } - - freq -= tbl; - } while ((get_tbu() != tbu) && (++loop_count < 2)); - - printk("time_init: decrementer frequency = %lu.%.6lu MHz\n", - freq/1000000, freq%1000000); - - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); - - return; -} diff --git a/arch/ppc/syslib/virtex_devices.c b/arch/ppc/syslib/virtex_devices.c deleted file mode 100644 index 7322781be1c6..000000000000 --- a/arch/ppc/syslib/virtex_devices.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Virtex hard ppc405 core common device listing - * - * Copyright 2005-2007 Secret Lab Technologies Ltd. - * Copyright 2005 Freescale Semiconductor Inc. - * Copyright 2002-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * UARTLITE: shortcut macro for single instance - */ -#define XPAR_UARTLITE(num) { \ - .name = "uartlite", \ - .id = num, \ - .num_resources = 2, \ - .resource = (struct resource[]) { \ - { \ - .start = XPAR_UARTLITE_##num##_BASEADDR + 3, \ - .end = XPAR_UARTLITE_##num##_HIGHADDR, \ - .flags = IORESOURCE_MEM, \ - }, \ - { \ - .start = XPAR_INTC_0_UARTLITE_##num##_VEC_ID, \ - .flags = IORESOURCE_IRQ, \ - }, \ - }, \ -} - -/* - * Full UART: shortcut macro for single instance + platform data structure - */ -#define XPAR_UART(num) { \ - .mapbase = XPAR_UARTNS550_##num##_BASEADDR + 3, \ - .irq = XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \ - .iotype = UPIO_MEM, \ - .uartclk = XPAR_UARTNS550_##num##_CLOCK_FREQ_HZ, \ - .flags = UPF_BOOT_AUTOCONF, \ - .regshift = 2, \ -} - -/* - * SystemACE: shortcut macro for single instance - */ -#define XPAR_SYSACE(num) { \ - .name = "xsysace", \ - .id = XPAR_SYSACE_##num##_DEVICE_ID, \ - .num_resources = 2, \ - .resource = (struct resource[]) { \ - { \ - .start = XPAR_SYSACE_##num##_BASEADDR, \ - .end = XPAR_SYSACE_##num##_HIGHADDR, \ - .flags = IORESOURCE_MEM, \ - }, \ - { \ - .start = XPAR_INTC_0_SYSACE_##num##_VEC_ID, \ - .flags = IORESOURCE_IRQ, \ - }, \ - }, \ -} - -/* - * ML300/ML403 Video Device: shortcut macro for single instance - */ -#define XPAR_TFT(num) { \ - .name = "xilinxfb", \ - .id = num, \ - .num_resources = 1, \ - .resource = (struct resource[]) { \ - { \ - .start = XPAR_TFT_##num##_BASEADDR, \ - .end = XPAR_TFT_##num##_BASEADDR+7, \ - .flags = IORESOURCE_IO, \ - }, \ - }, \ -} - -#define XPAR_AC97_CONTROLLER_REFERENCE(num) { \ - .name = "ml403_ac97cr", \ - .id = num, \ - .num_resources = 3, \ - .resource = (struct resource[]) { \ - { \ - .start = XPAR_OPB_AC97_CONTROLLER_REF_##num##_BASEADDR, \ - .end = XPAR_OPB_AC97_CONTROLLER_REF_##num##_HIGHADDR, \ - .flags = IORESOURCE_MEM, \ - }, \ - { \ - .start = XPAR_INTC_0_AC97_CONTROLLER_REF_##num##_PLAYBACK_VEC_ID, \ - .end = XPAR_INTC_0_AC97_CONTROLLER_REF_##num##_PLAYBACK_VEC_ID, \ - .flags = IORESOURCE_IRQ, \ - }, \ - { \ - .start = XPAR_INTC_0_AC97_CONTROLLER_REF_##num##_RECORD_VEC_ID, \ - .end = XPAR_INTC_0_AC97_CONTROLLER_REF_##num##_RECORD_VEC_ID, \ - .flags = IORESOURCE_IRQ, \ - }, \ - }, \ -} - -/* UART 8250 driver platform data table */ -struct plat_serial8250_port virtex_serial_platform_data[] = { -#if defined(XPAR_UARTNS550_0_BASEADDR) - XPAR_UART(0), -#endif -#if defined(XPAR_UARTNS550_1_BASEADDR) - XPAR_UART(1), -#endif -#if defined(XPAR_UARTNS550_2_BASEADDR) - XPAR_UART(2), -#endif -#if defined(XPAR_UARTNS550_3_BASEADDR) - XPAR_UART(3), -#endif -#if defined(XPAR_UARTNS550_4_BASEADDR) - XPAR_UART(4), -#endif -#if defined(XPAR_UARTNS550_5_BASEADDR) - XPAR_UART(5), -#endif -#if defined(XPAR_UARTNS550_6_BASEADDR) - XPAR_UART(6), -#endif -#if defined(XPAR_UARTNS550_7_BASEADDR) - XPAR_UART(7), -#endif - { }, /* terminated by empty record */ -}; - - -struct platform_device virtex_platform_devices[] = { - /* UARTLITE instances */ -#if defined(XPAR_UARTLITE_0_BASEADDR) - XPAR_UARTLITE(0), -#endif -#if defined(XPAR_UARTLITE_1_BASEADDR) - XPAR_UARTLITE(1), -#endif -#if defined(XPAR_UARTLITE_2_BASEADDR) - XPAR_UARTLITE(2), -#endif -#if defined(XPAR_UARTLITE_3_BASEADDR) - XPAR_UARTLITE(3), -#endif -#if defined(XPAR_UARTLITE_4_BASEADDR) - XPAR_UARTLITE(4), -#endif -#if defined(XPAR_UARTLITE_5_BASEADDR) - XPAR_UARTLITE(5), -#endif -#if defined(XPAR_UARTLITE_6_BASEADDR) - XPAR_UARTLITE(6), -#endif -#if defined(XPAR_UARTLITE_7_BASEADDR) - XPAR_UARTLITE(7), -#endif - - /* Full UART instances */ -#if defined(XPAR_UARTNS550_0_BASEADDR) - { - .name = "serial8250", - .id = 0, - .dev.platform_data = virtex_serial_platform_data, - }, -#endif - - /* SystemACE instances */ -#if defined(XPAR_SYSACE_0_BASEADDR) - XPAR_SYSACE(0), -#endif -#if defined(XPAR_SYSACE_1_BASEADDR) - XPAR_SYSACE(1), -#endif - -#if defined(XPAR_TFT_0_BASEADDR) - XPAR_TFT(0), -#endif -#if defined(XPAR_TFT_1_BASEADDR) - XPAR_TFT(1), -#endif -#if defined(XPAR_TFT_2_BASEADDR) - XPAR_TFT(2), -#endif -#if defined(XPAR_TFT_3_BASEADDR) - XPAR_TFT(3), -#endif - - /* AC97 Controller Reference instances */ -#if defined(XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR) - XPAR_AC97_CONTROLLER_REFERENCE(0), -#endif -#if defined(XPAR_OPB_AC97_CONTROLLER_REF_1_BASEADDR) - XPAR_AC97_CONTROLLER_REFERENCE(1), -#endif -}; - -/* Early serial support functions */ -static void __init -virtex_early_serial_init(int num, struct plat_serial8250_port *pdata) -{ -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - struct uart_port serial_req; - - memset(&serial_req, 0, sizeof(serial_req)); - serial_req.mapbase = pdata->mapbase; - serial_req.membase = pdata->membase; - serial_req.irq = pdata->irq; - serial_req.uartclk = pdata->uartclk; - serial_req.regshift = pdata->regshift; - serial_req.iotype = pdata->iotype; - serial_req.flags = pdata->flags; - gen550_init(num, &serial_req); -#endif -} - -void __init -virtex_early_serial_map(void) -{ -#ifdef CONFIG_SERIAL_8250 - struct plat_serial8250_port *pdata; - int i = 0; - - pdata = virtex_serial_platform_data; - while(pdata && pdata->flags) { - pdata->membase = ioremap(pdata->mapbase, 0x100); - virtex_early_serial_init(i, pdata); - pdata++; - i++; - } -#endif /* CONFIG_SERIAL_8250 */ -} - -/* - * default fixup routine; do nothing and return success. - * - * Reimplement this routine in your custom board support file to - * override the default behaviour - */ -int __attribute__ ((weak)) -virtex_device_fixup(struct platform_device *dev) -{ - return 0; -} - -static int __init virtex_init(void) -{ - struct platform_device *index = virtex_platform_devices; - unsigned int ret = 0; - int i; - - for (i = 0; i < ARRAY_SIZE(virtex_platform_devices); i++, index++) { - if (virtex_device_fixup(index) != 0) - continue; - - if (platform_device_register(index)) { - ret = 1; - printk(KERN_ERR "cannot register dev %s:%d\n", - index->name, index->id); - } - } - return ret; -} - -subsys_initcall(virtex_init); diff --git a/arch/ppc/syslib/virtex_devices.h b/arch/ppc/syslib/virtex_devices.h deleted file mode 100644 index 6ebd9b4b8f1c..000000000000 --- a/arch/ppc/syslib/virtex_devices.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Common support header for virtex ppc405 platforms - * - * Copyright 2007 Secret Lab Technologies Ltd. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef __ASM_VIRTEX_DEVICES_H__ -#define __ASM_VIRTEX_DEVICES_H__ - -#include -#include - -void __init virtex_early_serial_map(void); - -/* Prototype for device fixup routine. Implement this routine in the - * board specific fixup code and the generic setup code will call it for - * each device is the platform device list. - * - * If the hook returns a non-zero value, then the device will not get - * registered with the platform bus - */ -int virtex_device_fixup(struct platform_device *dev); - -/* SPI Controller IP */ -struct xspi_platform_data { - s16 bus_num; - u16 num_chipselect; - u32 speed_hz; -}; - -#endif /* __ASM_VIRTEX_DEVICES_H__ */ diff --git a/arch/ppc/syslib/xilinx_pic.c b/arch/ppc/syslib/xilinx_pic.c deleted file mode 100644 index 3b82333e96d8..000000000000 --- a/arch/ppc/syslib/xilinx_pic.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Interrupt controller driver for Xilinx Virtex-II Pro. - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include -#include -#include -#include -#include -#include - -/* No one else should require these constants, so define them locally here. */ -#define ISR 0 /* Interrupt Status Register */ -#define IPR 1 /* Interrupt Pending Register */ -#define IER 2 /* Interrupt Enable Register */ -#define IAR 3 /* Interrupt Acknowledge Register */ -#define SIE 4 /* Set Interrupt Enable bits */ -#define CIE 5 /* Clear Interrupt Enable bits */ -#define IVR 6 /* Interrupt Vector Register */ -#define MER 7 /* Master Enable Register */ - -#if XPAR_XINTC_USE_DCR == 0 -static volatile u32 *intc; -#define intc_out_be32(addr, mask) out_be32((addr), (mask)) -#define intc_in_be32(addr) in_be32((addr)) -#else -#define intc XPAR_INTC_0_BASEADDR -#define intc_out_be32(addr, mask) mtdcr((addr), (mask)) -#define intc_in_be32(addr) mfdcr((addr)) -#endif - -static void -xilinx_intc_enable(unsigned int irq) -{ - unsigned long mask = (0x00000001 << (irq & 31)); - pr_debug("enable: %d\n", irq); - intc_out_be32(intc + SIE, mask); -} - -static void -xilinx_intc_disable(unsigned int irq) -{ - unsigned long mask = (0x00000001 << (irq & 31)); - pr_debug("disable: %d\n", irq); - intc_out_be32(intc + CIE, mask); -} - -static void -xilinx_intc_disable_and_ack(unsigned int irq) -{ - unsigned long mask = (0x00000001 << (irq & 31)); - pr_debug("disable_and_ack: %d\n", irq); - intc_out_be32(intc + CIE, mask); - if (!(irq_desc[irq].status & IRQ_LEVEL)) - intc_out_be32(intc + IAR, mask); /* ack edge triggered intr */ -} - -static void -xilinx_intc_end(unsigned int irq) -{ - unsigned long mask = (0x00000001 << (irq & 31)); - - pr_debug("end: %d\n", irq); - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - intc_out_be32(intc + SIE, mask); - /* ack level sensitive intr */ - if (irq_desc[irq].status & IRQ_LEVEL) - intc_out_be32(intc + IAR, mask); - } -} - -static struct hw_interrupt_type xilinx_intc = { - .typename = "Xilinx Interrupt Controller", - .enable = xilinx_intc_enable, - .disable = xilinx_intc_disable, - .ack = xilinx_intc_disable_and_ack, - .end = xilinx_intc_end, -}; - -int -xilinx_pic_get_irq(void) -{ - int irq; - - /* - * NOTE: This function is the one that needs to be improved in - * order to handle multiple interrupt controllers. It currently - * is hardcoded to check for interrupts only on the first INTC. - */ - - irq = intc_in_be32(intc + IVR); - if (irq != -1) - irq = irq; - - pr_debug("get_irq: %d\n", irq); - - return (irq); -} - -void __init -ppc4xx_pic_init(void) -{ - int i; - - /* - * NOTE: The assumption here is that NR_IRQS is 32 or less - * (NR_IRQS is 32 for PowerPC 405 cores by default). - */ -#if (NR_IRQS > 32) -#error NR_IRQS > 32 not supported -#endif - -#if XPAR_XINTC_USE_DCR == 0 - intc = ioremap(XPAR_INTC_0_BASEADDR, 32); - - printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX mapped to 0x%08lX\n", - (unsigned long) XPAR_INTC_0_BASEADDR, (unsigned long) intc); -#else - printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX (DCR)\n", - (unsigned long) XPAR_INTC_0_BASEADDR); -#endif - - /* - * Disable all external interrupts until they are - * explicitly requested. - */ - intc_out_be32(intc + IER, 0); - - /* Acknowledge any pending interrupts just in case. */ - intc_out_be32(intc + IAR, ~(u32) 0); - - /* Turn on the Master Enable. */ - intc_out_be32(intc + MER, 0x3UL); - - ppc_md.get_irq = xilinx_pic_get_irq; - - for (i = 0; i < NR_IRQS; ++i) { - irq_desc[i].chip = &xilinx_intc; - - if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i)) - irq_desc[i].status &= ~IRQ_LEVEL; - else - irq_desc[i].status |= IRQ_LEVEL; - } -} diff --git a/arch/ppc/xmon/Makefile b/arch/ppc/xmon/Makefile deleted file mode 100644 index 9aa260b926f5..000000000000 --- a/arch/ppc/xmon/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# Makefile for xmon - -ifdef CONFIG_8xx -obj-y := start_8xx.o -else -obj-y := start.o -endif -obj-y += xmon.o ppc-dis.o ppc-opc.o subr_prf.o setjmp.o diff --git a/arch/ppc/xmon/ansidecl.h b/arch/ppc/xmon/ansidecl.h deleted file mode 100644 index c9b9f0929e9e..000000000000 --- a/arch/ppc/xmon/ansidecl.h +++ /dev/null @@ -1,141 +0,0 @@ -/* ANSI and traditional C compatibility macros - Copyright 1991, 1992 Free Software Foundation, Inc. - This file is part of the GNU C Library. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* ANSI and traditional C compatibility macros - - ANSI C is assumed if __STDC__ is #defined. - - Macro ANSI C definition Traditional C definition - ----- ---- - ---------- ----------- - ---------- - PTR `void *' `char *' - LONG_DOUBLE `long double' `double' - VOLATILE `volatile' `' - SIGNED `signed' `' - PTRCONST `void *const' `char *' - ANSI_PROTOTYPES 1 not defined - - CONST is also defined, but is obsolete. Just use const. - - DEFUN (name, arglist, args) - - Defines function NAME. - - ARGLIST lists the arguments, separated by commas and enclosed in - parentheses. ARGLIST becomes the argument list in traditional C. - - ARGS list the arguments with their types. It becomes a prototype in - ANSI C, and the type declarations in traditional C. Arguments should - be separated with `AND'. For functions with a variable number of - arguments, the last thing listed should be `DOTS'. - - DEFUN_VOID (name) - - Defines a function NAME, which takes no arguments. - - obsolete -- EXFUN (name, (prototype)) -- obsolete. - - Replaced by PARAMS. Do not use; will disappear someday soon. - Was used in external function declarations. - In ANSI C it is `NAME PROTOTYPE' (so PROTOTYPE should be enclosed in - parentheses). In traditional C it is `NAME()'. - For a function that takes no arguments, PROTOTYPE should be `(void)'. - - PARAMS ((args)) - - We could use the EXFUN macro to handle prototype declarations, but - the name is misleading and the result is ugly. So we just define a - simple macro to handle the parameter lists, as in: - - static int foo PARAMS ((int, char)); - - This produces: `static int foo();' or `static int foo (int, char);' - - EXFUN would have done it like this: - - static int EXFUN (foo, (int, char)); - - but the function is not external...and it's hard to visually parse - the function name out of the mess. EXFUN should be considered - obsolete; new code should be written to use PARAMS. - - For example: - extern int printf PARAMS ((CONST char *format DOTS)); - int DEFUN(fprintf, (stream, format), - FILE *stream AND CONST char *format DOTS) { ... } - void DEFUN_VOID(abort) { ... } -*/ - -#ifndef _ANSIDECL_H - -#define _ANSIDECL_H 1 - - -/* Every source file includes this file, - so they will all get the switch for lint. */ -/* LINTLIBRARY */ - - -#if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(WIN32) -/* All known AIX compilers implement these things (but don't always - define __STDC__). The RISC/OS MIPS compiler defines these things - in SVR4 mode, but does not define __STDC__. */ - -#define PTR void * -#define PTRCONST void *CONST -#define LONG_DOUBLE long double - -#define AND , -#define NOARGS void -#define CONST const -#define VOLATILE volatile -#define SIGNED signed -#define DOTS , ... - -#define EXFUN(name, proto) name proto -#define DEFUN(name, arglist, args) name(args) -#define DEFUN_VOID(name) name(void) - -#define PROTO(type, name, arglist) type name arglist -#define PARAMS(paramlist) paramlist -#define ANSI_PROTOTYPES 1 - -#else /* Not ANSI C. */ - -#define PTR char * -#define PTRCONST PTR -#define LONG_DOUBLE double - -#define AND ; -#define NOARGS -#define CONST -#ifndef const /* some systems define it in header files for non-ansi mode */ -#define const -#endif -#define VOLATILE -#define SIGNED -#define DOTS - -#define EXFUN(name, proto) name() -#define DEFUN(name, arglist, args) name arglist args; -#define DEFUN_VOID(name) name() -#define PROTO(type, name, arglist) type name () -#define PARAMS(paramlist) () - -#endif /* ANSI C. */ - -#endif /* ansidecl.h */ diff --git a/arch/ppc/xmon/nonstdio.h b/arch/ppc/xmon/nonstdio.h deleted file mode 100644 index 0240bc573c96..000000000000 --- a/arch/ppc/xmon/nonstdio.h +++ /dev/null @@ -1,22 +0,0 @@ -typedef int FILE; -extern FILE *xmon_stdin, *xmon_stdout; -#define EOF (-1) -#define stdin xmon_stdin -#define stdout xmon_stdout -#define printf xmon_printf -#define fprintf xmon_fprintf -#define fputs xmon_fputs -#define fgets xmon_fgets -#define putchar xmon_putchar -#define getchar xmon_getchar -#define putc xmon_putc -#define getc xmon_getc -#define fopen(n, m) NULL -#define fflush(f) do {} while (0) -#define fclose(f) do {} while (0) -extern char *fgets(char *, int, void *); -extern void xmon_fprintf(void *, const char *, ...); -extern void xmon_sprintf(char *, const char *, ...); -extern void xmon_puts(char*); - -#define perror(s) printf("%s: no files!\n", (s)) diff --git a/arch/ppc/xmon/ppc-dis.c b/arch/ppc/xmon/ppc-dis.c deleted file mode 100644 index 798ac1a677f6..000000000000 --- a/arch/ppc/xmon/ppc-dis.c +++ /dev/null @@ -1,190 +0,0 @@ -/* ppc-dis.c -- Disassemble PowerPC instructions - Copyright 1994 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "nonstdio.h" -#include "ansidecl.h" -#include "ppc.h" - -static int print_insn_powerpc PARAMS ((FILE *, unsigned long insn, - unsigned memaddr, int dialect)); - -extern void print_address PARAMS((unsigned memaddr)); - -/* Print a big endian PowerPC instruction. For convenience, also - disassemble instructions supported by the Motorola PowerPC 601. */ - -int -print_insn_big_powerpc (FILE *out, unsigned long insn, unsigned memaddr) -{ - return print_insn_powerpc (out, insn, memaddr, - PPC_OPCODE_PPC | PPC_OPCODE_601); -} - -/* Print a PowerPC or POWER instruction. */ - -static int -print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr, - int dialect) -{ - const struct powerpc_opcode *opcode; - const struct powerpc_opcode *opcode_end; - unsigned long op; - - /* Get the major opcode of the instruction. */ - op = PPC_OP (insn); - - /* Find the first match in the opcode table. We could speed this up - a bit by doing a binary search on the major opcode. */ - opcode_end = powerpc_opcodes + powerpc_num_opcodes; - for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) - { - unsigned long table_op; - const unsigned char *opindex; - const struct powerpc_operand *operand; - int invalid; - int need_comma; - int need_paren; - - table_op = PPC_OP (opcode->opcode); - if (op < table_op) - break; - if (op > table_op) - continue; - - if ((insn & opcode->mask) != opcode->opcode - || (opcode->flags & dialect) == 0) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - invalid = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - operand = powerpc_operands + *opindex; - if (operand->extract) - (*operand->extract) (insn, &invalid); - } - if (invalid) - continue; - - /* The instruction is valid. */ - fprintf(out, "%s", opcode->name); - if (opcode->operands[0] != 0) - fprintf(out, "\t"); - - /* Now extract and print the operands. */ - need_comma = 0; - need_paren = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - long value; - - operand = powerpc_operands + *opindex; - - /* Operands that are marked FAKE are simply ignored. We - already made sure that the extract function considered - the instruction to be valid. */ - if ((operand->flags & PPC_OPERAND_FAKE) != 0) - continue; - - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, (int *) 0); - else - { - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & PPC_OPERAND_SIGNED) != 0 - && (value & (1 << (operand->bits - 1))) != 0) - value -= 1 << operand->bits; - } - - /* If the operand is optional, and the value is zero, don't - print anything. */ - if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 - && (operand->flags & PPC_OPERAND_NEXT) == 0 - && value == 0) - continue; - - if (need_comma) - { - fprintf(out, ","); - need_comma = 0; - } - - /* Print the operand as directed by the flags. */ - if ((operand->flags & PPC_OPERAND_GPR) != 0) - fprintf(out, "r%ld", value); - else if ((operand->flags & PPC_OPERAND_FPR) != 0) - fprintf(out, "f%ld", value); - else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) - print_address (memaddr + value); - else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) - print_address (value & 0xffffffff); - else if ((operand->flags & PPC_OPERAND_CR) == 0 - || (dialect & PPC_OPCODE_PPC) == 0) - fprintf(out, "%ld", value); - else - { - if (operand->bits == 3) - fprintf(out, "cr%d", value); - else - { - static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; - int cr; - int cc; - - cr = value >> 2; - if (cr != 0) - fprintf(out, "4*cr%d", cr); - cc = value & 3; - if (cc != 0) - { - if (cr != 0) - fprintf(out, "+"); - fprintf(out, "%s", cbnames[cc]); - } - } - } - - if (need_paren) - { - fprintf(out, ")"); - need_paren = 0; - } - - if ((operand->flags & PPC_OPERAND_PARENS) == 0) - need_comma = 1; - else - { - fprintf(out, "("); - need_paren = 1; - } - } - - /* We have found and printed an instruction; return. */ - return 4; - } - - /* We could not find a match. */ - fprintf(out, ".long 0x%lx", insn); - - return 4; -} diff --git a/arch/ppc/xmon/ppc-opc.c b/arch/ppc/xmon/ppc-opc.c deleted file mode 100644 index 034313cef6e7..000000000000 --- a/arch/ppc/xmon/ppc-opc.c +++ /dev/null @@ -1,2720 +0,0 @@ -/* ppc-opc.c -- PowerPC opcode list - Copyright 1994 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include -#include -#include "ansidecl.h" -#include "ppc.h" - -/* This file holds the PowerPC opcode table. The opcode table - includes almost all of the extended instruction mnemonics. This - permits the disassembler to use them, and simplifies the assembler - logic, at the cost of increasing the table size. The table is - strictly constant data, so the compiler should be able to put it in - the .text section. - - This file also holds the operand table. All knowledge about - inserting operands into instructions and vice-versa is kept in this - file. */ - -/* Local insertion and extraction functions. */ - -static unsigned long insert_bat PARAMS ((unsigned long, long, const char **)); -static long extract_bat PARAMS ((unsigned long, int *)); -static unsigned long insert_bba PARAMS ((unsigned long, long, const char **)); -static long extract_bba PARAMS ((unsigned long, int *)); -static unsigned long insert_bd PARAMS ((unsigned long, long, const char **)); -static long extract_bd PARAMS ((unsigned long, int *)); -static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **)); -static long extract_bdm PARAMS ((unsigned long, int *)); -static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **)); -static long extract_bdp PARAMS ((unsigned long, int *)); -static unsigned long insert_bo PARAMS ((unsigned long, long, const char **)); -static long extract_bo PARAMS ((unsigned long, int *)); -static unsigned long insert_boe PARAMS ((unsigned long, long, const char **)); -static long extract_boe PARAMS ((unsigned long, int *)); -static unsigned long insert_ds PARAMS ((unsigned long, long, const char **)); -static long extract_ds PARAMS ((unsigned long, int *)); -static unsigned long insert_li PARAMS ((unsigned long, long, const char **)); -static long extract_li PARAMS ((unsigned long, int *)); -static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **)); -static long extract_mbe PARAMS ((unsigned long, int *)); -static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **)); -static long extract_mb6 PARAMS ((unsigned long, int *)); -static unsigned long insert_nb PARAMS ((unsigned long, long, const char **)); -static long extract_nb PARAMS ((unsigned long, int *)); -static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **)); -static long extract_nsi PARAMS ((unsigned long, int *)); -static unsigned long insert_ral PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_ram PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_ras PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **)); -static long extract_rbs PARAMS ((unsigned long, int *)); -static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **)); -static long extract_sh6 PARAMS ((unsigned long, int *)); -static unsigned long insert_spr PARAMS ((unsigned long, long, const char **)); -static long extract_spr PARAMS ((unsigned long, int *)); -static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **)); -static long extract_tbr PARAMS ((unsigned long, int *)); - -/* The operands table. - - The fields are bits, shift, signed, insert, extract, flags. */ - -const struct powerpc_operand powerpc_operands[] = -{ - /* The zero index is used to indicate the end of the list of - operands. */ -#define UNUSED (0) - { 0, 0, NULL, NULL, 0 }, - - /* The BA field in an XL form instruction. */ -#define BA (1) -#define BA_MASK (0x1f << 16) - { 5, 16, NULL, NULL, PPC_OPERAND_CR }, - - /* The BA field in an XL form instruction when it must be the same - as the BT field in the same instruction. */ -#define BAT (2) - { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, - - /* The BB field in an XL form instruction. */ -#define BB (3) -#define BB_MASK (0x1f << 11) - { 5, 11, NULL, NULL, PPC_OPERAND_CR }, - - /* The BB field in an XL form instruction when it must be the same - as the BA field in the same instruction. */ -#define BBA (4) - { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, - - /* The BD field in a B form instruction. The lower two bits are - forced to zero. */ -#define BD (5) - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when absolute addressing is - used. */ -#define BDA (6) - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDM (7) - { 16, 0, insert_bdm, extract_bdm, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used - and absolute address is used. */ -#define BDMA (8) - { 16, 0, insert_bdm, extract_bdm, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDP (9) - { 16, 0, insert_bdp, extract_bdp, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used - and absolute addressing is used. */ -#define BDPA (10) - { 16, 0, insert_bdp, extract_bdp, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BF field in an X or XL form instruction. */ -#define BF (11) - { 3, 23, NULL, NULL, PPC_OPERAND_CR }, - - /* An optional BF field. This is used for comparison instructions, - in which an omitted BF field is taken as zero. */ -#define OBF (12) - { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The BFA field in an X or XL form instruction. */ -#define BFA (13) - { 3, 18, NULL, NULL, PPC_OPERAND_CR }, - - /* The BI field in a B form or XL form instruction. */ -#define BI (14) -#define BI_MASK (0x1f << 16) - { 5, 16, NULL, NULL, PPC_OPERAND_CR }, - - /* The BO field in a B form instruction. Certain values are - illegal. */ -#define BO (15) -#define BO_MASK (0x1f << 21) - { 5, 21, insert_bo, extract_bo, 0 }, - - /* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. */ -#define BOE (16) - { 5, 21, insert_boe, extract_boe, 0 }, - - /* The BT field in an X or XL form instruction. */ -#define BT (17) - { 5, 21, NULL, NULL, PPC_OPERAND_CR }, - - /* The condition register number portion of the BI field in a B form - or XL form instruction. This is used for the extended - conditional branch mnemonics, which set the lower two bits of the - BI field. This field is optional. */ -#define CR (18) - { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The D field in a D form instruction. This is a displacement off - a register, and implies that the next operand is a register in - parentheses. */ -#define D (19) - { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ -#define DS (20) - { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The FL1 field in a POWER SC form instruction. */ -#define FL1 (21) - { 4, 12, NULL, NULL, 0 }, - - /* The FL2 field in a POWER SC form instruction. */ -#define FL2 (22) - { 3, 2, NULL, NULL, 0 }, - - /* The FLM field in an XFL form instruction. */ -#define FLM (23) - { 8, 17, NULL, NULL, 0 }, - - /* The FRA field in an X or A form instruction. */ -#define FRA (24) -#define FRA_MASK (0x1f << 16) - { 5, 16, NULL, NULL, PPC_OPERAND_FPR }, - - /* The FRB field in an X or A form instruction. */ -#define FRB (25) -#define FRB_MASK (0x1f << 11) - { 5, 11, NULL, NULL, PPC_OPERAND_FPR }, - - /* The FRC field in an A form instruction. */ -#define FRC (26) -#define FRC_MASK (0x1f << 6) - { 5, 6, NULL, NULL, PPC_OPERAND_FPR }, - - /* The FRS field in an X form instruction or the FRT field in a D, X - or A form instruction. */ -#define FRS (27) -#define FRT (FRS) - { 5, 21, NULL, NULL, PPC_OPERAND_FPR }, - - /* The FXM field in an XFX instruction. */ -#define FXM (28) -#define FXM_MASK (0xff << 12) - { 8, 12, NULL, NULL, 0 }, - - /* The L field in a D or X form instruction. */ -#define L (29) - { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, - - /* The LEV field in a POWER SC form instruction. */ -#define LEV (30) - { 7, 5, NULL, NULL, 0 }, - - /* The LI field in an I form instruction. The lower two bits are - forced to zero. */ -#define LI (31) - { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The LI field in an I form instruction when used as an absolute - address. */ -#define LIA (32) - { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The MB field in an M form instruction. */ -#define MB (33) -#define MB_MASK (0x1f << 6) - { 5, 6, NULL, NULL, 0 }, - - /* The ME field in an M form instruction. */ -#define ME (34) -#define ME_MASK (0x1f << 1) - { 5, 1, NULL, NULL, 0 }, - - /* The MB and ME fields in an M form instruction expressed a single - operand which is a bitmask indicating which bits to select. This - is a two operand form using PPC_OPERAND_NEXT. See the - description in opcode/ppc.h for what this means. */ -#define MBE (35) - { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, - { 32, 0, insert_mbe, extract_mbe, 0 }, - - /* The MB or ME field in an MD or MDS form instruction. The high - bit is wrapped to the low end. */ -#define MB6 (37) -#define ME6 (MB6) -#define MB6_MASK (0x3f << 5) - { 6, 5, insert_mb6, extract_mb6, 0 }, - - /* The NB field in an X form instruction. The value 32 is stored as - 0. */ -#define NB (38) - { 6, 11, insert_nb, extract_nb, 0 }, - - /* The NSI field in a D form instruction. This is the same as the - SI field, only negated. */ -#define NSI (39) - { 16, 0, insert_nsi, extract_nsi, - PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, - - /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ -#define RA (40) -#define RA_MASK (0x1f << 16) - { 5, 16, NULL, NULL, PPC_OPERAND_GPR }, - - /* The RA field in a D or X form instruction which is an updating - load, which means that the RA field may not be zero and may not - equal the RT field. */ -#define RAL (41) - { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR }, - - /* The RA field in an lmw instruction, which has special value - restrictions. */ -#define RAM (42) - { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR }, - - /* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ -#define RAS (43) - { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR }, - - /* The RB field in an X, XO, M, or MDS form instruction. */ -#define RB (44) -#define RB_MASK (0x1f << 11) - { 5, 11, NULL, NULL, PPC_OPERAND_GPR }, - - /* The RB field in an X form instruction when it must be the same as - the RS field in the instruction. This is used for extended - mnemonics like mr. */ -#define RBS (45) - { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, - - /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form - instruction or the RT field in a D, DS, X, XFX or XO form - instruction. */ -#define RS (46) -#define RT (RS) -#define RT_MASK (0x1f << 21) - { 5, 21, NULL, NULL, PPC_OPERAND_GPR }, - - /* The SH field in an X or M form instruction. */ -#define SH (47) -#define SH_MASK (0x1f << 11) - { 5, 11, NULL, NULL, 0 }, - - /* The SH field in an MD form instruction. This is split. */ -#define SH6 (48) -#define SH6_MASK ((0x1f << 11) | (1 << 1)) - { 6, 1, insert_sh6, extract_sh6, 0 }, - - /* The SI field in a D form instruction. */ -#define SI (49) - { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED }, - - /* The SI field in a D form instruction when we accept a wide range - of positive values. */ -#define SISIGNOPT (50) - { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, - - /* The SPR field in an XFX form instruction. This is flipped--the - lower 5 bits are stored in the upper 5 and vice- versa. */ -#define SPR (51) -#define SPR_MASK (0x3ff << 11) - { 10, 11, insert_spr, extract_spr, 0 }, - - /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ -#define SPRBAT (52) -#define SPRBAT_MASK (0x3 << 17) - { 2, 17, NULL, NULL, 0 }, - - /* The SPRG register number in an XFX form m[ft]sprg instruction. */ -#define SPRG (53) -#define SPRG_MASK (0x3 << 16) - { 2, 16, NULL, NULL, 0 }, - - /* The SR field in an X form instruction. */ -#define SR (54) - { 4, 16, NULL, NULL, 0 }, - - /* The SV field in a POWER SC form instruction. */ -#define SV (55) - { 14, 2, NULL, NULL, 0 }, - - /* The TBR field in an XFX form instruction. This is like the SPR - field, but it is optional. */ -#define TBR (56) - { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, - - /* The TO field in a D or X form instruction. */ -#define TO (57) -#define TO_MASK (0x1f << 21) - { 5, 21, NULL, NULL, 0 }, - - /* The U field in an X form instruction. */ -#define U (58) - { 4, 12, NULL, NULL, 0 }, - - /* The UI field in a D form instruction. */ -#define UI (59) - { 16, 0, NULL, NULL, 0 }, -}; - -/* The functions used to insert and extract complicated operands. */ - -/* The BA field in an XL form instruction when it must be the same as - the BT field in the same instruction. This operand is marked FAKE. - The insertion function just copies the BT field into the BA field, - and the extraction function just checks that the fields are the - same. */ - -/*ARGSUSED*/ -static unsigned long -insert_bat(unsigned long insn, long value, const char **errmsg) -{ - return insn | (((insn >> 21) & 0x1f) << 16); -} - -static long -extract_bat(unsigned long insn, int *invalid) -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The BB field in an XL form instruction when it must be the same as - the BA field in the same instruction. This operand is marked FAKE. - The insertion function just copies the BA field into the BB field, - and the extraction function just checks that the fields are the - same. */ - -/*ARGSUSED*/ -static unsigned long -insert_bba(unsigned long insn, long value, const char **errmsg) -{ - return insn | (((insn >> 16) & 0x1f) << 11); -} - -static long -extract_bba(unsigned long insn, int *invalid) -{ - if (invalid != (int *) NULL - && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The BD field in a B form instruction. The lower two bits are - forced to zero. */ - -/*ARGSUSED*/ -static unsigned long -insert_bd(unsigned long insn, long value, const char **errmsg) -{ - return insn | (value & 0xfffc); -} - -/*ARGSUSED*/ -static long -extract_bd(unsigned long insn, int *invalid) -{ - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* The BD field in a B form instruction when the - modifier is used. - This modifier means that the branch is not expected to be taken. - We must set the y bit of the BO field to 1 if the offset is - negative. When extracting, we require that the y bit be 1 and that - the offset be positive, since if the y bit is 0 we just want to - print the normal form of the instruction. */ - -/*ARGSUSED*/ -static unsigned long -insert_bdm(unsigned long insn, long value, const char **errmsg) -{ - if ((value & 0x8000) != 0) - insn |= 1 << 21; - return insn | (value & 0xfffc); -} - -static long -extract_bdm(unsigned long insn, int *invalid) -{ - if (invalid != (int *) NULL - && ((insn & (1 << 21)) == 0 - || (insn & (1 << 15)) == 0)) - *invalid = 1; - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* The BD field in a B form instruction when the + modifier is used. - This is like BDM, above, except that the branch is expected to be - taken. */ - -/*ARGSUSED*/ -static unsigned long -insert_bdp(unsigned long insn, long value, const char **errmsg) -{ - if ((value & 0x8000) == 0) - insn |= 1 << 21; - return insn | (value & 0xfffc); -} - -static long -extract_bdp(unsigned long insn, int *invalid) -{ - if (invalid != (int *) NULL - && ((insn & (1 << 21)) == 0 - || (insn & (1 << 15)) != 0)) - *invalid = 1; - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* Check for legal values of a BO field. */ - -static int -valid_bo (long value) -{ - /* Certain encodings have bits that are required to be zero. These - are (z must be zero, y may be anything): - 001zy - 011zy - 1z00y - 1z01y - 1z1zz - */ - switch (value & 0x14) - { - default: - case 0: - return 1; - case 0x4: - return (value & 0x2) == 0; - case 0x10: - return (value & 0x8) == 0; - case 0x14: - return value == 0x14; - } -} - -/* The BO field in a B form instruction. Warn about attempts to set - the field to an illegal value. */ - -static unsigned long -insert_bo(unsigned long insn, long value, const char **errmsg) -{ - if (errmsg != (const char **) NULL - && ! valid_bo (value)) - *errmsg = "invalid conditional option"; - return insn | ((value & 0x1f) << 21); -} - -static long -extract_bo(unsigned long insn, int *invalid) -{ - long value; - - value = (insn >> 21) & 0x1f; - if (invalid != (int *) NULL - && ! valid_bo (value)) - *invalid = 1; - return value; -} - -/* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. When - extracting it, we force it to be even. */ - -static unsigned long -insert_boe(unsigned long insn, long value, const char **errmsg) -{ - if (errmsg != (const char **) NULL) - { - if (! valid_bo (value)) - *errmsg = "invalid conditional option"; - else if ((value & 1) != 0) - *errmsg = "attempt to set y bit when using + or - modifier"; - } - return insn | ((value & 0x1f) << 21); -} - -static long -extract_boe(unsigned long insn, int *invalid) -{ - long value; - - value = (insn >> 21) & 0x1f; - if (invalid != (int *) NULL - && ! valid_bo (value)) - *invalid = 1; - return value & 0x1e; -} - -/* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ - -/*ARGSUSED*/ -static unsigned long -insert_ds(unsigned long insn, long value, const char **errmsg) -{ - return insn | (value & 0xfffc); -} - -/*ARGSUSED*/ -static long -extract_ds(unsigned long insn, int *invalid) -{ - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* The LI field in an I form instruction. The lower two bits are - forced to zero. */ - -/*ARGSUSED*/ -static unsigned long -insert_li(unsigned long insn, long value, const char **errmsg) -{ - return insn | (value & 0x3fffffc); -} - -/*ARGSUSED*/ -static long -extract_li(unsigned long insn, int *invalid) -{ - if ((insn & 0x2000000) != 0) - return (insn & 0x3fffffc) - 0x4000000; - else - return insn & 0x3fffffc; -} - -/* The MB and ME fields in an M form instruction expressed as a single - operand which is itself a bitmask. The extraction function always - marks it as invalid, since we never want to recognize an - instruction which uses a field of this type. */ - -static unsigned long -insert_mbe(unsigned long insn, long value, const char **errmsg) -{ - unsigned long uval; - int mb, me; - - uval = value; - - if (uval == 0) - { - if (errmsg != (const char **) NULL) - *errmsg = "illegal bitmask"; - return insn; - } - - me = 31; - while ((uval & 1) == 0) - { - uval >>= 1; - --me; - } - - mb = me; - uval >>= 1; - while ((uval & 1) != 0) - { - uval >>= 1; - --mb; - } - - if (uval != 0) - { - if (errmsg != (const char **) NULL) - *errmsg = "illegal bitmask"; - } - - return insn | (mb << 6) | (me << 1); -} - -static long -extract_mbe(unsigned long insn, int *invalid) -{ - long ret; - int mb, me; - int i; - - if (invalid != (int *) NULL) - *invalid = 1; - - ret = 0; - mb = (insn >> 6) & 0x1f; - me = (insn >> 1) & 0x1f; - for (i = mb; i < me; i++) - ret |= 1 << (31 - i); - return ret; -} - -/* The MB or ME field in an MD or MDS form instruction. The high bit - is wrapped to the low end. */ - -/*ARGSUSED*/ -static unsigned long -insert_mb6(unsigned long insn, long value, const char **errmsg) -{ - return insn | ((value & 0x1f) << 6) | (value & 0x20); -} - -/*ARGSUSED*/ -static long -extract_mb6(unsigned long insn, int *invalid) -{ - return ((insn >> 6) & 0x1f) | (insn & 0x20); -} - -/* The NB field in an X form instruction. The value 32 is stored as - 0. */ - -static unsigned long -insert_nb(unsigned long insn, long value, const char **errmsg) -{ - if (value < 0 || value > 32) - *errmsg = "value out of range"; - if (value == 32) - value = 0; - return insn | ((value & 0x1f) << 11); -} - -/*ARGSUSED*/ -static long -extract_nb(unsigned long insn, int *invalid) -{ - long ret; - - ret = (insn >> 11) & 0x1f; - if (ret == 0) - ret = 32; - return ret; -} - -/* The NSI field in a D form instruction. This is the same as the SI - field, only negated. The extraction function always marks it as - invalid, since we never want to recognize an instruction which uses - a field of this type. */ - -/*ARGSUSED*/ -static unsigned long -insert_nsi(unsigned long insn, long value, const char **errmsg) -{ - return insn | ((- value) & 0xffff); -} - -static long -extract_nsi(unsigned long insn, int *invalid) -{ - if (invalid != (int *) NULL) - *invalid = 1; - if ((insn & 0x8000) != 0) - return - ((insn & 0xffff) - 0x10000); - else - return - (insn & 0xffff); -} - -/* The RA field in a D or X form instruction which is an updating - load, which means that the RA field may not be zero and may not - equal the RT field. */ - -static unsigned long -insert_ral(unsigned long insn, long value, const char **errmsg) -{ - if (value == 0 - || value == ((insn >> 21) & 0x1f)) - *errmsg = "invalid register operand when updating"; - return insn | ((value & 0x1f) << 16); -} - -/* The RA field in an lmw instruction, which has special value - restrictions. */ - -static unsigned long -insert_ram(unsigned long insn, long value, const char **errmsg) -{ - if (value >= ((insn >> 21) & 0x1f)) - *errmsg = "index register in load range"; - return insn | ((value & 0x1f) << 16); -} - -/* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ - -static unsigned long -insert_ras(unsigned long insn, long value, const char **errmsg) -{ - if (value == 0) - *errmsg = "invalid register operand when updating"; - return insn | ((value & 0x1f) << 16); -} - -/* The RB field in an X form instruction when it must be the same as - the RS field in the instruction. This is used for extended - mnemonics like mr. This operand is marked FAKE. The insertion - function just copies the BT field into the BA field, and the - extraction function just checks that the fields are the same. */ - -/*ARGSUSED*/ -static unsigned long -insert_rbs(unsigned long insn, long value, const char **errmsg) -{ - return insn | (((insn >> 21) & 0x1f) << 11); -} - -static long -extract_rbs(unsigned long insn, int *invalid) -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The SH field in an MD form instruction. This is split. */ - -/*ARGSUSED*/ -static unsigned long -insert_sh6(unsigned long insn, long value, const char **errmsg) -{ - return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); -} - -/*ARGSUSED*/ -static long -extract_sh6(unsigned long insn, int *invalid) -{ - return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); -} - -/* The SPR field in an XFX form instruction. This is flipped--the - lower 5 bits are stored in the upper 5 and vice- versa. */ - -static unsigned long -insert_spr(unsigned long insn, long value, const char **errmsg) -{ - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); -} - -static long -extract_spr(unsigned long insn, int *invalid) -{ - return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); -} - -/* The TBR field in an XFX instruction. This is just like SPR, but it - is optional. When TBR is omitted, it must be inserted as 268 (the - magic number of the TB register). These functions treat 0 - (indicating an omitted optional operand) as 268. This means that - ``mftb 4,0'' is not handled correctly. This does not matter very - much, since the architecture manual does not define mftb as - accepting any values other than 268 or 269. */ - -#define TB (268) - -static unsigned long -insert_tbr(unsigned long insn, long value, const char **errmsg) -{ - if (value == 0) - value = TB; - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); -} - -static long -extract_tbr(unsigned long insn, int *invalid) -{ - long ret; - - ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); - if (ret == TB) - ret = 0; - return ret; -} - -/* Macros used to form opcodes. */ - -/* The main opcode. */ -#define OP(x) (((x) & 0x3f) << 26) -#define OP_MASK OP (0x3f) - -/* The main opcode combined with a trap code in the TO field of a D - form instruction. Used for extended mnemonics for the trap - instructions. */ -#define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21)) -#define OPTO_MASK (OP_MASK | TO_MASK) - -/* The main opcode combined with a comparison size bit in the L field - of a D form or X form instruction. Used for extended mnemonics for - the comparison instructions. */ -#define OPL(x,l) (OP (x) | (((l) & 1) << 21)) -#define OPL_MASK OPL (0x3f,1) - -/* An A form instruction. */ -#define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1)) -#define A_MASK A (0x3f, 0x1f, 1) - -/* An A_MASK with the FRB field fixed. */ -#define AFRB_MASK (A_MASK | FRB_MASK) - -/* An A_MASK with the FRC field fixed. */ -#define AFRC_MASK (A_MASK | FRC_MASK) - -/* An A_MASK with the FRA and FRC fields fixed. */ -#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) - -/* A B form instruction. */ -#define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1)) -#define B_MASK B (0x3f, 1, 1) - -/* A B form instruction setting the BO field. */ -#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21)) -#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) - -/* A BBO_MASK with the y bit of the BO field removed. This permits - matching a conditional branch regardless of the setting of the y - bit. */ -#define Y_MASK (1 << 21) -#define BBOY_MASK (BBO_MASK &~ Y_MASK) - -/* A B form instruction setting the BO field and the condition bits of - the BI field. */ -#define BBOCB(op, bo, cb, aa, lk) \ - (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16)) -#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) - -/* A BBOCB_MASK with the y bit of the BO field removed. */ -#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) - -/* A BBOYCB_MASK in which the BI field is fixed. */ -#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) - -/* The main opcode mask with the RA field clear. */ -#define DRA_MASK (OP_MASK | RA_MASK) - -/* A DS form instruction. */ -#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) -#define DS_MASK DSO (0x3f, 3) - -/* An M form instruction. */ -#define M(op, rc) (OP (op) | ((rc) & 1)) -#define M_MASK M (0x3f, 1) - -/* An M form instruction with the ME field specified. */ -#define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1)) - -/* An M_MASK with the MB and ME fields fixed. */ -#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) - -/* An M_MASK with the SH and ME fields fixed. */ -#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) - -/* An MD form instruction. */ -#define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1)) -#define MD_MASK MD (0x3f, 0x7, 1) - -/* An MD_MASK with the MB field fixed. */ -#define MDMB_MASK (MD_MASK | MB6_MASK) - -/* An MD_MASK with the SH field fixed. */ -#define MDSH_MASK (MD_MASK | SH6_MASK) - -/* An MDS form instruction. */ -#define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1)) -#define MDS_MASK MDS (0x3f, 0xf, 1) - -/* An MDS_MASK with the MB field fixed. */ -#define MDSMB_MASK (MDS_MASK | MB6_MASK) - -/* An SC form instruction. */ -#define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1)) -#define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1) - -/* An X form instruction. */ -#define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1)) - -/* An X form instruction with the RC bit specified. */ -#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) - -/* The mask for an X form instruction. */ -#define X_MASK XRC (0x3f, 0x3ff, 1) - -/* An X_MASK with the RA field fixed. */ -#define XRA_MASK (X_MASK | RA_MASK) - -/* An X_MASK with the RB field fixed. */ -#define XRB_MASK (X_MASK | RB_MASK) - -/* An X_MASK with the RT field fixed. */ -#define XRT_MASK (X_MASK | RT_MASK) - -/* An X_MASK with the RA and RB fields fixed. */ -#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) - -/* An X_MASK with the RT and RA fields fixed. */ -#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) - -/* An X form comparison instruction. */ -#define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21)) - -/* The mask for an X form comparison instruction. */ -#define XCMP_MASK (X_MASK | (1 << 22)) - -/* The mask for an X form comparison instruction with the L field - fixed. */ -#define XCMPL_MASK (XCMP_MASK | (1 << 21)) - -/* An X form trap instruction with the TO field specified. */ -#define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21)) -#define XTO_MASK (X_MASK | TO_MASK) - -/* An XFL form instruction. */ -#define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1)) -#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16)) - -/* An XL form instruction with the LK field set to 0. */ -#define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1)) - -/* An XL form instruction which uses the LK field. */ -#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) - -/* The mask for an XL form instruction. */ -#define XL_MASK XLLK (0x3f, 0x3ff, 1) - -/* An XL form instruction which explicitly sets the BO field. */ -#define XLO(op, bo, xop, lk) \ - (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21)) -#define XLO_MASK (XL_MASK | BO_MASK) - -/* An XL form instruction which explicitly sets the y bit of the BO - field. */ -#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21)) -#define XLYLK_MASK (XL_MASK | Y_MASK) - -/* An XL form instruction which sets the BO field and the condition - bits of the BI field. */ -#define XLOCB(op, bo, cb, xop, lk) \ - (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16)) -#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) - -/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ -#define XLBB_MASK (XL_MASK | BB_MASK) -#define XLYBB_MASK (XLYLK_MASK | BB_MASK) -#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) - -/* An XL_MASK with the BO and BB fields fixed. */ -#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) - -/* An XL_MASK with the BO, BI and BB fields fixed. */ -#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) - -/* An XO form instruction. */ -#define XO(op, xop, oe, rc) \ - (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1)) -#define XO_MASK XO (0x3f, 0x1ff, 1, 1) - -/* An XO_MASK with the RB field fixed. */ -#define XORB_MASK (XO_MASK | RB_MASK) - -/* An XS form instruction. */ -#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1)) -#define XS_MASK XS (0x3f, 0x1ff, 1) - -/* A mask for the FXM version of an XFX form instruction. */ -#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11)) - -/* An XFX form instruction with the FXM field filled in. */ -#define XFXM(op, xop, fxm) \ - (X ((op), (xop)) | (((fxm) & 0xff) << 12)) - -/* An XFX form instruction with the SPR field filled in. */ -#define XSPR(op, xop, spr) \ - (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6)) -#define XSPR_MASK (X_MASK | SPR_MASK) - -/* An XFX form instruction with the SPR field filled in except for the - SPRBAT field. */ -#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) - -/* An XFX form instruction with the SPR field filled in except for the - SPRG field. */ -#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) - -/* The BO encodings used in extended conditional branch mnemonics. */ -#define BODNZF (0x0) -#define BODNZFP (0x1) -#define BODZF (0x2) -#define BODZFP (0x3) -#define BOF (0x4) -#define BOFP (0x5) -#define BODNZT (0x8) -#define BODNZTP (0x9) -#define BODZT (0xa) -#define BODZTP (0xb) -#define BOT (0xc) -#define BOTP (0xd) -#define BODNZ (0x10) -#define BODNZP (0x11) -#define BODZ (0x12) -#define BODZP (0x13) -#define BOU (0x14) - -/* The BI condition bit encodings used in extended conditional branch - mnemonics. */ -#define CBLT (0) -#define CBGT (1) -#define CBEQ (2) -#define CBSO (3) - -/* The TO encodings used in extended trap mnemonics. */ -#define TOLGT (0x1) -#define TOLLT (0x2) -#define TOEQ (0x4) -#define TOLGE (0x5) -#define TOLNL (0x5) -#define TOLLE (0x6) -#define TOLNG (0x6) -#define TOGT (0x8) -#define TOGE (0xc) -#define TONL (0xc) -#define TOLT (0x10) -#define TOLE (0x14) -#define TONG (0x14) -#define TONE (0x18) -#define TOU (0x1f) - -/* Smaller names for the flags so each entry in the opcodes table will - fit on a single line. */ -#undef PPC -#define PPC PPC_OPCODE_PPC -#define POWER PPC_OPCODE_POWER -#define POWER2 PPC_OPCODE_POWER2 -#define B32 PPC_OPCODE_32 -#define B64 PPC_OPCODE_64 -#define M601 PPC_OPCODE_601 - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK FLAGS { OPERANDS } - - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - FLAGS are flags indicated what processors support the instruction. - OPERANDS is the list of operands. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. */ - -const struct powerpc_opcode powerpc_opcodes[] = { -{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } }, - -{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } }, -{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } }, -{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } }, -{ "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } }, -{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } }, -{ "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } }, -{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } }, -{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } }, -{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } }, -{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } }, -{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } }, -{ "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } }, -{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } }, -{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } }, -{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } }, -{ "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } }, -{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } }, -{ "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } }, -{ "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } }, -{ "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } }, -{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } }, -{ "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } }, -{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } }, -{ "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } }, -{ "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } }, -{ "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } }, -{ "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } }, -{ "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } }, -{ "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } }, -{ "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } }, - -{ "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } }, -{ "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } }, - -{ "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } }, -{ "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } }, - -{ "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } }, - -{ "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } }, -{ "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } }, - -{ "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } }, -{ "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } }, - -{ "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } }, -{ "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } }, -{ "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } }, - -{ "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } }, -{ "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } }, -{ "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } }, - -{ "li", OP(14), DRA_MASK, PPC, { RT, SI } }, -{ "lil", OP(14), DRA_MASK, POWER, { RT, SI } }, -{ "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } }, -{ "cal", OP(14), OP_MASK, POWER, { RT, D, RA } }, -{ "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } }, -{ "la", OP(14), OP_MASK, PPC, { RT, D, RA } }, - -{ "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } }, -{ "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } }, -{ "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } }, -{ "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } }, -{ "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } }, - -{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } }, -{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } }, -{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } }, -{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } }, -{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } }, -{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } }, -{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } }, -{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } }, -{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } }, -{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } }, -{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } }, -{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } }, -{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } }, -{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } }, -{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } }, -{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } }, -{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } }, -{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } }, -{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } }, -{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } }, -{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } }, -{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } }, -{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } }, -{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } }, -{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } }, -{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } }, -{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } }, -{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } }, -{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } }, -{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } }, -{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } }, -{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } }, -{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } }, -{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } }, -{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } }, -{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } }, -{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } }, -{ "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } }, -{ "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } }, -{ "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } }, -{ "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } }, -{ "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } }, -{ "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } }, -{ "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } }, -{ "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } }, -{ "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } }, -{ "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } }, -{ "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } }, - -{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, -{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, -{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, -{ "svca", SC(17,1,0), SC_MASK, POWER, { SV } }, -{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, - -{ "b", B(18,0,0), B_MASK, PPC|POWER, { LI } }, -{ "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } }, -{ "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } }, -{ "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } }, - -{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } }, - -{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } }, -{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } }, -{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } }, -{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } }, -{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } }, -{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } }, -{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } }, -{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } }, -{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } }, -{ "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } }, - -{ "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } }, -{ "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } }, -{ "rfci", XL(19,51), 0xffffffff, PPC, { 0 } }, - -{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, - -{ "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "isync", XL(19,150), 0xffffffff, PPC, { 0 } }, -{ "ics", XL(19,150), 0xffffffff, POWER, { 0 } }, - -{ "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } }, -{ "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } }, -{ "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } }, -{ "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } }, -{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } }, -{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } }, -{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } }, -{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } }, -{ "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } }, - -{ "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, -{ "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, - -{ "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, -{ "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, - -{ "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } }, -{ "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } }, -{ "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, -{ "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, -{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } }, -{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } }, -{ "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, -{ "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, - -{ "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } }, -{ "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } }, - -{ "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } }, -{ "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } }, -{ "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } }, -{ "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } }, -{ "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } }, -{ "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } }, - -{ "nop", OP(24), 0xffffffff, PPC, { 0 } }, -{ "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } }, -{ "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } }, - -{ "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } }, -{ "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } }, - -{ "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } }, -{ "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } }, - -{ "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } }, -{ "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } }, - -{ "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } }, -{ "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } }, - -{ "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } }, -{ "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } }, - -{ "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } }, -{ "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } }, -{ "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, -{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } }, -{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } }, -{ "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, - -{ "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } }, -{ "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } }, - -{ "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, -{ "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, - -{ "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, -{ "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, - -{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } }, -{ "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } }, -{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } }, -{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } }, - -{ "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } }, -{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } }, - -{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } }, -{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } }, -{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } }, - -{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } }, -{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } }, -{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } }, -{ "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } }, -{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } }, -{ "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } }, -{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } }, -{ "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } }, -{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } }, -{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } }, -{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } }, -{ "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } }, -{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } }, -{ "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } }, -{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } }, -{ "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } }, -{ "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } }, -{ "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } }, -{ "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } }, -{ "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } }, -{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } }, -{ "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } }, -{ "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } }, -{ "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } }, -{ "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } }, -{ "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } }, -{ "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } }, -{ "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } }, -{ "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } }, -{ "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } }, -{ "t", X(31,4), X_MASK, POWER, { TO, RA, RB } }, - -{ "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, - -{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } }, - -{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, - -{ "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } }, - -{ "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } }, -{ "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } }, - -{ "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } }, -{ "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } }, -{ "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } }, -{ "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } }, - -{ "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } }, -{ "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } }, -{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } }, -{ "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } }, - -{ "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } }, -{ "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } }, - -{ "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } }, -{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } }, -{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } }, - -{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, - -{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } }, - -{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, - -{ "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } }, -{ "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } }, - -{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } }, -{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } }, - -{ "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } }, - -{ "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } }, - -{ "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } }, - -{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, - -{ "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } }, - -{ "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } }, -{ "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } }, -{ "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } }, -{ "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } }, - -{ "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, - -{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } }, - -{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } }, - -{ "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } }, -{ "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } }, -{ "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }}, -{ "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } }, - -{ "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } }, - -{ "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } }, - -{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, - -{ "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } }, -{ "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } }, - -{ "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } }, - -{ "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } }, -{ "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } }, - -{ "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } }, -{ "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } }, -{ "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } }, -{ "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } }, -{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } }, -{ "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } }, -{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } }, -{ "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } }, - -{ "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } }, -{ "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } }, -{ "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } }, -{ "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } }, -{ "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } }, -{ "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } }, -{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } }, -{ "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } }, - -{ "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } }, - -{ "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } }, - -{ "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } }, - -{ "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } }, -{ "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } }, -{ "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } }, -{ "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } }, -{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } }, -{ "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } }, -{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } }, -{ "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } }, - -{ "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } }, -{ "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } }, -{ "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } }, -{ "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } }, -{ "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } }, -{ "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } }, -{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } }, -{ "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } }, - -{ "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } }, -{ "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } }, - -{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } }, - -{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } }, - -{ "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, - -{ "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } }, -{ "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } }, - -{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } }, - -{ "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } }, - -{ "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } }, - -{ "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } }, -{ "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } }, - -{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, - -{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } }, - -{ "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } }, - -{ "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, - -{ "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } }, -{ "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } }, -{ "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } }, -{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, -{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } }, -{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, -{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, -{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } }, -{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, -{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, -{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } }, - -{ "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } }, - -{ "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } }, - -{ "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } }, - -{ "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } }, -{ "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } }, -{ "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } }, -{ "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } }, - -{ "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, - -{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, - -{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } }, -{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } }, - -{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } }, - -{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } }, - -{ "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } }, - -{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } }, -{ "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } }, - -{ "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } }, - -{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, - -{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } }, - -{ "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } }, -{ "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } }, -{ "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } }, - -{ "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } }, -{ "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } }, -{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, -{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, -{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } }, -{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } }, -{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, -{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, -{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, -{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } }, - -{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, - -{ "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } }, -{ "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } }, -{ "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } }, -{ "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } }, - -{ "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } }, - -{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, - -{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } }, - -{ "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } }, - -{ "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } }, -{ "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } }, - -{ "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } }, -{ "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } }, - -{ "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } }, - -{ "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } }, -{ "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } }, -{ "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } }, -{ "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } }, - -{ "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } }, -{ "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } }, - -{ "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, - -{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } }, - -{ "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } }, - -{ "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } }, -{ "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } }, - -{ "sync", X(31,598), 0xffffffff, PPC, { 0 } }, -{ "dcs", X(31,598), 0xffffffff, POWER, { 0 } }, - -{ "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } }, - -{ "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } }, - -{ "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } }, - -{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } }, - -{ "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } }, - -{ "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } }, -{ "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } }, - -{ "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } }, -{ "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } }, - -{ "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } }, - -{ "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } }, - -{ "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } }, -{ "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } }, - -{ "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } }, - -{ "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } }, - -{ "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } }, - -{ "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } }, -{ "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } }, -{ "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } }, -{ "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } }, - -{ "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } }, -{ "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } }, - -{ "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } }, - -{ "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } }, -{ "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } }, -{ "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } }, -{ "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } }, - -{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, - -{ "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } }, - -{ "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } }, -{ "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } }, -{ "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } }, -{ "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } }, - -{ "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, -{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, - -{ "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } }, - -{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, - -{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, - -{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } }, -{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } }, - -{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, -{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, - -{ "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } }, -{ "l", OP(32), OP_MASK, POWER, { RT, D, RA } }, - -{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } }, -{ "lu", OP(33), OP_MASK, POWER, { RT, D, RA } }, - -{ "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } }, - -{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } }, - -{ "stw", OP(36), OP_MASK, PPC, { RS, D, RA } }, -{ "st", OP(36), OP_MASK, POWER, { RS, D, RA } }, - -{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } }, -{ "stu", OP(37), OP_MASK, POWER, { RS, D, RA } }, - -{ "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } }, - -{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } }, - -{ "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } }, - -{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } }, - -{ "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } }, - -{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } }, - -{ "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } }, - -{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } }, - -{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } }, -{ "lm", OP(46), OP_MASK, POWER, { RT, D, RA } }, - -{ "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } }, -{ "stm", OP(47), OP_MASK, POWER, { RS, D, RA } }, - -{ "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } }, - -{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } }, - -{ "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } }, - -{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } }, - -{ "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } }, - -{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } }, - -{ "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } }, - -{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } }, - -{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, - -{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, - -{ "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } }, - -{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } }, - -{ "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } }, - -{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, - -{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, - -{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, - -{ "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } }, - -{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } }, - -{ "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } }, - -{ "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } }, -{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } }, -{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, - -{ "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } }, -{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } }, -{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, - -{ "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, -{ "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, - -{ "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, -{ "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, - -{ "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, -{ "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, - -{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } }, -{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } }, - -{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } }, -{ "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } }, - -{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, -{ "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, - -{ "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, -{ "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, - -{ "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, -{ "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, - -{ "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, -{ "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, - -{ "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } }, - -{ "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } }, -{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } }, - -{ "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } }, - -{ "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } }, -{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } }, - -{ "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } }, -{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } }, - -{ "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } }, -{ "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } }, - -{ "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } }, -{ "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } }, - -{ "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } }, -{ "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } }, - -{ "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } }, -{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } }, - -{ "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } }, -{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } }, - -}; - -const int powerpc_num_opcodes = ARRAY_SIZE(powerpc_opcodes); - -/* The macro table. This is only used by the assembler. */ - -const struct powerpc_macro powerpc_macros[] = { -{ "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" }, -{ "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" }, -{ "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, -{ "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, -{ "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, -{ "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, -{ "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" }, -{ "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" }, -{ "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" }, -{ "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" }, -{ "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" }, -{ "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" }, -{ "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" }, -{ "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" }, -{ "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" }, -{ "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" }, - -{ "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" }, -{ "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" }, -{ "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" }, -{ "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" }, -{ "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" }, -{ "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" }, -{ "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, -{ "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, -{ "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" }, -{ "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" }, -{ "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" }, -{ "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" }, -{ "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" }, -{ "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" }, -{ "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" }, -{ "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" }, -{ "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" }, -{ "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" }, -{ "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" }, -{ "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" }, -{ "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, -{ "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, - -}; - -const int powerpc_num_macros = ARRAY_SIZE(powerpc_macros); diff --git a/arch/ppc/xmon/ppc.h b/arch/ppc/xmon/ppc.h deleted file mode 100644 index 2345ecba1fe9..000000000000 --- a/arch/ppc/xmon/ppc.h +++ /dev/null @@ -1,240 +0,0 @@ -/* ppc.h -- Header file for PowerPC opcode table - Copyright 1994 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#ifndef PPC_H -#define PPC_H - -/* The opcode table is an array of struct powerpc_opcode. */ - -struct powerpc_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The defined values - are listed below. */ - unsigned long flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct powerpc_opcode powerpc_opcodes[]; -extern const int powerpc_num_opcodes; - -/* Values defined for the flags field of a struct powerpc_opcode. */ - -/* Opcode is defined for the PowerPC architecture. */ -#define PPC_OPCODE_PPC (01) - -/* Opcode is defined for the POWER (RS/6000) architecture. */ -#define PPC_OPCODE_POWER (02) - -/* Opcode is defined for the POWER2 (Rios 2) architecture. */ -#define PPC_OPCODE_POWER2 (04) - -/* Opcode is only defined on 32 bit architectures. */ -#define PPC_OPCODE_32 (010) - -/* Opcode is only defined on 64 bit architectures. */ -#define PPC_OPCODE_64 (020) - -/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 - is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, - but it also supports many additional POWER instructions. */ -#define PPC_OPCODE_601 (040) - -/* A macro to extract the major opcode from an instruction. */ -#define PPC_OP(i) (((i) >> 26) & 0x3f) - -/* The operands table is an array of struct powerpc_operand. */ - -struct powerpc_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned long (*insert) PARAMS ((unsigned long instruction, long op, - const char **errmsg)); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & PPC_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - long (*extract) PARAMS ((unsigned long instruction, int *invalid)); - - /* One bit syntax flags. */ - unsigned long flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the powerpc_opcodes table. */ - -extern const struct powerpc_operand powerpc_operands[]; - -/* Values defined for the flags field of a struct powerpc_operand. */ - -/* This operand takes signed values. */ -#define PPC_OPERAND_SIGNED (01) - -/* This operand takes signed values, but also accepts a full positive - range of values when running in 32 bit mode. That is, if bits is - 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, - this flag is ignored. */ -#define PPC_OPERAND_SIGNOPT (02) - -/* This operand does not actually exist in the assembler input. This - is used to support extended mnemonics such as mr, for which two - operands fields are identical. The assembler should call the - insert function with any op value. The disassembler should call - the extract function, ignore the return value, and check the value - placed in the valid argument. */ -#define PPC_OPERAND_FAKE (04) - -/* The next operand should be wrapped in parentheses rather than - separated from this one by a comma. This is used for the load and - store instructions which want their operands to look like - reg,displacement(reg) - */ -#define PPC_OPERAND_PARENS (010) - -/* This operand may use the symbolic names for the CR fields, which - are - lt 0 gt 1 eq 2 so 3 un 3 - cr0 0 cr1 1 cr2 2 cr3 3 - cr4 4 cr5 5 cr6 6 cr7 7 - These may be combined arithmetically, as in cr2*4+gt. These are - only supported on the PowerPC, not the POWER. */ -#define PPC_OPERAND_CR (020) - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define PPC_OPERAND_GPR (040) - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define PPC_OPERAND_FPR (0100) - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define PPC_OPERAND_RELATIVE (0200) - -/* This operand is an absolute branch address. The disassembler - prints these symbolically if possible. */ -#define PPC_OPERAND_ABSOLUTE (0400) - -/* This operand is optional, and is zero if omitted. This is used for - the optional BF and L fields in the comparison instructions. The - assembler must count the number of operands remaining on the line, - and the number of operands remaining for the opcode, and decide - whether this operand is present or not. The disassembler should - print this operand out only if it is not zero. */ -#define PPC_OPERAND_OPTIONAL (01000) - -/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand - is omitted, then for the next operand use this operand value plus - 1, ignoring the next operand field for the opcode. This wretched - hack is needed because the Power rotate instructions can take - either 4 or 5 operands. The disassembler should print this operand - out regardless of the PPC_OPERAND_OPTIONAL field. */ -#define PPC_OPERAND_NEXT (02000) - -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ -#define PPC_OPERAND_NEGATIVE (04000) - -/* The POWER and PowerPC assemblers use a few macros. We keep them - with the operands table for simplicity. The macro table is an - array of struct powerpc_macro. */ - -struct powerpc_macro -{ - /* The macro name. */ - const char *name; - - /* The number of operands the macro takes. */ - unsigned int operands; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The values are the - same as those for the struct powerpc_opcode flags field. */ - unsigned long flags; - - /* A format string to turn the macro into a normal instruction. - Each %N in the string is replaced with operand number N (zero - based). */ - const char *format; -}; - -extern const struct powerpc_macro powerpc_macros[]; -extern const int powerpc_num_macros; - -#endif /* PPC_H */ diff --git a/arch/ppc/xmon/privinst.h b/arch/ppc/xmon/privinst.h deleted file mode 100644 index c492a35687bd..000000000000 --- a/arch/ppc/xmon/privinst.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 1996 Paul Mackerras. - */ - -#define GETREG(reg) \ - static inline int get_ ## reg (void) \ - { int ret; asm volatile ("mf" #reg " %0" : "=r" (ret) :); return ret; } - -#define SETREG(reg) \ - static inline void set_ ## reg (int val) \ - { asm volatile ("mt" #reg " %0" : : "r" (val)); } - -GETREG(msr) -SETREG(msr) -GETREG(cr) - -#define GSETSPR(n, name) \ - static inline int get_ ## name (void) \ - { int ret; asm volatile ("mfspr %0," #n : "=r" (ret) : ); return ret; } \ - static inline void set_ ## name (int val) \ - { asm volatile ("mtspr " #n ",%0" : : "r" (val)); } - -GSETSPR(0, mq) -GSETSPR(1, xer) -GSETSPR(4, rtcu) -GSETSPR(5, rtcl) -GSETSPR(8, lr) -GSETSPR(9, ctr) -GSETSPR(18, dsisr) -GSETSPR(19, dar) -GSETSPR(22, dec) -GSETSPR(25, sdr1) -GSETSPR(26, srr0) -GSETSPR(27, srr1) -GSETSPR(272, sprg0) -GSETSPR(273, sprg1) -GSETSPR(274, sprg2) -GSETSPR(275, sprg3) -GSETSPR(282, ear) -GSETSPR(287, pvr) -#ifndef CONFIG_8xx -GSETSPR(528, bat0u) -GSETSPR(529, bat0l) -GSETSPR(530, bat1u) -GSETSPR(531, bat1l) -GSETSPR(532, bat2u) -GSETSPR(533, bat2l) -GSETSPR(534, bat3u) -GSETSPR(535, bat3l) -GSETSPR(1008, hid0) -GSETSPR(1009, hid1) -GSETSPR(1010, iabr) -GSETSPR(1013, dabr) -GSETSPR(1023, pir) -#else -GSETSPR(144, cmpa) -GSETSPR(145, cmpb) -GSETSPR(146, cmpc) -GSETSPR(147, cmpd) -GSETSPR(158, ictrl) -#endif - -static inline int get_sr(int n) -{ - int ret; - - asm (" mfsrin %0,%1" : "=r" (ret) : "r" (n << 28)); - return ret; -} - -static inline void set_sr(int n, int val) -{ - asm ("mtsrin %0,%1" : : "r" (val), "r" (n << 28)); -} - -static inline void store_inst(void *p) -{ - asm volatile ("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r" (p)); -} - -static inline void cflush(void *p) -{ - asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p)); -} - -static inline void cinval(void *p) -{ - asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p)); -} - diff --git a/arch/ppc/xmon/setjmp.c b/arch/ppc/xmon/setjmp.c deleted file mode 100644 index 28352bac2ae6..000000000000 --- a/arch/ppc/xmon/setjmp.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 1996 Paul Mackerras. - * - * NB this file must be compiled with -O2. - */ - -int -xmon_setjmp(long *buf) -{ - asm ("mflr 0; stw 0,0(%0);" - "stw 1,4(%0); stw 2,8(%0);" - "mfcr 0; stw 0,12(%0);" - "stmw 13,16(%0)" - : : "r" (buf)); - /* XXX should save fp regs as well */ - return 0; -} - -void -xmon_longjmp(long *buf, int val) -{ - if (val == 0) - val = 1; - asm ("lmw 13,16(%0);" - "lwz 0,12(%0); mtcrf 0x38,0;" - "lwz 0,0(%0); lwz 1,4(%0); lwz 2,8(%0);" - "mtlr 0; mr 3,%1" - : : "r" (buf), "r" (val)); -} diff --git a/arch/ppc/xmon/start.c b/arch/ppc/xmon/start.c deleted file mode 100644 index 9056fe58aaa1..000000000000 --- a/arch/ppc/xmon/start.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright (C) 1996 Paul Mackerras. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static volatile unsigned char *sccc, *sccd; -unsigned int TXRDY, RXRDY, DLAB; -static int xmon_expect(const char *str, unsigned int timeout); - -static int via_modem; - -#define TB_SPEED 25000000 - -static inline unsigned int readtb(void) -{ - unsigned int ret; - - asm volatile("mftb %0" : "=r" (ret) :); - return ret; -} - -void buf_access(void) -{ - if (DLAB) - sccd[3] &= ~DLAB; /* reset DLAB */ -} - - -#ifdef CONFIG_MAGIC_SYSRQ -static void sysrq_handle_xmon(int key, struct pt_regs *regs, - struct tty_struct *tty) -{ - xmon(regs); -} - -static struct sysrq_key_op sysrq_xmon_op = -{ - .handler = sysrq_handle_xmon, - .help_msg = "Xmon", - .action_msg = "Entering xmon", -}; -#endif - -void -xmon_map_scc(void) -{ -#if defined(CONFIG_405GP) - sccd = (volatile unsigned char *)0xef600300; -#elif defined(CONFIG_440EP) - sccd = (volatile unsigned char *) ioremap(PPC440EP_UART0_ADDR, 8); -#elif defined(CONFIG_440SP) - sccd = (volatile unsigned char *) ioremap64(PPC440SP_UART0_ADDR, 8); -#elif defined(CONFIG_440SPE) - sccd = (volatile unsigned char *) ioremap64(PPC440SPE_UART0_ADDR, 8); -#elif defined(CONFIG_44x) - /* This is the default for 44x platforms. Any boards that have a - different UART address need to be put in cases before this or the - port will be mapped incorrectly */ - sccd = (volatile unsigned char *) ioremap64(PPC440GP_UART0_ADDR, 8); -#endif /* platform */ - -#ifndef CONFIG_PPC_PREP - sccc = sccd + 5; - TXRDY = 0x20; - RXRDY = 1; - DLAB = 0x80; -#endif - - register_sysrq_key('x', &sysrq_xmon_op); -} - -static int scc_initialized; - -void xmon_init_scc(void); - -int -xmon_write(void *handle, void *ptr, int nb) -{ - char *p = ptr; - int i, c, ct; - -#ifdef CONFIG_SMP - static unsigned long xmon_write_lock; - int lock_wait = 1000000; - int locked; - - while ((locked = test_and_set_bit(0, &xmon_write_lock)) != 0) - if (--lock_wait == 0) - break; -#endif - - if (!scc_initialized) - xmon_init_scc(); - ct = 0; - for (i = 0; i < nb; ++i) { - while ((*sccc & TXRDY) == 0) - ; - c = p[i]; - if (c == '\n' && !ct) { - c = '\r'; - ct = 1; - --i; - } else { - ct = 0; - } - buf_access(); - *sccd = c; - eieio(); - } - -#ifdef CONFIG_SMP - if (!locked) - clear_bit(0, &xmon_write_lock); -#endif - return nb; -} - -int xmon_wants_key; - - -int -xmon_read(void *handle, void *ptr, int nb) -{ - char *p = ptr; - int i; - - if (!scc_initialized) - xmon_init_scc(); - for (i = 0; i < nb; ++i) { - while ((*sccc & RXRDY) == 0) - ; - buf_access(); - *p++ = *sccd; - } - return i; -} - -int -xmon_read_poll(void) -{ - if ((*sccc & RXRDY) == 0) { - ; - return -1; - } - buf_access(); - return *sccd; -} - -void -xmon_init_scc(void) -{ - scc_initialized = 1; - if (via_modem) { - for (;;) { - xmon_write(NULL, "ATE1V1\r", 7); - if (xmon_expect("OK", 5)) { - xmon_write(NULL, "ATA\r", 4); - if (xmon_expect("CONNECT", 40)) - break; - } - xmon_write(NULL, "+++", 3); - xmon_expect("OK", 3); - } - } -} - - -void *xmon_stdin; -void *xmon_stdout; -void *xmon_stderr; - -void -xmon_init(int arg) -{ - xmon_map_scc(); -} - -int -xmon_putc(int c, void *f) -{ - char ch = c; - - if (c == '\n') - xmon_putc('\r', f); - return xmon_write(f, &ch, 1) == 1? c: -1; -} - -int -xmon_putchar(int c) -{ - return xmon_putc(c, xmon_stdout); -} - -int -xmon_fputs(char *str, void *f) -{ - int n = strlen(str); - - return xmon_write(f, str, n) == n? 0: -1; -} - -int -xmon_readchar(void) -{ - char ch; - - for (;;) { - switch (xmon_read(xmon_stdin, &ch, 1)) { - case 1: - return ch; - case -1: - xmon_printf("read(stdin) returned -1\r\n", 0, 0); - return -1; - } - } -} - -static char line[256]; -static char *lineptr; -static int lineleft; - -int xmon_expect(const char *str, unsigned int timeout) -{ - int c; - unsigned int t0; - - timeout *= TB_SPEED; - t0 = readtb(); - do { - lineptr = line; - for (;;) { - c = xmon_read_poll(); - if (c == -1) { - if (readtb() - t0 > timeout) - return 0; - continue; - } - if (c == '\n') - break; - if (c != '\r' && lineptr < &line[sizeof(line) - 1]) - *lineptr++ = c; - } - *lineptr = 0; - } while (strstr(line, str) == NULL); - return 1; -} - -int -xmon_getchar(void) -{ - int c; - - if (lineleft == 0) { - lineptr = line; - for (;;) { - c = xmon_readchar(); - if (c == -1 || c == 4) - break; - if (c == '\r' || c == '\n') { - *lineptr++ = '\n'; - xmon_putchar('\n'); - break; - } - switch (c) { - case 0177: - case '\b': - if (lineptr > line) { - xmon_putchar('\b'); - xmon_putchar(' '); - xmon_putchar('\b'); - --lineptr; - } - break; - case 'U' & 0x1F: - while (lineptr > line) { - xmon_putchar('\b'); - xmon_putchar(' '); - xmon_putchar('\b'); - --lineptr; - } - break; - default: - if (lineptr >= &line[sizeof(line) - 1]) - xmon_putchar('\a'); - else { - xmon_putchar(c); - *lineptr++ = c; - } - } - } - lineleft = lineptr - line; - lineptr = line; - } - if (lineleft == 0) - return -1; - --lineleft; - return *lineptr++; -} - -char * -xmon_fgets(char *str, int nb, void *f) -{ - char *p; - int c; - - for (p = str; p < str + nb - 1; ) { - c = xmon_getchar(); - if (c == -1) { - if (p == str) - return NULL; - break; - } - *p++ = c; - if (c == '\n') - break; - } - *p = 0; - return str; -} - -void -xmon_enter(void) -{ -} - -void -xmon_leave(void) -{ -} diff --git a/arch/ppc/xmon/start_8xx.c b/arch/ppc/xmon/start_8xx.c deleted file mode 100644 index 30974068c223..000000000000 --- a/arch/ppc/xmon/start_8xx.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright (C) 1996 Paul Mackerras. - * Copyright (C) 2000 Dan Malek. - * Quick hack of Paul's code to make XMON work on 8xx processors. Lots - * of assumptions, like the SMC1 is used, it has been initialized by the - * loader at some point, and we can just stuff and suck bytes. - * We rely upon the 8xx uart driver to support us, as the interface - * changes between boot up and operational phases of the kernel. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -extern void xmon_printf(const char *fmt, ...); -extern int xmon_8xx_write(char *str, int nb); -extern int xmon_8xx_read_poll(void); -extern int xmon_8xx_read_char(void); -void prom_drawhex(uint); -void prom_drawstring(const char *str); - -static int use_screen = 1; /* default */ - -#define TB_SPEED 25000000 - -static inline unsigned int readtb(void) -{ - unsigned int ret; - - asm volatile("mftb %0" : "=r" (ret) :); - return ret; -} - -void buf_access(void) -{ -} - -void -xmon_map_scc(void) -{ - - cpmp = (cpm8xx_t *)&(((immap_t *)IMAP_ADDR)->im_cpm); - use_screen = 0; - - prom_drawstring("xmon uses serial port\n"); -} - -static int scc_initialized = 0; - -void xmon_init_scc(void); - -int -xmon_write(void *handle, void *ptr, int nb) -{ - char *p = ptr; - int i, c, ct; - - if (!scc_initialized) - xmon_init_scc(); - - return(xmon_8xx_write(ptr, nb)); -} - -int xmon_wants_key; - -int -xmon_read(void *handle, void *ptr, int nb) -{ - char *p = ptr; - int i; - - if (!scc_initialized) - xmon_init_scc(); - - for (i = 0; i < nb; ++i) { - *p++ = xmon_8xx_read_char(); - } - return i; -} - -int -xmon_read_poll(void) -{ - return(xmon_8xx_read_poll()); -} - -void -xmon_init_scc() -{ - scc_initialized = 1; -} - -#if 0 -extern int (*prom_entry)(void *); - -int -xmon_exit(void) -{ - struct prom_args { - char *service; - } args; - - for (;;) { - args.service = "exit"; - (*prom_entry)(&args); - } -} -#endif - -void *xmon_stdin; -void *xmon_stdout; -void *xmon_stderr; - -void -xmon_init(void) -{ -} - -int -xmon_putc(int c, void *f) -{ - char ch = c; - - if (c == '\n') - xmon_putc('\r', f); - return xmon_write(f, &ch, 1) == 1? c: -1; -} - -int -xmon_putchar(int c) -{ - return xmon_putc(c, xmon_stdout); -} - -int -xmon_fputs(char *str, void *f) -{ - int n = strlen(str); - - return xmon_write(f, str, n) == n? 0: -1; -} - -int -xmon_readchar(void) -{ - char ch; - - for (;;) { - switch (xmon_read(xmon_stdin, &ch, 1)) { - case 1: - return ch; - case -1: - xmon_printf("read(stdin) returned -1\r\n", 0, 0); - return -1; - } - } -} - -static char line[256]; -static char *lineptr; -static int lineleft; - -#if 0 -int xmon_expect(const char *str, unsigned int timeout) -{ - int c; - unsigned int t0; - - timeout *= TB_SPEED; - t0 = readtb(); - do { - lineptr = line; - for (;;) { - c = xmon_read_poll(); - if (c == -1) { - if (readtb() - t0 > timeout) - return 0; - continue; - } - if (c == '\n') - break; - if (c != '\r' && lineptr < &line[sizeof(line) - 1]) - *lineptr++ = c; - } - *lineptr = 0; - } while (strstr(line, str) == NULL); - return 1; -} -#endif - -int -xmon_getchar(void) -{ - int c; - - if (lineleft == 0) { - lineptr = line; - for (;;) { - c = xmon_readchar(); - if (c == -1 || c == 4) - break; - if (c == '\r' || c == '\n') { - *lineptr++ = '\n'; - xmon_putchar('\n'); - break; - } - switch (c) { - case 0177: - case '\b': - if (lineptr > line) { - xmon_putchar('\b'); - xmon_putchar(' '); - xmon_putchar('\b'); - --lineptr; - } - break; - case 'U' & 0x1F: - while (lineptr > line) { - xmon_putchar('\b'); - xmon_putchar(' '); - xmon_putchar('\b'); - --lineptr; - } - break; - default: - if (lineptr >= &line[sizeof(line) - 1]) - xmon_putchar('\a'); - else { - xmon_putchar(c); - *lineptr++ = c; - } - } - } - lineleft = lineptr - line; - lineptr = line; - } - if (lineleft == 0) - return -1; - --lineleft; - return *lineptr++; -} - -char * -xmon_fgets(char *str, int nb, void *f) -{ - char *p; - int c; - - for (p = str; p < str + nb - 1; ) { - c = xmon_getchar(); - if (c == -1) { - if (p == str) - return 0; - break; - } - *p++ = c; - if (c == '\n') - break; - } - *p = 0; - return str; -} - -void -prom_drawhex(uint val) -{ - unsigned char buf[10]; - - int i; - for (i = 7; i >= 0; i--) - { - buf[i] = "0123456789abcdef"[val & 0x0f]; - val >>= 4; - } - buf[8] = '\0'; - xmon_fputs(buf, xmon_stdout); -} - -void -prom_drawstring(const char *str) -{ - xmon_fputs(str, xmon_stdout); -} diff --git a/arch/ppc/xmon/subr_prf.c b/arch/ppc/xmon/subr_prf.c deleted file mode 100644 index 126624f3f2ed..000000000000 --- a/arch/ppc/xmon/subr_prf.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Written by Cort Dougan to replace the version originally used - * by Paul Mackerras, which came from NetBSD and thus had copyright - * conflicts with Linux. - * - * This file makes liberal use of the standard linux utility - * routines to reduce the size of the binary. We assume we can - * trust some parts of Linux inside the debugger. - * -- Cort (cort@cs.nmt.edu) - * - * Copyright (C) 1999 Cort Dougan. - */ - -#include -#include -#include -#include "nonstdio.h" - -extern int xmon_write(void *, void *, int); - -void -xmon_vfprintf(void *f, const char *fmt, va_list ap) -{ - static char xmon_buf[2048]; - int n; - - n = vsprintf(xmon_buf, fmt, ap); - xmon_write(f, xmon_buf, n); -} - -void -xmon_printf(const char *fmt, ...) -{ - va_list ap; - - va_start(ap, fmt); - xmon_vfprintf(stdout, fmt, ap); - va_end(ap); -} - -void -xmon_fprintf(void *f, const char *fmt, ...) -{ - va_list ap; - - va_start(ap, fmt); - xmon_vfprintf(f, fmt, ap); - va_end(ap); -} - -void -xmon_puts(char *s) -{ - xmon_write(stdout, s, strlen(s)); -} diff --git a/arch/ppc/xmon/xmon.c b/arch/ppc/xmon/xmon.c deleted file mode 100644 index b1a91744fd2d..000000000000 --- a/arch/ppc/xmon/xmon.c +++ /dev/null @@ -1,1780 +0,0 @@ -/* - * Routines providing a simple monitor for use on the PowerMac. - * - * Copyright (C) 1996 Paul Mackerras. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "nonstdio.h" -#include "privinst.h" - -#define scanhex xmon_scanhex -#define skipbl xmon_skipbl - -#ifdef CONFIG_SMP -static unsigned long cpus_in_xmon = 0; -static unsigned long got_xmon = 0; -static volatile int take_xmon = -1; -#endif /* CONFIG_SMP */ - -static unsigned adrs; -static int size = 1; -static unsigned ndump = 64; -static unsigned nidump = 16; -static unsigned ncsum = 4096; -static int termch; - -static u_int bus_error_jmp[100]; -#define setjmp xmon_setjmp -#define longjmp xmon_longjmp - -/* Breakpoint stuff */ -struct bpt { - unsigned address; - unsigned instr; - unsigned count; - unsigned char enabled; -}; - -#define NBPTS 16 -static struct bpt bpts[NBPTS]; -static struct bpt dabr; -static struct bpt iabr; -static unsigned bpinstr = 0x7fe00008; /* trap */ - -/* Prototypes */ -extern void (*debugger_fault_handler)(struct pt_regs *); -static int cmds(struct pt_regs *); -static int mread(unsigned, void *, int); -static int mwrite(unsigned, void *, int); -static void handle_fault(struct pt_regs *); -static void byterev(unsigned char *, int); -static void memex(void); -static int bsesc(void); -static void dump(void); -static void prdump(unsigned, int); -#ifdef __MWERKS__ -static void prndump(unsigned, int); -static int nvreadb(unsigned); -#endif -static int ppc_inst_dump(unsigned, int); -void print_address(unsigned); -static int getsp(void); -static void dump_hash_table(void); -static void backtrace(struct pt_regs *); -static void excprint(struct pt_regs *); -static void prregs(struct pt_regs *); -static void memops(int); -static void memlocate(void); -static void memzcan(void); -static void memdiffs(unsigned char *, unsigned char *, unsigned, unsigned); -int skipbl(void); -int scanhex(unsigned *valp); -static void scannl(void); -static int hexdigit(int); -void getstring(char *, int); -static void flush_input(void); -static int inchar(void); -static void take_input(char *); -/* static void openforth(void); */ -static unsigned read_spr(int); -static void write_spr(int, unsigned); -static void super_regs(void); -static void symbol_lookup(void); -static void remove_bpts(void); -static void insert_bpts(void); -static struct bpt *at_breakpoint(unsigned pc); -static void bpt_cmds(void); -void cacheflush(void); -#ifdef CONFIG_SMP -static void cpu_cmd(void); -#endif /* CONFIG_SMP */ -static void csum(void); -static void bootcmds(void); -static void proccall(void); -static void printtime(void); - -extern int print_insn_big_powerpc(FILE *, unsigned long, unsigned); -extern void printf(const char *fmt, ...); -extern int putchar(int ch); -extern int setjmp(u_int *); -extern void longjmp(u_int *, int); - -extern void xmon_enter(void); -extern void xmon_leave(void); - -static unsigned start_tb[NR_CPUS][2]; -static unsigned stop_tb[NR_CPUS][2]; - -#define GETWORD(v) (((v)[0] << 24) + ((v)[1] << 16) + ((v)[2] << 8) + (v)[3]) - -#define isxdigit(c) (('0' <= (c) && (c) <= '9') \ - || ('a' <= (c) && (c) <= 'f') \ - || ('A' <= (c) && (c) <= 'F')) -#define isalnum(c) (('0' <= (c) && (c) <= '9') \ - || ('a' <= (c) && (c) <= 'z') \ - || ('A' <= (c) && (c) <= 'Z')) -#define isspace(c) (c == ' ' || c == '\t' || c == 10 || c == 13 || c == 0) - -static char *help_string = "\ -Commands:\n\ - d dump bytes\n\ - di dump instructions\n\ - df dump float values\n\ - dd dump double values\n\ - e print exception information\n\ - h dump hash table\n\ - m examine/change memory\n\ - mm move a block of memory\n\ - ms set a block of memory\n\ - md compare two blocks of memory\n\ - r print registers\n\ - S print special registers\n\ - t print backtrace\n\ - la lookup address\n\ - ls lookup symbol\n\ - C checksum\n\ - p call function with arguments\n\ - T print time\n\ - x exit monitor\n\ - zr reboot\n\ - zh halt\n\ -"; - -static int xmon_trace[NR_CPUS]; -#define SSTEP 1 /* stepping because of 's' command */ -#define BRSTEP 2 /* stepping over breakpoint */ - -#ifdef CONFIG_4xx -#define MSR_SSTEP_ENABLE 0x200 -#else -#define MSR_SSTEP_ENABLE 0x400 -#endif - -static struct pt_regs *xmon_regs[NR_CPUS]; - -extern inline void sync(void) -{ - asm volatile("sync; isync"); -} - -extern inline void __delay(unsigned int loops) -{ - if (loops != 0) - __asm__ __volatile__("mtctr %0; 1: bdnz 1b" : : - "r" (loops) : "ctr"); -} - -/* Print an address in numeric and symbolic form (if possible) */ -static void xmon_print_symbol(unsigned long address, const char *mid, - const char *after) -{ - char *modname; - const char *name = NULL; - unsigned long offset, size; - static char tmpstr[128]; - - printf("%.8lx", address); - if (setjmp(bus_error_jmp) == 0) { - debugger_fault_handler = handle_fault; - sync(); - name = kallsyms_lookup(address, &size, &offset, &modname, - tmpstr); - sync(); - /* wait a little while to see if we get a machine check */ - __delay(200); - } - debugger_fault_handler = NULL; - - if (name) { - printf("%s%s+%#lx/%#lx", mid, name, offset, size); - if (modname) - printf(" [%s]", modname); - } - printf("%s", after); -} - -static void get_tb(unsigned *p) -{ - unsigned hi, lo, hiagain; - - if ((get_pvr() >> 16) == 1) - return; - - do { - asm volatile("mftbu %0; mftb %1; mftbu %2" - : "=r" (hi), "=r" (lo), "=r" (hiagain)); - } while (hi != hiagain); - p[0] = hi; - p[1] = lo; -} - -static inline void xmon_enable_sstep(struct pt_regs *regs) -{ - regs->msr |= MSR_SSTEP_ENABLE; -#ifdef CONFIG_4xx - mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM); -#endif -} - -int xmon(struct pt_regs *excp) -{ - struct pt_regs regs; - int msr, cmd; - - get_tb(stop_tb[smp_processor_id()]); - if (excp == NULL) { - asm volatile ("stw 0,0(%0)\n\ - lwz 0,0(1)\n\ - stw 0,4(%0)\n\ - stmw 2,8(%0)" : : "b" (®s)); - regs.nip = regs.link = ((unsigned long *)regs.gpr[1])[1]; - regs.msr = get_msr(); - regs.ctr = get_ctr(); - regs.xer = get_xer(); - regs.ccr = get_cr(); - regs.trap = 0; - excp = ®s; - } - - msr = get_msr(); - set_msr(msr & ~0x8000); /* disable interrupts */ - xmon_regs[smp_processor_id()] = excp; - xmon_enter(); - excprint(excp); -#ifdef CONFIG_SMP - if (test_and_set_bit(smp_processor_id(), &cpus_in_xmon)) - for (;;) - ; - while (test_and_set_bit(0, &got_xmon)) { - if (take_xmon == smp_processor_id()) { - take_xmon = -1; - break; - } - } - /* - * XXX: breakpoints are removed while any cpu is in xmon - */ -#endif /* CONFIG_SMP */ - remove_bpts(); - cmd = cmds(excp); - if (cmd == 's') { - xmon_trace[smp_processor_id()] = SSTEP; - xmon_enable_sstep(excp); - } else if (at_breakpoint(excp->nip)) { - xmon_trace[smp_processor_id()] = BRSTEP; - xmon_enable_sstep(excp); - } else { - xmon_trace[smp_processor_id()] = 0; - insert_bpts(); - } - xmon_leave(); - xmon_regs[smp_processor_id()] = NULL; -#ifdef CONFIG_SMP - clear_bit(0, &got_xmon); - clear_bit(smp_processor_id(), &cpus_in_xmon); -#endif /* CONFIG_SMP */ - set_msr(msr); /* restore interrupt enable */ - get_tb(start_tb[smp_processor_id()]); - - return cmd != 'X'; -} - -irqreturn_t -xmon_irq(int irq, void *d, struct pt_regs *regs) -{ - unsigned long flags; - local_irq_save(flags); - printf("Keyboard interrupt\n"); - xmon(regs); - local_irq_restore(flags); - return IRQ_HANDLED; -} - -int -xmon_bpt(struct pt_regs *regs) -{ - struct bpt *bp; - - bp = at_breakpoint(regs->nip); - if (!bp) - return 0; - if (bp->count) { - --bp->count; - remove_bpts(); - excprint(regs); - xmon_trace[smp_processor_id()] = BRSTEP; - xmon_enable_sstep(regs); - } else { - xmon(regs); - } - return 1; -} - -int -xmon_sstep(struct pt_regs *regs) -{ - if (!xmon_trace[smp_processor_id()]) - return 0; - if (xmon_trace[smp_processor_id()] == BRSTEP) { - xmon_trace[smp_processor_id()] = 0; - insert_bpts(); - } else { - xmon(regs); - } - return 1; -} - -int -xmon_dabr_match(struct pt_regs *regs) -{ - if (dabr.enabled && dabr.count) { - --dabr.count; - remove_bpts(); - excprint(regs); - xmon_trace[smp_processor_id()] = BRSTEP; - regs->msr |= 0x400; - } else { - dabr.instr = regs->nip; - xmon(regs); - } - return 1; -} - -int -xmon_iabr_match(struct pt_regs *regs) -{ - if (iabr.enabled && iabr.count) { - --iabr.count; - remove_bpts(); - excprint(regs); - xmon_trace[smp_processor_id()] = BRSTEP; - regs->msr |= 0x400; - } else { - xmon(regs); - } - return 1; -} - -static struct bpt * -at_breakpoint(unsigned pc) -{ - int i; - struct bpt *bp; - - if (dabr.enabled && pc == dabr.instr) - return &dabr; - if (iabr.enabled && pc == iabr.address) - return &iabr; - bp = bpts; - for (i = 0; i < NBPTS; ++i, ++bp) - if (bp->enabled && pc == bp->address) - return bp; - return NULL; -} - -static void -insert_bpts(void) -{ - int i; - struct bpt *bp; - - bp = bpts; - for (i = 0; i < NBPTS; ++i, ++bp) { - if (!bp->enabled) - continue; - if (mread(bp->address, &bp->instr, 4) != 4 - || mwrite(bp->address, &bpinstr, 4) != 4) { - printf("Couldn't insert breakpoint at %x, disabling\n", - bp->address); - bp->enabled = 0; - } - store_inst((void *) bp->address); - } -#if ! (defined(CONFIG_8xx) || defined(CONFIG_4xx)) - if (dabr.enabled) - set_dabr(dabr.address); - if (iabr.enabled) - set_iabr(iabr.address); -#endif -} - -static void -remove_bpts(void) -{ - int i; - struct bpt *bp; - unsigned instr; - -#if ! (defined(CONFIG_8xx) || defined(CONFIG_4xx)) - set_dabr(0); - set_iabr(0); -#endif - bp = bpts; - for (i = 0; i < NBPTS; ++i, ++bp) { - if (!bp->enabled) - continue; - if (mread(bp->address, &instr, 4) == 4 - && instr == bpinstr - && mwrite(bp->address, &bp->instr, 4) != 4) - printf("Couldn't remove breakpoint at %x\n", - bp->address); - store_inst((void *) bp->address); - } -} - -static char *last_cmd; - -/* Command interpreting routine */ -static int -cmds(struct pt_regs *excp) -{ - int cmd; - - last_cmd = NULL; - for(;;) { -#ifdef CONFIG_SMP - printf("%d:", smp_processor_id()); -#endif /* CONFIG_SMP */ - printf("mon> "); - fflush(stdout); - flush_input(); - termch = 0; - cmd = skipbl(); - if( cmd == '\n' ) { - if (last_cmd == NULL) - continue; - take_input(last_cmd); - last_cmd = NULL; - cmd = inchar(); - } - switch (cmd) { - case 'm': - cmd = inchar(); - switch (cmd) { - case 'm': - case 's': - case 'd': - memops(cmd); - break; - case 'l': - memlocate(); - break; - case 'z': - memzcan(); - break; - default: - termch = cmd; - memex(); - } - break; - case 'd': - dump(); - break; - case 'l': - symbol_lookup(); - break; - case 'r': - if (excp != NULL) - prregs(excp); /* print regs */ - break; - case 'e': - if (excp == NULL) - printf("No exception information\n"); - else - excprint(excp); - break; - case 'S': - super_regs(); - break; - case 't': - backtrace(excp); - break; - case 'f': - cacheflush(); - break; - case 'h': - dump_hash_table(); - break; - case 's': - case 'x': - case EOF: - return cmd; - case '?': - printf(help_string); - break; - default: - printf("Unrecognized command: "); - if( ' ' < cmd && cmd <= '~' ) - putchar(cmd); - else - printf("\\x%x", cmd); - printf(" (type ? for help)\n"); - break; - case 'b': - bpt_cmds(); - break; - case 'C': - csum(); - break; -#ifdef CONFIG_SMP - case 'c': - cpu_cmd(); - break; -#endif /* CONFIG_SMP */ - case 'z': - bootcmds(); - break; - case 'p': - proccall(); - break; - case 'T': - printtime(); - break; - } - } -} - -extern unsigned tb_to_us; - -#define mulhwu(x,y) \ -({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) - -static void printtime(void) -{ - unsigned int delta; - - delta = stop_tb[smp_processor_id()][1] - - start_tb[smp_processor_id()][1]; - delta = mulhwu(tb_to_us, delta); - printf("%u.%06u seconds\n", delta / 1000000, delta % 1000000); -} - -static void bootcmds(void) -{ - int cmd; - - cmd = inchar(); - if (cmd == 'r') - ppc_md.restart(NULL); - else if (cmd == 'h') - ppc_md.halt(); - else if (cmd == 'p') - ppc_md.power_off(); -} - -#ifdef CONFIG_SMP -static void cpu_cmd(void) -{ - unsigned cpu; - int timeout; - int cmd; - - cmd = inchar(); - if (cmd == 'i') { - /* interrupt other cpu(s) */ - cpu = MSG_ALL_BUT_SELF; - if (scanhex(&cpu)) - smp_send_xmon_break(cpu); - return; - } - termch = cmd; - if (!scanhex(&cpu)) { - /* print cpus waiting or in xmon */ - printf("cpus stopped:"); - for (cpu = 0; cpu < NR_CPUS; ++cpu) { - if (test_bit(cpu, &cpus_in_xmon)) { - printf(" %d", cpu); - if (cpu == smp_processor_id()) - printf("*", cpu); - } - } - printf("\n"); - return; - } - /* try to switch to cpu specified */ - take_xmon = cpu; - timeout = 10000000; - while (take_xmon >= 0) { - if (--timeout == 0) { - /* yes there's a race here */ - take_xmon = -1; - printf("cpu %u didn't take control\n", cpu); - return; - } - } - /* now have to wait to be given control back */ - while (test_and_set_bit(0, &got_xmon)) { - if (take_xmon == smp_processor_id()) { - take_xmon = -1; - break; - } - } -} -#endif /* CONFIG_SMP */ - - -static unsigned short fcstab[256] = { - 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, - 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, - 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, - 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, - 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, - 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, - 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, - 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, - 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, - 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, - 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, - 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, - 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, - 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, - 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, - 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, - 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, - 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, - 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, - 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, - 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, - 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, - 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, - 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, - 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, - 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, - 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, - 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, - 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, - 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, - 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, - 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 -}; - -#define FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff]) - -static void -csum(void) -{ - unsigned int i; - unsigned short fcs; - unsigned char v; - - if (!scanhex(&adrs)) - return; - if (!scanhex(&ncsum)) - return; - fcs = 0xffff; - for (i = 0; i < ncsum; ++i) { - if (mread(adrs+i, &v, 1) == 0) { - printf("csum stopped at %x\n", adrs+i); - break; - } - fcs = FCS(fcs, v); - } - printf("%x\n", fcs); -} - -static void -bpt_cmds(void) -{ - int cmd; - unsigned a; - int mode, i; - struct bpt *bp; - - cmd = inchar(); - switch (cmd) { -#if ! (defined(CONFIG_8xx) || defined(CONFIG_4xx)) - case 'd': - mode = 7; - cmd = inchar(); - if (cmd == 'r') - mode = 5; - else if (cmd == 'w') - mode = 6; - else - termch = cmd; - cmd = inchar(); - if (cmd == 'p') - mode &= ~4; - else - termch = cmd; - dabr.address = 0; - dabr.count = 0; - dabr.enabled = scanhex(&dabr.address); - scanhex(&dabr.count); - if (dabr.enabled) - dabr.address = (dabr.address & ~7) | mode; - break; - case 'i': - cmd = inchar(); - if (cmd == 'p') - mode = 2; - else - mode = 3; - iabr.address = 0; - iabr.count = 0; - iabr.enabled = scanhex(&iabr.address); - if (iabr.enabled) - iabr.address |= mode; - scanhex(&iabr.count); - break; -#endif - case 'c': - if (!scanhex(&a)) { - /* clear all breakpoints */ - for (i = 0; i < NBPTS; ++i) - bpts[i].enabled = 0; - iabr.enabled = 0; - dabr.enabled = 0; - printf("All breakpoints cleared\n"); - } else { - bp = at_breakpoint(a); - if (bp == 0) { - printf("No breakpoint at %x\n", a); - } else { - bp->enabled = 0; - } - } - break; - default: - termch = cmd; - if (!scanhex(&a)) { - /* print all breakpoints */ - printf("type address count\n"); - if (dabr.enabled) { - printf("data %.8x %8x [", dabr.address & ~7, - dabr.count); - if (dabr.address & 1) - printf("r"); - if (dabr.address & 2) - printf("w"); - if (!(dabr.address & 4)) - printf("p"); - printf("]\n"); - } - if (iabr.enabled) - printf("inst %.8x %8x\n", iabr.address & ~3, - iabr.count); - for (bp = bpts; bp < &bpts[NBPTS]; ++bp) - if (bp->enabled) - printf("trap %.8x %8x\n", bp->address, - bp->count); - break; - } - bp = at_breakpoint(a); - if (bp == 0) { - for (bp = bpts; bp < &bpts[NBPTS]; ++bp) - if (!bp->enabled) - break; - if (bp >= &bpts[NBPTS]) { - printf("Sorry, no free breakpoints\n"); - break; - } - } - bp->enabled = 1; - bp->address = a; - bp->count = 0; - scanhex(&bp->count); - break; - } -} - -static void -backtrace(struct pt_regs *excp) -{ - unsigned sp; - unsigned stack[2]; - struct pt_regs regs; - extern char ret_from_except, ret_from_except_full, ret_from_syscall; - - printf("backtrace:\n"); - - if (excp != NULL) - sp = excp->gpr[1]; - else - sp = getsp(); - scanhex(&sp); - scannl(); - for (; sp != 0; sp = stack[0]) { - if (mread(sp, stack, sizeof(stack)) != sizeof(stack)) - break; - printf("[%.8lx] ", stack[0]); - xmon_print_symbol(stack[1], " ", "\n"); - if (stack[1] == (unsigned) &ret_from_except - || stack[1] == (unsigned) &ret_from_except_full - || stack[1] == (unsigned) &ret_from_syscall) { - if (mread(sp+16, ®s, sizeof(regs)) != sizeof(regs)) - break; - printf("exception:%x [%x] %x\n", regs.trap, sp+16, - regs.nip); - sp = regs.gpr[1]; - if (mread(sp, stack, sizeof(stack)) != sizeof(stack)) - break; - } - } -} - -int -getsp(void) -{ - int x; - - asm("mr %0,1" : "=r" (x) :); - return x; -} - -void -excprint(struct pt_regs *fp) -{ - int trap; - -#ifdef CONFIG_SMP - printf("cpu %d: ", smp_processor_id()); -#endif /* CONFIG_SMP */ - printf("vector: %x at pc=", fp->trap); - xmon_print_symbol(fp->nip, ": ", ", lr="); - xmon_print_symbol(fp->link, ": ", "\n"); - printf("msr = %x, sp = %x [%x]\n", fp->msr, fp->gpr[1], fp); - trap = TRAP(fp); - if (trap == 0x300 || trap == 0x600) - printf("dar = %x, dsisr = %x\n", fp->dar, fp->dsisr); - if (current) - printf("current = %x, pid = %d, comm = %s\n", - current, current->pid, current->comm); -} - -void -prregs(struct pt_regs *fp) -{ - int n; - unsigned base; - - if (scanhex(&base)) - fp = (struct pt_regs *) base; - for (n = 0; n < 32; ++n) { - printf("R%.2d = %.8x%s", n, fp->gpr[n], - (n & 3) == 3? "\n": " "); - if (n == 12 && !FULL_REGS(fp)) { - printf("\n"); - break; - } - } - printf("pc = %.8x msr = %.8x lr = %.8x cr = %.8x\n", - fp->nip, fp->msr, fp->link, fp->ccr); - printf("ctr = %.8x xer = %.8x trap = %4x\n", - fp->ctr, fp->xer, fp->trap); -} - -void -cacheflush(void) -{ - int cmd; - unsigned nflush; - - cmd = inchar(); - if (cmd != 'i') - termch = cmd; - scanhex(&adrs); - if (termch != '\n') - termch = 0; - nflush = 1; - scanhex(&nflush); - nflush = (nflush + 31) / 32; - if (cmd != 'i') { - for (; nflush > 0; --nflush, adrs += 0x20) - cflush((void *) adrs); - } else { - for (; nflush > 0; --nflush, adrs += 0x20) - cinval((void *) adrs); - } -} - -unsigned int -read_spr(int n) -{ - unsigned int instrs[2]; - int (*code)(void); - - instrs[0] = 0x7c6002a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6); - instrs[1] = 0x4e800020; - store_inst(instrs); - store_inst(instrs+1); - code = (int (*)(void)) instrs; - return code(); -} - -void -write_spr(int n, unsigned int val) -{ - unsigned int instrs[2]; - int (*code)(unsigned int); - - instrs[0] = 0x7c6003a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6); - instrs[1] = 0x4e800020; - store_inst(instrs); - store_inst(instrs+1); - code = (int (*)(unsigned int)) instrs; - code(val); -} - -static unsigned int regno; -extern char exc_prolog; -extern char dec_exc; - -void -super_regs(void) -{ - int i, cmd; - unsigned val; - - cmd = skipbl(); - if (cmd == '\n') { - printf("msr = %x, pvr = %x\n", get_msr(), get_pvr()); - printf("sprg0-3 = %x %x %x %x\n", get_sprg0(), get_sprg1(), - get_sprg2(), get_sprg3()); - printf("srr0 = %x, srr1 = %x\n", get_srr0(), get_srr1()); -#ifdef CONFIG_PPC_STD_MMU - printf("sr0-15 ="); - for (i = 0; i < 16; ++i) - printf(" %x", get_sr(i)); - printf("\n"); -#endif - asm("mr %0,1" : "=r" (i) :); - printf("sp = %x ", i); - asm("mr %0,2" : "=r" (i) :); - printf("toc = %x\n", i); - return; - } - - scanhex(®no); - switch (cmd) { - case 'w': - val = read_spr(regno); - scanhex(&val); - write_spr(regno, val); - /* fall through */ - case 'r': - printf("spr %x = %x\n", regno, read_spr(regno)); - break; - case 's': - val = get_sr(regno); - scanhex(&val); - set_sr(regno, val); - break; - case 'm': - val = get_msr(); - scanhex(&val); - set_msr(val); - break; - } - scannl(); -} - -#ifndef CONFIG_PPC_STD_MMU -static void -dump_hash_table(void) -{ - printf("This CPU doesn't have a hash table.\n"); -} -#else - -static void -dump_hash_table_seg(unsigned seg, unsigned start, unsigned end) -{ - extern void *Hash; - extern unsigned long Hash_size; - unsigned *htab = Hash; - unsigned hsize = Hash_size; - unsigned v, hmask, va, last_va = 0; - int found, last_found, i; - unsigned *hg, w1, last_w2 = 0, last_va0 = 0; - - last_found = 0; - hmask = hsize / 64 - 1; - va = start; - start = (start >> 12) & 0xffff; - end = (end >> 12) & 0xffff; - for (v = start; v < end; ++v) { - found = 0; - hg = htab + (((v ^ seg) & hmask) * 16); - w1 = 0x80000000 | (seg << 7) | (v >> 10); - for (i = 0; i < 8; ++i, hg += 2) { - if (*hg == w1) { - found = 1; - break; - } - } - if (!found) { - w1 ^= 0x40; - hg = htab + ((~(v ^ seg) & hmask) * 16); - for (i = 0; i < 8; ++i, hg += 2) { - if (*hg == w1) { - found = 1; - break; - } - } - } - if (!(last_found && found && (hg[1] & ~0x180) == last_w2 + 4096)) { - if (last_found) { - if (last_va != last_va0) - printf(" ... %x", last_va); - printf("\n"); - } - if (found) { - printf("%x to %x", va, hg[1]); - last_va0 = va; - } - last_found = found; - } - if (found) { - last_w2 = hg[1] & ~0x180; - last_va = va; - } - va += 4096; - } - if (last_found) - printf(" ... %x\n", last_va); -} - -static unsigned hash_ctx; -static unsigned hash_start; -static unsigned hash_end; - -static void -dump_hash_table(void) -{ - int seg; - unsigned seg_start, seg_end; - - hash_ctx = 0; - hash_start = 0; - hash_end = 0xfffff000; - scanhex(&hash_ctx); - scanhex(&hash_start); - scanhex(&hash_end); - printf("Mappings for context %x\n", hash_ctx); - seg_start = hash_start; - for (seg = hash_start >> 28; seg <= hash_end >> 28; ++seg) { - seg_end = (seg << 28) | 0x0ffff000; - if (seg_end > hash_end) - seg_end = hash_end; - dump_hash_table_seg((hash_ctx << 4) + (seg * 0x111), - seg_start, seg_end); - seg_start = seg_end + 0x1000; - } -} -#endif /* CONFIG_PPC_STD_MMU */ - -/* - * Stuff for reading and writing memory safely - */ - -int -mread(unsigned adrs, void *buf, int size) -{ - volatile int n; - char *p, *q; - - n = 0; - if( setjmp(bus_error_jmp) == 0 ){ - debugger_fault_handler = handle_fault; - sync(); - p = (char *) adrs; - q = (char *) buf; - switch (size) { - case 2: *(short *)q = *(short *)p; break; - case 4: *(int *)q = *(int *)p; break; - default: - for( ; n < size; ++n ) { - *q++ = *p++; - sync(); - } - } - sync(); - /* wait a little while to see if we get a machine check */ - __delay(200); - n = size; - } - debugger_fault_handler = NULL; - return n; -} - -int -mwrite(unsigned adrs, void *buf, int size) -{ - volatile int n; - char *p, *q; - - n = 0; - if( setjmp(bus_error_jmp) == 0 ){ - debugger_fault_handler = handle_fault; - sync(); - p = (char *) adrs; - q = (char *) buf; - switch (size) { - case 2: *(short *)p = *(short *)q; break; - case 4: *(int *)p = *(int *)q; break; - default: - for( ; n < size; ++n ) { - *p++ = *q++; - sync(); - } - } - sync(); - n = size; - } else { - printf("*** Error writing address %x\n", adrs + n); - } - debugger_fault_handler = NULL; - return n; -} - -static int fault_type; -static int fault_except; -static char *fault_chars[] = { "--", "**", "##" }; - -static void -handle_fault(struct pt_regs *regs) -{ - fault_except = TRAP(regs); - fault_type = TRAP(regs) == 0x200? 0: TRAP(regs) == 0x300? 1: 2; - longjmp(bus_error_jmp, 1); -} - -#define SWAP(a, b, t) ((t) = (a), (a) = (b), (b) = (t)) - -void -byterev(unsigned char *val, int size) -{ - int t; - - switch (size) { - case 2: - SWAP(val[0], val[1], t); - break; - case 4: - SWAP(val[0], val[3], t); - SWAP(val[1], val[2], t); - break; - } -} - -static int brev; -static int mnoread; - -void -memex(void) -{ - int cmd, inc, i, nslash; - unsigned n; - unsigned char val[4]; - - last_cmd = "m\n"; - scanhex(&adrs); - while ((cmd = skipbl()) != '\n') { - switch( cmd ){ - case 'b': size = 1; break; - case 'w': size = 2; break; - case 'l': size = 4; break; - case 'r': brev = !brev; break; - case 'n': mnoread = 1; break; - case '.': mnoread = 0; break; - } - } - if( size <= 0 ) - size = 1; - else if( size > 4 ) - size = 4; - for(;;){ - if (!mnoread) - n = mread(adrs, val, size); - printf("%.8x%c", adrs, brev? 'r': ' '); - if (!mnoread) { - if (brev) - byterev(val, size); - putchar(' '); - for (i = 0; i < n; ++i) - printf("%.2x", val[i]); - for (; i < size; ++i) - printf("%s", fault_chars[fault_type]); - } - putchar(' '); - inc = size; - nslash = 0; - for(;;){ - if( scanhex(&n) ){ - for (i = 0; i < size; ++i) - val[i] = n >> (i * 8); - if (!brev) - byterev(val, size); - mwrite(adrs, val, size); - inc = size; - } - cmd = skipbl(); - if (cmd == '\n') - break; - inc = 0; - switch (cmd) { - case '\'': - for(;;){ - n = inchar(); - if( n == '\\' ) - n = bsesc(); - else if( n == '\'' ) - break; - for (i = 0; i < size; ++i) - val[i] = n >> (i * 8); - if (!brev) - byterev(val, size); - mwrite(adrs, val, size); - adrs += size; - } - adrs -= size; - inc = size; - break; - case ',': - adrs += size; - break; - case '.': - mnoread = 0; - break; - case ';': - break; - case 'x': - case EOF: - scannl(); - return; - case 'b': - case 'v': - size = 1; - break; - case 'w': - size = 2; - break; - case 'l': - size = 4; - break; - case '^': - adrs -= size; - break; - break; - case '/': - if (nslash > 0) - adrs -= 1 << nslash; - else - nslash = 0; - nslash += 4; - adrs += 1 << nslash; - break; - case '\\': - if (nslash < 0) - adrs += 1 << -nslash; - else - nslash = 0; - nslash -= 4; - adrs -= 1 << -nslash; - break; - case 'm': - scanhex(&adrs); - break; - case 'n': - mnoread = 1; - break; - case 'r': - brev = !brev; - break; - case '<': - n = size; - scanhex(&n); - adrs -= n; - break; - case '>': - n = size; - scanhex(&n); - adrs += n; - break; - } - } - adrs += inc; - } -} - -int -bsesc(void) -{ - int c; - - c = inchar(); - switch( c ){ - case 'n': c = '\n'; break; - case 'r': c = '\r'; break; - case 'b': c = '\b'; break; - case 't': c = '\t'; break; - } - return c; -} - -void -dump(void) -{ - int c; - - c = inchar(); - if ((isxdigit(c) && c != 'f' && c != 'd') || c == '\n') - termch = c; - scanhex(&adrs); - if( termch != '\n') - termch = 0; - if( c == 'i' ){ - scanhex(&nidump); - if( nidump == 0 ) - nidump = 16; - adrs += ppc_inst_dump(adrs, nidump); - last_cmd = "di\n"; - } else { - scanhex(&ndump); - if( ndump == 0 ) - ndump = 64; - prdump(adrs, ndump); - adrs += ndump; - last_cmd = "d\n"; - } -} - -void -prdump(unsigned adrs, int ndump) -{ - register int n, m, c, r, nr; - unsigned char temp[16]; - - for( n = ndump; n > 0; ){ - printf("%.8x", adrs); - putchar(' '); - r = n < 16? n: 16; - nr = mread(adrs, temp, r); - adrs += nr; - for( m = 0; m < r; ++m ){ - putchar((m & 3) == 0 && m > 0? '.': ' '); - if( m < nr ) - printf("%.2x", temp[m]); - else - printf("%s", fault_chars[fault_type]); - } - for(; m < 16; ++m ) - printf(" "); - printf(" |"); - for( m = 0; m < r; ++m ){ - if( m < nr ){ - c = temp[m]; - putchar(' ' <= c && c <= '~'? c: '.'); - } else - putchar(' '); - } - n -= r; - for(; m < 16; ++m ) - putchar(' '); - printf("|\n"); - if( nr < r ) - break; - } -} - -int -ppc_inst_dump(unsigned adr, int count) -{ - int nr, dotted; - unsigned first_adr; - unsigned long inst, last_inst = 0; - unsigned char val[4]; - - dotted = 0; - for (first_adr = adr; count > 0; --count, adr += 4){ - nr = mread(adr, val, 4); - if( nr == 0 ){ - const char *x = fault_chars[fault_type]; - printf("%.8x %s%s%s%s\n", adr, x, x, x, x); - break; - } - inst = GETWORD(val); - if (adr > first_adr && inst == last_inst) { - if (!dotted) { - printf(" ...\n"); - dotted = 1; - } - continue; - } - dotted = 0; - last_inst = inst; - printf("%.8x ", adr); - printf("%.8x\t", inst); - print_insn_big_powerpc(stdout, inst, adr); /* always returns 4 */ - printf("\n"); - } - return adr - first_adr; -} - -void -print_address(unsigned addr) -{ - printf("0x%x", addr); -} - -/* - * Memory operations - move, set, print differences - */ -static unsigned mdest; /* destination address */ -static unsigned msrc; /* source address */ -static unsigned mval; /* byte value to set memory to */ -static unsigned mcount; /* # bytes to affect */ -static unsigned mdiffs; /* max # differences to print */ - -void -memops(int cmd) -{ - scanhex(&mdest); - if( termch != '\n' ) - termch = 0; - scanhex(cmd == 's'? &mval: &msrc); - if( termch != '\n' ) - termch = 0; - scanhex(&mcount); - switch( cmd ){ - case 'm': - memmove((void *)mdest, (void *)msrc, mcount); - break; - case 's': - memset((void *)mdest, mval, mcount); - break; - case 'd': - if( termch != '\n' ) - termch = 0; - scanhex(&mdiffs); - memdiffs((unsigned char *)mdest, (unsigned char *)msrc, mcount, mdiffs); - break; - } -} - -void -memdiffs(unsigned char *p1, unsigned char *p2, unsigned nb, unsigned maxpr) -{ - unsigned n, prt; - - prt = 0; - for( n = nb; n > 0; --n ) - if( *p1++ != *p2++ ) - if( ++prt <= maxpr ) - printf("%.8x %.2x # %.8x %.2x\n", (unsigned)p1 - 1, - p1[-1], (unsigned)p2 - 1, p2[-1]); - if( prt > maxpr ) - printf("Total of %d differences\n", prt); -} - -static unsigned mend; -static unsigned mask; - -void -memlocate(void) -{ - unsigned a, n; - unsigned char val[4]; - - last_cmd = "ml"; - scanhex(&mdest); - if (termch != '\n') { - termch = 0; - scanhex(&mend); - if (termch != '\n') { - termch = 0; - scanhex(&mval); - mask = ~0; - if (termch != '\n') termch = 0; - scanhex(&mask); - } - } - n = 0; - for (a = mdest; a < mend; a += 4) { - if (mread(a, val, 4) == 4 - && ((GETWORD(val) ^ mval) & mask) == 0) { - printf("%.8x: %.8x\n", a, GETWORD(val)); - if (++n >= 10) - break; - } - } -} - -static unsigned mskip = 0x1000; -static unsigned mlim = 0xffffffff; - -void -memzcan(void) -{ - unsigned char v; - unsigned a; - int ok, ook; - - scanhex(&mdest); - if (termch != '\n') termch = 0; - scanhex(&mskip); - if (termch != '\n') termch = 0; - scanhex(&mlim); - ook = 0; - for (a = mdest; a < mlim; a += mskip) { - ok = mread(a, &v, 1); - if (ok && !ook) { - printf("%.8x .. ", a); - fflush(stdout); - } else if (!ok && ook) - printf("%.8x\n", a - mskip); - ook = ok; - if (a + mskip < a) - break; - } - if (ook) - printf("%.8x\n", a - mskip); -} - -void proccall(void) -{ - unsigned int args[8]; - unsigned int ret; - int i; - typedef unsigned int (*callfunc_t)(unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int); - callfunc_t func; - - scanhex(&adrs); - if (termch != '\n') - termch = 0; - for (i = 0; i < 8; ++i) - args[i] = 0; - for (i = 0; i < 8; ++i) { - if (!scanhex(&args[i]) || termch == '\n') - break; - termch = 0; - } - func = (callfunc_t) adrs; - ret = 0; - if (setjmp(bus_error_jmp) == 0) { - debugger_fault_handler = handle_fault; - sync(); - ret = func(args[0], args[1], args[2], args[3], - args[4], args[5], args[6], args[7]); - sync(); - printf("return value is %x\n", ret); - } else { - printf("*** %x exception occurred\n", fault_except); - } - debugger_fault_handler = NULL; -} - -/* Input scanning routines */ -int -skipbl(void) -{ - int c; - - if( termch != 0 ){ - c = termch; - termch = 0; - } else - c = inchar(); - while( c == ' ' || c == '\t' ) - c = inchar(); - return c; -} - -#define N_PTREGS 44 -static char *regnames[N_PTREGS] = { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", - "pc", "msr", "or3", "ctr", "lr", "xer", "ccr", "mq", - "trap", "dar", "dsisr", "res" -}; - -int -scanhex(unsigned *vp) -{ - int c, d; - unsigned v; - - c = skipbl(); - if (c == '%') { - /* parse register name */ - char regname[8]; - int i; - - for (i = 0; i < sizeof(regname) - 1; ++i) { - c = inchar(); - if (!isalnum(c)) { - termch = c; - break; - } - regname[i] = c; - } - regname[i] = 0; - for (i = 0; i < N_PTREGS; ++i) { - if (strcmp(regnames[i], regname) == 0) { - unsigned *rp = (unsigned *) - xmon_regs[smp_processor_id()]; - if (rp == NULL) { - printf("regs not available\n"); - return 0; - } - *vp = rp[i]; - return 1; - } - } - printf("invalid register name '%%%s'\n", regname); - return 0; - } else if (c == '$') { - static char symname[128]; - int i; - for (i=0; i<63; i++) { - c = inchar(); - if (isspace(c)) { - termch = c; - break; - } - symname[i] = c; - } - symname[i++] = 0; - *vp = 0; - if (setjmp(bus_error_jmp) == 0) { - debugger_fault_handler = handle_fault; - sync(); - *vp = kallsyms_lookup_name(symname); - sync(); - } - debugger_fault_handler = NULL; - if (!(*vp)) { - printf("unknown symbol\n"); - return 0; - } - return 1; - } - - d = hexdigit(c); - if( d == EOF ){ - termch = c; - return 0; - } - v = 0; - do { - v = (v << 4) + d; - c = inchar(); - d = hexdigit(c); - } while( d != EOF ); - termch = c; - *vp = v; - return 1; -} - -void -scannl(void) -{ - int c; - - c = termch; - termch = 0; - while( c != '\n' ) - c = inchar(); -} - -int hexdigit(int c) -{ - if( '0' <= c && c <= '9' ) - return c - '0'; - if( 'A' <= c && c <= 'F' ) - return c - ('A' - 10); - if( 'a' <= c && c <= 'f' ) - return c - ('a' - 10); - return EOF; -} - -void -getstring(char *s, int size) -{ - int c; - - c = skipbl(); - do { - if( size > 1 ){ - *s++ = c; - --size; - } - c = inchar(); - } while( c != ' ' && c != '\t' && c != '\n' ); - termch = c; - *s = 0; -} - -static char line[256]; -static char *lineptr; - -void -flush_input(void) -{ - lineptr = NULL; -} - -int -inchar(void) -{ - if (lineptr == NULL || *lineptr == 0) { - if (fgets(line, sizeof(line), stdin) == NULL) { - lineptr = NULL; - return EOF; - } - lineptr = line; - } - return *lineptr++; -} - -void -take_input(char *str) -{ - lineptr = str; -} - -static void -symbol_lookup(void) -{ - int type = inchar(); - unsigned addr; - static char tmp[128]; - - switch (type) { - case 'a': - if (scanhex(&addr)) - xmon_print_symbol(addr, ": ", "\n"); - termch = 0; - break; - case 's': - getstring(tmp, 64); - if (setjmp(bus_error_jmp) == 0) { - debugger_fault_handler = handle_fault; - sync(); - addr = kallsyms_lookup_name(tmp); - if (addr) - printf("%s: %lx\n", tmp, addr); - else - printf("Symbol '%s' not found.\n", tmp); - sync(); - } - debugger_fault_handler = NULL; - termch = 0; - break; - } -} - diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h deleted file mode 100644 index 4b0e15206006..000000000000 --- a/include/asm-ppc/8xx_immap.h +++ /dev/null @@ -1,564 +0,0 @@ -/* - * MPC8xx Internal Memory Map - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * The I/O on the MPC860 is comprised of blocks of special registers - * and the dual port ram for the Communication Processor Module. - * Within this space are functional units such as the SIU, memory - * controller, system timers, and other control functions. It is - * a combination that I found difficult to separate into logical - * functional files.....but anyone else is welcome to try. -- Dan - */ -#ifdef __KERNEL__ -#ifndef __IMMAP_8XX__ -#define __IMMAP_8XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - uint sc_swt; - char res1[2]; - ushort sc_swsr; - uint sc_sipend; - uint sc_simask; - uint sc_siel; - uint sc_sivec; - uint sc_tesr; - char res2[0xc]; - uint sc_sdcr; - char res3[0x4c]; -} sysconf8xx_t; - -/* PCMCIA configuration registers. -*/ -typedef struct pcmcia_conf { - uint pcmc_pbr0; - uint pcmc_por0; - uint pcmc_pbr1; - uint pcmc_por1; - uint pcmc_pbr2; - uint pcmc_por2; - uint pcmc_pbr3; - uint pcmc_por3; - uint pcmc_pbr4; - uint pcmc_por4; - uint pcmc_pbr5; - uint pcmc_por5; - uint pcmc_pbr6; - uint pcmc_por6; - uint pcmc_pbr7; - uint pcmc_por7; - char res1[0x20]; - uint pcmc_pgcra; - uint pcmc_pgcrb; - uint pcmc_pscr; - char res2[4]; - uint pcmc_pipr; - char res3[4]; - uint pcmc_per; - char res4[4]; -} pcmconf8xx_t; - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - uint memc_br4; - uint memc_or4; - uint memc_br5; - uint memc_or5; - uint memc_br6; - uint memc_or6; - uint memc_br7; - uint memc_or7; - char res1[0x24]; - uint memc_mar; - uint memc_mcr; - char res2[4]; - uint memc_mamr; - uint memc_mbmr; - ushort memc_mstat; - ushort memc_mptpr; - uint memc_mdr; - char res3[0x80]; -} memctl8xx_t; - -/*----------------------------------------------------------------------- - * BR - Memory Controler: Base Register 16-9 - */ -#define BR_BA_MSK 0xffff8000 /* Base Address Mask */ -#define BR_AT_MSK 0x00007000 /* Address Type Mask */ -#define BR_PS_MSK 0x00000c00 /* Port Size Mask */ -#define BR_PS_32 0x00000000 /* 32 bit port size */ -#define BR_PS_16 0x00000800 /* 16 bit port size */ -#define BR_PS_8 0x00000400 /* 8 bit port size */ -#define BR_PARE 0x00000200 /* Parity Enable */ -#define BR_WP 0x00000100 /* Write Protect */ -#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */ -#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ -#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ -#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */ -#define BR_V 0x00000001 /* Bank Valid */ - -/*----------------------------------------------------------------------- - * OR - Memory Controler: Option Register 16-11 - */ -#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */ -#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ -#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ - /* Address Multiplex */ -#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ -#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ -#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ -#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ -#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ -#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ -#define OR_BI 0x00000100 /* Burst inhibit */ -#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */ -#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ -#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ -#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ -#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ -#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ -#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ -#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ -#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ -#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ -#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ -#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ -#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ -#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ -#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ -#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ -#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ -#define OR_SETA 0x00000008 /* External Transfer Acknowledge */ -#define OR_TRLX 0x00000004 /* Timing Relaxed */ -#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - ushort sit_tbscr; - char res0[0x02]; - uint sit_tbreff0; - uint sit_tbreff1; - char res1[0x14]; - ushort sit_rtcsc; - char res2[0x02]; - uint sit_rtc; - uint sit_rtsec; - uint sit_rtcal; - char res3[0x10]; - ushort sit_piscr; - char res4[2]; - uint sit_pitc; - uint sit_pitr; - char res5[0x34]; -} sit8xx_t; - -#define TBSCR_TBIRQ_MASK ((ushort)0xff00) -#define TBSCR_REFA ((ushort)0x0080) -#define TBSCR_REFB ((ushort)0x0040) -#define TBSCR_REFAE ((ushort)0x0008) -#define TBSCR_REFBE ((ushort)0x0004) -#define TBSCR_TBF ((ushort)0x0002) -#define TBSCR_TBE ((ushort)0x0001) - -#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) -#define RTCSC_SEC ((ushort)0x0080) -#define RTCSC_ALR ((ushort)0x0040) -#define RTCSC_38K ((ushort)0x0010) -#define RTCSC_SIE ((ushort)0x0008) -#define RTCSC_ALE ((ushort)0x0004) -#define RTCSC_RTF ((ushort)0x0002) -#define RTCSC_RTE ((ushort)0x0001) - -#define PISCR_PIRQ_MASK ((ushort)0xff00) -#define PISCR_PS ((ushort)0x0080) -#define PISCR_PIE ((ushort)0x0004) -#define PISCR_PTF ((ushort)0x0002) -#define PISCR_PTE ((ushort)0x0001) - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - uint car_sccr; - uint car_plprcr; - uint car_rsr; - char res[0x74]; /* Reserved area */ -} car8xx_t; - -/* System Integration Timers keys. -*/ -typedef struct sitk { - uint sitk_tbscrk; - uint sitk_tbreff0k; - uint sitk_tbreff1k; - uint sitk_tbk; - char res1[0x10]; - uint sitk_rtcsck; - uint sitk_rtck; - uint sitk_rtseck; - uint sitk_rtcalk; - char res2[0x10]; - uint sitk_piscrk; - uint sitk_pitck; - char res3[0x38]; -} sitk8xx_t; - -/* Clocks and reset keys. -*/ -typedef struct cark { - uint cark_sccrk; - uint cark_plprcrk; - uint cark_rsrk; - char res[0x474]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* Video interface. MPC823 Only. -*/ -typedef struct vid823 { - ushort vid_vccr; - ushort res1; - u_char vid_vsr; - u_char res2; - u_char vid_vcmr; - u_char res3; - uint vid_vbcb; - uint res4; - uint vid_vfcr0; - uint vid_vfaa0; - uint vid_vfba0; - uint vid_vfcr1; - uint vid_vfaa1; - uint vid_vfba1; - u_char res5[0x18]; -} vid823_t; - -/* LCD interface. 823 Only. -*/ -typedef struct lcd { - uint lcd_lccr; - uint lcd_lchcr; - uint lcd_lcvcr; - char res1[4]; - uint lcd_lcfaa; - uint lcd_lcfba; - char lcd_lcsr; - char res2[0x7]; -} lcd823_t; - -/* I2C -*/ -typedef struct i2c { - u_char i2c_i2mod; - char res1[3]; - u_char i2c_i2add; - char res2[3]; - u_char i2c_i2brg; - char res3[3]; - u_char i2c_i2com; - char res4[3]; - u_char i2c_i2cer; - char res5[3]; - u_char i2c_i2cmr; - char res6[0x8b]; -} i2c8xx_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res1[4]; - uint sdma_sdar; - u_char sdma_sdsr; - char res3[3]; - u_char sdma_sdmr; - char res4[3]; - u_char sdma_idsr1; - char res5[3]; - u_char sdma_idmr1; - char res6[3]; - u_char sdma_idsr2; - char res7[3]; - u_char sdma_idmr2; - char res8[0x13]; -} sdma8xx_t; - -/* Communication Processor Module Interrupt Controller. -*/ -typedef struct cpm_ic { - ushort cpic_civr; - char res[0xe]; - uint cpic_cicr; - uint cpic_cipr; - uint cpic_cimr; - uint cpic_cisr; -} cpic8xx_t; - -/* Input/Output Port control/status registers. -*/ -typedef struct io_port { - ushort iop_padir; - ushort iop_papar; - ushort iop_paodr; - ushort iop_padat; - char res1[8]; - ushort iop_pcdir; - ushort iop_pcpar; - ushort iop_pcso; - ushort iop_pcdat; - ushort iop_pcint; - char res2[6]; - ushort iop_pddir; - ushort iop_pdpar; - char res3[2]; - ushort iop_pddat; - uint utmode; - char res4[4]; -} iop8xx_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - ushort cpmt_tgcr; - char res1[0xe]; - ushort cpmt_tmr1; - ushort cpmt_tmr2; - ushort cpmt_trr1; - ushort cpmt_trr2; - ushort cpmt_tcr1; - ushort cpmt_tcr2; - ushort cpmt_tcn1; - ushort cpmt_tcn2; - ushort cpmt_tmr3; - ushort cpmt_tmr4; - ushort cpmt_trr3; - ushort cpmt_trr4; - ushort cpmt_tcr3; - ushort cpmt_tcr4; - ushort cpmt_tcn3; - ushort cpmt_tcn4; - ushort cpmt_ter1; - ushort cpmt_ter2; - ushort cpmt_ter3; - ushort cpmt_ter4; - char res2[8]; -} cpmtimer8xx_t; - -/* Finally, the Communication Processor stuff..... -*/ -typedef struct scc { /* Serial communication channels */ - uint scc_gsmrl; - uint scc_gsmrh; - ushort scc_psmr; - char res1[2]; - ushort scc_todr; - ushort scc_dsr; - ushort scc_scce; - char res2[2]; - ushort scc_sccm; - char res3; - u_char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - ushort smc_smcmr; - char res2[2]; - u_char smc_smce; - char res3[3]; - u_char smc_smcm; - char res4[5]; -} smc_t; - -/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but - * it fits within the address space. - */ - -typedef struct fec { - uint fec_addr_low; /* lower 32 bits of station address */ - ushort fec_addr_high; /* upper 16 bits of station address */ - ushort res1; /* reserved */ - uint fec_hash_table_high; /* upper 32-bits of hash table */ - uint fec_hash_table_low; /* lower 32-bits of hash table */ - uint fec_r_des_start; /* beginning of Rx descriptor ring */ - uint fec_x_des_start; /* beginning of Tx descriptor ring */ - uint fec_r_buff_size; /* Rx buffer size */ - uint res2[9]; /* reserved */ - uint fec_ecntrl; /* ethernet control register */ - uint fec_ievent; /* interrupt event register */ - uint fec_imask; /* interrupt mask register */ - uint fec_ivec; /* interrupt level and vector status */ - uint fec_r_des_active; /* Rx ring updated flag */ - uint fec_x_des_active; /* Tx ring updated flag */ - uint res3[10]; /* reserved */ - uint fec_mii_data; /* MII data register */ - uint fec_mii_speed; /* MII speed control register */ - uint res4[17]; /* reserved */ - uint fec_r_bound; /* end of RAM (read-only) */ - uint fec_r_fstart; /* Rx FIFO start address */ - uint res5[6]; /* reserved */ - uint fec_x_fstart; /* Tx FIFO start address */ - uint res6[17]; /* reserved */ - uint fec_fun_code; /* fec SDMA function code */ - uint res7[3]; /* reserved */ - uint fec_r_cntrl; /* Rx control register */ - uint fec_r_hash; /* Rx hash register */ - uint res8[14]; /* reserved */ - uint fec_x_cntrl; /* Tx control register */ - uint res9[0x1e]; /* reserved */ -} fec_t; - -/* The FEC and LCD color map share the same address space.... - * I guess we will never see an 823T :-). - */ -union fec_lcd { - fec_t fl_un_fec; - u_char fl_un_cmap[0x200]; -}; - -typedef struct comm_proc { - /* General control and status registers. - */ - ushort cp_cpcr; - u_char res1[2]; - ushort cp_rccr; - u_char res2; - u_char cp_rmds; - u_char res3[4]; - ushort cp_cpmcr1; - ushort cp_cpmcr2; - ushort cp_cpmcr3; - ushort cp_cpmcr4; - u_char res4[2]; - ushort cp_rter; - u_char res5[2]; - ushort cp_rtmr; - u_char res6[0x14]; - - /* Baud rate generators. - */ - uint cp_brgc1; - uint cp_brgc2; - uint cp_brgc3; - uint cp_brgc4; - - /* Serial Communication Channels. - */ - scc_t cp_scc[4]; - - /* Serial Management Channels. - */ - smc_t cp_smc[2]; - - /* Serial Peripheral Interface. - */ - ushort cp_spmode; - u_char res7[4]; - u_char cp_spie; - u_char res8[3]; - u_char cp_spim; - u_char res9[2]; - u_char cp_spcom; - u_char res10[2]; - - /* Parallel Interface Port. - */ - u_char res11[2]; - ushort cp_pipc; - u_char res12[2]; - ushort cp_ptpr; - uint cp_pbdir; - uint cp_pbpar; - u_char res13[2]; - ushort cp_pbodr; - uint cp_pbdat; - - /* Port E - MPC87x/88x only. - */ - uint cp_pedir; - uint cp_pepar; - uint cp_peso; - uint cp_peodr; - uint cp_pedat; - - /* Communications Processor Timing Register - - Contains RMII Timing for the FECs on MPC87x/88x only. - */ - uint cp_cptr; - - /* Serial Interface and Time Slot Assignment. - */ - uint cp_simode; - u_char cp_sigmr; - u_char res15; - u_char cp_sistr; - u_char cp_sicmr; - u_char res16[4]; - uint cp_sicr; - uint cp_sirp; - u_char res17[0xc]; - - /* 256 bytes of MPC823 video controller RAM array. - */ - u_char cp_vcram[0x100]; - u_char cp_siram[0x200]; - - /* The fast ethernet controller is not really part of the CPM, - * but it resides in the address space. - * The LCD color map is also here. - */ - union fec_lcd fl_un; -#define cp_fec fl_un.fl_un_fec -#define lcd_cmap fl_un.fl_un_cmap - char res18[0xE00]; - - /* The DUET family has a second FEC here */ - fec_t cp_fec2; -#define cp_fec1 cp_fec /* consistency macro */ - - /* Dual Ported RAM follows. - * There are many different formats for this memory area - * depending upon the devices used and options chosen. - * Some processors don't have all of it populated. - */ - u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ - u_char cp_dparam[0x400]; /* Parameter RAM */ -} cpm8xx_t; - -/* Internal memory map. -*/ -typedef struct immap { - sysconf8xx_t im_siu_conf; /* SIU Configuration */ - pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ - memctl8xx_t im_memctl; /* Memory Controller */ - sit8xx_t im_sit; /* System integration timers */ - car8xx_t im_clkrst; /* Clocks and reset */ - sitk8xx_t im_sitk; /* Sys int timer keys */ - cark8xx_t im_clkrstk; /* Clocks and reset keys */ - vid823_t im_vid; /* Video (823 only) */ - lcd823_t im_lcd; /* LCD (823 only) */ - i2c8xx_t im_i2c; /* I2C control/status */ - sdma8xx_t im_sdma; /* SDMA control/status */ - cpic8xx_t im_cpic; /* CPM Interrupt Controller */ - iop8xx_t im_ioport; /* IO Port control/status */ - cpmtimer8xx_t im_cpmtimer; /* CPM timers */ - cpm8xx_t im_cpm; /* Communication processor */ -} immap_t; - -#endif /* __IMMAP_8XX__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/amigayle.h b/include/asm-ppc/amigayle.h deleted file mode 100644 index 1fe0b87859b0..000000000000 --- a/include/asm-ppc/amigayle.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-ppc/amipcmcia.h b/include/asm-ppc/amipcmcia.h deleted file mode 100644 index 3f65f63f508f..000000000000 --- a/include/asm-ppc/amipcmcia.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h deleted file mode 100644 index f6ed77aee328..000000000000 --- a/include/asm-ppc/bootinfo.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Non-machine dependent bootinfo structure. Basic idea - * borrowed from the m68k. - * - * Copyright (C) 1999 Cort Dougan - */ - -#ifdef __KERNEL__ -#ifndef _PPC_BOOTINFO_H -#define _PPC_BOOTINFO_H - -#include - -struct bi_record { - unsigned long tag; /* tag ID */ - unsigned long size; /* size of record (in bytes) */ - unsigned long data[0]; /* data */ -}; - -#define BI_FIRST 0x1010 /* first record - marker */ -#define BI_LAST 0x1011 /* last record - marker */ -#define BI_CMD_LINE 0x1012 -#define BI_BOOTLOADER_ID 0x1013 -#define BI_INITRD 0x1014 -#define BI_SYSMAP 0x1015 -#define BI_MACHTYPE 0x1016 -#define BI_MEMSIZE 0x1017 -#define BI_BOARD_INFO 0x1018 - -extern struct bi_record *find_bootinfo(void); -extern void bootinfo_init(struct bi_record *rec); -extern void bootinfo_append(unsigned long tag, unsigned long size, void * data); -extern void parse_bootinfo(struct bi_record *rec); -extern unsigned long boot_mem_size; - -static inline struct bi_record * -bootinfo_addr(unsigned long offset) -{ - - return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1, - (1 << 20)); -} - - -#endif /* _PPC_BOOTINFO_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/bootx.h b/include/asm-ppc/bootx.h deleted file mode 100644 index b0c51b45d7a2..000000000000 --- a/include/asm-ppc/bootx.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file describes the structure passed from the BootX application - * (for MacOS) when it is used to boot Linux. - * - * Written by Benjamin Herrenschmidt. - */ - - -#ifndef __ASM_BOOTX_H__ -#define __ASM_BOOTX_H__ - -#ifdef macintosh -#include -#include "linux_type_defs.h" -#endif - -#ifdef macintosh -/* All this requires PowerPC alignment */ -#pragma options align=power -#endif - -/* On kernel entry: - * - * r3 = 0x426f6f58 ('BooX') - * r4 = pointer to boot_infos - * r5 = NULL - * - * Data and instruction translation disabled, interrupts - * disabled, kernel loaded at physical 0x00000000 on PCI - * machines (will be different on NuBus). - */ - -#define BOOT_INFO_VERSION 5 -#define BOOT_INFO_COMPATIBLE_VERSION 1 - -/* Bit in the architecture flag mask. More to be defined in - future versions. Note that either BOOT_ARCH_PCI or - BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are - set additionally when BOOT_ARCH_NUBUS is set. - */ -#define BOOT_ARCH_PCI 0x00000001UL -#define BOOT_ARCH_NUBUS 0x00000002UL -#define BOOT_ARCH_NUBUS_PDM 0x00000010UL -#define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL -#define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL - -/* Maximum number of ranges in phys memory map */ -#define MAX_MEM_MAP_SIZE 26 - -/* This is the format of an element in the physical memory map. Note that - the map is optional and current BootX will only build it for pre-PCI - machines */ -typedef struct boot_info_map_entry -{ - __u32 physAddr; /* Physical starting address */ - __u32 size; /* Size in bytes */ -} boot_info_map_entry_t; - - -/* Here are the boot informations that are passed to the bootstrap - * Note that the kernel arguments and the device tree are appended - * at the end of this structure. */ -typedef struct boot_infos -{ - /* Version of this structure */ - __u32 version; - /* backward compatible down to version: */ - __u32 compatible_version; - - /* NEW (vers. 2) this holds the current _logical_ base addr of - the frame buffer (for use by early boot message) */ - __u8* logicalDisplayBase; - - /* NEW (vers. 4) Apple's machine identification */ - __u32 machineID; - - /* NEW (vers. 4) Detected hw architecture */ - __u32 architecture; - - /* The device tree (internal addresses relative to the beginning of the tree, - * device tree offset relative to the beginning of this structure). - * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this - * field is 0. - */ - __u32 deviceTreeOffset; /* Device tree offset */ - __u32 deviceTreeSize; /* Size of the device tree */ - - /* Some infos about the current MacOS display */ - __u32 dispDeviceRect[4]; /* left,top,right,bottom */ - __u32 dispDeviceDepth; /* (8, 16 or 32) */ - __u8* dispDeviceBase; /* base address (physical) */ - __u32 dispDeviceRowBytes; /* rowbytes (in bytes) */ - __u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */ - /* Optional offset in the registry to the current - * MacOS display. (Can be 0 when not detected) */ - __u32 dispDeviceRegEntryOffset; - - /* Optional pointer to boot ramdisk (offset from this structure) */ - __u32 ramDisk; - __u32 ramDiskSize; /* size of ramdisk image */ - - /* Kernel command line arguments (offset from this structure) */ - __u32 kernelParamsOffset; - - /* ALL BELOW NEW (vers. 4) */ - - /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag - (non-PCI) only. On PCI, memory is contiguous and it's size is in the - device-tree. */ - boot_info_map_entry_t - physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */ - __u32 physMemoryMapSize; /* How many entries in map */ - - - /* The framebuffer size (optional, currently 0) */ - __u32 frameBufferSize; /* Represents a max size, can be 0. */ - - /* NEW (vers. 5) */ - - /* Total params size (args + colormap + device tree + ramdisk) */ - __u32 totalParamsSize; - -} boot_infos_t; - -/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented - * by 3 short words containing a 16 bits (unsigned) color component. - * Later versions may contain the gamma table for direct-color devices here. - */ -#define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL) - -#ifdef macintosh -#pragma options align=reset -#endif - -#endif diff --git a/include/asm-ppc/btext.h b/include/asm-ppc/btext.h deleted file mode 100644 index ed3630251b3b..000000000000 --- a/include/asm-ppc/btext.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Definitions for using the procedures in btext.c. - * - * Benjamin Herrenschmidt - */ -#ifndef __PPC_BTEXT_H -#define __PPC_BTEXT_H -#ifdef __KERNEL__ - -#include - -extern void btext_clearscreen(void); -extern void btext_flushscreen(void); - -extern unsigned long disp_BAT[2]; - -extern boot_infos_t disp_bi; -extern int boot_text_mapped; - -extern void btext_init(boot_infos_t *bi); -extern void btext_welcome(void); -extern void btext_prepare_BAT(void); -extern void btext_setup_display(int width, int height, int depth, int pitch, - unsigned long address); -extern void map_boot_text(void); -extern void btext_update_display(unsigned long phys, int width, int height, - int depth, int pitch); - -extern void btext_drawchar(char c); -extern void btext_drawstring(const char *str); -extern void btext_drawhex(unsigned long v); - -#endif /* __KERNEL__ */ -#endif /* __PPC_BTEXT_H */ diff --git a/include/asm-ppc/cpm1.h b/include/asm-ppc/cpm1.h deleted file mode 100644 index 03035acd85c6..000000000000 --- a/include/asm-ppc/cpm1.h +++ /dev/null @@ -1,688 +0,0 @@ -/* - * MPC8xx Communication Processor Module. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * This file contains structures and information for the communication - * processor channels. Some CPM control and status is available - * throught the MPC8xx internal memory map. See immap.h for details. - * This file only contains what I need for the moment, not the total - * CPM capabilities. I (or someone else) will add definitions as they - * are needed. -- Dan - * - * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 - * bytes of the DP RAM and relocates the I2C parameter area to the - * IDMA1 space. The remaining DP RAM is available for buffer descriptors - * or other use. - */ -#ifndef __CPM1__ -#define __CPM1__ - -#include -#include - -/* CPM Command register. -*/ -#define CPM_CR_RST ((ushort)0x8000) -#define CPM_CR_OPCODE ((ushort)0x0f00) -#define CPM_CR_CHAN ((ushort)0x00f0) -#define CPM_CR_FLG ((ushort)0x0001) - -/* Some commands (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) -#define CPM_CR_SET_GADDR ((ushort)0x0008) -#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR - -/* Channel numbers. -*/ -#define CPM_CR_CH_SCC1 ((ushort)0x0000) -#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ -#define CPM_CR_CH_SCC2 ((ushort)0x0004) -#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ -#define CPM_CR_CH_TIMER CPM_CR_CH_SPI -#define CPM_CR_CH_SCC3 ((ushort)0x0008) -#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ -#define CPM_CR_CH_SCC4 ((ushort)0x000c) -#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ - -#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) - -/* The dual ported RAM is multi-functional. Some areas can be (and are - * being) used for microcode. There is an area that can only be used - * as data ram for buffer descriptors, which is all we use right now. - * Currently the first 512 and last 256 bytes are used for microcode. - */ -#define CPM_DATAONLY_BASE ((uint)0x0800) -#define CPM_DATAONLY_SIZE ((uint)0x0700) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm8xx_t *cpmp; /* Pointer to comm processor */ -extern unsigned long cpm_dpalloc(uint size, uint align); -extern int cpm_dpfree(unsigned long offset); -extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); -extern void cpm_dpdump(void); -extern void *cpm_dpram_addr(unsigned long offset); -extern uint cpm_dpram_phys(u8 *addr); -extern void cpm_setbrg(uint brg, uint rate); - -extern void cpm_load_patch(volatile immap_t *immr); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_UN ((ushort)0x0002) /* Underrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ -#define BD_SC_CL ((ushort)0x0001) /* Collision */ - -/* Parameter RAM offsets. -*/ -#define PROFF_SCC1 ((uint)0x0000) -#define PROFF_IIC ((uint)0x0080) -#define PROFF_SCC2 ((uint)0x0100) -#define PROFF_SPI ((uint)0x0180) -#define PROFF_SCC3 ((uint)0x0200) -#define PROFF_SMC1 ((uint)0x0280) -#define PROFF_SCC4 ((uint)0x0300) -#define PROFF_SMC2 ((uint)0x0380) - -/* Define enough so I can at least use the serial port as a UART. - * The MBX uses SMC1 as the host serial port. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - char res1[8]; /* Reserved */ - ushort smc_rpbase; /* Relocation pointer */ -} smc_uart_t; - -/* Function code bits. -*/ -#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* SMC uart mode register. -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC2 as Centronics parallel printer. It is half duplex, in that - * it can only receive or transmit. The parameter ram values for - * each direction are either unique or properly overlap, so we can - * include them in one structure. - */ -typedef struct smc_centronics { - ushort scent_rbase; - ushort scent_tbase; - u_char scent_cfcr; - u_char scent_smask; - ushort scent_mrblr; - uint scent_rstate; - uint scent_r_ptr; - ushort scent_rbptr; - ushort scent_r_cnt; - uint scent_rtemp; - uint scent_tstate; - uint scent_t_ptr; - ushort scent_tbptr; - ushort scent_t_cnt; - uint scent_ttemp; - ushort scent_max_sl; - ushort scent_sl_cnt; - ushort scent_character1; - ushort scent_character2; - ushort scent_character3; - ushort scent_character4; - ushort scent_character5; - ushort scent_character6; - ushort scent_character7; - ushort scent_character8; - ushort scent_rccm; - ushort scent_rccr; -} smc_cent_t; - -/* Centronics Status Mask Register. -*/ -#define SMC_CENT_F ((u_char)0x08) -#define SMC_CENT_PE ((u_char)0x04) -#define SMC_CENT_S ((u_char)0x02) - -/* SMC Event and Mask register. -*/ -#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ -#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ -#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SI Clock Route Register -*/ -#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) -#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) -#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) -#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) -#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) -#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* Function code bits. -*/ -#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* CPM Ethernet through SCCx. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PMSR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - char res1[8]; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PMSR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0002) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ - char res1[4]; /* Reserved */ - ushort iic_rpbase; /* Relocation pointer */ - char res2[2]; /* Reserved */ -} iic_t; - -#define BD_IIC_START ((ushort)0x0400) - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; - ushort spi_rpbase; /* Relocation pointer */ - ushort spi_res2; -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */ -#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */ -#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -/* SPIE fields */ -#define SPIE_MME 0x20 -#define SPIE_TXE 0x10 -#define SPIE_BSY 0x04 -#define SPIE_TXB 0x02 -#define SPIE_RXB 0x01 - -/* - * RISC Controller Configuration Register definitons - */ -#define RCCR_TIME 0x8000 /* RISC Timer Enable */ -#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ -#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ - -/* RISC Timer Parameter RAM offset */ -#define PROFF_RTMR ((uint)0x01B0) - -typedef struct risc_timer_pram { - unsigned short tm_base; /* RISC Timer Table Base Address */ - unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ - unsigned short r_tmr; /* RISC Timer Mode Register */ - unsigned short r_tmv; /* RISC Timer Valid Register */ - unsigned long tm_cmd; /* RISC Timer Command Register */ - unsigned long tm_cnt; /* RISC Timer Internal Count */ -} rt_pram_t; - -/* Bits in RISC Timer Command Register */ -#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ -#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ -#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ -#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ -#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ - -/* CPM interrupts. There are nearly 32 interrupts generated by CPM - * channels or devices. All of these are presented to the PPC core - * as a single interrupt. The CPM interrupt handler dispatches its - * own handlers, in a similar fashion to the PPC core handler. We - * use the table as defined in the manuals (i.e. no special high - * priority and SCC1 == SCCa, etc...). - */ -#define CPMVEC_NR 32 -#define CPMVEC_PIO_PC15 ((ushort)0x1f) -#define CPMVEC_SCC1 ((ushort)0x1e) -#define CPMVEC_SCC2 ((ushort)0x1d) -#define CPMVEC_SCC3 ((ushort)0x1c) -#define CPMVEC_SCC4 ((ushort)0x1b) -#define CPMVEC_PIO_PC14 ((ushort)0x1a) -#define CPMVEC_TIMER1 ((ushort)0x19) -#define CPMVEC_PIO_PC13 ((ushort)0x18) -#define CPMVEC_PIO_PC12 ((ushort)0x17) -#define CPMVEC_SDMA_CB_ERR ((ushort)0x16) -#define CPMVEC_IDMA1 ((ushort)0x15) -#define CPMVEC_IDMA2 ((ushort)0x14) -#define CPMVEC_TIMER2 ((ushort)0x12) -#define CPMVEC_RISCTIMER ((ushort)0x11) -#define CPMVEC_I2C ((ushort)0x10) -#define CPMVEC_PIO_PC11 ((ushort)0x0f) -#define CPMVEC_PIO_PC10 ((ushort)0x0e) -#define CPMVEC_TIMER3 ((ushort)0x0c) -#define CPMVEC_PIO_PC9 ((ushort)0x0b) -#define CPMVEC_PIO_PC8 ((ushort)0x0a) -#define CPMVEC_PIO_PC7 ((ushort)0x09) -#define CPMVEC_TIMER4 ((ushort)0x07) -#define CPMVEC_PIO_PC6 ((ushort)0x06) -#define CPMVEC_SPI ((ushort)0x05) -#define CPMVEC_SMC1 ((ushort)0x04) -#define CPMVEC_SMC2 ((ushort)0x03) -#define CPMVEC_PIO_PC5 ((ushort)0x02) -#define CPMVEC_PIO_PC4 ((ushort)0x01) -#define CPMVEC_ERROR ((ushort)0x00) - -/* CPM interrupt configuration vector. -*/ -#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ -#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ -#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ -#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ -#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ -#define CICR_IEN ((uint)0x00000080) /* Int. enable */ -#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ - -extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); -extern void cpm_free_handler(int vec); - -#endif /* __CPM1__ */ diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h deleted file mode 100644 index 4c538228e42f..000000000000 --- a/include/asm-ppc/cpm2.h +++ /dev/null @@ -1,1248 +0,0 @@ -/* - * Communication Processor Module v2. - * - * This file contains structures and information for the communication - * processor channels found in the dual port RAM or parameter RAM. - * All CPM control and status is available through the CPM2 internal - * memory map. See immap_cpm2.h for details. - */ -#ifdef __KERNEL__ -#ifndef __CPM2__ -#define __CPM2__ - -#include - -/* CPM Command register. -*/ -#define CPM_CR_RST ((uint)0x80000000) -#define CPM_CR_PAGE ((uint)0x7c000000) -#define CPM_CR_SBLOCK ((uint)0x03e00000) -#define CPM_CR_FLG ((uint)0x00010000) -#define CPM_CR_MCN ((uint)0x00003fc0) -#define CPM_CR_OPCODE ((uint)0x0000000f) - -/* Device sub-block and page codes. -*/ -#define CPM_CR_SCC1_SBLOCK (0x04) -#define CPM_CR_SCC2_SBLOCK (0x05) -#define CPM_CR_SCC3_SBLOCK (0x06) -#define CPM_CR_SCC4_SBLOCK (0x07) -#define CPM_CR_SMC1_SBLOCK (0x08) -#define CPM_CR_SMC2_SBLOCK (0x09) -#define CPM_CR_SPI_SBLOCK (0x0a) -#define CPM_CR_I2C_SBLOCK (0x0b) -#define CPM_CR_TIMER_SBLOCK (0x0f) -#define CPM_CR_RAND_SBLOCK (0x0e) -#define CPM_CR_FCC1_SBLOCK (0x10) -#define CPM_CR_FCC2_SBLOCK (0x11) -#define CPM_CR_FCC3_SBLOCK (0x12) -#define CPM_CR_IDMA1_SBLOCK (0x14) -#define CPM_CR_IDMA2_SBLOCK (0x15) -#define CPM_CR_IDMA3_SBLOCK (0x16) -#define CPM_CR_IDMA4_SBLOCK (0x17) -#define CPM_CR_MCC1_SBLOCK (0x1c) - -#define CPM_CR_FCC_SBLOCK(x) (x + 0x10) - -#define CPM_CR_SCC1_PAGE (0x00) -#define CPM_CR_SCC2_PAGE (0x01) -#define CPM_CR_SCC3_PAGE (0x02) -#define CPM_CR_SCC4_PAGE (0x03) -#define CPM_CR_SMC1_PAGE (0x07) -#define CPM_CR_SMC2_PAGE (0x08) -#define CPM_CR_SPI_PAGE (0x09) -#define CPM_CR_I2C_PAGE (0x0a) -#define CPM_CR_TIMER_PAGE (0x0a) -#define CPM_CR_RAND_PAGE (0x0a) -#define CPM_CR_FCC1_PAGE (0x04) -#define CPM_CR_FCC2_PAGE (0x05) -#define CPM_CR_FCC3_PAGE (0x06) -#define CPM_CR_IDMA1_PAGE (0x07) -#define CPM_CR_IDMA2_PAGE (0x08) -#define CPM_CR_IDMA3_PAGE (0x09) -#define CPM_CR_IDMA4_PAGE (0x0a) -#define CPM_CR_MCC1_PAGE (0x07) -#define CPM_CR_MCC2_PAGE (0x08) - -#define CPM_CR_FCC_PAGE(x) (x + 0x04) - -/* Some opcodes (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) -#define CPM_CR_START_IDMA ((ushort)0x0009) -#define CPM_CR_STOP_IDMA ((ushort)0x000b) - -#define mk_cr_cmd(PG, SBC, MCN, OP) \ - ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) - -/* Dual Port RAM addresses. The first 16K is available for almost - * any CPM use, so we put the BDs there. The first 128 bytes are - * used for SMC1 and SMC2 parameter RAM, so we start allocating - * BDs above that. All of this must change when we start - * downloading RAM microcode. - */ -#define CPM_DATAONLY_BASE ((uint)128) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) -#if defined(CONFIG_8272) -#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) -#else -#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) -#endif - -/* The number of pages of host memory we allocate for CPM. This is - * done early in kernel initialization to get physically contiguous - * pages. - */ -#define NUM_CPM_HOST_PAGES 2 - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ - -extern unsigned long cpm_dpalloc(uint size, uint align); -extern int cpm_dpfree(unsigned long offset); -extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); -extern void cpm_dpdump(void); -extern void *cpm_dpram_addr(unsigned long offset); -extern void cpm_setbrg(uint brg, uint rate); -extern void cpm2_fastbrg(uint brg, uint rate, int div16); -extern void cpm2_reset(void); - - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - -/* Function code bits, usually generic to devices. -*/ -#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ -#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ -#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ -#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ -#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ - -/* Parameter RAM offsets from the base. -*/ -#define PROFF_SCC1 ((uint)0x8000) -#define PROFF_SCC2 ((uint)0x8100) -#define PROFF_SCC3 ((uint)0x8200) -#define PROFF_SCC4 ((uint)0x8300) -#define PROFF_FCC1 ((uint)0x8400) -#define PROFF_FCC2 ((uint)0x8500) -#define PROFF_FCC3 ((uint)0x8600) -#define PROFF_MCC1 ((uint)0x8700) -#define PROFF_SMC1_BASE ((uint)0x87fc) -#define PROFF_IDMA1_BASE ((uint)0x87fe) -#define PROFF_MCC2 ((uint)0x8800) -#define PROFF_SMC2_BASE ((uint)0x88fc) -#define PROFF_IDMA2_BASE ((uint)0x88fe) -#define PROFF_SPI_BASE ((uint)0x89fc) -#define PROFF_IDMA3_BASE ((uint)0x89fe) -#define PROFF_TIMERS ((uint)0x8ae0) -#define PROFF_REVNUM ((uint)0x8af0) -#define PROFF_RAND ((uint)0x8af8) -#define PROFF_I2C_BASE ((uint)0x8afc) -#define PROFF_IDMA4_BASE ((uint)0x8afe) - -#define PROFF_SCC_SIZE ((uint)0x100) -#define PROFF_FCC_SIZE ((uint)0x100) -#define PROFF_SMC_SIZE ((uint)64) - -/* The SMCs are relocated to any of the first eight DPRAM pages. - * We will fix these at the first locations of DPRAM, until we - * get some microcode patches :-). - * The parameter ram space for the SMCs is fifty-some bytes, and - * they are required to start on a 64 byte boundary. - */ -#define PROFF_SMC1 (0) -#define PROFF_SMC2 (64) - - -/* Define enough so I can at least use the serial port as a UART. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - uint smc_stmp; /* SDMA Temp */ -} smc_uart_t; - -/* SMC uart mode register (Internal memory map). -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC Event and Mask register. -*/ -#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ -#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ -#define SMCM_TXE ((unsigned char)0x10) -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* CPM Ethernet through SCC1. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0002) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* How about some FCCs..... -*/ -#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) -#define FCC_GFMR_DIAG_LE ((uint)0x40000000) -#define FCC_GFMR_DIAG_AE ((uint)0x80000000) -#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) -#define FCC_GFMR_TCI ((uint)0x20000000) -#define FCC_GFMR_TRX ((uint)0x10000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_CDP ((uint)0x04000000) -#define FCC_GFMR_CTSP ((uint)0x02000000) -#define FCC_GFMR_CDS ((uint)0x01000000) -#define FCC_GFMR_CTSS ((uint)0x00800000) -#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) -#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) -#define FCC_GFMR_SYNL_8 ((uint)0x00008000) -#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) -#define FCC_GFMR_RTSM ((uint)0x00002000) -#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) -#define FCC_GFMR_REVD ((uint)0x00000400) -#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) -#define FCC_GFMR_TCRC_16 ((uint)0x00000000) -#define FCC_GFMR_TCRC_32 ((uint)0x00000080) -#define FCC_GFMR_ENR ((uint)0x00000020) -#define FCC_GFMR_ENT ((uint)0x00000010) -#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) -#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) -#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) - -/* Generic FCC parameter ram. -*/ -typedef struct fcc_param { - ushort fcc_riptr; /* Rx Internal temp pointer */ - ushort fcc_tiptr; /* Tx Internal temp pointer */ - ushort fcc_res1; - ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ - uint fcc_rstate; /* Upper byte is Func code, must be set */ - uint fcc_rbase; /* Receive BD base */ - ushort fcc_rbdstat; /* RxBD status */ - ushort fcc_rbdlen; /* RxBD down counter */ - uint fcc_rdptr; /* RxBD internal data pointer */ - uint fcc_tstate; /* Upper byte is Func code, must be set */ - uint fcc_tbase; /* Transmit BD base */ - ushort fcc_tbdstat; /* TxBD status */ - ushort fcc_tbdlen; /* TxBD down counter */ - uint fcc_tdptr; /* TxBD internal data pointer */ - uint fcc_rbptr; /* Rx BD Internal buf pointer */ - uint fcc_tbptr; /* Tx BD Internal buf pointer */ - uint fcc_rcrc; /* Rx temp CRC */ - uint fcc_res2; - uint fcc_tcrc; /* Tx temp CRC */ -} fccp_t; - - -/* Ethernet controller through FCC. -*/ -typedef struct fcc_enet { - fccp_t fen_genfcc; - uint fen_statbuf; /* Internal status buffer */ - uint fen_camptr; /* CAM address */ - uint fen_cmask; /* Constant mask for CRC */ - uint fen_cpres; /* Preset CRC */ - uint fen_crcec; /* CRC Error counter */ - uint fen_alec; /* alignment error counter */ - uint fen_disfc; /* discard frame counter */ - ushort fen_retlim; /* Retry limit */ - ushort fen_retcnt; /* Retry counter */ - ushort fen_pper; /* Persistence */ - ushort fen_boffcnt; /* backoff counter */ - uint fen_gaddrh; /* Group address filter, high 32-bits */ - uint fen_gaddrl; /* Group address filter, low 32-bits */ - ushort fen_tfcstat; /* out of sequence TxBD */ - ushort fen_tfclen; - uint fen_tfcptr; - ushort fen_mflr; /* Maximum frame length (1518) */ - ushort fen_paddrh; /* MAC address */ - ushort fen_paddrm; - ushort fen_paddrl; - ushort fen_ibdcount; /* Internal BD counter */ - ushort fen_ibdstart; /* Internal BD start pointer */ - ushort fen_ibdend; /* Internal BD end pointer */ - ushort fen_txlen; /* Internal Tx frame length counter */ - uint fen_ibdbase[8]; /* Internal use */ - uint fen_iaddrh; /* Individual address filter */ - uint fen_iaddrl; - ushort fen_minflr; /* Minimum frame length (64) */ - ushort fen_taddrh; /* Filter transfer MAC address */ - ushort fen_taddrm; - ushort fen_taddrl; - ushort fen_padptr; /* Pointer to pad byte buffer */ - ushort fen_cftype; /* control frame type */ - ushort fen_cfrange; /* control frame range */ - ushort fen_maxb; /* maximum BD count */ - ushort fen_maxd1; /* Max DMA1 length (1520) */ - ushort fen_maxd2; /* Max DMA2 length (1520) */ - ushort fen_maxd; /* internal max DMA count */ - ushort fen_dmacnt; /* internal DMA counter */ - uint fen_octc; /* Total octect counter */ - uint fen_colc; /* Total collision counter */ - uint fen_broc; /* Total broadcast packet counter */ - uint fen_mulc; /* Total multicast packet count */ - uint fen_uspc; /* Total packets < 64 bytes */ - uint fen_frgc; /* Total packets < 64 bytes with errors */ - uint fen_ospc; /* Total packets > 1518 */ - uint fen_jbrc; /* Total packets > 1518 with errors */ - uint fen_p64c; /* Total packets == 64 bytes */ - uint fen_p65c; /* Total packets 64 < bytes <= 127 */ - uint fen_p128c; /* Total packets 127 < bytes <= 255 */ - uint fen_p256c; /* Total packets 256 < bytes <= 511 */ - uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ - uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ - uint fen_cambuf; /* Internal CAM buffer poiner */ - ushort fen_rfthr; /* Received frames threshold */ - ushort fen_rfcnt; /* Received frames count */ -} fcc_enet_t; - -/* FCC Event/Mask register as used by Ethernet. -*/ -#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ -#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ -#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ -#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* FCC Mode Register (FPSMR) as used by Ethernet. -*/ -#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ -#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ -#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ -#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ -#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ -#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ -#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ -#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ -#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ -#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ -#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ -#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ -#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; /* Tx temp. */ - uint spi_res1[4]; /* SDMA temp. */ -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -#define SPI_EB ((u_char)0x10) /* big endian byte order */ - -#define BD_IIC_START ((ushort)0x0400) - -/* IDMA parameter RAM -*/ -typedef struct idma { - ushort ibase; /* IDMA buffer descriptor table base address */ - ushort dcm; /* DMA channel mode */ - ushort ibdptr; /* IDMA current buffer descriptor pointer */ - ushort dpr_buf; /* IDMA transfer buffer base address */ - ushort buf_inv; /* internal buffer inventory */ - ushort ss_max; /* steady-state maximum transfer size */ - ushort dpr_in_ptr; /* write pointer inside the internal buffer */ - ushort sts; /* source transfer size */ - ushort dpr_out_ptr; /* read pointer inside the internal buffer */ - ushort seob; /* source end of burst */ - ushort deob; /* destination end of burst */ - ushort dts; /* destination transfer size */ - ushort ret_add; /* return address when working in ERM=1 mode */ - ushort res0; /* reserved */ - uint bd_cnt; /* internal byte count */ - uint s_ptr; /* source internal data pointer */ - uint d_ptr; /* destination internal data pointer */ - uint istate; /* internal state */ - u_char res1[20]; /* pad to 64-byte length */ -} idma_t; - -/* DMA channel mode bit fields -*/ -#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ -#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ -#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ -#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ -#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ -#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ -#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ -#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ -#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ -#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ -#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ -#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ -#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ - -/* IDMA Buffer Descriptors -*/ -typedef struct idma_bd { - uint flags; - uint len; /* data length */ - uint src; /* source data buffer pointer */ - uint dst; /* destination data buffer pointer */ -} idma_bd_t; - -/* IDMA buffer descriptor flag bit fields -*/ -#define IDMA_BD_V ((uint)0x80000000) /* valid */ -#define IDMA_BD_W ((uint)0x20000000) /* wrap */ -#define IDMA_BD_I ((uint)0x10000000) /* interrupt */ -#define IDMA_BD_L ((uint)0x08000000) /* last */ -#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ -#define IDMA_BD_SDN ((uint)0x00400000) /* source done */ -#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ -#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ -#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ -#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ -#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ -#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ -#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ -#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ -#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ - -/* per-channel IDMA registers -*/ -typedef struct im_idma { - u_char idsr; /* IDMAn event status register */ - u_char res0[3]; - u_char idmr; /* IDMAn event mask register */ - u_char res1[3]; -} im_idma_t; - -/* IDMA event register bit fields -*/ -#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ -#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ -#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ -#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ - -/* RISC Controller Configuration Register (RCCR) bit fields -*/ -#define RCCR_TIME ((uint)0x80000000) /* timer enable */ -#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ -#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ -#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ -#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ -#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ -#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ -#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ -#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ -#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ -#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ -#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ -#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ -#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ -#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ -#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ -#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ -#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ -#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ -#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ -#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ -#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ -#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ -#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ -#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ -#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ -#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ -#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ -#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ -#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ -#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ -#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ -#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ -#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ -#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ -#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ -#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ -#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ - -/*----------------------------------------------------------------------- - * CMXFCR - CMX FCC Clock Route Register - */ -#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ -#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ -#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ -#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ -#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ -#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ -#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ -#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ -#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ - -#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ -#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ -#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ -#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ -#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ -#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ -#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ -#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ - -#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ -#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ -#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ -#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ -#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ -#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ -#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ -#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ - -#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ -#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ -#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ -#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ -#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ -#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ -#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ -#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ - -#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ -#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ -#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ -#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ -#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ -#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ -#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ -#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ - -#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ -#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ -#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ -#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ -#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ -#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ -#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ -#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ - -#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ -#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ -#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ -#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ -#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ -#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ -#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ -#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ - -/*----------------------------------------------------------------------- - * CMXSCR - CMX SCC Clock Route Register - */ -#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ -#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ -#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ -#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ -#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ -#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ -#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ -#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ -#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ -#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ -#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ -#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ -#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ -#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ -#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ -#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ - -#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ -#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ -#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ -#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ -#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ -#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ -#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ -#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ -#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ -#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ -#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ -#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ -#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ -#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ -#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ -#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ -#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ -#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ -#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ -#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ -#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ -#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ -#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ -#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ -#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ -#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ -#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ -#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ -#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ -#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ -#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ -#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ -#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ -#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ -#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ -#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ -#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ -#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ -#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ -#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ -#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ -#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ -#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ - -#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ -#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ -#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ -#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ -#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ -#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ -#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ -#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ -#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ -#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ -#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ -#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ -#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ -#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ -#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration Register 4-31 - */ -#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ -#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ -#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ -#define SIUMCR_CDIS 0x10000000 /* Core Disable */ -#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ -#define SIUMCR_DPPC01 0x04000000 /* - " - */ -#define SIUMCR_DPPC10 0x08000000 /* - " - */ -#define SIUMCR_DPPC11 0x0c000000 /* - " - */ -#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ -#define SIUMCR_L2CPC01 0x01000000 /* - " - */ -#define SIUMCR_L2CPC10 0x02000000 /* - " - */ -#define SIUMCR_L2CPC11 0x03000000 /* - " - */ -#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ -#define SIUMCR_LBPC01 0x00400000 /* - " - */ -#define SIUMCR_LBPC10 0x00800000 /* - " - */ -#define SIUMCR_LBPC11 0x00c00000 /* - " - */ -#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ -#define SIUMCR_APPC01 0x00100000 /* - " - */ -#define SIUMCR_APPC10 0x00200000 /* - " - */ -#define SIUMCR_APPC11 0x00300000 /* - " - */ -#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ -#define SIUMCR_CS10PC01 0x00040000 /* - " - */ -#define SIUMCR_CS10PC10 0x00080000 /* - " - */ -#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ -#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ -#define SIUMCR_BCTLC01 0x00010000 /* - " - */ -#define SIUMCR_BCTLC10 0x00020000 /* - " - */ -#define SIUMCR_BCTLC11 0x00030000 /* - " - */ -#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ -#define SIUMCR_MMR01 0x00004000 /* - " - */ -#define SIUMCR_MMR10 0x00008000 /* - " - */ -#define SIUMCR_MMR11 0x0000c000 /* - " - */ -#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control Register 9-8 -*/ -#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ -#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ -#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ -#define SCCR_PCIDF_SHIFT 3 - -#ifndef CPM_IMMR_OFFSET -#define CPM_IMMR_OFFSET 0x101a8 -#endif - -#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ - -/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK - * in order to use clock-computing stuff below for the FCC x - */ - -/* Automatically generates register configurations */ -#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ - -#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ -#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ -#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ -#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ -#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ -#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ - -#define PC_F1RXCLK PC_CLK(F1_RXCLK) -#define PC_F1TXCLK PC_CLK(F1_TXCLK) -#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) -#define CMX1_CLK_MASK ((uint)0xff000000) - -#define PC_F2RXCLK PC_CLK(F2_RXCLK) -#define PC_F2TXCLK PC_CLK(F2_TXCLK) -#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) -#define CMX2_CLK_MASK ((uint)0x00ff0000) - -#define PC_F3RXCLK PC_CLK(F3_RXCLK) -#define PC_F3TXCLK PC_CLK(F3_TXCLK) -#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) -#define CMX3_CLK_MASK ((uint)0x0000ff00) - -#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK) -#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE) - -#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK) - -/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, - * but there is little variation among the choices. - */ -#define PA1_COL 0x00000001U -#define PA1_CRS 0x00000002U -#define PA1_TXER 0x00000004U -#define PA1_TXEN 0x00000008U -#define PA1_RXDV 0x00000010U -#define PA1_RXER 0x00000020U -#define PA1_TXDAT 0x00003c00U -#define PA1_RXDAT 0x0003c000U -#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) -#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ - PA1_RXDV | PA1_RXER) -#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) -#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) - - -/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, - * but there is little variation among the choices. - */ -#define PB2_TXER 0x00000001U -#define PB2_RXDV 0x00000002U -#define PB2_TXEN 0x00000004U -#define PB2_RXER 0x00000008U -#define PB2_COL 0x00000010U -#define PB2_CRS 0x00000020U -#define PB2_TXDAT 0x000003c0U -#define PB2_RXDAT 0x00003c00U -#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ - PB2_RXER | PB2_RXDV | PB2_TXER) -#define PB2_PSORB1 (PB2_TXEN) -#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) -#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) - - -/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, - * but there is little variation among the choices. - */ -#define PB3_RXDV 0x00004000U -#define PB3_RXER 0x00008000U -#define PB3_TXER 0x00010000U -#define PB3_TXEN 0x00020000U -#define PB3_COL 0x00040000U -#define PB3_CRS 0x00080000U -#define PB3_TXDAT 0x0f000000U -#define PC3_TXDAT 0x00000010U -#define PB3_RXDAT 0x00f00000U -#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ - PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) -#define PB3_PSORB1 0 -#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) -#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) -#define PC3_DIRC1 (PC3_TXDAT) - -/* Handy macro to specify mem for FCCs*/ -#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) -#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) -#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) -#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2) - -/* Clocks and GRG's */ - -enum cpm_clk_dir { - CPM_CLK_RX, - CPM_CLK_TX, - CPM_CLK_RTX -}; - -enum cpm_clk_target { - CPM_CLK_SCC1, - CPM_CLK_SCC2, - CPM_CLK_SCC3, - CPM_CLK_SCC4, - CPM_CLK_FCC1, - CPM_CLK_FCC2, - CPM_CLK_FCC3 -}; - -enum cpm_clk { - CPM_CLK_NONE = 0, - CPM_BRG1, /* Baud Rate Generator 1 */ - CPM_BRG2, /* Baud Rate Generator 2 */ - CPM_BRG3, /* Baud Rate Generator 3 */ - CPM_BRG4, /* Baud Rate Generator 4 */ - CPM_BRG5, /* Baud Rate Generator 5 */ - CPM_BRG6, /* Baud Rate Generator 6 */ - CPM_BRG7, /* Baud Rate Generator 7 */ - CPM_BRG8, /* Baud Rate Generator 8 */ - CPM_CLK1, /* Clock 1 */ - CPM_CLK2, /* Clock 2 */ - CPM_CLK3, /* Clock 3 */ - CPM_CLK4, /* Clock 4 */ - CPM_CLK5, /* Clock 5 */ - CPM_CLK6, /* Clock 6 */ - CPM_CLK7, /* Clock 7 */ - CPM_CLK8, /* Clock 8 */ - CPM_CLK9, /* Clock 9 */ - CPM_CLK10, /* Clock 10 */ - CPM_CLK11, /* Clock 11 */ - CPM_CLK12, /* Clock 12 */ - CPM_CLK13, /* Clock 13 */ - CPM_CLK14, /* Clock 14 */ - CPM_CLK15, /* Clock 15 */ - CPM_CLK16, /* Clock 16 */ - CPM_CLK17, /* Clock 17 */ - CPM_CLK18, /* Clock 18 */ - CPM_CLK19, /* Clock 19 */ - CPM_CLK20, /* Clock 20 */ - CPM_CLK_DUMMY -}; - -extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode); - -#endif /* __CPM2__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/delay.h b/include/asm-ppc/delay.h deleted file mode 100644 index badde6845af2..000000000000 --- a/include/asm-ppc/delay.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_DELAY_H -#define _PPC_DELAY_H - -#include - -/* - * Copyright 1996, Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -extern unsigned long loops_per_jiffy; - -extern void __delay(unsigned int loops); - -/* - * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so - * loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32. - * - * The mulhwu instruction gives us loops = (a * b) / 2^32. - * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226 - * because this lets us support a wide range of HZ and - * loops_per_jiffy values without either a or b overflowing 2^32. - * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and - * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280 - * (which corresponds to ~3800 bogomips at HZ = 100). - * -- paulus - */ -#define __MAX_UDELAY (226050910UL/HZ) /* maximum udelay argument */ -#define __MAX_NDELAY (4294967295UL/HZ) /* maximum ndelay argument */ - -extern __inline__ void __udelay(unsigned int x) -{ - unsigned int loops; - - __asm__("mulhwu %0,%1,%2" : "=r" (loops) : - "r" (x), "r" (loops_per_jiffy * 226)); - __delay(loops); -} - -extern __inline__ void __ndelay(unsigned int x) -{ - unsigned int loops; - - __asm__("mulhwu %0,%1,%2" : "=r" (loops) : - "r" (x), "r" (loops_per_jiffy * 5)); - __delay(loops); -} - -extern void __bad_udelay(void); /* deliberately undefined */ -extern void __bad_ndelay(void); /* deliberately undefined */ - -#define udelay(n) (__builtin_constant_p(n)? \ - ((n) > __MAX_UDELAY? __bad_udelay(): __udelay((n) * (19 * HZ))) : \ - __udelay((n) * (19 * HZ))) - -#define ndelay(n) (__builtin_constant_p(n)? \ - ((n) > __MAX_NDELAY? __bad_ndelay(): __ndelay((n) * HZ)) : \ - __ndelay((n) * HZ)) - -#endif /* defined(_PPC_DELAY_H) */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/device.h b/include/asm-ppc/device.h deleted file mode 100644 index d8f9872b0e2d..000000000000 --- a/include/asm-ppc/device.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Arch specific extensions to struct device - * - * This file is released under the GPLv2 - */ -#include - diff --git a/include/asm-ppc/floppy.h b/include/asm-ppc/floppy.h deleted file mode 100644 index 7d9b3f430d92..000000000000 --- a/include/asm-ppc/floppy.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Architecture specific parts of the Floppy driver - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 - */ -#ifdef __KERNEL__ -#ifndef __ASM_PPC_FLOPPY_H -#define __ASM_PPC_FLOPPY_H - -#define fd_inb(port) inb_p(port) -#define fd_outb(value,port) outb_p(value,port) - -#define fd_disable_dma() fd_ops->_disable_dma(FLOPPY_DMA) -#define fd_free_dma() fd_ops->_free_dma(FLOPPY_DMA) -#define fd_get_dma_residue() fd_ops->_get_dma_residue(FLOPPY_DMA) -#define fd_dma_setup(addr, size, mode, io) fd_ops->_dma_setup(addr, size, mode, io) -#define fd_enable_irq() enable_irq(FLOPPY_IRQ) -#define fd_disable_irq() disable_irq(FLOPPY_IRQ) -#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); - -static int fd_request_dma(void); - -struct fd_dma_ops { - void (*_disable_dma)(unsigned int dmanr); - void (*_free_dma)(unsigned int dmanr); - int (*_get_dma_residue)(unsigned int dummy); - int (*_dma_setup)(char *addr, unsigned long size, int mode, int io); -}; - -static int virtual_dma_count; -static int virtual_dma_residue; -static char *virtual_dma_addr; -static int virtual_dma_mode; -static int doing_vdma; -static struct fd_dma_ops *fd_ops; - -static irqreturn_t floppy_hardint(int irq, void *dev_id) -{ - unsigned char st; - int lcount; - char *lptr; - - if (!doing_vdma) - return floppy_interrupt(irq, dev_id); - - - st = 1; - for (lcount=virtual_dma_count, lptr=virtual_dma_addr; - lcount; lcount--, lptr++) { - st=inb(virtual_dma_port+4) & 0xa0 ; - if (st != 0xa0) - break; - if (virtual_dma_mode) - outb_p(*lptr, virtual_dma_port+5); - else - *lptr = inb_p(virtual_dma_port+5); - } - virtual_dma_count = lcount; - virtual_dma_addr = lptr; - st = inb(virtual_dma_port+4); - - if (st == 0x20) - return IRQ_HANDLED; - if (!(st & 0x20)) { - virtual_dma_residue += virtual_dma_count; - virtual_dma_count=0; - doing_vdma = 0; - floppy_interrupt(irq, dev_id); - return IRQ_HANDLED; - } - return IRQ_HANDLED; -} - -static void vdma_disable_dma(unsigned int dummy) -{ - doing_vdma = 0; - virtual_dma_residue += virtual_dma_count; - virtual_dma_count=0; -} - -static void vdma_nop(unsigned int dummy) -{ -} - - -static int vdma_get_dma_residue(unsigned int dummy) -{ - return virtual_dma_count + virtual_dma_residue; -} - - -static int fd_request_irq(void) -{ - if (can_use_virtual_dma) - return request_irq(FLOPPY_IRQ, floppy_hardint, - IRQF_DISABLED, "floppy", NULL); - else - return request_irq(FLOPPY_IRQ, floppy_interrupt, - IRQF_DISABLED, "floppy", NULL); -} - -static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io) -{ - doing_vdma = 1; - virtual_dma_port = io; - virtual_dma_mode = (mode == DMA_MODE_WRITE); - virtual_dma_addr = addr; - virtual_dma_count = size; - virtual_dma_residue = 0; - return 0; -} - -static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) -{ - /* actual, physical DMA */ - doing_vdma = 0; - clear_dma_ff(FLOPPY_DMA); - set_dma_mode(FLOPPY_DMA,mode); - set_dma_addr(FLOPPY_DMA,(unsigned int)virt_to_bus(addr)); - set_dma_count(FLOPPY_DMA,size); - enable_dma(FLOPPY_DMA); - return 0; -} - -static struct fd_dma_ops real_dma_ops = -{ - ._disable_dma = disable_dma, - ._free_dma = free_dma, - ._get_dma_residue = get_dma_residue, - ._dma_setup = hard_dma_setup -}; - -static struct fd_dma_ops virt_dma_ops = -{ - ._disable_dma = vdma_disable_dma, - ._free_dma = vdma_nop, - ._get_dma_residue = vdma_get_dma_residue, - ._dma_setup = vdma_dma_setup -}; - -static int fd_request_dma() -{ - if (can_use_virtual_dma & 1) { - fd_ops = &virt_dma_ops; - return 0; - } - else { - fd_ops = &real_dma_ops; - return request_dma(FLOPPY_DMA, "floppy"); - } -} - -static int FDC1 = 0x3f0; -static int FDC2 = -1; - -/* - * Again, the CMOS information not available - */ -#define FLOPPY0_TYPE 6 -#define FLOPPY1_TYPE 0 - -#define N_FDC 2 /* Don't change this! */ -#define N_DRIVE 8 - -/* - * The PowerPC has no problems with floppy DMA crossing 64k borders. - */ -#define CROSS_64KB(a,s) (0) - -#endif /* __ASM_PPC_FLOPPY_H */ - -#define EXTRA_FLOPPY_PARAMS - -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/fs_pd.h b/include/asm-ppc/fs_pd.h deleted file mode 100644 index 8691327653af..000000000000 --- a/include/asm-ppc/fs_pd.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Platform information definitions. - * - * 2006 (c) MontaVista Software, Inc. - * Vitaly Bordug - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef FS_PD_H -#define FS_PD_H - -static inline int uart_baudrate(void) -{ - int baud; - bd_t *bd = (bd_t *) __res; - - if (bd->bi_baudrate) - baud = bd->bi_baudrate; - else - baud = -1; - return baud; -} - -static inline int uart_clock(void) -{ - return (((bd_t *) __res)->bi_intfreq); -} - -#define cpm2_map(member) (&cpm2_immr->member) -#define cpm2_map_size(member, size) (&cpm2_immr->member) -#define cpm2_unmap(addr) do {} while(0) - -#endif diff --git a/include/asm-ppc/gg2.h b/include/asm-ppc/gg2.h deleted file mode 100644 index 341ae55b99fb..000000000000 --- a/include/asm-ppc/gg2.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions - * - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is based on the following documentation: - * - * The VAS96011/12 Chipset, Data Book, Edition 1.0 - * VLSI Technology, Inc. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _ASMPPC_GG2_H -#define _ASMPPC_GG2_H - - /* - * Memory Map (CHRP mode) - */ - -#define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ -#define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ -#define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ -#define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ -#define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ - /* special PCI cycles */ -#define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ -#define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ - - - /* - * GG2 specific PCI Registers - */ - -extern void __iomem *gg2_pci_config_base; /* kernel virtual address */ - -#define GG2_PCI_BUSNO 0x40 /* Bus number */ -#define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ -#define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ -#define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ -#define GG2_PCI_ADDR_MAP 0x5c /* Address map */ -#define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ -#define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ -#define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ -#define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ -#define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ -#define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ -#define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ -#define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ -#define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ -#define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ -#define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ -#define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ -#define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ -#define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ -#define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ - /* Cleared when read */ - -#endif /* _ASMPPC_GG2_H */ diff --git a/include/asm-ppc/gt64260.h b/include/asm-ppc/gt64260.h deleted file mode 100644 index 9e63b3cfffca..000000000000 --- a/include/asm-ppc/gt64260.h +++ /dev/null @@ -1,322 +0,0 @@ -/* - * include/asm-ppc/gt64260.h - * - * Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines. - * - * Author: Mark A. Greer - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASMPPC_GT64260_H -#define __ASMPPC_GT64260_H - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - - -extern u32 gt64260_base; -extern u32 gt64260_irq_base; /* We handle the next 96 IRQs from here */ -extern u32 gt64260_revision; -extern u8 gt64260_pci_exclude_bridge; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -/* IRQs defined by the 64260 */ -#define GT64260_IRQ_MPSC0 40 -#define GT64260_IRQ_MPSC1 42 -#define GT64260_IRQ_SDMA 36 - -/* - * Define a default physical memory map to be set up on the bridge. - * Also define a struct to pass that info from board-specific routines to - * GT64260 generic set up routines. By passing this info in, the board - * support developer can modify it at will. - */ - -/* - * This is the default memory map: - * CPU PCI - * --- --- - * PCI 0 I/O: 0xfa000000-0xfaffffff 0x00000000-0x00ffffff - * PCI 1 I/O: 0xfb000000-0xfbffffff 0x01000000-0x01ffffff - * PCI 0 MEM: 0x80000000-0x8fffffff 0x80000000-0x8fffffff - * PCI 1 MEM: 0x90000000-0x9fffffff 0x90000000-0x9fffffff - */ - -/* Default physical memory map for the GT64260 bridge */ - -/* - * PCI Bus 0 Definitions - */ -#define GT64260_PCI_0_IO_SIZE 0x01000000U -#define GT64260_PCI_0_MEM_SIZE 0x10000000U - -/* Processor Physical addresses */ -#define GT64260_PCI_0_IO_START_PROC 0xfa000000U -#define GT64260_PCI_0_IO_END_PROC (GT64260_PCI_0_IO_START_PROC + \ - GT64260_PCI_0_IO_SIZE - 1) - -/* PCI 0 addresses */ -#define GT64260_PCI_0_IO_START 0x00000000U -#define GT64260_PCI_0_IO_END (GT64260_PCI_0_IO_START + \ - GT64260_PCI_0_IO_SIZE - 1) - -/* Processor Physical addresses */ -#define GT64260_PCI_0_MEM_START_PROC 0x80000000U -#define GT64260_PCI_0_MEM_END_PROC (GT64260_PCI_0_MEM_START_PROC + \ - GT64260_PCI_0_MEM_SIZE - 1) - -/* PCI 0 addresses */ -#define GT64260_PCI_0_MEM_START 0x80000000U -#define GT64260_PCI_0_MEM_END (GT64260_PCI_0_MEM_START + \ - GT64260_PCI_0_MEM_SIZE - 1) - -/* - * PCI Bus 1 Definitions - */ -#define GT64260_PCI_1_IO_SIZE 0x01000000U -#define GT64260_PCI_1_MEM_SIZE 0x10000000U - -/* PCI 1 addresses */ -#define GT64260_PCI_1_IO_START 0x01000000U -#define GT64260_PCI_1_IO_END (GT64260_PCI_1_IO_START + \ - GT64260_PCI_1_IO_SIZE - 1) - -/* Processor Physical addresses */ -#define GT64260_PCI_1_IO_START_PROC 0xfb000000U -#define GT64260_PCI_1_IO_END_PROC (GT64260_PCI_1_IO_START_PROC + \ - GT64260_PCI_1_IO_SIZE - 1) - -/* PCI 1 addresses */ -#define GT64260_PCI_1_MEM_START 0x90000000U -#define GT64260_PCI_1_MEM_END (GT64260_PCI_1_MEM_START + \ - GT64260_PCI_1_MEM_SIZE - 1) - -/* Processor Physical addresses */ -#define GT64260_PCI_1_MEM_START_PROC 0x90000000U -#define GT64260_PCI_1_MEM_END_PROC (GT64260_PCI_1_MEM_START_PROC + \ - GT64260_PCI_1_MEM_SIZE - 1) - -/* Define struct to pass mem-map info into gt64260_common.c code */ -typedef struct { - struct pci_controller *hose_a; - struct pci_controller *hose_b; - - u32 mem_size; - - u32 pci_0_io_start_proc; - u32 pci_0_io_start_pci; - u32 pci_0_io_size; - u32 pci_0_io_swap; - - u32 pci_0_mem_start_proc; - u32 pci_0_mem_start_pci_hi; - u32 pci_0_mem_start_pci_lo; - u32 pci_0_mem_size; - u32 pci_0_mem_swap; - - u32 pci_1_io_start_proc; - u32 pci_1_io_start_pci; - u32 pci_1_io_size; - u32 pci_1_io_swap; - - u32 pci_1_mem_start_proc; - u32 pci_1_mem_start_pci_hi; - u32 pci_1_mem_start_pci_lo; - u32 pci_1_mem_size; - u32 pci_1_mem_swap; -} gt64260_bridge_info_t; - -#define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) { \ - (ip)->mem_size = (ms); \ - \ - (ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC; \ - (ip)->pci_0_io_start_pci = GT64260_PCI_0_IO_START; \ - (ip)->pci_0_io_size = GT64260_PCI_0_IO_SIZE; \ - (ip)->pci_0_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ - \ - (ip)->pci_0_mem_start_proc = GT64260_PCI_0_MEM_START_PROC; \ - (ip)->pci_0_mem_start_pci_hi = 0x00000000; \ - (ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START; \ - (ip)->pci_0_mem_size = GT64260_PCI_0_MEM_SIZE; \ - (ip)->pci_0_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ - \ - (ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC; \ - (ip)->pci_1_io_start_pci = GT64260_PCI_1_IO_START; \ - (ip)->pci_1_io_size = GT64260_PCI_1_IO_SIZE; \ - (ip)->pci_1_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ - \ - (ip)->pci_1_mem_start_proc = GT64260_PCI_1_MEM_START_PROC; \ - (ip)->pci_1_mem_start_pci_hi = 0x00000000; \ - (ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START; \ - (ip)->pci_1_mem_size = GT64260_PCI_1_MEM_SIZE; \ - (ip)->pci_1_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ -} - -/* - ***************************************************************************** - * - * I/O macros to access the 64260's registers - * - ***************************************************************************** - */ - -extern inline uint32_t gt_read(uint32_t offs){ - return (in_le32((volatile uint *)(gt64260_base + offs))); -} -extern inline void gt_write(uint32_t offs, uint32_t d){ - out_le32((volatile uint *)(gt64260_base + offs), d); -} - -#if 0 /* paranoid SMP version */ -extern inline void gt_modify(u32 offs, u32 data, u32 mask) \ -{ - uint32_t reg; - spin_lock(>64260_lock); - reg = gt_read(offs) & (~mask); /* zero any bits we care about*/ - reg |= data & mask; /* set bits from the data */ - gt_write(offs, reg); - spin_unlock(>64260_lock); -} -#else -extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask) -{ - uint32_t reg; - reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/ - reg |= (data) & (mask); /* set bits from the data */ - gt_write(offs, reg); -} -#endif -#define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits) - -#define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits) - - -/* - ***************************************************************************** - * - * Function Prototypes - * - ***************************************************************************** - */ - -int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info, - int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char))); -int gt64260_bridge_init(gt64260_bridge_info_t *info); -int gt64260_cpu_scs_set_window(u32 window, - u32 base_addr, - u32 size); -int gt64260_cpu_cs_set_window(u32 window, - u32 base_addr, - u32 size); -int gt64260_cpu_boot_set_window(u32 base_addr, - u32 size); -int gt64260_cpu_set_pci_io_window(u32 pci_bus, - u32 cpu_base_addr, - u32 pci_base_addr, - u32 size, - u32 swap); -int gt64260_cpu_set_pci_mem_window(u32 pci_bus, - u32 window, - u32 cpu_base_addr, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 size, - u32 swap_64bit); -int gt64260_cpu_prot_set_window(u32 window, - u32 base_addr, - u32 size, - u32 access_bits); -int gt64260_cpu_snoop_set_window(u32 window, - u32 base_addr, - u32 size, - u32 snoop_type); -void gt64260_cpu_disable_all_windows(void); -int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits); -int gt64260_pci_slave_scs_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_cs_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_boot_set_window(struct pci_controller *hose, - u32 pci_base_addr, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr, - u32 other_bus_base_addr, - u32 size); -int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose, - u32 pci_base_addr, - u32 other_bus_base_addr, - u32 size); -int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 other_bus_base_addr, - u32 size); -int gt64260_pci_acc_cntl_set_window(u32 pci_bus, - u32 window, - u32 base_addr_hi, - u32 base_addr_lo, - u32 size, - u32 features); -int gt64260_pci_snoop_set_window(u32 pci_bus, - u32 window, - u32 base_addr_hi, - u32 base_addr_lo, - u32 size, - u32 snoop_type); -int gt64260_set_base(u32 new_base); -int gt64260_get_base(u32 *base); -int gt64260_pci_exclude_device(u8 bus, u8 devfn); - -void gt64260_init_irq(void); -int gt64260_get_irq(void); - -void gt64260_mpsc_progress(char *s, unsigned short hex); - -#endif /* __ASMPPC_GT64260_H */ diff --git a/include/asm-ppc/gt64260_defs.h b/include/asm-ppc/gt64260_defs.h deleted file mode 100644 index 6ffd01a5373e..000000000000 --- a/include/asm-ppc/gt64260_defs.h +++ /dev/null @@ -1,1010 +0,0 @@ -/* - * include/asm-ppc/gt64260_defs.h - * - * Register definitions for the Marvell/Galileo GT64260 host bridge. - * - * Author: Mark A. Greer - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASMPPC_GT64260_DEFS_H -#define __ASMPPC_GT64260_DEFS_H - -/* - * Define a macro to represent the supported version of the 64260. - */ -#define GT64260 0x01 -#define GT64260A 0x10 - -/* - ***************************************************************************** - * - * CPU Interface Registers - * - ***************************************************************************** - */ - -/* CPU physical address of 64260's registers */ -#define GT64260_INTERNAL_SPACE_DECODE 0x0068 -#define GT64260_INTERNAL_SPACE_SIZE 0x10000 -#define GT64260_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000 - -/* CPU Memory Controller Window Registers (4 windows) */ -#define GT64260_CPU_SCS_DECODE_WINDOWS 4 - -#define GT64260_CPU_SCS_DECODE_0_BOT 0x0008 -#define GT64260_CPU_SCS_DECODE_0_TOP 0x0010 -#define GT64260_CPU_SCS_DECODE_1_BOT 0x0208 -#define GT64260_CPU_SCS_DECODE_1_TOP 0x0210 -#define GT64260_CPU_SCS_DECODE_2_BOT 0x0018 -#define GT64260_CPU_SCS_DECODE_2_TOP 0x0020 -#define GT64260_CPU_SCS_DECODE_3_BOT 0x0218 -#define GT64260_CPU_SCS_DECODE_3_TOP 0x0220 - -/* CPU Device Controller Window Registers (4 windows) */ -#define GT64260_CPU_CS_DECODE_WINDOWS 4 - -#define GT64260_CPU_CS_DECODE_0_BOT 0x0028 -#define GT64260_CPU_CS_DECODE_0_TOP 0x0030 -#define GT64260_CPU_CS_DECODE_1_BOT 0x0228 -#define GT64260_CPU_CS_DECODE_1_TOP 0x0230 -#define GT64260_CPU_CS_DECODE_2_BOT 0x0248 -#define GT64260_CPU_CS_DECODE_2_TOP 0x0250 -#define GT64260_CPU_CS_DECODE_3_BOT 0x0038 -#define GT64260_CPU_CS_DECODE_3_TOP 0x0040 - -#define GT64260_CPU_BOOT_CS_DECODE_0_BOT 0x0238 -#define GT64260_CPU_BOOT_CS_DECODE_0_TOP 0x0240 - -/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */ -#define GT64260_PCI_BUSES 2 -#define GT64260_PCI_IO_WINDOWS_PER_BUS 1 -#define GT64260_PCI_MEM_WINDOWS_PER_BUS 4 - -#define GT64260_CPU_PCI_SWAP_BYTE 0x00000000 -#define GT64260_CPU_PCI_SWAP_NONE 0x01000000 -#define GT64260_CPU_PCI_SWAP_BYTE_WORD 0x02000000 -#define GT64260_CPU_PCI_SWAP_WORD 0x03000000 -#define GT64260_CPU_PCI_SWAP_MASK 0x07000000 - -#define GT64260_CPU_PCI_MEM_REQ64 (1<<27) - -#define GT64260_CPU_PCI_0_IO_DECODE_BOT 0x0048 -#define GT64260_CPU_PCI_0_IO_DECODE_TOP 0x0050 -#define GT64260_CPU_PCI_0_MEM_0_DECODE_BOT 0x0058 -#define GT64260_CPU_PCI_0_MEM_0_DECODE_TOP 0x0060 -#define GT64260_CPU_PCI_0_MEM_1_DECODE_BOT 0x0080 -#define GT64260_CPU_PCI_0_MEM_1_DECODE_TOP 0x0088 -#define GT64260_CPU_PCI_0_MEM_2_DECODE_BOT 0x0258 -#define GT64260_CPU_PCI_0_MEM_2_DECODE_TOP 0x0260 -#define GT64260_CPU_PCI_0_MEM_3_DECODE_BOT 0x0280 -#define GT64260_CPU_PCI_0_MEM_3_DECODE_TOP 0x0288 - -#define GT64260_CPU_PCI_0_IO_REMAP 0x00f0 -#define GT64260_CPU_PCI_0_MEM_0_REMAP_LO 0x00f8 -#define GT64260_CPU_PCI_0_MEM_0_REMAP_HI 0x0320 -#define GT64260_CPU_PCI_0_MEM_1_REMAP_LO 0x0100 -#define GT64260_CPU_PCI_0_MEM_1_REMAP_HI 0x0328 -#define GT64260_CPU_PCI_0_MEM_2_REMAP_LO 0x02f8 -#define GT64260_CPU_PCI_0_MEM_2_REMAP_HI 0x0330 -#define GT64260_CPU_PCI_0_MEM_3_REMAP_LO 0x0300 -#define GT64260_CPU_PCI_0_MEM_3_REMAP_HI 0x0338 - -#define GT64260_CPU_PCI_1_IO_DECODE_BOT 0x0090 -#define GT64260_CPU_PCI_1_IO_DECODE_TOP 0x0098 -#define GT64260_CPU_PCI_1_MEM_0_DECODE_BOT 0x00a0 -#define GT64260_CPU_PCI_1_MEM_0_DECODE_TOP 0x00a8 -#define GT64260_CPU_PCI_1_MEM_1_DECODE_BOT 0x00b0 -#define GT64260_CPU_PCI_1_MEM_1_DECODE_TOP 0x00b8 -#define GT64260_CPU_PCI_1_MEM_2_DECODE_BOT 0x02a0 -#define GT64260_CPU_PCI_1_MEM_2_DECODE_TOP 0x02a8 -#define GT64260_CPU_PCI_1_MEM_3_DECODE_BOT 0x02b0 -#define GT64260_CPU_PCI_1_MEM_3_DECODE_TOP 0x02b8 - -#define GT64260_CPU_PCI_1_IO_REMAP 0x0108 -#define GT64260_CPU_PCI_1_MEM_0_REMAP_LO 0x0110 -#define GT64260_CPU_PCI_1_MEM_0_REMAP_HI 0x0340 -#define GT64260_CPU_PCI_1_MEM_1_REMAP_LO 0x0118 -#define GT64260_CPU_PCI_1_MEM_1_REMAP_HI 0x0348 -#define GT64260_CPU_PCI_1_MEM_2_REMAP_LO 0x0310 -#define GT64260_CPU_PCI_1_MEM_2_REMAP_HI 0x0350 -#define GT64260_CPU_PCI_1_MEM_3_REMAP_LO 0x0318 -#define GT64260_CPU_PCI_1_MEM_3_REMAP_HI 0x0358 - -/* CPU Control Registers */ -#define GT64260_CPU_CONFIG 0x0000 -#define GT64260_CPU_MODE 0x0120 -#define GT64260_CPU_MASTER_CNTL 0x0160 -#define GT64260_CPU_XBAR_CNTL_LO 0x0150 -#define GT64260_CPU_XBAR_CNTL_HI 0x0158 -#define GT64260_CPU_XBAR_TO 0x0168 -#define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170 -#define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178 - -/* CPU Sync Barrier Registers */ -#define GT64260_CPU_SYNC_BARRIER_PCI_0 0x00c0 -#define GT64260_CPU_SYNC_BARRIER_PCI_1 0x00c8 - -/* CPU Access Protection Registers */ -#define GT64260_CPU_PROT_WINDOWS 8 - -#define GT64260_CPU_PROT_ACCPROTECT (1<<16) -#define GT64260_CPU_PROT_WRPROTECT (1<<17) -#define GT64260_CPU_PROT_CACHEPROTECT (1<<18) - -#define GT64260_CPU_PROT_BASE_0 0x0180 -#define GT64260_CPU_PROT_TOP_0 0x0188 -#define GT64260_CPU_PROT_BASE_1 0x0190 -#define GT64260_CPU_PROT_TOP_1 0x0198 -#define GT64260_CPU_PROT_BASE_2 0x01a0 -#define GT64260_CPU_PROT_TOP_2 0x01a8 -#define GT64260_CPU_PROT_BASE_3 0x01b0 -#define GT64260_CPU_PROT_TOP_3 0x01b8 -#define GT64260_CPU_PROT_BASE_4 0x01c0 -#define GT64260_CPU_PROT_TOP_4 0x01c8 -#define GT64260_CPU_PROT_BASE_5 0x01d0 -#define GT64260_CPU_PROT_TOP_5 0x01d8 -#define GT64260_CPU_PROT_BASE_6 0x01e0 -#define GT64260_CPU_PROT_TOP_6 0x01e8 -#define GT64260_CPU_PROT_BASE_7 0x01f0 -#define GT64260_CPU_PROT_TOP_7 0x01f8 - -/* CPU Snoop Control Registers */ -#define GT64260_CPU_SNOOP_WINDOWS 4 - -#define GT64260_CPU_SNOOP_NONE 0x00000000 -#define GT64260_CPU_SNOOP_WT 0x00010000 -#define GT64260_CPU_SNOOP_WB 0x00020000 -#define GT64260_CPU_SNOOP_MASK 0x00030000 -#define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK - -#define GT64260_CPU_SNOOP_BASE_0 0x0380 -#define GT64260_CPU_SNOOP_TOP_0 0x0388 -#define GT64260_CPU_SNOOP_BASE_1 0x0390 -#define GT64260_CPU_SNOOP_TOP_1 0x0398 -#define GT64260_CPU_SNOOP_BASE_2 0x03a0 -#define GT64260_CPU_SNOOP_TOP_2 0x03a8 -#define GT64260_CPU_SNOOP_BASE_3 0x03b0 -#define GT64260_CPU_SNOOP_TOP_3 0x03b8 - -/* CPU Error Report Registers */ -#define GT64260_CPU_ERR_ADDR_LO 0x0070 -#define GT64260_CPU_ERR_ADDR_HI 0x0078 -#define GT64260_CPU_ERR_DATA_LO 0x0128 -#define GT64260_CPU_ERR_DATA_HI 0x0130 -#define GT64260_CPU_ERR_PARITY 0x0138 -#define GT64260_CPU_ERR_CAUSE 0x0140 -#define GT64260_CPU_ERR_MASK 0x0148 - - -/* - ***************************************************************************** - * - * SDRAM Cotnroller Registers - * - ***************************************************************************** - */ - -/* SDRAM Config Registers */ -#define GT64260_SDRAM_CONFIG 0x0448 -#define GT64260_SDRAM_OPERATION_MODE 0x0474 -#define GT64260_SDRAM_ADDR_CNTL 0x047c -#define GT64260_SDRAM_TIMING_PARAMS 0x04b4 -#define GT64260_SDRAM_UMA_CNTL 0x04a4 -#define GT64260_SDRAM_XBAR_CNTL_LO 0x04a8 -#define GT64260_SDRAM_XBAR_CNTL_HI 0x04ac -#define GT64260_SDRAM_XBAR_CNTL_TO 0x04b0 - -/* SDRAM Banks Parameters Registers */ -#define GT64260_SDRAM_BANK_PARAMS_0 0x044c -#define GT64260_SDRAM_BANK_PARAMS_1 0x0450 -#define GT64260_SDRAM_BANK_PARAMS_2 0x0454 -#define GT64260_SDRAM_BANK_PARAMS_3 0x0458 - -/* SDRAM Error Report Registers */ -#define GT64260_SDRAM_ERR_DATA_LO 0x0484 -#define GT64260_SDRAM_ERR_DATA_HI 0x0480 -#define GT64260_SDRAM_ERR_ADDR 0x0490 -#define GT64260_SDRAM_ERR_ECC_RCVD 0x0488 -#define GT64260_SDRAM_ERR_ECC_CALC 0x048c -#define GT64260_SDRAM_ERR_ECC_CNTL 0x0494 -#define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498 - - -/* - ***************************************************************************** - * - * Device/BOOT Cotnroller Registers - * - ***************************************************************************** - */ - -/* Device Control Registers */ -#define GT64260_DEV_BANK_PARAMS_0 0x045c -#define GT64260_DEV_BANK_PARAMS_1 0x0460 -#define GT64260_DEV_BANK_PARAMS_2 0x0464 -#define GT64260_DEV_BANK_PARAMS_3 0x0468 -#define GT64260_DEV_BOOT_PARAMS 0x046c -#define GT64260_DEV_IF_CNTL 0x04c0 -#define GT64260_DEV_IF_XBAR_CNTL_LO 0x04c8 -#define GT64260_DEV_IF_XBAR_CNTL_HI 0x04cc -#define GT64260_DEV_IF_XBAR_CNTL_TO 0x04c4 - -/* Device Interrupt Registers */ -#define GT64260_DEV_INTR_CAUSE 0x04d0 -#define GT64260_DEV_INTR_MASK 0x04d4 -#define GT64260_DEV_INTR_ERR_ADDR 0x04d8 - - -/* - ***************************************************************************** - * - * PCI Bridge Interface Registers - * - ***************************************************************************** - */ - -/* PCI Configuration Access Registers */ -#define GT64260_PCI_0_CONFIG_ADDR 0x0cf8 -#define GT64260_PCI_0_CONFIG_DATA 0x0cfc -#define GT64260_PCI_0_IACK 0x0c34 - -#define GT64260_PCI_1_CONFIG_ADDR 0x0c78 -#define GT64260_PCI_1_CONFIG_DATA 0x0c7c -#define GT64260_PCI_1_IACK 0x0cb4 - -/* PCI Control Registers */ -#define GT64260_PCI_0_CMD 0x0c00 -#define GT64260_PCI_0_MODE 0x0d00 -#define GT64260_PCI_0_TO_RETRY 0x0c04 -#define GT64260_PCI_0_RD_BUF_DISCARD_TIMER 0x0d04 -#define GT64260_PCI_0_MSI_TRIGGER_TIMER 0x0c38 -#define GT64260_PCI_0_ARBITER_CNTL 0x1d00 -#define GT64260_PCI_0_XBAR_CNTL_LO 0x1d08 -#define GT64260_PCI_0_XBAR_CNTL_HI 0x1d0c -#define GT64260_PCI_0_XBAR_CNTL_TO 0x1d04 -#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO 0x1d18 -#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI 0x1d1c -#define GT64260_PCI_0_SYNC_BARRIER 0x1d10 -#define GT64260_PCI_0_P2P_CONFIG 0x1d14 -#define GT64260_PCI_0_P2P_SWAP_CNTL 0x1d54 - -#define GT64260_PCI_1_CMD 0x0c80 -#define GT64260_PCI_1_MODE 0x0d80 -#define GT64260_PCI_1_TO_RETRY 0x0c84 -#define GT64260_PCI_1_RD_BUF_DISCARD_TIMER 0x0d84 -#define GT64260_PCI_1_MSI_TRIGGER_TIMER 0x0cb8 -#define GT64260_PCI_1_ARBITER_CNTL 0x1d80 -#define GT64260_PCI_1_XBAR_CNTL_LO 0x1d88 -#define GT64260_PCI_1_XBAR_CNTL_HI 0x1d8c -#define GT64260_PCI_1_XBAR_CNTL_TO 0x1d84 -#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO 0x1d98 -#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI 0x1d9c -#define GT64260_PCI_1_SYNC_BARRIER 0x1d90 -#define GT64260_PCI_1_P2P_CONFIG 0x1d94 -#define GT64260_PCI_1_P2P_SWAP_CNTL 0x1dd4 - -/* PCI Access Control Regions Registers */ -#define GT64260_PCI_ACC_CNTL_WINDOWS 8 - -#define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12) -#define GT64260_PCI_ACC_CNTL_DREADEN (1<<13) -#define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16) -#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17) -#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18) -#define GT64260_PCI_ACC_CNTL_MBURST_4_WORDS 0x00000000 -#define GT64260_PCI_ACC_CNTL_MBURST_8_WORDS 0x00100000 -#define GT64260_PCI_ACC_CNTL_MBURST_16_WORDS 0x00200000 -#define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000 -#define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 -#define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000 -#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000 -#define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000 -#define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000 -#define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28) -#define GT64260_PCI_ACC_CNTL_WRPROT (1<<29) - -#define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \ - GT64260_PCI_ACC_CNTL_DREADEN | \ - GT64260_PCI_ACC_CNTL_RDPREFETCH | \ - GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\ - GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \ - GT64260_PCI_ACC_CNTL_MBURST_MASK | \ - GT64260_PCI_ACC_CNTL_SWAP_MASK | \ - GT64260_PCI_ACC_CNTL_ACCPROT| \ - GT64260_PCI_ACC_CNTL_WRPROT) - -#define GT64260_PCI_0_ACC_CNTL_0_BASE_LO 0x1e00 -#define GT64260_PCI_0_ACC_CNTL_0_BASE_HI 0x1e04 -#define GT64260_PCI_0_ACC_CNTL_0_TOP 0x1e08 -#define GT64260_PCI_0_ACC_CNTL_1_BASE_LO 0x1e10 -#define GT64260_PCI_0_ACC_CNTL_1_BASE_HI 0x1e14 -#define GT64260_PCI_0_ACC_CNTL_1_TOP 0x1e18 -#define GT64260_PCI_0_ACC_CNTL_2_BASE_LO 0x1e20 -#define GT64260_PCI_0_ACC_CNTL_2_BASE_HI 0x1e24 -#define GT64260_PCI_0_ACC_CNTL_2_TOP 0x1e28 -#define GT64260_PCI_0_ACC_CNTL_3_BASE_LO 0x1e30 -#define GT64260_PCI_0_ACC_CNTL_3_BASE_HI 0x1e34 -#define GT64260_PCI_0_ACC_CNTL_3_TOP 0x1e38 -#define GT64260_PCI_0_ACC_CNTL_4_BASE_LO 0x1e40 -#define GT64260_PCI_0_ACC_CNTL_4_BASE_HI 0x1e44 -#define GT64260_PCI_0_ACC_CNTL_4_TOP 0x1e48 -#define GT64260_PCI_0_ACC_CNTL_5_BASE_LO 0x1e50 -#define GT64260_PCI_0_ACC_CNTL_5_BASE_HI 0x1e54 -#define GT64260_PCI_0_ACC_CNTL_5_TOP 0x1e58 -#define GT64260_PCI_0_ACC_CNTL_6_BASE_LO 0x1e60 -#define GT64260_PCI_0_ACC_CNTL_6_BASE_HI 0x1e64 -#define GT64260_PCI_0_ACC_CNTL_6_TOP 0x1e68 -#define GT64260_PCI_0_ACC_CNTL_7_BASE_LO 0x1e70 -#define GT64260_PCI_0_ACC_CNTL_7_BASE_HI 0x1e74 -#define GT64260_PCI_0_ACC_CNTL_7_TOP 0x1e78 - -#define GT64260_PCI_1_ACC_CNTL_0_BASE_LO 0x1e80 -#define GT64260_PCI_1_ACC_CNTL_0_BASE_HI 0x1e84 -#define GT64260_PCI_1_ACC_CNTL_0_TOP 0x1e88 -#define GT64260_PCI_1_ACC_CNTL_1_BASE_LO 0x1e90 -#define GT64260_PCI_1_ACC_CNTL_1_BASE_HI 0x1e94 -#define GT64260_PCI_1_ACC_CNTL_1_TOP 0x1e98 -#define GT64260_PCI_1_ACC_CNTL_2_BASE_LO 0x1ea0 -#define GT64260_PCI_1_ACC_CNTL_2_BASE_HI 0x1ea4 -#define GT64260_PCI_1_ACC_CNTL_2_TOP 0x1ea8 -#define GT64260_PCI_1_ACC_CNTL_3_BASE_LO 0x1eb0 -#define GT64260_PCI_1_ACC_CNTL_3_BASE_HI 0x1eb4 -#define GT64260_PCI_1_ACC_CNTL_3_TOP 0x1eb8 -#define GT64260_PCI_1_ACC_CNTL_4_BASE_LO 0x1ec0 -#define GT64260_PCI_1_ACC_CNTL_4_BASE_HI 0x1ec4 -#define GT64260_PCI_1_ACC_CNTL_4_TOP 0x1ec8 -#define GT64260_PCI_1_ACC_CNTL_5_BASE_LO 0x1ed0 -#define GT64260_PCI_1_ACC_CNTL_5_BASE_HI 0x1ed4 -#define GT64260_PCI_1_ACC_CNTL_5_TOP 0x1ed8 -#define GT64260_PCI_1_ACC_CNTL_6_BASE_LO 0x1ee0 -#define GT64260_PCI_1_ACC_CNTL_6_BASE_HI 0x1ee4 -#define GT64260_PCI_1_ACC_CNTL_6_TOP 0x1ee8 -#define GT64260_PCI_1_ACC_CNTL_7_BASE_LO 0x1ef0 -#define GT64260_PCI_1_ACC_CNTL_7_BASE_HI 0x1ef4 -#define GT64260_PCI_1_ACC_CNTL_7_TOP 0x1ef8 - -/* PCI Snoop Control Registers */ -#define GT64260_PCI_SNOOP_WINDOWS 4 - -#define GT64260_PCI_SNOOP_NONE 0x00000000 -#define GT64260_PCI_SNOOP_WT 0x00001000 -#define GT64260_PCI_SNOOP_WB 0x00002000 - -#define GT64260_PCI_0_SNOOP_0_BASE_LO 0x1f00 -#define GT64260_PCI_0_SNOOP_0_BASE_HI 0x1f04 -#define GT64260_PCI_0_SNOOP_0_TOP 0x1f08 -#define GT64260_PCI_0_SNOOP_1_BASE_LO 0x1f10 -#define GT64260_PCI_0_SNOOP_1_BASE_HI 0x1f14 -#define GT64260_PCI_0_SNOOP_1_TOP 0x1f18 -#define GT64260_PCI_0_SNOOP_2_BASE_LO 0x1f20 -#define GT64260_PCI_0_SNOOP_2_BASE_HI 0x1f24 -#define GT64260_PCI_0_SNOOP_2_TOP 0x1f28 -#define GT64260_PCI_0_SNOOP_3_BASE_LO 0x1f30 -#define GT64260_PCI_0_SNOOP_3_BASE_HI 0x1f34 -#define GT64260_PCI_0_SNOOP_3_TOP 0x1f38 - -#define GT64260_PCI_1_SNOOP_0_BASE_LO 0x1f80 -#define GT64260_PCI_1_SNOOP_0_BASE_HI 0x1f84 -#define GT64260_PCI_1_SNOOP_0_TOP 0x1f88 -#define GT64260_PCI_1_SNOOP_1_BASE_LO 0x1f90 -#define GT64260_PCI_1_SNOOP_1_BASE_HI 0x1f94 -#define GT64260_PCI_1_SNOOP_1_TOP 0x1f98 -#define GT64260_PCI_1_SNOOP_2_BASE_LO 0x1fa0 -#define GT64260_PCI_1_SNOOP_2_BASE_HI 0x1fa4 -#define GT64260_PCI_1_SNOOP_2_TOP 0x1fa8 -#define GT64260_PCI_1_SNOOP_3_BASE_LO 0x1fb0 -#define GT64260_PCI_1_SNOOP_3_BASE_HI 0x1fb4 -#define GT64260_PCI_1_SNOOP_3_TOP 0x1fb8 - -/* PCI Error Report Registers */ -#define GT64260_PCI_0_ERR_SERR_MASK 0x0c28 -#define GT64260_PCI_0_ERR_ADDR_LO 0x1d40 -#define GT64260_PCI_0_ERR_ADDR_HI 0x1d44 -#define GT64260_PCI_0_ERR_DATA_LO 0x1d48 -#define GT64260_PCI_0_ERR_DATA_HI 0x1d4c -#define GT64260_PCI_0_ERR_CMD 0x1d50 -#define GT64260_PCI_0_ERR_CAUSE 0x1d58 -#define GT64260_PCI_0_ERR_MASK 0x1d5c - -#define GT64260_PCI_1_ERR_SERR_MASK 0x0ca8 -#define GT64260_PCI_1_ERR_ADDR_LO 0x1dc0 -#define GT64260_PCI_1_ERR_ADDR_HI 0x1dc4 -#define GT64260_PCI_1_ERR_DATA_LO 0x1dc8 -#define GT64260_PCI_1_ERR_DATA_HI 0x1dcc -#define GT64260_PCI_1_ERR_CMD 0x1dd0 -#define GT64260_PCI_1_ERR_CAUSE 0x1dd8 -#define GT64260_PCI_1_ERR_MASK 0x1ddc - -/* PCI Slave Address Decoding Registers */ -#define GT64260_PCI_SCS_WINDOWS 4 -#define GT64260_PCI_CS_WINDOWS 4 -#define GT64260_PCI_BOOT_WINDOWS 1 -#define GT64260_PCI_P2P_MEM_WINDOWS 2 -#define GT64260_PCI_P2P_IO_WINDOWS 1 -#define GT64260_PCI_DAC_SCS_WINDOWS 4 -#define GT64260_PCI_DAC_CS_WINDOWS 4 -#define GT64260_PCI_DAC_BOOT_WINDOWS 1 -#define GT64260_PCI_DAC_P2P_MEM_WINDOWS 2 - -#define GT64260_PCI_0_SLAVE_SCS_0_SIZE 0x0c08 -#define GT64260_PCI_0_SLAVE_SCS_1_SIZE 0x0d08 -#define GT64260_PCI_0_SLAVE_SCS_2_SIZE 0x0c0c -#define GT64260_PCI_0_SLAVE_SCS_3_SIZE 0x0d0c -#define GT64260_PCI_0_SLAVE_CS_0_SIZE 0x0c10 -#define GT64260_PCI_0_SLAVE_CS_1_SIZE 0x0d10 -#define GT64260_PCI_0_SLAVE_CS_2_SIZE 0x0d18 -#define GT64260_PCI_0_SLAVE_CS_3_SIZE 0x0c14 -#define GT64260_PCI_0_SLAVE_BOOT_SIZE 0x0d14 -#define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE 0x0d1c -#define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE 0x0d20 -#define GT64260_PCI_0_SLAVE_P2P_IO_SIZE 0x0d24 -#define GT64260_PCI_0_SLAVE_CPU_SIZE 0x0d28 - -#define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE 0x0e00 -#define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE 0x0e04 -#define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE 0x0e08 -#define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE 0x0e0c -#define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE 0x0e10 -#define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE 0x0e14 -#define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE 0x0e18 -#define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE 0x0e1c -#define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE 0x0e20 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE 0x0e24 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE 0x0e28 -#define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE 0x0e2c - -#define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE 0x0d2c - -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0 (1<<0) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1 (1<<1) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2 (1<<2) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3 (1<<3) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0 (1<<4) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1 (1<<5) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2 (1<<6) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3 (1<<7) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT (1<<8) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM (1<<9) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO (1<<10) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0 (1<<11) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1 (1<<12) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO (1<<13) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU (1<<14) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0 (1<<15) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1 (1<<16) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2 (1<<17) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3 (1<<18) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0 (1<<19) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1 (1<<20) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2 (1<<21) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3 (1<<22) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT (1<<23) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU (1<<26) - -#define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES 0x0c3c -#define GT64260_PCI_0_SLAVE_SCS_0_REMAP 0x0c48 -#define GT64260_PCI_0_SLAVE_SCS_1_REMAP 0x0d48 -#define GT64260_PCI_0_SLAVE_SCS_2_REMAP 0x0c4c -#define GT64260_PCI_0_SLAVE_SCS_3_REMAP 0x0d4c -#define GT64260_PCI_0_SLAVE_CS_0_REMAP 0x0c50 -#define GT64260_PCI_0_SLAVE_CS_1_REMAP 0x0d50 -#define GT64260_PCI_0_SLAVE_CS_2_REMAP 0x0d58 -#define GT64260_PCI_0_SLAVE_CS_3_REMAP 0x0c54 -#define GT64260_PCI_0_SLAVE_BOOT_REMAP 0x0d54 -#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c -#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60 -#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64 -#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68 -#define GT64260_PCI_0_SLAVE_P2P_IO_REMAP 0x0d6c -#define GT64260_PCI_0_SLAVE_CPU_REMAP 0x0d70 - -#define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP 0x0f00 -#define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP 0x0f04 -#define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP 0x0f08 -#define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP 0x0f0c -#define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP 0x0f10 -#define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP 0x0f14 -#define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP 0x0f18 -#define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP 0x0f1c -#define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP 0x0f20 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0f24 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0f28 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0f2c -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0f30 -#define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP 0x0f34 - -#define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP 0x0f38 -#define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL 0x0d3c - -#define GT64260_PCI_1_SLAVE_SCS_0_SIZE 0x0c88 -#define GT64260_PCI_1_SLAVE_SCS_1_SIZE 0x0d88 -#define GT64260_PCI_1_SLAVE_SCS_2_SIZE 0x0c8c -#define GT64260_PCI_1_SLAVE_SCS_3_SIZE 0x0d8c -#define GT64260_PCI_1_SLAVE_CS_0_SIZE 0x0c90 -#define GT64260_PCI_1_SLAVE_CS_1_SIZE 0x0d90 -#define GT64260_PCI_1_SLAVE_CS_2_SIZE 0x0d98 -#define GT64260_PCI_1_SLAVE_CS_3_SIZE 0x0c94 -#define GT64260_PCI_1_SLAVE_BOOT_SIZE 0x0d94 -#define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE 0x0d9c -#define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE 0x0da0 -#define GT64260_PCI_1_SLAVE_P2P_IO_SIZE 0x0da4 -#define GT64260_PCI_1_SLAVE_CPU_SIZE 0x0da8 - -#define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE 0x0e80 -#define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE 0x0e84 -#define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE 0x0e88 -#define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE 0x0e8c -#define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE 0x0e90 -#define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE 0x0e94 -#define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE 0x0e98 -#define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE 0x0e9c -#define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE 0x0ea0 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE 0x0ea4 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE 0x0ea8 -#define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE 0x0eac - -#define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE 0x0dac - -#define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES 0x0cbc -#define GT64260_PCI_1_SLAVE_SCS_0_REMAP 0x0cc8 -#define GT64260_PCI_1_SLAVE_SCS_1_REMAP 0x0dc8 -#define GT64260_PCI_1_SLAVE_SCS_2_REMAP 0x0ccc -#define GT64260_PCI_1_SLAVE_SCS_3_REMAP 0x0dcc -#define GT64260_PCI_1_SLAVE_CS_0_REMAP 0x0cd0 -#define GT64260_PCI_1_SLAVE_CS_1_REMAP 0x0dd0 -#define GT64260_PCI_1_SLAVE_CS_2_REMAP 0x0dd8 -#define GT64260_PCI_1_SLAVE_CS_3_REMAP 0x0cd4 -#define GT64260_PCI_1_SLAVE_BOOT_REMAP 0x0dd4 -#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc -#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0 -#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4 -#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8 -#define GT64260_PCI_1_SLAVE_P2P_IO_REMAP 0x0dec -#define GT64260_PCI_1_SLAVE_CPU_REMAP 0x0df0 - -#define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP 0x0f80 -#define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP 0x0f84 -#define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP 0x0f88 -#define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP 0x0f8c -#define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP 0x0f90 -#define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP 0x0f94 -#define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP 0x0f98 -#define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP 0x0f9c -#define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP 0x0fa0 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0fa4 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0fa8 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0fac -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0fb0 -#define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP 0x0fb4 - -#define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP 0x0fb8 -#define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL 0x0dbc - - -/* - ***************************************************************************** - * - * I2O Controller Interface Registers - * - ***************************************************************************** - */ - -/* FIXME: fill in */ - - - -/* - ***************************************************************************** - * - * DMA Controller Interface Registers - * - ***************************************************************************** - */ - -/* FIXME: fill in */ - - -/* - ***************************************************************************** - * - * Timer/Counter Interface Registers - * - ***************************************************************************** - */ - -/* FIXME: fill in */ - - -/* - ***************************************************************************** - * - * Communications Controller (Enet, Serial, etc.) Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_ENET_0_CNTL_LO 0xf200 -#define GT64260_ENET_0_CNTL_HI 0xf204 -#define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI 0xf208 -#define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI 0xf20c -#define GT64260_ENET_0_RX_DESC_ADDR_HI 0xf210 -#define GT64260_ENET_0_TX_DESC_ADDR_HI 0xf214 -#define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI 0xf218 -#define GT64260_ENET_1_CNTL_LO 0xf220 -#define GT64260_ENET_1_CNTL_HI 0xf224 -#define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI 0xf228 -#define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI 0xf22c -#define GT64260_ENET_1_RX_DESC_ADDR_HI 0xf230 -#define GT64260_ENET_1_TX_DESC_ADDR_HI 0xf234 -#define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI 0xf238 -#define GT64260_ENET_2_CNTL_LO 0xf240 -#define GT64260_ENET_2_CNTL_HI 0xf244 -#define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI 0xf248 -#define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI 0xf24c -#define GT64260_ENET_2_RX_DESC_ADDR_HI 0xf250 -#define GT64260_ENET_2_TX_DESC_ADDR_HI 0xf254 -#define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI 0xf258 - -#define GT64260_MPSC_0_CNTL_LO 0xf280 -#define GT64260_MPSC_0_CNTL_HI 0xf284 -#define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI 0xf288 -#define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI 0xf28c -#define GT64260_MPSC_0_RX_DESC_ADDR_HI 0xf290 -#define GT64260_MPSC_0_TX_DESC_ADDR_HI 0xf294 -#define GT64260_MPSC_1_CNTL_LO 0xf2c0 -#define GT64260_MPSC_1_CNTL_HI 0xf2c4 -#define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI 0xf2c8 -#define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI 0xf2cc -#define GT64260_MPSC_1_RX_DESC_ADDR_HI 0xf2d0 -#define GT64260_MPSC_1_TX_DESC_ADDR_HI 0xf2d4 - -#define GT64260_SER_INIT_PCI_ADDR_HI 0xf320 -#define GT64260_SER_INIT_LAST_DATA 0xf324 -#define GT64260_SER_INIT_CONTROL 0xf328 -#define GT64260_SER_INIT_STATUS 0xf32c - -#define GT64260_COMM_ARBITER_CNTL 0xf300 -#define GT64260_COMM_CONFIG 0xb40c -#define GT64260_COMM_XBAR_TO 0xf304 -#define GT64260_COMM_INTR_CAUSE 0xf310 -#define GT64260_COMM_INTR_MASK 0xf314 -#define GT64260_COMM_ERR_ADDR 0xf318 - - -/* - ***************************************************************************** - * - * Fast Ethernet Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_ENET_PHY_ADDR 0x2000 -#define GT64260_ENET_ESMIR 0x2010 - -#define GT64260_ENET_E0PCR 0x2400 -#define GT64260_ENET_E0PCXR 0x2408 -#define GT64260_ENET_E0PCMR 0x2410 -#define GT64260_ENET_E0PSR 0x2418 -#define GT64260_ENET_E0SPR 0x2420 -#define GT64260_ENET_E0HTPR 0x2428 -#define GT64260_ENET_E0FCSAL 0x2430 -#define GT64260_ENET_E0FCSAH 0x2438 -#define GT64260_ENET_E0SDCR 0x2440 -#define GT64260_ENET_E0SDCMR 0x2448 -#define GT64260_ENET_E0ICR 0x2450 -#define GT64260_ENET_E0IMR 0x2458 -#define GT64260_ENET_E0FRDP0 0x2480 -#define GT64260_ENET_E0FRDP1 0x2484 -#define GT64260_ENET_E0FRDP2 0x2488 -#define GT64260_ENET_E0FRDP3 0x248c -#define GT64260_ENET_E0CRDP0 0x24a0 -#define GT64260_ENET_E0CRDP1 0x24a4 -#define GT64260_ENET_E0CRDP2 0x24a8 -#define GT64260_ENET_E0CRDP3 0x24ac -#define GT64260_ENET_E0CTDP0 0x24e0 -#define GT64260_ENET_E0CTDP1 0x24e4 -#define GT64260_ENET_0_DSCP2P0L 0x2460 -#define GT64260_ENET_0_DSCP2P0H 0x2464 -#define GT64260_ENET_0_DSCP2P1L 0x2468 -#define GT64260_ENET_0_DSCP2P1H 0x246c -#define GT64260_ENET_0_VPT2P 0x2470 -#define GT64260_ENET_0_MIB_CTRS 0x2500 - -#define GT64260_ENET_E1PCR 0x2800 -#define GT64260_ENET_E1PCXR 0x2808 -#define GT64260_ENET_E1PCMR 0x2810 -#define GT64260_ENET_E1PSR 0x2818 -#define GT64260_ENET_E1SPR 0x2820 -#define GT64260_ENET_E1HTPR 0x2828 -#define GT64260_ENET_E1FCSAL 0x2830 -#define GT64260_ENET_E1FCSAH 0x2838 -#define GT64260_ENET_E1SDCR 0x2840 -#define GT64260_ENET_E1SDCMR 0x2848 -#define GT64260_ENET_E1ICR 0x2850 -#define GT64260_ENET_E1IMR 0x2858 -#define GT64260_ENET_E1FRDP0 0x2880 -#define GT64260_ENET_E1FRDP1 0x2884 -#define GT64260_ENET_E1FRDP2 0x2888 -#define GT64260_ENET_E1FRDP3 0x288c -#define GT64260_ENET_E1CRDP0 0x28a0 -#define GT64260_ENET_E1CRDP1 0x28a4 -#define GT64260_ENET_E1CRDP2 0x28a8 -#define GT64260_ENET_E1CRDP3 0x28ac -#define GT64260_ENET_E1CTDP0 0x28e0 -#define GT64260_ENET_E1CTDP1 0x28e4 -#define GT64260_ENET_1_DSCP2P0L 0x2860 -#define GT64260_ENET_1_DSCP2P0H 0x2864 -#define GT64260_ENET_1_DSCP2P1L 0x2868 -#define GT64260_ENET_1_DSCP2P1H 0x286c -#define GT64260_ENET_1_VPT2P 0x2870 -#define GT64260_ENET_1_MIB_CTRS 0x2900 - -#define GT64260_ENET_E2PCR 0x2c00 -#define GT64260_ENET_E2PCXR 0x2c08 -#define GT64260_ENET_E2PCMR 0x2c10 -#define GT64260_ENET_E2PSR 0x2c18 -#define GT64260_ENET_E2SPR 0x2c20 -#define GT64260_ENET_E2HTPR 0x2c28 -#define GT64260_ENET_E2FCSAL 0x2c30 -#define GT64260_ENET_E2FCSAH 0x2c38 -#define GT64260_ENET_E2SDCR 0x2c40 -#define GT64260_ENET_E2SDCMR 0x2c48 -#define GT64260_ENET_E2ICR 0x2c50 -#define GT64260_ENET_E2IMR 0x2c58 -#define GT64260_ENET_E2FRDP0 0x2c80 -#define GT64260_ENET_E2FRDP1 0x2c84 -#define GT64260_ENET_E2FRDP2 0x2c88 -#define GT64260_ENET_E2FRDP3 0x2c8c -#define GT64260_ENET_E2CRDP0 0x2ca0 -#define GT64260_ENET_E2CRDP1 0x2ca4 -#define GT64260_ENET_E2CRDP2 0x2ca8 -#define GT64260_ENET_E2CRDP3 0x2cac -#define GT64260_ENET_E2CTDP0 0x2ce0 -#define GT64260_ENET_E2CTDP1 0x2ce4 -#define GT64260_ENET_2_DSCP2P0L 0x2c60 -#define GT64260_ENET_2_DSCP2P0H 0x2c64 -#define GT64260_ENET_2_DSCP2P1L 0x2c68 -#define GT64260_ENET_2_DSCP2P1H 0x2c6c -#define GT64260_ENET_2_VPT2P 0x2c70 -#define GT64260_ENET_2_MIB_CTRS 0x2d00 - - -/* - ***************************************************************************** - * - * Multi-Protocol Serial Controller Interface Registers - * - ***************************************************************************** - */ - -/* Signal Routing */ -#define GT64260_MPSC_MRR 0xb400 -#define GT64260_MPSC_RCRR 0xb404 -#define GT64260_MPSC_TCRR 0xb408 - -/* Main Configuratino Registers */ -#define GT64260_MPSC_0_MMCRL 0x8000 -#define GT64260_MPSC_0_MMCRH 0x8004 -#define GT64260_MPSC_0_MPCR 0x8008 -#define GT64260_MPSC_0_CHR_1 0x800c -#define GT64260_MPSC_0_CHR_2 0x8010 -#define GT64260_MPSC_0_CHR_3 0x8014 -#define GT64260_MPSC_0_CHR_4 0x8018 -#define GT64260_MPSC_0_CHR_5 0x801c -#define GT64260_MPSC_0_CHR_6 0x8020 -#define GT64260_MPSC_0_CHR_7 0x8024 -#define GT64260_MPSC_0_CHR_8 0x8028 -#define GT64260_MPSC_0_CHR_9 0x802c -#define GT64260_MPSC_0_CHR_10 0x8030 -#define GT64260_MPSC_0_CHR_11 0x8034 - -#define GT64260_MPSC_1_MMCRL 0x9000 -#define GT64260_MPSC_1_MMCRH 0x9004 -#define GT64260_MPSC_1_MPCR 0x9008 -#define GT64260_MPSC_1_CHR_1 0x900c -#define GT64260_MPSC_1_CHR_2 0x9010 -#define GT64260_MPSC_1_CHR_3 0x9014 -#define GT64260_MPSC_1_CHR_4 0x9018 -#define GT64260_MPSC_1_CHR_5 0x901c -#define GT64260_MPSC_1_CHR_6 0x9020 -#define GT64260_MPSC_1_CHR_7 0x9024 -#define GT64260_MPSC_1_CHR_8 0x9028 -#define GT64260_MPSC_1_CHR_9 0x902c -#define GT64260_MPSC_1_CHR_10 0x9030 -#define GT64260_MPSC_1_CHR_11 0x9034 - -#define GT64260_MPSC_0_INTR_CAUSE 0xb804 -#define GT64260_MPSC_0_INTR_MASK 0xb884 -#define GT64260_MPSC_1_INTR_CAUSE 0xb80c -#define GT64260_MPSC_1_INTR_MASK 0xb88c - -#define GT64260_MPSC_UART_CR_TEV (1<<1) -#define GT64260_MPSC_UART_CR_TA (1<<7) -#define GT64260_MPSC_UART_CR_TTCS (1<<9) -#define GT64260_MPSC_UART_CR_REV (1<<17) -#define GT64260_MPSC_UART_CR_RA (1<<23) -#define GT64260_MPSC_UART_CR_CRD (1<<25) -#define GT64260_MPSC_UART_CR_EH (1<<31) - -#define GT64260_MPSC_UART_ESR_CTS (1<<0) -#define GT64260_MPSC_UART_ESR_CD (1<<1) -#define GT64260_MPSC_UART_ESR_TIDLE (1<<3) -#define GT64260_MPSC_UART_ESR_RHS (1<<5) -#define GT64260_MPSC_UART_ESR_RLS (1<<7) -#define GT64260_MPSC_UART_ESR_RLIDL (1<<11) - - -/* - ***************************************************************************** - * - * Serial DMA Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_SDMA_0_SDC 0x4000 -#define GT64260_SDMA_0_SDCM 0x4008 -#define GT64260_SDMA_0_RX_DESC 0x4800 -#define GT64260_SDMA_0_RX_BUF_PTR 0x4808 -#define GT64260_SDMA_0_SCRDP 0x4810 -#define GT64260_SDMA_0_TX_DESC 0x4c00 -#define GT64260_SDMA_0_SCTDP 0x4c10 -#define GT64260_SDMA_0_SFTDP 0x4c14 - -#define GT64260_SDMA_1_SDC 0x6000 -#define GT64260_SDMA_1_SDCM 0x6008 -#define GT64260_SDMA_1_RX_DESC 0x6800 -#define GT64260_SDMA_1_RX_BUF_PTR 0x6808 -#define GT64260_SDMA_1_SCRDP 0x6810 -#define GT64260_SDMA_1_TX_DESC 0x6c00 -#define GT64260_SDMA_1_SCTDP 0x6c10 -#define GT64260_SDMA_1_SFTDP 0x6c14 - -#define GT64260_SDMA_INTR_CAUSE 0xb800 -#define GT64260_SDMA_INTR_MASK 0xb880 - -#define GT64260_SDMA_DESC_CMDSTAT_PE (1<<0) -#define GT64260_SDMA_DESC_CMDSTAT_CDL (1<<1) -#define GT64260_SDMA_DESC_CMDSTAT_FR (1<<3) -#define GT64260_SDMA_DESC_CMDSTAT_OR (1<<6) -#define GT64260_SDMA_DESC_CMDSTAT_BR (1<<9) -#define GT64260_SDMA_DESC_CMDSTAT_MI (1<<10) -#define GT64260_SDMA_DESC_CMDSTAT_A (1<<11) -#define GT64260_SDMA_DESC_CMDSTAT_AM (1<<12) -#define GT64260_SDMA_DESC_CMDSTAT_CT (1<<13) -#define GT64260_SDMA_DESC_CMDSTAT_C (1<<14) -#define GT64260_SDMA_DESC_CMDSTAT_ES (1<<15) -#define GT64260_SDMA_DESC_CMDSTAT_L (1<<16) -#define GT64260_SDMA_DESC_CMDSTAT_F (1<<17) -#define GT64260_SDMA_DESC_CMDSTAT_P (1<<18) -#define GT64260_SDMA_DESC_CMDSTAT_EI (1<<23) -#define GT64260_SDMA_DESC_CMDSTAT_O (1<<31) - -#define GT64260_SDMA_SDC_RFT (1<<0) -#define GT64260_SDMA_SDC_SFM (1<<1) -#define GT64260_SDMA_SDC_BLMR (1<<6) -#define GT64260_SDMA_SDC_BLMT (1<<7) -#define GT64260_SDMA_SDC_POVR (1<<8) -#define GT64260_SDMA_SDC_RIFB (1<<9) - -#define GT64260_SDMA_SDCM_ERD (1<<7) -#define GT64260_SDMA_SDCM_AR (1<<15) -#define GT64260_SDMA_SDCM_STD (1<<16) -#define GT64260_SDMA_SDCM_TXD (1<<23) -#define GT64260_SDMA_SDCM_AT (1<<31) - -#define GT64260_SDMA_0_CAUSE_RXBUF (1<<0) -#define GT64260_SDMA_0_CAUSE_RXERR (1<<1) -#define GT64260_SDMA_0_CAUSE_TXBUF (1<<2) -#define GT64260_SDMA_0_CAUSE_TXEND (1<<3) -#define GT64260_SDMA_1_CAUSE_RXBUF (1<<8) -#define GT64260_SDMA_1_CAUSE_RXERR (1<<9) -#define GT64260_SDMA_1_CAUSE_TXBUF (1<<10) -#define GT64260_SDMA_1_CAUSE_TXEND (1<<11) - - -/* - ***************************************************************************** - * - * Baud Rate Generator Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_BRG_0_BCR 0xb200 -#define GT64260_BRG_0_BTR 0xb204 -#define GT64260_BRG_1_BCR 0xb208 -#define GT64260_BRG_1_BTR 0xb20c -#define GT64260_BRG_2_BCR 0xb210 -#define GT64260_BRG_2_BTR 0xb214 - -#define GT64260_BRG_INTR_CAUSE 0xb834 -#define GT64260_BRG_INTR_MASK 0xb8b4 - - -/* - ***************************************************************************** - * - * Watchdog Timer Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_WDT_WDC 0xb410 -#define GT64260_WDT_WDV 0xb414 - - -/* - ***************************************************************************** - * - * General Purpose Pins Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_GPP_IO_CNTL 0xf100 -#define GT64260_GPP_LEVEL_CNTL 0xf110 -#define GT64260_GPP_VALUE 0xf104 -#define GT64260_GPP_INTR_CAUSE 0xf108 -#define GT64260_GPP_INTR_MASK 0xf10c - - -/* - ***************************************************************************** - * - * Multi-Purpose Pins Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_MPP_CNTL_0 0xf000 -#define GT64260_MPP_CNTL_1 0xf004 -#define GT64260_MPP_CNTL_2 0xf008 -#define GT64260_MPP_CNTL_3 0xf00c -#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010 - - -/* - ***************************************************************************** - * - * I2C Controller Interface Registers - * - ***************************************************************************** - */ - -/* FIXME: fill in */ - - -/* - ***************************************************************************** - * - * Interrupt Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_IC_MAIN_CAUSE_LO 0x0c18 -#define GT64260_IC_MAIN_CAUSE_HI 0x0c68 -#define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c -#define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c -#define GT64260_IC_CPU_SELECT_CAUSE 0x0c70 -#define GT64260_IC_PCI_0_INTR_MASK_LO 0x0c24 -#define GT64260_IC_PCI_0_INTR_MASK_HI 0x0c64 -#define GT64260_IC_PCI_0_SELECT_CAUSE 0x0c74 -#define GT64260_IC_PCI_1_INTR_MASK_LO 0x0ca4 -#define GT64260_IC_PCI_1_INTR_MASK_HI 0x0ce4 -#define GT64260_IC_PCI_1_SELECT_CAUSE 0x0cf4 -#define GT64260_IC_CPU_INT_0_MASK 0x0e60 -#define GT64260_IC_CPU_INT_1_MASK 0x0e64 -#define GT64260_IC_CPU_INT_2_MASK 0x0e68 -#define GT64260_IC_CPU_INT_3_MASK 0x0e6c - - -#endif /* __ASMPPC_GT64260_DEFS_H */ diff --git a/include/asm-ppc/harrier.h b/include/asm-ppc/harrier.h deleted file mode 100644 index 7acd7fc126ec..000000000000 --- a/include/asm-ppc/harrier.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Definitions for Motorola MCG Harrier North Bridge & Memory controller - * - * Author: Dale Farnsworth - * dale.farnsworth@mvista.com - * - * Modified by: Randy Vinson - * rvinson@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASMPPC_HARRIER_H -#define __ASMPPC_HARRIER_H - -#include -#include - -struct pci_controller; -int harrier_init(struct pci_controller *hose, - uint ppc_reg_base, - ulong processor_pci_mem_start, - ulong processor_pci_mem_end, - ulong processor_pci_io_start, - ulong processor_pci_io_end, - ulong processor_mpic_base); - -unsigned long harrier_get_mem_size(uint smc_base); - -int harrier_mpic_init(unsigned int pci_mem_offset); - -void harrier_setup_nonmonarch(uint ppc_reg_base, - uint in0_size); -void harrier_release_eready(uint ppc_reg_base); - -void harrier_wait_eready(uint ppc_reg_base); - -#endif /* __ASMPPC_HARRIER_H */ diff --git a/include/asm-ppc/hawk.h b/include/asm-ppc/hawk.h deleted file mode 100644 index f347007d22af..000000000000 --- a/include/asm-ppc/hawk.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * include/asm-ppc/hawk.h - * - * Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * Modified by Randy Vinson (rvinson@mvista.com) - * - * 2001,2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __ASMPPC_HAWK_H -#define __ASMPPC_HAWK_H - -#include -#include - -extern int hawk_init(struct pci_controller *hose, - unsigned int ppc_reg_base, unsigned long processor_pci_mem_start, - unsigned long processor_pci_mem_end, - unsigned long processor_pci_io_start, - unsigned long processor_pci_io_end, - unsigned long processor_mpic_base); -extern unsigned long hawk_get_mem_size(unsigned int smc_base); -extern int hawk_mpic_init(unsigned int pci_mem_offset); - -#endif /* __ASMPPC_HAWK_H */ diff --git a/include/asm-ppc/hawk_defs.h b/include/asm-ppc/hawk_defs.h deleted file mode 100644 index 6d1d2baf648c..000000000000 --- a/include/asm-ppc/hawk_defs.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * include/asm-ppc/hawk_defs.h - * - * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * Modified by Randy Vinson (rvinson@mvista.com) - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __ASMPPC_HAWK_DEFS_H -#define __ASMPPC_HAWK_DEFS_H - -#include - -/* - * The Falcon/Raven and HAWK have 4 sets of registers: - * 1) PPC Registers which define the mappings from PPC bus to PCI bus, - * etc. - * 2) PCI Registers which define the mappings from PCI bus to PPC bus and the - * MPIC base address. - * 3) MPIC registers - * 4) System Memory Controller (SMC) registers. - */ - -#define HAWK_PCI_CONFIG_ADDR_OFF 0x00000cf8 -#define HAWK_PCI_CONFIG_DATA_OFF 0x00000cfc - -#define HAWK_MPIC_SIZE 0x00040000U -#define HAWK_SMC_SIZE 0x00001000U - -/* - * Define PPC register offsets. - */ -#define HAWK_PPC_XSADD0_OFF 0x40 -#define HAWK_PPC_XSOFF0_OFF 0x44 -#define HAWK_PPC_XSADD1_OFF 0x48 -#define HAWK_PPC_XSOFF1_OFF 0x4c -#define HAWK_PPC_XSADD2_OFF 0x50 -#define HAWK_PPC_XSOFF2_OFF 0x54 -#define HAWK_PPC_XSADD3_OFF 0x58 -#define HAWK_PPC_XSOFF3_OFF 0x5c - -/* - * Define PCI register offsets. - */ -#define HAWK_PCI_PSADD0_OFF 0x80 -#define HAWK_PCI_PSOFF0_OFF 0x84 -#define HAWK_PCI_PSADD1_OFF 0x88 -#define HAWK_PCI_PSOFF1_OFF 0x8c -#define HAWK_PCI_PSADD2_OFF 0x90 -#define HAWK_PCI_PSOFF2_OFF 0x94 -#define HAWK_PCI_PSADD3_OFF 0x98 -#define HAWK_PCI_PSOFF3_OFF 0x9c - -/* - * Define the System Memory Controller (SMC) register offsets. - */ -#define HAWK_SMC_RAM_A_SIZE_REG_OFF 0x10 -#define HAWK_SMC_RAM_B_SIZE_REG_OFF 0x11 -#define HAWK_SMC_RAM_C_SIZE_REG_OFF 0x12 -#define HAWK_SMC_RAM_D_SIZE_REG_OFF 0x13 -#define HAWK_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */ -#define HAWK_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */ -#define HAWK_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */ -#define HAWK_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */ - -#define FALCON_SMC_REG_COUNT 4 -#define HAWK_SMC_REG_COUNT 8 -#endif /* __ASMPPC_HAWK_DEFS_H */ diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h deleted file mode 100644 index f7b21ee302b4..000000000000 --- a/include/asm-ppc/highmem.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * highmem.h: virtual kernel memory mappings for high memory - * - * PowerPC version, stolen from the i386 version. - * - * Used in CONFIG_HIGHMEM systems for memory pages which - * are not addressable by direct kernel virtual addresses. - * - * Copyright (C) 1999 Gerhard Wichert, Siemens AG - * Gerhard.Wichert@pdb.siemens.de - * - * - * Redesigned the x86 32-bit VM architecture to deal with - * up to 16 Terrabyte physical memory. With current x86 CPUs - * we now support up to 64 Gigabytes physical RAM. - * - * Copyright (C) 1999 Ingo Molnar - */ - -#ifndef _ASM_HIGHMEM_H -#define _ASM_HIGHMEM_H - -#ifdef __KERNEL__ - -#include -#include -#include -#include -#include - -/* undef for production */ -#define HIGHMEM_DEBUG 1 - -extern pte_t *kmap_pte; -extern pgprot_t kmap_prot; -extern pte_t *pkmap_page_table; - -/* - * Right now we initialize only a single pte table. It can be extended - * easily, subsequent pte tables have to be allocated in one physical - * chunk of RAM. - */ -#define PKMAP_BASE CONFIG_HIGHMEM_START -#define LAST_PKMAP (1 << PTE_SHIFT) -#define LAST_PKMAP_MASK (LAST_PKMAP-1) -#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) -#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) - -#define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL) - -extern void *kmap_high(struct page *page); -extern void kunmap_high(struct page *page); - -static inline void *kmap(struct page *page) -{ - might_sleep(); - if (!PageHighMem(page)) - return page_address(page); - return kmap_high(page); -} - -static inline void kunmap(struct page *page) -{ - BUG_ON(in_interrupt()); - if (!PageHighMem(page)) - return; - kunmap_high(page); -} - -/* - * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap - * gives a more generic (and caching) interface. But kmap_atomic can - * be used in IRQ contexts, so in some (very limited) cases we need - * it. - */ -static inline void *kmap_atomic(struct page *page, enum km_type type) -{ - unsigned int idx; - unsigned long vaddr; - - /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ - pagefault_disable(); - if (!PageHighMem(page)) - return page_address(page); - - idx = type + KM_TYPE_NR*smp_processor_id(); - vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE; -#ifdef HIGHMEM_DEBUG - BUG_ON(!pte_none(*(kmap_pte+idx))); -#endif - set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot)); - flush_tlb_page(NULL, vaddr); - - return (void*) vaddr; -} - -static inline void kunmap_atomic(void *kvaddr, enum km_type type) -{ -#ifdef HIGHMEM_DEBUG - unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; - unsigned int idx = type + KM_TYPE_NR*smp_processor_id(); - - if (vaddr < KMAP_FIX_BEGIN) { // FIXME - pagefault_enable(); - return; - } - - BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE); - - /* - * force other mappings to Oops if they'll try to access - * this pte without first remap it - */ - pte_clear(&init_mm, vaddr, kmap_pte+idx); - flush_tlb_page(NULL, vaddr); -#endif - pagefault_enable(); -} - -static inline struct page *kmap_atomic_to_page(void *ptr) -{ - unsigned long idx, vaddr = (unsigned long) ptr; - - if (vaddr < KMAP_FIX_BEGIN) - return virt_to_page(ptr); - - idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT; - return pte_page(kmap_pte[idx]); -} - -#define flush_cache_kmaps() flush_cache_all() - -#endif /* __KERNEL__ */ - -#endif /* _ASM_HIGHMEM_H */ diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h deleted file mode 100644 index 1ad4eed07fbe..000000000000 --- a/include/asm-ppc/hydra.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions - * - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is based on the following documentation: - * - * Macintosh Technology in the Common Hardware Reference Platform - * Apple Computer, Inc. - * - * © Copyright 1995 Apple Computer, Inc. All rights reserved. - * - * It's available online from http://chrp.apple.com/MacTech.pdf. - * You can obtain paper copies of this book from computer bookstores or by - * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San - * Francisco, CA 94104. Reference ISBN 1-55860-393-X. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _ASMPPC_HYDRA_H -#define _ASMPPC_HYDRA_H - -#ifdef __KERNEL__ - -struct Hydra { - /* DBDMA Controller Register Space */ - char Pad1[0x30]; - u_int CachePD; - u_int IDs; - u_int Feature_Control; - char Pad2[0x7fc4]; - /* DBDMA Channel Register Space */ - char SCSI_DMA[0x100]; - char Pad3[0x300]; - char SCCA_Tx_DMA[0x100]; - char SCCA_Rx_DMA[0x100]; - char SCCB_Tx_DMA[0x100]; - char SCCB_Rx_DMA[0x100]; - char Pad4[0x7800]; - /* Device Register Space */ - char SCSI[0x1000]; - char ADB[0x1000]; - char SCC_Legacy[0x1000]; - char SCC[0x1000]; - char Pad9[0x2000]; - char VIA[0x2000]; - char Pad10[0x28000]; - char OpenPIC[0x40000]; -}; - -extern volatile struct Hydra __iomem *Hydra; - - - /* - * Feature Control Register - */ - -#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */ -#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */ -#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */ -#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */ -#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */ -#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */ -#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */ -#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */ -#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */ - - - /* - * OpenPIC Interrupt Sources - */ - -#define HYDRA_INT_SIO 0 -#define HYDRA_INT_SCSI_DMA 1 -#define HYDRA_INT_SCCA_TX_DMA 2 -#define HYDRA_INT_SCCA_RX_DMA 3 -#define HYDRA_INT_SCCB_TX_DMA 4 -#define HYDRA_INT_SCCB_RX_DMA 5 -#define HYDRA_INT_SCSI 6 -#define HYDRA_INT_SCCA 7 -#define HYDRA_INT_SCCB 8 -#define HYDRA_INT_VIA 9 -#define HYDRA_INT_ADB 10 -#define HYDRA_INT_ADB_NMI 11 -#define HYDRA_INT_EXT1 12 /* PCI IRQW */ -#define HYDRA_INT_EXT2 13 /* PCI IRQX */ -#define HYDRA_INT_EXT3 14 /* PCI IRQY */ -#define HYDRA_INT_EXT4 15 /* PCI IRQZ */ -#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */ -#define HYDRA_INT_EXT6 17 /* IDE Secondary */ -#define HYDRA_INT_EXT7 18 /* Power Off Request */ -#define HYDRA_INT_SPARE 19 - -extern int hydra_init(void); -extern void macio_adb_init(void); - -#endif /* __KERNEL__ */ - -#endif /* _ASMPPC_HYDRA_H */ diff --git a/include/asm-ppc/ibm403.h b/include/asm-ppc/ibm403.h deleted file mode 100644 index c9c5d539cfdb..000000000000 --- a/include/asm-ppc/ibm403.h +++ /dev/null @@ -1,478 +0,0 @@ -/* - * Authors: Armin Kuster and Tom Rini - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - - -#ifdef __KERNEL__ -#ifndef __ASM_IBM403_H__ -#define __ASM_IBM403_H__ - - -#if defined(CONFIG_403GCX) - -#define DCRN_BE_BASE 0x090 -#define DCRN_DMA0_BASE 0x0C0 -#define DCRN_DMA1_BASE 0x0C8 -#define DCRN_DMA2_BASE 0x0D0 -#define DCRN_DMA3_BASE 0x0D8 -#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ -#define DCRN_DMASR_BASE 0x0E0 - -#define DCRN_EXIER_BASE 0x042 -#define DCRN_EXISR_BASE 0x040 -#define DCRN_IOCR_BASE 0x0A0 - - -/* ------------------------------------------------------------------------- */ -#endif - - - -#ifdef DCRN_BE_BASE -#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ -#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register*/ -#endif -/* DCRN_BESR */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 - -#ifdef DCRN_CHCR_BASE -#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ -#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ -#endif -#define CHR1_CETE 0x00800000 /* CPU external timer enable */ -#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ - -#ifdef DCRN_CHPSR_BASE -#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ -#endif - -#ifdef DCRN_CIC_BASE -#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ -#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ -#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ -#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ -#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ -#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ -#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ -#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ -#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ -#endif - -#ifdef DCRN_CPMFR_BASE -#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ -#endif - -#ifndef CPM_AUD -#define CPM_AUD 0x00000000 -#endif -#ifndef CPM_BRG -#define CPM_BRG 0x00000000 -#endif -#ifndef CPM_CBS -#define CPM_CBS 0x00000000 -#endif -#ifndef CPM_CPU -#define CPM_CPU 0x00000000 -#endif -#ifndef CPM_DCP -#define CPM_DCP 0x00000000 -#endif -#ifndef CPM_DCRX -#define CPM_DCRX 0x00000000 -#endif -#ifndef CPM_DENC -#define CPM_DENC 0x00000000 -#endif -#ifndef CPM_DMA -#define CPM_DMA 0x00000000 -#endif -#ifndef CPM_DSCR -#define CPM_DSCR 0x00000000 -#endif -#ifndef CPM_EBC -#define CPM_EBC 0x00000000 -#endif -#ifndef CPM_EBIU -#define CPM_EBIU 0x00000000 -#endif -#ifndef CPM_EMAC_MM -#define CPM_EMAC_MM 0x00000000 -#endif -#ifndef CPM_EMAC_RM -#define CPM_EMAC_RM 0x00000000 -#endif -#ifndef CPM_EMAC_TM -#define CPM_EMAC_TM 0x00000000 -#endif -#ifndef CPM_GPIO0 -#define CPM_GPIO0 0x00000000 -#endif -#ifndef CPM_GPT -#define CPM_GPT 0x00000000 -#endif -#ifndef CPM_I1284 -#define CPM_I1284 0x00000000 -#endif -#ifndef CPM_IIC0 -#define CPM_IIC0 0x00000000 -#endif -#ifndef CPM_IIC1 -#define CPM_IIC1 0x00000000 -#endif -#ifndef CPM_MSI -#define CPM_MSI 0x00000000 -#endif -#ifndef CPM_PCI -#define CPM_PCI 0x00000000 -#endif -#ifndef CPM_PLB -#define CPM_PLB 0x00000000 -#endif -#ifndef CPM_SC0 -#define CPM_SC0 0x00000000 -#endif -#ifndef CPM_SC1 -#define CPM_SC1 0x00000000 -#endif -#ifndef CPM_SDRAM0 -#define CPM_SDRAM0 0x00000000 -#endif -#ifndef CPM_SDRAM1 -#define CPM_SDRAM1 0x00000000 -#endif -#ifndef CPM_TMRCLK -#define CPM_TMRCLK 0x00000000 -#endif -#ifndef CPM_UART0 -#define CPM_UART0 0x00000000 -#endif -#ifndef CPM_UART1 -#define CPM_UART1 0x00000000 -#endif -#ifndef CPM_UART2 -#define CPM_UART2 0x00000000 -#endif -#ifndef CPM_UIC -#define CPM_UIC 0x00000000 -#endif -#ifndef CPM_VID2 -#define CPM_VID2 0x00000000 -#endif -#ifndef CPM_XPT27 -#define CPM_XPT27 0x00000000 -#endif -#ifndef CPM_XPT54 -#define CPM_XPT54 0x00000000 -#endif - -#ifdef DCRN_CPMSR_BASE -#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ -#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ -#endif - -#ifdef DCRN_DCP0_BASE -#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) /* Decompression Controller Address */ -#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) /* Decompression Controller Data */ -#endif - -#ifdef DCRN_DCRX_BASE -#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ -#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ -#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ -#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ -#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ -#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ -#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ -#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ -#endif - -#ifdef DCRN_DMA0_BASE -#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control Register 0 */ -#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ -#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) /* DMA Destination Address Register 0 */ -#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Source Address Register 0 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) /* DMA Chained Count Register 0 */ -#endif - -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 0 */ -#endif -#endif - -#ifdef DCRN_DMA1_BASE -#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control Register 1 */ -#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ -#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) /* DMA Destination Address Register 1 */ -#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ - -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) /* DMA Chained Count Register 1 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 1 */ -#endif -#endif - -#ifdef DCRN_DMA2_BASE -#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ -#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ -#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ -#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ -#endif -#endif - -#ifdef DCRN_DMA3_BASE -#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ -#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ -#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ -#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ -#endif -#endif - -#ifdef DCRN_DMASR_BASE -#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ -/* don't know if these two registers always exist if scatter/gather exists */ -#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ -#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ -#endif -#endif - -#ifdef DCRN_EBC_BASE -#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ -#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ -#endif - -#ifdef DCRN_EXIER_BASE -#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ -#endif - -#ifdef DCRN_EBIMC_BASE -#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ -#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ -#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ -#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ -#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ -#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ -#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ -#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ -#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */ -#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */ -#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */ -#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */ -#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */ -#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */ -#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */ -#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */ -#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */ -#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */ -#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */ -#endif - -#ifdef DCRN_EXISR_BASE -#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ -#endif -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ - -#ifdef DCRN_IOCR_BASE -#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ -#endif -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 - -#ifdef DCRN_MAL_BASE -#define DCRN_MALCR (DCRN_MAL_BASE + 0x0) /* MAL Configuration */ -#define DCRN_MALDBR (DCRN_MAL_BASE + 0x3) /* Debug Register */ -#define DCRN_MALESR (DCRN_MAL_BASE + 0x1) /* Error Status */ -#define DCRN_MALIER (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */ -#define DCRN_MALTXCARR (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */ -#define DCRN_MALTXCASR (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */ -#define DCRN_MALTXDEIR (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */ -#define DCRN_MALTXEOBISR (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status */ -#define DCRN_MALRXCARR (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */ -#define DCRN_MALRXCASR (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */ -#define DCRN_MALRXDEIR (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */ -#define DCRN_MALRXEOBISR (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status */ -#define DCRN_MALRXCTP0R (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP0R (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP1R (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */ -#define DCRN_MALRCBS0 (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */ -#endif -/* DCRN_MALCR */ -#define MALCR_MMSR 0x80000000/* MAL Software reset */ -#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ -#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ -#define MALCR_PLBP_3 0x00C00000 /* highest */ -#define MALCR_GA 0x00200000 /* Guarded Active Bit */ -#define MALCR_OA 0x00100000 /* Ordered Active Bit */ -#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ -#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ -#define MALCR_PLBLT_2 0x00020000 -#define MALCR_PLBLT_3 0x00010000 -#define MALCR_PLBLT_4 0x00008000 -#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ -#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ -#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ -#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ -#define MALCR_LEA 0x00000002 /* Locked Error Active */ -#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ -/* DCRN_MALESR */ -#define MALESR_EVB 0x80000000 /* Error Valid Bit */ -#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ -#define MALESR_DE 0x00100000 /* Descriptor Error */ -#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ -#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ -#define MALESR_OSE 0x00020000 /* OPB Slave Error */ -#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ -#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ -#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ -#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ -#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ -#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ -/* DCRN_MALIER */ -#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ -#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ -#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ -#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ -#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ -/* DCRN_MALTXEOBISR */ -#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ -#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ - -#ifdef DCRN_OCM0_BASE -#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ -#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ -#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ -#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ -#endif - -#ifdef DCRN_PLB0_BASE -#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) -#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) -/* doesn't exist on stb03xxx? */ -#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) -#endif - -#ifdef DCRN_PLB1_BASE -#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) -#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) -/* doesn't exist on stb03xxx? */ -#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) -#endif - -#ifdef DCRN_PLLMR_BASE -#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ -#endif - -#ifdef DCRN_POB0_BASE -#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) -#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) -#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) -#endif - -#ifdef DCRN_SCCR_BASE -#define DCRN_SCCR (DCRN_SCCR_BASE + 0x0) -#endif - -#ifdef DCRN_SDRAM0_BASE -#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */ -#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */ -#endif - -#ifdef DCRN_UIC0_BASE -#define DCRN_UIC0_SR (DCRN_UIC0_BASE + 0x0) -#define DCRN_UIC0_ER (DCRN_UIC0_BASE + 0x2) -#define DCRN_UIC0_CR (DCRN_UIC0_BASE + 0x3) -#define DCRN_UIC0_PR (DCRN_UIC0_BASE + 0x4) -#define DCRN_UIC0_TR (DCRN_UIC0_BASE + 0x5) -#define DCRN_UIC0_MSR (DCRN_UIC0_BASE + 0x6) -#define DCRN_UIC0_VR (DCRN_UIC0_BASE + 0x7) -#define DCRN_UIC0_VCR (DCRN_UIC0_BASE + 0x8) -#endif - -#ifdef DCRN_UIC1_BASE -#define DCRN_UIC1_SR (DCRN_UIC1_BASE + 0x0) -#define DCRN_UIC1_SRS (DCRN_UIC1_BASE + 0x1) -#define DCRN_UIC1_ER (DCRN_UIC1_BASE + 0x2) -#define DCRN_UIC1_CR (DCRN_UIC1_BASE + 0x3) -#define DCRN_UIC1_PR (DCRN_UIC1_BASE + 0x4) -#define DCRN_UIC1_TR (DCRN_UIC1_BASE + 0x5) -#define DCRN_UIC1_MSR (DCRN_UIC1_BASE + 0x6) -#define DCRN_UIC1_VR (DCRN_UIC1_BASE + 0x7) -#define DCRN_UIC1_VCR (DCRN_UIC1_BASE + 0x8) -#endif - -#ifdef DCRN_SDRAM0_BASE -#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ -#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ -#endif - -#ifdef DCRN_OCM0_BASE -#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ -#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ -#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ -#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ -#endif - -#endif /* __ASM_IBM403_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm405.h b/include/asm-ppc/ibm405.h deleted file mode 100644 index 4e5be9e2c153..000000000000 --- a/include/asm-ppc/ibm405.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM405_H__ -#define __ASM_IBM405_H__ - -#ifdef DCRN_BE_BASE -#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ -#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */ -#endif -/* DCRN_BESR */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 - -/* Clock and power management shifts for emacs */ -#define IBM_CPM_EMMII 0 /* Shift value for MII */ -#define IBM_CPM_EMRX 1 /* Shift value for recv */ -#define IBM_CPM_EMTX 2 /* Shift value for MAC */ - -#ifdef DCRN_CHCR_BASE -#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ -#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ -#endif -#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ - -#ifdef DCRN_CHPSR_BASE -#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ -#endif - -#ifdef DCRN_CPMFR_BASE -#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ -#endif - -#ifdef DCRN_CPMSR_BASE -#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ -#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ -#endif - -#ifdef DCRN_DCP0_BASE -/* Decompression Controller Address */ -#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) -/* Decompression Controller Data */ -#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) -#else -#define DCRN_DCP0_CFGADDR 0x0 -#define DCRN_DCP0_CFGDATA 0x0 -#endif - -#ifdef DCRN_DMA0_BASE -/* DMA Channel Control Register 0 */ -#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) -#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ -/* DMA Destination Address Register 0 */ -#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) -/* DMA Source Address Register 0 */ -#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) -#ifdef DCRNCAP_DMA_CC -/* DMA Chained Count Register 0 */ -#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) -#endif -#ifdef DCRNCAP_DMA_SG -/* DMA Scatter/Gather Descriptor Addr 0 */ -#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) -#endif -#endif - -#ifdef DCRN_DMA1_BASE -/* DMA Channel Control Register 1 */ -#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) -#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ -/* DMA Destination Address Register 1 */ -#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) -/* DMA Source Address Register 1 */ -#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ -#ifdef DCRNCAP_DMA_CC -/* DMA Chained Count Register 1 */ -#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) -#endif -#ifdef DCRNCAP_DMA_SG -/* DMA Scatter/Gather Descriptor Addr 1 */ -#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) -#endif -#endif - -#ifdef DCRN_DMA2_BASE -#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ -#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ -#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ -#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ -#endif -#endif - -#ifdef DCRN_DMA3_BASE -#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ -#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ -#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ -#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ -#endif -#endif - -#ifdef DCRN_DMASR_BASE -#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ -/* don't know if these two registers always exist if scatter/gather exists */ -#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ -#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ -#endif -#endif - -#ifdef DCRN_EBC_BASE -#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ -#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ -#endif - -#ifdef DCRN_EXIER_BASE -#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ -#endif - -#ifdef DCRN_EXISR_BASE -#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ -#endif - -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ - -#ifdef DCRN_IOCR_BASE -#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ -#endif -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 - -#define DCRN_MALCR(base) (base + 0x0) /* MAL Configuration */ -#define DCRN_MALDBR(base) ((base) + 0x3) /* Debug Register */ -#define DCRN_MALESR(base) ((base) + 0x1) /* Error Status */ -#define DCRN_MALIER(base) ((base) + 0x2) /* Interrupt Enable */ -#define DCRN_MALTXCARR(base) ((base) + 0x5) /* TX Channed Active Reset Register */ -#define DCRN_MALTXCASR(base) ((base) + 0x4) /* TX Channel Active Set Register */ -#define DCRN_MALTXDEIR(base) ((base) + 0x7) /* Tx Descriptor Error Interrupt */ -#define DCRN_MALTXEOBISR(base) ((base) + 0x6) /* Tx End of Buffer Interrupt Status */ -#define DCRN_MALRXCARR(base) ((base) + 0x11) /* RX Channed Active Reset Register */ -#define DCRN_MALRXCASR(base) ((base) + 0x10) /* RX Channel Active Set Register */ -#define DCRN_MALRXDEIR(base) ((base) + 0x13) /* Rx Descriptor Error Interrupt */ -#define DCRN_MALRXEOBISR(base) ((base) + 0x12) /* Rx End of Buffer Interrupt Status */ -#define DCRN_MALRXCTP0R(base) ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */ -#define DCRN_MALRXCTP1R(base) ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */ -#define DCRN_MALTXCTP0R(base) ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP1R(base) ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */ -#define DCRN_MALTXCTP2R(base) ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */ -#define DCRN_MALTXCTP3R(base) ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */ -#define DCRN_MALRCBS0(base) ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */ -#define DCRN_MALRCBS1(base) ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */ - - /* DCRN_MALCR */ -#define MALCR_MMSR 0x80000000 /* MAL Software reset */ -#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ -#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ -#define MALCR_PLBP_3 0x00C00000 /* highest */ -#define MALCR_GA 0x00200000 /* Guarded Active Bit */ -#define MALCR_OA 0x00100000 /* Ordered Active Bit */ -#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ -#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ -#define MALCR_PLBLT_2 0x00020000 -#define MALCR_PLBLT_3 0x00010000 -#define MALCR_PLBLT_4 0x00008000 -#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ -#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ -#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ -#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ -#define MALCR_LEA 0x00000002 /* Locked Error Active */ -#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ -/* DCRN_MALESR */ -#define MALESR_EVB 0x80000000 /* Error Valid Bit */ -#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ -#define MALESR_DE 0x00100000 /* Descriptor Error */ -#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ -#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ -#define MALESR_OSE 0x00020000 /* OPB Slave Error */ -#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ -#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ -#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ -#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ -#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ -#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ -/* DCRN_MALIER */ -#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ -#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ -#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ -#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ -#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ -/* DCRN_MALTXEOBISR */ -#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ -#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ - -#ifdef DCRN_PLB0_BASE -#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) -#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) -/* doesn't exist on stb03xxx? */ -#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) -#endif - -#ifdef DCRN_PLB1_BASE -#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) -#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) -/* doesn't exist on stb03xxx? */ -#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) -#endif - -#ifdef DCRN_PLLMR_BASE -#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ -#endif - -#ifdef DCRN_POB0_BASE -#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) -#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) -#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) -#endif - -#define DCRN_UIC_SR(base) (base + 0x0) -#define DCRN_UIC_ER(base) (base + 0x2) -#define DCRN_UIC_CR(base) (base + 0x3) -#define DCRN_UIC_PR(base) (base + 0x4) -#define DCRN_UIC_TR(base) (base + 0x5) -#define DCRN_UIC_MSR(base) (base + 0x6) -#define DCRN_UIC_VR(base) (base + 0x7) -#define DCRN_UIC_VCR(base) (base + 0x8) - -#ifdef DCRN_SDRAM0_BASE -#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ -#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ -#endif - -#ifdef DCRN_OCM0_BASE -#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ -#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ -#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ -#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ -#endif - -#endif /* __ASM_IBM405_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h deleted file mode 100644 index 7818b54b6e37..000000000000 --- a/include/asm-ppc/ibm44x.h +++ /dev/null @@ -1,674 +0,0 @@ -/* - * include/asm-ppc/ibm44x.h - * - * PPC44x definitions - * - * Matt Porter - * - * Copyright 2002-2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM44x_H__ -#define __ASM_IBM44x_H__ - - -#ifndef NR_BOARD_IRQS -#define NR_BOARD_IRQS 0 -#endif - -#define _IO_BASE isa_io_base -#define _ISA_MEM_BASE isa_mem_base -#define PCI_DRAM_OFFSET pci_dram_offset - -/* TLB entry offset/size used for pinning kernel lowmem */ -#define PPC44x_PIN_SHIFT 28 -#define PPC_PIN_SIZE (1 << PPC44x_PIN_SHIFT) - -/* Lowest TLB slot consumed by the default pinned TLBs */ -#define PPC44x_LOW_SLOT 63 - -/* - * Least significant 32-bits and extended real page number (ERPN) of - * UART0 physical address location for early serial text debug - */ -#if defined(CONFIG_440SP) -#define UART0_PHYS_ERPN 1 -#define UART0_PHYS_IO_BASE 0xf0000200 -#elif defined(CONFIG_440SPE) -#define UART0_PHYS_ERPN 4 -#define UART0_PHYS_IO_BASE 0xf0000200 -#elif defined(CONFIG_440EP) -#define UART0_PHYS_IO_BASE 0xe0000000 -#else -#define UART0_PHYS_ERPN 1 -#define UART0_PHYS_IO_BASE 0x40000200 -#endif - -/* - * XXX This 36-bit trap stuff will move somewhere in syslib/ - * when we rework/abstract the PPC44x PCI-X handling -mdp - */ - -/* - * Standard 4GB "page" definitions - */ -#if defined(CONFIG_440SP) -#define PPC44x_IO_PAGE 0x0000000100000000ULL -#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL -#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE -#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL -#elif defined(CONFIG_440SPE) -#define PPC44x_IO_PAGE 0x0000000400000000ULL -#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL -#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE -#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL -#elif defined(CONFIG_440EP) -#define PPC44x_IO_PAGE 0x0000000000000000ULL -#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL -#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE -#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL -#else -#define PPC44x_IO_PAGE 0x0000000100000000ULL -#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL -#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE -#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL -#endif - -/* - * 36-bit trap ranges - */ -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define PPC44x_IO_LO 0xf0000000UL -#define PPC44x_IO_HI 0xf0000fffUL -#define PPC44x_PCI0CFG_LO 0x0ec00000UL -#define PPC44x_PCI0CFG_HI 0x0ec00007UL -#define PPC44x_PCI1CFG_LO 0x1ec00000UL -#define PPC44x_PCI1CFG_HI 0x1ec00007UL -#define PPC44x_PCI2CFG_LO 0x2ec00000UL -#define PPC44x_PCI2CFG_HI 0x2ec00007UL -#define PPC44x_PCIMEM_LO 0x80000000UL -#define PPC44x_PCIMEM_HI 0xdfffffffUL -#elif defined(CONFIG_440EP) -#define PPC44x_IO_LO 0xef500000UL -#define PPC44x_IO_HI 0xefffffffUL -#define PPC44x_PCI0CFG_LO 0xeec00000UL -#define PPC44x_PCI0CFG_HI 0xeecfffffUL -#define PPC44x_PCIMEM_LO 0xa0000000UL -#define PPC44x_PCIMEM_HI 0xdfffffffUL -#else -#define PPC44x_IO_LO 0x40000000UL -#define PPC44x_IO_HI 0x40000fffUL -#define PPC44x_PCI0CFG_LO 0x0ec00000UL -#define PPC44x_PCI0CFG_HI 0x0ec00007UL -#define PPC44x_PCIMEM_LO 0x80002000UL -#define PPC44x_PCIMEM_HI 0xffffffffUL -#endif - -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -#ifndef __ASSEMBLY__ - -/* - * DCRN definitions - */ - - -/* CPRs (440GX and 440SP/440SPe) */ -#define DCRN_CPR_CONFIG_ADDR 0xc -#define DCRN_CPR_CONFIG_DATA 0xd - -#define DCRN_CPR_CLKUPD 0x0020 -#define DCRN_CPR_PLLC 0x0040 -#define DCRN_CPR_PLLD 0x0060 -#define DCRN_CPR_PRIMAD 0x0080 -#define DCRN_CPR_PRIMBD 0x00a0 -#define DCRN_CPR_OPBD 0x00c0 -#define DCRN_CPR_PERD 0x00e0 -#define DCRN_CPR_MALD 0x0100 - -/* CPRs read/write helper macros */ -#define CPR_READ(offset) ({\ - mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ - mfdcr(DCRN_CPR_CONFIG_DATA);}) -#define CPR_WRITE(offset, data) ({\ - mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ - mtdcr(DCRN_CPR_CONFIG_DATA, data);}) - -/* SDRs (440GX and 440SP/440SPe) */ -#define DCRN_SDR_CONFIG_ADDR 0xe -#define DCRN_SDR_CONFIG_DATA 0xf -#define DCRN_SDR_PFC0 0x4100 -#define DCRN_SDR_PFC1 0x4101 -#define DCRN_SDR_PFC1_EPS 0x1c00000 -#define DCRN_SDR_PFC1_EPS_SHIFT 22 -#define DCRN_SDR_PFC1_RMII 0x02000000 -#define DCRN_SDR_MFR 0x4300 -#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ -#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ -#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ -#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */ -#define DCRN_SDR_MFR_T0TXFL 0x00080000 -#define DCRN_SDR_MFR_T0TXFH 0x00040000 -#define DCRN_SDR_MFR_T1TXFL 0x00020000 -#define DCRN_SDR_MFR_T1TXFH 0x00010000 -#define DCRN_SDR_MFR_E0TXFL 0x00008000 -#define DCRN_SDR_MFR_E0TXFH 0x00004000 -#define DCRN_SDR_MFR_E0RXFL 0x00002000 -#define DCRN_SDR_MFR_E0RXFH 0x00001000 -#define DCRN_SDR_MFR_E1TXFL 0x00000800 -#define DCRN_SDR_MFR_E1TXFH 0x00000400 -#define DCRN_SDR_MFR_E1RXFL 0x00000200 -#define DCRN_SDR_MFR_E1RXFH 0x00000100 -#define DCRN_SDR_MFR_E2TXFL 0x00000080 -#define DCRN_SDR_MFR_E2TXFH 0x00000040 -#define DCRN_SDR_MFR_E2RXFL 0x00000020 -#define DCRN_SDR_MFR_E2RXFH 0x00000010 -#define DCRN_SDR_MFR_E3TXFL 0x00000008 -#define DCRN_SDR_MFR_E3TXFH 0x00000004 -#define DCRN_SDR_MFR_E3RXFL 0x00000002 -#define DCRN_SDR_MFR_E3RXFH 0x00000001 -#define DCRN_SDR_UART0 0x0120 -#define DCRN_SDR_UART1 0x0121 - -#ifdef CONFIG_440EP -#define DCRN_SDR_UART2 0x0122 -#define DCRN_SDR_UART3 0x0123 -#define DCRN_SDR_CUST0 0x4000 -#endif - -/* SDR read/write helper macros */ -#define SDR_READ(offset) ({\ - mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ - mfdcr(DCRN_SDR_CONFIG_DATA);}) -#define SDR_WRITE(offset, data) ({\ - mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ - mtdcr(DCRN_SDR_CONFIG_DATA,data);}) - -/* DMA (excluding 440SP/440SPe) */ -#define DCRN_DMA0_BASE 0x100 -#define DCRN_DMA1_BASE 0x108 -#define DCRN_DMA2_BASE 0x110 -#define DCRN_DMA3_BASE 0x118 -#define DCRN_DMASR_BASE 0x120 -#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ -#define DCRN_MAL_BASE 0x180 - -#ifdef CONFIG_440EP -#define DCRN_DMA2P40_BASE 0x300 -#define DCRN_DMA2P41_BASE 0x308 -#define DCRN_DMA2P42_BASE 0x310 -#define DCRN_DMA2P43_BASE 0x318 -#define DCRN_DMA2P4SR_BASE 0x320 -#endif - -/* UIC */ -#define DCRN_UIC0_BASE 0xc0 -#define DCRN_UIC1_BASE 0xd0 -#define UIC0 DCRN_UIC0_BASE -#define UIC1 DCRN_UIC1_BASE - -#ifdef CONFIG_440SPE -#define DCRN_UIC2_BASE 0xe0 -#define DCRN_UIC3_BASE 0xf0 -#define UIC2 DCRN_UIC2_BASE -#define UIC3 DCRN_UIC3_BASE -#else -#define DCRN_UIC2_BASE 0x210 -#define DCRN_UICB_BASE 0x200 -#define UIC2 DCRN_UIC2_BASE -#define UICB DCRN_UICB_BASE -#endif - -#define DCRN_UIC_SR(base) (base + 0x0) -#define DCRN_UIC_ER(base) (base + 0x2) -#define DCRN_UIC_CR(base) (base + 0x3) -#define DCRN_UIC_PR(base) (base + 0x4) -#define DCRN_UIC_TR(base) (base + 0x5) -#define DCRN_UIC_MSR(base) (base + 0x6) -#define DCRN_UIC_VR(base) (base + 0x7) -#define DCRN_UIC_VCR(base) (base + 0x8) - -#define UIC0_UIC1NC 0x00000002 - -#ifdef CONFIG_440SPE -#define UIC0_UIC1NC 0x00000002 -#define UIC0_UIC2NC 0x00200000 -#define UIC0_UIC3NC 0x00008000 -#endif - -#define UICB_UIC0NC 0x40000000 -#define UICB_UIC1NC 0x10000000 -#define UICB_UIC2NC 0x04000000 - -/* 440 MAL DCRs */ -#define DCRN_MALCR(base) (base + 0x0) /* Configuration */ -#define DCRN_MALESR(base) (base + 0x1) /* Error Status */ -#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */ -#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */ -#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */ -#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */ -#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */ -#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */ -#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */ -#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */ -#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */ -#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */ -#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */ -#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */ -#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */ -#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */ -#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */ -#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */ - -/* Compatibility DCRN's */ -#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */ -#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */ -#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */ -#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */ -#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */ -#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */ -#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */ -#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */ - -#define MALCR_MMSR 0x80000000 /* MAL Software reset */ -#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ -#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ -#define MALCR_PLBP_3 0x00C00000 /* highest */ -#define MALCR_GA 0x00200000 /* Guarded Active Bit */ -#define MALCR_OA 0x00100000 /* Ordered Active Bit */ -#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ -#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ -#define MALCR_PLBLT_2 0x00020000 -#define MALCR_PLBLT_3 0x00010000 -#define MALCR_PLBLT_4 0x00008000 -#ifdef CONFIG_440GP -#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */ -#else -#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */ -#endif -#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ -#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ -#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ -#define MALCR_LEA 0x00000002 /* Locked Error Active */ -#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ -/* DCRN_MALESR */ -#define MALESR_EVB 0x80000000 /* Error Valid Bit */ -#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ -#define MALESR_DE 0x00100000 /* Descriptor Error */ -#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ -#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ -#define MALESR_OSE 0x00020000 /* OPB Slave Error */ -#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ -#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ -#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ -#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ -#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ -#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ -/* DCRN_MALIER */ -#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ -#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ -#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ -#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ -#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ -/* DCRN_MALTXEOBISR */ -#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ -#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -/* 440SP/440SPe PLB Arbiter DCRs */ -#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ -#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ - -#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */ -#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */ -#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */ -#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */ -#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */ - -#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */ -#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */ -#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */ -#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */ -#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */ -#else -/* 440GP/GX PLB Arbiter DCRs */ -#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */ -#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */ -#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */ -#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */ -#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */ -#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */ -#endif - -/* 440GP/GX PLB to OPB bridge DCRs */ -#define DCRN_POB0_BESR0 0x090 -#define DCRN_POB0_BESR1 0x094 -#define DCRN_POB0_BEARL 0x092 -#define DCRN_POB0_BEARH 0x093 - -/* 440GP/GX OPB to PLB bridge DCRs */ -#define DCRN_OPB0_BSTAT 0x0a9 -#define DCRN_OPB0_BEARL 0x0aa -#define DCRN_OPB0_BEARH 0x0ab - -/* 440GP Clock, PM, chip control */ -#define DCRN_CPC0_SR 0x0b0 -#define DCRN_CPC0_ER 0x0b1 -#define DCRN_CPC0_FR 0x0b2 -#define DCRN_CPC0_SYS0 0x0e0 -#define DCRN_CPC0_SYS1 0x0e1 -#define DCRN_CPC0_CUST0 0x0e2 -#define DCRN_CPC0_CUST1 0x0e3 -#define DCRN_CPC0_STRP0 0x0e4 -#define DCRN_CPC0_STRP1 0x0e5 -#define DCRN_CPC0_STRP2 0x0e6 -#define DCRN_CPC0_STRP3 0x0e7 -#define DCRN_CPC0_GPIO 0x0e8 -#define DCRN_CPC0_PLB 0x0e9 -#define DCRN_CPC0_CR1 0x0ea -#define DCRN_CPC0_CR0 0x0eb -#define DCRN_CPC0_MIRQ0 0x0ec -#define DCRN_CPC0_MIRQ1 0x0ed -#define DCRN_CPC0_JTAGID 0x0ef - -/* 440GP DMA controller DCRs */ -#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */ -#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */ -#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */ -#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */ -#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */ -#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */ -#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */ -#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */ - -#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */ -#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */ -#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */ -#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */ -#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */ -#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */ -#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */ -#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */ - -#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */ -#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */ -#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */ -#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */ -#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */ -#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */ -#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */ -#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */ - -#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */ -#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */ -#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */ -#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */ -#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */ -#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */ -#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */ -#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */ - -#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ -#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ -#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ -#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ - -/* 440GP/440GX SDRAM controller DCRs */ -#define DCRN_SDRAM0_CFGADDR 0x010 -#define DCRN_SDRAM0_CFGDATA 0x011 - -#define SDRAM0_B0CR 0x40 -#define SDRAM0_B1CR 0x44 -#define SDRAM0_B2CR 0x48 -#define SDRAM0_B3CR 0x4c - -#define SDRAM_CONFIG_BANK_ENABLE 0x00000001 -#define SDRAM_CONFIG_SIZE_MASK 0x000e0000 -#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17) -#define SDRAM_CONFIG_SIZE_8M 0x00000001 -#define SDRAM_CONFIG_SIZE_16M 0x00000002 -#define SDRAM_CONFIG_SIZE_32M 0x00000003 -#define SDRAM_CONFIG_SIZE_64M 0x00000004 -#define SDRAM_CONFIG_SIZE_128M 0x00000005 -#define SDRAM_CONFIG_SIZE_256M 0x00000006 -#define SDRAM_CONFIG_SIZE_512M 0x00000007 -#define PPC44x_MEM_SIZE_8M 0x00800000 -#define PPC44x_MEM_SIZE_16M 0x01000000 -#define PPC44x_MEM_SIZE_32M 0x02000000 -#define PPC44x_MEM_SIZE_64M 0x04000000 -#define PPC44x_MEM_SIZE_128M 0x08000000 -#define PPC44x_MEM_SIZE_256M 0x10000000 -#define PPC44x_MEM_SIZE_512M 0x20000000 -#define PPC44x_MEM_SIZE_1G 0x40000000 -#define PPC44x_MEM_SIZE_2G 0x80000000 - -/* 440SP/440SPe memory controller DCRs */ -#define DCRN_MQ0_BS0BAS 0x40 -#if defined(CONFIG_440SP) -#define MQ0_NUM_BANKS 2 -#elif defined(CONFIG_440SPE) -#define MQ0_NUM_BANKS 4 -#endif - -#define MQ0_CONFIG_SIZE_MASK 0x0000fff0 -#define MQ0_CONFIG_SIZE_8M 0x0000ffc0 -#define MQ0_CONFIG_SIZE_16M 0x0000ff80 -#define MQ0_CONFIG_SIZE_32M 0x0000ff00 -#define MQ0_CONFIG_SIZE_64M 0x0000fe00 -#define MQ0_CONFIG_SIZE_128M 0x0000fc00 -#define MQ0_CONFIG_SIZE_256M 0x0000f800 -#define MQ0_CONFIG_SIZE_512M 0x0000f000 -#define MQ0_CONFIG_SIZE_1G 0x0000e000 -#define MQ0_CONFIG_SIZE_2G 0x0000c000 -#define MQ0_CONFIG_SIZE_4G 0x00008000 - -/* Internal SRAM Controller 440GX/440SP/440SPe */ -#define DCRN_SRAM0_BASE 0x000 - -#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) -#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021) -#define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022) -#define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023) -#define SRAM_SBCR_BAS0 0x80000000 -#define SRAM_SBCR_BAS1 0x80010000 -#define SRAM_SBCR_BAS2 0x80020000 -#define SRAM_SBCR_BAS3 0x80030000 -#define SRAM_SBCR_BU_MASK 0x00000180 -#define SRAM_SBCR_BS_64KB 0x00000800 -#define SRAM_SBCR_BU_RO 0x00000080 -#define SRAM_SBCR_BU_RW 0x00000180 -#define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024) -#define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025) -#define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026) -#define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027) -#define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028) -#define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029) -#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) -#define SRAM_DPC_ENABLE 0x80000000 - -/* L2 Cache Controller 440GX/440SP/440SPe */ -#define DCRN_L2C0_CFG 0x030 -#define L2C_CFG_L2M 0x80000000 -#define L2C_CFG_ICU 0x40000000 -#define L2C_CFG_DCU 0x20000000 -#define L2C_CFG_DCW_MASK 0x1e000000 -#define L2C_CFG_TPC 0x01000000 -#define L2C_CFG_CPC 0x00800000 -#define L2C_CFG_FRAN 0x00200000 -#define L2C_CFG_SS_MASK 0x00180000 -#define L2C_CFG_SS_256 0x00000000 -#define L2C_CFG_CPIM 0x00040000 -#define L2C_CFG_TPIM 0x00020000 -#define L2C_CFG_LIM 0x00010000 -#define L2C_CFG_PMUX_MASK 0x00007000 -#define L2C_CFG_PMUX_SNP 0x00000000 -#define L2C_CFG_PMUX_IF 0x00001000 -#define L2C_CFG_PMUX_DF 0x00002000 -#define L2C_CFG_PMUX_DS 0x00003000 -#define L2C_CFG_PMIM 0x00000800 -#define L2C_CFG_TPEI 0x00000400 -#define L2C_CFG_CPEI 0x00000200 -#define L2C_CFG_NAM 0x00000100 -#define L2C_CFG_SMCM 0x00000080 -#define L2C_CFG_NBRM 0x00000040 -#define DCRN_L2C0_CMD 0x031 -#define L2C_CMD_CLR 0x80000000 -#define L2C_CMD_DIAG 0x40000000 -#define L2C_CMD_INV 0x20000000 -#define L2C_CMD_CCP 0x10000000 -#define L2C_CMD_CTE 0x08000000 -#define L2C_CMD_STRC 0x04000000 -#define L2C_CMD_STPC 0x02000000 -#define L2C_CMD_RPMC 0x01000000 -#define L2C_CMD_HCC 0x00800000 -#define DCRN_L2C0_ADDR 0x032 -#define DCRN_L2C0_DATA 0x033 -#define DCRN_L2C0_SR 0x034 -#define L2C_SR_CC 0x80000000 -#define L2C_SR_CPE 0x40000000 -#define L2C_SR_TPE 0x20000000 -#define L2C_SR_LRU 0x10000000 -#define L2C_SR_PCS 0x08000000 -#define DCRN_L2C0_REVID 0x035 -#define DCRN_L2C0_SNP0 0x036 -#define DCRN_L2C0_SNP1 0x037 -#define L2C_SNP_BA_MASK 0xffff0000 -#define L2C_SNP_SSR_MASK 0x0000f000 -#define L2C_SNP_SSR_32G 0x0000f000 -#define L2C_SNP_ESR 0x00000800 - -/* - * PCI-X definitions - */ -#define PCIX0_CFGA 0x0ec00000UL -#define PCIX1_CFGA 0x1ec00000UL -#define PCIX2_CFGA 0x2ec00000UL -#define PCIX0_CFGD 0x0ec00004UL -#define PCIX1_CFGD 0x1ec00004UL -#define PCIX2_CFGD 0x2ec00004UL - -#define PCIX0_IO_BASE 0x0000000908000000ULL -#define PCIX1_IO_BASE 0x0000000908000000ULL -#define PCIX2_IO_BASE 0x0000000908000000ULL -#define PCIX_IO_SIZE 0x00010000 - -#ifdef CONFIG_440SP -#define PCIX0_REG_BASE 0x000000090ec80000ULL -#else -#define PCIX0_REG_BASE 0x000000020ec80000ULL -#endif -#define PCIX_REG_OFFSET 0x10000000 -#define PCIX_REG_SIZE 0x200 - -#define PCIX0_VENDID 0x000 -#define PCIX0_DEVID 0x002 -#define PCIX0_COMMAND 0x004 -#define PCIX0_STATUS 0x006 -#define PCIX0_REVID 0x008 -#define PCIX0_CLS 0x009 -#define PCIX0_CACHELS 0x00c -#define PCIX0_LATTIM 0x00d -#define PCIX0_HDTYPE 0x00e -#define PCIX0_BIST 0x00f -#define PCIX0_BAR0L 0x010 -#define PCIX0_BAR0H 0x014 -#define PCIX0_BAR1 0x018 -#define PCIX0_BAR2L 0x01c -#define PCIX0_BAR2H 0x020 -#define PCIX0_BAR3 0x024 -#define PCIX0_CISPTR 0x028 -#define PCIX0_SBSYSVID 0x02c -#define PCIX0_SBSYSID 0x02e -#define PCIX0_EROMBA 0x030 -#define PCIX0_CAP 0x034 -#define PCIX0_RES0 0x035 -#define PCIX0_RES1 0x036 -#define PCIX0_RES2 0x038 -#define PCIX0_INTLN 0x03c -#define PCIX0_INTPN 0x03d -#define PCIX0_MINGNT 0x03e -#define PCIX0_MAXLTNCY 0x03f -#define PCIX0_BRDGOPT1 0x040 -#define PCIX0_BRDGOPT2 0x044 -#define PCIX0_ERREN 0x050 -#define PCIX0_ERRSTS 0x054 -#define PCIX0_PLBBESR 0x058 -#define PCIX0_PLBBEARL 0x05c -#define PCIX0_PLBBEARH 0x060 -#define PCIX0_POM0LAL 0x068 -#define PCIX0_POM0LAH 0x06c -#define PCIX0_POM0SA 0x070 -#define PCIX0_POM0PCIAL 0x074 -#define PCIX0_POM0PCIAH 0x078 -#define PCIX0_POM1LAL 0x07c -#define PCIX0_POM1LAH 0x080 -#define PCIX0_POM1SA 0x084 -#define PCIX0_POM1PCIAL 0x088 -#define PCIX0_POM1PCIAH 0x08c -#define PCIX0_POM2SA 0x090 -#define PCIX0_PIM0SAL 0x098 -#define PCIX0_PIM0SA PCIX0_PIM0SAL -#define PCIX0_PIM0LAL 0x09c -#define PCIX0_PIM0LAH 0x0a0 -#define PCIX0_PIM1SA 0x0a4 -#define PCIX0_PIM1LAL 0x0a8 -#define PCIX0_PIM1LAH 0x0ac -#define PCIX0_PIM2SAL 0x0b0 -#define PCIX0_PIM2SA PCIX0_PIM2SAL -#define PCIX0_PIM2LAL 0x0b4 -#define PCIX0_PIM2LAH 0x0b8 -#define PCIX0_OMCAPID 0x0c0 -#define PCIX0_OMNIPTR 0x0c1 -#define PCIX0_OMMC 0x0c2 -#define PCIX0_OMMA 0x0c4 -#define PCIX0_OMMUA 0x0c8 -#define PCIX0_OMMDATA 0x0cc -#define PCIX0_OMMEOI 0x0ce -#define PCIX0_PMCAPID 0x0d0 -#define PCIX0_PMNIPTR 0x0d1 -#define PCIX0_PMC 0x0d2 -#define PCIX0_PMCSR 0x0d4 -#define PCIX0_PMCSRBSE 0x0d6 -#define PCIX0_PMDATA 0x0d7 -#define PCIX0_PMSCRR 0x0d8 -#define PCIX0_CAPID 0x0dc -#define PCIX0_NIPTR 0x0dd -#define PCIX0_CMD 0x0de -#define PCIX0_STS 0x0e0 -#define PCIX0_IDR 0x0e4 -#define PCIX0_CID 0x0e8 -#define PCIX0_RID 0x0ec -#define PCIX0_PIM0SAH 0x0f8 -#define PCIX0_PIM2SAH 0x0fc -#define PCIX0_MSGIL 0x100 -#define PCIX0_MSGIH 0x104 -#define PCIX0_MSGOL 0x108 -#define PCIX0_MSGOH 0x10c -#define PCIX0_IM 0x1f8 - -#define IIC_OWN 0x55 -#define IIC_CLOCK 50 - -#undef NR_UICS -#if defined(CONFIG_440GX) -#define NR_UICS 3 -#elif defined(CONFIG_440SPE) -#define NR_UICS 4 -#else -#define NR_UICS 2 -#endif - -#include - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_IBM44x_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h deleted file mode 100644 index ed6891af05d3..000000000000 --- a/include/asm-ppc/ibm4xx.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * - * Copyright (c) 1999 Grant Erickson - * - * Module name: ibm4xx.h - * - * Description: - * A generic include file which pulls in appropriate include files - * for specific board types based on configuration settings. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM4XX_H__ -#define __ASM_IBM4XX_H__ - -#include -#include - -#ifdef CONFIG_40x - -#if defined(CONFIG_BUBINGA) -#include -#endif - -#if defined(CONFIG_CPCI405) -#include -#endif - -#if defined(CONFIG_EP405) -#include -#endif - -#if defined(CONFIG_REDWOOD_5) -#include -#endif - -#if defined(CONFIG_REDWOOD_6) -#include -#endif - -#if defined(CONFIG_SYCAMORE) -#include -#endif - -#if defined(CONFIG_WALNUT) -#include -#endif - -#if defined(CONFIG_XILINX_VIRTEX) -#include -#endif - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_40x -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern bd_t __res; -#endif - -void ppc4xx_setup_arch(void); -void ppc4xx_map_io(void); -void ppc4xx_init_IRQ(void); -void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7); -#endif - -#ifndef PPC4xx_MACHINE_NAME -#define PPC4xx_MACHINE_NAME "Unidentified 4xx class" -#endif - - -/* IO_BASE is for PCI I/O. - * ISA not supported, just here to resolve copilation. - */ - -#ifndef _IO_BASE -#define _IO_BASE 0xe8000000 /* The PCI address window */ -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 -#endif - -#elif defined(CONFIG_44x) - -#if defined(CONFIG_BAMBOO) -#include -#endif - -#if defined(CONFIG_EBONY) -#include -#endif - -#if defined(CONFIG_LUAN) -#include -#endif - -#if defined(CONFIG_YUCCA) -#include -#endif - -#if defined(CONFIG_OCOTEA) -#include -#endif - -#if defined(CONFIG_TAISHAN) -#include -#endif - -#ifndef __ASSEMBLY__ -#ifdef CONFIG_40x -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern bd_t __res; -#endif -#endif -#endif /* CONFIG_40x */ - -#endif /* __ASM_IBM4XX_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h deleted file mode 100644 index ddce616f765a..000000000000 --- a/include/asm-ppc/ibm_ocp.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * ibm_ocp.h - * - * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) - * Mipsys - France - * - * Derived from work (c) Armin Kuster akuster@pacbell.net - * - * Additional support and port to 2.6 LDM/sysfs by - * Matt Porter - * Copyright 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#ifdef __KERNEL__ -#ifndef __IBM_OCP_H__ -#define __IBM_OCP_H__ - -#include - -/* - * IBM 4xx OCP system information - */ -struct ocp_sys_info_data { - int opb_bus_freq; /* OPB Bus Frequency (Hz) */ - int ebc_bus_freq; /* EBC Bus Frequency (Hz) */ -}; - -extern struct ocp_sys_info_data ocp_sys_info; - -/* - * EMAC additional data and sysfs support - * - * Note about mdio_idx: When you have a zmii, it's usually - * not necessary, it covers the case of the 405EP which has - * the MDIO lines on EMAC0 only - * - * Note about phy_map: Per EMAC map of PHY ids which should - * be probed by emac_probe. Different EMACs can have - * overlapping maps. - * - * Note, this map uses inverse logic for bits: - * 0 - id should be probed - * 1 - id should be ignored - * - * Default value of 0x00000000 - will result in usual - * auto-detection logic. - * - */ - -struct ocp_func_emac_data { - int rgmii_idx; /* RGMII device index or -1 */ - int rgmii_mux; /* RGMII input of this EMAC */ - int zmii_idx; /* ZMII device index or -1 */ - int zmii_mux; /* ZMII input of this EMAC */ - int mal_idx; /* MAL device index */ - int mal_rx_chan; /* MAL rx channel number */ - int mal_tx_chan; /* MAL tx channel number */ - int wol_irq; /* WOL interrupt */ - int mdio_idx; /* EMAC idx of MDIO master or -1 */ - int tah_idx; /* TAH device index or -1 */ - int phy_mode; /* PHY type or configurable mode */ - u8 mac_addr[6]; /* EMAC mac address */ - u32 phy_map; /* EMAC phy map */ - u32 phy_feat_exc; /* Excluded PHY features */ -}; - -/* Sysfs support */ -#define OCP_SYSFS_EMAC_DATA() \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\ - \ -void ocp_show_emac_data(struct device *dev) \ -{ \ - device_create_file(dev, &dev_attr_emac_rgmii_idx); \ - device_create_file(dev, &dev_attr_emac_rgmii_mux); \ - device_create_file(dev, &dev_attr_emac_zmii_idx); \ - device_create_file(dev, &dev_attr_emac_zmii_mux); \ - device_create_file(dev, &dev_attr_emac_mal_idx); \ - device_create_file(dev, &dev_attr_emac_mal_rx_chan); \ - device_create_file(dev, &dev_attr_emac_mal_tx_chan); \ - device_create_file(dev, &dev_attr_emac_wol_irq); \ - device_create_file(dev, &dev_attr_emac_mdio_idx); \ - device_create_file(dev, &dev_attr_emac_tah_idx); \ - device_create_file(dev, &dev_attr_emac_phy_mode); \ - device_create_file(dev, &dev_attr_emac_phy_map); \ - device_create_file(dev, &dev_attr_emac_phy_feat_exc); \ -} - -/* - * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY) - */ -#define PHY_MODE_NA 0 -#define PHY_MODE_MII 1 -#define PHY_MODE_RMII 2 -#define PHY_MODE_SMII 3 -#define PHY_MODE_RGMII 4 -#define PHY_MODE_TBI 5 -#define PHY_MODE_GMII 6 -#define PHY_MODE_RTBI 7 -#define PHY_MODE_SGMII 8 - -#ifdef CONFIG_40x -/* - * Helper function to copy MAC addresses from the bd_t to OCP EMAC - * additions. - * - * The range of EMAC indices (inclusive) to be copied are the arguments. - */ -static inline void ibm_ocp_set_emac(int start, int end) -{ - int i; - struct ocp_def *def; - - /* Copy MAC addresses to EMAC additions */ - for (i=start; i<=end; i++) { - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); - if (i == 0) - memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, - __res.bi_enetaddr, 6); -#if defined(CONFIG_405EP) || defined(CONFIG_44x) - else if (i == 1) - memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, - __res.bi_enet1addr, 6); -#endif -#if defined(CONFIG_440GX) - else if (i == 2) - memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, - __res.bi_enet2addr, 6); - else if (i == 3) - memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, - __res.bi_enet3addr, 6); -#endif - } -} -#endif - -/* - * MAL additional data and sysfs support - */ -struct ocp_func_mal_data { - int num_tx_chans; /* Number of TX channels */ - int num_rx_chans; /* Number of RX channels */ - int txeob_irq; /* TX End Of Buffer IRQ */ - int rxeob_irq; /* RX End Of Buffer IRQ */ - int txde_irq; /* TX Descriptor Error IRQ */ - int rxde_irq; /* RX Descriptor Error IRQ */ - int serr_irq; /* MAL System Error IRQ */ - int dcr_base; /* MALx_CFG DCR number */ -}; - -#define OCP_SYSFS_MAL_DATA() \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \ - \ -void ocp_show_mal_data(struct device *dev) \ -{ \ - device_create_file(dev, &dev_attr_mal_num_tx_chans); \ - device_create_file(dev, &dev_attr_mal_num_rx_chans); \ - device_create_file(dev, &dev_attr_mal_txeob_irq); \ - device_create_file(dev, &dev_attr_mal_rxeob_irq); \ - device_create_file(dev, &dev_attr_mal_txde_irq); \ - device_create_file(dev, &dev_attr_mal_rxde_irq); \ - device_create_file(dev, &dev_attr_mal_serr_irq); \ - device_create_file(dev, &dev_attr_mal_dcr_base); \ -} - -/* - * IIC additional data and sysfs support - */ -struct ocp_func_iic_data { - int fast_mode; /* IIC fast mode enabled */ -}; - -#define OCP_SYSFS_IIC_DATA() \ -OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \ - \ -void ocp_show_iic_data(struct device *dev) \ -{ \ - device_create_file(dev, &dev_attr_iic_fast_mode); \ -} -#endif /* __IBM_OCP_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm_ocp_pci.h b/include/asm-ppc/ibm_ocp_pci.h deleted file mode 100644 index a81ab6144358..000000000000 --- a/include/asm-ppc/ibm_ocp_pci.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Author: Armin Kuster - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM_OCP_PCI_H__ -#define __ASM_IBM_OCP_PCI_H__ - -/* PCI 32 */ - -struct pmm_regs { - u32 la; - u32 ma; - u32 pcila; - u32 pciha; -}; - -typedef struct pcil0_regs { - struct pmm_regs pmm[3]; - u32 ptm1ms; - u32 ptm1la; - u32 ptm2ms; - u32 ptm2la; -} pci0_t; - -#endif /* __ASM_IBM_OCP_PCI_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/immap_cpm2.h b/include/asm-ppc/immap_cpm2.h deleted file mode 100644 index 3c23d9cb47a6..000000000000 --- a/include/asm-ppc/immap_cpm2.h +++ /dev/null @@ -1,648 +0,0 @@ -/* - * CPM2 Internal Memory Map - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * The Internal Memory Map for devices with CPM2 on them. This - * is the superset of all CPM2 devices (8260, 8266, 8280, 8272, - * 8560). - */ -#ifdef __KERNEL__ -#ifndef __IMMAP_CPM2__ -#define __IMMAP_CPM2__ - -/* System configuration registers. -*/ -typedef struct sys_82xx_conf { - u32 sc_siumcr; - u32 sc_sypcr; - u8 res1[6]; - u16 sc_swsr; - u8 res2[20]; - u32 sc_bcr; - u8 sc_ppc_acr; - u8 res3[3]; - u32 sc_ppc_alrh; - u32 sc_ppc_alrl; - u8 sc_lcl_acr; - u8 res4[3]; - u32 sc_lcl_alrh; - u32 sc_lcl_alrl; - u32 sc_tescr1; - u32 sc_tescr2; - u32 sc_ltescr1; - u32 sc_ltescr2; - u32 sc_pdtea; - u8 sc_pdtem; - u8 res5[3]; - u32 sc_ldtea; - u8 sc_ldtem; - u8 res6[163]; -} sysconf_82xx_cpm2_t; - -typedef struct sys_85xx_conf { - u32 sc_cear; - u16 sc_ceer; - u16 sc_cemr; - u8 res1[70]; - u32 sc_smaer; - u8 res2[4]; - u32 sc_smevr; - u32 sc_smctr; - u32 sc_lmaer; - u8 res3[4]; - u32 sc_lmevr; - u32 sc_lmctr; - u8 res4[144]; -} sysconf_85xx_cpm2_t; - -typedef union sys_conf { - sysconf_82xx_cpm2_t siu_82xx; - sysconf_85xx_cpm2_t siu_85xx; -} sysconf_cpm2_t; - - - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - u32 memc_br0; - u32 memc_or0; - u32 memc_br1; - u32 memc_or1; - u32 memc_br2; - u32 memc_or2; - u32 memc_br3; - u32 memc_or3; - u32 memc_br4; - u32 memc_or4; - u32 memc_br5; - u32 memc_or5; - u32 memc_br6; - u32 memc_or6; - u32 memc_br7; - u32 memc_or7; - u32 memc_br8; - u32 memc_or8; - u32 memc_br9; - u32 memc_or9; - u32 memc_br10; - u32 memc_or10; - u32 memc_br11; - u32 memc_or11; - u8 res1[8]; - u32 memc_mar; - u8 res2[4]; - u32 memc_mamr; - u32 memc_mbmr; - u32 memc_mcmr; - u8 res3[8]; - u16 memc_mptpr; - u8 res4[2]; - u32 memc_mdr; - u8 res5[4]; - u32 memc_psdmr; - u32 memc_lsdmr; - u8 memc_purt; - u8 res6[3]; - u8 memc_psrt; - u8 res7[3]; - u8 memc_lurt; - u8 res8[3]; - u8 memc_lsrt; - u8 res9[3]; - u32 memc_immr; - u32 memc_pcibr0; - u32 memc_pcibr1; - u8 res10[16]; - u32 memc_pcimsk0; - u32 memc_pcimsk1; - u8 res11[52]; -} memctl_cpm2_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - u8 res1[32]; - u16 sit_tmcntsc; - u8 res2[2]; - u32 sit_tmcnt; - u8 res3[4]; - u32 sit_tmcntal; - u8 res4[16]; - u16 sit_piscr; - u8 res5[2]; - u32 sit_pitc; - u32 sit_pitr; - u8 res6[94]; - u8 res7[390]; -} sit_cpm2_t; - -#define PISCR_PIRQ_MASK ((u16)0xff00) -#define PISCR_PS ((u16)0x0080) -#define PISCR_PIE ((u16)0x0004) -#define PISCR_PTF ((u16)0x0002) -#define PISCR_PTE ((u16)0x0001) - -/* PCI Controller. -*/ -typedef struct pci_ctlr { - u32 pci_omisr; - u32 pci_omimr; - u8 res1[8]; - u32 pci_ifqpr; - u32 pci_ofqpr; - u8 res2[8]; - u32 pci_imr0; - u32 pci_imr1; - u32 pci_omr0; - u32 pci_omr1; - u32 pci_odr; - u8 res3[4]; - u32 pci_idr; - u8 res4[20]; - u32 pci_imisr; - u32 pci_imimr; - u8 res5[24]; - u32 pci_ifhpr; - u8 res6[4]; - u32 pci_iftpr; - u8 res7[4]; - u32 pci_iphpr; - u8 res8[4]; - u32 pci_iptpr; - u8 res9[4]; - u32 pci_ofhpr; - u8 res10[4]; - u32 pci_oftpr; - u8 res11[4]; - u32 pci_ophpr; - u8 res12[4]; - u32 pci_optpr; - u8 res13[8]; - u32 pci_mucr; - u8 res14[8]; - u32 pci_qbar; - u8 res15[12]; - u32 pci_dmamr0; - u32 pci_dmasr0; - u32 pci_dmacdar0; - u8 res16[4]; - u32 pci_dmasar0; - u8 res17[4]; - u32 pci_dmadar0; - u8 res18[4]; - u32 pci_dmabcr0; - u32 pci_dmandar0; - u8 res19[86]; - u32 pci_dmamr1; - u32 pci_dmasr1; - u32 pci_dmacdar1; - u8 res20[4]; - u32 pci_dmasar1; - u8 res21[4]; - u32 pci_dmadar1; - u8 res22[4]; - u32 pci_dmabcr1; - u32 pci_dmandar1; - u8 res23[88]; - u32 pci_dmamr2; - u32 pci_dmasr2; - u32 pci_dmacdar2; - u8 res24[4]; - u32 pci_dmasar2; - u8 res25[4]; - u32 pci_dmadar2; - u8 res26[4]; - u32 pci_dmabcr2; - u32 pci_dmandar2; - u8 res27[88]; - u32 pci_dmamr3; - u32 pci_dmasr3; - u32 pci_dmacdar3; - u8 res28[4]; - u32 pci_dmasar3; - u8 res29[4]; - u32 pci_dmadar3; - u8 res30[4]; - u32 pci_dmabcr3; - u32 pci_dmandar3; - u8 res31[344]; - u32 pci_potar0; - u8 res32[4]; - u32 pci_pobar0; - u8 res33[4]; - u32 pci_pocmr0; - u8 res34[4]; - u32 pci_potar1; - u8 res35[4]; - u32 pci_pobar1; - u8 res36[4]; - u32 pci_pocmr1; - u8 res37[4]; - u32 pci_potar2; - u8 res38[4]; - u32 pci_pobar2; - u8 res39[4]; - u32 pci_pocmr2; - u8 res40[50]; - u32 pci_ptcr; - u32 pci_gpcr; - u32 pci_gcr; - u32 pci_esr; - u32 pci_emr; - u32 pci_ecr; - u32 pci_eacr; - u8 res41[4]; - u32 pci_edcr; - u8 res42[4]; - u32 pci_eccr; - u8 res43[44]; - u32 pci_pitar1; - u8 res44[4]; - u32 pci_pibar1; - u8 res45[4]; - u32 pci_picmr1; - u8 res46[4]; - u32 pci_pitar0; - u8 res47[4]; - u32 pci_pibar0; - u8 res48[4]; - u32 pci_picmr0; - u8 res49[4]; - u32 pci_cfg_addr; - u32 pci_cfg_data; - u32 pci_int_ack; - u8 res50[756]; -} pci_cpm2_t; - -/* Interrupt Controller. -*/ -typedef struct interrupt_controller { - u16 ic_sicr; - u8 res1[2]; - u32 ic_sivec; - u32 ic_sipnrh; - u32 ic_sipnrl; - u32 ic_siprr; - u32 ic_scprrh; - u32 ic_scprrl; - u32 ic_simrh; - u32 ic_simrl; - u32 ic_siexr; - u8 res2[88]; -} intctl_cpm2_t; - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - u32 car_sccr; - u8 res1[4]; - u32 car_scmr; - u8 res2[4]; - u32 car_rsr; - u32 car_rmr; - u8 res[104]; -} car_cpm2_t; - -/* Input/Output Port control/status registers. - * Names consistent with processor manual, although they are different - * from the original 8xx names....... - */ -typedef struct io_port { - u32 iop_pdira; - u32 iop_ppara; - u32 iop_psora; - u32 iop_podra; - u32 iop_pdata; - u8 res1[12]; - u32 iop_pdirb; - u32 iop_pparb; - u32 iop_psorb; - u32 iop_podrb; - u32 iop_pdatb; - u8 res2[12]; - u32 iop_pdirc; - u32 iop_pparc; - u32 iop_psorc; - u32 iop_podrc; - u32 iop_pdatc; - u8 res3[12]; - u32 iop_pdird; - u32 iop_ppard; - u32 iop_psord; - u32 iop_podrd; - u32 iop_pdatd; - u8 res4[12]; -} iop_cpm2_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - u8 cpmt_tgcr1; - u8 res1[3]; - u8 cpmt_tgcr2; - u8 res2[11]; - u16 cpmt_tmr1; - u16 cpmt_tmr2; - u16 cpmt_trr1; - u16 cpmt_trr2; - u16 cpmt_tcr1; - u16 cpmt_tcr2; - u16 cpmt_tcn1; - u16 cpmt_tcn2; - u16 cpmt_tmr3; - u16 cpmt_tmr4; - u16 cpmt_trr3; - u16 cpmt_trr4; - u16 cpmt_tcr3; - u16 cpmt_tcr4; - u16 cpmt_tcn3; - u16 cpmt_tcn4; - u16 cpmt_ter1; - u16 cpmt_ter2; - u16 cpmt_ter3; - u16 cpmt_ter4; - u8 res3[584]; -} cpmtimer_cpm2_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - u8 res0[24]; - u8 sdma_sdsr; - u8 res1[3]; - u8 sdma_sdmr; - u8 res2[3]; - u8 sdma_idsr1; - u8 res3[3]; - u8 sdma_idmr1; - u8 res4[3]; - u8 sdma_idsr2; - u8 res5[3]; - u8 sdma_idmr2; - u8 res6[3]; - u8 sdma_idsr3; - u8 res7[3]; - u8 sdma_idmr3; - u8 res8[3]; - u8 sdma_idsr4; - u8 res9[3]; - u8 sdma_idmr4; - u8 res10[707]; -} sdma_cpm2_t; - -/* Fast controllers -*/ -typedef struct fcc { - u32 fcc_gfmr; - u32 fcc_fpsmr; - u16 fcc_ftodr; - u8 res1[2]; - u16 fcc_fdsr; - u8 res2[2]; - u16 fcc_fcce; - u8 res3[2]; - u16 fcc_fccm; - u8 res4[2]; - u8 fcc_fccs; - u8 res5[3]; - u8 fcc_ftirr_phy[4]; -} fcc_t; - -/* Fast controllers continued - */ -typedef struct fcc_c { - u32 fcc_firper; - u32 fcc_firer; - u32 fcc_firsr_hi; - u32 fcc_firsr_lo; - u8 fcc_gfemr; - u8 res1[15]; -} fcc_c_t; - -/* TC Layer - */ -typedef struct tclayer { - u16 tc_tcmode; - u16 tc_cdsmr; - u16 tc_tcer; - u16 tc_rcc; - u16 tc_tcmr; - u16 tc_fcc; - u16 tc_ccc; - u16 tc_icc; - u16 tc_tcc; - u16 tc_ecc; - u8 res1[12]; -} tclayer_t; - - -/* I2C -*/ -typedef struct i2c { - u8 i2c_i2mod; - u8 res1[3]; - u8 i2c_i2add; - u8 res2[3]; - u8 i2c_i2brg; - u8 res3[3]; - u8 i2c_i2com; - u8 res4[3]; - u8 i2c_i2cer; - u8 res5[3]; - u8 i2c_i2cmr; - u8 res6[331]; -} i2c_cpm2_t; - -typedef struct scc { /* Serial communication channels */ - u32 scc_gsmrl; - u32 scc_gsmrh; - u16 scc_psmr; - u8 res1[2]; - u16 scc_todr; - u16 scc_dsr; - u16 scc_scce; - u8 res2[2]; - u16 scc_sccm; - u8 res3; - u8 scc_sccs; - u8 res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - u8 res1[2]; - u16 smc_smcmr; - u8 res2[2]; - u8 smc_smce; - u8 res3[3]; - u8 smc_smcm; - u8 res4[5]; -} smc_t; - -/* Serial Peripheral Interface. -*/ -typedef struct spi_ctrl { - u16 spi_spmode; - u8 res1[4]; - u8 spi_spie; - u8 res2[3]; - u8 spi_spim; - u8 res3[2]; - u8 spi_spcom; - u8 res4[82]; -} spictl_cpm2_t; - -/* CPM Mux. -*/ -typedef struct cpmux { - u8 cmx_si1cr; - u8 res1; - u8 cmx_si2cr; - u8 res2; - u32 cmx_fcr; - u32 cmx_scr; - u8 cmx_smr; - u8 res3; - u16 cmx_uar; - u8 res4[16]; -} cpmux_t; - -/* SIRAM control -*/ -typedef struct siram { - u16 si_amr; - u16 si_bmr; - u16 si_cmr; - u16 si_dmr; - u8 si_gmr; - u8 res1; - u8 si_cmdr; - u8 res2; - u8 si_str; - u8 res3; - u16 si_rsr; -} siramctl_t; - -typedef struct mcc { - u16 mcc_mcce; - u8 res1[2]; - u16 mcc_mccm; - u8 res2[2]; - u8 mcc_mccf; - u8 res3[7]; -} mcc_t; - -typedef struct comm_proc { - u32 cp_cpcr; - u32 cp_rccr; - u8 res1[14]; - u16 cp_rter; - u8 res2[2]; - u16 cp_rtmr; - u16 cp_rtscr; - u8 res3[2]; - u32 cp_rtsr; - u8 res4[12]; -} cpm_cpm2_t; - -/* USB Controller. -*/ -typedef struct usb_ctlr { - u8 usb_usmod; - u8 usb_usadr; - u8 usb_uscom; - u8 res1[1]; - u16 usb_usep1; - u16 usb_usep2; - u16 usb_usep3; - u16 usb_usep4; - u8 res2[4]; - u16 usb_usber; - u8 res3[2]; - u16 usb_usbmr; - u8 usb_usbs; - u8 res4[7]; -} usb_cpm2_t; - -/* ...and the whole thing wrapped up.... -*/ - -typedef struct immap { - /* Some references are into the unique and known dpram spaces, - * others are from the generic base. - */ -#define im_dprambase im_dpram1 - u8 im_dpram1[16*1024]; - u8 res1[16*1024]; - u8 im_dpram2[4*1024]; - u8 res2[8*1024]; - u8 im_dpram3[4*1024]; - u8 res3[16*1024]; - - sysconf_cpm2_t im_siu_conf; /* SIU Configuration */ - memctl_cpm2_t im_memctl; /* Memory Controller */ - sit_cpm2_t im_sit; /* System Integration Timers */ - pci_cpm2_t im_pci; /* PCI Controller */ - intctl_cpm2_t im_intctl; /* Interrupt Controller */ - car_cpm2_t im_clkrst; /* Clocks and reset */ - iop_cpm2_t im_ioport; /* IO Port control/status */ - cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */ - sdma_cpm2_t im_sdma; /* SDMA control/status */ - - fcc_t im_fcc[3]; /* Three FCCs */ - u8 res4z[32]; - fcc_c_t im_fcc_c[3]; /* Continued FCCs */ - - u8 res4[32]; - - tclayer_t im_tclayer[8]; /* Eight TCLayers */ - u16 tc_tcgsr; - u16 tc_tcger; - - /* First set of baud rate generators. - */ - u8 res[236]; - u32 im_brgc5; - u32 im_brgc6; - u32 im_brgc7; - u32 im_brgc8; - - u8 res5[608]; - - i2c_cpm2_t im_i2c; /* I2C control/status */ - cpm_cpm2_t im_cpm; /* Communication processor */ - - /* Second set of baud rate generators. - */ - u32 im_brgc1; - u32 im_brgc2; - u32 im_brgc3; - u32 im_brgc4; - - scc_t im_scc[4]; /* Four SCCs */ - smc_t im_smc[2]; /* Couple of SMCs */ - spictl_cpm2_t im_spi; /* A SPI */ - cpmux_t im_cpmux; /* CPM clock route mux */ - siramctl_t im_siramctl1; /* First SI RAM Control */ - mcc_t im_mcc1; /* First MCC */ - siramctl_t im_siramctl2; /* Second SI RAM Control */ - mcc_t im_mcc2; /* Second MCC */ - usb_cpm2_t im_usb; /* USB Controller */ - - u8 res6[1153]; - - u16 im_si1txram[256]; - u8 res7[512]; - u16 im_si1rxram[256]; - u8 res8[512]; - u16 im_si2txram[256]; - u8 res9[512]; - u16 im_si2rxram[256]; - u8 res10[512]; - u8 res11[4096]; -} cpm2_map_t; - -extern cpm2_map_t *cpm2_immr; - -#endif /* __IMMAP_CPM2__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h deleted file mode 100644 index a0d409a5d80f..000000000000 --- a/include/asm-ppc/io.h +++ /dev/null @@ -1,502 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_IO_H -#define _PPC_IO_H - -#include -#include - -#include -#include -#include -#include - -#define SIO_CONFIG_RA 0x398 -#define SIO_CONFIG_RD 0x399 - -#define SLOW_DOWN_IO - -#define PMAC_ISA_MEM_BASE 0 -#define PMAC_PCI_DRAM_OFFSET 0 -#define CHRP_ISA_IO_BASE 0xf8000000 -#define CHRP_ISA_MEM_BASE 0xf7000000 -#define CHRP_PCI_DRAM_OFFSET 0 -#define PREP_ISA_IO_BASE 0x80000000 -#define PREP_ISA_MEM_BASE 0xc0000000 -#define PREP_PCI_DRAM_OFFSET 0x80000000 - -#if defined(CONFIG_4xx) -#include -#elif defined(CONFIG_8xx) -#include -#elif defined(CONFIG_8260) -#include -#elif !defined(CONFIG_PCI) -#define _IO_BASE 0 -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 -#else /* Everyone else */ -#define _IO_BASE isa_io_base -#define _ISA_MEM_BASE isa_mem_base -#define PCI_DRAM_OFFSET pci_dram_offset -#endif /* Platform-dependent I/O */ - -#define ___IO_BASE ((void __iomem *)_IO_BASE) -extern unsigned long isa_io_base; -extern unsigned long isa_mem_base; -extern unsigned long pci_dram_offset; - -/* - * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - * - * Read operations have additional twi & isync to make sure the read - * is actually performed (i.e. the data has come back) before we start - * executing any following instructions. - */ -extern inline int in_8(const volatile unsigned char __iomem *addr) -{ - int ret; - - __asm__ __volatile__( - "sync; lbz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_8(volatile unsigned char __iomem *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -extern inline int in_le16(const volatile unsigned short __iomem *addr) -{ - int ret; - - __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline int in_be16(const volatile unsigned short __iomem *addr) -{ - int ret; - - __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le16(volatile unsigned short __iomem *addr, int val) -{ - __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be16(volatile unsigned short __iomem *addr, int val) -{ - __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); -} - -extern inline unsigned in_le32(const volatile unsigned __iomem *addr) -{ - unsigned ret; - - __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline unsigned in_be32(const volatile unsigned __iomem *addr) -{ - unsigned ret; - - __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le32(volatile unsigned __iomem *addr, int val) -{ - __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be32(volatile unsigned __iomem *addr, int val) -{ - __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); -} -#if defined (CONFIG_8260_PCI9) -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) -#else -static inline __u8 readb(const volatile void __iomem *addr) -{ - return in_8(addr); -} -static inline void writeb(__u8 b, volatile void __iomem *addr) -{ - out_8(addr, b); -} -#endif - -#if defined (CONFIG_8260_PCI9) -/* Use macros if PCI9 workaround enabled */ -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) -#else -static inline __u16 readw(const volatile void __iomem *addr) -{ - return in_le16(addr); -} -static inline __u32 readl(const volatile void __iomem *addr) -{ - return in_le32(addr); -} -static inline void writew(__u16 b, volatile void __iomem *addr) -{ - out_le16(addr, b); -} -static inline void writel(__u32 b, volatile void __iomem *addr) -{ - out_le32(addr, b); -} -#endif /* CONFIG_8260_PCI9 */ - -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) - -static inline __u8 __raw_readb(const volatile void __iomem *addr) -{ - return *(__force volatile __u8 *)(addr); -} -static inline __u16 __raw_readw(const volatile void __iomem *addr) -{ - return *(__force volatile __u16 *)(addr); -} -static inline __u32 __raw_readl(const volatile void __iomem *addr) -{ - return *(__force volatile __u32 *)(addr); -} -static inline void __raw_writeb(__u8 b, volatile void __iomem *addr) -{ - *(__force volatile __u8 *)(addr) = b; -} -static inline void __raw_writew(__u16 b, volatile void __iomem *addr) -{ - *(__force volatile __u16 *)(addr) = b; -} -static inline void __raw_writel(__u32 b, volatile void __iomem *addr) -{ - *(__force volatile __u32 *)(addr) = b; -} - -#define mmiowb() - -/* - * The insw/outsw/insl/outsl macros don't do byte-swapping. - * They are only used in practice for transferring buffers which - * are arrays of bytes, and byte-swapping is not appropriate in - * that case. - paulus - */ -#define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns)) -#define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl)) - -#define readsb(a, b, n) _insb((a), (b), (n)) -#define readsw(a, b, n) _insw_ns((a), (b), (n)) -#define readsl(a, b, n) _insl_ns((a), (b), (n)) -#define writesb(a, b, n) _outsb((a),(b),(n)) -#define writesw(a, b, n) _outsw_ns((a),(b),(n)) -#define writesl(a, b, n) _outsl_ns((a),(b),(n)) - - -/* - * On powermacs and 8xx we will get a machine check exception - * if we try to read data from a non-existent I/O port. Because - * the machine check is an asynchronous exception, it isn't - * well-defined which instruction SRR0 will point to when the - * exception occurs. - * With the sequence below (twi; isync; nop), we have found that - * the machine check occurs on one of the three instructions on - * all PPC implementations tested so far. The twi and isync are - * needed on the 601 (in fact twi; sync works too), the isync and - * nop are needed on 604[e|r], and any of twi, sync or isync will - * work on 603[e], 750, 74xx. - * The twi creates an explicit data dependency on the returned - * value which seems to be needed to make the 601 wait for the - * load to finish. - */ - -#define __do_in_asm(name, op) \ -extern __inline__ unsigned int name(unsigned int port) \ -{ \ - unsigned int x; \ - __asm__ __volatile__( \ - "sync\n" \ - "0:" op " %0,0,%1\n" \ - "1: twi 0,%0,0\n" \ - "2: isync\n" \ - "3: nop\n" \ - "4:\n" \ - ".section .fixup,\"ax\"\n" \ - "5: li %0,-1\n" \ - " b 4b\n" \ - ".previous\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 0b,5b\n" \ - " .long 1b,5b\n" \ - " .long 2b,5b\n" \ - " .long 3b,5b\n" \ - ".previous" \ - : "=&r" (x) \ - : "r" (port + ___IO_BASE)); \ - return x; \ -} - -#define __do_out_asm(name, op) \ -extern __inline__ void name(unsigned int val, unsigned int port) \ -{ \ - __asm__ __volatile__( \ - "sync\n" \ - "0:" op " %0,0,%1\n" \ - "1: sync\n" \ - "2:\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 0b,2b\n" \ - " .long 1b,2b\n" \ - ".previous" \ - : : "r" (val), "r" (port + ___IO_BASE)); \ -} - -__do_out_asm(outb, "stbx") -#if defined (CONFIG_8260_PCI9) -/* in asm cannot be defined if PCI9 workaround is used */ -#define inb(port) in_8((port)+___IO_BASE) -#define inw(port) in_le16((port)+___IO_BASE) -#define inl(port) in_le32((port)+___IO_BASE) -__do_out_asm(outw, "sthbrx") -__do_out_asm(outl, "stwbrx") -#else -__do_in_asm(inb, "lbzx") -__do_in_asm(inw, "lhbrx") -__do_in_asm(inl, "lwbrx") -__do_out_asm(outw, "sthbrx") -__do_out_asm(outl, "stwbrx") - -#endif - -#define inb_p(port) inb((port)) -#define outb_p(val, port) outb((val), (port)) -#define inw_p(port) inw((port)) -#define outw_p(val, port) outw((val), (port)) -#define inl_p(port) inl((port)) -#define outl_p(val, port) outl((val), (port)) - -extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); -extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); -extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); -extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); -extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); -extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); - - -#define IO_SPACE_LIMIT ~0 - -#if defined (CONFIG_8260_PCI9) -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) -#else -static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) -{ - memset((void __force *)addr, val, count); -} -static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count) -{ - memcpy(dst, (void __force *) src, count); -} -static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) -{ - memcpy((void __force *) dst, src, count); -} -#endif - -/* - * Map in an area of physical address space, for accessing - * I/O devices etc. - */ -extern void __iomem *__ioremap(phys_addr_t address, unsigned long size, - unsigned long flags); -extern void __iomem *ioremap(phys_addr_t address, unsigned long size); -#ifdef CONFIG_44x -extern void __iomem *ioremap64(unsigned long long address, unsigned long size); -#endif -#define ioremap_nocache(addr, size) ioremap((addr), (size)) -extern void iounmap(volatile void __iomem *addr); -extern unsigned long iopa(unsigned long addr); -extern void io_block_mapping(unsigned long virt, phys_addr_t phys, - unsigned int size, int flags); - -/* - * The PCI bus is inherently Little-Endian. The PowerPC is being - * run Big-Endian. Thus all values which cross the [PCI] barrier - * must be endian-adjusted. Also, the local DRAM has a different - * address from the PCI point of view, thus buffer addresses also - * have to be modified [mapped] appropriately. - */ -extern inline unsigned long virt_to_bus(volatile void * address) -{ - if (address == (void *)0) - return 0; - return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET; -} - -extern inline void * bus_to_virt(unsigned long address) -{ - if (address == 0) - return NULL; - return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE); -} - -/* - * Change virtual addresses to physical addresses and vv, for - * addresses in the area where the kernel has the RAM mapped. - */ -extern inline unsigned long virt_to_phys(volatile void * address) -{ - return (unsigned long) address - KERNELBASE; -} - -extern inline void * phys_to_virt(unsigned long address) -{ - return (void *) (address + KERNELBASE); -} - -/* - * Change "struct page" to physical address. - */ -#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) -#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) - -/* Enforce in-order execution of data I/O. - * No distinction between read/write on PPC; use eieio for all three. - */ -#define iobarrier_rw() eieio() -#define iobarrier_r() eieio() -#define iobarrier_w() eieio() - -/* - * Here comes the ppc implementation of the IOMAP - * interfaces. - */ -static inline unsigned int ioread8(void __iomem *addr) -{ - return readb(addr); -} - -static inline unsigned int ioread16(void __iomem *addr) -{ - return readw(addr); -} - -static inline unsigned int ioread32(void __iomem *addr) -{ - return readl(addr); -} - -static inline void iowrite8(u8 val, void __iomem *addr) -{ - writeb(val, addr); -} - -static inline void iowrite16(u16 val, void __iomem *addr) -{ - writew(val, addr); -} - -static inline void iowrite32(u32 val, void __iomem *addr) -{ - writel(val, addr); -} - -static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count) -{ - _insb(addr, dst, count); -} - -static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count) -{ - _insw_ns(addr, dst, count); -} - -static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count) -{ - _insl_ns(addr, dst, count); -} - -static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count) -{ - _outsb(addr, src, count); -} - -static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count) -{ - _outsw_ns(addr, src, count); -} - -static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count) -{ - _outsl_ns(addr, src, count); -} - -/* Create a virtual mapping cookie for an IO port range */ -extern void __iomem *ioport_map(unsigned long port, unsigned int nr); -extern void ioport_unmap(void __iomem *); - -/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ -struct pci_dev; -extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); -extern void pci_iounmap(struct pci_dev *dev, void __iomem *); - -#endif /* _PPC_IO_H */ - -#ifdef CONFIG_8260_PCI9 -#include -#endif - -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) - -/* - * Convert a virtual cached pointer to an uncached pointer - */ -#define xlate_dev_kmem_ptr(p) p - -/* access ports */ -#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) -#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) - -#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) -#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) - -#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) -#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) - -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/irq_regs.h b/include/asm-ppc/irq_regs.h deleted file mode 100644 index 3dd9c0b70270..000000000000 --- a/include/asm-ppc/irq_regs.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-ppc/kdebug.h b/include/asm-ppc/kdebug.h deleted file mode 100644 index 6ece1b037665..000000000000 --- a/include/asm-ppc/kdebug.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-ppc/kgdb.h b/include/asm-ppc/kgdb.h deleted file mode 100644 index b617dac82969..000000000000 --- a/include/asm-ppc/kgdb.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * kgdb.h: Defines and declarations for serial line source level - * remote debugging of the Linux kernel using gdb. - * - * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu) - * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - */ -#ifdef __KERNEL__ -#ifndef _PPC_KGDB_H -#define _PPC_KGDB_H - -#ifndef __ASSEMBLY__ - -/* Things specific to the gen550 backend. */ -struct uart_port; - -extern void gen550_progress(char *, unsigned short); -extern void gen550_kgdb_map_scc(void); -extern void gen550_init(int, struct uart_port *); - -/* Things specific to the pmac backend. */ -extern void zs_kgdb_hook(int tty_num); - -/* To init the kgdb engine. (called by serial hook)*/ -extern void set_debug_traps(void); - -/* To enter the debugger explicitly. */ -extern void breakpoint(void); - -/* For taking exceptions - * these are defined in traps.c - */ -extern int (*debugger)(struct pt_regs *regs); -extern int (*debugger_bpt)(struct pt_regs *regs); -extern int (*debugger_sstep)(struct pt_regs *regs); -extern int (*debugger_iabr_match)(struct pt_regs *regs); -extern int (*debugger_dabr_match)(struct pt_regs *regs); -extern void (*debugger_fault_handler)(struct pt_regs *regs); - -/* What we bring to the party */ -int kgdb_bpt(struct pt_regs *regs); -int kgdb_sstep(struct pt_regs *regs); -void kgdb(struct pt_regs *regs); -int kgdb_iabr_match(struct pt_regs *regs); -int kgdb_dabr_match(struct pt_regs *regs); - -/* - * external low-level support routines (ie macserial.c) - */ -extern void kgdb_interruptible(int); /* control interrupts from serial */ -extern void putDebugChar(char); /* write a single character */ -extern char getDebugChar(void); /* read and return a single char */ - -#endif /* !(__ASSEMBLY__) */ -#endif /* !(_PPC_KGDB_H) */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h deleted file mode 100644 index bf9e05dd54b5..000000000000 --- a/include/asm-ppc/m8260_pci.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * include/asm-ppc/m8260_pci.h - * - * Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __M8260_PCI_H -#define __M8260_PCI_H - -#include - -/* - * Define the vendor/device ID for the MPC8265. - */ -#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA) -#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA) - -#define M8265_PCIBR0 0x101ac -#define M8265_PCIBR1 0x101b0 -#define M8265_PCIMSK0 0x101c4 -#define M8265_PCIMSK1 0x101c8 - -/* Bit definitions for PCIBR registers */ - -#define PCIBR_ENABLE 0x00000001 - -/* Bit definitions for PCIMSK registers */ - -#define PCIMSK_32KiB 0xFFFF8000 /* Size of window, smallest */ -#define PCIMSK_64KiB 0xFFFF0000 -#define PCIMSK_128KiB 0xFFFE0000 -#define PCIMSK_256KiB 0xFFFC0000 -#define PCIMSK_512KiB 0xFFF80000 -#define PCIMSK_1MiB 0xFFF00000 -#define PCIMSK_2MiB 0xFFE00000 -#define PCIMSK_4MiB 0xFFC00000 -#define PCIMSK_8MiB 0xFF800000 -#define PCIMSK_16MiB 0xFF000000 -#define PCIMSK_32MiB 0xFE000000 -#define PCIMSK_64MiB 0xFC000000 -#define PCIMSK_128MiB 0xF8000000 -#define PCIMSK_256MiB 0xF0000000 -#define PCIMSK_512MiB 0xE0000000 -#define PCIMSK_1GiB 0xC0000000 /* Size of window, largest */ - - -#define M826X_SCCR_PCI_MODE_EN 0x100 - - -/* - * Outbound ATU registers (3 sets). These registers control how 60x bus (local) - * addresses are translated to PCI addresses when the MPC826x is a PCI bus - * master (initiator). - */ - -#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ -#define POTAR_REG1 0x10818 -#define POTAR_REG2 0x10830 - -#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ -#define POBAR_REG1 0x10820 -#define POBAR_REG2 0x10838 - -#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ -#define POCMR_REG1 0x10828 -#define POCMR_REG2 0x10840 - -/* Bit definitions for POMCR registers */ - -#define POCMR_MASK_4KiB 0x000FFFFF -#define POCMR_MASK_8KiB 0x000FFFFE -#define POCMR_MASK_16KiB 0x000FFFFC -#define POCMR_MASK_32KiB 0x000FFFF8 -#define POCMR_MASK_64KiB 0x000FFFF0 -#define POCMR_MASK_128KiB 0x000FFFE0 -#define POCMR_MASK_256KiB 0x000FFFC0 -#define POCMR_MASK_512KiB 0x000FFF80 -#define POCMR_MASK_1MiB 0x000FFF00 -#define POCMR_MASK_2MiB 0x000FFE00 -#define POCMR_MASK_4MiB 0x000FFC00 -#define POCMR_MASK_8MiB 0x000FF800 -#define POCMR_MASK_16MiB 0x000FF000 -#define POCMR_MASK_32MiB 0x000FE000 -#define POCMR_MASK_64MiB 0x000FC000 -#define POCMR_MASK_128MiB 0x000F8000 -#define POCMR_MASK_256MiB 0x000F0000 -#define POCMR_MASK_512MiB 0x000E0000 -#define POCMR_MASK_1GiB 0x000C0000 - -#define POCMR_ENABLE 0x80000000 -#define POCMR_PCI_IO 0x40000000 -#define POCMR_PREFETCH_EN 0x20000000 - -/* Soft PCI reset */ - -#define PCI_GCR_REG 0x10880 - -/* Bit definitions for PCI_GCR registers */ - -#define PCIGCR_PCI_BUS_EN 0x1 - -#define PCI_EMR_REG 0x10888 -/* - * Inbound ATU registers (2 sets). These registers control how PCI addresses - * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. - */ - -#define PITAR_REG1 0x108D0 -#define PIBAR_REG1 0x108D8 -#define PICMR_REG1 0x108E0 -#define PITAR_REG0 0x108E8 -#define PIBAR_REG0 0x108F0 -#define PICMR_REG0 0x108F8 - -/* Bit definitions for PCI Inbound Comparison Mask registers */ - -#define PICMR_MASK_4KiB 0x000FFFFF -#define PICMR_MASK_8KiB 0x000FFFFE -#define PICMR_MASK_16KiB 0x000FFFFC -#define PICMR_MASK_32KiB 0x000FFFF8 -#define PICMR_MASK_64KiB 0x000FFFF0 -#define PICMR_MASK_128KiB 0x000FFFE0 -#define PICMR_MASK_256KiB 0x000FFFC0 -#define PICMR_MASK_512KiB 0x000FFF80 -#define PICMR_MASK_1MiB 0x000FFF00 -#define PICMR_MASK_2MiB 0x000FFE00 -#define PICMR_MASK_4MiB 0x000FFC00 -#define PICMR_MASK_8MiB 0x000FF800 -#define PICMR_MASK_16MiB 0x000FF000 -#define PICMR_MASK_32MiB 0x000FE000 -#define PICMR_MASK_64MiB 0x000FC000 -#define PICMR_MASK_128MiB 0x000F8000 -#define PICMR_MASK_256MiB 0x000F0000 -#define PICMR_MASK_512MiB 0x000E0000 -#define PICMR_MASK_1GiB 0x000C0000 - -#define PICMR_ENABLE 0x80000000 -#define PICMR_NO_SNOOP_EN 0x40000000 -#define PICMR_PREFETCH_EN 0x20000000 - -/* PCI error Registers */ - -#define PCI_ERROR_STATUS_REG 0x10884 -#define PCI_ERROR_MASK_REG 0x10888 -#define PCI_ERROR_CONTROL_REG 0x1088C -#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 -#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 -#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 - -/* PCI error Register bit defines */ - -#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 -#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 -#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 -#define PCI_ERROR_PCI_NO_RSP 0x00000008 -#define PCI_ERROR_PCI_TAR_ABT 0x00000010 -#define PCI_ERROR_PCI_SERR 0x00000020 -#define PCI_ERROR_PCI_PERR_RD 0x00000040 -#define PCI_ERROR_PCI_PERR_WR 0x00000080 -#define PCI_ERROR_I2O_OFQO 0x00000100 -#define PCI_ERROR_I2O_IPQO 0x00000200 -#define PCI_ERROR_IRA 0x00000400 -#define PCI_ERROR_NMI 0x00000800 -#define PCI_ERROR_I2O_DBMC 0x00001000 - -/* - * Register pair used to generate configuration cycles on the PCI bus - * and access the MPC826x's own PCI configuration registers. - */ - -#define PCI_CFG_ADDR_REG 0x10900 -#define PCI_CFG_DATA_REG 0x10904 - -/* Bus parking decides where the bus control sits when idle */ -/* If modifying memory controllers for PCI park on the core */ - -#define PPC_ACR_BUS_PARK_CORE 0x6 -#define PPC_ACR_BUS_PARK_PCI 0x3 - -#endif /* __M8260_PCI_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h deleted file mode 100644 index a20b499b0186..000000000000 --- a/include/asm-ppc/machdep.h +++ /dev/null @@ -1,178 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_MACHDEP_H -#define _PPC_MACHDEP_H - -#include -#include - -#include -#include - -struct pt_regs; -struct pci_bus; -struct pci_dev; -struct seq_file; -struct file; - -/* - * This is for compatibility with ARCH=powerpc. - */ -#define machine_is(x) __MACHINE_IS_##x -#define __MACHINE_IS_powermac 0 -#define __MACHINE_IS_chrp 0 -#ifdef CONFIG_PPC_PREP -#define __MACHINE_IS_prep 1 -#else -#define __MACHINE_IS_prep 0 -#endif - -/* We export this macro for external modules like Alsa to know if - * ppc_md.feature_call is implemented or not - */ -#define CONFIG_PPC_HAS_FEATURE_CALLS - -struct machdep_calls { - void (*setup_arch)(void); - /* Optional, may be NULL. */ - int (*show_cpuinfo)(struct seq_file *m); - int (*show_percpuinfo)(struct seq_file *m, int i); - /* Optional, may be NULL. */ - unsigned int (*irq_canonicalize)(unsigned int irq); - void (*init_IRQ)(void); - int (*get_irq)(void); - - /* A general init function, called by ppc_init in init/main.c. - May be NULL. DEPRECATED ! */ - void (*init)(void); - /* For compatibility with merged platforms */ - void (*init_early)(void); - - void (*restart)(char *cmd); - void (*power_off)(void); - void (*halt)(void); - - void (*idle_loop)(void); - void (*power_save)(void); - - long (*time_init)(void); /* Optional, may be NULL */ - int (*set_rtc_time)(unsigned long nowtime); - unsigned long (*get_rtc_time)(void); - unsigned char (*rtc_read_val)(int addr); - void (*rtc_write_val)(int addr, unsigned char val); - void (*calibrate_decr)(void); - - void (*heartbeat)(void); - unsigned long heartbeat_reset; - unsigned long heartbeat_count; - - unsigned long (*find_end_of_memory)(void); - void (*setup_io_mappings)(void); - - void (*early_serial_map)(void); - void (*progress)(char *, unsigned short); - void (*kgdb_map_scc)(void); - - unsigned char (*nvram_read_val)(int addr); - void (*nvram_write_val)(int addr, unsigned char val); - void (*nvram_sync)(void); - - /* - * optional PCI "hooks" - */ - - /* Called after scanning the bus, before allocating resources */ - void (*pcibios_fixup)(void); - - /* Called after PPC generic resource fixup to perform - machine specific fixups */ - void (*pcibios_fixup_resources)(struct pci_dev *); - - /* Called for each PCI bus in the system when it's probed */ - void (*pcibios_fixup_bus)(struct pci_bus *); - - /* Called when pci_enable_device() is called (initial=0) or - * when a device with no assigned resource is found (initial=1). - * Returns 0 to allow assignment/enabling of the device. */ - int (*pcibios_enable_device_hook)(struct pci_dev *, int initial); - - /* For interrupt routing */ - unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *); - int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char); - - /* Called in indirect_* to avoid touching devices */ - int (*pci_exclude_device)(unsigned char, unsigned char); - - /* Called at then very end of pcibios_init() */ - void (*pcibios_after_init)(void); - - /* Get access protection for /dev/mem */ - pgprot_t (*phys_mem_access_prot)(struct file *file, - unsigned long pfn, - unsigned long size, - pgprot_t vma_prot); - - /* Motherboard/chipset features. This is a kind of general purpose - * hook used to control some machine specific features (like reset - * lines, chip power control, etc...). - */ - long (*feature_call)(unsigned int feature, ...); - -#ifdef CONFIG_SMP - /* functions for dealing with other cpus */ - struct smp_ops_t *smp_ops; -#endif /* CONFIG_SMP */ - -#ifdef CONFIG_KEXEC - /* Called to shutdown machine specific hardware not already controlled - * by other drivers. - * XXX Should we move this one out of kexec scope? - */ - void (*machine_shutdown)(void); - - /* Called to do the minimal shutdown needed to run a kexec'd kernel - * to run successfully. - * XXX Should we move this one out of kexec scope? - */ - void (*machine_crash_shutdown)(void); - - /* Called to do what every setup is needed on image and the - * reboot code buffer. Returns 0 on success. - * Provide your own (maybe dummy) implementation if your platform - * claims to support kexec. - */ - int (*machine_kexec_prepare)(struct kimage *image); - - /* Called to handle any machine specific cleanup on image */ - void (*machine_kexec_cleanup)(struct kimage *image); - - /* Called to perform the _real_ kexec. - * Do NOT allocate memory or fail here. We are past the point of - * no return. - */ - void (*machine_kexec)(struct kimage *image); -#endif /* CONFIG_KEXEC */ -}; - -extern struct machdep_calls ppc_md; -extern char cmd_line[COMMAND_LINE_SIZE]; - -extern void setup_pci_ptrs(void); - -#ifdef CONFIG_SMP -struct smp_ops_t { - void (*message_pass)(int target, int msg); - int (*probe)(void); - void (*kick_cpu)(int nr); - void (*setup_cpu)(int nr); - void (*space_timers)(int nr); - void (*take_timebase)(void); - void (*give_timebase)(void); -}; - -/* Poor default implementations */ -extern void __devinit smp_generic_give_timebase(void); -extern void __devinit smp_generic_take_timebase(void); -#endif /* CONFIG_SMP */ - -#endif /* _PPC_MACHDEP_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/md.h b/include/asm-ppc/md.h deleted file mode 100644 index 9a9b6b42b4b4..000000000000 --- a/include/asm-ppc/md.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * md.h: High speed xor_block operation for RAID4/5 - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_MD_H -#define __ASM_MD_H - -/* #define HAVE_ARCH_XORBLOCK */ - -#define MD_XORBLOCK_ALIGNMENT sizeof(long) - -#endif /* __ASM_MD_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mk48t59.h b/include/asm-ppc/mk48t59.h deleted file mode 100644 index 6a0ed6fc2d56..000000000000 --- a/include/asm-ppc/mk48t59.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Registers for the mk48t59 real-time-clock - */ - -#ifndef _PPC_MK48T59_H -#define _PPC_MK48T59_H - -/* RTC Offsets */ - -#define MK48T59_RTC_SECONDS 0x1FF9 -#define MK48T59_RTC_MINUTES 0x1FFA -#define MK48T59_RTC_HOURS 0x1FFB -#define MK48T59_RTC_DAY_OF_WEEK 0x1FFC -#define MK48T59_RTC_DAY_OF_MONTH 0x1FFD -#define MK48T59_RTC_MONTH 0x1FFE -#define MK48T59_RTC_YEAR 0x1FFF - -#define MK48T59_RTC_CONTROLA 0x1FF8 -#define MK48T59_RTC_CA_WRITE 0x80 -#define MK48T59_RTC_CA_READ 0x40 -#define MK48T59_RTC_CA_CALIB_SIGN 0x20 -#define MK48T59_RTC_CA_CALIB_MASK 0x1f - -#define MK48T59_RTC_CONTROLB 0x1FF9 -#define MK48T59_RTC_CB_STOP 0x80 - -#endif /* _PPC_MK48T59_H */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h deleted file mode 100644 index d76ef098ed37..000000000000 --- a/include/asm-ppc/mmu.h +++ /dev/null @@ -1,444 +0,0 @@ -/* - * PowerPC memory management structures - */ - -#ifdef __KERNEL__ -#ifndef _PPC_MMU_H_ -#define _PPC_MMU_H_ - - -#ifndef __ASSEMBLY__ - -/* - * Define physical address type. Machines using split size - * virtual/physical addressing like 32-bit virtual / 36-bit - * physical need a larger than native word size type. -Matt - */ -#ifndef CONFIG_PHYS_64BIT -#define PHYS_FMT "%.8lx" -#else -extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t); -#define PHYS_FMT "%16Lx" -#endif - -typedef struct { - unsigned long id; - unsigned long vdso_base; -} mm_context_t; - -/* Hardware Page Table Entry */ -typedef struct _PTE { - unsigned long v:1; /* Entry is valid */ - unsigned long vsid:24; /* Virtual segment identifier */ - unsigned long h:1; /* Hash algorithm indicator */ - unsigned long api:6; /* Abbreviated page index */ - unsigned long rpn:20; /* Real (physical) page number */ - unsigned long :3; /* Unused */ - unsigned long r:1; /* Referenced */ - unsigned long c:1; /* Changed */ - unsigned long w:1; /* Write-thru cache mode */ - unsigned long i:1; /* Cache inhibited */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page protection */ -} PTE; - -/* Values for PP (assumes Ks=0, Kp=1) */ -#define PP_RWXX 0 /* Supervisor read/write, User none */ -#define PP_RWRX 1 /* Supervisor read/write, User read */ -#define PP_RWRW 2 /* Supervisor read/write, User read/write */ -#define PP_RXRX 3 /* Supervisor read, User read */ - -/* Segment Register */ -typedef struct _SEGREG { - unsigned long t:1; /* Normal or I/O type */ - unsigned long ks:1; /* Supervisor 'key' (normally 0) */ - unsigned long kp:1; /* User 'key' (normally 1) */ - unsigned long n:1; /* No-execute */ - unsigned long :4; /* Unused */ - unsigned long vsid:24; /* Virtual Segment Identifier */ -} SEGREG; - -/* Block Address Translation (BAT) Registers */ -typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :8; /* unused */ - unsigned long w:1; - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long ks:1; /* Supervisor key (normally 0) */ - unsigned long kp:1; /* User key (normally 1) */ - unsigned long pp:2; /* Page access protections */ -} P601_BATU; - -typedef struct _BATU { /* Upper part of BAT (all except 601) */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :4; /* Unused */ - unsigned long bl:11; /* Block size mask */ - unsigned long vs:1; /* Supervisor valid */ - unsigned long vp:1; /* User valid */ -} BATU; - -typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long v:1; /* Valid bit */ - unsigned long bl:6; /* Block size mask */ -} P601_BATL; - -typedef struct _BATL { /* Lower part of BAT (all except 601) */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long w:1; /* Write-thru cache */ - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded (MBZ in IBAT) */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page access protections */ -} BATL; - -typedef struct _BAT { - BATU batu; /* Upper register */ - BATL batl; /* Lower register */ -} BAT; - -typedef struct _P601_BAT { - P601_BATU batu; /* Upper register */ - P601_BATL batl; /* Lower register */ -} P601_BAT; - -#endif /* __ASSEMBLY__ */ - -/* Block size masks */ -#define BL_128K 0x000 -#define BL_256K 0x001 -#define BL_512K 0x003 -#define BL_1M 0x007 -#define BL_2M 0x00F -#define BL_4M 0x01F -#define BL_8M 0x03F -#define BL_16M 0x07F -#define BL_32M 0x0FF -#define BL_64M 0x1FF -#define BL_128M 0x3FF -#define BL_256M 0x7FF - -/* BAT Access Protection */ -#define BPP_XX 0x00 /* No access */ -#define BPP_RX 0x01 /* Read only */ -#define BPP_RW 0x02 /* Read/write */ - -/* Control/status registers for the MPC8xx. - * A write operation to these registers causes serialized access. - * During software tablewalk, the registers used perform mask/shift-add - * operations when written/read. A TLB entry is created when the Mx_RPN - * is written, and the contents of several registers are used to - * create the entry. - */ -#define SPRN_MI_CTR 784 /* Instruction TLB control register */ -#define MI_GPM 0x80000000 /* Set domain manager mode */ -#define MI_PPM 0x40000000 /* Set subpage protection */ -#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MI_RESETVAL 0x00000000 /* Value of register at reset */ - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define SPRN_MI_AP 786 -#define MI_Ks 0x80000000 /* Should not be set */ -#define MI_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MI_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define SPRN_MI_EPN 787 -#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MI_EVALID 0x00000200 /* Entry is valid */ -#define MI_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the instruction TLB, it contains bits that get loaded into the - * TLB entry when the MI_RPN is written. - */ -#define SPRN_MI_TWC 789 -#define MI_APG 0x000001e0 /* Access protection group (0) */ -#define MI_GUARDED 0x00000010 /* Guarded storage */ -#define MI_PSMASK 0x0000000c /* Mask of page size bits */ -#define MI_PS8MEG 0x0000000c /* 8M page size */ -#define MI_PS512K 0x00000004 /* 512K page size */ -#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MI_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the instruction TLB, using - * additional information from the MI_EPN, and MI_TWC registers. - */ -#define SPRN_MI_RPN 790 - -/* Define an RPN value for mapping kernel memory to large virtual - * pages for boot initialization. This has real page number of 0, - * large page size, shared page, cache enabled, and valid. - * Also mark all subpages valid and write access. - */ -#define MI_BOOTINIT 0x000001fd - -#define SPRN_MD_CTR 792 /* Data TLB control register */ -#define MD_GPM 0x80000000 /* Set domain manager mode */ -#define MD_PPM 0x40000000 /* Set subpage protection */ -#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ -#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ -#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MD_RESETVAL 0x04000000 /* Value of register at reset */ - -#define SPRN_M_CASID 793 /* Address space ID (context) to match */ -#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ - - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define SPRN_MD_AP 794 -#define MD_Ks 0x80000000 /* Should not be set */ -#define MD_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MD_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define SPRN_MD_EPN 795 -#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MD_EVALID 0x00000200 /* Entry is valid */ -#define MD_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* The pointer to the base address of the first level page table. - * During a software tablewalk, reading this register provides the address - * of the entry associated with MD_EPN. - */ -#define SPRN_M_TWB 796 -#define M_L1TB 0xfffff000 /* Level 1 table base address */ -#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the data TLB, it contains bits that get loaded into the TLB entry - * when the MD_RPN is written. It is also provides the hardware assist - * for finding the PTE address during software tablewalk. - */ -#define SPRN_MD_TWC 797 -#define MD_L2TB 0xfffff000 /* Level 2 table base address */ -#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ -#define MD_APG 0x000001e0 /* Access protection group (0) */ -#define MD_GUARDED 0x00000010 /* Guarded storage */ -#define MD_PSMASK 0x0000000c /* Mask of page size bits */ -#define MD_PS8MEG 0x0000000c /* 8M page size */ -#define MD_PS512K 0x00000004 /* 512K page size */ -#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MD_WT 0x00000002 /* Use writethrough page attribute */ -#define MD_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the data TLB, using - * additional information from the MD_EPN, and MD_TWC registers. - */ -#define SPRN_MD_RPN 798 - -/* This is a temporary storage register that could be used to save - * a processor working register during a tablewalk. - */ -#define SPRN_M_TW 799 - -/* - * At present, all PowerPC 400-class processors share a similar TLB - * architecture. The instruction and data sides share a unified, - * 64-entry, fully-associative TLB which is maintained totally under - * software control. In addition, the instruction side has a - * hardware-managed, 4-entry, fully- associative TLB which serves as a - * first level to the shared TLB. These two TLBs are known as the UTLB - * and ITLB, respectively. - */ - -#define PPC4XX_TLB_SIZE 64 - -/* - * TLB entries are defined by a "high" tag portion and a "low" data - * portion. On all architectures, the data portion is 32-bits. - * - * TLB entries are managed entirely under software control by reading, - * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx - * instructions. - */ - -#define TLB_LO 1 -#define TLB_HI 0 - -#define TLB_DATA TLB_LO -#define TLB_TAG TLB_HI - -/* Tag portion */ - -#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ -#define TLB_PAGESZ_MASK 0x00000380 -#define TLB_PAGESZ(x) (((x) & 0x7) << 7) -#define PAGESZ_1K 0 -#define PAGESZ_4K 1 -#define PAGESZ_16K 2 -#define PAGESZ_64K 3 -#define PAGESZ_256K 4 -#define PAGESZ_1M 5 -#define PAGESZ_4M 6 -#define PAGESZ_16M 7 -#define TLB_VALID 0x00000040 /* Entry is valid */ - -/* Data portion */ - -#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ -#define TLB_PERM_MASK 0x00000300 -#define TLB_EX 0x00000200 /* Instruction execution allowed */ -#define TLB_WR 0x00000100 /* Writes permitted */ -#define TLB_ZSEL_MASK 0x000000F0 -#define TLB_ZSEL(x) (((x) & 0xF) << 4) -#define TLB_ATTR_MASK 0x0000000F -#define TLB_W 0x00000008 /* Caching is write-through */ -#define TLB_I 0x00000004 /* Caching is inhibited */ -#define TLB_M 0x00000002 /* Memory is coherent */ -#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ - -/* - * PPC440 support - */ -#define PPC44x_MMUCR_TID 0x000000ff -#define PPC44x_MMUCR_STS 0x00010000 - -#define PPC44x_TLB_PAGEID 0 -#define PPC44x_TLB_XLAT 1 -#define PPC44x_TLB_ATTRIB 2 - -/* Page identification fields */ -#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ -#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ -#define PPC44x_TLB_TS 0x00000100 /* Translation address space */ -#define PPC44x_TLB_1K 0x00000000 /* Page sizes */ -#define PPC44x_TLB_4K 0x00000010 -#define PPC44x_TLB_16K 0x00000020 -#define PPC44x_TLB_64K 0x00000030 -#define PPC44x_TLB_256K 0x00000040 -#define PPC44x_TLB_1M 0x00000050 -#define PPC44x_TLB_16M 0x00000070 -#define PPC44x_TLB_256M 0x00000090 - -/* Translation fields */ -#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ -#define PPC44x_TLB_ERPN_MASK 0x0000000f - -/* Storage attribute and access control fields */ -#define PPC44x_TLB_ATTR_MASK 0x0000ff80 -#define PPC44x_TLB_U0 0x00008000 /* User 0 */ -#define PPC44x_TLB_U1 0x00004000 /* User 1 */ -#define PPC44x_TLB_U2 0x00002000 /* User 2 */ -#define PPC44x_TLB_U3 0x00001000 /* User 3 */ -#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ -#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ -#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ -#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ -#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */ - -#define PPC44x_TLB_PERM_MASK 0x0000003f -#define PPC44x_TLB_UX 0x00000020 /* User execution */ -#define PPC44x_TLB_UW 0x00000010 /* User write */ -#define PPC44x_TLB_UR 0x00000008 /* User read */ -#define PPC44x_TLB_SX 0x00000004 /* Super execution */ -#define PPC44x_TLB_SW 0x00000002 /* Super write */ -#define PPC44x_TLB_SR 0x00000001 /* Super read */ - -/* Book-E defined page sizes */ -#define BOOKE_PAGESZ_1K 0 -#define BOOKE_PAGESZ_4K 1 -#define BOOKE_PAGESZ_16K 2 -#define BOOKE_PAGESZ_64K 3 -#define BOOKE_PAGESZ_256K 4 -#define BOOKE_PAGESZ_1M 5 -#define BOOKE_PAGESZ_4M 6 -#define BOOKE_PAGESZ_16M 7 -#define BOOKE_PAGESZ_64M 8 -#define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1GB 10 -#define BOOKE_PAGESZ_4GB 11 -#define BOOKE_PAGESZ_16GB 12 -#define BOOKE_PAGESZ_64GB 13 -#define BOOKE_PAGESZ_256GB 14 -#define BOOKE_PAGESZ_1TB 15 - -#ifndef CONFIG_SERIAL_TEXT_DEBUG -#define PPC44x_EARLY_TLBS 1 -#else -#define PPC44x_EARLY_TLBS 2 -#endif - -/* - * Freescale Book-E MMU support - */ - -#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) -#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) -#define MAS0_NV(x) ((x) & 0x00000FFF) - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) -#define MAS1_TS 0x00001000 -#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) - -#define MAS2_EPN 0xFFFFF000 -#define MAS2_X0 0x00000040 -#define MAS2_X1 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 - -#define MAS3_RPN 0xFFFFF000 -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 - -#define MAS4_TLBSELD(x) MAS0_TLBSEL(x) -#define MAS4_TIDDSEL 0x000F0000 -#define MAS4_TSIZED(x) MAS1_TSIZE(x) -#define MAS4_X0D 0x00000040 -#define MAS4_X1D 0x00000020 -#define MAS4_WD 0x00000010 -#define MAS4_ID 0x00000008 -#define MAS4_MD 0x00000004 -#define MAS4_GD 0x00000002 -#define MAS4_ED 0x00000001 - -#define MAS6_SPID0 0x3FFF0000 -#define MAS6_SPID1 0x00007FFE -#define MAS6_SAS 0x00000001 -#define MAS6_SPID MAS6_SPID0 - -#define MAS7_RPN 0xFFFFFFFF - -#endif /* _PPC_MMU_H_ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h deleted file mode 100644 index 9f097e25b169..000000000000 --- a/include/asm-ppc/mmu_context.h +++ /dev/null @@ -1,198 +0,0 @@ -#ifdef __KERNEL__ -#ifndef __PPC_MMU_CONTEXT_H -#define __PPC_MMU_CONTEXT_H - -#include - -#include -#include -#include -#include - -/* - * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs - * (virtual segment identifiers) for each context. Although the - * hardware supports 24-bit VSIDs, and thus >1 million contexts, - * we only use 32,768 of them. That is ample, since there can be - * at most around 30,000 tasks in the system anyway, and it means - * that we can use a bitmap to indicate which contexts are in use. - * Using a bitmap means that we entirely avoid all of the problems - * that we used to have when the context number overflowed, - * particularly on SMP systems. - * -- paulus. - */ - -/* - * This function defines the mapping from contexts to VSIDs (virtual - * segment IDs). We use a skew on both the context and the high 4 bits - * of the 32-bit virtual address (the "effective segment ID") in order - * to spread out the entries in the MMU hash table. Note, if this - * function is changed then arch/ppc/mm/hashtable.S will have to be - * changed to correspond. - */ -#define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \ - & 0xffffff) - -/* - The MPC8xx has only 16 contexts. We rotate through them on each - task switch. A better way would be to keep track of tasks that - own contexts, and implement an LRU usage. That way very active - tasks don't always have to pay the TLB reload overhead. The - kernel pages are mapped shared, so the kernel can run on behalf - of any task that makes a kernel entry. Shared does not mean they - are not protected, just that the ASID comparison is not performed. - -- Dan - - The IBM4xx has 256 contexts, so we can just rotate through these - as a way of "switching" contexts. If the TID of the TLB is zero, - the PID/TID comparison is disabled, so we can use a TID of zero - to represent all kernel pages as shared among all contexts. - -- Dan - */ - -static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -#ifdef CONFIG_8xx -#define NO_CONTEXT 16 -#define LAST_CONTEXT 15 -#define FIRST_CONTEXT 0 - -#elif defined(CONFIG_4xx) -#define NO_CONTEXT 256 -#define LAST_CONTEXT 255 -#define FIRST_CONTEXT 1 - -#else - -/* PPC 6xx, 7xx CPUs */ -#define NO_CONTEXT ((unsigned long) -1) -#define LAST_CONTEXT 32767 -#define FIRST_CONTEXT 1 -#endif - -/* - * Set the current MMU context. - * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by - * loading up the segment registers for the user part of the address space. - * - * Since the PGD is immediately available, it is much faster to simply - * pass this along as a second parameter, which is required for 8xx and - * can be used for debugging on all processors (if you happen to have - * an Abatron). - */ -extern void set_context(unsigned long contextid, pgd_t *pgd); - -/* - * Bitmap of contexts in use. - * The size of this bitmap is LAST_CONTEXT + 1 bits. - */ -extern unsigned long context_map[]; - -/* - * This caches the next context number that we expect to be free. - * Its use is an optimization only, we can't rely on this context - * number to be free, but it usually will be. - */ -extern unsigned long next_mmu_context; - -/* - * If we don't have sufficient contexts to give one to every task - * that could be in the system, we need to be able to steal contexts. - * These variables support that. - */ -#if LAST_CONTEXT < 30000 -#define FEW_CONTEXTS 1 -extern atomic_t nr_free_contexts; -extern struct mm_struct *context_mm[LAST_CONTEXT+1]; -extern void steal_context(void); -#endif - -/* - * Get a new mmu context for the address space described by `mm'. - */ -static inline void get_mmu_context(struct mm_struct *mm) -{ - unsigned long ctx; - - if (mm->context.id != NO_CONTEXT) - return; -#ifdef FEW_CONTEXTS - while (atomic_dec_if_positive(&nr_free_contexts) < 0) - steal_context(); -#endif - ctx = next_mmu_context; - while (test_and_set_bit(ctx, context_map)) { - ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); - if (ctx > LAST_CONTEXT) - ctx = 0; - } - next_mmu_context = (ctx + 1) & LAST_CONTEXT; - mm->context.id = ctx; -#ifdef FEW_CONTEXTS - context_mm[ctx] = mm; -#endif -} - -/* - * Set up the context for a new address space. - */ -static inline int init_new_context(struct task_struct *t, struct mm_struct *mm) -{ - mm->context.id = NO_CONTEXT; - mm->context.vdso_base = 0; - return 0; -} - -/* - * We're finished using the context for an address space. - */ -static inline void destroy_context(struct mm_struct *mm) -{ - preempt_disable(); - if (mm->context.id != NO_CONTEXT) { - clear_bit(mm->context.id, context_map); - mm->context.id = NO_CONTEXT; -#ifdef FEW_CONTEXTS - atomic_inc(&nr_free_contexts); -#endif - } - preempt_enable(); -} - -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ -#ifdef CONFIG_ALTIVEC - if (cpu_has_feature(CPU_FTR_ALTIVEC)) - asm volatile ("dssall;\n" -#ifndef CONFIG_POWER4 - "sync;\n" /* G4 needs a sync here, G5 apparently not */ -#endif - : : ); -#endif /* CONFIG_ALTIVEC */ - - tsk->thread.pgdir = next->pgd; - - /* No need to flush userspace segments if the mm doesnt change */ - if (prev == next) - return; - - /* Setup new userspace context */ - get_mmu_context(next); - set_context(next->context.id, next->pgd); -} - -#define deactivate_mm(tsk,mm) do { } while (0) - -/* - * After we have set current->mm to a new value, this activates - * the context for the new mm so we see the new mappings. - */ -#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current) - -extern void mmu_context_init(void); - -#endif /* __PPC_MMU_CONTEXT_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h deleted file mode 100644 index b30a6a3b5bd2..000000000000 --- a/include/asm-ppc/mpc10x.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem - * ctlr/EPIC/etc. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __PPC_KERNEL_MPC10X_H -#define __PPC_KERNEL_MPC10X_H - -#include -#include - -/* - * The values here don't completely map everything but should work in most - * cases. - * - * MAP A (PReP Map) - * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff - * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff - * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 - * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) - * - * MAP B (CHRP Map) - * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff - * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff - * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 - * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) - */ - -/* - * Define the vendor/device IDs for the various bridges--should be added to - * - */ -#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ - PCI_VENDOR_ID_MOTOROLA) -#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) -#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) -#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) - -/* Define the type of map to use */ -#define MPC10X_MEM_MAP_A 1 -#define MPC10X_MEM_MAP_B 2 - -/* Map A (PReP Map) Defines */ -#define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 -#define MPC10X_MAPA_CNFG_DATA 0x80000cfc - -#define MPC10X_MAPA_ISA_IO_BASE 0x80000000 -#define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 -#define MPC10X_MAPA_DRAM_OFFSET 0x80000000 - -#define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0 -#define MPC10X_MAPA_PCI_IO_START 0x00000000 -#define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) -#define MPC10X_MAPA_PCI_MEM_START 0x00000000 -#define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) - -#define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ - MPC10X_MAPA_PCI_MEM_START) - -/* Map B (CHRP Map) Defines */ -#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 -#define MPC10X_MAPB_CNFG_DATA 0xfee00000 - -#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 -#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 -#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 - -#define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000 -#define MPC10X_MAPB_PCI_IO_START 0x00000000 -#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) -#define MPC10X_MAPB_PCI_MEM_START 0x80000000 -#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) - -#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ - MPC10X_MAPB_PCI_MEM_START) - -/* Set hose members to values appropriate for the mem map used */ -#define MPC10X_SETUP_HOSE(hose, map) { \ - (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET; \ - (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START; \ - (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END; \ - (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START; \ - (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END; \ - (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE; \ -} - - -/* Miscellaneous Configuration register offsets */ -#define MPC10X_CFG_PIR_REG 0x09 -#define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 -#define MPC10X_CFG_PIR_AGENT 0x01 - -#define MPC10X_CFG_EUMBBAR 0x78 - -#define MPC10X_CFG_PICR1_REG 0xa8 -#define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 -#define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 -#define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 -#define MPC10X_CFG_PICR1_SPEC_PCI_RD 0x00000004 -#define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 - -#define MPC10X_CFG_PICR2_REG 0xac -#define MPC10X_CFG_PICR2_COPYBACK_OPT 0x00000001 - -#define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 -#define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ -#define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ -#define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ -#define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x08 /* PCI_COMPATIBILITY_HOLE */ -#define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x04 /* PROC_COMPATIBILITY_HOLE */ - -/* Define offsets for the memory controller registers in the config space */ -#define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ -#define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ -#define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ -#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ - -#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ -#define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ -#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ -#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ - -#define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 - -/* Define some offset in the EUMB */ -#define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ - -#define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ -#define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ -#define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ -#define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ -#define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ -#define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ -#define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ -#define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ -#define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ -#define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ -#define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ -#define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ -#define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ -#define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ -#define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ -#define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ - -/* - * Define some recommended places to put the EUMB regs. - * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff. - */ -extern unsigned long ioremap_base; -#define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE) -#define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE - -enum ppc_sys_devices { - MPC10X_IIC1, - MPC10X_DMA0, - MPC10X_DMA1, - MPC10X_UART0, - MPC10X_UART1, - NUM_PPC_SYS_DEVS, -}; - -int mpc10x_bridge_init(struct pci_controller *hose, - uint current_map, - uint new_map, - uint phys_eumb_base); -unsigned long mpc10x_get_mem_size(uint mem_map); -int mpc10x_enable_store_gathering(struct pci_controller *hose); -int mpc10x_disable_store_gathering(struct pci_controller *hose); - -/* For MPC107 boards that use the built-in openpic */ -void mpc10x_set_openpic(void); - -#endif /* __PPC_KERNEL_MPC10X_H */ diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h deleted file mode 100644 index d9d21aa68ba3..000000000000 --- a/include/asm-ppc/mpc52xx.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * include/asm-ppc/mpc52xx.h - * - * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips - * May need to be cleaned as the port goes on ... - * - * - * Maintainer : Sylvain Munaut - * - * Originally written by Dale Farnsworth - * for the 2.4 kernel. - * - * Copyright (C) 2004-2005 Sylvain Munaut - * Copyright (C) 2003 MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef __ASM_MPC52xx_H__ -#define __ASM_MPC52xx_H__ - -#ifndef __ASSEMBLY__ -#include -#include - -struct pt_regs; -#endif /* __ASSEMBLY__ */ - - -/* ======================================================================== */ -/* PPC Sys devices definition */ -/* ======================================================================== */ - -enum ppc_sys_devices { - MPC52xx_MSCAN1, - MPC52xx_MSCAN2, - MPC52xx_SPI, - MPC52xx_USB, - MPC52xx_BDLC, - MPC52xx_PSC1, - MPC52xx_PSC2, - MPC52xx_PSC3, - MPC52xx_PSC4, - MPC52xx_PSC5, - MPC52xx_PSC6, - MPC52xx_FEC, - MPC52xx_ATA, - MPC52xx_I2C1, - MPC52xx_I2C2, - NUM_PPC_SYS_DEVS, -}; - - -/* ======================================================================== */ -/* Main registers/struct addresses */ -/* ======================================================================== */ - -/* MBAR position */ -#define MPC52xx_MBAR 0xf0000000 /* Phys address */ -#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */ -#define MPC52xx_MBAR_SIZE 0x00010000 - -#define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x))) -#define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x))) - -/* Registers zone offset/size */ -#define MPC52xx_MMAP_CTL_OFFSET 0x0000 -#define MPC52xx_MMAP_CTL_SIZE 0x068 -#define MPC52xx_SDRAM_OFFSET 0x0100 -#define MPC52xx_SDRAM_SIZE 0x010 -#define MPC52xx_CDM_OFFSET 0x0200 -#define MPC52xx_CDM_SIZE 0x038 -#define MPC52xx_INTR_OFFSET 0x0500 -#define MPC52xx_INTR_SIZE 0x04c -#define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4)) -#define MPC52xx_GPT_SIZE 0x010 -#define MPC52xx_RTC_OFFSET 0x0800 -#define MPC52xx_RTC_SIZE 0x024 -#define MPC52xx_GPIO_OFFSET 0x0b00 -#define MPC52xx_GPIO_SIZE 0x040 -#define MPC52xx_GPIO_WKUP_OFFSET 0x0c00 -#define MPC52xx_GPIO_WKUP_SIZE 0x028 -#define MPC52xx_PCI_OFFSET 0x0d00 -#define MPC52xx_PCI_SIZE 0x100 -#define MPC52xx_SDMA_OFFSET 0x1200 -#define MPC52xx_SDMA_SIZE 0x100 -#define MPC52xx_XLB_OFFSET 0x1f00 -#define MPC52xx_XLB_SIZE 0x100 -#define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00) -#define MPC52xx_PSC_SIZE 0x0a0 - -/* SRAM used for SDMA */ -#define MPC52xx_SRAM_OFFSET 0x8000 -#define MPC52xx_SRAM_SIZE 0x4000 - - -/* ======================================================================== */ -/* IRQ mapping */ -/* ======================================================================== */ -/* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change - * this - */ - -#define MPC52xx_CRIT_IRQ_NUM 4 -#define MPC52xx_MAIN_IRQ_NUM 17 -#define MPC52xx_SDMA_IRQ_NUM 17 -#define MPC52xx_PERP_IRQ_NUM 23 - -#define MPC52xx_CRIT_IRQ_BASE 1 -#define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM) -#define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM) -#define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM) - -#define MPC52xx_IRQ0 (MPC52xx_CRIT_IRQ_BASE + 0) -#define MPC52xx_SLICE_TIMER_0_IRQ (MPC52xx_CRIT_IRQ_BASE + 1) -#define MPC52xx_HI_INT_IRQ (MPC52xx_CRIT_IRQ_BASE + 2) -#define MPC52xx_CCS_IRQ (MPC52xx_CRIT_IRQ_BASE + 3) - -#define MPC52xx_IRQ1 (MPC52xx_MAIN_IRQ_BASE + 1) -#define MPC52xx_IRQ2 (MPC52xx_MAIN_IRQ_BASE + 2) -#define MPC52xx_IRQ3 (MPC52xx_MAIN_IRQ_BASE + 3) - -#define MPC52xx_SDMA_IRQ (MPC52xx_PERP_IRQ_BASE + 0) -#define MPC52xx_PSC1_IRQ (MPC52xx_PERP_IRQ_BASE + 1) -#define MPC52xx_PSC2_IRQ (MPC52xx_PERP_IRQ_BASE + 2) -#define MPC52xx_PSC3_IRQ (MPC52xx_PERP_IRQ_BASE + 3) -#define MPC52xx_PSC6_IRQ (MPC52xx_PERP_IRQ_BASE + 4) -#define MPC52xx_IRDA_IRQ (MPC52xx_PERP_IRQ_BASE + 4) -#define MPC52xx_FEC_IRQ (MPC52xx_PERP_IRQ_BASE + 5) -#define MPC52xx_USB_IRQ (MPC52xx_PERP_IRQ_BASE + 6) -#define MPC52xx_ATA_IRQ (MPC52xx_PERP_IRQ_BASE + 7) -#define MPC52xx_PCI_CNTRL_IRQ (MPC52xx_PERP_IRQ_BASE + 8) -#define MPC52xx_PCI_SCIRX_IRQ (MPC52xx_PERP_IRQ_BASE + 9) -#define MPC52xx_PCI_SCITX_IRQ (MPC52xx_PERP_IRQ_BASE + 10) -#define MPC52xx_PSC4_IRQ (MPC52xx_PERP_IRQ_BASE + 11) -#define MPC52xx_PSC5_IRQ (MPC52xx_PERP_IRQ_BASE + 12) -#define MPC52xx_SPI_MODF_IRQ (MPC52xx_PERP_IRQ_BASE + 13) -#define MPC52xx_SPI_SPIF_IRQ (MPC52xx_PERP_IRQ_BASE + 14) -#define MPC52xx_I2C1_IRQ (MPC52xx_PERP_IRQ_BASE + 15) -#define MPC52xx_I2C2_IRQ (MPC52xx_PERP_IRQ_BASE + 16) -#define MPC52xx_MSCAN1_IRQ (MPC52xx_PERP_IRQ_BASE + 17) -#define MPC52xx_MSCAN2_IRQ (MPC52xx_PERP_IRQ_BASE + 18) -#define MPC52xx_IR_RX_IRQ (MPC52xx_PERP_IRQ_BASE + 19) -#define MPC52xx_IR_TX_IRQ (MPC52xx_PERP_IRQ_BASE + 20) -#define MPC52xx_XLB_ARB_IRQ (MPC52xx_PERP_IRQ_BASE + 21) -#define MPC52xx_BDLC_IRQ (MPC52xx_PERP_IRQ_BASE + 22) - - - -/* ======================================================================== */ -/* Structures mapping of some unit register set */ -/* ======================================================================== */ - -#ifndef __ASSEMBLY__ - -/* Memory Mapping Control */ -struct mpc52xx_mmap_ctl { - u32 mbar; /* MMAP_CTRL + 0x00 */ - - u32 cs0_start; /* MMAP_CTRL + 0x04 */ - u32 cs0_stop; /* MMAP_CTRL + 0x08 */ - u32 cs1_start; /* MMAP_CTRL + 0x0c */ - u32 cs1_stop; /* MMAP_CTRL + 0x10 */ - u32 cs2_start; /* MMAP_CTRL + 0x14 */ - u32 cs2_stop; /* MMAP_CTRL + 0x18 */ - u32 cs3_start; /* MMAP_CTRL + 0x1c */ - u32 cs3_stop; /* MMAP_CTRL + 0x20 */ - u32 cs4_start; /* MMAP_CTRL + 0x24 */ - u32 cs4_stop; /* MMAP_CTRL + 0x28 */ - u32 cs5_start; /* MMAP_CTRL + 0x2c */ - u32 cs5_stop; /* MMAP_CTRL + 0x30 */ - - u32 sdram0; /* MMAP_CTRL + 0x34 */ - u32 sdram1; /* MMAP_CTRL + 0X38 */ - - u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */ - - u32 boot_start; /* MMAP_CTRL + 0x4c */ - u32 boot_stop; /* MMAP_CTRL + 0x50 */ - - u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */ - - u32 cs6_start; /* MMAP_CTRL + 0x58 */ - u32 cs6_stop; /* MMAP_CTRL + 0x5c */ - u32 cs7_start; /* MMAP_CTRL + 0x60 */ - u32 cs7_stop; /* MMAP_CTRL + 0x64 */ -}; - -/* SDRAM control */ -struct mpc52xx_sdram { - u32 mode; /* SDRAM + 0x00 */ - u32 ctrl; /* SDRAM + 0x04 */ - u32 config1; /* SDRAM + 0x08 */ - u32 config2; /* SDRAM + 0x0c */ -}; - -/* Interrupt controller */ -struct mpc52xx_intr { - u32 per_mask; /* INTR + 0x00 */ - u32 per_pri1; /* INTR + 0x04 */ - u32 per_pri2; /* INTR + 0x08 */ - u32 per_pri3; /* INTR + 0x0c */ - u32 ctrl; /* INTR + 0x10 */ - u32 main_mask; /* INTR + 0x14 */ - u32 main_pri1; /* INTR + 0x18 */ - u32 main_pri2; /* INTR + 0x1c */ - u32 reserved1; /* INTR + 0x20 */ - u32 enc_status; /* INTR + 0x24 */ - u32 crit_status; /* INTR + 0x28 */ - u32 main_status; /* INTR + 0x2c */ - u32 per_status; /* INTR + 0x30 */ - u32 reserved2; /* INTR + 0x34 */ - u32 per_error; /* INTR + 0x38 */ -}; - -/* SDMA */ -struct mpc52xx_sdma { - u32 taskBar; /* SDMA + 0x00 */ - u32 currentPointer; /* SDMA + 0x04 */ - u32 endPointer; /* SDMA + 0x08 */ - u32 variablePointer;/* SDMA + 0x0c */ - - u8 IntVect1; /* SDMA + 0x10 */ - u8 IntVect2; /* SDMA + 0x11 */ - u16 PtdCntrl; /* SDMA + 0x12 */ - - u32 IntPend; /* SDMA + 0x14 */ - u32 IntMask; /* SDMA + 0x18 */ - - u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */ - - u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */ - - u32 cReqSelect; /* SDMA + 0x5c */ - u32 task_size0; /* SDMA + 0x60 */ - u32 task_size1; /* SDMA + 0x64 */ - u32 MDEDebug; /* SDMA + 0x68 */ - u32 ADSDebug; /* SDMA + 0x6c */ - u32 Value1; /* SDMA + 0x70 */ - u32 Value2; /* SDMA + 0x74 */ - u32 Control; /* SDMA + 0x78 */ - u32 Status; /* SDMA + 0x7c */ - u32 PTDDebug; /* SDMA + 0x80 */ -}; - -/* GPT */ -struct mpc52xx_gpt { - u32 mode; /* GPTx + 0x00 */ - u32 count; /* GPTx + 0x04 */ - u32 pwm; /* GPTx + 0x08 */ - u32 status; /* GPTx + 0X0c */ -}; - -/* RTC */ -struct mpc52xx_rtc { - u32 time_set; /* RTC + 0x00 */ - u32 date_set; /* RTC + 0x04 */ - u32 stopwatch; /* RTC + 0x08 */ - u32 int_enable; /* RTC + 0x0c */ - u32 time; /* RTC + 0x10 */ - u32 date; /* RTC + 0x14 */ - u32 stopwatch_intr; /* RTC + 0x18 */ - u32 bus_error; /* RTC + 0x1c */ - u32 dividers; /* RTC + 0x20 */ -}; - -/* GPIO */ -struct mpc52xx_gpio { - u32 port_config; /* GPIO + 0x00 */ - u32 simple_gpioe; /* GPIO + 0x04 */ - u32 simple_ode; /* GPIO + 0x08 */ - u32 simple_ddr; /* GPIO + 0x0c */ - u32 simple_dvo; /* GPIO + 0x10 */ - u32 simple_ival; /* GPIO + 0x14 */ - u8 outo_gpioe; /* GPIO + 0x18 */ - u8 reserved1[3]; /* GPIO + 0x19 */ - u8 outo_dvo; /* GPIO + 0x1c */ - u8 reserved2[3]; /* GPIO + 0x1d */ - u8 sint_gpioe; /* GPIO + 0x20 */ - u8 reserved3[3]; /* GPIO + 0x21 */ - u8 sint_ode; /* GPIO + 0x24 */ - u8 reserved4[3]; /* GPIO + 0x25 */ - u8 sint_ddr; /* GPIO + 0x28 */ - u8 reserved5[3]; /* GPIO + 0x29 */ - u8 sint_dvo; /* GPIO + 0x2c */ - u8 reserved6[3]; /* GPIO + 0x2d */ - u8 sint_inten; /* GPIO + 0x30 */ - u8 reserved7[3]; /* GPIO + 0x31 */ - u16 sint_itype; /* GPIO + 0x34 */ - u16 reserved8; /* GPIO + 0x36 */ - u8 gpio_control; /* GPIO + 0x38 */ - u8 reserved9[3]; /* GPIO + 0x39 */ - u8 sint_istat; /* GPIO + 0x3c */ - u8 sint_ival; /* GPIO + 0x3d */ - u8 bus_errs; /* GPIO + 0x3e */ - u8 reserved10; /* GPIO + 0x3f */ -}; - -#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4 -#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5 -#define MPC52xx_GPIO_PCI_DIS (1<<15) - -/* GPIO with WakeUp*/ -struct mpc52xx_gpio_wkup { - u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */ - u8 reserved1[3]; /* GPIO_WKUP + 0x03 */ - u8 wkup_ode; /* GPIO_WKUP + 0x04 */ - u8 reserved2[3]; /* GPIO_WKUP + 0x05 */ - u8 wkup_ddr; /* GPIO_WKUP + 0x08 */ - u8 reserved3[3]; /* GPIO_WKUP + 0x09 */ - u8 wkup_dvo; /* GPIO_WKUP + 0x0C */ - u8 reserved4[3]; /* GPIO_WKUP + 0x0D */ - u8 wkup_inten; /* GPIO_WKUP + 0x10 */ - u8 reserved5[3]; /* GPIO_WKUP + 0x11 */ - u8 wkup_iinten; /* GPIO_WKUP + 0x14 */ - u8 reserved6[3]; /* GPIO_WKUP + 0x15 */ - u16 wkup_itype; /* GPIO_WKUP + 0x18 */ - u8 reserved7[2]; /* GPIO_WKUP + 0x1A */ - u8 wkup_maste; /* GPIO_WKUP + 0x1C */ - u8 reserved8[3]; /* GPIO_WKUP + 0x1D */ - u8 wkup_ival; /* GPIO_WKUP + 0x20 */ - u8 reserved9[3]; /* GPIO_WKUP + 0x21 */ - u8 wkup_istat; /* GPIO_WKUP + 0x24 */ - u8 reserved10[3]; /* GPIO_WKUP + 0x25 */ -}; - -/* XLB Bus control */ -struct mpc52xx_xlb { - u8 reserved[0x40]; - u32 config; /* XLB + 0x40 */ - u32 version; /* XLB + 0x44 */ - u32 status; /* XLB + 0x48 */ - u32 int_enable; /* XLB + 0x4c */ - u32 addr_capture; /* XLB + 0x50 */ - u32 bus_sig_capture; /* XLB + 0x54 */ - u32 addr_timeout; /* XLB + 0x58 */ - u32 data_timeout; /* XLB + 0x5c */ - u32 bus_act_timeout; /* XLB + 0x60 */ - u32 master_pri_enable; /* XLB + 0x64 */ - u32 master_priority; /* XLB + 0x68 */ - u32 base_address; /* XLB + 0x6c */ - u32 snoop_window; /* XLB + 0x70 */ -}; - -#define MPC52xx_XLB_CFG_PLDIS (1 << 31) -#define MPC52xx_XLB_CFG_SNOOP (1 << 15) - -/* Clock Distribution control */ -struct mpc52xx_cdm { - u32 jtag_id; /* CDM + 0x00 reg0 read only */ - u32 rstcfg; /* CDM + 0x04 reg1 read only */ - u32 breadcrumb; /* CDM + 0x08 reg2 */ - - u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */ - u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */ - u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */ - u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */ - - u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */ - u8 fd_enable; /* CDM + 0x11 reg4 byte1 */ - u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */ - - u32 clk_enables; /* CDM + 0x14 reg5 */ - - u8 osc_disable; /* CDM + 0x18 reg6 byte0 */ - u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */ - - u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */ - u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */ - u8 reserved1; /* CDM + 0x1e reg7 byte2 */ - u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */ - - u8 soft_reset; /* CDM + 0x20 u8 byte0 */ - u8 no_ckstp; /* CDM + 0x21 u8 byte0 */ - u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */ - - u8 pll_lock; /* CDM + 0x24 reg9 byte0 */ - u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */ - u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */ - u8 reserved3; /* CDM + 0x27 reg9 byte3 */ - - u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */ - u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */ - - u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */ - u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */ - - u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */ - u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */ - - u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */ - u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */ -}; - -#endif /* __ASSEMBLY__ */ - - -/* ========================================================================= */ -/* Prototypes for MPC52xx syslib */ -/* ========================================================================= */ - -#ifndef __ASSEMBLY__ - -extern void mpc52xx_init_irq(void); -extern int mpc52xx_get_irq(void); - -extern unsigned long mpc52xx_find_end_of_memory(void); -extern void mpc52xx_set_bat(void); -extern void mpc52xx_map_io(void); -extern void mpc52xx_restart(char *cmd); -extern void mpc52xx_halt(void); -extern void mpc52xx_power_off(void); -extern void mpc52xx_progress(char *s, unsigned short hex); -extern void mpc52xx_calibrate_decr(void); - -extern void mpc52xx_find_bridges(void); - -extern void mpc52xx_setup_cpu(void); - - - - /* Matching of PSC function */ -struct mpc52xx_psc_func { - int id; - char *func; -}; - -extern int mpc52xx_match_psc_function(int psc_idx, const char *func); -extern struct mpc52xx_psc_func mpc52xx_psc_functions[]; - /* This array is to be defined in platform file */ - -#endif /* __ASSEMBLY__ */ - - -/* ========================================================================= */ -/* Platform configuration */ -/* ========================================================================= */ - -/* The U-Boot platform information struct */ -extern bd_t __res; - -/* Platform options */ -#if defined(CONFIG_LITE5200) -#include -#endif - - -#endif /* __ASM_MPC52xx_H__ */ diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h deleted file mode 100644 index 39fcd02cd4e8..000000000000 --- a/include/asm-ppc/mpc52xx_psc.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - * include/asm-ppc/mpc52xx_psc.h - * - * Definitions of consts/structs to drive the Freescale MPC52xx OnChip - * PSCs. Theses are shared between multiple drivers since a PSC can be - * UART, AC97, IR, I2S, ... So this header is in asm-ppc. - * - * - * Maintainer : Sylvain Munaut - * - * Based/Extracted from some header of the 2.4 originally written by - * Dale Farnsworth - * - * Copyright (C) 2004 Sylvain Munaut - * Copyright (C) 2003 MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef __ASM_MPC52xx_PSC_H__ -#define __ASM_MPC52xx_PSC_H__ - -#include - -/* Max number of PSCs */ -#define MPC52xx_PSC_MAXNUM 6 - -/* Programmable Serial Controller (PSC) status register bits */ -#define MPC52xx_PSC_SR_UNEX_RX 0x0001 -#define MPC52xx_PSC_SR_DATA_VAL 0x0002 -#define MPC52xx_PSC_SR_DATA_OVR 0x0004 -#define MPC52xx_PSC_SR_CMDSEND 0x0008 -#define MPC52xx_PSC_SR_CDE 0x0080 -#define MPC52xx_PSC_SR_RXRDY 0x0100 -#define MPC52xx_PSC_SR_RXFULL 0x0200 -#define MPC52xx_PSC_SR_TXRDY 0x0400 -#define MPC52xx_PSC_SR_TXEMP 0x0800 -#define MPC52xx_PSC_SR_OE 0x1000 -#define MPC52xx_PSC_SR_PE 0x2000 -#define MPC52xx_PSC_SR_FE 0x4000 -#define MPC52xx_PSC_SR_RB 0x8000 - -/* PSC Command values */ -#define MPC52xx_PSC_RX_ENABLE 0x0001 -#define MPC52xx_PSC_RX_DISABLE 0x0002 -#define MPC52xx_PSC_TX_ENABLE 0x0004 -#define MPC52xx_PSC_TX_DISABLE 0x0008 -#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010 -#define MPC52xx_PSC_RST_RX 0x0020 -#define MPC52xx_PSC_RST_TX 0x0030 -#define MPC52xx_PSC_RST_ERR_STAT 0x0040 -#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050 -#define MPC52xx_PSC_START_BRK 0x0060 -#define MPC52xx_PSC_STOP_BRK 0x0070 - -/* PSC TxRx FIFO status bits */ -#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040 -#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020 -#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010 -#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008 -#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004 -#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002 -#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 - -/* PSC interrupt mask bits */ -#define MPC52xx_PSC_IMR_TXRDY 0x0100 -#define MPC52xx_PSC_IMR_RXRDY 0x0200 -#define MPC52xx_PSC_IMR_DB 0x0400 -#define MPC52xx_PSC_IMR_IPC 0x8000 - -/* PSC input port change bit */ -#define MPC52xx_PSC_CTS 0x01 -#define MPC52xx_PSC_DCD 0x02 -#define MPC52xx_PSC_D_CTS 0x10 -#define MPC52xx_PSC_D_DCD 0x20 - -/* PSC mode fields */ -#define MPC52xx_PSC_MODE_5_BITS 0x00 -#define MPC52xx_PSC_MODE_6_BITS 0x01 -#define MPC52xx_PSC_MODE_7_BITS 0x02 -#define MPC52xx_PSC_MODE_8_BITS 0x03 -#define MPC52xx_PSC_MODE_BITS_MASK 0x03 -#define MPC52xx_PSC_MODE_PAREVEN 0x00 -#define MPC52xx_PSC_MODE_PARODD 0x04 -#define MPC52xx_PSC_MODE_PARFORCE 0x08 -#define MPC52xx_PSC_MODE_PARNONE 0x10 -#define MPC52xx_PSC_MODE_ERR 0x20 -#define MPC52xx_PSC_MODE_FFULL 0x40 -#define MPC52xx_PSC_MODE_RXRTS 0x80 - -#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00 -#define MPC52xx_PSC_MODE_ONE_STOP 0x07 -#define MPC52xx_PSC_MODE_TWO_STOP 0x0f - -#define MPC52xx_PSC_RFNUM_MASK 0x01ff - - -/* Structure of the hardware registers */ -struct mpc52xx_psc { - u8 mode; /* PSC + 0x00 */ - u8 reserved0[3]; - union { /* PSC + 0x04 */ - u16 status; - u16 clock_select; - } sr_csr; -#define mpc52xx_psc_status sr_csr.status -#define mpc52xx_psc_clock_select sr_csr.clock_select - u16 reserved1; - u8 command; /* PSC + 0x08 */ - u8 reserved2[3]; - union { /* PSC + 0x0c */ - u8 buffer_8; - u16 buffer_16; - u32 buffer_32; - } buffer; -#define mpc52xx_psc_buffer_8 buffer.buffer_8 -#define mpc52xx_psc_buffer_16 buffer.buffer_16 -#define mpc52xx_psc_buffer_32 buffer.buffer_32 - union { /* PSC + 0x10 */ - u8 ipcr; - u8 acr; - } ipcr_acr; -#define mpc52xx_psc_ipcr ipcr_acr.ipcr -#define mpc52xx_psc_acr ipcr_acr.acr - u8 reserved3[3]; - union { /* PSC + 0x14 */ - u16 isr; - u16 imr; - } isr_imr; -#define mpc52xx_psc_isr isr_imr.isr -#define mpc52xx_psc_imr isr_imr.imr - u16 reserved4; - u8 ctur; /* PSC + 0x18 */ - u8 reserved5[3]; - u8 ctlr; /* PSC + 0x1c */ - u8 reserved6[3]; - u32 ccr; /* PSC + 0x20 */ - u32 ac97_slots; /* PSC + 0x24 */ - u32 ac97_cmd; /* PSC + 0x28 */ - u32 ac97_data; /* PSC + 0x2c */ - u8 ivr; /* PSC + 0x30 */ - u8 reserved8[3]; - u8 ip; /* PSC + 0x34 */ - u8 reserved9[3]; - u8 op1; /* PSC + 0x38 */ - u8 reserved10[3]; - u8 op0; /* PSC + 0x3c */ - u8 reserved11[3]; - u32 sicr; /* PSC + 0x40 */ - u8 ircr1; /* PSC + 0x44 */ - u8 reserved13[3]; - u8 ircr2; /* PSC + 0x44 */ - u8 reserved14[3]; - u8 irsdr; /* PSC + 0x4c */ - u8 reserved15[3]; - u8 irmdr; /* PSC + 0x50 */ - u8 reserved16[3]; - u8 irfdr; /* PSC + 0x54 */ - u8 reserved17[3]; -}; - -struct mpc52xx_psc_fifo { - u16 rfnum; /* PSC + 0x58 */ - u16 reserved18; - u16 tfnum; /* PSC + 0x5c */ - u16 reserved19; - u32 rfdata; /* PSC + 0x60 */ - u16 rfstat; /* PSC + 0x64 */ - u16 reserved20; - u8 rfcntl; /* PSC + 0x68 */ - u8 reserved21[5]; - u16 rfalarm; /* PSC + 0x6e */ - u16 reserved22; - u16 rfrptr; /* PSC + 0x72 */ - u16 reserved23; - u16 rfwptr; /* PSC + 0x76 */ - u16 reserved24; - u16 rflrfptr; /* PSC + 0x7a */ - u16 reserved25; - u16 rflwfptr; /* PSC + 0x7e */ - u32 tfdata; /* PSC + 0x80 */ - u16 tfstat; /* PSC + 0x84 */ - u16 reserved26; - u8 tfcntl; /* PSC + 0x88 */ - u8 reserved27[5]; - u16 tfalarm; /* PSC + 0x8e */ - u16 reserved28; - u16 tfrptr; /* PSC + 0x92 */ - u16 reserved29; - u16 tfwptr; /* PSC + 0x96 */ - u16 reserved30; - u16 tflrfptr; /* PSC + 0x9a */ - u16 reserved31; - u16 tflwfptr; /* PSC + 0x9e */ -}; - - -#endif /* __ASM_MPC52xx_PSC_H__ */ diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h deleted file mode 100644 index 402ba15c2e80..000000000000 --- a/include/asm-ppc/mpc8260.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Since there are many different boards and no standard configuration, - * we have a unique include file for each. Rather than change every - * file that has to include MPC8260 configuration, they all include - * this one and the configuration switching is done here. - */ -#ifdef __KERNEL__ -#ifndef __ASM_PPC_MPC8260_H__ -#define __ASM_PPC_MPC8260_H__ - - -#ifdef CONFIG_8260 - -#ifdef CONFIG_EST8260 -#include -#endif - -#ifdef CONFIG_SBC82xx -#include -#endif - -#ifdef CONFIG_SBS8260 -#include -#endif - -#ifdef CONFIG_RPX8260 -#include -#endif - -#ifdef CONFIG_WILLOW -#include -#endif - -#ifdef CONFIG_TQM8260 -#include -#endif - -#ifdef CONFIG_PCI_8260 -#include -#endif - -/* Make sure the memory translation stuff is there if PCI not used. - */ -#ifndef _IO_BASE -#define _IO_BASE 0 -#endif - -#ifndef _ISA_MEM_BASE -#define _ISA_MEM_BASE 0 -#endif - -#ifndef PCI_DRAM_OFFSET -#define PCI_DRAM_OFFSET 0 -#endif - -/* Map 256MB I/O region - */ -#ifndef IO_PHYS_ADDR -#define IO_PHYS_ADDR 0xe0000000 -#endif -#ifndef IO_VIRT_ADDR -#define IO_VIRT_ADDR IO_PHYS_ADDR -#endif - -enum ppc_sys_devices { - MPC82xx_CPM_FCC1, - MPC82xx_CPM_FCC2, - MPC82xx_CPM_FCC3, - MPC82xx_CPM_I2C, - MPC82xx_CPM_SCC1, - MPC82xx_CPM_SCC2, - MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, - MPC82xx_CPM_SPI, - MPC82xx_CPM_MCC1, - MPC82xx_CPM_MCC2, - MPC82xx_CPM_SMC1, - MPC82xx_CPM_SMC2, - MPC82xx_CPM_USB, - MPC82xx_SEC1, - MPC82xx_MDIO_BB, - NUM_PPC_SYS_DEVS, -}; - -#ifndef __ASSEMBLY__ -/* The "residual" data board information structure the boot loader - * hands to us. - */ -extern unsigned char __res[]; -#endif - -#ifndef BOARD_CHIP_NAME -#define BOARD_CHIP_NAME "" -#endif - -#endif /* CONFIG_8260 */ -#endif /* !__ASM_PPC_MPC8260_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc8260_pci9.h b/include/asm-ppc/mpc8260_pci9.h deleted file mode 100644 index 9f7176881c56..000000000000 --- a/include/asm-ppc/mpc8260_pci9.h +++ /dev/null @@ -1,47 +0,0 @@ -/* include/asm-ppc/mpc8260_pci9.h - * - * Undefine the PCI read* and in* macros so we can define them as functions - * that implement the workaround for the MPC8260 device erratum PCI 9. - * - * This header file should only be included at the end of include/asm-ppc/io.h - * and never included directly anywhere else. - * - * Author: andy_lowe@mvista.com - * - * 2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef _PPC_IO_H -#error "Do not include mpc8260_pci9.h directly." -#endif - -#ifdef __KERNEL__ -#ifndef __CONFIG_8260_PCI9_DEFS -#define __CONFIG_8260_PCI9_DEFS - -#undef readb -#undef readw -#undef readl -#undef insb -#undef insw -#undef insl -#undef inb -#undef inw -#undef inl -#undef memcpy_fromio - -extern int readb(volatile unsigned char *addr); -extern int readw(volatile unsigned short *addr); -extern unsigned readl(volatile unsigned *addr); -extern void insb(unsigned port, void *buf, int ns); -extern void insw(unsigned port, void *buf, int ns); -extern void insl(unsigned port, void *buf, int nl); -extern int inb(unsigned port); -extern int inw(unsigned port); -extern unsigned inl(unsigned port); -extern void *memcpy_fromio(void *dest, unsigned long src, size_t count); - -#endif /* !__CONFIG_8260_PCI9_DEFS */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h deleted file mode 100644 index b9e3060b0278..000000000000 --- a/include/asm-ppc/mpc8xx.h +++ /dev/null @@ -1,122 +0,0 @@ -/* This is the single file included by all MPC8xx build options. - * Since there are many different boards and no standard configuration, - * we have a unique include file for each. Rather than change every - * file that has to include MPC8xx configuration, they all include - * this one and the configuration switching is done here. - */ -#ifdef __KERNEL__ -#ifndef __CONFIG_8xx_DEFS -#define __CONFIG_8xx_DEFS - - -#ifdef CONFIG_8xx - -#ifdef CONFIG_MBX -#include -#endif - -#ifdef CONFIG_FADS -#include -#endif - -#ifdef CONFIG_RPXLITE -#include -#endif - -#ifdef CONFIG_BSEIP -#include -#endif - -#ifdef CONFIG_RPXCLASSIC -#include -#endif - -#if defined(CONFIG_TQM8xxL) -#include -#endif - -#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) -#include -#endif - -#if defined(CONFIG_HERMES_PRO) -#include -#endif - -#if defined(CONFIG_IP860) -#include -#endif - -#if defined(CONFIG_LWMON) -#include -#endif - -#if defined(CONFIG_PCU_E) -#include -#endif - -#if defined(CONFIG_CCM) -#include -#endif - -#if defined(CONFIG_LANTEC) -#include -#endif - -/* Currently, all 8xx boards that support a processor to PCI/ISA bridge - * use the same memory map. - */ -#if 0 -#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR) -#define _IO_BASE PCI_ISA_IO_ADDR -#define _ISA_MEM_BASE PCI_ISA_MEM_ADDR -#define PCI_DRAM_OFFSET 0x80000000 -#else -#define _IO_BASE 0 -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 -#endif -#else -#if !defined(_IO_BASE) /* defined in board specific header */ -#define _IO_BASE 0 -#endif -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 -#endif - -#ifndef __ASSEMBLY__ -/* The "residual" data board information structure the boot loader - * hands to us. - */ -extern unsigned char __res[]; - -struct pt_regs; - -enum ppc_sys_devices { - MPC8xx_CPM_FEC1, - MPC8xx_CPM_FEC2, - MPC8xx_CPM_I2C, - MPC8xx_CPM_SCC1, - MPC8xx_CPM_SCC2, - MPC8xx_CPM_SCC3, - MPC8xx_CPM_SCC4, - MPC8xx_CPM_SPI, - MPC8xx_CPM_MCC1, - MPC8xx_CPM_MCC2, - MPC8xx_CPM_SMC1, - MPC8xx_CPM_SMC2, - MPC8xx_CPM_USB, - MPC8xx_MDIO_FEC, - NUM_PPC_SYS_DEVS, -}; - -#define PPC_PIN_SIZE (24 * 1024 * 1024) /* 24Mbytes of data pinned */ - -#ifndef BOARD_CHIP_NAME -#define BOARD_CHIP_NAME "" -#endif - -#endif /* !__ASSEMBLY__ */ -#endif /* CONFIG_8xx */ -#endif /* __CONFIG_8xx_DEFS */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h deleted file mode 100644 index 2963d6aa3ea5..000000000000 --- a/include/asm-ppc/mv64x60.h +++ /dev/null @@ -1,353 +0,0 @@ -/* - * include/asm-ppc/mv64x60.h - * - * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines. - * - * Author: Mark A. Greer - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASMPPC_MV64x60_H -#define __ASMPPC_MV64x60_H - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -struct platform_device; - -extern u8 mv64x60_pci_exclude_bridge; - -extern spinlock_t mv64x60_lock; - -/* 32-bit Window table entry defines */ -#define MV64x60_CPU2MEM_0_WIN 0 -#define MV64x60_CPU2MEM_1_WIN 1 -#define MV64x60_CPU2MEM_2_WIN 2 -#define MV64x60_CPU2MEM_3_WIN 3 -#define MV64x60_CPU2DEV_0_WIN 4 -#define MV64x60_CPU2DEV_1_WIN 5 -#define MV64x60_CPU2DEV_2_WIN 6 -#define MV64x60_CPU2DEV_3_WIN 7 -#define MV64x60_CPU2BOOT_WIN 8 -#define MV64x60_CPU2PCI0_IO_WIN 9 -#define MV64x60_CPU2PCI0_MEM_0_WIN 10 -#define MV64x60_CPU2PCI0_MEM_1_WIN 11 -#define MV64x60_CPU2PCI0_MEM_2_WIN 12 -#define MV64x60_CPU2PCI0_MEM_3_WIN 13 -#define MV64x60_CPU2PCI1_IO_WIN 14 -#define MV64x60_CPU2PCI1_MEM_0_WIN 15 -#define MV64x60_CPU2PCI1_MEM_1_WIN 16 -#define MV64x60_CPU2PCI1_MEM_2_WIN 17 -#define MV64x60_CPU2PCI1_MEM_3_WIN 18 -#define MV64x60_CPU2SRAM_WIN 19 -#define MV64x60_CPU2PCI0_IO_REMAP_WIN 20 -#define MV64x60_CPU2PCI1_IO_REMAP_WIN 21 -#define MV64x60_CPU_PROT_0_WIN 22 -#define MV64x60_CPU_PROT_1_WIN 23 -#define MV64x60_CPU_PROT_2_WIN 24 -#define MV64x60_CPU_PROT_3_WIN 25 -#define MV64x60_CPU_SNOOP_0_WIN 26 -#define MV64x60_CPU_SNOOP_1_WIN 27 -#define MV64x60_CPU_SNOOP_2_WIN 28 -#define MV64x60_CPU_SNOOP_3_WIN 29 -#define MV64x60_PCI02MEM_REMAP_0_WIN 30 -#define MV64x60_PCI02MEM_REMAP_1_WIN 31 -#define MV64x60_PCI02MEM_REMAP_2_WIN 32 -#define MV64x60_PCI02MEM_REMAP_3_WIN 33 -#define MV64x60_PCI12MEM_REMAP_0_WIN 34 -#define MV64x60_PCI12MEM_REMAP_1_WIN 35 -#define MV64x60_PCI12MEM_REMAP_2_WIN 36 -#define MV64x60_PCI12MEM_REMAP_3_WIN 37 -#define MV64x60_ENET2MEM_0_WIN 38 -#define MV64x60_ENET2MEM_1_WIN 39 -#define MV64x60_ENET2MEM_2_WIN 40 -#define MV64x60_ENET2MEM_3_WIN 41 -#define MV64x60_ENET2MEM_4_WIN 42 -#define MV64x60_ENET2MEM_5_WIN 43 -#define MV64x60_MPSC2MEM_0_WIN 44 -#define MV64x60_MPSC2MEM_1_WIN 45 -#define MV64x60_MPSC2MEM_2_WIN 46 -#define MV64x60_MPSC2MEM_3_WIN 47 -#define MV64x60_IDMA2MEM_0_WIN 48 -#define MV64x60_IDMA2MEM_1_WIN 49 -#define MV64x60_IDMA2MEM_2_WIN 50 -#define MV64x60_IDMA2MEM_3_WIN 51 -#define MV64x60_IDMA2MEM_4_WIN 52 -#define MV64x60_IDMA2MEM_5_WIN 53 -#define MV64x60_IDMA2MEM_6_WIN 54 -#define MV64x60_IDMA2MEM_7_WIN 55 - -#define MV64x60_32BIT_WIN_COUNT 56 - -/* 64-bit Window table entry defines */ -#define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN 0 -#define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN 1 -#define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN 2 -#define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN 3 -#define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN 4 -#define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN 5 -#define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN 6 -#define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN 7 -#define MV64x60_PCI02MEM_ACC_CNTL_0_WIN 8 -#define MV64x60_PCI02MEM_ACC_CNTL_1_WIN 9 -#define MV64x60_PCI02MEM_ACC_CNTL_2_WIN 10 -#define MV64x60_PCI02MEM_ACC_CNTL_3_WIN 11 -#define MV64x60_PCI12MEM_ACC_CNTL_0_WIN 12 -#define MV64x60_PCI12MEM_ACC_CNTL_1_WIN 13 -#define MV64x60_PCI12MEM_ACC_CNTL_2_WIN 14 -#define MV64x60_PCI12MEM_ACC_CNTL_3_WIN 15 -#define MV64x60_PCI02MEM_SNOOP_0_WIN 16 -#define MV64x60_PCI02MEM_SNOOP_1_WIN 17 -#define MV64x60_PCI02MEM_SNOOP_2_WIN 18 -#define MV64x60_PCI02MEM_SNOOP_3_WIN 19 -#define MV64x60_PCI12MEM_SNOOP_0_WIN 20 -#define MV64x60_PCI12MEM_SNOOP_1_WIN 21 -#define MV64x60_PCI12MEM_SNOOP_2_WIN 22 -#define MV64x60_PCI12MEM_SNOOP_3_WIN 23 - -#define MV64x60_64BIT_WIN_COUNT 24 - -/* - * Define a structure that's used to pass in config information to the - * core routines. - */ -struct mv64x60_pci_window { - u32 cpu_base; - u32 pci_base_hi; - u32 pci_base_lo; - u32 size; - u32 swap; -}; - -struct mv64x60_pci_info { - u8 enable_bus; /* allow access to this PCI bus? */ - - struct mv64x60_pci_window pci_io; - struct mv64x60_pci_window pci_mem[3]; - - u32 acc_cntl_options[MV64x60_CPU2MEM_WINDOWS]; - u32 snoop_options[MV64x60_CPU2MEM_WINDOWS]; - u16 pci_cmd_bits; - u16 latency_timer; -}; - -struct mv64x60_setup_info { - u32 phys_reg_base; - u32 window_preserve_mask_32_hi; - u32 window_preserve_mask_32_lo; - u32 window_preserve_mask_64; - - u32 cpu_prot_options[MV64x60_CPU2MEM_WINDOWS]; - u32 cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS]; - u32 enet_options[MV64x60_CPU2MEM_WINDOWS]; - u32 mpsc_options[MV64x60_CPU2MEM_WINDOWS]; - u32 idma_options[MV64x60_CPU2MEM_WINDOWS]; - - struct mv64x60_pci_info pci_0; - struct mv64x60_pci_info pci_1; -}; - -/* Define what the top bits in the extra member of a window entry means. */ -#define MV64x60_EXTRA_INVALID 0x00000000 -#define MV64x60_EXTRA_CPUWIN_ENAB 0x10000000 -#define MV64x60_EXTRA_CPUPROT_ENAB 0x20000000 -#define MV64x60_EXTRA_ENET_ENAB 0x30000000 -#define MV64x60_EXTRA_MPSC_ENAB 0x40000000 -#define MV64x60_EXTRA_IDMA_ENAB 0x50000000 -#define MV64x60_EXTRA_PCIACC_ENAB 0x60000000 - -#define MV64x60_EXTRA_MASK 0xf0000000 - -/* - * Define the 'handle' struct that will be passed between the 64x60 core - * code and the platform-specific code that will use it. The handle - * will contain pointers to chip-specific routines & information. - */ -struct mv64x60_32bit_window { - u32 base_reg; - u32 size_reg; - u8 base_bits; - u8 size_bits; - u32 (*get_from_field)(u32 val, u32 num_bits); - u32 (*map_to_field)(u32 val, u32 num_bits); - u32 extra; -}; - -struct mv64x60_64bit_window { - u32 base_hi_reg; - u32 base_lo_reg; - u32 size_reg; - u8 base_lo_bits; - u8 size_bits; - u32 (*get_from_field)(u32 val, u32 num_bits); - u32 (*map_to_field)(u32 val, u32 num_bits); - u32 extra; -}; - -typedef struct mv64x60_handle mv64x60_handle_t; -struct mv64x60_chip_info { - u32 (*translate_size)(u32 base, u32 size, u32 num_bits); - u32 (*untranslate_size)(u32 base, u32 size, u32 num_bits); - void (*set_pci2mem_window)(struct pci_controller *hose, u32 bus, - u32 window, u32 base); - void (*set_pci2regs_window)(struct mv64x60_handle *bh, - struct pci_controller *hose, u32 bus, u32 base); - u32 (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window); - void (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window); - void (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window); - void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window); - void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window); - void (*disable_all_windows)(mv64x60_handle_t *bh, - struct mv64x60_setup_info *si); - void (*config_io2mem_windows)(mv64x60_handle_t *bh, - struct mv64x60_setup_info *si, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); - void (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base); - void (*chip_specific_init)(mv64x60_handle_t *bh, - struct mv64x60_setup_info *si); - - struct mv64x60_32bit_window *window_tab_32bit; - struct mv64x60_64bit_window *window_tab_64bit; -}; - -struct mv64x60_handle { - u32 type; /* type of bridge */ - u32 rev; /* revision of bridge */ - void __iomem *v_base;/* virtual base addr of bridge regs */ - phys_addr_t p_base; /* physical base addr of bridge regs */ - - u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/ - u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/ - - u32 io_base_a; /* vaddr of pci 0's I/O space */ - u32 io_base_b; /* vaddr of pci 1's I/O space */ - - struct pci_controller *hose_a; - struct pci_controller *hose_b; - - struct mv64x60_chip_info *ci; /* chip/bridge-specific info */ -}; - - -/* Define I/O routines for accessing registers on the 64x60 bridge. */ -extern inline void -mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) { - ulong flags; - - spin_lock_irqsave(&mv64x60_lock, flags); - out_le32(bh->v_base + offset, val); - spin_unlock_irqrestore(&mv64x60_lock, flags); -} - -extern inline u32 -mv64x60_read(struct mv64x60_handle *bh, u32 offset) { - ulong flags; - u32 reg; - - spin_lock_irqsave(&mv64x60_lock, flags); - reg = in_le32(bh->v_base + offset); - spin_unlock_irqrestore(&mv64x60_lock, flags); - return reg; -} - -extern inline void -mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask) -{ - u32 reg; - ulong flags; - - spin_lock_irqsave(&mv64x60_lock, flags); - reg = in_le32(bh->v_base + offs) & (~mask); - reg |= data & mask; - out_le32(bh->v_base + offs, reg); - spin_unlock_irqrestore(&mv64x60_lock, flags); -} - -#define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits) -#define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits) - -#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) -#define MV64XXX_DEV_NAME "mv64xxx" - -struct mv64xxx_pdata { - u32 hs_reg_valid; -}; -#endif - -/* Externally visible function prototypes */ -int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si); -u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type); -void mv64x60_early_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si); -void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, - u32 cfg_data, struct pci_controller **hose); -int mv64x60_get_type(struct mv64x60_handle *bh); -int mv64x60_setup_for_chip(struct mv64x60_handle *bh); -void __iomem *mv64x60_get_bridge_vbase(void); -u32 mv64x60_get_bridge_type(void); -u32 mv64x60_get_bridge_rev(void); -void mv64x60_get_mem_windows(struct mv64x60_handle *bh, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); -void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); -void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, - struct mv64x60_pci_info *pi, u32 bus); -void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh, - struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); -void mv64x60_config_resources(struct pci_controller *hose, - struct mv64x60_pci_info *pi, u32 io_base); -void mv64x60_config_pci_params(struct pci_controller *hose, - struct mv64x60_pci_info *pi); -void mv64x60_pd_fixup(struct mv64x60_handle *bh, - struct platform_device *pd_devs[], u32 entries); -void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window, - u32 *base, u32 *size); -void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base, - u32 size, u32 other_bits); -void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, - u32 *base_hi, u32 *base_lo, u32 *size); -void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window, - u32 base_hi, u32 base_lo, u32 size, u32 other_bits); -void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus); -int mv64x60_pci_exclude_device(u8 bus, u8 devfn); - - -void gt64260_init_irq(void); -int gt64260_get_irq(void); -void mv64360_init_irq(void); -int mv64360_get_irq(void); - -u32 mv64x60_mask(u32 val, u32 num_bits); -u32 mv64x60_shift_left(u32 val, u32 num_bits); -u32 mv64x60_shift_right(u32 val, u32 num_bits); -u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); - -void mv64x60_progress_init(u32 base); -void mv64x60_mpsc_progress(char *s, unsigned short hex); - -extern struct mv64x60_32bit_window - gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT]; -extern struct mv64x60_64bit_window - gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT]; -extern struct mv64x60_32bit_window - mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT]; -extern struct mv64x60_64bit_window - mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT]; - -#endif /* __ASMPPC_MV64x60_H */ diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h deleted file mode 100644 index 5b0704a3e6ea..000000000000 --- a/include/asm-ppc/mv64x60_defs.h +++ /dev/null @@ -1,976 +0,0 @@ -/* - * include/asm-ppc/mv64x60_defs.h - * - * Register definitions for the Marvell/Galileo GT64260, MV64360, etc. - * host bridges. - * - * Author: Mark A. Greer - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASMPPC_MV64x60_DEFS_H -#define __ASMPPC_MV64x60_DEFS_H - -/* - * Define the Marvell bridges that are supported - */ -#define MV64x60_TYPE_INVALID 0 -#define MV64x60_TYPE_GT64260A 1 -#define MV64x60_TYPE_GT64260B 2 -#define MV64x60_TYPE_MV64360 3 -#define MV64x60_TYPE_MV64361 4 -#define MV64x60_TYPE_MV64362 5 -#define MV64x60_TYPE_MV64460 6 - - -/* Revisions of each supported chip */ -#define GT64260_REV_A 0x10 -#define GT64260_REV_B 0x20 -#define MV64360 0x01 -#define MV64460 0x01 - -/* Minimum window size supported by 64260 is 1MB */ -#define GT64260_WINDOW_SIZE_MIN 0x00100000 -#define MV64360_WINDOW_SIZE_MIN 0x00010000 - -#define MV64x60_TCLK_FREQ_MAX 133333333U - -/* IRQ's for embedded controllers */ -#define MV64x60_IRQ_DEV 1 -#define MV64x60_IRQ_CPU_ERR 3 -#define MV64x60_IRQ_TIMER_0_1 8 -#define MV64x60_IRQ_TIMER_2_3 9 -#define MV64x60_IRQ_TIMER_4_5 10 -#define MV64x60_IRQ_TIMER_6_7 11 -#define MV64x60_IRQ_P1_GPP_0_7 24 -#define MV64x60_IRQ_P1_GPP_8_15 25 -#define MV64x60_IRQ_P1_GPP_16_23 26 -#define MV64x60_IRQ_P1_GPP_24_31 27 -#define MV64x60_IRQ_DOORBELL 28 -#define MV64x60_IRQ_ETH_0 32 -#define MV64x60_IRQ_ETH_1 33 -#define MV64x60_IRQ_ETH_2 34 -#define MV64x60_IRQ_SDMA_0 36 -#define MV64x60_IRQ_I2C 37 -#define MV64x60_IRQ_BRG 39 -#define MV64x60_IRQ_MPSC_0 40 -#define MV64x60_IRQ_MPSC_1 42 -#define MV64x60_IRQ_COMM 43 -#define MV64x60_IRQ_P0_GPP_0_7 56 -#define MV64x60_IRQ_P0_GPP_8_15 57 -#define MV64x60_IRQ_P0_GPP_16_23 58 -#define MV64x60_IRQ_P0_GPP_24_31 59 - -#define MV64360_IRQ_PCI0 12 -#define MV64360_IRQ_SRAM_PAR_ERR 13 -#define MV64360_IRQ_PCI1 16 -#define MV64360_IRQ_SDMA_1 38 - -#define MV64x60_IRQ_GPP0 64 -#define MV64x60_IRQ_GPP1 65 -#define MV64x60_IRQ_GPP2 66 -#define MV64x60_IRQ_GPP3 67 -#define MV64x60_IRQ_GPP4 68 -#define MV64x60_IRQ_GPP5 69 -#define MV64x60_IRQ_GPP6 70 -#define MV64x60_IRQ_GPP7 71 -#define MV64x60_IRQ_GPP8 72 -#define MV64x60_IRQ_GPP9 73 -#define MV64x60_IRQ_GPP10 74 -#define MV64x60_IRQ_GPP11 75 -#define MV64x60_IRQ_GPP12 76 -#define MV64x60_IRQ_GPP13 77 -#define MV64x60_IRQ_GPP14 78 -#define MV64x60_IRQ_GPP15 79 -#define MV64x60_IRQ_GPP16 80 -#define MV64x60_IRQ_GPP17 81 -#define MV64x60_IRQ_GPP18 82 -#define MV64x60_IRQ_GPP19 83 -#define MV64x60_IRQ_GPP20 84 -#define MV64x60_IRQ_GPP21 85 -#define MV64x60_IRQ_GPP22 86 -#define MV64x60_IRQ_GPP23 87 -#define MV64x60_IRQ_GPP24 88 -#define MV64x60_IRQ_GPP25 89 -#define MV64x60_IRQ_GPP26 90 -#define MV64x60_IRQ_GPP27 91 -#define MV64x60_IRQ_GPP28 92 -#define MV64x60_IRQ_GPP29 93 -#define MV64x60_IRQ_GPP30 94 -#define MV64x60_IRQ_GPP31 95 - -/* Offsets for register blocks */ -#define GT64260_ENET_PHY_ADDR 0x2000 -#define GT64260_ENET_ESMIR 0x2010 -#define GT64260_ENET_0_OFFSET 0x2400 -#define GT64260_ENET_1_OFFSET 0x2800 -#define GT64260_ENET_2_OFFSET 0x2c00 -#define MV64x60_SDMA_0_OFFSET 0x4000 -#define MV64x60_SDMA_1_OFFSET 0x6000 -#define MV64x60_MPSC_0_OFFSET 0x8000 -#define MV64x60_MPSC_1_OFFSET 0x9000 -#define MV64x60_MPSC_ROUTING_OFFSET 0xb400 -#define MV64x60_SDMA_INTR_OFFSET 0xb800 -#define MV64x60_BRG_0_OFFSET 0xb200 -#define MV64x60_BRG_1_OFFSET 0xb208 - -/* - ***************************************************************************** - * - * CPU Interface Registers - * - ***************************************************************************** - */ - -/* CPU physical address of bridge's registers */ -#define MV64x60_INTERNAL_SPACE_DECODE 0x0068 -#define MV64x60_INTERNAL_SPACE_SIZE 0x10000 -#define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000 - -#define MV64360_CPU_BAR_ENABLE 0x0278 - -/* CPU Memory Controller Window Registers (4 windows) */ -#define MV64x60_CPU2MEM_WINDOWS 4 - -#define MV64x60_CPU2MEM_0_BASE 0x0008 -#define MV64x60_CPU2MEM_0_SIZE 0x0010 -#define MV64x60_CPU2MEM_1_BASE 0x0208 -#define MV64x60_CPU2MEM_1_SIZE 0x0210 -#define MV64x60_CPU2MEM_2_BASE 0x0018 -#define MV64x60_CPU2MEM_2_SIZE 0x0020 -#define MV64x60_CPU2MEM_3_BASE 0x0218 -#define MV64x60_CPU2MEM_3_SIZE 0x0220 - -/* CPU Device Controller Window Registers (4 windows) */ -#define MV64x60_CPU2DEV_WINDOWS 4 - -#define MV64x60_CPU2DEV_0_BASE 0x0028 -#define MV64x60_CPU2DEV_0_SIZE 0x0030 -#define MV64x60_CPU2DEV_1_BASE 0x0228 -#define MV64x60_CPU2DEV_1_SIZE 0x0230 -#define MV64x60_CPU2DEV_2_BASE 0x0248 -#define MV64x60_CPU2DEV_2_SIZE 0x0250 -#define MV64x60_CPU2DEV_3_BASE 0x0038 -#define MV64x60_CPU2DEV_3_SIZE 0x0040 - -#define MV64x60_CPU2BOOT_0_BASE 0x0238 -#define MV64x60_CPU2BOOT_0_SIZE 0x0240 - -#define MV64360_CPU2SRAM_BASE 0x0268 - -/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */ -#define MV64x60_PCI_BUSES 2 -#define MV64x60_PCI_IO_WINDOWS_PER_BUS 1 -#define MV64x60_PCI_MEM_WINDOWS_PER_BUS 4 - -#define MV64x60_CPU2PCI_SWAP_BYTE 0x00000000 -#define MV64x60_CPU2PCI_SWAP_NONE 0x01000000 -#define MV64x60_CPU2PCI_SWAP_BYTE_WORD 0x02000000 -#define MV64x60_CPU2PCI_SWAP_WORD 0x03000000 - -#define MV64x60_CPU2PCI_MEM_REQ64 (1<<27) - -#define MV64x60_CPU2PCI0_IO_BASE 0x0048 -#define MV64x60_CPU2PCI0_IO_SIZE 0x0050 -#define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058 -#define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060 -#define MV64x60_CPU2PCI0_MEM_1_BASE 0x0080 -#define MV64x60_CPU2PCI0_MEM_1_SIZE 0x0088 -#define MV64x60_CPU2PCI0_MEM_2_BASE 0x0258 -#define MV64x60_CPU2PCI0_MEM_2_SIZE 0x0260 -#define MV64x60_CPU2PCI0_MEM_3_BASE 0x0280 -#define MV64x60_CPU2PCI0_MEM_3_SIZE 0x0288 - -#define MV64x60_CPU2PCI0_IO_REMAP 0x00f0 -#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8 -#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320 -#define MV64x60_CPU2PCI0_MEM_1_REMAP_LO 0x0100 -#define MV64x60_CPU2PCI0_MEM_1_REMAP_HI 0x0328 -#define MV64x60_CPU2PCI0_MEM_2_REMAP_LO 0x02f8 -#define MV64x60_CPU2PCI0_MEM_2_REMAP_HI 0x0330 -#define MV64x60_CPU2PCI0_MEM_3_REMAP_LO 0x0300 -#define MV64x60_CPU2PCI0_MEM_3_REMAP_HI 0x0338 - -#define MV64x60_CPU2PCI1_IO_BASE 0x0090 -#define MV64x60_CPU2PCI1_IO_SIZE 0x0098 -#define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0 -#define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8 -#define MV64x60_CPU2PCI1_MEM_1_BASE 0x00b0 -#define MV64x60_CPU2PCI1_MEM_1_SIZE 0x00b8 -#define MV64x60_CPU2PCI1_MEM_2_BASE 0x02a0 -#define MV64x60_CPU2PCI1_MEM_2_SIZE 0x02a8 -#define MV64x60_CPU2PCI1_MEM_3_BASE 0x02b0 -#define MV64x60_CPU2PCI1_MEM_3_SIZE 0x02b8 - -#define MV64x60_CPU2PCI1_IO_REMAP 0x0108 -#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110 -#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340 -#define MV64x60_CPU2PCI1_MEM_1_REMAP_LO 0x0118 -#define MV64x60_CPU2PCI1_MEM_1_REMAP_HI 0x0348 -#define MV64x60_CPU2PCI1_MEM_2_REMAP_LO 0x0310 -#define MV64x60_CPU2PCI1_MEM_2_REMAP_HI 0x0350 -#define MV64x60_CPU2PCI1_MEM_3_REMAP_LO 0x0318 -#define MV64x60_CPU2PCI1_MEM_3_REMAP_HI 0x0358 - -/* CPU Control Registers */ -#define MV64x60_CPU_CONFIG 0x0000 -#define MV64x60_CPU_MODE 0x0120 -#define MV64x60_CPU_MASTER_CNTL 0x0160 -#define MV64x60_CPU_XBAR_CNTL_LO 0x0150 -#define MV64x60_CPU_XBAR_CNTL_HI 0x0158 -#define MV64x60_CPU_XBAR_TO 0x0168 - -#define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170 -#define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178 - -#define MV64360_CPU_PADS_CALIBRATION 0x03b4 -#define MV64360_CPU_RESET_SAMPLE_LO 0x03c4 -#define MV64360_CPU_RESET_SAMPLE_HI 0x03d4 - -/* SMP Register Map */ -#define MV64360_WHO_AM_I 0x0200 -#define MV64360_CPU0_DOORBELL 0x0214 -#define MV64360_CPU0_DOORBELL_CLR 0x021c -#define MV64360_CPU0_DOORBELL_MASK 0x0234 -#define MV64360_CPU1_DOORBELL 0x0224 -#define MV64360_CPU1_DOORBELL_CLR 0x022c -#define MV64360_CPU1_DOORBELL_MASK 0x023c -#define MV64360_CPUx_DOORBELL(x) (0x0214 + ((x)*0x10)) -#define MV64360_CPUx_DOORBELL_CLR(x) (0x021c + ((x)*0x10)) -#define MV64360_CPUx_DOORBELL_MASK(x) (0x0234 + ((x)*0x08)) -#define MV64360_SEMAPHORE_0 0x0244 -#define MV64360_SEMAPHORE_1 0x024c -#define MV64360_SEMAPHORE_2 0x0254 -#define MV64360_SEMAPHORE_3 0x025c -#define MV64360_SEMAPHORE_4 0x0264 -#define MV64360_SEMAPHORE_5 0x026c -#define MV64360_SEMAPHORE_6 0x0274 -#define MV64360_SEMAPHORE_7 0x027c - -/* CPU Sync Barrier Registers */ -#define GT64260_CPU_SYNC_BARRIER_PCI0 0x00c0 -#define GT64260_CPU_SYNC_BARRIER_PCI1 0x00c8 - -#define MV64360_CPU0_SYNC_BARRIER_TRIG 0x00c0 -#define MV64360_CPU0_SYNC_BARRIER_VIRT 0x00c8 -#define MV64360_CPU1_SYNC_BARRIER_TRIG 0x00d0 -#define MV64360_CPU1_SYNC_BARRIER_VIRT 0x00d8 - -/* CPU Deadlock and Ordering registers (Rev B part only) */ -#define GT64260_CPU_DEADLOCK_ORDERING 0x02d0 -#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8 -#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0 - -/* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */ -#define MV64x260_CPU_PROT_WINDOWS 4 - -#define GT64260_CPU_PROT_ACCPROTECT (1<<16) -#define GT64260_CPU_PROT_WRPROTECT (1<<17) -#define GT64260_CPU_PROT_CACHEPROTECT (1<<18) - -#define MV64360_CPU_PROT_ACCPROTECT (1<<20) -#define MV64360_CPU_PROT_WRPROTECT (1<<21) -#define MV64360_CPU_PROT_CACHEPROTECT (1<<22) -#define MV64360_CPU_PROT_WIN_ENABLE (1<<31) - -#define MV64x60_CPU_PROT_BASE_0 0x0180 -#define MV64x60_CPU_PROT_SIZE_0 0x0188 -#define MV64x60_CPU_PROT_BASE_1 0x0190 -#define MV64x60_CPU_PROT_SIZE_1 0x0198 -#define MV64x60_CPU_PROT_BASE_2 0x01a0 -#define MV64x60_CPU_PROT_SIZE_2 0x01a8 -#define MV64x60_CPU_PROT_BASE_3 0x01b0 -#define MV64x60_CPU_PROT_SIZE_3 0x01b8 - -#define GT64260_CPU_PROT_BASE_4 0x01c0 -#define GT64260_CPU_PROT_SIZE_4 0x01c8 -#define GT64260_CPU_PROT_BASE_5 0x01d0 -#define GT64260_CPU_PROT_SIZE_5 0x01d8 -#define GT64260_CPU_PROT_BASE_6 0x01e0 -#define GT64260_CPU_PROT_SIZE_6 0x01e8 -#define GT64260_CPU_PROT_BASE_7 0x01f0 -#define GT64260_CPU_PROT_SIZE_7 0x01f8 - -/* CPU Snoop Control Registers (64260 only) */ -#define GT64260_CPU_SNOOP_WINDOWS 4 - -#define GT64260_CPU_SNOOP_NONE 0x00000000 -#define GT64260_CPU_SNOOP_WT 0x00010000 -#define GT64260_CPU_SNOOP_WB 0x00020000 -#define GT64260_CPU_SNOOP_MASK 0x00030000 -#define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK - -#define GT64260_CPU_SNOOP_BASE_0 0x0380 -#define GT64260_CPU_SNOOP_SIZE_0 0x0388 -#define GT64260_CPU_SNOOP_BASE_1 0x0390 -#define GT64260_CPU_SNOOP_SIZE_1 0x0398 -#define GT64260_CPU_SNOOP_BASE_2 0x03a0 -#define GT64260_CPU_SNOOP_SIZE_2 0x03a8 -#define GT64260_CPU_SNOOP_BASE_3 0x03b0 -#define GT64260_CPU_SNOOP_SIZE_3 0x03b8 - -/* CPU Snoop Control Registers (64360 only) */ -#define MV64360_CPU_SNOOP_WINDOWS 4 -#define MV64360_CPU_SNOOP_NONE 0x00000000 -#define MV64360_CPU_SNOOP_WT 0x00010000 -#define MV64360_CPU_SNOOP_WB 0x00020000 -#define MV64360_CPU_SNOOP_MASK 0x00030000 -#define MV64360_CPU_SNOOP_ALL_BITS MV64360_CPU_SNOOP_MASK - - -/* CPU Error Report Registers */ -#define MV64x60_CPU_ERR_ADDR_LO 0x0070 -#define MV64x60_CPU_ERR_ADDR_HI 0x0078 -#define MV64x60_CPU_ERR_DATA_LO 0x0128 -#define MV64x60_CPU_ERR_DATA_HI 0x0130 -#define MV64x60_CPU_ERR_PARITY 0x0138 -#define MV64x60_CPU_ERR_CAUSE 0x0140 -#define MV64x60_CPU_ERR_MASK 0x0148 - -/* - ***************************************************************************** - * - * SRAM Controller Registers - * - ***************************************************************************** - */ - -#define MV64360_SRAM_CONFIG 0x0380 -#define MV64360_SRAM_TEST_MODE 0x03f4 -#define MV64360_SRAM_ERR_CAUSE 0x0388 -#define MV64360_SRAM_ERR_ADDR_LO 0x0390 -#define MV64360_SRAM_ERR_ADDR_HI 0x03f8 -#define MV64360_SRAM_ERR_DATA_LO 0x0398 -#define MV64360_SRAM_ERR_DATA_HI 0x03a0 -#define MV64360_SRAM_ERR_PARITY 0x03a8 - -#define MV64360_SRAM_SIZE 0x00040000 /* 2Mb/256KB SRAM */ - -/* - ***************************************************************************** - * - * SDRAM/MEM Controller Registers - * - ***************************************************************************** - */ - -/* SDRAM Config Registers (64260) */ -#define GT64260_SDRAM_CONFIG 0x0448 - -/* SDRAM Error Report Registers (64260) */ -#define GT64260_SDRAM_ERR_DATA_LO 0x0484 -#define GT64260_SDRAM_ERR_DATA_HI 0x0480 -#define GT64260_SDRAM_ERR_ADDR 0x0490 -#define GT64260_SDRAM_ERR_ECC_RCVD 0x0488 -#define GT64260_SDRAM_ERR_ECC_CALC 0x048c -#define GT64260_SDRAM_ERR_ECC_CNTL 0x0494 -#define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498 - -/* SDRAM Config Registers (64360) */ -#define MV64360_SDRAM_CONFIG 0x1400 - -/* SDRAM Control Registers */ -#define MV64360_D_UNIT_CONTROL_LOW 0x1404 -#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64460_D_UNIT_MMASK 0x14b0 - -/* SDRAM Error Report Registers (64360) */ -#define MV64360_SDRAM_ERR_DATA_LO 0x1444 -#define MV64360_SDRAM_ERR_DATA_HI 0x1440 -#define MV64360_SDRAM_ERR_ADDR 0x1450 -#define MV64360_SDRAM_ERR_ECC_RCVD 0x1448 -#define MV64360_SDRAM_ERR_ECC_CALC 0x144c -#define MV64360_SDRAM_ERR_ECC_CNTL 0x1454 -#define MV64360_SDRAM_ERR_ECC_ERR_CNT 0x1458 - -/* - ***************************************************************************** - * - * Device/BOOT Controller Registers - * - ***************************************************************************** - */ - -/* Device Control Registers */ -#define MV64x60_DEV_BANK_PARAMS_0 0x045c -#define MV64x60_DEV_BANK_PARAMS_1 0x0460 -#define MV64x60_DEV_BANK_PARAMS_2 0x0464 -#define MV64x60_DEV_BANK_PARAMS_3 0x0468 -#define MV64x60_DEV_BOOT_PARAMS 0x046c -#define MV64x60_DEV_IF_CNTL 0x04c0 -#define MV64x60_DEV_IF_XBAR_CNTL_LO 0x04c8 -#define MV64x60_DEV_IF_XBAR_CNTL_HI 0x04cc -#define MV64x60_DEV_IF_XBAR_CNTL_TO 0x04c4 - -/* Device Interrupt Registers */ -#define MV64x60_DEV_INTR_CAUSE 0x04d0 -#define MV64x60_DEV_INTR_MASK 0x04d4 -#define MV64x60_DEV_INTR_ERR_ADDR 0x04d8 - -#define MV64360_DEV_INTR_ERR_DATA 0x04dc -#define MV64360_DEV_INTR_ERR_PAR 0x04e0 - -/* - ***************************************************************************** - * - * PCI Bridge Interface Registers - * - ***************************************************************************** - */ - -/* PCI Configuration Access Registers */ -#define MV64x60_PCI0_CONFIG_ADDR 0x0cf8 -#define MV64x60_PCI0_CONFIG_DATA 0x0cfc -#define MV64x60_PCI0_IACK 0x0c34 - -#define MV64x60_PCI1_CONFIG_ADDR 0x0c78 -#define MV64x60_PCI1_CONFIG_DATA 0x0c7c -#define MV64x60_PCI1_IACK 0x0cb4 - -/* PCI Control Registers */ -#define MV64x60_PCI0_CMD 0x0c00 -#define MV64x60_PCI0_MODE 0x0d00 -#define MV64x60_PCI0_TO_RETRY 0x0c04 -#define MV64x60_PCI0_RD_BUF_DISCARD_TIMER 0x0d04 -#define MV64x60_PCI0_MSI_TRIGGER_TIMER 0x0c38 -#define MV64x60_PCI0_ARBITER_CNTL 0x1d00 -#define MV64x60_PCI0_XBAR_CNTL_LO 0x1d08 -#define MV64x60_PCI0_XBAR_CNTL_HI 0x1d0c -#define MV64x60_PCI0_XBAR_CNTL_TO 0x1d04 -#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO 0x1d18 -#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI 0x1d1c -#define MV64x60_PCI0_SYNC_BARRIER 0x1d10 -#define MV64x60_PCI0_P2P_CONFIG 0x1d14 -#define MV64x60_PCI0_INTR_MASK - -#define GT64260_PCI0_P2P_SWAP_CNTL 0x1d54 - -#define MV64x60_PCI1_CMD 0x0c80 -#define MV64x60_PCI1_MODE 0x0d80 -#define MV64x60_PCI1_TO_RETRY 0x0c84 -#define MV64x60_PCI1_RD_BUF_DISCARD_TIMER 0x0d84 -#define MV64x60_PCI1_MSI_TRIGGER_TIMER 0x0cb8 -#define MV64x60_PCI1_ARBITER_CNTL 0x1d80 -#define MV64x60_PCI1_XBAR_CNTL_LO 0x1d88 -#define MV64x60_PCI1_XBAR_CNTL_HI 0x1d8c -#define MV64x60_PCI1_XBAR_CNTL_TO 0x1d84 -#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO 0x1d98 -#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI 0x1d9c -#define MV64x60_PCI1_SYNC_BARRIER 0x1d90 -#define MV64x60_PCI1_P2P_CONFIG 0x1d94 - -#define GT64260_PCI1_P2P_SWAP_CNTL 0x1dd4 - -/* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */ -#define MV64x60_PCIMODE_CONVENTIONAL 0 -#define MV64x60_PCIMODE_PCIX_66 (1 << 4) -#define MV64x60_PCIMODE_PCIX_100 (2 << 4) -#define MV64x60_PCIMODE_PCIX_133 (3 << 4) -#define MV64x60_PCIMODE_MASK (0x3 << 4) - -/* PCI Access Control Regions Registers */ -#define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12) -#define GT64260_PCI_ACC_CNTL_DREADEN (1<<13) -#define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16) -#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17) -#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18) -#define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES 0x00000000 -#define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES 0x00100000 -#define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES 0x00200000 -#define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000 -#define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 -#define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000 -#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000 -#define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000 -#define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000 -#define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28) -#define GT64260_PCI_ACC_CNTL_WRPROT (1<<29) - -#define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \ - GT64260_PCI_ACC_CNTL_DREADEN | \ - GT64260_PCI_ACC_CNTL_RDPREFETCH | \ - GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\ - GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \ - GT64260_PCI_ACC_CNTL_MBURST_MASK | \ - GT64260_PCI_ACC_CNTL_SWAP_MASK | \ - GT64260_PCI_ACC_CNTL_ACCPROT| \ - GT64260_PCI_ACC_CNTL_WRPROT) - -#define MV64360_PCI_ACC_CNTL_ENABLE (1<<0) -#define MV64360_PCI_ACC_CNTL_REQ64 (1<<1) -#define MV64360_PCI_ACC_CNTL_SNOOP_NONE 0x00000000 -#define MV64360_PCI_ACC_CNTL_SNOOP_WT 0x00000004 -#define MV64360_PCI_ACC_CNTL_SNOOP_WB 0x00000008 -#define MV64360_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c -#define MV64360_PCI_ACC_CNTL_ACCPROT (1<<4) -#define MV64360_PCI_ACC_CNTL_WRPROT (1<<5) -#define MV64360_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 -#define MV64360_PCI_ACC_CNTL_SWAP_NONE 0x00000040 -#define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080 -#define MV64360_PCI_ACC_CNTL_SWAP_WORD 0x000000c0 -#define MV64360_PCI_ACC_CNTL_SWAP_MASK 0x000000c0 -#define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000 -#define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100 -#define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200 -#define MV64360_PCI_ACC_CNTL_MBURST_MASK 0x00000300 -#define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000 -#define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400 -#define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800 -#define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00 -#define MV64360_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00 - -#define MV64360_PCI_ACC_CNTL_ALL_BITS (MV64360_PCI_ACC_CNTL_ENABLE | \ - MV64360_PCI_ACC_CNTL_REQ64 | \ - MV64360_PCI_ACC_CNTL_SNOOP_MASK | \ - MV64360_PCI_ACC_CNTL_ACCPROT | \ - MV64360_PCI_ACC_CNTL_WRPROT | \ - MV64360_PCI_ACC_CNTL_SWAP_MASK | \ - MV64360_PCI_ACC_CNTL_MBURST_MASK | \ - MV64360_PCI_ACC_CNTL_RDSIZE_MASK) - -#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00 -#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04 -#define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08 -#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10 -#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14 -#define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18 -#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20 -#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24 -#define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28 -#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30 -#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34 -#define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38 -#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40 -#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44 -#define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48 -#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50 -#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54 -#define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58 - -#define GT64260_PCI0_ACC_CNTL_6_BASE_LO 0x1e60 -#define GT64260_PCI0_ACC_CNTL_6_BASE_HI 0x1e64 -#define GT64260_PCI0_ACC_CNTL_6_SIZE 0x1e68 -#define GT64260_PCI0_ACC_CNTL_7_BASE_LO 0x1e70 -#define GT64260_PCI0_ACC_CNTL_7_BASE_HI 0x1e74 -#define GT64260_PCI0_ACC_CNTL_7_SIZE 0x1e78 - -#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80 -#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84 -#define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88 -#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90 -#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94 -#define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98 -#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0 -#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4 -#define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8 -#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0 -#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4 -#define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8 -#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0 -#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4 -#define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8 -#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0 -#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4 -#define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8 - -#define GT64260_PCI1_ACC_CNTL_6_BASE_LO 0x1ee0 -#define GT64260_PCI1_ACC_CNTL_6_BASE_HI 0x1ee4 -#define GT64260_PCI1_ACC_CNTL_6_SIZE 0x1ee8 -#define GT64260_PCI1_ACC_CNTL_7_BASE_LO 0x1ef0 -#define GT64260_PCI1_ACC_CNTL_7_BASE_HI 0x1ef4 -#define GT64260_PCI1_ACC_CNTL_7_SIZE 0x1ef8 - -/* PCI Snoop Control Registers (64260 only) */ -#define GT64260_PCI_SNOOP_NONE 0x00000000 -#define GT64260_PCI_SNOOP_WT 0x00001000 -#define GT64260_PCI_SNOOP_WB 0x00002000 - -#define GT64260_PCI0_SNOOP_0_BASE_LO 0x1f00 -#define GT64260_PCI0_SNOOP_0_BASE_HI 0x1f04 -#define GT64260_PCI0_SNOOP_0_SIZE 0x1f08 -#define GT64260_PCI0_SNOOP_1_BASE_LO 0x1f10 -#define GT64260_PCI0_SNOOP_1_BASE_HI 0x1f14 -#define GT64260_PCI0_SNOOP_1_SIZE 0x1f18 -#define GT64260_PCI0_SNOOP_2_BASE_LO 0x1f20 -#define GT64260_PCI0_SNOOP_2_BASE_HI 0x1f24 -#define GT64260_PCI0_SNOOP_2_SIZE 0x1f28 -#define GT64260_PCI0_SNOOP_3_BASE_LO 0x1f30 -#define GT64260_PCI0_SNOOP_3_BASE_HI 0x1f34 -#define GT64260_PCI0_SNOOP_3_SIZE 0x1f38 - -#define GT64260_PCI1_SNOOP_0_BASE_LO 0x1f80 -#define GT64260_PCI1_SNOOP_0_BASE_HI 0x1f84 -#define GT64260_PCI1_SNOOP_0_SIZE 0x1f88 -#define GT64260_PCI1_SNOOP_1_BASE_LO 0x1f90 -#define GT64260_PCI1_SNOOP_1_BASE_HI 0x1f94 -#define GT64260_PCI1_SNOOP_1_SIZE 0x1f98 -#define GT64260_PCI1_SNOOP_2_BASE_LO 0x1fa0 -#define GT64260_PCI1_SNOOP_2_BASE_HI 0x1fa4 -#define GT64260_PCI1_SNOOP_2_SIZE 0x1fa8 -#define GT64260_PCI1_SNOOP_3_BASE_LO 0x1fb0 -#define GT64260_PCI1_SNOOP_3_BASE_HI 0x1fb4 -#define GT64260_PCI1_SNOOP_3_SIZE 0x1fb8 - -/* PCI Error Report Registers */ -#define MV64x60_PCI0_ERR_SERR_MASK 0x0c28 -#define MV64x60_PCI0_ERR_ADDR_LO 0x1d40 -#define MV64x60_PCI0_ERR_ADDR_HI 0x1d44 -#define MV64x60_PCI0_ERR_DATA_LO 0x1d48 -#define MV64x60_PCI0_ERR_DATA_HI 0x1d4c -#define MV64x60_PCI0_ERR_CMD 0x1d50 -#define MV64x60_PCI0_ERR_CAUSE 0x1d58 -#define MV64x60_PCI0_ERR_MASK 0x1d5c - -#define MV64x60_PCI1_ERR_SERR_MASK 0x0ca8 -#define MV64x60_PCI1_ERR_ADDR_LO 0x1dc0 -#define MV64x60_PCI1_ERR_ADDR_HI 0x1dc4 -#define MV64x60_PCI1_ERR_DATA_LO 0x1dc8 -#define MV64x60_PCI1_ERR_DATA_HI 0x1dcc -#define MV64x60_PCI1_ERR_CMD 0x1dd0 -#define MV64x60_PCI1_ERR_CAUSE 0x1dd8 -#define MV64x60_PCI1_ERR_MASK 0x1ddc - -/* PCI Slave Address Decoding Registers */ -#define MV64x60_PCI0_MEM_0_SIZE 0x0c08 -#define MV64x60_PCI0_MEM_1_SIZE 0x0d08 -#define MV64x60_PCI0_MEM_2_SIZE 0x0c0c -#define MV64x60_PCI0_MEM_3_SIZE 0x0d0c -#define MV64x60_PCI1_MEM_0_SIZE 0x0c88 -#define MV64x60_PCI1_MEM_1_SIZE 0x0d88 -#define MV64x60_PCI1_MEM_2_SIZE 0x0c8c -#define MV64x60_PCI1_MEM_3_SIZE 0x0d8c - -#define MV64x60_PCI0_BAR_ENABLE 0x0c3c -#define MV64x60_PCI1_BAR_ENABLE 0x0cbc - -#define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c -#define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc - -#define MV64x60_PCI0_SLAVE_MEM_0_REMAP 0x0c48 -#define MV64x60_PCI0_SLAVE_MEM_1_REMAP 0x0d48 -#define MV64x60_PCI0_SLAVE_MEM_2_REMAP 0x0c4c -#define MV64x60_PCI0_SLAVE_MEM_3_REMAP 0x0d4c -#define MV64x60_PCI0_SLAVE_DEV_0_REMAP 0x0c50 -#define MV64x60_PCI0_SLAVE_DEV_1_REMAP 0x0d50 -#define MV64x60_PCI0_SLAVE_DEV_2_REMAP 0x0d58 -#define MV64x60_PCI0_SLAVE_DEV_3_REMAP 0x0c54 -#define MV64x60_PCI0_SLAVE_BOOT_REMAP 0x0d54 -#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c -#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60 -#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64 -#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68 -#define MV64x60_PCI0_SLAVE_P2P_IO_REMAP 0x0d6c -#define MV64x60_PCI0_SLAVE_CPU_REMAP 0x0d70 - -#define MV64x60_PCI1_SLAVE_MEM_0_REMAP 0x0cc8 -#define MV64x60_PCI1_SLAVE_MEM_1_REMAP 0x0dc8 -#define MV64x60_PCI1_SLAVE_MEM_2_REMAP 0x0ccc -#define MV64x60_PCI1_SLAVE_MEM_3_REMAP 0x0dcc -#define MV64x60_PCI1_SLAVE_DEV_0_REMAP 0x0cd0 -#define MV64x60_PCI1_SLAVE_DEV_1_REMAP 0x0dd0 -#define MV64x60_PCI1_SLAVE_DEV_2_REMAP 0x0dd8 -#define MV64x60_PCI1_SLAVE_DEV_3_REMAP 0x0cd4 -#define MV64x60_PCI1_SLAVE_BOOT_REMAP 0x0dd4 -#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc -#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0 -#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4 -#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8 -#define MV64x60_PCI1_SLAVE_P2P_IO_REMAP 0x0dec -#define MV64x60_PCI1_SLAVE_CPU_REMAP 0x0df0 - -#define MV64360_PCICFG_CPCI_HOTSWAP 0x68 - -/* - ***************************************************************************** - * - * ENET Controller Interface Registers - * - ***************************************************************************** - */ - -/* ENET Controller Window Registers (6 windows) */ -#define MV64360_ENET2MEM_WINDOWS 6 - -#define MV64360_ENET2MEM_0_BASE 0x2200 -#define MV64360_ENET2MEM_0_SIZE 0x2204 -#define MV64360_ENET2MEM_1_BASE 0x2208 -#define MV64360_ENET2MEM_1_SIZE 0x220c -#define MV64360_ENET2MEM_2_BASE 0x2210 -#define MV64360_ENET2MEM_2_SIZE 0x2214 -#define MV64360_ENET2MEM_3_BASE 0x2218 -#define MV64360_ENET2MEM_3_SIZE 0x221c -#define MV64360_ENET2MEM_4_BASE 0x2220 -#define MV64360_ENET2MEM_4_SIZE 0x2224 -#define MV64360_ENET2MEM_5_BASE 0x2228 -#define MV64360_ENET2MEM_5_SIZE 0x222c - -#define MV64360_ENET2MEM_SNOOP_NONE 0x00000000 -#define MV64360_ENET2MEM_SNOOP_WT 0x00001000 -#define MV64360_ENET2MEM_SNOOP_WB 0x00002000 - -#define MV64360_ENET2MEM_BAR_ENABLE 0x2290 - -#define MV64360_ENET2MEM_ACC_PROT_0 0x2294 -#define MV64360_ENET2MEM_ACC_PROT_1 0x2298 -#define MV64360_ENET2MEM_ACC_PROT_2 0x229c - -/* - ***************************************************************************** - * - * MPSC Controller Interface Registers - * - ***************************************************************************** - */ - -/* MPSC Controller Window Registers (4 windows) */ -#define MV64360_MPSC2MEM_WINDOWS 4 - -#define MV64360_MPSC2MEM_0_BASE 0xf200 -#define MV64360_MPSC2MEM_0_SIZE 0xf204 -#define MV64360_MPSC2MEM_1_BASE 0xf208 -#define MV64360_MPSC2MEM_1_SIZE 0xf20c -#define MV64360_MPSC2MEM_2_BASE 0xf210 -#define MV64360_MPSC2MEM_2_SIZE 0xf214 -#define MV64360_MPSC2MEM_3_BASE 0xf218 -#define MV64360_MPSC2MEM_3_SIZE 0xf21c - -#define MV64360_MPSC_0_REMAP 0xf240 -#define MV64360_MPSC_1_REMAP 0xf244 - -#define MV64360_MPSC2MEM_SNOOP_NONE 0x00000000 -#define MV64360_MPSC2MEM_SNOOP_WT 0x00001000 -#define MV64360_MPSC2MEM_SNOOP_WB 0x00002000 - -#define MV64360_MPSC2MEM_BAR_ENABLE 0xf250 - -#define MV64360_MPSC2MEM_ACC_PROT_0 0xf254 -#define MV64360_MPSC2MEM_ACC_PROT_1 0xf258 - -#define MV64360_MPSC2REGS_BASE 0xf25c - -/* - ***************************************************************************** - * - * Timer/Counter Interface Registers - * - ***************************************************************************** - */ - -#define MV64x60_TIMR_CNTR_0 0x0850 -#define MV64x60_TIMR_CNTR_1 0x0854 -#define MV64x60_TIMR_CNTR_2 0x0858 -#define MV64x60_TIMR_CNTR_3 0x085c -#define MV64x60_TIMR_CNTR_0_3_CNTL 0x0864 -#define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE 0x0868 -#define MV64x60_TIMR_CNTR_0_3_INTR_MASK 0x086c - -#define GT64260_TIMR_CNTR_4 0x0950 -#define GT64260_TIMR_CNTR_5 0x0954 -#define GT64260_TIMR_CNTR_6 0x0958 -#define GT64260_TIMR_CNTR_7 0x095c -#define GT64260_TIMR_CNTR_4_7_CNTL 0x0964 -#define GT64260_TIMR_CNTR_4_7_INTR_CAUSE 0x0968 -#define GT64260_TIMR_CNTR_4_7_INTR_MASK 0x096c - -/* - ***************************************************************************** - * - * Communications Controller - * - ***************************************************************************** - */ - -#define GT64260_SER_INIT_PCI_ADDR_HI 0xf320 -#define GT64260_SER_INIT_LAST_DATA 0xf324 -#define GT64260_SER_INIT_CONTROL 0xf328 -#define GT64260_SER_INIT_STATUS 0xf32c - -#define MV64x60_COMM_ARBITER_CNTL 0xf300 -#define MV64x60_COMM_CONFIG 0xb40c -#define MV64x60_COMM_XBAR_TO 0xf304 -#define MV64x60_COMM_INTR_CAUSE 0xf310 -#define MV64x60_COMM_INTR_MASK 0xf314 -#define MV64x60_COMM_ERR_ADDR 0xf318 - -#define MV64360_COMM_ARBITER_CNTL 0xf300 - -/* - ***************************************************************************** - * - * IDMA Controller Interface Registers - * - ***************************************************************************** - */ - -/* IDMA Controller Window Registers (8 windows) */ -#define MV64360_IDMA2MEM_WINDOWS 8 - -#define MV64360_IDMA2MEM_0_BASE 0x0a00 -#define MV64360_IDMA2MEM_0_SIZE 0x0a04 -#define MV64360_IDMA2MEM_1_BASE 0x0a08 -#define MV64360_IDMA2MEM_1_SIZE 0x0a0c -#define MV64360_IDMA2MEM_2_BASE 0x0a10 -#define MV64360_IDMA2MEM_2_SIZE 0x0a14 -#define MV64360_IDMA2MEM_3_BASE 0x0a18 -#define MV64360_IDMA2MEM_3_SIZE 0x0a1c -#define MV64360_IDMA2MEM_4_BASE 0x0a20 -#define MV64360_IDMA2MEM_4_SIZE 0x0a24 -#define MV64360_IDMA2MEM_5_BASE 0x0a28 -#define MV64360_IDMA2MEM_5_SIZE 0x0a2c -#define MV64360_IDMA2MEM_6_BASE 0x0a30 -#define MV64360_IDMA2MEM_6_SIZE 0x0a34 -#define MV64360_IDMA2MEM_7_BASE 0x0a38 -#define MV64360_IDMA2MEM_7_SIZE 0x0a3c - -#define MV64360_IDMA2MEM_SNOOP_NONE 0x00000000 -#define MV64360_IDMA2MEM_SNOOP_WT 0x00001000 -#define MV64360_IDMA2MEM_SNOOP_WB 0x00002000 - -#define MV64360_IDMA2MEM_BAR_ENABLE 0x0a80 - -#define MV64360_IDMA2MEM_ACC_PROT_0 0x0a70 -#define MV64360_IDMA2MEM_ACC_PROT_1 0x0a74 -#define MV64360_IDMA2MEM_ACC_PROT_2 0x0a78 -#define MV64360_IDMA2MEM_ACC_PROT_3 0x0a7c - -#define MV64x60_IDMA_0_OFFSET 0x0800 -#define MV64x60_IDMA_1_OFFSET 0x0804 -#define MV64x60_IDMA_2_OFFSET 0x0808 -#define MV64x60_IDMA_3_OFFSET 0x080c -#define MV64x60_IDMA_4_OFFSET 0x0900 -#define MV64x60_IDMA_5_OFFSET 0x0904 -#define MV64x60_IDMA_6_OFFSET 0x0908 -#define MV64x60_IDMA_7_OFFSET 0x090c - -#define MV64x60_IDMA_BYTE_COUNT (0x0800 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_SRC_ADDR (0x0810 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_DST_ADDR (0x0820 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_NEXT_DESC (0x0830 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_CUR_DESC (0x0870 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_SRC_PCI_ADDR_HI (0x0890 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_DST_PCI_ADDR_HI (0x08a0 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI (0x08b0 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_CONTROL_LO (0x0840 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_CONTROL_HI (0x0880 - MV64x60_IDMA_0_OFFSET) - -#define MV64x60_IDMA_0_3_ARBITER_CNTL 0x0860 -#define MV64x60_IDMA_4_7_ARBITER_CNTL 0x0960 - -#define MV64x60_IDMA_0_3_XBAR_TO 0x08d0 -#define MV64x60_IDMA_4_7_XBAR_TO 0x09d0 - -#define MV64x60_IDMA_0_3_INTR_CAUSE 0x08c0 -#define MV64x60_IDMA_0_3_INTR_MASK 0x08c4 -#define MV64x60_IDMA_0_3_ERROR_ADDR 0x08c8 -#define MV64x60_IDMA_0_3_ERROR_SELECT 0x08cc -#define MV64x60_IDMA_4_7_INTR_CAUSE 0x09c0 -#define MV64x60_IDMA_4_7_INTR_MASK 0x09c4 -#define MV64x60_IDMA_4_7_ERROR_ADDR 0x09c8 -#define MV64x60_IDMA_4_7_ERROR_SELECT 0x09cc - -/* - ***************************************************************************** - * - * Watchdog Timer Interface Registers - * - ***************************************************************************** - */ - -#define MV64x60_WDT_WDC 0xb410 -#define MV64x60_WDT_WDV 0xb414 - - -/* - ***************************************************************************** - * - * General Purpose Pins Controller Interface Registers - * - ***************************************************************************** - */ - -#define MV64x60_GPP_IO_CNTL 0xf100 -#define MV64x60_GPP_LEVEL_CNTL 0xf110 -#define MV64x60_GPP_VALUE 0xf104 -#define MV64x60_GPP_INTR_CAUSE 0xf108 -#define MV64x60_GPP_INTR_MASK 0xf10c -#define MV64x60_GPP_VALUE_SET 0xf118 -#define MV64x60_GPP_VALUE_CLR 0xf11c - - -/* - ***************************************************************************** - * - * Multi-Purpose Pins Controller Interface Registers - * - ***************************************************************************** - */ - -#define MV64x60_MPP_CNTL_0 0xf000 -#define MV64x60_MPP_CNTL_1 0xf004 -#define MV64x60_MPP_CNTL_2 0xf008 -#define MV64x60_MPP_CNTL_3 0xf00c -#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010 - -#define MV64x60_ETH_BAR_GAP 0x8 -#define MV64x60_ETH_SIZE_REG_GAP 0x8 -#define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define MV64x60_ETH_PORT_ACCESS_CTRL_GAP 0x4 - -#define MV64x60_EBAR_ATTR_DRAM_CS0 0x00000E00 -#define MV64x60_EBAR_ATTR_DRAM_CS1 0x00000D00 -#define MV64x60_EBAR_ATTR_DRAM_CS2 0x00000B00 -#define MV64x60_EBAR_ATTR_DRAM_CS3 0x00000700 - -#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define MV64x60_EBAR_ATTR_CBS_SRAM 0x00000000 -#define MV64x60_EBAR_ATTR_CBS_CPU_BUS 0x00000800 - - -/* - ***************************************************************************** - * - * Interrupt Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_IC_OFFSET 0x0c18 - -#define GT64260_IC_MAIN_CAUSE_LO 0x0c18 -#define GT64260_IC_MAIN_CAUSE_HI 0x0c68 -#define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c -#define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c -#define GT64260_IC_CPU_SELECT_CAUSE 0x0c70 -#define GT64260_IC_PCI0_INTR_MASK_LO 0x0c24 -#define GT64260_IC_PCI0_INTR_MASK_HI 0x0c64 -#define GT64260_IC_PCI0_SELECT_CAUSE 0x0c74 -#define GT64260_IC_PCI1_INTR_MASK_LO 0x0ca4 -#define GT64260_IC_PCI1_INTR_MASK_HI 0x0ce4 -#define GT64260_IC_PCI1_SELECT_CAUSE 0x0cf4 -#define GT64260_IC_CPU_INT_0_MASK 0x0e60 -#define GT64260_IC_CPU_INT_1_MASK 0x0e64 -#define GT64260_IC_CPU_INT_2_MASK 0x0e68 -#define GT64260_IC_CPU_INT_3_MASK 0x0e6c - -#define MV64360_IC_OFFSET 0x0000 - -#define MV64360_IC_MAIN_CAUSE_LO 0x0004 -#define MV64360_IC_MAIN_CAUSE_HI 0x000c -#define MV64360_IC_CPU0_INTR_MASK_LO 0x0014 -#define MV64360_IC_CPU0_INTR_MASK_HI 0x001c -#define MV64360_IC_CPU0_SELECT_CAUSE 0x0024 -#define MV64360_IC_CPU1_INTR_MASK_LO 0x0034 -#define MV64360_IC_CPU1_INTR_MASK_HI 0x003c -#define MV64360_IC_CPU1_SELECT_CAUSE 0x0044 -#define MV64360_IC_INT0_MASK_LO 0x0054 -#define MV64360_IC_INT0_MASK_HI 0x005c -#define MV64360_IC_INT0_SELECT_CAUSE 0x0064 -#define MV64360_IC_INT1_MASK_LO 0x0074 -#define MV64360_IC_INT1_MASK_HI 0x007c -#define MV64360_IC_INT1_SELECT_CAUSE 0x0084 - -#endif /* __ASMPPC_MV64x60_DEFS_H */ diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h deleted file mode 100644 index 3909a2eec286..000000000000 --- a/include/asm-ppc/ocp.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * ocp.h - * - * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) - * Mipsys - France - * - * Derived from work (c) Armin Kuster akuster@pacbell.net - * - * Additional support and port to 2.6 LDM/sysfs by - * Matt Porter - * Copyright 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * TODO: - Add get/put interface & fixup locking to provide same API for - * 2.4 and 2.5 - * - Rework PM callbacks - */ - -#ifdef __KERNEL__ -#ifndef __OCP_H__ -#define __OCP_H__ - -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_PPC_OCP - -#define OCP_MAX_IRQS 7 -#define MAX_EMACS 4 -#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */ -#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */ -#define OCP_NULL_TYPE -1 /* used to mark end of list */ -#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */ -#define OCP_PADDR_NA 0 /* No MMIO registers */ - -#define OCP_ANY_ID (~0) -#define OCP_ANY_INDEX -1 - -extern struct list_head ocp_devices; -extern struct rw_semaphore ocp_devices_sem; - -struct ocp_device_id { - unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */ - unsigned long driver_data; /* Data private to the driver */ -}; - - -/* - * Static definition of an OCP device. - * - * @vendor: Vendor code. It is _STRONGLY_ discouraged to use - * the vendor code as a way to match a unique device, - * though I kept that possibility open, you should - * really define different function codes for different - * device types - * @function: This is the function code for this device. - * @index: This index is used for mapping the Nth function of a - * given core. This is typically used for cross-driver - * matching, like looking for a given MAL or ZMII from - * an EMAC or for getting to the proper set of DCRs. - * Indices are no longer magically calculated based on - * structure ordering, they have to be actually coded - * into the ocp_def to avoid any possible confusion - * I _STRONGLY_ (again ? wow !) encourage anybody relying - * on index mapping to encode the "target" index in an - * associated structure pointed to by "additions", see - * how it's done for the EMAC driver. - * @paddr: Device physical address (may not mean anything...) - * @irq: Interrupt line for this device (TODO: think about making - * an array with this) - * @pm: Currently, contains the bitmask in CPMFR DCR for the device - * @additions: Optionally points to a function specific structure - * providing additional informations for a given device - * instance. It's currently used by the EMAC driver for MAL - * channel & ZMII port mapping among others. - * @show: Optionally points to a function specific structure - * providing a sysfs show routine for additions fields. - */ -struct ocp_def { - unsigned int vendor; - unsigned int function; - int index; - phys_addr_t paddr; - int irq; - unsigned long pm; - void *additions; - void (*show)(struct device *); -}; - - -/* Struct for a given device instance */ -struct ocp_device { - struct list_head link; - char name[80]; /* device name */ - struct ocp_def *def; /* device definition */ - void *drvdata; /* driver data for this device */ - struct ocp_driver *driver; - u32 current_state; /* Current operating state. In ACPI-speak, - this is D0-D3, D0 being fully functional, - and D3 being off. */ - struct device dev; -}; - -struct ocp_driver { - struct list_head node; - char *name; - const struct ocp_device_id *id_table; /* NULL if wants all devices */ - int (*probe) (struct ocp_device *dev); /* New device inserted */ - void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a hot-plug capable driver) */ - int (*suspend) (struct ocp_device *dev, pm_message_t state); /* Device suspended */ - int (*resume) (struct ocp_device *dev); /* Device woken up */ - struct device_driver driver; -}; - -#define to_ocp_dev(n) container_of(n, struct ocp_device, dev) -#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver) - -/* Similar to the helpers above, these manipulate per-ocp_dev - * driver-specific data. Currently stored as ocp_dev::ocpdev, - * a void pointer, but it is not present on older kernels. - */ -static inline void * -ocp_get_drvdata(struct ocp_device *pdev) -{ - return pdev->drvdata; -} - -static inline void -ocp_set_drvdata(struct ocp_device *pdev, void *data) -{ - pdev->drvdata = data; -} - -#if defined (CONFIG_PM) -/* - * This is right for the IBM 405 and 440 but will need to be - * generalized if the OCP stuff gets used on other processors. - */ -static inline void -ocp_force_power_off(struct ocp_device *odev) -{ - mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm); -} - -static inline void -ocp_force_power_on(struct ocp_device *odev) -{ - mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm); -} -#else -#define ocp_force_power_off(x) (void)(x) -#define ocp_force_power_on(x) (void)(x) -#endif - -/* Register/Unregister an OCP driver */ -extern int ocp_register_driver(struct ocp_driver *drv); -extern void ocp_unregister_driver(struct ocp_driver *drv); - -/* Build list of devices */ -extern int ocp_early_init(void) __init; - -/* Find a device by index */ -extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index); - -/* Get a def by index */ -extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index); - -/* Add a device by index */ -extern int ocp_add_one_device(struct ocp_def *def); - -/* Remove a device by index */ -extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index); - -/* Iterate over devices and execute a routine */ -extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg); - -/* Sysfs support */ -#define OCP_SYSFS_ADDTL(type, format, name, field) \ -static ssize_t \ -show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf) \ -{ \ - struct ocp_device *odev = to_ocp_dev(dev); \ - type *add = odev->def->additions; \ - \ - return sprintf(buf, format, add->field); \ -} \ -static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL); - -#ifdef CONFIG_IBM_OCP -#include -#endif - -#endif /* CONFIG_PPC_OCP */ -#endif /* __OCP_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h deleted file mode 100644 index 8ae4b311a37c..000000000000 --- a/include/asm-ppc/ocp_ids.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * ocp_ids.h - * - * OCP device ids based on the ideas from PCI - * - * The numbers below are almost completely arbitrary, and in fact - * strings might work better. -- paulus - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * Vender device - * [xxxx] [xxxx] - * - * Keep in order, please - */ - -/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */ - -#define OCP_VENDOR_INVALID 0x0000 -#define OCP_VENDOR_ARM 0x0004 -#define OCP_VENDOR_FREESCALE 0x1057 -#define OCP_VENDOR_IBM 0x1014 -#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE -#define OCP_VENDOR_XILINX 0x10ee -#define OCP_VENDOR_UNKNOWN 0xFFFF - -/* device identification */ - -/* define type */ -#define OCP_FUNC_INVALID 0x0000 - -/* system 0x0001 - 0x001F */ - -/* Timers 0x0020 - 0x002F */ - -/* Serial 0x0030 - 0x006F*/ -#define OCP_FUNC_16550 0x0031 -#define OCP_FUNC_IIC 0x0032 -#define OCP_FUNC_USB 0x0033 -#define OCP_FUNC_PSC_UART 0x0034 - -/* Memory devices 0x0090 - 0x009F */ -#define OCP_FUNC_MAL 0x0090 -#define OCP_FUNC_DMA 0x0091 - -/* Display 0x00A0 - 0x00AF */ - -/* Sound 0x00B0 - 0x00BF */ - -/* Mass Storage 0x00C0 - 0xxCF */ -#define OCP_FUNC_IDE 0x00C0 - -/* Misc 0x00D0 - 0x00DF*/ -#define OCP_FUNC_GPIO 0x00D0 -#define OCP_FUNC_ZMII 0x00D1 -#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */ -#define OCP_FUNC_RGMII 0x00D3 -#define OCP_FUNC_TAH 0x00D4 -#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */ - -/* Network 0x0200 - 0x02FF */ -#define OCP_FUNC_EMAC 0x0200 -#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */ - -/* Bridge devices 0xE00 - 0xEFF */ -#define OCP_FUNC_OPB 0x0E00 - -#define OCP_FUNC_UNKNOWN 0xFFFF diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h deleted file mode 100644 index 778d5726212c..000000000000 --- a/include/asm-ppc/open_pic.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling - * - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - */ - -#ifndef _PPC_KERNEL_OPEN_PIC_H -#define _PPC_KERNEL_OPEN_PIC_H - -#include - -#define OPENPIC_SIZE 0x40000 - -/* - * Non-offset'ed vector numbers - */ - -#define OPENPIC_VEC_TIMER 110 /* and up */ -#define OPENPIC_VEC_IPI 118 /* and up */ -#define OPENPIC_VEC_SPURIOUS 255 - -/* Priorities */ -#define OPENPIC_PRIORITY_IPI_BASE 10 -#define OPENPIC_PRIORITY_DEFAULT 4 -#define OPENPIC_PRIORITY_NMI 9 - -/* OpenPIC IRQ controller structure */ -extern struct hw_interrupt_type open_pic; - -/* OpenPIC IPI controller structure */ -#ifdef CONFIG_SMP -extern struct hw_interrupt_type open_pic_ipi; -#endif /* CONFIG_SMP */ - -extern u_int OpenPIC_NumInitSenses; -extern u_char *OpenPIC_InitSenses; -extern void __iomem * OpenPIC_Addr; -extern int epic_serial_mode; - -/* Exported functions */ -extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr); -extern void openpic_init(int linux_irq_offset); -extern void openpic_init_nmi_irq(u_int irq); -extern void openpic_set_irq_priority(u_int irq, u_int pri); -extern void openpic_hookup_cascade(u_int irq, char *name, - int (*cascade_fn)(void)); -extern u_int openpic_irq(void); -extern void openpic_eoi(void); -extern void openpic_request_IPIs(void); -extern void do_openpic_setup_cpu(void); -extern int openpic_get_irq(void); -extern void openpic_reset_processor_phys(u_int cpumask); -extern void openpic_setup_ISU(int isu_num, unsigned long addr); -extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask); -extern void smp_openpic_message_pass(int target, int msg); -extern void openpic_set_k2_cascade(int irq); -extern void openpic_set_priority(u_int pri); -extern u_int openpic_get_priority(void); - -extern inline int openpic_to_irq(int irq) -{ - /* IRQ 0 usually means 'disabled'.. don't mess with it - * exceptions to this (sandpoint maybe?) - * shouldn't use openpic_to_irq - */ - if (irq != 0){ - return irq += NUM_8259_INTERRUPTS; - } else { - return 0; - } -} -/* Support for second openpic on G5 macs */ - -// FIXME: To be replaced by sane cascaded controller management */ - -#define PMAC_OPENPIC2_OFFSET 128 - -#define OPENPIC2_VEC_TIMER 110 /* and up */ -#define OPENPIC2_VEC_IPI 118 /* and up */ -#define OPENPIC2_VEC_SPURIOUS 127 - - -extern void* OpenPIC2_Addr; - -/* Exported functions */ -extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr); -extern void openpic2_init(int linux_irq_offset); -extern void openpic2_init_nmi_irq(u_int irq); -extern u_int openpic2_irq(void); -extern void openpic2_eoi(void); -extern int openpic2_get_irq(void); -extern void openpic2_setup_ISU(int isu_num, unsigned long addr); -#endif /* _PPC_KERNEL_OPEN_PIC_H */ diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h deleted file mode 100644 index 37e4756b6b2d..000000000000 --- a/include/asm-ppc/page.h +++ /dev/null @@ -1,140 +0,0 @@ -#ifndef _PPC_PAGE_H -#define _PPC_PAGE_H - -#include - -/* PAGE_SHIFT determines the page size */ -#define PAGE_SHIFT 12 -#define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT) - -/* - * Subtle: this is an int (not an unsigned long) and so it - * gets extended to 64 bits the way want (i.e. with 1s). -- paulus - */ -#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) - -#ifdef __KERNEL__ - -/* This must match what is in arch/ppc/Makefile */ -#define PAGE_OFFSET CONFIG_KERNEL_START -#define KERNELBASE PAGE_OFFSET -#define is_kernel_addr(x) ((x) >= PAGE_OFFSET) - -#ifndef __ASSEMBLY__ - -/* - * The basic type of a PTE - 64 bits for those CPUs with > 32 bit - * physical addressing. For now this just the IBM PPC440. - */ -#ifdef CONFIG_PTE_64BIT -typedef unsigned long long pte_basic_t; -#define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */ -#define PTE_FMT "%16Lx" -#else -typedef unsigned long pte_basic_t; -#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */ -#define PTE_FMT "%.8lx" -#endif - -/* align addr on a size boundary - adjust address up/down if needed */ -#define _ALIGN_UP(addr,size) (((addr)+((size)-1))&(~((size)-1))) -#define _ALIGN_DOWN(addr,size) ((addr)&(~((size)-1))) - -/* align addr on a size boundary - adjust address up if needed */ -#define _ALIGN(addr,size) _ALIGN_UP(addr,size) - -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE) - - -#undef STRICT_MM_TYPECHECKS - -#ifdef STRICT_MM_TYPECHECKS -/* - * These are used to make use of C type-checking.. - */ -typedef struct { pte_basic_t pte; } pte_t; -typedef struct { unsigned long pmd; } pmd_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((x).pmd) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -#else -/* - * .. while these make it easier on the compiler - */ -typedef pte_basic_t pte_t; -typedef unsigned long pmd_t; -typedef unsigned long pgd_t; -typedef unsigned long pgprot_t; - -#define pte_val(x) (x) -#define pmd_val(x) (x) -#define pgd_val(x) (x) -#define pgprot_val(x) (x) - -#define __pte(x) (x) -#define __pmd(x) (x) -#define __pgd(x) (x) -#define __pgprot(x) (x) - -#endif - -struct page; -extern void clear_pages(void *page, int order); -static inline void clear_page(void *page) { clear_pages(page, 0); } -extern void copy_page(void *to, void *from); -extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg); -extern void copy_user_page(void *to, void *from, unsigned long vaddr, - struct page *pg); - -#define PPC_MEMSTART 0 -#define PPC_MEMOFFSET PAGE_OFFSET - -#define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET) -#define ___va(paddr) ((paddr)+PPC_MEMOFFSET) - -extern int page_is_ram(unsigned long pfn); - -#define __pa(x) ___pa((unsigned long)(x)) -#define __va(x) ((void *)(___va((unsigned long)(x)))) - -#define ARCH_PFN_OFFSET 0 -#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) -#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT) - -#define pfn_valid(pfn) ((pfn) < max_mapnr) -#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) - -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int lz; - - size = (size-1) >> PAGE_SHIFT; - asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size)); - return 32 - lz; -} - -typedef struct page *pgtable_t; - -#endif /* __ASSEMBLY__ */ - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */ -#define __HAVE_ARCH_GATE_AREA 1 - -#include -#endif /* __KERNEL__ */ -#endif /* _PPC_PAGE_H */ diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h deleted file mode 100644 index 81a2d0fdaf00..000000000000 --- a/include/asm-ppc/pc_serial.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * include/asm-ppc/pc_serial.h - * - * This is basically a copy of include/asm-i386/serial.h. - * It is used on platforms which have an ISA bus and thus are likely - * to have PC-style serial ports at the legacy I/O port addresses. - * It also includes the definitions for the fourport, accent, boca - * and hub6 multiport serial cards, although I have never heard of - * anyone using any of those on a PPC platform. -- paulus - */ - - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD ( 1843200 / 16 ) - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 4 -#endif - -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF -#endif - -#define SERIAL_PORT_DFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ - { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ - { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h deleted file mode 100644 index 4d35b844bc58..000000000000 --- a/include/asm-ppc/pci-bridge.h +++ /dev/null @@ -1,151 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _ASM_PCI_BRIDGE_H -#define _ASM_PCI_BRIDGE_H - -#include -#include - -struct device_node; -struct pci_controller; - -/* - * pci_io_base returns the memory address at which you can access - * the I/O space for PCI bus number `bus' (or NULL on error). - */ -extern void __iomem *pci_bus_io_base(unsigned int bus); -extern unsigned long pci_bus_io_base_phys(unsigned int bus); -extern unsigned long pci_bus_mem_base_phys(unsigned int bus); - -/* Allocate a new PCI host bridge structure */ -extern struct pci_controller* pcibios_alloc_controller(void); - -/* Helper function for setting up resources */ -extern void pci_init_resource(struct resource *res, resource_size_t start, - resource_size_t end, int flags, char *name); - -/* Get the PCI host controller for a bus */ -extern struct pci_controller* pci_bus_to_hose(int bus); - -/* Get the PCI host controller for an OF device */ -extern struct pci_controller* -pci_find_hose_for_OF_device(struct device_node* node); - -/* Fill up host controller resources from the OF node */ -extern void -pci_process_bridge_OF_ranges(struct pci_controller *hose, - struct device_node *dev, int primary); - -/* - * Structure of a PCI controller (host bridge) - */ -struct pci_controller { - int index; /* PCI domain number */ - struct pci_controller *next; - struct pci_bus *bus; - void *arch_data; - struct device *parent; - - int first_busno; - int last_busno; - int bus_offset; - - void __iomem *io_base_virt; - resource_size_t io_base_phys; - - /* Some machines (PReP) have a non 1:1 mapping of - * the PCI memory space in the CPU bus space - */ - resource_size_t pci_mem_offset; - - struct pci_ops *ops; - volatile unsigned int __iomem *cfg_addr; - volatile void __iomem *cfg_data; - /* - * If set, indirect method will set the cfg_type bit as - * needed to generate type 1 configuration transactions. - */ - int set_cfg_type; - - /* Currently, we limit ourselves to 1 IO range and 3 mem - * ranges since the common pci_bus structure can't handle more - */ - struct resource io_resource; - struct resource mem_resources[3]; - int mem_resource_count; - - /* Host bridge I/O and Memory space - * Used for BAR placement algorithms - */ - struct resource io_space; - struct resource mem_space; -}; - -static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) -{ - return bus->sysdata; -} - -/* These are used for config access before all the PCI probing - has been done. */ -int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, - int where, u8 *val); -int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, - int where, u16 *val); -int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, - int where, u32 *val); -int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, - int where, u8 val); -int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, - int where, u16 val); -int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, - int where, u32 val); - -extern void setup_indirect_pci_nomap(struct pci_controller* hose, - void __iomem *cfg_addr, void __iomem *cfg_data); -extern void setup_indirect_pci(struct pci_controller* hose, - u32 cfg_addr, u32 cfg_data); -extern void setup_grackle(struct pci_controller *hose); - -extern unsigned char common_swizzle(struct pci_dev *, unsigned char *); - -/* - * The following code swizzles for exactly one bridge. The routine - * common_swizzle below handles multiple bridges. But there are a - * some boards that don't follow the PCI spec's suggestion so we - * break this piece out separately. - */ -static inline unsigned char bridge_swizzle(unsigned char pin, - unsigned char idsel) -{ - return (((pin-1) + idsel) % 4) + 1; -} - -/* - * The following macro is used to lookup irqs in a standard table - * format for those PPC systems that do not already have PCI - * interrupts properly routed. - */ -/* FIXME - double check this */ -#define PCI_IRQ_TABLE_LOOKUP \ -({ long _ctl_ = -1; \ - if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ - _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ - _ctl_; }) - -/* - * Scan the buses below a given PCI host bridge and assign suitable - * resources to all devices found. - */ -extern int pciauto_bus_scan(struct pci_controller *, int); - -#ifdef CONFIG_PCI -extern unsigned long pci_address_to_pio(phys_addr_t address); -#else -static inline unsigned long pci_address_to_pio(phys_addr_t address) -{ - return (unsigned long)-1; -} -#endif - -#endif -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h deleted file mode 100644 index d2442cd72a59..000000000000 --- a/include/asm-ppc/pci.h +++ /dev/null @@ -1,156 +0,0 @@ -#ifndef __PPC_PCI_H -#define __PPC_PCI_H -#ifdef __KERNEL__ - -#include -#include -#include -#include -#include -#include -#include -#include - -struct pci_dev; - -/* Values for the `which' argument to sys_pciconfig_iobase syscall. */ -#define IOBASE_BRIDGE_NUMBER 0 -#define IOBASE_MEMORY 1 -#define IOBASE_IO 2 -#define IOBASE_ISA_IO 3 -#define IOBASE_ISA_MEM 4 - -/* - * Set this to 1 if you want the kernel to re-assign all PCI - * bus numbers - */ -extern int pci_assign_all_buses; - -#define pcibios_assign_all_busses() (pci_assign_all_buses) -#define pcibios_scan_all_fns(a, b) 0 - -#define PCIBIOS_MIN_IO 0x1000 -#define PCIBIOS_MIN_MEM 0x10000000 - -extern inline void pcibios_set_master(struct pci_dev *dev) -{ - /* No special bus mastering setup handling */ -} - -extern inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - -extern unsigned long pci_resource_to_bus(struct pci_dev *pdev, struct resource *res); - -/* - * The PCI bus bridge can translate addresses issued by the processor(s) - * into a different address on the PCI bus. On 32-bit cpus, we assume - * this mapping is 1-1, but on 64-bit systems it often isn't. - * - * Obsolete ! Drivers should now use pci_resource_to_bus - */ -extern unsigned long phys_to_bus(unsigned long pa); -extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr); -extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr); - -/* The PCI address space does equal the physical memory - * address space. The networking and block device layers use - * this boolean for bounce buffer decisions. - */ -#define PCI_DMA_BUS_IS_PHYS (1) - -#ifdef CONFIG_NOT_COHERENT_CACHE -/* - * pci_unmap_{page,single} are NOPs but pci_dma_sync_single_for_cpu() - * and so on are not, so... - */ - -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ - dma_addr_t ADDR_NAME; -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ - __u32 LEN_NAME; -#define pci_unmap_addr(PTR, ADDR_NAME) \ - ((PTR)->ADDR_NAME) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ - (((PTR)->ADDR_NAME) = (VAL)) -#define pci_unmap_len(PTR, LEN_NAME) \ - ((PTR)->LEN_NAME) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ - (((PTR)->LEN_NAME) = (VAL)) - -#else /* coherent */ - -/* pci_unmap_{page,single} is a nop so... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) -#define pci_unmap_addr(PTR, ADDR_NAME) (0) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) -#define pci_unmap_len(PTR, LEN_NAME) (0) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) - -#endif /* CONFIG_NOT_COHERENT_CACHE */ - -#ifdef CONFIG_PCI -static inline void pci_dma_burst_advice(struct pci_dev *pdev, - enum pci_dma_burst_strategy *strat, - unsigned long *strategy_parameter) -{ - *strat = PCI_DMA_BURST_INFINITY; - *strategy_parameter = ~0UL; -} -#endif - -/* Return the index of the PCI controller for device PDEV. */ -#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index - -/* Set the name of the bus as it appears in /proc/bus/pci */ -static inline int pci_proc_domain(struct pci_bus *bus) -{ - return 0; -} - -/* Map a range of PCI memory or I/O space for a device into user space */ -int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, - enum pci_mmap_state mmap_state, int write_combine); - -/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ -#define HAVE_PCI_MMAP 1 - -extern void -pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, - struct resource *res); - -extern void -pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, - struct pci_bus_region *region); - -static inline struct resource * -pcibios_select_root(struct pci_dev *pdev, struct resource *res) -{ - struct resource *root = NULL; - - if (res->flags & IORESOURCE_IO) - root = &ioport_resource; - if (res->flags & IORESOURCE_MEM) - root = &iomem_resource; - - return root; -} - -struct file; -extern pgprot_t pci_phys_mem_access_prot(struct file *file, - unsigned long pfn, - unsigned long size, - pgprot_t prot); - -#define HAVE_ARCH_PCI_RESOURCE_TO_USER -extern void pci_resource_to_user(const struct pci_dev *dev, int bar, - const struct resource *rsrc, - resource_size_t *start, resource_size_t *end); - - -#endif /* __KERNEL__ */ - -#endif /* __PPC_PCI_H */ diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h deleted file mode 100644 index fd4d1d74cfb1..000000000000 --- a/include/asm-ppc/pgalloc.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_PGALLOC_H -#define _PPC_PGALLOC_H - -#include - -extern void __bad_pte(pmd_t *pmd); - -extern pgd_t *pgd_alloc(struct mm_struct *mm); -extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); - -/* - * We don't have any real pmd's, and this code never triggers because - * the pgd will always be present.. - */ -#define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); }) -#define pmd_free(mm, x) do { } while (0) -#define __pmd_free_tlb(tlb,x) do { } while (0) -#define pgd_populate(mm, pmd, pte) BUG() - -#ifndef CONFIG_BOOKE -#define pmd_populate_kernel(mm, pmd, pte) \ - (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) -#define pmd_populate(mm, pmd, pte) \ - (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) -#define pmd_pgtable(pmd) pmd_page(pmd) -#else -#define pmd_populate_kernel(mm, pmd, pte) \ - (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) -#define pmd_populate(mm, pmd, pte) \ - (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT) -#define pmd_pgtable(pmd) pmd_page(pmd) -#endif - -extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); -extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr); -extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte); -extern void pte_free(struct mm_struct *mm, pgtable_t pte); - -#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte)) - -#define check_pgt_cache() do { } while (0) - -#endif /* _PPC_PGALLOC_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h deleted file mode 100644 index 55f9d38e3bf8..000000000000 --- a/include/asm-ppc/pgtable.h +++ /dev/null @@ -1,771 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_PGTABLE_H -#define _PPC_PGTABLE_H - -#include - - -#ifndef __ASSEMBLY__ -#include -#include -#include /* For TASK_SIZE */ -#include -#include -#include /* For sub-arch specific PPC_PIN_SIZE */ -struct mm_struct; - -extern unsigned long va_to_phys(unsigned long address); -extern pte_t *va_to_pte(unsigned long address); -extern unsigned long ioremap_bot, ioremap_base; -#endif /* __ASSEMBLY__ */ - -/* - * The PowerPC MMU uses a hash table containing PTEs, together with - * a set of 16 segment registers (on 32-bit implementations), to define - * the virtual to physical address mapping. - * - * We use the hash table as an extended TLB, i.e. a cache of currently - * active mappings. We maintain a two-level page table tree, much - * like that used by the i386, for the sake of the Linux memory - * management code. Low-level assembler code in hashtable.S - * (procedure hash_page) is responsible for extracting ptes from the - * tree and putting them into the hash table when necessary, and - * updating the accessed and modified bits in the page table tree. - */ - -/* - * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. - * We also use the two level tables, but we can put the real bits in them - * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, - * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has - * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit - * based upon user/super access. The TLB does not have accessed nor write - * protect. We assume that if the TLB get loaded with an entry it is - * accessed, and overload the changed bit for write protect. We use - * two bits in the software pte that are supposed to be set to zero in - * the TLB entry (24 and 25) for these indicators. Although the level 1 - * descriptor contains the guarded and writethrough/copyback bits, we can - * set these at the page level since they get copied from the Mx_TWC - * register when the TLB entry is loaded. We will use bit 27 for guard, since - * that is where it exists in the MD_TWC, and bit 26 for writethrough. - * These will get masked from the level 2 descriptor at TLB load time, and - * copied to the MD_TWC before it gets loaded. - * Large page sizes added. We currently support two sizes, 4K and 8M. - * This also allows a TLB hander optimization because we can directly - * load the PMD into MD_TWC. The 8M pages are only used for kernel - * mapping of well known areas. The PMD (PGD) entries contain control - * flags in addition to the address, so care must be taken that the - * software no longer assumes these are only pointers. - */ - -/* - * At present, all PowerPC 400-class processors share a similar TLB - * architecture. The instruction and data sides share a unified, - * 64-entry, fully-associative TLB which is maintained totally under - * software control. In addition, the instruction side has a - * hardware-managed, 4-entry, fully-associative TLB which serves as a - * first level to the shared TLB. These two TLBs are known as the UTLB - * and ITLB, respectively (see "mmu.h" for definitions). - */ - -/* - * The normal case is that PTEs are 32-bits and we have a 1-page - * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus - * - * For any >32-bit physical address platform, we can use the following - * two level page table layout where the pgdir is 8KB and the MS 13 bits - * are an index to the second level table. The combined pgdir/pmd first - * level has 2048 entries and the second level has 512 64-bit PTE entries. - * -Matt - */ -/* PMD_SHIFT determines the size of the area mapped by the PTE pages */ -#define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT) -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a top-level page table entry can map */ -#define PGDIR_SHIFT PMD_SHIFT -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * entries per page directory level: our page-table tree is two-level, so - * we don't really have any PMD directory. - */ -#define PTRS_PER_PTE (1 << PTE_SHIFT) -#define PTRS_PER_PMD 1 -#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) - -#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0 - -#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) -#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) - -#define pte_ERROR(e) \ - printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e)) -#define pmd_ERROR(e) \ - printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) -#define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 64MB value just means that there will be a 64MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - * - * We no longer map larger than phys RAM with the BATs so we don't have - * to worry about the VMALLOC_OFFSET causing problems. We do have to worry - * about clashes between our early calls to ioremap() that start growing down - * from ioremap_base being run into the VM area allocations (growing upwards - * from VMALLOC_START). For this reason we have ioremap_bot to check when - * we actually run into our mappings setup in the early boot with the VM - * system. This really does become a problem for machines with good amounts - * of RAM. -- Cort - */ -#define VMALLOC_OFFSET (0x1000000) /* 16M */ -#ifdef PPC_PIN_SIZE -#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) -#else -#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) -#endif -#define VMALLOC_END ioremap_bot - -/* - * Bits in a linux-style PTE. These match the bits in the - * (hardware-defined) PowerPC PTE as closely as possible. - */ - -#if defined(CONFIG_40x) - -/* There are several potential gotchas here. The 40x hardware TLBLO - field looks like this: - - 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - RPN..................... 0 0 EX WR ZSEL....... W I M G - - Where possible we make the Linux PTE bits match up with this - - - bits 20 and 21 must be cleared, because we use 4k pages (40x can - support down to 1k pages), this is done in the TLBMiss exception - handler. - - We use only zones 0 (for kernel pages) and 1 (for user pages) - of the 16 available. Bit 24-26 of the TLB are cleared in the TLB - miss handler. Bit 27 is PAGE_USER, thus selecting the correct - zone. - - PRESENT *must* be in the bottom two bits because swap cache - entries use the top 30 bits. Because 40x doesn't support SMP - anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 - is cleared in the TLB miss handler before the TLB entry is loaded. - - All other bits of the PTE are loaded into TLBLO without - modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for - software PTE bits. We actually use use bits 21, 24, 25, and - 30 respectively for the software bits: ACCESSED, DIRTY, RW, and - PRESENT. -*/ - -/* Definitions for 40x embedded chips. */ -#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ -#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */ -#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ -#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ -#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ -#define _PAGE_USER 0x010 /* matches one of the zone permission bits */ -#define _PAGE_RW 0x040 /* software: Writes permitted */ -#define _PAGE_DIRTY 0x080 /* software: dirty page */ -#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ -#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ -#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ - -#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */ -#define _PMD_BAD 0x802 -#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */ -#define _PMD_SIZE_4M 0x0c0 -#define _PMD_SIZE_16M 0x0e0 -#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4)) - -#elif defined(CONFIG_44x) -/* - * Definitions for PPC440 - * - * Because of the 3 word TLB entries to support 36-bit addressing, - * the attribute are difficult to map in such a fashion that they - * are easily loaded during exception processing. I decided to - * organize the entry so the ERPN is the only portion in the - * upper word of the PTE and the attribute bits below are packed - * in as sensibly as they can be in the area below a 4KB page size - * oriented RPN. This at least makes it easy to load the RPN and - * ERPN fields in the TLB. -Matt - * - * Note that these bits preclude future use of a page size - * less than 4KB. - * - * - * PPC 440 core has following TLB attribute fields; - * - * TLB1: - * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - * RPN................................. - - - - - - ERPN....... - * - * TLB2: - * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR - * - * There are some constrains and options, to decide mapping software bits - * into TLB entry. - * - * - PRESENT *must* be in the bottom three bits because swap cache - * entries use the top 29 bits for TLB2. - * - * - FILE *must* be in the bottom three bits because swap cache - * entries use the top 29 bits for TLB2. - * - * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it - * doesn't support SMP. So we can use this as software bit, like - * DIRTY. - * - * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used - * for memory protection related functions (see PTE structure in - * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the - * above bits. Note that the bit values are CPU specific, not architecture - * specific. - * - * The kernel PTE entry holds an arch-dependent swp_entry structure under - * certain situations. In other words, in such situations some portion of - * the PTE bits are used as a swp_entry. In the PPC implementation, the - * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still - * hold protection values. That means the three protection bits are - * reserved for both PTE and SWAP entry at the most significant three - * LSBs. - * - * There are three protection bits available for SWAP entry: - * _PAGE_PRESENT - * _PAGE_FILE - * _PAGE_HASHPTE (if HW has) - * - * So those three bits have to be inside of 0-2nd LSB of PTE. - * - */ - -#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ -#define _PAGE_RW 0x00000002 /* S: Write permission */ -#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */ -#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ -#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ -#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ -#define _PAGE_USER 0x00000040 /* S: User page */ -#define _PAGE_ENDIAN 0x00000080 /* H: E bit */ -#define _PAGE_GUARDED 0x00000100 /* H: G bit */ -#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */ -#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ -#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ - -/* TODO: Add large page lowmem mapping support */ -#define _PMD_PRESENT 0 -#define _PMD_PRESENT_MASK (PAGE_MASK) -#define _PMD_BAD (~PAGE_MASK) - -/* ERPN in a PTE never gets cleared, ignore it */ -#define _PTE_NONE_MASK 0xffffffff00000000ULL - -#elif defined(CONFIG_8xx) -/* Definitions for 8xx embedded chips. */ -#define _PAGE_PRESENT 0x0001 /* Page is valid */ -#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */ -#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ -#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ - -/* These five software bits must be masked out when the entry is loaded - * into the TLB. - */ -#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ -#define _PAGE_GUARDED 0x0010 /* software: guarded access */ -#define _PAGE_DIRTY 0x0020 /* software: page changed */ -#define _PAGE_RW 0x0040 /* software: user write access allowed */ -#define _PAGE_ACCESSED 0x0080 /* software: page referenced */ - -/* Setting any bits in the nibble with the follow two controls will - * require a TLB exception handler change. It is assumed unused bits - * are always zero. - */ -#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */ -#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */ - -#define _PMD_PRESENT 0x0001 -#define _PMD_BAD 0x0ff0 -#define _PMD_PAGE_MASK 0x000c -#define _PMD_PAGE_8M 0x000c - -#define _PTE_NONE_MASK _PAGE_ACCESSED - -#else /* CONFIG_6xx */ -/* Definitions for 60x, 740/750, etc. */ -#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ -#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ -#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */ -#define _PAGE_USER 0x004 /* usermode access allowed */ -#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ -#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ -#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ -#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ -#define _PAGE_DIRTY 0x080 /* C: page changed */ -#define _PAGE_ACCESSED 0x100 /* R: page referenced */ -#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */ -#define _PAGE_RW 0x400 /* software: user write access allowed */ - -#define _PTE_NONE_MASK _PAGE_HASHPTE - -#define _PMD_PRESENT 0 -#define _PMD_PRESENT_MASK (PAGE_MASK) -#define _PMD_BAD (~PAGE_MASK) -#endif - -/* - * Some bits are only used on some cpu families... - */ -#ifndef _PAGE_HASHPTE -#define _PAGE_HASHPTE 0 -#endif -#ifndef _PTE_NONE_MASK -#define _PTE_NONE_MASK 0 -#endif -#ifndef _PAGE_SHARED -#define _PAGE_SHARED 0 -#endif -#ifndef _PAGE_HWWRITE -#define _PAGE_HWWRITE 0 -#endif -#ifndef _PAGE_HWEXEC -#define _PAGE_HWEXEC 0 -#endif -#ifndef _PAGE_EXEC -#define _PAGE_EXEC 0 -#endif -#ifndef _PMD_PRESENT_MASK -#define _PMD_PRESENT_MASK _PMD_PRESENT -#endif -#ifndef _PMD_SIZE -#define _PMD_SIZE 0 -#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE() -#endif - -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) - -/* - * Note: the _PAGE_COHERENT bit automatically gets set in the hardware - * PTE if CONFIG_SMP is defined (hash_page does this); there is no need - * to have it in the Linux PTE, and in fact the bit could be reused for - * another purpose. -- paulus. - */ - -#ifdef CONFIG_44x -#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED) -#else -#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) -#endif -#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) -#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE) - -#ifdef CONFIG_PPC_STD_MMU -/* On standard PPC MMU, no user access implies kernel read/write access, - * so to write-protect kernel memory we must turn on user access */ -#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER) -#else -#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED) -#endif - -#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) -#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC) - -#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) -/* We want the debuggers to be able to set breakpoints anywhere, so - * don't write protect the kernel text */ -#define _PAGE_RAM_TEXT _PAGE_RAM -#else -#define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC) -#endif - -#define PAGE_NONE __pgprot(_PAGE_BASE) -#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) -#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) -#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) -#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) -#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) -#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) - -#define PAGE_KERNEL __pgprot(_PAGE_RAM) -#define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO) - -/* - * The PowerPC can only do execute protection on a segment (256MB) basis, - * not on a page basis. So we consider execute permission the same as read. - * Also, write permissions imply read permissions. - * This is the closest we can get.. - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY_X -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY_X -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY_X -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY_X - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY_X -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED_X -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY_X -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED_X - -#ifndef __ASSEMBLY__ -/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a - * kernel without large page PMD support */ -extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); - -/* - * Conversions between PTE values and page frame numbers. - */ - -/* in some case we want to additionaly adjust where the pfn is in the pte to - * allow room for more flags */ -#define PFN_SHIFT_OFFSET (PAGE_SHIFT) - -#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) -#define pte_page(x) pfn_to_page(pte_pfn(x)) - -#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\ - pgprot_val(prot)) -#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) - -/* - * ZERO_PAGE is a global shared page that is always zero: used - * for zero-mapped memory areas etc.. - */ -extern unsigned long empty_zero_page[1024]; -#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) - -#endif /* __ASSEMBLY__ */ - -#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) -#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) -#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) - -#define pmd_none(pmd) (!pmd_val(pmd)) -#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) -#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) -#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) - -#ifndef __ASSEMBLY__ -/* - * The "pgd_xxx()" functions here are trivial for a folded two-level - * setup: the pgd is never bad, and a pmd always exists (as it's folded - * into the pgd entry) - */ -static inline int pgd_none(pgd_t pgd) { return 0; } -static inline int pgd_bad(pgd_t pgd) { return 0; } -static inline int pgd_present(pgd_t pgd) { return 1; } -#define pgd_clear(xp) do { } while (0) - -#define pgd_page_vaddr(pgd) \ - ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK)) - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ -static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } -static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } -static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } -static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } -static inline int pte_special(pte_t pte) { return 0; } - -static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } -static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } - -static inline pte_t pte_wrprotect(pte_t pte) { - pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } -static inline pte_t pte_mkclean(pte_t pte) { - pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } -static inline pte_t pte_mkold(pte_t pte) { - pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } - -static inline pte_t pte_mkwrite(pte_t pte) { - pte_val(pte) |= _PAGE_RW; return pte; } -static inline pte_t pte_mkdirty(pte_t pte) { - pte_val(pte) |= _PAGE_DIRTY; return pte; } -static inline pte_t pte_mkyoung(pte_t pte) { - pte_val(pte) |= _PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkspecial(pte_t pte) { - return pte; } - -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); - return pte; -} - -/* - * When flushing the tlb entry for a page, we also need to flush the hash - * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. - */ -extern int flush_hash_pages(unsigned context, unsigned long va, - unsigned long pmdval, int count); - -/* Add an HPTE to the hash table */ -extern void add_hash_page(unsigned context, unsigned long va, - unsigned long pmdval); - -/* - * Atomic PTE updates. - * - * pte_update clears and sets bit atomically, and returns - * the old pte value. In the 64-bit PTE case we lock around the - * low PTE word since we expect ALL flag bits to be there - */ -#ifndef CONFIG_PTE_64BIT -static inline unsigned long pte_update(pte_t *p, unsigned long clr, - unsigned long set) -{ - unsigned long old, tmp; - - __asm__ __volatile__("\ -1: lwarx %0,0,%3\n\ - andc %1,%0,%4\n\ - or %1,%1,%5\n" - PPC405_ERR77(0,%3) -" stwcx. %1,0,%3\n\ - bne- 1b" - : "=&r" (old), "=&r" (tmp), "=m" (*p) - : "r" (p), "r" (clr), "r" (set), "m" (*p) - : "cc" ); - return old; -} -#else -static inline unsigned long long pte_update(pte_t *p, unsigned long clr, - unsigned long set) -{ - unsigned long long old; - unsigned long tmp; - - __asm__ __volatile__("\ -1: lwarx %L0,0,%4\n\ - lwzx %0,0,%3\n\ - andc %1,%L0,%5\n\ - or %1,%1,%6\n" - PPC405_ERR77(0,%3) -" stwcx. %1,0,%4\n\ - bne- 1b" - : "=&r" (old), "=&r" (tmp), "=m" (*p) - : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) - : "cc" ); - return old; -} -#endif - -/* - * set_pte stores a linux PTE into the linux page table. - * On machines which use an MMU hash table we avoid changing the - * _PAGE_HASHPTE bit. - */ -static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, - pte_t *ptep, pte_t pte) -{ -#if _PAGE_HASHPTE != 0 - pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE); -#else - *ptep = pte; -#endif -} - -/* - * 2.6 calles this without flushing the TLB entry, this is wrong - * for our hash-based implementation, we fix that up here - */ -#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG -static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep) -{ - unsigned long old; - old = pte_update(ptep, _PAGE_ACCESSED, 0); -#if _PAGE_HASHPTE != 0 - if (old & _PAGE_HASHPTE) { - unsigned long ptephys = __pa(ptep) & PAGE_MASK; - flush_hash_pages(context, addr, ptephys, 1); - } -#endif - return (old & _PAGE_ACCESSED) != 0; -} -#define ptep_test_and_clear_young(__vma, __addr, __ptep) \ - __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep) - -#define __HAVE_ARCH_PTEP_GET_AND_CLEAR -static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, - pte_t *ptep) -{ - return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); -} - -#define __HAVE_ARCH_PTEP_SET_WRPROTECT -static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, - pte_t *ptep) -{ - pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); -} - -#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS -static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) -{ - unsigned long bits = pte_val(entry) & - (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW); - pte_update(ptep, 0, bits); -} - -#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ -({ \ - int __changed = !pte_same(*(__ptep), __entry); \ - if (__changed) { \ - __ptep_set_access_flags(__ptep, __entry, __dirty); \ - flush_tlb_page_nohash(__vma, __address); \ - } \ - __changed; \ -}) - -/* - * Macro to mark a page protection value as "uncacheable". - */ -#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) - -struct file; -extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, - unsigned long size, pgprot_t vma_prot); -#define __HAVE_PHYS_MEM_ACCESS_PROT - -#define __HAVE_ARCH_PTE_SAME -#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) - -/* - * Note that on Book E processors, the pmd contains the kernel virtual - * (lowmem) address of the pte page. The physical address is less useful - * because everything runs with translation enabled (even the TLB miss - * handler). On everything else the pmd contains the physical address - * of the pte page. -- paulus - */ -#ifndef CONFIG_BOOKE -#define pmd_page_vaddr(pmd) \ - ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) -#define pmd_page(pmd) \ - (mem_map + (pmd_val(pmd) >> PAGE_SHIFT)) -#else -#define pmd_page_vaddr(pmd) \ - ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) -#define pmd_page(pmd) \ - (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT)) -#endif - -/* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -/* to find an entry in a page-table-directory */ -#define pgd_index(address) ((address) >> PGDIR_SHIFT) -#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) - -/* Find an entry in the second-level page table.. */ -static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) -{ - return (pmd_t *) dir; -} - -/* Find an entry in the third-level page table.. */ -#define pte_index(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset_kernel(dir, addr) \ - ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr)) -#define pte_offset_map(dir, addr) \ - ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr)) -#define pte_offset_map_nested(dir, addr) \ - ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr)) - -#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) -#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) - -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; - -extern void paging_init(void); - -/* - * Encode and decode a swap entry. - * Note that the bits we use in a PTE for representing a swap entry - * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the - *_PAGE_HASHPTE bit (if used). -- paulus - */ -#define __swp_type(entry) ((entry).val & 0x1f) -#define __swp_offset(entry) ((entry).val >> 5) -#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) - -/* Encode and decode a nonlinear file mapping entry */ -#define PTE_FILE_MAX_BITS 29 -#define pte_to_pgoff(pte) (pte_val(pte) >> 3) -#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) - -/* Values for nocacheflag and cmode */ -/* These are not used by the APUS kernel_map, but prevents - compilation errors. */ -#define KERNELMAP_FULL_CACHING 0 -#define KERNELMAP_NOCACHE_SER 1 -#define KERNELMAP_NOCACHE_NONSER 2 -#define KERNELMAP_NO_COPYBACK 3 - -/* - * Map some physical address range into the kernel address space. - */ -extern unsigned long kernel_map(unsigned long paddr, unsigned long size, - int nocacheflag, unsigned long *memavailp ); - -/* - * Set cache mode of (kernel space) address range. - */ -extern void kernel_set_cachemode (unsigned long address, unsigned long size, - unsigned int cmode); - -/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ -#define kern_addr_valid(addr) (1) - -#ifdef CONFIG_PHYS_64BIT -extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, - unsigned long paddr, unsigned long size, pgprot_t prot); - -static inline int io_remap_pfn_range(struct vm_area_struct *vma, - unsigned long vaddr, - unsigned long pfn, - unsigned long size, - pgprot_t prot) -{ - phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); - return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot); -} -#else -#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ - remap_pfn_range(vma, vaddr, pfn, size, prot) -#endif - -/* - * No page table caches to initialise - */ -#define pgtable_cache_init() do { } while (0) - -extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep, - pmd_t **pmdp); - -#include - -#endif /* !__ASSEMBLY__ */ - -#endif /* _PPC_PGTABLE_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h deleted file mode 100644 index 6f6760b30dd8..000000000000 --- a/include/asm-ppc/pnp.h +++ /dev/null @@ -1,645 +0,0 @@ -#ifdef __KERNEL__ -/* 11/02/95 */ -/*----------------------------------------------------------------------------*/ -/* Plug and Play header definitions */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for PnP on PowerPC Reference Platform */ -/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ -/* (or later versions) is available on Compuserve in the PLUGPLAY area. */ -/* This code has extensions to that specification, namely new short and */ -/* long tag types for platform dependent information */ - -/* Warning: LE notation used throughout this file */ - -/* For enum's: if given in hex then they are bit significant, i.e. */ -/* only one bit is on for each enum */ - -#ifndef _PNP_ -#define _PNP_ - -#ifndef __ASSEMBLY__ -#define MAX_MEM_REGISTERS 9 -#define MAX_IO_PORTS 20 -#define MAX_IRQS 7 -/*#define MAX_DMA_CHANNELS 7*/ - -/* Interrupt controllers */ - -#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ -#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ -#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ -#define PNPinterrupt3 "PNP0003" /* APIC */ -#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ - -/* Timers */ - -#define PNPtimer0 "PNP0100" /* AT Timer */ -#define PNPtimer1 "PNP0101" /* EISA Timer */ -#define PNPtimer2 "PNP0102" /* MCA Timer */ - -/* DMA controllers */ - -#define PNPdma0 "PNP0200" /* AT DMA Controller */ -#define PNPdma1 "PNP0201" /* EISA DMA Controller */ -#define PNPdma2 "PNP0202" /* MCA DMA Controller */ - -/* start of August 15, 1994 additions */ -/* CMOS */ -#define PNPCMOS "IBM0009" /* CMOS */ - -/* L2 Cache */ -#define PNPL2 "IBM0007" /* L2 Cache */ - -/* NVRAM */ -#define PNPNVRAM "IBM0008" /* NVRAM */ - -/* Power Management */ -#define PNPPM "IBM0005" /* Power Management */ -/* end of August 15, 1994 additions */ - -/* Keyboards */ - -#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ -#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ -#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ -#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ -#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ -#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ -#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ -#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ - -/* Parallel port controllers */ - -#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ -#define PNPparallel1 "PNP0401" /* ECP Parallel Port */ -#define PNPepp "IBM001C" /* EPP Parallel Port */ - -/* Serial port controllers */ - -#define PNPserial0 "PNP0500" /* Standard PC Serial port */ -#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ - -/* Disk controllers */ - -#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ -#define PNPdisk1 "PNP0601" /* Plus Hardcard II */ -#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ - -/* Diskette controllers */ - -#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ - -/* Display controllers */ - -#define PNPdisplay0 "PNP0900" /* VGA Compatible */ -#define PNPdisplay1 "PNP0901" /* Video Seven VGA */ -#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ -#define PNPdisplay3 "PNP0903" /* Trident VGA */ -#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ -#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ -#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ -#define PNPdisplay7 "PNP0907" /* Western Digital VGA */ -#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ -#define PNPdisplay9 "PNP0909" /* S3 */ -#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ -#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ -#define PNPdisplayC "PNP090C" /* XGA Compatible */ -#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ -#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ -#define PNPdisplayF "PNP090F" /* Oak Technology VGA */ - -/* Peripheral busses */ - -#define PNPbuses0 "PNP0A00" /* ISA Bus */ -#define PNPbuses1 "PNP0A01" /* EISA Bus */ -#define PNPbuses2 "PNP0A02" /* MCA Bus */ -#define PNPbuses3 "PNP0A03" /* PCI Bus */ -#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ - -/* RTC, BIOS, planar devices */ - -#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ -#define PNPrtc0 "PNP0B00" /* AT RTC */ -#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ -#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ -#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ -#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ - -/* PCMCIA controller */ - -#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ - -/* Mice */ - -#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ -#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ -#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ -#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ -#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ -#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ -#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ -#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ -#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ -#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ -#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ -#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ - -/* Modems */ - -#define PNPmodem0 "PNP9000" /* Specific IDs TBD */ - -/* Network controllers */ - -#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ -#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ -#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ -#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ -#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ -#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ -#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ -#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ - -/* SCSI controllers */ - -#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ -#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ -#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ -#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ -#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ -#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ -#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ - -/* Sound/Video, Multimedia */ - -#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ -#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ -#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ -#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ -#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ -#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ -#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ -#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ - -/* Operator Panel */ -#define PNPopctl "IBM000B" /* Operator's panel */ - -/* Service Processor */ -#define PNPsp "IBM0011" /* IBM Service Processor */ -#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ -#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ - -/* Memory Controller */ -#define PNPmemctl "IBM000A" /* Memory controller */ - -/* Graphics Assist */ -#define PNPg_assist "IBM0014" /* Graphics Assist */ - -/* Miscellaneous Device Controllers */ -#define PNPtablet "IBM0019" /* IBM Tablet Controller */ - -/* PNP Packet Handles */ - -#define S1_Packet 0x0A /* Version resource */ -#define S2_Packet 0x15 /* Logical DEVID (without flags) */ -#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ -#define S3_Packet 0x1C /* Compatible device ID */ -#define S4_Packet 0x22 /* IRQ resource (without flags) */ -#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ -#define S5_Packet 0x2A /* DMA resource */ -#define S6_Packet 0x30 /* Depend funct start (w/o priority) */ -#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ -#define S7_Packet 0x38 /* Depend funct end */ -#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ -#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ -#define S14_Packet 0x71 /* Vendor defined */ -#define S15_Packet 0x78 /* End of resource (w/o checksum) */ -#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ -#define L1_Packet 0x81 /* Memory range */ -#define L1_Shadow 0x20 /* Memory is shadowable */ -#define L1_32bit_mem 0x18 /* 32-bit memory only */ -#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ -#define L1_Decode_Hi 0x04 /* decode supports high address */ -#define L1_Cache 0x02 /* read cacheable, write-through */ -#define L1_Writeable 0x01 /* Memory is writeable */ -#define L2_Packet 0x82 /* ANSI ID string */ -#define L3_Packet 0x83 /* Unicode ID string */ -#define L4_Packet 0x84 /* Vendor defined */ -#define L5_Packet 0x85 /* Large I/O */ -#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ -#define END_TAG 0x78 /* End of resource */ -#define DF_START_TAG 0x30 /* Dependent function start */ -#define DF_START_TAG_priority 0x31 /* Dependent function start */ -#define DF_END_TAG 0x38 /* Dependent function end */ -#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ - -/* Device Base Type Codes */ - -typedef enum _PnP_BASE_TYPE { - Reserved = 0, - MassStorageDevice = 1, - NetworkInterfaceController = 2, - DisplayController = 3, - MultimediaController = 4, - MemoryController = 5, - BridgeController = 6, - CommunicationsDevice = 7, - SystemPeripheral = 8, - InputDevice = 9, - ServiceProcessor = 0x0A, /* 11/2/95 */ - } PnP_BASE_TYPE; - -/* Device Sub Type Codes */ - -typedef enum _PnP_SUB_TYPE { - SCSIController = 0, - IDEController = 1, - FloppyController = 2, - IPIController = 3, - OtherMassStorageController = 0x80, - - EthernetController = 0, - TokenRingController = 1, - FDDIController = 2, - OtherNetworkController = 0x80, - - VGAController= 0, - SVGAController= 1, - XGAController= 2, - OtherDisplayController = 0x80, - - VideoController = 0, - AudioController = 1, - OtherMultimediaController = 0x80, - - RAM = 0, - FLASH = 1, - OtherMemoryDevice = 0x80, - - HostProcessorBridge = 0, - ISABridge = 1, - EISABridge = 2, - MicroChannelBridge = 3, - PCIBridge = 4, - PCMCIABridge = 5, - VMEBridge = 6, - OtherBridgeDevice = 0x80, - - RS232Device = 0, - ATCompatibleParallelPort = 1, - OtherCommunicationsDevice = 0x80, - - ProgrammableInterruptController = 0, - DMAController = 1, - SystemTimer = 2, - RealTimeClock = 3, - L2Cache = 4, - NVRAM = 5, - PowerManagement = 6, - CMOS = 7, - OperatorPanel = 8, - ServiceProcessorClass1 = 9, - ServiceProcessorClass2 = 0xA, - ServiceProcessorClass3 = 0xB, - GraphicAssist = 0xC, - SystemPlanar = 0xF, /* 10/5/95 */ - OtherSystemPeripheral = 0x80, - - KeyboardController = 0, - Digitizer = 1, - MouseController = 2, - TabletController = 3, /* 10/27/95 */ - OtherInputController = 0x80, - - GeneralMemoryController = 0, - } PnP_SUB_TYPE; - -/* Device Interface Type Codes */ - -typedef enum _PnP_INTERFACE { - General = 0, - GeneralSCSI = 0, - GeneralIDE = 0, - ATACompatible = 1, - - GeneralFloppy = 0, - Compatible765 = 1, - NS398_Floppy = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26E_Floppy = 3, /* Ports 26E and 26F */ - NS15C_Floppy = 4, /* Ports 15C and 15D */ - NS2E_Floppy = 5, /* Ports 2E and 2F */ - CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ - - GeneralIPI = 0, - - GeneralEther = 0, - GeneralToken = 0, - GeneralFDDI = 0, - - GeneralVGA = 0, - GeneralSVGA = 0, - GeneralXGA = 0, - - GeneralVideo = 0, - GeneralAudio = 0, - CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ - - GeneralRAM = 0, - GeneralFLASH = 0, - PCIMemoryController = 0, /* PCI Config Method */ - RS6KMemoryController = 1, /* RS6K Config Method */ - - GeneralHostBridge = 0, - GeneralISABridge = 0, - GeneralEISABridge = 0, - GeneralMCABridge = 0, - GeneralPCIBridge = 0, - PCIBridgeDirect = 0, - PCIBridgeIndirect = 1, - PCIBridgeRS6K = 2, - GeneralPCMCIABridge = 0, - GeneralVMEBridge = 0, - - GeneralRS232 = 0, - COMx = 1, - Compatible16450 = 2, - Compatible16550 = 3, - NS398SerPort = 4, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26ESerPort = 5, /* Ports 26E and 26F */ - NS15CSerPort = 6, /* Ports 15C and 15D */ - NS2ESerPort = 7, /* Ports 2E and 2F */ - - GeneralParPort = 0, - LPTx = 1, - NS398ParPort = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26EParPort = 3, /* Ports 26E and 26F */ - NS15CParPort = 4, /* Ports 15C and 15D */ - NS2EParPort = 5, /* Ports 2E and 2F */ - - GeneralPIC = 0, - ISA_PIC = 1, - EISA_PIC = 2, - MPIC = 3, - RS6K_PIC = 4, - - GeneralDMA = 0, - ISA_DMA = 1, - EISA_DMA = 2, - - GeneralTimer = 0, - ISA_Timer = 1, - EISA_Timer = 2, - GeneralRTC = 0, - ISA_RTC = 1, - - StoreThruOnly = 1, - StoreInEnabled = 2, - RS6KL2Cache = 3, - - IndirectNVRAM = 0, /* Indirectly addressed */ - DirectNVRAM = 1, /* Memory Mapped */ - IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ - - GeneralPowerManagement = 0, - EPOWPowerManagement = 1, - PowerControl = 2, // d1378 - - GeneralCMOS = 0, - - GeneralOPPanel = 0, - HarddiskLight = 1, - CDROMLight = 2, - PowerLight = 3, - KeyLock = 4, - ANDisplay = 5, /* AlphaNumeric Display */ - SystemStatusLED = 6, /* 3 digit 7 segment LED */ - CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ - - GeneralServiceProcessor = 0, - - TransferData = 1, - IGMC32 = 2, - IGMC64 = 3, - - GeneralSystemPlanar = 0, /* 10/5/95 */ - - } PnP_INTERFACE; - -/* PnP resources */ - -/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ - -typedef struct _SERIAL_ID { - unsigned char VendorID0; /* Bit(7)=0 */ - /* Bits(6:2)=1st character in */ - /* compressed ASCII */ - /* Bits(1:0)=2nd character in */ - /* compressed ASCII bits(4:3) */ - unsigned char VendorID1; /* Bits(7:5)=2nd character in */ - /* compressed ASCII bits(2:0) */ - /* Bits(4:0)=3rd character in */ - /* compressed ASCII */ - unsigned char VendorID2; /* Product number - vendor assigned */ - unsigned char VendorID3; /* Product number - vendor assigned */ - -/* Serial number is to provide uniqueness if more than one board of same */ -/* type is in system. Must be "FFFFFFFF" if feature not supported. */ - - unsigned char Serial0; /* Unique serial number bits (7:0) */ - unsigned char Serial1; /* Unique serial number bits (15:8) */ - unsigned char Serial2; /* Unique serial number bits (23:16) */ - unsigned char Serial3; /* Unique serial number bits (31:24) */ - unsigned char Checksum; - } SERIAL_ID; - -typedef enum _PnPItemName { - Unused = 0, - PnPVersion = 1, - LogicalDevice = 2, - CompatibleDevice = 3, - IRQFormat = 4, - DMAFormat = 5, - StartDepFunc = 6, - EndDepFunc = 7, - IOPort = 8, - FixedIOPort = 9, - Res1 = 10, - Res2 = 11, - Res3 = 12, - SmallVendorItem = 14, - EndTag = 15, - MemoryRange = 1, - ANSIIdentifier = 2, - UnicodeIdentifier = 3, - LargeVendorItem = 4, - MemoryRange32 = 5, - MemoryRangeFixed32 = 6, - } PnPItemName; - -/* Define a bunch of access functions for the bits in the tag field */ - -/* Tag type - 0 = small; 1 = large */ -#define tag_type(t) (((t) & 0x80)>>7) -#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) - -/* Small item name is 4 bits - one of PnPItemName enum above */ -#define tag_small_item_name(t) (((t) & 0x78)>>3) -#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) - -/* Small item count is 3 bits - count of further bytes in packet */ -#define tag_small_count(t) ((t) & 0x07) -#define set_tag_count(t,v) (t = (t & 0x78) | (v)) - -/* Large item name is 7 bits - one of PnPItemName enum above */ -#define tag_large_item_name(t) ((t) & 0x7f) -#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) - -/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ - -typedef union _PnP_TAG_PACKET { - struct _S1_Pack{ /* VERSION PACKET */ - unsigned char Tag; /* small tag = 0x0a */ - unsigned char Version[2]; /* PnP version, Vendor version */ - } S1_Pack; - - struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x15 or 0x16 */ - unsigned char DevId[4]; /* Logical device id */ - unsigned char Flags[2]; /* bit(0) boot device; */ - /* bit(7:1) cmd in range x31-x37 */ - /* bit(7:0) cmd in range x28-x3f (opt)*/ - } S2_Pack; - - struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x1c */ - unsigned char CompatId[4]; /* Compatible device id */ - } S3_Pack; - - struct _S4_Pack{ /* IRQ PACKET */ - unsigned char Tag; /* small tag = 0x22 or 0x23 */ - unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ - /* bit(0) is IRQ8 ... */ - unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ - /* bit(0) - high true edge sensitive */ - /* bit(1) - low true edge sensitive */ - /* bit(2) - high true level sensitive*/ - /* bit(3) - low true level sensitive */ - /* bit(7:4) - must be 0 */ - } S4_Pack; - - struct _S5_Pack{ /* DMA PACKET */ - unsigned char Tag; /* small tag = 0x2a */ - unsigned char DMAMask; /* bit(0) is channel 0 ... */ - unsigned char DMAInfo; - } S5_Pack; - - struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x30 or 0x31 */ - unsigned char Priority; /* Optional; if missing then x01; else*/ - /* x00 = best possible */ - /* x01 = acceptible */ - /* x02 = sub-optimal but functional */ - } S6_Pack; - - struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x38 */ - } S7_Pack; - - struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ - unsigned char Tag; /* small tag x47 */ - unsigned char IOInfo; /* x0 = decode only bits(9:0); */ -#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ - unsigned char RangeMin[2]; /* Min base address */ - unsigned char RangeMax[2]; /* Max base address */ - unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S8_Pack; - - struct _S9_Pack{ /* FIXED I/O PORT PACKET */ - unsigned char Tag; /* small tag = 0x4b */ - unsigned char Range[2]; /* base address 10 bits */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S9_Pack; - - struct _S14_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* small tag = 0x7m m = 1-7 */ - union _S14_Data{ - unsigned char Data[7]; /* Vendor defined */ - struct _S14_PPCPack{ /* Pr*p s14 pack */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[6]; /* Vendor defined */ - } S14_PPCPack; - } S14_Data; - } S14_Pack; - - struct _S15_Pack{ /* END PACKET */ - unsigned char Tag; /* small tag = 0x78 or 0x79 */ - unsigned char Check; /* optional - checksum */ - } S15_Pack; - - struct _L1_Pack{ /* MEMORY RANGE PACKET */ - unsigned char Tag; /* large tag = 0x81 */ - unsigned char Count0; /* x09 */ - unsigned char Count1; /* x00 */ - unsigned char Data[9]; /* a variable array of bytes, */ - /* count in tag */ - } L1_Pack; - - struct _L2_Pack{ /* ANSI ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x82 */ - unsigned char Count0; /* Length of string */ - unsigned char Count1; - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L2_Pack; - - struct _L3_Pack{ /* UNICODE ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x83 */ - unsigned char Count0; /* Length + 2 of string */ - unsigned char Count1; - unsigned char Country0; /* TBD */ - unsigned char Country1; /* TBD */ - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L3_Pack; - - struct _L4_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* large tag = 0x84 */ - unsigned char Count0; - unsigned char Count1; - union _L4_Data{ - unsigned char Data[1]; /* a variable array of bytes, */ - /* count in tag */ - struct _L4_PPCPack{ /* Pr*p L4 packet */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[1]; /* a variable array of bytes, */ - /* count in tag */ - } L4_PPCPack; - } L4_Data; - } L4_Pack; - - struct _L5_Pack{ - unsigned char Tag; /* large tag = 0x85 */ - unsigned char Count0; /* Count = 17 */ - unsigned char Count1; - unsigned char Data[17]; - } L5_Pack; - - struct _L6_Pack{ - unsigned char Tag; /* large tag = 0x86 */ - unsigned char Count0; /* Count = 9 */ - unsigned char Count1; - unsigned char Data[9]; - } L6_Pack; - - } PnP_TAG_PACKET; - -#endif /* __ASSEMBLY__ */ -#endif /* ndef _PNP_ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h deleted file mode 100644 index 935d1e05366b..000000000000 --- a/include/asm-ppc/ppc4xx_dma.h +++ /dev/null @@ -1,579 +0,0 @@ -/* - * include/asm-ppc/ppc4xx_dma.h - * - * IBM PPC4xx DMA engine library - * - * Copyright 2000-2004 MontaVista Software Inc. - * - * Cleaned up a bit more, Matt Porter - * - * Original code by Armin Kuster - * and Pete Popov - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifdef __KERNEL__ -#ifndef __ASMPPC_PPC4xx_DMA_H -#define __ASMPPC_PPC4xx_DMA_H - -#include -#include -#include - -#undef DEBUG_4xxDMA - -#define MAX_PPC4xx_DMA_CHANNELS 4 - -/* - * Function return status codes - * These values are used to indicate whether or not the function - * call was successful, or a bad/invalid parameter was passed. - */ -#define DMA_STATUS_GOOD 0 -#define DMA_STATUS_BAD_CHANNEL 1 -#define DMA_STATUS_BAD_HANDLE 2 -#define DMA_STATUS_BAD_MODE 3 -#define DMA_STATUS_NULL_POINTER 4 -#define DMA_STATUS_OUT_OF_MEMORY 5 -#define DMA_STATUS_SGL_LIST_EMPTY 6 -#define DMA_STATUS_GENERAL_ERROR 7 -#define DMA_STATUS_CHANNEL_NOTFREE 8 - -#define DMA_CHANNEL_BUSY 0x80000000 - -/* - * These indicate status as returned from the DMA Status Register. - */ -#define DMA_STATUS_NO_ERROR 0 -#define DMA_STATUS_CS 1 /* Count Status */ -#define DMA_STATUS_TS 2 /* Transfer Status */ -#define DMA_STATUS_DMA_ERROR 3 /* DMA Error Occurred */ -#define DMA_STATUS_DMA_BUSY 4 /* The channel is busy */ - - -/* - * DMA Channel Control Registers - */ - -#ifdef CONFIG_44x -#define PPC4xx_DMA_64BIT -#define DMA_CR_OFFSET 1 -#else -#define DMA_CR_OFFSET 0 -#endif - -#define DMA_CE_ENABLE (1<<31) /* DMA Channel Enable */ -#define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31) -#define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31) - -#define DMA_CIE_ENABLE (1<<30) /* DMA Channel Interrupt Enable */ -#define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30) -#define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30) - -#define DMA_TD (1<<29) -#define SET_DMA_TD(x) (((x)&0x1)<<29) -#define GET_DMA_TD(x) (((x)&DMA_TD)>>29) - -#define DMA_PL (1<<28) /* Peripheral Location */ -#define SET_DMA_PL(x) (((x)&0x1)<<28) -#define GET_DMA_PL(x) (((x)&DMA_PL)>>28) - -#define EXTERNAL_PERIPHERAL 0 -#define INTERNAL_PERIPHERAL 1 - -#define SET_DMA_PW(x) (((x)&0x3)<<(26-DMA_CR_OFFSET)) /* Peripheral Width */ -#define DMA_PW_MASK SET_DMA_PW(3) -#define PW_8 0 -#define PW_16 1 -#define PW_32 2 -#define PW_64 3 -/* FIXME: Add PW_128 support for 440GP DMA block */ -#define GET_DMA_PW(x) (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET)) - -#define DMA_DAI (1<<(25-DMA_CR_OFFSET)) /* Destination Address Increment */ -#define SET_DMA_DAI(x) (((x)&0x1)<<(25-DMA_CR_OFFSET)) - -#define DMA_SAI (1<<(24-DMA_CR_OFFSET)) /* Source Address Increment */ -#define SET_DMA_SAI(x) (((x)&0x1)<<(24-DMA_CR_OFFSET)) - -#define DMA_BEN (1<<(23-DMA_CR_OFFSET)) /* Buffer Enable */ -#define SET_DMA_BEN(x) (((x)&0x1)<<(23-DMA_CR_OFFSET)) - -#define SET_DMA_TM(x) (((x)&0x3)<<(21-DMA_CR_OFFSET)) /* Transfer Mode */ -#define DMA_TM_MASK SET_DMA_TM(3) -#define TM_PERIPHERAL 0 /* Peripheral */ -#define TM_RESERVED 1 /* Reserved */ -#define TM_S_MM 2 /* Memory to Memory */ -#define TM_D_MM 3 /* Device Paced Memory to Memory */ -#define GET_DMA_TM(x) (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET)) - -#define SET_DMA_PSC(x) (((x)&0x3)<<(19-DMA_CR_OFFSET)) /* Peripheral Setup Cycles */ -#define DMA_PSC_MASK SET_DMA_PSC(3) -#define GET_DMA_PSC(x) (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET)) - -#define SET_DMA_PWC(x) (((x)&0x3F)<<(13-DMA_CR_OFFSET)) /* Peripheral Wait Cycles */ -#define DMA_PWC_MASK SET_DMA_PWC(0x3F) -#define GET_DMA_PWC(x) (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET)) - -#define SET_DMA_PHC(x) (((x)&0x7)<<(10-DMA_CR_OFFSET)) /* Peripheral Hold Cycles */ -#define DMA_PHC_MASK SET_DMA_PHC(0x7) -#define GET_DMA_PHC(x) (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET)) - -#define DMA_ETD_OUTPUT (1<<(9-DMA_CR_OFFSET)) /* EOT pin is a TC output */ -#define SET_DMA_ETD(x) (((x)&0x1)<<(9-DMA_CR_OFFSET)) - -#define DMA_TCE_ENABLE (1<<(8-DMA_CR_OFFSET)) -#define SET_DMA_TCE(x) (((x)&0x1)<<(8-DMA_CR_OFFSET)) - -#define DMA_DEC (1<<(2)) /* Address Decrement */ -#define SET_DMA_DEC(x) (((x)&0x1)<<2) -#define GET_DMA_DEC(x) (((x)&DMA_DEC)>>2) - - -/* - * Transfer Modes - * These modes are defined in a way that makes it possible to - * simply "or" in the value in the control register. - */ - -#define DMA_MODE_MM (SET_DMA_TM(TM_S_MM)) /* memory to memory */ - - /* Device-paced memory to memory, */ - /* device is at source address */ -#define DMA_MODE_MM_DEVATSRC (DMA_TD | SET_DMA_TM(TM_D_MM)) - - /* Device-paced memory to memory, */ - /* device is at destination address */ -#define DMA_MODE_MM_DEVATDST (SET_DMA_TM(TM_D_MM)) - -/* 405gp/440gp */ -#define SET_DMA_PREFETCH(x) (((x)&0x3)<<(4-DMA_CR_OFFSET)) /* Memory Read Prefetch */ -#define DMA_PREFETCH_MASK SET_DMA_PREFETCH(3) -#define PREFETCH_1 0 /* Prefetch 1 Double Word */ -#define PREFETCH_2 1 -#define PREFETCH_4 2 -#define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET)) - -#define DMA_PCE (1<<(3-DMA_CR_OFFSET)) /* Parity Check Enable */ -#define SET_DMA_PCE(x) (((x)&0x1)<<(3-DMA_CR_OFFSET)) -#define GET_DMA_PCE(x) (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET)) - -/* stb3x */ - -#define DMA_ECE_ENABLE (1<<5) -#define SET_DMA_ECE(x) (((x)&0x1)<<5) -#define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5) - -#define DMA_TCD_DISABLE (1<<4) -#define SET_DMA_TCD(x) (((x)&0x1)<<4) -#define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4) - -typedef uint32_t sgl_handle_t; - -#ifdef CONFIG_PPC4xx_EDMA - -#define SGL_LIST_SIZE 4096 -#define DMA_PPC4xx_SIZE SGL_LIST_SIZE - -#define SET_DMA_PRIORITY(x) (((x)&0x3)<<(6-DMA_CR_OFFSET)) /* DMA Channel Priority */ -#define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3) -#define PRIORITY_LOW 0 -#define PRIORITY_MID_LOW 1 -#define PRIORITY_MID_HIGH 2 -#define PRIORITY_HIGH 3 -#define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET)) - -/* - * DMA Polarity Configuration Register - */ -#define DMAReq_ActiveLow(chan) (1<<(31-(chan*3))) -#define DMAAck_ActiveLow(chan) (1<<(30-(chan*3))) -#define EOT_ActiveLow(chan) (1<<(29-(chan*3))) /* End of Transfer */ - -/* - * DMA Sleep Mode Register - */ -#define SLEEP_MODE_ENABLE (1<<21) - -/* - * DMA Status Register - */ -#define DMA_CS0 (1<<31) /* Terminal Count has been reached */ -#define DMA_CS1 (1<<30) -#define DMA_CS2 (1<<29) -#define DMA_CS3 (1<<28) - -#define DMA_TS0 (1<<27) /* End of Transfer has been requested */ -#define DMA_TS1 (1<<26) -#define DMA_TS2 (1<<25) -#define DMA_TS3 (1<<24) - -#define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ -#define DMA_CH1_ERR (1<<22) -#define DMA_CH2_ERR (1<<21) -#define DMA_CH3_ERR (1<<20) - -#define DMA_IN_DMA_REQ0 (1<<19) /* Internal DMA Request is pending */ -#define DMA_IN_DMA_REQ1 (1<<18) -#define DMA_IN_DMA_REQ2 (1<<17) -#define DMA_IN_DMA_REQ3 (1<<16) - -#define DMA_EXT_DMA_REQ0 (1<<15) /* External DMA Request is pending */ -#define DMA_EXT_DMA_REQ1 (1<<14) -#define DMA_EXT_DMA_REQ2 (1<<13) -#define DMA_EXT_DMA_REQ3 (1<<12) - -#define DMA_CH0_BUSY (1<<11) /* DMA Channel 0 Busy */ -#define DMA_CH1_BUSY (1<<10) -#define DMA_CH2_BUSY (1<<9) -#define DMA_CH3_BUSY (1<<8) - -#define DMA_SG0 (1<<7) /* DMA Channel 0 Scatter/Gather in progress */ -#define DMA_SG1 (1<<6) -#define DMA_SG2 (1<<5) -#define DMA_SG3 (1<<4) - -/* DMA Channel Count Register */ -#define DMA_CTC_BTEN (1<<23) /* Burst Enable/Disable bit */ -#define DMA_CTC_BSIZ_MSK (3<<21) /* Mask of the Burst size bits */ -#define DMA_CTC_BSIZ_2 (0) -#define DMA_CTC_BSIZ_4 (1<<21) -#define DMA_CTC_BSIZ_8 (2<<21) -#define DMA_CTC_BSIZ_16 (3<<21) - -/* - * DMA SG Command Register - */ -#define SSG_ENABLE(chan) (1<<(31-chan)) /* Start Scatter Gather */ -#define SSG_MASK_ENABLE(chan) (1<<(15-chan)) /* Enable writing to SSG0 bit */ - -/* - * DMA Scatter/Gather Descriptor Bit fields - */ -#define SG_LINK (1<<31) /* Link */ -#define SG_TCI_ENABLE (1<<29) /* Enable Terminal Count Interrupt */ -#define SG_ETI_ENABLE (1<<28) /* Enable End of Transfer Interrupt */ -#define SG_ERI_ENABLE (1<<27) /* Enable Error Interrupt */ -#define SG_COUNT_MASK 0xFFFF /* Count Field */ - -#define SET_DMA_CONTROL \ - (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ - SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */\ - SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ - SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ - SET_DMA_PL(p_init->pl) | /* peripheral location */ \ - SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ - SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ - SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ - SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ - SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ - SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ - SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ - SET_DMA_PREFETCH(p_init->pf) /* read prefetch */) - -#define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan)) - -#elif defined(CONFIG_STB03xxx) /* stb03xxx */ - -#define DMA_PPC4xx_SIZE 4096 - -/* - * DMA Status Register - */ - -#define SET_DMA_PRIORITY(x) (((x)&0x00800001)) /* DMA Channel Priority */ -#define DMA_PRIORITY_MASK 0x00800001 -#define PRIORITY_LOW 0x00000000 -#define PRIORITY_MID_LOW 0x00000001 -#define PRIORITY_MID_HIGH 0x00800000 -#define PRIORITY_HIGH 0x00800001 -#define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001)) - -#define DMA_CS0 (1<<31) /* Terminal Count has been reached */ -#define DMA_CS1 (1<<30) -#define DMA_CS2 (1<<29) -#define DMA_CS3 (1<<28) - -#define DMA_TS0 (1<<27) /* End of Transfer has been requested */ -#define DMA_TS1 (1<<26) -#define DMA_TS2 (1<<25) -#define DMA_TS3 (1<<24) - -#define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ -#define DMA_CH1_ERR (1<<22) -#define DMA_CH2_ERR (1<<21) -#define DMA_CH3_ERR (1<<20) - -#define DMA_CT0 (1<<19) /* Chained transfere */ - -#define DMA_IN_DMA_REQ0 (1<<18) /* Internal DMA Request is pending */ -#define DMA_IN_DMA_REQ1 (1<<17) -#define DMA_IN_DMA_REQ2 (1<<16) -#define DMA_IN_DMA_REQ3 (1<<15) - -#define DMA_EXT_DMA_REQ0 (1<<14) /* External DMA Request is pending */ -#define DMA_EXT_DMA_REQ1 (1<<13) -#define DMA_EXT_DMA_REQ2 (1<<12) -#define DMA_EXT_DMA_REQ3 (1<<11) - -#define DMA_CH0_BUSY (1<<10) /* DMA Channel 0 Busy */ -#define DMA_CH1_BUSY (1<<9) -#define DMA_CH2_BUSY (1<<8) -#define DMA_CH3_BUSY (1<<7) - -#define DMA_CT1 (1<<6) /* Chained transfere */ -#define DMA_CT2 (1<<5) -#define DMA_CT3 (1<<4) - -#define DMA_CH_ENABLE (1<<7) -#define SET_DMA_CH(x) (((x)&0x1)<<7) -#define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7) - -/* STBx25xxx dma unique */ -/* enable device port on a dma channel - * example ext 0 on dma 1 - */ - -#define SSP0_RECV 15 -#define SSP0_XMIT 14 -#define EXT_DMA_0 12 -#define SC1_XMIT 11 -#define SC1_RECV 10 -#define EXT_DMA_2 9 -#define EXT_DMA_3 8 -#define SERIAL2_XMIT 7 -#define SERIAL2_RECV 6 -#define SC0_XMIT 5 -#define SC0_RECV 4 -#define SERIAL1_XMIT 3 -#define SERIAL1_RECV 2 -#define SERIAL0_XMIT 1 -#define SERIAL0_RECV 0 - -#define DMA_CHAN_0 1 -#define DMA_CHAN_1 2 -#define DMA_CHAN_2 3 -#define DMA_CHAN_3 4 - -/* end STBx25xx */ - -/* - * Bit 30 must be one for Redwoods, otherwise transfers may receive errors. - */ -#define DMA_CR_MB0 0x2 - -#define SET_DMA_CONTROL \ - (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ - SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ - SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ - SET_DMA_PL(p_init->pl) | /* peripheral location */ \ - SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ - SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ - SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ - SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ - SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ - SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ - SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ - SET_DMA_TCD(p_init->tcd_disable) | /* TC chain mode disable */ \ - SET_DMA_ECE(p_init->ece_enable) | /* ECE chanin mode enable */ \ - SET_DMA_CH(p_init->ch_enable) | /* Chain enable */ \ - DMA_CR_MB0 /* must be one */) - -#define GET_DMA_POLARITY(chan) chan - -#endif - -typedef struct { - unsigned short in_use; /* set when channel is being used, clr when - * available. - */ - /* - * Valid polarity settings: - * DMAReq_ActiveLow(n) - * DMAAck_ActiveLow(n) - * EOT_ActiveLow(n) - * - * n is 0 to max dma chans - */ - unsigned int polarity; - - char buffer_enable; /* Boolean: buffer enable */ - char tce_enable; /* Boolean: terminal count enable */ - char etd_output; /* Boolean: eot pin is a tc output */ - char pce; /* Boolean: parity check enable */ - - /* - * Peripheral location: - * INTERNAL_PERIPHERAL (UART0 on the 405GP) - * EXTERNAL_PERIPHERAL - */ - char pl; /* internal/external peripheral */ - - /* - * Valid pwidth settings: - * PW_8 - * PW_16 - * PW_32 - * PW_64 - */ - unsigned int pwidth; - - char dai; /* Boolean: dst address increment */ - char sai; /* Boolean: src address increment */ - - /* - * Valid psc settings: 0-3 - */ - unsigned int psc; /* Peripheral Setup Cycles */ - - /* - * Valid pwc settings: - * 0-63 - */ - unsigned int pwc; /* Peripheral Wait Cycles */ - - /* - * Valid phc settings: - * 0-7 - */ - unsigned int phc; /* Peripheral Hold Cycles */ - - /* - * Valid cp (channel priority) settings: - * PRIORITY_LOW - * PRIORITY_MID_LOW - * PRIORITY_MID_HIGH - * PRIORITY_HIGH - */ - unsigned int cp; /* channel priority */ - - /* - * Valid pf (memory read prefetch) settings: - * - * PREFETCH_1 - * PREFETCH_2 - * PREFETCH_4 - */ - unsigned int pf; /* memory read prefetch */ - - /* - * Boolean: channel interrupt enable - * NOTE: for sgl transfers, only the last descriptor will be setup to - * interrupt. - */ - char int_enable; - - char shift; /* easy access to byte_count shift, based on */ - /* the width of the channel */ - - uint32_t control; /* channel control word */ - - /* These variabled are used ONLY in single dma transfers */ - unsigned int mode; /* transfer mode */ - phys_addr_t addr; - char ce; /* channel enable */ -#ifdef CONFIG_STB03xxx - char ch_enable; - char tcd_disable; - char ece_enable; - char td; /* transfer direction */ -#endif - - char int_on_final_sg;/* for scatter/gather - only interrupt on last sg */ -} ppc_dma_ch_t; - -/* - * PPC44x DMA implementations have a slightly different - * descriptor layout. Probably moved about due to the - * change to 64-bit addresses and link pointer. I don't - * know why they didn't just leave control_count after - * the dst_addr. - */ -#ifdef PPC4xx_DMA_64BIT -typedef struct { - uint32_t control; - uint32_t control_count; - phys_addr_t src_addr; - phys_addr_t dst_addr; - phys_addr_t next; -} ppc_sgl_t; -#else -typedef struct { - uint32_t control; - phys_addr_t src_addr; - phys_addr_t dst_addr; - uint32_t control_count; - uint32_t next; -} ppc_sgl_t; -#endif - -typedef struct { - unsigned int dmanr; - uint32_t control; /* channel ctrl word; loaded from each descrptr */ - uint32_t sgl_control; /* LK, TCI, ETI, and ERI bits in sgl descriptor */ - dma_addr_t dma_addr; /* dma (physical) address of this list */ - ppc_sgl_t *phead; - dma_addr_t phead_dma; - ppc_sgl_t *ptail; - dma_addr_t ptail_dma; -} sgl_list_info_t; - -typedef struct { - phys_addr_t *src_addr; - phys_addr_t *dst_addr; - phys_addr_t dma_src_addr; - phys_addr_t dma_dst_addr; -} pci_alloc_desc_t; - -extern ppc_dma_ch_t dma_channels[]; - -/* - * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c - */ -extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *); -extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *); -extern int ppc4xx_set_channel_priority(unsigned int, unsigned int); -extern unsigned int ppc4xx_get_peripheral_width(unsigned int); -extern void ppc4xx_set_sg_addr(int, phys_addr_t); -extern int ppc4xx_add_dma_sgl(sgl_handle_t, phys_addr_t, phys_addr_t, unsigned int); -extern void ppc4xx_enable_dma_sgl(sgl_handle_t); -extern void ppc4xx_disable_dma_sgl(sgl_handle_t); -extern int ppc4xx_get_dma_sgl_residue(sgl_handle_t, phys_addr_t *, phys_addr_t *); -extern int ppc4xx_delete_dma_sgl_element(sgl_handle_t, phys_addr_t *, phys_addr_t *); -extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int); -extern void ppc4xx_free_dma_handle(sgl_handle_t); -extern int ppc4xx_get_dma_status(void); -extern int ppc4xx_enable_burst(unsigned int); -extern int ppc4xx_disable_burst(unsigned int); -extern int ppc4xx_set_burst_size(unsigned int, unsigned int); -extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr); -extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr); -extern void ppc4xx_enable_dma(unsigned int dmanr); -extern void ppc4xx_disable_dma(unsigned int dmanr); -extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count); -extern int ppc4xx_get_dma_residue(unsigned int dmanr); -extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr, - phys_addr_t dst_dma_addr); -extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr); -extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr); -extern int ppc4xx_clr_dma_status(unsigned int dmanr); -extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); -extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); -extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode); - -/* These are in kernel/dma.c: */ - -/* reserve a DMA channel */ -extern int request_dma(unsigned int dmanr, const char *device_id); -/* release it again */ -extern void free_dma(unsigned int dmanr); -#endif -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h deleted file mode 100644 index e44261206f8b..000000000000 --- a/include/asm-ppc/ppc4xx_pic.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * include/asm-ppc/ppc4xx_pic.h - * - * Interrupt controller driver for PowerPC 4xx-based processors. - * - * Copyright (c) 1999 Grant Erickson - * - * Eugene Surovegin or - * Copyright (c) 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __PPC4XX_PIC_H__ -#define __PPC4XX_PIC_H__ - -#include -#include - -/* "Fixed" UIC settings (they are chip, not board specific), - * e.g. polarity/triggerring for internal interrupt sources. - * - * Platform port should provide NR_UICS-sized array named ppc4xx_core_uic_cfg - * with these "fixed" settings: .polarity contains exact value which will - * be written (masked with "ext_irq_mask") into UICx_PR register, - * .triggering - to UICx_TR. - * - * Settings for external IRQs can be specified separately by the - * board support code. In this case properly sized array of unsigned - * char named ppc4xx_uic_ext_irq_cfg should be filled with correct - * values using IRQ_SENSE_XXXXX and IRQ_POLARITY_XXXXXXX defines. - * - * If these arrays aren't provided, UIC initialization code keeps firmware - * configuration. Also, ppc4xx_uic_ext_irq_cfg implies ppc4xx_core_uic_cfg - * is defined. - * - * Both ppc4xx_core_uic_cfg and ppc4xx_uic_ext_irq_cfg are declared as - * "weak" symbols in ppc4xx_pic.c - * - */ -struct ppc4xx_uic_settings { - u32 polarity; - u32 triggering; - u32 ext_irq_mask; -}; - -extern void ppc4xx_pic_init(void); - -#endif /* __PPC4XX_PIC_H__ */ diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h deleted file mode 100644 index d2fee41d600b..000000000000 --- a/include/asm-ppc/ppc_sys.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * include/asm-ppc/ppc_sys.h - * - * PPC system definitions and library functions - * - * Maintainer: Kumar Gala - * - * Copyright 2005 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_PPC_SYS_H -#define __ASM_PPC_SYS_H - -#include -#include -#include - -#if defined(CONFIG_8260) -#include -#elif defined(CONFIG_8xx) -#include -#elif defined(CONFIG_PPC_MPC52xx) -#include -#elif defined(CONFIG_MPC10X_BRIDGE) -#include -#else -#error "need definition of ppc_sys_devices" -#endif - -#define PPC_SYS_IORESOURCE_FIXUPPED 0x00000001 - -struct ppc_sys_spec { - /* PPC sys is matched via (ID & mask) == value, id could be - * PVR, SVR, IMMR, * etc. */ - u32 mask; - u32 value; - u32 num_devices; - char *ppc_sys_name; - u8 config[NUM_PPC_SYS_DEVS]; - enum ppc_sys_devices *device_list; -}; - -struct platform_notify_dev_map { - const char *bus_id; - void (*rtn)(struct platform_device * pdev, int idx); -}; - -enum platform_device_func { - PPC_SYS_FUNC_DUMMY = 0, - PPC_SYS_FUNC_ETH = 1, - PPC_SYS_FUNC_UART = 2, - PPC_SYS_FUNC_HLDC = 3, - PPC_SYS_FUNC_USB = 4, - PPC_SYS_FUNC_IRDA = 5, -}; - -#define PPC_SYS_CONFIG_DISABLED 1 - -/* describes all specific chips and which devices they have on them */ -extern struct ppc_sys_spec ppc_sys_specs[]; -extern struct ppc_sys_spec *cur_ppc_sys_spec; - -/* determine which specific SOC we are */ -extern void identify_ppc_sys_by_id(u32 id) __init; -extern void identify_ppc_sys_by_name(char *name) __init; -extern void identify_ppc_sys_by_name_and_id(char *name, u32 id) __init; - -/* describes all devices that may exist in a given family of processors */ -extern struct platform_device ppc_sys_platform_devices[]; - -/* allow any platform_device fixup to occur before device is registered */ -extern int (*ppc_sys_device_fixup) (struct platform_device * pdev); - -/* Update all memory resources by paddr, call before platform_device_register */ -extern void ppc_sys_fixup_mem_resource(struct platform_device *pdev, - phys_addr_t paddr) __init; - -/* Get platform_data pointer out of platform device, call before platform_device_register */ -extern void *ppc_sys_get_pdata(enum ppc_sys_devices dev) __init; - -/* remove a device from the system */ -extern void ppc_sys_device_remove(enum ppc_sys_devices dev); - -/* Function assignment stuff */ -void ppc_sys_device_initfunc(void); -void ppc_sys_device_setfunc(enum ppc_sys_devices dev, - enum platform_device_func func); -void ppc_sys_device_set_func_all(enum platform_device_func func); - -void platform_notify_map(const struct platform_notify_dev_map *map, - struct device *dev); - -/* Enable / disable stuff */ -void ppc_sys_device_disable(enum ppc_sys_devices dev); -void ppc_sys_device_enable(enum ppc_sys_devices dev); -void ppc_sys_device_enable_all(void); -void ppc_sys_device_disable_all(void); - -#endif /* __ASM_PPC_SYS_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h deleted file mode 100644 index 3819e17cd7b0..000000000000 --- a/include/asm-ppc/ppcboot.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_PPCBOOT_H__ -#define __ASM_PPCBOOT_H__ - -/* - * Board information passed to kernel from PPCBoot - * - * include/asm-ppc/ppcboot.h - */ - -#ifndef __ASSEMBLY__ -#include - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ -#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) - unsigned long bi_immr_base; /* base of IMMR register */ -#endif -#if defined(CONFIG_PPC_MPC52xx) - unsigned long bi_mbar_base; /* base of internal registers */ -#endif - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* Ethernet address */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ -#if defined(CONFIG_CPM2) - unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ - unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ - unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ - unsigned long bi_vco; /* VCO Out from PLL, in MHz */ -#endif -#if defined(CONFIG_PPC_MPC52xx) - unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ - unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ -#endif - unsigned long bi_baudrate; /* Console Baudrate */ -#if defined(CONFIG_4xx) - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */ - unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ - unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ -#endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif -#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) - /* second onboard ethernet port */ - unsigned char bi_enet1addr[6]; -#endif -#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) - /* third onboard ethernet ports */ - unsigned char bi_enet2addr[6]; -#endif -#if defined(CONFIG_440GX) - /* fourth onboard ethernet ports */ - unsigned char bi_enet3addr[6]; -#endif -#if defined(CONFIG_4xx) - unsigned int bi_opbfreq; /* OB clock in Hz */ - int bi_iic_fast[2]; /* Use fast i2c mode */ -#endif -#if defined(CONFIG_440GX) - int bi_phynum[4]; /* phy mapping */ - int bi_phymode[4]; /* phy mode */ -#endif -} bd_t; - -#define bi_tbfreq bi_intfreq - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_PPCBOOT_H__ */ diff --git a/include/asm-ppc/prep_nvram.h b/include/asm-ppc/prep_nvram.h deleted file mode 100644 index 6dbc36a84df2..000000000000 --- a/include/asm-ppc/prep_nvram.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * PreP compliant NVRAM access - */ - -/* Corey Minyard (minyard@acm.org) - Stolen from PReP book. Per the - license I must say: - (C) Copyright (Corey Minyard), (1998). All rights reserved - */ - -/* Structure map for NVRAM on PowerPC Reference Platform */ -/* All fields are either character/byte strings which are valid either - endian or they are big-endian numbers. - - There are a number of Date and Time fields which are in RTC format, - big-endian. These are stored in UT (GMT). - - For enum's: if given in hex then they are bit significant, i.e. only - one bit is on for each enum. -*/ -#ifdef __KERNEL__ -#ifndef _PPC_PREP_NVRAM_H -#define _PPC_PREP_NVRAM_H - -#define MAX_PREP_NVRAM 0x8000 -#define PREP_NVRAM_AS0 0x74 -#define PREP_NVRAM_AS1 0x75 -#define PREP_NVRAM_DATA 0x77 - -#define NVSIZE 4096 /* size of NVRAM */ -#define OSAREASIZE 512 /* size of OSArea space */ -#define CONFSIZE 1024 /* guess at size of Configuration space */ - -typedef struct _SECURITY { - unsigned long BootErrCnt; /* Count of boot password errors */ - unsigned long ConfigErrCnt; /* Count of config password errors */ - unsigned long BootErrorDT[2]; /* Date&Time from RTC of last error in pw */ - unsigned long ConfigErrorDT[2]; /* Date&Time from RTC of last error in pw */ - unsigned long BootCorrectDT[2]; /* Date&Time from RTC of last correct pw */ - unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */ - unsigned long BootSetDT[2]; /* Date&Time from RTC of last set of pw */ - unsigned long ConfigSetDT[2]; /* Date&Time from RTC of last set of pw */ - unsigned char Serial[16]; /* Box serial number */ -} SECURITY; - -typedef enum _OS_ID { - Unknown = 0, - Firmware = 1, - AIX = 2, - NT = 3, - MKOS2 = 4, - MKAIX = 5, - Taligent = 6, - Solaris = 7, - MK = 12 -} OS_ID; - -typedef struct _ERROR_LOG { - unsigned char ErrorLogEntry[40]; /* To be architected */ -} ERROR_LOG; - -typedef enum _BOOT_STATUS { - BootStarted = 0x01, - BootFinished = 0x02, - RestartStarted = 0x04, - RestartFinished = 0x08, - PowerFailStarted = 0x10, - PowerFailFinished = 0x20, - ProcessorReady = 0x40, - ProcessorRunning = 0x80, - ProcessorStart = 0x0100 -} BOOT_STATUS; - -typedef struct _RESTART_BLOCK { - unsigned short Version; - unsigned short Revision; - unsigned long ResumeReserve1[2]; - volatile unsigned long BootStatus; - unsigned long CheckSum; /* Checksum of RESTART_BLOCK */ - void * RestartAddress; - void * SaveAreaAddr; - unsigned long SaveAreaLength; -} RESTART_BLOCK; - -typedef enum _OSAREA_USAGE { - Empty = 0, - Used = 1 -} OSAREA_USAGE; - -typedef enum _PM_MODE { - Suspend = 0x80, /* Part of state is in memory */ - Normal = 0x00 /* No power management in effect */ -} PMMODE; - -typedef struct _HEADER { - unsigned short Size; /* NVRAM size in K(1024) */ - unsigned char Version; /* Structure map different */ - unsigned char Revision; /* Structure map the same -may - be new values in old fields - in other words old code still works */ - unsigned short Crc1; /* check sum from beginning of nvram to OSArea */ - unsigned short Crc2; /* check sum of config */ - unsigned char LastOS; /* OS_ID */ - unsigned char Endian; /* B if big endian, L if little endian */ - unsigned char OSAreaUsage; /* OSAREA_USAGE */ - unsigned char PMMode; /* Shutdown mode */ - RESTART_BLOCK RestartBlock; - SECURITY Security; - ERROR_LOG ErrorLog[2]; - - /* Global Environment information */ - void * GEAddress; - unsigned long GELength; - - /* Date&Time from RTC of last change to Global Environment */ - unsigned long GELastWriteDT[2]; - - /* Configuration information */ - void * ConfigAddress; - unsigned long ConfigLength; - - /* Date&Time from RTC of last change to Configuration */ - unsigned long ConfigLastWriteDT[2]; - unsigned long ConfigCount; /* Count of entries in Configuration */ - - /* OS dependent temp area */ - void * OSAreaAddress; - unsigned long OSAreaLength; - - /* Date&Time from RTC of last change to OSAreaArea */ - unsigned long OSAreaLastWriteDT[2]; -} HEADER; - -/* Here is the whole map of the NVRAM */ -typedef struct _NVRAM_MAP { - HEADER Header; - unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)]; - unsigned char OSArea[OSAREASIZE]; - unsigned char ConfigArea[CONFSIZE]; -} NVRAM_MAP; - -/* Routines to manipulate the NVRAM */ -void init_prep_nvram(void); -char *prep_nvram_get_var(const char *name); -char *prep_nvram_first_var(void); -char *prep_nvram_next_var(char *name); - -/* Routines to read and write directly to the NVRAM */ -unsigned char prep_nvram_read_val(int addr); -void prep_nvram_write_val(int addr, - unsigned char val); - -#endif /* _PPC_PREP_NVRAM_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h deleted file mode 100644 index 71f4c996fe75..000000000000 --- a/include/asm-ppc/prom.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Definitions for talking to the Open Firmware PROM on - * Power Macintosh computers. - * - * Copyright (C) 1996 Paul Mackerras. - */ -#ifdef __KERNEL__ -#ifndef _PPC_PROM_H -#define _PPC_PROM_H - -/* This is used in arch/ppc/mm/mem_pieces.h */ -struct reg_property { - unsigned int address; - unsigned int size; -}; - -/* - * These macros assist in performing the address calculations that we - * need to do to access data when the kernel is running at an address - * that is different from the address that the kernel is linked at. - * The reloc_offset() function returns the difference between these - * two addresses and the macros simplify the process of adding or - * subtracting this offset to/from pointer values. - */ -extern unsigned long reloc_offset(void); -extern unsigned long add_reloc_offset(unsigned long); -extern unsigned long sub_reloc_offset(unsigned long); - -#define PTRRELOC(x) ((typeof(x))add_reloc_offset((unsigned long)(x))) -#define PTRUNRELOC(x) ((typeof(x))sub_reloc_offset((unsigned long)(x))) - -/* - * Fallback definitions since we don't support OF in arch/ppc any more. - */ -#define machine_is_compatible(x) 0 -#define of_find_compatible_node(f, t, c) NULL -#define of_get_property(p, n, l) NULL - -#endif /* _PPC_PROM_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/raven.h b/include/asm-ppc/raven.h deleted file mode 100644 index 66f52cc0a03c..000000000000 --- a/include/asm-ppc/raven.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * include/asm-ppc/raven.h -- Raven MPIC chip. - * - * Copyright (C) 1998 Johnnie Peters - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifdef __KERNEL__ -#ifndef _ASMPPC_RAVEN_H -#define _ASMPPC_RAVEN_H - -#define MVME2600_INT_SIO 0 -#define MVME2600_INT_FALCN_ECC_ERR 1 -#define MVME2600_INT_PCI_ETHERNET 2 -#define MVME2600_INT_PCI_SCSI 3 -#define MVME2600_INT_PCI_GRAPHICS 4 -#define MVME2600_INT_PCI_VME0 5 -#define MVME2600_INT_PCI_VME1 6 -#define MVME2600_INT_PCI_VME2 7 -#define MVME2600_INT_PCI_VME3 8 -#define MVME2600_INT_PCI_INTA 9 -#define MVME2600_INT_PCI_INTB 10 -#define MVME2600_INT_PCI_INTC 11 -#define MVME2600_INT_PCI_INTD 12 -#define MVME2600_INT_LM_SIG0 13 -#define MVME2600_INT_LM_SIG1 14 - -extern struct hw_interrupt_type raven_pic; - -extern int raven_init(void); -#endif /* _ASMPPC_RAVEN_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h deleted file mode 100644 index 91e96af88bd8..000000000000 --- a/include/asm-ppc/reg_booke.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * Contains register definitions common to the Book E PowerPC - * specification. Notice that while the IBM-40x series of CPUs - * are not true Book E PowerPCs, they borrowed a number of features - * before Book E was finalized, and are included here as well. Unfortunatly, - * they sometimes used different locations than true Book E CPUs did. - */ -#ifdef __KERNEL__ -#ifndef __ASM_PPC_REG_BOOKE_H__ -#define __ASM_PPC_REG_BOOKE_H__ - -#ifndef __ASSEMBLY__ -/* Performance Monitor Registers */ -#define mfpmr(rn) ({unsigned int rval; \ - asm volatile("mfpmr %0," __stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) -#endif /* __ASSEMBLY__ */ - -/* Freescale Book E Performance Monitor APU Registers */ -#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ -#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ -#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ -#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ -#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ -#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ -#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ -#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ - -#define PMLCA_FC 0x80000000 /* Freeze Counter */ -#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ -#define PMLCA_FCU 0x20000000 /* Freeze in User */ -#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ -#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ -#define PMLCA_CE 0x04000000 /* Condition Enable */ - -#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */ -#define PMLCA_EVENT_SHIFT 16 - -#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ -#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ -#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ -#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ - -#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */ -#define PMLCB_THRESHMUL_SHIFT 8 - -#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */ -#define PMLCB_THRESHOLD_SHIFT 0 - -#define PMRN_PMGC0 0x190 /* PM Global Control 0 */ - -#define PMGC0_FAC 0x80000000 /* Freeze all Counters */ -#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */ -#define PMGC0_FCECE 0x20000000 /* Freeze countes on - Enabled Condition or - Event */ - -#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ -#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ -#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ -#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ -#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ -#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ -#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ -#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ -#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ -#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ -#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ -#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ -#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ - - -/* Machine State Register (MSR) Fields */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable */ -#define MSR_SPE (1<<25) /* Enable SPE */ -#define MSR_DWE (1<<10) /* Debug Wait Enable */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ -#define MSR_IS MSR_IR /* Instruction Space */ -#define MSR_DS MSR_DR /* Data Space */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit */ - -/* Default MSR for kernel mode. */ -#if defined (CONFIG_40x) -#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) -#elif defined(CONFIG_BOOKE) -#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) -#endif - -/* Special Purpose Registers (SPRNs)*/ -#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ -#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ -#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ -#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ -#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ -#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ -#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ -#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ -#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ -#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ -#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ -#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ -#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ -#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ -#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ -#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ -#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ -#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ -#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ -#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ -#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ -#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ -#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ -#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ -#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ -#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ -#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ -#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ -#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ -#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ -#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ -#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ -#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ -#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ -#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ -#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ -#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ -#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ -#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ -#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ -#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ -#define SPRN_MCSR 0x23C /* Machine Check Status Register */ -#define SPRN_MCAR 0x23D /* Machine Check Address Register */ -#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ -#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ -#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ -#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ -#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ -#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ -#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ -#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ -#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ -#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */ -#define SPRN_PID1 0x279 /* Process ID Register 1 */ -#define SPRN_PID2 0x27A /* Process ID Register 2 */ -#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ -#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ -#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ -#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ -#define SPRN_MMUCR 0x3B2 /* MMU Control Register */ -#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ -#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ -#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ -#define SPRN_SLER 0x3BB /* Little-endian real mode */ -#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ -#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ -#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ -#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ -#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ -#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ -#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ -#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ -#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ -#define SPRN_SVR 0x3FF /* System Version Register */ - -/* - * SPRs which have conflicting definitions on true Book E versus classic, - * or IBM 40x. - */ -#ifdef CONFIG_BOOKE -#define SPRN_PID 0x030 /* Process ID */ -#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ -#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ -#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ -#define SPRN_DEAR 0x03D /* Data Error Address Register */ -#define SPRN_ESR 0x03E /* Exception Syndrome Register */ -#define SPRN_PIR 0x11E /* Processor Identification Register */ -#define SPRN_DBSR 0x130 /* Debug Status Register */ -#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ -#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ -#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ -#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ -#define SPRN_DAC1 0x13C /* Data Address Compare 1 */ -#define SPRN_DAC2 0x13D /* Data Address Compare 2 */ -#define SPRN_TSR 0x150 /* Timer Status Register */ -#define SPRN_TCR 0x154 /* Timer Control Register */ -#endif /* Book E */ -#ifdef CONFIG_40x -#define SPRN_PID 0x3B1 /* Process ID */ -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ -#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ -#define SPRN_TSR 0x3D8 /* Timer Status Register */ -#define SPRN_TCR 0x3DA /* Timer Control Register */ -#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ -#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ -#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ -#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ -#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ -#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ -#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ -#endif - -/* Bit definitions for CCR1. */ -#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ -#define CCR1_TCS 0x00000080 /* Timer Clock Select */ - -/* Bit definitions for the MCSR. */ -#ifdef CONFIG_4xx -#define MCSR_MCS 0x80000000 /* Machine Check Summary */ -#define MCSR_IB 0x40000000 /* Instruction PLB Error */ -#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ -#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ -#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ -#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ -#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ -#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ -#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ -#endif - -/* Bit definitions for the DBSR. */ -/* - * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. - */ -#ifdef CONFIG_BOOKE -#define DBSR_IC 0x08000000 /* Instruction Completion */ -#define DBSR_BT 0x04000000 /* Branch Taken */ -#define DBSR_TIE 0x01000000 /* Trap Instruction Event */ -#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ -#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ -#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ -#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ -#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ -#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ -#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ -#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ -#endif -#ifdef CONFIG_40x -#define DBSR_IC 0x80000000 /* Instruction Completion */ -#define DBSR_BT 0x40000000 /* Branch taken */ -#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ -#define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ -#define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ -#define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ -#define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ -#define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ -#define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ -#define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ -#define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ -#endif - -/* Bit definitions related to the ESR. */ -#define ESR_MCI 0x80000000 /* Machine Check - Instruction */ -#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ -#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ -#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ -#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ -#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Privileged */ -#define ESR_PTR 0x02000000 /* Program Exception - Trap */ -#define ESR_FP 0x01000000 /* Floating Point Operation */ -#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ -#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ -#define ESR_ST 0x00800000 /* Store Operation */ -#define ESR_DLK 0x00200000 /* Data Cache Locking */ -#define ESR_ILK 0x00100000 /* Instr. Cache Locking */ -#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ -#define ESR_BO 0x00020000 /* Byte Ordering */ - -/* Bit definitions related to the DBCR0. */ -#define DBCR0_EDM 0x80000000 /* External Debug Mode */ -#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ -#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ -#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ -#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ -#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ -#define DBCR0_RST_NONE 0x00000000 /* No Reset */ -#define DBCR0_IC 0x08000000 /* Instruction Completion */ -#define DBCR0_BT 0x04000000 /* Branch Taken */ -#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ -#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ -#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ -#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ -#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ -#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ -#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ -#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ -#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ -#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ -#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ - -/* Bit definitions related to the TCR. */ -#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ -#define TCR_WP_MASK TCR_WP(3) -#define WP_2_17 0 /* 2^17 clocks */ -#define WP_2_21 1 /* 2^21 clocks */ -#define WP_2_25 2 /* 2^25 clocks */ -#define WP_2_29 3 /* 2^29 clocks */ -#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ -#define TCR_WRC_MASK TCR_WRC(3) -#define WRC_NONE 0 /* No reset will occur */ -#define WRC_CORE 1 /* Core reset will occur */ -#define WRC_CHIP 2 /* Chip reset will occur */ -#define WRC_SYSTEM 3 /* System reset will occur */ -#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ -#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ -#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ -#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ -#define TCR_FP_MASK TCR_FP(3) -#define FP_2_9 0 /* 2^9 clocks */ -#define FP_2_13 1 /* 2^13 clocks */ -#define FP_2_17 2 /* 2^17 clocks */ -#define FP_2_21 3 /* 2^21 clocks */ -#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ -#define TCR_ARE 0x00400000 /* Auto Reload Enable */ - -/* Bit definitions for the TSR. */ -#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ -#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ -#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ -#define WRS_NONE 0 /* No WDT reset occurred */ -#define WRS_CORE 1 /* WDT forced core reset */ -#define WRS_CHIP 2 /* WDT forced chip reset */ -#define WRS_SYSTEM 3 /* WDT forced system reset */ -#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ -#define TSR_DIS TSR_PIS /* DEC Interrupt Status */ -#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ - -/* Bit definitions for the DCCR. */ -#define DCCR_NOCACHE 0 /* Noncacheable */ -#define DCCR_CACHE 1 /* Cacheable */ - -/* Bit definitions for DCWR. */ -#define DCWR_COPY 0 /* Copy-back */ -#define DCWR_WRITE 1 /* Write-through */ - -/* Bit definitions for ICCR. */ -#define ICCR_NOCACHE 0 /* Noncacheable */ -#define ICCR_CACHE 1 /* Cacheable */ - -/* Bit definitions for L1CSR0. */ -#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ -#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ -#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ -#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ - -/* Bit definitions for L1CSR1. */ -#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ -#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ -#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ - -/* Bit definitions for SGR. */ -#define SGR_NORMAL 0 /* Speculative fetching allowed. */ -#define SGR_GUARDED 1 /* Speculative fetching disallowed. */ - -/* Bit definitions for SPEFSCR. */ -#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ -#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ -#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ -#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ -#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ -#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ -#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ -#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ -#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ -#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ -#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ -#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ -#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ -#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ -#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ -#define SPEFSCR_OV 0x00004000 /* Integer overflow */ -#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ -#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ -#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ -#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ -#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ -#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ -#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ -#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ -#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ -#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ -#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ -#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ - -/* - * The IBM-403 is an even more odd special case, as it is much - * older than the IBM-405 series. We put these down here incase someone - * wishes to support these machines again. - */ -#ifdef CONFIG_403GCX -/* Special Purpose Registers (SPRNs)*/ -#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ -#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ -#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ -#define SPRN_TBHI 0x3DC /* Time Base High */ -#define SPRN_TBLO 0x3DD /* Time Base Low */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ -#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ -#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ -#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ -#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ - - -/* Bit definitions for the DBCR. */ -#define DBCR_EDM DBCR0_EDM -#define DBCR_IDM DBCR0_IDM -#define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 -#define DBCR_RST_SYSTEM 3 -#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ -#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ -#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ -#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ -#define DAC_BYTE 0 -#define DAC_HALF 1 -#define DAC_WORD 2 -#define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ -#endif /* 403GCX */ -#endif /* __ASM_PPC_REG_BOOKE_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h deleted file mode 100644 index 934810d25667..000000000000 --- a/include/asm-ppc/residual.h +++ /dev/null @@ -1,350 +0,0 @@ -/* 7/18/95 */ -/*----------------------------------------------------------------------------*/ -/* Residual Data header definitions and prototypes */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for RESIDUAL on PowerPC Reference Platform */ -/* residual.h - Residual data structure passed in r3. */ -/* Load point passed in r4 to boot image. */ -/* For enum's: if given in hex then they are bit significant, */ -/* i.e. only one bit is on for each enum */ -/* Reserved fields must be filled with zeros. */ - -#ifdef __KERNEL__ -#ifndef _RESIDUAL_ -#define _RESIDUAL_ - -#ifndef __ASSEMBLY__ - -#define MAX_CPUS 32 /* These should be set to the maximum */ -#define MAX_MEMS 64 /* number possible for this system. */ -#define MAX_DEVICES 256 /* Changing these will change the */ -#define AVE_PNP_SIZE 32 /* structure, hence the version of */ -#define MAX_MEM_SEGS 64 /* this header file. */ - -/*----------------------------------------------------------------------------*/ -/* Public structures... */ -/*----------------------------------------------------------------------------*/ - -#include - -typedef enum _L1CACHE_TYPE { - NoneCAC = 0, - SplitCAC = 1, - CombinedCAC = 2 - } L1CACHE_TYPE; - -typedef enum _TLB_TYPE { - NoneTLB = 0, - SplitTLB = 1, - CombinedTLB = 2 - } TLB_TYPE; - -typedef enum _FIRMWARE_SUPPORT { - Conventional = 0x01, - OpenFirmware = 0x02, - Diagnostics = 0x04, - LowDebug = 0x08, - Multiboot = 0x10, - LowClient = 0x20, - Hex41 = 0x40, - FAT = 0x80, - ISO9660 = 0x0100, - SCSI_InitiatorID_Override = 0x0200, - Tape_Boot = 0x0400, - FW_Boot_Path = 0x0800 - } FIRMWARE_SUPPORT; - -typedef enum _FIRMWARE_SUPPLIERS { - IBMFirmware = 0x00, - MotoFirmware = 0x01, /* 7/18/95 */ - FirmWorks = 0x02, /* 10/5/95 */ - Bull = 0x03, /* 04/03/96 */ - } FIRMWARE_SUPPLIERS; - -typedef enum _ENDIAN_SWITCH_METHODS { - UsePort92 = 0x01, - UsePCIConfigA8 = 0x02, - UseFF001030 = 0x03, - } ENDIAN_SWITCH_METHODS; - -typedef enum _SPREAD_IO_METHODS { - UsePort850 = 0x00, -/*UsePCIConfigA8 = 0x02,*/ - } SPREAD_IO_METHODS; - -typedef struct _VPD { - - /* Box dependent stuff */ - unsigned char PrintableModel[32]; /* Null terminated string. - Must be of the form: - vvv,<20h>,,<0x0> - where vvv is the vendor ID - e.g. IBM PPS MODEL 6015<0x0> */ - unsigned char Serial[16]; /* 12/94: - Serial Number; must be of the form: - vvv where vvv is the - vendor ID. - e.g. IBM60151234567<20h><20h> */ - unsigned char Reserved[48]; - unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ - unsigned long FirmwareSupports; /* See FirmwareSupport enum */ - unsigned long NvramSize; /* Size of nvram in bytes */ - unsigned long NumSIMMSlots; - unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ - unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ - unsigned long SmpIar; - unsigned long RAMErrLogOffset; /* Heap offset to error log */ - unsigned long Reserved5; - unsigned long Reserved6; - unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ - unsigned long ProcessorBusHz; /* Processor bus clock frequency */ - unsigned long Reserved7; - unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ - unsigned long WordWidth; /* Word width in bits */ - unsigned long PageSize; /* Page size in bytes */ - unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache - for which coherency is maintained; - normally <= CacheLineSize. */ - unsigned long GranuleSize; /* Unit of lock allocation to avoid */ - /* false sharing of locks. */ - - /* L1 Cache variables */ - unsigned long CacheSize; /* L1 Cache size in KB. This is the */ - /* total size of the L1, whether */ - /* combined or split */ - unsigned long CacheAttrib; /* L1CACHE_TYPE */ - unsigned long CacheAssoc; /* L1 Cache associativity. Use this - for combined cache. If split, put - zeros here. */ - unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use - for combined cache. If split, put - zeros here. */ - /* For split L1 Cache: (= combined if combined cache) */ - unsigned long I_CacheSize; - unsigned long I_CacheAssoc; - unsigned long I_CacheLineSize; - unsigned long D_CacheSize; - unsigned long D_CacheAssoc; - unsigned long D_CacheLineSize; - - /* Translation Lookaside Buffer variables */ - unsigned long TLBSize; /* Total number of TLBs on the system */ - unsigned long TLBAttrib; /* Combined I+D or split TLB */ - unsigned long TLBAssoc; /* TLB Associativity. Use this for - combined TLB. If split, put zeros - here. */ - /* For split TLB: (= combined if combined TLB) */ - unsigned long I_TLBSize; - unsigned long I_TLBAssoc; - unsigned long D_TLBSize; - unsigned long D_TLBAssoc; - - unsigned long ExtendedVPD; /* Offset to extended VPD area; - null if unused */ - } VPD; - -typedef enum _DEVICE_FLAGS { - Enabled = 0x4000, /* 1 - PCI device is enabled */ - Integrated = 0x2000, - Failed = 0x1000, /* 1 - device failed POST code tests */ - Static = 0x0800, /* 0 - dynamically configurable - 1 - static */ - Dock = 0x0400, /* 0 - not a docking station device - 1 - is a docking station device */ - Boot = 0x0200, /* 0 - device cannot be used for BOOT - 1 - can be a BOOT device */ - Configurable = 0x0100, /* 1 - device is configurable */ - Disableable = 0x80, /* 1 - device can be disabled */ - PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ - ReadOnly = 0x20, /* 1 - device is read only */ - Removable = 0x10, /* 1 - device is removable */ - ConsoleIn = 0x08, - ConsoleOut = 0x04, - Input = 0x02, - Output = 0x01 - } DEVICE_FLAGS; - -typedef enum _BUS_ID { - ISADEVICE = 0x01, - EISADEVICE = 0x02, - PCIDEVICE = 0x04, - PCMCIADEVICE = 0x08, - PNPISADEVICE = 0x10, - MCADEVICE = 0x20, - MXDEVICE = 0x40, /* Devices on mezzanine bus */ - PROCESSORDEVICE = 0x80, /* Devices on processor bus */ - VMEDEVICE = 0x100, - } BUS_ID; - -typedef struct _DEVICE_ID { - unsigned long BusId; /* See BUS_ID enum above */ - unsigned long DevId; /* Big Endian format */ - unsigned long SerialNum; /* For multiple usage of a single - DevId */ - unsigned long Flags; /* See DEVICE_FLAGS enum above */ - unsigned char BaseType; /* See pnp.h for bit definitions */ - unsigned char SubType; /* See pnp.h for bit definitions */ - unsigned char Interface; /* See pnp.h for bit definitions */ - unsigned char Spare; - } DEVICE_ID; - -typedef union _BUS_ACCESS { - struct _PnPAccess{ - unsigned char CSN; - unsigned char LogicalDevNumber; - unsigned short ReadDataPort; - } PnPAccess; - struct _ISAAccess{ - unsigned char SlotNumber; /* ISA Slot Number generally not - available; 0 if unknown */ - unsigned char LogicalDevNumber; - unsigned short ISAReserved; - } ISAAccess; - struct _MCAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short MCAReserved; - } MCAAccess; - struct _PCMCIAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short PCMCIAReserved; - } PCMCIAAccess; - struct _EISAAccess{ - unsigned char SlotNumber; - unsigned char FunctionNumber; - unsigned short EISAReserved; - } EISAAccess; - struct _PCIAccess{ - unsigned char BusNumber; - unsigned char DevFuncNumber; - unsigned short PCIReserved; - } PCIAccess; - struct _ProcBusAccess{ - unsigned char BusNumber; - unsigned char BUID; - unsigned short ProcBusReserved; - } ProcBusAccess; - } BUS_ACCESS; - -/* Per logical device information */ -typedef struct _PPC_DEVICE { - DEVICE_ID DeviceId; - BUS_ACCESS BusAccess; - - /* The following three are offsets into the DevicePnPHeap */ - /* All are in PnP compressed format */ - unsigned long AllocatedOffset; /* Allocated resource description */ - unsigned long PossibleOffset; /* Possible resource description */ - unsigned long CompatibleOffset; /* Compatible device identifiers */ - } PPC_DEVICE; - -typedef enum _CPU_STATE { - CPU_GOOD = 0, /* CPU is present, and active */ - CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ - CPU_OFF = 2, /* CPU is present, but inactive */ - CPU_FAILED = 3, /* CPU is present, but failed POST */ - CPU_NOT_PRESENT = 255 /* CPU not present */ - } CPU_STATE; - -typedef struct _PPC_CPU { - unsigned long CpuType; /* Result of mfspr from Processor - Version Register (PVR). - PVR(0-15) = Version (e.g. 601) - PVR(16-31 = EC Level */ - unsigned char CpuNumber; /* CPU Number for this processor */ - unsigned char CpuState; /* CPU State, see CPU_STATE enum */ - unsigned short Reserved; - } PPC_CPU; - -typedef struct _PPC_MEM { - unsigned long SIMMSize; /* 0 - absent or bad - 8M, 32M (in MB) */ - } PPC_MEM; - -typedef enum _MEM_USAGE { - Other = 0x8000, - ResumeBlock = 0x4000, /* for use by power management */ - SystemROM = 0x2000, /* Flash memory (populated) */ - UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ - IOMemory = 0x0800, - SystemIO = 0x0400, - SystemRegs = 0x0200, - PCIAddr = 0x0100, - PCIConfig = 0x80, - ISAAddr = 0x40, - Unpopulated = 0x20, /* Unpopulated part of System Memory */ - Free = 0x10, /* Free part of System Memory */ - BootImage = 0x08, /* BootImage part of System Memory */ - FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ - FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ - FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ - } MEM_USAGE; - -typedef struct _MEM_MAP { - unsigned long Usage; /* See MEM_USAGE above */ - unsigned long BasePage; /* Page number measured in 4KB pages */ - unsigned long PageCount; /* Page count measured in 4KB pages */ - } MEM_MAP; - -typedef struct _RESIDUAL { - unsigned long ResidualLength; /* Length of Residual */ - unsigned char Version; /* of this data structure */ - unsigned char Revision; /* of this data structure */ - unsigned short EC; /* of this data structure */ - /* VPD */ - VPD VitalProductData; - /* CPU */ - unsigned short MaxNumCpus; /* Max CPUs in this system */ - unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ - /* that there are unpopulated or */ - /* otherwise unusable cpu locations */ - PPC_CPU Cpus[MAX_CPUS]; - /* Memory */ - unsigned long TotalMemory; /* Total amount of memory installed */ - unsigned long GoodMemory; /* Total amount of good memory */ - unsigned long ActualNumMemSegs; - MEM_MAP Segs[MAX_MEM_SEGS]; - unsigned long ActualNumMemories; - PPC_MEM Memories[MAX_MEMS]; - /* Devices */ - unsigned long ActualNumDevices; - PPC_DEVICE Devices[MAX_DEVICES]; - unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; - } RESIDUAL; - - -/* - * Forward declaration - we can't include because it - * breaks the boot loader - */ -struct pci_dev; - -extern RESIDUAL *res; -extern void print_residual_device_info(void); -extern PPC_DEVICE *residual_find_device(unsigned long BusMask, - unsigned char * DevID, int BaseType, - int SubType, int Interface, int n); -extern int residual_pcidev_irq(struct pci_dev *dev); -extern void residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi); -extern unsigned int residual_isapic_addr(void); -extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, - int n); -extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); -extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); - -#ifdef CONFIG_PREP_RESIDUAL -#define have_residual_data (res && res->ResidualLength) -#else -#define have_residual_data 0 -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* ndef _RESIDUAL_ */ - -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/rtc.h b/include/asm-ppc/rtc.h deleted file mode 100644 index 6025b46d0a2a..000000000000 --- a/include/asm-ppc/rtc.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * include/asm-ppc/rtc.h - * - * Author: Tom Rini - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Based on: - * include/asm-m68k/rtc.h - * - * Copyright Richard Zidlicky - * implementation details for genrtc/q40rtc driver - * - * And the old drivers/macintosh/rtc.c which was heavily based on: - * Linux/SPARC Real Time Clock Driver - * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) - * - * With additional work by Paul Mackerras and Franz Sirl. - */ - -#ifndef __ASM_RTC_H__ -#define __ASM_RTC_H__ - -#ifdef __KERNEL__ - -#include - -#include -#include - -#define RTC_PIE 0x40 /* periodic interrupt enable */ -#define RTC_AIE 0x20 /* alarm interrupt enable */ -#define RTC_UIE 0x10 /* update-finished interrupt enable */ - -/* some dummy definitions */ -#define RTC_BATT_BAD 0x100 /* battery bad */ -#define RTC_SQWE 0x08 /* enable square-wave output */ -#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ -#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ -#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ - -static inline unsigned int get_rtc_time(struct rtc_time *time) -{ - if (ppc_md.get_rtc_time) { - unsigned long nowtime; - - nowtime = (ppc_md.get_rtc_time)(); - - to_tm(nowtime, time); - - time->tm_year -= 1900; - time->tm_mon -= 1; /* Make sure userland has a 0-based month */ - } - return RTC_24H; -} - -/* Set the current date and time in the real time clock. */ -static inline int set_rtc_time(struct rtc_time *time) -{ - if (ppc_md.get_rtc_time) { - unsigned long nowtime; - - nowtime = mktime(time->tm_year+1900, time->tm_mon+1, - time->tm_mday, time->tm_hour, time->tm_min, - time->tm_sec); - - (ppc_md.set_rtc_time)(nowtime); - - return 0; - } else - return -EINVAL; -} - -static inline unsigned int get_rtc_ss(void) -{ - struct rtc_time h; - - get_rtc_time(&h); - return h.tm_sec; -} - -static inline int get_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} -static inline int set_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} - -#endif /* __KERNEL__ */ -#endif /* __ASM_RTC_H__ */ diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h deleted file mode 100644 index d35ed10315b1..000000000000 --- a/include/asm-ppc/serial.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * include/asm-ppc/serial.h - */ - -#ifdef __KERNEL__ -#ifndef __ASM_SERIAL_H__ -#define __ASM_SERIAL_H__ - - -#if defined(CONFIG_EV64260) -#include -#elif defined(CONFIG_CHESTNUT) -#include -#elif defined(CONFIG_POWERPMC250) -#include -#elif defined(CONFIG_LOPEC) -#include -#elif defined(CONFIG_MVME5100) -#include -#elif defined(CONFIG_PAL4) -#include -#elif defined(CONFIG_PRPMC750) -#include -#elif defined(CONFIG_PRPMC800) -#include -#elif defined(CONFIG_SANDPOINT) -#include -#elif defined(CONFIG_SPRUCE) -#include -#elif defined(CONFIG_4xx) -#include -#elif defined(CONFIG_RADSTONE_PPC7D) -#include -#else - -/* - * XXX Assume it has PC-style ISA serial ports - true for PReP at least. - */ -#include - -#endif /* !CONFIG_GEMINI and others */ -#endif /* __ASM_SERIAL_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h deleted file mode 100644 index e75791ea33a6..000000000000 --- a/include/asm-ppc/smp.h +++ /dev/null @@ -1,75 +0,0 @@ -/* smp.h: PPC specific SMP stuff. - * - * Original was a copy of sparc smp.h. Now heavily modified - * for PPC. - * - * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 1996-2001 Cort Dougan - */ -#ifdef __KERNEL__ -#ifndef _PPC_SMP_H -#define _PPC_SMP_H - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SMP - -#ifndef __ASSEMBLY__ - -struct cpuinfo_PPC { - unsigned long loops_per_jiffy; - unsigned long pvr; - unsigned long *pgd_cache; - unsigned long *pte_cache; - unsigned long pgtable_cache_sz; -}; - -extern struct cpuinfo_PPC cpu_data[]; -extern cpumask_t cpu_online_map; -extern cpumask_t cpu_possible_map; -extern unsigned long smp_proc_in_lock[]; -extern volatile unsigned long cpu_callin_map[]; -extern int smp_tb_synchronized; -extern struct smp_ops_t *smp_ops; - -extern void smp_send_tlb_invalidate(int); -extern void smp_send_xmon_break(int cpu); -struct pt_regs; -extern void smp_message_recv(int); - -extern int __cpu_disable(void); -extern void __cpu_die(unsigned int cpu); -extern void cpu_die(void) __attribute__((noreturn)); - -#define raw_smp_processor_id() (current_thread_info()->cpu) - -extern int __cpu_up(unsigned int cpu); - -extern int smp_hw_index[]; -#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) -#define get_hard_smp_processor_id(cpu) (smp_hw_index[(cpu)]) -#define set_hard_smp_processor_id(cpu, phys)\ - (smp_hw_index[(cpu)] = (phys)) - -#endif /* __ASSEMBLY__ */ - -#else /* !(CONFIG_SMP) */ - -static inline void cpu_die(void) { } -#define get_hard_smp_processor_id(cpu) 0 -#define set_hard_smp_processor_id(cpu, phys) -#define hard_smp_processor_id() 0 - -#endif /* !(CONFIG_SMP) */ - -#ifndef __ASSEMBLY__ -extern int boot_cpuid; -extern int boot_cpuid_phys; -#endif - -#endif /* !(_PPC_SMP_H) */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h deleted file mode 100644 index fccaf5531e57..000000000000 --- a/include/asm-ppc/spinlock.h +++ /dev/null @@ -1,168 +0,0 @@ -#ifndef __ASM_SPINLOCK_H -#define __ASM_SPINLOCK_H - -#include - -/* - * Simple spin lock operations. - * - * (the type definitions are in asm/raw_spinlock_types.h) - */ - -#define __raw_spin_is_locked(x) ((x)->slock != 0) -#define __raw_spin_unlock_wait(lock) \ - do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0) -#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) - -static inline void __raw_spin_lock(raw_spinlock_t *lock) -{ - unsigned long tmp; - - __asm__ __volatile__( - "b 1f # __raw_spin_lock\n\ -2: lwzx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne+ 2b\n\ -1: lwarx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne- 2b\n" - PPC405_ERR77(0,%1) -" stwcx. %2,0,%1\n\ - bne- 2b\n\ - isync" - : "=&r"(tmp) - : "r"(&lock->slock), "r"(1) - : "cr0", "memory"); -} - -static inline void __raw_spin_unlock(raw_spinlock_t *lock) -{ - __asm__ __volatile__("eieio # __raw_spin_unlock": : :"memory"); - lock->slock = 0; -} - -#define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock))) - -/* - * Read-write spinlocks, allowing multiple readers - * but only one writer. - * - * NOTE! it is quite common to have readers in interrupts - * but no interrupt writers. For those circumstances we - * can "mix" irq-safe locks - any writer needs to get a - * irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - */ - -#define __raw_read_can_lock(rw) ((rw)->lock >= 0) -#define __raw_write_can_lock(rw) (!(rw)->lock) - -static __inline__ int __raw_read_trylock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( -"2: lwarx %0,0,%1 # read_trylock\n\ - addic. %0,%0,1\n\ - ble- 1f\n" - PPC405_ERR77(0,%1) -" stwcx. %0,0,%1\n\ - bne- 2b\n\ - isync\n\ -1:" - : "=&r"(tmp) - : "r"(&rw->lock) - : "cr0", "memory"); - - return tmp > 0; -} - -static __inline__ void __raw_read_lock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( - "b 2f # read_lock\n\ -1: lwzx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - blt+ 1b\n\ -2: lwarx %0,0,%1\n\ - addic. %0,%0,1\n\ - ble- 1b\n" - PPC405_ERR77(0,%1) -" stwcx. %0,0,%1\n\ - bne- 2b\n\ - isync" - : "=&r"(tmp) - : "r"(&rw->lock) - : "cr0", "memory"); -} - -static __inline__ void __raw_read_unlock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( - "eieio # read_unlock\n\ -1: lwarx %0,0,%1\n\ - addic %0,%0,-1\n" - PPC405_ERR77(0,%1) -" stwcx. %0,0,%1\n\ - bne- 1b" - : "=&r"(tmp) - : "r"(&rw->lock) - : "cr0", "memory"); -} - -static __inline__ int __raw_write_trylock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( -"2: lwarx %0,0,%1 # write_trylock\n\ - cmpwi 0,%0,0\n\ - bne- 1f\n" - PPC405_ERR77(0,%1) -" stwcx. %2,0,%1\n\ - bne- 2b\n\ - isync\n\ -1:" - : "=&r"(tmp) - : "r"(&rw->lock), "r"(-1) - : "cr0", "memory"); - - return tmp == 0; -} - -static __inline__ void __raw_write_lock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( - "b 2f # write_lock\n\ -1: lwzx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne+ 1b\n\ -2: lwarx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne- 1b\n" - PPC405_ERR77(0,%1) -" stwcx. %2,0,%1\n\ - bne- 2b\n\ - isync" - : "=&r"(tmp) - : "r"(&rw->lock), "r"(-1) - : "cr0", "memory"); -} - -static __inline__ void __raw_write_unlock(raw_rwlock_t *rw) -{ - __asm__ __volatile__("eieio # write_unlock": : :"memory"); - rw->lock = 0; -} - -#define _raw_spin_relax(lock) cpu_relax() -#define _raw_read_relax(lock) cpu_relax() -#define _raw_write_relax(lock) cpu_relax() - -#endif /* __ASM_SPINLOCK_H */ diff --git a/include/asm-ppc/suspend.h b/include/asm-ppc/suspend.h deleted file mode 100644 index 3df9f32bd834..000000000000 --- a/include/asm-ppc/suspend.h +++ /dev/null @@ -1,12 +0,0 @@ -static inline int arch_prepare_suspend(void) -{ - return 0; -} - -static inline void save_processor_state(void) -{ -} - -static inline void restore_processor_state(void) -{ -} diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h deleted file mode 100644 index 70ebd333c55b..000000000000 --- a/include/asm-ppc/system.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (C) 1999 Cort Dougan - */ -#ifndef __PPC_SYSTEM_H -#define __PPC_SYSTEM_H - -#include - -#include - -/* - * Memory barrier. - * The sync instruction guarantees that all memory accesses initiated - * by this processor have been performed (with respect to all other - * mechanisms that access memory). The eieio instruction is a barrier - * providing an ordering (separately) for (a) cacheable stores and (b) - * loads and stores to non-cacheable memory (e.g. I/O devices). - * - * mb() prevents loads and stores being reordered across this point. - * rmb() prevents loads being reordered across this point. - * wmb() prevents stores being reordered across this point. - * read_barrier_depends() prevents data-dependent loads being reordered - * across this point (nop on PPC). - * - * We can use the eieio instruction for wmb, but since it doesn't - * give any ordering guarantees about loads, we have to use the - * stronger but slower sync instruction for mb and rmb. - */ -#define mb() __asm__ __volatile__ ("sync" : : : "memory") -#define rmb() __asm__ __volatile__ ("sync" : : : "memory") -#define wmb() __asm__ __volatile__ ("eieio" : : : "memory") -#define read_barrier_depends() do { } while(0) - -#define set_mb(var, value) do { var = value; mb(); } while (0) - -#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */ -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory") -#define smp_read_barrier_depends() read_barrier_depends() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) -#endif /* CONFIG_SMP */ - -#ifdef __KERNEL__ -struct task_struct; -struct pt_regs; - -extern void print_backtrace(unsigned long *); -extern void show_regs(struct pt_regs * regs); -extern void flush_instruction_cache(void); -extern void hard_reset_now(void); -extern void poweroff_now(void); -extern int set_dabr(unsigned long dabr); -#ifdef CONFIG_6xx -extern long _get_L2CR(void); -extern long _get_L3CR(void); -extern void _set_L2CR(unsigned long); -extern void _set_L3CR(unsigned long); -#else -#define _get_L2CR() 0L -#define _get_L3CR() 0L -#define _set_L2CR(val) do { } while(0) -#define _set_L3CR(val) do { } while(0) -#endif -extern void via_cuda_init(void); -extern void pmac_nvram_init(void); -extern void chrp_nvram_init(void); -extern void read_rtc_time(void); -extern void pmac_find_display(void); -extern void giveup_fpu(struct task_struct *); -extern void disable_kernel_fp(void); -extern void enable_kernel_fp(void); -extern void flush_fp_to_thread(struct task_struct *); -extern void enable_kernel_altivec(void); -extern void giveup_altivec(struct task_struct *); -extern void load_up_altivec(struct task_struct *); -extern int emulate_altivec(struct pt_regs *); -extern void giveup_spe(struct task_struct *); -extern void load_up_spe(struct task_struct *); -extern int fix_alignment(struct pt_regs *); -extern void cvt_fd(float *from, double *to, struct thread_struct *thread); -extern void cvt_df(double *from, float *to, struct thread_struct *thread); - -#ifndef CONFIG_SMP -extern void discard_lazy_cpu_state(void); -#else -static inline void discard_lazy_cpu_state(void) -{ -} -#endif - -#ifdef CONFIG_ALTIVEC -extern void flush_altivec_to_thread(struct task_struct *); -#else -static inline void flush_altivec_to_thread(struct task_struct *t) -{ -} -#endif - -#ifdef CONFIG_SPE -extern void flush_spe_to_thread(struct task_struct *); -#else -static inline void flush_spe_to_thread(struct task_struct *t) -{ -} -#endif - -extern int call_rtas(const char *, int, int, unsigned long *, ...); -extern void cacheable_memzero(void *p, unsigned int nb); -extern void *cacheable_memcpy(void *, const void *, unsigned int); -extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); -extern void bad_page_fault(struct pt_regs *, unsigned long, int); -extern int die(const char *, struct pt_regs *, long); -extern void _exception(int, struct pt_regs *, int, unsigned long); -void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); - -#ifdef CONFIG_BOOKE_WDT -extern u32 booke_wdt_enabled; -extern u32 booke_wdt_period; -#endif /* CONFIG_BOOKE_WDT */ - -struct device_node; -extern void note_scsi_host(struct device_node *, void *); - -extern struct task_struct *__switch_to(struct task_struct *, - struct task_struct *); -#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) - -struct thread_struct; -extern struct task_struct *_switch(struct thread_struct *prev, - struct thread_struct *next); - -extern unsigned int rtas_data; - -static __inline__ unsigned long -xchg_u32(volatile void *p, unsigned long val) -{ - unsigned long prev; - - __asm__ __volatile__ ("\n\ -1: lwarx %0,0,%2 \n" - PPC405_ERR77(0,%2) -" stwcx. %3,0,%2 \n\ - bne- 1b" - : "=&r" (prev), "=m" (*(volatile unsigned long *)p) - : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) - : "cc", "memory"); - - return prev; -} - -/* - * This function doesn't exist, so you'll get a linker error - * if something tries to do an invalid xchg(). - */ -extern void __xchg_called_with_bad_pointer(void); - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) -{ - switch (size) { - case 4: - return (unsigned long) xchg_u32(ptr, x); -#if 0 /* xchg_u64 doesn't exist on 32-bit PPC */ - case 8: - return (unsigned long) xchg_u64(ptr, x); -#endif /* 0 */ - } - __xchg_called_with_bad_pointer(); - return x; - - -} - -static inline void * xchg_ptr(void * m, void * val) -{ - return (void *) xchg_u32(m, (unsigned long) val); -} - - -#define __HAVE_ARCH_CMPXCHG 1 - -static __inline__ unsigned long -__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new) -{ - unsigned int prev; - - __asm__ __volatile__ ("\n\ -1: lwarx %0,0,%2 \n\ - cmpw 0,%0,%3 \n\ - bne 2f \n" - PPC405_ERR77(0,%2) -" stwcx. %4,0,%2 \n\ - bne- 1b\n" -#ifdef CONFIG_SMP -" sync\n" -#endif /* CONFIG_SMP */ -"2:" - : "=&r" (prev), "=m" (*p) - : "r" (p), "r" (old), "r" (new), "m" (*p) - : "cc", "memory"); - - return prev; -} - -static inline unsigned long -__cmpxchg_u32_local(volatile unsigned int *p, unsigned int old, - unsigned int new) -{ - unsigned int prev; - - __asm__ __volatile__ ("\n\ -1: lwarx %0,0,%2 \n\ - cmpw 0,%0,%3 \n\ - bne 2f \n" - PPC405_ERR77(0,%2) -" stwcx. %4,0,%2 \n\ - bne- 1b\n" -"2:" - : "=&r" (prev), "=m" (*p) - : "r" (p), "r" (old), "r" (new), "m" (*p) - : "cc", "memory"); - - return prev; -} - -/* This function doesn't exist, so you'll get a linker error - if something tries to do an invalid cmpxchg(). */ -extern void __cmpxchg_called_with_bad_pointer(void); - -static __inline__ unsigned long -__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, - unsigned int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32(ptr, old, new); -#if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */ - case 8: - return __cmpxchg_u64(ptr, old, new); -#endif /* 0 */ - } - __cmpxchg_called_with_bad_pointer(); - return old; -} - -#define cmpxchg(ptr, o, n) \ - ({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ - (unsigned long)_n_, sizeof(*(ptr))); \ - }) - -#include - -static inline unsigned long __cmpxchg_local(volatile void *ptr, - unsigned long old, - unsigned long new, int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32_local(ptr, old, new); - default: - return __cmpxchg_local_generic(ptr, old, new, size); - } - - return old; -} - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \ - (unsigned long)(n), sizeof(*(ptr)))) -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#define arch_align_stack(x) (x) - -#endif /* __KERNEL__ */ -#endif /* __PPC_SYSTEM_H */ diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h deleted file mode 100644 index 81dbcd43a501..000000000000 --- a/include/asm-ppc/time.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Common time prototypes and such for all ppc machines. - * - * Written by Cort Dougan (cort@fsmlabs.com) to merge - * Paul Mackerras' version and mine for PReP and Pmac. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_TIME_H__ -#define __ASM_TIME_H__ - -#include -#include -#include - -#include - -/* time.c */ -extern unsigned tb_ticks_per_jiffy; -extern unsigned tb_to_us; -extern unsigned tb_last_stamp; -extern unsigned long disarm_decr[NR_CPUS]; - -extern void to_tm(int tim, struct rtc_time * tm); -extern time_t last_rtc_update; - -extern void set_dec_cpu6(unsigned int val); - -int via_calibrate_decr(void); - -/* Accessor functions for the decrementer register. - * The 4xx doesn't even have a decrementer. I tried to use the - * generic timer interrupt code, which seems OK, with the 4xx PIT - * in auto-reload mode. The problem is PIT stops counting when it - * hits zero. If it would wrap, we could use it just like a decrementer. - */ -static __inline__ unsigned int get_dec(void) -{ -#if defined(CONFIG_40x) - return (mfspr(SPRN_PIT)); -#else - return (mfspr(SPRN_DEC)); -#endif -} - -static __inline__ void set_dec(unsigned int val) -{ -#if defined(CONFIG_40x) - return; /* Have to let it auto-reload */ -#elif defined(CONFIG_8xx_CPU6) - set_dec_cpu6(val); -#else - mtspr(SPRN_DEC, val); -#endif -} - -/* Accessor functions for the timebase (RTC on 601) registers. */ -/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */ -#ifdef CONFIG_6xx -extern __inline__ int __pure __USE_RTC(void) { - return (mfspr(SPRN_PVR)>>16) == 1; -} -#else -#define __USE_RTC() 0 -#endif - -extern __inline__ unsigned long get_tbl(void) { - unsigned long tbl; -#if defined(CONFIG_403GCX) - asm volatile("mfspr %0, 0x3dd" : "=r" (tbl)); -#else - asm volatile("mftb %0" : "=r" (tbl)); -#endif - return tbl; -} - -extern __inline__ unsigned long get_tbu(void) { - unsigned long tbl; -#if defined(CONFIG_403GCX) - asm volatile("mfspr %0, 0x3dc" : "=r" (tbl)); -#else - asm volatile("mftbu %0" : "=r" (tbl)); -#endif - return tbl; -} - -extern __inline__ void set_tb(unsigned int upper, unsigned int lower) -{ - mtspr(SPRN_TBWL, 0); - mtspr(SPRN_TBWU, upper); - mtspr(SPRN_TBWL, lower); -} - -extern __inline__ unsigned long get_rtcl(void) { - unsigned long rtcl; - asm volatile("mfrtcl %0" : "=r" (rtcl)); - return rtcl; -} - -extern __inline__ unsigned long get_rtcu(void) -{ - unsigned long rtcu; - asm volatile("mfrtcu %0" : "=r" (rtcu)); - return rtcu; -} - -extern __inline__ unsigned get_native_tbl(void) { - if (__USE_RTC()) - return get_rtcl(); - else - return get_tbl(); -} - -/* On machines with RTC, this function can only be used safely - * after the timestamp and for 1 second. It is only used by gettimeofday - * however so it should not matter. - */ -extern __inline__ unsigned tb_ticks_since(unsigned tstamp) { - if (__USE_RTC()) { - int delta = get_rtcl() - tstamp; - return delta<0 ? delta + 1000000000 : delta; - } else { - return get_tbl() - tstamp; - } -} - -#if 0 -extern __inline__ unsigned long get_bin_rtcl(void) { - unsigned long rtcl, rtcu1, rtcu2; - asm volatile("\ -1: mfrtcu %0\n\ - mfrtcl %1\n\ - mfrtcu %2\n\ - cmpw %0,%2\n\ - bne- 1b\n" - : "=r" (rtcu1), "=r" (rtcl), "=r" (rtcu2) - : : "cr0"); - return rtcu2*1000000000+rtcl; -} - -extern __inline__ unsigned binary_tbl(void) { - if (__USE_RTC()) - return get_bin_rtcl(); - else - return get_tbl(); -} -#endif - -/* Use mulhwu to scale processor timebase to timeval */ -/* Specifically, this computes (x * y) / 2^32. -- paulus */ -#define mulhwu(x,y) \ -({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) - -unsigned mulhwu_scale_factor(unsigned, unsigned); - -#define account_process_vtime(tsk) do { } while (0) -#define calculate_steal_time() do { } while (0) -#define snapshot_timebases() do { } while (0) - -#endif /* __ASM_TIME_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/todc.h b/include/asm-ppc/todc.h deleted file mode 100644 index 937c7dbe6e5c..000000000000 --- a/include/asm-ppc/todc.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Definitions for the M48Txx and mc146818 series of Time of day/Real Time - * Clock chips. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips. - * Purpose is to make one generic file that handles all of these chips instead - * of every platform implementing the same code over & over again. - */ - -#ifndef __PPC_KERNEL_TODC_H -#define __PPC_KERNEL_TODC_H - -typedef struct { - uint rtc_type; /* your particular chip */ - - /* - * Following are the addresses of the AS0, AS1, and DATA registers - * of these chips. Note that these are board-specific. - */ - unsigned int nvram_as0; - unsigned int nvram_as1; - unsigned int nvram_data; - - /* - * Define bits to stop external set of regs from changing so - * the chip can be read/written reliably. - */ - unsigned char enable_read; - unsigned char enable_write; - - /* - * Following is the number of AS0 address bits. This is normally - * 8 but some bad hardware routes address lines incorrectly. - */ - int as0_bits; - - int nvram_size; /* Size of NVRAM on chip */ - int sw_flags; /* Software control flags */ - - /* Following are the register offsets for the particular chip */ - int year; - int month; - int day_of_month; - int day_of_week; - int hours; - int minutes; - int seconds; - int control_b; - int control_a; - int watchdog; - int interrupts; - int alarm_date; - int alarm_hour; - int alarm_minutes; - int alarm_seconds; - int century; - int flags; - - /* - * Some RTC chips have their NVRAM buried behind a addr/data pair of - * regs on the first level/clock registers. The following fields - * are the addresses for those addr/data regs. - */ - int nvram_addr_reg; - int nvram_data_reg; -} todc_info_t; - -/* - * Define the types of TODC/RTC variants that are supported in - * arch/ppc/kernel/todc_time.c - * Make a new one of these for any chip somehow differs from what's already - * defined. That way, if you ever need to put in code to touch those - * bits/registers in todc_time.c, you can put it inside an - * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break - * anyone else. - */ -#define TODC_TYPE_MK48T35 1 -#define TODC_TYPE_MK48T37 2 -#define TODC_TYPE_MK48T59 3 -#define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */ -#define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */ -#define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */ -#define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */ -#define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */ -#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */ -#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */ -#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */ -#define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */ -#define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */ -#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */ - -/* - * Bit to clear/set to enable reads/writes to the chip - */ -#define TODC_MK48TXX_CNTL_A_R 0x40 -#define TODC_MK48TXX_CNTL_A_W 0x80 -#define TODC_MK48TXX_DAY_CB 0x80 - -#define TODC_DS1501_CNTL_B_TE 0x80 - -/* - * Define flag bits used by todc routines. - */ -#define TODC_FLAG_2_LEVEL_NVRAM 0x00000001 - -/* - * Define the values for the various RTC's that should to into the todc_info - * table. - * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only - * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set. - */ -#define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8 -#define TODC_TYPE_MK48T35_SW_FLAGS 0 -#define TODC_TYPE_MK48T35_YEAR 0x7fff -#define TODC_TYPE_MK48T35_MONTH 0x7ffe -#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */ -#define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */ -#define TODC_TYPE_MK48T35_HOURS 0x7ffb -#define TODC_TYPE_MK48T35_MINUTES 0x7ffa -#define TODC_TYPE_MK48T35_SECONDS 0x7ff9 -#define TODC_TYPE_MK48T35_CNTL_B 0x7ff9 -#define TODC_TYPE_MK48T35_CNTL_A 0x7ff8 -#define TODC_TYPE_MK48T35_WATCHDOG 0x0000 -#define TODC_TYPE_MK48T35_INTERRUPTS 0x0000 -#define TODC_TYPE_MK48T35_ALARM_DATE 0x0000 -#define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000 -#define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000 -#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000 -#define TODC_TYPE_MK48T35_CENTURY 0x0000 -#define TODC_TYPE_MK48T35_FLAGS 0x0000 -#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0 -#define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0 - -#define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0 -#define TODC_TYPE_MK48T37_SW_FLAGS 0 -#define TODC_TYPE_MK48T37_YEAR 0x7fff -#define TODC_TYPE_MK48T37_MONTH 0x7ffe -#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */ -#define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */ -#define TODC_TYPE_MK48T37_HOURS 0x7ffb -#define TODC_TYPE_MK48T37_MINUTES 0x7ffa -#define TODC_TYPE_MK48T37_SECONDS 0x7ff9 -#define TODC_TYPE_MK48T37_CNTL_B 0x7ff9 -#define TODC_TYPE_MK48T37_CNTL_A 0x7ff8 -#define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7 -#define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6 -#define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5 -#define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4 -#define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3 -#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2 -#define TODC_TYPE_MK48T37_CENTURY 0x7ff1 -#define TODC_TYPE_MK48T37_FLAGS 0x7ff0 -#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0 -#define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0 - -#define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0 -#define TODC_TYPE_MK48T59_SW_FLAGS 0 -#define TODC_TYPE_MK48T59_YEAR 0x1fff -#define TODC_TYPE_MK48T59_MONTH 0x1ffe -#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */ -#define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */ -#define TODC_TYPE_MK48T59_HOURS 0x1ffb -#define TODC_TYPE_MK48T59_MINUTES 0x1ffa -#define TODC_TYPE_MK48T59_SECONDS 0x1ff9 -#define TODC_TYPE_MK48T59_CNTL_B 0x1ff9 -#define TODC_TYPE_MK48T59_CNTL_A 0x1ff8 -#define TODC_TYPE_MK48T59_WATCHDOG 0x1fff -#define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff -#define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff -#define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff -#define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff -#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff -#define TODC_TYPE_MK48T59_CENTURY 0x1fff -#define TODC_TYPE_MK48T59_FLAGS 0x1fff -#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0 -#define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1501_NVRAM_SIZE 0x100 -#define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM -#define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06) -#define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05) -#define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04) -#define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03) -#define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02) -#define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01) -#define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00) -#define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f) -#define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f) -#define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) -#define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) -#define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b) -#define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a) -#define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09) -#define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08) -#define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07) -#define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) -#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10 -#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13 - -#define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0 -#define TODC_TYPE_DS1553_SW_FLAGS 0 -#define TODC_TYPE_DS1553_YEAR 0x1fff -#define TODC_TYPE_DS1553_MONTH 0x1ffe -#define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */ -#define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */ -#define TODC_TYPE_DS1553_HOURS 0x1ffb -#define TODC_TYPE_DS1553_MINUTES 0x1ffa -#define TODC_TYPE_DS1553_SECONDS 0x1ff9 -#define TODC_TYPE_DS1553_CNTL_B 0x1ff9 -#define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1553_WATCHDOG 0x1ff7 -#define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6 -#define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5 -#define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4 -#define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3 -#define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2 -#define TODC_TYPE_DS1553_CENTURY 0x1ff8 -#define TODC_TYPE_DS1553_FLAGS 0x1ff0 -#define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1553_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0 -#define TODC_TYPE_DS1557_SW_FLAGS 0 -#define TODC_TYPE_DS1557_YEAR 0x7ffff -#define TODC_TYPE_DS1557_MONTH 0x7fffe -#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */ -#define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */ -#define TODC_TYPE_DS1557_HOURS 0x7fffb -#define TODC_TYPE_DS1557_MINUTES 0x7fffa -#define TODC_TYPE_DS1557_SECONDS 0x7fff9 -#define TODC_TYPE_DS1557_CNTL_B 0x7fff9 -#define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1557_WATCHDOG 0x7fff7 -#define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6 -#define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5 -#define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4 -#define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3 -#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2 -#define TODC_TYPE_DS1557_CENTURY 0x7fff8 -#define TODC_TYPE_DS1557_FLAGS 0x7fff0 -#define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1557_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8 -#define TODC_TYPE_DS1643_SW_FLAGS 0 -#define TODC_TYPE_DS1643_YEAR 0x1fff -#define TODC_TYPE_DS1643_MONTH 0x1ffe -#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */ -#define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */ -#define TODC_TYPE_DS1643_HOURS 0x1ffb -#define TODC_TYPE_DS1643_MINUTES 0x1ffa -#define TODC_TYPE_DS1643_SECONDS 0x1ff9 -#define TODC_TYPE_DS1643_CNTL_B 0x1ff9 -#define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1643_WATCHDOG 0x1fff -#define TODC_TYPE_DS1643_INTERRUPTS 0x1fff -#define TODC_TYPE_DS1643_ALARM_DATE 0x1fff -#define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff -#define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff -#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff -#define TODC_TYPE_DS1643_CENTURY 0x1ff8 -#define TODC_TYPE_DS1643_FLAGS 0x1fff -#define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1643_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */ -#define TODC_TYPE_DS1693_SW_FLAGS 0 -#define TODC_TYPE_DS1693_YEAR 0x09 -#define TODC_TYPE_DS1693_MONTH 0x08 -#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */ -#define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */ -#define TODC_TYPE_DS1693_HOURS 0x04 -#define TODC_TYPE_DS1693_MINUTES 0x02 -#define TODC_TYPE_DS1693_SECONDS 0x00 -#define TODC_TYPE_DS1693_CNTL_B 0x0b -#define TODC_TYPE_DS1693_CNTL_A 0x0a -#define TODC_TYPE_DS1693_WATCHDOG 0xff -#define TODC_TYPE_DS1693_INTERRUPTS 0xff -#define TODC_TYPE_DS1693_ALARM_DATE 0x49 -#define TODC_TYPE_DS1693_ALARM_HOUR 0x05 -#define TODC_TYPE_DS1693_ALARM_MINUTES 0x03 -#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01 -#define TODC_TYPE_DS1693_CENTURY 0x48 -#define TODC_TYPE_DS1693_FLAGS 0xff -#define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1693_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8 -#define TODC_TYPE_DS1743_SW_FLAGS 0 -#define TODC_TYPE_DS1743_YEAR 0x1fff -#define TODC_TYPE_DS1743_MONTH 0x1ffe -#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */ -#define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */ -#define TODC_TYPE_DS1743_HOURS 0x1ffb -#define TODC_TYPE_DS1743_MINUTES 0x1ffa -#define TODC_TYPE_DS1743_SECONDS 0x1ff9 -#define TODC_TYPE_DS1743_CNTL_B 0x1ff9 -#define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1743_WATCHDOG 0x1fff -#define TODC_TYPE_DS1743_INTERRUPTS 0x1fff -#define TODC_TYPE_DS1743_ALARM_DATE 0x1fff -#define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff -#define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff -#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff -#define TODC_TYPE_DS1743_CENTURY 0x1ff8 -#define TODC_TYPE_DS1743_FLAGS 0x1fff -#define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1743_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8 -#define TODC_TYPE_DS1746_SW_FLAGS 0 -#define TODC_TYPE_DS1746_YEAR 0x1ffff -#define TODC_TYPE_DS1746_MONTH 0x1fffe -#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */ -#define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */ -#define TODC_TYPE_DS1746_HOURS 0x1fffb -#define TODC_TYPE_DS1746_MINUTES 0x1fffa -#define TODC_TYPE_DS1746_SECONDS 0x1fff9 -#define TODC_TYPE_DS1746_CNTL_B 0x1fff9 -#define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1746_WATCHDOG 0x00000 -#define TODC_TYPE_DS1746_INTERRUPTS 0x00000 -#define TODC_TYPE_DS1746_ALARM_DATE 0x00000 -#define TODC_TYPE_DS1746_ALARM_HOUR 0x00000 -#define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000 -#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000 -#define TODC_TYPE_DS1746_CENTURY 0x00000 -#define TODC_TYPE_DS1746_FLAGS 0x00000 -#define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1746_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8 -#define TODC_TYPE_DS1747_SW_FLAGS 0 -#define TODC_TYPE_DS1747_YEAR 0x7ffff -#define TODC_TYPE_DS1747_MONTH 0x7fffe -#define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */ -#define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */ -#define TODC_TYPE_DS1747_HOURS 0x7fffb -#define TODC_TYPE_DS1747_MINUTES 0x7fffa -#define TODC_TYPE_DS1747_SECONDS 0x7fff9 -#define TODC_TYPE_DS1747_CNTL_B 0x7fff9 -#define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1747_WATCHDOG 0x00000 -#define TODC_TYPE_DS1747_INTERRUPTS 0x00000 -#define TODC_TYPE_DS1747_ALARM_DATE 0x00000 -#define TODC_TYPE_DS1747_ALARM_HOUR 0x00000 -#define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000 -#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000 -#define TODC_TYPE_DS1747_CENTURY 0x00000 -#define TODC_TYPE_DS1747_FLAGS 0x00000 -#define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1747_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */ -#define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM -#define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00) -#define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01) -#define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02) -#define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03) -#define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04) -#define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05) -#define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06) -#define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07) -#define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08) -#define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09) -#define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A) -#define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B) -#define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C) -#define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D) -#define TODC_TYPE_DS17285_WATCHDOG 0 -#define TODC_TYPE_DS17285_INTERRUPTS 0 -#define TODC_TYPE_DS17285_ALARM_DATE 0 -#define TODC_TYPE_DS17285_CENTURY 0 -#define TODC_TYPE_DS17285_FLAGS 0 -#define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50 -#define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53 - -#define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */ -#define TODC_TYPE_MC146818_SW_FLAGS 0 -#define TODC_TYPE_MC146818_YEAR 0x09 -#define TODC_TYPE_MC146818_MONTH 0x08 -#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */ -#define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */ -#define TODC_TYPE_MC146818_HOURS 0x04 -#define TODC_TYPE_MC146818_MINUTES 0x02 -#define TODC_TYPE_MC146818_SECONDS 0x00 -#define TODC_TYPE_MC146818_CNTL_B 0x0a -#define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */ -#define TODC_TYPE_MC146818_WATCHDOG 0 -#define TODC_TYPE_MC146818_INTERRUPTS 0x0c -#define TODC_TYPE_MC146818_ALARM_DATE 0xff -#define TODC_TYPE_MC146818_ALARM_HOUR 0x05 -#define TODC_TYPE_MC146818_ALARM_MINUTES 0x03 -#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01 -#define TODC_TYPE_MC146818_CENTURY 0xff -#define TODC_TYPE_MC146818_FLAGS 0xff -#define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0 -#define TODC_TYPE_MC146818_NVRAM_DATA_REG 0 - -#define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */ -#define TODC_TYPE_PC97307_SW_FLAGS 0 -#define TODC_TYPE_PC97307_YEAR 0x09 -#define TODC_TYPE_PC97307_MONTH 0x08 -#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */ -#define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */ -#define TODC_TYPE_PC97307_HOURS 0x04 -#define TODC_TYPE_PC97307_MINUTES 0x02 -#define TODC_TYPE_PC97307_SECONDS 0x00 -#define TODC_TYPE_PC97307_CNTL_B 0x0a -#define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */ -#define TODC_TYPE_PC97307_WATCHDOG 0x0c -#define TODC_TYPE_PC97307_INTERRUPTS 0x0d -#define TODC_TYPE_PC97307_ALARM_DATE 0xff -#define TODC_TYPE_PC97307_ALARM_HOUR 0x05 -#define TODC_TYPE_PC97307_ALARM_MINUTES 0x03 -#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01 -#define TODC_TYPE_PC97307_CENTURY 0xff -#define TODC_TYPE_PC97307_FLAGS 0xff -#define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0 -#define TODC_TYPE_PC97307_NVRAM_DATA_REG 0 - -/* - * Define macros to allocate and init the todc_info_t table that will - * be used by the todc_time.c routines. - */ -#define TODC_ALLOC() \ - static todc_info_t todc_info_alloc; \ - todc_info_t *todc_info = &todc_info_alloc; - -#define TODC_INIT(clock_type, as0, as1, data, bits) { \ - todc_info->rtc_type = clock_type; \ - \ - todc_info->nvram_as0 = (unsigned int)(as0); \ - todc_info->nvram_as1 = (unsigned int)(as1); \ - todc_info->nvram_data = (unsigned int)(data); \ - \ - todc_info->as0_bits = (bits); \ - \ - todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \ - todc_info->sw_flags = clock_type ##_SW_FLAGS; \ - \ - todc_info->year = clock_type ##_YEAR; \ - todc_info->month = clock_type ##_MONTH; \ - todc_info->day_of_month = clock_type ##_DOM; \ - todc_info->day_of_week = clock_type ##_DOW; \ - todc_info->hours = clock_type ##_HOURS; \ - todc_info->minutes = clock_type ##_MINUTES; \ - todc_info->seconds = clock_type ##_SECONDS; \ - todc_info->control_b = clock_type ##_CNTL_B; \ - todc_info->control_a = clock_type ##_CNTL_A; \ - todc_info->watchdog = clock_type ##_WATCHDOG; \ - todc_info->interrupts = clock_type ##_INTERRUPTS; \ - todc_info->alarm_date = clock_type ##_ALARM_DATE; \ - todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \ - todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \ - todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \ - todc_info->century = clock_type ##_CENTURY; \ - todc_info->flags = clock_type ##_FLAGS; \ - \ - todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \ - todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \ -} - -extern todc_info_t *todc_info; - -unsigned char todc_direct_read_val(int addr); -void todc_direct_write_val(int addr, unsigned char val); -unsigned char todc_m48txx_read_val(int addr); -void todc_m48txx_write_val(int addr, unsigned char val); -unsigned char todc_mc146818_read_val(int addr); -void todc_mc146818_write_val(int addr, unsigned char val); - -long todc_time_init(void); -unsigned long todc_get_rtc_time(void); -int todc_set_rtc_time(unsigned long nowtime); -void todc_calibrate_decr(void); - -#endif /* __PPC_KERNEL_TODC_H */ diff --git a/include/asm-ppc/traps.h b/include/asm-ppc/traps.h deleted file mode 100644 index 68e7326b56f1..000000000000 --- a/include/asm-ppc/traps.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-ppc/zorro.h b/include/asm-ppc/zorro.h deleted file mode 100644 index 1e5fbc65e77b..000000000000 --- a/include/asm-ppc/zorro.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _ASM_PPC_ZORRO_H -#define _ASM_PPC_ZORRO_H - -#include - -#define z_readb in_8 -#define z_readw in_be16 -#define z_readl in_be32 - -#define z_writeb(val, port) out_8((port), (val)) -#define z_writew(val, port) out_be16((port), (val)) -#define z_writel(val, port) out_be32((port), (val)) - -#define z_memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define z_memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define z_memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -extern void *__ioremap(unsigned long address, unsigned long size, - unsigned long flags); - -extern void *ioremap(unsigned long address, unsigned long size); -extern void iounmap(void *addr); - -extern void *__ioremap(unsigned long address, unsigned long size, - unsigned long flags); - -#define z_ioremap ioremap -#define z_iounmap iounmap - -#endif /* _ASM_PPC_ZORRO_H */ -- cgit v1.2.3 From 83ff9dcf375c418ca3b98eb950711525ca1269e2 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Fri, 23 May 2008 20:38:54 +0400 Subject: powerpc/sysdev: implement FSL GTM support GTM stands for General-purpose Timers Module and able to generate timer{1,2,3,4} interrupts. These timers are used by the drivers that need time precise interrupts (like for USB transactions scheduling for the Freescale USB Host controller as found in some QE and CPM chips), or these timers could be used as wakeup events from the CPU deep-sleep mode. Things unimplemented: 1. Cascaded (32 bit) timers (1-2, 3-4). This is straightforward to implement when needed, two timers should be marked as "requested" and configured as appropriate. 2. Super-cascaded (64 bit) timers (1-2-3-4). This is also straightforward to implement when needed, all timers should be marked as "requested" and configured as appropriate. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- Documentation/powerpc/booting-without-of.txt | 32 ++ arch/powerpc/Kconfig | 6 + arch/powerpc/sysdev/Makefile | 1 + arch/powerpc/sysdev/fsl_gtm.c | 434 +++++++++++++++++++++++++++ include/asm-powerpc/fsl_gtm.h | 47 +++ 5 files changed, 520 insertions(+) create mode 100644 arch/powerpc/sysdev/fsl_gtm.c create mode 100644 include/asm-powerpc/fsl_gtm.h (limited to 'include') diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt index 948f6417a40b..8675ebca2cfd 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt @@ -61,6 +61,7 @@ Table of Contents r) Freescale Display Interface Unit s) Freescale on board FPGA t) Freescael MSI interrupt controller + u) Freescale General-purpose Timers Module VII - Marvell Discovery mv64[345]6x System Controller chips 1) The /system-controller node @@ -2907,6 +2908,37 @@ platforms are moved over to use the flattened-device-tree model. interrupt-parent = <&mpic>; }; + u) Freescale General-purpose Timers Module + + Required properties: + - compatible : should be + "fsl,-gtm", "fsl,gtm" for SOC GTMs + "fsl,-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs + "fsl,-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs + - reg : should contain gtm registers location and length (0x40). + - interrupts : should contain four interrupts. + - interrupt-parent : interrupt source phandle. + - clock-frequency : specifies the frequency driving the timer. + + Example: + + timer@500 { + compatible = "fsl,mpc8360-gtm", "fsl,gtm"; + reg = <0x500 0x40>; + interrupts = <90 8 78 8 84 8 72 8>; + interrupt-parent = <&ipic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + timer@440 { + compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; + reg = <0x440 0x40>; + interrupts = <12 13 14 15>; + interrupt-parent = <&qeic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; VII - Marvell Discovery mv64[345]6x System Controller chips =========================================================== diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 3934e2659407..2cde4e333fd5 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -538,6 +538,12 @@ config FSL_LBC help Freescale Localbus support +config FSL_GTM + bool + depends on PPC_83xx || QUICC_ENGINE || CPM2 + help + Freescale General-purpose Timers support + # Yes MCA RS/6000s exist but Linux-PPC does not currently support any config MCA bool diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index dd6dff3ffb0f..2bfbb39380e9 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o obj-$(CONFIG_FSL_SOC) += fsl_soc.o obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y) obj-$(CONFIG_FSL_LBC) += fsl_lbc.o +obj-$(CONFIG_FSL_GTM) += fsl_gtm.o obj-$(CONFIG_RAPIDIO) += fsl_rio.o obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ diff --git a/arch/powerpc/sysdev/fsl_gtm.c b/arch/powerpc/sysdev/fsl_gtm.c new file mode 100644 index 000000000000..714ec02fed2e --- /dev/null +++ b/arch/powerpc/sysdev/fsl_gtm.c @@ -0,0 +1,434 @@ +/* + * Freescale General-purpose Timers Module + * + * Copyright (c) Freescale Semicondutor, Inc. 2006. + * Shlomi Gridish + * Jerry Huang + * Copyright (c) MontaVista Software, Inc. 2008. + * Anton Vorontsov + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GTCFR_STP(x) ((x) & 1 ? 1 << 5 : 1 << 1) +#define GTCFR_RST(x) ((x) & 1 ? 1 << 4 : 1 << 0) + +#define GTMDR_ICLK_MASK (3 << 1) +#define GTMDR_ICLK_ICAS (0 << 1) +#define GTMDR_ICLK_ICLK (1 << 1) +#define GTMDR_ICLK_SLGO (2 << 1) +#define GTMDR_FRR (1 << 3) +#define GTMDR_ORI (1 << 4) +#define GTMDR_SPS(x) ((x) << 8) + +struct gtm_timers_regs { + u8 gtcfr1; /* Timer 1, Timer 2 global config register */ + u8 res0[0x3]; + u8 gtcfr2; /* Timer 3, timer 4 global config register */ + u8 res1[0xB]; + __be16 gtmdr1; /* Timer 1 mode register */ + __be16 gtmdr2; /* Timer 2 mode register */ + __be16 gtrfr1; /* Timer 1 reference register */ + __be16 gtrfr2; /* Timer 2 reference register */ + __be16 gtcpr1; /* Timer 1 capture register */ + __be16 gtcpr2; /* Timer 2 capture register */ + __be16 gtcnr1; /* Timer 1 counter */ + __be16 gtcnr2; /* Timer 2 counter */ + __be16 gtmdr3; /* Timer 3 mode register */ + __be16 gtmdr4; /* Timer 4 mode register */ + __be16 gtrfr3; /* Timer 3 reference register */ + __be16 gtrfr4; /* Timer 4 reference register */ + __be16 gtcpr3; /* Timer 3 capture register */ + __be16 gtcpr4; /* Timer 4 capture register */ + __be16 gtcnr3; /* Timer 3 counter */ + __be16 gtcnr4; /* Timer 4 counter */ + __be16 gtevr1; /* Timer 1 event register */ + __be16 gtevr2; /* Timer 2 event register */ + __be16 gtevr3; /* Timer 3 event register */ + __be16 gtevr4; /* Timer 4 event register */ + __be16 gtpsr1; /* Timer 1 prescale register */ + __be16 gtpsr2; /* Timer 2 prescale register */ + __be16 gtpsr3; /* Timer 3 prescale register */ + __be16 gtpsr4; /* Timer 4 prescale register */ + u8 res2[0x40]; +} __attribute__ ((packed)); + +struct gtm { + unsigned int clock; + struct gtm_timers_regs __iomem *regs; + struct gtm_timer timers[4]; + spinlock_t lock; + struct list_head list_node; +}; + +static LIST_HEAD(gtms); + +/** + * gtm_get_timer - request GTM timer to use it with the rest of GTM API + * Context: non-IRQ + * + * This function reserves GTM timer for later use. It returns gtm_timer + * structure to use with the rest of GTM API, you should use timer->irq + * to manage timer interrupt. + */ +struct gtm_timer *gtm_get_timer16(void) +{ + struct gtm *gtm = NULL; + int i; + + list_for_each_entry(gtm, >ms, list_node) { + spin_lock_irq(>m->lock); + + for (i = 0; i < ARRAY_SIZE(gtm->timers); i++) { + if (!gtm->timers[i].requested) { + gtm->timers[i].requested = true; + spin_unlock_irq(>m->lock); + return >m->timers[i]; + } + } + + spin_unlock_irq(>m->lock); + } + + if (gtm) + return ERR_PTR(-EBUSY); + return ERR_PTR(-ENODEV); +} +EXPORT_SYMBOL(gtm_get_timer16); + +/** + * gtm_get_specific_timer - request specific GTM timer + * @gtm: specific GTM, pass here GTM's device_node->data + * @timer: specific timer number, Timer1 is 0. + * Context: non-IRQ + * + * This function reserves GTM timer for later use. It returns gtm_timer + * structure to use with the rest of GTM API, you should use timer->irq + * to manage timer interrupt. + */ +struct gtm_timer *gtm_get_specific_timer16(struct gtm *gtm, + unsigned int timer) +{ + struct gtm_timer *ret = ERR_PTR(-EBUSY); + + if (timer > 3) + return ERR_PTR(-EINVAL); + + spin_lock_irq(>m->lock); + + if (gtm->timers[timer].requested) + goto out; + + ret = >m->timers[timer]; + ret->requested = true; + +out: + spin_unlock_irq(>m->lock); + return ret; +} +EXPORT_SYMBOL(gtm_get_specific_timer16); + +/** + * gtm_put_timer16 - release 16 bits GTM timer + * @tmr: pointer to the gtm_timer structure obtained from gtm_get_timer + * Context: any + * + * This function releases GTM timer so others may request it. + */ +void gtm_put_timer16(struct gtm_timer *tmr) +{ + gtm_stop_timer16(tmr); + + spin_lock_irq(&tmr->gtm->lock); + tmr->requested = false; + spin_unlock_irq(&tmr->gtm->lock); +} +EXPORT_SYMBOL(gtm_put_timer16); + +/* + * This is back-end for the exported functions, it's used to reset single + * timer in reference mode. + */ +static int gtm_set_ref_timer16(struct gtm_timer *tmr, int frequency, + int reference_value, bool free_run) +{ + struct gtm *gtm = tmr->gtm; + int num = tmr - >m->timers[0]; + unsigned int prescaler; + u8 iclk = GTMDR_ICLK_ICLK; + u8 psr; + u8 sps; + unsigned long flags; + int max_prescaler = 256 * 256 * 16; + + /* CPM2 doesn't have primary prescaler */ + if (!tmr->gtpsr) + max_prescaler /= 256; + + prescaler = gtm->clock / frequency; + /* + * We have two 8 bit prescalers -- primary and secondary (psr, sps), + * plus "slow go" mode (clk / 16). So, total prescale value is + * 16 * (psr + 1) * (sps + 1). Though, for CPM2 GTMs we losing psr. + */ + if (prescaler > max_prescaler) + return -EINVAL; + + if (prescaler > max_prescaler / 16) { + iclk = GTMDR_ICLK_SLGO; + prescaler /= 16; + } + + if (prescaler <= 256) { + psr = 0; + sps = prescaler - 1; + } else { + psr = 256 - 1; + sps = prescaler / 256 - 1; + } + + spin_lock_irqsave(>m->lock, flags); + + /* + * Properly reset timers: stop, reset, set up prescalers, reference + * value and clear event register. + */ + clrsetbits_8(tmr->gtcfr, ~(GTCFR_STP(num) | GTCFR_RST(num)), + GTCFR_STP(num) | GTCFR_RST(num)); + + setbits8(tmr->gtcfr, GTCFR_STP(num)); + + if (tmr->gtpsr) + out_be16(tmr->gtpsr, psr); + clrsetbits_be16(tmr->gtmdr, 0xFFFF, iclk | GTMDR_SPS(sps) | + GTMDR_ORI | (free_run ? GTMDR_FRR : 0)); + out_be16(tmr->gtcnr, 0); + out_be16(tmr->gtrfr, reference_value); + out_be16(tmr->gtevr, 0xFFFF); + + /* Let it be. */ + clrbits8(tmr->gtcfr, GTCFR_STP(num)); + + spin_unlock_irqrestore(>m->lock, flags); + + return 0; +} + +/** + * gtm_set_timer16 - (re)set 16 bit timer with arbitrary precision + * @tmr: pointer to the gtm_timer structure obtained from gtm_get_timer + * @usec: timer interval in microseconds + * @reload: if set, the timer will reset upon expiry rather than + * continue running free. + * Context: any + * + * This function (re)sets the GTM timer so that it counts up to the requested + * interval value, and fires the interrupt when the value is reached. This + * function will reduce the precision of the timer as needed in order for the + * requested timeout to fit in a 16-bit register. + */ +int gtm_set_timer16(struct gtm_timer *tmr, unsigned long usec, bool reload) +{ + /* quite obvious, frequency which is enough for µSec precision */ + int freq = 1000000; + unsigned int bit; + + bit = fls_long(usec); + if (bit > 15) { + freq >>= bit - 15; + usec >>= bit - 15; + } + + if (!freq) + return -EINVAL; + + return gtm_set_ref_timer16(tmr, freq, usec, reload); +} +EXPORT_SYMBOL(gtm_set_timer16); + +/** + * gtm_set_exact_utimer16 - (re)set 16 bits timer + * @tmr: pointer to the gtm_timer structure obtained from gtm_get_timer + * @usec: timer interval in microseconds + * @reload: if set, the timer will reset upon expiry rather than + * continue running free. + * Context: any + * + * This function (re)sets GTM timer so that it counts up to the requested + * interval value, and fires the interrupt when the value is reached. If reload + * flag was set, timer will also reset itself upon reference value, otherwise + * it continues to increment. + * + * The _exact_ bit in the function name states that this function will not + * crop precision of the "usec" argument, thus usec is limited to 16 bits + * (single timer width). + */ +int gtm_set_exact_timer16(struct gtm_timer *tmr, u16 usec, bool reload) +{ + /* quite obvious, frequency which is enough for µSec precision */ + const int freq = 1000000; + + /* + * We can lower the frequency (and probably power consumption) by + * dividing both frequency and usec by 2 until there is no remainder. + * But we won't bother with this unless savings are measured, so just + * run the timer as is. + */ + + return gtm_set_ref_timer16(tmr, freq, usec, reload); +} +EXPORT_SYMBOL(gtm_set_exact_timer16); + +/** + * gtm_stop_timer16 - stop single timer + * @tmr: pointer to the gtm_timer structure obtained from gtm_get_timer + * Context: any + * + * This function simply stops the GTM timer. + */ +void gtm_stop_timer16(struct gtm_timer *tmr) +{ + struct gtm *gtm = tmr->gtm; + int num = tmr - >m->timers[0]; + unsigned long flags; + + spin_lock_irqsave(>m->lock, flags); + + setbits8(tmr->gtcfr, GTCFR_STP(num)); + out_be16(tmr->gtevr, 0xFFFF); + + spin_unlock_irqrestore(>m->lock, flags); +} +EXPORT_SYMBOL(gtm_stop_timer16); + +/** + * gtm_ack_timer16 - acknowledge timer event (free-run timers only) + * @tmr: pointer to the gtm_timer structure obtained from gtm_get_timer + * @events: events mask to ack + * Context: any + * + * Thus function used to acknowledge timer interrupt event, use it inside the + * interrupt handler. + */ +void gtm_ack_timer16(struct gtm_timer *tmr, u16 events) +{ + out_be16(tmr->gtevr, events); +} +EXPORT_SYMBOL(gtm_ack_timer16); + +static void __init gtm_set_shortcuts(struct device_node *np, + struct gtm_timer *timers, + struct gtm_timers_regs __iomem *regs) +{ + /* + * Yeah, I don't like this either, but timers' registers a bit messed, + * so we have to provide shortcuts to write timer independent code. + * Alternative option is to create gt*() accessors, but that will be + * even uglier and cryptic. + */ + timers[0].gtcfr = ®s->gtcfr1; + timers[0].gtmdr = ®s->gtmdr1; + timers[0].gtcnr = ®s->gtcnr1; + timers[0].gtrfr = ®s->gtrfr1; + timers[0].gtevr = ®s->gtevr1; + + timers[1].gtcfr = ®s->gtcfr1; + timers[1].gtmdr = ®s->gtmdr2; + timers[1].gtcnr = ®s->gtcnr2; + timers[1].gtrfr = ®s->gtrfr2; + timers[1].gtevr = ®s->gtevr2; + + timers[2].gtcfr = ®s->gtcfr2; + timers[2].gtmdr = ®s->gtmdr3; + timers[2].gtcnr = ®s->gtcnr3; + timers[2].gtrfr = ®s->gtrfr3; + timers[2].gtevr = ®s->gtevr3; + + timers[3].gtcfr = ®s->gtcfr2; + timers[3].gtmdr = ®s->gtmdr4; + timers[3].gtcnr = ®s->gtcnr4; + timers[3].gtrfr = ®s->gtrfr4; + timers[3].gtevr = ®s->gtevr4; + + /* CPM2 doesn't have primary prescaler */ + if (!of_device_is_compatible(np, "fsl,cpm2-gtm")) { + timers[0].gtpsr = ®s->gtpsr1; + timers[1].gtpsr = ®s->gtpsr2; + timers[2].gtpsr = ®s->gtpsr3; + timers[3].gtpsr = ®s->gtpsr4; + } +} + +static int __init fsl_gtm_init(void) +{ + struct device_node *np; + + for_each_compatible_node(np, NULL, "fsl,gtm") { + int i; + struct gtm *gtm; + const u32 *clock; + int size; + + gtm = kzalloc(sizeof(*gtm), GFP_KERNEL); + if (!gtm) { + pr_err("%s: unable to allocate memory\n", + np->full_name); + continue; + } + + spin_lock_init(>m->lock); + + clock = of_get_property(np, "clock-frequency", &size); + if (!clock || size != sizeof(*clock)) { + pr_err("%s: no clock-frequency\n", np->full_name); + goto err; + } + gtm->clock = *clock; + + for (i = 0; i < ARRAY_SIZE(gtm->timers); i++) { + int ret; + struct resource irq; + + ret = of_irq_to_resource(np, i, &irq); + if (ret == NO_IRQ) { + pr_err("%s: not enough interrupts specified\n", + np->full_name); + goto err; + } + gtm->timers[i].irq = irq.start; + gtm->timers[i].gtm = gtm; + } + + gtm->regs = of_iomap(np, 0); + if (!gtm->regs) { + pr_err("%s: unable to iomap registers\n", + np->full_name); + goto err; + } + + gtm_set_shortcuts(np, gtm->timers, gtm->regs); + list_add(>m->list_node, >ms); + + /* We don't want to lose the node and its ->data */ + np->data = gtm; + of_node_get(np); + + continue; +err: + kfree(gtm); + } + return 0; +} +arch_initcall(fsl_gtm_init); diff --git a/include/asm-powerpc/fsl_gtm.h b/include/asm-powerpc/fsl_gtm.h new file mode 100644 index 000000000000..8e8c9b5032d3 --- /dev/null +++ b/include/asm-powerpc/fsl_gtm.h @@ -0,0 +1,47 @@ +/* + * Freescale General-purpose Timers Module + * + * Copyright (c) Freescale Semicondutor, Inc. 2006. + * Shlomi Gridish + * Jerry Huang + * Copyright (c) MontaVista Software, Inc. 2008. + * Anton Vorontsov + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_FSL_GTM_H +#define __ASM_FSL_GTM_H + +#include + +struct gtm; + +struct gtm_timer { + unsigned int irq; + + struct gtm *gtm; + bool requested; + u8 __iomem *gtcfr; + __be16 __iomem *gtmdr; + __be16 __iomem *gtpsr; + __be16 __iomem *gtcnr; + __be16 __iomem *gtrfr; + __be16 __iomem *gtevr; +}; + +extern struct gtm_timer *gtm_get_timer16(void); +extern struct gtm_timer *gtm_get_specific_timer16(struct gtm *gtm, + unsigned int timer); +extern void gtm_put_timer16(struct gtm_timer *tmr); +extern int gtm_set_timer16(struct gtm_timer *tmr, unsigned long usec, + bool reload); +extern int gtm_set_exact_timer16(struct gtm_timer *tmr, u16 usec, + bool reload); +extern void gtm_stop_timer16(struct gtm_timer *tmr); +extern void gtm_ack_timer16(struct gtm_timer *tmr, u16 events); + +#endif /* __ASM_FSL_GTM_H */ -- cgit v1.2.3 From 5e41486c408eb4206aee09303631427f57771691 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Fri, 23 May 2008 20:38:56 +0400 Subject: powerpc/QE: add support for QE USB clocks routing This patch adds a function to the qe_lib to setup QE USB clocks routing. To setup clocks safely, cmxgcr register needs locking, so I just reused ucc_lock since it was used only to protect cmxgcr. The idea behind placing clocks routing functions into the qe_lib is that later we'll hopefully switch to the generic Linux Clock API, thus, for example, FHCI driver may be used for QE and CPM chips without nasty #ifdefs. This patch also fixes QE_USB_RESTART_TX command definition in the qe.h. Signed-off-by: Anton Vorontsov Acked-By: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/qe_lib/Kconfig | 4 +++ arch/powerpc/sysdev/qe_lib/Makefile | 1 + arch/powerpc/sysdev/qe_lib/ucc.c | 7 +++-- arch/powerpc/sysdev/qe_lib/usb.c | 55 +++++++++++++++++++++++++++++++++++++ include/asm-powerpc/qe.h | 23 +++++++++++++++- 5 files changed, 86 insertions(+), 4 deletions(-) create mode 100644 arch/powerpc/sysdev/qe_lib/usb.c (limited to 'include') diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig index adc66212a419..76ffbc48d4b9 100644 --- a/arch/powerpc/sysdev/qe_lib/Kconfig +++ b/arch/powerpc/sysdev/qe_lib/Kconfig @@ -20,3 +20,7 @@ config UCC bool default y if UCC_FAST || UCC_SLOW +config QE_USB + bool + help + QE USB Host Controller support diff --git a/arch/powerpc/sysdev/qe_lib/Makefile b/arch/powerpc/sysdev/qe_lib/Makefile index 874fe1a5b1cf..e9ff8884f74a 100644 --- a/arch/powerpc/sysdev/qe_lib/Makefile +++ b/arch/powerpc/sysdev/qe_lib/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_ic.o qe_io.o obj-$(CONFIG_UCC) += ucc.o obj-$(CONFIG_UCC_SLOW) += ucc_slow.o obj-$(CONFIG_UCC_FAST) += ucc_fast.o +obj-$(CONFIG_QE_USB) += usb.o diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c index 0e348d9af8a6..d3c7f5af9bc8 100644 --- a/arch/powerpc/sysdev/qe_lib/ucc.c +++ b/arch/powerpc/sysdev/qe_lib/ucc.c @@ -26,7 +26,8 @@ #include #include -static DEFINE_SPINLOCK(ucc_lock); +DEFINE_SPINLOCK(cmxgcr_lock); +EXPORT_SYMBOL(cmxgcr_lock); int ucc_set_qe_mux_mii_mng(unsigned int ucc_num) { @@ -35,10 +36,10 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num) if (ucc_num > UCC_MAX_NUM - 1) return -EINVAL; - spin_lock_irqsave(&ucc_lock, flags); + spin_lock_irqsave(&cmxgcr_lock, flags); clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT); - spin_unlock_irqrestore(&ucc_lock, flags); + spin_unlock_irqrestore(&cmxgcr_lock, flags); return 0; } diff --git a/arch/powerpc/sysdev/qe_lib/usb.c b/arch/powerpc/sysdev/qe_lib/usb.c new file mode 100644 index 000000000000..8105462078eb --- /dev/null +++ b/arch/powerpc/sysdev/qe_lib/usb.c @@ -0,0 +1,55 @@ +/* + * QE USB routines + * + * Copyright (c) Freescale Semicondutor, Inc. 2006. + * Shlomi Gridish + * Jerry Huang + * Copyright (c) MontaVista Software, Inc. 2008. + * Anton Vorontsov + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +int qe_usb_clock_set(enum qe_clock clk, int rate) +{ + struct qe_mux __iomem *mux = &qe_immr->qmx; + unsigned long flags; + u32 val; + + switch (clk) { + case QE_CLK3: val = QE_CMXGCR_USBCS_CLK3; break; + case QE_CLK5: val = QE_CMXGCR_USBCS_CLK5; break; + case QE_CLK7: val = QE_CMXGCR_USBCS_CLK7; break; + case QE_CLK9: val = QE_CMXGCR_USBCS_CLK9; break; + case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break; + case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break; + case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break; + case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break; + case QE_BRG9: val = QE_CMXGCR_USBCS_BRG9; break; + case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break; + default: + pr_err("%s: requested unknown clock %d\n", __func__, clk); + return -EINVAL; + } + + if (qe_clock_is_brg(clk)) + qe_setbrg(clk, rate, 1); + + spin_lock_irqsave(&cmxgcr_lock, flags); + + clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val); + + spin_unlock_irqrestore(&cmxgcr_lock, flags); + + return 0; +} +EXPORT_SYMBOL(qe_usb_clock_set); diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index c3be6e2e1490..d217288ec6bf 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -16,6 +16,7 @@ #define _ASM_POWERPC_QE_H #ifdef __KERNEL__ +#include #include #define QE_NUM_OF_SNUM 28 @@ -74,6 +75,13 @@ enum qe_clock { QE_CLK_DUMMY }; +static inline bool qe_clock_is_brg(enum qe_clock clk) +{ + return clk >= QE_BRG1 && clk <= QE_BRG16; +} + +extern spinlock_t cmxgcr_lock; + /* Export QE common operations */ extern void qe_reset(void); extern int par_io_init(struct device_node *np); @@ -156,6 +164,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware); /* Obtain information on the uploaded firmware */ struct qe_firmware_info *qe_get_firmware_info(void); +/* QE USB */ +int qe_usb_clock_set(enum qe_clock clk, int rate); + /* Buffer descriptors */ struct qe_bd { __be16 status; @@ -254,6 +265,16 @@ enum comm_dir { #define QE_CMXGCR_MII_ENET_MNG 0x00007000 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 #define QE_CMXGCR_USBCS 0x0000000f +#define QE_CMXGCR_USBCS_CLK3 0x1 +#define QE_CMXGCR_USBCS_CLK5 0x2 +#define QE_CMXGCR_USBCS_CLK7 0x3 +#define QE_CMXGCR_USBCS_CLK9 0x4 +#define QE_CMXGCR_USBCS_CLK13 0x5 +#define QE_CMXGCR_USBCS_CLK17 0x6 +#define QE_CMXGCR_USBCS_CLK19 0x7 +#define QE_CMXGCR_USBCS_CLK21 0x8 +#define QE_CMXGCR_USBCS_BRG9 0x9 +#define QE_CMXGCR_USBCS_BRG10 0xa /* QE CECR Commands. */ @@ -283,7 +304,7 @@ enum comm_dir { #define QE_HPAC_START_TX 0x0000060b #define QE_HPAC_START_RX 0x0000070b #define QE_USB_STOP_TX 0x0000000a -#define QE_USB_RESTART_TX 0x0000000b +#define QE_USB_RESTART_TX 0x0000000c #define QE_QMC_STOP_TX 0x0000000c #define QE_QMC_STOP_RX 0x0000000d #define QE_SS7_SU_FIL_RESET 0x0000000e -- cgit v1.2.3 From 9572653ee01a2134ae3a1d7aa29ce9d026a6afe9 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Fri, 23 May 2008 20:38:58 +0400 Subject: powerpc/QE: prepare QE PIO code for GPIO LIB support - split and export __par_io_config_pin() out of par_io_config_pin(), so we could use the prefixed version with GPIO LIB API; - rename struct port_regs to qe_pio_regs, and place it into qe.h; - rename #define NUM_OF_PINS to QE_PIO_PINS, and place it into qe.h. Signed-off-by: Anton Vorontsov Acked-By: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/qe_lib/qe_io.c | 94 ++++++++++++++++++-------------------- include/asm-powerpc/qe.h | 19 ++++++++ 2 files changed, 64 insertions(+), 49 deletions(-) (limited to 'include') diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c index 93916a48afec..7c87460179ef 100644 --- a/arch/powerpc/sysdev/qe_lib/qe_io.c +++ b/arch/powerpc/sysdev/qe_lib/qe_io.c @@ -28,21 +28,7 @@ #undef DEBUG -#define NUM_OF_PINS 32 - -struct port_regs { - __be32 cpodr; /* Open drain register */ - __be32 cpdata; /* Data register */ - __be32 cpdir1; /* Direction register */ - __be32 cpdir2; /* Direction register */ - __be32 cppar1; /* Pin assignment register */ - __be32 cppar2; /* Pin assignment register */ -#ifdef CONFIG_PPC_85xx - u8 pad[8]; -#endif -}; - -static struct port_regs __iomem *par_io; +static struct qe_pio_regs __iomem *par_io; static int num_par_io_ports = 0; int par_io_init(struct device_node *np) @@ -64,69 +50,79 @@ int par_io_init(struct device_node *np) return 0; } -int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, - int assignment, int has_irq) +void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, + int open_drain, int assignment, int has_irq) { - u32 pin_mask1bit, pin_mask2bits, new_mask2bits, tmp_val; - - if (!par_io) - return -1; + u32 pin_mask1bit; + u32 pin_mask2bits; + u32 new_mask2bits; + u32 tmp_val; /* calculate pin location for single and 2 bits information */ - pin_mask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1))); + pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1))); /* Set open drain, if required */ - tmp_val = in_be32(&par_io[port].cpodr); + tmp_val = in_be32(&par_io->cpodr); if (open_drain) - out_be32(&par_io[port].cpodr, pin_mask1bit | tmp_val); + out_be32(&par_io->cpodr, pin_mask1bit | tmp_val); else - out_be32(&par_io[port].cpodr, ~pin_mask1bit & tmp_val); + out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val); /* define direction */ - tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? - in_be32(&par_io[port].cpdir2) : - in_be32(&par_io[port].cpdir1); + tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? + in_be32(&par_io->cpdir2) : + in_be32(&par_io->cpdir1); /* get all bits mask for 2 bit per port */ - pin_mask2bits = (u32) (0x3 << (NUM_OF_PINS - - (pin % (NUM_OF_PINS / 2) + 1) * 2)); + pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS - + (pin % (QE_PIO_PINS / 2) + 1) * 2)); /* Get the final mask we need for the right definition */ - new_mask2bits = (u32) (dir << (NUM_OF_PINS - - (pin % (NUM_OF_PINS / 2) + 1) * 2)); + new_mask2bits = (u32) (dir << (QE_PIO_PINS - + (pin % (QE_PIO_PINS / 2) + 1) * 2)); /* clear and set 2 bits mask */ - if (pin > (NUM_OF_PINS / 2) - 1) { - out_be32(&par_io[port].cpdir2, + if (pin > (QE_PIO_PINS / 2) - 1) { + out_be32(&par_io->cpdir2, ~pin_mask2bits & tmp_val); tmp_val &= ~pin_mask2bits; - out_be32(&par_io[port].cpdir2, new_mask2bits | tmp_val); + out_be32(&par_io->cpdir2, new_mask2bits | tmp_val); } else { - out_be32(&par_io[port].cpdir1, + out_be32(&par_io->cpdir1, ~pin_mask2bits & tmp_val); tmp_val &= ~pin_mask2bits; - out_be32(&par_io[port].cpdir1, new_mask2bits | tmp_val); + out_be32(&par_io->cpdir1, new_mask2bits | tmp_val); } /* define pin assignment */ - tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? - in_be32(&par_io[port].cppar2) : - in_be32(&par_io[port].cppar1); + tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? + in_be32(&par_io->cppar2) : + in_be32(&par_io->cppar1); - new_mask2bits = (u32) (assignment << (NUM_OF_PINS - - (pin % (NUM_OF_PINS / 2) + 1) * 2)); + new_mask2bits = (u32) (assignment << (QE_PIO_PINS - + (pin % (QE_PIO_PINS / 2) + 1) * 2)); /* clear and set 2 bits mask */ - if (pin > (NUM_OF_PINS / 2) - 1) { - out_be32(&par_io[port].cppar2, + if (pin > (QE_PIO_PINS / 2) - 1) { + out_be32(&par_io->cppar2, ~pin_mask2bits & tmp_val); tmp_val &= ~pin_mask2bits; - out_be32(&par_io[port].cppar2, new_mask2bits | tmp_val); + out_be32(&par_io->cppar2, new_mask2bits | tmp_val); } else { - out_be32(&par_io[port].cppar1, + out_be32(&par_io->cppar1, ~pin_mask2bits & tmp_val); tmp_val &= ~pin_mask2bits; - out_be32(&par_io[port].cppar1, new_mask2bits | tmp_val); + out_be32(&par_io->cppar1, new_mask2bits | tmp_val); } +} +EXPORT_SYMBOL(__par_io_config_pin); + +int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, + int assignment, int has_irq) +{ + if (!par_io || port >= num_par_io_ports) + return -EINVAL; + __par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment, + has_irq); return 0; } EXPORT_SYMBOL(par_io_config_pin); @@ -137,10 +133,10 @@ int par_io_data_set(u8 port, u8 pin, u8 val) if (port >= num_par_io_ports) return -EINVAL; - if (pin >= NUM_OF_PINS) + if (pin >= QE_PIO_PINS) return -EINVAL; /* calculate pin location */ - pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - pin)); + pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); tmp_val = in_be32(&par_io[port].cpdata); diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index d217288ec6bf..c4523acad48b 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -84,8 +84,27 @@ extern spinlock_t cmxgcr_lock; /* Export QE common operations */ extern void qe_reset(void); + +/* QE PIO */ +#define QE_PIO_PINS 32 + +struct qe_pio_regs { + __be32 cpodr; /* Open drain register */ + __be32 cpdata; /* Data register */ + __be32 cpdir1; /* Direction register */ + __be32 cpdir2; /* Direction register */ + __be32 cppar1; /* Pin assignment register */ + __be32 cppar2; /* Pin assignment register */ +#ifdef CONFIG_PPC_85xx + u8 pad[8]; +#endif +}; + extern int par_io_init(struct device_node *np); extern int par_io_of_config(struct device_node *np); +extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, + int dir, int open_drain, int assignment, + int has_irq); extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, int assignment, int has_irq); extern int par_io_data_set(u8 port, u8 pin, u8 val); -- cgit v1.2.3 From 32def337aafee0bc65eb58d5b1b3617525eb7fb7 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Mon, 19 May 2008 21:47:05 +0400 Subject: powerpc/QE: implement support for the GPIO LIB API This is needed to access QE GPIOs via Linux GPIO API. Signed-off-by: Anton Vorontsov Acked-By: Timur Tabi Signed-off-by: Kumar Gala --- Documentation/powerpc/booting-without-of.txt | 27 +++++ arch/powerpc/sysdev/qe_lib/Kconfig | 9 ++ arch/powerpc/sysdev/qe_lib/Makefile | 1 + arch/powerpc/sysdev/qe_lib/gpio.c | 146 +++++++++++++++++++++++++++ include/asm-powerpc/qe.h | 3 + 5 files changed, 186 insertions(+) create mode 100644 arch/powerpc/sysdev/qe_lib/gpio.c (limited to 'include') diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt index 8675ebca2cfd..b68684d39f96 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt @@ -1736,6 +1736,33 @@ platforms are moved over to use the flattened-device-tree model. ...... }; + Note that "par_io" nodes are obsolete, and should not be used for + the new device trees. Instead, each Par I/O bank should be represented + via its own gpio-controller node: + + Required properties: + - #gpio-cells : should be "2". + - compatible : should be "fsl,-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank". + - reg : offset to the register set and its length. + - gpio-controller : node to identify gpio controllers. + + Example: + qe_pio_a: gpio-controller@1400 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1400 0x18>; + gpio-controller; + }; + + qe_pio_e: gpio-controller@1460 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1460 0x18>; + gpio-controller; + }; vi) Pin configuration nodes diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig index 76ffbc48d4b9..4bb18f57901e 100644 --- a/arch/powerpc/sysdev/qe_lib/Kconfig +++ b/arch/powerpc/sysdev/qe_lib/Kconfig @@ -24,3 +24,12 @@ config QE_USB bool help QE USB Host Controller support + +config QE_GPIO + bool "QE GPIO support" + depends on QUICC_ENGINE + select GENERIC_GPIO + select HAVE_GPIO_LIB + help + Say Y here if you're going to use hardware that connects to the + QE GPIOs. diff --git a/arch/powerpc/sysdev/qe_lib/Makefile b/arch/powerpc/sysdev/qe_lib/Makefile index e9ff8884f74a..f1855c185291 100644 --- a/arch/powerpc/sysdev/qe_lib/Makefile +++ b/arch/powerpc/sysdev/qe_lib/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_UCC) += ucc.o obj-$(CONFIG_UCC_SLOW) += ucc_slow.o obj-$(CONFIG_UCC_FAST) += ucc_fast.o obj-$(CONFIG_QE_USB) += usb.o +obj-$(CONFIG_QE_GPIO) += gpio.o diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c new file mode 100644 index 000000000000..c712e245dc4c --- /dev/null +++ b/arch/powerpc/sysdev/qe_lib/gpio.c @@ -0,0 +1,146 @@ +/* + * QUICC Engine GPIOs + * + * Copyright (c) MontaVista Software, Inc. 2008. + * + * Author: Anton Vorontsov + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct qe_gpio_chip { + struct of_mm_gpio_chip mm_gc; + spinlock_t lock; + + /* shadowed data register to clear/set bits safely */ + u32 cpdata; +}; + +static inline struct qe_gpio_chip * +to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc) +{ + return container_of(mm_gc, struct qe_gpio_chip, mm_gc); +} + +static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) +{ + struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc); + struct qe_pio_regs __iomem *regs = mm_gc->regs; + + qe_gc->cpdata = in_be32(®s->cpdata); +} + +static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct qe_pio_regs __iomem *regs = mm_gc->regs; + u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); + + return in_be32(®s->cpdata) & pin_mask; +} + +static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc); + struct qe_pio_regs __iomem *regs = mm_gc->regs; + unsigned long flags; + u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); + + spin_lock_irqsave(&qe_gc->lock, flags); + + if (val) + qe_gc->cpdata |= pin_mask; + else + qe_gc->cpdata &= ~pin_mask; + + out_be32(®s->cpdata, qe_gc->cpdata); + + spin_unlock_irqrestore(&qe_gc->lock, flags); +} + +static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc); + unsigned long flags; + + spin_lock_irqsave(&qe_gc->lock, flags); + + __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); + + spin_unlock_irqrestore(&qe_gc->lock, flags); + + return 0; +} + +static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc); + unsigned long flags; + + spin_lock_irqsave(&qe_gc->lock, flags); + + __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); + + spin_unlock_irqrestore(&qe_gc->lock, flags); + + qe_gpio_set(gc, gpio, val); + + return 0; +} + +void __init qe_add_gpiochips(void) +{ + struct device_node *np; + + for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") { + int ret; + struct qe_gpio_chip *qe_gc; + struct of_mm_gpio_chip *mm_gc; + struct of_gpio_chip *of_gc; + struct gpio_chip *gc; + + qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL); + if (!qe_gc) { + ret = -ENOMEM; + goto err; + } + + spin_lock_init(&qe_gc->lock); + + mm_gc = &qe_gc->mm_gc; + of_gc = &mm_gc->of_gc; + gc = &of_gc->gc; + + mm_gc->save_regs = qe_gpio_save_regs; + of_gc->gpio_cells = 2; + gc->ngpio = QE_PIO_PINS; + gc->direction_input = qe_gpio_dir_in; + gc->direction_output = qe_gpio_dir_out; + gc->get = qe_gpio_get; + gc->set = qe_gpio_set; + + ret = of_mm_gpiochip_add(np, mm_gc); + if (ret) + goto err; + continue; +err: + pr_err("%s: registration failed with status %d\n", + np->full_name, ret); + kfree(qe_gc); + /* try others anyway */ + } +} diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index c4523acad48b..01e3c70b93ab 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -100,8 +100,11 @@ struct qe_pio_regs { #endif }; +extern void __init qe_add_gpiochips(void); extern int par_io_init(struct device_node *np); extern int par_io_of_config(struct device_node *np); +#define QE_PIO_DIR_IN 2 +#define QE_PIO_DIR_OUT 1 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, int open_drain, int assignment, int has_irq); -- cgit v1.2.3 From 5093bb965a163fe288c3e5db0275165f86c895c2 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Fri, 23 May 2008 20:39:06 +0400 Subject: powerpc/QE: switch to the cpm_muram implementation This is very trivial patch. We're transitioning to the cpm_muram_* calls. That's it. Less trivial changes: - BD_SC_* defines were defined in the cpm.h and qe.h, so to avoid redefines we remove BD_SC from the qe.h and use cpm.h along with cpm_muram_* prototypes; - qe_muram_dump was unused and thus removed; - added some code to the cpm_common.c to support legacy QE bindings (data-only node name). - For convenience, define qe_* calls to cpm_*. So drivers need not to be changed. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/Makefile | 1 + arch/powerpc/sysdev/cpm_common.c | 16 +++++-- arch/powerpc/sysdev/qe_lib/qe.c | 92 ---------------------------------------- include/asm-powerpc/cpm.h | 1 + include/asm-powerpc/qe.h | 36 ++++------------ 5 files changed, 23 insertions(+), 123 deletions(-) (limited to 'include') diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index 2bfbb39380e9..16a0ed28eb00 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -42,6 +42,7 @@ endif ifeq ($(ARCH),powerpc) obj-$(CONFIG_CPM) += cpm_common.o obj-$(CONFIG_CPM2) += cpm2.o cpm2_pic.o +obj-$(CONFIG_QUICC_ENGINE) += cpm_common.o obj-$(CONFIG_PPC_DCR) += dcr.o obj-$(CONFIG_8xx) += mpc8xx_pic.o cpm1.o obj-$(CONFIG_UCODE_PATCH) += micropatch.o diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c index cb7df2dce44f..9b75d164bdf9 100644 --- a/arch/powerpc/sysdev/cpm_common.c +++ b/arch/powerpc/sysdev/cpm_common.c @@ -85,9 +85,13 @@ int __init cpm_muram_init(void) np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data"); if (!np) { - printk(KERN_ERR "Cannot find CPM muram data node"); - ret = -ENODEV; - goto out; + /* try legacy bindings */ + np = of_find_node_by_name(NULL, "data-only"); + if (!np) { + printk(KERN_ERR "Cannot find CPM muram data node"); + ret = -ENODEV; + goto out; + } } muram_pbase = of_translate_address(np, zero); @@ -189,6 +193,12 @@ void __iomem *cpm_muram_addr(unsigned long offset) } EXPORT_SYMBOL(cpm_muram_addr); +unsigned long cpm_muram_offset(void __iomem *addr) +{ + return addr - (void __iomem *)muram_vbase; +} +EXPORT_SYMBOL(cpm_muram_offset); + /** * cpm_muram_dma - turn a muram virtual address into a DMA address * @offset: virtual address from cpm_muram_addr() to convert diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index cff550eec7e8..28e05df952de 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -35,7 +35,6 @@ #include static void qe_snums_init(void); -static void qe_muram_init(void); static int qe_sdma_init(void); static DEFINE_SPINLOCK(qe_lock); @@ -325,97 +324,6 @@ static int qe_sdma_init(void) return 0; } -/* - * muram_alloc / muram_free bits. - */ -static DEFINE_SPINLOCK(qe_muram_lock); - -/* 16 blocks should be enough to satisfy all requests - * until the memory subsystem goes up... */ -static rh_block_t qe_boot_muram_rh_block[16]; -static rh_info_t qe_muram_info; - -static void qe_muram_init(void) -{ - struct device_node *np; - const u32 *address; - u64 size; - unsigned int flags; - - /* initialize the info header */ - rh_init(&qe_muram_info, 1, - sizeof(qe_boot_muram_rh_block) / - sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block); - - /* Attach the usable muram area */ - /* XXX: This is a subset of the available muram. It - * varies with the processor and the microcode patches activated. - */ - np = of_find_compatible_node(NULL, NULL, "fsl,qe-muram-data"); - if (!np) { - np = of_find_node_by_name(NULL, "data-only"); - if (!np) { - WARN_ON(1); - return; - } - } - - address = of_get_address(np, 0, &size, &flags); - WARN_ON(!address); - - of_node_put(np); - if (address) - rh_attach_region(&qe_muram_info, *address, (int)size); -} - -/* This function returns an index into the MURAM area. - */ -unsigned long qe_muram_alloc(int size, int align) -{ - unsigned long start; - unsigned long flags; - - spin_lock_irqsave(&qe_muram_lock, flags); - start = rh_alloc_align(&qe_muram_info, size, align, "QE"); - spin_unlock_irqrestore(&qe_muram_lock, flags); - - return start; -} -EXPORT_SYMBOL(qe_muram_alloc); - -int qe_muram_free(unsigned long offset) -{ - int ret; - unsigned long flags; - - spin_lock_irqsave(&qe_muram_lock, flags); - ret = rh_free(&qe_muram_info, offset); - spin_unlock_irqrestore(&qe_muram_lock, flags); - - return ret; -} -EXPORT_SYMBOL(qe_muram_free); - -/* not sure if this is ever needed */ -unsigned long qe_muram_alloc_fixed(unsigned long offset, int size) -{ - unsigned long start; - unsigned long flags; - - spin_lock_irqsave(&qe_muram_lock, flags); - start = rh_alloc_fixed(&qe_muram_info, offset, size, "commproc"); - spin_unlock_irqrestore(&qe_muram_lock, flags); - - return start; -} -EXPORT_SYMBOL(qe_muram_alloc_fixed); - -void qe_muram_dump(void) -{ - rh_dump(&qe_muram_info); -} -EXPORT_SYMBOL(qe_muram_dump); - /* The maximum number of RISCs we support */ #define MAX_QE_RISC 2 diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h index ede38ffe466a..63a55337c2de 100644 --- a/include/asm-powerpc/cpm.h +++ b/include/asm-powerpc/cpm.h @@ -96,6 +96,7 @@ unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); int cpm_muram_free(unsigned long offset); unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); void __iomem *cpm_muram_addr(unsigned long offset); +unsigned long cpm_muram_offset(void __iomem *addr); dma_addr_t cpm_muram_dma(void __iomem *addr); int cpm_command(u32 command, u8 opcode); diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index 01e3c70b93ab..80807fd6a706 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -17,6 +17,7 @@ #ifdef __KERNEL__ #include +#include #include #define QE_NUM_OF_SNUM 28 @@ -119,20 +120,13 @@ unsigned int qe_get_brg_clk(void); int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); int qe_get_snum(void); void qe_put_snum(u8 snum); -unsigned long qe_muram_alloc(int size, int align); -int qe_muram_free(unsigned long offset); -unsigned long qe_muram_alloc_fixed(unsigned long offset, int size); -void qe_muram_dump(void); - -static inline void __iomem *qe_muram_addr(unsigned long offset) -{ - return (void __iomem *)&qe_immr->muram[offset]; -} - -static inline unsigned long qe_muram_offset(void __iomem *addr) -{ - return addr - (void __iomem *)qe_immr->muram; -} +/* we actually use cpm_muram implementation, define this for convenience */ +#define qe_muram_init cpm_muram_init +#define qe_muram_alloc cpm_muram_alloc +#define qe_muram_alloc_fixed cpm_muram_alloc_fixed +#define qe_muram_free cpm_muram_free +#define qe_muram_addr cpm_muram_addr +#define qe_muram_offset cpm_muram_offset /* Structure that defines QE firmware binary files. * @@ -199,20 +193,6 @@ struct qe_bd { #define BD_STATUS_MASK 0xffff0000 #define BD_LENGTH_MASK 0x0000ffff -#define BD_SC_EMPTY 0x8000 /* Receive is empty */ -#define BD_SC_READY 0x8000 /* Transmit is ready */ -#define BD_SC_WRAP 0x2000 /* Last buffer descriptor */ -#define BD_SC_INTRPT 0x1000 /* Interrupt on change */ -#define BD_SC_LAST 0x0800 /* Last buffer in frame */ -#define BD_SC_CM 0x0200 /* Continous mode */ -#define BD_SC_ID 0x0100 /* Rec'd too many idles */ -#define BD_SC_P 0x0100 /* xmt preamble */ -#define BD_SC_BR 0x0020 /* Break received */ -#define BD_SC_FR 0x0010 /* Framing error */ -#define BD_SC_PR 0x0008 /* Parity error */ -#define BD_SC_OV 0x0002 /* Overrun */ -#define BD_SC_CD 0x0001 /* ?? */ - /* Alignment */ #define QE_INTR_TABLE_ALIGN 16 /* ??? */ #define QE_ALIGNMENT_OF_BD 8 -- cgit v1.2.3 From 19792a0859f96e9fc8ce87d97b269bcb895389e5 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Mon, 5 May 2008 21:25:47 +0300 Subject: PCI: drivers/pci/pci.c: add prototypes This patch adds prototypes for pcibios_disable_device() and pcibios_set_pcie_reset_state() in include/linux/pci.h While I was at it, I also removed the unneeded "extern" from the prototype of pcibios_add_platform_entries(). Signed-off-by: Adrian Bunk Signed-off-by: Jesse Barnes --- include/linux/pci.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/pci.h b/include/linux/pci.h index 509159bcd4e7..aaa9f333fb44 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1059,7 +1059,10 @@ extern int pci_pci_problems; extern unsigned long pci_cardbus_io_size; extern unsigned long pci_cardbus_mem_size; -extern int pcibios_add_platform_entries(struct pci_dev *dev); +int pcibios_add_platform_entries(struct pci_dev *dev); +void pcibios_disable_device(struct pci_dev *dev); +int pcibios_set_pcie_reset_state(struct pci_dev *dev, + enum pcie_reset_state state); #ifdef CONFIG_PCI_MMCONFIG extern void __init pci_mmcfg_early_init(void); -- cgit v1.2.3 From e1a2a51e684bfe9d6165992d4a065439617a3107 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Thu, 15 May 2008 21:51:31 +0200 Subject: Suspend/Resume bug in PCI layer wrt quirks Some quirks should be called with interrupt disabled, we can't directly call them in .resume_early. Also the patch introduces pci_fixup_resume_early and pci_fixup_suspend, which matches current device core callbacks (.suspend/.resume_early). TBD: Somebody knows why we need quirk resume should double check if a quirk should be called in resume or resume_early. I changed some per my understanding, but can't make sure I fixed all. Signed-off-by: Shaohua Li Signed-off-by: Jesse Barnes --- drivers/pci/pci-driver.c | 6 +- drivers/pci/quirks.c | 118 ++++++++++++++++++++++++++------------ include/asm-generic/vmlinux.lds.h | 6 ++ include/linux/pci.h | 10 +++- 4 files changed, 101 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 72cf61ed8f96..677fd9d6db12 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -292,6 +292,9 @@ static int pci_device_suspend(struct device * dev, pm_message_t state) if (pci_dev->current_state == PCI_D0) pci_dev->current_state = PCI_UNKNOWN; } + + pci_fixup_device(pci_fixup_suspend, pci_dev); + return i; } @@ -337,6 +340,7 @@ static int pci_device_resume(struct device * dev) error = drv->resume(pci_dev); else error = pci_default_resume(pci_dev); + pci_fixup_device(pci_fixup_resume, pci_dev); return error; } @@ -346,7 +350,7 @@ static int pci_device_resume_early(struct device * dev) struct pci_dev * pci_dev = to_pci_dev(dev); struct pci_driver * drv = pci_dev->driver; - pci_fixup_device(pci_fixup_resume, pci_dev); + pci_fixup_device(pci_fixup_resume_early, pci_dev); if (drv && drv->resume_early) error = drv->resume_early(pci_dev); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index dabb563f51d9..44aabb1519a9 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -556,7 +556,7 @@ static void quirk_via_ioapic(struct pci_dev *dev) pci_write_config_byte (dev, 0x58, tmp); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); /* * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. @@ -576,7 +576,7 @@ static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); /* * The AMD io apic can hang the box when an apic irq is masked. @@ -622,7 +622,7 @@ static void quirk_amd_8131_ioapic(struct pci_dev *dev) } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); #endif /* CONFIG_X86_IO_APIC */ /* @@ -774,7 +774,7 @@ static void quirk_cardbus_legacy(struct pci_dev *dev) pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); } DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); -DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); /* * Following the PCI ordering rules is optional on the AMD762. I'm not @@ -797,7 +797,7 @@ static void quirk_amd_ordering(struct pci_dev *dev) } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); /* * DreamWorks provided workaround for Dunord I-3000 problem @@ -865,7 +865,7 @@ static void quirk_disable_pxb(struct pci_dev *pdev) } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) { @@ -885,9 +885,9 @@ static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); /* * Serverworks CSB5 IDE does not fully support native mode @@ -1093,31 +1093,61 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asu DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); -static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) +/* It appears we just have one such device. If not, we have a warning */ +static void __iomem *asus_rcba_base; +static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) { - u32 val, rcba; - void __iomem *base; + u32 rcba; if (likely(!asus_hides_smbus)) return; + WARN_ON(asus_rcba_base); + pci_read_config_dword(dev, 0xF0, &rcba); - base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ - if (base == NULL) return; - val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ - writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ - iounmap(base); + /* use bits 31:14, 16 kB aligned */ + asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); + if (asus_rcba_base == NULL) + return; +} + +static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) +{ + u32 val; + + if (likely(!asus_hides_smbus || !asus_rcba_base)) + return; + /* read the Function Disable register, dword mode only */ + val = readl(asus_rcba_base + 0x3418); + writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ +} + +static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) +{ + if (likely(!asus_hides_smbus || !asus_rcba_base)) + return; + iounmap(asus_rcba_base); + asus_rcba_base = NULL; dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); } + +static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) +{ + asus_hides_smbus_lpc_ich6_suspend(dev); + asus_hides_smbus_lpc_ich6_resume_early(dev); + asus_hides_smbus_lpc_ich6_resume(dev); +} DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); +DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); /* * SiS 96x south bridge: BIOS typically hides SMBus device... @@ -1135,10 +1165,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); /* * ... This is further complicated by the fact that some SiS96x south @@ -1172,7 +1202,7 @@ static void quirk_sis_503(struct pci_dev *dev) quirk_sis_96x_smbus(dev); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); /* @@ -1205,7 +1235,7 @@ static void asus_hides_ac97_lpc(struct pci_dev *dev) } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) @@ -1270,12 +1300,12 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, qui DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); #endif @@ -1521,6 +1551,10 @@ extern struct pci_fixup __start_pci_fixups_enable[]; extern struct pci_fixup __end_pci_fixups_enable[]; extern struct pci_fixup __start_pci_fixups_resume[]; extern struct pci_fixup __end_pci_fixups_resume[]; +extern struct pci_fixup __start_pci_fixups_resume_early[]; +extern struct pci_fixup __end_pci_fixups_resume_early[]; +extern struct pci_fixup __start_pci_fixups_suspend[]; +extern struct pci_fixup __end_pci_fixups_suspend[]; void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) @@ -1553,6 +1587,16 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) end = __end_pci_fixups_resume; break; + case pci_fixup_resume_early: + start = __start_pci_fixups_resume_early; + end = __end_pci_fixups_resume_early; + break; + + case pci_fixup_suspend: + start = __start_pci_fixups_suspend; + end = __end_pci_fixups_suspend; + break; + default: /* stupid compiler warning, you would think with an enum... */ return; @@ -1629,7 +1673,7 @@ static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, quirk_nvidia_ck804_pcie_aer_ext_cap); -DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, quirk_nvidia_ck804_pcie_aer_ext_cap); static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index f054778e916c..cf108a3c7f59 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -84,6 +84,12 @@ VMLINUX_SYMBOL(__start_pci_fixups_resume) = .; \ *(.pci_fixup_resume) \ VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume_early) = .; \ + *(.pci_fixup_resume_early) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \ + *(.pci_fixup_suspend) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \ } \ \ /* RapidIO route ops */ \ diff --git a/include/linux/pci.h b/include/linux/pci.h index aaa9f333fb44..700704ef70f3 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1013,7 +1013,9 @@ enum pci_fixup_pass { pci_fixup_header, /* After reading configuration header */ pci_fixup_final, /* Final phase of device fixups */ pci_fixup_enable, /* pci_enable_device() time */ - pci_fixup_resume, /* pci_enable_device() time */ + pci_fixup_resume, /* pci_device_resume() */ + pci_fixup_suspend, /* pci_device_suspend */ + pci_fixup_resume_early, /* pci_device_resume_early() */ }; /* Anonymous variables would be nice... */ @@ -1035,6 +1037,12 @@ enum pci_fixup_pass { #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ resume##vendor##device##hook, vendor, device, hook) +#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ + DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ + resume_early##vendor##device##hook, vendor, device, hook) +#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ + DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ + suspend##vendor##device##hook, vendor, device, hook) void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); -- cgit v1.2.3 From 1eede070a59e1cc73da51e1aaa00d9ab86572cfc Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Tue, 20 May 2008 23:00:01 +0200 Subject: Introduce new top level suspend and hibernation callbacks Introduce 'struct pm_ops' and 'struct pm_ext_ops' ('ext' meaning 'extended') representing suspend and hibernation operations for bus types, device classes, device types and device drivers. Modify the PM core to use 'struct pm_ops' and 'struct pm_ext_ops' objects, if defined, instead of the ->suspend(), ->resume(), ->suspend_late(), and ->resume_early() callbacks (the old callbacks will be considered as legacy and gradually phased out). The main purpose of doing this is to separate suspend (aka S2RAM and standby) callbacks from hibernation callbacks in such a way that the new callbacks won't take arguments and the semantics of each of them will be clearly specified. This has been requested for multiple times by many people, including Linus himself, and the reason is that within the current scheme if ->resume() is called, for example, it's difficult to say why it's been called (ie. is it a resume from RAM or from hibernation or a suspend/hibernation failure etc.?). The second purpose is to make the suspend/hibernation callbacks more flexible so that device drivers can handle more than they can within the current scheme. For example, some drivers may need to prevent new children of the device from being registered before their ->suspend() callbacks are executed or they may want to carry out some operations requiring the availability of some other devices, not directly bound via the parent-child relationship, in order to prepare for the execution of ->suspend(), etc. Ultimately, we'd like to stop using the freezing of tasks for suspend and therefore the drivers' suspend/hibernation code will have to take care of the handling of the user space during suspend/hibernation. That, in turn, would be difficult within the current scheme, without the new ->prepare() and ->complete() callbacks. Signed-off-by: Rafael J. Wysocki Acked-by: Pavel Machek Signed-off-by: Jesse Barnes --- arch/x86/kernel/apm_32.c | 8 +- drivers/base/power/main.c | 675 +++++++++++++++++++++++++++++++++++---------- drivers/base/power/power.h | 2 +- drivers/base/power/trace.c | 4 +- include/linux/device.h | 9 + include/linux/pm.h | 314 +++++++++++++++++++-- kernel/power/disk.c | 22 +- kernel/power/main.c | 6 +- 8 files changed, 845 insertions(+), 195 deletions(-) (limited to 'include') diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index bf9290e29013..c1735f61a2c0 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -1211,9 +1211,9 @@ static int suspend(int vetoable) if (err != APM_SUCCESS) apm_error("suspend", err); err = (err == APM_SUCCESS) ? 0 : -EIO; - device_power_up(); + device_power_up(PMSG_RESUME); local_irq_enable(); - device_resume(); + device_resume(PMSG_RESUME); queue_event(APM_NORMAL_RESUME, NULL); spin_lock(&user_list_lock); for (as = user_list; as != NULL; as = as->next) { @@ -1238,7 +1238,7 @@ static void standby(void) apm_error("standby", err); local_irq_disable(); - device_power_up(); + device_power_up(PMSG_RESUME); local_irq_enable(); } @@ -1324,7 +1324,7 @@ static void check_events(void) ignore_bounce = 1; if ((event != APM_NORMAL_RESUME) || (ignore_normal_resume == 0)) { - device_resume(); + device_resume(PMSG_RESUME); queue_event(event, NULL); } ignore_normal_resume = 0; diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c index 45cc3d9eacb8..d571204aaff7 100644 --- a/drivers/base/power/main.c +++ b/drivers/base/power/main.c @@ -12,11 +12,9 @@ * and add it to the list of power-controlled devices. sysfs entries for * controlling device power management will also be added. * - * A different set of lists than the global subsystem list are used to - * keep track of power info because we use different lists to hold - * devices based on what stage of the power management process they - * are in. The power domain dependencies may also differ from the - * ancestral dependencies that the subsystem list maintains. + * A separate list is used for keeping track of power info, because the power + * domain dependencies may differ from the ancestral dependencies that the + * subsystem list maintains. */ #include @@ -30,31 +28,40 @@ #include "power.h" /* - * The entries in the dpm_active list are in a depth first order, simply + * The entries in the dpm_list list are in a depth first order, simply * because children are guaranteed to be discovered after parents, and * are inserted at the back of the list on discovery. * - * All the other lists are kept in the same order, for consistency. - * However the lists aren't always traversed in the same order. - * Semaphores must be acquired from the top (i.e., front) down - * and released in the opposite order. Devices must be suspended - * from the bottom (i.e., end) up and resumed in the opposite order. - * That way no parent will be suspended while it still has an active - * child. - * * Since device_pm_add() may be called with a device semaphore held, * we must never try to acquire a device semaphore while holding * dpm_list_mutex. */ -LIST_HEAD(dpm_active); -static LIST_HEAD(dpm_off); -static LIST_HEAD(dpm_off_irq); +LIST_HEAD(dpm_list); static DEFINE_MUTEX(dpm_list_mtx); -/* 'true' if all devices have been suspended, protected by dpm_list_mtx */ -static bool all_sleeping; +/* + * Set once the preparation of devices for a PM transition has started, reset + * before starting to resume devices. Protected by dpm_list_mtx. + */ +static bool transition_started; + +/** + * device_pm_lock - lock the list of active devices used by the PM core + */ +void device_pm_lock(void) +{ + mutex_lock(&dpm_list_mtx); +} + +/** + * device_pm_unlock - unlock the list of active devices used by the PM core + */ +void device_pm_unlock(void) +{ + mutex_unlock(&dpm_list_mtx); +} /** * device_pm_add - add a device to the list of active devices @@ -68,17 +75,25 @@ int device_pm_add(struct device *dev) dev->bus ? dev->bus->name : "No Bus", kobject_name(&dev->kobj)); mutex_lock(&dpm_list_mtx); - if ((dev->parent && dev->parent->power.sleeping) || all_sleeping) { - if (dev->parent->power.sleeping) - dev_warn(dev, "parent %s is sleeping\n", + if (dev->parent) { + if (dev->parent->power.status >= DPM_SUSPENDING) { + dev_warn(dev, "parent %s is sleeping, will not add\n", dev->parent->bus_id); - else - dev_warn(dev, "all devices are sleeping\n"); + WARN_ON(true); + } + } else if (transition_started) { + /* + * We refuse to register parentless devices while a PM + * transition is in progress in order to avoid leaving them + * unhandled down the road + */ WARN_ON(true); } error = dpm_sysfs_add(dev); - if (!error) - list_add_tail(&dev->power.entry, &dpm_active); + if (!error) { + dev->power.status = DPM_ON; + list_add_tail(&dev->power.entry, &dpm_list); + } mutex_unlock(&dpm_list_mtx); return error; } @@ -100,73 +115,243 @@ void device_pm_remove(struct device *dev) mutex_unlock(&dpm_list_mtx); } +/** + * pm_op - execute the PM operation appropiate for given PM event + * @dev: Device. + * @ops: PM operations to choose from. + * @state: PM transition of the system being carried out. + */ +static int pm_op(struct device *dev, struct pm_ops *ops, pm_message_t state) +{ + int error = 0; + + switch (state.event) { +#ifdef CONFIG_SUSPEND + case PM_EVENT_SUSPEND: + if (ops->suspend) { + error = ops->suspend(dev); + suspend_report_result(ops->suspend, error); + } + break; + case PM_EVENT_RESUME: + if (ops->resume) { + error = ops->resume(dev); + suspend_report_result(ops->resume, error); + } + break; +#endif /* CONFIG_SUSPEND */ +#ifdef CONFIG_HIBERNATION + case PM_EVENT_FREEZE: + case PM_EVENT_QUIESCE: + if (ops->freeze) { + error = ops->freeze(dev); + suspend_report_result(ops->freeze, error); + } + break; + case PM_EVENT_HIBERNATE: + if (ops->poweroff) { + error = ops->poweroff(dev); + suspend_report_result(ops->poweroff, error); + } + break; + case PM_EVENT_THAW: + case PM_EVENT_RECOVER: + if (ops->thaw) { + error = ops->thaw(dev); + suspend_report_result(ops->thaw, error); + } + break; + case PM_EVENT_RESTORE: + if (ops->restore) { + error = ops->restore(dev); + suspend_report_result(ops->restore, error); + } + break; +#endif /* CONFIG_HIBERNATION */ + default: + error = -EINVAL; + } + return error; +} + +/** + * pm_noirq_op - execute the PM operation appropiate for given PM event + * @dev: Device. + * @ops: PM operations to choose from. + * @state: PM transition of the system being carried out. + * + * The operation is executed with interrupts disabled by the only remaining + * functional CPU in the system. + */ +static int pm_noirq_op(struct device *dev, struct pm_ext_ops *ops, + pm_message_t state) +{ + int error = 0; + + switch (state.event) { +#ifdef CONFIG_SUSPEND + case PM_EVENT_SUSPEND: + if (ops->suspend_noirq) { + error = ops->suspend_noirq(dev); + suspend_report_result(ops->suspend_noirq, error); + } + break; + case PM_EVENT_RESUME: + if (ops->resume_noirq) { + error = ops->resume_noirq(dev); + suspend_report_result(ops->resume_noirq, error); + } + break; +#endif /* CONFIG_SUSPEND */ +#ifdef CONFIG_HIBERNATION + case PM_EVENT_FREEZE: + case PM_EVENT_QUIESCE: + if (ops->freeze_noirq) { + error = ops->freeze_noirq(dev); + suspend_report_result(ops->freeze_noirq, error); + } + break; + case PM_EVENT_HIBERNATE: + if (ops->poweroff_noirq) { + error = ops->poweroff_noirq(dev); + suspend_report_result(ops->poweroff_noirq, error); + } + break; + case PM_EVENT_THAW: + case PM_EVENT_RECOVER: + if (ops->thaw_noirq) { + error = ops->thaw_noirq(dev); + suspend_report_result(ops->thaw_noirq, error); + } + break; + case PM_EVENT_RESTORE: + if (ops->restore_noirq) { + error = ops->restore_noirq(dev); + suspend_report_result(ops->restore_noirq, error); + } + break; +#endif /* CONFIG_HIBERNATION */ + default: + error = -EINVAL; + } + return error; +} + +static char *pm_verb(int event) +{ + switch (event) { + case PM_EVENT_SUSPEND: + return "suspend"; + case PM_EVENT_RESUME: + return "resume"; + case PM_EVENT_FREEZE: + return "freeze"; + case PM_EVENT_QUIESCE: + return "quiesce"; + case PM_EVENT_HIBERNATE: + return "hibernate"; + case PM_EVENT_THAW: + return "thaw"; + case PM_EVENT_RESTORE: + return "restore"; + case PM_EVENT_RECOVER: + return "recover"; + default: + return "(unknown PM event)"; + } +} + +static void pm_dev_dbg(struct device *dev, pm_message_t state, char *info) +{ + dev_dbg(dev, "%s%s%s\n", info, pm_verb(state.event), + ((state.event & PM_EVENT_SLEEP) && device_may_wakeup(dev)) ? + ", may wakeup" : ""); +} + +static void pm_dev_err(struct device *dev, pm_message_t state, char *info, + int error) +{ + printk(KERN_ERR "PM: Device %s failed to %s%s: error %d\n", + kobject_name(&dev->kobj), pm_verb(state.event), info, error); +} + /*------------------------- Resume routines -------------------------*/ /** - * resume_device_early - Power on one device (early resume). + * resume_device_noirq - Power on one device (early resume). * @dev: Device. + * @state: PM transition of the system being carried out. * * Must be called with interrupts disabled. */ -static int resume_device_early(struct device *dev) +static int resume_device_noirq(struct device *dev, pm_message_t state) { int error = 0; TRACE_DEVICE(dev); TRACE_RESUME(0); - if (dev->bus && dev->bus->resume_early) { - dev_dbg(dev, "EARLY resume\n"); + if (!dev->bus) + goto End; + + if (dev->bus->pm) { + pm_dev_dbg(dev, state, "EARLY "); + error = pm_noirq_op(dev, dev->bus->pm, state); + } else if (dev->bus->resume_early) { + pm_dev_dbg(dev, state, "legacy EARLY "); error = dev->bus->resume_early(dev); } - + End: TRACE_RESUME(error); return error; } /** * dpm_power_up - Power on all regular (non-sysdev) devices. + * @state: PM transition of the system being carried out. * - * Walk the dpm_off_irq list and power each device up. This - * is used for devices that required they be powered down with - * interrupts disabled. As devices are powered on, they are moved - * to the dpm_off list. + * Execute the appropriate "noirq resume" callback for all devices marked + * as DPM_OFF_IRQ. * * Must be called with interrupts disabled and only one CPU running. */ -static void dpm_power_up(void) +static void dpm_power_up(pm_message_t state) { + struct device *dev; - while (!list_empty(&dpm_off_irq)) { - struct list_head *entry = dpm_off_irq.next; - struct device *dev = to_device(entry); + list_for_each_entry(dev, &dpm_list, power.entry) + if (dev->power.status > DPM_OFF) { + int error; - list_move_tail(entry, &dpm_off); - resume_device_early(dev); - } + dev->power.status = DPM_OFF; + error = resume_device_noirq(dev, state); + if (error) + pm_dev_err(dev, state, " early", error); + } } /** * device_power_up - Turn on all devices that need special attention. + * @state: PM transition of the system being carried out. * * Power on system devices, then devices that required we shut them down * with interrupts disabled. * * Must be called with interrupts disabled. */ -void device_power_up(void) +void device_power_up(pm_message_t state) { sysdev_resume(); - dpm_power_up(); + dpm_power_up(state); } EXPORT_SYMBOL_GPL(device_power_up); /** * resume_device - Restore state for one device. * @dev: Device. - * + * @state: PM transition of the system being carried out. */ -static int resume_device(struct device *dev) +static int resume_device(struct device *dev, pm_message_t state) { int error = 0; @@ -175,21 +360,40 @@ static int resume_device(struct device *dev) down(&dev->sem); - if (dev->bus && dev->bus->resume) { - dev_dbg(dev,"resuming\n"); - error = dev->bus->resume(dev); + if (dev->bus) { + if (dev->bus->pm) { + pm_dev_dbg(dev, state, ""); + error = pm_op(dev, &dev->bus->pm->base, state); + } else if (dev->bus->resume) { + pm_dev_dbg(dev, state, "legacy "); + error = dev->bus->resume(dev); + } + if (error) + goto End; } - if (!error && dev->type && dev->type->resume) { - dev_dbg(dev,"resuming\n"); - error = dev->type->resume(dev); + if (dev->type) { + if (dev->type->pm) { + pm_dev_dbg(dev, state, "type "); + error = pm_op(dev, dev->type->pm, state); + } else if (dev->type->resume) { + pm_dev_dbg(dev, state, "legacy type "); + error = dev->type->resume(dev); + } + if (error) + goto End; } - if (!error && dev->class && dev->class->resume) { - dev_dbg(dev,"class resume\n"); - error = dev->class->resume(dev); + if (dev->class) { + if (dev->class->pm) { + pm_dev_dbg(dev, state, "class "); + error = pm_op(dev, dev->class->pm, state); + } else if (dev->class->resume) { + pm_dev_dbg(dev, state, "legacy class "); + error = dev->class->resume(dev); + } } - + End: up(&dev->sem); TRACE_RESUME(error); @@ -198,78 +402,161 @@ static int resume_device(struct device *dev) /** * dpm_resume - Resume every device. + * @state: PM transition of the system being carried out. * - * Resume the devices that have either not gone through - * the late suspend, or that did go through it but also - * went through the early resume. + * Execute the appropriate "resume" callback for all devices the status of + * which indicates that they are inactive. + */ +static void dpm_resume(pm_message_t state) +{ + struct list_head list; + + INIT_LIST_HEAD(&list); + mutex_lock(&dpm_list_mtx); + transition_started = false; + while (!list_empty(&dpm_list)) { + struct device *dev = to_device(dpm_list.next); + + get_device(dev); + if (dev->power.status >= DPM_OFF) { + int error; + + dev->power.status = DPM_RESUMING; + mutex_unlock(&dpm_list_mtx); + + error = resume_device(dev, state); + + mutex_lock(&dpm_list_mtx); + if (error) + pm_dev_err(dev, state, "", error); + } else if (dev->power.status == DPM_SUSPENDING) { + /* Allow new children of the device to be registered */ + dev->power.status = DPM_RESUMING; + } + if (!list_empty(&dev->power.entry)) + list_move_tail(&dev->power.entry, &list); + put_device(dev); + } + list_splice(&list, &dpm_list); + mutex_unlock(&dpm_list_mtx); +} + +/** + * complete_device - Complete a PM transition for given device + * @dev: Device. + * @state: PM transition of the system being carried out. + */ +static void complete_device(struct device *dev, pm_message_t state) +{ + down(&dev->sem); + + if (dev->class && dev->class->pm && dev->class->pm->complete) { + pm_dev_dbg(dev, state, "completing class "); + dev->class->pm->complete(dev); + } + + if (dev->type && dev->type->pm && dev->type->pm->complete) { + pm_dev_dbg(dev, state, "completing type "); + dev->type->pm->complete(dev); + } + + if (dev->bus && dev->bus->pm && dev->bus->pm->base.complete) { + pm_dev_dbg(dev, state, "completing "); + dev->bus->pm->base.complete(dev); + } + + up(&dev->sem); +} + +/** + * dpm_complete - Complete a PM transition for all devices. + * @state: PM transition of the system being carried out. * - * Take devices from the dpm_off_list, resume them, - * and put them on the dpm_locked list. + * Execute the ->complete() callbacks for all devices that are not marked + * as DPM_ON. */ -static void dpm_resume(void) +static void dpm_complete(pm_message_t state) { + struct list_head list; + + INIT_LIST_HEAD(&list); mutex_lock(&dpm_list_mtx); - all_sleeping = false; - while(!list_empty(&dpm_off)) { - struct list_head *entry = dpm_off.next; - struct device *dev = to_device(entry); + while (!list_empty(&dpm_list)) { + struct device *dev = to_device(dpm_list.prev); - list_move_tail(entry, &dpm_active); - dev->power.sleeping = false; - mutex_unlock(&dpm_list_mtx); - resume_device(dev); - mutex_lock(&dpm_list_mtx); + get_device(dev); + if (dev->power.status > DPM_ON) { + dev->power.status = DPM_ON; + mutex_unlock(&dpm_list_mtx); + + complete_device(dev, state); + + mutex_lock(&dpm_list_mtx); + } + if (!list_empty(&dev->power.entry)) + list_move(&dev->power.entry, &list); + put_device(dev); } + list_splice(&list, &dpm_list); mutex_unlock(&dpm_list_mtx); } /** * device_resume - Restore state of each device in system. + * @state: PM transition of the system being carried out. * * Resume all the devices, unlock them all, and allow new * devices to be registered once again. */ -void device_resume(void) +void device_resume(pm_message_t state) { might_sleep(); - dpm_resume(); + dpm_resume(state); + dpm_complete(state); } EXPORT_SYMBOL_GPL(device_resume); /*------------------------- Suspend routines -------------------------*/ -static inline char *suspend_verb(u32 event) +/** + * resume_event - return a PM message representing the resume event + * corresponding to given sleep state. + * @sleep_state: PM message representing a sleep state. + */ +static pm_message_t resume_event(pm_message_t sleep_state) { - switch (event) { - case PM_EVENT_SUSPEND: return "suspend"; - case PM_EVENT_FREEZE: return "freeze"; - case PM_EVENT_PRETHAW: return "prethaw"; - default: return "(unknown suspend event)"; + switch (sleep_state.event) { + case PM_EVENT_SUSPEND: + return PMSG_RESUME; + case PM_EVENT_FREEZE: + case PM_EVENT_QUIESCE: + return PMSG_RECOVER; + case PM_EVENT_HIBERNATE: + return PMSG_RESTORE; } -} - -static void -suspend_device_dbg(struct device *dev, pm_message_t state, char *info) -{ - dev_dbg(dev, "%s%s%s\n", info, suspend_verb(state.event), - ((state.event == PM_EVENT_SUSPEND) && device_may_wakeup(dev)) ? - ", may wakeup" : ""); + return PMSG_ON; } /** - * suspend_device_late - Shut down one device (late suspend). + * suspend_device_noirq - Shut down one device (late suspend). * @dev: Device. - * @state: Power state device is entering. + * @state: PM transition of the system being carried out. * * This is called with interrupts off and only a single CPU running. */ -static int suspend_device_late(struct device *dev, pm_message_t state) +static int suspend_device_noirq(struct device *dev, pm_message_t state) { int error = 0; - if (dev->bus && dev->bus->suspend_late) { - suspend_device_dbg(dev, state, "LATE "); + if (!dev->bus) + return 0; + + if (dev->bus->pm) { + pm_dev_dbg(dev, state, "LATE "); + error = pm_noirq_op(dev, dev->bus->pm, state); + } else if (dev->bus->suspend_late) { + pm_dev_dbg(dev, state, "legacy LATE "); error = dev->bus->suspend_late(dev, state); suspend_report_result(dev->bus->suspend_late, error); } @@ -278,37 +565,30 @@ static int suspend_device_late(struct device *dev, pm_message_t state) /** * device_power_down - Shut down special devices. - * @state: Power state to enter. + * @state: PM transition of the system being carried out. * - * Power down devices that require interrupts to be disabled - * and move them from the dpm_off list to the dpm_off_irq list. + * Power down devices that require interrupts to be disabled. * Then power down system devices. * * Must be called with interrupts disabled and only one CPU running. */ int device_power_down(pm_message_t state) { + struct device *dev; int error = 0; - while (!list_empty(&dpm_off)) { - struct list_head *entry = dpm_off.prev; - struct device *dev = to_device(entry); - - error = suspend_device_late(dev, state); + list_for_each_entry_reverse(dev, &dpm_list, power.entry) { + error = suspend_device_noirq(dev, state); if (error) { - printk(KERN_ERR "Could not power down device %s: " - "error %d\n", - kobject_name(&dev->kobj), error); + pm_dev_err(dev, state, " late", error); break; } - if (!list_empty(&dev->power.entry)) - list_move(&dev->power.entry, &dpm_off_irq); + dev->power.status = DPM_OFF_IRQ; } - if (!error) error = sysdev_suspend(state); if (error) - dpm_power_up(); + dpm_power_up(resume_event(state)); return error; } EXPORT_SYMBOL_GPL(device_power_down); @@ -316,7 +596,7 @@ EXPORT_SYMBOL_GPL(device_power_down); /** * suspend_device - Save state of one device. * @dev: Device. - * @state: Power state device is entering. + * @state: PM transition of the system being carried out. */ static int suspend_device(struct device *dev, pm_message_t state) { @@ -324,24 +604,43 @@ static int suspend_device(struct device *dev, pm_message_t state) down(&dev->sem); - if (dev->class && dev->class->suspend) { - suspend_device_dbg(dev, state, "class "); - error = dev->class->suspend(dev, state); - suspend_report_result(dev->class->suspend, error); + if (dev->class) { + if (dev->class->pm) { + pm_dev_dbg(dev, state, "class "); + error = pm_op(dev, dev->class->pm, state); + } else if (dev->class->suspend) { + pm_dev_dbg(dev, state, "legacy class "); + error = dev->class->suspend(dev, state); + suspend_report_result(dev->class->suspend, error); + } + if (error) + goto End; } - if (!error && dev->type && dev->type->suspend) { - suspend_device_dbg(dev, state, "type "); - error = dev->type->suspend(dev, state); - suspend_report_result(dev->type->suspend, error); + if (dev->type) { + if (dev->type->pm) { + pm_dev_dbg(dev, state, "type "); + error = pm_op(dev, dev->type->pm, state); + } else if (dev->type->suspend) { + pm_dev_dbg(dev, state, "legacy type "); + error = dev->type->suspend(dev, state); + suspend_report_result(dev->type->suspend, error); + } + if (error) + goto End; } - if (!error && dev->bus && dev->bus->suspend) { - suspend_device_dbg(dev, state, ""); - error = dev->bus->suspend(dev, state); - suspend_report_result(dev->bus->suspend, error); + if (dev->bus) { + if (dev->bus->pm) { + pm_dev_dbg(dev, state, ""); + error = pm_op(dev, &dev->bus->pm->base, state); + } else if (dev->bus->suspend) { + pm_dev_dbg(dev, state, "legacy "); + error = dev->bus->suspend(dev, state); + suspend_report_result(dev->bus->suspend, error); + } } - + End: up(&dev->sem); return error; @@ -349,67 +648,141 @@ static int suspend_device(struct device *dev, pm_message_t state) /** * dpm_suspend - Suspend every device. - * @state: Power state to put each device in. + * @state: PM transition of the system being carried out. * - * Walk the dpm_locked list. Suspend each device and move it - * to the dpm_off list. - * - * (For historical reasons, if it returns -EAGAIN, that used to mean - * that the device would be called again with interrupts disabled. - * These days, we use the "suspend_late()" callback for that, so we - * print a warning and consider it an error). + * Execute the appropriate "suspend" callbacks for all devices. */ static int dpm_suspend(pm_message_t state) { + struct list_head list; int error = 0; + INIT_LIST_HEAD(&list); mutex_lock(&dpm_list_mtx); - while (!list_empty(&dpm_active)) { - struct list_head *entry = dpm_active.prev; - struct device *dev = to_device(entry); - - WARN_ON(dev->parent && dev->parent->power.sleeping); + while (!list_empty(&dpm_list)) { + struct device *dev = to_device(dpm_list.prev); - dev->power.sleeping = true; + get_device(dev); mutex_unlock(&dpm_list_mtx); + error = suspend_device(dev, state); + mutex_lock(&dpm_list_mtx); if (error) { - printk(KERN_ERR "Could not suspend device %s: " - "error %d%s\n", - kobject_name(&dev->kobj), - error, - (error == -EAGAIN ? - " (please convert to suspend_late)" : - "")); - dev->power.sleeping = false; + pm_dev_err(dev, state, "", error); + put_device(dev); break; } + dev->power.status = DPM_OFF; if (!list_empty(&dev->power.entry)) - list_move(&dev->power.entry, &dpm_off); + list_move(&dev->power.entry, &list); + put_device(dev); } - if (!error) - all_sleeping = true; + list_splice(&list, dpm_list.prev); mutex_unlock(&dpm_list_mtx); + return error; +} + +/** + * prepare_device - Execute the ->prepare() callback(s) for given device. + * @dev: Device. + * @state: PM transition of the system being carried out. + */ +static int prepare_device(struct device *dev, pm_message_t state) +{ + int error = 0; + + down(&dev->sem); + + if (dev->bus && dev->bus->pm && dev->bus->pm->base.prepare) { + pm_dev_dbg(dev, state, "preparing "); + error = dev->bus->pm->base.prepare(dev); + suspend_report_result(dev->bus->pm->base.prepare, error); + if (error) + goto End; + } + + if (dev->type && dev->type->pm && dev->type->pm->prepare) { + pm_dev_dbg(dev, state, "preparing type "); + error = dev->type->pm->prepare(dev); + suspend_report_result(dev->type->pm->prepare, error); + if (error) + goto End; + } + + if (dev->class && dev->class->pm && dev->class->pm->prepare) { + pm_dev_dbg(dev, state, "preparing class "); + error = dev->class->pm->prepare(dev); + suspend_report_result(dev->class->pm->prepare, error); + } + End: + up(&dev->sem); + + return error; +} +/** + * dpm_prepare - Prepare all devices for a PM transition. + * @state: PM transition of the system being carried out. + * + * Execute the ->prepare() callback for all devices. + */ +static int dpm_prepare(pm_message_t state) +{ + struct list_head list; + int error = 0; + + INIT_LIST_HEAD(&list); + mutex_lock(&dpm_list_mtx); + transition_started = true; + while (!list_empty(&dpm_list)) { + struct device *dev = to_device(dpm_list.next); + + get_device(dev); + dev->power.status = DPM_PREPARING; + mutex_unlock(&dpm_list_mtx); + + error = prepare_device(dev, state); + + mutex_lock(&dpm_list_mtx); + if (error) { + dev->power.status = DPM_ON; + if (error == -EAGAIN) { + put_device(dev); + continue; + } + printk(KERN_ERR "PM: Failed to prepare device %s " + "for power transition: error %d\n", + kobject_name(&dev->kobj), error); + put_device(dev); + break; + } + dev->power.status = DPM_SUSPENDING; + if (!list_empty(&dev->power.entry)) + list_move_tail(&dev->power.entry, &list); + put_device(dev); + } + list_splice(&list, &dpm_list); + mutex_unlock(&dpm_list_mtx); return error; } /** * device_suspend - Save state and stop all devices in system. - * @state: new power management state + * @state: PM transition of the system being carried out. * - * Prevent new devices from being registered, then lock all devices - * and suspend them. + * Prepare and suspend all devices. */ int device_suspend(pm_message_t state) { int error; might_sleep(); - error = dpm_suspend(state); + error = dpm_prepare(state); + if (!error) + error = dpm_suspend(state); if (error) - device_resume(); + device_resume(resume_event(state)); return error; } EXPORT_SYMBOL_GPL(device_suspend); diff --git a/drivers/base/power/power.h b/drivers/base/power/power.h index a6894f2a4b99..a3252c0e2887 100644 --- a/drivers/base/power/power.h +++ b/drivers/base/power/power.h @@ -4,7 +4,7 @@ * main.c */ -extern struct list_head dpm_active; /* The active device list */ +extern struct list_head dpm_list; /* The active device list */ static inline struct device *to_device(struct list_head *entry) { diff --git a/drivers/base/power/trace.c b/drivers/base/power/trace.c index 2b4b392dcbc1..8c1e656b5f8b 100644 --- a/drivers/base/power/trace.c +++ b/drivers/base/power/trace.c @@ -188,9 +188,9 @@ static int show_file_hash(unsigned int value) static int show_dev_hash(unsigned int value) { int match = 0; - struct list_head * entry = dpm_active.prev; + struct list_head *entry = dpm_list.prev; - while (entry != &dpm_active) { + while (entry != &dpm_list) { struct device * dev = to_device(entry); unsigned int hash = hash_string(DEVSEED, dev->bus_id, DEVHASH); if (hash == value) { diff --git a/include/linux/device.h b/include/linux/device.h index 6a2d04c011bc..f71a78d123ae 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -68,6 +68,8 @@ struct bus_type { int (*resume_early)(struct device *dev); int (*resume)(struct device *dev); + struct pm_ext_ops *pm; + struct bus_type_private *p; }; @@ -131,6 +133,8 @@ struct device_driver { int (*resume) (struct device *dev); struct attribute_group **groups; + struct pm_ops *pm; + struct driver_private *p; }; @@ -197,6 +201,8 @@ struct class { int (*suspend)(struct device *dev, pm_message_t state); int (*resume)(struct device *dev); + + struct pm_ops *pm; }; extern int __must_check class_register(struct class *class); @@ -248,8 +254,11 @@ struct device_type { struct attribute_group **groups; int (*uevent)(struct device *dev, struct kobj_uevent_env *env); void (*release)(struct device *dev); + int (*suspend)(struct device *dev, pm_message_t state); int (*resume)(struct device *dev); + + struct pm_ops *pm; }; /* interface for exporting device attributes */ diff --git a/include/linux/pm.h b/include/linux/pm.h index 39a7ee859b67..4ad9de94449a 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -112,7 +112,9 @@ typedef struct pm_message { int event; } pm_message_t; -/* +/** + * struct pm_ops - device PM callbacks + * * Several driver power state transitions are externally visible, affecting * the state of pending I/O queues and (for drivers that touch hardware) * interrupts, wakeups, DMA, and other hardware state. There may also be @@ -120,6 +122,284 @@ typedef struct pm_message { * to the rest of the driver stack (such as a driver that's ON gating off * clocks which are not in active use). * + * The externally visible transitions are handled with the help of the following + * callbacks included in this structure: + * + * @prepare: Prepare the device for the upcoming transition, but do NOT change + * its hardware state. Prevent new children of the device from being + * registered after @prepare() returns (the driver's subsystem and + * generally the rest of the kernel is supposed to prevent new calls to the + * probe method from being made too once @prepare() has succeeded). If + * @prepare() detects a situation it cannot handle (e.g. registration of a + * child already in progress), it may return -EAGAIN, so that the PM core + * can execute it once again (e.g. after the new child has been registered) + * to recover from the race condition. This method is executed for all + * kinds of suspend transitions and is followed by one of the suspend + * callbacks: @suspend(), @freeze(), or @poweroff(). + * The PM core executes @prepare() for all devices before starting to + * execute suspend callbacks for any of them, so drivers may assume all of + * the other devices to be present and functional while @prepare() is being + * executed. In particular, it is safe to make GFP_KERNEL memory + * allocations from within @prepare(). However, drivers may NOT assume + * anything about the availability of the user space at that time and it + * is not correct to request firmware from within @prepare() (it's too + * late to do that). [To work around this limitation, drivers may + * register suspend and hibernation notifiers that are executed before the + * freezing of tasks.] + * + * @complete: Undo the changes made by @prepare(). This method is executed for + * all kinds of resume transitions, following one of the resume callbacks: + * @resume(), @thaw(), @restore(). Also called if the state transition + * fails before the driver's suspend callback (@suspend(), @freeze(), + * @poweroff()) can be executed (e.g. if the suspend callback fails for one + * of the other devices that the PM core has unsuccessfully attempted to + * suspend earlier). + * The PM core executes @complete() after it has executed the appropriate + * resume callback for all devices. + * + * @suspend: Executed before putting the system into a sleep state in which the + * contents of main memory are preserved. Quiesce the device, put it into + * a low power state appropriate for the upcoming system state (such as + * PCI_D3hot), and enable wakeup events as appropriate. + * + * @resume: Executed after waking the system up from a sleep state in which the + * contents of main memory were preserved. Put the device into the + * appropriate state, according to the information saved in memory by the + * preceding @suspend(). The driver starts working again, responding to + * hardware events and software requests. The hardware may have gone + * through a power-off reset, or it may have maintained state from the + * previous suspend() which the driver may rely on while resuming. On most + * platforms, there are no restrictions on availability of resources like + * clocks during @resume(). + * + * @freeze: Hibernation-specific, executed before creating a hibernation image. + * Quiesce operations so that a consistent image can be created, but do NOT + * otherwise put the device into a low power device state and do NOT emit + * system wakeup events. Save in main memory the device settings to be + * used by @restore() during the subsequent resume from hibernation or by + * the subsequent @thaw(), if the creation of the image or the restoration + * of main memory contents from it fails. + * + * @thaw: Hibernation-specific, executed after creating a hibernation image OR + * if the creation of the image fails. Also executed after a failing + * attempt to restore the contents of main memory from such an image. + * Undo the changes made by the preceding @freeze(), so the device can be + * operated in the same way as immediately before the call to @freeze(). + * + * @poweroff: Hibernation-specific, executed after saving a hibernation image. + * Quiesce the device, put it into a low power state appropriate for the + * upcoming system state (such as PCI_D3hot), and enable wakeup events as + * appropriate. + * + * @restore: Hibernation-specific, executed after restoring the contents of main + * memory from a hibernation image. Driver starts working again, + * responding to hardware events and software requests. Drivers may NOT + * make ANY assumptions about the hardware state right prior to @restore(). + * On most platforms, there are no restrictions on availability of + * resources like clocks during @restore(). + * + * All of the above callbacks, except for @complete(), return error codes. + * However, the error codes returned by the resume operations, @resume(), + * @thaw(), and @restore(), do not cause the PM core to abort the resume + * transition during which they are returned. The error codes returned in + * that cases are only printed by the PM core to the system logs for debugging + * purposes. Still, it is recommended that drivers only return error codes + * from their resume methods in case of an unrecoverable failure (i.e. when the + * device being handled refuses to resume and becomes unusable) to allow us to + * modify the PM core in the future, so that it can avoid attempting to handle + * devices that failed to resume and their children. + * + * It is allowed to unregister devices while the above callbacks are being + * executed. However, it is not allowed to unregister a device from within any + * of its own callbacks. + */ + +struct pm_ops { + int (*prepare)(struct device *dev); + void (*complete)(struct device *dev); + int (*suspend)(struct device *dev); + int (*resume)(struct device *dev); + int (*freeze)(struct device *dev); + int (*thaw)(struct device *dev); + int (*poweroff)(struct device *dev); + int (*restore)(struct device *dev); +}; + +/** + * struct pm_ext_ops - extended device PM callbacks + * + * Some devices require certain operations related to suspend and hibernation + * to be carried out with interrupts disabled. Thus, 'struct pm_ext_ops' below + * is defined, adding callbacks to be executed with interrupts disabled to + * 'struct pm_ops'. + * + * The following callbacks included in 'struct pm_ext_ops' are executed with + * the nonboot CPUs switched off and with interrupts disabled on the only + * functional CPU. They also are executed with the PM core list of devices + * locked, so they must NOT unregister any devices. + * + * @suspend_noirq: Complete the operations of ->suspend() by carrying out any + * actions required for suspending the device that need interrupts to be + * disabled + * + * @resume_noirq: Prepare for the execution of ->resume() by carrying out any + * actions required for resuming the device that need interrupts to be + * disabled + * + * @freeze_noirq: Complete the operations of ->freeze() by carrying out any + * actions required for freezing the device that need interrupts to be + * disabled + * + * @thaw_noirq: Prepare for the execution of ->thaw() by carrying out any + * actions required for thawing the device that need interrupts to be + * disabled + * + * @poweroff_noirq: Complete the operations of ->poweroff() by carrying out any + * actions required for handling the device that need interrupts to be + * disabled + * + * @restore_noirq: Prepare for the execution of ->restore() by carrying out any + * actions required for restoring the operations of the device that need + * interrupts to be disabled + * + * All of the above callbacks return error codes, but the error codes returned + * by the resume operations, @resume_noirq(), @thaw_noirq(), and + * @restore_noirq(), do not cause the PM core to abort the resume transition + * during which they are returned. The error codes returned in that cases are + * only printed by the PM core to the system logs for debugging purposes. + * Still, as stated above, it is recommended that drivers only return error + * codes from their resume methods if the device being handled fails to resume + * and is not usable any more. + */ + +struct pm_ext_ops { + struct pm_ops base; + int (*suspend_noirq)(struct device *dev); + int (*resume_noirq)(struct device *dev); + int (*freeze_noirq)(struct device *dev); + int (*thaw_noirq)(struct device *dev); + int (*poweroff_noirq)(struct device *dev); + int (*restore_noirq)(struct device *dev); +}; + +/** + * PM_EVENT_ messages + * + * The following PM_EVENT_ messages are defined for the internal use of the PM + * core, in order to provide a mechanism allowing the high level suspend and + * hibernation code to convey the necessary information to the device PM core + * code: + * + * ON No transition. + * + * FREEZE System is going to hibernate, call ->prepare() and ->freeze() + * for all devices. + * + * SUSPEND System is going to suspend, call ->prepare() and ->suspend() + * for all devices. + * + * HIBERNATE Hibernation image has been saved, call ->prepare() and + * ->poweroff() for all devices. + * + * QUIESCE Contents of main memory are going to be restored from a (loaded) + * hibernation image, call ->prepare() and ->freeze() for all + * devices. + * + * RESUME System is resuming, call ->resume() and ->complete() for all + * devices. + * + * THAW Hibernation image has been created, call ->thaw() and + * ->complete() for all devices. + * + * RESTORE Contents of main memory have been restored from a hibernation + * image, call ->restore() and ->complete() for all devices. + * + * RECOVER Creation of a hibernation image or restoration of the main + * memory contents from a hibernation image has failed, call + * ->thaw() and ->complete() for all devices. + */ + +#define PM_EVENT_ON 0x0000 +#define PM_EVENT_FREEZE 0x0001 +#define PM_EVENT_SUSPEND 0x0002 +#define PM_EVENT_HIBERNATE 0x0004 +#define PM_EVENT_QUIESCE 0x0008 +#define PM_EVENT_RESUME 0x0010 +#define PM_EVENT_THAW 0x0020 +#define PM_EVENT_RESTORE 0x0040 +#define PM_EVENT_RECOVER 0x0080 + +#define PM_EVENT_SLEEP (PM_EVENT_SUSPEND | PM_EVENT_HIBERNATE) + +#define PMSG_FREEZE ((struct pm_message){ .event = PM_EVENT_FREEZE, }) +#define PMSG_QUIESCE ((struct pm_message){ .event = PM_EVENT_QUIESCE, }) +#define PMSG_SUSPEND ((struct pm_message){ .event = PM_EVENT_SUSPEND, }) +#define PMSG_HIBERNATE ((struct pm_message){ .event = PM_EVENT_HIBERNATE, }) +#define PMSG_RESUME ((struct pm_message){ .event = PM_EVENT_RESUME, }) +#define PMSG_THAW ((struct pm_message){ .event = PM_EVENT_THAW, }) +#define PMSG_RESTORE ((struct pm_message){ .event = PM_EVENT_RESTORE, }) +#define PMSG_RECOVER ((struct pm_message){ .event = PM_EVENT_RECOVER, }) +#define PMSG_ON ((struct pm_message){ .event = PM_EVENT_ON, }) + +/** + * Device power management states + * + * These state labels are used internally by the PM core to indicate the current + * status of a device with respect to the PM core operations. + * + * DPM_ON Device is regarded as operational. Set this way + * initially and when ->complete() is about to be called. + * Also set when ->prepare() fails. + * + * DPM_PREPARING Device is going to be prepared for a PM transition. Set + * when ->prepare() is about to be called. + * + * DPM_RESUMING Device is going to be resumed. Set when ->resume(), + * ->thaw(), or ->restore() is about to be called. + * + * DPM_SUSPENDING Device has been prepared for a power transition. Set + * when ->prepare() has just succeeded. + * + * DPM_OFF Device is regarded as inactive. Set immediately after + * ->suspend(), ->freeze(), or ->poweroff() has succeeded. + * Also set when ->resume()_noirq, ->thaw_noirq(), or + * ->restore_noirq() is about to be called. + * + * DPM_OFF_IRQ Device is in a "deep sleep". Set immediately after + * ->suspend_noirq(), ->freeze_noirq(), or + * ->poweroff_noirq() has just succeeded. + */ + +enum dpm_state { + DPM_INVALID, + DPM_ON, + DPM_PREPARING, + DPM_RESUMING, + DPM_SUSPENDING, + DPM_OFF, + DPM_OFF_IRQ, +}; + +struct dev_pm_info { + pm_message_t power_state; + unsigned can_wakeup:1; + unsigned should_wakeup:1; + enum dpm_state status; /* Owned by the PM core */ +#ifdef CONFIG_PM_SLEEP + struct list_head entry; +#endif +}; + +/* + * The PM_EVENT_ messages are also used by drivers implementing the legacy + * suspend framework, based on the ->suspend() and ->resume() callbacks common + * for suspend and hibernation transitions, according to the rules below. + */ + +/* Necessary, because several drivers use PM_EVENT_PRETHAW */ +#define PM_EVENT_PRETHAW PM_EVENT_QUIESCE + +/* * One transition is triggered by resume(), after a suspend() call; the * message is implicit: * @@ -164,35 +444,13 @@ typedef struct pm_message { * or from system low-power states such as standby or suspend-to-RAM. */ -#define PM_EVENT_ON 0 -#define PM_EVENT_FREEZE 1 -#define PM_EVENT_SUSPEND 2 -#define PM_EVENT_HIBERNATE 4 -#define PM_EVENT_PRETHAW 8 - -#define PM_EVENT_SLEEP (PM_EVENT_SUSPEND | PM_EVENT_HIBERNATE) - -#define PMSG_FREEZE ((struct pm_message){ .event = PM_EVENT_FREEZE, }) -#define PMSG_PRETHAW ((struct pm_message){ .event = PM_EVENT_PRETHAW, }) -#define PMSG_SUSPEND ((struct pm_message){ .event = PM_EVENT_SUSPEND, }) -#define PMSG_HIBERNATE ((struct pm_message){ .event = PM_EVENT_HIBERNATE, }) -#define PMSG_ON ((struct pm_message){ .event = PM_EVENT_ON, }) - -struct dev_pm_info { - pm_message_t power_state; - unsigned can_wakeup:1; - unsigned should_wakeup:1; - bool sleeping:1; /* Owned by the PM core */ -#ifdef CONFIG_PM_SLEEP - struct list_head entry; -#endif -}; +#ifdef CONFIG_PM_SLEEP +extern void device_pm_lock(void); +extern void device_power_up(pm_message_t state); +extern void device_resume(pm_message_t state); +extern void device_pm_unlock(void); extern int device_power_down(pm_message_t state); -extern void device_power_up(void); -extern void device_resume(void); - -#ifdef CONFIG_PM_SLEEP extern int device_suspend(pm_message_t state); extern int device_prepare_suspend(pm_message_t state); diff --git a/kernel/power/disk.c b/kernel/power/disk.c index 14a656cdc652..d416be0efa8a 100644 --- a/kernel/power/disk.c +++ b/kernel/power/disk.c @@ -193,6 +193,7 @@ static int create_image(int platform_mode) if (error) return error; + device_pm_lock(); local_irq_disable(); /* At this point, device_suspend() has been called, but *not* * device_power_down(). We *must* call device_power_down() now. @@ -224,9 +225,11 @@ static int create_image(int platform_mode) /* NOTE: device_power_up() is just a resume() for devices * that suspended with irqs off ... no overall powerup. */ - device_power_up(); + device_power_up(in_suspend ? + (error ? PMSG_RECOVER : PMSG_THAW) : PMSG_RESTORE); Enable_irqs: local_irq_enable(); + device_pm_unlock(); return error; } @@ -280,7 +283,8 @@ int hibernation_snapshot(int platform_mode) Finish: platform_finish(platform_mode); Resume_devices: - device_resume(); + device_resume(in_suspend ? + (error ? PMSG_RECOVER : PMSG_THAW) : PMSG_RESTORE); Resume_console: resume_console(); Close: @@ -300,8 +304,9 @@ static int resume_target_kernel(void) { int error; + device_pm_lock(); local_irq_disable(); - error = device_power_down(PMSG_PRETHAW); + error = device_power_down(PMSG_QUIESCE); if (error) { printk(KERN_ERR "PM: Some devices failed to power down, " "aborting resume\n"); @@ -329,9 +334,10 @@ static int resume_target_kernel(void) swsusp_free(); restore_processor_state(); touch_softlockup_watchdog(); - device_power_up(); + device_power_up(PMSG_RECOVER); Enable_irqs: local_irq_enable(); + device_pm_unlock(); return error; } @@ -350,7 +356,7 @@ int hibernation_restore(int platform_mode) pm_prepare_console(); suspend_console(); - error = device_suspend(PMSG_PRETHAW); + error = device_suspend(PMSG_QUIESCE); if (error) goto Finish; @@ -362,7 +368,7 @@ int hibernation_restore(int platform_mode) enable_nonboot_cpus(); } platform_restore_cleanup(platform_mode); - device_resume(); + device_resume(PMSG_RECOVER); Finish: resume_console(); pm_restore_console(); @@ -403,6 +409,7 @@ int hibernation_platform_enter(void) if (error) goto Finish; + device_pm_lock(); local_irq_disable(); error = device_power_down(PMSG_HIBERNATE); if (!error) { @@ -411,6 +418,7 @@ int hibernation_platform_enter(void) while (1); } local_irq_enable(); + device_pm_unlock(); /* * We don't need to reenable the nonboot CPUs or resume consoles, since @@ -419,7 +427,7 @@ int hibernation_platform_enter(void) Finish: hibernation_ops->finish(); Resume_devices: - device_resume(); + device_resume(PMSG_RESTORE); Resume_console: resume_console(); Close: diff --git a/kernel/power/main.c b/kernel/power/main.c index 6a6d5eb3524e..d023b6b584e5 100644 --- a/kernel/power/main.c +++ b/kernel/power/main.c @@ -228,6 +228,7 @@ static int suspend_enter(suspend_state_t state) { int error = 0; + device_pm_lock(); arch_suspend_disable_irqs(); BUG_ON(!irqs_disabled()); @@ -239,10 +240,11 @@ static int suspend_enter(suspend_state_t state) if (!suspend_test(TEST_CORE)) error = suspend_ops->enter(state); - device_power_up(); + device_power_up(PMSG_RESUME); Done: arch_suspend_enable_irqs(); BUG_ON(irqs_disabled()); + device_pm_unlock(); return error; } @@ -291,7 +293,7 @@ int suspend_devices_and_enter(suspend_state_t state) if (suspend_ops->finish) suspend_ops->finish(); Resume_devices: - device_resume(); + device_resume(PMSG_RESUME); Resume_console: resume_console(); Close: -- cgit v1.2.3 From bbb44d9f23d868a2837c6b22b8dfb123d8e7800c Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Tue, 20 May 2008 00:49:04 +0200 Subject: PCI: implement new suspend/resume callbacks Implement new suspend and hibernation callbacks for the PCI bus type. Signed-off-by: Rafael J. Wysocki Acked-by: Pavel Machek Signed-off-by: Jesse Barnes --- drivers/pci/pci-driver.c | 392 +++++++++++++++++++++++++++++++++++++++++------ include/linux/pci.h | 2 +- 2 files changed, 347 insertions(+), 47 deletions(-) (limited to 'include') diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 677fd9d6db12..8eb8a3091dc7 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -274,7 +274,57 @@ static int pci_device_remove(struct device * dev) return 0; } -static int pci_device_suspend(struct device * dev, pm_message_t state) +static void pci_device_shutdown(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct pci_driver *drv = pci_dev->driver; + + if (drv && drv->shutdown) + drv->shutdown(pci_dev); + pci_msi_shutdown(pci_dev); + pci_msix_shutdown(pci_dev); +} + +#ifdef CONFIG_PM_SLEEP + +/* + * Default "suspend" method for devices that have no driver provided suspend, + * or not even a driver at all. + */ +static void pci_default_pm_suspend(struct pci_dev *pci_dev) +{ + pci_save_state(pci_dev); + /* + * mark its power state as "unknown", since we don't know if + * e.g. the BIOS will change its device state when we suspend. + */ + if (pci_dev->current_state == PCI_D0) + pci_dev->current_state = PCI_UNKNOWN; +} + +/* + * Default "resume" method for devices that have no driver provided resume, + * or not even a driver at all. + */ +static int pci_default_pm_resume(struct pci_dev *pci_dev) +{ + int retval = 0; + + /* restore the PCI config space */ + pci_restore_state(pci_dev); + /* if the device was enabled before suspend, reenable */ + retval = pci_reenable_device(pci_dev); + /* + * if the device was busmaster before the suspend, make it busmaster + * again + */ + if (pci_dev->is_busmaster) + pci_set_master(pci_dev); + + return retval; +} + +static int pci_legacy_suspend(struct device *dev, pm_message_t state) { struct pci_dev * pci_dev = to_pci_dev(dev); struct pci_driver * drv = pci_dev->driver; @@ -284,21 +334,12 @@ static int pci_device_suspend(struct device * dev, pm_message_t state) i = drv->suspend(pci_dev, state); suspend_report_result(drv->suspend, i); } else { - pci_save_state(pci_dev); - /* - * mark its power state as "unknown", since we don't know if - * e.g. the BIOS will change its device state when we suspend. - */ - if (pci_dev->current_state == PCI_D0) - pci_dev->current_state = PCI_UNKNOWN; + pci_default_pm_suspend(pci_dev); } - - pci_fixup_device(pci_fixup_suspend, pci_dev); - return i; } -static int pci_device_suspend_late(struct device * dev, pm_message_t state) +static int pci_legacy_suspend_late(struct device *dev, pm_message_t state) { struct pci_dev * pci_dev = to_pci_dev(dev); struct pci_driver * drv = pci_dev->driver; @@ -311,26 +352,7 @@ static int pci_device_suspend_late(struct device * dev, pm_message_t state) return i; } -/* - * Default resume method for devices that have no driver provided resume, - * or not even a driver at all. - */ -static int pci_default_resume(struct pci_dev *pci_dev) -{ - int retval = 0; - - /* restore the PCI config space */ - pci_restore_state(pci_dev); - /* if the device was enabled before suspend, reenable */ - retval = pci_reenable_device(pci_dev); - /* if the device was busmaster before the suspend, make it busmaster again */ - if (pci_dev->is_busmaster) - pci_set_master(pci_dev); - - return retval; -} - -static int pci_device_resume(struct device * dev) +static int pci_legacy_resume(struct device *dev) { int error; struct pci_dev * pci_dev = to_pci_dev(dev); @@ -339,35 +361,313 @@ static int pci_device_resume(struct device * dev) if (drv && drv->resume) error = drv->resume(pci_dev); else - error = pci_default_resume(pci_dev); - pci_fixup_device(pci_fixup_resume, pci_dev); + error = pci_default_pm_resume(pci_dev); return error; } -static int pci_device_resume_early(struct device * dev) +static int pci_legacy_resume_early(struct device *dev) { int error = 0; struct pci_dev * pci_dev = to_pci_dev(dev); struct pci_driver * drv = pci_dev->driver; - pci_fixup_device(pci_fixup_resume_early, pci_dev); - if (drv && drv->resume_early) error = drv->resume_early(pci_dev); return error; } -static void pci_device_shutdown(struct device *dev) +static int pci_pm_prepare(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int error = 0; + + if (drv && drv->pm && drv->pm->prepare) + error = drv->pm->prepare(dev); + + return error; +} + +static void pci_pm_complete(struct device *dev) +{ + struct device_driver *drv = dev->driver; + + if (drv && drv->pm && drv->pm->complete) + drv->pm->complete(dev); +} + +#ifdef CONFIG_SUSPEND + +static int pci_pm_suspend(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct device_driver *drv = dev->driver; + int error = 0; + + if (drv && drv->pm) { + if (drv->pm->suspend) { + error = drv->pm->suspend(dev); + suspend_report_result(drv->pm->suspend, error); + } else { + pci_default_pm_suspend(pci_dev); + } + } else { + error = pci_legacy_suspend(dev, PMSG_SUSPEND); + } + pci_fixup_device(pci_fixup_suspend, pci_dev); + + return error; +} + +static int pci_pm_suspend_noirq(struct device *dev) { struct pci_dev *pci_dev = to_pci_dev(dev); struct pci_driver *drv = pci_dev->driver; + int error = 0; - if (drv && drv->shutdown) - drv->shutdown(pci_dev); - pci_msi_shutdown(pci_dev); - pci_msix_shutdown(pci_dev); + if (drv && drv->pm) { + if (drv->pm->suspend_noirq) { + error = drv->pm->suspend_noirq(dev); + suspend_report_result(drv->pm->suspend_noirq, error); + } + } else { + error = pci_legacy_suspend_late(dev, PMSG_SUSPEND); + } + + return error; +} + +static int pci_pm_resume(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct device_driver *drv = dev->driver; + int error; + + pci_fixup_device(pci_fixup_resume, pci_dev); + + if (drv && drv->pm) { + error = drv->pm->resume ? drv->pm->resume(dev) : + pci_default_pm_resume(pci_dev); + } else { + error = pci_legacy_resume(dev); + } + + return error; +} + +static int pci_pm_resume_noirq(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct pci_driver *drv = pci_dev->driver; + int error = 0; + + pci_fixup_device(pci_fixup_resume_early, pci_dev); + + if (drv && drv->pm) { + if (drv->pm->resume_noirq) + error = drv->pm->resume_noirq(dev); + } else { + error = pci_legacy_resume_early(dev); + } + + return error; +} + +#else /* !CONFIG_SUSPEND */ + +#define pci_pm_suspend NULL +#define pci_pm_suspend_noirq NULL +#define pci_pm_resume NULL +#define pci_pm_resume_noirq NULL + +#endif /* !CONFIG_SUSPEND */ + +#ifdef CONFIG_HIBERNATION + +static int pci_pm_freeze(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct device_driver *drv = dev->driver; + int error = 0; + + if (drv && drv->pm) { + if (drv->pm->freeze) { + error = drv->pm->freeze(dev); + suspend_report_result(drv->pm->freeze, error); + } else { + pci_default_pm_suspend(pci_dev); + } + } else { + error = pci_legacy_suspend(dev, PMSG_FREEZE); + pci_fixup_device(pci_fixup_suspend, pci_dev); + } + + return error; +} + +static int pci_pm_freeze_noirq(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct pci_driver *drv = pci_dev->driver; + int error = 0; + + if (drv && drv->pm) { + if (drv->pm->freeze_noirq) { + error = drv->pm->freeze_noirq(dev); + suspend_report_result(drv->pm->freeze_noirq, error); + } + } else { + error = pci_legacy_suspend_late(dev, PMSG_FREEZE); + } + + return error; +} + +static int pci_pm_thaw(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int error = 0; + + if (drv && drv->pm) { + if (drv->pm->thaw) + error = drv->pm->thaw(dev); + } else { + pci_fixup_device(pci_fixup_resume, to_pci_dev(dev)); + error = pci_legacy_resume(dev); + } + + return error; +} + +static int pci_pm_thaw_noirq(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct pci_driver *drv = pci_dev->driver; + int error = 0; + + if (drv && drv->pm) { + if (drv->pm->thaw_noirq) + error = drv->pm->thaw_noirq(dev); + } else { + pci_fixup_device(pci_fixup_resume_early, pci_dev); + error = pci_legacy_resume_early(dev); + } + + return error; +} + +static int pci_pm_poweroff(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int error = 0; + + pci_fixup_device(pci_fixup_suspend, to_pci_dev(dev)); + + if (drv && drv->pm) { + if (drv->pm->poweroff) { + error = drv->pm->poweroff(dev); + suspend_report_result(drv->pm->poweroff, error); + } + } else { + error = pci_legacy_suspend(dev, PMSG_HIBERNATE); + } + + return error; +} + +static int pci_pm_poweroff_noirq(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct pci_driver *drv = pci_dev->driver; + int error = 0; + + if (drv && drv->pm) { + if (drv->pm->poweroff_noirq) { + error = drv->pm->poweroff_noirq(dev); + suspend_report_result(drv->pm->poweroff_noirq, error); + } + } else { + error = pci_legacy_suspend_late(dev, PMSG_HIBERNATE); + } + + return error; +} + +static int pci_pm_restore(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct device_driver *drv = dev->driver; + int error; + + if (drv && drv->pm) { + error = drv->pm->restore ? drv->pm->restore(dev) : + pci_default_pm_resume(pci_dev); + } else { + error = pci_legacy_resume(dev); + } + pci_fixup_device(pci_fixup_resume, pci_dev); + + return error; +} + +static int pci_pm_restore_noirq(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct pci_driver *drv = pci_dev->driver; + int error = 0; + + pci_fixup_device(pci_fixup_resume, pci_dev); + + if (drv && drv->pm) { + if (drv->pm->restore_noirq) + error = drv->pm->restore_noirq(dev); + } else { + error = pci_legacy_resume_early(dev); + } + pci_fixup_device(pci_fixup_resume_early, pci_dev); + + return error; } +#else /* !CONFIG_HIBERNATION */ + +#define pci_pm_freeze NULL +#define pci_pm_freeze_noirq NULL +#define pci_pm_thaw NULL +#define pci_pm_thaw_noirq NULL +#define pci_pm_poweroff NULL +#define pci_pm_poweroff_noirq NULL +#define pci_pm_restore NULL +#define pci_pm_restore_noirq NULL + +#endif /* !CONFIG_HIBERNATION */ + +struct pm_ext_ops pci_pm_ops = { + .base = { + .prepare = pci_pm_prepare, + .complete = pci_pm_complete, + .suspend = pci_pm_suspend, + .resume = pci_pm_resume, + .freeze = pci_pm_freeze, + .thaw = pci_pm_thaw, + .poweroff = pci_pm_poweroff, + .restore = pci_pm_restore, + }, + .suspend_noirq = pci_pm_suspend_noirq, + .resume_noirq = pci_pm_resume_noirq, + .freeze_noirq = pci_pm_freeze_noirq, + .thaw_noirq = pci_pm_thaw_noirq, + .poweroff_noirq = pci_pm_poweroff_noirq, + .restore_noirq = pci_pm_restore_noirq, +}; + +#define PCI_PM_OPS_PTR &pci_pm_ops + +#else /* !CONFIG_PM_SLEEP */ + +#define PCI_PM_OPS_PTR NULL + +#endif /* !CONFIG_PM_SLEEP */ + /** * __pci_register_driver - register a new pci driver * @drv: the driver structure to register @@ -390,6 +690,9 @@ int __pci_register_driver(struct pci_driver *drv, struct module *owner, drv->driver.owner = owner; drv->driver.mod_name = mod_name; + if (drv->pm) + drv->driver.pm = &drv->pm->base; + spin_lock_init(&drv->dynids.lock); INIT_LIST_HEAD(&drv->dynids.list); @@ -515,12 +818,9 @@ struct bus_type pci_bus_type = { .uevent = pci_uevent, .probe = pci_device_probe, .remove = pci_device_remove, - .suspend = pci_device_suspend, - .suspend_late = pci_device_suspend_late, - .resume_early = pci_device_resume_early, - .resume = pci_device_resume, .shutdown = pci_device_shutdown, .dev_attrs = pci_dev_attrs, + .pm = PCI_PM_OPS_PTR, }; static int __init pci_driver_init(void) diff --git a/include/linux/pci.h b/include/linux/pci.h index 700704ef70f3..507ee52323cd 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -389,7 +389,7 @@ struct pci_driver { int (*resume_early) (struct pci_dev *dev); int (*resume) (struct pci_dev *dev); /* Device woken up */ void (*shutdown) (struct pci_dev *dev); - + struct pm_ext_ops *pm; struct pci_error_handlers *err_handler; struct device_driver driver; struct pci_dynids dynids; -- cgit v1.2.3 From 25e18499e08cb097cbbfeab5de25d094d5312ee5 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Wed, 21 May 2008 01:40:43 +0200 Subject: Implement new suspend and hibernation callbacks for platform busses Implement new suspend and hibernation callbacks for the platform bus type. Signed-off-by: Rafael J. Wysocki Acked-by: Pavel Machek Signed-off-by: Greg KH Signed-off-by: Jesse Barnes --- drivers/base/platform.c | 296 ++++++++++++++++++++++++++++++++++++++-- include/linux/platform_device.h | 1 + 2 files changed, 289 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 911ec600fe71..3f940393d6c7 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -453,6 +453,8 @@ int platform_driver_register(struct platform_driver *drv) drv->driver.suspend = platform_drv_suspend; if (drv->resume) drv->driver.resume = platform_drv_resume; + if (drv->pm) + drv->driver.pm = &drv->pm->base; return driver_register(&drv->driver); } EXPORT_SYMBOL_GPL(platform_driver_register); @@ -560,7 +562,9 @@ static int platform_match(struct device *dev, struct device_driver *drv) return (strncmp(pdev->name, drv->name, BUS_ID_SIZE) == 0); } -static int platform_suspend(struct device *dev, pm_message_t mesg) +#ifdef CONFIG_PM_SLEEP + +static int platform_legacy_suspend(struct device *dev, pm_message_t mesg) { int ret = 0; @@ -570,7 +574,7 @@ static int platform_suspend(struct device *dev, pm_message_t mesg) return ret; } -static int platform_suspend_late(struct device *dev, pm_message_t mesg) +static int platform_legacy_suspend_late(struct device *dev, pm_message_t mesg) { struct platform_driver *drv = to_platform_driver(dev->driver); struct platform_device *pdev; @@ -583,7 +587,7 @@ static int platform_suspend_late(struct device *dev, pm_message_t mesg) return ret; } -static int platform_resume_early(struct device *dev) +static int platform_legacy_resume_early(struct device *dev) { struct platform_driver *drv = to_platform_driver(dev->driver); struct platform_device *pdev; @@ -596,7 +600,7 @@ static int platform_resume_early(struct device *dev) return ret; } -static int platform_resume(struct device *dev) +static int platform_legacy_resume(struct device *dev) { int ret = 0; @@ -606,15 +610,291 @@ static int platform_resume(struct device *dev) return ret; } +static int platform_pm_prepare(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (drv && drv->pm && drv->pm->prepare) + ret = drv->pm->prepare(dev); + + return ret; +} + +static void platform_pm_complete(struct device *dev) +{ + struct device_driver *drv = dev->driver; + + if (drv && drv->pm && drv->pm->complete) + drv->pm->complete(dev); +} + +#ifdef CONFIG_SUSPEND + +static int platform_pm_suspend(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (drv && drv->pm) { + if (drv->pm->suspend) + ret = drv->pm->suspend(dev); + } else { + ret = platform_legacy_suspend(dev, PMSG_SUSPEND); + } + + return ret; +} + +static int platform_pm_suspend_noirq(struct device *dev) +{ + struct platform_driver *pdrv; + int ret = 0; + + if (!dev->driver) + return 0; + + pdrv = to_platform_driver(dev->driver); + if (pdrv->pm) { + if (pdrv->pm->suspend_noirq) + ret = pdrv->pm->suspend_noirq(dev); + } else { + ret = platform_legacy_suspend_late(dev, PMSG_SUSPEND); + } + + return ret; +} + +static int platform_pm_resume(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (drv && drv->pm) { + if (drv->pm->resume) + ret = drv->pm->resume(dev); + } else { + ret = platform_legacy_resume(dev); + } + + return ret; +} + +static int platform_pm_resume_noirq(struct device *dev) +{ + struct platform_driver *pdrv; + int ret = 0; + + if (!dev->driver) + return 0; + + pdrv = to_platform_driver(dev->driver); + if (pdrv->pm) { + if (pdrv->pm->resume_noirq) + ret = pdrv->pm->resume_noirq(dev); + } else { + ret = platform_legacy_resume_early(dev); + } + + return ret; +} + +#else /* !CONFIG_SUSPEND */ + +#define platform_pm_suspend NULL +#define platform_pm_resume NULL +#define platform_pm_suspend_noirq NULL +#define platform_pm_resume_noirq NULL + +#endif /* !CONFIG_SUSPEND */ + +#ifdef CONFIG_HIBERNATION + +static int platform_pm_freeze(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (!drv) + return 0; + + if (drv->pm) { + if (drv->pm->freeze) + ret = drv->pm->freeze(dev); + } else { + ret = platform_legacy_suspend(dev, PMSG_FREEZE); + } + + return ret; +} + +static int platform_pm_freeze_noirq(struct device *dev) +{ + struct platform_driver *pdrv; + int ret = 0; + + if (!dev->driver) + return 0; + + pdrv = to_platform_driver(dev->driver); + if (pdrv->pm) { + if (pdrv->pm->freeze_noirq) + ret = pdrv->pm->freeze_noirq(dev); + } else { + ret = platform_legacy_suspend_late(dev, PMSG_FREEZE); + } + + return ret; +} + +static int platform_pm_thaw(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (drv && drv->pm) { + if (drv->pm->thaw) + ret = drv->pm->thaw(dev); + } else { + ret = platform_legacy_resume(dev); + } + + return ret; +} + +static int platform_pm_thaw_noirq(struct device *dev) +{ + struct platform_driver *pdrv; + int ret = 0; + + if (!dev->driver) + return 0; + + pdrv = to_platform_driver(dev->driver); + if (pdrv->pm) { + if (pdrv->pm->thaw_noirq) + ret = pdrv->pm->thaw_noirq(dev); + } else { + ret = platform_legacy_resume_early(dev); + } + + return ret; +} + +static int platform_pm_poweroff(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (drv && drv->pm) { + if (drv->pm->poweroff) + ret = drv->pm->poweroff(dev); + } else { + ret = platform_legacy_suspend(dev, PMSG_HIBERNATE); + } + + return ret; +} + +static int platform_pm_poweroff_noirq(struct device *dev) +{ + struct platform_driver *pdrv; + int ret = 0; + + if (!dev->driver) + return 0; + + pdrv = to_platform_driver(dev->driver); + if (pdrv->pm) { + if (pdrv->pm->poweroff_noirq) + ret = pdrv->pm->poweroff_noirq(dev); + } else { + ret = platform_legacy_suspend_late(dev, PMSG_HIBERNATE); + } + + return ret; +} + +static int platform_pm_restore(struct device *dev) +{ + struct device_driver *drv = dev->driver; + int ret = 0; + + if (drv && drv->pm) { + if (drv->pm->restore) + ret = drv->pm->restore(dev); + } else { + ret = platform_legacy_resume(dev); + } + + return ret; +} + +static int platform_pm_restore_noirq(struct device *dev) +{ + struct platform_driver *pdrv; + int ret = 0; + + if (!dev->driver) + return 0; + + pdrv = to_platform_driver(dev->driver); + if (pdrv->pm) { + if (pdrv->pm->restore_noirq) + ret = pdrv->pm->restore_noirq(dev); + } else { + ret = platform_legacy_resume_early(dev); + } + + return ret; +} + +#else /* !CONFIG_HIBERNATION */ + +#define platform_pm_freeze NULL +#define platform_pm_thaw NULL +#define platform_pm_poweroff NULL +#define platform_pm_restore NULL +#define platform_pm_freeze_noirq NULL +#define platform_pm_thaw_noirq NULL +#define platform_pm_poweroff_noirq NULL +#define platform_pm_restore_noirq NULL + +#endif /* !CONFIG_HIBERNATION */ + +struct pm_ext_ops platform_pm_ops = { + .base = { + .prepare = platform_pm_prepare, + .complete = platform_pm_complete, + .suspend = platform_pm_suspend, + .resume = platform_pm_resume, + .freeze = platform_pm_freeze, + .thaw = platform_pm_thaw, + .poweroff = platform_pm_poweroff, + .restore = platform_pm_restore, + }, + .suspend_noirq = platform_pm_suspend_noirq, + .resume_noirq = platform_pm_resume_noirq, + .freeze_noirq = platform_pm_freeze_noirq, + .thaw_noirq = platform_pm_thaw_noirq, + .poweroff_noirq = platform_pm_poweroff_noirq, + .restore_noirq = platform_pm_restore_noirq, +}; + +#define PLATFORM_PM_OPS_PTR &platform_pm_ops + +#else /* !CONFIG_PM_SLEEP */ + +#define PLATFORM_PM_OPS_PTR NULL + +#endif /* !CONFIG_PM_SLEEP */ + struct bus_type platform_bus_type = { .name = "platform", .dev_attrs = platform_dev_attrs, .match = platform_match, .uevent = platform_uevent, - .suspend = platform_suspend, - .suspend_late = platform_suspend_late, - .resume_early = platform_resume_early, - .resume = platform_resume, + .pm = PLATFORM_PM_OPS_PTR, }; EXPORT_SYMBOL_GPL(platform_bus_type); diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 3261681c82a4..95ac21ab3a09 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -53,6 +53,7 @@ struct platform_driver { int (*suspend_late)(struct platform_device *, pm_message_t state); int (*resume_early)(struct platform_device *); int (*resume)(struct platform_device *); + struct pm_ext_ops *pm; struct device_driver driver; }; -- cgit v1.2.3 From e7891c733f9b26c851edde50cf886a30bd133dbd Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Thu, 22 May 2008 14:35:21 -0700 Subject: PCI/x86: write_pci_config_byte fix offset also add write_pci_config_16 Signed-off-by: Yinghai Lu Signed-off-by: Jesse Barnes --- arch/x86/pci/early.c | 9 ++++++++- include/asm-x86/pci-direct.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/x86/pci/early.c b/arch/x86/pci/early.c index 42df4b6606df..8e2821e8dac5 100644 --- a/arch/x86/pci/early.c +++ b/arch/x86/pci/early.c @@ -49,7 +49,14 @@ void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val) { PDprintk("%x writing to %x: %x\n", slot, offset, val); outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); - outb(val, 0xcfc); + outb(val, 0xcfc + (offset&3)); +} + +void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val) +{ + PDprintk("%x writing to %x: %x\n", slot, offset, val); + outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); + outw(val, 0xcfc + (offset&2)); } int early_pci_allowed(void) diff --git a/include/asm-x86/pci-direct.h b/include/asm-x86/pci-direct.h index 5b21485be573..7bd40b4de751 100644 --- a/include/asm-x86/pci-direct.h +++ b/include/asm-x86/pci-direct.h @@ -11,6 +11,7 @@ extern u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset); extern u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset); extern void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, u32 val); extern void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val); +extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val); extern int early_pci_allowed(void); -- cgit v1.2.3 From e3f2baebf4209b5927e23fa65d5977d31db936b3 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Thu, 22 May 2008 14:35:11 -0700 Subject: PCI/x86: early dump pci conf space v2 Allows us to dump PCI space before any kernel changes have been made. Signed-off-by: Yinghai Lu Signed-off-by: Jesse Barnes --- arch/x86/kernel/setup_64.c | 5 +++++ arch/x86/pci/common.c | 4 ++++ arch/x86/pci/early.c | 51 ++++++++++++++++++++++++++++++++++++++++++++ include/asm-x86/pci-direct.h | 3 +++ 4 files changed, 63 insertions(+) (limited to 'include') diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c index 6dff1286ad8a..524b6850b2c0 100644 --- a/arch/x86/kernel/setup_64.c +++ b/arch/x86/kernel/setup_64.c @@ -361,6 +361,11 @@ void __init setup_arch(char **cmdline_p) parse_early_param(); +#ifdef CONFIG_PCI + if (pci_early_dump_regs) + early_dump_pci_devices(); +#endif + #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT if (init_ohci1394_dma_early) init_ohci1394_dma_on_all_controllers(); diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 3a5261bdff5d..d19fd07bafd6 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -20,6 +20,7 @@ unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 | PCI_PROBE_MMCONF; +unsigned int pci_early_dump_regs; static int pci_bf_sort; int pci_routeirq; int pcibios_last_bus = -1; @@ -511,6 +512,9 @@ char * __devinit pcibios_setup(char *str) } else if (!strcmp(str, "use_crs")) { pci_probe |= PCI_USE__CRS; return NULL; + } else if (!strcmp(str, "earlydump")) { + pci_early_dump_regs = 1; + return NULL; } else if (!strcmp(str, "routeirq")) { pci_routeirq = 1; return NULL; diff --git a/arch/x86/pci/early.c b/arch/x86/pci/early.c index 8e2821e8dac5..858dbe3399f9 100644 --- a/arch/x86/pci/early.c +++ b/arch/x86/pci/early.c @@ -64,3 +64,54 @@ int early_pci_allowed(void) return (pci_probe & (PCI_PROBE_CONF1|PCI_PROBE_NOEARLY)) == PCI_PROBE_CONF1; } + +void early_dump_pci_device(u8 bus, u8 slot, u8 func) +{ + int i; + int j; + u32 val; + + printk("PCI: %02x:%02x:%02x", bus, slot, func); + + for (i = 0; i < 256; i += 4) { + if (!(i & 0x0f)) + printk("\n%04x:",i); + + val = read_pci_config(bus, slot, func, i); + for (j = 0; j < 4; j++) { + printk(" %02x", val & 0xff); + val >>= 8; + } + } + printk("\n"); +} + +void early_dump_pci_devices(void) +{ + unsigned bus, slot, func; + + if (!early_pci_allowed()) + return; + + for (bus = 0; bus < 256; bus++) { + for (slot = 0; slot < 32; slot++) { + for (func = 0; func < 8; func++) { + u32 class; + u8 type; + class = read_pci_config(bus, slot, func, + PCI_CLASS_REVISION); + if (class == 0xffffffff) + break; + + early_dump_pci_device(bus, slot, func); + + /* No multi-function device? */ + type = read_pci_config_byte(bus, slot, func, + PCI_HEADER_TYPE); + if (!(type & 0x80)) + break; + } + } + } +} + diff --git a/include/asm-x86/pci-direct.h b/include/asm-x86/pci-direct.h index 7bd40b4de751..80c775d9fe20 100644 --- a/include/asm-x86/pci-direct.h +++ b/include/asm-x86/pci-direct.h @@ -15,4 +15,7 @@ extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val); extern int early_pci_allowed(void); +extern unsigned int pci_early_dump_regs; +extern void early_dump_pci_device(u8 bus, u8 slot, u8 func); +extern void early_dump_pci_devices(void); #endif -- cgit v1.2.3 From ac9c052d10d8d6f46a30cb46c0d6d753997c299f Mon Sep 17 00:00:00 2001 From: Kenji Kaneshige Date: Wed, 28 May 2008 15:01:03 +0900 Subject: shpchp: check firmware before taking control Fix the following problems of shpchp driver about getting hotplug control from firmware. - The shpchp driver must not control the hotplug controller if it fails to get control from the firmware. But current shpchp controls the hotplug controller regardless the result, because it doesn't check the return value of get_hp_hw_control_from_firmware(). - Current shpchp driver doesn't support _OSC. The pciehp driver already have the code for evaluating _OSC and OSHP and shpchp and pciehp can share it. So this patch move that code from pciehp to acpi_pcihp.c. Signed-off-by: Kenji Kaneshige Signed-off-by: Jesse Barnes --- drivers/pci/hotplug/acpi_pcihp.c | 85 +++++++++++++++++++++++++++++++++++++-- drivers/pci/hotplug/pciehp.h | 10 +++-- drivers/pci/hotplug/pciehp_hpc.c | 69 ------------------------------- drivers/pci/hotplug/shpchp.h | 14 ++++--- drivers/pci/hotplug/shpchp_core.c | 15 +++---- drivers/pci/hotplug/shpchp_hpc.c | 1 - include/linux/pci_hotplug.h | 2 +- 7 files changed, 105 insertions(+), 91 deletions(-) (limited to 'include') diff --git a/drivers/pci/hotplug/acpi_pcihp.c b/drivers/pci/hotplug/acpi_pcihp.c index f8c187a763bd..93e37f0666ab 100644 --- a/drivers/pci/hotplug/acpi_pcihp.c +++ b/drivers/pci/hotplug/acpi_pcihp.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -299,7 +300,7 @@ free_and_return: * * @handle - the handle of the hotplug controller. */ -acpi_status acpi_run_oshp(acpi_handle handle) +static acpi_status acpi_run_oshp(acpi_handle handle) { acpi_status status; struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; @@ -322,9 +323,6 @@ acpi_status acpi_run_oshp(acpi_handle handle) kfree(string.pointer); return status; } -EXPORT_SYMBOL_GPL(acpi_run_oshp); - - /* acpi_get_hp_params_from_firmware * @@ -374,6 +372,85 @@ acpi_status acpi_get_hp_params_from_firmware(struct pci_bus *bus, } EXPORT_SYMBOL_GPL(acpi_get_hp_params_from_firmware); +/** + * acpi_get_hp_hw_control_from_firmware + * @dev: the pci_dev of the bridge that has a hotplug controller + * @flags: requested control bits for _OSC + * + * Attempt to take hotplug control from firmware. + */ +int acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev, u32 flags) +{ + acpi_status status; + acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); + struct pci_dev *pdev = dev; + struct pci_bus *parent; + struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; + + flags &= (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | + OSC_SHPC_NATIVE_HP_CONTROL | + OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); + if (!flags) { + err("Invalid flags %u specified!\n", flags); + return -EINVAL; + } + + /* + * Per PCI firmware specification, we should run the ACPI _OSC + * method to get control of hotplug hardware before using it. If + * an _OSC is missing, we look for an OSHP to do the same thing. + * To handle different BIOS behavior, we look for _OSC and OSHP + * within the scope of the hotplug controller and its parents, + * upto the host bridge under which this controller exists. + */ + while (!handle) { + /* + * This hotplug controller was not listed in the ACPI name + * space at all. Try to get acpi handle of parent pci bus. + */ + if (!pdev || !pdev->bus->parent) + break; + parent = pdev->bus->parent; + dbg("Could not find %s in acpi namespace, trying parent\n", + pci_name(pdev)); + if (!parent->self) + /* Parent must be a host bridge */ + handle = acpi_get_pci_rootbridge_handle( + pci_domain_nr(parent), + parent->number); + else + handle = DEVICE_ACPI_HANDLE(&(parent->self->dev)); + pdev = parent->self; + } + + while (handle) { + acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); + dbg("Trying to get hotplug control for %s \n", + (char *)string.pointer); + status = pci_osc_control_set(handle, flags); + if (status == AE_NOT_FOUND) + status = acpi_run_oshp(handle); + if (ACPI_SUCCESS(status)) { + dbg("Gained control for hotplug HW for pci %s (%s)\n", + pci_name(dev), (char *)string.pointer); + kfree(string.pointer); + return 0; + } + if (acpi_root_bridge(handle)) + break; + chandle = handle; + status = acpi_get_parent(chandle, &handle); + if (ACPI_FAILURE(status)) + break; + } + + dbg("Cannot get control of hotplug hardware for pci %s\n", + pci_name(dev)); + + kfree(string.pointer); + return -ENODEV; +} +EXPORT_SYMBOL(acpi_get_hp_hw_control_from_firmware); /* acpi_root_bridge - check to see if this acpi object is a root bridge * diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index 084b73efacb3..8492fab800cc 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h @@ -202,9 +202,13 @@ struct hpc_ops { #include #include -extern int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev); -#define pciehp_get_hp_hw_control_from_firmware(dev) \ - pciehp_acpi_get_hp_hw_control_from_firmware(dev) +static inline int pciehp_get_hp_hw_control_from_firmware(struct pci_dev *dev) +{ + u32 flags = (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | + OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); + return acpi_get_hp_hw_control_from_firmware(dev, flags); +} + static inline int pciehp_get_hp_params_from_firmware(struct pci_dev *dev, struct hotplug_params *hpp) { diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 7e3a3d17c334..a48021d85f22 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -1009,75 +1009,6 @@ static struct hpc_ops pciehp_hpc_ops = { .check_lnk_status = hpc_check_lnk_status, }; -#ifdef CONFIG_ACPI -int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) -{ - acpi_status status; - acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); - struct pci_dev *pdev = dev; - struct pci_bus *parent; - struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; - - /* - * Per PCI firmware specification, we should run the ACPI _OSC - * method to get control of hotplug hardware before using it. - * If an _OSC is missing, we look for an OSHP to do the same thing. - * To handle different BIOS behavior, we look for _OSC and OSHP - * within the scope of the hotplug controller and its parents, upto - * the host bridge under which this controller exists. - */ - while (!handle) { - /* - * This hotplug controller was not listed in the ACPI name - * space at all. Try to get acpi handle of parent pci bus. - */ - if (!pdev || !pdev->bus->parent) - break; - parent = pdev->bus->parent; - dbg("Could not find %s in acpi namespace, trying parent\n", - pci_name(pdev)); - if (!parent->self) - /* Parent must be a host bridge */ - handle = acpi_get_pci_rootbridge_handle( - pci_domain_nr(parent), - parent->number); - else - handle = DEVICE_ACPI_HANDLE( - &(parent->self->dev)); - pdev = parent->self; - } - - while (handle) { - acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); - dbg("Trying to get hotplug control for %s \n", - (char *)string.pointer); - status = pci_osc_control_set(handle, - OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL | - OSC_PCI_EXPRESS_NATIVE_HP_CONTROL); - if (status == AE_NOT_FOUND) - status = acpi_run_oshp(handle); - if (ACPI_SUCCESS(status)) { - dbg("Gained control for hotplug HW for pci %s (%s)\n", - pci_name(dev), (char *)string.pointer); - kfree(string.pointer); - return 0; - } - if (acpi_root_bridge(handle)) - break; - chandle = handle; - status = acpi_get_parent(chandle, &handle); - if (ACPI_FAILURE(status)) - break; - } - - dbg("Cannot get control of hotplug hardware for pci %s\n", - pci_name(dev)); - - kfree(string.pointer); - return -1; -} -#endif - static int pcie_init_hardware_part1(struct controller *ctrl, struct pcie_device *dev) { diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h index f66e8d6315ab..8a026f750deb 100644 --- a/drivers/pci/hotplug/shpchp.h +++ b/drivers/pci/hotplug/shpchp.h @@ -170,6 +170,7 @@ extern void shpchp_queue_pushbutton_work(struct work_struct *work); extern int shpc_init( struct controller *ctrl, struct pci_dev *pdev); #ifdef CONFIG_ACPI +#include static inline int get_hp_params_from_firmware(struct pci_dev *dev, struct hotplug_params *hpp) { @@ -177,14 +178,15 @@ static inline int get_hp_params_from_firmware(struct pci_dev *dev, return -ENODEV; return 0; } -#define get_hp_hw_control_from_firmware(pdev) \ - do { \ - if (DEVICE_ACPI_HANDLE(&(pdev->dev))) \ - acpi_run_oshp(DEVICE_ACPI_HANDLE(&(pdev->dev)));\ - } while (0) + +static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev) +{ + u32 flags = OSC_SHPC_NATIVE_HP_CONTROL; + return acpi_get_hp_hw_control_from_firmware(dev, flags); +} #else #define get_hp_params_from_firmware(dev, hpp) (-ENODEV) -#define get_hp_hw_control_from_firmware(dev) do { } while (0) +#define get_hp_hw_control_from_firmware(dev) (0) #endif struct ctrl_reg { diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c index 0066b0be0928..df41ecc4e7fc 100644 --- a/drivers/pci/hotplug/shpchp_core.c +++ b/drivers/pci/hotplug/shpchp_core.c @@ -330,13 +330,14 @@ static int get_cur_bus_speed (struct hotplug_slot *hotplug_slot, enum pci_bus_sp static int is_shpc_capable(struct pci_dev *dev) { - if ((dev->vendor == PCI_VENDOR_ID_AMD) || (dev->device == - PCI_DEVICE_ID_AMD_GOLAM_7450)) - return 1; - if (pci_find_capability(dev, PCI_CAP_ID_SHPC)) - return 1; - - return 0; + if ((dev->vendor == PCI_VENDOR_ID_AMD) || (dev->device == + PCI_DEVICE_ID_AMD_GOLAM_7450)) + return 1; + if (!pci_find_capability(dev, PCI_CAP_ID_SHPC)) + return 0; + if (get_hp_hw_control_from_firmware(dev)) + return 0; + return 1; } static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent) diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c index 7d770b2cd889..7a0bff364cd4 100644 --- a/drivers/pci/hotplug/shpchp_hpc.c +++ b/drivers/pci/hotplug/shpchp_hpc.c @@ -1084,7 +1084,6 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __func__, pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), pdev->irq); - get_hp_hw_control_from_firmware(pdev); /* * If this is the first controller to be initialized, diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index 8f67e8f2a3cc..dbdcd1ad3c6a 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -227,9 +227,9 @@ struct hotplug_params { #include #include #include -extern acpi_status acpi_run_oshp(acpi_handle handle); extern acpi_status acpi_get_hp_params_from_firmware(struct pci_bus *bus, struct hotplug_params *hpp); +int acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev, u32 flags); int acpi_root_bridge(acpi_handle handle); #endif #endif -- cgit v1.2.3 From f46753c5e354b857b20ab8e0fe7b2579831dc369 Mon Sep 17 00:00:00 2001 From: Alex Chiang Date: Tue, 10 Jun 2008 15:28:50 -0600 Subject: PCI: introduce pci_slot Currently, /sys/bus/pci/slots/ only exposes hotplug attributes when a hotplug driver is loaded, but PCI slots have attributes such as address, speed, width, etc. that are not related to hotplug at all. Introduce pci_slot as the primary data structure and kobject model. Hotplug attributes described in hotplug_slot become a secondary structure associated with the pci_slot. This patch only creates the infrastructure that allows the separation of PCI slot attributes and hotplug attributes. In this patch, the PCI hotplug core remains the only user of this infrastructure, and thus, /sys/bus/pci/slots/ will still only become populated when a hotplug driver is loaded. A later patch in this series will add a second user of this new infrastructure and demonstrate splitting the task of exposing pci_slot attributes from hotplug_slot attributes. - Make pci_slot the primary sysfs entity. hotplug_slot becomes a subsidiary structure. o pci_create_slot() creates and registers a slot with the PCI core o pci_slot_add_hotplug() gives it hotplug capability - Change the prototype of pci_hp_register() to take the bus and slot number (on parent bus) as parameters. - Remove all the ->get_address methods since this functionality is now handled by pci_slot directly. [achiang@hp.com: rpaphp-correctly-pci_hp_register-for-empty-pci-slots] Tested-by: Badari Pulavarty Acked-by: Benjamin Herrenschmidt [akpm@linux-foundation.org: build fix] [akpm@linux-foundation.org: make headers_check happy] [akpm@linux-foundation.org: nuther build fix] [akpm@linux-foundation.org: fix typo in #include] Signed-off-by: Alex Chiang Signed-off-by: Matthew Wilcox Cc: Greg KH Cc: Kristen Carlson Accardi Cc: Len Brown Acked-by: Kenji Kaneshige Signed-off-by: Andrew Morton Signed-off-by: Jesse Barnes --- drivers/pci/Makefile | 2 +- drivers/pci/hotplug/acpiphp.h | 1 - drivers/pci/hotplug/acpiphp_core.c | 25 +--- drivers/pci/hotplug/acpiphp_glue.c | 23 +-- drivers/pci/hotplug/acpiphp_ibm.c | 6 +- drivers/pci/hotplug/cpci_hotplug_core.c | 2 +- drivers/pci/hotplug/cpqphp_core.c | 4 +- drivers/pci/hotplug/fakephp.c | 2 +- drivers/pci/hotplug/ibmphp_ebda.c | 3 +- drivers/pci/hotplug/pci_hotplug_core.c | 258 ++++++++++++-------------------- drivers/pci/hotplug/pciehp_core.c | 32 ++-- drivers/pci/hotplug/rpadlpar_sysfs.c | 5 +- drivers/pci/hotplug/rpaphp_slot.c | 44 +----- drivers/pci/hotplug/sgi_hotplug.c | 10 +- drivers/pci/hotplug/shpchp_core.c | 20 +-- drivers/pci/pci.h | 13 ++ drivers/pci/probe.c | 1 + drivers/pci/slot.c | 233 ++++++++++++++++++++++++++++ include/linux/pci.h | 19 ++- include/linux/pci_hotplug.h | 12 +- 20 files changed, 422 insertions(+), 293 deletions(-) create mode 100644 drivers/pci/slot.c (limited to 'include') diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 4d1ce2e7361e..7d63f8ced24b 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -2,7 +2,7 @@ # Makefile for the PCI bus specific drivers. # -obj-y += access.o bus.o probe.o remove.o pci.o quirks.o \ +obj-y += access.o bus.o probe.o remove.o pci.o quirks.o slot.o \ pci-driver.o search.o pci-sysfs.o rom.o setup-res.o obj-$(CONFIG_PROC_FS) += proc.o diff --git a/drivers/pci/hotplug/acpiphp.h b/drivers/pci/hotplug/acpiphp.h index 7a29164d4b32..eecf7cbf4139 100644 --- a/drivers/pci/hotplug/acpiphp.h +++ b/drivers/pci/hotplug/acpiphp.h @@ -215,7 +215,6 @@ extern u8 acpiphp_get_power_status (struct acpiphp_slot *slot); extern u8 acpiphp_get_attention_status (struct acpiphp_slot *slot); extern u8 acpiphp_get_latch_status (struct acpiphp_slot *slot); extern u8 acpiphp_get_adapter_status (struct acpiphp_slot *slot); -extern u32 acpiphp_get_address (struct acpiphp_slot *slot); /* variables */ extern int acpiphp_debug; diff --git a/drivers/pci/hotplug/acpiphp_core.c b/drivers/pci/hotplug/acpiphp_core.c index 7af68ba27903..0e496e866a84 100644 --- a/drivers/pci/hotplug/acpiphp_core.c +++ b/drivers/pci/hotplug/acpiphp_core.c @@ -70,7 +70,6 @@ static int disable_slot (struct hotplug_slot *slot); static int set_attention_status (struct hotplug_slot *slot, u8 value); static int get_power_status (struct hotplug_slot *slot, u8 *value); static int get_attention_status (struct hotplug_slot *slot, u8 *value); -static int get_address (struct hotplug_slot *slot, u32 *value); static int get_latch_status (struct hotplug_slot *slot, u8 *value); static int get_adapter_status (struct hotplug_slot *slot, u8 *value); @@ -83,7 +82,6 @@ static struct hotplug_slot_ops acpi_hotplug_slot_ops = { .get_attention_status = get_attention_status, .get_latch_status = get_latch_status, .get_adapter_status = get_adapter_status, - .get_address = get_address, }; @@ -274,23 +272,6 @@ static int get_adapter_status(struct hotplug_slot *hotplug_slot, u8 *value) return 0; } - -/** - * get_address - get pci address of a slot - * @hotplug_slot: slot to get status - * @value: pointer to struct pci_busdev (seg, bus, dev) - */ -static int get_address(struct hotplug_slot *hotplug_slot, u32 *value) -{ - struct slot *slot = hotplug_slot->private; - - dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name); - - *value = acpiphp_get_address(slot->acpi_slot); - - return 0; -} - static int __init init_acpi(void) { int retval; @@ -357,7 +338,11 @@ int acpiphp_register_hotplug_slot(struct acpiphp_slot *acpiphp_slot) acpiphp_slot->slot = slot; snprintf(slot->name, sizeof(slot->name), "%u", slot->acpi_slot->sun); - retval = pci_hp_register(slot->hotplug_slot); + retval = pci_hp_register(slot->hotplug_slot, + acpiphp_slot->bridge->pci_bus, + acpiphp_slot->device); + if (retval == -EBUSY) + goto error_hpslot; if (retval) { err("pci_hp_register failed with error %d\n", retval); goto error_hpslot; diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c index 648596d469f6..9342c848db29 100644 --- a/drivers/pci/hotplug/acpiphp_glue.c +++ b/drivers/pci/hotplug/acpiphp_glue.c @@ -258,7 +258,12 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv) bridge->pci_bus->number, slot->device); retval = acpiphp_register_hotplug_slot(slot); if (retval) { - warn("acpiphp_register_hotplug_slot failed(err code = 0x%x)\n", retval); + if (retval == -EBUSY) + warn("Slot %d already registered by another " + "hotplug driver\n", slot->sun); + else + warn("acpiphp_register_hotplug_slot failed " + "(err code = 0x%x)\n", retval); goto err_exit; } } @@ -1867,19 +1872,3 @@ u8 acpiphp_get_adapter_status(struct acpiphp_slot *slot) return (sta == 0) ? 0 : 1; } - - -/* - * pci address (seg/bus/dev) - */ -u32 acpiphp_get_address(struct acpiphp_slot *slot) -{ - u32 address; - struct pci_bus *pci_bus = slot->bridge->pci_bus; - - address = (pci_domain_nr(pci_bus) << 16) | - (pci_bus->number << 8) | - slot->device; - - return address; -} diff --git a/drivers/pci/hotplug/acpiphp_ibm.c b/drivers/pci/hotplug/acpiphp_ibm.c index ede9051fdb5d..2b7c45e39370 100644 --- a/drivers/pci/hotplug/acpiphp_ibm.c +++ b/drivers/pci/hotplug/acpiphp_ibm.c @@ -33,8 +33,10 @@ #include #include #include +#include #include "acpiphp.h" +#include "../pci.h" #define DRIVER_VERSION "1.0.1" #define DRIVER_AUTHOR "Irene Zubarev , Vernon Mauery " @@ -430,7 +432,7 @@ static int __init ibm_acpiphp_init(void) int retval = 0; acpi_status status; struct acpi_device *device; - struct kobject *sysdir = &pci_hotplug_slots_kset->kobj; + struct kobject *sysdir = &pci_slots_kset->kobj; dbg("%s\n", __func__); @@ -477,7 +479,7 @@ init_return: static void __exit ibm_acpiphp_exit(void) { acpi_status status; - struct kobject *sysdir = &pci_hotplug_slots_kset->kobj; + struct kobject *sysdir = &pci_slots_kset->kobj; dbg("%s\n", __func__); diff --git a/drivers/pci/hotplug/cpci_hotplug_core.c b/drivers/pci/hotplug/cpci_hotplug_core.c index d8a6b80ab42a..935947991dc9 100644 --- a/drivers/pci/hotplug/cpci_hotplug_core.c +++ b/drivers/pci/hotplug/cpci_hotplug_core.c @@ -285,7 +285,7 @@ cpci_hp_register_bus(struct pci_bus *bus, u8 first, u8 last) info->attention_status = cpci_get_attention_status(slot); dbg("registering slot %s", slot->hotplug_slot->name); - status = pci_hp_register(slot->hotplug_slot); + status = pci_hp_register(slot->hotplug_slot, bus, i); if (status) { err("pci_hp_register failed with error %d", status); goto error_name; diff --git a/drivers/pci/hotplug/cpqphp_core.c b/drivers/pci/hotplug/cpqphp_core.c index 36b115b27b0b..54defec51d08 100644 --- a/drivers/pci/hotplug/cpqphp_core.c +++ b/drivers/pci/hotplug/cpqphp_core.c @@ -434,7 +434,9 @@ static int ctrl_slot_setup(struct controller *ctrl, slot->bus, slot->device, slot->number, ctrl->slot_device_offset, slot_number); - result = pci_hp_register(hotplug_slot); + result = pci_hp_register(hotplug_slot, + ctrl->pci_dev->subordinate, + slot->device); if (result) { err("pci_hp_register failed with error %d\n", result); goto error_name; diff --git a/drivers/pci/hotplug/fakephp.c b/drivers/pci/hotplug/fakephp.c index b57223f7e830..40337a06c18a 100644 --- a/drivers/pci/hotplug/fakephp.c +++ b/drivers/pci/hotplug/fakephp.c @@ -126,7 +126,7 @@ static int add_slot(struct pci_dev *dev) slot->release = &dummy_release; slot->private = dslot; - retval = pci_hp_register(slot); + retval = pci_hp_register(slot, dev->bus, PCI_SLOT(dev->devfn)); if (retval) { err("pci_hp_register failed with error %d\n", retval); goto error_dslot; diff --git a/drivers/pci/hotplug/ibmphp_ebda.c b/drivers/pci/hotplug/ibmphp_ebda.c index dca7efc14be2..8467d0287325 100644 --- a/drivers/pci/hotplug/ibmphp_ebda.c +++ b/drivers/pci/hotplug/ibmphp_ebda.c @@ -1001,7 +1001,8 @@ static int __init ebda_rsrc_controller (void) tmp_slot = list_entry (list, struct slot, ibm_slot_list); snprintf (tmp_slot->hotplug_slot->name, 30, "%s", create_file_name (tmp_slot)); - pci_hp_register (tmp_slot->hotplug_slot); + pci_hp_register(tmp_slot->hotplug_slot, + pci_find_bus(0, tmp_slot->bus), tmp_slot->device); } print_ebda_hpc (); diff --git a/drivers/pci/hotplug/pci_hotplug_core.c b/drivers/pci/hotplug/pci_hotplug_core.c index a11021e8ce37..4df31f375197 100644 --- a/drivers/pci/hotplug/pci_hotplug_core.c +++ b/drivers/pci/hotplug/pci_hotplug_core.c @@ -40,6 +40,7 @@ #include #include #include +#include "../pci.h" #define MY_NAME "pci_hotplug" @@ -60,41 +61,7 @@ static int debug; ////////////////////////////////////////////////////////////////// static LIST_HEAD(pci_hotplug_slot_list); - -struct kset *pci_hotplug_slots_kset; - -static ssize_t hotplug_slot_attr_show(struct kobject *kobj, - struct attribute *attr, char *buf) -{ - struct hotplug_slot *slot = to_hotplug_slot(kobj); - struct hotplug_slot_attribute *attribute = to_hotplug_attr(attr); - return attribute->show ? attribute->show(slot, buf) : -EIO; -} - -static ssize_t hotplug_slot_attr_store(struct kobject *kobj, - struct attribute *attr, const char *buf, size_t len) -{ - struct hotplug_slot *slot = to_hotplug_slot(kobj); - struct hotplug_slot_attribute *attribute = to_hotplug_attr(attr); - return attribute->store ? attribute->store(slot, buf, len) : -EIO; -} - -static struct sysfs_ops hotplug_slot_sysfs_ops = { - .show = hotplug_slot_attr_show, - .store = hotplug_slot_attr_store, -}; - -static void hotplug_slot_release(struct kobject *kobj) -{ - struct hotplug_slot *slot = to_hotplug_slot(kobj); - if (slot->release) - slot->release(slot); -} - -static struct kobj_type hotplug_slot_ktype = { - .sysfs_ops = &hotplug_slot_sysfs_ops, - .release = &hotplug_slot_release, -}; +static DEFINE_SPINLOCK(pci_hotplug_slot_list_lock); /* these strings match up with the values in pci_bus_speed */ static char *pci_bus_speed_strings[] = { @@ -149,16 +116,15 @@ GET_STATUS(power_status, u8) GET_STATUS(attention_status, u8) GET_STATUS(latch_status, u8) GET_STATUS(adapter_status, u8) -GET_STATUS(address, u32) GET_STATUS(max_bus_speed, enum pci_bus_speed) GET_STATUS(cur_bus_speed, enum pci_bus_speed) -static ssize_t power_read_file (struct hotplug_slot *slot, char *buf) +static ssize_t power_read_file(struct pci_slot *slot, char *buf) { int retval; u8 value; - retval = get_power_status (slot, &value); + retval = get_power_status(slot->hotplug, &value); if (retval) goto exit; retval = sprintf (buf, "%d\n", value); @@ -166,9 +132,10 @@ exit: return retval; } -static ssize_t power_write_file (struct hotplug_slot *slot, const char *buf, +static ssize_t power_write_file(struct pci_slot *pci_slot, const char *buf, size_t count) { + struct hotplug_slot *slot = pci_slot->hotplug; unsigned long lpower; u8 power; int retval = 0; @@ -204,29 +171,30 @@ exit: return count; } -static struct hotplug_slot_attribute hotplug_slot_attr_power = { +static struct pci_slot_attribute hotplug_slot_attr_power = { .attr = {.name = "power", .mode = S_IFREG | S_IRUGO | S_IWUSR}, .show = power_read_file, .store = power_write_file }; -static ssize_t attention_read_file (struct hotplug_slot *slot, char *buf) +static ssize_t attention_read_file(struct pci_slot *slot, char *buf) { int retval; u8 value; - retval = get_attention_status (slot, &value); + retval = get_attention_status(slot->hotplug, &value); if (retval) goto exit; - retval = sprintf (buf, "%d\n", value); + retval = sprintf(buf, "%d\n", value); exit: return retval; } -static ssize_t attention_write_file (struct hotplug_slot *slot, const char *buf, +static ssize_t attention_write_file(struct pci_slot *slot, const char *buf, size_t count) { + struct hotplug_slot_ops *ops = slot->hotplug->ops; unsigned long lattention; u8 attention; int retval = 0; @@ -235,13 +203,13 @@ static ssize_t attention_write_file (struct hotplug_slot *slot, const char *buf, attention = (u8)(lattention & 0xff); dbg (" - attention = %d\n", attention); - if (!try_module_get(slot->ops->owner)) { + if (!try_module_get(ops->owner)) { retval = -ENODEV; goto exit; } - if (slot->ops->set_attention_status) - retval = slot->ops->set_attention_status(slot, attention); - module_put(slot->ops->owner); + if (ops->set_attention_status) + retval = ops->set_attention_status(slot->hotplug, attention); + module_put(ops->owner); exit: if (retval) @@ -249,18 +217,18 @@ exit: return count; } -static struct hotplug_slot_attribute hotplug_slot_attr_attention = { +static struct pci_slot_attribute hotplug_slot_attr_attention = { .attr = {.name = "attention", .mode = S_IFREG | S_IRUGO | S_IWUSR}, .show = attention_read_file, .store = attention_write_file }; -static ssize_t latch_read_file (struct hotplug_slot *slot, char *buf) +static ssize_t latch_read_file(struct pci_slot *slot, char *buf) { int retval; u8 value; - retval = get_latch_status (slot, &value); + retval = get_latch_status(slot->hotplug, &value); if (retval) goto exit; retval = sprintf (buf, "%d\n", value); @@ -269,17 +237,17 @@ exit: return retval; } -static struct hotplug_slot_attribute hotplug_slot_attr_latch = { +static struct pci_slot_attribute hotplug_slot_attr_latch = { .attr = {.name = "latch", .mode = S_IFREG | S_IRUGO}, .show = latch_read_file, }; -static ssize_t presence_read_file (struct hotplug_slot *slot, char *buf) +static ssize_t presence_read_file(struct pci_slot *slot, char *buf) { int retval; u8 value; - retval = get_adapter_status (slot, &value); + retval = get_adapter_status(slot->hotplug, &value); if (retval) goto exit; retval = sprintf (buf, "%d\n", value); @@ -288,42 +256,20 @@ exit: return retval; } -static struct hotplug_slot_attribute hotplug_slot_attr_presence = { +static struct pci_slot_attribute hotplug_slot_attr_presence = { .attr = {.name = "adapter", .mode = S_IFREG | S_IRUGO}, .show = presence_read_file, }; -static ssize_t address_read_file (struct hotplug_slot *slot, char *buf) -{ - int retval; - u32 address; - - retval = get_address (slot, &address); - if (retval) - goto exit; - retval = sprintf (buf, "%04x:%02x:%02x\n", - (address >> 16) & 0xffff, - (address >> 8) & 0xff, - address & 0xff); - -exit: - return retval; -} - -static struct hotplug_slot_attribute hotplug_slot_attr_address = { - .attr = {.name = "address", .mode = S_IFREG | S_IRUGO}, - .show = address_read_file, -}; - static char *unknown_speed = "Unknown bus speed"; -static ssize_t max_bus_speed_read_file (struct hotplug_slot *slot, char *buf) +static ssize_t max_bus_speed_read_file(struct pci_slot *slot, char *buf) { char *speed_string; int retval; enum pci_bus_speed value; - retval = get_max_bus_speed (slot, &value); + retval = get_max_bus_speed(slot->hotplug, &value); if (retval) goto exit; @@ -338,18 +284,18 @@ exit: return retval; } -static struct hotplug_slot_attribute hotplug_slot_attr_max_bus_speed = { +static struct pci_slot_attribute hotplug_slot_attr_max_bus_speed = { .attr = {.name = "max_bus_speed", .mode = S_IFREG | S_IRUGO}, .show = max_bus_speed_read_file, }; -static ssize_t cur_bus_speed_read_file (struct hotplug_slot *slot, char *buf) +static ssize_t cur_bus_speed_read_file(struct pci_slot *slot, char *buf) { char *speed_string; int retval; enum pci_bus_speed value; - retval = get_cur_bus_speed (slot, &value); + retval = get_cur_bus_speed(slot->hotplug, &value); if (retval) goto exit; @@ -364,14 +310,15 @@ exit: return retval; } -static struct hotplug_slot_attribute hotplug_slot_attr_cur_bus_speed = { +static struct pci_slot_attribute hotplug_slot_attr_cur_bus_speed = { .attr = {.name = "cur_bus_speed", .mode = S_IFREG | S_IRUGO}, .show = cur_bus_speed_read_file, }; -static ssize_t test_write_file (struct hotplug_slot *slot, const char *buf, +static ssize_t test_write_file(struct pci_slot *pci_slot, const char *buf, size_t count) { + struct hotplug_slot *slot = pci_slot->hotplug; unsigned long ltest; u32 test; int retval = 0; @@ -394,13 +341,14 @@ exit: return count; } -static struct hotplug_slot_attribute hotplug_slot_attr_test = { +static struct pci_slot_attribute hotplug_slot_attr_test = { .attr = {.name = "test", .mode = S_IFREG | S_IRUGO | S_IWUSR}, .store = test_write_file }; -static int has_power_file (struct hotplug_slot *slot) +static int has_power_file(struct pci_slot *pci_slot) { + struct hotplug_slot *slot = pci_slot->hotplug; if ((!slot) || (!slot->ops)) return -ENODEV; if ((slot->ops->enable_slot) || @@ -410,8 +358,9 @@ static int has_power_file (struct hotplug_slot *slot) return -ENOENT; } -static int has_attention_file (struct hotplug_slot *slot) +static int has_attention_file(struct pci_slot *pci_slot) { + struct hotplug_slot *slot = pci_slot->hotplug; if ((!slot) || (!slot->ops)) return -ENODEV; if ((slot->ops->set_attention_status) || @@ -420,8 +369,9 @@ static int has_attention_file (struct hotplug_slot *slot) return -ENOENT; } -static int has_latch_file (struct hotplug_slot *slot) +static int has_latch_file(struct pci_slot *pci_slot) { + struct hotplug_slot *slot = pci_slot->hotplug; if ((!slot) || (!slot->ops)) return -ENODEV; if (slot->ops->get_latch_status) @@ -429,8 +379,9 @@ static int has_latch_file (struct hotplug_slot *slot) return -ENOENT; } -static int has_adapter_file (struct hotplug_slot *slot) +static int has_adapter_file(struct pci_slot *pci_slot) { + struct hotplug_slot *slot = pci_slot->hotplug; if ((!slot) || (!slot->ops)) return -ENODEV; if (slot->ops->get_adapter_status) @@ -438,17 +389,9 @@ static int has_adapter_file (struct hotplug_slot *slot) return -ENOENT; } -static int has_address_file (struct hotplug_slot *slot) -{ - if ((!slot) || (!slot->ops)) - return -ENODEV; - if (slot->ops->get_address) - return 0; - return -ENOENT; -} - -static int has_max_bus_speed_file (struct hotplug_slot *slot) +static int has_max_bus_speed_file(struct pci_slot *pci_slot) { + struct hotplug_slot *slot = pci_slot->hotplug; if ((!slot) || (!slot->ops)) return -ENODEV; if (slot->ops->get_max_bus_speed) @@ -456,8 +399,9 @@ static int has_max_bus_speed_file (struct hotplug_slot *slot) return -ENOENT; } -static int has_cur_bus_speed_file (struct hotplug_slot *slot) +static int has_cur_bus_speed_file(struct pci_slot *pci_slot) { + struct hotplug_slot *slot = pci_slot->hotplug; if ((!slot) || (!slot->ops)) return -ENODEV; if (slot->ops->get_cur_bus_speed) @@ -465,8 +409,9 @@ static int has_cur_bus_speed_file (struct hotplug_slot *slot) return -ENOENT; } -static int has_test_file (struct hotplug_slot *slot) +static int has_test_file(struct pci_slot *pci_slot) { + struct hotplug_slot *slot = pci_slot->hotplug; if ((!slot) || (!slot->ops)) return -ENODEV; if (slot->ops->hardware_test) @@ -474,7 +419,7 @@ static int has_test_file (struct hotplug_slot *slot) return -ENOENT; } -static int fs_add_slot (struct hotplug_slot *slot) +static int fs_add_slot(struct pci_slot *slot) { int retval = 0; @@ -505,13 +450,6 @@ static int fs_add_slot (struct hotplug_slot *slot) goto exit_adapter; } - if (has_address_file(slot) == 0) { - retval = sysfs_create_file(&slot->kobj, - &hotplug_slot_attr_address.attr); - if (retval) - goto exit_address; - } - if (has_max_bus_speed_file(slot) == 0) { retval = sysfs_create_file(&slot->kobj, &hotplug_slot_attr_max_bus_speed.attr); @@ -544,10 +482,6 @@ exit_cur_speed: sysfs_remove_file(&slot->kobj, &hotplug_slot_attr_max_bus_speed.attr); exit_max_speed: - if (has_address_file(slot) == 0) - sysfs_remove_file(&slot->kobj, &hotplug_slot_attr_address.attr); - -exit_address: if (has_adapter_file(slot) == 0) sysfs_remove_file(&slot->kobj, &hotplug_slot_attr_presence.attr); @@ -567,7 +501,7 @@ exit: return retval; } -static void fs_remove_slot (struct hotplug_slot *slot) +static void fs_remove_slot(struct pci_slot *slot) { if (has_power_file(slot) == 0) sysfs_remove_file(&slot->kobj, &hotplug_slot_attr_power.attr); @@ -581,9 +515,6 @@ static void fs_remove_slot (struct hotplug_slot *slot) if (has_adapter_file(slot) == 0) sysfs_remove_file(&slot->kobj, &hotplug_slot_attr_presence.attr); - if (has_address_file(slot) == 0) - sysfs_remove_file(&slot->kobj, &hotplug_slot_attr_address.attr); - if (has_max_bus_speed_file(slot) == 0) sysfs_remove_file(&slot->kobj, &hotplug_slot_attr_max_bus_speed.attr); @@ -599,12 +530,16 @@ static struct hotplug_slot *get_slot_from_name (const char *name) struct hotplug_slot *slot; struct list_head *tmp; + spin_lock(&pci_hotplug_slot_list_lock); list_for_each (tmp, &pci_hotplug_slot_list) { slot = list_entry (tmp, struct hotplug_slot, slot_list); if (strcmp(slot->name, name) == 0) - return slot; + goto out; } - return NULL; + slot = NULL; +out: + spin_unlock(&pci_hotplug_slot_list_lock); + return slot; } /** @@ -616,9 +551,10 @@ static struct hotplug_slot *get_slot_from_name (const char *name) * * Returns 0 if successful, anything else for an error. */ -int pci_hp_register (struct hotplug_slot *slot) +int pci_hp_register(struct hotplug_slot *slot, struct pci_bus *bus, int slot_nr) { int result; + struct pci_slot *pci_slot; struct hotplug_slot *tmp; if (slot == NULL) @@ -636,19 +572,28 @@ int pci_hp_register (struct hotplug_slot *slot) if (tmp) return -EEXIST; - slot->kobj.kset = pci_hotplug_slots_kset; - result = kobject_init_and_add(&slot->kobj, &hotplug_slot_ktype, NULL, - "%s", slot->name); - if (result) { - err("Unable to register kobject '%s'", slot->name); - return -EINVAL; + pci_slot = pci_create_slot(bus, slot_nr, slot->name); + if (IS_ERR(pci_slot)) + return PTR_ERR(pci_slot); + + if (pci_slot->hotplug) { + dbg("%s: already claimed\n", __func__); + pci_destroy_slot(pci_slot); + return -EBUSY; } - list_add (&slot->slot_list, &pci_hotplug_slot_list); + slot->pci_slot = pci_slot; + pci_slot->hotplug = slot; + + spin_lock(&pci_hotplug_slot_list_lock); + list_add(&slot->slot_list, &pci_hotplug_slot_list); + spin_unlock(&pci_hotplug_slot_list_lock); + + result = fs_add_slot(pci_slot); + kobject_uevent(&pci_slot->kobj, KOBJ_ADD); + dbg("Added slot %s to the list\n", slot->name); + - result = fs_add_slot (slot); - kobject_uevent(&slot->kobj, KOBJ_ADD); - dbg ("Added slot %s to the list\n", slot->name); return result; } @@ -661,22 +606,30 @@ int pci_hp_register (struct hotplug_slot *slot) * * Returns 0 if successful, anything else for an error. */ -int pci_hp_deregister (struct hotplug_slot *slot) +int pci_hp_deregister(struct hotplug_slot *hotplug) { struct hotplug_slot *temp; + struct pci_slot *slot; - if (slot == NULL) + if (!hotplug) return -ENODEV; - temp = get_slot_from_name (slot->name); - if (temp != slot) { + temp = get_slot_from_name(hotplug->name); + if (temp != hotplug) return -ENODEV; - } - list_del (&slot->slot_list); - fs_remove_slot (slot); - dbg ("Removed slot %s from the list\n", slot->name); - kobject_put(&slot->kobj); + spin_lock(&pci_hotplug_slot_list_lock); + list_del(&hotplug->slot_list); + spin_unlock(&pci_hotplug_slot_list_lock); + + slot = hotplug->pci_slot; + fs_remove_slot(slot); + dbg("Removed slot %s from the list\n", hotplug->name); + + hotplug->release(hotplug); + slot->hotplug = NULL; + pci_destroy_slot(slot); + return 0; } @@ -690,13 +643,15 @@ int pci_hp_deregister (struct hotplug_slot *slot) * * Returns 0 if successful, anything else for an error. */ -int __must_check pci_hp_change_slot_info(struct hotplug_slot *slot, +int __must_check pci_hp_change_slot_info(struct hotplug_slot *hotplug, struct hotplug_slot_info *info) { - if ((slot == NULL) || (info == NULL)) + struct pci_slot *slot; + if (!hotplug || !info) return -ENODEV; + slot = hotplug->pci_slot; - memcpy (slot->info, info, sizeof (struct hotplug_slot_info)); + memcpy(hotplug->info, info, sizeof(struct hotplug_slot_info)); return 0; } @@ -704,36 +659,22 @@ int __must_check pci_hp_change_slot_info(struct hotplug_slot *slot, static int __init pci_hotplug_init (void) { int result; - struct kset *pci_bus_kset; - pci_bus_kset = bus_get_kset(&pci_bus_type); - - pci_hotplug_slots_kset = kset_create_and_add("slots", NULL, - &pci_bus_kset->kobj); - if (!pci_hotplug_slots_kset) { - result = -ENOMEM; - err("Register subsys error\n"); - goto exit; - } result = cpci_hotplug_init(debug); if (result) { err ("cpci_hotplug_init with error %d\n", result); - goto err_subsys; + goto err_cpci; } info (DRIVER_DESC " version: " DRIVER_VERSION "\n"); - goto exit; -err_subsys: - kset_unregister(pci_hotplug_slots_kset); -exit: +err_cpci: return result; } static void __exit pci_hotplug_exit (void) { cpci_hotplug_exit(); - kset_unregister(pci_hotplug_slots_kset); } module_init(pci_hotplug_init); @@ -745,7 +686,6 @@ MODULE_LICENSE("GPL"); module_param(debug, bool, 0644); MODULE_PARM_DESC(debug, "Debugging mode enabled or not"); -EXPORT_SYMBOL_GPL(pci_hotplug_slots_kset); EXPORT_SYMBOL_GPL(pci_hp_register); EXPORT_SYMBOL_GPL(pci_hp_deregister); EXPORT_SYMBOL_GPL(pci_hp_change_slot_info); diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c index 49414e9100de..7b21c86e4bff 100644 --- a/drivers/pci/hotplug/pciehp_core.c +++ b/drivers/pci/hotplug/pciehp_core.c @@ -72,7 +72,6 @@ static int get_power_status (struct hotplug_slot *slot, u8 *value); static int get_attention_status (struct hotplug_slot *slot, u8 *value); static int get_latch_status (struct hotplug_slot *slot, u8 *value); static int get_adapter_status (struct hotplug_slot *slot, u8 *value); -static int get_address (struct hotplug_slot *slot, u32 *value); static int get_max_bus_speed (struct hotplug_slot *slot, enum pci_bus_speed *value); static int get_cur_bus_speed (struct hotplug_slot *slot, enum pci_bus_speed *value); @@ -85,7 +84,6 @@ static struct hotplug_slot_ops pciehp_hotplug_slot_ops = { .get_attention_status = get_attention_status, .get_latch_status = get_latch_status, .get_adapter_status = get_adapter_status, - .get_address = get_address, .get_max_bus_speed = get_max_bus_speed, .get_cur_bus_speed = get_cur_bus_speed, }; @@ -252,7 +250,9 @@ static int init_slots(struct controller *ctrl) dbg("Registering bus=%x dev=%x hp_slot=%x sun=%x " "slot_device_offset=%x\n", slot->bus, slot->device, slot->hp_slot, slot->number, ctrl->slot_device_offset); - retval = pci_hp_register(hotplug_slot); + retval = pci_hp_register(hotplug_slot, + ctrl->pci_dev->subordinate, + slot->device); if (retval) { err("pci_hp_register failed with error %d\n", retval); if (retval == -EEXIST) @@ -263,7 +263,7 @@ static int init_slots(struct controller *ctrl) } /* create additional sysfs entries */ if (EMI(ctrl)) { - retval = sysfs_create_file(&hotplug_slot->kobj, + retval = sysfs_create_file(&hotplug_slot->pci_slot->kobj, &hotplug_slot_attr_lock.attr); if (retval) { pci_hp_deregister(hotplug_slot); @@ -296,7 +296,7 @@ static void cleanup_slots(struct controller *ctrl) slot = list_entry(tmp, struct slot, slot_list); list_del(&slot->slot_list); if (EMI(ctrl)) - sysfs_remove_file(&slot->hotplug_slot->kobj, + sysfs_remove_file(&slot->hotplug_slot->pci_slot->kobj, &hotplug_slot_attr_lock.attr); cancel_delayed_work(&slot->work); flush_scheduled_work(); @@ -398,19 +398,8 @@ static int get_adapter_status(struct hotplug_slot *hotplug_slot, u8 *value) return 0; } -static int get_address(struct hotplug_slot *hotplug_slot, u32 *value) -{ - struct slot *slot = hotplug_slot->private; - struct pci_bus *bus = slot->ctrl->pci_dev->subordinate; - - dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name); - - *value = (pci_domain_nr(bus) << 16) | (slot->bus << 8) | slot->device; - - return 0; -} - -static int get_max_bus_speed(struct hotplug_slot *hotplug_slot, enum pci_bus_speed *value) +static int get_max_bus_speed(struct hotplug_slot *hotplug_slot, + enum pci_bus_speed *value) { struct slot *slot = hotplug_slot->private; int retval; @@ -474,7 +463,12 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_ /* Setup the slot information structures */ rc = init_slots(ctrl); if (rc) { - err("%s: slot initialization failed\n", PCIE_MODULE_NAME); + if (rc == -EBUSY) + warn("%s: slot already registered by another " + "hotplug driver\n", PCIE_MODULE_NAME); + else + err("%s: slot initialization failed\n", + PCIE_MODULE_NAME); goto err_out_release_ctlr; } diff --git a/drivers/pci/hotplug/rpadlpar_sysfs.c b/drivers/pci/hotplug/rpadlpar_sysfs.c index 779c5db71be4..a796301ea03f 100644 --- a/drivers/pci/hotplug/rpadlpar_sysfs.c +++ b/drivers/pci/hotplug/rpadlpar_sysfs.c @@ -14,8 +14,10 @@ */ #include #include +#include #include #include "rpadlpar.h" +#include "../pci.h" #define DLPAR_KOBJ_NAME "control" @@ -27,7 +29,6 @@ #define MAX_DRC_NAME_LEN 64 - static ssize_t add_slot_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t nbytes) { @@ -112,7 +113,7 @@ int dlpar_sysfs_init(void) int error; dlpar_kobj = kobject_create_and_add(DLPAR_KOBJ_NAME, - &pci_hotplug_slots_kset->kobj); + &pci_slots_kset->kobj); if (!dlpar_kobj) return -EINVAL; diff --git a/drivers/pci/hotplug/rpaphp_slot.c b/drivers/pci/hotplug/rpaphp_slot.c index 56197b600d36..9b714ea93d20 100644 --- a/drivers/pci/hotplug/rpaphp_slot.c +++ b/drivers/pci/hotplug/rpaphp_slot.c @@ -33,33 +33,6 @@ #include #include "rpaphp.h" -static ssize_t address_read_file (struct hotplug_slot *php_slot, char *buf) -{ - int retval; - struct slot *slot = (struct slot *)php_slot->private; - struct pci_bus *bus; - - if (!slot) - return -ENOENT; - - bus = slot->bus; - if (!bus) - return -ENOENT; - - if (bus->self) - retval = sprintf(buf, pci_name(bus->self)); - else - retval = sprintf(buf, "%04x:%02x:00.0", - pci_domain_nr(bus), bus->number); - - return retval; -} - -static struct hotplug_slot_attribute php_attr_address = { - .attr = {.name = "address", .mode = S_IFREG | S_IRUGO}, - .show = address_read_file, -}; - /* free up the memory used by a slot */ static void rpaphp_release_slot(struct hotplug_slot *hotplug_slot) { @@ -135,9 +108,6 @@ int rpaphp_deregister_slot(struct slot *slot) list_del(&slot->rpaphp_slot_list); - /* remove "address" file */ - sysfs_remove_file(&php_slot->kobj, &php_attr_address.attr); - retval = pci_hp_deregister(php_slot); if (retval) err("Problem unregistering a slot %s\n", slot->name); @@ -151,6 +121,7 @@ int rpaphp_register_slot(struct slot *slot) { struct hotplug_slot *php_slot = slot->hotplug_slot; int retval; + int slotno; dbg("%s registering slot:path[%s] index[%x], name[%s] pdomain[%x] type[%d]\n", __func__, slot->dn->full_name, slot->index, slot->name, @@ -162,19 +133,16 @@ int rpaphp_register_slot(struct slot *slot) return -EAGAIN; } - retval = pci_hp_register(php_slot); + if (slot->dn->child) + slotno = PCI_SLOT(PCI_DN(slot->dn->child)->devfn); + else + slotno = -1; + retval = pci_hp_register(php_slot, slot->bus, slotno); if (retval) { err("pci_hp_register failed with error %d\n", retval); return retval; } - /* create "address" file */ - retval = sysfs_create_file(&php_slot->kobj, &php_attr_address.attr); - if (retval) { - err("sysfs_create_file failed with error %d\n", retval); - goto sysfs_fail; - } - /* add slot to our internal list */ list_add(&slot->rpaphp_slot_list, &rpaphp_slot_head); info("Slot [%s] registered\n", slot->name); diff --git a/drivers/pci/hotplug/sgi_hotplug.c b/drivers/pci/hotplug/sgi_hotplug.c index 2fe37cd85b69..2036a43ff2fd 100644 --- a/drivers/pci/hotplug/sgi_hotplug.c +++ b/drivers/pci/hotplug/sgi_hotplug.c @@ -197,13 +197,15 @@ static int sn_hp_slot_private_alloc(struct hotplug_slot *bss_hotplug_slot, static struct hotplug_slot * sn_hp_destroy(void) { struct slot *slot; + struct pci_slot *pci_slot; struct hotplug_slot *bss_hotplug_slot = NULL; list_for_each_entry(slot, &sn_hp_list, hp_list) { bss_hotplug_slot = slot->hotplug_slot; + pci_slot = bss_hotplug_slot->pci_slot; list_del(&((struct slot *)bss_hotplug_slot->private)-> hp_list); - sysfs_remove_file(&bss_hotplug_slot->kobj, + sysfs_remove_file(&pci_slot->kobj, &sn_slot_path_attr.attr); break; } @@ -614,6 +616,7 @@ static void sn_release_slot(struct hotplug_slot *bss_hotplug_slot) static int sn_hotplug_slot_register(struct pci_bus *pci_bus) { int device; + struct pci_slot *pci_slot; struct hotplug_slot *bss_hotplug_slot; int rc = 0; @@ -650,11 +653,12 @@ static int sn_hotplug_slot_register(struct pci_bus *pci_bus) bss_hotplug_slot->ops = &sn_hotplug_slot_ops; bss_hotplug_slot->release = &sn_release_slot; - rc = pci_hp_register(bss_hotplug_slot); + rc = pci_hp_register(bss_hotplug_slot, pci_bus, device); if (rc) goto register_err; - rc = sysfs_create_file(&bss_hotplug_slot->kobj, + pci_slot = bss_hotplug_slot->pci_slot; + rc = sysfs_create_file(&pci_slot->kobj, &sn_slot_path_attr.attr); if (rc) goto register_err; diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c index df41ecc4e7fc..a8cbd039b85b 100644 --- a/drivers/pci/hotplug/shpchp_core.c +++ b/drivers/pci/hotplug/shpchp_core.c @@ -68,7 +68,6 @@ static int get_power_status (struct hotplug_slot *slot, u8 *value); static int get_attention_status (struct hotplug_slot *slot, u8 *value); static int get_latch_status (struct hotplug_slot *slot, u8 *value); static int get_adapter_status (struct hotplug_slot *slot, u8 *value); -static int get_address (struct hotplug_slot *slot, u32 *value); static int get_max_bus_speed (struct hotplug_slot *slot, enum pci_bus_speed *value); static int get_cur_bus_speed (struct hotplug_slot *slot, enum pci_bus_speed *value); @@ -81,7 +80,6 @@ static struct hotplug_slot_ops shpchp_hotplug_slot_ops = { .get_attention_status = get_attention_status, .get_latch_status = get_latch_status, .get_adapter_status = get_adapter_status, - .get_address = get_address, .get_max_bus_speed = get_max_bus_speed, .get_cur_bus_speed = get_cur_bus_speed, }; @@ -159,7 +157,8 @@ static int init_slots(struct controller *ctrl) dbg("Registering bus=%x dev=%x hp_slot=%x sun=%x " "slot_device_offset=%x\n", slot->bus, slot->device, slot->hp_slot, slot->number, ctrl->slot_device_offset); - retval = pci_hp_register(slot->hotplug_slot); + retval = pci_hp_register(slot->hotplug_slot, + ctrl->pci_dev->subordinate, slot->device); if (retval) { err("pci_hp_register failed with error %d\n", retval); if (retval == -EEXIST) @@ -288,19 +287,8 @@ static int get_adapter_status (struct hotplug_slot *hotplug_slot, u8 *value) return 0; } -static int get_address (struct hotplug_slot *hotplug_slot, u32 *value) -{ - struct slot *slot = get_slot(hotplug_slot); - struct pci_bus *bus = slot->ctrl->pci_dev->subordinate; - - dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name); - - *value = (pci_domain_nr(bus) << 16) | (slot->bus << 8) | slot->device; - - return 0; -} - -static int get_max_bus_speed (struct hotplug_slot *hotplug_slot, enum pci_bus_speed *value) +static int get_max_bus_speed(struct hotplug_slot *hotplug_slot, + enum pci_bus_speed *value) { struct slot *slot = get_slot(hotplug_slot); int retval; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0a497c1b4227..e1d7bbf079b4 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -106,3 +106,16 @@ pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) } struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); + +/* PCI slot sysfs helper code */ +#define to_pci_slot(s) container_of(s, struct pci_slot, kobj) + +extern struct kset *pci_slots_kset; + +struct pci_slot_attribute { + struct attribute attr; + ssize_t (*show)(struct pci_slot *, char *); + ssize_t (*store)(struct pci_slot *, const char *, size_t); +}; +#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) + diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index aebab71abebf..4562827b7e22 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -414,6 +414,7 @@ static struct pci_bus * pci_alloc_bus(void) INIT_LIST_HEAD(&b->node); INIT_LIST_HEAD(&b->children); INIT_LIST_HEAD(&b->devices); + INIT_LIST_HEAD(&b->slots); } return b; } diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c new file mode 100644 index 000000000000..7e5b85cbd948 --- /dev/null +++ b/drivers/pci/slot.c @@ -0,0 +1,233 @@ +/* + * drivers/pci/slot.c + * Copyright (C) 2006 Matthew Wilcox + * Copyright (C) 2006-2008 Hewlett-Packard Development Company, L.P. + * Alex Chiang + */ + +#include +#include +#include +#include "pci.h" + +struct kset *pci_slots_kset; +EXPORT_SYMBOL_GPL(pci_slots_kset); + +static ssize_t pci_slot_attr_show(struct kobject *kobj, + struct attribute *attr, char *buf) +{ + struct pci_slot *slot = to_pci_slot(kobj); + struct pci_slot_attribute *attribute = to_pci_slot_attr(attr); + return attribute->show ? attribute->show(slot, buf) : -EIO; +} + +static ssize_t pci_slot_attr_store(struct kobject *kobj, + struct attribute *attr, const char *buf, size_t len) +{ + struct pci_slot *slot = to_pci_slot(kobj); + struct pci_slot_attribute *attribute = to_pci_slot_attr(attr); + return attribute->store ? attribute->store(slot, buf, len) : -EIO; +} + +static struct sysfs_ops pci_slot_sysfs_ops = { + .show = pci_slot_attr_show, + .store = pci_slot_attr_store, +}; + +static ssize_t address_read_file(struct pci_slot *slot, char *buf) +{ + if (slot->number == 0xff) + return sprintf(buf, "%04x:%02x\n", + pci_domain_nr(slot->bus), + slot->bus->number); + else + return sprintf(buf, "%04x:%02x:%02x\n", + pci_domain_nr(slot->bus), + slot->bus->number, + slot->number); +} + +static void pci_slot_release(struct kobject *kobj) +{ + struct pci_slot *slot = to_pci_slot(kobj); + + pr_debug("%s: releasing pci_slot on %x:%d\n", __func__, + slot->bus->number, slot->number); + + list_del(&slot->list); + + kfree(slot); +} + +static struct pci_slot_attribute pci_slot_attr_address = + __ATTR(address, (S_IFREG | S_IRUGO), address_read_file, NULL); + +static struct attribute *pci_slot_default_attrs[] = { + &pci_slot_attr_address.attr, + NULL, +}; + +static struct kobj_type pci_slot_ktype = { + .sysfs_ops = &pci_slot_sysfs_ops, + .release = &pci_slot_release, + .default_attrs = pci_slot_default_attrs, +}; + +/** + * pci_create_slot - create or increment refcount for physical PCI slot + * @parent: struct pci_bus of parent bridge + * @slot_nr: PCI_SLOT(pci_dev->devfn) or -1 for placeholder + * @name: user visible string presented in /sys/bus/pci/slots/ + * + * PCI slots have first class attributes such as address, speed, width, + * and a &struct pci_slot is used to manage them. This interface will + * either return a new &struct pci_slot to the caller, or if the pci_slot + * already exists, its refcount will be incremented. + * + * Slots are uniquely identified by a @pci_bus, @slot_nr, @name tuple. + * + * Placeholder slots: + * In most cases, @pci_bus, @slot_nr will be sufficient to uniquely identify + * a slot. There is one notable exception - pSeries (rpaphp), where the + * @slot_nr cannot be determined until a device is actually inserted into + * the slot. In this scenario, the caller may pass -1 for @slot_nr. + * + * The following semantics are imposed when the caller passes @slot_nr == + * -1. First, the check for existing %struct pci_slot is skipped, as the + * caller may know about several unpopulated slots on a given %struct + * pci_bus, and each slot would have a @slot_nr of -1. Uniqueness for + * these slots is then determined by the @name parameter. We expect + * kobject_init_and_add() to warn us if the caller attempts to create + * multiple slots with the same name. The other change in semantics is + * user-visible, which is the 'address' parameter presented in sysfs will + * consist solely of a dddd:bb tuple, where dddd is the PCI domain of the + * %struct pci_bus and bb is the bus number. In other words, the devfn of + * the 'placeholder' slot will not be displayed. + */ + +struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, + const char *name) +{ + struct pci_slot *slot; + int err; + + down_write(&pci_bus_sem); + + if (slot_nr == -1) + goto placeholder; + + /* If we've already created this slot, bump refcount and return. */ + list_for_each_entry(slot, &parent->slots, list) { + if (slot->number == slot_nr) { + kobject_get(&slot->kobj); + pr_debug("%s: inc refcount to %d on %04x:%02x:%02x\n", + __func__, + atomic_read(&slot->kobj.kref.refcount), + pci_domain_nr(parent), parent->number, + slot_nr); + goto out; + } + } + +placeholder: + slot = kzalloc(sizeof(*slot), GFP_KERNEL); + if (!slot) { + slot = ERR_PTR(-ENOMEM); + goto out; + } + + slot->bus = parent; + slot->number = slot_nr; + + slot->kobj.kset = pci_slots_kset; + err = kobject_init_and_add(&slot->kobj, &pci_slot_ktype, NULL, + "%s", name); + if (err) { + printk(KERN_ERR "Unable to register kobject %s\n", name); + goto err; + } + + INIT_LIST_HEAD(&slot->list); + list_add(&slot->list, &parent->slots); + + /* Don't care if debug printk has a -1 for slot_nr */ + pr_debug("%s: created pci_slot on %04x:%02x:%02x\n", + __func__, pci_domain_nr(parent), parent->number, slot_nr); + + out: + up_write(&pci_bus_sem); + return slot; + err: + kfree(slot); + slot = ERR_PTR(err); + goto out; +} +EXPORT_SYMBOL_GPL(pci_create_slot); + +/** + * pci_update_slot_number - update %struct pci_slot -> number + * @slot - %struct pci_slot to update + * @slot_nr - new number for slot + * + * The primary purpose of this interface is to allow callers who earlier + * created a placeholder slot in pci_create_slot() by passing a -1 as + * slot_nr, to update their %struct pci_slot with the correct @slot_nr. + */ + +void pci_update_slot_number(struct pci_slot *slot, int slot_nr) +{ + int name_count = 0; + struct pci_slot *tmp; + + down_write(&pci_bus_sem); + + list_for_each_entry(tmp, &slot->bus->slots, list) { + WARN_ON(tmp->number == slot_nr); + if (!strcmp(kobject_name(&tmp->kobj), kobject_name(&slot->kobj))) + name_count++; + } + + if (name_count > 1) + printk(KERN_WARNING "pci_update_slot_number found %d slots with the same name: %s\n", name_count, kobject_name(&slot->kobj)); + + slot->number = slot_nr; + up_write(&pci_bus_sem); +} +EXPORT_SYMBOL_GPL(pci_update_slot_number); + +/** + * pci_destroy_slot - decrement refcount for physical PCI slot + * @slot: struct pci_slot to decrement + * + * %struct pci_slot is refcounted, so destroying them is really easy; we + * just call kobject_put on its kobj and let our release methods do the + * rest. + */ + +void pci_destroy_slot(struct pci_slot *slot) +{ + pr_debug("%s: dec refcount to %d on %04x:%02x:%02x\n", __func__, + atomic_read(&slot->kobj.kref.refcount) - 1, + pci_domain_nr(slot->bus), slot->bus->number, slot->number); + + down_write(&pci_bus_sem); + kobject_put(&slot->kobj); + up_write(&pci_bus_sem); +} +EXPORT_SYMBOL_GPL(pci_destroy_slot); + +static int pci_slot_init(void) +{ + struct kset *pci_bus_kset; + + pci_bus_kset = bus_get_kset(&pci_bus_type); + pci_slots_kset = kset_create_and_add("slots", NULL, + &pci_bus_kset->kobj); + if (!pci_slots_kset) { + printk(KERN_ERR "PCI: Slot initialization failure\n"); + return -ENOMEM; + } + return 0; +} + +subsys_initcall(pci_slot_init); diff --git a/include/linux/pci.h b/include/linux/pci.h index 507ee52323cd..f1f73f79a180 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -17,8 +17,7 @@ #ifndef LINUX_PCI_H #define LINUX_PCI_H -/* Include the pci register defines */ -#include +#include /* The pci register defines */ /* * The PCI interface treats multi-function devices as independent @@ -49,12 +48,22 @@ #include #include #include +#include #include #include /* Include the ID list */ #include +/* pci_slot represents a physical slot */ +struct pci_slot { + struct pci_bus *bus; /* The bus this slot is on */ + struct list_head list; /* node in list of slots on this bus */ + struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ + unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ + struct kobject kobj; +}; + /* File state for mmap()s on /proc/bus/pci/X/Y */ enum pci_mmap_state { pci_mmap_io, @@ -142,6 +151,7 @@ struct pci_dev { void *sysdata; /* hook for sys-specific extension */ struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ + struct pci_slot *slot; /* Physical slot this device is in */ unsigned int devfn; /* encoded device & function index */ unsigned short vendor; @@ -266,6 +276,7 @@ struct pci_bus { struct list_head children; /* list of child buses */ struct list_head devices; /* list of devices on this bus */ struct pci_dev *self; /* bridge device as seen by parent */ + struct list_head slots; /* list of slots on this bus */ struct resource *resource[PCI_BUS_NUM_RESOURCES]; /* address space routed to this bus */ @@ -488,6 +499,10 @@ struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata); struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr); +struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, + const char *name); +void pci_destroy_slot(struct pci_slot *slot); +void pci_update_slot_number(struct pci_slot *slot, int slot_nr); int pci_scan_slot(struct pci_bus *bus, int devfn); struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index dbdcd1ad3c6a..a08cd06b541a 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -95,9 +95,6 @@ struct hotplug_slot_attribute { * @get_adapter_status: Called to get see if an adapter is present in the slot or not. * If this field is NULL, the value passed in the struct hotplug_slot_info * will be used when this value is requested by a user. - * @get_address: Called to get pci address of a slot. - * If this field is NULL, the value passed in the struct hotplug_slot_info - * will be used when this value is requested by a user. * @get_max_bus_speed: Called to get the max bus speed for a slot. * If this field is NULL, the value passed in the struct hotplug_slot_info * will be used when this value is requested by a user. @@ -120,7 +117,6 @@ struct hotplug_slot_ops { int (*get_attention_status) (struct hotplug_slot *slot, u8 *value); int (*get_latch_status) (struct hotplug_slot *slot, u8 *value); int (*get_adapter_status) (struct hotplug_slot *slot, u8 *value); - int (*get_address) (struct hotplug_slot *slot, u32 *value); int (*get_max_bus_speed) (struct hotplug_slot *slot, enum pci_bus_speed *value); int (*get_cur_bus_speed) (struct hotplug_slot *slot, enum pci_bus_speed *value); }; @@ -140,7 +136,6 @@ struct hotplug_slot_info { u8 attention_status; u8 latch_status; u8 adapter_status; - u32 address; enum pci_bus_speed max_bus_speed; enum pci_bus_speed cur_bus_speed; }; @@ -166,15 +161,14 @@ struct hotplug_slot { /* Variables below this are for use only by the hotplug pci core. */ struct list_head slot_list; - struct kobject kobj; + struct pci_slot *pci_slot; }; #define to_hotplug_slot(n) container_of(n, struct hotplug_slot, kobj) -extern int pci_hp_register (struct hotplug_slot *slot); -extern int pci_hp_deregister (struct hotplug_slot *slot); +extern int pci_hp_register(struct hotplug_slot *, struct pci_bus *, int nr); +extern int pci_hp_deregister(struct hotplug_slot *slot); extern int __must_check pci_hp_change_slot_info (struct hotplug_slot *slot, struct hotplug_slot_info *info); -extern struct kset *pci_hotplug_slots_kset; /* PCI Setting Record (Type 0) */ struct hpp_type0 { -- cgit v1.2.3 From 5848f16947026601b9cb4df694bb9f44dfefc354 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 11 Jun 2008 16:32:48 +0400 Subject: powerpc/QE: qe_reset should be __init This patch fixes following section mismatch: WARNING: arch/powerpc/sysdev/built-in.o(.text+0x11d8): Section mismatch in reference from the function qe_reset() to the function .init.text:cpm_muram_init() Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/qe_lib/qe.c | 2 +- include/asm-powerpc/qe.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index 28e05df952de..9e82d7e725a5 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -87,7 +87,7 @@ phys_addr_t get_qe_base(void) EXPORT_SYMBOL(get_qe_base); -void qe_reset(void) +void __init qe_reset(void) { if (qe_immr == NULL) qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE); diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index 80807fd6a706..1355e7267013 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -84,7 +84,7 @@ static inline bool qe_clock_is_brg(enum qe_clock clk) extern spinlock_t cmxgcr_lock; /* Export QE common operations */ -extern void qe_reset(void); +extern void __init qe_reset(void); /* QE PIO */ #define QE_PIO_PINS 32 -- cgit v1.2.3 From 06166780eb53685e72b589814d535d1f9948e761 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 5 Jun 2008 01:15:40 +0200 Subject: ACPI PM: acpi_pm_device_sleep_state() cleanup Get rid of a superfluous acpi_pm_device_sleep_state() parameter. The only legitimate value of that parameter must be derived from the first parameter, which is what all the callers already do. (However, this does not address the fact that ACPI still doesn't set up those flags.) Signed-off-by: David Brownell Acked-by: Pavel Machek Signed-off-by: Rafael J. Wysocki Signed-off-by: Len Brown --- drivers/acpi/sleep/main.c | 8 ++++---- drivers/pci/pci-acpi.c | 3 +-- drivers/pnp/pnpacpi/core.c | 4 +--- include/acpi/acpi_bus.h | 4 ++-- 4 files changed, 8 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/drivers/acpi/sleep/main.c b/drivers/acpi/sleep/main.c index c3b0cd88d09f..fbd40e96ed14 100644 --- a/drivers/acpi/sleep/main.c +++ b/drivers/acpi/sleep/main.c @@ -369,8 +369,8 @@ int acpi_suspend(u32 acpi_state) /** * acpi_pm_device_sleep_state - return preferred power state of ACPI device * in the system sleep state given by %acpi_target_sleep_state - * @dev: device to examine - * @wake: if set, the device should be able to wake up the system + * @dev: device to examine; its driver model wakeup flags control + * whether it should be able to wake up the system * @d_min_p: used to store the upper limit of allowed states range * Return value: preferred power state of the device on success, -ENODEV on * failure (ie. if there's no 'struct acpi_device' for @dev) @@ -388,7 +388,7 @@ int acpi_suspend(u32 acpi_state) * via @wake. */ -int acpi_pm_device_sleep_state(struct device *dev, int wake, int *d_min_p) +int acpi_pm_device_sleep_state(struct device *dev, int *d_min_p) { acpi_handle handle = DEVICE_ACPI_HANDLE(dev); struct acpi_device *adev; @@ -427,7 +427,7 @@ int acpi_pm_device_sleep_state(struct device *dev, int wake, int *d_min_p) * can wake the system. _S0W may be valid, too. */ if (acpi_target_sleep_state == ACPI_STATE_S0 || - (wake && adev->wakeup.state.enabled && + (device_may_wakeup(dev) && adev->wakeup.state.enabled && adev->wakeup.sleep_state <= acpi_target_sleep_state)) { acpi_status status; diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 9d6fc8e6285d..caabf0573c3d 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -298,8 +298,7 @@ static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev, { int acpi_state; - acpi_state = acpi_pm_device_sleep_state(&pdev->dev, - device_may_wakeup(&pdev->dev), NULL); + acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL); if (acpi_state < 0) return PCI_POWER_ERROR; diff --git a/drivers/pnp/pnpacpi/core.c b/drivers/pnp/pnpacpi/core.c index 50902773beaf..c1b9ea34977b 100644 --- a/drivers/pnp/pnpacpi/core.c +++ b/drivers/pnp/pnpacpi/core.c @@ -117,9 +117,7 @@ static int pnpacpi_suspend(struct pnp_dev *dev, pm_message_t state) { int power_state; - power_state = acpi_pm_device_sleep_state(&dev->dev, - device_may_wakeup(&dev->dev), - NULL); + power_state = acpi_pm_device_sleep_state(&dev->dev, NULL); if (power_state < 0) power_state = (state.event == PM_EVENT_ON) ? ACPI_STATE_D0 : ACPI_STATE_D3; diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 2f1c68c7a727..db90a74f8714 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -376,9 +376,9 @@ acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int); #define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)((dev)->archdata.acpi_handle)) #ifdef CONFIG_PM_SLEEP -int acpi_pm_device_sleep_state(struct device *, int, int *); +int acpi_pm_device_sleep_state(struct device *, int *); #else /* !CONFIG_PM_SLEEP */ -static inline int acpi_pm_device_sleep_state(struct device *d, int w, int *p) +static inline int acpi_pm_device_sleep_state(struct device *d, int *p) { if (p) *p = ACPI_STATE_D0; -- cgit v1.2.3 From d8f3de0d2412bb91639cfefc5b3c79dbf3812212 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Thu, 12 Jun 2008 23:24:06 +0200 Subject: Suspend-related patches for 2.6.27 ACPI PM: Add possibility to change suspend sequence There are some systems out there that don't work correctly with our current suspend/hibernation code ordering. Provide a workaround for these systems allowing them to pass 'acpi_sleep=old_ordering' in the kernel command line so that it will use the pre-ACPI 2.0 ("old") suspend code ordering. Unfortunately, this requires us to add a platform hook to the resuming of devices for recovering the platform in case one of the device drivers' .suspend() routines returns error code. Namely, ACPI 1.0 specifies that _PTS should be called before suspending devices, but _WAK still should be called before resuming them in order to undo the changes made by _PTS. However, if there is an error during suspending devices, they are automatically resumed without returning control to the PM core, so the _WAK has to be called from within device_resume() in that cases. The patch also reorders and refactors the ACPI suspend/hibernation code to avoid duplication as far as reasonably possible. Signed-off-by: Rafael J. Wysocki Acked-by: Pavel Machek Signed-off-by: Jesse Barnes --- Documentation/kernel-parameters.txt | 6 +- arch/x86/kernel/acpi/sleep.c | 2 + drivers/acpi/sleep/main.c | 276 +++++++++++++++++++++--------------- drivers/base/power/main.c | 2 - include/linux/acpi.h | 3 + include/linux/suspend.h | 14 +- kernel/power/disk.c | 28 +++- kernel/power/main.c | 10 +- 8 files changed, 215 insertions(+), 126 deletions(-) (limited to 'include') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 9cf7b34f2db0..18d793ea0dd3 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -147,10 +147,14 @@ and is between 256 and 4096 characters. It is defined in the file default: 0 acpi_sleep= [HW,ACPI] Sleep options - Format: { s3_bios, s3_mode, s3_beep } + Format: { s3_bios, s3_mode, s3_beep, old_ordering } See Documentation/power/video.txt for s3_bios and s3_mode. s3_beep is for debugging; it makes the PC's speaker beep as soon as the kernel's real-mode entry point is called. + old_ordering causes the ACPI 1.0 ordering of the _PTS + control method, wrt putting devices into low power + states, to be enforced (the ACPI 2.0 ordering of _PTS is + used by default). acpi_sci= [HW,ACPI] ACPI System Control Interrupt trigger mode Format: { level | edge | high | low } diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index afc25ee9964b..882e970032d5 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -124,6 +124,8 @@ static int __init acpi_sleep_setup(char *str) acpi_realmode_flags |= 2; if (strncmp(str, "s3_beep", 7) == 0) acpi_realmode_flags |= 4; + if (strncmp(str, "old_ordering", 12) == 0) + acpi_old_suspend_ordering(); str = strchr(str, ','); if (str != NULL) str += strspn(str, ", \t"); diff --git a/drivers/acpi/sleep/main.c b/drivers/acpi/sleep/main.c index 0f2caea2fc83..4addf8ad50ae 100644 --- a/drivers/acpi/sleep/main.c +++ b/drivers/acpi/sleep/main.c @@ -24,10 +24,6 @@ u8 sleep_states[ACPI_S_STATE_COUNT]; -#ifdef CONFIG_PM_SLEEP -static u32 acpi_target_sleep_state = ACPI_STATE_S0; -#endif - static int acpi_sleep_prepare(u32 acpi_state) { #ifdef CONFIG_ACPI_SLEEP @@ -50,9 +46,96 @@ static int acpi_sleep_prepare(u32 acpi_state) return 0; } -#ifdef CONFIG_SUSPEND -static struct platform_suspend_ops acpi_suspend_ops; +#ifdef CONFIG_PM_SLEEP +static u32 acpi_target_sleep_state = ACPI_STATE_S0; + +/* + * ACPI 1.0 wants us to execute _PTS before suspending devices, so we allow the + * user to request that behavior by using the 'acpi_old_suspend_ordering' + * kernel command line option that causes the following variable to be set. + */ +static bool old_suspend_ordering; + +void __init acpi_old_suspend_ordering(void) +{ + old_suspend_ordering = true; +} + +/** + * acpi_pm_disable_gpes - Disable the GPEs. + */ +static int acpi_pm_disable_gpes(void) +{ + acpi_hw_disable_all_gpes(); + return 0; +} + +/** + * __acpi_pm_prepare - Prepare the platform to enter the target state. + * + * If necessary, set the firmware waking vector and do arch-specific + * nastiness to get the wakeup code to the waking vector. + */ +static int __acpi_pm_prepare(void) +{ + int error = acpi_sleep_prepare(acpi_target_sleep_state); + + if (error) + acpi_target_sleep_state = ACPI_STATE_S0; + return error; +} + +/** + * acpi_pm_prepare - Prepare the platform to enter the target sleep + * state and disable the GPEs. + */ +static int acpi_pm_prepare(void) +{ + int error = __acpi_pm_prepare(); + + if (!error) + acpi_hw_disable_all_gpes(); + return error; +} + +/** + * acpi_pm_finish - Instruct the platform to leave a sleep state. + * + * This is called after we wake back up (or if entering the sleep state + * failed). + */ +static void acpi_pm_finish(void) +{ + u32 acpi_state = acpi_target_sleep_state; + + if (acpi_state == ACPI_STATE_S0) + return; + printk(KERN_INFO PREFIX "Waking up from system sleep state S%d\n", + acpi_state); + acpi_disable_wakeup_device(acpi_state); + acpi_leave_sleep_state(acpi_state); + + /* reset firmware waking vector */ + acpi_set_firmware_waking_vector((acpi_physical_address) 0); + + acpi_target_sleep_state = ACPI_STATE_S0; +} + +/** + * acpi_pm_end - Finish up suspend sequence. + */ +static void acpi_pm_end(void) +{ + /* + * This is necessary in case acpi_pm_finish() is not called during a + * failing transition to a sleep state. + */ + acpi_target_sleep_state = ACPI_STATE_S0; +} +#endif /* CONFIG_PM_SLEEP */ + +#ifdef CONFIG_SUSPEND extern void do_suspend_lowlevel(void); static u32 acpi_suspend_states[] = { @@ -66,7 +149,6 @@ static u32 acpi_suspend_states[] = { * acpi_suspend_begin - Set the target system sleep state to the state * associated with given @pm_state, if supported. */ - static int acpi_suspend_begin(suspend_state_t pm_state) { u32 acpi_state = acpi_suspend_states[pm_state]; @@ -82,25 +164,6 @@ static int acpi_suspend_begin(suspend_state_t pm_state) return error; } -/** - * acpi_suspend_prepare - Do preliminary suspend work. - * - * If necessary, set the firmware waking vector and do arch-specific - * nastiness to get the wakeup code to the waking vector. - */ - -static int acpi_suspend_prepare(void) -{ - int error = acpi_sleep_prepare(acpi_target_sleep_state); - - if (error) { - acpi_target_sleep_state = ACPI_STATE_S0; - return error; - } - - return ACPI_SUCCESS(acpi_hw_disable_all_gpes()) ? 0 : -EFAULT; -} - /** * acpi_suspend_enter - Actually enter a sleep state. * @pm_state: ignored @@ -109,7 +172,6 @@ static int acpi_suspend_prepare(void) * assembly, which in turn call acpi_enter_sleep_state(). * It's unfortunate, but it works. Please fix if you're feeling frisky. */ - static int acpi_suspend_enter(suspend_state_t pm_state) { acpi_status status = AE_OK; @@ -166,39 +228,6 @@ static int acpi_suspend_enter(suspend_state_t pm_state) return ACPI_SUCCESS(status) ? 0 : -EFAULT; } -/** - * acpi_suspend_finish - Instruct the platform to leave a sleep state. - * - * This is called after we wake back up (or if entering the sleep state - * failed). - */ - -static void acpi_suspend_finish(void) -{ - u32 acpi_state = acpi_target_sleep_state; - - acpi_disable_wakeup_device(acpi_state); - acpi_leave_sleep_state(acpi_state); - - /* reset firmware waking vector */ - acpi_set_firmware_waking_vector((acpi_physical_address) 0); - - acpi_target_sleep_state = ACPI_STATE_S0; -} - -/** - * acpi_suspend_end - Finish up suspend sequence. - */ - -static void acpi_suspend_end(void) -{ - /* - * This is necessary in case acpi_suspend_finish() is not called during a - * failing transition to a sleep state. - */ - acpi_target_sleep_state = ACPI_STATE_S0; -} - static int acpi_suspend_state_valid(suspend_state_t pm_state) { u32 acpi_state; @@ -218,10 +247,39 @@ static int acpi_suspend_state_valid(suspend_state_t pm_state) static struct platform_suspend_ops acpi_suspend_ops = { .valid = acpi_suspend_state_valid, .begin = acpi_suspend_begin, - .prepare = acpi_suspend_prepare, + .prepare = acpi_pm_prepare, + .enter = acpi_suspend_enter, + .finish = acpi_pm_finish, + .end = acpi_pm_end, +}; + +/** + * acpi_suspend_begin_old - Set the target system sleep state to the + * state associated with given @pm_state, if supported, and + * execute the _PTS control method. This function is used if the + * pre-ACPI 2.0 suspend ordering has been requested. + */ +static int acpi_suspend_begin_old(suspend_state_t pm_state) +{ + int error = acpi_suspend_begin(pm_state); + + if (!error) + error = __acpi_pm_prepare(); + return error; +} + +/* + * The following callbacks are used if the pre-ACPI 2.0 suspend ordering has + * been requested. + */ +static struct platform_suspend_ops acpi_suspend_ops_old = { + .valid = acpi_suspend_state_valid, + .begin = acpi_suspend_begin_old, + .prepare = acpi_pm_disable_gpes, .enter = acpi_suspend_enter, - .finish = acpi_suspend_finish, - .end = acpi_suspend_end, + .finish = acpi_pm_finish, + .end = acpi_pm_end, + .recover = acpi_pm_finish, }; #endif /* CONFIG_SUSPEND */ @@ -229,22 +287,9 @@ static struct platform_suspend_ops acpi_suspend_ops = { static int acpi_hibernation_begin(void) { acpi_target_sleep_state = ACPI_STATE_S4; - return 0; } -static int acpi_hibernation_prepare(void) -{ - int error = acpi_sleep_prepare(ACPI_STATE_S4); - - if (error) { - acpi_target_sleep_state = ACPI_STATE_S0; - return error; - } - - return ACPI_SUCCESS(acpi_hw_disable_all_gpes()) ? 0 : -EFAULT; -} - static int acpi_hibernation_enter(void) { acpi_status status = AE_OK; @@ -274,52 +319,55 @@ static void acpi_hibernation_leave(void) acpi_leave_sleep_state_prep(ACPI_STATE_S4); } -static void acpi_hibernation_finish(void) +static void acpi_pm_enable_gpes(void) { - acpi_disable_wakeup_device(ACPI_STATE_S4); - acpi_leave_sleep_state(ACPI_STATE_S4); - - /* reset firmware waking vector */ - acpi_set_firmware_waking_vector((acpi_physical_address) 0); - - acpi_target_sleep_state = ACPI_STATE_S0; + acpi_hw_enable_all_runtime_gpes(); } -static void acpi_hibernation_end(void) -{ - /* - * This is necessary in case acpi_hibernation_finish() is not called - * during a failing transition to the sleep state. - */ - acpi_target_sleep_state = ACPI_STATE_S0; -} +static struct platform_hibernation_ops acpi_hibernation_ops = { + .begin = acpi_hibernation_begin, + .end = acpi_pm_end, + .pre_snapshot = acpi_pm_prepare, + .finish = acpi_pm_finish, + .prepare = acpi_pm_prepare, + .enter = acpi_hibernation_enter, + .leave = acpi_hibernation_leave, + .pre_restore = acpi_pm_disable_gpes, + .restore_cleanup = acpi_pm_enable_gpes, +}; -static int acpi_hibernation_pre_restore(void) +/** + * acpi_hibernation_begin_old - Set the target system sleep state to + * ACPI_STATE_S4 and execute the _PTS control method. This + * function is used if the pre-ACPI 2.0 suspend ordering has been + * requested. + */ +static int acpi_hibernation_begin_old(void) { - acpi_status status; - - status = acpi_hw_disable_all_gpes(); - - return ACPI_SUCCESS(status) ? 0 : -EFAULT; -} + int error = acpi_sleep_prepare(ACPI_STATE_S4); -static void acpi_hibernation_restore_cleanup(void) -{ - acpi_hw_enable_all_runtime_gpes(); + if (!error) + acpi_target_sleep_state = ACPI_STATE_S4; + return error; } -static struct platform_hibernation_ops acpi_hibernation_ops = { - .begin = acpi_hibernation_begin, - .end = acpi_hibernation_end, - .pre_snapshot = acpi_hibernation_prepare, - .finish = acpi_hibernation_finish, - .prepare = acpi_hibernation_prepare, +/* + * The following callbacks are used if the pre-ACPI 2.0 suspend ordering has + * been requested. + */ +static struct platform_hibernation_ops acpi_hibernation_ops_old = { + .begin = acpi_hibernation_begin_old, + .end = acpi_pm_end, + .pre_snapshot = acpi_pm_disable_gpes, + .finish = acpi_pm_finish, + .prepare = acpi_pm_disable_gpes, .enter = acpi_hibernation_enter, .leave = acpi_hibernation_leave, - .pre_restore = acpi_hibernation_pre_restore, - .restore_cleanup = acpi_hibernation_restore_cleanup, + .pre_restore = acpi_pm_disable_gpes, + .restore_cleanup = acpi_pm_enable_gpes, + .recover = acpi_pm_finish, }; -#endif /* CONFIG_HIBERNATION */ +#endif /* CONFIG_HIBERNATION */ int acpi_suspend(u32 acpi_state) { @@ -461,13 +509,15 @@ int __init acpi_sleep_init(void) } } - suspend_set_ops(&acpi_suspend_ops); + suspend_set_ops(old_suspend_ordering ? + &acpi_suspend_ops_old : &acpi_suspend_ops); #endif #ifdef CONFIG_HIBERNATION status = acpi_get_sleep_type_data(ACPI_STATE_S4, &type_a, &type_b); if (ACPI_SUCCESS(status)) { - hibernation_set_ops(&acpi_hibernation_ops); + hibernation_set_ops(old_suspend_ordering ? + &acpi_hibernation_ops_old : &acpi_hibernation_ops); sleep_states[ACPI_STATE_S4] = 1; printk(" S4"); } diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c index d571204aaff7..3250c5257b74 100644 --- a/drivers/base/power/main.c +++ b/drivers/base/power/main.c @@ -781,8 +781,6 @@ int device_suspend(pm_message_t state) error = dpm_prepare(state); if (!error) error = dpm_suspend(state); - if (error) - device_resume(resume_event(state)); return error; } EXPORT_SYMBOL_GPL(device_suspend); diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 41f7ce7edd7a..33adcf91ef41 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -234,6 +234,9 @@ int acpi_check_region(resource_size_t start, resource_size_t n, int acpi_check_mem_region(resource_size_t start, resource_size_t n, const char *name); +#ifdef CONFIG_PM_SLEEP +void __init acpi_old_suspend_ordering(void); +#endif /* CONFIG_PM_SLEEP */ #else /* CONFIG_ACPI */ static inline int early_acpi_boot_init(void) diff --git a/include/linux/suspend.h b/include/linux/suspend.h index a6977423baf7..e8e69159af71 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -86,6 +86,11 @@ typedef int __bitwise suspend_state_t; * that implement @begin(), but platforms implementing @begin() should * also provide a @end() which cleans up transitions aborted before * @enter(). + * + * @recover: Recover the platform from a suspend failure. + * Called by the PM core if the suspending of devices fails. + * This callback is optional and should only be implemented by platforms + * which require special recovery actions in that situation. */ struct platform_suspend_ops { int (*valid)(suspend_state_t state); @@ -94,6 +99,7 @@ struct platform_suspend_ops { int (*enter)(suspend_state_t state); void (*finish)(void); void (*end)(void); + void (*recover)(void); }; #ifdef CONFIG_SUSPEND @@ -149,7 +155,7 @@ extern void mark_free_pages(struct zone *zone); * The methods in this structure allow a platform to carry out special * operations required by it during a hibernation transition. * - * All the methods below must be implemented. + * All the methods below, except for @recover(), must be implemented. * * @begin: Tell the platform driver that we're starting hibernation. * Called right after shrinking memory and before freezing devices. @@ -189,6 +195,11 @@ extern void mark_free_pages(struct zone *zone); * @restore_cleanup: Clean up after a failing image restoration. * Called right after the nonboot CPUs have been enabled and before * thawing devices (runs with IRQs on). + * + * @recover: Recover the platform from a failure to suspend devices. + * Called by the PM core if the suspending of devices during hibernation + * fails. This callback is optional and should only be implemented by + * platforms which require special recovery actions in that situation. */ struct platform_hibernation_ops { int (*begin)(void); @@ -200,6 +211,7 @@ struct platform_hibernation_ops { void (*leave)(void); int (*pre_restore)(void); void (*restore_cleanup)(void); + void (*recover)(void); }; #ifdef CONFIG_HIBERNATION diff --git a/kernel/power/disk.c b/kernel/power/disk.c index d416be0efa8a..f011e0870b52 100644 --- a/kernel/power/disk.c +++ b/kernel/power/disk.c @@ -179,6 +179,17 @@ static void platform_restore_cleanup(int platform_mode) hibernation_ops->restore_cleanup(); } +/** + * platform_recover - recover the platform from a failure to suspend + * devices. + */ + +static void platform_recover(int platform_mode) +{ + if (platform_mode && hibernation_ops && hibernation_ops->recover) + hibernation_ops->recover(); +} + /** * create_image - freeze devices that need to be frozen with interrupts * off, create the hibernation image and thaw those devices. Control @@ -258,10 +269,10 @@ int hibernation_snapshot(int platform_mode) suspend_console(); error = device_suspend(PMSG_FREEZE); if (error) - goto Resume_console; + goto Recover_platform; if (hibernation_test(TEST_DEVICES)) - goto Resume_devices; + goto Recover_platform; error = platform_pre_snapshot(platform_mode); if (error || hibernation_test(TEST_PLATFORM)) @@ -285,11 +296,14 @@ int hibernation_snapshot(int platform_mode) Resume_devices: device_resume(in_suspend ? (error ? PMSG_RECOVER : PMSG_THAW) : PMSG_RESTORE); - Resume_console: resume_console(); Close: platform_end(platform_mode); return error; + + Recover_platform: + platform_recover(platform_mode); + goto Resume_devices; } /** @@ -398,8 +412,11 @@ int hibernation_platform_enter(void) suspend_console(); error = device_suspend(PMSG_HIBERNATE); - if (error) - goto Resume_console; + if (error) { + if (hibernation_ops->recover) + hibernation_ops->recover(); + goto Resume_devices; + } error = hibernation_ops->prepare(); if (error) @@ -428,7 +445,6 @@ int hibernation_platform_enter(void) hibernation_ops->finish(); Resume_devices: device_resume(PMSG_RESTORE); - Resume_console: resume_console(); Close: hibernation_ops->end(); diff --git a/kernel/power/main.c b/kernel/power/main.c index d023b6b584e5..3398f4651aa1 100644 --- a/kernel/power/main.c +++ b/kernel/power/main.c @@ -269,11 +269,11 @@ int suspend_devices_and_enter(suspend_state_t state) error = device_suspend(PMSG_SUSPEND); if (error) { printk(KERN_ERR "PM: Some devices failed to suspend\n"); - goto Resume_console; + goto Recover_platform; } if (suspend_test(TEST_DEVICES)) - goto Resume_devices; + goto Recover_platform; if (suspend_ops->prepare) { error = suspend_ops->prepare(); @@ -294,12 +294,16 @@ int suspend_devices_and_enter(suspend_state_t state) suspend_ops->finish(); Resume_devices: device_resume(PMSG_RESUME); - Resume_console: resume_console(); Close: if (suspend_ops->end) suspend_ops->end(); return error; + + Recover_platform: + if (suspend_ops->recover) + suspend_ops->recover(); + goto Resume_devices; } /** -- cgit v1.2.3 From bccaea8fe287454d70f5b2546910561e9f884053 Mon Sep 17 00:00:00 2001 From: Jerone Young Date: Fri, 6 Jun 2008 14:09:05 -0500 Subject: powerpc/booke: Fix definitions for dbcr[1-2] and dbsr registers This takes values from the PowerPC ISA BookIII-E specifications that are for DBCR0. Many of these values are different from those currently specified, which are for the ppc405. Also added some bookE definitions for DBCR1 & DBCR2. [ galak@kernel.crashing.org: Added aliases to 40x DBCR0 to match Book-E, Added enhanced debug DBCR0/DBSR _CIRPT and _CRET defines and DBSR IRPT and RET. ] Signed-off-by: Jerone Young Acked-by: Josh Boyer Signed-off-by: Kumar Gala --- include/asm-powerpc/reg_booke.h | 55 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'include') diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h index cf54a3f31753..a1ab2ba8f1b2 100644 --- a/include/asm-powerpc/reg_booke.h +++ b/include/asm-powerpc/reg_booke.h @@ -210,6 +210,7 @@ #ifdef CONFIG_BOOKE #define DBSR_IC 0x08000000 /* Instruction Completion */ #define DBSR_BT 0x04000000 /* Branch Taken */ +#define DBSR_IRPT 0x02000000 /* Exception Debug Event */ #define DBSR_TIE 0x01000000 /* Trap Instruction Event */ #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ @@ -219,10 +220,14 @@ #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ +#define DBSR_RET 0x00008000 /* Return Debug Event */ +#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ +#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */ #endif #ifdef CONFIG_40x #define DBSR_IC 0x80000000 /* Instruction Completion */ #define DBSR_BT 0x40000000 /* Branch taken */ +#define DBSR_IRPT 0x20000000 /* Exception Debug Event */ #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ #define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ #define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ @@ -253,6 +258,7 @@ #define ESR_BO 0x00020000 /* Byte Ordering */ /* Bit definitions related to the DBCR0. */ +#if defined(CONFIG_40x) #define DBCR0_EDM 0x80000000 /* External Debug Mode */ #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ @@ -261,20 +267,69 @@ #define DBCR0_RST_CORE 0x10000000 /* Core Reset */ #define DBCR0_RST_NONE 0x00000000 /* No Reset */ #define DBCR0_IC 0x08000000 /* Instruction Completion */ +#define DBCR0_ICMP DBCR0_IC #define DBCR0_BT 0x04000000 /* Branch Taken */ +#define DBCR0_BRT DBCR0_BT #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR0_IRPT DBCR0_EDE #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ +#define DBCR0_IAC1 DBCR0_IA1 #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ +#define DBCR0_IAC2 DBCR0_IA2 #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ +#define DBCR0_IAC3 DBCR0_IA3 #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ +#define DBCR0_IAC4 DBCR0_IA4 #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ +#elif defined(CONFIG_BOOKE) +#define DBCR0_EDM 0x80000000 /* External Debug Mode */ +#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ +#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ +/* DBCR0_RST_* is 44x specific and not followed in fsl booke */ +#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ +#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ +#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ +#define DBCR0_RST_NONE 0x00000000 /* No Reset */ +#define DBCR0_ICMP 0x08000000 /* Instruction Completion */ +#define DBCR0_IC DBCR0_ICMP +#define DBCR0_BRT 0x04000000 /* Branch Taken */ +#define DBCR0_BT DBCR0_BRT +#define DBCR0_IRPT 0x02000000 /* Exception Debug Event */ +#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR0_TIE DBCR0_TDE +#define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */ +#define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */ +#define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */ +#define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */ +#define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */ +#define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */ +#define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */ +#define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */ +#define DBCR0_RET 0x00008000 /* Return Debug Event */ +#define DBCR0_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ +#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */ +#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ + +/* Bit definitions related to the DBCR1. */ +#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */ +#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */ +#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */ +#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */ +#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */ +#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */ + +/* Bit definitions related to the DBCR2. */ +#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */ +#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */ +#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */ +#endif /* Bit definitions related to the TCR. */ #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ -- cgit v1.2.3 From 5ce4b59653b2c2053cd9a011918ac1e4747f24cc Mon Sep 17 00:00:00 2001 From: Josh Boyer Date: Tue, 17 Jun 2008 19:01:38 -0400 Subject: powerpc/4xx: Workaround for PPC440EPx/GRx PCI_28 Errata The 440EPx/GRx chips don't support PCI MRM commands. Drivers determine this by looking for a zero value in the PCI cache line size register. However, some drivers write to this register upon initialization. This can cause MRMs to be used on these chips, which may cause deadlocks on PLB4. The workaround implemented here introduces a new indirect_type flag, called PPC_INDIRECT_TYPE_BROKEN_MRM. This is set in the pci_controller structure in the pci fixup function for 4xx PCI bridges by determining if the bridge is compatible with 440EPx/GRx. The flag is checked in the indirect_write_config function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be zero, which will disable MRMs for these chips. A similar workaround has been tested by AMCC on various PCI cards, such as the Silicon Image ATA card and Intel E1000 GIGE card. Hangs were seen with the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer. With the workaround in place, the card functioned properly and only Memory Reads were seen on the bus with the analyzer. Acked-by: Stefan Roese Signed-off-by: Josh Boyer --- arch/powerpc/sysdev/indirect_pci.c | 6 ++++++ arch/powerpc/sysdev/ppc4xx_pci.c | 5 +++++ include/asm-powerpc/pci-bridge.h | 3 +++ 3 files changed, 14 insertions(+) (limited to 'include') diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index cfbd2aae93e8..7fd49c97501a 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -123,6 +123,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, (bus->number == hose->first_busno)) val &= 0xffffff00; + /* Workaround for PCI_28 Errata in 440EPx/GRx */ + if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) && + offset == PCI_CACHE_LINE_SIZE) { + val = 0; + } + /* * Note: the caller has already checked that offset is * suitably aligned and that len is 1, 2 or 4. diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index 76886cf0e6dc..fb368dfde5d4 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c @@ -75,6 +75,11 @@ static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev) !of_device_is_compatible(hose->dn, "ibm,plb-pci")) return; + if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") || + of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) { + hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM; + } + /* Hide the PCI host BARs from the kernel as their content doesn't * fit well in the resource management */ diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index b95d033ae6e6..ae2ea803a0f2 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -92,12 +92,15 @@ struct pci_controller { * anything but the PHB. Only allow talking to the PHB if this is * set. * BIG_ENDIAN - cfg_addr is a big endian register + * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on + * the PLB4. Effectively disable MRM commands by setting this. */ #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 +#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 u32 indirect_type; #endif /* !CONFIG_PPC64 */ /* Currently, we limit ourselves to 1 IO range and 3 mem -- cgit v1.2.3 From 3dfa8773674e16f95f70a0e631e80c69390d04d7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 16 Jun 2008 09:41:32 -0500 Subject: powerpc/booke: Add support for new e500mc core The new e500mc core from Freescale is based on the e500v2 but with the following changes: * Supports only the Enhanced Debug Architecture (DSRR0/1, etc) * Floating Point * No SPE * Supports lwsync * Doorbell Exceptions * Hypervisor * Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line) Signed-off-by: Kumar Gala --- arch/powerpc/kernel/cputable.c | 15 +++++++++++++++ arch/powerpc/kernel/head_booke.h | 6 +++++- arch/powerpc/kernel/head_fsl_booke.S | 10 ++++++++-- arch/powerpc/platforms/Kconfig.cputype | 7 ++++++- include/asm-powerpc/cache.h | 3 +++ include/asm-powerpc/cputable.h | 6 ++++-- include/asm-powerpc/synch.h | 2 +- 7 files changed, 42 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index e44d5530f0a6..aa421f5651c8 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -1522,6 +1522,21 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_e500, .platform = "ppc8548", }, + { /* e500mc */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x80230000, + .cpu_name = "e500mc", + /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ + .cpu_features = CPU_FTRS_E500MC, + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, + .icache_bsize = 64, + .dcache_bsize = 64, + .num_pmcs = 4, + .oprofile_cpu_type = "ppc/e500", /* xxx - galak, e500mc? */ + .oprofile_type = PPC_OPROFILE_FSL_EMB, + .machine_check = machine_check_e500, + .platform = "ppce500mc", + }, { /* default match */ .pvr_mask = 0x00000000, .pvr_value = 0x00000000, diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 9501c580ce87..505494f1ee7c 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -68,9 +68,13 @@ #define MCHECK_STACK_BASE mcheckirq_ctx #define CRIT_STACK_BASE critirq_ctx -/* only on e200 for now */ +/* only on e500mc/e200 */ #define DEBUG_STACK_BASE dbgirq_ctx +#ifdef CONFIG_PPC_E500MC +#define DEBUG_SPRG SPRN_SPRG9 +#else #define DEBUG_SPRG SPRN_SPRG6W +#endif #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 503f86030b6e..7c2b65380658 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -304,7 +304,7 @@ skpinv: addi r6,r6,1 /* Increment */ SET_IVOR(13, DataTLBError); SET_IVOR(14, InstructionTLBError); SET_IVOR(15, DebugDebug); -#if defined(CONFIG_E500) +#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC) SET_IVOR(15, DebugCrit); #endif SET_IVOR(32, SPEUnavailable); @@ -313,6 +313,9 @@ skpinv: addi r6,r6,1 /* Increment */ #ifndef CONFIG_E200 SET_IVOR(35, PerformanceMonitor); #endif +#ifdef CONFIG_PPC_E500MC + SET_IVOR(36, Doorbell); +#endif /* Establish the interrupt vector base */ lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ @@ -750,10 +753,13 @@ interrupt_base: /* Performance Monitor */ EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD) +#ifdef CONFIG_PPC_E500MC + EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE) +#endif /* Debug Interrupt */ DEBUG_DEBUG_EXCEPTION -#if defined(CONFIG_E500) +#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC) DEBUG_CRIT_EXCEPTION #endif diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype index f7efaa925a13..1a1ccfbb9232 100644 --- a/arch/powerpc/platforms/Kconfig.cputype +++ b/arch/powerpc/platforms/Kconfig.cputype @@ -95,6 +95,11 @@ config E500 select FSL_EMB_PERFMON bool +config PPC_E500MC + bool "e500mc Support" + select PPC_FPU + depends on E500 + config PPC_FPU bool default y if PPC64 @@ -157,7 +162,7 @@ config ALTIVEC config SPE bool "SPE Support" - depends on E200 || E500 + depends on E200 || (E500 && !PPC_E500MC) default y ---help--- This option enables kernel support for the Signal Processing diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h index 53507046a1b1..81de6eb3455d 100644 --- a/include/asm-powerpc/cache.h +++ b/include/asm-powerpc/cache.h @@ -8,6 +8,9 @@ #if defined(CONFIG_8xx) || defined(CONFIG_403GCX) #define L1_CACHE_SHIFT 4 #define MAX_COPY_PREFETCH 1 +#elif defined(CONFIG_PPC_E500MC) +#define L1_CACHE_SHIFT 6 +#define MAX_COPY_PREFETCH 4 #elif defined(CONFIG_PPC32) #define L1_CACHE_SHIFT 5 #define MAX_COPY_PREFETCH 4 diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 1e79673b7316..a3dce178b728 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -351,6 +351,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, CPU_FTR_NODSISRALIGN) #define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) +#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS | \ + CPU_FTR_NODSISRALIGN) #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) /* 64-bit CPUs */ @@ -421,7 +423,7 @@ enum { CPU_FTRS_E200 | #endif #ifdef CONFIG_E500 - CPU_FTRS_E500 | CPU_FTRS_E500_2 | + CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC | #endif 0, }; @@ -461,7 +463,7 @@ enum { CPU_FTRS_E200 & #endif #ifdef CONFIG_E500 - CPU_FTRS_E500 & CPU_FTRS_E500_2 & + CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC & #endif CPU_FTRS_POSSIBLE, }; diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h index 2cda3c38a9fa..42a1ef590690 100644 --- a/include/asm-powerpc/synch.h +++ b/include/asm-powerpc/synch.h @@ -4,7 +4,7 @@ #include -#ifdef __powerpc64__ +#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC) #define __SUBARCH_HAS_LWSYNC #endif -- cgit v1.2.3 From fc4033b2f8b1482022bff3d05505a1b1631bb6de Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 18 Jun 2008 16:26:52 -0500 Subject: powerpc/85xx: add DOZE/NAP support for e500 core The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- arch/powerpc/kernel/Makefile | 1 + arch/powerpc/kernel/cputable.c | 3 -- arch/powerpc/kernel/entry_32.S | 8 ++-- arch/powerpc/kernel/head_fsl_booke.S | 47 ++++++++++++++++++++ arch/powerpc/kernel/idle_6xx.S | 2 +- arch/powerpc/kernel/idle_e500.S | 84 ++++++++++++++++++++++++++++++++++++ arch/powerpc/kernel/setup_32.c | 5 +++ include/asm-powerpc/cputable.h | 11 ++--- include/asm-powerpc/machdep.h | 1 + include/asm-powerpc/reg.h | 2 +- include/asm-powerpc/reg_booke.h | 2 + 11 files changed, 152 insertions(+), 14 deletions(-) create mode 100644 arch/powerpc/kernel/idle_e500.S (limited to 'include') diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index 2346d271fbfd..0e8f928fef70 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_IBMVIO) += vio.o obj-$(CONFIG_IBMEBUS) += ibmebus.o obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsync.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o +obj-$(CONFIG_E500) += idle_e500.o obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o obj-$(CONFIG_TAU) += tau_6xx.o obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \ diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index aa421f5651c8..c5397c11ae91 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -1491,7 +1491,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pvr_mask = 0xffff0000, .pvr_value = 0x80200000, .cpu_name = "e500", - /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .cpu_features = CPU_FTRS_E500, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_SPE_COMP | @@ -1508,7 +1507,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pvr_mask = 0xffff0000, .pvr_value = 0x80210000, .cpu_name = "e500v2", - /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .cpu_features = CPU_FTRS_E500_2, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_SPE_COMP | @@ -1526,7 +1524,6 @@ static struct cpu_spec __initdata cpu_specs[] = { .pvr_mask = 0xffff0000, .pvr_value = 0x80230000, .cpu_name = "e500mc", - /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .cpu_features = CPU_FTRS_E500MC, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, .icache_bsize = 64, diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index fe21674d4f06..ab2d62f70b14 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -176,14 +176,14 @@ transfer_to_handler: cmplw r1,r9 /* if r1 <= ksp_limit */ ble- stack_ovf /* then the kernel stack overflowed */ 5: -#ifdef CONFIG_6xx +#if defined(CONFIG_6xx) || defined(CONFIG_E500) rlwinm r9,r1,0,0,31-THREAD_SHIFT tophys(r9,r9) /* check local flags */ lwz r12,TI_LOCAL_FLAGS(r9) mtcrf 0x01,r12 bt- 31-TLF_NAPPING,4f bt- 31-TLF_SLEEPING,7f -#endif /* CONFIG_6xx */ +#endif /* CONFIG_6xx || CONFIG_E500 */ .globl transfer_to_handler_cont transfer_to_handler_cont: 3: @@ -196,10 +196,10 @@ transfer_to_handler_cont: SYNC RFI /* jump to handler, enable MMU */ -#ifdef CONFIG_6xx +#if defined (CONFIG_6xx) || defined(CONFIG_E500) 4: rlwinm r12,r12,0,~_TLF_NAPPING stw r12,TI_LOCAL_FLAGS(r9) - b power_save_6xx_restore + b power_save_ppc32_restore 7: rlwinm r12,r12,0,~_TLF_SLEEPING stw r12,TI_LOCAL_FLAGS(r9) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 7c2b65380658..c4268500e856 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -39,6 +39,7 @@ #include #include #include +#include #include "head_booke.h" /* As with the other PowerPC ports, it is expected that when code @@ -1071,6 +1072,52 @@ _GLOBAL(set_context) isync /* Force context change */ blr +_GLOBAL(flush_dcache_L1) + mfspr r3,SPRN_L1CFG0 + + rlwinm r5,r3,9,3 /* Extract cache block size */ + twlgti r5,1 /* Only 32 and 64 byte cache blocks + * are currently defined. + */ + li r4,32 + subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - + * log2(number of ways) + */ + slw r5,r4,r5 /* r5 = cache block size */ + + rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ + mulli r7,r7,13 /* An 8-way cache will require 13 + * loads per set. + */ + slw r7,r7,r6 + + /* save off HID0 and set DCFA */ + mfspr r8,SPRN_HID0 + ori r9,r8,HID0_DCFA@l + mtspr SPRN_HID0,r9 + isync + + lis r4,KERNELBASE@h + mtctr r7 + +1: lwz r3,0(r4) /* Load... */ + add r4,r4,r5 + bdnz 1b + + msync + lis r4,KERNELBASE@h + mtctr r7 + +1: dcbf 0,r4 /* ...and flush. */ + add r4,r4,r5 + bdnz 1b + + /* restore HID0 */ + mtspr SPRN_HID0,r8 + isync + + blr + /* * We put a few things here that have to be page-aligned. This stuff * goes at the beginning of the data segment, which is page-aligned. diff --git a/arch/powerpc/kernel/idle_6xx.S b/arch/powerpc/kernel/idle_6xx.S index 01bcd52bbf8e..019b02d8844f 100644 --- a/arch/powerpc/kernel/idle_6xx.S +++ b/arch/powerpc/kernel/idle_6xx.S @@ -153,7 +153,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) * address of current. R11 points to the exception frame (physical * address). We have to preserve r10. */ -_GLOBAL(power_save_6xx_restore) +_GLOBAL(power_save_ppc32_restore) lwz r9,_LINK(r11) /* interrupted in ppc6xx_idle: */ stw r9,_NIP(r11) /* make it do a blr */ diff --git a/arch/powerpc/kernel/idle_e500.S b/arch/powerpc/kernel/idle_e500.S new file mode 100644 index 000000000000..267adec2491b --- /dev/null +++ b/arch/powerpc/kernel/idle_e500.S @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved. + * Dave Liu + * copy from idle_6xx.S and modify for e500 based processor, + * implement the power_save function in idle. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + + .text + +_GLOBAL(e500_idle) + rlwinm r3,r1,0,0,31-THREAD_SHIFT /* current thread_info */ + lwz r4,TI_LOCAL_FLAGS(r3) /* set napping bit */ + ori r4,r4,_TLF_NAPPING /* so when we take an exception */ + stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */ + + /* Check if we can nap or doze, put HID0 mask in r3 */ + lis r3,0 +BEGIN_FTR_SECTION + lis r3,HID0_DOZE@h +END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) + +BEGIN_FTR_SECTION + /* Now check if user enabled NAP mode */ + lis r4,powersave_nap@ha + lwz r4,powersave_nap@l(r4) + cmpwi 0,r4,0 + beq 1f + stwu r1,-16(r1) + mflr r0 + stw r0,20(r1) + bl flush_dcache_L1 + lwz r0,20(r1) + addi r1,r1,16 + mtlr r0 + lis r3,HID0_NAP@h +END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) +1: + /* Go to NAP or DOZE now */ + mfspr r4,SPRN_HID0 + rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP) + or r4,r4,r3 + isync + mtspr SPRN_HID0,r4 + isync + + mfmsr r7 + oris r7,r7,MSR_WE@h + ori r7,r7,MSR_EE + msync + mtmsr r7 + isync +2: b 2b + +/* + * Return from NAP/DOZE mode, restore some CPU specific registers, + * r2 containing physical address of current. + * r11 points to the exception frame (physical address). + * We have to preserve r10. + */ +_GLOBAL(power_save_ppc32_restore) + lwz r9,_LINK(r11) /* interrupted in e500_idle */ + stw r9,_NIP(r11) /* make it do a blr */ + +#ifdef CONFIG_SMP + mfspr r12,SPRN_SPRG3 + lwz r11,TI_CPU(r12) /* get cpu number * 4 */ + slwi r11,r11,2 +#else + li r11,0 +#endif + b transfer_to_handler_cont diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index bef0be3fd98b..9e83add54290 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -127,6 +127,11 @@ void __init machine_init(unsigned long dt_ptr, unsigned long phys) ppc_md.power_save = ppc6xx_idle; #endif +#ifdef CONFIG_E500 + if (cpu_has_feature(CPU_FTR_CAN_DOZE) || + cpu_has_feature(CPU_FTR_CAN_NAP)) + ppc_md.power_save = e500_idle; +#endif if (ppc_md.progress) ppc_md.progress("id mach(): done", 0x200); } diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index a3dce178b728..18feb63dd3c0 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -347,12 +347,13 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ CPU_FTR_UNIFIED_ID_CACHE) -#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ - CPU_FTR_NODSISRALIGN) -#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ - CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) -#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS | \ +#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ + CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN) +#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ + CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \ CPU_FTR_NODSISRALIGN) +#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) /* 64-bit CPUs */ diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h index 54ed64df95b8..989922621e35 100644 --- a/include/asm-powerpc/machdep.h +++ b/include/asm-powerpc/machdep.h @@ -262,6 +262,7 @@ struct machdep_calls { #endif }; +extern void e500_idle(void); extern void power4_idle(void); extern void power4_cpu_offline_powersave(void); extern void ppc6xx_idle(void); diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index edc0cfd7f6e2..079999b032af 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h @@ -240,7 +240,7 @@ #define HID0_DAPUEN (1<<8) /* Debug APU enable */ #define HID0_SGE (1<<7) /* Store Gathering Enable */ #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ -#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ +#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ #define HID0_ABE (1<<3) /* Address Broadcast Enable */ diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h index a1ab2ba8f1b2..a5e8903bbc87 100644 --- a/include/asm-powerpc/reg_booke.h +++ b/include/asm-powerpc/reg_booke.h @@ -61,6 +61,8 @@ #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ +#define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */ +#define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */ #define SPRN_ATB 0x20E /* Alternate Time Base */ #define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ #define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ -- cgit v1.2.3 From aba11fc50c925bbd6fb25d54eae2f86277a3b107 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Jun 2008 09:40:31 -0500 Subject: powerpc/e500mc: flush L2 on NAP for e500mc If we have an L2CSR register (e500mc) we need to flush the L2 before going to nap. We use the HW flush mechanism provided in that register. The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by any code in the kernel. Additionally we didn't reuse the exist L2CR feature bit as this is intended for the 7xxx L2CR register and L2CSR is part of the new Freescale "Book-E" registers. Signed-off-by: Kumar Gala --- arch/powerpc/kernel/idle_e500.S | 9 +++++++++ include/asm-powerpc/cputable.h | 8 ++++---- include/asm-powerpc/reg_booke.h | 17 +++++++++++++++++ 3 files changed, 30 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/idle_e500.S b/arch/powerpc/kernel/idle_e500.S index 267adec2491b..06304034b393 100644 --- a/arch/powerpc/kernel/idle_e500.S +++ b/arch/powerpc/kernel/idle_e500.S @@ -47,6 +47,15 @@ BEGIN_FTR_SECTION mtlr r0 lis r3,HID0_NAP@h END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) +BEGIN_FTR_SECTION + msync + li r7,L2CSR0_L2FL@l + mtspr SPRN_L2CSR0,r7 +2: + mfspr r7,SPRN_L2CSR0 + andi. r4,r7,L2CSR0_L2FL@l + bne 2b +END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP) 1: /* Go to NAP or DOZE now */ mfspr r4,SPRN_HID0 diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 18feb63dd3c0..9106113ae0b5 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -132,7 +132,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTR_TAU ASM_CONST(0x0000000000000010) #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) -#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080) +#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080) #define CPU_FTR_601 ASM_CONST(0x0000000000000100) #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200) #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) @@ -245,8 +245,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) #define CPU_FTRS_604 (CPU_FTR_COMMON | \ - CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \ - CPU_FTR_PPC_LE) + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE) #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) @@ -353,7 +352,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \ CPU_FTR_NODSISRALIGN) #define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \ + CPU_FTR_L2CSR) #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) /* 64-bit CPUs */ diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h index a5e8903bbc87..be980f4ee495 100644 --- a/include/asm-powerpc/reg_booke.h +++ b/include/asm-powerpc/reg_booke.h @@ -80,6 +80,7 @@ #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ #define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */ #define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */ +#define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ @@ -110,6 +111,8 @@ #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ #define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ +#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */ +#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ #define SPRN_SVR 0x3FF /* System Version Register */ @@ -393,6 +396,20 @@ #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ +/* Bit definitions for L2CSR0. */ +#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ +#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ +#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ +#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ +#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ +#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ +#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ +#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ +#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ +#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ +#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ +#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ + /* Bit definitions for SGR. */ #define SGR_NORMAL 0 /* Speculative fetching allowed. */ #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ -- cgit v1.2.3 From d3c511ac1d72661fcf5f9c6f0ab60b889199a542 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 12 Jun 2008 08:12:49 -0500 Subject: powerpc/cpm: Remove !CONFIG_PPC_CPM_NEW_BINDING code Now that arch/ppc is gone we always define CONFIG_PPC_CPM_NEW_BINDING so we can remove all the code associated with !CONFIG_PPC_CPM_NEW_BINDING. Signed-off-by: Kumar Gala --- include/asm-powerpc/cpm1.h | 20 -------------------- include/asm-powerpc/cpm2.h | 26 -------------------------- 2 files changed, 46 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/cpm1.h b/include/asm-powerpc/cpm1.h index 3df439678006..2ff798744c1d 100644 --- a/include/asm-powerpc/cpm1.h +++ b/include/asm-powerpc/cpm1.h @@ -42,35 +42,15 @@ #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) -#ifndef CONFIG_PPC_CPM_NEW_BINDING -/* The dual ported RAM is multi-functional. Some areas can be (and are - * being) used for microcode. There is an area that can only be used - * as data ram for buffer descriptors, which is all we use right now. - * Currently the first 512 and last 256 bytes are used for microcode. - */ -#define CPM_DATAONLY_BASE ((uint)0x0800) -#define CPM_DATAONLY_SIZE ((uint)0x0700) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) -#endif - /* Export the base address of the communication processor registers * and dual port ram. */ extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */ -#ifdef CONFIG_PPC_CPM_NEW_BINDING #define cpm_dpalloc cpm_muram_alloc #define cpm_dpfree cpm_muram_free #define cpm_dpram_addr cpm_muram_addr #define cpm_dpram_phys cpm_muram_dma -#else -extern unsigned long cpm_dpalloc(uint size, uint align); -extern int cpm_dpfree(unsigned long offset); -extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); -extern void cpm_dpdump(void); -extern void *cpm_dpram_addr(unsigned long offset); -extern uint cpm_dpram_phys(u8 *addr); -#endif extern void cpm_setbrg(uint brg, uint rate); diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h index 4c85ed9cd43f..2c7fd9cee291 100644 --- a/include/asm-powerpc/cpm2.h +++ b/include/asm-powerpc/cpm2.h @@ -78,24 +78,6 @@ #define mk_cr_cmd(PG, SBC, MCN, OP) \ ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) -#ifndef CONFIG_PPC_CPM_NEW_BINDING -/* Dual Port RAM addresses. The first 16K is available for almost - * any CPM use, so we put the BDs there. The first 128 bytes are - * used for SMC1 and SMC2 parameter RAM, so we start allocating - * BDs above that. All of this must change when we start - * downloading RAM microcode. - */ -#define CPM_DATAONLY_BASE ((uint)128) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) -#if defined(CONFIG_8272) || defined(CONFIG_MPC8555) -#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) -#else -#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) -#endif -#endif - /* The number of pages of host memory we allocate for CPM. This is * done early in kernel initialization to get physically contiguous * pages. @@ -107,17 +89,9 @@ */ extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */ -#ifdef CONFIG_PPC_CPM_NEW_BINDING #define cpm_dpalloc cpm_muram_alloc #define cpm_dpfree cpm_muram_free #define cpm_dpram_addr cpm_muram_addr -#else -extern unsigned long cpm_dpalloc(uint size, uint align); -extern int cpm_dpfree(unsigned long offset); -extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); -extern void cpm_dpdump(void); -extern void *cpm_dpram_addr(unsigned long offset); -#endif extern void cpm_setbrg(uint brg, uint rate); extern void cpm2_fastbrg(uint brg, uint rate, int div16); -- cgit v1.2.3 From d14b3dd6190af7ce4f88be68f8df828af6d44584 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 12 Jun 2008 03:42:14 +0400 Subject: powerpc/QE: use arch_initcall to probe QUICC Engine GPIOs It was discussed that global arch_initcall() is preferred way to probe QE GPIOs, so let's use it. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/qe_lib/gpio.c | 5 ++++- include/asm-powerpc/qe.h | 1 - 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c index c712e245dc4c..8e5a0bc36d0b 100644 --- a/arch/powerpc/sysdev/qe_lib/gpio.c +++ b/arch/powerpc/sysdev/qe_lib/gpio.c @@ -12,6 +12,7 @@ */ #include +#include #include #include #include @@ -102,7 +103,7 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) return 0; } -void __init qe_add_gpiochips(void) +static int __init qe_add_gpiochips(void) { struct device_node *np; @@ -143,4 +144,6 @@ err: kfree(qe_gc); /* try others anyway */ } + return 0; } +arch_initcall(qe_add_gpiochips); diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index 1355e7267013..edee15d269ea 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -101,7 +101,6 @@ struct qe_pio_regs { #endif }; -extern void __init qe_add_gpiochips(void); extern int par_io_init(struct device_node *np); extern int par_io_of_config(struct device_node *np); #define QE_PIO_DIR_IN 2 -- cgit v1.2.3 From 9433f6dd3a4677e9b92c6e1cd7f98b11598b7c2c Mon Sep 17 00:00:00 2001 From: Wang Chen Date: Thu, 26 Jun 2008 10:50:04 +0800 Subject: PCI: Fix comment of pci_dynids struct pci_driver has no field of driver_data. It's in pci_device_id. Signed-off-by: Wang Chen Signed-off-by: Jesse Barnes --- include/linux/pci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/pci.h b/include/linux/pci.h index f1f73f79a180..76c9a4a96152 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -338,7 +338,7 @@ struct pci_bus_region { struct pci_dynids { spinlock_t lock; /* protects list, index */ struct list_head list; /* for IDs added at runtime */ - unsigned int use_driver_data:1; /* pci_driver->driver_data is used */ + unsigned int use_driver_data:1; /* pci_device_id->driver_data is used */ }; /* ---------------------------------------------------------------- */ -- cgit v1.2.3 From 74f0609526afddd88bef40b651da24f3167b10b2 Mon Sep 17 00:00:00 2001 From: Nick Piggin Date: Thu, 22 May 2008 00:12:31 +1000 Subject: powerpc: Optimise smp_wmb on 64-bit processors For 64-bit processors, lwsync is the recommended method of store/store ordering on caching enabled memory. For those subarchs which have lwsync, use it rather than eieio for smp_wmb. Signed-off-by: Nick Piggin Signed-off-by: Paul Mackerras --- include/asm-powerpc/system.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index d1ced5029c42..145b70f6d22b 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -30,8 +30,8 @@ * * For wmb(), we use sync since wmb is used in drivers to order * stores to system memory with respect to writes to the device. - * However, smp_wmb() can be a lighter-weight eieio barrier on - * SMP since it is only used to order updates to system memory. + * However, smp_wmb() can be a lighter-weight lwsync or eieio barrier + * on SMP since it is only used to order updates to system memory. */ #define mb() __asm__ __volatile__ ("sync" : : : "memory") #define rmb() __asm__ __volatile__ ("sync" : : : "memory") @@ -43,9 +43,16 @@ #ifdef __KERNEL__ #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */ #ifdef CONFIG_SMP + +#ifdef __SUBARCH_HAS_LWSYNC +# define SMPWMB lwsync +#else +# define SMPWMB eieio +#endif + #define smp_mb() mb() #define smp_rmb() rmb() -#define smp_wmb() eieio() +#define smp_wmb() __asm__ __volatile__ (__stringify(SMPWMB) : : :"memory") #define smp_read_barrier_depends() read_barrier_depends() #else #define smp_mb() barrier() -- cgit v1.2.3 From ff1f4ee94c3c4480b9cee95da2d19668262636c6 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 11 Jun 2008 08:31:00 +1000 Subject: powerpc: Implement OF PCI address accessors stubs for CONFIG_PCI=n To avoid "#ifdef CONFIG_PCI" in the drivers we should provide stubs in place of OF PCI address accessors. Without these stubs build breaks for drivers not strictly requiring PCI, for example CONFIG_FB_OF=y without CONFIG_PCI: LD .tmp_vmlinux1 drivers/built-in.o: In function `offb_map_reg': offb.c:(.text+0x6e7c): undefined reference to `of_get_pci_address' OF PCI IRQ accessors require pci_dev argument, so drivers using PCI IRQs should depend on CONFIG_PCI anyway. Signed-off-by: Anton Vorontsov Signed-off-by: Paul Mackerras --- include/asm-powerpc/prom.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include') diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h index 78b7b0d494c0..eb3bd2e1c7f6 100644 --- a/include/asm-powerpc/prom.h +++ b/include/asm-powerpc/prom.h @@ -212,8 +212,16 @@ extern u64 of_translate_dma_address(struct device_node *dev, */ extern const u32 *of_get_address(struct device_node *dev, int index, u64 *size, unsigned int *flags); +#ifdef CONFIG_PCI extern const u32 *of_get_pci_address(struct device_node *dev, int bar_no, u64 *size, unsigned int *flags); +#else +static inline const u32 *of_get_pci_address(struct device_node *dev, + int bar_no, u64 *size, unsigned int *flags) +{ + return NULL; +} +#endif /* CONFIG_PCI */ /* Get an address as a resource. Note that if your address is * a PIO address, the conversion will fail if the physical address @@ -223,8 +231,16 @@ extern const u32 *of_get_pci_address(struct device_node *dev, int bar_no, */ extern int of_address_to_resource(struct device_node *dev, int index, struct resource *r); +#ifdef CONFIG_PCI extern int of_pci_address_to_resource(struct device_node *dev, int bar, struct resource *r); +#else +static inline int of_pci_address_to_resource(struct device_node *dev, int bar, + struct resource *r) +{ + return -ENOSYS; +} +#endif /* CONFIG_PCI */ /* Parse the ibm,dma-window property of an OF node into the busno, phys and * size parameters. -- cgit v1.2.3 From 41743a4e34f0777f51c1cf0675b91508ba143050 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 11 Jun 2008 15:37:10 +1000 Subject: powerpc: Free a PTE bit on ppc64 with 64K pages This frees a PTE bit when using 64K pages on ppc64. This is done by getting rid of the separate _PAGE_HASHPTE bit. Instead, we just test if any of the 16 sub-page bits is set. For non-combo pages (ie. real 64K pages), we set SUB0 and the location encoding in that field. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras --- arch/powerpc/mm/hash_low_64.S | 17 ++++++++++------- arch/powerpc/mm/hugetlbpage.c | 8 +++++--- include/asm-powerpc/pgtable-4k.h | 1 + include/asm-powerpc/pgtable-64k.h | 17 +++++++++++++++-- include/asm-powerpc/pgtable-ppc64.h | 1 - 5 files changed, 31 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S index 70f4c833fa32..a719f53921a5 100644 --- a/arch/powerpc/mm/hash_low_64.S +++ b/arch/powerpc/mm/hash_low_64.S @@ -388,7 +388,7 @@ _GLOBAL(__hash_page_4K) */ rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */ or r30,r30,r31 - ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED | _PAGE_HASHPTE + ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED oris r30,r30,_PAGE_COMBO@h /* Write the linux PTE atomically (setting busy) */ stdcx. r30,0,r6 @@ -468,7 +468,7 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE) * go to out-of-line code to try to modify the HPTE. We look for * the bit at (1 >> (index + 32)) */ - andi. r0,r31,_PAGE_HASHPTE + rldicl. r0,r31,64-12,48 li r26,0 /* Default hidx */ beq htab_insert_pte @@ -726,11 +726,11 @@ BEGIN_FTR_SECTION bne- ht64_bail_ok END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE) /* Prepare new PTE value (turn access RW into DIRTY, then - * add BUSY,HASHPTE and ACCESSED) + * add BUSY and ACCESSED) */ rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */ or r30,r30,r31 - ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED | _PAGE_HASHPTE + ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED /* Write the linux PTE atomically (setting busy) */ stdcx. r30,0,r6 bne- 1b @@ -798,18 +798,21 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE) /* Check if we may already be in the hashtable, in this case, we * go to out-of-line code to try to modify the HPTE */ - andi. r0,r31,_PAGE_HASHPTE + rldicl. r0,r31,64-12,48 bne ht64_modify_pte ht64_insert_pte: /* Clear hpte bits in new pte (we also clear BUSY btw) and - * add _PAGE_HASHPTE + * add _PAGE_HPTE_SUB0 */ lis r0,_PAGE_HPTEFLAGS@h ori r0,r0,_PAGE_HPTEFLAGS@l andc r30,r30,r0 +#ifdef CONFIG_PPC_64K_PAGES + oris r30,r30,_PAGE_HPTE_SUB0@h +#else ori r30,r30,_PAGE_HASHPTE - +#endif /* Phyical address in r5 */ rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT sldi r5,r5,PAGE_SHIFT diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c index a02266dad215..8fa07f3f6c2b 100644 --- a/arch/powerpc/mm/hugetlbpage.c +++ b/arch/powerpc/mm/hugetlbpage.c @@ -458,8 +458,7 @@ int hash_huge_page(struct mm_struct *mm, unsigned long access, old_pte = pte_val(*ptep); if (old_pte & _PAGE_BUSY) goto out; - new_pte = old_pte | _PAGE_BUSY | - _PAGE_ACCESSED | _PAGE_HASHPTE; + new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED; } while(old_pte != __cmpxchg_u64((unsigned long *)ptep, old_pte, new_pte)); @@ -499,8 +498,11 @@ repeat: HPTES_PER_GROUP) & ~0x7UL; /* clear HPTE slot informations in new PTE */ +#ifdef CONFIG_PPC_64K_PAGES + new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HPTE_SUB0; +#else new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE; - +#endif /* Add in WIMG bits */ /* XXX We should store these in the pte */ /* --BenH: I think they are ... */ diff --git a/include/asm-powerpc/pgtable-4k.h b/include/asm-powerpc/pgtable-4k.h index 818e2abc81e2..fd2090dc1dce 100644 --- a/include/asm-powerpc/pgtable-4k.h +++ b/include/asm-powerpc/pgtable-4k.h @@ -41,6 +41,7 @@ #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* PTE bits */ +#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */ #define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */ #define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */ #define _PAGE_F_SECOND _PAGE_SECONDARY diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h index 1cbd6b377eea..c5007712473f 100644 --- a/include/asm-powerpc/pgtable-64k.h +++ b/include/asm-powerpc/pgtable-64k.h @@ -75,6 +75,20 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd) #define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */ #define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */ +/* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead, + * we set that to be the whole sub-bits mask. The C code will only + * test this, so a multi-bit mask will work. For combo pages, this + * is equivalent as effectively, the old _PAGE_HASHPTE was an OR of + * all the sub bits. For real 64k pages, we now have the assembly set + * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap + * that mask. This is fine as long as the HIDX bits are never set on + * a PTE that isn't hashed, which is the case today. + * + * A little nit is for the huge page C code, which does the hashing + * in C, we need to provide which bit to use. + */ +#define _PAGE_HASHPTE _PAGE_HPTE_SUB + /* Note the full page bits must be in the same location as for normal * 4k pages as the same asssembly will be used to insert 64K pages * wether the kernel has CONFIG_PPC_64K_PAGES or not @@ -83,8 +97,7 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd) #define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */ /* PTE flags to conserve for HPTE identification */ -#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\ - _PAGE_COMBO) +#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO) /* Shift to put page number into pte. * diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h index cc6a43ba41d0..2e48be841cc9 100644 --- a/include/asm-powerpc/pgtable-ppc64.h +++ b/include/asm-powerpc/pgtable-ppc64.h @@ -91,7 +91,6 @@ #define _PAGE_DIRTY 0x0080 /* C: page changed */ #define _PAGE_ACCESSED 0x0100 /* R: page referenced */ #define _PAGE_RW 0x0200 /* software: user write access allowed */ -#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */ #define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */ #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT) -- cgit v1.2.3 From aee10c6145199f872bc51f811b115a4b686b2426 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 12 Jun 2008 19:14:34 +1000 Subject: powerpc: Provide dummy crash_shutdown_register When kexec is disabled, the crash_shutdown_{un,}register functions are not available in the kernel. This provides dummy inline functions for those so that the callers don't have to worry about it. Signed-off-by: Arnd Bergmann Signed-off-by: Paul Mackerras --- include/asm-powerpc/kexec.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h index 701857bc8e24..acdcdc66f1b6 100644 --- a/include/asm-powerpc/kexec.h +++ b/include/asm-powerpc/kexec.h @@ -34,6 +34,8 @@ #ifndef __ASSEMBLY__ #include +typedef void (*crash_shutdown_t)(void); + #ifdef CONFIG_KEXEC #ifdef __powerpc64__ @@ -123,7 +125,6 @@ struct pt_regs; extern void default_machine_kexec(struct kimage *image); extern int default_machine_kexec_prepare(struct kimage *image); extern void default_machine_crash_shutdown(struct pt_regs *regs); -typedef void (*crash_shutdown_t)(void); extern int crash_shutdown_register(crash_shutdown_t handler); extern int crash_shutdown_unregister(crash_shutdown_t handler); @@ -143,6 +144,16 @@ static inline int overlaps_crashkernel(unsigned long start, unsigned long size) static inline void reserve_crashkernel(void) { ; } +static inline int crash_shutdown_register(crash_shutdown_t handler) +{ + return 0; +} + +static inline int crash_shutdown_unregister(crash_shutdown_t handler) +{ + return 0; +} + #endif /* CONFIG_KEXEC */ #endif /* ! __ASSEMBLY__ */ #endif /* __KERNEL__ */ -- cgit v1.2.3 From bf2737f74ffd36f43c6ed11cd2c0826e1d59ad48 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Sat, 14 Jun 2008 09:12:44 +1000 Subject: powerpc: Silly spelling fix in pgtable-ppc32 Signed-off-by: Becky Bruce Signed-off-by: Paul Mackerras --- include/asm-powerpc/pgtable-ppc32.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h index c08e714d0c42..dde466bd2cea 100644 --- a/include/asm-powerpc/pgtable-ppc32.h +++ b/include/asm-powerpc/pgtable-ppc32.h @@ -620,8 +620,8 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, } /* - * 2.6 calles this without flushing the TLB entry, this is wrong - * for our hash-based implementation, we fix that up here + * 2.6 calls this without flushing the TLB entry; this is wrong + * for our hash-based implementation, we fix that up here. */ #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep) -- cgit v1.2.3 From 7c5c4325d2d911fe54db3bc14149bfa558ae0acb Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Sat, 14 Jun 2008 09:41:42 +1000 Subject: powerpc: Change BAT code to use phys_addr_t Currently, the physical address is an unsigned long, but it should be phys_addr_t in set_bat, [v/p]_mapped_by_bat. Also, create a macro that can convert a large physical address into the correct format for programming the BAT registers. Signed-off-by: Becky Bruce Signed-off-by: Paul Mackerras --- arch/powerpc/mm/mmu_decl.h | 2 +- arch/powerpc/mm/pgtable_32.c | 6 +++--- arch/powerpc/mm/ppc_mmu_32.c | 10 +++++----- include/asm-powerpc/mmu-hash32.h | 9 +++++++++ 4 files changed, 18 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h index 04802252a64f..46585b7bb194 100644 --- a/arch/powerpc/mm/mmu_decl.h +++ b/arch/powerpc/mm/mmu_decl.h @@ -29,7 +29,7 @@ extern void hash_preload(struct mm_struct *mm, unsigned long ea, #ifdef CONFIG_PPC32 extern void mapin_ram(void); extern int map_page(unsigned long va, phys_addr_t pa, int flags); -extern void setbat(int index, unsigned long virt, unsigned long phys, +extern void setbat(int index, unsigned long virt, phys_addr_t phys, unsigned int size, int flags); extern void settlbcam(int index, unsigned long virt, phys_addr_t phys, unsigned int size, int flags, unsigned int pid); diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c index e0ff59f21135..c7584072dfcc 100644 --- a/arch/powerpc/mm/pgtable_32.c +++ b/arch/powerpc/mm/pgtable_32.c @@ -53,9 +53,9 @@ extern void hash_page_sync(void); #endif #ifdef HAVE_BATS -extern unsigned long v_mapped_by_bats(unsigned long va); -extern unsigned long p_mapped_by_bats(unsigned long pa); -void setbat(int index, unsigned long virt, unsigned long phys, +extern phys_addr_t v_mapped_by_bats(unsigned long va); +extern unsigned long p_mapped_by_bats(phys_addr_t pa); +void setbat(int index, unsigned long virt, phys_addr_t phys, unsigned int size, int flags); #else /* !HAVE_BATS */ diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c index cef9f156874b..55ec17ed8d7c 100644 --- a/arch/powerpc/mm/ppc_mmu_32.c +++ b/arch/powerpc/mm/ppc_mmu_32.c @@ -46,13 +46,13 @@ union ubat { /* BAT register values to be loaded */ struct batrange { /* stores address ranges mapped by BATs */ unsigned long start; unsigned long limit; - unsigned long phys; + phys_addr_t phys; } bat_addrs[8]; /* * Return PA for this VA if it is mapped by a BAT, or 0 */ -unsigned long v_mapped_by_bats(unsigned long va) +phys_addr_t v_mapped_by_bats(unsigned long va) { int b; for (b = 0; b < 4; ++b) @@ -64,7 +64,7 @@ unsigned long v_mapped_by_bats(unsigned long va) /* * Return VA for a given PA or 0 if not mapped */ -unsigned long p_mapped_by_bats(unsigned long pa) +unsigned long p_mapped_by_bats(phys_addr_t pa) { int b; for (b = 0; b < 4; ++b) @@ -119,7 +119,7 @@ unsigned long __init mmu_mapin_ram(void) * The parameters are not checked; in particular size must be a power * of 2 between 128k and 256M. */ -void __init setbat(int index, unsigned long virt, unsigned long phys, +void __init setbat(int index, unsigned long virt, phys_addr_t phys, unsigned int size, int flags) { unsigned int bl; @@ -138,7 +138,7 @@ void __init setbat(int index, unsigned long virt, unsigned long phys, | _PAGE_COHERENT | _PAGE_GUARDED); wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX; bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */ - bat[1].word[1] = phys | wimgxpp; + bat[1].word[1] = BAT_PHYS_ADDR(phys) | wimgxpp; #ifndef CONFIG_KGDB /* want user access for breakpoints */ if (flags & _PAGE_USER) #endif diff --git a/include/asm-powerpc/mmu-hash32.h b/include/asm-powerpc/mmu-hash32.h index 6e21ca618ec3..f39ff983b381 100644 --- a/include/asm-powerpc/mmu-hash32.h +++ b/include/asm-powerpc/mmu-hash32.h @@ -28,6 +28,15 @@ #define BPP_RW 0x02 /* Read/write */ #ifndef __ASSEMBLY__ +/* Contort a phys_addr_t into the right format/bits for a BAT */ +#ifdef CONFIG_PHYS_64BIT +#define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \ + ((x & 0x0000000e00000000ULL) >> 24) | \ + ((x & 0x0000000100000000ULL) >> 30))) +#else +#define BAT_PHYS_ADDR(x) (x) +#endif + struct ppc_bat { struct { unsigned long bepi:15; /* Effective page index (virtual address) */ -- cgit v1.2.3 From 316a405841cc03723d401b098d188aa4e3daa69b Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Sat, 14 Jun 2008 09:41:43 +1000 Subject: powerpc: Get rid of bitfields in ppc_bat struct While working on the 36-bit physical support, I noticed that there was exactly one line of code that actually referenced the bitfields. So I got rid of them and redefined ppc_bat as a struct of 2 u32's: batu and batl. I also got rid of the previous union that held the bitfield structs and a word representation of the batu/l values. This seems like a nicer solution than adding in a bunch of new bitfields to support extended bat addressing that would never get used, and just leaving the struct as-is would have been incomplete in the face of large physical addressing. Signed-off-by: Becky Bruce Signed-off-by: Paul Mackerras --- arch/powerpc/mm/ppc_mmu_32.c | 19 ++++++++----------- include/asm-powerpc/mmu-hash32.h | 19 ++----------------- 2 files changed, 10 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c index 55ec17ed8d7c..c53145f61942 100644 --- a/arch/powerpc/mm/ppc_mmu_32.c +++ b/arch/powerpc/mm/ppc_mmu_32.c @@ -38,10 +38,7 @@ struct hash_pte *Hash, *Hash_end; unsigned long Hash_size, Hash_mask; unsigned long _SDR1; -union ubat { /* BAT register values to be loaded */ - struct ppc_bat bat; - u32 word[2]; -} BATS[8][2]; /* 8 pairs of IBAT, DBAT */ +struct ppc_bat BATS[8][2]; /* 8 pairs of IBAT, DBAT */ struct batrange { /* stores address ranges mapped by BATs */ unsigned long start; @@ -124,7 +121,7 @@ void __init setbat(int index, unsigned long virt, phys_addr_t phys, { unsigned int bl; int wimgxpp; - union ubat *bat = BATS[index]; + struct ppc_bat *bat = BATS[index]; if (((flags & _PAGE_NO_CACHE) == 0) && cpu_has_feature(CPU_FTR_NEED_COHERENT)) @@ -137,15 +134,15 @@ void __init setbat(int index, unsigned long virt, phys_addr_t phys, wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT | _PAGE_GUARDED); wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX; - bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */ - bat[1].word[1] = BAT_PHYS_ADDR(phys) | wimgxpp; + bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */ + bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp; #ifndef CONFIG_KGDB /* want user access for breakpoints */ if (flags & _PAGE_USER) #endif - bat[1].bat.batu.vp = 1; + bat[1].batu |= 1; /* Vp = 1 */ if (flags & _PAGE_GUARDED) { /* G bit must be zero in IBATs */ - bat[0].word[0] = bat[0].word[1] = 0; + bat[0].batu = bat[0].batl = 0; } else { /* make IBAT same as DBAT */ bat[0] = bat[1]; @@ -158,8 +155,8 @@ void __init setbat(int index, unsigned long virt, phys_addr_t phys, | _PAGE_COHERENT); wimgxpp |= (flags & _PAGE_RW)? ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX; - bat->word[0] = virt | wimgxpp | 4; /* Ks=0, Ku=1 */ - bat->word[1] = phys | bl | 0x40; /* V=1 */ + bat->batu = virt | wimgxpp | 4; /* Ks=0, Ku=1 */ + bat->batl = phys | bl | 0x40; /* V=1 */ } bat_addrs[index].start = virt; diff --git a/include/asm-powerpc/mmu-hash32.h b/include/asm-powerpc/mmu-hash32.h index f39ff983b381..16b1a1e77e64 100644 --- a/include/asm-powerpc/mmu-hash32.h +++ b/include/asm-powerpc/mmu-hash32.h @@ -38,23 +38,8 @@ #endif struct ppc_bat { - struct { - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :4; /* Unused */ - unsigned long bl:11; /* Block size mask */ - unsigned long vs:1; /* Supervisor valid */ - unsigned long vp:1; /* User valid */ - } batu; /* Upper register */ - struct { - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long w:1; /* Write-thru cache */ - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded (MBZ in IBAT) */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page access protections */ - } batl; /* Lower register */ + u32 batu; + u32 batl; }; #endif /* !__ASSEMBLY__ */ -- cgit v1.2.3 From e2d755051129c61a9f67bf752d0b7cc82b115338 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Wed, 18 Jun 2008 02:59:59 +1000 Subject: powerpc: Fix copy-and-paste error in clrsetbits_le16 This was pointed out by Detlev Zundel when this code was being added to U-boot. Signed-off-by: Scott Wood Signed-off-by: Paul Mackerras --- include/asm-powerpc/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h index 6db422d8e2a0..8b627823f5f9 100644 --- a/include/asm-powerpc/io.h +++ b/include/asm-powerpc/io.h @@ -772,7 +772,7 @@ static inline void * bus_to_virt(unsigned long address) #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) -#define clrsetbits_le16(addr, clear, set) clrsetbits(le32, addr, clear, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) -- cgit v1.2.3 From e952e6c4d6635b36c212c056a9427bd93460178c Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 18 Jun 2008 10:47:26 +1000 Subject: powerpc: Add cputable entry for POWER7 Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by: Michael Neuling Signed-off-by: Joel Schopp Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/cputable.c | 25 +++++++++++++++++++++++++ arch/powerpc/kernel/misc.S | 5 +++++ arch/powerpc/kernel/prom_init.c | 1 + include/asm-powerpc/cputable.h | 12 ++++++++++-- 4 files changed, 41 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index f247fc6ad12d..d8d669308403 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -53,6 +53,8 @@ extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec); extern void __restore_cpu_pa6t(void); extern void __restore_cpu_ppc970(void); +extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec); +extern void __restore_cpu_power7(void); #endif /* CONFIG_PPC64 */ /* This table only contains "desktop" CPUs, it need to be filled with embedded @@ -69,6 +71,9 @@ extern void __restore_cpu_ppc970(void); #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\ PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ PPC_FEATURE_TRUE_LE) +#define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ + PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ + PPC_FEATURE_TRUE_LE) #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\ PPC_FEATURE_TRUE_LE | \ PPC_FEATURE_HAS_ALTIVEC_COMP) @@ -381,6 +386,26 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_generic, .platform = "power6", }, + { /* Power7 */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x003f0000, + .cpu_name = "POWER7", + .cpu_features = CPU_FTRS_POWER7, + .cpu_user_features = COMMON_USER_POWER7, + .icache_bsize = 128, + .dcache_bsize = 128, + .num_pmcs = 6, + .pmc_type = PPC_PMC_IBM, + .cpu_setup = __setup_cpu_power7, + .cpu_restore = __restore_cpu_power7, + .oprofile_cpu_type = "ppc64/power7", + .oprofile_type = PPC_OPROFILE_POWER4, + .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV, + .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR, + .oprofile_mmcra_clear = POWER6_MMCRA_THRM | + POWER6_MMCRA_OTHER, + .platform = "power7", + }, { /* Cell Broadband Engine */ .pvr_mask = 0xffff0000, .pvr_value = 0x00700000, diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S index 7b9160220698..85cb6f340846 100644 --- a/arch/powerpc/kernel/misc.S +++ b/arch/powerpc/kernel/misc.S @@ -116,3 +116,8 @@ _GLOBAL(longjmp) mtlr r0 mr r3,r4 blr + +_GLOBAL(__setup_cpu_power7) +_GLOBAL(__restore_cpu_power7) + /* place holder */ + blr diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c index 6d6df1e60325..7585ed181ff8 100644 --- a/arch/powerpc/kernel/prom_init.c +++ b/arch/powerpc/kernel/prom_init.c @@ -650,6 +650,7 @@ static void __init early_cmdline_parse(void) static unsigned char ibm_architecture_vec[] = { W(0xfffe0000), W(0x003a0000), /* POWER5/POWER5+ */ W(0xffff0000), W(0x003e0000), /* POWER6 */ + W(0xffff0000), W(0x003f0000), /* POWER7 */ W(0xffffffff), W(0x0f000002), /* all 2.05-compliant */ W(0xfffffffe), W(0x0f000001), /* all 2.04-compliant and earlier */ 5 - 1, /* 5 option vectors */ diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 9106113ae0b5..3e5b2deafe44 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -26,6 +26,7 @@ #define PPC_FEATURE_PA6T 0x00000800 #define PPC_FEATURE_HAS_DFP 0x00000400 #define PPC_FEATURE_POWER6_EXT 0x00000200 +#define PPC_FEATURE_ARCH_2_06 0x00000100 #define PPC_FEATURE_TRUE_LE 0x00000002 #define PPC_FEATURE_PPC_LE 0x00000001 @@ -379,6 +380,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ CPU_FTR_DSCR) +#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \ + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ + CPU_FTR_MMCRA | CPU_FTR_SMT | \ + CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ + CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ + CPU_FTR_DSCR) #define CPU_FTRS_CELL (CPU_FTR_USE_TB | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ @@ -394,7 +401,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTRS_POSSIBLE \ (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ - CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT) + CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ + CPU_FTR_1T_SEGMENT) #else enum { CPU_FTRS_POSSIBLE = @@ -434,7 +442,7 @@ enum { #define CPU_FTRS_ALWAYS \ (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ - CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) + CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) #else enum { CPU_FTRS_ALWAYS = -- cgit v1.2.3 From 80be038593dba7aa46fb24a14f0ba83e5ade0edb Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Mon, 30 Jun 2008 11:35:53 -0700 Subject: PCI: add stub for pci_set_consistent_dma_mask() When CONFIG_PCI=n, there is no stub for pci_set_consistent_dma_mask(), so add one like other similar stubs. Otherwise there can be build errors, as here: linux-next-20080630/drivers/ssb/main.c:1175: error: implicit declaration of function 'pci_set_consistent_dma_mask' Signed-off-by: Randy Dunlap Signed-off-by: Jesse Barnes --- include/linux/pci.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/linux/pci.h b/include/linux/pci.h index 76c9a4a96152..96ebaa8d80e3 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -853,6 +853,11 @@ static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) return -EIO; } +static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) +{ + return -EIO; +} + static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) { -- cgit v1.2.3 From 3a8247cc2c856930f34eafce33f6a039227ee175 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 18 Jun 2008 15:29:12 +1000 Subject: powerpc: Only demote individual slices rather than whole process At present, if we have a kernel with a 64kB page size, and some process maps something that has to be mapped with 4kB pages (such as a cache-inhibited mapping on POWER5+, or the eHCA infiniband queue-pair pages), we change the process to use 4kB pages everywhere. This hurts the performance of HPC programs that access eHCA from userspace. With this patch, the kernel will only demote the slice(s) containing the eHCA or cache-inhibited mappings, leaving the remaining slices able to use 64kB hardware pages. This also changes the slice_get_unmapped_area code so that it is willing to place a 64k-page mapping into (or across) a 4k-page slice if there is no better alternative, i.e. if the program specified MAP_FIXED or if there is not sufficient space available in slices that are either empty or already have 64k-page mappings in them. Signed-off-by: Paul Mackerras Acked-by: Benjamin Herrenschmidt --- arch/powerpc/mm/hash_utils_64.c | 36 +++++-- arch/powerpc/mm/slice.c | 177 +++++++++++++++++++++++++-------- arch/powerpc/platforms/Kconfig.cputype | 2 +- include/asm-powerpc/page_64.h | 6 ++ 4 files changed, 167 insertions(+), 54 deletions(-) (limited to 'include') diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index bf5b6d7ed30f..8d3b58ebd38e 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -695,6 +695,28 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) return pp; } +#ifdef CONFIG_PPC_MM_SLICES +unsigned int get_paca_psize(unsigned long addr) +{ + unsigned long index, slices; + + if (addr < SLICE_LOW_TOP) { + slices = get_paca()->context.low_slices_psize; + index = GET_LOW_SLICE_INDEX(addr); + } else { + slices = get_paca()->context.high_slices_psize; + index = GET_HIGH_SLICE_INDEX(addr); + } + return (slices >> (index * 4)) & 0xF; +} + +#else +unsigned int get_paca_psize(unsigned long addr) +{ + return get_paca()->context.user_psize; +} +#endif + /* * Demote a segment to using 4k pages. * For now this makes the whole process use 4k pages. @@ -702,13 +724,13 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) #ifdef CONFIG_PPC_64K_PAGES void demote_segment_4k(struct mm_struct *mm, unsigned long addr) { - if (mm->context.user_psize == MMU_PAGE_4K) + if (get_slice_psize(mm, addr) == MMU_PAGE_4K) return; - slice_set_user_psize(mm, MMU_PAGE_4K); + slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); #ifdef CONFIG_SPU_BASE spu_flush_all_slbs(mm); #endif - if (get_paca()->context.user_psize != MMU_PAGE_4K) { + if (get_paca_psize(addr) != MMU_PAGE_4K) { get_paca()->context = mm->context; slb_flush_and_rebolt(); } @@ -792,11 +814,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap) DBG_LOW(" user region with no mm !\n"); return 1; } -#ifdef CONFIG_PPC_MM_SLICES psize = get_slice_psize(mm, ea); -#else - psize = mm->context.user_psize; -#endif ssize = user_segment_size(ea); vsid = get_vsid(mm->context.id, ea, ssize); break; @@ -868,7 +886,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap) /* Do actual hashing */ #ifdef CONFIG_PPC_64K_PAGES /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */ - if (pte_val(*ptep) & _PAGE_4K_PFN) { + if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) { demote_segment_4k(mm, ea); psize = MMU_PAGE_4K; } @@ -897,7 +915,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap) } } if (user_region) { - if (psize != get_paca()->context.user_psize) { + if (psize != get_paca_psize(ea)) { get_paca()->context = mm->context; slb_flush_and_rebolt(); } diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c index ad928edafb0a..583be67ad938 100644 --- a/arch/powerpc/mm/slice.c +++ b/arch/powerpc/mm/slice.c @@ -215,10 +215,7 @@ static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psiz mm->context.high_slices_psize); spin_unlock_irqrestore(&slice_convert_lock, flags); - mb(); - /* XXX this is sub-optimal but will do for now */ - on_each_cpu(slice_flush_segments, mm, 0, 1); #ifdef CONFIG_SPU_BASE spu_flush_all_slbs(mm); #endif @@ -384,17 +381,34 @@ static unsigned long slice_find_area(struct mm_struct *mm, unsigned long len, return slice_find_area_bottomup(mm, len, mask, psize, use_cache); } +#define or_mask(dst, src) do { \ + (dst).low_slices |= (src).low_slices; \ + (dst).high_slices |= (src).high_slices; \ +} while (0) + +#define andnot_mask(dst, src) do { \ + (dst).low_slices &= ~(src).low_slices; \ + (dst).high_slices &= ~(src).high_slices; \ +} while (0) + +#ifdef CONFIG_PPC_64K_PAGES +#define MMU_PAGE_BASE MMU_PAGE_64K +#else +#define MMU_PAGE_BASE MMU_PAGE_4K +#endif + unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len, unsigned long flags, unsigned int psize, int topdown, int use_cache) { - struct slice_mask mask; + struct slice_mask mask = {0, 0}; struct slice_mask good_mask; struct slice_mask potential_mask = {0,0} /* silence stupid warning */; - int pmask_set = 0; + struct slice_mask compat_mask = {0, 0}; int fixed = (flags & MAP_FIXED); int pshift = max_t(int, mmu_psize_defs[psize].shift, PAGE_SHIFT); struct mm_struct *mm = current->mm; + unsigned long newaddr; /* Sanity checks */ BUG_ON(mm->task_size == 0); @@ -416,21 +430,48 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len, if (!fixed && addr) { addr = _ALIGN_UP(addr, 1ul << pshift); slice_dbg(" aligned addr=%lx\n", addr); + /* Ignore hint if it's too large or overlaps a VMA */ + if (addr > mm->task_size - len || + !slice_area_is_free(mm, addr, len)) + addr = 0; } - /* First makeup a "good" mask of slices that have the right size + /* First make up a "good" mask of slices that have the right size * already */ good_mask = slice_mask_for_size(mm, psize); slice_print_mask(" good_mask", good_mask); - /* First check hint if it's valid or if we have MAP_FIXED */ - if ((addr != 0 || fixed) && (mm->task_size - len) >= addr) { + /* + * Here "good" means slices that are already the right page size, + * "compat" means slices that have a compatible page size (i.e. + * 4k in a 64k pagesize kernel), and "free" means slices without + * any VMAs. + * + * If MAP_FIXED: + * check if fits in good | compat => OK + * check if fits in good | compat | free => convert free + * else bad + * If have hint: + * check if hint fits in good => OK + * check if hint fits in good | free => convert free + * Otherwise: + * search in good, found => OK + * search in good | free, found => convert free + * search in good | compat | free, found => convert free. + */ - /* Don't bother with hint if it overlaps a VMA */ - if (!fixed && !slice_area_is_free(mm, addr, len)) - goto search; +#ifdef CONFIG_PPC_64K_PAGES + /* If we support combo pages, we can allow 64k pages in 4k slices */ + if (psize == MMU_PAGE_64K) { + compat_mask = slice_mask_for_size(mm, MMU_PAGE_4K); + if (fixed) + or_mask(good_mask, compat_mask); + } +#endif + /* First check hint if it's valid or if we have MAP_FIXED */ + if (addr != 0 || fixed) { /* Build a mask for the requested range */ mask = slice_range_to_mask(addr, len); slice_print_mask(" mask", mask); @@ -442,54 +483,66 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len, slice_dbg(" fits good !\n"); return addr; } - - /* We don't fit in the good mask, check what other slices are - * empty and thus can be converted + } else { + /* Now let's see if we can find something in the existing + * slices for that size */ - potential_mask = slice_mask_for_free(mm); - potential_mask.low_slices |= good_mask.low_slices; - potential_mask.high_slices |= good_mask.high_slices; - pmask_set = 1; - slice_print_mask(" potential", potential_mask); - if (slice_check_fit(mask, potential_mask)) { - slice_dbg(" fits potential !\n"); - goto convert; + newaddr = slice_find_area(mm, len, good_mask, psize, topdown, + use_cache); + if (newaddr != -ENOMEM) { + /* Found within the good mask, we don't have to setup, + * we thus return directly + */ + slice_dbg(" found area at 0x%lx\n", newaddr); + return newaddr; } } - /* If we have MAP_FIXED and failed the above step, then error out */ + /* We don't fit in the good mask, check what other slices are + * empty and thus can be converted + */ + potential_mask = slice_mask_for_free(mm); + or_mask(potential_mask, good_mask); + slice_print_mask(" potential", potential_mask); + + if ((addr != 0 || fixed) && slice_check_fit(mask, potential_mask)) { + slice_dbg(" fits potential !\n"); + goto convert; + } + + /* If we have MAP_FIXED and failed the above steps, then error out */ if (fixed) return -EBUSY; - search: slice_dbg(" search...\n"); - /* Now let's see if we can find something in the existing slices - * for that size + /* If we had a hint that didn't work out, see if we can fit + * anywhere in the good area. */ - addr = slice_find_area(mm, len, good_mask, psize, topdown, use_cache); - if (addr != -ENOMEM) { - /* Found within the good mask, we don't have to setup, - * we thus return directly - */ - slice_dbg(" found area at 0x%lx\n", addr); - return addr; - } - - /* Won't fit, check what can be converted */ - if (!pmask_set) { - potential_mask = slice_mask_for_free(mm); - potential_mask.low_slices |= good_mask.low_slices; - potential_mask.high_slices |= good_mask.high_slices; - pmask_set = 1; - slice_print_mask(" potential", potential_mask); + if (addr) { + addr = slice_find_area(mm, len, good_mask, psize, topdown, + use_cache); + if (addr != -ENOMEM) { + slice_dbg(" found area at 0x%lx\n", addr); + return addr; + } } /* Now let's see if we can find something in the existing slices - * for that size + * for that size plus free slices */ addr = slice_find_area(mm, len, potential_mask, psize, topdown, use_cache); + +#ifdef CONFIG_PPC_64K_PAGES + if (addr == -ENOMEM && psize == MMU_PAGE_64K) { + /* retry the search with 4k-page slices included */ + or_mask(potential_mask, compat_mask); + addr = slice_find_area(mm, len, potential_mask, psize, + topdown, use_cache); + } +#endif + if (addr == -ENOMEM) return -ENOMEM; @@ -498,7 +551,13 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len, slice_print_mask(" mask", mask); convert: - slice_convert(mm, mask, psize); + andnot_mask(mask, good_mask); + andnot_mask(mask, compat_mask); + if (mask.low_slices || mask.high_slices) { + slice_convert(mm, mask, psize); + if (psize > MMU_PAGE_BASE) + on_each_cpu(slice_flush_segments, mm, 0, 1); + } return addr; } @@ -598,6 +657,36 @@ void slice_set_user_psize(struct mm_struct *mm, unsigned int psize) spin_unlock_irqrestore(&slice_convert_lock, flags); } +void slice_set_psize(struct mm_struct *mm, unsigned long address, + unsigned int psize) +{ + unsigned long i, flags; + u64 *p; + + spin_lock_irqsave(&slice_convert_lock, flags); + if (address < SLICE_LOW_TOP) { + i = GET_LOW_SLICE_INDEX(address); + p = &mm->context.low_slices_psize; + } else { + i = GET_HIGH_SLICE_INDEX(address); + p = &mm->context.high_slices_psize; + } + *p = (*p & ~(0xful << (i * 4))) | ((unsigned long) psize << (i * 4)); + spin_unlock_irqrestore(&slice_convert_lock, flags); + +#ifdef CONFIG_SPU_BASE + spu_flush_all_slbs(mm); +#endif +} + +void slice_set_range_psize(struct mm_struct *mm, unsigned long start, + unsigned long len, unsigned int psize) +{ + struct slice_mask mask = slice_range_to_mask(start, len); + + slice_convert(mm, mask, psize); +} + /* * is_hugepage_only_range() is used by generic code to verify wether * a normal mmap mapping (non hugetlbfs) is valid on a given area. diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype index 1a1ccfbb9232..c66b8ed7e7d9 100644 --- a/arch/powerpc/platforms/Kconfig.cputype +++ b/arch/powerpc/platforms/Kconfig.cputype @@ -187,7 +187,7 @@ config PPC_STD_MMU_32 config PPC_MM_SLICES bool - default y if HUGETLB_PAGE + default y if HUGETLB_PAGE || PPC_64K_PAGES default n config VIRT_CPU_ACCOUNTING diff --git a/include/asm-powerpc/page_64.h b/include/asm-powerpc/page_64.h index 25af4fc8daf4..02fd80710e9d 100644 --- a/include/asm-powerpc/page_64.h +++ b/include/asm-powerpc/page_64.h @@ -126,16 +126,22 @@ extern unsigned int get_slice_psize(struct mm_struct *mm, extern void slice_init_context(struct mm_struct *mm, unsigned int psize); extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize); +extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start, + unsigned long len, unsigned int psize); + #define slice_mm_new_context(mm) ((mm)->context.id == 0) #endif /* __ASSEMBLY__ */ #else #define slice_init() +#define get_slice_psize(mm, addr) ((mm)->context.user_psize) #define slice_set_user_psize(mm, psize) \ do { \ (mm)->context.user_psize = (psize); \ (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \ } while (0) +#define slice_set_range_psize(mm, start, len, psize) \ + slice_set_user_psize((mm), (psize)) #define slice_mm_new_context(mm) 1 #endif /* CONFIG_PPC_MM_SLICES */ -- cgit v1.2.3 From 9b4a8dd2e9f8af206eb39e3d99c442b0d6158953 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Tue, 24 Jun 2008 03:46:57 +1000 Subject: drivers/macintosh: Various cleanups This contains the following cleanups: - make the following needlessly global code static: - adb.c: adb_controller - adb.c: adb_init() - adbhid.c: adb_to_linux_keycodes[] (also make it const) - via-pmu68k.c: backlight_level - via-pmu68k.c: backlight_enabled - remove the following unused code: - via-pmu68k.c: sleep_notifier_list Signed-off-by: Adrian Bunk Acked-by: Geert Uytterhoeven Acked-by: Stephen Rothwell Signed-off-by: Paul Mackerras --- drivers/macintosh/adb.c | 5 ++--- drivers/macintosh/adbhid.c | 2 +- drivers/macintosh/via-pmu68k.c | 5 ++--- include/linux/adb.h | 1 - 4 files changed, 5 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/drivers/macintosh/adb.c b/drivers/macintosh/adb.c index dbaad39020a1..61b62a6f681b 100644 --- a/drivers/macintosh/adb.c +++ b/drivers/macintosh/adb.c @@ -46,7 +46,6 @@ #endif -EXPORT_SYMBOL(adb_controller); EXPORT_SYMBOL(adb_client_list); extern struct adb_driver via_macii_driver; @@ -80,7 +79,7 @@ static struct adb_driver *adb_driver_list[] = { static struct class *adb_dev_class; -struct adb_driver *adb_controller; +static struct adb_driver *adb_controller; BLOCKING_NOTIFIER_HEAD(adb_client_list); static int adb_got_sleep; static int adb_inited; @@ -290,7 +289,7 @@ static int adb_resume(struct platform_device *dev) } #endif /* CONFIG_PM */ -int __init adb_init(void) +static int __init adb_init(void) { struct adb_driver *driver; int i; diff --git a/drivers/macintosh/adbhid.c b/drivers/macintosh/adbhid.c index ef4c117ea35f..59ea520a5d7a 100644 --- a/drivers/macintosh/adbhid.c +++ b/drivers/macintosh/adbhid.c @@ -75,7 +75,7 @@ static struct notifier_block adbhid_adb_notifier = { #define ADB_KEY_POWER_OLD 0x7e #define ADB_KEY_POWER 0x7f -u16 adb_to_linux_keycodes[128] = { +static const u16 adb_to_linux_keycodes[128] = { /* 0x00 */ KEY_A, /* 30 */ /* 0x01 */ KEY_S, /* 31 */ /* 0x02 */ KEY_D, /* 32 */ diff --git a/drivers/macintosh/via-pmu68k.c b/drivers/macintosh/via-pmu68k.c index e2f84da09e7c..b64741c95ac4 100644 --- a/drivers/macintosh/via-pmu68k.c +++ b/drivers/macintosh/via-pmu68k.c @@ -101,7 +101,6 @@ static int pmu_kind = PMU_UNKNOWN; static int pmu_fully_inited; int asleep; -BLOCKING_NOTIFIER_HEAD(sleep_notifier_list); static int pmu_probe(void); static int pmu_init(void); @@ -741,8 +740,8 @@ pmu_handle_data(unsigned char *data, int len) } } -int backlight_level = -1; -int backlight_enabled = 0; +static int backlight_level = -1; +static int backlight_enabled = 0; #define LEVEL_TO_BRIGHT(lev) ((lev) < 1? 0x7f: 0x4a - ((lev) << 1)) diff --git a/include/linux/adb.h b/include/linux/adb.h index 64d8878e1444..63bca502fa55 100644 --- a/include/linux/adb.h +++ b/include/linux/adb.h @@ -84,7 +84,6 @@ enum adb_message { ADB_MSG_PRE_RESET, /* Called before resetting the bus */ ADB_MSG_POST_RESET /* Called after resetting the bus (re-do init & register) */ }; -extern struct adb_driver *adb_controller; extern struct blocking_notifier_head adb_client_list; int adb_request(struct adb_request *req, void (*done)(struct adb_request *), -- cgit v1.2.3 From d1cdcf2241723d6596d56abb8777b5ef79b4a878 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Tue, 24 Jun 2008 03:48:21 +1000 Subject: powerpc: Don't export asm/asm-compat.h to userspace asm/asm-compat.h doesn't seem to be intended for userspace usage. Signed-off-by: Adrian Bunk Signed-off-by: Paul Mackerras --- include/asm-powerpc/Kbuild | 1 - include/asm-powerpc/cputable.h | 5 +++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild index bca352e033c3..34a0a8db0104 100644 --- a/include/asm-powerpc/Kbuild +++ b/include/asm-powerpc/Kbuild @@ -23,7 +23,6 @@ header-y += sigcontext.h header-y += statfs.h header-y += ps3fb.h -unifdef-y += asm-compat.h unifdef-y += bootx.h unifdef-y += byteorder.h unifdef-y += cputable.h diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 3e5b2deafe44..3189ac5d0a69 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -1,8 +1,6 @@ #ifndef __ASM_POWERPC_CPUTABLE_H #define __ASM_POWERPC_CPUTABLE_H -#include - #define PPC_FEATURE_32 0x80000000 #define PPC_FEATURE_64 0x40000000 #define PPC_FEATURE_601_INSTR 0x20000000 @@ -32,6 +30,9 @@ #define PPC_FEATURE_PPC_LE 0x00000001 #ifdef __KERNEL__ + +#include + #ifndef __ASSEMBLY__ /* This structure can grow, it's real size is used by head.S code -- cgit v1.2.3 From 178f8d78fdeaace8b22a759a059b74f39caf23a4 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Tue, 24 Jun 2008 03:48:28 +1000 Subject: powerpc: asm/elf.h: Reduce userspace header This makes asm/elf.h export less non-userspace stuff to userspace. Signed-off-by: Adrian Bunk Signed-off-by: Paul Mackerras --- include/asm-powerpc/elf.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h index 9080d85cb9d0..d1e3bda0625d 100644 --- a/include/asm-powerpc/elf.h +++ b/include/asm-powerpc/elf.h @@ -224,8 +224,6 @@ extern int dump_task_altivec(struct task_struct *, elf_vrregset_t *vrregs); #define ELF_CORE_XFPREG_TYPE NT_PPC_VMX #endif -#endif /* __KERNEL__ */ - /* ELF_HWCAP yields a mask that user programs can use to figure out what instruction set this cpu supports. This could be done in userspace, but it's not easy, and we've already done it here. */ @@ -243,8 +241,6 @@ extern int dump_task_altivec(struct task_struct *, elf_vrregset_t *vrregs); } while (0) #endif /* __powerpc64__ */ -#ifdef __KERNEL__ - #ifdef __powerpc64__ # define SET_PERSONALITY(ex, ibcs2) \ do { \ @@ -272,8 +268,6 @@ do { \ # define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) #endif /* __powerpc64__ */ -#endif /* __KERNEL__ */ - extern int dcache_bsize; extern int icache_bsize; extern int ucache_bsize; @@ -285,6 +279,8 @@ extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack); #define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b); +#endif /* __KERNEL__ */ + /* * The requirements here are: * - keep the final alignment of sp (sp & 0xf) @@ -422,6 +418,8 @@ do { \ /* Keep this the last entry. */ #define R_PPC64_NUM 107 +#ifdef __KERNEL__ + #ifdef CONFIG_SPU_BASE /* Notes used in ET_CORE. Note name is "SPU//". */ #define NT_SPU 1 @@ -430,4 +428,6 @@ do { \ #endif /* CONFIG_SPU_BASE */ +#endif /* __KERNEL */ + #endif /* _ASM_POWERPC_ELF_H */ -- cgit v1.2.3 From aaddd3eacaeaef3503035750b3f21ac2bfe97cbf Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 24 Jun 2008 11:32:21 +1000 Subject: powerpc: Move code patching code into arch/powerpc/lib/code-patching.c We currently have a few routines for patching code in asm/system.h, because they didn't fit anywhere else. I'd like to clean them up a little and add some more, so first move them into a dedicated C file - they don't need to be inlined. While we're moving the code, drop create_function_call(), it's intended caller never got merged and will be replaced in future with something different. Signed-off-by: Michael Ellerman Acked-by: Kumar Gala Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/crash_dump.c | 1 + arch/powerpc/lib/Makefile | 2 ++ arch/powerpc/lib/code-patching.c | 33 +++++++++++++++++++++ arch/powerpc/platforms/86xx/mpc86xx_smp.c | 1 + arch/powerpc/platforms/powermac/smp.c | 1 + include/asm-powerpc/code-patching.h | 25 ++++++++++++++++ include/asm-powerpc/system.h | 48 ------------------------------- 7 files changed, 63 insertions(+), 48 deletions(-) create mode 100644 arch/powerpc/lib/code-patching.c create mode 100644 include/asm-powerpc/code-patching.h (limited to 'include') diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c index 9ee3c5278db0..35b9a668b0e1 100644 --- a/arch/powerpc/kernel/crash_dump.c +++ b/arch/powerpc/kernel/crash_dump.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index e522b06cc42f..e7f7042b9f61 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -24,3 +24,5 @@ obj-$(CONFIG_SMP) += locks.o endif obj-$(CONFIG_PPC_LIB_RHEAP) += rheap.o + +obj-y += code-patching.o diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c new file mode 100644 index 000000000000..7afae88ed1d4 --- /dev/null +++ b/arch/powerpc/lib/code-patching.c @@ -0,0 +1,33 @@ +/* + * Copyright 2008 Michael Ellerman, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include + + +void create_instruction(unsigned long addr, unsigned int instr) +{ + unsigned int *p; + p = (unsigned int *)addr; + *p = instr; + asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p)); +} + +void create_branch(unsigned long addr, unsigned long target, int flags) +{ + unsigned int instruction; + + if (! (flags & BRANCH_ABSOLUTE)) + target = target - addr; + + /* Mask out the flags and target, so they don't step on each other. */ + instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC); + + create_instruction(addr, instruction); +} diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c index ba55b0ff0f74..63f55853cd69 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index cb2d894541c6..bf202f7eadf8 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c @@ -36,6 +36,7 @@ #include #include +#include #include #include #include diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h new file mode 100644 index 000000000000..0b91fdf944db --- /dev/null +++ b/include/asm-powerpc/code-patching.h @@ -0,0 +1,25 @@ +#ifndef _ASM_POWERPC_CODE_PATCHING_H +#define _ASM_POWERPC_CODE_PATCHING_H + +/* + * Copyright 2008, Michael Ellerman, IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/* Flags for create_branch: + * "b" == create_branch(addr, target, 0); + * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE); + * "bl" == create_branch(addr, target, BRANCH_SET_LINK); + * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK); + */ +#define BRANCH_SET_LINK 0x1 +#define BRANCH_ABSOLUTE 0x2 + +extern void create_branch(unsigned long addr, unsigned long target, int flags); +extern void create_instruction(unsigned long addr, unsigned int instr); + +#endif /* _ASM_POWERPC_CODE_PATCHING_H */ diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 145b70f6d22b..2642a92b724f 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -526,54 +526,6 @@ extern void reloc_got2(unsigned long); #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x))) -static inline void create_instruction(unsigned long addr, unsigned int instr) -{ - unsigned int *p; - p = (unsigned int *)addr; - *p = instr; - asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p)); -} - -/* Flags for create_branch: - * "b" == create_branch(addr, target, 0); - * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE); - * "bl" == create_branch(addr, target, BRANCH_SET_LINK); - * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK); - */ -#define BRANCH_SET_LINK 0x1 -#define BRANCH_ABSOLUTE 0x2 - -static inline void create_branch(unsigned long addr, - unsigned long target, int flags) -{ - unsigned int instruction; - - if (! (flags & BRANCH_ABSOLUTE)) - target = target - addr; - - /* Mask out the flags and target, so they don't step on each other. */ - instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC); - - create_instruction(addr, instruction); -} - -static inline void create_function_call(unsigned long addr, void * func) -{ - unsigned long func_addr; - -#ifdef CONFIG_PPC64 - /* - * On PPC64 the function pointer actually points to the function's - * descriptor. The first entry in the descriptor is the address - * of the function text. - */ - func_addr = *(unsigned long *)func; -#else - func_addr = (unsigned long)func; -#endif - create_branch(addr, func_addr, BRANCH_SET_LINK); -} - #ifdef CONFIG_VIRT_CPU_ACCOUNTING extern void account_system_vtime(struct task_struct *); #endif -- cgit v1.2.3 From e7a57273c6407bb6903fbaddec8c2119bf318617 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 24 Jun 2008 11:32:22 +1000 Subject: powerpc: Allow create_branch() to return errors Currently create_branch() creates a branch instruction for you, and patches it into the call site. In some circumstances it would be nice to be able to create the instruction and patch it later, and also some code might want to check for errors in the branch creation before doing the patching. A future commit will change create_branch() to check for errors. For callers that don't care, replace create_branch() with patch_branch(), which just creates the branch and patches it directly. While we're touching all the callers, change to using unsigned int *, as this seems to match usage better. That allows (and requires) us to remove the volatile in the definition of vector in powermac/smp.c and mpc86xx_smp.c, that's correct because now that we're passing vector as an unsigned int * the compiler knows that it's value might change across the patch_branch() call. Signed-off-by: Michael Ellerman Acked-by: Kumar Gala Acked-by: Jon Loeliger Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/crash_dump.c | 6 ++++-- arch/powerpc/lib/code-patching.c | 20 ++++++++++++-------- arch/powerpc/platforms/86xx/mpc86xx_smp.c | 5 ++--- arch/powerpc/platforms/powermac/smp.c | 5 ++--- include/asm-powerpc/code-patching.h | 6 ++++-- 5 files changed, 24 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c index 35b9a668b0e1..26648544d5e4 100644 --- a/arch/powerpc/kernel/crash_dump.c +++ b/arch/powerpc/kernel/crash_dump.c @@ -34,6 +34,8 @@ void __init reserve_kdump_trampoline(void) static void __init create_trampoline(unsigned long addr) { + unsigned int *p = (unsigned int *)addr; + /* The maximum range of a single instruction branch, is the current * instruction's address + (32 MB - 4) bytes. For the trampoline we * need to branch to current address + 32 MB. So we insert a nop at @@ -42,8 +44,8 @@ static void __init create_trampoline(unsigned long addr) * branch to "addr" we jump to ("addr" + 32 MB). Although it requires * two instructions it doesn't require any registers. */ - create_instruction(addr, 0x60000000); /* nop */ - create_branch(addr + 4, addr + PHYSICAL_START, 0); + patch_instruction(p, 0x60000000); /* nop */ + patch_branch(++p, addr + PHYSICAL_START, 0); } void __init setup_kdump_trampoline(void) diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c index 7afae88ed1d4..638dde313cbc 100644 --- a/arch/powerpc/lib/code-patching.c +++ b/arch/powerpc/lib/code-patching.c @@ -11,23 +11,27 @@ #include -void create_instruction(unsigned long addr, unsigned int instr) +void patch_instruction(unsigned int *addr, unsigned int instr) { - unsigned int *p; - p = (unsigned int *)addr; - *p = instr; - asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p)); + *addr = instr; + asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (addr)); } -void create_branch(unsigned long addr, unsigned long target, int flags) +void patch_branch(unsigned int *addr, unsigned long target, int flags) +{ + patch_instruction(addr, create_branch(addr, target, flags)); +} + +unsigned int create_branch(const unsigned int *addr, + unsigned long target, int flags) { unsigned int instruction; if (! (flags & BRANCH_ABSOLUTE)) - target = target - addr; + target = target - (unsigned long)addr; /* Mask out the flags and target, so they don't step on each other. */ instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC); - create_instruction(addr, instruction); + return instruction; } diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c index 63f55853cd69..835f2dc24dc9 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c @@ -57,8 +57,7 @@ smp_86xx_kick_cpu(int nr) unsigned int save_vector; unsigned long target, flags; int n = 0; - volatile unsigned int *vector - = (volatile unsigned int *)(KERNELBASE + 0x100); + unsigned int *vector = (unsigned int *)(KERNELBASE + 0x100); if (nr < 0 || nr >= NR_CPUS) return; @@ -72,7 +71,7 @@ smp_86xx_kick_cpu(int nr) /* Setup fake reset vector to call __secondary_start_mpc86xx. */ target = (unsigned long) __secondary_start_mpc86xx; - create_branch((unsigned long)vector, target, BRANCH_SET_LINK); + patch_branch(vector, target, BRANCH_SET_LINK); /* Kick that CPU */ smp_86xx_release_core(nr); diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index bf202f7eadf8..4ae3d00e0bdd 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c @@ -787,8 +787,7 @@ static void __devinit smp_core99_kick_cpu(int nr) { unsigned int save_vector; unsigned long target, flags; - volatile unsigned int *vector - = ((volatile unsigned int *)(KERNELBASE+0x100)); + unsigned int *vector = (unsigned int *)(KERNELBASE+0x100); if (nr < 0 || nr > 3) return; @@ -805,7 +804,7 @@ static void __devinit smp_core99_kick_cpu(int nr) * b __secondary_start_pmac_0 + nr*8 - KERNELBASE */ target = (unsigned long) __secondary_start_pmac_0 + nr * 8; - create_branch((unsigned long)vector, target, BRANCH_SET_LINK); + patch_branch(vector, target, BRANCH_SET_LINK); /* Put some life in our friend */ pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h index 0b91fdf944db..fdb187cbc40d 100644 --- a/include/asm-powerpc/code-patching.h +++ b/include/asm-powerpc/code-patching.h @@ -19,7 +19,9 @@ #define BRANCH_SET_LINK 0x1 #define BRANCH_ABSOLUTE 0x2 -extern void create_branch(unsigned long addr, unsigned long target, int flags); -extern void create_instruction(unsigned long addr, unsigned int instr); +unsigned int create_branch(const unsigned int *addr, + unsigned long target, int flags); +void patch_branch(unsigned int *addr, unsigned long target, int flags); +void patch_instruction(unsigned int *addr, unsigned int instr); #endif /* _ASM_POWERPC_CODE_PATCHING_H */ -- cgit v1.2.3 From 07630a37beefe8e4401c602f04e3e5bcbba50b31 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 24 Jun 2008 11:32:28 +1000 Subject: powerpc: Add ppc_function_entry() which gets the entry point for a function Because function pointers point to different things on 32-bit vs 64-bit, add a macro that deals with dereferencing the OPD on 64-bit. The soon to be merged ftrace wants this, as well as other code I am working on. Signed-off-by: Michael Ellerman Acked-by: Kumar Gala Signed-off-by: Paul Mackerras --- include/asm-powerpc/code-patching.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include') diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h index fdb187cbc40d..a45a7ff78725 100644 --- a/include/asm-powerpc/code-patching.h +++ b/include/asm-powerpc/code-patching.h @@ -10,6 +10,8 @@ * 2 of the License, or (at your option) any later version. */ +#include + /* Flags for create_branch: * "b" == create_branch(addr, target, 0); * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE); @@ -24,4 +26,18 @@ unsigned int create_branch(const unsigned int *addr, void patch_branch(unsigned int *addr, unsigned long target, int flags); void patch_instruction(unsigned int *addr, unsigned int instr); +static inline unsigned long ppc_function_entry(void *func) +{ +#ifdef CONFIG_PPC64 + /* + * On PPC64 the function pointer actually points to the function's + * descriptor. The first entry in the descriptor is the address + * of the function text. + */ + return ((func_descr_t *)func)->entry; +#else + return (unsigned long)func; +#endif +} + #endif /* _ASM_POWERPC_CODE_PATCHING_H */ -- cgit v1.2.3 From 411781a290b0d0a31fd73826b3ee110f1e3cc3b6 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 24 Jun 2008 11:32:29 +1000 Subject: powerpc: Add new code patching routines This commit adds some new routines for patching code, which will be used in a following commit. Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras --- arch/powerpc/lib/code-patching.c | 107 ++++++++++++++++++++++++++++++++++++ include/asm-powerpc/code-patching.h | 8 +++ 2 files changed, 115 insertions(+) (limited to 'include') diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c index 430f4c15d786..27957c4ea9e0 100644 --- a/arch/powerpc/lib/code-patching.c +++ b/arch/powerpc/lib/code-patching.c @@ -41,3 +41,110 @@ unsigned int create_branch(const unsigned int *addr, return instruction; } + +unsigned int create_cond_branch(const unsigned int *addr, + unsigned long target, int flags) +{ + unsigned int instruction; + long offset; + + offset = target; + if (! (flags & BRANCH_ABSOLUTE)) + offset = offset - (unsigned long)addr; + + /* Check we can represent the target in the instruction format */ + if (offset < -0x8000 || offset > 0x7FFF || offset & 0x3) + return 0; + + /* Mask out the flags and target, so they don't step on each other. */ + instruction = 0x40000000 | (flags & 0x3FF0003) | (offset & 0xFFFC); + + return instruction; +} + +static unsigned int branch_opcode(unsigned int instr) +{ + return (instr >> 26) & 0x3F; +} + +static int instr_is_branch_iform(unsigned int instr) +{ + return branch_opcode(instr) == 18; +} + +static int instr_is_branch_bform(unsigned int instr) +{ + return branch_opcode(instr) == 16; +} + +int instr_is_relative_branch(unsigned int instr) +{ + if (instr & BRANCH_ABSOLUTE) + return 0; + + return instr_is_branch_iform(instr) || instr_is_branch_bform(instr); +} + +static unsigned long branch_iform_target(const unsigned int *instr) +{ + signed long imm; + + imm = *instr & 0x3FFFFFC; + + /* If the top bit of the immediate value is set this is negative */ + if (imm & 0x2000000) + imm -= 0x4000000; + + if ((*instr & BRANCH_ABSOLUTE) == 0) + imm += (unsigned long)instr; + + return (unsigned long)imm; +} + +static unsigned long branch_bform_target(const unsigned int *instr) +{ + signed long imm; + + imm = *instr & 0xFFFC; + + /* If the top bit of the immediate value is set this is negative */ + if (imm & 0x8000) + imm -= 0x10000; + + if ((*instr & BRANCH_ABSOLUTE) == 0) + imm += (unsigned long)instr; + + return (unsigned long)imm; +} + +unsigned long branch_target(const unsigned int *instr) +{ + if (instr_is_branch_iform(*instr)) + return branch_iform_target(instr); + else if (instr_is_branch_bform(*instr)) + return branch_bform_target(instr); + + return 0; +} + +int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr) +{ + if (instr_is_branch_iform(*instr) || instr_is_branch_bform(*instr)) + return branch_target(instr) == addr; + + return 0; +} + +unsigned int translate_branch(const unsigned int *dest, const unsigned int *src) +{ + unsigned long target; + + target = branch_target(src); + + if (instr_is_branch_iform(*src)) + return create_branch(dest, target, *src); + else if (instr_is_branch_bform(*src)) + return create_cond_branch(dest, target, *src); + + return 0; +} diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h index a45a7ff78725..40ad46b1dd9d 100644 --- a/include/asm-powerpc/code-patching.h +++ b/include/asm-powerpc/code-patching.h @@ -23,9 +23,17 @@ unsigned int create_branch(const unsigned int *addr, unsigned long target, int flags); +unsigned int create_cond_branch(const unsigned int *addr, + unsigned long target, int flags); void patch_branch(unsigned int *addr, unsigned long target, int flags); void patch_instruction(unsigned int *addr, unsigned int instr); +int instr_is_relative_branch(unsigned int instr); +int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr); +unsigned long branch_target(const unsigned int *instr); +unsigned int translate_branch(const unsigned int *dest, + const unsigned int *src); + static inline unsigned long ppc_function_entry(void *func) { #ifdef CONFIG_PPC64 -- cgit v1.2.3 From b7bcda631e87eb3466d0baa9885650ba7d7ed89d Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 24 Jun 2008 11:32:35 +1000 Subject: powerpc: Add PPC_NOP_INSTR, a hash define for the preferred nop instruction A bunch of code has hard-coded the value for a "nop" instruction, it would be nice to have a #define for it. Signed-off-by: Michael Ellerman Acked-by: Kumar Gala Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/cputable.c | 3 ++- arch/powerpc/kernel/crash_dump.c | 2 +- arch/powerpc/kernel/module_64.c | 3 ++- include/asm-powerpc/code-patching.h | 2 ++ 4 files changed, 7 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index f8deb3761de4..ba5b23f54764 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -17,6 +17,7 @@ #include #include +#include #include #include /* for PTRRELOC on ARCH=ppc */ @@ -1663,7 +1664,7 @@ void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end) pend = ((unsigned int *)fcur) + (fcur->end_off / 4); for (p = pstart; p < pend; p++) { - *p = 0x60000000u; + *p = PPC_NOP_INSTR; asm volatile ("dcbst 0, %0" : : "r" (p)); } asm volatile ("sync" : : : "memory"); diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c index 26648544d5e4..e0debcca0bfa 100644 --- a/arch/powerpc/kernel/crash_dump.c +++ b/arch/powerpc/kernel/crash_dump.c @@ -44,7 +44,7 @@ static void __init create_trampoline(unsigned long addr) * branch to "addr" we jump to ("addr" + 32 MB). Although it requires * two instructions it doesn't require any registers. */ - patch_instruction(p, 0x60000000); /* nop */ + patch_instruction(p, PPC_NOP_INSTR); patch_branch(++p, addr + PHYSICAL_START, 0); } diff --git a/arch/powerpc/kernel/module_64.c b/arch/powerpc/kernel/module_64.c index 4803f2de98dd..ee6a2982d567 100644 --- a/arch/powerpc/kernel/module_64.c +++ b/arch/powerpc/kernel/module_64.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include "setup.h" @@ -330,7 +331,7 @@ static unsigned long stub_for_addr(Elf64_Shdr *sechdrs, restore r2. */ static int restore_r2(u32 *instruction, struct module *me) { - if (*instruction != 0x60000000) { + if (*instruction != PPC_NOP_INSTR) { printk("%s: Expect noop after relocate, got %08x\n", me->name, *instruction); return 0; diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h index 40ad46b1dd9d..ef3a5d156dba 100644 --- a/include/asm-powerpc/code-patching.h +++ b/include/asm-powerpc/code-patching.h @@ -12,6 +12,8 @@ #include +#define PPC_NOP_INSTR 0x60000000 + /* Flags for create_branch: * "b" == create_branch(addr, target, 0); * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE); -- cgit v1.2.3 From c5157e587b33b1185cf73207fc53760cf1351430 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 24 Jun 2008 11:32:39 +1000 Subject: powerpc: Consolidate CPU and firmware feature fixup macros The CPU and firmware feature fixup macros are currently spread across three files, firmware.h, cputable.h and asm-compat.h. Consolidate them into their own file, feature-fixups.h Signed-off-by: Michael Ellerman Acked-by: Kumar Gala Signed-off-by: Paul Mackerras --- include/asm-powerpc/asm-compat.h | 51 ------------------ include/asm-powerpc/cputable.h | 14 +---- include/asm-powerpc/feature-fixups.h | 102 +++++++++++++++++++++++++++++++++++ include/asm-powerpc/firmware.h | 13 +---- 4 files changed, 104 insertions(+), 76 deletions(-) create mode 100644 include/asm-powerpc/feature-fixups.h (limited to 'include') diff --git a/include/asm-powerpc/asm-compat.h b/include/asm-powerpc/asm-compat.h index c19e7367fce6..8ec2e1da68bf 100644 --- a/include/asm-powerpc/asm-compat.h +++ b/include/asm-powerpc/asm-compat.h @@ -15,57 +15,6 @@ #endif -/* - * Feature section common macros - * - * Note that the entries now contain offsets between the table entry - * and the code rather than absolute code pointers in order to be - * useable with the vdso shared library. There is also an assumption - * that values will be negative, that is, the fixup table has to be - * located after the code it fixes up. - */ -#ifdef CONFIG_PPC64 -#ifdef __powerpc64__ -/* 64 bits kernel, 64 bits code */ -#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ -99: \ - .section sect,"a"; \ - .align 3; \ -98: \ - .llong msk; \ - .llong val; \ - .llong label##b-98b; \ - .llong 99b-98b; \ - .previous -#else /* __powerpc64__ */ -/* 64 bits kernel, 32 bits code (ie. vdso32) */ -#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ -99: \ - .section sect,"a"; \ - .align 3; \ -98: \ - .llong msk; \ - .llong val; \ - .long 0xffffffff; \ - .long label##b-98b; \ - .long 0xffffffff; \ - .long 99b-98b; \ - .previous -#endif /* !__powerpc64__ */ -#else /* CONFIG_PPC64 */ -/* 32 bits kernel, 32 bits code */ -#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ -99: \ - .section sect,"a"; \ - .align 2; \ -98: \ - .long msk; \ - .long val; \ - .long label##b-98b; \ - .long 99b-98b; \ - .previous -#endif /* !CONFIG_PPC64 */ - #ifdef __powerpc64__ /* operations for longs and pointers */ diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 3189ac5d0a69..0d96b0284a73 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -32,6 +32,7 @@ #ifdef __KERNEL__ #include +#include #ifndef __ASSEMBLY__ @@ -489,18 +490,5 @@ static inline int cpu_has_feature(unsigned long feature) #endif /* !__ASSEMBLY__ */ -#ifdef __ASSEMBLY__ - -#define BEGIN_FTR_SECTION_NESTED(label) label: -#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97) -#define END_FTR_SECTION_NESTED(msk, val, label) \ - MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup) -#define END_FTR_SECTION(msk, val) \ - END_FTR_SECTION_NESTED(msk, val, 97) - -#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) -#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) -#endif /* __ASSEMBLY__ */ - #endif /* __KERNEL__ */ #endif /* __ASM_POWERPC_CPUTABLE_H */ diff --git a/include/asm-powerpc/feature-fixups.h b/include/asm-powerpc/feature-fixups.h new file mode 100644 index 000000000000..85972125bbb8 --- /dev/null +++ b/include/asm-powerpc/feature-fixups.h @@ -0,0 +1,102 @@ +#ifndef __ASM_POWERPC_FEATURE_FIXUPS_H +#define __ASM_POWERPC_FEATURE_FIXUPS_H + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifdef __ASSEMBLY__ + +/* + * Feature section common macros + * + * Note that the entries now contain offsets between the table entry + * and the code rather than absolute code pointers in order to be + * useable with the vdso shared library. There is also an assumption + * that values will be negative, that is, the fixup table has to be + * located after the code it fixes up. + */ +#ifdef CONFIG_PPC64 + +#ifdef __powerpc64__ + +/* 64 bits kernel, 64 bits code */ +#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ +99: \ + .section sect,"a"; \ + .align 3; \ +98: \ + .llong msk; \ + .llong val; \ + .llong label##b-98b; \ + .llong 99b-98b; \ + .previous + +#else /* __powerpc64__ */ + +/* 64 bits kernel, 32 bits code (ie. vdso32) */ +#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ +99: \ + .section sect,"a"; \ + .align 3; \ +98: \ + .llong msk; \ + .llong val; \ + .long 0xffffffff; \ + .long label##b-98b; \ + .long 0xffffffff; \ + .long 99b-98b; \ + .previous + +#endif /* !__powerpc64__ */ + +#else /* CONFIG_PPC64 */ + +/* 32 bits kernel, 32 bits code */ +#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ +99: \ + .section sect,"a"; \ + .align 2; \ +98: \ + .long msk; \ + .long val; \ + .long label##b-98b; \ + .long 99b-98b; \ + .previous + +#endif /* !CONFIG_PPC64 */ + + +/* CPU feature dependent sections */ +#define BEGIN_FTR_SECTION_NESTED(label) label: +#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97) + +#define END_FTR_SECTION_NESTED(msk, val, label) \ + MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup) + +#define END_FTR_SECTION(msk, val) \ + END_FTR_SECTION_NESTED(msk, val, 97) + +#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) +#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) + + +/* Firmware feature dependent sections */ +#define BEGIN_FW_FTR_SECTION_NESTED(label) label: +#define BEGIN_FW_FTR_SECTION BEGIN_FW_FTR_SECTION_NESTED(97) + +#define END_FW_FTR_SECTION_NESTED(msk, val, label) \ + MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup) + +#define END_FW_FTR_SECTION(msk, val) \ + END_FW_FTR_SECTION_NESTED(msk, val, 97) + +#define END_FW_FTR_SECTION_IFSET(msk) END_FW_FTR_SECTION((msk), (msk)) +#define END_FW_FTR_SECTION_IFCLR(msk) END_FW_FTR_SECTION((msk), 0) + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */ diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h index 1e41bd1c8502..ef328995ba9d 100644 --- a/include/asm-powerpc/firmware.h +++ b/include/asm-powerpc/firmware.h @@ -15,6 +15,7 @@ #ifdef __KERNEL__ #include +#include /* firmware feature bitmask values */ #define FIRMWARE_MAX_FEATURES 63 @@ -125,18 +126,6 @@ extern int fwnmi_active; extern unsigned int __start___fw_ftr_fixup, __stop___fw_ftr_fixup; -#else /* __ASSEMBLY__ */ - -#define BEGIN_FW_FTR_SECTION_NESTED(label) label: -#define BEGIN_FW_FTR_SECTION BEGIN_FW_FTR_SECTION_NESTED(97) -#define END_FW_FTR_SECTION_NESTED(msk, val, label) \ - MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup) -#define END_FW_FTR_SECTION(msk, val) \ - END_FW_FTR_SECTION_NESTED(msk, val, 97) - -#define END_FW_FTR_SECTION_IFSET(msk) END_FW_FTR_SECTION((msk), (msk)) -#define END_FW_FTR_SECTION_IFCLR(msk) END_FW_FTR_SECTION((msk), 0) - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* __ASM_POWERPC_FIRMWARE_H */ -- cgit v1.2.3 From c1137c37a9370f510dc022e6e95fff036ccb90be Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 24 Jun 2008 11:32:48 +1000 Subject: powerpc: Consolidate feature fixup macros for 64/32 bit Currently we have three versions of MAKE_FTR_SECTION_ENTRY(), the macro that generates a feature section entry. There is 64bit version, a 32bit version and version for 32bit code built with a 64bit kernel. Rather than triplicating (?) the MAKE_FTR_SECTION_ENTRY() logic, we can move the 64bit/32bit differences into separate macros, and then only have one version of MAKE_FTR_SECTION_ENTRY(). Signed-off-by: Michael Ellerman Acked-by: Kumar Gala Signed-off-by: Paul Mackerras --- include/asm-powerpc/feature-fixups.h | 54 +++++++++--------------------------- 1 file changed, 13 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/feature-fixups.h b/include/asm-powerpc/feature-fixups.h index 85972125bbb8..35f927888fe8 100644 --- a/include/asm-powerpc/feature-fixups.h +++ b/include/asm-powerpc/feature-fixups.h @@ -19,55 +19,27 @@ * that values will be negative, that is, the fixup table has to be * located after the code it fixes up. */ -#ifdef CONFIG_PPC64 - -#ifdef __powerpc64__ - -/* 64 bits kernel, 64 bits code */ -#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ -99: \ - .section sect,"a"; \ - .align 3; \ -98: \ - .llong msk; \ - .llong val; \ - .llong label##b-98b; \ - .llong 99b-98b; \ - .previous - -#else /* __powerpc64__ */ - +#if defined(CONFIG_PPC64) && !defined(__powerpc64__) /* 64 bits kernel, 32 bits code (ie. vdso32) */ +#define FTR_ENTRY_LONG .llong +#define FTR_ENTRY_OFFSET .long 0xffffffff; .long +#else +/* 64 bit kernel 64 bit code, or 32 bit kernel 32 bit code */ +#define FTR_ENTRY_LONG PPC_LONG +#define FTR_ENTRY_OFFSET PPC_LONG +#endif + #define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ 99: \ .section sect,"a"; \ .align 3; \ 98: \ - .llong msk; \ - .llong val; \ - .long 0xffffffff; \ - .long label##b-98b; \ - .long 0xffffffff; \ - .long 99b-98b; \ - .previous - -#endif /* !__powerpc64__ */ - -#else /* CONFIG_PPC64 */ - -/* 32 bits kernel, 32 bits code */ -#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ -99: \ - .section sect,"a"; \ - .align 2; \ -98: \ - .long msk; \ - .long val; \ - .long label##b-98b; \ - .long 99b-98b; \ + FTR_ENTRY_LONG msk; \ + FTR_ENTRY_LONG val; \ + FTR_ENTRY_OFFSET label##b-98b; \ + FTR_ENTRY_OFFSET 99b-98b; \ .previous -#endif /* !CONFIG_PPC64 */ /* CPU feature dependent sections */ -- cgit v1.2.3 From fac23fe4be23259a8eaa9bad822f5b14dd07d15c Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 24 Jun 2008 11:32:54 +1000 Subject: powerpc: Introduce infrastructure for feature sections with alternatives The current feature section logic only supports nop'ing out code, this means if you want to choose at runtime between instruction sequences, one or both cases will have to execute the nop'ed out contents of the other section, eg: BEGIN_FTR_SECTION or 1,1,1 END_FTR_SECTION_IFSET(FOO) BEGIN_FTR_SECTION or 2,2,2 END_FTR_SECTION_IFCLR(FOO) and the resulting code will be either, or 1,1,1 nop or, nop or 2,2,2 For small code segments this is fine, but for larger code blocks and in performance criticial code segments, it would be nice to avoid the nops. This commit starts to implement logic to allow the following: BEGIN_FTR_SECTION or 1,1,1 FTR_SECTION_ELSE or 2,2,2 ALT_FTR_SECTION_END_IFSET(FOO) and the resulting code will be: or 1,1,1 or, or 2,2,2 We achieve this by extending the existing FTR macros. The current feature section semantic just becomes a special case, ie. if the else case is empty we nop out the default case. The key limitation is that the size of the else case must be less than or equal to the size of the default case. If the else case is smaller the remainder of the section is nop'ed. We let the linker put the else case code in with the rest of the text, so that relative branches from the else case are more likley to link, this has the disadvantage that we can't free the unused else cases. This commit introduces the required macro and linker script changes, but does not enable the patching of the alternative sections. We also need to update two hand-made section entries in reg.h and timex.h Signed-off-by: Michael Ellerman Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/vdso32/vdso32.lds.S | 2 +- arch/powerpc/kernel/vdso64/vdso64.lds.S | 2 +- arch/powerpc/kernel/vmlinux.lds.S | 2 +- arch/powerpc/lib/feature-fixups.c | 2 + include/asm-powerpc/feature-fixups.h | 68 ++++++++++++++++++++++++++------- include/asm-powerpc/reg.h | 2 + include/asm-powerpc/timex.h | 2 + 7 files changed, 64 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/vdso32/vdso32.lds.S b/arch/powerpc/kernel/vdso32/vdso32.lds.S index 9352ab5200e5..271793577cdc 100644 --- a/arch/powerpc/kernel/vdso32/vdso32.lds.S +++ b/arch/powerpc/kernel/vdso32/vdso32.lds.S @@ -24,7 +24,7 @@ SECTIONS . = ALIGN(16); .text : { - *(.text .stub .text.* .gnu.linkonce.t.*) + *(.text .stub .text.* .gnu.linkonce.t.* __ftr_alt_*) } PROVIDE(__etext = .); PROVIDE(_etext = .); diff --git a/arch/powerpc/kernel/vdso64/vdso64.lds.S b/arch/powerpc/kernel/vdso64/vdso64.lds.S index 7d6585f90277..e608d1bd3bff 100644 --- a/arch/powerpc/kernel/vdso64/vdso64.lds.S +++ b/arch/powerpc/kernel/vdso64/vdso64.lds.S @@ -24,7 +24,7 @@ SECTIONS . = ALIGN(16); .text : { - *(.text .stub .text.* .gnu.linkonce.t.*) + *(.text .stub .text.* .gnu.linkonce.t.* __ftr_alt_*) *(.sfpr .glink) } :text PROVIDE(__etext = .); diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index 0c3000bf8d75..3c07811989fc 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -35,7 +35,7 @@ SECTIONS ALIGN_FUNCTION(); *(.text.head) _text = .; - *(.text .fixup .text.init.refok .exit.text.refok) + *(.text .fixup .text.init.refok .exit.text.refok __ftr_alt_*) SCHED_TEXT LOCK_TEXT KPROBES_TEXT diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c index f6fd5d2ff10d..973d547ef01d 100644 --- a/arch/powerpc/lib/feature-fixups.c +++ b/arch/powerpc/lib/feature-fixups.c @@ -22,6 +22,8 @@ struct fixup_entry { unsigned long value; long start_off; long end_off; + long alt_start_off; + long alt_end_off; }; static void patch_feature_section(unsigned long value, struct fixup_entry *fcur) diff --git a/include/asm-powerpc/feature-fixups.h b/include/asm-powerpc/feature-fixups.h index 35f927888fe8..ab30129dced7 100644 --- a/include/asm-powerpc/feature-fixups.h +++ b/include/asm-powerpc/feature-fixups.h @@ -29,24 +29,35 @@ #define FTR_ENTRY_OFFSET PPC_LONG #endif +#define START_FTR_SECTION(label) label##1: + +#define FTR_SECTION_ELSE_NESTED(label) \ +label##2: \ + .pushsection __ftr_alt_##label,"a"; \ + .align 2; \ +label##3: + #define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ -99: \ - .section sect,"a"; \ +label##4: \ + .popsection; \ + .pushsection sect,"a"; \ .align 3; \ -98: \ +label##5: \ FTR_ENTRY_LONG msk; \ FTR_ENTRY_LONG val; \ - FTR_ENTRY_OFFSET label##b-98b; \ - FTR_ENTRY_OFFSET 99b-98b; \ - .previous - + FTR_ENTRY_OFFSET label##1b-label##5b; \ + FTR_ENTRY_OFFSET label##2b-label##5b; \ + FTR_ENTRY_OFFSET label##3b-label##5b; \ + FTR_ENTRY_OFFSET label##4b-label##5b; \ + .popsection; /* CPU feature dependent sections */ -#define BEGIN_FTR_SECTION_NESTED(label) label: -#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97) +#define BEGIN_FTR_SECTION_NESTED(label) START_FTR_SECTION(label) +#define BEGIN_FTR_SECTION START_FTR_SECTION(97) -#define END_FTR_SECTION_NESTED(msk, val, label) \ +#define END_FTR_SECTION_NESTED(msk, val, label) \ + FTR_SECTION_ELSE_NESTED(label) \ MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup) #define END_FTR_SECTION(msk, val) \ @@ -55,12 +66,27 @@ #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) +/* CPU feature sections with alternatives, use BEGIN_FTR_SECTION to start */ +#define FTR_SECTION_ELSE FTR_SECTION_ELSE_NESTED(97) +#define ALT_FTR_SECTION_END_NESTED(msk, val, label) \ + MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup) +#define ALT_FTR_SECTION_END_NESTED_IFSET(msk, label) \ + ALT_FTR_SECTION_END_NESTED(msk, msk, label) +#define ALT_FTR_SECTION_END_NESTED_IFCLR(msk, label) \ + ALT_FTR_SECTION_END_NESTED(msk, 0, label) +#define ALT_FTR_SECTION_END(msk, val) \ + ALT_FTR_SECTION_END_NESTED(msk, val, 97) +#define ALT_FTR_SECTION_END_IFSET(msk) \ + ALT_FTR_SECTION_END_NESTED_IFSET(msk, 97) +#define ALT_FTR_SECTION_END_IFCLR(msk) \ + ALT_FTR_SECTION_END_NESTED_IFCLR(msk, 97) /* Firmware feature dependent sections */ -#define BEGIN_FW_FTR_SECTION_NESTED(label) label: -#define BEGIN_FW_FTR_SECTION BEGIN_FW_FTR_SECTION_NESTED(97) +#define BEGIN_FW_FTR_SECTION_NESTED(label) START_FTR_SECTION(label) +#define BEGIN_FW_FTR_SECTION START_FTR_SECTION(97) -#define END_FW_FTR_SECTION_NESTED(msk, val, label) \ +#define END_FW_FTR_SECTION_NESTED(msk, val, label) \ + FTR_SECTION_ELSE_NESTED(label) \ MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup) #define END_FW_FTR_SECTION(msk, val) \ @@ -69,6 +95,22 @@ #define END_FW_FTR_SECTION_IFSET(msk) END_FW_FTR_SECTION((msk), (msk)) #define END_FW_FTR_SECTION_IFCLR(msk) END_FW_FTR_SECTION((msk), 0) +/* Firmware feature sections with alternatives */ +#define FW_FTR_SECTION_ELSE_NESTED(label) FTR_SECTION_ELSE_NESTED(label) +#define FW_FTR_SECTION_ELSE FTR_SECTION_ELSE_NESTED(97) +#define ALT_FW_FTR_SECTION_END_NESTED(msk, val, label) \ + MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup) +#define ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, label) \ + ALT_FW_FTR_SECTION_END_NESTED(msk, msk, label) +#define ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, label) \ + ALT_FW_FTR_SECTION_END_NESTED(msk, 0, label) +#define ALT_FW_FTR_SECTION_END(msk, val) \ + ALT_FW_FTR_SECTION_END_NESTED(msk, val, 97) +#define ALT_FW_FTR_SECTION_END_IFSET(msk) \ + ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, 97) +#define ALT_FW_FTR_SECTION_END_IFCLR(msk) \ + ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */ diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index 079999b032af..7256efb5c140 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h @@ -732,6 +732,8 @@ " .llong %1\n" \ " .llong 97b-98b\n" \ " .llong 99b-98b\n" \ + " .llong 0\n" \ + " .llong 0\n" \ ".previous" \ : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;}) #else diff --git a/include/asm-powerpc/timex.h b/include/asm-powerpc/timex.h index 92dedde761d1..c55e14f7ef44 100644 --- a/include/asm-powerpc/timex.h +++ b/include/asm-powerpc/timex.h @@ -38,6 +38,8 @@ static inline cycles_t get_cycles(void) " .long 0\n" " .long 97b-98b\n" " .long 99b-98b\n" + " .long 0\n" + " .long 0\n" ".previous" : "=r" (ret) : "i" (CPU_FTR_601)); return ret; -- cgit v1.2.3 From 9c75a31c3525a127f70b919856e32be3d8b03755 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 26 Jun 2008 17:07:48 +1000 Subject: powerpc: Add macros to access floating point registers in thread_struct. We are going to change where the floating point registers are stored in the thread_struct, so in preparation add some macros to access the floating point registers. Update all code to use these new macros. Signed-off-by: Michael Neuling Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/align.c | 6 ++--- arch/powerpc/kernel/process.c | 2 +- arch/powerpc/kernel/ptrace.c | 10 ++++--- arch/powerpc/kernel/ptrace32.c | 14 +++++++--- arch/powerpc/kernel/softemu8xx.c | 4 +-- arch/powerpc/math-emu/math.c | 56 ++++++++++++++++++++-------------------- include/asm-powerpc/ppc_asm.h | 5 ++-- include/asm-powerpc/processor.h | 4 +++ 8 files changed, 58 insertions(+), 43 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c index e06f75daeba3..c95954c81454 100644 --- a/arch/powerpc/kernel/align.c +++ b/arch/powerpc/kernel/align.c @@ -366,7 +366,7 @@ static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr, static int emulate_fp_pair(struct pt_regs *regs, unsigned char __user *addr, unsigned int reg, unsigned int flags) { - char *ptr = (char *) ¤t->thread.fpr[reg]; + char *ptr = (char *) ¤t->thread.TS_FPR(reg); int i, ret; if (!(flags & F)) @@ -784,7 +784,7 @@ int fix_alignment(struct pt_regs *regs) return -EFAULT; } } else if (flags & F) { - data.dd = current->thread.fpr[reg]; + data.dd = current->thread.TS_FPR(reg); if (flags & S) { /* Single-precision FP store requires conversion... */ #ifdef CONFIG_PPC_FPU @@ -862,7 +862,7 @@ int fix_alignment(struct pt_regs *regs) if (unlikely(ret)) return -EFAULT; } else if (flags & F) - current->thread.fpr[reg] = data.dd; + current->thread.TS_FPR(reg) = data.dd; else regs->gpr[reg] = data.ll; diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 7de41c3948ec..582df70439cb 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -110,7 +110,7 @@ int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpregs) return 0; flush_fp_to_thread(current); - memcpy(fpregs, &tsk->thread.fpr[0], sizeof(*fpregs)); + memcpy(fpregs, &tsk->thread.TS_FPR(0), sizeof(*fpregs)); return 1; } diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 2a9fe97e4521..59ff08704e94 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -218,7 +218,7 @@ static int fpr_get(struct task_struct *target, const struct user_regset *regset, flush_fp_to_thread(target); BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != - offsetof(struct thread_struct, fpr[32])); + offsetof(struct thread_struct, TS_FPR(32))); return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &target->thread.fpr, 0, -1); @@ -231,7 +231,7 @@ static int fpr_set(struct task_struct *target, const struct user_regset *regset, flush_fp_to_thread(target); BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != - offsetof(struct thread_struct, fpr[32])); + offsetof(struct thread_struct, TS_FPR(32))); return user_regset_copyin(&pos, &count, &kbuf, &ubuf, &target->thread.fpr, 0, -1); @@ -728,7 +728,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) tmp = ptrace_get_reg(child, (int) index); } else { flush_fp_to_thread(child); - tmp = ((unsigned long *)child->thread.fpr)[index - PT_FPR0]; + tmp = ((unsigned long *)child->thread.fpr) + [TS_FPRWIDTH * (index - PT_FPR0)]; } ret = put_user(tmp,(unsigned long __user *) data); break; @@ -755,7 +756,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) ret = ptrace_put_reg(child, index, data); } else { flush_fp_to_thread(child); - ((unsigned long *)child->thread.fpr)[index - PT_FPR0] = data; + ((unsigned long *)child->thread.fpr) + [TS_FPRWIDTH * (index - PT_FPR0)] = data; ret = 0; } break; diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c index 4c1de6af4c09..67bf1a1e7e14 100644 --- a/arch/powerpc/kernel/ptrace32.c +++ b/arch/powerpc/kernel/ptrace32.c @@ -64,6 +64,11 @@ static long compat_ptrace_old(struct task_struct *child, long request, return -EPERM; } +/* Macros to workout the correct index for the FPR in the thread struct */ +#define FPRNUMBER(i) (((i) - PT_FPR0) >> 1) +#define FPRHALF(i) (((i) - PT_FPR0) & 1) +#define FPRINDEX(i) TS_FPRWIDTH * FPRNUMBER(i) + FPRHALF(i) + long compat_arch_ptrace(struct task_struct *child, compat_long_t request, compat_ulong_t caddr, compat_ulong_t cdata) { @@ -122,7 +127,8 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, * to be an array of unsigned int (32 bits) - the * index passed in is based on this assumption. */ - tmp = ((unsigned int *)child->thread.fpr)[index - PT_FPR0]; + tmp = ((unsigned int *)child->thread.fpr) + [FPRINDEX(index)]; } ret = put_user((unsigned int)tmp, (u32 __user *)data); break; @@ -162,7 +168,8 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, CHECK_FULL_REGS(child->thread.regs); if (numReg >= PT_FPR0) { flush_fp_to_thread(child); - tmp = ((unsigned long int *)child->thread.fpr)[numReg - PT_FPR0]; + tmp = ((unsigned long int *)child->thread.fpr) + [FPRINDEX(numReg)]; } else { /* register within PT_REGS struct */ tmp = ptrace_get_reg(child, numReg); } @@ -217,7 +224,8 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, * to be an array of unsigned int (32 bits) - the * index passed in is based on this assumption. */ - ((unsigned int *)child->thread.fpr)[index - PT_FPR0] = data; + ((unsigned int *)child->thread.fpr) + [FPRINDEX(index)] = data; ret = 0; } break; diff --git a/arch/powerpc/kernel/softemu8xx.c b/arch/powerpc/kernel/softemu8xx.c index 67d6f6890edc..c906c4bf6835 100644 --- a/arch/powerpc/kernel/softemu8xx.c +++ b/arch/powerpc/kernel/softemu8xx.c @@ -124,7 +124,7 @@ int Soft_emulate_8xx(struct pt_regs *regs) disp = instword & 0xffff; ea = (u32 *)(regs->gpr[idxreg] + disp); - ip = (u32 *)¤t->thread.fpr[flreg]; + ip = (u32 *)¤t->thread.TS_FPR(flreg); switch ( inst ) { @@ -168,7 +168,7 @@ int Soft_emulate_8xx(struct pt_regs *regs) break; case FMR: /* assume this is a fp move -- Cort */ - memcpy(ip, ¤t->thread.fpr[(instword>>11)&0x1f], + memcpy(ip, ¤t->thread.TS_FPR((instword>>11)&0x1f), sizeof(double)); break; default: diff --git a/arch/powerpc/math-emu/math.c b/arch/powerpc/math-emu/math.c index 381306bb1590..29e545e0272e 100644 --- a/arch/powerpc/math-emu/math.c +++ b/arch/powerpc/math-emu/math.c @@ -230,14 +230,14 @@ do_mathemu(struct pt_regs *regs) case LFD: idx = (insn >> 16) & 0x1f; sdisp = (insn & 0xffff); - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp); lfd(op0, op1, op2, op3); break; case LFDU: idx = (insn >> 16) & 0x1f; sdisp = (insn & 0xffff); - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp); lfd(op0, op1, op2, op3); regs->gpr[idx] = (unsigned long)op1; @@ -245,21 +245,21 @@ do_mathemu(struct pt_regs *regs) case STFD: idx = (insn >> 16) & 0x1f; sdisp = (insn & 0xffff); - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp); stfd(op0, op1, op2, op3); break; case STFDU: idx = (insn >> 16) & 0x1f; sdisp = (insn & 0xffff); - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp); stfd(op0, op1, op2, op3); regs->gpr[idx] = (unsigned long)op1; break; case OP63: - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; - op1 = (void *)¤t->thread.fpr[(insn >> 11) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); + op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f); fmr(op0, op1, op2, op3); break; default: @@ -356,28 +356,28 @@ do_mathemu(struct pt_regs *regs) switch (type) { case AB: - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; - op1 = (void *)¤t->thread.fpr[(insn >> 16) & 0x1f]; - op2 = (void *)¤t->thread.fpr[(insn >> 11) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); + op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f); + op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f); break; case AC: - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; - op1 = (void *)¤t->thread.fpr[(insn >> 16) & 0x1f]; - op2 = (void *)¤t->thread.fpr[(insn >> 6) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); + op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f); + op2 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f); break; case ABC: - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; - op1 = (void *)¤t->thread.fpr[(insn >> 16) & 0x1f]; - op2 = (void *)¤t->thread.fpr[(insn >> 11) & 0x1f]; - op3 = (void *)¤t->thread.fpr[(insn >> 6) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); + op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f); + op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f); + op3 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f); break; case D: idx = (insn >> 16) & 0x1f; sdisp = (insn & 0xffff); - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp); break; @@ -387,27 +387,27 @@ do_mathemu(struct pt_regs *regs) goto illegal; sdisp = (insn & 0xffff); - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); op1 = (void *)(regs->gpr[idx] + sdisp); break; case X: - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); break; case XA: - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; - op1 = (void *)¤t->thread.fpr[(insn >> 16) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); + op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f); break; case XB: - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; - op1 = (void *)¤t->thread.fpr[(insn >> 11) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); + op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f); break; case XE: idx = (insn >> 16) & 0x1f; - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); if (!idx) { if (((insn >> 1) & 0x3ff) == STFIWX) op1 = (void *)(regs->gpr[(insn >> 11) & 0x1f]); @@ -421,7 +421,7 @@ do_mathemu(struct pt_regs *regs) case XEU: idx = (insn >> 16) & 0x1f; - op0 = (void *)¤t->thread.fpr[(insn >> 21) & 0x1f]; + op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); op1 = (void *)((idx ? regs->gpr[idx] : 0) + regs->gpr[(insn >> 11) & 0x1f]); break; @@ -429,8 +429,8 @@ do_mathemu(struct pt_regs *regs) case XCR: op0 = (void *)®s->ccr; op1 = (void *)((insn >> 23) & 0x7); - op2 = (void *)¤t->thread.fpr[(insn >> 16) & 0x1f]; - op3 = (void *)¤t->thread.fpr[(insn >> 11) & 0x1f]; + op2 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f); + op3 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f); break; case XCRL: @@ -450,7 +450,7 @@ do_mathemu(struct pt_regs *regs) case XFLB: op0 = (void *)((insn >> 17) & 0xff); - op1 = (void *)¤t->thread.fpr[(insn >> 11) & 0x1f]; + op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f); break; default: diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h index ef96bfd4ef4c..8f0426f973c9 100644 --- a/include/asm-powerpc/ppc_asm.h +++ b/include/asm-powerpc/ppc_asm.h @@ -6,6 +6,7 @@ #include #include +#include #ifndef __ASSEMBLY__ #error __FILE__ should only be used in assembler files @@ -83,13 +84,13 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) -#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base) +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base) +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index a1deed85f31d..a23da6356e06 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h @@ -12,6 +12,8 @@ #include +#define TS_FPRWIDTH 1 + #ifndef __ASSEMBLY__ #include #include @@ -140,6 +142,8 @@ typedef struct { unsigned long seg; } mm_segment_t; +#define TS_FPR(i) fpr[i] + struct thread_struct { unsigned long ksp; /* Kernel stack pointer */ unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ -- cgit v1.2.3 From c6e6771b87d4e339d27f1383c8a808ae9b4ee5b8 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 25 Jun 2008 14:07:18 +1000 Subject: powerpc: Introduce VSX thread_struct and CONFIG_VSX The layout of the new VSR registers and how they overlap on top of the legacy FPR and VR registers is: VSR doubleword 0 VSR doubleword 1 ---------------------------------------------------------------- VSR[0] | FPR[0] | | ---------------------------------------------------------------- VSR[1] | FPR[1] | | ---------------------------------------------------------------- | ... | | | ... | | ---------------------------------------------------------------- VSR[30] | FPR[30] | | ---------------------------------------------------------------- VSR[31] | FPR[31] | | ---------------------------------------------------------------- VSR[32] | VR[0] | ---------------------------------------------------------------- VSR[33] | VR[1] | ---------------------------------------------------------------- | ... | | ... | ---------------------------------------------------------------- VSR[62] | VR[30] | ---------------------------------------------------------------- VSR[63] | VR[31] | ---------------------------------------------------------------- VSX has 64 128bit registers. The first 32 regs overlap with the FP registers and hence extend them with and additional 64 bits. The second 32 regs overlap with the VMX registers. This commit introduces the thread_struct changes required to reflect this register layout. Ptrace and signals code is updated so that the floating point registers are correctly accessed from the thread_struct when CONFIG_VSX is enabled. Signed-off-by: Michael Neuling Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/asm-offsets.c | 4 +++ arch/powerpc/kernel/ptrace.c | 29 ++++++++++++++++++- arch/powerpc/kernel/signal_32.c | 59 +++++++++++++++++++++++++++++---------- arch/powerpc/kernel/signal_64.c | 32 +++++++++++++++++++-- include/asm-powerpc/processor.h | 18 ++++++++++-- 5 files changed, 121 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index 8655c7670350..92768d3006f7 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -78,6 +78,10 @@ int main(void) DEFINE(THREAD_VSCR, offsetof(struct thread_struct, vscr)); DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr)); #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX + DEFINE(THREAD_VSR0, offsetof(struct thread_struct, fpr)); + DEFINE(THREAD_USED_VSR, offsetof(struct thread_struct, used_vsr)); +#endif /* CONFIG_VSX */ #ifdef CONFIG_PPC64 DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid)); #else /* CONFIG_PPC64 */ diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 59ff08704e94..70fbde84b83f 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -215,29 +215,56 @@ static int fpr_get(struct task_struct *target, const struct user_regset *regset, unsigned int pos, unsigned int count, void *kbuf, void __user *ubuf) { +#ifdef CONFIG_VSX + double buf[33]; + int i; +#endif flush_fp_to_thread(target); +#ifdef CONFIG_VSX + /* copy to local buffer then write that out */ + for (i = 0; i < 32 ; i++) + buf[i] = target->thread.TS_FPR(i); + memcpy(&buf[32], &target->thread.fpscr, sizeof(double)); + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); + +#else BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != offsetof(struct thread_struct, TS_FPR(32))); return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &target->thread.fpr, 0, -1); +#endif } static int fpr_set(struct task_struct *target, const struct user_regset *regset, unsigned int pos, unsigned int count, const void *kbuf, const void __user *ubuf) { +#ifdef CONFIG_VSX + double buf[33]; + int i; +#endif flush_fp_to_thread(target); +#ifdef CONFIG_VSX + /* copy to local buffer then write that out */ + i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); + if (i) + return i; + for (i = 0; i < 32 ; i++) + target->thread.TS_FPR(i) = buf[i]; + memcpy(&target->thread.fpscr, &buf[32], sizeof(double)); + return 0; +#else BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != offsetof(struct thread_struct, TS_FPR(32))); return user_regset_copyin(&pos, &count, &kbuf, &ubuf, &target->thread.fpr, 0, -1); +#endif } - #ifdef CONFIG_ALTIVEC /* * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index b057e6852a7d..f7fa395b9fb5 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c @@ -337,14 +337,16 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame, int sigret) { unsigned long msr = regs->msr; +#ifdef CONFIG_VSX + double buf[32]; + int i; +#endif /* Make sure floating point registers are stored in regs */ flush_fp_to_thread(current); - /* save general and floating-point registers */ - if (save_general_regs(regs, frame) || - __copy_to_user(&frame->mc_fregs, current->thread.fpr, - ELF_NFPREG * sizeof(double))) + /* save general registers */ + if (save_general_regs(regs, frame)) return 1; #ifdef CONFIG_ALTIVEC @@ -368,7 +370,20 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame, if (__put_user(current->thread.vrsave, (u32 __user *)&frame->mc_vregs[32])) return 1; #endif /* CONFIG_ALTIVEC */ - +#ifdef CONFIG_VSX + /* save FPR copy to local buffer then write to the thread_struct */ + flush_fp_to_thread(current); + for (i = 0; i < 32 ; i++) + buf[i] = current->thread.TS_FPR(i); + memcpy(&buf[i], ¤t->thread.fpscr, sizeof(double)); + if (__copy_to_user(&frame->mc_fregs, buf, ELF_NFPREG * sizeof(double))) + return 1; +#else + /* save floating-point registers */ + if (__copy_to_user(&frame->mc_fregs, current->thread.fpr, + ELF_NFPREG * sizeof(double))) + return 1; +#endif /* CONFIG_VSX */ #ifdef CONFIG_SPE /* save spe registers */ if (current->thread.used_spe) { @@ -411,6 +426,10 @@ static long restore_user_regs(struct pt_regs *regs, long err; unsigned int save_r2 = 0; unsigned long msr; +#ifdef CONFIG_VSX + double buf[32]; + int i; +#endif /* * restore general registers but not including MSR or SOFTE. Also @@ -438,16 +457,11 @@ static long restore_user_regs(struct pt_regs *regs, */ discard_lazy_cpu_state(); - /* force the process to reload the FP registers from - current->thread when it next does FP instructions */ - regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1); - if (__copy_from_user(current->thread.fpr, &sr->mc_fregs, - sizeof(sr->mc_fregs))) - return 1; - #ifdef CONFIG_ALTIVEC - /* force the process to reload the altivec registers from - current->thread when it next does altivec instructions */ + /* + * Force the process to reload the altivec registers from + * current->thread when it next does altivec instructions + */ regs->msr &= ~MSR_VEC; if (msr & MSR_VEC) { /* restore altivec registers from the stack */ @@ -462,6 +476,23 @@ static long restore_user_regs(struct pt_regs *regs, return 1; #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX + if (__copy_from_user(buf, &sr->mc_fregs,sizeof(sr->mc_fregs))) + return 1; + for (i = 0; i < 32 ; i++) + current->thread.TS_FPR(i) = buf[i]; + memcpy(¤t->thread.fpscr, &buf[i], sizeof(double)); +#else + if (__copy_from_user(current->thread.fpr, &sr->mc_fregs, + sizeof(sr->mc_fregs))) + return 1; +#endif /* CONFIG_VSX */ + /* + * force the process to reload the FP registers from + * current->thread when it next does FP instructions + */ + regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1); + #ifdef CONFIG_SPE /* force the process to reload the spe registers from current->thread when it next does spe instructions */ diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c index da7c058e3731..a587b33cd6b9 100644 --- a/arch/powerpc/kernel/signal_64.c +++ b/arch/powerpc/kernel/signal_64.c @@ -89,6 +89,10 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, #endif unsigned long msr = regs->msr; long err = 0; +#ifdef CONFIG_VSX + double buf[FP_REGS_SIZE]; + int i; +#endif flush_fp_to_thread(current); @@ -112,11 +116,21 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, #else /* CONFIG_ALTIVEC */ err |= __put_user(0, &sc->v_regs); #endif /* CONFIG_ALTIVEC */ + flush_fp_to_thread(current); +#ifdef CONFIG_VSX + /* Copy FP to local buffer then write that out */ + for (i = 0; i < 32 ; i++) + buf[i] = current->thread.TS_FPR(i); + memcpy(&buf[i], ¤t->thread.fpscr, sizeof(double)); + err |= __copy_to_user(&sc->fp_regs, buf, FP_REGS_SIZE); +#else /* CONFIG_VSX */ + /* copy fpr regs and fpscr */ + err |= __copy_to_user(&sc->fp_regs, ¤t->thread.fpr, FP_REGS_SIZE); +#endif /* CONFIG_VSX */ err |= __put_user(&sc->gp_regs, &sc->regs); WARN_ON(!FULL_REGS(regs)); err |= __copy_to_user(&sc->gp_regs, regs, GP_REGS_SIZE); err |= __put_user(msr, &sc->gp_regs[PT_MSR]); - err |= __copy_to_user(&sc->fp_regs, ¤t->thread.fpr, FP_REGS_SIZE); err |= __put_user(signr, &sc->signal); err |= __put_user(handler, &sc->handler); if (set != NULL) @@ -134,6 +148,9 @@ static long restore_sigcontext(struct pt_regs *regs, sigset_t *set, int sig, { #ifdef CONFIG_ALTIVEC elf_vrreg_t __user *v_regs; +#endif +#ifdef CONFIG_VSX + double buf[FP_REGS_SIZE]; #endif unsigned long err = 0; unsigned long save_r13 = 0; @@ -182,8 +199,6 @@ static long restore_sigcontext(struct pt_regs *regs, sigset_t *set, int sig, */ regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC); - err |= __copy_from_user(¤t->thread.fpr, &sc->fp_regs, FP_REGS_SIZE); - #ifdef CONFIG_ALTIVEC err |= __get_user(v_regs, &sc->v_regs); if (err) @@ -202,7 +217,18 @@ static long restore_sigcontext(struct pt_regs *regs, sigset_t *set, int sig, else current->thread.vrsave = 0; #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX + /* restore floating point */ + err |= __copy_from_user(buf, &sc->fp_regs, FP_REGS_SIZE); + if (err) + return err; + for (i = 0; i < 32 ; i++) + current->thread.TS_FPR(i) = buf[i]; + memcpy(¤t->thread.fpscr, &buf[i], sizeof(double)); +#else + err |= __copy_from_user(¤t->thread.fpr, &sc->fp_regs, FP_REGS_SIZE); +#endif return err; } diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index a23da6356e06..e93e72df4bca 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h @@ -12,7 +12,11 @@ #include +#ifdef CONFIG_VSX +#define TS_FPRWIDTH 2 +#else #define TS_FPRWIDTH 1 +#endif #ifndef __ASSEMBLY__ #include @@ -80,6 +84,7 @@ extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); /* Lazy FPU handling on uni-processor */ extern struct task_struct *last_task_used_math; extern struct task_struct *last_task_used_altivec; +extern struct task_struct *last_task_used_vsx; extern struct task_struct *last_task_used_spe; #ifdef CONFIG_PPC32 @@ -142,7 +147,9 @@ typedef struct { unsigned long seg; } mm_segment_t; -#define TS_FPR(i) fpr[i] +#define TS_FPROFFSET 0 +#define TS_VSRLOWOFFSET 1 +#define TS_FPR(i) fpr[i][TS_FPROFFSET] struct thread_struct { unsigned long ksp; /* Kernel stack pointer */ @@ -160,8 +167,9 @@ struct thread_struct { unsigned long dbcr0; /* debug control register values */ unsigned long dbcr1; #endif - double fpr[32]; /* Complete floating point set */ - struct { /* fpr ... fpscr must be contiguous */ + /* FP and VSX 0-31 register set */ + double fpr[32][TS_FPRWIDTH]; + struct { unsigned int pad; unsigned int val; /* Floating point status */ @@ -181,6 +189,10 @@ struct thread_struct { unsigned long vrsave; int used_vr; /* set if process has used altivec */ #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX + /* VSR status */ + int used_vsr; /* set if process has used altivec */ +#endif /* CONFIG_VSX */ #ifdef CONFIG_SPE unsigned long evr[32]; /* upper 32-bits of SPE regs */ u64 acc; /* Accumulator */ -- cgit v1.2.3 From b962ce9d26fd6677e6720949642420ceb029a102 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 25 Jun 2008 14:07:18 +1000 Subject: powerpc: Add VSX CPU feature Add a VSX CPU feature. Also add code to detect if VSX is available from the device tree. Signed-off-by: Michael Neuling Signed-off-by: Joel Schopp Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/prom.c | 4 ++++ include/asm-powerpc/cputable.h | 15 ++++++++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 2aefe2a4129a..87d83c56b31e 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -609,6 +609,10 @@ static struct feature_property { {"altivec", 0, CPU_FTR_ALTIVEC, PPC_FEATURE_HAS_ALTIVEC}, {"ibm,vmx", 1, CPU_FTR_ALTIVEC, PPC_FEATURE_HAS_ALTIVEC}, #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX + /* Yes, this _really_ is ibm,vmx == 2 to enable VSX */ + {"ibm,vmx", 2, CPU_FTR_VSX, PPC_FEATURE_HAS_VSX}, +#endif /* CONFIG_VSX */ #ifdef CONFIG_PPC64 {"ibm,dfp", 1, 0, PPC_FEATURE_HAS_DFP}, {"ibm,purr", 1, CPU_FTR_PURR, 0}, diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 0d96b0284a73..4e4491cb9d3b 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -25,6 +25,7 @@ #define PPC_FEATURE_HAS_DFP 0x00000400 #define PPC_FEATURE_POWER6_EXT 0x00000200 #define PPC_FEATURE_ARCH_2_06 0x00000100 +#define PPC_FEATURE_HAS_VSX 0x00000080 #define PPC_FEATURE_TRUE_LE 0x00000002 #define PPC_FEATURE_PPC_LE 0x00000001 @@ -183,6 +184,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) #define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000) #define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000) +#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000) #ifndef __ASSEMBLY__ @@ -201,6 +203,17 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 #endif +/* We only set the VSX features if the kernel was compiled with VSX + * support + */ +#ifdef CONFIG_VSX +#define CPU_FTR_VSX_COMP CPU_FTR_VSX +#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX +#else +#define CPU_FTR_VSX_COMP 0 +#define PPC_FEATURE_HAS_VSX_COMP 0 +#endif + /* We only set the spe features if the kernel was compiled with spe * support */ @@ -404,7 +417,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ - CPU_FTR_1T_SEGMENT) + CPU_FTR_1T_SEGMENT | CPU_FTR_VSX) #else enum { CPU_FTRS_POSSIBLE = -- cgit v1.2.3 From 72ffff5b1792b0fa4d40a8e2f3276fff999820ec Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 25 Jun 2008 14:07:18 +1000 Subject: powerpc: Add VSX assembler code macros This adds the macros for the VSX load/store instruction as most binutils are not going to support this for a while. Also add VSX register save/restore macros and vsr[0-63] register definitions. Signed-off-by: Michael Neuling Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/fpu.S | 23 ++++++++++ include/asm-powerpc/ppc_asm.h | 103 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+) (limited to 'include') diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index 8a2b3d62b9b8..15247fe171a8 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S @@ -24,6 +24,29 @@ #include #include +#ifdef CONFIG_VSX +#define REST_32FPVSRS(n,c,base) \ +BEGIN_FTR_SECTION \ + b 2f; \ +END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ + REST_32FPRS(n,base); \ + b 3f; \ +2: REST_32VSRS(n,c,base); \ +3: + +#define SAVE_32FPVSRS(n,c,base) \ +BEGIN_FTR_SECTION \ + b 2f; \ +END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ + SAVE_32FPRS(n,base); \ + b 3f; \ +2: SAVE_32VSRS(n,c,base); \ +3: +#else +#define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) +#define SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) +#endif + /* * This task wants to use the FPU now. * On UP, disable FP for the task which had the FPU previously, diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h index 8f0426f973c9..0966899d974b 100644 --- a/include/asm-powerpc/ppc_asm.h +++ b/include/asm-powerpc/ppc_asm.h @@ -74,6 +74,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ REST_10GPRS(22, base) #endif +/* + * Define what the VSX XX1 form instructions will look like, then add + * the 128 bit load store instructions based on that. + */ +#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \ + ((rb) << 11) | (((xs) >> 5))) + +#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb))) +#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb))) #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) @@ -110,6 +119,33 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) +/* Save the lower 32 VSRs in the thread VSR region */ +#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base) +#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) +#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) +#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) +#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) +#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) +#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base) +#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) +#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) +#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) +#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) +#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) +/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ +#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base) +#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) +#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) +#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) +#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) +#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) +#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base) +#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) +#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) +#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) +#define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base) +#define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base) + #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base) #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base) #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base) @@ -540,6 +576,73 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #define vr30 30 #define vr31 31 +/* VSX Registers (VSRs) */ + +#define vsr0 0 +#define vsr1 1 +#define vsr2 2 +#define vsr3 3 +#define vsr4 4 +#define vsr5 5 +#define vsr6 6 +#define vsr7 7 +#define vsr8 8 +#define vsr9 9 +#define vsr10 10 +#define vsr11 11 +#define vsr12 12 +#define vsr13 13 +#define vsr14 14 +#define vsr15 15 +#define vsr16 16 +#define vsr17 17 +#define vsr18 18 +#define vsr19 19 +#define vsr20 20 +#define vsr21 21 +#define vsr22 22 +#define vsr23 23 +#define vsr24 24 +#define vsr25 25 +#define vsr26 26 +#define vsr27 27 +#define vsr28 28 +#define vsr29 29 +#define vsr30 30 +#define vsr31 31 +#define vsr32 32 +#define vsr33 33 +#define vsr34 34 +#define vsr35 35 +#define vsr36 36 +#define vsr37 37 +#define vsr38 38 +#define vsr39 39 +#define vsr40 40 +#define vsr41 41 +#define vsr42 42 +#define vsr43 43 +#define vsr44 44 +#define vsr45 45 +#define vsr46 46 +#define vsr47 47 +#define vsr48 48 +#define vsr49 49 +#define vsr50 50 +#define vsr51 51 +#define vsr52 52 +#define vsr53 53 +#define vsr54 54 +#define vsr55 55 +#define vsr56 56 +#define vsr57 57 +#define vsr58 58 +#define vsr59 59 +#define vsr60 60 +#define vsr61 61 +#define vsr62 62 +#define vsr63 63 + /* SPE Registers (EVPRs) */ #define evr0 0 -- cgit v1.2.3 From ce48b2100785e5ca629fb3aa8e3b50aca808f692 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 25 Jun 2008 14:07:18 +1000 Subject: powerpc: Add VSX context save/restore, ptrace and signal support This patch extends the floating point save and restore code to use the VSX load/stores when VSX is available. This will make FP context save/restore marginally slower on FP only code, when VSX is available, as it has to load/store 128bits rather than just 64bits. Mixing FP, VMX and VSX code will get constant architected state. The signals interface is extended to enable access to VSR 0-31 doubleword 1 after discussions with tool chain maintainers. Backward compatibility is maintained. The ptrace interface is also extended to allow access to VSR 0-31 full registers. Signed-off-by: Michael Neuling Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/entry_64.S | 5 ++ arch/powerpc/kernel/fpu.S | 16 ++++-- arch/powerpc/kernel/head_64.S | 65 ++++++++++++++++++++++++ arch/powerpc/kernel/misc_64.S | 33 ++++++++++++ arch/powerpc/kernel/ppc32.h | 1 + arch/powerpc/kernel/ppc_ksyms.c | 3 ++ arch/powerpc/kernel/process.c | 107 ++++++++++++++++++++++++++++++++++++++- arch/powerpc/kernel/ptrace.c | 70 +++++++++++++++++++++++++ arch/powerpc/kernel/signal_32.c | 33 ++++++++++++ arch/powerpc/kernel/signal_64.c | 31 +++++++++++- arch/powerpc/kernel/traps.c | 29 +++++++++++ include/asm-powerpc/elf.h | 6 ++- include/asm-powerpc/ptrace.h | 12 +++++ include/asm-powerpc/reg.h | 2 + include/asm-powerpc/sigcontext.h | 37 +++++++++++++- include/asm-powerpc/system.h | 9 ++++ 16 files changed, 451 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 6ca3044e2e32..12eb95a80ce9 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -353,6 +353,11 @@ _GLOBAL(_switch) mflr r20 /* Return to switch caller */ mfmsr r22 li r0, MSR_FP +#ifdef CONFIG_VSX +BEGIN_FTR_SECTION + oris r0,r0,MSR_VSX@h /* Disable VSX */ +END_FTR_SECTION_IFSET(CPU_FTR_VSX) +#endif /* CONFIG_VSX */ #ifdef CONFIG_ALTIVEC BEGIN_FTR_SECTION oris r0,r0,MSR_VEC@h /* Disable altivec */ diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index 15247fe171a8..a088c064ae40 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S @@ -57,6 +57,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ _GLOBAL(load_up_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_VSX +BEGIN_FTR_SECTION + oris r5,r5,MSR_VSX@h +END_FTR_SECTION_IFSET(CPU_FTR_VSX) +#endif SYNC MTMSRD(r5) /* enable use of fpu now */ isync @@ -73,7 +78,7 @@ _GLOBAL(load_up_fpu) beq 1f toreal(r4) addi r4,r4,THREAD /* want last_task_used_math->thread */ - SAVE_32FPRS(0, r4) + SAVE_32FPVSRS(0, r5, r4) mffs fr0 stfd fr0,THREAD_FPSCR(r4) PPC_LL r5,PT_REGS(r4) @@ -100,7 +105,7 @@ _GLOBAL(load_up_fpu) #endif lfd fr0,THREAD_FPSCR(r5) MTFSF_L(fr0) - REST_32FPRS(0, r5) + REST_32FPVSRS(0, r4, r5) #ifndef CONFIG_SMP subi r4,r5,THREAD fromreal(r4) @@ -119,6 +124,11 @@ _GLOBAL(load_up_fpu) _GLOBAL(giveup_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_VSX +BEGIN_FTR_SECTION + oris r5,r5,MSR_VSX@h +END_FTR_SECTION_IFSET(CPU_FTR_VSX) +#endif SYNC_601 ISYNC_601 MTMSRD(r5) /* enable use of fpu now */ @@ -129,7 +139,7 @@ _GLOBAL(giveup_fpu) addi r3,r3,THREAD /* want THREAD of task */ PPC_LL r5,PT_REGS(r3) PPC_LCMPI 0,r5,0 - SAVE_32FPRS(0, r3) + SAVE_32FPVSRS(0, r4 ,r3) mffs fr0 stfd fr0,THREAD_FPSCR(r3) beq 1f diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 64433731d995..ecced1eb03ae 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -278,6 +278,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) . = 0xf20 b altivec_unavailable_pSeries + . = 0xf40 + b vsx_unavailable_pSeries + #ifdef CONFIG_CBE_RAS HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) #endif /* CONFIG_CBE_RAS */ @@ -297,6 +300,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) /* moved from 0xf00 */ STD_EXCEPTION_PSERIES(., performance_monitor) STD_EXCEPTION_PSERIES(., altivec_unavailable) + STD_EXCEPTION_PSERIES(., vsx_unavailable) /* * An interrupt came in while soft-disabled; clear EE in SRR1, @@ -836,6 +840,67 @@ _STATIC(load_up_altivec) blr #endif /* CONFIG_ALTIVEC */ + .align 7 + .globl vsx_unavailable_common +vsx_unavailable_common: + EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) +#ifdef CONFIG_VSX +BEGIN_FTR_SECTION + bne .load_up_vsx +1: +END_FTR_SECTION_IFSET(CPU_FTR_VSX) +#endif + bl .save_nvgprs + addi r3,r1,STACK_FRAME_OVERHEAD + ENABLE_INTS + bl .vsx_unavailable_exception + b .ret_from_except + +#ifdef CONFIG_VSX +/* + * load_up_vsx(unused, unused, tsk) + * Disable VSX for the task which had it previously, + * and save its vector registers in its thread_struct. + * Reuse the fp and vsx saves, but first check to see if they have + * been saved already. + * On entry: r13 == 'current' && last_task_used_vsx != 'current' + */ +_STATIC(load_up_vsx) +/* Load FP and VSX registers if they haven't been done yet */ + andi. r5,r12,MSR_FP + beql+ load_up_fpu /* skip if already loaded */ + andis. r5,r12,MSR_VEC@h + beql+ load_up_altivec /* skip if already loaded */ + +#ifndef CONFIG_SMP + ld r3,last_task_used_vsx@got(r2) + ld r4,0(r3) + cmpdi 0,r4,0 + beq 1f + /* Disable VSX for last_task_used_vsx */ + addi r4,r4,THREAD + ld r5,PT_REGS(r4) + ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) + lis r6,MSR_VSX@h + andc r6,r4,r6 + std r6,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#endif /* CONFIG_SMP */ + ld r4,PACACURRENT(r13) + addi r4,r4,THREAD /* Get THREAD */ + li r6,1 + stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */ + /* enable use of VSX after return */ + oris r12,r12,MSR_VSX@h + std r12,_MSR(r1) +#ifndef CONFIG_SMP + /* Update last_task_used_math to 'current' */ + ld r4,PACACURRENT(r13) + std r4,0(r3) +#endif /* CONFIG_SMP */ + b fast_exception_return +#endif /* CONFIG_VSX */ + /* * Hash table stuff */ diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index 942951e76586..31b9026cf1e3 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S @@ -506,6 +506,39 @@ _GLOBAL(giveup_altivec) #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX +/* + * giveup_vsx(tsk) + * Disable VSX for the task given as the argument, + * and save the vector registers in its thread_struct. + * Enables the VSX for use in the kernel on return. + */ +_GLOBAL(giveup_vsx) + mfmsr r5 + oris r5,r5,MSR_VSX@h + mtmsrd r5 /* enable use of VSX now */ + isync + + cmpdi 0,r3,0 + beqlr- /* if no previous owner, done */ + addi r3,r3,THREAD /* want THREAD of task */ + ld r5,PT_REGS(r3) + cmpdi 0,r5,0 + beq 1f + ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) + lis r3,MSR_VSX@h + andc r4,r4,r3 /* disable VSX for previous task */ + std r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#ifndef CONFIG_SMP + li r5,0 + ld r4,last_task_used_vsx@got(r2) + std r5,0(r4) +#endif /* CONFIG_SMP */ + blr + +#endif /* CONFIG_VSX */ + /* kexec_wait(phys_cpu) * * wait for the flag to change, indicating this kernel is going away but diff --git a/arch/powerpc/kernel/ppc32.h b/arch/powerpc/kernel/ppc32.h index 90e562771791..dc16aefe1dd0 100644 --- a/arch/powerpc/kernel/ppc32.h +++ b/arch/powerpc/kernel/ppc32.h @@ -120,6 +120,7 @@ struct mcontext32 { elf_fpregset_t mc_fregs; unsigned int mc_pad[2]; elf_vrregset_t32 mc_vregs __attribute__((__aligned__(16))); + elf_vsrreghalf_t32 mc_vsregs __attribute__((__aligned__(16))); }; struct ucontext32 { diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c index d3ac631cbd26..958ecb9ae7dc 100644 --- a/arch/powerpc/kernel/ppc_ksyms.c +++ b/arch/powerpc/kernel/ppc_ksyms.c @@ -102,6 +102,9 @@ EXPORT_SYMBOL(giveup_fpu); #ifdef CONFIG_ALTIVEC EXPORT_SYMBOL(giveup_altivec); #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX +EXPORT_SYMBOL(giveup_vsx); +#endif /* CONFIG_VSX */ #ifdef CONFIG_SPE EXPORT_SYMBOL(giveup_spe); #endif /* CONFIG_SPE */ diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 582df70439cb..d52ded366f14 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -53,6 +53,7 @@ extern unsigned long _get_SP(void); #ifndef CONFIG_SMP struct task_struct *last_task_used_math = NULL; struct task_struct *last_task_used_altivec = NULL; +struct task_struct *last_task_used_vsx = NULL; struct task_struct *last_task_used_spe = NULL; #endif @@ -106,11 +107,23 @@ EXPORT_SYMBOL(enable_kernel_fp); int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpregs) { +#ifdef CONFIG_VSX + int i; + elf_fpreg_t *reg; +#endif + if (!tsk->thread.regs) return 0; flush_fp_to_thread(current); +#ifdef CONFIG_VSX + reg = (elf_fpreg_t *)fpregs; + for (i = 0; i < ELF_NFPREG - 1; i++, reg++) + *reg = tsk->thread.TS_FPR(i); + memcpy(reg, &tsk->thread.fpscr, sizeof(elf_fpreg_t)); +#else memcpy(fpregs, &tsk->thread.TS_FPR(0), sizeof(*fpregs)); +#endif return 1; } @@ -149,7 +162,7 @@ void flush_altivec_to_thread(struct task_struct *tsk) } } -int dump_task_altivec(struct task_struct *tsk, elf_vrregset_t *vrregs) +int dump_task_altivec(struct task_struct *tsk, elf_vrreg_t *vrregs) { /* ELF_NVRREG includes the VSCR and VRSAVE which we need to save * separately, see below */ @@ -179,6 +192,80 @@ int dump_task_altivec(struct task_struct *tsk, elf_vrregset_t *vrregs) } #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX +#if 0 +/* not currently used, but some crazy RAID module might want to later */ +void enable_kernel_vsx(void) +{ + WARN_ON(preemptible()); + +#ifdef CONFIG_SMP + if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) + giveup_vsx(current); + else + giveup_vsx(NULL); /* just enable vsx for kernel - force */ +#else + giveup_vsx(last_task_used_vsx); +#endif /* CONFIG_SMP */ +} +EXPORT_SYMBOL(enable_kernel_vsx); +#endif + +void flush_vsx_to_thread(struct task_struct *tsk) +{ + if (tsk->thread.regs) { + preempt_disable(); + if (tsk->thread.regs->msr & MSR_VSX) { +#ifdef CONFIG_SMP + BUG_ON(tsk != current); +#endif + giveup_vsx(tsk); + } + preempt_enable(); + } +} + +/* + * This dumps the lower half 64bits of the first 32 VSX registers. + * This needs to be called with dump_task_fp and dump_task_altivec to + * get all the VSX state. + */ +int dump_task_vsx(struct task_struct *tsk, elf_vrreg_t *vrregs) +{ + elf_vrreg_t *reg; + double buf[32]; + int i; + + if (tsk == current) + flush_vsx_to_thread(tsk); + + reg = (elf_vrreg_t *)vrregs; + + for (i = 0; i < 32 ; i++) + buf[i] = current->thread.fpr[i][TS_VSRLOWOFFSET]; + memcpy(reg, buf, sizeof(buf)); + + return 1; +} +#endif /* CONFIG_VSX */ + +int dump_task_vector(struct task_struct *tsk, elf_vrregset_t *vrregs) +{ + int rc = 0; + elf_vrreg_t *regs = (elf_vrreg_t *)vrregs; +#ifdef CONFIG_ALTIVEC + rc = dump_task_altivec(tsk, regs); + if (rc) + return rc; + regs += ELF_NVRREG; +#endif + +#ifdef CONFIG_VSX + rc = dump_task_vsx(tsk, regs); +#endif + return rc; +} + #ifdef CONFIG_SPE void enable_kernel_spe(void) @@ -233,6 +320,10 @@ void discard_lazy_cpu_state(void) if (last_task_used_altivec == current) last_task_used_altivec = NULL; #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX + if (last_task_used_vsx == current) + last_task_used_vsx = NULL; +#endif /* CONFIG_VSX */ #ifdef CONFIG_SPE if (last_task_used_spe == current) last_task_used_spe = NULL; @@ -297,6 +388,10 @@ struct task_struct *__switch_to(struct task_struct *prev, if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) giveup_altivec(prev); #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX + if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) + giveup_vsx(prev); +#endif /* CONFIG_VSX */ #ifdef CONFIG_SPE /* * If the previous thread used spe in the last quantum @@ -317,6 +412,10 @@ struct task_struct *__switch_to(struct task_struct *prev, if (new->thread.regs && last_task_used_altivec == new) new->thread.regs->msr |= MSR_VEC; #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX + if (new->thread.regs && last_task_used_vsx == new) + new->thread.regs->msr |= MSR_VSX; +#endif /* CONFIG_VSX */ #ifdef CONFIG_SPE /* Avoid the trap. On smp this this never happens since * we don't set last_task_used_spe @@ -417,6 +516,8 @@ static struct regbit { {MSR_EE, "EE"}, {MSR_PR, "PR"}, {MSR_FP, "FP"}, + {MSR_VEC, "VEC"}, + {MSR_VSX, "VSX"}, {MSR_ME, "ME"}, {MSR_IR, "IR"}, {MSR_DR, "DR"}, @@ -534,6 +635,7 @@ void prepare_to_copy(struct task_struct *tsk) { flush_fp_to_thread(current); flush_altivec_to_thread(current); + flush_vsx_to_thread(current); flush_spe_to_thread(current); } @@ -689,6 +791,9 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) #endif discard_lazy_cpu_state(); +#ifdef CONFIG_VSX + current->thread.used_vsr = 0; +#endif memset(current->thread.fpr, 0, sizeof(current->thread.fpr)); current->thread.fpscr.val = 0; #ifdef CONFIG_ALTIVEC diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 70fbde84b83f..4e203a89e189 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -350,6 +350,51 @@ static int vr_set(struct task_struct *target, const struct user_regset *regset, } #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX +/* + * Currently to set and and get all the vsx state, you need to call + * the fp and VMX calls aswell. This only get/sets the lower 32 + * 128bit VSX registers. + */ + +static int vsr_active(struct task_struct *target, + const struct user_regset *regset) +{ + flush_vsx_to_thread(target); + return target->thread.used_vsr ? regset->n : 0; +} + +static int vsr_get(struct task_struct *target, const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + int ret; + + flush_vsx_to_thread(target); + + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + target->thread.fpr, 0, + 32 * sizeof(vector128)); + + return ret; +} + +static int vsr_set(struct task_struct *target, const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + + flush_vsx_to_thread(target); + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + target->thread.fpr, 0, + 32 * sizeof(vector128)); + + return ret; +} +#endif /* CONFIG_VSX */ + #ifdef CONFIG_SPE /* @@ -426,6 +471,9 @@ enum powerpc_regset { #ifdef CONFIG_ALTIVEC REGSET_VMX, #endif +#ifdef CONFIG_VSX + REGSET_VSX, +#endif #ifdef CONFIG_SPE REGSET_SPE, #endif @@ -449,6 +497,13 @@ static const struct user_regset native_regsets[] = { .active = vr_active, .get = vr_get, .set = vr_set }, #endif +#ifdef CONFIG_VSX + [REGSET_VSX] = { + .n = 32, + .size = sizeof(vector128), .align = sizeof(vector128), + .active = vsr_active, .get = vsr_get, .set = vsr_set + }, +#endif #ifdef CONFIG_SPE [REGSET_SPE] = { .n = 35, @@ -849,6 +904,21 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) sizeof(u32)), (const void __user *) data); #endif +#ifdef CONFIG_VSX + case PTRACE_GETVSRREGS: + return copy_regset_to_user(child, &user_ppc_native_view, + REGSET_VSX, + 0, (32 * sizeof(vector128) + + sizeof(u32)), + (void __user *) data); + + case PTRACE_SETVSRREGS: + return copy_regset_from_user(child, &user_ppc_native_view, + REGSET_VSX, + 0, (32 * sizeof(vector128) + + sizeof(u32)), + (const void __user *) data); +#endif #ifdef CONFIG_SPE case PTRACE_GETEVRREGS: /* Get the child spe register state. */ diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index f7fa395b9fb5..349d3487d920 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c @@ -378,6 +378,21 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame, memcpy(&buf[i], ¤t->thread.fpscr, sizeof(double)); if (__copy_to_user(&frame->mc_fregs, buf, ELF_NFPREG * sizeof(double))) return 1; + /* + * Copy VSR 0-31 upper half from thread_struct to local + * buffer, then write that to userspace. Also set MSR_VSX in + * the saved MSR value to indicate that frame->mc_vregs + * contains valid data + */ + if (current->thread.used_vsr) { + flush_vsx_to_thread(current); + for (i = 0; i < 32 ; i++) + buf[i] = current->thread.fpr[i][TS_VSRLOWOFFSET]; + if (__copy_to_user(&frame->mc_vsregs, buf, + ELF_NVSRHALFREG * sizeof(double))) + return 1; + msr |= MSR_VSX; + } #else /* save floating-point registers */ if (__copy_to_user(&frame->mc_fregs, current->thread.fpr, @@ -482,6 +497,24 @@ static long restore_user_regs(struct pt_regs *regs, for (i = 0; i < 32 ; i++) current->thread.TS_FPR(i) = buf[i]; memcpy(¤t->thread.fpscr, &buf[i], sizeof(double)); + /* + * Force the process to reload the VSX registers from + * current->thread when it next does VSX instruction. + */ + regs->msr &= ~MSR_VSX; + if (msr & MSR_VSX) { + /* + * Restore altivec registers from the stack to a local + * buffer, then write this out to the thread_struct + */ + if (__copy_from_user(buf, &sr->mc_vsregs, + sizeof(sr->mc_vsregs))) + return 1; + for (i = 0; i < 32 ; i++) + current->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i]; + } else if (current->thread.used_vsr) + for (i = 0; i < 32 ; i++) + current->thread.fpr[i][TS_VSRLOWOFFSET] = 0; #else if (__copy_from_user(current->thread.fpr, &sr->mc_fregs, sizeof(sr->mc_fregs))) diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c index a587b33cd6b9..34f37e59bacc 100644 --- a/arch/powerpc/kernel/signal_64.c +++ b/arch/powerpc/kernel/signal_64.c @@ -123,6 +123,22 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, buf[i] = current->thread.TS_FPR(i); memcpy(&buf[i], ¤t->thread.fpscr, sizeof(double)); err |= __copy_to_user(&sc->fp_regs, buf, FP_REGS_SIZE); + /* + * Copy VSX low doubleword to local buffer for formatting, + * then out to userspace. Update v_regs to point after the + * VMX data. + */ + if (current->thread.used_vsr) { + flush_vsx_to_thread(current); + v_regs += ELF_NVRREG; + for (i = 0; i < 32 ; i++) + buf[i] = current->thread.fpr[i][TS_VSRLOWOFFSET]; + err |= __copy_to_user(v_regs, buf, 32 * sizeof(double)); + /* set MSR_VSX in the MSR value in the frame to + * indicate that sc->vs_reg) contains valid data. + */ + msr |= MSR_VSX; + } #else /* CONFIG_VSX */ /* copy fpr regs and fpscr */ err |= __copy_to_user(&sc->fp_regs, ¤t->thread.fpr, FP_REGS_SIZE); @@ -197,7 +213,7 @@ static long restore_sigcontext(struct pt_regs *regs, sigset_t *set, int sig, * This has to be done before copying stuff into current->thread.fpr/vr * for the reasons explained in the previous comment. */ - regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC); + regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX); #ifdef CONFIG_ALTIVEC err |= __get_user(v_regs, &sc->v_regs); @@ -226,6 +242,19 @@ static long restore_sigcontext(struct pt_regs *regs, sigset_t *set, int sig, current->thread.TS_FPR(i) = buf[i]; memcpy(¤t->thread.fpscr, &buf[i], sizeof(double)); + /* + * Get additional VSX data. Update v_regs to point after the + * VMX data. Copy VSX low doubleword from userspace to local + * buffer for formatting, then into the taskstruct. + */ + v_regs += ELF_NVRREG; + if ((msr & MSR_VSX) != 0) + err |= __copy_from_user(buf, v_regs, 32 * sizeof(double)); + else + memset(buf, 0, 32 * sizeof(double)); + + for (i = 0; i < 32 ; i++) + current->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i]; #else err |= __copy_from_user(¤t->thread.fpr, &sc->fp_regs, FP_REGS_SIZE); #endif diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index b463d48145a4..878fbddb6ae1 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -967,6 +967,20 @@ void altivec_unavailable_exception(struct pt_regs *regs) die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); } +void vsx_unavailable_exception(struct pt_regs *regs) +{ + if (user_mode(regs)) { + /* A user program has executed an vsx instruction, + but this kernel doesn't support vsx. */ + _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); + return; + } + + printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " + "%lx at %lx\n", regs->trap, regs->nip); + die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); +} + void performance_monitor_exception(struct pt_regs *regs) { perf_irq(regs); @@ -1099,6 +1113,21 @@ void altivec_assist_exception(struct pt_regs *regs) } #endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_VSX +void vsx_assist_exception(struct pt_regs *regs) +{ + if (!user_mode(regs)) { + printk(KERN_EMERG "VSX assist exception in kernel mode" + " at %lx\n", regs->nip); + die("Kernel VSX assist exception", regs, SIGILL); + } + + flush_vsx_to_thread(current); + printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); + _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); +} +#endif /* CONFIG_VSX */ + #ifdef CONFIG_FSL_BOOKE void CacheLockingException(struct pt_regs *regs, unsigned long address, unsigned long error_code) diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h index d1e3bda0625d..746e53d60cbe 100644 --- a/include/asm-powerpc/elf.h +++ b/include/asm-powerpc/elf.h @@ -109,6 +109,7 @@ typedef elf_gregset_t32 compat_elf_gregset_t; #ifdef __powerpc64__ # define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */ # define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */ +# define ELF_NVSRHALFREG 32 /* Half the vsx registers */ # define ELF_GREG_TYPE elf_greg_t64 #else # define ELF_NEVRREG 34 /* includes acc (as 2) */ @@ -158,6 +159,7 @@ typedef __vector128 elf_vrreg_t; typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG]; #ifdef __powerpc64__ typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32]; +typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG]; #endif #ifdef __KERNEL__ @@ -219,8 +221,8 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); typedef elf_vrregset_t elf_fpxregset_t; #ifdef CONFIG_ALTIVEC -extern int dump_task_altivec(struct task_struct *, elf_vrregset_t *vrregs); -#define ELF_CORE_COPY_XFPREGS(tsk, regs) dump_task_altivec(tsk, regs) +extern int dump_task_vector(struct task_struct *, elf_vrregset_t *vrregs); +#define ELF_CORE_COPY_XFPREGS(tsk, regs) dump_task_vector(tsk, regs) #define ELF_CORE_XFPREG_TYPE NT_PPC_VMX #endif diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h index 38d87e5e569d..3d6e31024e56 100644 --- a/include/asm-powerpc/ptrace.h +++ b/include/asm-powerpc/ptrace.h @@ -224,6 +224,14 @@ extern void user_disable_single_step(struct task_struct *); #define PT_VRSAVE_32 (PT_VR0 + 33*4) #endif +/* + * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 + */ +#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ +#define PT_VSR31 (PT_VSR0 + 2*31) +#ifdef __KERNEL__ +#define PT_VSR0_32 300 /* each VSR reg occupies 4 slots in 32-bit */ +#endif #endif /* __powerpc64__ */ /* @@ -246,6 +254,10 @@ extern void user_disable_single_step(struct task_struct *); #define PTRACE_GETEVRREGS 20 #define PTRACE_SETEVRREGS 21 +/* Get the first 32 128bit VSX registers */ +#define PTRACE_GETVSRREGS 27 +#define PTRACE_SETVSRREGS 28 + /* * Get or set a debug register. The first 16 are DABR registers and the * second 16 are IABR registers. diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index 7256efb5c140..bbccadfee0d6 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h @@ -30,6 +30,7 @@ #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ #define MSR_HV_LG 60 /* Hypervisor state */ #define MSR_VEC_LG 25 /* Enable AltiVec */ +#define MSR_VSX_LG 23 /* Enable VSX */ #define MSR_POW_LG 18 /* Enable Power Management */ #define MSR_WE_LG 18 /* Wait State Enable */ #define MSR_TGPR_LG 17 /* TLB Update registers in use */ @@ -71,6 +72,7 @@ #endif #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ +#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ diff --git a/include/asm-powerpc/sigcontext.h b/include/asm-powerpc/sigcontext.h index 165d630e1cf3..9c1f24fd5d11 100644 --- a/include/asm-powerpc/sigcontext.h +++ b/include/asm-powerpc/sigcontext.h @@ -43,9 +43,44 @@ struct sigcontext { * it must be copied via a vector register to/from storage) or as a word. * The entry with index 33 contains the vrsave as the first word (offset 0) * within the quadword. + * + * Part of the VSX data is stored here also by extending vmx_restore + * by an additional 32 double words. Architecturally the layout of + * the VSR registers and how they overlap on top of the legacy FPR and + * VR registers is shown below: + * + * VSR doubleword 0 VSR doubleword 1 + * ---------------------------------------------------------------- + * VSR[0] | FPR[0] | | + * ---------------------------------------------------------------- + * VSR[1] | FPR[1] | | + * ---------------------------------------------------------------- + * | ... | | + * | ... | | + * ---------------------------------------------------------------- + * VSR[30] | FPR[30] | | + * ---------------------------------------------------------------- + * VSR[31] | FPR[31] | | + * ---------------------------------------------------------------- + * VSR[32] | VR[0] | + * ---------------------------------------------------------------- + * VSR[33] | VR[1] | + * ---------------------------------------------------------------- + * | ... | + * | ... | + * ---------------------------------------------------------------- + * VSR[62] | VR[30] | + * ---------------------------------------------------------------- + * VSR[63] | VR[31] | + * ---------------------------------------------------------------- + * + * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63 + * is stored at the start of vmx_reserve. vmx_reserve is extended for + * backwards compatility to store VSR 0-31 doubleword 1 after the VMX + * registers and vscr/vrsave. */ elf_vrreg_t __user *v_regs; - long vmx_reserve[ELF_NVRREG+ELF_NVRREG+1]; + long vmx_reserve[ELF_NVRREG+ELF_NVRREG+32+1]; #endif }; diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 2642a92b724f..0c12c66733f6 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -139,6 +139,7 @@ extern void enable_kernel_altivec(void); extern void giveup_altivec(struct task_struct *); extern void load_up_altivec(struct task_struct *); extern int emulate_altivec(struct pt_regs *); +extern void giveup_vsx(struct task_struct *); extern void enable_kernel_spe(void); extern void giveup_spe(struct task_struct *); extern void load_up_spe(struct task_struct *); @@ -162,6 +163,14 @@ static inline void flush_altivec_to_thread(struct task_struct *t) } #endif +#ifdef CONFIG_VSX +extern void flush_vsx_to_thread(struct task_struct *); +#else +static inline void flush_vsx_to_thread(struct task_struct *t) +{ +} +#endif + #ifdef CONFIG_SPE extern void flush_spe_to_thread(struct task_struct *); #else -- cgit v1.2.3 From 016b33c4958681c24056abed8ec95844a0da80a3 Mon Sep 17 00:00:00 2001 From: Andy Whitcroft Date: Thu, 26 Jun 2008 19:55:58 +1000 Subject: powerpc: Add 64 bit version of huge_ptep_set_wrprotect The implementation of huge_ptep_set_wrprotect() directly calls ptep_set_wrprotect() to mark a hugepte write protected. However this call is not appropriate on ppc64 kernels as this is a small page only implementation. This can lead to the hash not being flushed correctly when a mapping is being converted to COW, allowing processes to continue using the original copy. Currently huge_ptep_set_wrprotect() unconditionally calls ptep_set_wrprotect(). This is fine on ppc32 kernels as this call is generic. On 64 bit this is implemented as: pte_update(mm, addr, ptep, _PAGE_RW, 0); On ppc64 this last parameter is the page size and is passed directly on to hpte_need_flush(): hpte_need_flush(mm, addr, ptep, old, huge); And this directly affects the page size we pass to flush_hash_page(): flush_hash_page(vaddr, rpte, psize, ssize, 0); As this changes the way the hash is calculated we will flush the wrong pages, potentially leaving live hashes to the original page. Move the definition of huge_ptep_set_wrprotect() to the 32/64 bit specific headers. Signed-off-by: Andy Whitcroft Acked-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras --- include/asm-powerpc/hugetlb.h | 6 ------ include/asm-powerpc/pgtable-ppc32.h | 6 ++++++ include/asm-powerpc/pgtable-ppc64.h | 9 +++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/hugetlb.h b/include/asm-powerpc/hugetlb.h index 649c6c3b87b3..be32ff02f4a0 100644 --- a/include/asm-powerpc/hugetlb.h +++ b/include/asm-powerpc/hugetlb.h @@ -49,12 +49,6 @@ static inline pte_t huge_pte_wrprotect(pte_t pte) return pte_wrprotect(pte); } -static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, - unsigned long addr, pte_t *ptep) -{ - ptep_set_wrprotect(mm, addr, ptep); -} - static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, pte_t pte, int dirty) diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h index dde466bd2cea..e1d2bb57f1d5 100644 --- a/include/asm-powerpc/pgtable-ppc32.h +++ b/include/asm-powerpc/pgtable-ppc32.h @@ -652,6 +652,12 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, { pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); } +static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, + unsigned long addr, pte_t *ptep) +{ + ptep_set_wrprotect(mm, addr, ptep); +} + #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h index 2e48be841cc9..b2754d46be44 100644 --- a/include/asm-powerpc/pgtable-ppc64.h +++ b/include/asm-powerpc/pgtable-ppc64.h @@ -312,6 +312,15 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, return; old = pte_update(mm, addr, ptep, _PAGE_RW, 0); } +static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, + unsigned long addr, pte_t *ptep) +{ + unsigned long old; + + if ((pte_val(*ptep) & _PAGE_RW) == 0) + return; + old = pte_update(mm, addr, ptep, _PAGE_RW, 1); +} /* * We currently remove entries from the hashtable regardless of whether -- cgit v1.2.3 From 89b5810f6ed4b2d42415e5ec656ab6b148cd2bde Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Sat, 28 Jun 2008 16:51:35 +1000 Subject: powerpc: Make sure that include/asm-powerpc/spinlock.h does not trigger compilation warnings When compiling kernel modules for ppc that include , gcc prints a warning message every time it encounters a function declaration where the inline keyword appears after the return type. This makes sure that the order of the inline keyword and the return type is as gcc expects it. Additionally, the __inline__ keyword is replaced by inline, as checkpatch expects. Signed-off-by: Bart Van Assche Signed-off-by: Paul Mackerras --- include/asm-powerpc/spinlock.h | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/spinlock.h b/include/asm-powerpc/spinlock.h index 258c93993190..f56a843f4705 100644 --- a/include/asm-powerpc/spinlock.h +++ b/include/asm-powerpc/spinlock.h @@ -54,7 +54,7 @@ * This returns the old value in the lock, so we succeeded * in getting the lock if the return value is 0. */ -static __inline__ unsigned long __spin_trylock(raw_spinlock_t *lock) +static inline unsigned long __spin_trylock(raw_spinlock_t *lock) { unsigned long tmp, token; @@ -73,7 +73,7 @@ static __inline__ unsigned long __spin_trylock(raw_spinlock_t *lock) return tmp; } -static int __inline__ __raw_spin_trylock(raw_spinlock_t *lock) +static inline int __raw_spin_trylock(raw_spinlock_t *lock) { CLEAR_IO_SYNC; return __spin_trylock(lock) == 0; @@ -104,7 +104,7 @@ extern void __rw_yield(raw_rwlock_t *lock); #define SHARED_PROCESSOR 0 #endif -static void __inline__ __raw_spin_lock(raw_spinlock_t *lock) +static inline void __raw_spin_lock(raw_spinlock_t *lock) { CLEAR_IO_SYNC; while (1) { @@ -119,7 +119,8 @@ static void __inline__ __raw_spin_lock(raw_spinlock_t *lock) } } -static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) +static inline +void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) { unsigned long flags_dis; @@ -139,7 +140,7 @@ static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long } } -static __inline__ void __raw_spin_unlock(raw_spinlock_t *lock) +static inline void __raw_spin_unlock(raw_spinlock_t *lock) { SYNC_IO; __asm__ __volatile__("# __raw_spin_unlock\n\t" @@ -180,7 +181,7 @@ extern void __raw_spin_unlock_wait(raw_spinlock_t *lock); * This returns the old value in the lock + 1, * so we got a read lock if the return value is > 0. */ -static long __inline__ __read_trylock(raw_rwlock_t *rw) +static inline long __read_trylock(raw_rwlock_t *rw) { long tmp; @@ -204,7 +205,7 @@ static long __inline__ __read_trylock(raw_rwlock_t *rw) * This returns the old value in the lock, * so we got the write lock if the return value is 0. */ -static __inline__ long __write_trylock(raw_rwlock_t *rw) +static inline long __write_trylock(raw_rwlock_t *rw) { long tmp, token; @@ -224,7 +225,7 @@ static __inline__ long __write_trylock(raw_rwlock_t *rw) return tmp; } -static void __inline__ __raw_read_lock(raw_rwlock_t *rw) +static inline void __raw_read_lock(raw_rwlock_t *rw) { while (1) { if (likely(__read_trylock(rw) > 0)) @@ -238,7 +239,7 @@ static void __inline__ __raw_read_lock(raw_rwlock_t *rw) } } -static void __inline__ __raw_write_lock(raw_rwlock_t *rw) +static inline void __raw_write_lock(raw_rwlock_t *rw) { while (1) { if (likely(__write_trylock(rw) == 0)) @@ -252,17 +253,17 @@ static void __inline__ __raw_write_lock(raw_rwlock_t *rw) } } -static int __inline__ __raw_read_trylock(raw_rwlock_t *rw) +static inline int __raw_read_trylock(raw_rwlock_t *rw) { return __read_trylock(rw) > 0; } -static int __inline__ __raw_write_trylock(raw_rwlock_t *rw) +static inline int __raw_write_trylock(raw_rwlock_t *rw) { return __write_trylock(rw) == 0; } -static void __inline__ __raw_read_unlock(raw_rwlock_t *rw) +static inline void __raw_read_unlock(raw_rwlock_t *rw) { long tmp; @@ -279,7 +280,7 @@ static void __inline__ __raw_read_unlock(raw_rwlock_t *rw) : "cr0", "memory"); } -static __inline__ void __raw_write_unlock(raw_rwlock_t *rw) +static inline void __raw_write_unlock(raw_rwlock_t *rw) { __asm__ __volatile__("# write_unlock\n\t" LWSYNC_ON_SMP: : :"memory"); -- cgit v1.2.3 From a91a03ee31a5c29a934708b7cf37bb8da516d016 Mon Sep 17 00:00:00 2001 From: Eric B Munson Date: Tue, 1 Jul 2008 02:12:13 +1000 Subject: powerpc: Keep 3 high personality bytes across exec Currently when a 32 bit process is exec'd on a powerpc 64 bit host the value in the top three bytes of the personality is clobbered. patch adds a check in the SET_PERSONALITY macro that will carry all the values in the top three bytes across the exec. These three bytes currently carry flags to disable address randomisation, limit the address space, force zeroing of an mmapped page, etc. Should an application set any of these bits they will be maintained and honoured on homogeneous environment but discarded and ignored on a heterogeneous environment. So if an application requires all mmapped pages to be initialised to zero and a wrapper is used to setup the personality and exec the target, these flags will remain set on an all 32 or all 64 bit envrionment, but they will be lost in the exec on a mixed 32/64 bit environment. Losing these bits means that the same application would behave differently in different environments. Tested on a POWER5+ machine with 64bit kernel and a mixed 64/32 bit user space. Signed-off-by: Eric B Munson Signed-off-by: Paul Mackerras --- include/asm-powerpc/elf.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h index 746e53d60cbe..b6a874db801d 100644 --- a/include/asm-powerpc/elf.h +++ b/include/asm-powerpc/elf.h @@ -255,7 +255,8 @@ do { \ else \ clear_thread_flag(TIF_ABI_PENDING); \ if (personality(current->personality) != PER_LINUX32) \ - set_personality(PER_LINUX); \ + set_personality(PER_LINUX | \ + (current->personality & (~PER_MASK))); \ } while (0) /* * An executable for which elf_read_implies_exec() returns TRUE will -- cgit v1.2.3 From f3e909c2750eb20536bacacc867dc9047b70546a Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Tue, 1 Jul 2008 14:01:39 +1000 Subject: powerpc: Update for VSX core file and ptrace This correctly hooks the VSX dump into Roland McGrath core file infrastructure. It adds the VSX dump information as an additional elf note in the core file (after talking more to the tool chain/gdb guys). This also ensures the formats are consistent between signals, ptrace and core files. Signed-off-by: Michael Neuling Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/process.c | 19 +------------------ arch/powerpc/kernel/ptrace.c | 21 +++++++++++++-------- include/asm-powerpc/elf.h | 4 ++-- include/linux/elf.h | 1 + 4 files changed, 17 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index d52ded366f14..1924b57bd241 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -162,7 +162,7 @@ void flush_altivec_to_thread(struct task_struct *tsk) } } -int dump_task_altivec(struct task_struct *tsk, elf_vrreg_t *vrregs) +int dump_task_altivec(struct task_struct *tsk, elf_vrregset_t *vrregs) { /* ELF_NVRREG includes the VSCR and VRSAVE which we need to save * separately, see below */ @@ -249,23 +249,6 @@ int dump_task_vsx(struct task_struct *tsk, elf_vrreg_t *vrregs) } #endif /* CONFIG_VSX */ -int dump_task_vector(struct task_struct *tsk, elf_vrregset_t *vrregs) -{ - int rc = 0; - elf_vrreg_t *regs = (elf_vrreg_t *)vrregs; -#ifdef CONFIG_ALTIVEC - rc = dump_task_altivec(tsk, regs); - if (rc) - return rc; - regs += ELF_NVRREG; -#endif - -#ifdef CONFIG_VSX - rc = dump_task_vsx(tsk, regs); -#endif - return rc; -} - #ifdef CONFIG_SPE void enable_kernel_spe(void) diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 4e203a89e189..8feb93e7890c 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -368,13 +368,15 @@ static int vsr_get(struct task_struct *target, const struct user_regset *regset, unsigned int pos, unsigned int count, void *kbuf, void __user *ubuf) { - int ret; + double buf[32]; + int ret, i; flush_vsx_to_thread(target); + for (i = 0; i < 32 ; i++) + buf[i] = current->thread.fpr[i][TS_VSRLOWOFFSET]; ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, - target->thread.fpr, 0, - 32 * sizeof(vector128)); + buf, 0, 32 * sizeof(double)); return ret; } @@ -383,13 +385,16 @@ static int vsr_set(struct task_struct *target, const struct user_regset *regset, unsigned int pos, unsigned int count, const void *kbuf, const void __user *ubuf) { - int ret; + double buf[32]; + int ret,i; flush_vsx_to_thread(target); ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - target->thread.fpr, 0, - 32 * sizeof(vector128)); + buf, 0, 32 * sizeof(double)); + for (i = 0; i < 32 ; i++) + current->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i]; + return ret; } @@ -499,8 +504,8 @@ static const struct user_regset native_regsets[] = { #endif #ifdef CONFIG_VSX [REGSET_VSX] = { - .n = 32, - .size = sizeof(vector128), .align = sizeof(vector128), + .core_note_type = NT_PPC_VSX, .n = 32, + .size = sizeof(double), .align = sizeof(double), .active = vsr_active, .get = vsr_get, .set = vsr_set }, #endif diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h index b6a874db801d..38a51728406f 100644 --- a/include/asm-powerpc/elf.h +++ b/include/asm-powerpc/elf.h @@ -221,8 +221,8 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); typedef elf_vrregset_t elf_fpxregset_t; #ifdef CONFIG_ALTIVEC -extern int dump_task_vector(struct task_struct *, elf_vrregset_t *vrregs); -#define ELF_CORE_COPY_XFPREGS(tsk, regs) dump_task_vector(tsk, regs) +extern int dump_task_altivec(struct task_struct *, elf_vrregset_t *vrregs); +#define ELF_CORE_COPY_XFPREGS(tsk, regs) dump_task_altivec(tsk, regs) #define ELF_CORE_XFPREG_TYPE NT_PPC_VMX #endif diff --git a/include/linux/elf.h b/include/linux/elf.h index ff9fbed90123..edc3dac3f02f 100644 --- a/include/linux/elf.h +++ b/include/linux/elf.h @@ -358,6 +358,7 @@ typedef struct elf64_shdr { #define NT_PRXFPREG 0x46e62b7f /* copied from gdb5.1/include/elf/common.h */ #define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ #define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ +#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ #define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ -- cgit v1.2.3 From db7f37de2c8346c33cf9279fa9d8e8316e8d821c Mon Sep 17 00:00:00 2001 From: Tony Breeds Date: Tue, 1 Jul 2008 11:30:06 +1000 Subject: powerpc: Fix building of arch/powerpc/mm/mem.o when MEMORY_HOTPLUG=y and SPARSEMEM=n Currently the kernel fails to build with the above config options with: CC arch/powerpc/mm/mem.o arch/powerpc/mm/mem.c: In function 'arch_add_memory': arch/powerpc/mm/mem.c:130: error: implicit declaration of function 'create_section_mapping' This explicitly includes asm/sparsemem.h in arch/powerpc/mm/mem.c and moves the guards in include/asm-powerpc/sparsemem.h to protect the SPARSEMEM specific portions only. Signed-off-by: Tony Breeds Signed-off-by: Paul Mackerras --- arch/powerpc/mm/mem.c | 1 + include/asm-powerpc/sparsemem.h | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index 51f82d83bf14..776ba6ad5e1e 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h index 9aea8e9f0bd1..54a47ea2c3aa 100644 --- a/include/asm-powerpc/sparsemem.h +++ b/include/asm-powerpc/sparsemem.h @@ -13,6 +13,8 @@ #define MAX_PHYSADDR_BITS 44 #define MAX_PHYSMEM_BITS 44 +#endif /* CONFIG_SPARSEMEM */ + #ifdef CONFIG_MEMORY_HOTPLUG extern void create_section_mapping(unsigned long start, unsigned long end); extern int remove_section_mapping(unsigned long start, unsigned long end); @@ -26,7 +28,5 @@ static inline int hot_add_scn_to_nid(unsigned long scn_addr) #endif /* CONFIG_NUMA */ #endif /* CONFIG_MEMORY_HOTPLUG */ -#endif /* CONFIG_SPARSEMEM */ - #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_SPARSEMEM_H */ -- cgit v1.2.3 From e17a2565bf61204cb925c3f77c3c7f6a09eb2fbe Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Tue, 1 Jul 2008 17:00:39 +1000 Subject: powerpc: Fix compile warning in init_thread Currently we get this warning: arch/powerpc/kernel/init_task.c:33: warning: missing braces around initializer arch/powerpc/kernel/init_task.c:33: warning: (near initialization for 'init_task.thread.fpr[0]') This fixes it. Noticed by Stephen Rothwell. Signed-off-by: Michael Neuling Signed-off-by: Paul Mackerras --- include/asm-powerpc/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index e93e72df4bca..061cd17ba83b 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h @@ -222,7 +222,7 @@ struct thread_struct { .ksp_limit = INIT_SP_LIMIT, \ .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \ .fs = KERNEL_DS, \ - .fpr = {0}, \ + .fpr = {{0}}, \ .fpscr = { .val = 0, }, \ .fpexc_mode = 0, \ } -- cgit v1.2.3 From 2d1b2027626d5151fff8ef7c06ca8e7876a1a510 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 2 Jul 2008 01:16:40 +1000 Subject: powerpc: Fixup lwsync at runtime To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by: Kumar Gala Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/module.c | 6 ++++++ arch/powerpc/kernel/setup_32.c | 4 ++++ arch/powerpc/kernel/setup_64.c | 2 ++ arch/powerpc/kernel/vdso.c | 10 +++++++++ arch/powerpc/kernel/vdso32/vdso32.lds.S | 3 +++ arch/powerpc/kernel/vdso64/vdso64.lds.S | 3 +++ arch/powerpc/kernel/vmlinux.lds.S | 6 ++++++ arch/powerpc/lib/feature-fixups-test.S | 15 +++++++++++++ arch/powerpc/lib/feature-fixups.c | 36 +++++++++++++++++++++++++++++++ include/asm-powerpc/code-patching.h | 3 ++- include/asm-powerpc/cputable.h | 21 +++++++++--------- include/asm-powerpc/feature-fixups.h | 10 +++++++++ include/asm-powerpc/synch.h | 38 ++++++++++++++++++++------------- 13 files changed, 131 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c index 40dd52d81c18..af07003573c4 100644 --- a/arch/powerpc/kernel/module.c +++ b/arch/powerpc/kernel/module.c @@ -86,6 +86,12 @@ int module_finalize(const Elf_Ehdr *hdr, (void *)sect->sh_addr + sect->sh_size); #endif + sect = find_section(hdr, sechdrs, "__lwsync_fixup"); + if (sect != NULL) + do_lwsync_fixups(cur_cpu_spec->cpu_features, + (void *)sect->sh_addr, + (void *)sect->sh_addr + sect->sh_size); + return 0; } diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index 9e83add54290..0109e7f0ccf9 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -101,6 +101,10 @@ unsigned long __init early_init(unsigned long dt_ptr) PTRRELOC(&__start___ftr_fixup), PTRRELOC(&__stop___ftr_fixup)); + do_lwsync_fixups(spec->cpu_features, + PTRRELOC(&__start___lwsync_fixup), + PTRRELOC(&__stop___lwsync_fixup)); + return KERNELBASE + offset; } diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index 098fd96a394a..04d8de9f0fc6 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c @@ -363,6 +363,8 @@ void __init setup_system(void) &__start___ftr_fixup, &__stop___ftr_fixup); do_feature_fixups(powerpc_firmware_features, &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); + do_lwsync_fixups(cur_cpu_spec->cpu_features, + &__start___lwsync_fixup, &__stop___lwsync_fixup); /* * Unflatten the device-tree passed by prom_init or kexec diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c index ce245a850db2..f177c60ea766 100644 --- a/arch/powerpc/kernel/vdso.c +++ b/arch/powerpc/kernel/vdso.c @@ -571,6 +571,11 @@ static __init int vdso_fixup_features(struct lib32_elfinfo *v32, if (start64) do_feature_fixups(powerpc_firmware_features, start64, start64 + size64); + + start64 = find_section64(v64->hdr, "__lwsync_fixup", &size64); + if (start64) + do_lwsync_fixups(cur_cpu_spec->cpu_features, + start64, start64 + size64); #endif /* CONFIG_PPC64 */ start32 = find_section32(v32->hdr, "__ftr_fixup", &size32); @@ -585,6 +590,11 @@ static __init int vdso_fixup_features(struct lib32_elfinfo *v32, start32, start32 + size32); #endif /* CONFIG_PPC64 */ + start32 = find_section32(v32->hdr, "__lwsync_fixup", &size32); + if (start32) + do_lwsync_fixups(cur_cpu_spec->cpu_features, + start32, start32 + size32); + return 0; } diff --git a/arch/powerpc/kernel/vdso32/vdso32.lds.S b/arch/powerpc/kernel/vdso32/vdso32.lds.S index 271793577cdc..be3b6a41dc09 100644 --- a/arch/powerpc/kernel/vdso32/vdso32.lds.S +++ b/arch/powerpc/kernel/vdso32/vdso32.lds.S @@ -33,6 +33,9 @@ SECTIONS . = ALIGN(8); __ftr_fixup : { *(__ftr_fixup) } + . = ALIGN(8); + __lwsync_fixup : { *(__lwsync_fixup) } + #ifdef CONFIG_PPC64 . = ALIGN(8); __fw_ftr_fixup : { *(__fw_ftr_fixup) } diff --git a/arch/powerpc/kernel/vdso64/vdso64.lds.S b/arch/powerpc/kernel/vdso64/vdso64.lds.S index e608d1bd3bff..d0b2526dd38d 100644 --- a/arch/powerpc/kernel/vdso64/vdso64.lds.S +++ b/arch/powerpc/kernel/vdso64/vdso64.lds.S @@ -34,6 +34,9 @@ SECTIONS . = ALIGN(8); __ftr_fixup : { *(__ftr_fixup) } + . = ALIGN(8); + __lwsync_fixup : { *(__lwsync_fixup) } + . = ALIGN(8); __fw_ftr_fixup : { *(__fw_ftr_fixup) } diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index 3c07811989fc..6856f6c15727 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -127,6 +127,12 @@ SECTIONS *(__ftr_fixup) __stop___ftr_fixup = .; } + . = ALIGN(8); + __lwsync_fixup : AT(ADDR(__lwsync_fixup) - LOAD_OFFSET) { + __start___lwsync_fixup = .; + *(__lwsync_fixup) + __stop___lwsync_fixup = .; + } #ifdef CONFIG_PPC64 . = ALIGN(8); __fw_ftr_fixup : AT(ADDR(__fw_ftr_fixup) - LOAD_OFFSET) { diff --git a/arch/powerpc/lib/feature-fixups-test.S b/arch/powerpc/lib/feature-fixups-test.S index 0549be04399c..cb737484c5aa 100644 --- a/arch/powerpc/lib/feature-fixups-test.S +++ b/arch/powerpc/lib/feature-fixups-test.S @@ -10,6 +10,7 @@ #include #include +#include .text @@ -725,3 +726,17 @@ MAKE_MACRO_TEST_EXPECTED(FTR); MAKE_MACRO_TEST(FW_FTR); MAKE_MACRO_TEST_EXPECTED(FW_FTR); #endif + +globl(lwsync_fixup_test) +1: or 1,1,1 + LWSYNC +globl(end_lwsync_fixup_test) + +globl(lwsync_fixup_test_expected_LWSYNC) +1: or 1,1,1 + lwsync + +globl(lwsync_fixup_test_expected_SYNC) +1: or 1,1,1 + sync + diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c index 48e1ed89052d..4e43702b9813 100644 --- a/arch/powerpc/lib/feature-fixups.c +++ b/arch/powerpc/lib/feature-fixups.c @@ -110,6 +110,22 @@ void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end) } } +void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end) +{ + unsigned int *start, *end, *dest; + + if (!(value & CPU_FTR_LWSYNC)) + return ; + + start = fixup_start; + end = fixup_end; + + for (; start < end; start++) { + dest = (void *)start + *start; + patch_instruction(dest, PPC_LWSYNC_INSTR); + } +} + #ifdef CONFIG_FTR_FIXUP_SELFTEST #define check(x) \ @@ -295,6 +311,25 @@ static void test_fw_macros(void) #endif } +static void test_lwsync_macros(void) +{ + extern void lwsync_fixup_test; + extern void end_lwsync_fixup_test; + extern void lwsync_fixup_test_expected_LWSYNC; + extern void lwsync_fixup_test_expected_SYNC; + unsigned long size = &end_lwsync_fixup_test - + &lwsync_fixup_test; + + /* The fixups have already been done for us during boot */ + if (cur_cpu_spec->cpu_features & CPU_FTR_LWSYNC) { + check(memcmp(&lwsync_fixup_test, + &lwsync_fixup_test_expected_LWSYNC, size) == 0); + } else { + check(memcmp(&lwsync_fixup_test, + &lwsync_fixup_test_expected_SYNC, size) == 0); + } +} + static int __init test_feature_fixups(void) { printk(KERN_DEBUG "Running feature fixup self-tests ...\n"); @@ -307,6 +342,7 @@ static int __init test_feature_fixups(void) test_alternative_case_with_external_branch(); test_cpu_macros(); test_fw_macros(); + test_lwsync_macros(); return 0; } diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h index ef3a5d156dba..107d9b915e33 100644 --- a/include/asm-powerpc/code-patching.h +++ b/include/asm-powerpc/code-patching.h @@ -12,7 +12,8 @@ #include -#define PPC_NOP_INSTR 0x60000000 +#define PPC_NOP_INSTR 0x60000000 +#define PPC_LWSYNC_INSTR 0x7c2004ac /* Flags for create_branch: * "b" == create_branch(addr, target, 0); diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 4e4491cb9d3b..3171ac904b91 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -156,6 +156,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) #define CPU_FTR_SPE ASM_CONST(0x0000000002000000) #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000) +#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000) /* * Add the 64-bit processor unique features in the top half of the word; @@ -369,43 +370,43 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, CPU_FTR_NODSISRALIGN) #define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \ - CPU_FTR_L2CSR) + CPU_FTR_L2CSR | CPU_FTR_LWSYNC) #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) /* 64-bit CPUs */ -#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) -#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ CPU_FTR_MMCRA | CPU_FTR_CTRL) -#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA) -#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA) -#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ CPU_FTR_PURR) -#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ CPU_FTR_DSCR) -#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ CPU_FTR_DSCR) -#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \ +#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG) -#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \ +#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B) diff --git a/include/asm-powerpc/feature-fixups.h b/include/asm-powerpc/feature-fixups.h index ab30129dced7..a1029967620b 100644 --- a/include/asm-powerpc/feature-fixups.h +++ b/include/asm-powerpc/feature-fixups.h @@ -113,4 +113,14 @@ label##5: \ #endif /* __ASSEMBLY__ */ +/* LWSYNC feature sections */ +#define START_LWSYNC_SECTION(label) label##1: +#define MAKE_LWSYNC_SECTION_ENTRY(label, sect) \ +label##2: \ + .pushsection sect,"a"; \ + .align 2; \ +label##3: \ + .long label##1b-label##3b; \ + .popsection; + #endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */ diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h index 42a1ef590690..45963e80f557 100644 --- a/include/asm-powerpc/synch.h +++ b/include/asm-powerpc/synch.h @@ -3,34 +3,42 @@ #ifdef __KERNEL__ #include +#include -#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC) -#define __SUBARCH_HAS_LWSYNC -#endif +#ifndef __ASSEMBLY__ +extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup; +extern void do_lwsync_fixups(unsigned long value, void *fixup_start, + void *fixup_end); + +static inline void eieio(void) +{ + __asm__ __volatile__ ("eieio" : : : "memory"); +} + +static inline void isync(void) +{ + __asm__ __volatile__ ("isync" : : : "memory"); +} +#endif /* __ASSEMBLY__ */ -#ifdef __SUBARCH_HAS_LWSYNC +#if defined(__powerpc64__) # define LWSYNC lwsync +#elif defined(CONFIG_E500) +# define LWSYNC \ + START_LWSYNC_SECTION(96); \ + sync; \ + MAKE_LWSYNC_SECTION_ENTRY(96, __lwsync_fixup); #else # define LWSYNC sync #endif #ifdef CONFIG_SMP #define ISYNC_ON_SMP "\n\tisync\n" -#define LWSYNC_ON_SMP __stringify(LWSYNC) "\n" +#define LWSYNC_ON_SMP stringify_in_c(LWSYNC) "\n" #else #define ISYNC_ON_SMP #define LWSYNC_ON_SMP #endif -static inline void eieio(void) -{ - __asm__ __volatile__ ("eieio" : : : "memory"); -} - -static inline void isync(void) -{ - __asm__ __volatile__ ("isync" : : : "memory"); -} - #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_SYNCH_H */ -- cgit v1.2.3 From 138fc1ee06e58f12fc2b755e435ce15bb36a0471 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 2 Jul 2008 22:51:37 +1000 Subject: powerpc: Remove old dump_task_* functions Since Roland's ptrace cleanup starting with commit f65255e8d51ecbc6c9eef20d39e0377d19b658ca ("[POWERPC] Use user_regset accessors for FP regs"), the dump_task_* functions are no longer being used. Signed-off-by: Michael Neuling Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/process.c | 83 ------------------------------------------- include/asm-powerpc/elf.h | 20 ----------- 2 files changed, 103 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 1924b57bd241..85e557300d86 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -105,29 +105,6 @@ void enable_kernel_fp(void) } EXPORT_SYMBOL(enable_kernel_fp); -int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpregs) -{ -#ifdef CONFIG_VSX - int i; - elf_fpreg_t *reg; -#endif - - if (!tsk->thread.regs) - return 0; - flush_fp_to_thread(current); - -#ifdef CONFIG_VSX - reg = (elf_fpreg_t *)fpregs; - for (i = 0; i < ELF_NFPREG - 1; i++, reg++) - *reg = tsk->thread.TS_FPR(i); - memcpy(reg, &tsk->thread.fpscr, sizeof(elf_fpreg_t)); -#else - memcpy(fpregs, &tsk->thread.TS_FPR(0), sizeof(*fpregs)); -#endif - - return 1; -} - #ifdef CONFIG_ALTIVEC void enable_kernel_altivec(void) { @@ -161,35 +138,6 @@ void flush_altivec_to_thread(struct task_struct *tsk) preempt_enable(); } } - -int dump_task_altivec(struct task_struct *tsk, elf_vrregset_t *vrregs) -{ - /* ELF_NVRREG includes the VSCR and VRSAVE which we need to save - * separately, see below */ - const int nregs = ELF_NVRREG - 2; - elf_vrreg_t *reg; - u32 *dest; - - if (tsk == current) - flush_altivec_to_thread(tsk); - - reg = (elf_vrreg_t *)vrregs; - - /* copy the 32 vr registers */ - memcpy(reg, &tsk->thread.vr[0], nregs * sizeof(*reg)); - reg += nregs; - - /* copy the vscr */ - memcpy(reg, &tsk->thread.vscr, sizeof(*reg)); - reg++; - - /* vrsave is stored in the high 32bit slot of the final 128bits */ - memset(reg, 0, sizeof(*reg)); - dest = (u32 *)reg; - *dest = tsk->thread.vrsave; - - return 1; -} #endif /* CONFIG_ALTIVEC */ #ifdef CONFIG_VSX @@ -224,29 +172,6 @@ void flush_vsx_to_thread(struct task_struct *tsk) preempt_enable(); } } - -/* - * This dumps the lower half 64bits of the first 32 VSX registers. - * This needs to be called with dump_task_fp and dump_task_altivec to - * get all the VSX state. - */ -int dump_task_vsx(struct task_struct *tsk, elf_vrreg_t *vrregs) -{ - elf_vrreg_t *reg; - double buf[32]; - int i; - - if (tsk == current) - flush_vsx_to_thread(tsk); - - reg = (elf_vrreg_t *)vrregs; - - for (i = 0; i < 32 ; i++) - buf[i] = current->thread.fpr[i][TS_VSRLOWOFFSET]; - memcpy(reg, buf, sizeof(buf)); - - return 1; -} #endif /* CONFIG_VSX */ #ifdef CONFIG_SPE @@ -279,14 +204,6 @@ void flush_spe_to_thread(struct task_struct *tsk) preempt_enable(); } } - -int dump_spe(struct pt_regs *regs, elf_vrregset_t *evrregs) -{ - flush_spe_to_thread(current); - /* We copy u32 evr[32] + u64 acc + u32 spefscr -> 35 */ - memcpy(evrregs, ¤t->thread.evr[0], sizeof(u32) * 35); - return 1; -} #endif /* CONFIG_SPE */ #ifndef CONFIG_SMP diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h index 38a51728406f..89664675b469 100644 --- a/include/asm-powerpc/elf.h +++ b/include/asm-powerpc/elf.h @@ -204,28 +204,8 @@ static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs, } #define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs); -static inline int dump_task_regs(struct task_struct *tsk, - elf_gregset_t *elf_regs) -{ - struct pt_regs *regs = tsk->thread.regs; - if (regs) - ppc_elf_core_copy_regs(*elf_regs, regs); - - return 1; -} -#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs) - -extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); -#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs) - typedef elf_vrregset_t elf_fpxregset_t; -#ifdef CONFIG_ALTIVEC -extern int dump_task_altivec(struct task_struct *, elf_vrregset_t *vrregs); -#define ELF_CORE_COPY_XFPREGS(tsk, regs) dump_task_altivec(tsk, regs) -#define ELF_CORE_XFPREG_TYPE NT_PPC_VMX -#endif - /* ELF_HWCAP yields a mask that user programs can use to figure out what instruction set this cpu supports. This could be done in userspace, but it's not easy, and we've already done it here. */ -- cgit v1.2.3 From 3c3f67eafad12d4ccabe491c6c8a50bf6e75b89a Mon Sep 17 00:00:00 2001 From: Nathan Fontenot Date: Thu, 3 Jul 2008 13:22:39 +1000 Subject: powerpc/pseries: Update the device tree correctly for drconf memory add/remove This updates the device tree manipulation routines so that memory add/remove of lmbs represented under the ibm,dynamic-reconfiguration-memory node of the device tree invokes the hotplug notifier chain. This change is needed because of the change in the way memory is represented under the ibm,dynamic-reconfiguration-memory node. All lmbs are described in the ibm,dynamic-memory property instead of having a separate node for each lmb as in previous device tree layouts. This requires the update_node() routine to check for updates to the ibm,dynamic-memory property and invoke the hotplug notifier chain. This also updates the pseries hotplug notifier to be able to gather information for lmbs represented under the ibm,dynamic-reconfiguration-memory node and have the lmbs added/removed. Signed-off-by: Nathan Fontenot Signed-off-by: Paul Mackerras --- arch/powerpc/platforms/pseries/hotplug-memory.c | 95 ++++++++++++++++++------- arch/powerpc/platforms/pseries/reconfig.c | 36 ++++++++-- include/asm-powerpc/pSeries_reconfig.h | 6 +- 3 files changed, 104 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c index 18a8138ef99f..a1a368dd2d99 100644 --- a/arch/powerpc/platforms/pseries/hotplug-memory.c +++ b/arch/powerpc/platforms/pseries/hotplug-memory.c @@ -15,32 +15,11 @@ #include #include -static int pseries_remove_memory(struct device_node *np) +static int pseries_remove_lmb(unsigned long base, unsigned int lmb_size) { - const char *type; - const unsigned int *regs; - unsigned long base; - unsigned int lmb_size; - u64 start_pfn, start; + unsigned long start, start_pfn; struct zone *zone; - int ret = -EINVAL; - - /* - * Check to see if we are actually removing memory - */ - type = of_get_property(np, "device_type", NULL); - if (type == NULL || strcmp(type, "memory") != 0) - return 0; - - /* - * Find the bae address and size of the lmb - */ - regs = of_get_property(np, "reg", NULL); - if (!regs) - return ret; - - base = *(unsigned long *)regs; - lmb_size = regs[3]; + int ret; start_pfn = base >> PFN_SECTION_SHIFT; zone = page_zone(pfn_to_page(start_pfn)); @@ -71,13 +50,41 @@ static int pseries_remove_memory(struct device_node *np) return ret; } +static int pseries_remove_memory(struct device_node *np) +{ + const char *type; + const unsigned int *regs; + unsigned long base; + unsigned int lmb_size; + int ret = -EINVAL; + + /* + * Check to see if we are actually removing memory + */ + type = of_get_property(np, "device_type", NULL); + if (type == NULL || strcmp(type, "memory") != 0) + return 0; + + /* + * Find the bae address and size of the lmb + */ + regs = of_get_property(np, "reg", NULL); + if (!regs) + return ret; + + base = *(unsigned long *)regs; + lmb_size = regs[3]; + + ret = pseries_remove_lmb(base, lmb_size); + return ret; +} + static int pseries_add_memory(struct device_node *np) { const char *type; const unsigned int *regs; unsigned long base; unsigned int lmb_size; - u64 start_pfn; int ret = -EINVAL; /* @@ -100,8 +107,37 @@ static int pseries_add_memory(struct device_node *np) /* * Update memory region to represent the memory add */ - lmb_add(base, lmb_size); - return 0; + ret = lmb_add(base, lmb_size); + return (ret < 0) ? -EINVAL : 0; +} + +static int pseries_drconf_memory(unsigned long *base, unsigned int action) +{ + struct device_node *np; + const unsigned long *lmb_size; + int rc; + + np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory"); + if (!np) + return -EINVAL; + + lmb_size = of_get_property(np, "ibm,lmb-size", NULL); + if (!lmb_size) { + of_node_put(np); + return -EINVAL; + } + + if (action == PSERIES_DRCONF_MEM_ADD) { + rc = lmb_add(*base, *lmb_size); + rc = (rc < 0) ? -EINVAL : 0; + } else if (action == PSERIES_DRCONF_MEM_REMOVE) { + rc = pseries_remove_lmb(*base, *lmb_size); + } else { + rc = -EINVAL; + } + + of_node_put(np); + return rc; } static int pseries_memory_notifier(struct notifier_block *nb, @@ -118,6 +154,11 @@ static int pseries_memory_notifier(struct notifier_block *nb, if (pseries_remove_memory(node)) err = NOTIFY_BAD; break; + case PSERIES_DRCONF_MEM_ADD: + case PSERIES_DRCONF_MEM_REMOVE: + if (pseries_drconf_memory(node, action)) + err = NOTIFY_BAD; + break; default: err = NOTIFY_DONE; break; diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c index dfa2ebd2deb5..7637bd38c795 100644 --- a/arch/powerpc/platforms/pseries/reconfig.c +++ b/arch/powerpc/platforms/pseries/reconfig.c @@ -422,8 +422,8 @@ static int do_update_property(char *buf, size_t bufsize) { struct device_node *np; unsigned char *value; - char *name, *end; - int length; + char *name, *end, *next_prop; + int rc, length; struct property *newprop, *oldprop; buf = parse_node(buf, bufsize, &np); end = buf + bufsize; @@ -431,7 +431,8 @@ static int do_update_property(char *buf, size_t bufsize) if (!np) return -ENODEV; - if (parse_next_property(buf, end, &name, &length, &value) == NULL) + next_prop = parse_next_property(buf, end, &name, &length, &value); + if (!next_prop) return -EINVAL; newprop = new_property(name, length, value, NULL); @@ -442,7 +443,34 @@ static int do_update_property(char *buf, size_t bufsize) if (!oldprop) return -ENODEV; - return prom_update_property(np, newprop, oldprop); + rc = prom_update_property(np, newprop, oldprop); + if (rc) + return rc; + + /* For memory under the ibm,dynamic-reconfiguration-memory node + * of the device tree, adding and removing memory is just an update + * to the ibm,dynamic-memory property instead of adding/removing a + * memory node in the device tree. For these cases we still need to + * involve the notifier chain. + */ + if (!strcmp(name, "ibm,dynamic-memory")) { + int action; + + next_prop = parse_next_property(next_prop, end, &name, + &length, &value); + if (!next_prop) + return -EINVAL; + + if (!strcmp(name, "add")) + action = PSERIES_DRCONF_MEM_ADD; + else + action = PSERIES_DRCONF_MEM_REMOVE; + + blocking_notifier_call_chain(&pSeries_reconfig_chain, + action, value); + } + + return 0; } /** diff --git a/include/asm-powerpc/pSeries_reconfig.h b/include/asm-powerpc/pSeries_reconfig.h index ea6cfb8efb84..e482e5352e69 100644 --- a/include/asm-powerpc/pSeries_reconfig.h +++ b/include/asm-powerpc/pSeries_reconfig.h @@ -9,8 +9,10 @@ * added or removed on pSeries systems. */ -#define PSERIES_RECONFIG_ADD 0x0001 -#define PSERIES_RECONFIG_REMOVE 0x0002 +#define PSERIES_RECONFIG_ADD 0x0001 +#define PSERIES_RECONFIG_REMOVE 0x0002 +#define PSERIES_DRCONF_MEM_ADD 0x0003 +#define PSERIES_DRCONF_MEM_REMOVE 0x0004 #ifdef CONFIG_PPC_PSERIES extern int pSeries_reconfig_notifier_register(struct notifier_block *); -- cgit v1.2.3 From c6c4f070a61b2b6e5cd317a5fbf25255878688a2 Mon Sep 17 00:00:00 2001 From: Greg KH Date: Thu, 3 Jul 2008 09:49:39 -0700 Subject: PCI: make pci_name use dev_name Also fixes up the sparc code that was assuming this is not a constant. Acked-by: David S. Miller Signed-off-by: Kay Sievers Signed-off-by: Greg Kroah-Hartman Signed-off-by: Jesse Barnes --- arch/sparc64/kernel/pci.c | 2 +- include/linux/pci.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c index 112b09f16f36..d00a3656c287 100644 --- a/arch/sparc64/kernel/pci.c +++ b/arch/sparc64/kernel/pci.c @@ -408,7 +408,7 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, dev->class = class >> 8; dev->revision = class & 0xff; - sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), + sprintf(dev->dev.bus_id, "%04x:%02x:%02x.%d", pci_domain_nr(bus), dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); if (ofpci_verbose) diff --git a/include/linux/pci.h b/include/linux/pci.h index 96ebaa8d80e3..4c80dc3f2990 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -996,9 +996,9 @@ static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) /* If you want to know what to call your pci_dev, ask this function. * Again, it's a wrapper around the generic device. */ -static inline char *pci_name(struct pci_dev *pdev) +static inline const char *pci_name(struct pci_dev *pdev) { - return pdev->dev.bus_id; + return dev_name(&pdev->dev); } -- cgit v1.2.3 From 3737b2b1046900660b42e25c904b85e78139d25b Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 7 Jul 2008 03:30:55 +0200 Subject: ACPI: Introduce acpi_bus_power_manageable function Introduce function acpi_bus_power_manageable() allowing other (dependent) subsystems to check if ACPI is able to power manage given device. This may be useful, for example, for PCI device power management. Signed-off-by: Rafael J. Wysocki Acked-by: Pavel Machek Signed-off-by: Jesse Barnes --- drivers/acpi/bus.c | 11 +++++++++++ include/acpi/acpi_bus.h | 1 + 2 files changed, 12 insertions(+) (limited to 'include') diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index a6dbcf4d9ef5..b9b69d9629b5 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -295,6 +295,17 @@ int acpi_bus_set_power(acpi_handle handle, int state) EXPORT_SYMBOL(acpi_bus_set_power); +bool acpi_bus_power_manageable(acpi_handle handle) +{ + struct acpi_device *device; + int result; + + result = acpi_bus_get_device(handle, &device); + return result ? false : device->flags.power_manageable; +} + +EXPORT_SYMBOL(acpi_bus_power_manageable); + /* -------------------------------------------------------------------------- Event Management -------------------------------------------------------------------------- */ diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index db90a74f8714..0c21ea3bb672 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -335,6 +335,7 @@ void acpi_bus_data_handler(acpi_handle handle, u32 function, void *context); int acpi_bus_get_status(struct acpi_device *device); int acpi_bus_get_power(acpi_handle handle, int *state); int acpi_bus_set_power(acpi_handle handle, int state); +bool acpi_bus_power_manageable(acpi_handle handle); #ifdef CONFIG_ACPI_PROC_EVENT int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data); int acpi_bus_generate_proc_event4(const char *class, const char *bid, u8 type, int data); -- cgit v1.2.3 From 77e766099efc29d8b01db4b8244ff64fa3d3d0ca Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 7 Jul 2008 03:33:34 +0200 Subject: ACPI: Introduce acpi_device_sleep_wake function The currect ACPI code attempts to execute _PSW at three different places and in one of them only it tries to execute _DSW before _PSW, which is inconsistent with the other two cases. Move the execution of _DSW and _PSW into a separate function called acpi_device_sleep_wake() and call it wherever appropriate instead of executing _DSW and/or _PSW directly. Signed-off-by: Rafael J. Wysocki Acked-by: Pavel Machek Signed-off-by: Jesse Barnes --- drivers/acpi/power.c | 118 ++++++++++++++++++++++++++++++-------------- drivers/acpi/scan.c | 42 +++------------- drivers/acpi/sleep/wakeup.c | 2 +- include/acpi/acpi_drivers.h | 4 +- 4 files changed, 92 insertions(+), 74 deletions(-) (limited to 'include') diff --git a/drivers/acpi/power.c b/drivers/acpi/power.c index 81e4f081a4ae..2e959aa1ef0e 100644 --- a/drivers/acpi/power.c +++ b/drivers/acpi/power.c @@ -292,69 +292,115 @@ static int acpi_power_off_device(acpi_handle handle, struct acpi_device *dev) return 0; } +/** + * acpi_device_sleep_wake - execute _DSW (Device Sleep Wake) or (deprecated in + * ACPI 3.0) _PSW (Power State Wake) + * @dev: Device to handle. + * @enable: 0 - disable, 1 - enable the wake capabilities of the device. + * @sleep_state: Target sleep state of the system. + * @dev_state: Target power state of the device. + * + * Execute _DSW (Device Sleep Wake) or (deprecated in ACPI 3.0) _PSW (Power + * State Wake) for the device, if present. On failure reset the device's + * wakeup.flags.valid flag. + * + * RETURN VALUE: + * 0 if either _DSW or _PSW has been successfully executed + * 0 if neither _DSW nor _PSW has been found + * -ENODEV if the execution of either _DSW or _PSW has failed + */ +int acpi_device_sleep_wake(struct acpi_device *dev, + int enable, int sleep_state, int dev_state) +{ + union acpi_object in_arg[3]; + struct acpi_object_list arg_list = { 3, in_arg }; + acpi_status status = AE_OK; + + /* + * Try to execute _DSW first. + * + * Three agruments are needed for the _DSW object: + * Argument 0: enable/disable the wake capabilities + * Argument 1: target system state + * Argument 2: target device state + * When _DSW object is called to disable the wake capabilities, maybe + * the first argument is filled. The values of the other two agruments + * are meaningless. + */ + in_arg[0].type = ACPI_TYPE_INTEGER; + in_arg[0].integer.value = enable; + in_arg[1].type = ACPI_TYPE_INTEGER; + in_arg[1].integer.value = sleep_state; + in_arg[2].type = ACPI_TYPE_INTEGER; + in_arg[2].integer.value = dev_state; + status = acpi_evaluate_object(dev->handle, "_DSW", &arg_list, NULL); + if (ACPI_SUCCESS(status)) { + return 0; + } else if (status != AE_NOT_FOUND) { + printk(KERN_ERR PREFIX "_DSW execution failed\n"); + dev->wakeup.flags.valid = 0; + return -ENODEV; + } + + /* Execute _PSW */ + arg_list.count = 1; + in_arg[0].integer.value = enable; + status = acpi_evaluate_object(dev->handle, "_PSW", &arg_list, NULL); + if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) { + printk(KERN_ERR PREFIX "_PSW execution failed\n"); + dev->wakeup.flags.valid = 0; + return -ENODEV; + } + + return 0; +} + /* * Prepare a wakeup device, two steps (Ref ACPI 2.0:P229): * 1. Power on the power resources required for the wakeup device - * 2. Enable _PSW (power state wake) for the device if present + * 2. Execute _DSW (Device Sleep Wake) or (deprecated in ACPI 3.0) _PSW (Power + * State Wake) for the device, if present */ -int acpi_enable_wakeup_device_power(struct acpi_device *dev) +int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state) { - union acpi_object arg = { ACPI_TYPE_INTEGER }; - struct acpi_object_list arg_list = { 1, &arg }; - acpi_status status = AE_OK; int i; - int ret = 0; if (!dev || !dev->wakeup.flags.valid) - return -1; + return -EINVAL; - arg.integer.value = 1; /* Open power resource */ for (i = 0; i < dev->wakeup.resources.count; i++) { - ret = acpi_power_on(dev->wakeup.resources.handles[i], dev); + int ret = acpi_power_on(dev->wakeup.resources.handles[i], dev); if (ret) { printk(KERN_ERR PREFIX "Transition power state\n"); dev->wakeup.flags.valid = 0; - return -1; + return -ENODEV; } } - /* Execute PSW */ - status = acpi_evaluate_object(dev->handle, "_PSW", &arg_list, NULL); - if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) { - printk(KERN_ERR PREFIX "Evaluate _PSW\n"); - dev->wakeup.flags.valid = 0; - ret = -1; - } - - return ret; + /* + * Passing 3 as the third argument below means the device may be placed + * in arbitrary power state afterwards. + */ + return acpi_device_sleep_wake(dev, 1, sleep_state, 3); } /* * Shutdown a wakeup device, counterpart of above method - * 1. Disable _PSW (power state wake) + * 1. Execute _DSW (Device Sleep Wake) or (deprecated in ACPI 3.0) _PSW (Power + * State Wake) for the device, if present * 2. Shutdown down the power resources */ int acpi_disable_wakeup_device_power(struct acpi_device *dev) { - union acpi_object arg = { ACPI_TYPE_INTEGER }; - struct acpi_object_list arg_list = { 1, &arg }; - acpi_status status = AE_OK; - int i; - int ret = 0; - + int i, ret; if (!dev || !dev->wakeup.flags.valid) - return -1; + return -EINVAL; - arg.integer.value = 0; - /* Execute PSW */ - status = acpi_evaluate_object(dev->handle, "_PSW", &arg_list, NULL); - if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) { - printk(KERN_ERR PREFIX "Evaluate _PSW\n"); - dev->wakeup.flags.valid = 0; - return -1; - } + ret = acpi_device_sleep_wake(dev, 0, 0, 0); + if (ret) + return ret; /* Close power resource */ for (i = 0; i < dev->wakeup.resources.count; i++) { @@ -362,7 +408,7 @@ int acpi_disable_wakeup_device_power(struct acpi_device *dev) if (ret) { printk(KERN_ERR PREFIX "Transition power state\n"); dev->wakeup.flags.valid = 0; - return -1; + return -ENODEV; } } diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 6d85289f1c12..f276890cfde7 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -691,9 +691,7 @@ static int acpi_bus_get_wakeup_device_flags(struct acpi_device *device) acpi_status status = 0; struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; union acpi_object *package = NULL; - union acpi_object in_arg[3]; - struct acpi_object_list arg_list = { 3, in_arg }; - acpi_status psw_status = AE_OK; + int psw_error; struct acpi_device_id button_device_ids[] = { {"PNP0C0D", 0}, @@ -725,39 +723,11 @@ static int acpi_bus_get_wakeup_device_flags(struct acpi_device *device) * So it is necessary to call _DSW object first. Only when it is not * present will the _PSW object used. */ - /* - * Three agruments are needed for the _DSW object. - * Argument 0: enable/disable the wake capabilities - * When _DSW object is called to disable the wake capabilities, maybe - * the first argument is filled. The value of the other two agruments - * is meaningless. - */ - in_arg[0].type = ACPI_TYPE_INTEGER; - in_arg[0].integer.value = 0; - in_arg[1].type = ACPI_TYPE_INTEGER; - in_arg[1].integer.value = 0; - in_arg[2].type = ACPI_TYPE_INTEGER; - in_arg[2].integer.value = 0; - psw_status = acpi_evaluate_object(device->handle, "_DSW", - &arg_list, NULL); - if (ACPI_FAILURE(psw_status) && (psw_status != AE_NOT_FOUND)) - ACPI_DEBUG_PRINT((ACPI_DB_INFO, "error in evaluate _DSW\n")); - /* - * When the _DSW object is not present, OSPM will call _PSW object. - */ - if (psw_status == AE_NOT_FOUND) { - /* - * Only one agruments is required for the _PSW object. - * agrument 0: enable/disable the wake capabilities - */ - arg_list.count = 1; - in_arg[0].integer.value = 0; - psw_status = acpi_evaluate_object(device->handle, "_PSW", - &arg_list, NULL); - if (ACPI_FAILURE(psw_status) && (psw_status != AE_NOT_FOUND)) - ACPI_DEBUG_PRINT((ACPI_DB_INFO, "error in " - "evaluate _PSW\n")); - } + psw_error = acpi_device_sleep_wake(device, 0, 0, 0); + if (psw_error) + ACPI_DEBUG_PRINT((ACPI_DB_INFO, + "error in _DSW or _PSW evaluation\n")); + /* Power button, Lid switch always enable wakeup */ if (!acpi_match_device_ids(device, button_device_ids)) device->wakeup.flags.run_wake = 1; diff --git a/drivers/acpi/sleep/wakeup.c b/drivers/acpi/sleep/wakeup.c index ed8e41becf0c..7422a2213944 100644 --- a/drivers/acpi/sleep/wakeup.c +++ b/drivers/acpi/sleep/wakeup.c @@ -42,7 +42,7 @@ void acpi_enable_wakeup_device_prep(u8 sleep_state) continue; spin_unlock(&acpi_device_lock); - acpi_enable_wakeup_device_power(dev); + acpi_enable_wakeup_device_power(dev, sleep_state); spin_lock(&acpi_device_lock); } spin_unlock(&acpi_device_lock); diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h index 9757a040a505..e5f38e5ce86f 100644 --- a/include/acpi/acpi_drivers.h +++ b/include/acpi/acpi_drivers.h @@ -87,7 +87,9 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_device *device, int domain, -------------------------------------------------------------------------- */ #ifdef CONFIG_ACPI_POWER -int acpi_enable_wakeup_device_power(struct acpi_device *dev); +int acpi_device_sleep_wake(struct acpi_device *dev, + int enable, int sleep_state, int dev_state); +int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state); int acpi_disable_wakeup_device_power(struct acpi_device *dev); int acpi_power_get_inferred_state(struct acpi_device *device); int acpi_power_transition(struct acpi_device *device, int state); -- cgit v1.2.3 From 0af4b8c4fb31193dc666f4893107a18fef82baab Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 7 Jul 2008 03:34:11 +0200 Subject: ACPI: Introduce new device wakeup flag 'prepared' Introduce additional flag 'prepared' in struct acpi_device_wakeup_flags and use it to prevent devices from being enable/disabled do wake up the system multiple times in a row (this does not happen currently, but will be possible after some of the following patches). Signed-off-by: Rafael J. Wysocki Signed-off-by: Jesse Barnes --- drivers/acpi/power.c | 24 ++++++++++++++++++++++-- include/acpi/acpi_bus.h | 1 + 2 files changed, 23 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/acpi/power.c b/drivers/acpi/power.c index 2e959aa1ef0e..4ab21cb1c8c7 100644 --- a/drivers/acpi/power.c +++ b/drivers/acpi/power.c @@ -363,11 +363,18 @@ int acpi_device_sleep_wake(struct acpi_device *dev, */ int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state) { - int i; + int i, err; if (!dev || !dev->wakeup.flags.valid) return -EINVAL; + /* + * Do not execute the code below twice in a row without calling + * acpi_disable_wakeup_device_power() in between for the same device + */ + if (dev->wakeup.flags.prepared) + return 0; + /* Open power resource */ for (i = 0; i < dev->wakeup.resources.count; i++) { int ret = acpi_power_on(dev->wakeup.resources.handles[i], dev); @@ -382,7 +389,11 @@ int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state) * Passing 3 as the third argument below means the device may be placed * in arbitrary power state afterwards. */ - return acpi_device_sleep_wake(dev, 1, sleep_state, 3); + err = acpi_device_sleep_wake(dev, 1, sleep_state, 3); + if (!err) + dev->wakeup.flags.prepared = 1; + + return err; } /* @@ -398,6 +409,15 @@ int acpi_disable_wakeup_device_power(struct acpi_device *dev) if (!dev || !dev->wakeup.flags.valid) return -EINVAL; + /* + * Do not execute the code below twice in a row without calling + * acpi_enable_wakeup_device_power() in between for the same device + */ + if (!dev->wakeup.flags.prepared) + return 0; + + dev->wakeup.flags.prepared = 0; + ret = acpi_device_sleep_wake(dev, 0, 0, 0); if (ret) return ret; diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 0c21ea3bb672..071daf8db600 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -259,6 +259,7 @@ struct acpi_device_perf { /* Wakeup Management */ struct acpi_device_wakeup_flags { u8 valid:1; /* Can successfully enable wakeup? */ + u8 prepared:1; /* Has the wake-up capability been enabled? */ u8 run_wake:1; /* Run-Wake GPE devices */ }; -- cgit v1.2.3 From eb9d0fe40e313c0a74115ef456a2e43a6c8da72f Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 7 Jul 2008 03:34:48 +0200 Subject: PCI ACPI: Rework PCI handling of wake-up * Introduce function acpi_pm_device_sleep_wake() for enabling and disabling the system wake-up capability of devices that are power manageable by ACPI. * Introduce function acpi_bus_can_wakeup() allowing other (dependent) subsystems to check if ACPI is able to enable the system wake-up capability of given device. * Introduce callback .sleep_wake() in struct pci_platform_pm_ops and for the ACPI PCI 'driver' make it use acpi_pm_device_sleep_wake(). * Introduce callback .can_wakeup() in struct pci_platform_pm_ops and for the ACPI 'driver' make it use acpi_bus_can_wakeup(). * Move the PME# handlig code out of pci_enable_wake() and split it into two functions, pci_pme_capable() and pci_pme_active(), allowing the caller to check if given device is capable of generating PME# from given power state and to enable/disable the device's PME# functionality, respectively. * Modify pci_enable_wake() to use the new ACPI callbacks and the new PME#-related functions. * Drop the generic .platform_enable_wakeup() callback that is not used any more. * Introduce device_set_wakeup_capable() that will set the power.can_wakeup flag of given device. * Rework PCI device PM initialization so that, if given device is capable of generating wake-up events, either natively through the PME# mechanism, or with the help of the platform, its power.can_wakeup flag is set and its power.should_wakeup flag is unset as appropriate. * Make ACPI set the power.can_wakeup flag for devices found to be wake-up capable by it. * Make the ACPI wake-up code enable/disable GPEs for devices that have the wakeup.flags.prepared flag set (which means that their wake-up power has been enabled). Signed-off-by: Rafael J. Wysocki Signed-off-by: Jesse Barnes --- drivers/acpi/bus.c | 11 +++ drivers/acpi/glue.c | 2 + drivers/acpi/sleep/main.c | 25 +++++++ drivers/acpi/sleep/wakeup.c | 11 +-- drivers/base/power/sysfs.c | 3 - drivers/pci/pci-acpi.c | 20 ++++++ drivers/pci/pci.c | 169 ++++++++++++++++++++++++++++++++------------ drivers/pci/pci.h | 8 +++ drivers/pci/probe.c | 47 +----------- include/acpi/acpi_bus.h | 2 + include/linux/pm_wakeup.h | 26 ++----- 11 files changed, 208 insertions(+), 116 deletions(-) (limited to 'include') diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index b9b69d9629b5..fc1110d6a078 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -306,6 +306,17 @@ bool acpi_bus_power_manageable(acpi_handle handle) EXPORT_SYMBOL(acpi_bus_power_manageable); +bool acpi_bus_can_wakeup(acpi_handle handle) +{ + struct acpi_device *device; + int result; + + result = acpi_bus_get_device(handle, &device); + return result ? false : device->wakeup.flags.valid; +} + +EXPORT_SYMBOL(acpi_bus_can_wakeup); + /* -------------------------------------------------------------------------- Event Management -------------------------------------------------------------------------- */ diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c index 06f8634fe58b..87c5d456e180 100644 --- a/drivers/acpi/glue.c +++ b/drivers/acpi/glue.c @@ -166,6 +166,8 @@ static int acpi_bind_one(struct device *dev, acpi_handle handle) "firmware_node"); ret = sysfs_create_link(&acpi_dev->dev.kobj, &dev->kobj, "physical_node"); + if (acpi_dev->wakeup.flags.valid) + device_set_wakeup_capable(dev, true); } return 0; diff --git a/drivers/acpi/sleep/main.c b/drivers/acpi/sleep/main.c index 4addf8ad50ae..af7f4663deaa 100644 --- a/drivers/acpi/sleep/main.c +++ b/drivers/acpi/sleep/main.c @@ -468,6 +468,31 @@ int acpi_pm_device_sleep_state(struct device *dev, int *d_min_p) *d_min_p = d_min; return d_max; } + +/** + * acpi_pm_device_sleep_wake - enable or disable the system wake-up + * capability of given device + * @dev: device to handle + * @enable: 'true' - enable, 'false' - disable the wake-up capability + */ +int acpi_pm_device_sleep_wake(struct device *dev, bool enable) +{ + acpi_handle handle; + struct acpi_device *adev; + + if (!device_may_wakeup(dev)) + return -EINVAL; + + handle = DEVICE_ACPI_HANDLE(dev); + if (!handle || ACPI_FAILURE(acpi_bus_get_device(handle, &adev))) { + printk(KERN_DEBUG "ACPI handle has no context!\n"); + return -ENODEV; + } + + return enable ? + acpi_enable_wakeup_device_power(adev, acpi_target_sleep_state) : + acpi_disable_wakeup_device_power(adev); +} #endif static void acpi_power_off_prepare(void) diff --git a/drivers/acpi/sleep/wakeup.c b/drivers/acpi/sleep/wakeup.c index 7422a2213944..38655eb132dc 100644 --- a/drivers/acpi/sleep/wakeup.c +++ b/drivers/acpi/sleep/wakeup.c @@ -66,13 +66,15 @@ void acpi_enable_wakeup_device(u8 sleep_state) list_for_each_safe(node, next, &acpi_wakeup_device_list) { struct acpi_device *dev = container_of(node, struct acpi_device, wakeup_list); + if (!dev->wakeup.flags.valid) continue; + /* If users want to disable run-wake GPE, * we only disable it for wake and leave it for runtime */ - if (!dev->wakeup.state.enabled || - sleep_state > (u32) dev->wakeup.sleep_state) { + if ((!dev->wakeup.state.enabled && !dev->wakeup.flags.prepared) + || sleep_state > (u32) dev->wakeup.sleep_state) { if (dev->wakeup.flags.run_wake) { spin_unlock(&acpi_device_lock); /* set_gpe_type will disable GPE, leave it like that */ @@ -110,8 +112,9 @@ void acpi_disable_wakeup_device(u8 sleep_state) if (!dev->wakeup.flags.valid) continue; - if (!dev->wakeup.state.enabled || - sleep_state > (u32) dev->wakeup.sleep_state) { + + if ((!dev->wakeup.state.enabled && !dev->wakeup.flags.prepared) + || sleep_state > (u32) dev->wakeup.sleep_state) { if (dev->wakeup.flags.run_wake) { spin_unlock(&acpi_device_lock); acpi_set_gpe_type(dev->wakeup.gpe_device, diff --git a/drivers/base/power/sysfs.c b/drivers/base/power/sysfs.c index d11f74b038db..596aeecfdffe 100644 --- a/drivers/base/power/sysfs.c +++ b/drivers/base/power/sysfs.c @@ -6,9 +6,6 @@ #include #include "power.h" -int (*platform_enable_wakeup)(struct device *dev, int is_on); - - /* * wakeup - Report/change current wakeup option for device * diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 6bc0d8c870af..7764768b6a0e 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -299,10 +299,30 @@ static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) return error; } +static bool acpi_pci_can_wakeup(struct pci_dev *dev) +{ + acpi_handle handle = DEVICE_ACPI_HANDLE(&dev->dev); + + return handle ? acpi_bus_can_wakeup(handle) : false; +} + +static int acpi_pci_sleep_wake(struct pci_dev *dev, bool enable) +{ + int error = acpi_pm_device_sleep_wake(&dev->dev, enable); + + if (!error) + dev_printk(KERN_INFO, &dev->dev, + "wake-up capability %s by ACPI\n", + enable ? "enabled" : "disabled"); + return error; +} + static struct pci_platform_pm_ops acpi_pci_platform_pm = { .is_manageable = acpi_pci_power_manageable, .set_state = acpi_pci_set_power_state, .choose_state = acpi_pci_choose_state, + .can_wakeup = acpi_pci_can_wakeup, + .sleep_wake = acpi_pci_sleep_wake, }; /* ACPI bus type */ diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 20e28077b96d..a6b1b6f96abc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -380,7 +380,8 @@ static struct pci_platform_pm_ops *pci_platform_pm; int pci_set_platform_pm(struct pci_platform_pm_ops *ops) { - if (!ops->is_manageable || !ops->set_state || !ops->choose_state) + if (!ops->is_manageable || !ops->set_state || !ops->choose_state + || !ops->sleep_wake || !ops->can_wakeup) return -EINVAL; pci_platform_pm = ops; return 0; @@ -403,6 +404,17 @@ static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; } +static inline bool platform_pci_can_wakeup(struct pci_dev *dev) +{ + return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; +} + +static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) +{ + return pci_platform_pm ? + pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; +} + /** * pci_raw_set_power_state - Use PCI PM registers to set the power state of * given PCI device @@ -1035,6 +1047,56 @@ int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) return pcibios_set_pcie_reset_state(dev, state); } +/** + * pci_pme_capable - check the capability of PCI device to generate PME# + * @dev: PCI device to handle. + * @pm: PCI PM capability offset of the device. + * @state: PCI state from which device will issue PME#. + */ +static bool pci_pme_capable(struct pci_dev *dev, int pm, pci_power_t state) +{ + u16 pmc; + + if (!pm) + return false; + + /* Check device's ability to generate PME# from given state */ + pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); + + pmc &= PCI_PM_CAP_PME_MASK; + pmc >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ + + return !!(pmc & (1 << state)); +} + +/** + * pci_pme_active - enable or disable PCI device's PME# function + * @dev: PCI device to handle. + * @pm: PCI PM capability offset of the device. + * @enable: 'true' to enable PME# generation; 'false' to disable it. + * + * The caller must verify that the device is capable of generating PME# before + * calling this function with @enable equal to 'true'. + */ +static void pci_pme_active(struct pci_dev *dev, int pm, bool enable) +{ + u16 pmcsr; + + if (!pm) + return; + + pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); + /* Clear PME_Status by writing 1 to it and enable PME# */ + pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; + if (!enable) + pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; + + pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); + + dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", + enable ? "enabled" : "disabled"); +} + /** * pci_enable_wake - enable PCI device as wakeup event source * @dev: PCI device affected @@ -1046,66 +1108,83 @@ int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) * called automatically by this routine. * * Devices with legacy power management (no standard PCI PM capabilities) - * always require such platform hooks. Depending on the platform, devices - * supporting the standard PCI PME# signal may require such platform hooks; - * they always update bits in config space to allow PME# generation. + * always require such platform hooks. * - * -EIO is returned if the device can't ever be a wakeup event source. - * -EINVAL is returned if the device can't generate wakeup events from - * the specified PCI state. Returns zero if the operation is successful. + * RETURN VALUE: + * 0 is returned on success + * -EINVAL is returned if device is not supposed to wake up the system + * Error code depending on the platform is returned if both the platform and + * the native mechanism fail to enable the generation of wake-up events */ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { int pm; - int status; - u16 value; - - /* Note that drivers should verify device_may_wakeup(&dev->dev) - * before calling this function. Platform code should report - * errors when drivers try to enable wakeup on devices that - * can't issue wakeups, or on which wakeups were disabled by - * userspace updating the /sys/devices.../power/wakeup file. - */ + int error = 0; + bool pme_done = false; - status = call_platform_enable_wakeup(&dev->dev, enable); - - /* find PCI PM capability in list */ - pm = pci_find_capability(dev, PCI_CAP_ID_PM); + if (!device_may_wakeup(&dev->dev)) + return -EINVAL; - /* If device doesn't support PM Capabilities, but caller wants to - * disable wake events, it's a NOP. Otherwise fail unless the - * platform hooks handled this legacy device already. + /* + * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don + * Anderson we should be doing PME# wake enable followed by ACPI wake + * enable. To disable wake-up we call the platform first, for symmetry. */ - if (!pm) - return enable ? status : 0; - /* Check device's ability to generate PME# */ - pci_read_config_word(dev,pm+PCI_PM_PMC,&value); + if (!enable && platform_pci_can_wakeup(dev)) + error = platform_pci_sleep_wake(dev, false); - value &= PCI_PM_CAP_PME_MASK; - value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ - - /* Check if it can generate PME# from requested state. */ - if (!value || !(value & (1 << state))) { - /* if it can't, revert what the platform hook changed, - * always reporting the base "EINVAL, can't PME#" error - */ - if (enable) - call_platform_enable_wakeup(&dev->dev, 0); - return enable ? -EINVAL : 0; + pm = pci_find_capability(dev, PCI_CAP_ID_PM); + if (!enable || pci_pme_capable(dev, pm, state)) { + pci_pme_active(dev, pm, enable); + pme_done = true; } - pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); + if (enable && platform_pci_can_wakeup(dev)) + error = platform_pci_sleep_wake(dev, true); - /* Clear PME_Status by writing 1 to it and enable PME# */ - value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; + return pme_done ? 0 : error; +} - if (!enable) - value &= ~PCI_PM_CTRL_PME_ENABLE; +/** + * pci_pm_init - Initialize PM functions of given PCI device + * @dev: PCI device to handle. + */ +void pci_pm_init(struct pci_dev *dev) +{ + int pm; + u16 pmc; - pci_write_config_word(dev, pm + PCI_PM_CTRL, value); + /* find PCI PM capability in list */ + pm = pci_find_capability(dev, PCI_CAP_ID_PM); + if (!pm) + return; + /* Check device's ability to generate PME# */ + pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); - return 0; + if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { + dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", + pmc & PCI_PM_CAP_VER_MASK); + return; + } + + if (pmc & PCI_PM_CAP_PME_MASK) { + dev_printk(KERN_INFO, &dev->dev, + "PME# supported from%s%s%s%s%s\n", + (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", + (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", + (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", + (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", + (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); + /* + * Make device's PM flags reflect the wake-up capability, but + * let the user space enable it to wake up the system as needed. + */ + device_set_wakeup_capable(&dev->dev, true); + device_set_wakeup_enable(&dev->dev, false); + /* Disable the PME# generation functionality */ + pci_pme_active(dev, pm, false); + } } int diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0cd2e719933b..b08dfc9746af 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -17,6 +17,11 @@ extern void pci_cleanup_rom(struct pci_dev *dev); * platform; to be used during system-wide transitions from a * sleeping state to the working state and vice versa * + * @can_wakeup - returns 'true' if given device is capable of waking up the + * system from a sleeping state + * + * @sleep_wake - enables/disables the system wake up capability of given device + * * If given platform is generally capable of power managing PCI devices, all of * these callbacks are mandatory. */ @@ -24,9 +29,12 @@ struct pci_platform_pm_ops { bool (*is_manageable)(struct pci_dev *dev); int (*set_state)(struct pci_dev *dev, pci_power_t state); pci_power_t (*choose_state)(struct pci_dev *dev); + bool (*can_wakeup)(struct pci_dev *dev); + int (*sleep_wake)(struct pci_dev *dev, bool enable); }; extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops); +extern void pci_pm_init(struct pci_dev *dev); extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2f0ae70710d6..b1724cf31b66 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -860,49 +860,6 @@ int pci_cfg_space_size_ext(struct pci_dev *dev) return PCI_CFG_SPACE_SIZE; } -/** - * pci_disable_pme - Disable the PME function of PCI device - * @dev: PCI device affected - * -EINVAL is returned if PCI device doesn't support PME. - * Zero is returned if the PME is supported and can be disabled. - */ -static int pci_disable_pme(struct pci_dev *dev) -{ - int pm; - u16 value; - - /* find PCI PM capability in list */ - pm = pci_find_capability(dev, PCI_CAP_ID_PM); - - /* If device doesn't support PM Capabilities, it means that PME is - * not supported. - */ - if (!pm) - return -EINVAL; - /* Check device's ability to generate PME# */ - pci_read_config_word(dev, pm + PCI_PM_PMC, &value); - - value &= PCI_PM_CAP_PME_MASK; - /* Check if it can generate PME# */ - if (!value) { - /* - * If it is zero, it means that PME is still unsupported - * although there exists the PM capability. - */ - return -EINVAL; - } - - pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); - - /* Clear PME_Status by writing 1 to it */ - value |= PCI_PM_CTRL_PME_STATUS ; - /* Disable PME enable bit */ - value &= ~PCI_PM_CTRL_PME_ENABLE; - pci_write_config_word(dev, pm + PCI_PM_CTRL, value); - - return 0; -} - int pci_cfg_space_size(struct pci_dev *dev) { int pos; @@ -1010,7 +967,6 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) } pci_vpd_pci22_init(dev); - pci_disable_pme(dev); return dev; } @@ -1031,6 +987,9 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) /* Fix up broken headers */ pci_fixup_device(pci_fixup_header, dev); + /* Initialize power management of the device */ + pci_pm_init(dev); + /* * Add the device to our list of discovered devices * and the bus list for fixup functions, etc. diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 071daf8db600..7ab5a611e43f 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -337,6 +337,7 @@ int acpi_bus_get_status(struct acpi_device *device); int acpi_bus_get_power(acpi_handle handle, int *state); int acpi_bus_set_power(acpi_handle handle, int state); bool acpi_bus_power_manageable(acpi_handle handle); +bool acpi_bus_can_wakeup(acpi_handle handle); #ifdef CONFIG_ACPI_PROC_EVENT int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data); int acpi_bus_generate_proc_event4(const char *class, const char *bid, u8 type, int data); @@ -379,6 +380,7 @@ acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int); #ifdef CONFIG_PM_SLEEP int acpi_pm_device_sleep_state(struct device *, int *); +int acpi_pm_device_sleep_wake(struct device *, bool); #else /* !CONFIG_PM_SLEEP */ static inline int acpi_pm_device_sleep_state(struct device *d, int *p) { diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h index f0d0b2cb8d20..3af0c8d05cdc 100644 --- a/include/linux/pm_wakeup.h +++ b/include/linux/pm_wakeup.h @@ -35,6 +35,11 @@ static inline void device_init_wakeup(struct device *dev, int val) dev->power.can_wakeup = dev->power.should_wakeup = !!val; } +static inline void device_set_wakeup_capable(struct device *dev, int val) +{ + dev->power.can_wakeup = !!val; +} + static inline int device_can_wakeup(struct device *dev) { return dev->power.can_wakeup; @@ -47,21 +52,7 @@ static inline void device_set_wakeup_enable(struct device *dev, int val) static inline int device_may_wakeup(struct device *dev) { - return dev->power.can_wakeup & dev->power.should_wakeup; -} - -/* - * Platform hook to activate device wakeup capability, if that's not already - * handled by enable_irq_wake() etc. - * Returns zero on success, else negative errno - */ -extern int (*platform_enable_wakeup)(struct device *dev, int is_on); - -static inline int call_platform_enable_wakeup(struct device *dev, int is_on) -{ - if (platform_enable_wakeup) - return (*platform_enable_wakeup)(dev, is_on); - return 0; + return dev->power.can_wakeup && dev->power.should_wakeup; } #else /* !CONFIG_PM */ @@ -80,11 +71,6 @@ static inline int device_can_wakeup(struct device *dev) #define device_set_wakeup_enable(dev, val) do {} while (0) #define device_may_wakeup(dev) 0 -static inline int call_platform_enable_wakeup(struct device *dev, int is_on) -{ - return 0; -} - #endif /* !CONFIG_PM */ #endif /* _LINUX_PM_WAKEUP_H */ -- cgit v1.2.3 From 404cc2d8ce41ed4031958fba8e633767e8a2e028 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 7 Jul 2008 03:35:26 +0200 Subject: PCI PM: Introduce pci_prepare_to_sleep and pci_back_from_sleep Introduce functions pci_prepare_to_sleep() and pci_back_from_sleep(), to be used by the PCI drivers that want to place their devices into the lowest power state appropiate for them (PCI_D3hot, if the device is not supposed to wake up the system, or the deepest state from which the wake-up is possible, otherwise) while the system is being prepared to go into a sleeping state and to put them back into D0 during the subsequent transition to the working state. Signed-off-by: Rafael J. Wysocki Signed-off-by: Jesse Barnes --- drivers/pci/pci.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 85 insertions(+) (limited to 'include') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index a6b1b6f96abc..1b0ec45e9934 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1146,6 +1146,87 @@ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) return pme_done ? 0 : error; } +/** + * pci_prepare_to_sleep - prepare PCI device for system-wide transition into + * a sleep state + * @dev: Device to handle. + * + * Choose the power state appropriate for the device depending on whether + * it can wake up the system and/or is power manageable by the platform + * (PCI_D3hot is the default) and put the device into that state. + */ +int pci_prepare_to_sleep(struct pci_dev *dev) +{ + pci_power_t target_state = PCI_D3hot; + int pm = pci_find_capability(dev, PCI_CAP_ID_PM); + int error; + + if (platform_pci_power_manageable(dev)) { + /* + * Call the platform to choose the target state of the device + * and enable wake-up from this state if supported. + */ + pci_power_t state = platform_pci_choose_state(dev); + + switch (state) { + case PCI_POWER_ERROR: + case PCI_UNKNOWN: + break; + case PCI_D1: + case PCI_D2: + if (pci_no_d1d2(dev)) + break; + default: + target_state = state; + pci_enable_wake(dev, target_state, true); + } + } else if (device_may_wakeup(&dev->dev)) { + /* + * Find the deepest state from which the device can generate + * wake-up events, make it the target state and enable device + * to generate PME#. + */ + u16 pmc; + + if (!pm) + return -EIO; + + pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); + if (pmc & PCI_PM_CAP_PME_MASK) { + if (!(pmc & PCI_PM_CAP_PME_D3)) { + /* Device cannot generate PME# from D3_hot */ + if (pmc & PCI_PM_CAP_PME_D2) + target_state = PCI_D2; + else if (pmc & PCI_PM_CAP_PME_D1) + target_state = PCI_D1; + else + target_state = PCI_D0; + } + pci_pme_active(dev, pm, true); + } + } + + error = pci_set_power_state(dev, target_state); + + if (error) + pci_enable_wake(dev, target_state, false); + + return error; +} + +/** + * pci_back_from_sleep - turn PCI device on during system-wide transition into + * the working state a sleep state + * @dev: Device to handle. + * + * Disable device's sytem wake-up capability and put it into D0. + */ +int pci_back_from_sleep(struct pci_dev *dev) +{ + pci_enable_wake(dev, PCI_D0, false); + return pci_set_power_state(dev, PCI_D0); +} + /** * pci_pm_init - Initialize PM functions of given PCI device * @dev: PCI device to handle. @@ -1853,5 +1934,7 @@ EXPORT_SYMBOL(pci_set_power_state); EXPORT_SYMBOL(pci_save_state); EXPORT_SYMBOL(pci_restore_state); EXPORT_SYMBOL(pci_enable_wake); +EXPORT_SYMBOL(pci_prepare_to_sleep); +EXPORT_SYMBOL(pci_back_from_sleep); EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); diff --git a/include/linux/pci.h b/include/linux/pci.h index 4c80dc3f2990..52ac06dcce98 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -632,6 +632,8 @@ int pci_restore_state(struct pci_dev *dev); int pci_set_power_state(struct pci_dev *dev, pci_power_t state); pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); +int pci_prepare_to_sleep(struct pci_dev *dev); +int pci_back_from_sleep(struct pci_dev *dev); /* Functions for PCI Hotplug drivers to use */ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); -- cgit v1.2.3 From 337001b6c42938f49a880b1b8306c3ed771a7e61 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 7 Jul 2008 03:36:24 +0200 Subject: PCI: Simplify PCI device PM code If the offset of PCI device's PM capability in its configuration space, the mask of states that the device supports PME# from and the D1 and D2 support bits are cached in the corresponding struct pci_dev, the PCI device PM code can be simplified quite a bit. Signed-off-by: Rafael J. Wysocki Signed-off-by: Jesse Barnes --- drivers/pci/pci.c | 118 +++++++++++++++++++++-------------------------- include/linux/pci.h | 8 +++- include/linux/pci_regs.h | 1 + 3 files changed, 60 insertions(+), 67 deletions(-) (limited to 'include') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1b0ec45e9934..e632a58ba5d0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -419,7 +419,6 @@ static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) * pci_raw_set_power_state - Use PCI PM registers to set the power state of * given PCI device * @dev: PCI device to handle. - * @pm: PCI PM capability offset of the device. * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. * * RETURN VALUE: @@ -430,12 +429,12 @@ static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) * 0 if device's power state has been successfully changed. */ static int -pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state) +pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) { - u16 pmcsr, pmc; + u16 pmcsr; bool need_restore = false; - if (!pm) + if (!dev->pm_cap) return -EIO; if (state < PCI_D0 || state > PCI_D3hot) @@ -455,20 +454,12 @@ pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state) return -EINVAL; } - pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); - - if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { - dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", - pmc & PCI_PM_CAP_VER_MASK); - return -EIO; - } - /* check if this device supports the desired state */ - if ((state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) - || (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))) + if ((state == PCI_D1 && !dev->d1_support) + || (state == PCI_D2 && !dev->d2_support)) return -EIO; - pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); /* If we're (effectively) in D3, force entire word to 0. * This doesn't affect PME_Status, disables PME_En, and @@ -492,7 +483,7 @@ pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state) } /* enter specified state */ - pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); + pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); /* Mandatory power management transition delays */ /* see PCI PM 1.1 5.6.1 table 18 */ @@ -528,14 +519,13 @@ pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state) * pci_update_current_state - Read PCI power state of given device from its * PCI PM registers and cache it * @dev: PCI device to handle. - * @pm: PCI PM capability offset of the device. */ -static void pci_update_current_state(struct pci_dev *dev, int pm) +static void pci_update_current_state(struct pci_dev *dev) { - if (pm) { + if (dev->pm_cap) { u16 pmcsr; - pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); } } @@ -557,7 +547,7 @@ static void pci_update_current_state(struct pci_dev *dev, int pm) */ int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { - int pm, error; + int error; /* bound the state we're entering */ if (state > PCI_D3hot) @@ -572,9 +562,6 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state) */ return 0; - /* Find PCI PM capability in the list */ - pm = pci_find_capability(dev, PCI_CAP_ID_PM); - if (state == PCI_D0 && platform_pci_power_manageable(dev)) { /* * Allow the platform to change the state, for example via ACPI @@ -582,16 +569,16 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state) */ int ret = platform_pci_set_power_state(dev, PCI_D0); if (!ret) - pci_update_current_state(dev, pm); + pci_update_current_state(dev); } - error = pci_raw_set_power_state(dev, pm, state); + error = pci_raw_set_power_state(dev, state); if (state > PCI_D0 && platform_pci_power_manageable(dev)) { /* Allow the platform to finalize the transition */ int ret = platform_pci_set_power_state(dev, state); if (!ret) { - pci_update_current_state(dev, pm); + pci_update_current_state(dev); error = 0; } } @@ -1050,48 +1037,38 @@ int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) /** * pci_pme_capable - check the capability of PCI device to generate PME# * @dev: PCI device to handle. - * @pm: PCI PM capability offset of the device. * @state: PCI state from which device will issue PME#. */ -static bool pci_pme_capable(struct pci_dev *dev, int pm, pci_power_t state) +static bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) { - u16 pmc; - - if (!pm) + if (!dev->pm_cap) return false; - /* Check device's ability to generate PME# from given state */ - pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); - - pmc &= PCI_PM_CAP_PME_MASK; - pmc >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ - - return !!(pmc & (1 << state)); + return !!(dev->pme_support & (1 << state)); } /** * pci_pme_active - enable or disable PCI device's PME# function * @dev: PCI device to handle. - * @pm: PCI PM capability offset of the device. * @enable: 'true' to enable PME# generation; 'false' to disable it. * * The caller must verify that the device is capable of generating PME# before * calling this function with @enable equal to 'true'. */ -static void pci_pme_active(struct pci_dev *dev, int pm, bool enable) +static void pci_pme_active(struct pci_dev *dev, bool enable) { u16 pmcsr; - if (!pm) + if (!dev->pm_cap) return; - pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); /* Clear PME_Status by writing 1 to it and enable PME# */ pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; if (!enable) pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; - pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); + pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); @@ -1118,7 +1095,6 @@ static void pci_pme_active(struct pci_dev *dev, int pm, bool enable) */ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { - int pm; int error = 0; bool pme_done = false; @@ -1134,9 +1110,8 @@ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) if (!enable && platform_pci_can_wakeup(dev)) error = platform_pci_sleep_wake(dev, false); - pm = pci_find_capability(dev, PCI_CAP_ID_PM); - if (!enable || pci_pme_capable(dev, pm, state)) { - pci_pme_active(dev, pm, enable); + if (!enable || pci_pme_capable(dev, state)) { + pci_pme_active(dev, enable); pme_done = true; } @@ -1158,7 +1133,6 @@ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) int pci_prepare_to_sleep(struct pci_dev *dev) { pci_power_t target_state = PCI_D3hot; - int pm = pci_find_capability(dev, PCI_CAP_ID_PM); int error; if (platform_pci_power_manageable(dev)) { @@ -1186,23 +1160,14 @@ int pci_prepare_to_sleep(struct pci_dev *dev) * wake-up events, make it the target state and enable device * to generate PME#. */ - u16 pmc; - - if (!pm) + if (!dev->pm_cap) return -EIO; - pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); - if (pmc & PCI_PM_CAP_PME_MASK) { - if (!(pmc & PCI_PM_CAP_PME_D3)) { - /* Device cannot generate PME# from D3_hot */ - if (pmc & PCI_PM_CAP_PME_D2) - target_state = PCI_D2; - else if (pmc & PCI_PM_CAP_PME_D1) - target_state = PCI_D1; - else - target_state = PCI_D0; - } - pci_pme_active(dev, pm, true); + if (dev->pme_support) { + while (target_state + && !(dev->pme_support & (1 << target_state))) + target_state--; + pci_pme_active(dev, true); } } @@ -1236,6 +1201,8 @@ void pci_pm_init(struct pci_dev *dev) int pm; u16 pmc; + dev->pm_cap = 0; + /* find PCI PM capability in list */ pm = pci_find_capability(dev, PCI_CAP_ID_PM); if (!pm) @@ -1249,7 +1216,23 @@ void pci_pm_init(struct pci_dev *dev) return; } - if (pmc & PCI_PM_CAP_PME_MASK) { + dev->pm_cap = pm; + + dev->d1_support = false; + dev->d2_support = false; + if (!pci_no_d1d2(dev)) { + if (pmc & PCI_PM_CAP_D1) { + dev_printk(KERN_DEBUG, &dev->dev, "supports D1\n"); + dev->d1_support = true; + } + if (pmc & PCI_PM_CAP_D2) { + dev_printk(KERN_DEBUG, &dev->dev, "supports D2\n"); + dev->d2_support = true; + } + } + + pmc &= PCI_PM_CAP_PME_MASK; + if (pmc) { dev_printk(KERN_INFO, &dev->dev, "PME# supported from%s%s%s%s%s\n", (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", @@ -1257,6 +1240,7 @@ void pci_pm_init(struct pci_dev *dev) (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); + dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; /* * Make device's PM flags reflect the wake-up capability, but * let the user space enable it to wake up the system as needed. @@ -1264,7 +1248,9 @@ void pci_pm_init(struct pci_dev *dev) device_set_wakeup_capable(&dev->dev, true); device_set_wakeup_enable(&dev->dev, false); /* Disable the PME# generation functionality */ - pci_pme_active(dev, pm, false); + pci_pme_active(dev, false); + } else { + dev->pme_support = 0; } } diff --git a/include/linux/pci.h b/include/linux/pci.h index 52ac06dcce98..68a29f0f2748 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -177,6 +177,13 @@ struct pci_dev { pci_power_t current_state; /* Current operating state. In ACPI-speak, this is D0-D3, D0 being fully functional, and D3 being off. */ + int pm_cap; /* PM capability offset in the + configuration space */ + unsigned int pme_support:5; /* Bitmask of states from which PME# + can be generated */ + unsigned int d1_support:1; /* Low power state D1 is supported */ + unsigned int d2_support:1; /* Low power state D2 is supported */ + unsigned int no_d1d2:1; /* Only allow D0 and D3 */ #ifdef CONFIG_PCIEASPM struct pcie_link_state *link_state; /* ASPM link state. */ @@ -201,7 +208,6 @@ struct pci_dev { unsigned int is_added:1; unsigned int is_busmaster:1; /* device is busmaster */ unsigned int no_msi:1; /* device may not use msi */ - unsigned int no_d1d2:1; /* only allow d0 or d3 */ unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ unsigned int broken_parity_status:1; /* Device generates false positive parity */ unsigned int msi_enabled:1; diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index c0c1223c9194..19958b929905 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -231,6 +231,7 @@ #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ +#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ #define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ -- cgit v1.2.3 From f7a1b86095bf7fd1578ef54067545b9cb7084713 Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 8 Jul 2008 15:00:54 +0100 Subject: Fix acpi_pm_device_sleep_wake() by providing a stub for CONFIG_PM_SLEEP=n So that one of the several config option permutations will build again. Tested-by: Alexander Beregalov Signed-off-by: David Howells Signed-off-by: Jesse Barnes --- include/acpi/acpi_bus.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 7ab5a611e43f..a5ac0bc7f52e 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -388,6 +388,10 @@ static inline int acpi_pm_device_sleep_state(struct device *d, int *p) *p = ACPI_STATE_D0; return ACPI_STATE_D3; } +static inline int acpi_pm_device_sleep_wake(struct device *dev, bool enable) +{ + return -ENODEV; +} #endif /* !CONFIG_PM_SLEEP */ #endif /* CONFIG_ACPI */ -- cgit v1.2.3 From fabb657005edbbcb0d13ee49a40f1f4b042a1d19 Mon Sep 17 00:00:00 2001 From: Maxim Shchetynin Date: Sat, 5 Jul 2008 05:05:39 +1000 Subject: powerpc/spufs: add atomic busy_spus counter to struct cbe_spu_info As nr_active counter includes also spus waiting for syscalls to return we need a seperate counter that only counts spus that are currently running on spu side. This counter shall be used by a cpufreq governor that targets a frequency dependent from the number of running spus. Signed-off-by: Christian Krafft Acked-by: Jeremy Kerr Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/cell/spufs/sched.c | 6 ++++++ include/asm-powerpc/spu.h | 1 + 2 files changed, 7 insertions(+) (limited to 'include') diff --git a/arch/powerpc/platforms/cell/spufs/sched.c b/arch/powerpc/platforms/cell/spufs/sched.c index afb92d4fbcf5..34654743363d 100644 --- a/arch/powerpc/platforms/cell/spufs/sched.c +++ b/arch/powerpc/platforms/cell/spufs/sched.c @@ -994,6 +994,7 @@ void spuctx_switch_state(struct spu_context *ctx, struct timespec ts; struct spu *spu; enum spu_utilization_state old_state; + int node; ktime_get_ts(&ts); curtime = timespec_to_ns(&ts); @@ -1015,6 +1016,11 @@ void spuctx_switch_state(struct spu_context *ctx, spu->stats.times[old_state] += delta; spu->stats.util_state = new_state; spu->stats.tstamp = curtime; + node = spu->node; + if (old_state == SPU_UTIL_USER) + atomic_dec(&cbe_spu_info[node].busy_spus); + if (new_state == SPU_UTIL_USER); + atomic_inc(&cbe_spu_info[node].busy_spus); } } diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h index 99348c1f4cab..8b2eb044270a 100644 --- a/include/asm-powerpc/spu.h +++ b/include/asm-powerpc/spu.h @@ -191,6 +191,7 @@ struct cbe_spu_info { struct list_head spus; int n_spus; int nr_active; + atomic_t busy_spus; atomic_t reserved_spus; }; -- cgit v1.2.3 From c8692362db3db3a6f644e05a477161d967430aac Mon Sep 17 00:00:00 2001 From: Mark Nelson Date: Sat, 5 Jul 2008 05:05:41 +1000 Subject: powerpc/dma: Add struct iommu_table argument to iommu_map_sg() Make iommu_map_sg take a struct iommu_table. It did so before commit 740c3ce66700640a6e6136ff679b067e92125794 (iommu sg merging: ppc: make iommu respect the segment size limits). This stops the function looking in the archdata.dma_data for the iommu table because in the future it will be called with a device that has no table there. This also has the nice side effect of making iommu_map_sg() match the other map functions. Signed-off-by: Mark Nelson Signed-off-by: Arnd Bergmann Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/dma_64.c | 2 +- arch/powerpc/kernel/iommu.c | 7 +++---- include/asm-powerpc/iommu.h | 6 +++--- 3 files changed, 7 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/dma_64.c b/arch/powerpc/kernel/dma_64.c index 3a317cb0636a..739744508c6e 100644 --- a/arch/powerpc/kernel/dma_64.c +++ b/arch/powerpc/kernel/dma_64.c @@ -68,7 +68,7 @@ static void dma_iommu_unmap_single(struct device *dev, dma_addr_t dma_handle, static int dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist, int nelems, enum dma_data_direction direction) { - return iommu_map_sg(dev, sglist, nelems, + return iommu_map_sg(dev, dev->archdata.dma_data, sglist, nelems, device_to_mask(dev), direction); } diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c index 0c663669bc32..ccf00fe9cee6 100644 --- a/arch/powerpc/kernel/iommu.c +++ b/arch/powerpc/kernel/iommu.c @@ -267,11 +267,10 @@ static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, spin_unlock_irqrestore(&(tbl->it_lock), flags); } -int iommu_map_sg(struct device *dev, struct scatterlist *sglist, - int nelems, unsigned long mask, - enum dma_data_direction direction) +int iommu_map_sg(struct device *dev, struct iommu_table *tbl, + struct scatterlist *sglist, int nelems, + unsigned long mask, enum dma_data_direction direction) { - struct iommu_table *tbl = dev->archdata.dma_data; dma_addr_t dma_next = 0, dma_addr; unsigned long flags; struct scatterlist *s, *outs, *segstart; diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h index 852e15f51a1e..65f6682bee87 100644 --- a/include/asm-powerpc/iommu.h +++ b/include/asm-powerpc/iommu.h @@ -79,9 +79,9 @@ extern void iommu_free_table(struct iommu_table *tbl, const char *node_name); extern struct iommu_table *iommu_init_table(struct iommu_table * tbl, int nid); -extern int iommu_map_sg(struct device *dev, struct scatterlist *sglist, - int nelems, unsigned long mask, - enum dma_data_direction direction); +extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl, + struct scatterlist *sglist, int nelems, + unsigned long mask, enum dma_data_direction direction); extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist, int nelems, enum dma_data_direction direction); -- cgit v1.2.3 From 3affedc4e1ce837033b6c5e9289d2ce2f5a62d31 Mon Sep 17 00:00:00 2001 From: Mark Nelson Date: Sat, 5 Jul 2008 05:05:42 +1000 Subject: powerpc/dma: implement new dma_*map*_attrs() interfaces Update powerpc to use the new dma_*map*_attrs() interfaces. In doing so update struct dma_mapping_ops to accept a struct dma_attrs and propagate these changes through to all users of the code (generic IOMMU and the 64bit DMA code, and the iseries and ps3 platform code). The old dma_*map_*() interfaces are reimplemented as calls to the corresponding new interfaces. Signed-off-by: Mark Nelson Signed-off-by: Arnd Bergmann Acked-by: Geoff Levand Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/Kconfig | 1 + arch/powerpc/kernel/dma_64.c | 34 ++++++---- arch/powerpc/kernel/ibmebus.c | 12 ++-- arch/powerpc/kernel/iommu.c | 11 +-- arch/powerpc/platforms/iseries/iommu.c | 4 +- arch/powerpc/platforms/ps3/system-bus.c | 17 +++-- include/asm-powerpc/dma-mapping.h | 116 +++++++++++++++++++++++--------- include/asm-powerpc/iommu.h | 12 ++-- 8 files changed, 144 insertions(+), 63 deletions(-) (limited to 'include') diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index f2a0f50146e1..462c86a4eefb 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -110,6 +110,7 @@ config PPC select HAVE_KPROBES select HAVE_KRETPROBES select HAVE_LMB + select HAVE_DMA_ATTRS config EARLY_PRINTK bool diff --git a/arch/powerpc/kernel/dma_64.c b/arch/powerpc/kernel/dma_64.c index 739744508c6e..3ae0c35d21f9 100644 --- a/arch/powerpc/kernel/dma_64.c +++ b/arch/powerpc/kernel/dma_64.c @@ -50,32 +50,38 @@ static void dma_iommu_free_coherent(struct device *dev, size_t size, */ static dma_addr_t dma_iommu_map_single(struct device *dev, void *vaddr, size_t size, - enum dma_data_direction direction) + enum dma_data_direction direction, + struct dma_attrs *attrs) { return iommu_map_single(dev, dev->archdata.dma_data, vaddr, size, - device_to_mask(dev), direction); + device_to_mask(dev), direction, attrs); } static void dma_iommu_unmap_single(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) + enum dma_data_direction direction, + struct dma_attrs *attrs) { - iommu_unmap_single(dev->archdata.dma_data, dma_handle, size, direction); + iommu_unmap_single(dev->archdata.dma_data, dma_handle, size, direction, + attrs); } static int dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist, - int nelems, enum dma_data_direction direction) + int nelems, enum dma_data_direction direction, + struct dma_attrs *attrs) { return iommu_map_sg(dev, dev->archdata.dma_data, sglist, nelems, - device_to_mask(dev), direction); + device_to_mask(dev), direction, attrs); } static void dma_iommu_unmap_sg(struct device *dev, struct scatterlist *sglist, - int nelems, enum dma_data_direction direction) + int nelems, enum dma_data_direction direction, + struct dma_attrs *attrs) { - iommu_unmap_sg(dev->archdata.dma_data, sglist, nelems, direction); + iommu_unmap_sg(dev->archdata.dma_data, sglist, nelems, direction, + attrs); } /* We support DMA to/from any memory page via the iommu */ @@ -148,19 +154,22 @@ static void dma_direct_free_coherent(struct device *dev, size_t size, static dma_addr_t dma_direct_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction) + enum dma_data_direction direction, + struct dma_attrs *attrs) { return virt_to_abs(ptr) + get_dma_direct_offset(dev); } static void dma_direct_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction direction) + enum dma_data_direction direction, + struct dma_attrs *attrs) { } static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, - int nents, enum dma_data_direction direction) + int nents, enum dma_data_direction direction, + struct dma_attrs *attrs) { struct scatterlist *sg; int i; @@ -174,7 +183,8 @@ static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, } static void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction direction) + int nents, enum dma_data_direction direction, + struct dma_attrs *attrs) { } diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c index 9971159c8040..e3b1fcd6d991 100644 --- a/arch/powerpc/kernel/ibmebus.c +++ b/arch/powerpc/kernel/ibmebus.c @@ -82,7 +82,8 @@ static void ibmebus_free_coherent(struct device *dev, static dma_addr_t ibmebus_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction) + enum dma_data_direction direction, + struct dma_attrs *attrs) { return (dma_addr_t)(ptr); } @@ -90,14 +91,16 @@ static dma_addr_t ibmebus_map_single(struct device *dev, static void ibmebus_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction direction) + enum dma_data_direction direction, + struct dma_attrs *attrs) { return; } static int ibmebus_map_sg(struct device *dev, struct scatterlist *sgl, - int nents, enum dma_data_direction direction) + int nents, enum dma_data_direction direction, + struct dma_attrs *attrs) { struct scatterlist *sg; int i; @@ -112,7 +115,8 @@ static int ibmebus_map_sg(struct device *dev, static void ibmebus_unmap_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction direction) + int nents, enum dma_data_direction direction, + struct dma_attrs *attrs) { return; } diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c index ccf00fe9cee6..8c68ee9e5d1c 100644 --- a/arch/powerpc/kernel/iommu.c +++ b/arch/powerpc/kernel/iommu.c @@ -269,7 +269,8 @@ static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, int iommu_map_sg(struct device *dev, struct iommu_table *tbl, struct scatterlist *sglist, int nelems, - unsigned long mask, enum dma_data_direction direction) + unsigned long mask, enum dma_data_direction direction, + struct dma_attrs *attrs) { dma_addr_t dma_next = 0, dma_addr; unsigned long flags; @@ -411,7 +412,8 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl, void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist, - int nelems, enum dma_data_direction direction) + int nelems, enum dma_data_direction direction, + struct dma_attrs *attrs) { struct scatterlist *sg; unsigned long flags; @@ -553,7 +555,7 @@ void iommu_free_table(struct iommu_table *tbl, const char *node_name) */ dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl, void *vaddr, size_t size, unsigned long mask, - enum dma_data_direction direction) + enum dma_data_direction direction, struct dma_attrs *attrs) { dma_addr_t dma_handle = DMA_ERROR_CODE; unsigned long uaddr; @@ -586,7 +588,8 @@ dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl, } void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction) + size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs) { unsigned int npages; diff --git a/arch/powerpc/platforms/iseries/iommu.c b/arch/powerpc/platforms/iseries/iommu.c index 11fa3c772ed5..ab5d8687c3cf 100644 --- a/arch/powerpc/platforms/iseries/iommu.c +++ b/arch/powerpc/platforms/iseries/iommu.c @@ -214,13 +214,13 @@ dma_addr_t iseries_hv_map(void *vaddr, size_t size, enum dma_data_direction direction) { return iommu_map_single(NULL, &vio_iommu_table, vaddr, size, - DMA_32BIT_MASK, direction); + DMA_32BIT_MASK, direction, NULL); } void iseries_hv_unmap(dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - iommu_unmap_single(&vio_iommu_table, dma_handle, size, direction); + iommu_unmap_single(&vio_iommu_table, dma_handle, size, direction, NULL); } void __init iommu_vio_init(void) diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c index cf215e981c3e..d66c3628a112 100644 --- a/arch/powerpc/platforms/ps3/system-bus.c +++ b/arch/powerpc/platforms/ps3/system-bus.c @@ -555,7 +555,7 @@ static void ps3_free_coherent(struct device *_dev, size_t size, void *vaddr, */ static dma_addr_t ps3_sb_map_single(struct device *_dev, void *ptr, size_t size, - enum dma_data_direction direction) + enum dma_data_direction direction, struct dma_attrs *attrs) { struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev); int result; @@ -575,7 +575,8 @@ static dma_addr_t ps3_sb_map_single(struct device *_dev, void *ptr, size_t size, static dma_addr_t ps3_ioc0_map_single(struct device *_dev, void *ptr, size_t size, - enum dma_data_direction direction) + enum dma_data_direction direction, + struct dma_attrs *attrs) { struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev); int result; @@ -608,7 +609,7 @@ static dma_addr_t ps3_ioc0_map_single(struct device *_dev, void *ptr, } static void ps3_unmap_single(struct device *_dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction direction) + size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) { struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev); int result; @@ -622,7 +623,7 @@ static void ps3_unmap_single(struct device *_dev, dma_addr_t dma_addr, } static int ps3_sb_map_sg(struct device *_dev, struct scatterlist *sgl, - int nents, enum dma_data_direction direction) + int nents, enum dma_data_direction direction, struct dma_attrs *attrs) { #if defined(CONFIG_PS3_DYNAMIC_DMA) BUG_ON("do"); @@ -651,14 +652,15 @@ static int ps3_sb_map_sg(struct device *_dev, struct scatterlist *sgl, static int ps3_ioc0_map_sg(struct device *_dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) + enum dma_data_direction direction, + struct dma_attrs *attrs) { BUG(); return 0; } static void ps3_sb_unmap_sg(struct device *_dev, struct scatterlist *sg, - int nents, enum dma_data_direction direction) + int nents, enum dma_data_direction direction, struct dma_attrs *attrs) { #if defined(CONFIG_PS3_DYNAMIC_DMA) BUG_ON("do"); @@ -666,7 +668,8 @@ static void ps3_sb_unmap_sg(struct device *_dev, struct scatterlist *sg, } static void ps3_ioc0_unmap_sg(struct device *_dev, struct scatterlist *sg, - int nents, enum dma_data_direction direction) + int nents, enum dma_data_direction direction, + struct dma_attrs *attrs) { BUG(); } diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h index bbefb69bfb67..de1395023cb1 100644 --- a/include/asm-powerpc/dma-mapping.h +++ b/include/asm-powerpc/dma-mapping.h @@ -13,6 +13,7 @@ /* need struct page definitions */ #include #include +#include #include #define DMA_ERROR_CODE (~(dma_addr_t)0x0) @@ -53,13 +54,17 @@ struct dma_mapping_ops { void (*free_coherent)(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle); dma_addr_t (*map_single)(struct device *dev, void *ptr, - size_t size, enum dma_data_direction direction); + size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs); void (*unmap_single)(struct device *dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction direction); + size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs); int (*map_sg)(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction direction); + int nents, enum dma_data_direction direction, + struct dma_attrs *attrs); void (*unmap_sg)(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction direction); + int nents, enum dma_data_direction direction, + struct dma_attrs *attrs); int (*dma_supported)(struct device *dev, u64 mask); int (*set_dma_mask)(struct device *dev, u64 dma_mask); }; @@ -109,6 +114,77 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask) return 0; } +static inline dma_addr_t dma_map_single_attrs(struct device *dev, + void *cpu_addr, + size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) +{ + struct dma_mapping_ops *dma_ops = get_dma_ops(dev); + + BUG_ON(!dma_ops); + return dma_ops->map_single(dev, cpu_addr, size, direction, attrs); +} + +static inline void dma_unmap_single_attrs(struct device *dev, + dma_addr_t dma_addr, + size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) +{ + struct dma_mapping_ops *dma_ops = get_dma_ops(dev); + + BUG_ON(!dma_ops); + dma_ops->unmap_single(dev, dma_addr, size, direction, attrs); +} + +static inline dma_addr_t dma_map_page_attrs(struct device *dev, + struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) +{ + struct dma_mapping_ops *dma_ops = get_dma_ops(dev); + + BUG_ON(!dma_ops); + return dma_ops->map_single(dev, page_address(page) + offset, size, + direction, attrs); +} + +static inline void dma_unmap_page_attrs(struct device *dev, + dma_addr_t dma_address, + size_t size, + enum dma_data_direction direction, + struct dma_attrs *attrs) +{ + struct dma_mapping_ops *dma_ops = get_dma_ops(dev); + + BUG_ON(!dma_ops); + dma_ops->unmap_single(dev, dma_address, size, direction, attrs); +} + +static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction direction, + struct dma_attrs *attrs) +{ + struct dma_mapping_ops *dma_ops = get_dma_ops(dev); + + BUG_ON(!dma_ops); + return dma_ops->map_sg(dev, sg, nents, direction, attrs); +} + +static inline void dma_unmap_sg_attrs(struct device *dev, + struct scatterlist *sg, + int nhwentries, + enum dma_data_direction direction, + struct dma_attrs *attrs) +{ + struct dma_mapping_ops *dma_ops = get_dma_ops(dev); + + BUG_ON(!dma_ops); + dma_ops->unmap_sg(dev, sg, nhwentries, direction, attrs); +} + static inline void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) { @@ -131,63 +207,43 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction direction) { - struct dma_mapping_ops *dma_ops = get_dma_ops(dev); - - BUG_ON(!dma_ops); - return dma_ops->map_single(dev, cpu_addr, size, direction); + return dma_map_single_attrs(dev, cpu_addr, size, direction, NULL); } static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction) { - struct dma_mapping_ops *dma_ops = get_dma_ops(dev); - - BUG_ON(!dma_ops); - dma_ops->unmap_single(dev, dma_addr, size, direction); + dma_unmap_single_attrs(dev, dma_addr, size, direction, NULL); } static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, unsigned long offset, size_t size, enum dma_data_direction direction) { - struct dma_mapping_ops *dma_ops = get_dma_ops(dev); - - BUG_ON(!dma_ops); - return dma_ops->map_single(dev, page_address(page) + offset, size, - direction); + return dma_map_page_attrs(dev, page, offset, size, direction, NULL); } static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, enum dma_data_direction direction) { - struct dma_mapping_ops *dma_ops = get_dma_ops(dev); - - BUG_ON(!dma_ops); - dma_ops->unmap_single(dev, dma_address, size, direction); + dma_unmap_page_attrs(dev, dma_address, size, direction, NULL); } static inline int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction) { - struct dma_mapping_ops *dma_ops = get_dma_ops(dev); - - BUG_ON(!dma_ops); - return dma_ops->map_sg(dev, sg, nents, direction); + return dma_map_sg_attrs(dev, sg, nents, direction, NULL); } static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, enum dma_data_direction direction) { - struct dma_mapping_ops *dma_ops = get_dma_ops(dev); - - BUG_ON(!dma_ops); - dma_ops->unmap_sg(dev, sg, nhwentries, direction); + dma_unmap_sg_attrs(dev, sg, nhwentries, direction, NULL); } - /* * Available generic sets of operations */ diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h index 65f6682bee87..51ecfef8d843 100644 --- a/include/asm-powerpc/iommu.h +++ b/include/asm-powerpc/iommu.h @@ -81,9 +81,11 @@ extern struct iommu_table *iommu_init_table(struct iommu_table * tbl, extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl, struct scatterlist *sglist, int nelems, - unsigned long mask, enum dma_data_direction direction); + unsigned long mask, enum dma_data_direction direction, + struct dma_attrs *attrs); extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist, - int nelems, enum dma_data_direction direction); + int nelems, enum dma_data_direction direction, + struct dma_attrs *attrs); extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl, size_t size, dma_addr_t *dma_handle, @@ -92,9 +94,11 @@ extern void iommu_free_coherent(struct iommu_table *tbl, size_t size, void *vaddr, dma_addr_t dma_handle); extern dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl, void *vaddr, size_t size, unsigned long mask, - enum dma_data_direction direction); + enum dma_data_direction direction, + struct dma_attrs *attrs); extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction); + size_t size, enum dma_data_direction direction, + struct dma_attrs *attrs); extern void iommu_init_early_pSeries(void); extern void iommu_init_early_iSeries(void); -- cgit v1.2.3 From 3a4c6f0b1540811110a59112b4c83f55c229728c Mon Sep 17 00:00:00 2001 From: Mark Nelson Date: Sat, 5 Jul 2008 05:05:45 +1000 Subject: powerpc: move device_to_mask() to dma-mapping.h Move device_to_mask() to dma-mapping.h because we need to use it from outside dma_64.c in a later patch. Signed-off-by: Mark Nelson Signed-off-by: Arnd Bergmann Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/dma_64.c | 9 --------- include/asm-powerpc/dma-mapping.h | 9 +++++++++ 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/dma_64.c b/arch/powerpc/kernel/dma_64.c index 3ae0c35d21f9..ae5708e3a312 100644 --- a/arch/powerpc/kernel/dma_64.c +++ b/arch/powerpc/kernel/dma_64.c @@ -15,15 +15,6 @@ * Generic iommu implementation */ -static inline unsigned long device_to_mask(struct device *dev) -{ - if (dev->dma_mask && *dev->dma_mask) - return *dev->dma_mask; - /* Assume devices without mask can take 32 bit addresses */ - return 0xfffffffful; -} - - /* Allocates a contiguous real buffer and creates mappings over it. * Returns the virtual address of the buffer and sets dma_handle * to the dma address (mapping) of the first page. diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h index de1395023cb1..74c549780987 100644 --- a/include/asm-powerpc/dma-mapping.h +++ b/include/asm-powerpc/dma-mapping.h @@ -45,6 +45,15 @@ extern void __dma_sync_page(struct page *page, unsigned long offset, #endif /* ! CONFIG_NOT_COHERENT_CACHE */ #ifdef CONFIG_PPC64 + +static inline unsigned long device_to_mask(struct device *dev) +{ + if (dev->dma_mask && *dev->dma_mask) + return *dev->dma_mask; + /* Assume devices without mask can take 32 bit addresses */ + return 0xfffffffful; +} + /* * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO */ -- cgit v1.2.3 From e5093ff05d36c64e8f36a9ddb26358256dc133ea Mon Sep 17 00:00:00 2001 From: Srinivasa Ds Date: Tue, 8 Jul 2008 00:22:27 +1000 Subject: powerpc: Implement task_pt_regs() accessor The task_pt_regs() macro allows access to the pt_regs of a given task. This macro is not currently defined for the powerpc architecture, but we need it for some upcoming utrace additions. Signed-off-by: Srinivasa DS Signed-off-by: Benjamin Herrenschmidt --- include/asm-powerpc/processor.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index 061cd17ba83b..101ed87f7d84 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h @@ -234,6 +234,8 @@ struct thread_struct { #define thread_saved_pc(tsk) \ ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) +#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs) + unsigned long get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) -- cgit v1.2.3 From b845f313d78e4e259ec449909e3bbadf77b53a6d Mon Sep 17 00:00:00 2001 From: Dave Kleikamp Date: Tue, 8 Jul 2008 00:28:51 +1000 Subject: mm: Allow architectures to define additional protection bits This patch allows architectures to define functions to deal with additional protections bits for mmap() and mprotect(). arch_calc_vm_prot_bits() maps additonal protection bits to vm_flags arch_vm_get_page_prot() maps additional vm_flags to the vma's vm_page_prot arch_validate_prot() checks for valid values of the protection bits Note: vm_get_page_prot() is now pretty ugly, but the generated code should be identical for architectures that don't define additional protection bits. Signed-off-by: Dave Kleikamp Acked-by: Andrew Morton Acked-by: Hugh Dickins Signed-off-by: Benjamin Herrenschmidt --- include/linux/mman.h | 29 ++++++++++++++++++++++++++++- mm/mmap.c | 5 +++-- mm/mprotect.c | 2 +- 3 files changed, 32 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/linux/mman.h b/include/linux/mman.h index dab8892e6ff1..30d1073bac3b 100644 --- a/include/linux/mman.h +++ b/include/linux/mman.h @@ -33,6 +33,32 @@ static inline void vm_unacct_memory(long pages) vm_acct_memory(-pages); } +/* + * Allow architectures to handle additional protection bits + */ + +#ifndef arch_calc_vm_prot_bits +#define arch_calc_vm_prot_bits(prot) 0 +#endif + +#ifndef arch_vm_get_page_prot +#define arch_vm_get_page_prot(vm_flags) __pgprot(0) +#endif + +#ifndef arch_validate_prot +/* + * This is called from mprotect(). PROT_GROWSDOWN and PROT_GROWSUP have + * already been masked out. + * + * Returns true if the prot flags are valid + */ +static inline int arch_validate_prot(unsigned long prot) +{ + return (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM)) == 0; +} +#define arch_validate_prot arch_validate_prot +#endif + /* * Optimisation macro. It is equivalent to: * (x & bit1) ? bit2 : 0 @@ -51,7 +77,8 @@ calc_vm_prot_bits(unsigned long prot) { return _calc_vm_trans(prot, PROT_READ, VM_READ ) | _calc_vm_trans(prot, PROT_WRITE, VM_WRITE) | - _calc_vm_trans(prot, PROT_EXEC, VM_EXEC ); + _calc_vm_trans(prot, PROT_EXEC, VM_EXEC) | + arch_calc_vm_prot_bits(prot); } /* diff --git a/mm/mmap.c b/mm/mmap.c index 3354fdd83d4b..1d102b956fd8 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -72,8 +72,9 @@ pgprot_t protection_map[16] = { pgprot_t vm_get_page_prot(unsigned long vm_flags) { - return protection_map[vm_flags & - (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]; + return __pgprot(pgprot_val(protection_map[vm_flags & + (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]) | + pgprot_val(arch_vm_get_page_prot(vm_flags))); } EXPORT_SYMBOL(vm_get_page_prot); diff --git a/mm/mprotect.c b/mm/mprotect.c index a5bf31c27375..ecfaa5844b5f 100644 --- a/mm/mprotect.c +++ b/mm/mprotect.c @@ -239,7 +239,7 @@ sys_mprotect(unsigned long start, size_t len, unsigned long prot) end = start + len; if (end <= start) return -ENOMEM; - if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM)) + if (!arch_validate_prot(prot)) return -EINVAL; reqprot = prot; -- cgit v1.2.3 From aba46c5027cb59d98052231b36efcbbde9c77a1d Mon Sep 17 00:00:00 2001 From: Dave Kleikamp Date: Tue, 8 Jul 2008 00:28:52 +1000 Subject: powerpc/mm: Define flags for Strong Access Ordering This patch defines: - PROT_SAO, which is passed into mmap() and mprotect() in the prot field - VM_SAO in vma->vm_flags, and - _PAGE_SAO, the combination of WIMG bits in the pte that enables strong access ordering for the page. Signed-off-by: Dave Kleikamp Signed-off-by: Benjamin Herrenschmidt --- include/asm-powerpc/mman.h | 2 ++ include/asm-powerpc/pgtable-ppc64.h | 3 +++ include/linux/mm.h | 1 + 3 files changed, 6 insertions(+) (limited to 'include') diff --git a/include/asm-powerpc/mman.h b/include/asm-powerpc/mman.h index 24cf664a8295..0c46bf2c7d5f 100644 --- a/include/asm-powerpc/mman.h +++ b/include/asm-powerpc/mman.h @@ -10,6 +10,8 @@ * 2 of the License, or (at your option) any later version. */ +#define PROT_SAO 0x10 /* Strong Access Ordering */ + #define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */ #define MAP_NORESERVE 0x40 /* don't reserve swap pages */ #define MAP_LOCKED 0x80 diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h index b2754d46be44..d09599cccb35 100644 --- a/include/asm-powerpc/pgtable-ppc64.h +++ b/include/asm-powerpc/pgtable-ppc64.h @@ -93,6 +93,9 @@ #define _PAGE_RW 0x0200 /* software: user write access allowed */ #define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */ +/* Strong Access Ordering */ +#define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT) + #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT) #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY) diff --git a/include/linux/mm.h b/include/linux/mm.h index 586a943cab01..689184446fc6 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -108,6 +108,7 @@ extern unsigned int kobjsize(const void *objp); #define VM_CAN_NONLINEAR 0x08000000 /* Has ->fault & does nonlinear pages */ #define VM_MIXEDMAP 0x10000000 /* Can contain "struct page" and pure PFN pages */ +#define VM_SAO 0x20000000 /* Strong Access Ordering (powerpc) */ #ifndef VM_STACK_DEFAULT_FLAGS /* arch can override this */ #define VM_STACK_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS -- cgit v1.2.3 From 379070491e1e744a59e69e5bcf3765012d15ecb4 Mon Sep 17 00:00:00 2001 From: Dave Kleikamp Date: Tue, 8 Jul 2008 00:28:53 +1000 Subject: powerpc/mm: Add SAO Feature bit to the cputable Add the CPU feature bit for the new Strong Access Ordering facility of Power7 Signed-off-by: Dave Kleikamp Signed-off-by: Joel Schopp Signed-off-by: Benjamin Herrenschmidt --- include/asm-powerpc/cputable.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 3171ac904b91..4fd76898975b 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -186,6 +186,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000) #define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000) #define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000) +#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000) #ifndef __ASSEMBLY__ @@ -401,7 +402,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ - CPU_FTR_DSCR) + CPU_FTR_DSCR | CPU_FTR_SAO) #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ -- cgit v1.2.3 From ef3d3246a0d06be622867d21af25f997aeeb105f Mon Sep 17 00:00:00 2001 From: Dave Kleikamp Date: Tue, 8 Jul 2008 00:28:54 +1000 Subject: powerpc/mm: Add Strong Access Ordering support Allow an application to enable Strong Access Ordering on specific pages of memory on Power 7 hardware. Currently, power has a weaker memory model than x86. Implementing a stronger memory model allows an emulator to more efficiently translate x86 code into power code, resulting in faster code execution. On Power 7 hardware, storing 0b1110 in the WIMG bits of the hpte enables strong access ordering mode for the memory page. This patchset allows a user to specify which pages are thus enabled by passing a new protection bit through mmap() and mprotect(). I have defined PROT_SAO to be 0x10. Signed-off-by: Dave Kleikamp Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/syscalls.c | 3 +++ include/asm-powerpc/mman.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) (limited to 'include') diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c index 4fe69ca24481..c04832c4a02e 100644 --- a/arch/powerpc/kernel/syscalls.c +++ b/arch/powerpc/kernel/syscalls.c @@ -143,6 +143,9 @@ static inline unsigned long do_mmap2(unsigned long addr, size_t len, struct file * file = NULL; unsigned long ret = -EINVAL; + if (!arch_validate_prot(prot)) + goto out; + if (shift) { if (off & ((1 << shift) - 1)) goto out; diff --git a/include/asm-powerpc/mman.h b/include/asm-powerpc/mman.h index 0c46bf2c7d5f..f8a32e20ba04 100644 --- a/include/asm-powerpc/mman.h +++ b/include/asm-powerpc/mman.h @@ -1,7 +1,9 @@ #ifndef _ASM_POWERPC_MMAN_H #define _ASM_POWERPC_MMAN_H +#include #include +#include /* * This program is free software; you can redistribute it and/or @@ -26,4 +28,32 @@ #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ #define MAP_NONBLOCK 0x10000 /* do not block on IO */ +#ifdef CONFIG_PPC64 +/* + * This file is included by linux/mman.h, so we can't use cacl_vm_prot_bits() + * here. How important is the optimization? + */ +static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot) +{ + return (prot & PROT_SAO) ? VM_SAO : 0; +} +#define arch_calc_vm_prot_bits(prot) arch_calc_vm_prot_bits(prot) + +static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags) +{ + return (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : 0; +} +#define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags) + +static inline int arch_validate_prot(unsigned long prot) +{ + if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO)) + return 0; + if ((prot & PROT_SAO) && !cpu_has_feature(CPU_FTR_SAO)) + return 0; + return 1; +} +#define arch_validate_prot(prot) arch_validate_prot(prot) + +#endif /* CONFIG_PPC64 */ #endif /* _ASM_POWERPC_MMAN_H */ -- cgit v1.2.3 From 2116271a347d1181b5497602c2bfada1de8fd53b Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Tue, 20 May 2008 19:34:39 -0400 Subject: NFS: Add correct bounds checking to NFSv2 locks NFSv2 file locking currently fails the Connectathon tests, because the calls to the VFS locking code do not return an EINVAL error if the struct file_lock overflows the 32-bit boundaries. The problem is due to the fact that we occasionally call helpers from fs/locks.c in order to avoid RPC calls to the server when we know that a local process holds the lock. These helpers are, of course, always 64-bit enabled, so EINVAL is not returned in cases when it would if the call had gone to the NLM code. For consistency, we therefore add support for a bounds-checking helper. Signed-off-by: Trond Myklebust --- fs/nfs/file.c | 20 +++++++++++++++----- fs/nfs/proc.c | 24 ++++++++++++++++++++++++ include/linux/nfs_xdr.h | 1 + 3 files changed, 40 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/fs/nfs/file.c b/fs/nfs/file.c index d84a3d8f32af..7c73f06692b6 100644 --- a/fs/nfs/file.c +++ b/fs/nfs/file.c @@ -593,6 +593,7 @@ out: static int nfs_lock(struct file *filp, int cmd, struct file_lock *fl) { struct inode * inode = filp->f_mapping->host; + int ret = -ENOLCK; dprintk("NFS: nfs_lock(f=%s/%ld, t=%x, fl=%x, r=%Ld:%Ld)\n", inode->i_sb->s_id, inode->i_ino, @@ -602,13 +603,22 @@ static int nfs_lock(struct file *filp, int cmd, struct file_lock *fl) /* No mandatory locks over NFS */ if (__mandatory_lock(inode) && fl->fl_type != F_UNLCK) - return -ENOLCK; + goto out_err; + + if (NFS_PROTO(inode)->lock_check_bounds != NULL) { + ret = NFS_PROTO(inode)->lock_check_bounds(fl); + if (ret < 0) + goto out_err; + } if (IS_GETLK(cmd)) - return do_getlk(filp, cmd, fl); - if (fl->fl_type == F_UNLCK) - return do_unlk(filp, cmd, fl); - return do_setlk(filp, cmd, fl); + ret = do_getlk(filp, cmd, fl); + else if (fl->fl_type == F_UNLCK) + ret = do_unlk(filp, cmd, fl); + else + ret = do_setlk(filp, cmd, fl); +out_err: + return ret; } /* diff --git a/fs/nfs/proc.c b/fs/nfs/proc.c index 03599bfe81cf..5c35b02857f3 100644 --- a/fs/nfs/proc.c +++ b/fs/nfs/proc.c @@ -598,6 +598,29 @@ nfs_proc_lock(struct file *filp, int cmd, struct file_lock *fl) return nlmclnt_proc(NFS_SERVER(inode)->nlm_host, cmd, fl); } +/* Helper functions for NFS lock bounds checking */ +#define NFS_LOCK32_OFFSET_MAX ((__s32)0x7fffffffUL) +static int nfs_lock_check_bounds(const struct file_lock *fl) +{ + __s32 start, end; + + start = (__s32)fl->fl_start; + if ((loff_t)start != fl->fl_start) + goto out_einval; + + if (fl->fl_end != OFFSET_MAX) { + end = (__s32)fl->fl_end; + if ((loff_t)end != fl->fl_end) + goto out_einval; + } else + end = NFS_LOCK32_OFFSET_MAX; + + if (start < 0 || start > end) + goto out_einval; + return 0; +out_einval: + return -EINVAL; +} const struct nfs_rpc_ops nfs_v2_clientops = { .version = 2, /* protocol version */ @@ -633,4 +656,5 @@ const struct nfs_rpc_ops nfs_v2_clientops = { .file_open = nfs_open, .file_release = nfs_release, .lock = nfs_proc_lock, + .lock_check_bounds = nfs_lock_check_bounds, }; diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index 24263bb8e0be..8d780de371f0 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -832,6 +832,7 @@ struct nfs_rpc_ops { int (*file_open) (struct inode *, struct file *); int (*file_release) (struct inode *, struct file *); int (*lock)(struct file *, int, struct file_lock *); + int (*lock_check_bounds)(const struct file_lock *); void (*clear_acl_cache)(struct inode *); }; -- cgit v1.2.3 From b6b6152c46861dd914d0e6cea9c27df057d6e235 Mon Sep 17 00:00:00 2001 From: Olga Kornievskaia Date: Mon, 9 Jun 2008 16:51:31 -0400 Subject: rpc: bring back cl_chatty The cl_chatty flag alows us to control whether a given rpc client leaves "server X not responding, timed out" messages in the syslog. Such messages make sense for ordinary nfs clients (where an unresponsive server means applications on the mountpoint are probably hanging), but not for the callback client (which can fail more commonly, with the only result just of disabling some optimizations). Previously cl_chatty was removed, do to lack of users; reinstate it, and use it for the nfsd's callback client. Signed-off-by: J. Bruce Fields Signed-off-by: Trond Myklebust --- fs/nfsd/nfs4callback.c | 2 +- include/linux/sunrpc/clnt.h | 4 +++- net/sunrpc/clnt.c | 16 +++++++++++----- 3 files changed, 15 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/fs/nfsd/nfs4callback.c b/fs/nfsd/nfs4callback.c index 4d4760e687c3..702fa577aa6e 100644 --- a/fs/nfsd/nfs4callback.c +++ b/fs/nfsd/nfs4callback.c @@ -381,7 +381,7 @@ static int do_probe_callback(void *data) .program = &cb_program, .version = nfs_cb_version[1]->number, .authflavor = RPC_AUTH_UNIX, /* XXX: need AUTH_GSS... */ - .flags = (RPC_CLNT_CREATE_NOPING), + .flags = (RPC_CLNT_CREATE_NOPING | RPC_CLNT_CREATE_QUIET), }; struct rpc_message msg = { .rpc_proc = &nfs4_cb_procedures[NFSPROC4_CLNT_CB_NULL], diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index 6fff7f82ef12..764fd4c286e0 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -42,7 +42,8 @@ struct rpc_clnt { unsigned int cl_softrtry : 1,/* soft timeouts */ cl_discrtry : 1,/* disconnect before retry */ - cl_autobind : 1;/* use getport() */ + cl_autobind : 1,/* use getport() */ + cl_chatty : 1;/* be verbose */ struct rpc_rtt * cl_rtt; /* RTO estimator data */ const struct rpc_timeout *cl_timeout; /* Timeout strategy */ @@ -114,6 +115,7 @@ struct rpc_create_args { #define RPC_CLNT_CREATE_NONPRIVPORT (1UL << 3) #define RPC_CLNT_CREATE_NOPING (1UL << 4) #define RPC_CLNT_CREATE_DISCRTRY (1UL << 5) +#define RPC_CLNT_CREATE_QUIET (1UL << 6) struct rpc_clnt *rpc_create(struct rpc_create_args *args); struct rpc_clnt *rpc_bind_new_program(struct rpc_clnt *, diff --git a/net/sunrpc/clnt.c b/net/sunrpc/clnt.c index 0530eea37b59..09631f6e30e9 100644 --- a/net/sunrpc/clnt.c +++ b/net/sunrpc/clnt.c @@ -324,6 +324,8 @@ struct rpc_clnt *rpc_create(struct rpc_create_args *args) clnt->cl_autobind = 1; if (args->flags & RPC_CLNT_CREATE_DISCRTRY) clnt->cl_discrtry = 1; + if (!(args->flags & RPC_CLNT_CREATE_QUIET)) + clnt->cl_chatty = 1; return clnt; } @@ -1149,7 +1151,8 @@ call_status(struct rpc_task *task) rpc_exit(task, status); break; default: - printk("%s: RPC call returned error %d\n", + if (clnt->cl_chatty) + printk("%s: RPC call returned error %d\n", clnt->cl_protname, -status); rpc_exit(task, status); } @@ -1174,7 +1177,8 @@ call_timeout(struct rpc_task *task) task->tk_timeouts++; if (RPC_IS_SOFT(task)) { - printk(KERN_NOTICE "%s: server %s not responding, timed out\n", + if (clnt->cl_chatty) + printk(KERN_NOTICE "%s: server %s not responding, timed out\n", clnt->cl_protname, clnt->cl_server); rpc_exit(task, -EIO); return; @@ -1182,7 +1186,8 @@ call_timeout(struct rpc_task *task) if (!(task->tk_flags & RPC_CALL_MAJORSEEN)) { task->tk_flags |= RPC_CALL_MAJORSEEN; - printk(KERN_NOTICE "%s: server %s not responding, still trying\n", + if (clnt->cl_chatty) + printk(KERN_NOTICE "%s: server %s not responding, still trying\n", clnt->cl_protname, clnt->cl_server); } rpc_force_rebind(clnt); @@ -1213,8 +1218,9 @@ call_decode(struct rpc_task *task) task->tk_pid, task->tk_status); if (task->tk_flags & RPC_CALL_MAJORSEEN) { - printk(KERN_NOTICE "%s: server %s OK\n", - clnt->cl_protname, clnt->cl_server); + if (clnt->cl_chatty) + printk(KERN_NOTICE "%s: server %s OK\n", + clnt->cl_protname, clnt->cl_server); task->tk_flags &= ~RPC_CALL_MAJORSEEN; } -- cgit v1.2.3 From a486aeda9b2b0d944aecce7871b3186379b898de Mon Sep 17 00:00:00 2001 From: "\\\\\\\"J. Bruce Fields\\\\\\" Date: Mon, 9 Jun 2008 16:51:35 -0400 Subject: rpc: minor cleanup of scheduler callback code Try to make the comment here a little more clear and concise. Also, this macro definition seems unnecessary. Signed-off-by: J. Bruce Fields Signed-off-by: Trond Myklebust --- include/linux/sunrpc/sched.h | 1 - net/sunrpc/sched.c | 14 +++++--------- 2 files changed, 5 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h index d1a5c8c1a0f1..64981a2f1cae 100644 --- a/include/linux/sunrpc/sched.h +++ b/include/linux/sunrpc/sched.h @@ -135,7 +135,6 @@ struct rpc_task_setup { #define RPC_IS_SWAPPER(t) ((t)->tk_flags & RPC_TASK_SWAPPER) #define RPC_DO_ROOTOVERRIDE(t) ((t)->tk_flags & RPC_TASK_ROOTCREDS) #define RPC_ASSASSINATED(t) ((t)->tk_flags & RPC_TASK_KILLED) -#define RPC_DO_CALLBACK(t) ((t)->tk_callback != NULL) #define RPC_IS_SOFT(t) ((t)->tk_flags & RPC_TASK_SOFT) #define RPC_TASK_RUNNING 0 diff --git a/net/sunrpc/sched.c b/net/sunrpc/sched.c index 6eab9bf94baf..6288af05c20f 100644 --- a/net/sunrpc/sched.c +++ b/net/sunrpc/sched.c @@ -626,19 +626,15 @@ static void __rpc_execute(struct rpc_task *task) /* * Execute any pending callback. */ - if (RPC_DO_CALLBACK(task)) { - /* Define a callback save pointer */ + if (task->tk_callback) { void (*save_callback)(struct rpc_task *); /* - * If a callback exists, save it, reset it, - * call it. - * The save is needed to stop from resetting - * another callback set within the callback handler - * - Dave + * We set tk_callback to NULL before calling it, + * in case it sets the tk_callback field itself: */ - save_callback=task->tk_callback; - task->tk_callback=NULL; + save_callback = task->tk_callback; + task->tk_callback = NULL; save_callback(task); } -- cgit v1.2.3 From 46cb650c224bb8e64a749090105d74b9e8eda669 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Wed, 11 Jun 2008 16:32:46 -0400 Subject: NFS: Remove the redundant file_open entry from struct nfs_rpc_ops All instances are set to nfs_open(), so we should just remove the redundant indirection. Ditto for the file_release op Signed-off-by: Trond Myklebust --- fs/nfs/file.c | 4 ++-- fs/nfs/nfs3proc.c | 2 -- fs/nfs/nfs4proc.c | 2 -- fs/nfs/proc.c | 2 -- include/linux/nfs_xdr.h | 2 -- 5 files changed, 2 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/fs/nfs/file.c b/fs/nfs/file.c index 78b26f875eee..509dcb58959e 100644 --- a/fs/nfs/file.c +++ b/fs/nfs/file.c @@ -129,7 +129,7 @@ nfs_file_open(struct inode *inode, struct file *filp) nfs_inc_stats(inode, NFSIOS_VFSOPEN); lock_kernel(); - res = NFS_PROTO(inode)->file_open(inode, filp); + res = nfs_open(inode, filp); unlock_kernel(); return res; } @@ -147,7 +147,7 @@ nfs_file_release(struct inode *inode, struct file *filp) if (filp->f_mode & FMODE_WRITE) nfs_wb_all(dentry->d_inode); nfs_inc_stats(inode, NFSIOS_VFSRELEASE); - return NFS_PROTO(inode)->file_release(inode, filp); + return nfs_release(inode, filp); } /** diff --git a/fs/nfs/nfs3proc.c b/fs/nfs/nfs3proc.c index b9c2d995332b..1e750e4574a9 100644 --- a/fs/nfs/nfs3proc.c +++ b/fs/nfs/nfs3proc.c @@ -816,8 +816,6 @@ const struct nfs_rpc_ops nfs_v3_clientops = { .write_done = nfs3_write_done, .commit_setup = nfs3_proc_commit_setup, .commit_done = nfs3_commit_done, - .file_open = nfs_open, - .file_release = nfs_release, .lock = nfs3_proc_lock, .clear_acl_cache = nfs3_forget_cached_acls, }; diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c index 31a7e4c54a12..dfdd19a6d17e 100644 --- a/fs/nfs/nfs4proc.c +++ b/fs/nfs/nfs4proc.c @@ -3714,8 +3714,6 @@ const struct nfs_rpc_ops nfs_v4_clientops = { .write_done = nfs4_write_done, .commit_setup = nfs4_proc_commit_setup, .commit_done = nfs4_commit_done, - .file_open = nfs_open, - .file_release = nfs_release, .lock = nfs4_proc_lock, .clear_acl_cache = nfs4_zap_acl_attr, }; diff --git a/fs/nfs/proc.c b/fs/nfs/proc.c index c7605587d0eb..4dbb84df1b68 100644 --- a/fs/nfs/proc.c +++ b/fs/nfs/proc.c @@ -655,8 +655,6 @@ const struct nfs_rpc_ops nfs_v2_clientops = { .write_setup = nfs_proc_write_setup, .write_done = nfs_write_done, .commit_setup = nfs_proc_commit_setup, - .file_open = nfs_open, - .file_release = nfs_release, .lock = nfs_proc_lock, .lock_check_bounds = nfs_lock_check_bounds, }; diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index 8d780de371f0..8c77c11224d1 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -829,8 +829,6 @@ struct nfs_rpc_ops { int (*write_done) (struct rpc_task *, struct nfs_write_data *); void (*commit_setup) (struct nfs_write_data *, struct rpc_message *); int (*commit_done) (struct rpc_task *, struct nfs_write_data *); - int (*file_open) (struct inode *, struct file *); - int (*file_release) (struct inode *, struct file *); int (*lock)(struct file *, int, struct file_lock *); int (*lock_check_bounds)(const struct file_lock *); void (*clear_acl_cache)(struct inode *); -- cgit v1.2.3 From 34e8f92831cb5c40b3137e47a3daf4c09016ef02 Mon Sep 17 00:00:00 2001 From: Chuck Lever Date: Thu, 12 Jun 2008 12:32:25 -0400 Subject: NFS: Move fs/nfs/iostat.h to include/linux The fs/nfs/iostat.h header has definitions that were designed to be exposed to user space. Move these definitions under include/linux so user space can use the definitions in applications that read /proc/self/mountstats. Also address a handful of coding style issues called out by checkpatch.pl in fs/nfs/iostat.h. Signed-off-by: Chuck Lever Signed-off-by: Trond Myklebust --- fs/nfs/iostat.h | 119 +++++---------------------------------------- include/linux/nfs_iostat.h | 119 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+), 106 deletions(-) create mode 100644 include/linux/nfs_iostat.h (limited to 'include') diff --git a/fs/nfs/iostat.h b/fs/nfs/iostat.h index 6350ecbde589..2ec65e12bfed 100644 --- a/fs/nfs/iostat.h +++ b/fs/nfs/iostat.h @@ -5,135 +5,41 @@ * * Copyright (C) 2005, 2006 Chuck Lever * - * NFS client per-mount statistics provide information about the health of - * the NFS client and the health of each NFS mount point. Generally these - * are not for detailed problem diagnosis, but simply to indicate that there - * is a problem. - * - * These counters are not meant to be human-readable, but are meant to be - * integrated into system monitoring tools such as "sar" and "iostat". As - * such, the counters are sampled by the tools over time, and are never - * zeroed after a file system is mounted. Moving averages can be computed - * by the tools by taking the difference between two instantaneous samples - * and dividing that by the time between the samples. */ #ifndef _NFS_IOSTAT #define _NFS_IOSTAT -#define NFS_IOSTAT_VERS "1.0" - -/* - * NFS byte counters - * - * 1. SERVER - the number of payload bytes read from or written to the - * server by the NFS client via an NFS READ or WRITE request. - * - * 2. NORMAL - the number of bytes read or written by applications via - * the read(2) and write(2) system call interfaces. - * - * 3. DIRECT - the number of bytes read or written from files opened - * with the O_DIRECT flag. - * - * These counters give a view of the data throughput into and out of the NFS - * client. Comparing the number of bytes requested by an application with the - * number of bytes the client requests from the server can provide an - * indication of client efficiency (per-op, cache hits, etc). - * - * These counters can also help characterize which access methods are in - * use. DIRECT by itself shows whether there is any O_DIRECT traffic. - * NORMAL + DIRECT shows how much data is going through the system call - * interface. A large amount of SERVER traffic without much NORMAL or - * DIRECT traffic shows that applications are using mapped files. - * - * NFS page counters - * - * These count the number of pages read or written via nfs_readpage(), - * nfs_readpages(), or their write equivalents. - */ -enum nfs_stat_bytecounters { - NFSIOS_NORMALREADBYTES = 0, - NFSIOS_NORMALWRITTENBYTES, - NFSIOS_DIRECTREADBYTES, - NFSIOS_DIRECTWRITTENBYTES, - NFSIOS_SERVERREADBYTES, - NFSIOS_SERVERWRITTENBYTES, - NFSIOS_READPAGES, - NFSIOS_WRITEPAGES, - __NFSIOS_BYTESMAX, -}; - -/* - * NFS event counters - * - * These counters provide a low-overhead way of monitoring client activity - * without enabling NFS trace debugging. The counters show the rate at - * which VFS requests are made, and how often the client invalidates its - * data and attribute caches. This allows system administrators to monitor - * such things as how close-to-open is working, and answer questions such - * as "why are there so many GETATTR requests on the wire?" - * - * They also count anamolous events such as short reads and writes, silly - * renames due to close-after-delete, and operations that change the size - * of a file (such operations can often be the source of data corruption - * if applications aren't using file locking properly). - */ -enum nfs_stat_eventcounters { - NFSIOS_INODEREVALIDATE = 0, - NFSIOS_DENTRYREVALIDATE, - NFSIOS_DATAINVALIDATE, - NFSIOS_ATTRINVALIDATE, - NFSIOS_VFSOPEN, - NFSIOS_VFSLOOKUP, - NFSIOS_VFSACCESS, - NFSIOS_VFSUPDATEPAGE, - NFSIOS_VFSREADPAGE, - NFSIOS_VFSREADPAGES, - NFSIOS_VFSWRITEPAGE, - NFSIOS_VFSWRITEPAGES, - NFSIOS_VFSGETDENTS, - NFSIOS_VFSSETATTR, - NFSIOS_VFSFLUSH, - NFSIOS_VFSFSYNC, - NFSIOS_VFSLOCK, - NFSIOS_VFSRELEASE, - NFSIOS_CONGESTIONWAIT, - NFSIOS_SETATTRTRUNC, - NFSIOS_EXTENDWRITE, - NFSIOS_SILLYRENAME, - NFSIOS_SHORTREAD, - NFSIOS_SHORTWRITE, - NFSIOS_DELAY, - __NFSIOS_COUNTSMAX, -}; - -#ifdef __KERNEL__ - #include #include +#include struct nfs_iostats { unsigned long long bytes[__NFSIOS_BYTESMAX]; unsigned long events[__NFSIOS_COUNTSMAX]; } ____cacheline_aligned; -static inline void nfs_inc_server_stats(struct nfs_server *server, enum nfs_stat_eventcounters stat) +static inline void nfs_inc_server_stats(struct nfs_server *server, + enum nfs_stat_eventcounters stat) { struct nfs_iostats *iostats; int cpu; cpu = get_cpu(); iostats = per_cpu_ptr(server->io_stats, cpu); - iostats->events[stat] ++; + iostats->events[stat]++; put_cpu_no_resched(); } -static inline void nfs_inc_stats(struct inode *inode, enum nfs_stat_eventcounters stat) +static inline void nfs_inc_stats(struct inode *inode, + enum nfs_stat_eventcounters stat) { nfs_inc_server_stats(NFS_SERVER(inode), stat); } -static inline void nfs_add_server_stats(struct nfs_server *server, enum nfs_stat_bytecounters stat, unsigned long addend) +static inline void nfs_add_server_stats(struct nfs_server *server, + enum nfs_stat_bytecounters stat, + unsigned long addend) { struct nfs_iostats *iostats; int cpu; @@ -144,7 +50,9 @@ static inline void nfs_add_server_stats(struct nfs_server *server, enum nfs_stat put_cpu_no_resched(); } -static inline void nfs_add_stats(struct inode *inode, enum nfs_stat_bytecounters stat, unsigned long addend) +static inline void nfs_add_stats(struct inode *inode, + enum nfs_stat_bytecounters stat, + unsigned long addend) { nfs_add_server_stats(NFS_SERVER(inode), stat, addend); } @@ -160,5 +68,4 @@ static inline void nfs_free_iostats(struct nfs_iostats *stats) free_percpu(stats); } -#endif -#endif +#endif /* _NFS_IOSTAT */ diff --git a/include/linux/nfs_iostat.h b/include/linux/nfs_iostat.h new file mode 100644 index 000000000000..1cb9a3fed2b3 --- /dev/null +++ b/include/linux/nfs_iostat.h @@ -0,0 +1,119 @@ +/* + * User-space visible declarations for NFS client per-mount + * point statistics + * + * Copyright (C) 2005, 2006 Chuck Lever + * + * NFS client per-mount statistics provide information about the + * health of the NFS client and the health of each NFS mount point. + * Generally these are not for detailed problem diagnosis, but + * simply to indicate that there is a problem. + * + * These counters are not meant to be human-readable, but are meant + * to be integrated into system monitoring tools such as "sar" and + * "iostat". As such, the counters are sampled by the tools over + * time, and are never zeroed after a file system is mounted. + * Moving averages can be computed by the tools by taking the + * difference between two instantaneous samples and dividing that + * by the time between the samples. + */ + +#ifndef _LINUX_NFS_IOSTAT +#define _LINUX_NFS_IOSTAT + +#define NFS_IOSTAT_VERS "1.0" + +/* + * NFS byte counters + * + * 1. SERVER - the number of payload bytes read from or written + * to the server by the NFS client via an NFS READ or WRITE + * request. + * + * 2. NORMAL - the number of bytes read or written by applications + * via the read(2) and write(2) system call interfaces. + * + * 3. DIRECT - the number of bytes read or written from files + * opened with the O_DIRECT flag. + * + * These counters give a view of the data throughput into and out + * of the NFS client. Comparing the number of bytes requested by + * an application with the number of bytes the client requests from + * the server can provide an indication of client efficiency + * (per-op, cache hits, etc). + * + * These counters can also help characterize which access methods + * are in use. DIRECT by itself shows whether there is any O_DIRECT + * traffic. NORMAL + DIRECT shows how much data is going through + * the system call interface. A large amount of SERVER traffic + * without much NORMAL or DIRECT traffic shows that applications + * are using mapped files. + * + * NFS page counters + * + * These count the number of pages read or written via nfs_readpage(), + * nfs_readpages(), or their write equivalents. + * + * NB: When adding new byte counters, please include the measured + * units in the name of each byte counter to help users of this + * interface determine what exactly is being counted. + */ +enum nfs_stat_bytecounters { + NFSIOS_NORMALREADBYTES = 0, + NFSIOS_NORMALWRITTENBYTES, + NFSIOS_DIRECTREADBYTES, + NFSIOS_DIRECTWRITTENBYTES, + NFSIOS_SERVERREADBYTES, + NFSIOS_SERVERWRITTENBYTES, + NFSIOS_READPAGES, + NFSIOS_WRITEPAGES, + __NFSIOS_BYTESMAX, +}; + +/* + * NFS event counters + * + * These counters provide a low-overhead way of monitoring client + * activity without enabling NFS trace debugging. The counters + * show the rate at which VFS requests are made, and how often the + * client invalidates its data and attribute caches. This allows + * system administrators to monitor such things as how close-to-open + * is working, and answer questions such as "why are there so many + * GETATTR requests on the wire?" + * + * They also count anamolous events such as short reads and writes, + * silly renames due to close-after-delete, and operations that + * change the size of a file (such operations can often be the + * source of data corruption if applications aren't using file + * locking properly). + */ +enum nfs_stat_eventcounters { + NFSIOS_INODEREVALIDATE = 0, + NFSIOS_DENTRYREVALIDATE, + NFSIOS_DATAINVALIDATE, + NFSIOS_ATTRINVALIDATE, + NFSIOS_VFSOPEN, + NFSIOS_VFSLOOKUP, + NFSIOS_VFSACCESS, + NFSIOS_VFSUPDATEPAGE, + NFSIOS_VFSREADPAGE, + NFSIOS_VFSREADPAGES, + NFSIOS_VFSWRITEPAGE, + NFSIOS_VFSWRITEPAGES, + NFSIOS_VFSGETDENTS, + NFSIOS_VFSSETATTR, + NFSIOS_VFSFLUSH, + NFSIOS_VFSFSYNC, + NFSIOS_VFSLOCK, + NFSIOS_VFSRELEASE, + NFSIOS_CONGESTIONWAIT, + NFSIOS_SETATTRTRUNC, + NFSIOS_EXTENDWRITE, + NFSIOS_SILLYRENAME, + NFSIOS_SHORTREAD, + NFSIOS_SHORTWRITE, + NFSIOS_DELAY, + __NFSIOS_COUNTSMAX, +}; + +#endif /* _LINUX_NFS_IOSTAT */ -- cgit v1.2.3 From e468bae97d243fe0e1515abaa1f7d0edf1476ad0 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Fri, 13 Jun 2008 13:25:22 -0400 Subject: NFS: Allow redirtying of a completed unstable write. Currently, if an unstable write completes, we cannot redirty the page in order to reflect a new change in the page data until after we've sent a COMMIT request. This patch allows a page rewrite to proceed without the unnecessary COMMIT step, putting it immediately back onto the dirty page list, undoing the VM unstable write accounting, and removing the NFS_PAGE_TAG_COMMIT tag from the NFS radix tree. Signed-off-by: Trond Myklebust --- fs/nfs/write.c | 65 ++++++++++++++++++++++++------------------------ include/linux/nfs_page.h | 9 ++++--- 2 files changed, 38 insertions(+), 36 deletions(-) (limited to 'include') diff --git a/fs/nfs/write.c b/fs/nfs/write.c index 04f51e52e184..feca8c648766 100644 --- a/fs/nfs/write.c +++ b/fs/nfs/write.c @@ -242,12 +242,9 @@ static int nfs_page_async_flush(struct nfs_pageio_descriptor *pgio, return ret; spin_lock(&inode->i_lock); } - if (test_bit(PG_NEED_COMMIT, &req->wb_flags)) { - /* This request is marked for commit */ + if (test_bit(PG_CLEAN, &req->wb_flags)) { spin_unlock(&inode->i_lock); - nfs_clear_page_tag_locked(req); - nfs_pageio_complete(pgio); - return 0; + BUG(); } if (nfs_set_page_writeback(page) != 0) { spin_unlock(&inode->i_lock); @@ -391,19 +388,6 @@ nfs_mark_request_dirty(struct nfs_page *req) __set_page_dirty_nobuffers(req->wb_page); } -/* - * Check if a request is dirty - */ -static inline int -nfs_dirty_request(struct nfs_page *req) -{ - struct page *page = req->wb_page; - - if (page == NULL || test_bit(PG_NEED_COMMIT, &req->wb_flags)) - return 0; - return !PageWriteback(page); -} - #if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4) /* * Add a request to the inode's commit list. @@ -416,7 +400,7 @@ nfs_mark_request_commit(struct nfs_page *req) spin_lock(&inode->i_lock); nfsi->ncommit++; - set_bit(PG_NEED_COMMIT, &(req)->wb_flags); + set_bit(PG_CLEAN, &(req)->wb_flags); radix_tree_tag_set(&nfsi->nfs_page_tree, req->wb_index, NFS_PAGE_TAG_COMMIT); @@ -426,6 +410,19 @@ nfs_mark_request_commit(struct nfs_page *req) __mark_inode_dirty(inode, I_DIRTY_DATASYNC); } +static int +nfs_clear_request_commit(struct nfs_page *req) +{ + struct page *page = req->wb_page; + + if (test_and_clear_bit(PG_CLEAN, &(req)->wb_flags)) { + dec_zone_page_state(page, NR_UNSTABLE_NFS); + dec_bdi_stat(page->mapping->backing_dev_info, BDI_RECLAIMABLE); + return 1; + } + return 0; +} + static inline int nfs_write_need_commit(struct nfs_write_data *data) { @@ -435,7 +432,7 @@ int nfs_write_need_commit(struct nfs_write_data *data) static inline int nfs_reschedule_unstable_write(struct nfs_page *req) { - if (test_bit(PG_NEED_COMMIT, &req->wb_flags)) { + if (test_and_clear_bit(PG_NEED_COMMIT, &req->wb_flags)) { nfs_mark_request_commit(req); return 1; } @@ -451,6 +448,12 @@ nfs_mark_request_commit(struct nfs_page *req) { } +static inline int +nfs_clear_request_commit(struct nfs_page *req) +{ + return 0; +} + static inline int nfs_write_need_commit(struct nfs_write_data *data) { @@ -508,11 +511,8 @@ static void nfs_cancel_commit_list(struct list_head *head) while(!list_empty(head)) { req = nfs_list_entry(head->next); - dec_zone_page_state(req->wb_page, NR_UNSTABLE_NFS); - dec_bdi_stat(req->wb_page->mapping->backing_dev_info, - BDI_RECLAIMABLE); nfs_list_remove_request(req); - clear_bit(PG_NEED_COMMIT, &(req)->wb_flags); + nfs_clear_request_commit(req); nfs_inode_remove_request(req); nfs_unlock_request(req); } @@ -584,8 +584,7 @@ static struct nfs_page *nfs_try_to_update_request(struct inode *inode, * Note: nfs_flush_incompatible() will already * have flushed out requests having wrong owners. */ - if (!nfs_dirty_request(req) - || offset > rqend + if (offset > rqend || end < req->wb_offset) goto out_flushme; @@ -601,6 +600,10 @@ static struct nfs_page *nfs_try_to_update_request(struct inode *inode, spin_lock(&inode->i_lock); } + if (nfs_clear_request_commit(req)) + radix_tree_tag_clear(&NFS_I(inode)->nfs_page_tree, + req->wb_index, NFS_PAGE_TAG_COMMIT); + /* Okay, the request matches. Update the region */ if (offset < req->wb_offset) { req->wb_offset = offset; @@ -682,8 +685,7 @@ int nfs_flush_incompatible(struct file *file, struct page *page) req = nfs_page_find_request(page); if (req == NULL) return 0; - do_flush = req->wb_page != page || req->wb_context != ctx - || !nfs_dirty_request(req); + do_flush = req->wb_page != page || req->wb_context != ctx; nfs_release_request(req); if (!do_flush) return 0; @@ -1288,10 +1290,7 @@ static void nfs_commit_release(void *calldata) while (!list_empty(&data->pages)) { req = nfs_list_entry(data->pages.next); nfs_list_remove_request(req); - clear_bit(PG_NEED_COMMIT, &(req)->wb_flags); - dec_zone_page_state(req->wb_page, NR_UNSTABLE_NFS); - dec_bdi_stat(req->wb_page->mapping->backing_dev_info, - BDI_RECLAIMABLE); + nfs_clear_request_commit(req); dprintk("NFS: commit (%s/%lld %d@%lld)", req->wb_context->path.dentry->d_inode->i_sb->s_id, @@ -1467,7 +1466,7 @@ int nfs_wb_page_cancel(struct inode *inode, struct page *page) req = nfs_page_find_request(page); if (req == NULL) goto out; - if (test_bit(PG_NEED_COMMIT, &req->wb_flags)) { + if (test_bit(PG_CLEAN, &req->wb_flags)) { nfs_release_request(req); break; } diff --git a/include/linux/nfs_page.h b/include/linux/nfs_page.h index a1676e19e491..3c60685d972b 100644 --- a/include/linux/nfs_page.h +++ b/include/linux/nfs_page.h @@ -27,9 +27,12 @@ /* * Valid flags for a dirty buffer */ -#define PG_BUSY 0 -#define PG_NEED_COMMIT 1 -#define PG_NEED_RESCHED 2 +enum { + PG_BUSY = 0, + PG_CLEAN, + PG_NEED_COMMIT, + PG_NEED_RESCHED, +}; struct nfs_inode; struct nfs_page { -- cgit v1.2.3 From ce3b7e1906ebbe96753fe090b36de6ffb8e0e0e7 Mon Sep 17 00:00:00 2001 From: Chuck Lever Date: Mon, 23 Jun 2008 12:36:53 -0400 Subject: NFS: Add string length argument to nfs_parse_server_address To make nfs_parse_server_address() more generally useful, allow it to accept input strings that are not terminated with '\0'. Signed-off-by: Chuck Lever Signed-off-by: Trond Myklebust --- fs/nfs/super.c | 100 +++++++++++++++++++++++++++++++++++---------------- include/linux/inet.h | 7 ++++ 2 files changed, 77 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/fs/nfs/super.c b/fs/nfs/super.c index ea4abd266a7a..d27aa1db0074 100644 --- a/fs/nfs/super.c +++ b/fs/nfs/super.c @@ -705,38 +705,76 @@ static int nfs_verify_server_address(struct sockaddr *addr) return 0; } -/* - * Parse string addresses passed in via a mount option, - * and construct a sockaddr based on the result. - * - * If address parsing fails, set the sockaddr's address - * family to AF_UNSPEC to force nfs_verify_server_address() - * to punt the mount. - */ -static void nfs_parse_server_address(char *value, - struct sockaddr *sap, - size_t *len) +static void nfs_parse_ipv4_address(char *string, size_t str_len, + struct sockaddr *sap, size_t *addr_len) { - if (strchr(value, ':')) { - struct sockaddr_in6 *ap = (struct sockaddr_in6 *)sap; - u8 *addr = (u8 *)&ap->sin6_addr.in6_u; + struct sockaddr_in *sin = (struct sockaddr_in *)sap; + u8 *addr = (u8 *)&sin->sin_addr.s_addr; - ap->sin6_family = AF_INET6; - *len = sizeof(*ap); - if (in6_pton(value, -1, addr, '\0', NULL)) + if (str_len <= INET_ADDRSTRLEN) { + dfprintk(MOUNT, "NFS: parsing IPv4 address %*s\n", + (int)str_len, string); + + sin->sin_family = AF_INET; + *addr_len = sizeof(*sin); + if (in4_pton(string, str_len, addr, '\0', NULL)) return; - } else { - struct sockaddr_in *ap = (struct sockaddr_in *)sap; - u8 *addr = (u8 *)&ap->sin_addr.s_addr; + } + + sap->sa_family = AF_UNSPEC; + *addr_len = 0; +} + +#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) +static void nfs_parse_ipv6_address(char *string, size_t str_len, + struct sockaddr *sap, size_t *addr_len) +{ + struct sockaddr_in6 *sin6 = (struct sockaddr_in6 *)sap; + u8 *addr = (u8 *)&sin6->sin6_addr.in6_u; + + if (str_len <= INET6_ADDRSTRLEN) { + dfprintk(MOUNT, "NFS: parsing IPv6 address %*s\n", + (int)str_len, string); - ap->sin_family = AF_INET; - *len = sizeof(*ap); - if (in4_pton(value, -1, addr, '\0', NULL)) + sin6->sin6_family = AF_INET6; + *addr_len = sizeof(*sin6); + if (in6_pton(string, str_len, addr, '\0', NULL)) return; } sap->sa_family = AF_UNSPEC; - *len = 0; + *addr_len = 0; +} +#else +static void nfs_parse_ipv6_address(char *string, size_t str_len, + struct sockaddr *sap, size_t *addr_len) +{ + sap->sa_family = AF_UNSPEC; + *addr_len = 0; +} +#endif + +/* + * Construct a sockaddr based on the contents of a string that contains + * an IP address in presentation format. + * + * If there is a problem constructing the new sockaddr, set the address + * family to AF_UNSPEC. + */ +static void nfs_parse_ip_address(char *string, size_t str_len, + struct sockaddr *sap, size_t *addr_len) +{ + unsigned int i, colons; + + colons = 0; + for (i = 0; i < str_len; i++) + if (string[i] == ':') + colons++; + + if (colons >= 2) + nfs_parse_ipv6_address(string, str_len, sap, addr_len); + else + nfs_parse_ipv4_address(string, str_len, sap, addr_len); } /* @@ -1070,9 +1108,10 @@ static int nfs_parse_mount_options(char *raw, string = match_strdup(args); if (string == NULL) goto out_nomem; - nfs_parse_server_address(string, (struct sockaddr *) - &mnt->nfs_server.address, - &mnt->nfs_server.addrlen); + nfs_parse_ip_address(string, strlen(string), + (struct sockaddr *) + &mnt->nfs_server.address, + &mnt->nfs_server.addrlen); kfree(string); break; case Opt_clientaddr: @@ -1093,9 +1132,10 @@ static int nfs_parse_mount_options(char *raw, string = match_strdup(args); if (string == NULL) goto out_nomem; - nfs_parse_server_address(string, (struct sockaddr *) - &mnt->mount_server.address, - &mnt->mount_server.addrlen); + nfs_parse_ip_address(string, strlen(string), + (struct sockaddr *) + &mnt->mount_server.address, + &mnt->mount_server.addrlen); kfree(string); break; diff --git a/include/linux/inet.h b/include/linux/inet.h index 1354080cf8cf..4cca05c9678e 100644 --- a/include/linux/inet.h +++ b/include/linux/inet.h @@ -44,6 +44,13 @@ #include +/* + * These mimic similar macros defined in user-space for inet_ntop(3). + * See /usr/include/netinet/in.h . + */ +#define INET_ADDRSTRLEN (16) +#define INET6_ADDRSTRLEN (48) + extern __be32 in_aton(const char *str); extern int in4_pton(const char *src, int srclen, u8 *dst, int delim, const char **end); extern int in6_pton(const char *src, int srclen, u8 *dst, int delim, const char **end); -- cgit v1.2.3 From 259875efed06d6936f54c9a264e868937f1bc217 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Wed, 2 Jul 2008 14:43:47 -0400 Subject: NFS: set transport defaults after mount option parsing is finished Move the UDP/TCP default timeo/retrans settings for text mounts to nfs_init_timeout_values(), which was were they were always being initialised (and sanity checked) for binary mounts. Document the default timeout values using appropriate #defines. Ensure that we initialise and sanity check the transport protocols that may have been specified by the user. Signed-off-by: Trond Myklebust --- fs/nfs/client.c | 13 ++++++----- fs/nfs/super.c | 60 +++++++++++++++++++++++++++++++++++--------------- include/linux/nfs_fs.h | 5 +++++ 3 files changed, 55 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/fs/nfs/client.c b/fs/nfs/client.c index f2a092ca69b5..5ee23e7058b3 100644 --- a/fs/nfs/client.c +++ b/fs/nfs/client.c @@ -431,14 +431,14 @@ static void nfs_init_timeout_values(struct rpc_timeout *to, int proto, { to->to_initval = timeo * HZ / 10; to->to_retries = retrans; - if (!to->to_retries) - to->to_retries = 2; switch (proto) { case XPRT_TRANSPORT_TCP: case XPRT_TRANSPORT_RDMA: + if (to->to_retries == 0) + to->to_retries = NFS_DEF_TCP_RETRANS; if (to->to_initval == 0) - to->to_initval = 60 * HZ; + to->to_initval = NFS_DEF_TCP_TIMEO * HZ / 10; if (to->to_initval > NFS_MAX_TCP_TIMEOUT) to->to_initval = NFS_MAX_TCP_TIMEOUT; to->to_increment = to->to_initval; @@ -450,14 +450,17 @@ static void nfs_init_timeout_values(struct rpc_timeout *to, int proto, to->to_exponential = 0; break; case XPRT_TRANSPORT_UDP: - default: + if (to->to_retries == 0) + to->to_retries = NFS_DEF_UDP_RETRANS; if (!to->to_initval) - to->to_initval = 11 * HZ / 10; + to->to_initval = NFS_DEF_UDP_TIMEO * HZ / 10; if (to->to_initval > NFS_MAX_UDP_TIMEOUT) to->to_initval = NFS_MAX_UDP_TIMEOUT; to->to_maxval = NFS_MAX_UDP_TIMEOUT; to->to_exponential = 1; break; + default: + BUG(); } } diff --git a/fs/nfs/super.c b/fs/nfs/super.c index 73a8e5970f02..9c1a960f5b94 100644 --- a/fs/nfs/super.c +++ b/fs/nfs/super.c @@ -816,6 +816,43 @@ static void nfs_parse_ip_address(char *string, size_t str_len, nfs_parse_ipv4_address(string, str_len, sap, addr_len); } +/* + * Sanity check the NFS transport protocol. + * + */ +static void nfs_validate_transport_protocol(struct nfs_parsed_mount_data *mnt) +{ + switch (mnt->nfs_server.protocol) { + case XPRT_TRANSPORT_UDP: + case XPRT_TRANSPORT_TCP: + case XPRT_TRANSPORT_RDMA: + break; + default: + mnt->nfs_server.protocol = XPRT_TRANSPORT_TCP; + } +} + +/* + * For text based NFSv2/v3 mounts, the mount protocol transport default + * settings should depend upon the specified NFS transport. + */ +static void nfs_set_mount_transport_protocol(struct nfs_parsed_mount_data *mnt) +{ + nfs_validate_transport_protocol(mnt); + + if (mnt->mount_server.protocol == XPRT_TRANSPORT_UDP || + mnt->mount_server.protocol == XPRT_TRANSPORT_TCP) + return; + switch (mnt->nfs_server.protocol) { + case XPRT_TRANSPORT_UDP: + mnt->mount_server.protocol = XPRT_TRANSPORT_UDP; + break; + case XPRT_TRANSPORT_TCP: + case XPRT_TRANSPORT_RDMA: + mnt->mount_server.protocol = XPRT_TRANSPORT_TCP; + } +} + /* * Error-check and convert a string of mount options from user space into * a data structure @@ -896,20 +933,14 @@ static int nfs_parse_mount_options(char *raw, case Opt_udp: mnt->flags &= ~NFS_MOUNT_TCP; mnt->nfs_server.protocol = XPRT_TRANSPORT_UDP; - mnt->timeo = 7; - mnt->retrans = 5; break; case Opt_tcp: mnt->flags |= NFS_MOUNT_TCP; mnt->nfs_server.protocol = XPRT_TRANSPORT_TCP; - mnt->timeo = 600; - mnt->retrans = 2; break; case Opt_rdma: mnt->flags |= NFS_MOUNT_TCP; /* for side protocols */ mnt->nfs_server.protocol = XPRT_TRANSPORT_RDMA; - mnt->timeo = 600; - mnt->retrans = 2; break; case Opt_acl: mnt->flags &= ~NFS_MOUNT_NOACL; @@ -1103,21 +1134,15 @@ static int nfs_parse_mount_options(char *raw, case Opt_xprt_udp: mnt->flags &= ~NFS_MOUNT_TCP; mnt->nfs_server.protocol = XPRT_TRANSPORT_UDP; - mnt->timeo = 7; - mnt->retrans = 5; break; case Opt_xprt_tcp: mnt->flags |= NFS_MOUNT_TCP; mnt->nfs_server.protocol = XPRT_TRANSPORT_TCP; - mnt->timeo = 600; - mnt->retrans = 2; break; case Opt_xprt_rdma: /* vector side protocols to TCP */ mnt->flags |= NFS_MOUNT_TCP; mnt->nfs_server.protocol = XPRT_TRANSPORT_RDMA; - mnt->timeo = 600; - mnt->retrans = 2; break; default: goto out_unrec_xprt; @@ -1438,14 +1463,11 @@ static int nfs_validate_mount_data(void *options, args->flags = (NFS_MOUNT_VER3 | NFS_MOUNT_TCP); args->rsize = NFS_MAX_FILE_IO_SIZE; args->wsize = NFS_MAX_FILE_IO_SIZE; - args->timeo = 600; - args->retrans = 2; args->acregmin = 3; args->acregmax = 60; args->acdirmin = 30; args->acdirmax = 60; args->mount_server.port = 0; /* autobind unless user sets port */ - args->mount_server.protocol = XPRT_TRANSPORT_UDP; args->nfs_server.port = 0; /* autobind unless user sets port */ args->nfs_server.protocol = XPRT_TRANSPORT_TCP; @@ -1546,6 +1568,8 @@ static int nfs_validate_mount_data(void *options, &args->nfs_server.address)) goto out_no_address; + nfs_set_mount_transport_protocol(args); + status = nfs_parse_devname(dev_name, &args->nfs_server.hostname, PAGE_SIZE, @@ -2095,14 +2119,11 @@ static int nfs4_validate_mount_data(void *options, args->rsize = NFS_MAX_FILE_IO_SIZE; args->wsize = NFS_MAX_FILE_IO_SIZE; - args->timeo = 600; - args->retrans = 2; args->acregmin = 3; args->acregmax = 60; args->acdirmin = 30; args->acdirmax = 60; args->nfs_server.port = NFS_PORT; /* 2049 unless user set port= */ - args->nfs_server.protocol = XPRT_TRANSPORT_TCP; switch (data->version) { case 1: @@ -2163,6 +2184,7 @@ static int nfs4_validate_mount_data(void *options, args->acdirmin = data->acdirmin; args->acdirmax = data->acdirmax; args->nfs_server.protocol = data->proto; + nfs_validate_transport_protocol(args); break; default: { @@ -2175,6 +2197,8 @@ static int nfs4_validate_mount_data(void *options, &args->nfs_server.address)) return -EINVAL; + nfs_validate_transport_protocol(args); + switch (args->auth_flavor_len) { case 0: args->auth_flavors[0] = RPC_AUTH_UNIX; diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index 27d6a8d98cef..830d9cc8cdce 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -12,6 +12,11 @@ #include /* Default timeout values */ +#define NFS_DEF_UDP_TIMEO (11) +#define NFS_DEF_UDP_RETRANS (3) +#define NFS_DEF_TCP_TIMEO (600) +#define NFS_DEF_TCP_RETRANS (2) + #define NFS_MAX_UDP_TIMEOUT (60*HZ) #define NFS_MAX_TCP_TIMEOUT (600*HZ) -- cgit v1.2.3 From 0e0cab744b17a70ef0f08d818d66935feade7cad Mon Sep 17 00:00:00 2001 From: Chuck Lever Date: Thu, 26 Jun 2008 17:47:12 -0400 Subject: NFS: use documenting macro constants for initializing ac{reg, dir}{min, max} Clean up. Signed-off-by: Chuck Lever Signed-off-by: Trond Myklebust --- fs/nfs/nfsroot.c | 8 ++++---- fs/nfs/super.c | 24 ++++++++++++------------ include/linux/nfs_fs.h | 5 +++++ 3 files changed, 21 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/fs/nfs/nfsroot.c b/fs/nfs/nfsroot.c index 15afe3a6c5be..46763d1cd397 100644 --- a/fs/nfs/nfsroot.c +++ b/fs/nfs/nfsroot.c @@ -295,10 +295,10 @@ static int __init root_nfs_name(char *name) nfs_data.flags = NFS_MOUNT_NONLM; /* No lockd in nfs root yet */ nfs_data.rsize = NFS_DEF_FILE_IO_SIZE; nfs_data.wsize = NFS_DEF_FILE_IO_SIZE; - nfs_data.acregmin = 3; - nfs_data.acregmax = 60; - nfs_data.acdirmin = 30; - nfs_data.acdirmax = 60; + nfs_data.acregmin = NFS_DEF_ACREGMIN; + nfs_data.acregmax = NFS_DEF_ACREGMAX; + nfs_data.acdirmin = NFS_DEF_ACDIRMIN; + nfs_data.acdirmax = NFS_DEF_ACDIRMAX; strcpy(buf, NFS_ROOT); /* Process options received from the remote server */ diff --git a/fs/nfs/super.c b/fs/nfs/super.c index de424d2f3155..ebed63e0ff8e 100644 --- a/fs/nfs/super.c +++ b/fs/nfs/super.c @@ -518,13 +518,13 @@ static void nfs_show_mount_options(struct seq_file *m, struct nfs_server *nfss, if (nfss->bsize != 0) seq_printf(m, ",bsize=%u", nfss->bsize); seq_printf(m, ",namlen=%u", nfss->namelen); - if (nfss->acregmin != 3*HZ || showdefaults) + if (nfss->acregmin != NFS_DEF_ACREGMIN*HZ || showdefaults) seq_printf(m, ",acregmin=%u", nfss->acregmin/HZ); - if (nfss->acregmax != 60*HZ || showdefaults) + if (nfss->acregmax != NFS_DEF_ACREGMAX*HZ || showdefaults) seq_printf(m, ",acregmax=%u", nfss->acregmax/HZ); - if (nfss->acdirmin != 30*HZ || showdefaults) + if (nfss->acdirmin != NFS_DEF_ACDIRMIN*HZ || showdefaults) seq_printf(m, ",acdirmin=%u", nfss->acdirmin/HZ); - if (nfss->acdirmax != 60*HZ || showdefaults) + if (nfss->acdirmax != NFS_DEF_ACDIRMAX*HZ || showdefaults) seq_printf(m, ",acdirmax=%u", nfss->acdirmax/HZ); for (nfs_infop = nfs_info; nfs_infop->flag; nfs_infop++) { if (nfss->flags & nfs_infop->flag) @@ -1460,10 +1460,10 @@ static int nfs_validate_mount_data(void *options, args->flags = (NFS_MOUNT_VER3 | NFS_MOUNT_TCP); args->rsize = NFS_MAX_FILE_IO_SIZE; args->wsize = NFS_MAX_FILE_IO_SIZE; - args->acregmin = 3; - args->acregmax = 60; - args->acdirmin = 30; - args->acdirmax = 60; + args->acregmin = NFS_DEF_ACREGMIN; + args->acregmax = NFS_DEF_ACREGMAX; + args->acdirmin = NFS_DEF_ACDIRMIN; + args->acdirmax = NFS_DEF_ACDIRMAX; args->mount_server.port = 0; /* autobind unless user sets port */ args->nfs_server.port = 0; /* autobind unless user sets port */ args->nfs_server.protocol = XPRT_TRANSPORT_TCP; @@ -2119,10 +2119,10 @@ static int nfs4_validate_mount_data(void *options, args->rsize = NFS_MAX_FILE_IO_SIZE; args->wsize = NFS_MAX_FILE_IO_SIZE; - args->acregmin = 3; - args->acregmax = 60; - args->acdirmin = 30; - args->acdirmax = 60; + args->acregmin = NFS_DEF_ACREGMIN; + args->acregmax = NFS_DEF_ACREGMAX; + args->acdirmin = NFS_DEF_ACDIRMIN; + args->acdirmax = NFS_DEF_ACDIRMAX; args->nfs_server.port = NFS_PORT; /* 2049 unless user set port= */ switch (data->version) { diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index 830d9cc8cdce..29d261918734 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -20,6 +20,11 @@ #define NFS_MAX_UDP_TIMEOUT (60*HZ) #define NFS_MAX_TCP_TIMEOUT (600*HZ) +#define NFS_DEF_ACREGMIN (3) +#define NFS_DEF_ACREGMAX (60) +#define NFS_DEF_ACDIRMIN (30) +#define NFS_DEF_ACDIRMAX (60) + /* * When flushing a cluster of dirty pages, there can be different * strategies: -- cgit v1.2.3 From 1bc54c03117b90716e0dedd7abb2a20405de65df Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 8 Jul 2008 15:54:40 +1000 Subject: powerpc: rework 4xx PTE access and TLB miss This is some preliminary work to improve TLB management on SW loaded TLB powerpc platforms. This introduce support for non-atomic PTE operations in pgtable-ppc32.h and removes write back to the PTE from the TLB miss handlers. In addition, the DSI interrupt code no longer tries to fixup write permission, this is left to generic code, and _PAGE_HWWRITE is gone. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Josh Boyer --- arch/powerpc/kernel/head_44x.S | 286 ++++++++++++------------------------ arch/powerpc/kernel/head_booke.h | 8 + arch/powerpc/mm/44x_mmu.c | 29 +++- arch/powerpc/mm/fault.c | 3 +- include/asm-powerpc/pgtable-ppc32.h | 61 ++++++-- 5 files changed, 180 insertions(+), 207 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 2944529e8bf9..f3a1ea9d7fe4 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -293,119 +293,9 @@ interrupt_base: MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception) /* Data Storage Interrupt */ - START_EXCEPTION(DataStorage) - mtspr SPRN_SPRG0, r10 /* Save some working registers */ - mtspr SPRN_SPRG1, r11 - mtspr SPRN_SPRG4W, r12 - mtspr SPRN_SPRG5W, r13 - mfcr r11 - mtspr SPRN_SPRG7W, r11 - - /* - * Check if it was a store fault, if not then bail - * because a user tried to access a kernel or - * read-protected page. Otherwise, get the - * offending address and handle it. - */ - mfspr r10, SPRN_ESR - andis. r10, r10, ESR_ST@h - beq 2f - - mfspr r10, SPRN_DEAR /* Get faulting address */ - - /* If we are faulting a kernel address, we have to use the - * kernel page tables. - */ - lis r11, PAGE_OFFSET@h - cmplw r10, r11 - blt+ 3f - lis r11, swapper_pg_dir@h - ori r11, r11, swapper_pg_dir@l - - mfspr r12,SPRN_MMUCR - rlwinm r12,r12,0,0,23 /* Clear TID */ - - b 4f - - /* Get the PGD for the current thread */ -3: - mfspr r11,SPRN_SPRG3 - lwz r11,PGDIR(r11) - - /* Load PID into MMUCR TID */ - mfspr r12,SPRN_MMUCR /* Get MMUCR */ - mfspr r13,SPRN_PID /* Get PID */ - rlwimi r12,r13,0,24,31 /* Set TID */ - -4: - mtspr SPRN_MMUCR,r12 - - rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ - lwzx r11, r12, r11 /* Get pgd/pmd entry */ - rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ - beq 2f /* Bail if no table */ - - rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ - lwz r11, 4(r12) /* Get pte entry */ - - andi. r13, r11, _PAGE_RW /* Is it writeable? */ - beq 2f /* Bail if not */ - - /* Update 'changed'. - */ - ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE - stw r11, 4(r12) /* Update Linux page table */ - - li r13, PPC44x_TLB_SR@l /* Set SR */ - rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */ - rlwimi r13, r11, 0, 30, 30 /* SW = _PAGE_RW */ - rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */ - rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */ - rlwimi r12, r11, 29, 30, 30 /* (_PAGE_USER>>3)->r12 */ - and r12, r12, r11 /* HWEXEC/RW & USER */ - rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */ - rlwimi r13, r12, 3, 27, 27 /* UW = RW & USER */ - - rlwimi r11,r13,0,26,31 /* Insert static perms */ - - /* - * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added - * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see - * include/asm-powerpc/pgtable-ppc32.h for details). - */ - rlwinm r11,r11,0,20,10 - - /* find the TLB index that caused the fault. It has to be here. */ - tlbsx r10, 0, r10 - - tlbwe r11, r10, PPC44x_TLB_ATTRIB /* Write ATTRIB */ - - /* Done...restore registers and get out of here. - */ - mfspr r11, SPRN_SPRG7R - mtcr r11 - mfspr r13, SPRN_SPRG5R - mfspr r12, SPRN_SPRG4R + DATA_STORAGE_EXCEPTION - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - rfi /* Force context change */ - -2: - /* - * The bailout. Restore registers to pre-exception conditions - * and call the heavyweights to help us out. - */ - mfspr r11, SPRN_SPRG7R - mtcr r11 - mfspr r13, SPRN_SPRG5R - mfspr r12, SPRN_SPRG4R - - mfspr r11, SPRN_SPRG1 - mfspr r10, SPRN_SPRG0 - b data_access - - /* Instruction Storage Interrupt */ + /* Instruction Storage Interrupt */ INSTRUCTION_STORAGE_EXCEPTION /* External Input Interrupt */ @@ -423,7 +313,6 @@ interrupt_base: #else EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) #endif - /* System Call Interrupt */ START_EXCEPTION(SystemCall) NORMAL_EXCEPTION_PROLOG @@ -484,18 +373,57 @@ interrupt_base: 4: mtspr SPRN_MMUCR,r12 + /* Mask of required permission bits. Note that while we + * do copy ESR:ST to _PAGE_RW position as trying to write + * to an RO page is pretty common, we don't do it with + * _PAGE_DIRTY. We could do it, but it's a fairly rare + * event so I'd rather take the overhead when it happens + * rather than adding an instruction here. We should measure + * whether the whole thing is worth it in the first place + * as we could avoid loading SPRN_ESR completely in the first + * place... + * + * TODO: Is it worth doing that mfspr & rlwimi in the first + * place or can we save a couple of instructions here ? + */ + mfspr r12,SPRN_ESR + li r13,_PAGE_PRESENT|_PAGE_ACCESSED + rlwimi r13,r12,10,30,30 + + /* Load the PTE */ rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ lwzx r11, r12, r11 /* Get pgd/pmd entry */ rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ beq 2f /* Bail if no table */ rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ - lwz r11, 4(r12) /* Get pte entry */ - andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ - beq 2f /* Bail if not present */ + lwz r11, 0(r12) /* Get high word of pte entry */ + lwz r12, 4(r12) /* Get low word of pte entry */ - ori r11, r11, _PAGE_ACCESSED - stw r11, 4(r12) + lis r10,tlb_44x_index@ha + + andc. r13,r13,r12 /* Check permission */ + + /* Load the next available TLB index */ + lwz r13,tlb_44x_index@l(r10) + + bne 2f /* Bail if permission mismach */ + + /* Increment, rollover, and store TLB index */ + addi r13,r13,1 + + /* Compare with watermark (instruction gets patched) */ + .globl tlb_44x_patch_hwater_D +tlb_44x_patch_hwater_D: + cmpwi 0,r13,1 /* reserve entries */ + ble 5f + li r13,0 +5: + /* Store the next available TLB index */ + stw r13,tlb_44x_index@l(r10) + + /* Re-load the faulting address */ + mfspr r10,SPRN_DEAR /* Jump to common tlb load */ b finish_tlb_load @@ -510,7 +438,7 @@ interrupt_base: mfspr r12, SPRN_SPRG4R mfspr r11, SPRN_SPRG1 mfspr r10, SPRN_SPRG0 - b data_access + b DataStorage /* Instruction TLB Error Interrupt */ /* @@ -554,18 +482,42 @@ interrupt_base: 4: mtspr SPRN_MMUCR,r12 + /* Make up the required permissions */ + li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC + rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ lwzx r11, r12, r11 /* Get pgd/pmd entry */ rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ beq 2f /* Bail if no table */ rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ - lwz r11, 4(r12) /* Get pte entry */ - andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ - beq 2f /* Bail if not present */ + lwz r11, 0(r12) /* Get high word of pte entry */ + lwz r12, 4(r12) /* Get low word of pte entry */ - ori r11, r11, _PAGE_ACCESSED - stw r11, 4(r12) + lis r10,tlb_44x_index@ha + + andc. r13,r13,r12 /* Check permission */ + + /* Load the next available TLB index */ + lwz r13,tlb_44x_index@l(r10) + + bne 2f /* Bail if permission mismach */ + + /* Increment, rollover, and store TLB index */ + addi r13,r13,1 + + /* Compare with watermark (instruction gets patched) */ + .globl tlb_44x_patch_hwater_I +tlb_44x_patch_hwater_I: + cmpwi 0,r13,1 /* reserve entries */ + ble 5f + li r13,0 +5: + /* Store the next available TLB index */ + stw r13,tlb_44x_index@l(r10) + + /* Re-load the faulting address */ + mfspr r10,SPRN_SRR0 /* Jump to common TLB load point */ b finish_tlb_load @@ -587,86 +539,40 @@ interrupt_base: /* * Local functions - */ - /* - * Data TLB exceptions will bail out to this point - * if they can't resolve the lightweight TLB fault. - */ -data_access: - NORMAL_EXCEPTION_PROLOG - mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ - stw r5,_ESR(r11) - mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ - EXC_XFER_EE_LITE(0x0300, handle_page_fault) + */ /* * Both the instruction and data TLB miss get to this * point to load the TLB. * r10 - EA of fault - * r11 - available to use - * r12 - Pointer to the 64-bit PTE - * r13 - available to use + * r11 - PTE high word value + * r12 - PTE low word value + * r13 - TLB index * MMUCR - loaded with proper value when we get here * Upon exit, we reload everything and RFI. */ finish_tlb_load: - /* - * We set execute, because we don't have the granularity to - * properly set this at the page level (Linux problem). - * If shared is set, we cause a zero PID->TID load. - * Many of these bits are software only. Bits we don't set - * here we (properly should) assume have the appropriate value. - */ - - /* Load the next available TLB index */ - lis r13, tlb_44x_index@ha - lwz r13, tlb_44x_index@l(r13) - /* Load the TLB high watermark */ - lis r11, tlb_44x_hwater@ha - lwz r11, tlb_44x_hwater@l(r11) - - /* Increment, rollover, and store TLB index */ - addi r13, r13, 1 - cmpw 0, r13, r11 /* reserve entries */ - ble 7f - li r13, 0 -7: - /* Store the next available TLB index */ - lis r11, tlb_44x_index@ha - stw r13, tlb_44x_index@l(r11) - - lwz r11, 0(r12) /* Get MS word of PTE */ - lwz r12, 4(r12) /* Get LS word of PTE */ - rlwimi r11, r12, 0, 0 , 19 /* Insert RPN */ - tlbwe r11, r13, PPC44x_TLB_XLAT /* Write XLAT */ + /* Combine RPN & ERPN an write WS 0 */ + rlwimi r11,r12,0,0,19 + tlbwe r11,r13,PPC44x_TLB_XLAT /* - * Create PAGEID. This is the faulting address, + * Create WS1. This is the faulting address (EPN), * page size, and valid flag. */ - li r11, PPC44x_TLB_VALID | PPC44x_TLB_4K - rlwimi r10, r11, 0, 20, 31 /* Insert valid and page size */ - tlbwe r10, r13, PPC44x_TLB_PAGEID /* Write PAGEID */ - - li r10, PPC44x_TLB_SR@l /* Set SR */ - rlwimi r10, r12, 0, 30, 30 /* Set SW = _PAGE_RW */ - rlwimi r10, r12, 29, 29, 29 /* SX = _PAGE_HWEXEC */ - rlwimi r10, r12, 29, 28, 28 /* UR = _PAGE_USER */ - rlwimi r11, r12, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */ - and r11, r12, r11 /* HWEXEC & USER */ - rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */ - - rlwimi r12, r10, 0, 26, 31 /* Insert static perms */ - - /* - * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added - * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see - * include/asm-powerpc/pgtable-ppc32.h for details). - */ - rlwinm r12, r12, 0, 20, 10 - - tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */ + li r11,PPC44x_TLB_VALID | PPC44x_TLB_4K + rlwimi r10,r11,0,20,31 /* Insert valid and page size*/ + tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */ + + /* And WS 2 */ + li r10,0xf85 /* Mask to apply from PTE */ + rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */ + and r11,r12,r10 /* Mask PTE bits to keep */ + andi. r10,r12,_PAGE_USER /* User page ? */ + beq 1f /* nope, leave U bits empty */ + rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */ +1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */ /* Done...restore registers and get out of here. */ diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index b0461be1c928..fce2df988504 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -340,6 +340,14 @@ label: addi r3,r1,STACK_FRAME_OVERHEAD; \ EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) +#define DATA_STORAGE_EXCEPTION \ + START_EXCEPTION(DataStorage) \ + NORMAL_EXCEPTION_PROLOG; \ + mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ + stw r5,_ESR(r11); \ + mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \ + EXC_XFER_EE_LITE(0x0300, handle_page_fault) + #define INSTRUCTION_STORAGE_EXCEPTION \ START_EXCEPTION(InstructionStorage) \ NORMAL_EXCEPTION_PROLOG; \ diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c index 953fb919eb06..98052ac96580 100644 --- a/arch/powerpc/mm/44x_mmu.c +++ b/arch/powerpc/mm/44x_mmu.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "mmu_decl.h" @@ -37,11 +38,35 @@ unsigned int tlb_44x_index; /* = 0 */ unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS; int icache_44x_need_flush; +static void __init ppc44x_update_tlb_hwater(void) +{ + extern unsigned int tlb_44x_patch_hwater_D[]; + extern unsigned int tlb_44x_patch_hwater_I[]; + + /* The TLB miss handlers hard codes the watermark in a cmpli + * instruction to improve performances rather than loading it + * from the global variable. Thus, we patch the instructions + * in the 2 TLB miss handlers when updating the value + */ + tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) | + tlb_44x_hwater; + flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0], + (unsigned long)&tlb_44x_patch_hwater_D[1]); + tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) | + tlb_44x_hwater; + flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0], + (unsigned long)&tlb_44x_patch_hwater_I[1]); +} + /* * "Pins" a 256MB TLB entry in AS0 for kernel lowmem */ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys) { + unsigned int entry = tlb_44x_hwater--; + + ppc44x_update_tlb_hwater(); + __asm__ __volatile__( "tlbwe %2,%3,%4\n" "tlbwe %1,%3,%5\n" @@ -50,7 +75,7 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys) : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G), "r" (phys), "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M), - "r" (tlb_44x_hwater--), /* slot for this TLB entry */ + "r" (entry), "i" (PPC44x_TLB_PAGEID), "i" (PPC44x_TLB_XLAT), "i" (PPC44x_TLB_ATTRIB)); @@ -58,6 +83,8 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys) void __init MMU_init_hw(void) { + ppc44x_update_tlb_hwater(); + flush_instruction_cache(); } diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index 7b2510799266..1707d00331fc 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -306,7 +306,8 @@ good_area: flush_dcache_icache_page(page); set_bit(PG_arch_1, &page->flags); } - pte_update(ptep, 0, _PAGE_HWEXEC); + pte_update(ptep, 0, _PAGE_HWEXEC | + _PAGE_ACCESSED); _tlbie(address, mm->context.id); pte_unmap_unlock(ptep, ptl); up_read(&mm->mmap_sem); diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h index e1d2bb57f1d5..11eede4a2906 100644 --- a/include/asm-powerpc/pgtable-ppc32.h +++ b/include/asm-powerpc/pgtable-ppc32.h @@ -182,6 +182,9 @@ extern int icache_44x_need_flush; #define _PMD_SIZE_16M 0x0e0 #define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4)) +/* Until my rework is finished, 40x still needs atomic PTE updates */ +#define PTE_ATOMIC_UPDATES 1 + #elif defined(CONFIG_44x) /* * Definitions for PPC440 @@ -253,17 +256,17 @@ extern int icache_44x_need_flush; */ #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ -#define _PAGE_RW 0x00000002 /* S: Write permission */ +#define _PAGE_RW 0x00000002 /* S: Write permission */ #define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */ +#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */ #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ -#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ -#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ -#define _PAGE_USER 0x00000040 /* S: User page */ -#define _PAGE_ENDIAN 0x00000080 /* H: E bit */ -#define _PAGE_GUARDED 0x00000100 /* H: G bit */ -#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */ -#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ -#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ +#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */ +#define _PAGE_USER 0x00000040 /* S: User page */ +#define _PAGE_ENDIAN 0x00000080 /* H: E bit */ +#define _PAGE_GUARDED 0x00000100 /* H: G bit */ +#define _PAGE_COHERENT 0x00000200 /* H: M bit */ +#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ +#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ /* TODO: Add large page lowmem mapping support */ #define _PMD_PRESENT 0 @@ -273,6 +276,7 @@ extern int icache_44x_need_flush; /* ERPN in a PTE never gets cleared, ignore it */ #define _PTE_NONE_MASK 0xffffffff00000000ULL + #elif defined(CONFIG_FSL_BOOKE) /* MMU Assist Register 3: @@ -315,6 +319,9 @@ extern int icache_44x_need_flush; #define _PMD_PRESENT_MASK (PAGE_MASK) #define _PMD_BAD (~PAGE_MASK) +/* Until my rework is finished, FSL BookE still needs atomic PTE updates */ +#define PTE_ATOMIC_UPDATES 1 + #elif defined(CONFIG_8xx) /* Definitions for 8xx embedded chips. */ #define _PAGE_PRESENT 0x0001 /* Page is valid */ @@ -345,6 +352,9 @@ extern int icache_44x_need_flush; #define _PTE_NONE_MASK _PAGE_ACCESSED +/* Until my rework is finished, 8xx still needs atomic PTE updates */ +#define PTE_ATOMIC_UPDATES 1 + #else /* CONFIG_6xx */ /* Definitions for 60x, 740/750, etc. */ #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ @@ -365,6 +375,10 @@ extern int icache_44x_need_flush; #define _PMD_PRESENT 0 #define _PMD_PRESENT_MASK (PAGE_MASK) #define _PMD_BAD (~PAGE_MASK) + +/* Hash table based platforms need atomic updates of the linux PTE */ +#define PTE_ATOMIC_UPDATES 1 + #endif /* @@ -557,9 +571,11 @@ extern void add_hash_page(unsigned context, unsigned long va, * low PTE word since we expect ALL flag bits to be there */ #ifndef CONFIG_PTE_64BIT -static inline unsigned long pte_update(pte_t *p, unsigned long clr, +static inline unsigned long pte_update(pte_t *p, + unsigned long clr, unsigned long set) { +#ifdef PTE_ATOMIC_UPDATES unsigned long old, tmp; __asm__ __volatile__("\ @@ -572,16 +588,26 @@ static inline unsigned long pte_update(pte_t *p, unsigned long clr, : "=&r" (old), "=&r" (tmp), "=m" (*p) : "r" (p), "r" (clr), "r" (set), "m" (*p) : "cc" ); +#else /* PTE_ATOMIC_UPDATES */ + unsigned long old = pte_val(*p); + *p = __pte((old & ~clr) | set); +#endif /* !PTE_ATOMIC_UPDATES */ + #ifdef CONFIG_44x if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC)) icache_44x_need_flush = 1; #endif return old; } -#else -static inline unsigned long long pte_update(pte_t *p, unsigned long clr, - unsigned long set) +#else /* CONFIG_PTE_64BIT */ +/* TODO: Change that to only modify the low word and move set_pte_at() + * out of line + */ +static inline unsigned long long pte_update(pte_t *p, + unsigned long clr, + unsigned long set) { +#ifdef PTE_ATOMIC_UPDATES unsigned long long old; unsigned long tmp; @@ -596,13 +622,18 @@ static inline unsigned long long pte_update(pte_t *p, unsigned long clr, : "=&r" (old), "=&r" (tmp), "=m" (*p) : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) : "cc" ); +#else /* PTE_ATOMIC_UPDATES */ + unsigned long long old = pte_val(*p); + *p = __pte((old & ~clr) | set); +#endif /* !PTE_ATOMIC_UPDATES */ + #ifdef CONFIG_44x if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC)) icache_44x_need_flush = 1; #endif return old; } -#endif +#endif /* CONFIG_PTE_64BIT */ /* * set_pte stores a linux PTE into the linux page table. @@ -671,7 +702,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) ({ \ int __changed = !pte_same(*(__ptep), __entry); \ if (__changed) { \ - __ptep_set_access_flags(__ptep, __entry, __dirty); \ + __ptep_set_access_flags(__ptep, __entry, __dirty); \ flush_tlb_page_nohash(__vma, __address); \ } \ __changed; \ -- cgit v1.2.3 From 40753caa364bfba60ebd5e2a8bdf366ef175d03c Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:53:56 -0500 Subject: [SCSI] iscsi class, iscsi_tcp/iser: add host arg to session creation iscsi offload (bnx2i and qla4xx) allocate a scsi host per hba, so the session creation path needs a shost/host_no argument. Software iscsi/iser will follow the same behabior as before where it allcoates a host per session, but in the future iser will probably look more like bnx2i where the host's parent is the hardware (rnic for iser and for bnx2i it is the nic), because it does not use a socket layer like how iscsi_tcp does. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 1 + drivers/scsi/iscsi_tcp.c | 5 ++-- drivers/scsi/scsi_transport_iscsi.c | 46 +++++++++++++++++++++++++------- include/scsi/iscsi_if.h | 7 +++++ include/scsi/libiscsi.h | 1 + include/scsi/scsi_transport_iscsi.h | 4 +-- 6 files changed, 51 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index aeb58cae9a3f..efc121986c50 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -368,6 +368,7 @@ static struct iscsi_transport iscsi_iser_transport; static struct iscsi_cls_session * iscsi_iser_session_create(struct iscsi_transport *iscsit, struct scsi_transport_template *scsit, + struct Scsi_Host *shost, uint16_t cmds_max, uint16_t qdepth, uint32_t initial_cmdsn, uint32_t *hostno) { diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 72b9b2a0eba3..81c421a7d477 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -1871,8 +1871,9 @@ iscsi_conn_get_stats(struct iscsi_cls_conn *cls_conn, struct iscsi_stats *stats) static struct iscsi_cls_session * iscsi_tcp_session_create(struct iscsi_transport *iscsit, struct scsi_transport_template *scsit, - uint16_t cmds_max, uint16_t qdepth, - uint32_t initial_cmdsn, uint32_t *hostno) + struct Scsi_Host *shost, uint16_t cmds_max, + uint16_t qdepth, uint32_t initial_cmdsn, + uint32_t *hostno) { struct iscsi_cls_session *cls_session; struct iscsi_session *session; diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index 65d1737eb664..2a6669d967cb 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -1017,21 +1017,38 @@ int iscsi_session_event(struct iscsi_cls_session *session, EXPORT_SYMBOL_GPL(iscsi_session_event); static int -iscsi_if_create_session(struct iscsi_internal *priv, struct iscsi_uevent *ev) +iscsi_if_create_session(struct iscsi_internal *priv, struct iscsi_uevent *ev, + uint32_t host_no, uint32_t initial_cmdsn, + uint16_t cmds_max, uint16_t queue_depth) { struct iscsi_transport *transport = priv->iscsi_transport; struct iscsi_cls_session *session; - uint32_t hostno; + struct Scsi_Host *shost = NULL; - session = transport->create_session(transport, &priv->t, - ev->u.c_session.cmds_max, - ev->u.c_session.queue_depth, - ev->u.c_session.initial_cmdsn, - &hostno); + /* + * Software iscsi allocates a host per session, but + * offload drivers (and possibly iser one day) allocate a host per + * hba/nic/rnic. Offload will match a host here, but software will + * return a new hostno after the create_session callback has returned. + */ + if (host_no != UINT_MAX) { + shost = scsi_host_lookup(host_no); + if (IS_ERR(shost)) { + printk(KERN_ERR "Could not find host no %u to " + "create session\n", host_no); + return -ENODEV; + } + } + + session = transport->create_session(transport, &priv->t, shost, + cmds_max, queue_depth, + initial_cmdsn, &host_no); + if (shost) + scsi_host_put(shost); if (!session) return -ENOMEM; - ev->r.c_session_ret.host_no = hostno; + ev->r.c_session_ret.host_no = host_no; ev->r.c_session_ret.sid = session->sid; return 0; } @@ -1190,6 +1207,7 @@ static int iscsi_if_recv_msg(struct sk_buff *skb, struct nlmsghdr *nlh) { int err = 0; + uint32_t host_no = UINT_MAX; struct iscsi_uevent *ev = NLMSG_DATA(nlh); struct iscsi_transport *transport = NULL; struct iscsi_internal *priv; @@ -1208,7 +1226,17 @@ iscsi_if_recv_msg(struct sk_buff *skb, struct nlmsghdr *nlh) switch (nlh->nlmsg_type) { case ISCSI_UEVENT_CREATE_SESSION: - err = iscsi_if_create_session(priv, ev); + err = iscsi_if_create_session(priv, ev, host_no, + ev->u.c_session.initial_cmdsn, + ev->u.c_session.cmds_max, + ev->u.c_session.queue_depth); + break; + case ISCSI_UEVENT_CREATE_BOUND_SESSION: + err = iscsi_if_create_session(priv, ev, + ev->u.c_bound_session.host_no, + ev->u.c_bound_session.initial_cmdsn, + ev->u.c_bound_session.cmds_max, + ev->u.c_bound_session.queue_depth); break; case ISCSI_UEVENT_DESTROY_SESSION: session = iscsi_session_lookup(ev->u.d_session.sid); diff --git a/include/scsi/iscsi_if.h b/include/scsi/iscsi_if.h index e19e58423166..1883c85cd3ee 100644 --- a/include/scsi/iscsi_if.h +++ b/include/scsi/iscsi_if.h @@ -50,6 +50,7 @@ enum iscsi_uevent_e { ISCSI_UEVENT_TGT_DSCVR = UEVENT_BASE + 15, ISCSI_UEVENT_SET_HOST_PARAM = UEVENT_BASE + 16, ISCSI_UEVENT_UNBIND_SESSION = UEVENT_BASE + 17, + ISCSI_UEVENT_CREATE_BOUND_SESSION = UEVENT_BASE + 18, /* up events */ ISCSI_KEVENT_RECV_PDU = KEVENT_BASE + 1, @@ -78,6 +79,12 @@ struct iscsi_uevent { uint16_t cmds_max; uint16_t queue_depth; } c_session; + struct msg_create_bound_session { + uint32_t host_no; + uint32_t initial_cmdsn; + uint16_t cmds_max; + uint16_t queue_depth; + } c_bound_session; struct msg_destroy_session { uint32_t sid; } d_session; diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index cd3ca63d4fb1..f24cf0246739 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -24,6 +24,7 @@ #define LIBISCSI_H #include +#include #include #include #include diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index aab1eae2ec4c..02a852000be7 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -92,8 +92,8 @@ struct iscsi_transport { unsigned int max_conn; unsigned int max_cmd_len; struct iscsi_cls_session *(*create_session) (struct iscsi_transport *it, - struct scsi_transport_template *t, uint16_t, uint16_t, - uint32_t sn, uint32_t *hn); + struct scsi_transport_template *t, struct Scsi_Host *shost, + uint16_t cmds_max, uint16_t qdepth, uint32_t sn, uint32_t *hn); void (*destroy_session) (struct iscsi_cls_session *session); struct iscsi_cls_conn *(*create_conn) (struct iscsi_cls_session *sess, uint32_t cid); -- cgit v1.2.3 From d3826721b198001c55353b1c54e10843068aae63 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:53:57 -0500 Subject: [SCSI] iscsi class, iscsi drivers: remove unused iscsi_transport attrs max_cmd_len and max_conn are not really used. max_cmd_len is always 16 and can be set by the LLD. max_conn is always one since we do not support MCS. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 1 - drivers/infiniband/ulp/iser/iscsi_iser.h | 1 - drivers/scsi/iscsi_tcp.c | 2 -- drivers/scsi/libiscsi.c | 2 +- drivers/scsi/scsi_transport_iscsi.c | 4 ---- include/scsi/scsi_transport_iscsi.h | 2 -- 6 files changed, 1 insertion(+), 11 deletions(-) (limited to 'include') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index efc121986c50..32f5d5e79abf 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -592,7 +592,6 @@ static struct iscsi_transport iscsi_iser_transport = { .host_template = &iscsi_iser_sht, .conndata_size = sizeof(struct iscsi_conn), .max_lun = ISCSI_ISER_MAX_LUN, - .max_cmd_len = ISCSI_ISER_MAX_CMD_LEN, /* session management */ .create_session = iscsi_iser_session_create, .destroy_session = iscsi_session_teardown, diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.h b/drivers/infiniband/ulp/iser/iscsi_iser.h index a8c1b300e34d..66a2f30ada01 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.h +++ b/drivers/infiniband/ulp/iser/iscsi_iser.h @@ -96,7 +96,6 @@ /* support upto 512KB in one RDMA */ #define ISCSI_ISER_SG_TABLESIZE (0x80000 >> SHIFT_4K) #define ISCSI_ISER_MAX_LUN 256 -#define ISCSI_ISER_MAX_CMD_LEN 16 /* QP settings */ /* Maximal bounds on received asynchronous PDUs */ diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 81c421a7d477..aecadbdce9df 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -1978,8 +1978,6 @@ static struct iscsi_transport iscsi_tcp_transport = { ISCSI_HOST_NETDEV_NAME, .host_template = &iscsi_sht, .conndata_size = sizeof(struct iscsi_conn), - .max_conn = 1, - .max_cmd_len = 16, /* session management */ .create_session = iscsi_tcp_session_create, .destroy_session = iscsi_tcp_session_destroy, diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index b43bf1d60dac..01a1a4d36f21 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -1830,7 +1830,7 @@ iscsi_session_setup(struct iscsi_transport *iscsit, shost->max_id = 1; shost->max_channel = 0; shost->max_lun = iscsit->max_lun; - shost->max_cmd_len = iscsit->max_cmd_len; + shost->max_cmd_len = 16; shost->transportt = scsit; shost->transportt->create_work_queue = 1; shost->transportt->eh_timed_out = iscsi_eh_cmd_timed_out; diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index 2a6669d967cb..e6a090e9c8a4 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -102,15 +102,11 @@ static DEVICE_ATTR(name, S_IRUGO, show_transport_##name, NULL); show_transport_attr(caps, "0x%x"); show_transport_attr(max_lun, "%d"); -show_transport_attr(max_conn, "%d"); -show_transport_attr(max_cmd_len, "%d"); static struct attribute *iscsi_transport_attrs[] = { &dev_attr_handle.attr, &dev_attr_caps.attr, &dev_attr_max_lun.attr, - &dev_attr_max_conn.attr, - &dev_attr_max_cmd_len.attr, NULL, }; diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index 02a852000be7..afed70ec2aa5 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -89,8 +89,6 @@ struct iscsi_transport { /* LLD session data size */ int sessiondata_size; int max_lun; - unsigned int max_conn; - unsigned int max_cmd_len; struct iscsi_cls_session *(*create_session) (struct iscsi_transport *it, struct scsi_transport_template *t, struct Scsi_Host *shost, uint16_t cmds_max, uint16_t qdepth, uint32_t sn, uint32_t *hn); -- cgit v1.2.3 From 32c6e1b9a2e27076b7070a9ec56a9e5437ebd725 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:53:58 -0500 Subject: [SCSI] iscsi class: rename iscsi_host to iscsi_cls_host This renames the iscsi_host to iscsi_cls_host to match the other structs, because libiscsi wants to use the iscsi_host name in the future. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/scsi/scsi_transport_iscsi.c | 24 +++++++++++------------- include/scsi/scsi_transport_iscsi.h | 2 +- 2 files changed, 12 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index e6a090e9c8a4..5577a60bec4e 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -114,13 +114,11 @@ static struct attribute_group iscsi_transport_group = { .attrs = iscsi_transport_attrs, }; - - static int iscsi_setup_host(struct transport_container *tc, struct device *dev, struct device *cdev) { struct Scsi_Host *shost = dev_to_shost(dev); - struct iscsi_host *ihost = shost->shost_data; + struct iscsi_cls_host *ihost = shost->shost_data; memset(ihost, 0, sizeof(*ihost)); INIT_LIST_HEAD(&ihost->sessions); @@ -140,7 +138,7 @@ static int iscsi_remove_host(struct transport_container *tc, struct device *dev, struct device *cdev) { struct Scsi_Host *shost = dev_to_shost(dev); - struct iscsi_host *ihost = shost->shost_data; + struct iscsi_cls_host *ihost = shost->shost_data; destroy_workqueue(ihost->scan_workq); return 0; @@ -293,7 +291,7 @@ static int iscsi_is_session_dev(const struct device *dev) */ int iscsi_scan_finished(struct Scsi_Host *shost, unsigned long time) { - struct iscsi_host *ihost = shost->shost_data; + struct iscsi_cls_host *ihost = shost->shost_data; /* * qla4xxx will have kicked off some session unblocks before calling * scsi_scan_host, so just wait for them to complete. @@ -305,7 +303,7 @@ EXPORT_SYMBOL_GPL(iscsi_scan_finished); static int iscsi_user_scan(struct Scsi_Host *shost, uint channel, uint id, uint lun) { - struct iscsi_host *ihost = shost->shost_data; + struct iscsi_cls_host *ihost = shost->shost_data; struct iscsi_cls_session *session; mutex_lock(&ihost->mutex); @@ -325,7 +323,7 @@ static void iscsi_scan_session(struct work_struct *work) struct iscsi_cls_session *session = container_of(work, struct iscsi_cls_session, scan_work); struct Scsi_Host *shost = iscsi_session_to_shost(session); - struct iscsi_host *ihost = shost->shost_data; + struct iscsi_cls_host *ihost = shost->shost_data; unsigned long flags; spin_lock_irqsave(&session->lock, flags); @@ -377,7 +375,7 @@ static void __iscsi_unblock_session(struct work_struct *work) container_of(work, struct iscsi_cls_session, unblock_work); struct Scsi_Host *shost = iscsi_session_to_shost(session); - struct iscsi_host *ihost = shost->shost_data; + struct iscsi_cls_host *ihost = shost->shost_data; unsigned long flags; /* @@ -445,7 +443,7 @@ static void __iscsi_unbind_session(struct work_struct *work) container_of(work, struct iscsi_cls_session, unbind_work); struct Scsi_Host *shost = iscsi_session_to_shost(session); - struct iscsi_host *ihost = shost->shost_data; + struct iscsi_cls_host *ihost = shost->shost_data; /* Prevent new scans and make sure scanning is not in progress */ mutex_lock(&ihost->mutex); @@ -463,7 +461,7 @@ static void __iscsi_unbind_session(struct work_struct *work) static int iscsi_unbind_session(struct iscsi_cls_session *session) { struct Scsi_Host *shost = iscsi_session_to_shost(session); - struct iscsi_host *ihost = shost->shost_data; + struct iscsi_cls_host *ihost = shost->shost_data; return queue_work(ihost->scan_workq, &session->unbind_work); } @@ -505,7 +503,7 @@ EXPORT_SYMBOL_GPL(iscsi_alloc_session); int iscsi_add_session(struct iscsi_cls_session *session, unsigned int target_id) { struct Scsi_Host *shost = iscsi_session_to_shost(session); - struct iscsi_host *ihost; + struct iscsi_cls_host *ihost; unsigned long flags; int err; @@ -591,7 +589,7 @@ static int iscsi_iter_destroy_conn_fn(struct device *dev, void *data) void iscsi_remove_session(struct iscsi_cls_session *session) { struct Scsi_Host *shost = iscsi_session_to_shost(session); - struct iscsi_host *ihost = shost->shost_data; + struct iscsi_cls_host *ihost = shost->shost_data; unsigned long flags; int err; @@ -1619,7 +1617,7 @@ iscsi_register_transport(struct iscsi_transport *tt) priv->t.host_attrs.ac.attrs = &priv->host_attrs[0]; priv->t.host_attrs.ac.class = &iscsi_host_class.class; priv->t.host_attrs.ac.match = iscsi_host_match; - priv->t.host_size = sizeof(struct iscsi_host); + priv->t.host_size = sizeof(struct iscsi_cls_host); transport_container_register(&priv->t.host_attrs); SETUP_HOST_RD_ATTR(netdev, ISCSI_HOST_NETDEV_NAME); diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index afed70ec2aa5..728702292a80 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -201,7 +201,7 @@ struct iscsi_cls_session { #define starget_to_session(_stgt) \ iscsi_dev_to_session(_stgt->dev.parent) -struct iscsi_host { +struct iscsi_cls_host { struct list_head sessions; atomic_t nr_scans; struct mutex mutex; -- cgit v1.2.3 From 756135215ec743be6fdce2bdebe8cdb9f8a231f6 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:53:59 -0500 Subject: [SCSI] iscsi: remove session and host binding in libiscsi bnx2i allocates a host per netdevice but will use libiscsi, so this unbinds the session from the host in that code. This will also be useful for the iser parent device dma settings fixes. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 74 ++++++++--- drivers/scsi/iscsi_tcp.c | 102 ++++++++------- drivers/scsi/libiscsi.c | 213 ++++++++++++++----------------- drivers/scsi/qla4xxx/ql4_os.c | 1 - drivers/scsi/scsi_transport_iscsi.c | 5 +- include/scsi/iscsi_if.h | 7 - include/scsi/libiscsi.h | 31 ++--- include/scsi/scsi_transport_iscsi.h | 8 +- 8 files changed, 225 insertions(+), 216 deletions(-) (limited to 'include') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index 32f5d5e79abf..5a750042e2b2 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -74,6 +74,10 @@ #include "iscsi_iser.h" +static struct scsi_host_template iscsi_iser_sht; +static struct iscsi_transport iscsi_iser_transport; +static struct scsi_transport_template *iscsi_iser_scsi_transport; + static unsigned int iscsi_max_lun = 512; module_param_named(max_lun, iscsi_max_lun, uint, S_IRUGO); @@ -363,40 +367,64 @@ iscsi_iser_conn_start(struct iscsi_cls_conn *cls_conn) return iscsi_conn_start(cls_conn); } -static struct iscsi_transport iscsi_iser_transport; +static void iscsi_iser_session_destroy(struct iscsi_cls_session *cls_session) +{ + struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); + + iscsi_session_teardown(cls_session); + scsi_remove_host(shost); + iscsi_host_teardown(shost); + scsi_host_put(shost); +} static struct iscsi_cls_session * -iscsi_iser_session_create(struct iscsi_transport *iscsit, - struct scsi_transport_template *scsit, - struct Scsi_Host *shost, - uint16_t cmds_max, uint16_t qdepth, - uint32_t initial_cmdsn, uint32_t *hostno) +iscsi_iser_session_create(struct Scsi_Host *shost, + uint16_t cmds_max, uint16_t qdepth, + uint32_t initial_cmdsn, uint32_t *hostno) { struct iscsi_cls_session *cls_session; struct iscsi_session *session; int i; - uint32_t hn; struct iscsi_cmd_task *ctask; struct iscsi_mgmt_task *mtask; struct iscsi_iser_cmd_task *iser_ctask; struct iser_desc *desc; + if (shost) { + printk(KERN_ERR "iscsi_tcp: invalid shost %d.\n", + shost->host_no); + return NULL; + } + + shost = scsi_host_alloc(&iscsi_iser_sht, 0); + if (!shost) + return NULL; + shost->transportt = iscsi_iser_scsi_transport; + shost->max_lun = iscsi_max_lun; + shost->max_id = 0; + shost->max_channel = 0; + shost->max_cmd_len = 16; + + iscsi_host_setup(shost, qdepth); + + if (scsi_add_host(shost, NULL)) + goto free_host; + *hostno = shost->host_no; + /* * we do not support setting can_queue cmd_per_lun from userspace yet * because we preallocate so many resources */ - cls_session = iscsi_session_setup(iscsit, scsit, + cls_session = iscsi_session_setup(&iscsi_iser_transport, shost, ISCSI_DEF_XMIT_CMDS_MAX, - ISCSI_MAX_CMD_PER_LUN, sizeof(struct iscsi_iser_cmd_task), sizeof(struct iser_desc), - initial_cmdsn, &hn); + initial_cmdsn); if (!cls_session) - return NULL; - - *hostno = hn; - session = class_to_transport_session(cls_session); + goto remove_host; + session = cls_session->dd_data; + shost->can_queue = session->cmds_max; /* libiscsi setup itts, data and pool so just set desc fields */ for (i = 0; i < session->cmds_max; i++) { ctask = session->cmds[i]; @@ -413,6 +441,13 @@ iscsi_iser_session_create(struct iscsi_transport *iscsit, } return cls_session; + +remove_host: + scsi_remove_host(shost); +free_host: + iscsi_host_teardown(shost); + scsi_host_put(shost); + return NULL; } static int @@ -589,12 +624,11 @@ static struct iscsi_transport iscsi_iser_transport = { .host_param_mask = ISCSI_HOST_HWADDRESS | ISCSI_HOST_NETDEV_NAME | ISCSI_HOST_INITIATOR_NAME, - .host_template = &iscsi_iser_sht, .conndata_size = sizeof(struct iscsi_conn), - .max_lun = ISCSI_ISER_MAX_LUN, + .sessiondata_size = sizeof(struct iscsi_session), /* session management */ .create_session = iscsi_iser_session_create, - .destroy_session = iscsi_session_teardown, + .destroy_session = iscsi_iser_session_destroy, /* connection management */ .create_conn = iscsi_iser_conn_create, .bind_conn = iscsi_iser_conn_bind, @@ -633,8 +667,6 @@ static int __init iser_init(void) return -EINVAL; } - iscsi_iser_transport.max_lun = iscsi_max_lun; - memset(&ig, 0, sizeof(struct iser_global)); ig.desc_cache = kmem_cache_create("iser_descriptors", @@ -650,7 +682,9 @@ static int __init iser_init(void) mutex_init(&ig.connlist_mutex); INIT_LIST_HEAD(&ig.connlist); - if (!iscsi_register_transport(&iscsi_iser_transport)) { + iscsi_iser_scsi_transport = iscsi_register_transport( + &iscsi_iser_transport); + if (!iscsi_iser_scsi_transport) { iser_err("iscsi_register_transport failed\n"); err = -EINVAL; goto register_transport_failure; diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index aecadbdce9df..8cdcaf33fb4e 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -64,6 +64,10 @@ MODULE_LICENSE("GPL"); #define BUG_ON(expr) #endif +static struct scsi_transport_template *iscsi_tcp_scsi_transport; +static struct scsi_host_template iscsi_sht; +static struct iscsi_transport iscsi_tcp_transport; + static unsigned int iscsi_max_lun = 512; module_param_named(max_lun, iscsi_max_lun, uint, S_IRUGO); @@ -1623,6 +1627,8 @@ iscsi_tcp_conn_bind(struct iscsi_cls_session *cls_session, struct iscsi_cls_conn *cls_conn, uint64_t transport_eph, int is_leading) { + struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); + struct iscsi_host *ihost = shost_priv(shost); struct iscsi_conn *conn = cls_conn->dd_data; struct iscsi_tcp_conn *tcp_conn = conn->dd_data; struct sock *sk; @@ -1646,8 +1652,8 @@ iscsi_tcp_conn_bind(struct iscsi_cls_session *cls_session, if (err) goto free_socket; - err = iscsi_tcp_get_addr(conn, sock, conn->local_address, - &conn->local_port, kernel_getsockname); + err = iscsi_tcp_get_addr(conn, sock, ihost->local_address, + &ihost->local_port, kernel_getsockname); if (err) goto free_socket; @@ -1821,29 +1827,6 @@ iscsi_tcp_conn_get_param(struct iscsi_cls_conn *cls_conn, return len; } -static int -iscsi_tcp_host_get_param(struct Scsi_Host *shost, enum iscsi_host_param param, - char *buf) -{ - struct iscsi_session *session = iscsi_hostdata(shost->hostdata); - int len; - - switch (param) { - case ISCSI_HOST_PARAM_IPADDRESS: - spin_lock_bh(&session->lock); - if (!session->leadconn) - len = -ENODEV; - else - len = sprintf(buf, "%s\n", - session->leadconn->local_address); - spin_unlock_bh(&session->lock); - break; - default: - return iscsi_host_get_param(shost, param, buf); - } - return len; -} - static void iscsi_conn_get_stats(struct iscsi_cls_conn *cls_conn, struct iscsi_stats *stats) { @@ -1869,26 +1852,44 @@ iscsi_conn_get_stats(struct iscsi_cls_conn *cls_conn, struct iscsi_stats *stats) } static struct iscsi_cls_session * -iscsi_tcp_session_create(struct iscsi_transport *iscsit, - struct scsi_transport_template *scsit, - struct Scsi_Host *shost, uint16_t cmds_max, +iscsi_tcp_session_create(struct Scsi_Host *shost, uint16_t cmds_max, uint16_t qdepth, uint32_t initial_cmdsn, uint32_t *hostno) { struct iscsi_cls_session *cls_session; struct iscsi_session *session; - uint32_t hn; int cmd_i; - cls_session = iscsi_session_setup(iscsit, scsit, cmds_max, qdepth, - sizeof(struct iscsi_tcp_cmd_task), - sizeof(struct iscsi_tcp_mgmt_task), - initial_cmdsn, &hn); - if (!cls_session) + if (shost) { + printk(KERN_ERR "iscsi_tcp: invalid shost %d.\n", + shost->host_no); + return NULL; + } + + shost = scsi_host_alloc(&iscsi_sht, sizeof(struct iscsi_host)); + if (!shost) return NULL; - *hostno = hn; + shost->transportt = iscsi_tcp_scsi_transport; + shost->max_lun = iscsi_max_lun; + shost->max_id = 0; + shost->max_channel = 0; + shost->max_cmd_len = 16; + + iscsi_host_setup(shost, qdepth); + + if (scsi_add_host(shost, NULL)) + goto free_host; + *hostno = shost->host_no; + + cls_session = iscsi_session_setup(&iscsi_tcp_transport, shost, cmds_max, + sizeof(struct iscsi_tcp_cmd_task), + sizeof(struct iscsi_tcp_mgmt_task), + initial_cmdsn); + if (!cls_session) + goto remove_host; + session = cls_session->dd_data; - session = class_to_transport_session(cls_session); + shost->can_queue = session->cmds_max; for (cmd_i = 0; cmd_i < session->cmds_max; cmd_i++) { struct iscsi_cmd_task *ctask = session->cmds[cmd_i]; struct iscsi_tcp_cmd_task *tcp_ctask = ctask->dd_data; @@ -1904,20 +1905,30 @@ iscsi_tcp_session_create(struct iscsi_transport *iscsit, mtask->hdr = (struct iscsi_hdr *) &tcp_mtask->hdr; } - if (iscsi_r2tpool_alloc(class_to_transport_session(cls_session))) - goto r2tpool_alloc_fail; - + if (iscsi_r2tpool_alloc(session)) + goto remove_session; return cls_session; -r2tpool_alloc_fail: +remove_session: iscsi_session_teardown(cls_session); +remove_host: + scsi_remove_host(shost); +free_host: + iscsi_host_teardown(shost); + scsi_host_put(shost); return NULL; } static void iscsi_tcp_session_destroy(struct iscsi_cls_session *cls_session) { - iscsi_r2tpool_free(class_to_transport_session(cls_session)); + struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); + + iscsi_r2tpool_free(cls_session->dd_data); iscsi_session_teardown(cls_session); + + scsi_remove_host(shost); + iscsi_host_teardown(shost); + scsi_host_put(shost); } static int iscsi_tcp_slave_configure(struct scsi_device *sdev) @@ -1976,8 +1987,8 @@ static struct iscsi_transport iscsi_tcp_transport = { .host_param_mask = ISCSI_HOST_HWADDRESS | ISCSI_HOST_IPADDRESS | ISCSI_HOST_INITIATOR_NAME | ISCSI_HOST_NETDEV_NAME, - .host_template = &iscsi_sht, .conndata_size = sizeof(struct iscsi_conn), + .sessiondata_size = sizeof(struct iscsi_session), /* session management */ .create_session = iscsi_tcp_session_create, .destroy_session = iscsi_tcp_session_destroy, @@ -1991,7 +2002,7 @@ static struct iscsi_transport iscsi_tcp_transport = { .start_conn = iscsi_conn_start, .stop_conn = iscsi_tcp_conn_stop, /* iscsi host params */ - .get_host_param = iscsi_tcp_host_get_param, + .get_host_param = iscsi_host_get_param, .set_host_param = iscsi_host_set_param, /* IO */ .send_pdu = iscsi_conn_send_pdu, @@ -2013,9 +2024,10 @@ iscsi_tcp_init(void) iscsi_max_lun); return -EINVAL; } - iscsi_tcp_transport.max_lun = iscsi_max_lun; - if (!iscsi_register_transport(&iscsi_tcp_transport)) + iscsi_tcp_scsi_transport = iscsi_register_transport( + &iscsi_tcp_transport); + if (!iscsi_tcp_scsi_transport) return -ENODEV; return 0; diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index 01a1a4d36f21..64b1dd827366 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -38,14 +38,6 @@ #include #include -struct iscsi_session * -class_to_transport_session(struct iscsi_cls_session *cls_session) -{ - struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); - return iscsi_hostdata(shost->hostdata); -} -EXPORT_SYMBOL_GPL(class_to_transport_session); - /* Serial Number Arithmetic, 32 bits, less than, RFC1982 */ #define SNA32_CHECK 2147483648UL @@ -1096,6 +1088,7 @@ enum { int iscsi_queuecommand(struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *)) { + struct iscsi_cls_session *cls_session; struct Scsi_Host *host; int reason = 0; struct iscsi_session *session; @@ -1109,10 +1102,11 @@ int iscsi_queuecommand(struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *)) host = sc->device->host; spin_unlock(host->host_lock); - session = iscsi_hostdata(host->hostdata); + cls_session = starget_to_session(scsi_target(sc->device)); + session = cls_session->dd_data; spin_lock(&session->lock); - reason = iscsi_session_chkready(session_to_cls(session)); + reason = iscsi_session_chkready(cls_session); if (reason) { sc->result = reason; goto fault; @@ -1222,7 +1216,7 @@ EXPORT_SYMBOL_GPL(iscsi_change_queue_depth); void iscsi_session_recovery_timedout(struct iscsi_cls_session *cls_session) { - struct iscsi_session *session = class_to_transport_session(cls_session); + struct iscsi_session *session = cls_session->dd_data; spin_lock_bh(&session->lock); if (session->state != ISCSI_STATE_LOGGED_IN) { @@ -1236,9 +1230,13 @@ EXPORT_SYMBOL_GPL(iscsi_session_recovery_timedout); int iscsi_eh_host_reset(struct scsi_cmnd *sc) { - struct Scsi_Host *host = sc->device->host; - struct iscsi_session *session = iscsi_hostdata(host->hostdata); - struct iscsi_conn *conn = session->leadconn; + struct iscsi_cls_session *cls_session; + struct iscsi_session *session; + struct iscsi_conn *conn; + + cls_session = starget_to_session(scsi_target(sc->device)); + session = cls_session->dd_data; + conn = session->leadconn; mutex_lock(&session->eh_mutex); spin_lock_bh(&session->lock); @@ -1405,7 +1403,7 @@ static enum scsi_eh_timer_return iscsi_eh_cmd_timed_out(struct scsi_cmnd *scmd) enum scsi_eh_timer_return rc = EH_NOT_HANDLED; cls_session = starget_to_session(scsi_target(scmd->device)); - session = class_to_transport_session(cls_session); + session = cls_session->dd_data; debug_scsi("scsi cmd %p timedout\n", scmd); @@ -1507,13 +1505,16 @@ static void iscsi_prep_abort_task_pdu(struct iscsi_cmd_task *ctask, int iscsi_eh_abort(struct scsi_cmnd *sc) { - struct Scsi_Host *host = sc->device->host; - struct iscsi_session *session = iscsi_hostdata(host->hostdata); + struct iscsi_cls_session *cls_session; + struct iscsi_session *session; struct iscsi_conn *conn; struct iscsi_cmd_task *ctask; struct iscsi_tm *hdr; int rc, age; + cls_session = starget_to_session(scsi_target(sc->device)); + session = cls_session->dd_data; + mutex_lock(&session->eh_mutex); spin_lock_bh(&session->lock); /* @@ -1630,12 +1631,15 @@ static void iscsi_prep_lun_reset_pdu(struct scsi_cmnd *sc, struct iscsi_tm *hdr) int iscsi_eh_device_reset(struct scsi_cmnd *sc) { - struct Scsi_Host *host = sc->device->host; - struct iscsi_session *session = iscsi_hostdata(host->hostdata); + struct iscsi_cls_session *cls_session; + struct iscsi_session *session; struct iscsi_conn *conn; struct iscsi_tm *hdr; int rc = FAILED; + cls_session = starget_to_session(scsi_target(sc->device)); + session = cls_session->dd_data; + debug_scsi("LU Reset [sc %p lun %u]\n", sc, sc->device->lun); mutex_lock(&session->eh_mutex); @@ -1760,55 +1764,53 @@ void iscsi_pool_free(struct iscsi_pool *q) } EXPORT_SYMBOL_GPL(iscsi_pool_free); -/* - * iSCSI Session's hostdata organization: - * - * *------------------* <== hostdata_session(host->hostdata) - * | ptr to class sess| - * |------------------| <== iscsi_hostdata(host->hostdata) - * | iscsi_session | - * *------------------* - */ +void iscsi_host_setup(struct Scsi_Host *shost, uint16_t qdepth) +{ + if (qdepth > ISCSI_MAX_CMD_PER_LUN || qdepth < 1) { + if (qdepth != 0) + printk(KERN_ERR "iscsi: invalid queue depth of %d. " + "Queue depth must be between 1 and %d.\n", + qdepth, ISCSI_MAX_CMD_PER_LUN); + qdepth = ISCSI_DEF_CMD_PER_LUN; + } + + shost->transportt->create_work_queue = 1; + shost->transportt->eh_timed_out = iscsi_eh_cmd_timed_out; + shost->cmd_per_lun = qdepth; +} +EXPORT_SYMBOL_GPL(iscsi_host_setup); -#define hostdata_privsize(_sz) (sizeof(unsigned long) + _sz + \ - _sz % sizeof(unsigned long)) +void iscsi_host_teardown(struct Scsi_Host *shost) +{ + struct iscsi_host *ihost = shost_priv(shost); -#define hostdata_session(_hostdata) (iscsi_ptr(*(unsigned long *)_hostdata)) + kfree(ihost->netdev); + kfree(ihost->hwaddress); + kfree(ihost->initiatorname); +} +EXPORT_SYMBOL_GPL(iscsi_host_teardown); /** * iscsi_session_setup - create iscsi cls session and host and session - * @scsit: scsi transport template * @iscsit: iscsi transport template - * @cmds_max: scsi host can queue - * @qdepth: scsi host cmds per lun + * @shost: scsi host + * @cmds_max: session can queue * @cmd_task_size: LLD ctask private data size * @mgmt_task_size: LLD mtask private data size * @initial_cmdsn: initial CmdSN - * @hostno: host no allocated * * This can be used by software iscsi_transports that allocate * a session per scsi host. - **/ + */ struct iscsi_cls_session * -iscsi_session_setup(struct iscsi_transport *iscsit, - struct scsi_transport_template *scsit, - uint16_t cmds_max, uint16_t qdepth, - int cmd_task_size, int mgmt_task_size, - uint32_t initial_cmdsn, uint32_t *hostno) +iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, + uint16_t cmds_max, int cmd_task_size, int mgmt_task_size, + uint32_t initial_cmdsn) { - struct Scsi_Host *shost; struct iscsi_session *session; struct iscsi_cls_session *cls_session; int cmd_i; - if (qdepth > ISCSI_MAX_CMD_PER_LUN || qdepth < 1) { - if (qdepth != 0) - printk(KERN_ERR "iscsi: invalid queue depth of %d. " - "Queue depth must be between 1 and %d.\n", - qdepth, ISCSI_MAX_CMD_PER_LUN); - qdepth = ISCSI_DEF_CMD_PER_LUN; - } - if (!is_power_of_2(cmds_max) || cmds_max >= ISCSI_MGMT_ITT_OFFSET || cmds_max < 2) { if (cmds_max != 0) @@ -1819,25 +1821,11 @@ iscsi_session_setup(struct iscsi_transport *iscsit, cmds_max = ISCSI_DEF_XMIT_CMDS_MAX; } - shost = scsi_host_alloc(iscsit->host_template, - hostdata_privsize(sizeof(*session))); - if (!shost) + cls_session = iscsi_alloc_session(shost, iscsit); + if (!cls_session) return NULL; - - /* the iscsi layer takes one task for reserve */ - shost->can_queue = cmds_max - 1; - shost->cmd_per_lun = qdepth; - shost->max_id = 1; - shost->max_channel = 0; - shost->max_lun = iscsit->max_lun; - shost->max_cmd_len = 16; - shost->transportt = scsit; - shost->transportt->create_work_queue = 1; - shost->transportt->eh_timed_out = iscsi_eh_cmd_timed_out; - *hostno = shost->host_no; - - session = iscsi_hostdata(shost->hostdata); - memset(session, 0, sizeof(struct iscsi_session)); + session = cls_session->dd_data; + session->cls_session = cls_session; session->host = shost; session->state = ISCSI_STATE_FREE; session->fast_abort = 1; @@ -1851,6 +1839,7 @@ iscsi_session_setup(struct iscsi_transport *iscsit, session->max_r2t = 1; session->tt = iscsit; mutex_init(&session->eh_mutex); + spin_lock_init(&session->lock); /* initialize SCSI PDU commands pool */ if (iscsi_pool_init(&session->cmdpool, session->cmds_max, @@ -1868,8 +1857,6 @@ iscsi_session_setup(struct iscsi_transport *iscsit, INIT_LIST_HEAD(&ctask->running); } - spin_lock_init(&session->lock); - /* initialize immediate command pool */ if (iscsi_pool_init(&session->mgmtpool, session->mgmtpool_max, (void***)&session->mgmt_cmds, @@ -1887,49 +1874,37 @@ iscsi_session_setup(struct iscsi_transport *iscsit, INIT_LIST_HEAD(&mtask->running); } - if (scsi_add_host(shost, NULL)) - goto add_host_fail; - if (!try_module_get(iscsit->owner)) - goto cls_session_fail; - - cls_session = iscsi_create_session(shost, iscsit, 0); - if (!cls_session) - goto module_put; - *(unsigned long*)shost->hostdata = (unsigned long)cls_session; + goto module_get_fail; + if (iscsi_add_session(cls_session, 0)) + goto cls_session_fail; return cls_session; -module_put: - module_put(iscsit->owner); cls_session_fail: - scsi_remove_host(shost); -add_host_fail: + module_put(iscsit->owner); +module_get_fail: iscsi_pool_free(&session->mgmtpool); mgmtpool_alloc_fail: iscsi_pool_free(&session->cmdpool); cmdpool_alloc_fail: - scsi_host_put(shost); + iscsi_free_session(cls_session); return NULL; } EXPORT_SYMBOL_GPL(iscsi_session_setup); /** * iscsi_session_teardown - destroy session, host, and cls_session - * shost: scsi host + * @cls_session: iscsi session * - * This can be used by software iscsi_transports that allocate - * a session per scsi host. - **/ + * The driver must have called iscsi_remove_session before + * calling this. + */ void iscsi_session_teardown(struct iscsi_cls_session *cls_session) { - struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); - struct iscsi_session *session = iscsi_hostdata(shost->hostdata); + struct iscsi_session *session = cls_session->dd_data; struct module *owner = cls_session->transport->owner; - iscsi_remove_session(cls_session); - scsi_remove_host(shost); - iscsi_pool_free(&session->mgmtpool); iscsi_pool_free(&session->cmdpool); @@ -1938,12 +1913,8 @@ void iscsi_session_teardown(struct iscsi_cls_session *cls_session) kfree(session->username); kfree(session->username_in); kfree(session->targetname); - kfree(session->netdev); - kfree(session->hwaddress); - kfree(session->initiatorname); - iscsi_free_session(cls_session); - scsi_host_put(shost); + iscsi_destroy_session(cls_session); module_put(owner); } EXPORT_SYMBOL_GPL(iscsi_session_teardown); @@ -1956,7 +1927,7 @@ EXPORT_SYMBOL_GPL(iscsi_session_teardown); struct iscsi_cls_conn * iscsi_conn_setup(struct iscsi_cls_session *cls_session, uint32_t conn_idx) { - struct iscsi_session *session = class_to_transport_session(cls_session); + struct iscsi_session *session = cls_session->dd_data; struct iscsi_conn *conn; struct iscsi_cls_conn *cls_conn; char *data; @@ -2140,7 +2111,7 @@ int iscsi_conn_start(struct iscsi_cls_conn *cls_conn) } spin_unlock_bh(&session->lock); - iscsi_unblock_session(session_to_cls(session)); + iscsi_unblock_session(session->cls_session); wake_up(&conn->ehwait); return 0; } @@ -2225,7 +2196,7 @@ static void iscsi_start_session_recovery(struct iscsi_session *session, if (session->state == ISCSI_STATE_IN_RECOVERY && old_stop_stage != STOP_CONN_RECOVER) { debug_scsi("blocking session\n"); - iscsi_block_session(session_to_cls(session)); + iscsi_block_session(session->cls_session); } } @@ -2260,7 +2231,7 @@ EXPORT_SYMBOL_GPL(iscsi_conn_stop); int iscsi_conn_bind(struct iscsi_cls_session *cls_session, struct iscsi_cls_conn *cls_conn, int is_leading) { - struct iscsi_session *session = class_to_transport_session(cls_session); + struct iscsi_session *session = cls_session->dd_data; struct iscsi_conn *conn = cls_conn->dd_data; spin_lock_bh(&session->lock); @@ -2410,8 +2381,7 @@ EXPORT_SYMBOL_GPL(iscsi_set_param); int iscsi_session_get_param(struct iscsi_cls_session *cls_session, enum iscsi_param param, char *buf) { - struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); - struct iscsi_session *session = iscsi_hostdata(shost->hostdata); + struct iscsi_session *session = cls_session->dd_data; int len; switch(param) { @@ -2525,29 +2495,34 @@ EXPORT_SYMBOL_GPL(iscsi_conn_get_param); int iscsi_host_get_param(struct Scsi_Host *shost, enum iscsi_host_param param, char *buf) { - struct iscsi_session *session = iscsi_hostdata(shost->hostdata); + struct iscsi_host *ihost = shost_priv(shost); int len; switch (param) { case ISCSI_HOST_PARAM_NETDEV_NAME: - if (!session->netdev) + if (!ihost->netdev) len = sprintf(buf, "%s\n", "default"); else - len = sprintf(buf, "%s\n", session->netdev); + len = sprintf(buf, "%s\n", ihost->netdev); break; case ISCSI_HOST_PARAM_HWADDRESS: - if (!session->hwaddress) + if (!ihost->hwaddress) len = sprintf(buf, "%s\n", "default"); else - len = sprintf(buf, "%s\n", session->hwaddress); + len = sprintf(buf, "%s\n", ihost->hwaddress); break; case ISCSI_HOST_PARAM_INITIATOR_NAME: - if (!session->initiatorname) + if (!ihost->initiatorname) len = sprintf(buf, "%s\n", "unknown"); else - len = sprintf(buf, "%s\n", session->initiatorname); + len = sprintf(buf, "%s\n", ihost->initiatorname); break; - + case ISCSI_HOST_PARAM_IPADDRESS: + if (!strlen(ihost->local_address)) + len = sprintf(buf, "%s\n", "unknown"); + else + len = sprintf(buf, "%s\n", + ihost->local_address); default: return -ENOSYS; } @@ -2559,20 +2534,20 @@ EXPORT_SYMBOL_GPL(iscsi_host_get_param); int iscsi_host_set_param(struct Scsi_Host *shost, enum iscsi_host_param param, char *buf, int buflen) { - struct iscsi_session *session = iscsi_hostdata(shost->hostdata); + struct iscsi_host *ihost = shost_priv(shost); switch (param) { case ISCSI_HOST_PARAM_NETDEV_NAME: - if (!session->netdev) - session->netdev = kstrdup(buf, GFP_KERNEL); + if (!ihost->netdev) + ihost->netdev = kstrdup(buf, GFP_KERNEL); break; case ISCSI_HOST_PARAM_HWADDRESS: - if (!session->hwaddress) - session->hwaddress = kstrdup(buf, GFP_KERNEL); + if (!ihost->hwaddress) + ihost->hwaddress = kstrdup(buf, GFP_KERNEL); break; case ISCSI_HOST_PARAM_INITIATOR_NAME: - if (!session->initiatorname) - session->initiatorname = kstrdup(buf, GFP_KERNEL); + if (!ihost->initiatorname) + ihost->initiatorname = kstrdup(buf, GFP_KERNEL); break; default: return -ENOSYS; diff --git a/drivers/scsi/qla4xxx/ql4_os.c b/drivers/scsi/qla4xxx/ql4_os.c index 0c786944d2c2..6c6ee0f34995 100644 --- a/drivers/scsi/qla4xxx/ql4_os.c +++ b/drivers/scsi/qla4xxx/ql4_os.c @@ -114,7 +114,6 @@ static struct iscsi_transport qla4xxx_iscsi_transport = { ISCSI_HOST_IPADDRESS | ISCSI_HOST_INITIATOR_NAME, .sessiondata_size = sizeof(struct ddb_entry), - .host_template = &qla4xxx_driver_template, .tgt_dscvr = qla4xxx_tgt_dscvr, .get_conn_param = qla4xxx_conn_get_param, diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index 5577a60bec4e..9c00a157b485 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -101,12 +101,10 @@ show_transport_##name(struct device *dev, \ static DEVICE_ATTR(name, S_IRUGO, show_transport_##name, NULL); show_transport_attr(caps, "0x%x"); -show_transport_attr(max_lun, "%d"); static struct attribute *iscsi_transport_attrs[] = { &dev_attr_handle.attr, &dev_attr_caps.attr, - &dev_attr_max_lun.attr, NULL, }; @@ -1034,8 +1032,7 @@ iscsi_if_create_session(struct iscsi_internal *priv, struct iscsi_uevent *ev, } } - session = transport->create_session(transport, &priv->t, shost, - cmds_max, queue_depth, + session = transport->create_session(shost, cmds_max, queue_depth, initial_cmdsn, &host_no); if (shost) scsi_host_put(shost); diff --git a/include/scsi/iscsi_if.h b/include/scsi/iscsi_if.h index 1883c85cd3ee..801a677777cc 100644 --- a/include/scsi/iscsi_if.h +++ b/include/scsi/iscsi_if.h @@ -310,13 +310,6 @@ enum iscsi_host_param { #define iscsi_ptr(_handle) ((void*)(unsigned long)_handle) #define iscsi_handle(_ptr) ((uint64_t)(unsigned long)_ptr) -#define hostdata_session(_hostdata) (iscsi_ptr(*(unsigned long *)_hostdata)) - -/** - * iscsi_hostdata - get LLD hostdata from scsi_host - * @_hostdata: pointer to scsi host's hostdata - **/ -#define iscsi_hostdata(_hostdata) ((void*)_hostdata + sizeof(unsigned long)) /* * These flags presents iSCSI Data-Path capabilities. diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index f24cf0246739..8a6271c20935 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -209,9 +209,6 @@ struct iscsi_conn { /* remote portal currently connected to */ int portal_port; char portal_address[ISCSI_ADDRESS_BUF_LEN]; - /* local address */ - int local_port; - char local_address[ISCSI_ADDRESS_BUF_LEN]; /* MIB-statistics */ uint64_t txdata_octets; @@ -247,6 +244,7 @@ enum { }; struct iscsi_session { + struct iscsi_cls_session *cls_session; /* * Syncs up the scsi eh thread with the iscsi eh thread when sending * task management functions. This must be taken before the session @@ -282,10 +280,6 @@ struct iscsi_session { char *password; char *password_in; char *targetname; - char *initiatorname; - /* hw address or netdev iscsi connection is bound to */ - char *hwaddress; - char *netdev; /* control data */ struct iscsi_transport *tt; struct Scsi_Host *host; @@ -307,6 +301,16 @@ struct iscsi_session { struct iscsi_pool mgmtpool; /* Mgmt PDU's pool */ }; +struct iscsi_host { + char *initiatorname; + /* hw address or netdev iscsi connection is bound to */ + char *hwaddress; + char *netdev; + /* local address */ + int local_port; + char local_address[ISCSI_ADDRESS_BUF_LEN]; +}; + /* * scsi host template */ @@ -326,27 +330,24 @@ extern int iscsi_host_set_param(struct Scsi_Host *shost, int buflen); extern int iscsi_host_get_param(struct Scsi_Host *shost, enum iscsi_host_param param, char *buf); +extern void iscsi_host_setup(struct Scsi_Host *shost, uint16_t qdepth); +extern void iscsi_host_teardown(struct Scsi_Host *shost); /* * session management */ extern struct iscsi_cls_session * -iscsi_session_setup(struct iscsi_transport *, struct scsi_transport_template *, - uint16_t, uint16_t, int, int, uint32_t, uint32_t *); +iscsi_session_setup(struct iscsi_transport *, struct Scsi_Host *shost, + uint16_t, int, int, uint32_t); extern void iscsi_session_teardown(struct iscsi_cls_session *); -extern struct iscsi_session *class_to_transport_session(struct iscsi_cls_session *); extern void iscsi_session_recovery_timedout(struct iscsi_cls_session *); extern int iscsi_set_param(struct iscsi_cls_conn *cls_conn, enum iscsi_param param, char *buf, int buflen); extern int iscsi_session_get_param(struct iscsi_cls_session *cls_session, enum iscsi_param param, char *buf); -#define session_to_cls(_sess) \ - hostdata_session(_sess->host->hostdata) - #define iscsi_session_printk(prefix, _sess, fmt, a...) \ - iscsi_cls_session_printk(prefix, \ - (struct iscsi_cls_session *)session_to_cls(_sess), fmt, ##a) + iscsi_cls_session_printk(prefix, _sess->cls_session, fmt, ##a) /* * connection management diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index 728702292a80..702eda2904d7 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -83,15 +83,13 @@ struct iscsi_transport { /* LLD sets this to indicate what values it can export to sysfs */ uint64_t param_mask; uint64_t host_param_mask; - struct scsi_host_template *host_template; /* LLD connection data size */ int conndata_size; /* LLD session data size */ int sessiondata_size; - int max_lun; - struct iscsi_cls_session *(*create_session) (struct iscsi_transport *it, - struct scsi_transport_template *t, struct Scsi_Host *shost, - uint16_t cmds_max, uint16_t qdepth, uint32_t sn, uint32_t *hn); + struct iscsi_cls_session *(*create_session) (struct Scsi_Host *shost, + uint16_t cmds_max, uint16_t qdepth, + uint32_t sn, uint32_t *hn); void (*destroy_session) (struct iscsi_cls_session *session); struct iscsi_cls_conn *(*create_conn) (struct iscsi_cls_session *sess, uint32_t cid); -- cgit v1.2.3 From a4804cd6eb19318ae8d08ea967cfeaaf5c5b68a6 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:00 -0500 Subject: [SCSI] iscsi: add iscsi host helpers This finishes the host/session unbinding, by adding some helpers to add and remove hosts and the session they manage. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 17 ++++----- drivers/scsi/iscsi_tcp.c | 18 ++++------ drivers/scsi/libiscsi.c | 60 ++++++++++++++++++++++++++++---- drivers/scsi/scsi_transport_iscsi.c | 20 +++++++++++ include/scsi/libiscsi.h | 11 ++++-- include/scsi/scsi_transport_iscsi.h | 4 +++ 6 files changed, 99 insertions(+), 31 deletions(-) (limited to 'include') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index 5a750042e2b2..62e35e503e49 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -371,10 +371,8 @@ static void iscsi_iser_session_destroy(struct iscsi_cls_session *cls_session) { struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); - iscsi_session_teardown(cls_session); - scsi_remove_host(shost); - iscsi_host_teardown(shost); - scsi_host_put(shost); + iscsi_host_remove(shost); + iscsi_host_free(shost); } static struct iscsi_cls_session * @@ -396,7 +394,7 @@ iscsi_iser_session_create(struct Scsi_Host *shost, return NULL; } - shost = scsi_host_alloc(&iscsi_iser_sht, 0); + shost = iscsi_host_alloc(&iscsi_iser_sht, 0, ISCSI_MAX_CMD_PER_LUN); if (!shost) return NULL; shost->transportt = iscsi_iser_scsi_transport; @@ -405,9 +403,7 @@ iscsi_iser_session_create(struct Scsi_Host *shost, shost->max_channel = 0; shost->max_cmd_len = 16; - iscsi_host_setup(shost, qdepth); - - if (scsi_add_host(shost, NULL)) + if (iscsi_host_add(shost, NULL)) goto free_host; *hostno = shost->host_no; @@ -443,10 +439,9 @@ iscsi_iser_session_create(struct Scsi_Host *shost, return cls_session; remove_host: - scsi_remove_host(shost); + iscsi_host_remove(shost); free_host: - iscsi_host_teardown(shost); - scsi_host_put(shost); + iscsi_host_free(shost); return NULL; } diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 8cdcaf33fb4e..e19d92f2d753 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -1866,7 +1866,7 @@ iscsi_tcp_session_create(struct Scsi_Host *shost, uint16_t cmds_max, return NULL; } - shost = scsi_host_alloc(&iscsi_sht, sizeof(struct iscsi_host)); + shost = iscsi_host_alloc(&iscsi_sht, 0, qdepth); if (!shost) return NULL; shost->transportt = iscsi_tcp_scsi_transport; @@ -1874,10 +1874,9 @@ iscsi_tcp_session_create(struct Scsi_Host *shost, uint16_t cmds_max, shost->max_id = 0; shost->max_channel = 0; shost->max_cmd_len = 16; + shost->can_queue = cmds_max; - iscsi_host_setup(shost, qdepth); - - if (scsi_add_host(shost, NULL)) + if (iscsi_host_add(shost, NULL)) goto free_host; *hostno = shost->host_no; @@ -1912,10 +1911,9 @@ iscsi_tcp_session_create(struct Scsi_Host *shost, uint16_t cmds_max, remove_session: iscsi_session_teardown(cls_session); remove_host: - scsi_remove_host(shost); + iscsi_host_remove(shost); free_host: - iscsi_host_teardown(shost); - scsi_host_put(shost); + iscsi_host_free(shost); return NULL; } @@ -1924,11 +1922,9 @@ static void iscsi_tcp_session_destroy(struct iscsi_cls_session *cls_session) struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); iscsi_r2tpool_free(cls_session->dd_data); - iscsi_session_teardown(cls_session); - scsi_remove_host(shost); - iscsi_host_teardown(shost); - scsi_host_put(shost); + iscsi_host_remove(shost); + iscsi_host_free(shost); } static int iscsi_tcp_slave_configure(struct scsi_device *sdev) diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index 64b1dd827366..73c37c04ca66 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -1764,8 +1764,39 @@ void iscsi_pool_free(struct iscsi_pool *q) } EXPORT_SYMBOL_GPL(iscsi_pool_free); -void iscsi_host_setup(struct Scsi_Host *shost, uint16_t qdepth) +/** + * iscsi_host_add - add host to system + * @shost: scsi host + * @pdev: parent device + * + * This should be called by partial offload and software iscsi drivers + * to add a host to the system. + */ +int iscsi_host_add(struct Scsi_Host *shost, struct device *pdev) +{ + return scsi_add_host(shost, pdev); +} +EXPORT_SYMBOL_GPL(iscsi_host_add); + +/** + * iscsi_host_alloc - allocate a host and driver data + * @sht: scsi host template + * @dd_data_size: driver host data size + * @qdepth: default device queue depth + * + * This should be called by partial offload and software iscsi drivers. + * To access the driver specific memory use the iscsi_host_priv() macro. + */ +struct Scsi_Host *iscsi_host_alloc(struct scsi_host_template *sht, + int dd_data_size, uint16_t qdepth) { + struct Scsi_Host *shost; + + shost = scsi_host_alloc(sht, sizeof(struct iscsi_host) + dd_data_size); + if (!shost) + return NULL; + shost->transportt->eh_timed_out = iscsi_eh_cmd_timed_out; + if (qdepth > ISCSI_MAX_CMD_PER_LUN || qdepth < 1) { if (qdepth != 0) printk(KERN_ERR "iscsi: invalid queue depth of %d. " @@ -1773,22 +1804,37 @@ void iscsi_host_setup(struct Scsi_Host *shost, uint16_t qdepth) qdepth, ISCSI_MAX_CMD_PER_LUN); qdepth = ISCSI_DEF_CMD_PER_LUN; } - - shost->transportt->create_work_queue = 1; - shost->transportt->eh_timed_out = iscsi_eh_cmd_timed_out; shost->cmd_per_lun = qdepth; + return shost; +} +EXPORT_SYMBOL_GPL(iscsi_host_alloc); + +/** + * iscsi_host_remove - remove host and sessions + * @shost: scsi host + * + * This will also remove any sessions attached to the host, but if userspace + * is managing the session at the same time this will break. TODO: add + * refcounting to the netlink iscsi interface so a rmmod or host hot unplug + * does not remove the memory from under us. + */ +void iscsi_host_remove(struct Scsi_Host *shost) +{ + iscsi_host_for_each_session(shost, iscsi_session_teardown); + scsi_remove_host(shost); } -EXPORT_SYMBOL_GPL(iscsi_host_setup); +EXPORT_SYMBOL_GPL(iscsi_host_remove); -void iscsi_host_teardown(struct Scsi_Host *shost) +void iscsi_host_free(struct Scsi_Host *shost) { struct iscsi_host *ihost = shost_priv(shost); kfree(ihost->netdev); kfree(ihost->hwaddress); kfree(ihost->initiatorname); + scsi_host_put(shost); } -EXPORT_SYMBOL_GPL(iscsi_host_teardown); +EXPORT_SYMBOL_GPL(iscsi_host_free); /** * iscsi_session_setup - create iscsi cls session and host and session diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index 9c00a157b485..6fdaa2ee6632 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -279,6 +279,24 @@ static int iscsi_is_session_dev(const struct device *dev) return dev->release == iscsi_session_release; } +static int iscsi_iter_session_fn(struct device *dev, void *data) +{ + void (* fn) (struct iscsi_cls_session *) = data; + + if (!iscsi_is_session_dev(dev)) + return 0; + fn(iscsi_dev_to_session(dev)); + return 0; +} + +void iscsi_host_for_each_session(struct Scsi_Host *shost, + void (*fn)(struct iscsi_cls_session *)) +{ + device_for_each_child(&shost->shost_gendev, fn, + iscsi_iter_session_fn); +} +EXPORT_SYMBOL_GPL(iscsi_host_for_each_session); + /** * iscsi_scan_finished - helper to report when running scans are done * @shost: scsi host @@ -1599,6 +1617,8 @@ iscsi_register_transport(struct iscsi_transport *tt) priv->daemon_pid = -1; priv->iscsi_transport = tt; priv->t.user_scan = iscsi_user_scan; + if (!(tt->caps & CAP_DATA_PATH_OFFLOAD)) + priv->t.create_work_queue = 1; priv->dev.class = &iscsi_transport_class; snprintf(priv->dev.bus_id, BUS_ID_SIZE, "%s", tt->name); diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index 8a6271c20935..9a26d715a953 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -32,6 +32,7 @@ #include struct scsi_transport_template; +struct scsi_host_template; struct scsi_device; struct Scsi_Host; struct scsi_cmnd; @@ -41,6 +42,7 @@ struct iscsi_cls_session; struct iscsi_cls_conn; struct iscsi_session; struct iscsi_nopin; +struct device; /* #define DEBUG_SCSI */ #ifdef DEBUG_SCSI @@ -311,6 +313,8 @@ struct iscsi_host { char local_address[ISCSI_ADDRESS_BUF_LEN]; }; +#define iscsi_host_priv(_shost) \ + (shost_priv(_shost) + sizeof(struct iscsi_host)) /* * scsi host template */ @@ -330,8 +334,11 @@ extern int iscsi_host_set_param(struct Scsi_Host *shost, int buflen); extern int iscsi_host_get_param(struct Scsi_Host *shost, enum iscsi_host_param param, char *buf); -extern void iscsi_host_setup(struct Scsi_Host *shost, uint16_t qdepth); -extern void iscsi_host_teardown(struct Scsi_Host *shost); +extern int iscsi_host_add(struct Scsi_Host *shost, struct device *pdev); +extern struct Scsi_Host *iscsi_host_alloc(struct scsi_host_template *sht, + int dd_data_size, uint16_t qdepth); +extern void iscsi_host_remove(struct Scsi_Host *shost); +extern void iscsi_host_free(struct Scsi_Host *shost); /* * session management diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index 702eda2904d7..761f62da7cc8 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -207,6 +207,10 @@ struct iscsi_cls_host { char scan_workq_name[KOBJ_NAME_LEN]; }; +extern void iscsi_host_for_each_session(struct Scsi_Host *shost, + void (*fn)(struct iscsi_cls_session *)); + + /* * session and connection functions that can be used by HW iSCSI LLDs */ -- cgit v1.2.3 From 5d91e209fb21fb9cc765729d4c6a85a9fb6c9187 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:01 -0500 Subject: [SCSI] iscsi: remove session/conn_data_size from iscsi_transport This removes the session and conn data_size fields from the iscsi_transport. Just pass in the value like with host allocation. This patch also makes it so the LLD iscsi_conn data is allocated with the iscsi_cls_conn. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 16 +++------------- drivers/scsi/iscsi_tcp.c | 19 +++++-------------- drivers/scsi/libiscsi.c | 15 ++++++++++----- drivers/scsi/qla4xxx/ql4_os.c | 7 +++---- drivers/scsi/scsi_transport_iscsi.c | 24 ++++++++++++------------ include/scsi/libiscsi.h | 8 ++++---- include/scsi/scsi_transport_iscsi.h | 9 +++------ 7 files changed, 40 insertions(+), 58 deletions(-) (limited to 'include') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index 62e35e503e49..9b34946eb00d 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -279,7 +279,7 @@ iscsi_iser_conn_create(struct iscsi_cls_session *cls_session, uint32_t conn_idx) struct iscsi_cls_conn *cls_conn; struct iscsi_iser_conn *iser_conn; - cls_conn = iscsi_conn_setup(cls_session, conn_idx); + cls_conn = iscsi_conn_setup(cls_session, sizeof(*iser_conn), conn_idx); if (!cls_conn) return NULL; conn = cls_conn->dd_data; @@ -290,10 +290,7 @@ iscsi_iser_conn_create(struct iscsi_cls_session *cls_session, uint32_t conn_idx) */ conn->max_recv_dlength = 128; - iser_conn = kzalloc(sizeof(*iser_conn), GFP_KERNEL); - if (!iser_conn) - goto conn_alloc_fail; - + iser_conn = conn->dd_data; /* currently this is the only field which need to be initiated */ rwlock_init(&iser_conn->lock); @@ -301,10 +298,6 @@ iscsi_iser_conn_create(struct iscsi_cls_session *cls_session, uint32_t conn_idx) iser_conn->iscsi_conn = conn; return cls_conn; - -conn_alloc_fail: - iscsi_conn_teardown(cls_conn); - return NULL; } static void @@ -313,10 +306,9 @@ iscsi_iser_conn_destroy(struct iscsi_cls_conn *cls_conn) struct iscsi_conn *conn = cls_conn->dd_data; struct iscsi_iser_conn *iser_conn = conn->dd_data; - iscsi_conn_teardown(cls_conn); if (iser_conn->ib_conn) iser_conn->ib_conn->iser_conn = NULL; - kfree(iser_conn); + iscsi_conn_teardown(cls_conn); } static int @@ -619,8 +611,6 @@ static struct iscsi_transport iscsi_iser_transport = { .host_param_mask = ISCSI_HOST_HWADDRESS | ISCSI_HOST_NETDEV_NAME | ISCSI_HOST_INITIATOR_NAME, - .conndata_size = sizeof(struct iscsi_conn), - .sessiondata_size = sizeof(struct iscsi_session), /* session management */ .create_session = iscsi_iser_session_create, .destroy_session = iscsi_iser_session_destroy, diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index e19d92f2d753..dfaf9fa57340 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -1490,7 +1490,7 @@ iscsi_tcp_conn_create(struct iscsi_cls_session *cls_session, uint32_t conn_idx) struct iscsi_cls_conn *cls_conn; struct iscsi_tcp_conn *tcp_conn; - cls_conn = iscsi_conn_setup(cls_session, conn_idx); + cls_conn = iscsi_conn_setup(cls_session, sizeof(*tcp_conn), conn_idx); if (!cls_conn) return NULL; conn = cls_conn->dd_data; @@ -1500,18 +1500,14 @@ iscsi_tcp_conn_create(struct iscsi_cls_session *cls_session, uint32_t conn_idx) */ conn->max_recv_dlength = ISCSI_DEF_MAX_RECV_SEG_LEN; - tcp_conn = kzalloc(sizeof(*tcp_conn), GFP_KERNEL); - if (!tcp_conn) - goto tcp_conn_alloc_fail; - - conn->dd_data = tcp_conn; + tcp_conn = conn->dd_data; tcp_conn->iscsi_conn = conn; tcp_conn->tx_hash.tfm = crypto_alloc_hash("crc32c", 0, CRYPTO_ALG_ASYNC); tcp_conn->tx_hash.flags = 0; if (IS_ERR(tcp_conn->tx_hash.tfm)) - goto free_tcp_conn; + goto free_conn; tcp_conn->rx_hash.tfm = crypto_alloc_hash("crc32c", 0, CRYPTO_ALG_ASYNC); @@ -1523,14 +1519,12 @@ iscsi_tcp_conn_create(struct iscsi_cls_session *cls_session, uint32_t conn_idx) free_tx_tfm: crypto_free_hash(tcp_conn->tx_hash.tfm); -free_tcp_conn: +free_conn: iscsi_conn_printk(KERN_ERR, conn, "Could not create connection due to crc32c " "loading error. Make sure the crc32c " "module is built as a module or into the " "kernel\n"); - kfree(tcp_conn); -tcp_conn_alloc_fail: iscsi_conn_teardown(cls_conn); return NULL; } @@ -1563,14 +1557,13 @@ iscsi_tcp_conn_destroy(struct iscsi_cls_conn *cls_conn) struct iscsi_tcp_conn *tcp_conn = conn->dd_data; iscsi_tcp_release_conn(conn); - iscsi_conn_teardown(cls_conn); if (tcp_conn->tx_hash.tfm) crypto_free_hash(tcp_conn->tx_hash.tfm); if (tcp_conn->rx_hash.tfm) crypto_free_hash(tcp_conn->rx_hash.tfm); - kfree(tcp_conn); + iscsi_conn_teardown(cls_conn); } static void @@ -1983,8 +1976,6 @@ static struct iscsi_transport iscsi_tcp_transport = { .host_param_mask = ISCSI_HOST_HWADDRESS | ISCSI_HOST_IPADDRESS | ISCSI_HOST_INITIATOR_NAME | ISCSI_HOST_NETDEV_NAME, - .conndata_size = sizeof(struct iscsi_conn), - .sessiondata_size = sizeof(struct iscsi_session), /* session management */ .create_session = iscsi_tcp_session_create, .destroy_session = iscsi_tcp_session_destroy, diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index 73c37c04ca66..784a935fad4a 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -1867,7 +1867,8 @@ iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, cmds_max = ISCSI_DEF_XMIT_CMDS_MAX; } - cls_session = iscsi_alloc_session(shost, iscsit); + cls_session = iscsi_alloc_session(shost, iscsit, + sizeof(struct iscsi_session)); if (!cls_session) return NULL; session = cls_session->dd_data; @@ -1968,22 +1969,26 @@ EXPORT_SYMBOL_GPL(iscsi_session_teardown); /** * iscsi_conn_setup - create iscsi_cls_conn and iscsi_conn * @cls_session: iscsi_cls_session + * @dd_size: private driver data size * @conn_idx: cid - **/ + */ struct iscsi_cls_conn * -iscsi_conn_setup(struct iscsi_cls_session *cls_session, uint32_t conn_idx) +iscsi_conn_setup(struct iscsi_cls_session *cls_session, int dd_size, + uint32_t conn_idx) { struct iscsi_session *session = cls_session->dd_data; struct iscsi_conn *conn; struct iscsi_cls_conn *cls_conn; char *data; - cls_conn = iscsi_create_conn(cls_session, conn_idx); + cls_conn = iscsi_create_conn(cls_session, sizeof(*conn) + dd_size, + conn_idx); if (!cls_conn) return NULL; conn = cls_conn->dd_data; - memset(conn, 0, sizeof(*conn)); + memset(conn, 0, sizeof(*conn) + dd_size); + conn->dd_data = cls_conn->dd_data + sizeof(*conn); conn->session = session; conn->cls_conn = cls_conn; conn->c_stage = ISCSI_CONN_INITIAL_STAGE; diff --git a/drivers/scsi/qla4xxx/ql4_os.c b/drivers/scsi/qla4xxx/ql4_os.c index 6c6ee0f34995..5822dd595826 100644 --- a/drivers/scsi/qla4xxx/ql4_os.c +++ b/drivers/scsi/qla4xxx/ql4_os.c @@ -113,8 +113,6 @@ static struct iscsi_transport qla4xxx_iscsi_transport = { .host_param_mask = ISCSI_HOST_HWADDRESS | ISCSI_HOST_IPADDRESS | ISCSI_HOST_INITIATOR_NAME, - .sessiondata_size = sizeof(struct ddb_entry), - .tgt_dscvr = qla4xxx_tgt_dscvr, .get_conn_param = qla4xxx_conn_get_param, .get_session_param = qla4xxx_sess_get_param, @@ -274,7 +272,7 @@ int qla4xxx_add_sess(struct ddb_entry *ddb_entry) return err; } - ddb_entry->conn = iscsi_create_conn(ddb_entry->sess, 0); + ddb_entry->conn = iscsi_create_conn(ddb_entry->sess, 0, 0); if (!ddb_entry->conn) { iscsi_remove_session(ddb_entry->sess); DEBUG2(printk(KERN_ERR "Could not add connection.\n")); @@ -291,7 +289,8 @@ struct ddb_entry *qla4xxx_alloc_sess(struct scsi_qla_host *ha) struct ddb_entry *ddb_entry; struct iscsi_cls_session *sess; - sess = iscsi_alloc_session(ha->host, &qla4xxx_iscsi_transport); + sess = iscsi_alloc_session(ha->host, &qla4xxx_iscsi_transport, + sizeof(struct ddb_entry)); if (!sess) return NULL; diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index 6fdaa2ee6632..6b8516a0970b 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -483,12 +483,12 @@ static int iscsi_unbind_session(struct iscsi_cls_session *session) } struct iscsi_cls_session * -iscsi_alloc_session(struct Scsi_Host *shost, - struct iscsi_transport *transport) +iscsi_alloc_session(struct Scsi_Host *shost, struct iscsi_transport *transport, + int dd_size) { struct iscsi_cls_session *session; - session = kzalloc(sizeof(*session) + transport->sessiondata_size, + session = kzalloc(sizeof(*session) + dd_size, GFP_KERNEL); if (!session) return NULL; @@ -510,7 +510,7 @@ iscsi_alloc_session(struct Scsi_Host *shost, session->dev.parent = &shost->shost_gendev; session->dev.release = iscsi_session_release; device_initialize(&session->dev); - if (transport->sessiondata_size) + if (dd_size) session->dd_data = &session[1]; return session; } @@ -558,18 +558,18 @@ EXPORT_SYMBOL_GPL(iscsi_add_session); * iscsi_create_session - create iscsi class session * @shost: scsi host * @transport: iscsi transport + * @dd_size: private driver data size * @target_id: which target * * This can be called from a LLD or iscsi_transport. */ struct iscsi_cls_session * -iscsi_create_session(struct Scsi_Host *shost, - struct iscsi_transport *transport, - unsigned int target_id) +iscsi_create_session(struct Scsi_Host *shost, struct iscsi_transport *transport, + int dd_size, unsigned int target_id) { struct iscsi_cls_session *session; - session = iscsi_alloc_session(shost, transport); + session = iscsi_alloc_session(shost, transport, dd_size); if (!session) return NULL; @@ -671,6 +671,7 @@ EXPORT_SYMBOL_GPL(iscsi_destroy_session); /** * iscsi_create_conn - create iscsi class connection * @session: iscsi cls session + * @dd_size: private driver data size * @cid: connection id * * This can be called from a LLD or iscsi_transport. The connection @@ -683,18 +684,17 @@ EXPORT_SYMBOL_GPL(iscsi_destroy_session); * non-zero. */ struct iscsi_cls_conn * -iscsi_create_conn(struct iscsi_cls_session *session, uint32_t cid) +iscsi_create_conn(struct iscsi_cls_session *session, int dd_size, uint32_t cid) { struct iscsi_transport *transport = session->transport; struct iscsi_cls_conn *conn; unsigned long flags; int err; - conn = kzalloc(sizeof(*conn) + transport->conndata_size, GFP_KERNEL); + conn = kzalloc(sizeof(*conn) + dd_size, GFP_KERNEL); if (!conn) return NULL; - - if (transport->conndata_size) + if (dd_size) conn->dd_data = &conn[1]; INIT_LIST_HEAD(&conn->conn_list); diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index 9a26d715a953..4e1c14f20ddd 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -313,8 +313,6 @@ struct iscsi_host { char local_address[ISCSI_ADDRESS_BUF_LEN]; }; -#define iscsi_host_priv(_shost) \ - (shost_priv(_shost) + sizeof(struct iscsi_host)) /* * scsi host template */ @@ -325,10 +323,12 @@ extern int iscsi_eh_device_reset(struct scsi_cmnd *sc); extern int iscsi_queuecommand(struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *)); - /* * iSCSI host helpers. */ +#define iscsi_host_priv(_shost) \ + (shost_priv(_shost) + sizeof(struct iscsi_host)) + extern int iscsi_host_set_param(struct Scsi_Host *shost, enum iscsi_host_param param, char *buf, int buflen); @@ -360,7 +360,7 @@ extern int iscsi_session_get_param(struct iscsi_cls_session *cls_session, * connection management */ extern struct iscsi_cls_conn *iscsi_conn_setup(struct iscsi_cls_session *, - uint32_t); + int, uint32_t); extern void iscsi_conn_teardown(struct iscsi_cls_conn *); extern int iscsi_conn_start(struct iscsi_cls_conn *); extern void iscsi_conn_stop(struct iscsi_cls_conn *, int); diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index 761f62da7cc8..4028f121d548 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -83,10 +83,6 @@ struct iscsi_transport { /* LLD sets this to indicate what values it can export to sysfs */ uint64_t param_mask; uint64_t host_param_mask; - /* LLD connection data size */ - int conndata_size; - /* LLD session data size */ - int sessiondata_size; struct iscsi_cls_session *(*create_session) (struct Scsi_Host *shost, uint16_t cmds_max, uint16_t qdepth, uint32_t sn, uint32_t *hn); @@ -222,19 +218,20 @@ extern void iscsi_host_for_each_session(struct Scsi_Host *shost, extern int iscsi_session_chkready(struct iscsi_cls_session *session); extern struct iscsi_cls_session *iscsi_alloc_session(struct Scsi_Host *shost, - struct iscsi_transport *transport); + struct iscsi_transport *transport, int dd_size); extern int iscsi_add_session(struct iscsi_cls_session *session, unsigned int target_id); extern int iscsi_session_event(struct iscsi_cls_session *session, enum iscsi_uevent_e event); extern struct iscsi_cls_session *iscsi_create_session(struct Scsi_Host *shost, struct iscsi_transport *t, + int dd_size, unsigned int target_id); extern void iscsi_remove_session(struct iscsi_cls_session *session); extern void iscsi_free_session(struct iscsi_cls_session *session); extern int iscsi_destroy_session(struct iscsi_cls_session *session); extern struct iscsi_cls_conn *iscsi_create_conn(struct iscsi_cls_session *sess, - uint32_t cid); + int dd_size, uint32_t cid); extern int iscsi_destroy_conn(struct iscsi_cls_conn *conn); extern void iscsi_unblock_session(struct iscsi_cls_session *session); extern void iscsi_block_session(struct iscsi_cls_session *session); -- cgit v1.2.3 From 5af3e91d232b7e022f258202f72ebb79b8b0c706 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:02 -0500 Subject: [SCSI] iscsi: modify iscsi printk so it can take driver data pointers Some drivers want to be able to just pass in the driver data pointers to the iscsi objects. To enable this we need the iscsi printk macro to cast the object. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- include/scsi/libiscsi.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index 4e1c14f20ddd..f54aeb1e8ae3 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -369,9 +369,11 @@ extern int iscsi_conn_bind(struct iscsi_cls_session *, struct iscsi_cls_conn *, extern void iscsi_conn_failure(struct iscsi_conn *conn, enum iscsi_err err); extern int iscsi_conn_get_param(struct iscsi_cls_conn *cls_conn, enum iscsi_param param, char *buf); +extern void iscsi_suspend_tx(struct iscsi_conn *conn); #define iscsi_conn_printk(prefix, _c, fmt, a...) \ - iscsi_cls_conn_printk(prefix, _c->cls_conn, fmt, ##a) + iscsi_cls_conn_printk(prefix, ((struct iscsi_conn *)_c)->cls_conn, \ + fmt, ##a) /* * pdu and task processing -- cgit v1.2.3 From 0af967f5d4f2dd1e00618d34ac988037d37a6c3b Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:04 -0500 Subject: [SCSI] libiscsi, iscsi_tcp, iser: add session cmds array accessor Currently to get a ctask from the session cmd array, you have to know to use the itt modifier. To make this easier on LLDs and so in the future we can easilly kill the session array and use the host shared map instead, this patch adds a nice wrapper to strip the itt into a session->cmds index and return a ctask. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 8 +--- drivers/infiniband/ulp/iser/iser_initiator.c | 23 +++++------ drivers/scsi/iscsi_tcp.c | 13 ++++-- drivers/scsi/libiscsi.c | 60 ++++++++++++++++++++-------- include/scsi/libiscsi.h | 4 +- 5 files changed, 65 insertions(+), 43 deletions(-) (limited to 'include') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index 8a1bfb7277c8..7b1468869066 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -98,7 +98,6 @@ iscsi_iser_recv(struct iscsi_conn *conn, struct iscsi_hdr *hdr, char *rx_data, int rx_data_len) { int rc = 0; - uint32_t ret_itt; int datalen; int ahslen; @@ -114,12 +113,7 @@ iscsi_iser_recv(struct iscsi_conn *conn, /* read AHS */ ahslen = hdr->hlength * 4; - /* verify itt (itt encoding: age+cid+itt) */ - rc = iscsi_verify_itt(conn, hdr, &ret_itt); - - if (!rc) - rc = iscsi_complete_pdu(conn, hdr, rx_data, rx_data_len); - + rc = iscsi_complete_pdu(conn, hdr, rx_data, rx_data_len); if (rc && rc != ISCSI_ERR_NO_SCSI_CMD) goto error; diff --git a/drivers/infiniband/ulp/iser/iser_initiator.c b/drivers/infiniband/ulp/iser/iser_initiator.c index 08dc81c46f41..b82a5f2d4d37 100644 --- a/drivers/infiniband/ulp/iser/iser_initiator.c +++ b/drivers/infiniband/ulp/iser/iser_initiator.c @@ -537,13 +537,11 @@ void iser_rcv_completion(struct iser_desc *rx_desc, { struct iser_dto *dto = &rx_desc->dto; struct iscsi_iser_conn *conn = dto->ib_conn->iser_conn; - struct iscsi_session *session = conn->iscsi_conn->session; struct iscsi_cmd_task *ctask; struct iscsi_iser_cmd_task *iser_ctask; struct iscsi_hdr *hdr; char *rx_data = NULL; int rx_data_len = 0; - unsigned int itt; unsigned char opcode; hdr = &rx_desc->iscsi_header; @@ -559,19 +557,18 @@ void iser_rcv_completion(struct iser_desc *rx_desc, opcode = hdr->opcode & ISCSI_OPCODE_MASK; if (opcode == ISCSI_OP_SCSI_CMD_RSP) { - itt = get_itt(hdr->itt); /* mask out cid and age bits */ - if (!(itt < session->cmds_max)) + ctask = iscsi_itt_to_ctask(conn->iscsi_conn, hdr->itt); + if (!ctask) iser_err("itt can't be matched to task!!! " - "conn %p opcode %d cmds_max %d itt %d\n", - conn->iscsi_conn,opcode,session->cmds_max,itt); - /* use the mapping given with the cmds array indexed by itt */ - ctask = (struct iscsi_cmd_task *)session->cmds[itt]; - iser_ctask = ctask->dd_data; - iser_dbg("itt %d ctask %p\n",itt,ctask); - iser_ctask->status = ISER_TASK_STATUS_COMPLETED; - iser_ctask_rdma_finalize(iser_ctask); + "conn %p opcode %d itt %d\n", + conn->iscsi_conn, opcode, hdr->itt); + else { + iser_ctask = ctask->dd_data; + iser_dbg("itt %d ctask %p\n",hdr->itt, ctask); + iser_ctask->status = ISER_TASK_STATUS_COMPLETED; + iser_ctask_rdma_finalize(iser_ctask); + } } - iser_dto_buffs_release(dto); iscsi_iser_recv(conn->iscsi_conn, hdr, rx_data, rx_data_len); diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index dfaf9fa57340..f2a08f7ed902 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -740,7 +740,6 @@ iscsi_tcp_hdr_dissect(struct iscsi_conn *conn, struct iscsi_hdr *hdr) struct iscsi_session *session = conn->session; struct iscsi_tcp_conn *tcp_conn = conn->dd_data; struct iscsi_cmd_task *ctask; - uint32_t itt; /* verify PDU length */ tcp_conn->in.datalen = ntoh24(hdr->dlength); @@ -758,7 +757,7 @@ iscsi_tcp_hdr_dissect(struct iscsi_conn *conn, struct iscsi_hdr *hdr) opcode = hdr->opcode & ISCSI_OPCODE_MASK; /* verify itt (itt encoding: age+cid+itt) */ - rc = iscsi_verify_itt(conn, hdr, &itt); + rc = iscsi_verify_itt(conn, hdr->itt); if (rc) return rc; @@ -767,7 +766,10 @@ iscsi_tcp_hdr_dissect(struct iscsi_conn *conn, struct iscsi_hdr *hdr) switch(opcode) { case ISCSI_OP_SCSI_DATA_IN: - ctask = session->cmds[itt]; + ctask = iscsi_itt_to_ctask(conn, hdr->itt); + if (!ctask) + return ISCSI_ERR_BAD_ITT; + spin_lock(&conn->session->lock); rc = iscsi_data_rsp(conn, ctask); spin_unlock(&conn->session->lock); @@ -810,7 +812,10 @@ iscsi_tcp_hdr_dissect(struct iscsi_conn *conn, struct iscsi_hdr *hdr) rc = iscsi_complete_pdu(conn, hdr, NULL, 0); break; case ISCSI_OP_R2T: - ctask = session->cmds[itt]; + ctask = iscsi_itt_to_ctask(conn, hdr->itt); + if (!ctask) + return ISCSI_ERR_BAD_ITT; + if (ahslen) rc = ISCSI_ERR_AHSLEN; else if (ctask->sc->sc_data_direction == DMA_TO_DEVICE) { diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index 79bc49fd7f12..4bc63c4b3c10 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -640,6 +640,10 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, uint32_t itt; conn->last_recv = jiffies; + rc = iscsi_verify_itt(conn, hdr->itt); + if (rc) + return rc; + if (hdr->itt != RESERVED_ITT) itt = get_itt(hdr->itt); else @@ -776,27 +780,22 @@ int iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, } EXPORT_SYMBOL_GPL(iscsi_complete_pdu); -/* verify itt (itt encoding: age+cid+itt) */ -int iscsi_verify_itt(struct iscsi_conn *conn, struct iscsi_hdr *hdr, - uint32_t *ret_itt) +int iscsi_verify_itt(struct iscsi_conn *conn, itt_t itt) { struct iscsi_session *session = conn->session; struct iscsi_cmd_task *ctask; - uint32_t itt; - if (hdr->itt != RESERVED_ITT) { - if (((__force u32)hdr->itt & ISCSI_AGE_MASK) != - (session->age << ISCSI_AGE_SHIFT)) { - iscsi_conn_printk(KERN_ERR, conn, - "received itt %x expected session " - "age (%x)\n", (__force u32)hdr->itt, - session->age & ISCSI_AGE_MASK); - return ISCSI_ERR_BAD_ITT; - } + if (itt == RESERVED_ITT) + return 0; - itt = get_itt(hdr->itt); - } else - itt = ~0U; + if (((__force u32)itt & ISCSI_AGE_MASK) != + (session->age << ISCSI_AGE_SHIFT)) { + iscsi_conn_printk(KERN_ERR, conn, + "received itt %x expected session age (%x)\n", + (__force u32)itt, + session->age & ISCSI_AGE_MASK); + return ISCSI_ERR_BAD_ITT; + } if (itt < session->cmds_max) { ctask = session->cmds[itt]; @@ -817,11 +816,38 @@ int iscsi_verify_itt(struct iscsi_conn *conn, struct iscsi_hdr *hdr, } } - *ret_itt = itt; return 0; } EXPORT_SYMBOL_GPL(iscsi_verify_itt); +struct iscsi_cmd_task * +iscsi_itt_to_ctask(struct iscsi_conn *conn, itt_t itt) +{ + struct iscsi_session *session = conn->session; + struct iscsi_cmd_task *ctask; + uint32_t i; + + if (iscsi_verify_itt(conn, itt)) + return NULL; + + if (itt == RESERVED_ITT) + return NULL; + + i = get_itt(itt); + if (i >= session->cmds_max) + return NULL; + + ctask = session->cmds[i]; + if (!ctask->sc) + return NULL; + + if (ctask->sc->SCp.phase != session->age) + return NULL; + + return ctask; +} +EXPORT_SYMBOL_GPL(iscsi_itt_to_ctask); + void iscsi_conn_failure(struct iscsi_conn *conn, enum iscsi_err err) { struct iscsi_session *session = conn->session; diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index f54aeb1e8ae3..9be6a70faff5 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -385,8 +385,8 @@ extern int iscsi_conn_send_pdu(struct iscsi_cls_conn *, struct iscsi_hdr *, char *, uint32_t); extern int iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *, char *, int); -extern int iscsi_verify_itt(struct iscsi_conn *, struct iscsi_hdr *, - uint32_t *); +extern int iscsi_verify_itt(struct iscsi_conn *, itt_t); +extern struct iscsi_cmd_task *iscsi_itt_to_ctask(struct iscsi_conn *, itt_t); extern void iscsi_requeue_ctask(struct iscsi_cmd_task *ctask); extern void iscsi_free_mgmt_task(struct iscsi_conn *conn, struct iscsi_mgmt_task *mtask); -- cgit v1.2.3 From 3e5c28ad0391389959ccae81c938c7533efb3490 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:06 -0500 Subject: [SCSI] libiscsi: merge iscsi_mgmt_task and iscsi_cmd_task There is no need to have the mgmt and cmd tasks separate structs. It used to save a lot of memory when we overprealocated memory for tasks, but the next patches will set up the driver so in the future they can use a mempool or some other common scsi command allocator and common tagging. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/scsi/libiscsi.c | 518 +++++++++++++++++------------------- include/scsi/libiscsi.h | 29 +- include/scsi/scsi_transport_iscsi.h | 41 ++- 3 files changed, 272 insertions(+), 316 deletions(-) (limited to 'include') diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index 1e605de07cff..ef92b1b0f16e 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -197,7 +197,7 @@ static int iscsi_prep_bidi_ahs(struct iscsi_cmd_task *ctask) /** * iscsi_prep_scsi_cmd_pdu - prep iscsi scsi cmd pdu - * @ctask: iscsi cmd task + * @ctask: iscsi task * * Prep basic iSCSI PDU fields for a scsi cmd pdu. The LLD should set * fields like dlength or final based on how much data it sends @@ -300,31 +300,31 @@ static int iscsi_prep_scsi_cmd_pdu(struct iscsi_cmd_task *ctask) WARN_ON(hdrlength >= 256); hdr->hlength = hdrlength & 0xFF; - if (conn->session->tt->init_cmd_task && - conn->session->tt->init_cmd_task(ctask)) + if (conn->session->tt->init_task && + conn->session->tt->init_task(ctask)) return -EIO; ctask->state = ISCSI_TASK_RUNNING; list_move_tail(&ctask->running, &conn->run_list); conn->scsicmd_pdus_cnt++; - debug_scsi("iscsi prep [%s cid %d sc %p cdb 0x%x itt 0x%x " - "len %d bidi_len %d cmdsn %d win %d]\n", - scsi_bidi_cmnd(sc) ? "bidirectional" : - sc->sc_data_direction == DMA_TO_DEVICE ? "write" : "read", - conn->id, sc, sc->cmnd[0], ctask->itt, - scsi_bufflen(sc), scsi_bidi_cmnd(sc) ? scsi_in(sc)->length : 0, - session->cmdsn, session->max_cmdsn - session->exp_cmdsn + 1); + debug_scsi("iscsi prep [%s cid %d sc %p cdb 0x%x itt 0x%x len %d " + "bidi_len %d cmdsn %d win %d]\n", scsi_bidi_cmnd(sc) ? + "bidirectional" : sc->sc_data_direction == DMA_TO_DEVICE ? + "write" : "read", conn->id, sc, sc->cmnd[0], ctask->itt, + scsi_bufflen(sc), + scsi_bidi_cmnd(sc) ? scsi_in(sc)->length : 0, + session->cmdsn, session->max_cmdsn - session->exp_cmdsn + 1); return 0; } /** - * iscsi_complete_command - return command back to scsi-ml + * iscsi_complete_command - finish a task * @ctask: iscsi cmd task * * Must be called with session lock. - * This function returns the scsi command to scsi-ml and returns - * the cmd task to the pool of available cmd tasks. + * This function returns the scsi command to scsi-ml or cleans + * up mgmt tasks then returns the task to the pool. */ static void iscsi_complete_command(struct iscsi_cmd_task *ctask) { @@ -332,17 +332,34 @@ static void iscsi_complete_command(struct iscsi_cmd_task *ctask) struct iscsi_session *session = conn->session; struct scsi_cmnd *sc = ctask->sc; + list_del_init(&ctask->running); ctask->state = ISCSI_TASK_COMPLETED; ctask->sc = NULL; - /* SCSI eh reuses commands to verify us */ - sc->SCp.ptr = NULL; + if (conn->ctask == ctask) conn->ctask = NULL; - list_del_init(&ctask->running); + /* + * login ctask is preallocated so do not free + */ + if (conn->login_ctask == ctask) + return; + __kfifo_put(session->cmdpool.queue, (void*)&ctask, sizeof(void*)); - if (sc->scsi_done) - sc->scsi_done(sc); + if (conn->ping_ctask == ctask) + conn->ping_ctask = NULL; + + if (sc) { + ctask->sc = NULL; + /* SCSI eh reuses commands to verify us */ + sc->SCp.ptr = NULL; + /* + * queue command may call this to free the task, but + * not have setup the sc callback + */ + if (sc->scsi_done) + sc->scsi_done(sc); + } } static void __iscsi_get_ctask(struct iscsi_cmd_task *ctask) @@ -356,6 +373,16 @@ static void __iscsi_put_ctask(struct iscsi_cmd_task *ctask) iscsi_complete_command(ctask); } +void iscsi_put_ctask(struct iscsi_cmd_task *ctask) +{ + struct iscsi_session *session = ctask->conn->session; + + spin_lock_bh(&session->lock); + __iscsi_put_ctask(ctask); + spin_unlock_bh(&session->lock); +} +EXPORT_SYMBOL_GPL(iscsi_put_ctask); + /* * session lock must be held */ @@ -375,47 +402,28 @@ static void fail_command(struct iscsi_conn *conn, struct iscsi_cmd_task *ctask, */ conn->session->queued_cmdsn--; else - conn->session->tt->cleanup_cmd_task(conn, ctask); + conn->session->tt->cleanup_task(conn, ctask); sc->result = err; + if (!scsi_bidi_cmnd(sc)) scsi_set_resid(sc, scsi_bufflen(sc)); else { scsi_out(sc)->resid = scsi_out(sc)->length; scsi_in(sc)->resid = scsi_in(sc)->length; } + if (conn->ctask == ctask) conn->ctask = NULL; /* release ref from queuecommand */ __iscsi_put_ctask(ctask); } -/** - * iscsi_free_mgmt_task - return mgmt task back to pool - * @conn: iscsi connection - * @mtask: mtask - * - * Must be called with session lock. - */ -void iscsi_free_mgmt_task(struct iscsi_conn *conn, - struct iscsi_mgmt_task *mtask) -{ - list_del_init(&mtask->running); - if (conn->login_mtask == mtask) - return; - - if (conn->ping_mtask == mtask) - conn->ping_mtask = NULL; - __kfifo_put(conn->session->mgmtpool.queue, - (void*)&mtask, sizeof(void*)); -} -EXPORT_SYMBOL_GPL(iscsi_free_mgmt_task); - -static int iscsi_prep_mtask(struct iscsi_conn *conn, - struct iscsi_mgmt_task *mtask) +static int iscsi_prep_mgmt_task(struct iscsi_conn *conn, + struct iscsi_cmd_task *ctask) { struct iscsi_session *session = conn->session; - struct iscsi_hdr *hdr = mtask->hdr; + struct iscsi_hdr *hdr = (struct iscsi_hdr *)ctask->hdr; struct iscsi_nopout *nop = (struct iscsi_nopout *)hdr; if (conn->session->state == ISCSI_STATE_LOGGING_OUT) @@ -429,7 +437,7 @@ static int iscsi_prep_mtask(struct iscsi_conn *conn, */ nop->cmdsn = cpu_to_be32(session->cmdsn); if (hdr->itt != RESERVED_ITT) { - hdr->itt = build_itt(mtask->itt, session->age); + hdr->itt = build_itt(ctask->itt, session->age); /* * TODO: We always use immediate, so we never hit this. * If we start to send tmfs or nops as non-immediate then @@ -442,25 +450,25 @@ static int iscsi_prep_mtask(struct iscsi_conn *conn, } } - if (session->tt->init_mgmt_task) - session->tt->init_mgmt_task(conn, mtask); + if (session->tt->init_task) + session->tt->init_task(ctask); if ((hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT) session->state = ISCSI_STATE_LOGGING_OUT; - list_move_tail(&mtask->running, &conn->mgmt_run_list); + list_move_tail(&ctask->running, &conn->mgmt_run_list); debug_scsi("mgmtpdu [op 0x%x hdr->itt 0x%x datalen %d]\n", hdr->opcode & ISCSI_OPCODE_MASK, hdr->itt, - mtask->data_count); + ctask->data_count); return 0; } -static struct iscsi_mgmt_task * +static struct iscsi_cmd_task * __iscsi_conn_send_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, char *data, uint32_t data_size) { struct iscsi_session *session = conn->session; - struct iscsi_mgmt_task *mtask; + struct iscsi_cmd_task *ctask; if (session->state == ISCSI_STATE_TERMINATE) return NULL; @@ -470,48 +478,56 @@ __iscsi_conn_send_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, /* * Login and Text are sent serially, in * request-followed-by-response sequence. - * Same mtask can be used. Same ITT must be used. - * Note that login_mtask is preallocated at conn_create(). + * Same task can be used. Same ITT must be used. + * Note that login_task is preallocated at conn_create(). */ - mtask = conn->login_mtask; + ctask = conn->login_ctask; else { BUG_ON(conn->c_stage == ISCSI_CONN_INITIAL_STAGE); BUG_ON(conn->c_stage == ISCSI_CONN_STOPPED); - if (!__kfifo_get(session->mgmtpool.queue, - (void*)&mtask, sizeof(void*))) + if (!__kfifo_get(session->cmdpool.queue, + (void*)&ctask, sizeof(void*))) return NULL; if ((hdr->opcode == (ISCSI_OP_NOOP_OUT | ISCSI_OP_IMMEDIATE)) && hdr->ttt == RESERVED_ITT) { - conn->ping_mtask = mtask; + conn->ping_ctask = ctask; conn->last_ping = jiffies; } } + /* + * released in complete pdu for task we expect a response for, and + * released by the lld when it has transmitted the task for + * pdus we do not expect a response for. + */ + atomic_set(&ctask->refcount, 1); + ctask->conn = conn; + ctask->sc = NULL; if (data_size) { - memcpy(mtask->data, data, data_size); - mtask->data_count = data_size; + memcpy(ctask->data, data, data_size); + ctask->data_count = data_size; } else - mtask->data_count = 0; + ctask->data_count = 0; - memcpy(mtask->hdr, hdr, sizeof(struct iscsi_hdr)); - INIT_LIST_HEAD(&mtask->running); - list_add_tail(&mtask->running, &conn->mgmtqueue); + memcpy(ctask->hdr, hdr, sizeof(struct iscsi_hdr)); + INIT_LIST_HEAD(&ctask->running); + list_add_tail(&ctask->running, &conn->mgmtqueue); if (session->tt->caps & CAP_DATA_PATH_OFFLOAD) { - if (iscsi_prep_mtask(conn, mtask)) { - iscsi_free_mgmt_task(conn, mtask); + if (iscsi_prep_mgmt_task(conn, ctask)) { + __iscsi_put_ctask(ctask); return NULL; } - if (session->tt->xmit_mgmt_task(conn, mtask)) - mtask = NULL; + if (session->tt->xmit_task(ctask)) + ctask = NULL; } else scsi_queue_work(conn->session->host, &conn->xmitwork); - return mtask; + return ctask; } int iscsi_conn_send_pdu(struct iscsi_cls_conn *cls_conn, struct iscsi_hdr *hdr, @@ -538,7 +554,7 @@ EXPORT_SYMBOL_GPL(iscsi_conn_send_pdu); * @datalen: len of buffer * * iscsi_cmd_rsp sets up the scsi_cmnd fields based on the PDU and - * then completes the command and task. + * then completes the command and ctask. **/ static void iscsi_scsi_cmd_rsp(struct iscsi_conn *conn, struct iscsi_hdr *hdr, struct iscsi_cmd_task *ctask, char *data, @@ -634,9 +650,9 @@ static void iscsi_tmf_rsp(struct iscsi_conn *conn, struct iscsi_hdr *hdr) static void iscsi_send_nopout(struct iscsi_conn *conn, struct iscsi_nopin *rhdr) { struct iscsi_nopout hdr; - struct iscsi_mgmt_task *mtask; + struct iscsi_cmd_task *ctask; - if (!rhdr && conn->ping_mtask) + if (!rhdr && conn->ping_ctask) return; memset(&hdr, 0, sizeof(struct iscsi_nopout)); @@ -650,8 +666,8 @@ static void iscsi_send_nopout(struct iscsi_conn *conn, struct iscsi_nopin *rhdr) } else hdr.ttt = RESERVED_ITT; - mtask = __iscsi_conn_send_pdu(conn, (struct iscsi_hdr *)&hdr, NULL, 0); - if (!mtask) + ctask = __iscsi_conn_send_pdu(conn, (struct iscsi_hdr *)&hdr, NULL, 0); + if (!ctask) iscsi_conn_printk(KERN_ERR, conn, "Could not send nopout\n"); } @@ -697,7 +713,6 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, struct iscsi_session *session = conn->session; int opcode = hdr->opcode & ISCSI_OPCODE_MASK, rc = 0; struct iscsi_cmd_task *ctask; - struct iscsi_mgmt_task *mtask; uint32_t itt; conn->last_recv = jiffies; @@ -710,93 +725,10 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, else itt = ~0U; - if (itt < session->cmds_max) { - ctask = session->cmds[itt]; - - debug_scsi("cmdrsp [op 0x%x cid %d itt 0x%x len %d]\n", - opcode, conn->id, ctask->itt, datalen); - - switch(opcode) { - case ISCSI_OP_SCSI_CMD_RSP: - BUG_ON((void*)ctask != ctask->sc->SCp.ptr); - iscsi_scsi_cmd_rsp(conn, hdr, ctask, data, - datalen); - break; - case ISCSI_OP_SCSI_DATA_IN: - BUG_ON((void*)ctask != ctask->sc->SCp.ptr); - if (hdr->flags & ISCSI_FLAG_DATA_STATUS) { - conn->scsirsp_pdus_cnt++; - __iscsi_put_ctask(ctask); - } - break; - case ISCSI_OP_R2T: - /* LLD handles this for now */ - break; - default: - rc = ISCSI_ERR_BAD_OPCODE; - break; - } - } else if (itt >= ISCSI_MGMT_ITT_OFFSET && - itt < ISCSI_MGMT_ITT_OFFSET + session->mgmtpool_max) { - mtask = session->mgmt_cmds[itt - ISCSI_MGMT_ITT_OFFSET]; - - debug_scsi("immrsp [op 0x%x cid %d itt 0x%x len %d]\n", - opcode, conn->id, mtask->itt, datalen); + debug_scsi("[op 0x%x cid %d itt 0x%x len %d]\n", + opcode, conn->id, itt, datalen); - iscsi_update_cmdsn(session, (struct iscsi_nopin*)hdr); - switch(opcode) { - case ISCSI_OP_LOGOUT_RSP: - if (datalen) { - rc = ISCSI_ERR_PROTO; - break; - } - conn->exp_statsn = be32_to_cpu(hdr->statsn) + 1; - /* fall through */ - case ISCSI_OP_LOGIN_RSP: - case ISCSI_OP_TEXT_RSP: - /* - * login related PDU's exp_statsn is handled in - * userspace - */ - if (iscsi_recv_pdu(conn->cls_conn, hdr, data, datalen)) - rc = ISCSI_ERR_CONN_FAILED; - iscsi_free_mgmt_task(conn, mtask); - break; - case ISCSI_OP_SCSI_TMFUNC_RSP: - if (datalen) { - rc = ISCSI_ERR_PROTO; - break; - } - - iscsi_tmf_rsp(conn, hdr); - iscsi_free_mgmt_task(conn, mtask); - break; - case ISCSI_OP_NOOP_IN: - if (hdr->ttt != cpu_to_be32(ISCSI_RESERVED_TAG) || - datalen) { - rc = ISCSI_ERR_PROTO; - break; - } - conn->exp_statsn = be32_to_cpu(hdr->statsn) + 1; - - if (conn->ping_mtask != mtask) { - /* - * If this is not in response to one of our - * nops then it must be from userspace. - */ - if (iscsi_recv_pdu(conn->cls_conn, hdr, data, - datalen)) - rc = ISCSI_ERR_CONN_FAILED; - } else - mod_timer(&conn->transport_timer, - jiffies + conn->recv_timeout); - iscsi_free_mgmt_task(conn, mtask); - break; - default: - rc = ISCSI_ERR_BAD_OPCODE; - break; - } - } else if (itt == ~0U) { + if (itt == ~0U) { iscsi_update_cmdsn(session, (struct iscsi_nopin*)hdr); switch(opcode) { @@ -823,9 +755,88 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, rc = ISCSI_ERR_BAD_OPCODE; break; } - } else - rc = ISCSI_ERR_BAD_ITT; + goto out; + } + + ctask = session->cmds[itt]; + switch(opcode) { + case ISCSI_OP_SCSI_CMD_RSP: + if (!ctask->sc) { + rc = ISCSI_ERR_NO_SCSI_CMD; + break; + } + BUG_ON((void*)ctask != ctask->sc->SCp.ptr); + iscsi_scsi_cmd_rsp(conn, hdr, ctask, data, datalen); + break; + case ISCSI_OP_SCSI_DATA_IN: + if (!ctask->sc) { + rc = ISCSI_ERR_NO_SCSI_CMD; + break; + } + BUG_ON((void*)ctask != ctask->sc->SCp.ptr); + if (hdr->flags & ISCSI_FLAG_DATA_STATUS) { + conn->scsirsp_pdus_cnt++; + iscsi_update_cmdsn(session, + (struct iscsi_nopin*) hdr); + __iscsi_put_ctask(ctask); + } + break; + case ISCSI_OP_R2T: + /* LLD handles this for now */ + break; + case ISCSI_OP_LOGOUT_RSP: + iscsi_update_cmdsn(session, (struct iscsi_nopin*)hdr); + if (datalen) { + rc = ISCSI_ERR_PROTO; + break; + } + conn->exp_statsn = be32_to_cpu(hdr->statsn) + 1; + goto recv_pdu; + case ISCSI_OP_LOGIN_RSP: + case ISCSI_OP_TEXT_RSP: + iscsi_update_cmdsn(session, (struct iscsi_nopin*)hdr); + /* + * login related PDU's exp_statsn is handled in + * userspace + */ + goto recv_pdu; + case ISCSI_OP_SCSI_TMFUNC_RSP: + iscsi_update_cmdsn(session, (struct iscsi_nopin*)hdr); + if (datalen) { + rc = ISCSI_ERR_PROTO; + break; + } + + iscsi_tmf_rsp(conn, hdr); + __iscsi_put_ctask(ctask); + break; + case ISCSI_OP_NOOP_IN: + iscsi_update_cmdsn(session, (struct iscsi_nopin*)hdr); + if (hdr->ttt != cpu_to_be32(ISCSI_RESERVED_TAG) || datalen) { + rc = ISCSI_ERR_PROTO; + break; + } + conn->exp_statsn = be32_to_cpu(hdr->statsn) + 1; + + if (conn->ping_ctask != ctask) + /* + * If this is not in response to one of our + * nops then it must be from userspace. + */ + goto recv_pdu; + __iscsi_put_ctask(ctask); + break; + default: + rc = ISCSI_ERR_BAD_OPCODE; + break; + } +out: + return rc; +recv_pdu: + if (iscsi_recv_pdu(conn->cls_conn, hdr, data, datalen)) + rc = ISCSI_ERR_CONN_FAILED; + __iscsi_put_ctask(ctask); return rc; } @@ -845,6 +856,7 @@ int iscsi_verify_itt(struct iscsi_conn *conn, itt_t itt) { struct iscsi_session *session = conn->session; struct iscsi_cmd_task *ctask; + uint32_t i; if (itt == RESERVED_ITT) return 0; @@ -858,25 +870,22 @@ int iscsi_verify_itt(struct iscsi_conn *conn, itt_t itt) return ISCSI_ERR_BAD_ITT; } - if (itt < session->cmds_max) { - ctask = session->cmds[itt]; - - if (!ctask->sc) { - iscsi_conn_printk(KERN_INFO, conn, "dropping ctask " - "with itt 0x%x\n", ctask->itt); - /* force drop */ - return ISCSI_ERR_NO_SCSI_CMD; - } - - if (ctask->sc->SCp.phase != session->age) { - iscsi_conn_printk(KERN_ERR, conn, - "iscsi: ctask's session age %d, " - "expected %d\n", ctask->sc->SCp.phase, - session->age); - return ISCSI_ERR_SESSION_FAILED; - } + i = get_itt(itt); + if (i >= session->cmds_max) { + iscsi_conn_printk(KERN_ERR, conn, + "received invalid itt index %u (max cmds " + "%u.\n", i, session->cmds_max); + return ISCSI_ERR_BAD_ITT; } + ctask = session->cmds[i]; + if (ctask->sc && ctask->sc->SCp.phase != session->age) { + iscsi_conn_printk(KERN_ERR, conn, + "iscsi: ctask's session age %d, " + "expected %d\n", ctask->sc->SCp.phase, + session->age); + return ISCSI_ERR_SESSION_FAILED; + } return 0; } EXPORT_SYMBOL_GPL(iscsi_verify_itt); @@ -929,20 +938,6 @@ void iscsi_conn_failure(struct iscsi_conn *conn, enum iscsi_err err) } EXPORT_SYMBOL_GPL(iscsi_conn_failure); -static int iscsi_xmit_mtask(struct iscsi_conn *conn) -{ - int rc; - - spin_unlock_bh(&conn->session->lock); - rc = conn->session->tt->xmit_mgmt_task(conn, conn->mtask); - spin_lock_bh(&conn->session->lock); - if (rc) - return rc; - /* done with this in-progress mtask */ - conn->mtask = NULL; - return 0; -} - static int iscsi_check_cmdsn_window_closed(struct iscsi_conn *conn) { struct iscsi_session *session = conn->session; @@ -967,7 +962,7 @@ static int iscsi_xmit_ctask(struct iscsi_conn *conn) __iscsi_get_ctask(ctask); spin_unlock_bh(&conn->session->lock); - rc = conn->session->tt->xmit_cmd_task(conn, ctask); + rc = conn->session->tt->xmit_task(ctask); spin_lock_bh(&conn->session->lock); __iscsi_put_ctask(ctask); if (!rc) @@ -1015,12 +1010,6 @@ static int iscsi_data_xmit(struct iscsi_conn *conn) if (conn->ctask) { rc = iscsi_xmit_ctask(conn); - if (rc) - goto again; - } - - if (conn->mtask) { - rc = iscsi_xmit_mtask(conn); if (rc) goto again; } @@ -1032,14 +1021,14 @@ static int iscsi_data_xmit(struct iscsi_conn *conn) */ check_mgmt: while (!list_empty(&conn->mgmtqueue)) { - conn->mtask = list_entry(conn->mgmtqueue.next, - struct iscsi_mgmt_task, running); - if (iscsi_prep_mtask(conn, conn->mtask)) { - iscsi_free_mgmt_task(conn, conn->mtask); - conn->mtask = NULL; + conn->ctask = list_entry(conn->mgmtqueue.next, + struct iscsi_cmd_task, running); + if (iscsi_prep_mgmt_task(conn, conn->ctask)) { + __iscsi_put_ctask(conn->ctask); + conn->ctask = NULL; continue; } - rc = iscsi_xmit_mtask(conn); + rc = iscsi_xmit_ctask(conn); if (rc) goto again; } @@ -1224,7 +1213,7 @@ int iscsi_queuecommand(struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *)) iscsi_complete_command(ctask); goto fault; } - if (session->tt->xmit_cmd_task(conn, ctask)) { + if (session->tt->xmit_task(ctask)) { sc->scsi_done = NULL; iscsi_complete_command(ctask); reason = FAILURE_SESSION_NOT_READY; @@ -1347,16 +1336,16 @@ static void iscsi_tmf_timedout(unsigned long data) spin_unlock(&session->lock); } -static int iscsi_exec_task_mgmt_fn(struct iscsi_conn *conn, +static int iscsi_exec_ctask_mgmt_fn(struct iscsi_conn *conn, struct iscsi_tm *hdr, int age, int timeout) { struct iscsi_session *session = conn->session; - struct iscsi_mgmt_task *mtask; + struct iscsi_cmd_task *ctask; - mtask = __iscsi_conn_send_pdu(conn, (struct iscsi_hdr *)hdr, + ctask = __iscsi_conn_send_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); - if (!mtask) { + if (!ctask) { spin_unlock_bh(&session->lock); iscsi_conn_failure(conn, ISCSI_ERR_CONN_FAILED); spin_lock_bh(&session->lock); @@ -1390,7 +1379,7 @@ static int iscsi_exec_task_mgmt_fn(struct iscsi_conn *conn, mutex_lock(&session->eh_mutex); spin_lock_bh(&session->lock); - /* if the session drops it will clean up the mtask */ + /* if the session drops it will clean up the ctask */ if (age != session->age || session->state != ISCSI_STATE_LOGGED_IN) return -ENOTCONN; @@ -1497,7 +1486,7 @@ static enum scsi_eh_timer_return iscsi_eh_cmd_timed_out(struct scsi_cmnd *scmd) jiffies)) rc = EH_RESET_TIMER; /* if in the middle of checking the transport then give us more time */ - if (conn->ping_mtask) + if (conn->ping_ctask) rc = EH_RESET_TIMER; done: spin_unlock(&session->lock); @@ -1521,7 +1510,7 @@ static void iscsi_check_transport_timeouts(unsigned long data) recv_timeout *= HZ; last_recv = conn->last_recv; - if (conn->ping_mtask && + if (conn->ping_ctask && time_before_eq(conn->last_ping + (conn->ping_timeout * HZ), jiffies)) { iscsi_conn_printk(KERN_ERR, conn, "ping timeout of %d secs " @@ -1547,7 +1536,7 @@ done: spin_unlock(&session->lock); } -static void iscsi_prep_abort_task_pdu(struct iscsi_cmd_task *ctask, +static void iscsi_prep_abort_ctask_pdu(struct iscsi_cmd_task *ctask, struct iscsi_tm *hdr) { memset(hdr, 0, sizeof(*hdr)); @@ -1619,9 +1608,9 @@ int iscsi_eh_abort(struct scsi_cmnd *sc) conn->tmf_state = TMF_QUEUED; hdr = &conn->tmhdr; - iscsi_prep_abort_task_pdu(ctask, hdr); + iscsi_prep_abort_ctask_pdu(ctask, hdr); - if (iscsi_exec_task_mgmt_fn(conn, hdr, age, session->abort_timeout)) { + if (iscsi_exec_ctask_mgmt_fn(conn, hdr, age, session->abort_timeout)) { rc = FAILED; goto failed; } @@ -1631,7 +1620,7 @@ int iscsi_eh_abort(struct scsi_cmnd *sc) spin_unlock_bh(&session->lock); iscsi_suspend_tx(conn); /* - * clean up task if aborted. grab the recv lock as a writer + * clean up ctask if aborted. grab the recv lock as a writer */ write_lock_bh(conn->recv_lock); spin_lock(&session->lock); @@ -1716,7 +1705,7 @@ int iscsi_eh_device_reset(struct scsi_cmnd *sc) hdr = &conn->tmhdr; iscsi_prep_lun_reset_pdu(sc, hdr); - if (iscsi_exec_task_mgmt_fn(conn, hdr, session->age, + if (iscsi_exec_ctask_mgmt_fn(conn, hdr, session->age, session->lu_reset_timeout)) { rc = FAILED; goto unlock; @@ -1897,8 +1886,7 @@ EXPORT_SYMBOL_GPL(iscsi_host_free); * @iscsit: iscsi transport template * @shost: scsi host * @cmds_max: session can queue - * @cmd_task_size: LLD ctask private data size - * @mgmt_task_size: LLD mtask private data size + * @cmd_ctask_size: LLD ctask private data size * @initial_cmdsn: initial CmdSN * * This can be used by software iscsi_transports that allocate @@ -1906,22 +1894,26 @@ EXPORT_SYMBOL_GPL(iscsi_host_free); */ struct iscsi_cls_session * iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, - uint16_t cmds_max, int cmd_task_size, int mgmt_task_size, + uint16_t scsi_cmds_max, int cmd_ctask_size, uint32_t initial_cmdsn) { struct iscsi_session *session; struct iscsi_cls_session *cls_session; - int cmd_i; + int cmd_i, cmds_max; - if (!is_power_of_2(cmds_max) || cmds_max >= ISCSI_MGMT_ITT_OFFSET || - cmds_max < 2) { - if (cmds_max != 0) - printk(KERN_ERR "iscsi: invalid can_queue of %d. " - "can_queue must be a power of 2 and between " - "2 and %d - setting to %d.\n", cmds_max, - ISCSI_MGMT_ITT_OFFSET, ISCSI_DEF_XMIT_CMDS_MAX); - cmds_max = ISCSI_DEF_XMIT_CMDS_MAX; + /* + * The iscsi layer needs some ctasks for nop handling and tmfs. + */ + if (scsi_cmds_max < 1) + scsi_cmds_max = ISCSI_MGMT_CMDS_MAX; + if ((scsi_cmds_max + ISCSI_MGMT_CMDS_MAX) >= ISCSI_MGMT_ITT_OFFSET) { + printk(KERN_ERR "iscsi: invalid can_queue of %d. " + "can_queue must be less than %d.\n", + scsi_cmds_max, + ISCSI_MGMT_ITT_OFFSET - ISCSI_MGMT_CMDS_MAX); + scsi_cmds_max = ISCSI_DEF_XMIT_CMDS_MAX; } + cmds_max = roundup_pow_of_two(scsi_cmds_max + ISCSI_MGMT_CMDS_MAX); cls_session = iscsi_alloc_session(shost, iscsit, sizeof(struct iscsi_session)); @@ -1934,7 +1926,7 @@ iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, session->fast_abort = 1; session->lu_reset_timeout = 15; session->abort_timeout = 10; - session->mgmtpool_max = ISCSI_MGMT_CMDS_MAX; + session->scsi_cmds_max = scsi_cmds_max; session->cmds_max = cmds_max; session->queued_cmdsn = session->cmdsn = initial_cmdsn; session->exp_cmdsn = initial_cmdsn + 1; @@ -1947,36 +1939,19 @@ iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, /* initialize SCSI PDU commands pool */ if (iscsi_pool_init(&session->cmdpool, session->cmds_max, (void***)&session->cmds, - cmd_task_size + sizeof(struct iscsi_cmd_task))) + cmd_ctask_size + sizeof(struct iscsi_cmd_task))) goto cmdpool_alloc_fail; /* pre-format cmds pool with ITT */ for (cmd_i = 0; cmd_i < session->cmds_max; cmd_i++) { struct iscsi_cmd_task *ctask = session->cmds[cmd_i]; - if (cmd_task_size) + if (cmd_ctask_size) ctask->dd_data = &ctask[1]; ctask->itt = cmd_i; INIT_LIST_HEAD(&ctask->running); } - /* initialize immediate command pool */ - if (iscsi_pool_init(&session->mgmtpool, session->mgmtpool_max, - (void***)&session->mgmt_cmds, - mgmt_task_size + sizeof(struct iscsi_mgmt_task))) - goto mgmtpool_alloc_fail; - - - /* pre-format immediate cmds pool with ITT */ - for (cmd_i = 0; cmd_i < session->mgmtpool_max; cmd_i++) { - struct iscsi_mgmt_task *mtask = session->mgmt_cmds[cmd_i]; - - if (mgmt_task_size) - mtask->dd_data = &mtask[1]; - mtask->itt = ISCSI_MGMT_ITT_OFFSET + cmd_i; - INIT_LIST_HEAD(&mtask->running); - } - if (!try_module_get(iscsit->owner)) goto module_get_fail; @@ -1987,8 +1962,6 @@ iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, cls_session_fail: module_put(iscsit->owner); module_get_fail: - iscsi_pool_free(&session->mgmtpool); -mgmtpool_alloc_fail: iscsi_pool_free(&session->cmdpool); cmdpool_alloc_fail: iscsi_free_session(cls_session); @@ -2008,7 +1981,6 @@ void iscsi_session_teardown(struct iscsi_cls_session *cls_session) struct iscsi_session *session = cls_session->dd_data; struct module *owner = cls_session->transport->owner; - iscsi_pool_free(&session->mgmtpool); iscsi_pool_free(&session->cmdpool); kfree(session->password); @@ -2063,30 +2035,30 @@ iscsi_conn_setup(struct iscsi_cls_session *cls_session, int dd_size, INIT_LIST_HEAD(&conn->requeue); INIT_WORK(&conn->xmitwork, iscsi_xmitworker); - /* allocate login_mtask used for the login/text sequences */ + /* allocate login_ctask used for the login/text sequences */ spin_lock_bh(&session->lock); - if (!__kfifo_get(session->mgmtpool.queue, - (void*)&conn->login_mtask, + if (!__kfifo_get(session->cmdpool.queue, + (void*)&conn->login_ctask, sizeof(void*))) { spin_unlock_bh(&session->lock); - goto login_mtask_alloc_fail; + goto login_ctask_alloc_fail; } spin_unlock_bh(&session->lock); data = kmalloc(ISCSI_DEF_MAX_RECV_SEG_LEN, GFP_KERNEL); if (!data) - goto login_mtask_data_alloc_fail; - conn->login_mtask->data = conn->data = data; + goto login_ctask_data_alloc_fail; + conn->login_ctask->data = conn->data = data; init_timer(&conn->tmf_timer); init_waitqueue_head(&conn->ehwait); return cls_conn; -login_mtask_data_alloc_fail: - __kfifo_put(session->mgmtpool.queue, (void*)&conn->login_mtask, +login_ctask_data_alloc_fail: + __kfifo_put(session->cmdpool.queue, (void*)&conn->login_ctask, sizeof(void*)); -login_mtask_alloc_fail: +login_ctask_alloc_fail: iscsi_destroy_conn(cls_conn); return NULL; } @@ -2146,7 +2118,7 @@ void iscsi_conn_teardown(struct iscsi_cls_conn *cls_conn) spin_lock_bh(&session->lock); kfree(conn->data); kfree(conn->persistent_address); - __kfifo_put(session->mgmtpool.queue, (void*)&conn->login_mtask, + __kfifo_put(session->cmdpool.queue, (void*)&conn->login_ctask, sizeof(void*)); if (session->leadconn == conn) session->leadconn = NULL; @@ -2227,21 +2199,23 @@ EXPORT_SYMBOL_GPL(iscsi_conn_start); static void flush_control_queues(struct iscsi_session *session, struct iscsi_conn *conn) { - struct iscsi_mgmt_task *mtask, *tmp; + struct iscsi_cmd_task *ctask, *tmp; /* handle pending */ - list_for_each_entry_safe(mtask, tmp, &conn->mgmtqueue, running) { - debug_scsi("flushing pending mgmt task itt 0x%x\n", mtask->itt); - iscsi_free_mgmt_task(conn, mtask); + list_for_each_entry_safe(ctask, tmp, &conn->mgmtqueue, running) { + debug_scsi("flushing pending mgmt ctask itt 0x%x\n", ctask->itt); + /* release ref from prep ctask */ + __iscsi_put_ctask(ctask); } /* handle running */ - list_for_each_entry_safe(mtask, tmp, &conn->mgmt_run_list, running) { - debug_scsi("flushing running mgmt task itt 0x%x\n", mtask->itt); - iscsi_free_mgmt_task(conn, mtask); + list_for_each_entry_safe(ctask, tmp, &conn->mgmt_run_list, running) { + debug_scsi("flushing running mgmt ctask itt 0x%x\n", ctask->itt); + /* release ref from prep ctask */ + __iscsi_put_ctask(ctask); } - conn->mtask = NULL; + conn->ctask = NULL; } static void iscsi_start_session_recovery(struct iscsi_session *session, @@ -2272,7 +2246,7 @@ static void iscsi_start_session_recovery(struct iscsi_session *session, /* * When this is called for the in_login state, we only want to clean - * up the login task and connection. We do not need to block and set + * up the login ctask and connection. We do not need to block and set * the recovery state again */ if (flag == STOP_CONN_TERM) diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index 9be6a70faff5..d1c36759b350 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -85,18 +85,6 @@ enum { ISCSI_DIGEST_SIZE = sizeof(__u32), }; -struct iscsi_mgmt_task { - /* - * Becuae LLDs allocate their hdr differently, this is a pointer to - * that storage. It must be setup at session creation time. - */ - struct iscsi_hdr *hdr; - char *data; /* mgmt payload */ - unsigned data_count; /* counts data to be sent */ - uint32_t itt; /* this ITT */ - void *dd_data; /* driver/transport data */ - struct list_head running; -}; enum { ISCSI_TASK_COMPLETED, @@ -121,6 +109,7 @@ struct iscsi_cmd_task { /* offset in unsolicited stream (bytes); */ unsigned unsol_offset; unsigned data_count; /* remaining Data-Out */ + char *data; /* mgmt payload */ struct scsi_cmnd *sc; /* associated SCSI cmd*/ struct iscsi_conn *conn; /* used connection */ @@ -162,7 +151,7 @@ struct iscsi_conn { unsigned long last_ping; int ping_timeout; int recv_timeout; - struct iscsi_mgmt_task *ping_mtask; + struct iscsi_cmd_task *ping_ctask; /* iSCSI connection-wide sequencing */ uint32_t exp_statsn; @@ -178,9 +167,8 @@ struct iscsi_conn { * should always fit in this buffer */ char *data; - struct iscsi_mgmt_task *login_mtask; /* mtask used for login/text */ - struct iscsi_mgmt_task *mtask; /* xmit mtask in progress */ - struct iscsi_cmd_task *ctask; /* xmit ctask in progress */ + struct iscsi_cmd_task *login_ctask; /* mtask used for login/text */ + struct iscsi_cmd_task *ctask; /* xmit task in progress */ /* xmit */ struct list_head mgmtqueue; /* mgmt (control) xmit queue */ @@ -295,12 +283,10 @@ struct iscsi_session { int state; /* session state */ int age; /* counts session re-opens */ + int scsi_cmds_max; /* max scsi commands */ int cmds_max; /* size of cmds array */ struct iscsi_cmd_task **cmds; /* Original Cmds arr */ struct iscsi_pool cmdpool; /* PDU's pool */ - int mgmtpool_max; /* size of mgmt array */ - struct iscsi_mgmt_task **mgmt_cmds; /* Original mgmt arr */ - struct iscsi_pool mgmtpool; /* Mgmt PDU's pool */ }; struct iscsi_host { @@ -345,7 +331,7 @@ extern void iscsi_host_free(struct Scsi_Host *shost); */ extern struct iscsi_cls_session * iscsi_session_setup(struct iscsi_transport *, struct Scsi_Host *shost, - uint16_t, int, int, uint32_t); + uint16_t, int, uint32_t); extern void iscsi_session_teardown(struct iscsi_cls_session *); extern void iscsi_session_recovery_timedout(struct iscsi_cls_session *); extern int iscsi_set_param(struct iscsi_cls_conn *cls_conn, @@ -388,8 +374,7 @@ extern int iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *, extern int iscsi_verify_itt(struct iscsi_conn *, itt_t); extern struct iscsi_cmd_task *iscsi_itt_to_ctask(struct iscsi_conn *, itt_t); extern void iscsi_requeue_ctask(struct iscsi_cmd_task *ctask); -extern void iscsi_free_mgmt_task(struct iscsi_conn *conn, - struct iscsi_mgmt_task *mtask); +extern void iscsi_put_ctask(struct iscsi_cmd_task *ctask); /* * generic helpers diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index 4028f121d548..3f24503dfdf9 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -34,7 +34,6 @@ struct Scsi_Host; struct iscsi_cls_conn; struct iscsi_conn; struct iscsi_cmd_task; -struct iscsi_mgmt_task; struct sockaddr; /** @@ -58,19 +57,22 @@ struct sockaddr; * @stop_conn: suspend/recover/terminate connection * @send_pdu: send iSCSI PDU, Login, Logout, NOP-Out, Reject, Text. * @session_recovery_timedout: notify LLD a block during recovery timed out - * @init_cmd_task: Initialize a iscsi_cmd_task and any internal structs. - * Called from queuecommand with session lock held. - * @init_mgmt_task: Initialize a iscsi_mgmt_task and any internal structs. - * Called from iscsi_conn_send_generic with xmitmutex. - * @xmit_cmd_task: Requests LLD to transfer cmd task. Returns 0 or the + * @init_task: Initialize a iscsi_task and any internal structs. + * When offloading the data path, this is called from + * queuecommand with the session lock, or from the + * iscsi_conn_send_pdu context with the session lock. + * When not offloading the data path, this is called + * from the scsi work queue without the session lock. + * @xmit_task Requests LLD to transfer cmd task. Returns 0 or the * the number of bytes transferred on success, and -Exyz - * value on error. - * @xmit_mgmt_task: Requests LLD to transfer mgmt task. Returns 0 or the - * the number of bytes transferred on success, and -Exyz - * value on error. - * @cleanup_cmd_task: requests LLD to fail cmd task. Called with xmitmutex - * and session->lock after the connection has been - * suspended and terminated during recovery. If called + * value on error. When offloading the data path, this + * is called from queuecommand with the session lock, or + * from the iscsi_conn_send_pdu context with the session + * lock. When not offloading the data path, this is called + * from the scsi work queue without the session lock. + * @cleanup_task: requests LLD to fail task. Called with session lock + * and after the connection has been suspended and + * terminated during recovery. If called * from abort task then connection is not suspended * or terminated but sk_callback_lock is held * @@ -110,15 +112,10 @@ struct iscsi_transport { char *data, uint32_t data_size); void (*get_stats) (struct iscsi_cls_conn *conn, struct iscsi_stats *stats); - int (*init_cmd_task) (struct iscsi_cmd_task *ctask); - void (*init_mgmt_task) (struct iscsi_conn *conn, - struct iscsi_mgmt_task *mtask); - int (*xmit_cmd_task) (struct iscsi_conn *conn, - struct iscsi_cmd_task *ctask); - void (*cleanup_cmd_task) (struct iscsi_conn *conn, - struct iscsi_cmd_task *ctask); - int (*xmit_mgmt_task) (struct iscsi_conn *conn, - struct iscsi_mgmt_task *mtask); + int (*init_task) (struct iscsi_cmd_task *task); + int (*xmit_task) (struct iscsi_cmd_task *task); + void (*cleanup_task) (struct iscsi_conn *conn, + struct iscsi_cmd_task *task); void (*session_recovery_timedout) (struct iscsi_cls_session *session); int (*ep_connect) (struct sockaddr *dst_addr, int non_blocking, uint64_t *ep_handle); -- cgit v1.2.3 From 9c19a7d0387124a508d2cdb38ebf8cd484631ad0 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:09 -0500 Subject: [SCSI] libiscsi: rename iscsi_cmd_task to iscsi_task This is the second part of the iscsi task merging, and all it does it rename iscsi_cmd_task to iscsi_task and mtask/ctask to just task. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/scsi/libiscsi.c | 514 ++++++++++++++++++------------------ include/scsi/libiscsi.h | 22 +- include/scsi/scsi_transport_iscsi.h | 8 +- 3 files changed, 273 insertions(+), 271 deletions(-) (limited to 'include') diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index ef92b1b0f16e..92ee6d94aaf9 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -88,61 +88,61 @@ iscsi_update_cmdsn(struct iscsi_session *session, struct iscsi_nopin *hdr) } EXPORT_SYMBOL_GPL(iscsi_update_cmdsn); -void iscsi_prep_unsolicit_data_pdu(struct iscsi_cmd_task *ctask, +void iscsi_prep_unsolicit_data_pdu(struct iscsi_task *task, struct iscsi_data *hdr) { - struct iscsi_conn *conn = ctask->conn; + struct iscsi_conn *conn = task->conn; memset(hdr, 0, sizeof(struct iscsi_data)); hdr->ttt = cpu_to_be32(ISCSI_RESERVED_TAG); - hdr->datasn = cpu_to_be32(ctask->unsol_datasn); - ctask->unsol_datasn++; + hdr->datasn = cpu_to_be32(task->unsol_datasn); + task->unsol_datasn++; hdr->opcode = ISCSI_OP_SCSI_DATA_OUT; - memcpy(hdr->lun, ctask->hdr->lun, sizeof(hdr->lun)); + memcpy(hdr->lun, task->hdr->lun, sizeof(hdr->lun)); - hdr->itt = ctask->hdr->itt; + hdr->itt = task->hdr->itt; hdr->exp_statsn = cpu_to_be32(conn->exp_statsn); - hdr->offset = cpu_to_be32(ctask->unsol_offset); + hdr->offset = cpu_to_be32(task->unsol_offset); - if (ctask->unsol_count > conn->max_xmit_dlength) { + if (task->unsol_count > conn->max_xmit_dlength) { hton24(hdr->dlength, conn->max_xmit_dlength); - ctask->data_count = conn->max_xmit_dlength; - ctask->unsol_offset += ctask->data_count; + task->data_count = conn->max_xmit_dlength; + task->unsol_offset += task->data_count; hdr->flags = 0; } else { - hton24(hdr->dlength, ctask->unsol_count); - ctask->data_count = ctask->unsol_count; + hton24(hdr->dlength, task->unsol_count); + task->data_count = task->unsol_count; hdr->flags = ISCSI_FLAG_CMD_FINAL; } } EXPORT_SYMBOL_GPL(iscsi_prep_unsolicit_data_pdu); -static int iscsi_add_hdr(struct iscsi_cmd_task *ctask, unsigned len) +static int iscsi_add_hdr(struct iscsi_task *task, unsigned len) { - unsigned exp_len = ctask->hdr_len + len; + unsigned exp_len = task->hdr_len + len; - if (exp_len > ctask->hdr_max) { + if (exp_len > task->hdr_max) { WARN_ON(1); return -EINVAL; } WARN_ON(len & (ISCSI_PAD_LEN - 1)); /* caller must pad the AHS */ - ctask->hdr_len = exp_len; + task->hdr_len = exp_len; return 0; } /* * make an extended cdb AHS */ -static int iscsi_prep_ecdb_ahs(struct iscsi_cmd_task *ctask) +static int iscsi_prep_ecdb_ahs(struct iscsi_task *task) { - struct scsi_cmnd *cmd = ctask->sc; + struct scsi_cmnd *cmd = task->sc; unsigned rlen, pad_len; unsigned short ahslength; struct iscsi_ecdb_ahdr *ecdb_ahdr; int rc; - ecdb_ahdr = iscsi_next_hdr(ctask); + ecdb_ahdr = iscsi_next_hdr(task); rlen = cmd->cmd_len - ISCSI_CDB_SIZE; BUG_ON(rlen > sizeof(ecdb_ahdr->ecdb)); @@ -150,7 +150,7 @@ static int iscsi_prep_ecdb_ahs(struct iscsi_cmd_task *ctask) pad_len = iscsi_padding(rlen); - rc = iscsi_add_hdr(ctask, sizeof(ecdb_ahdr->ahslength) + + rc = iscsi_add_hdr(task, sizeof(ecdb_ahdr->ahslength) + sizeof(ecdb_ahdr->ahstype) + ahslength + pad_len); if (rc) return rc; @@ -165,19 +165,19 @@ static int iscsi_prep_ecdb_ahs(struct iscsi_cmd_task *ctask) debug_scsi("iscsi_prep_ecdb_ahs: varlen_cdb_len %d " "rlen %d pad_len %d ahs_length %d iscsi_headers_size %u\n", - cmd->cmd_len, rlen, pad_len, ahslength, ctask->hdr_len); + cmd->cmd_len, rlen, pad_len, ahslength, task->hdr_len); return 0; } -static int iscsi_prep_bidi_ahs(struct iscsi_cmd_task *ctask) +static int iscsi_prep_bidi_ahs(struct iscsi_task *task) { - struct scsi_cmnd *sc = ctask->sc; + struct scsi_cmnd *sc = task->sc; struct iscsi_rlength_ahdr *rlen_ahdr; int rc; - rlen_ahdr = iscsi_next_hdr(ctask); - rc = iscsi_add_hdr(ctask, sizeof(*rlen_ahdr)); + rlen_ahdr = iscsi_next_hdr(task); + rc = iscsi_add_hdr(task, sizeof(*rlen_ahdr)); if (rc) return rc; @@ -197,28 +197,28 @@ static int iscsi_prep_bidi_ahs(struct iscsi_cmd_task *ctask) /** * iscsi_prep_scsi_cmd_pdu - prep iscsi scsi cmd pdu - * @ctask: iscsi task + * @task: iscsi task * * Prep basic iSCSI PDU fields for a scsi cmd pdu. The LLD should set * fields like dlength or final based on how much data it sends */ -static int iscsi_prep_scsi_cmd_pdu(struct iscsi_cmd_task *ctask) +static int iscsi_prep_scsi_cmd_pdu(struct iscsi_task *task) { - struct iscsi_conn *conn = ctask->conn; + struct iscsi_conn *conn = task->conn; struct iscsi_session *session = conn->session; - struct iscsi_cmd *hdr = ctask->hdr; - struct scsi_cmnd *sc = ctask->sc; + struct iscsi_cmd *hdr = task->hdr; + struct scsi_cmnd *sc = task->sc; unsigned hdrlength, cmd_len; int rc; - ctask->hdr_len = 0; - rc = iscsi_add_hdr(ctask, sizeof(*hdr)); + task->hdr_len = 0; + rc = iscsi_add_hdr(task, sizeof(*hdr)); if (rc) return rc; hdr->opcode = ISCSI_OP_SCSI_CMD; hdr->flags = ISCSI_ATTR_SIMPLE; int_to_scsilun(sc->device->lun, (struct scsi_lun *)hdr->lun); - hdr->itt = build_itt(ctask->itt, session->age); + hdr->itt = build_itt(task->itt, session->age); hdr->cmdsn = cpu_to_be32(session->cmdsn); session->cmdsn++; hdr->exp_statsn = cpu_to_be32(conn->exp_statsn); @@ -226,17 +226,17 @@ static int iscsi_prep_scsi_cmd_pdu(struct iscsi_cmd_task *ctask) if (cmd_len < ISCSI_CDB_SIZE) memset(&hdr->cdb[cmd_len], 0, ISCSI_CDB_SIZE - cmd_len); else if (cmd_len > ISCSI_CDB_SIZE) { - rc = iscsi_prep_ecdb_ahs(ctask); + rc = iscsi_prep_ecdb_ahs(task); if (rc) return rc; cmd_len = ISCSI_CDB_SIZE; } memcpy(hdr->cdb, sc->cmnd, cmd_len); - ctask->imm_count = 0; + task->imm_count = 0; if (scsi_bidi_cmnd(sc)) { hdr->flags |= ISCSI_FLAG_CMD_READ; - rc = iscsi_prep_bidi_ahs(ctask); + rc = iscsi_prep_bidi_ahs(task); if (rc) return rc; } @@ -258,28 +258,28 @@ static int iscsi_prep_scsi_cmd_pdu(struct iscsi_cmd_task *ctask) * * pad_count bytes to be sent as zero-padding */ - ctask->unsol_count = 0; - ctask->unsol_offset = 0; - ctask->unsol_datasn = 0; + task->unsol_count = 0; + task->unsol_offset = 0; + task->unsol_datasn = 0; if (session->imm_data_en) { if (out_len >= session->first_burst) - ctask->imm_count = min(session->first_burst, + task->imm_count = min(session->first_burst, conn->max_xmit_dlength); else - ctask->imm_count = min(out_len, + task->imm_count = min(out_len, conn->max_xmit_dlength); - hton24(hdr->dlength, ctask->imm_count); + hton24(hdr->dlength, task->imm_count); } else zero_data(hdr->dlength); if (!session->initial_r2t_en) { - ctask->unsol_count = min(session->first_burst, out_len) - - ctask->imm_count; - ctask->unsol_offset = ctask->imm_count; + task->unsol_count = min(session->first_burst, out_len) + - task->imm_count; + task->unsol_offset = task->imm_count; } - if (!ctask->unsol_count) + if (!task->unsol_count) /* No unsolicit Data-Out's */ hdr->flags |= ISCSI_FLAG_CMD_FINAL; } else { @@ -292,7 +292,7 @@ static int iscsi_prep_scsi_cmd_pdu(struct iscsi_cmd_task *ctask) } /* calculate size of additional header segments (AHSs) */ - hdrlength = ctask->hdr_len - sizeof(*hdr); + hdrlength = task->hdr_len - sizeof(*hdr); WARN_ON(hdrlength & (ISCSI_PAD_LEN-1)); hdrlength /= ISCSI_PAD_LEN; @@ -301,17 +301,17 @@ static int iscsi_prep_scsi_cmd_pdu(struct iscsi_cmd_task *ctask) hdr->hlength = hdrlength & 0xFF; if (conn->session->tt->init_task && - conn->session->tt->init_task(ctask)) + conn->session->tt->init_task(task)) return -EIO; - ctask->state = ISCSI_TASK_RUNNING; - list_move_tail(&ctask->running, &conn->run_list); + task->state = ISCSI_TASK_RUNNING; + list_move_tail(&task->running, &conn->run_list); conn->scsicmd_pdus_cnt++; debug_scsi("iscsi prep [%s cid %d sc %p cdb 0x%x itt 0x%x len %d " "bidi_len %d cmdsn %d win %d]\n", scsi_bidi_cmnd(sc) ? "bidirectional" : sc->sc_data_direction == DMA_TO_DEVICE ? - "write" : "read", conn->id, sc, sc->cmnd[0], ctask->itt, + "write" : "read", conn->id, sc, sc->cmnd[0], task->itt, scsi_bufflen(sc), scsi_bidi_cmnd(sc) ? scsi_in(sc)->length : 0, session->cmdsn, session->max_cmdsn - session->exp_cmdsn + 1); @@ -320,37 +320,37 @@ static int iscsi_prep_scsi_cmd_pdu(struct iscsi_cmd_task *ctask) /** * iscsi_complete_command - finish a task - * @ctask: iscsi cmd task + * @task: iscsi cmd task * * Must be called with session lock. * This function returns the scsi command to scsi-ml or cleans * up mgmt tasks then returns the task to the pool. */ -static void iscsi_complete_command(struct iscsi_cmd_task *ctask) +static void iscsi_complete_command(struct iscsi_task *task) { - struct iscsi_conn *conn = ctask->conn; + struct iscsi_conn *conn = task->conn; struct iscsi_session *session = conn->session; - struct scsi_cmnd *sc = ctask->sc; + struct scsi_cmnd *sc = task->sc; - list_del_init(&ctask->running); - ctask->state = ISCSI_TASK_COMPLETED; - ctask->sc = NULL; + list_del_init(&task->running); + task->state = ISCSI_TASK_COMPLETED; + task->sc = NULL; - if (conn->ctask == ctask) - conn->ctask = NULL; + if (conn->task == task) + conn->task = NULL; /* - * login ctask is preallocated so do not free + * login task is preallocated so do not free */ - if (conn->login_ctask == ctask) + if (conn->login_task == task) return; - __kfifo_put(session->cmdpool.queue, (void*)&ctask, sizeof(void*)); + __kfifo_put(session->cmdpool.queue, (void*)&task, sizeof(void*)); - if (conn->ping_ctask == ctask) - conn->ping_ctask = NULL; + if (conn->ping_task == task) + conn->ping_task = NULL; if (sc) { - ctask->sc = NULL; + task->sc = NULL; /* SCSI eh reuses commands to verify us */ sc->SCp.ptr = NULL; /* @@ -362,47 +362,47 @@ static void iscsi_complete_command(struct iscsi_cmd_task *ctask) } } -static void __iscsi_get_ctask(struct iscsi_cmd_task *ctask) +static void __iscsi_get_task(struct iscsi_task *task) { - atomic_inc(&ctask->refcount); + atomic_inc(&task->refcount); } -static void __iscsi_put_ctask(struct iscsi_cmd_task *ctask) +static void __iscsi_put_task(struct iscsi_task *task) { - if (atomic_dec_and_test(&ctask->refcount)) - iscsi_complete_command(ctask); + if (atomic_dec_and_test(&task->refcount)) + iscsi_complete_command(task); } -void iscsi_put_ctask(struct iscsi_cmd_task *ctask) +void iscsi_put_task(struct iscsi_task *task) { - struct iscsi_session *session = ctask->conn->session; + struct iscsi_session *session = task->conn->session; spin_lock_bh(&session->lock); - __iscsi_put_ctask(ctask); + __iscsi_put_task(task); spin_unlock_bh(&session->lock); } -EXPORT_SYMBOL_GPL(iscsi_put_ctask); +EXPORT_SYMBOL_GPL(iscsi_put_task); /* * session lock must be held */ -static void fail_command(struct iscsi_conn *conn, struct iscsi_cmd_task *ctask, +static void fail_command(struct iscsi_conn *conn, struct iscsi_task *task, int err) { struct scsi_cmnd *sc; - sc = ctask->sc; + sc = task->sc; if (!sc) return; - if (ctask->state == ISCSI_TASK_PENDING) + if (task->state == ISCSI_TASK_PENDING) /* * cmd never made it to the xmit thread, so we should not count * the cmd in the sequencing */ conn->session->queued_cmdsn--; else - conn->session->tt->cleanup_task(conn, ctask); + conn->session->tt->cleanup_task(conn, task); sc->result = err; @@ -413,17 +413,17 @@ static void fail_command(struct iscsi_conn *conn, struct iscsi_cmd_task *ctask, scsi_in(sc)->resid = scsi_in(sc)->length; } - if (conn->ctask == ctask) - conn->ctask = NULL; + if (conn->task == task) + conn->task = NULL; /* release ref from queuecommand */ - __iscsi_put_ctask(ctask); + __iscsi_put_task(task); } static int iscsi_prep_mgmt_task(struct iscsi_conn *conn, - struct iscsi_cmd_task *ctask) + struct iscsi_task *task) { struct iscsi_session *session = conn->session; - struct iscsi_hdr *hdr = (struct iscsi_hdr *)ctask->hdr; + struct iscsi_hdr *hdr = (struct iscsi_hdr *)task->hdr; struct iscsi_nopout *nop = (struct iscsi_nopout *)hdr; if (conn->session->state == ISCSI_STATE_LOGGING_OUT) @@ -437,7 +437,7 @@ static int iscsi_prep_mgmt_task(struct iscsi_conn *conn, */ nop->cmdsn = cpu_to_be32(session->cmdsn); if (hdr->itt != RESERVED_ITT) { - hdr->itt = build_itt(ctask->itt, session->age); + hdr->itt = build_itt(task->itt, session->age); /* * TODO: We always use immediate, so we never hit this. * If we start to send tmfs or nops as non-immediate then @@ -451,24 +451,24 @@ static int iscsi_prep_mgmt_task(struct iscsi_conn *conn, } if (session->tt->init_task) - session->tt->init_task(ctask); + session->tt->init_task(task); if ((hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT) session->state = ISCSI_STATE_LOGGING_OUT; - list_move_tail(&ctask->running, &conn->mgmt_run_list); + list_move_tail(&task->running, &conn->mgmt_run_list); debug_scsi("mgmtpdu [op 0x%x hdr->itt 0x%x datalen %d]\n", hdr->opcode & ISCSI_OPCODE_MASK, hdr->itt, - ctask->data_count); + task->data_count); return 0; } -static struct iscsi_cmd_task * +static struct iscsi_task * __iscsi_conn_send_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, char *data, uint32_t data_size) { struct iscsi_session *session = conn->session; - struct iscsi_cmd_task *ctask; + struct iscsi_task *task; if (session->state == ISCSI_STATE_TERMINATE) return NULL; @@ -481,18 +481,18 @@ __iscsi_conn_send_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, * Same task can be used. Same ITT must be used. * Note that login_task is preallocated at conn_create(). */ - ctask = conn->login_ctask; + task = conn->login_task; else { BUG_ON(conn->c_stage == ISCSI_CONN_INITIAL_STAGE); BUG_ON(conn->c_stage == ISCSI_CONN_STOPPED); if (!__kfifo_get(session->cmdpool.queue, - (void*)&ctask, sizeof(void*))) + (void*)&task, sizeof(void*))) return NULL; if ((hdr->opcode == (ISCSI_OP_NOOP_OUT | ISCSI_OP_IMMEDIATE)) && hdr->ttt == RESERVED_ITT) { - conn->ping_ctask = ctask; + conn->ping_task = task; conn->last_ping = jiffies; } } @@ -501,33 +501,33 @@ __iscsi_conn_send_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, * released by the lld when it has transmitted the task for * pdus we do not expect a response for. */ - atomic_set(&ctask->refcount, 1); - ctask->conn = conn; - ctask->sc = NULL; + atomic_set(&task->refcount, 1); + task->conn = conn; + task->sc = NULL; if (data_size) { - memcpy(ctask->data, data, data_size); - ctask->data_count = data_size; + memcpy(task->data, data, data_size); + task->data_count = data_size; } else - ctask->data_count = 0; + task->data_count = 0; - memcpy(ctask->hdr, hdr, sizeof(struct iscsi_hdr)); - INIT_LIST_HEAD(&ctask->running); - list_add_tail(&ctask->running, &conn->mgmtqueue); + memcpy(task->hdr, hdr, sizeof(struct iscsi_hdr)); + INIT_LIST_HEAD(&task->running); + list_add_tail(&task->running, &conn->mgmtqueue); if (session->tt->caps & CAP_DATA_PATH_OFFLOAD) { - if (iscsi_prep_mgmt_task(conn, ctask)) { - __iscsi_put_ctask(ctask); + if (iscsi_prep_mgmt_task(conn, task)) { + __iscsi_put_task(task); return NULL; } - if (session->tt->xmit_task(ctask)) - ctask = NULL; + if (session->tt->xmit_task(task)) + task = NULL; } else scsi_queue_work(conn->session->host, &conn->xmitwork); - return ctask; + return task; } int iscsi_conn_send_pdu(struct iscsi_cls_conn *cls_conn, struct iscsi_hdr *hdr, @@ -549,20 +549,20 @@ EXPORT_SYMBOL_GPL(iscsi_conn_send_pdu); * iscsi_cmd_rsp - SCSI Command Response processing * @conn: iscsi connection * @hdr: iscsi header - * @ctask: scsi command task + * @task: scsi command task * @data: cmd data buffer * @datalen: len of buffer * * iscsi_cmd_rsp sets up the scsi_cmnd fields based on the PDU and - * then completes the command and ctask. + * then completes the command and task. **/ static void iscsi_scsi_cmd_rsp(struct iscsi_conn *conn, struct iscsi_hdr *hdr, - struct iscsi_cmd_task *ctask, char *data, + struct iscsi_task *task, char *data, int datalen) { struct iscsi_cmd_rsp *rhdr = (struct iscsi_cmd_rsp *)hdr; struct iscsi_session *session = conn->session; - struct scsi_cmnd *sc = ctask->sc; + struct scsi_cmnd *sc = task->sc; iscsi_update_cmdsn(session, (struct iscsi_nopin*)rhdr); conn->exp_statsn = be32_to_cpu(rhdr->statsn) + 1; @@ -622,10 +622,10 @@ invalid_datalen: } out: debug_scsi("done [sc %lx res %d itt 0x%x]\n", - (long)sc, sc->result, ctask->itt); + (long)sc, sc->result, task->itt); conn->scsirsp_pdus_cnt++; - __iscsi_put_ctask(ctask); + __iscsi_put_task(task); } static void iscsi_tmf_rsp(struct iscsi_conn *conn, struct iscsi_hdr *hdr) @@ -650,9 +650,9 @@ static void iscsi_tmf_rsp(struct iscsi_conn *conn, struct iscsi_hdr *hdr) static void iscsi_send_nopout(struct iscsi_conn *conn, struct iscsi_nopin *rhdr) { struct iscsi_nopout hdr; - struct iscsi_cmd_task *ctask; + struct iscsi_task *task; - if (!rhdr && conn->ping_ctask) + if (!rhdr && conn->ping_task) return; memset(&hdr, 0, sizeof(struct iscsi_nopout)); @@ -666,8 +666,8 @@ static void iscsi_send_nopout(struct iscsi_conn *conn, struct iscsi_nopin *rhdr) } else hdr.ttt = RESERVED_ITT; - ctask = __iscsi_conn_send_pdu(conn, (struct iscsi_hdr *)&hdr, NULL, 0); - if (!ctask) + task = __iscsi_conn_send_pdu(conn, (struct iscsi_hdr *)&hdr, NULL, 0); + if (!task) iscsi_conn_printk(KERN_ERR, conn, "Could not send nopout\n"); } @@ -712,7 +712,7 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, { struct iscsi_session *session = conn->session; int opcode = hdr->opcode & ISCSI_OPCODE_MASK, rc = 0; - struct iscsi_cmd_task *ctask; + struct iscsi_task *task; uint32_t itt; conn->last_recv = jiffies; @@ -758,27 +758,27 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, goto out; } - ctask = session->cmds[itt]; + task = session->cmds[itt]; switch(opcode) { case ISCSI_OP_SCSI_CMD_RSP: - if (!ctask->sc) { + if (!task->sc) { rc = ISCSI_ERR_NO_SCSI_CMD; break; } - BUG_ON((void*)ctask != ctask->sc->SCp.ptr); - iscsi_scsi_cmd_rsp(conn, hdr, ctask, data, datalen); + BUG_ON((void*)task != task->sc->SCp.ptr); + iscsi_scsi_cmd_rsp(conn, hdr, task, data, datalen); break; case ISCSI_OP_SCSI_DATA_IN: - if (!ctask->sc) { + if (!task->sc) { rc = ISCSI_ERR_NO_SCSI_CMD; break; } - BUG_ON((void*)ctask != ctask->sc->SCp.ptr); + BUG_ON((void*)task != task->sc->SCp.ptr); if (hdr->flags & ISCSI_FLAG_DATA_STATUS) { conn->scsirsp_pdus_cnt++; iscsi_update_cmdsn(session, (struct iscsi_nopin*) hdr); - __iscsi_put_ctask(ctask); + __iscsi_put_task(task); } break; case ISCSI_OP_R2T: @@ -808,7 +808,7 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, } iscsi_tmf_rsp(conn, hdr); - __iscsi_put_ctask(ctask); + __iscsi_put_task(task); break; case ISCSI_OP_NOOP_IN: iscsi_update_cmdsn(session, (struct iscsi_nopin*)hdr); @@ -818,13 +818,15 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, } conn->exp_statsn = be32_to_cpu(hdr->statsn) + 1; - if (conn->ping_ctask != ctask) + if (conn->ping_task != task) /* * If this is not in response to one of our * nops then it must be from userspace. */ goto recv_pdu; - __iscsi_put_ctask(ctask); + + mod_timer(&conn->transport_timer, jiffies + conn->recv_timeout); + __iscsi_put_task(task); break; default: rc = ISCSI_ERR_BAD_OPCODE; @@ -836,7 +838,7 @@ out: recv_pdu: if (iscsi_recv_pdu(conn->cls_conn, hdr, data, datalen)) rc = ISCSI_ERR_CONN_FAILED; - __iscsi_put_ctask(ctask); + __iscsi_put_task(task); return rc; } @@ -855,7 +857,7 @@ EXPORT_SYMBOL_GPL(iscsi_complete_pdu); int iscsi_verify_itt(struct iscsi_conn *conn, itt_t itt) { struct iscsi_session *session = conn->session; - struct iscsi_cmd_task *ctask; + struct iscsi_task *task; uint32_t i; if (itt == RESERVED_ITT) @@ -878,11 +880,11 @@ int iscsi_verify_itt(struct iscsi_conn *conn, itt_t itt) return ISCSI_ERR_BAD_ITT; } - ctask = session->cmds[i]; - if (ctask->sc && ctask->sc->SCp.phase != session->age) { + task = session->cmds[i]; + if (task->sc && task->sc->SCp.phase != session->age) { iscsi_conn_printk(KERN_ERR, conn, - "iscsi: ctask's session age %d, " - "expected %d\n", ctask->sc->SCp.phase, + "iscsi: task's session age %d, " + "expected %d\n", task->sc->SCp.phase, session->age); return ISCSI_ERR_SESSION_FAILED; } @@ -890,11 +892,11 @@ int iscsi_verify_itt(struct iscsi_conn *conn, itt_t itt) } EXPORT_SYMBOL_GPL(iscsi_verify_itt); -struct iscsi_cmd_task * +struct iscsi_task * iscsi_itt_to_ctask(struct iscsi_conn *conn, itt_t itt) { struct iscsi_session *session = conn->session; - struct iscsi_cmd_task *ctask; + struct iscsi_task *task; uint32_t i; if (iscsi_verify_itt(conn, itt)) @@ -907,14 +909,14 @@ iscsi_itt_to_ctask(struct iscsi_conn *conn, itt_t itt) if (i >= session->cmds_max) return NULL; - ctask = session->cmds[i]; - if (!ctask->sc) + task = session->cmds[i]; + if (!task->sc) return NULL; - if (ctask->sc->SCp.phase != session->age) + if (task->sc->SCp.phase != session->age) return NULL; - return ctask; + return task; } EXPORT_SYMBOL_GPL(iscsi_itt_to_ctask); @@ -955,38 +957,38 @@ static int iscsi_check_cmdsn_window_closed(struct iscsi_conn *conn) return 0; } -static int iscsi_xmit_ctask(struct iscsi_conn *conn) +static int iscsi_xmit_task(struct iscsi_conn *conn) { - struct iscsi_cmd_task *ctask = conn->ctask; + struct iscsi_task *task = conn->task; int rc; - __iscsi_get_ctask(ctask); + __iscsi_get_task(task); spin_unlock_bh(&conn->session->lock); - rc = conn->session->tt->xmit_task(ctask); + rc = conn->session->tt->xmit_task(task); spin_lock_bh(&conn->session->lock); - __iscsi_put_ctask(ctask); + __iscsi_put_task(task); if (!rc) - /* done with this ctask */ - conn->ctask = NULL; + /* done with this task */ + conn->task = NULL; return rc; } /** - * iscsi_requeue_ctask - requeue ctask to run from session workqueue - * @ctask: ctask to requeue + * iscsi_requeue_task - requeue task to run from session workqueue + * @task: task to requeue * - * LLDs that need to run a ctask from the session workqueue should call + * LLDs that need to run a task from the session workqueue should call * this. The session lock must be held. This should only be called * by software drivers. */ -void iscsi_requeue_ctask(struct iscsi_cmd_task *ctask) +void iscsi_requeue_task(struct iscsi_task *task) { - struct iscsi_conn *conn = ctask->conn; + struct iscsi_conn *conn = task->conn; - list_move_tail(&ctask->running, &conn->requeue); + list_move_tail(&task->running, &conn->requeue); scsi_queue_work(conn->session->host, &conn->xmitwork); } -EXPORT_SYMBOL_GPL(iscsi_requeue_ctask); +EXPORT_SYMBOL_GPL(iscsi_requeue_task); /** * iscsi_data_xmit - xmit any command into the scheduled connection @@ -1008,8 +1010,8 @@ static int iscsi_data_xmit(struct iscsi_conn *conn) return -ENODATA; } - if (conn->ctask) { - rc = iscsi_xmit_ctask(conn); + if (conn->task) { + rc = iscsi_xmit_task(conn); if (rc) goto again; } @@ -1021,14 +1023,14 @@ static int iscsi_data_xmit(struct iscsi_conn *conn) */ check_mgmt: while (!list_empty(&conn->mgmtqueue)) { - conn->ctask = list_entry(conn->mgmtqueue.next, - struct iscsi_cmd_task, running); - if (iscsi_prep_mgmt_task(conn, conn->ctask)) { - __iscsi_put_ctask(conn->ctask); - conn->ctask = NULL; + conn->task = list_entry(conn->mgmtqueue.next, + struct iscsi_task, running); + if (iscsi_prep_mgmt_task(conn, conn->task)) { + __iscsi_put_task(conn->task); + conn->task = NULL; continue; } - rc = iscsi_xmit_ctask(conn); + rc = iscsi_xmit_task(conn); if (rc) goto again; } @@ -1038,21 +1040,21 @@ check_mgmt: if (conn->tmf_state == TMF_QUEUED) break; - conn->ctask = list_entry(conn->xmitqueue.next, - struct iscsi_cmd_task, running); + conn->task = list_entry(conn->xmitqueue.next, + struct iscsi_task, running); if (conn->session->state == ISCSI_STATE_LOGGING_OUT) { - fail_command(conn, conn->ctask, DID_IMM_RETRY << 16); + fail_command(conn, conn->task, DID_IMM_RETRY << 16); continue; } - if (iscsi_prep_scsi_cmd_pdu(conn->ctask)) { - fail_command(conn, conn->ctask, DID_ABORT << 16); + if (iscsi_prep_scsi_cmd_pdu(conn->task)) { + fail_command(conn, conn->task, DID_ABORT << 16); continue; } - rc = iscsi_xmit_ctask(conn); + rc = iscsi_xmit_task(conn); if (rc) goto again; /* - * we could continuously get new ctask requests so + * we could continuously get new task requests so * we need to check the mgmt queue for nops that need to * be sent to aviod starvation */ @@ -1070,11 +1072,11 @@ check_mgmt: if (conn->session->state == ISCSI_STATE_LOGGING_OUT) break; - conn->ctask = list_entry(conn->requeue.next, - struct iscsi_cmd_task, running); - conn->ctask->state = ISCSI_TASK_RUNNING; + conn->task = list_entry(conn->requeue.next, + struct iscsi_task, running); + conn->task->state = ISCSI_TASK_RUNNING; list_move_tail(conn->requeue.next, &conn->run_list); - rc = iscsi_xmit_ctask(conn); + rc = iscsi_xmit_task(conn); if (rc) goto again; if (!list_empty(&conn->mgmtqueue)) @@ -1123,7 +1125,7 @@ int iscsi_queuecommand(struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *)) int reason = 0; struct iscsi_session *session; struct iscsi_conn *conn; - struct iscsi_cmd_task *ctask = NULL; + struct iscsi_task *task = NULL; sc->scsi_done = done; sc->result = 0; @@ -1191,31 +1193,31 @@ int iscsi_queuecommand(struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *)) goto reject; } - if (!__kfifo_get(session->cmdpool.queue, (void*)&ctask, + if (!__kfifo_get(session->cmdpool.queue, (void*)&task, sizeof(void*))) { reason = FAILURE_OOM; goto reject; } sc->SCp.phase = session->age; - sc->SCp.ptr = (char *)ctask; + sc->SCp.ptr = (char *)task; - atomic_set(&ctask->refcount, 1); - ctask->state = ISCSI_TASK_PENDING; - ctask->conn = conn; - ctask->sc = sc; - INIT_LIST_HEAD(&ctask->running); - list_add_tail(&ctask->running, &conn->xmitqueue); + atomic_set(&task->refcount, 1); + task->state = ISCSI_TASK_PENDING; + task->conn = conn; + task->sc = sc; + INIT_LIST_HEAD(&task->running); + list_add_tail(&task->running, &conn->xmitqueue); if (session->tt->caps & CAP_DATA_PATH_OFFLOAD) { - if (iscsi_prep_scsi_cmd_pdu(ctask)) { + if (iscsi_prep_scsi_cmd_pdu(task)) { sc->result = DID_ABORT << 16; sc->scsi_done = NULL; - iscsi_complete_command(ctask); + iscsi_complete_command(task); goto fault; } - if (session->tt->xmit_task(ctask)) { + if (session->tt->xmit_task(task)) { sc->scsi_done = NULL; - iscsi_complete_command(ctask); + iscsi_complete_command(task); reason = FAILURE_SESSION_NOT_READY; goto reject; } @@ -1336,16 +1338,16 @@ static void iscsi_tmf_timedout(unsigned long data) spin_unlock(&session->lock); } -static int iscsi_exec_ctask_mgmt_fn(struct iscsi_conn *conn, +static int iscsi_exec_task_mgmt_fn(struct iscsi_conn *conn, struct iscsi_tm *hdr, int age, int timeout) { struct iscsi_session *session = conn->session; - struct iscsi_cmd_task *ctask; + struct iscsi_task *task; - ctask = __iscsi_conn_send_pdu(conn, (struct iscsi_hdr *)hdr, + task = __iscsi_conn_send_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); - if (!ctask) { + if (!task) { spin_unlock_bh(&session->lock); iscsi_conn_failure(conn, ISCSI_ERR_CONN_FAILED); spin_lock_bh(&session->lock); @@ -1379,7 +1381,7 @@ static int iscsi_exec_ctask_mgmt_fn(struct iscsi_conn *conn, mutex_lock(&session->eh_mutex); spin_lock_bh(&session->lock); - /* if the session drops it will clean up the ctask */ + /* if the session drops it will clean up the task */ if (age != session->age || session->state != ISCSI_STATE_LOGGED_IN) return -ENOTCONN; @@ -1393,34 +1395,34 @@ static int iscsi_exec_ctask_mgmt_fn(struct iscsi_conn *conn, static void fail_all_commands(struct iscsi_conn *conn, unsigned lun, int error) { - struct iscsi_cmd_task *ctask, *tmp; + struct iscsi_task *task, *tmp; - if (conn->ctask && (conn->ctask->sc->device->lun == lun || lun == -1)) - conn->ctask = NULL; + if (conn->task && (conn->task->sc->device->lun == lun || lun == -1)) + conn->task = NULL; /* flush pending */ - list_for_each_entry_safe(ctask, tmp, &conn->xmitqueue, running) { - if (lun == ctask->sc->device->lun || lun == -1) { + list_for_each_entry_safe(task, tmp, &conn->xmitqueue, running) { + if (lun == task->sc->device->lun || lun == -1) { debug_scsi("failing pending sc %p itt 0x%x\n", - ctask->sc, ctask->itt); - fail_command(conn, ctask, error << 16); + task->sc, task->itt); + fail_command(conn, task, error << 16); } } - list_for_each_entry_safe(ctask, tmp, &conn->requeue, running) { - if (lun == ctask->sc->device->lun || lun == -1) { + list_for_each_entry_safe(task, tmp, &conn->requeue, running) { + if (lun == task->sc->device->lun || lun == -1) { debug_scsi("failing requeued sc %p itt 0x%x\n", - ctask->sc, ctask->itt); - fail_command(conn, ctask, error << 16); + task->sc, task->itt); + fail_command(conn, task, error << 16); } } /* fail all other running */ - list_for_each_entry_safe(ctask, tmp, &conn->run_list, running) { - if (lun == ctask->sc->device->lun || lun == -1) { + list_for_each_entry_safe(task, tmp, &conn->run_list, running) { + if (lun == task->sc->device->lun || lun == -1) { debug_scsi("failing in progress sc %p itt 0x%x\n", - ctask->sc, ctask->itt); - fail_command(conn, ctask, DID_BUS_BUSY << 16); + task->sc, task->itt); + fail_command(conn, task, DID_BUS_BUSY << 16); } } } @@ -1486,7 +1488,7 @@ static enum scsi_eh_timer_return iscsi_eh_cmd_timed_out(struct scsi_cmnd *scmd) jiffies)) rc = EH_RESET_TIMER; /* if in the middle of checking the transport then give us more time */ - if (conn->ping_ctask) + if (conn->ping_task) rc = EH_RESET_TIMER; done: spin_unlock(&session->lock); @@ -1510,7 +1512,7 @@ static void iscsi_check_transport_timeouts(unsigned long data) recv_timeout *= HZ; last_recv = conn->last_recv; - if (conn->ping_ctask && + if (conn->ping_task && time_before_eq(conn->last_ping + (conn->ping_timeout * HZ), jiffies)) { iscsi_conn_printk(KERN_ERR, conn, "ping timeout of %d secs " @@ -1536,16 +1538,16 @@ done: spin_unlock(&session->lock); } -static void iscsi_prep_abort_ctask_pdu(struct iscsi_cmd_task *ctask, +static void iscsi_prep_abort_task_pdu(struct iscsi_task *task, struct iscsi_tm *hdr) { memset(hdr, 0, sizeof(*hdr)); hdr->opcode = ISCSI_OP_SCSI_TMFUNC | ISCSI_OP_IMMEDIATE; hdr->flags = ISCSI_TM_FUNC_ABORT_TASK & ISCSI_FLAG_TM_FUNC_MASK; hdr->flags |= ISCSI_FLAG_CMD_FINAL; - memcpy(hdr->lun, ctask->hdr->lun, sizeof(hdr->lun)); - hdr->rtt = ctask->hdr->itt; - hdr->refcmdsn = ctask->hdr->cmdsn; + memcpy(hdr->lun, task->hdr->lun, sizeof(hdr->lun)); + hdr->rtt = task->hdr->itt; + hdr->refcmdsn = task->hdr->cmdsn; } int iscsi_eh_abort(struct scsi_cmnd *sc) @@ -1553,7 +1555,7 @@ int iscsi_eh_abort(struct scsi_cmnd *sc) struct iscsi_cls_session *cls_session; struct iscsi_session *session; struct iscsi_conn *conn; - struct iscsi_cmd_task *ctask; + struct iscsi_task *task; struct iscsi_tm *hdr; int rc, age; @@ -1588,17 +1590,17 @@ int iscsi_eh_abort(struct scsi_cmnd *sc) conn->eh_abort_cnt++; age = session->age; - ctask = (struct iscsi_cmd_task *)sc->SCp.ptr; - debug_scsi("aborting [sc %p itt 0x%x]\n", sc, ctask->itt); + task = (struct iscsi_task *)sc->SCp.ptr; + debug_scsi("aborting [sc %p itt 0x%x]\n", sc, task->itt); - /* ctask completed before time out */ - if (!ctask->sc) { + /* task completed before time out */ + if (!task->sc) { debug_scsi("sc completed while abort in progress\n"); goto success; } - if (ctask->state == ISCSI_TASK_PENDING) { - fail_command(conn, ctask, DID_ABORT << 16); + if (task->state == ISCSI_TASK_PENDING) { + fail_command(conn, task, DID_ABORT << 16); goto success; } @@ -1608,9 +1610,9 @@ int iscsi_eh_abort(struct scsi_cmnd *sc) conn->tmf_state = TMF_QUEUED; hdr = &conn->tmhdr; - iscsi_prep_abort_ctask_pdu(ctask, hdr); + iscsi_prep_abort_task_pdu(task, hdr); - if (iscsi_exec_ctask_mgmt_fn(conn, hdr, age, session->abort_timeout)) { + if (iscsi_exec_task_mgmt_fn(conn, hdr, age, session->abort_timeout)) { rc = FAILED; goto failed; } @@ -1620,11 +1622,11 @@ int iscsi_eh_abort(struct scsi_cmnd *sc) spin_unlock_bh(&session->lock); iscsi_suspend_tx(conn); /* - * clean up ctask if aborted. grab the recv lock as a writer + * clean up task if aborted. grab the recv lock as a writer */ write_lock_bh(conn->recv_lock); spin_lock(&session->lock); - fail_command(conn, ctask, DID_ABORT << 16); + fail_command(conn, task, DID_ABORT << 16); conn->tmf_state = TMF_INITIAL; spin_unlock(&session->lock); write_unlock_bh(conn->recv_lock); @@ -1637,7 +1639,7 @@ int iscsi_eh_abort(struct scsi_cmnd *sc) case TMF_NOT_FOUND: if (!sc->SCp.ptr) { conn->tmf_state = TMF_INITIAL; - /* ctask completed before tmf abort response */ + /* task completed before tmf abort response */ debug_scsi("sc completed while abort in progress\n"); goto success; } @@ -1650,7 +1652,7 @@ int iscsi_eh_abort(struct scsi_cmnd *sc) success: spin_unlock_bh(&session->lock); success_unlocked: - debug_scsi("abort success [sc %lx itt 0x%x]\n", (long)sc, ctask->itt); + debug_scsi("abort success [sc %lx itt 0x%x]\n", (long)sc, task->itt); mutex_unlock(&session->eh_mutex); return SUCCESS; @@ -1658,7 +1660,7 @@ failed: spin_unlock_bh(&session->lock); failed_unlocked: debug_scsi("abort failed [sc %p itt 0x%x]\n", sc, - ctask ? ctask->itt : 0); + task ? task->itt : 0); mutex_unlock(&session->eh_mutex); return FAILED; } @@ -1705,7 +1707,7 @@ int iscsi_eh_device_reset(struct scsi_cmnd *sc) hdr = &conn->tmhdr; iscsi_prep_lun_reset_pdu(sc, hdr); - if (iscsi_exec_ctask_mgmt_fn(conn, hdr, session->age, + if (iscsi_exec_task_mgmt_fn(conn, hdr, session->age, session->lu_reset_timeout)) { rc = FAILED; goto unlock; @@ -1886,7 +1888,7 @@ EXPORT_SYMBOL_GPL(iscsi_host_free); * @iscsit: iscsi transport template * @shost: scsi host * @cmds_max: session can queue - * @cmd_ctask_size: LLD ctask private data size + * @cmd_task_size: LLD task private data size * @initial_cmdsn: initial CmdSN * * This can be used by software iscsi_transports that allocate @@ -1894,7 +1896,7 @@ EXPORT_SYMBOL_GPL(iscsi_host_free); */ struct iscsi_cls_session * iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, - uint16_t scsi_cmds_max, int cmd_ctask_size, + uint16_t scsi_cmds_max, int cmd_task_size, uint32_t initial_cmdsn) { struct iscsi_session *session; @@ -1902,7 +1904,7 @@ iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, int cmd_i, cmds_max; /* - * The iscsi layer needs some ctasks for nop handling and tmfs. + * The iscsi layer needs some tasks for nop handling and tmfs. */ if (scsi_cmds_max < 1) scsi_cmds_max = ISCSI_MGMT_CMDS_MAX; @@ -1939,17 +1941,17 @@ iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, /* initialize SCSI PDU commands pool */ if (iscsi_pool_init(&session->cmdpool, session->cmds_max, (void***)&session->cmds, - cmd_ctask_size + sizeof(struct iscsi_cmd_task))) + cmd_task_size + sizeof(struct iscsi_task))) goto cmdpool_alloc_fail; /* pre-format cmds pool with ITT */ for (cmd_i = 0; cmd_i < session->cmds_max; cmd_i++) { - struct iscsi_cmd_task *ctask = session->cmds[cmd_i]; + struct iscsi_task *task = session->cmds[cmd_i]; - if (cmd_ctask_size) - ctask->dd_data = &ctask[1]; - ctask->itt = cmd_i; - INIT_LIST_HEAD(&ctask->running); + if (cmd_task_size) + task->dd_data = &task[1]; + task->itt = cmd_i; + INIT_LIST_HEAD(&task->running); } if (!try_module_get(iscsit->owner)) @@ -2035,30 +2037,30 @@ iscsi_conn_setup(struct iscsi_cls_session *cls_session, int dd_size, INIT_LIST_HEAD(&conn->requeue); INIT_WORK(&conn->xmitwork, iscsi_xmitworker); - /* allocate login_ctask used for the login/text sequences */ + /* allocate login_task used for the login/text sequences */ spin_lock_bh(&session->lock); if (!__kfifo_get(session->cmdpool.queue, - (void*)&conn->login_ctask, + (void*)&conn->login_task, sizeof(void*))) { spin_unlock_bh(&session->lock); - goto login_ctask_alloc_fail; + goto login_task_alloc_fail; } spin_unlock_bh(&session->lock); data = kmalloc(ISCSI_DEF_MAX_RECV_SEG_LEN, GFP_KERNEL); if (!data) - goto login_ctask_data_alloc_fail; - conn->login_ctask->data = conn->data = data; + goto login_task_data_alloc_fail; + conn->login_task->data = conn->data = data; init_timer(&conn->tmf_timer); init_waitqueue_head(&conn->ehwait); return cls_conn; -login_ctask_data_alloc_fail: - __kfifo_put(session->cmdpool.queue, (void*)&conn->login_ctask, +login_task_data_alloc_fail: + __kfifo_put(session->cmdpool.queue, (void*)&conn->login_task, sizeof(void*)); -login_ctask_alloc_fail: +login_task_alloc_fail: iscsi_destroy_conn(cls_conn); return NULL; } @@ -2118,7 +2120,7 @@ void iscsi_conn_teardown(struct iscsi_cls_conn *cls_conn) spin_lock_bh(&session->lock); kfree(conn->data); kfree(conn->persistent_address); - __kfifo_put(session->cmdpool.queue, (void*)&conn->login_ctask, + __kfifo_put(session->cmdpool.queue, (void*)&conn->login_task, sizeof(void*)); if (session->leadconn == conn) session->leadconn = NULL; @@ -2199,23 +2201,23 @@ EXPORT_SYMBOL_GPL(iscsi_conn_start); static void flush_control_queues(struct iscsi_session *session, struct iscsi_conn *conn) { - struct iscsi_cmd_task *ctask, *tmp; + struct iscsi_task *task, *tmp; /* handle pending */ - list_for_each_entry_safe(ctask, tmp, &conn->mgmtqueue, running) { - debug_scsi("flushing pending mgmt ctask itt 0x%x\n", ctask->itt); - /* release ref from prep ctask */ - __iscsi_put_ctask(ctask); + list_for_each_entry_safe(task, tmp, &conn->mgmtqueue, running) { + debug_scsi("flushing pending mgmt task itt 0x%x\n", task->itt); + /* release ref from prep task */ + __iscsi_put_task(task); } /* handle running */ - list_for_each_entry_safe(ctask, tmp, &conn->mgmt_run_list, running) { - debug_scsi("flushing running mgmt ctask itt 0x%x\n", ctask->itt); - /* release ref from prep ctask */ - __iscsi_put_ctask(ctask); + list_for_each_entry_safe(task, tmp, &conn->mgmt_run_list, running) { + debug_scsi("flushing running mgmt task itt 0x%x\n", task->itt); + /* release ref from prep task */ + __iscsi_put_task(task); } - conn->ctask = NULL; + conn->task = NULL; } static void iscsi_start_session_recovery(struct iscsi_session *session, @@ -2246,7 +2248,7 @@ static void iscsi_start_session_recovery(struct iscsi_session *session, /* * When this is called for the in_login state, we only want to clean - * up the login ctask and connection. We do not need to block and set + * up the login task and connection. We do not need to block and set * the recovery state again */ if (flag == STOP_CONN_TERM) diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index d1c36759b350..176353c117b6 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -92,7 +92,7 @@ enum { ISCSI_TASK_RUNNING, }; -struct iscsi_cmd_task { +struct iscsi_task { /* * Because LLDs allocate their hdr differently, this is a pointer * and length to that storage. It must be setup at session @@ -120,9 +120,9 @@ struct iscsi_cmd_task { void *dd_data; /* driver/transport data */ }; -static inline void* iscsi_next_hdr(struct iscsi_cmd_task *ctask) +static inline void* iscsi_next_hdr(struct iscsi_task *task) { - return (void*)ctask->hdr + ctask->hdr_len; + return (void*)task->hdr + task->hdr_len; } /* Connection's states */ @@ -151,7 +151,7 @@ struct iscsi_conn { unsigned long last_ping; int ping_timeout; int recv_timeout; - struct iscsi_cmd_task *ping_ctask; + struct iscsi_task *ping_task; /* iSCSI connection-wide sequencing */ uint32_t exp_statsn; @@ -167,8 +167,8 @@ struct iscsi_conn { * should always fit in this buffer */ char *data; - struct iscsi_cmd_task *login_ctask; /* mtask used for login/text */ - struct iscsi_cmd_task *ctask; /* xmit task in progress */ + struct iscsi_task *login_task; /* mtask used for login/text */ + struct iscsi_task *task; /* xmit task in progress */ /* xmit */ struct list_head mgmtqueue; /* mgmt (control) xmit queue */ @@ -285,7 +285,7 @@ struct iscsi_session { int scsi_cmds_max; /* max scsi commands */ int cmds_max; /* size of cmds array */ - struct iscsi_cmd_task **cmds; /* Original Cmds arr */ + struct iscsi_task **cmds; /* Original Cmds arr */ struct iscsi_pool cmdpool; /* PDU's pool */ }; @@ -365,16 +365,16 @@ extern void iscsi_suspend_tx(struct iscsi_conn *conn); * pdu and task processing */ extern void iscsi_update_cmdsn(struct iscsi_session *, struct iscsi_nopin *); -extern void iscsi_prep_unsolicit_data_pdu(struct iscsi_cmd_task *, +extern void iscsi_prep_unsolicit_data_pdu(struct iscsi_task *, struct iscsi_data *hdr); extern int iscsi_conn_send_pdu(struct iscsi_cls_conn *, struct iscsi_hdr *, char *, uint32_t); extern int iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *, char *, int); extern int iscsi_verify_itt(struct iscsi_conn *, itt_t); -extern struct iscsi_cmd_task *iscsi_itt_to_ctask(struct iscsi_conn *, itt_t); -extern void iscsi_requeue_ctask(struct iscsi_cmd_task *ctask); -extern void iscsi_put_ctask(struct iscsi_cmd_task *ctask); +extern struct iscsi_task *iscsi_itt_to_ctask(struct iscsi_conn *, itt_t); +extern void iscsi_requeue_task(struct iscsi_task *task); +extern void iscsi_put_task(struct iscsi_task *task); /* * generic helpers diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index 3f24503dfdf9..0553240796e9 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -33,7 +33,7 @@ struct iscsi_transport; struct Scsi_Host; struct iscsi_cls_conn; struct iscsi_conn; -struct iscsi_cmd_task; +struct iscsi_task; struct sockaddr; /** @@ -112,10 +112,10 @@ struct iscsi_transport { char *data, uint32_t data_size); void (*get_stats) (struct iscsi_cls_conn *conn, struct iscsi_stats *stats); - int (*init_task) (struct iscsi_cmd_task *task); - int (*xmit_task) (struct iscsi_cmd_task *task); + int (*init_task) (struct iscsi_task *task); + int (*xmit_task) (struct iscsi_task *task); void (*cleanup_task) (struct iscsi_conn *conn, - struct iscsi_cmd_task *task); + struct iscsi_task *task); void (*session_recovery_timedout) (struct iscsi_cls_session *session); int (*ep_connect) (struct sockaddr *dst_addr, int non_blocking, uint64_t *ep_handle); -- cgit v1.2.3 From 7970634b81a6e3561954517bca42615542c4535b Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:12 -0500 Subject: [SCSI] iscsi class: user device_for_each_child instead of duplicating session list Currently we duplicate the list of sessions, because we were using the test for if a session was on the host list to indicate if the session was bound or unbound. We can instead use the target_id and fix up the class so that drivers like bnx2i do not have to manage the target id space. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 2 +- drivers/scsi/iscsi_tcp.c | 2 +- drivers/scsi/libiscsi.c | 4 +- drivers/scsi/scsi_transport_iscsi.c | 125 ++++++++++++++++++++++++------- include/scsi/libiscsi.h | 2 +- include/scsi/scsi_transport_iscsi.h | 6 +- 6 files changed, 104 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index 86d9c42f0d33..3a89039e9a96 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -437,7 +437,7 @@ iscsi_iser_session_create(struct Scsi_Host *shost, cls_session = iscsi_session_setup(&iscsi_iser_transport, shost, ISCSI_DEF_XMIT_CMDS_MAX, sizeof(struct iscsi_iser_task), - initial_cmdsn); + initial_cmdsn, 0); if (!cls_session) goto remove_host; session = cls_session->dd_data; diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 33cd0ca7cc8d..aa3c7f0c550d 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -1868,7 +1868,7 @@ iscsi_tcp_session_create(struct Scsi_Host *shost, uint16_t cmds_max, cls_session = iscsi_session_setup(&iscsi_tcp_transport, shost, cmds_max, sizeof(struct iscsi_tcp_task), - initial_cmdsn); + initial_cmdsn, 0); if (!cls_session) goto remove_host; session = cls_session->dd_data; diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index 92ee6d94aaf9..e88b726ab2e0 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -1897,7 +1897,7 @@ EXPORT_SYMBOL_GPL(iscsi_host_free); struct iscsi_cls_session * iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, uint16_t scsi_cmds_max, int cmd_task_size, - uint32_t initial_cmdsn) + uint32_t initial_cmdsn, unsigned int id) { struct iscsi_session *session; struct iscsi_cls_session *cls_session; @@ -1957,7 +1957,7 @@ iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, if (!try_module_get(iscsit->owner)) goto module_get_fail; - if (iscsi_add_session(cls_session, 0)) + if (iscsi_add_session(cls_session, id)) goto cls_session_fail; return cls_session; diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index 6b8516a0970b..ac9d298f54e7 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -119,9 +119,8 @@ static int iscsi_setup_host(struct transport_container *tc, struct device *dev, struct iscsi_cls_host *ihost = shost->shost_data; memset(ihost, 0, sizeof(*ihost)); - INIT_LIST_HEAD(&ihost->sessions); - mutex_init(&ihost->mutex); atomic_set(&ihost->nr_scans, 0); + mutex_init(&ihost->mutex); snprintf(ihost->scan_workq_name, KOBJ_NAME_LEN, "iscsi_scan_%d", shost->host_no); @@ -316,42 +315,76 @@ int iscsi_scan_finished(struct Scsi_Host *shost, unsigned long time) } EXPORT_SYMBOL_GPL(iscsi_scan_finished); -static int iscsi_user_scan(struct Scsi_Host *shost, uint channel, - uint id, uint lun) +struct iscsi_scan_data { + unsigned int channel; + unsigned int id; + unsigned int lun; +}; + +static int iscsi_user_scan_session(struct device *dev, void *data) { - struct iscsi_cls_host *ihost = shost->shost_data; + struct iscsi_scan_data *scan_data = data; struct iscsi_cls_session *session; + struct Scsi_Host *shost; + struct iscsi_cls_host *ihost; + unsigned long flags; + unsigned int id; + + if (!iscsi_is_session_dev(dev)) + return 0; + + session = iscsi_dev_to_session(dev); + shost = iscsi_session_to_shost(session); + ihost = shost->shost_data; mutex_lock(&ihost->mutex); - list_for_each_entry(session, &ihost->sessions, host_list) { - if ((channel == SCAN_WILD_CARD || channel == 0) && - (id == SCAN_WILD_CARD || id == session->target_id)) - scsi_scan_target(&session->dev, 0, - session->target_id, lun, 1); + spin_lock_irqsave(&session->lock, flags); + if (session->state != ISCSI_SESSION_LOGGED_IN) { + spin_unlock_irqrestore(&session->lock, flags); + mutex_unlock(&ihost->mutex); + return 0; } - mutex_unlock(&ihost->mutex); + id = session->target_id; + spin_unlock_irqrestore(&session->lock, flags); + if (id != ISCSI_MAX_TARGET) { + if ((scan_data->channel == SCAN_WILD_CARD || + scan_data->channel == 0) && + (scan_data->id == SCAN_WILD_CARD || + scan_data->id == id)) + scsi_scan_target(&session->dev, 0, id, + scan_data->lun, 1); + } + mutex_unlock(&ihost->mutex); return 0; } +static int iscsi_user_scan(struct Scsi_Host *shost, uint channel, + uint id, uint lun) +{ + struct iscsi_scan_data scan_data; + + scan_data.channel = channel; + scan_data.id = id; + scan_data.lun = lun; + + return device_for_each_child(&shost->shost_gendev, &scan_data, + iscsi_user_scan_session); +} + static void iscsi_scan_session(struct work_struct *work) { struct iscsi_cls_session *session = container_of(work, struct iscsi_cls_session, scan_work); struct Scsi_Host *shost = iscsi_session_to_shost(session); struct iscsi_cls_host *ihost = shost->shost_data; - unsigned long flags; + struct iscsi_scan_data scan_data; - spin_lock_irqsave(&session->lock, flags); - if (session->state != ISCSI_SESSION_LOGGED_IN) { - spin_unlock_irqrestore(&session->lock, flags); - goto done; - } - spin_unlock_irqrestore(&session->lock, flags); + scan_data.channel = 0; + scan_data.id = SCAN_WILD_CARD; + scan_data.lun = SCAN_WILD_CARD; - scsi_scan_target(&session->dev, 0, session->target_id, - SCAN_WILD_CARD, 1); -done: + iscsi_user_scan_session(&session->dev, &scan_data); atomic_dec(&ihost->nr_scans); } @@ -460,14 +493,18 @@ static void __iscsi_unbind_session(struct work_struct *work) unbind_work); struct Scsi_Host *shost = iscsi_session_to_shost(session); struct iscsi_cls_host *ihost = shost->shost_data; + unsigned long flags; /* Prevent new scans and make sure scanning is not in progress */ mutex_lock(&ihost->mutex); - if (list_empty(&session->host_list)) { + spin_lock_irqsave(&session->lock, flags); + if (session->target_id == ISCSI_MAX_TARGET) { + spin_unlock_irqrestore(&session->lock, flags); mutex_unlock(&ihost->mutex); return; } - list_del_init(&session->host_list); + session->target_id = ISCSI_MAX_TARGET; + spin_unlock_irqrestore(&session->lock, flags); mutex_unlock(&ihost->mutex); scsi_remove_target(&session->dev); @@ -497,7 +534,6 @@ iscsi_alloc_session(struct Scsi_Host *shost, struct iscsi_transport *transport, session->recovery_tmo = 120; session->state = ISCSI_SESSION_FREE; INIT_DELAYED_WORK(&session->recovery_work, session_recovery_timedout); - INIT_LIST_HEAD(&session->host_list); INIT_LIST_HEAD(&session->sess_list); INIT_WORK(&session->unblock_work, __iscsi_unblock_session); INIT_WORK(&session->block_work, __iscsi_block_session); @@ -516,16 +552,51 @@ iscsi_alloc_session(struct Scsi_Host *shost, struct iscsi_transport *transport, } EXPORT_SYMBOL_GPL(iscsi_alloc_session); +static int iscsi_get_next_target_id(struct device *dev, void *data) +{ + struct iscsi_cls_session *session; + unsigned long flags; + int err = 0; + + if (!iscsi_is_session_dev(dev)) + return 0; + + session = iscsi_dev_to_session(dev); + spin_lock_irqsave(&session->lock, flags); + if (*((unsigned int *) data) == session->target_id) + err = -EEXIST; + spin_unlock_irqrestore(&session->lock, flags); + return err; +} + int iscsi_add_session(struct iscsi_cls_session *session, unsigned int target_id) { struct Scsi_Host *shost = iscsi_session_to_shost(session); struct iscsi_cls_host *ihost; unsigned long flags; + unsigned int id = target_id; int err; ihost = shost->shost_data; session->sid = atomic_add_return(1, &iscsi_session_nr); - session->target_id = target_id; + + if (id == ISCSI_MAX_TARGET) { + for (id = 0; id < ISCSI_MAX_TARGET; id++) { + err = device_for_each_child(&shost->shost_gendev, &id, + iscsi_get_next_target_id); + if (!err) + break; + } + + if (id == ISCSI_MAX_TARGET) { + iscsi_cls_session_printk(KERN_ERR, session, + "Too many iscsi targets. Max " + "number of targets is %d.\n", + ISCSI_MAX_TARGET - 1); + goto release_host; + } + } + session->target_id = id; snprintf(session->dev.bus_id, BUS_ID_SIZE, "session%u", session->sid); @@ -541,10 +612,6 @@ int iscsi_add_session(struct iscsi_cls_session *session, unsigned int target_id) list_add(&session->sess_list, &sesslist); spin_unlock_irqrestore(&sesslock, flags); - mutex_lock(&ihost->mutex); - list_add(&session->host_list, &ihost->sessions); - mutex_unlock(&ihost->mutex); - iscsi_session_event(session, ISCSI_KEVENT_CREATE_SESSION); return 0; diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index 176353c117b6..13c92d7ba969 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -331,7 +331,7 @@ extern void iscsi_host_free(struct Scsi_Host *shost); */ extern struct iscsi_cls_session * iscsi_session_setup(struct iscsi_transport *, struct Scsi_Host *shost, - uint16_t, int, uint32_t); + uint16_t, int, uint32_t, unsigned int); extern void iscsi_session_teardown(struct iscsi_cls_session *); extern void iscsi_session_recovery_timedout(struct iscsi_cls_session *); extern int iscsi_set_param(struct iscsi_cls_conn *cls_conn, diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index 0553240796e9..d6b823195563 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -161,9 +161,10 @@ enum { ISCSI_SESSION_FREE, }; +#define ISCSI_MAX_TARGET -1 + struct iscsi_cls_session { struct list_head sess_list; /* item in session_list */ - struct list_head host_list; struct iscsi_transport *transport; spinlock_t lock; struct work_struct block_work; @@ -175,7 +176,7 @@ struct iscsi_cls_session { int recovery_tmo; struct delayed_work recovery_work; - int target_id; + unsigned int target_id; int state; int sid; /* session id */ @@ -193,7 +194,6 @@ struct iscsi_cls_session { iscsi_dev_to_session(_stgt->dev.parent) struct iscsi_cls_host { - struct list_head sessions; atomic_t nr_scans; struct mutex mutex; struct workqueue_struct *scan_workq; -- cgit v1.2.3 From d82ff9be733a2e6da4f6c2ab4e9216f3f536503d Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:13 -0500 Subject: [SCSI] iscsi class: add endpoint class Add sysfs representation for the endpoint, so userspace can match the host and session to the endpoint. This will allow us to set the host's parent correctly at host creation time. The next patches will convert tcp and iser, and fix iser's dma_mask bug. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/scsi/scsi_transport_iscsi.c | 190 +++++++++++++++++++++++++++++------- include/scsi/iscsi_if.h | 2 +- include/scsi/scsi_transport_iscsi.h | 19 +++- 3 files changed, 172 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index ac9d298f54e7..c3c07ccccca7 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -33,6 +33,7 @@ #define ISCSI_SESSION_ATTRS 19 #define ISCSI_CONN_ATTRS 13 #define ISCSI_HOST_ATTRS 4 + #define ISCSI_TRANSPORT_VERSION "2.0-869" struct iscsi_internal { @@ -112,6 +113,123 @@ static struct attribute_group iscsi_transport_group = { .attrs = iscsi_transport_attrs, }; +/* + * iSCSI endpoint attrs + */ +#define iscsi_dev_to_endpoint(_dev) \ + container_of(_dev, struct iscsi_endpoint, dev) + +#define ISCSI_ATTR(_prefix,_name,_mode,_show,_store) \ +struct device_attribute dev_attr_##_prefix##_##_name = \ + __ATTR(_name,_mode,_show,_store) + +static void iscsi_endpoint_release(struct device *dev) +{ + struct iscsi_endpoint *ep = iscsi_dev_to_endpoint(dev); + kfree(ep); +} + +static struct class iscsi_endpoint_class = { + .name = "iscsi_endpoint", + .dev_release = iscsi_endpoint_release, +}; + +static ssize_t +show_ep_handle(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct iscsi_endpoint *ep = iscsi_dev_to_endpoint(dev); + return sprintf(buf, "%u\n", ep->id); +} +static ISCSI_ATTR(ep, handle, S_IRUGO, show_ep_handle, NULL); + +static struct attribute *iscsi_endpoint_attrs[] = { + &dev_attr_ep_handle.attr, + NULL, +}; + +static struct attribute_group iscsi_endpoint_group = { + .attrs = iscsi_endpoint_attrs, +}; + +#define ISCSI_MAX_EPID -1 + +static int iscsi_match_epid(struct device *dev, void *data) +{ + struct iscsi_endpoint *ep = iscsi_dev_to_endpoint(dev); + unsigned int *epid = (unsigned int *) data; + + return *epid == ep->id; +} + +struct iscsi_endpoint * +iscsi_create_endpoint(int dd_size) +{ + struct device *dev; + struct iscsi_endpoint *ep; + unsigned int id; + int err; + + for (id = 1; id < ISCSI_MAX_EPID; id++) { + dev = class_find_device(&iscsi_endpoint_class, &id, + iscsi_match_epid); + if (!dev) + break; + } + if (id == ISCSI_MAX_EPID) { + printk(KERN_ERR "Too many connections. Max supported %u\n", + ISCSI_MAX_EPID - 1); + return NULL; + } + + ep = kzalloc(sizeof(*ep) + dd_size, GFP_KERNEL); + if (!ep) + return NULL; + + ep->id = id; + ep->dev.class = &iscsi_endpoint_class; + snprintf(ep->dev.bus_id, BUS_ID_SIZE, "ep-%u", id); + err = device_register(&ep->dev); + if (err) + goto free_ep; + + err = sysfs_create_group(&ep->dev.kobj, &iscsi_endpoint_group); + if (err) + goto unregister_dev; + + if (dd_size) + ep->dd_data = &ep[1]; + return ep; + +unregister_dev: + device_unregister(&ep->dev); + return NULL; + +free_ep: + kfree(ep); + return NULL; +} +EXPORT_SYMBOL_GPL(iscsi_create_endpoint); + +void iscsi_destroy_endpoint(struct iscsi_endpoint *ep) +{ + sysfs_remove_group(&ep->dev.kobj, &iscsi_endpoint_group); + device_unregister(&ep->dev); +} +EXPORT_SYMBOL_GPL(iscsi_destroy_endpoint); + +struct iscsi_endpoint *iscsi_lookup_endpoint(u64 handle) +{ + struct device *dev; + + dev = class_find_device(&iscsi_endpoint_class, &handle, + iscsi_match_epid); + if (!dev) + return NULL; + + return iscsi_dev_to_endpoint(dev); +} +EXPORT_SYMBOL_GPL(iscsi_lookup_endpoint); + static int iscsi_setup_host(struct transport_container *tc, struct device *dev, struct device *cdev) { @@ -1094,33 +1212,16 @@ int iscsi_session_event(struct iscsi_cls_session *session, EXPORT_SYMBOL_GPL(iscsi_session_event); static int -iscsi_if_create_session(struct iscsi_internal *priv, struct iscsi_uevent *ev, - uint32_t host_no, uint32_t initial_cmdsn, +iscsi_if_create_session(struct iscsi_internal *priv, struct iscsi_endpoint *ep, + struct iscsi_uevent *ev, uint32_t initial_cmdsn, uint16_t cmds_max, uint16_t queue_depth) { struct iscsi_transport *transport = priv->iscsi_transport; struct iscsi_cls_session *session; - struct Scsi_Host *shost = NULL; + uint32_t host_no; - /* - * Software iscsi allocates a host per session, but - * offload drivers (and possibly iser one day) allocate a host per - * hba/nic/rnic. Offload will match a host here, but software will - * return a new hostno after the create_session callback has returned. - */ - if (host_no != UINT_MAX) { - shost = scsi_host_lookup(host_no); - if (IS_ERR(shost)) { - printk(KERN_ERR "Could not find host no %u to " - "create session\n", host_no); - return -ENODEV; - } - } - - session = transport->create_session(shost, cmds_max, queue_depth, + session = transport->create_session(ep, cmds_max, queue_depth, initial_cmdsn, &host_no); - if (shost) - scsi_host_put(shost); if (!session) return -ENOMEM; @@ -1199,6 +1300,7 @@ static int iscsi_if_transport_ep(struct iscsi_transport *transport, struct iscsi_uevent *ev, int msg_type) { + struct iscsi_endpoint *ep; struct sockaddr *dst_addr; int rc = 0; @@ -1208,22 +1310,33 @@ iscsi_if_transport_ep(struct iscsi_transport *transport, return -EINVAL; dst_addr = (struct sockaddr *)((char*)ev + sizeof(*ev)); - rc = transport->ep_connect(dst_addr, - ev->u.ep_connect.non_blocking, - &ev->r.ep_connect_ret.handle); + ep = transport->ep_connect(dst_addr, + ev->u.ep_connect.non_blocking); + if (IS_ERR(ep)) + return PTR_ERR(ep); + + ev->r.ep_connect_ret.handle = ep->id; break; case ISCSI_UEVENT_TRANSPORT_EP_POLL: if (!transport->ep_poll) return -EINVAL; - ev->r.retcode = transport->ep_poll(ev->u.ep_poll.ep_handle, + ep = iscsi_lookup_endpoint(ev->u.ep_poll.ep_handle); + if (!ep) + return -EINVAL; + + ev->r.retcode = transport->ep_poll(ep, ev->u.ep_poll.timeout_ms); break; case ISCSI_UEVENT_TRANSPORT_EP_DISCONNECT: if (!transport->ep_disconnect) return -EINVAL; - transport->ep_disconnect(ev->u.ep_disconnect.ep_handle); + ep = iscsi_lookup_endpoint(ev->u.ep_disconnect.ep_handle); + if (!ep) + return -EINVAL; + + transport->ep_disconnect(ep); break; } return rc; @@ -1283,12 +1396,12 @@ static int iscsi_if_recv_msg(struct sk_buff *skb, struct nlmsghdr *nlh) { int err = 0; - uint32_t host_no = UINT_MAX; struct iscsi_uevent *ev = NLMSG_DATA(nlh); struct iscsi_transport *transport = NULL; struct iscsi_internal *priv; struct iscsi_cls_session *session; struct iscsi_cls_conn *conn; + struct iscsi_endpoint *ep = NULL; priv = iscsi_if_transport_lookup(iscsi_ptr(ev->transport_handle)); if (!priv) @@ -1302,14 +1415,17 @@ iscsi_if_recv_msg(struct sk_buff *skb, struct nlmsghdr *nlh) switch (nlh->nlmsg_type) { case ISCSI_UEVENT_CREATE_SESSION: - err = iscsi_if_create_session(priv, ev, host_no, + err = iscsi_if_create_session(priv, ep, ev, ev->u.c_session.initial_cmdsn, ev->u.c_session.cmds_max, ev->u.c_session.queue_depth); break; case ISCSI_UEVENT_CREATE_BOUND_SESSION: - err = iscsi_if_create_session(priv, ev, - ev->u.c_bound_session.host_no, + ep = iscsi_lookup_endpoint(ev->u.c_bound_session.ep_handle); + if (!ep) + return -EINVAL; + + err = iscsi_if_create_session(priv, ep, ev, ev->u.c_bound_session.initial_cmdsn, ev->u.c_bound_session.cmds_max, ev->u.c_bound_session.queue_depth); @@ -1774,6 +1890,7 @@ iscsi_register_transport(struct iscsi_transport *tt) unregister_dev: device_unregister(&priv->dev); + return NULL; free_priv: kfree(priv); return NULL; @@ -1821,10 +1938,14 @@ static __init int iscsi_transport_init(void) if (err) return err; - err = transport_class_register(&iscsi_host_class); + err = class_register(&iscsi_endpoint_class); if (err) goto unregister_transport_class; + err = transport_class_register(&iscsi_host_class); + if (err) + goto unregister_endpoint_class; + err = transport_class_register(&iscsi_connection_class); if (err) goto unregister_host_class; @@ -1833,8 +1954,8 @@ static __init int iscsi_transport_init(void) if (err) goto unregister_conn_class; - nls = netlink_kernel_create(&init_net, NETLINK_ISCSI, 1, iscsi_if_rx, NULL, - THIS_MODULE); + nls = netlink_kernel_create(&init_net, NETLINK_ISCSI, 1, iscsi_if_rx, + NULL, THIS_MODULE); if (!nls) { err = -ENOBUFS; goto unregister_session_class; @@ -1854,6 +1975,8 @@ unregister_conn_class: transport_class_unregister(&iscsi_connection_class); unregister_host_class: transport_class_unregister(&iscsi_host_class); +unregister_endpoint_class: + class_unregister(&iscsi_endpoint_class); unregister_transport_class: class_unregister(&iscsi_transport_class); return err; @@ -1866,6 +1989,7 @@ static void __exit iscsi_transport_exit(void) transport_class_unregister(&iscsi_connection_class); transport_class_unregister(&iscsi_session_class); transport_class_unregister(&iscsi_host_class); + class_unregister(&iscsi_endpoint_class); class_unregister(&iscsi_transport_class); } diff --git a/include/scsi/iscsi_if.h b/include/scsi/iscsi_if.h index 801a677777cc..a0f13a280e71 100644 --- a/include/scsi/iscsi_if.h +++ b/include/scsi/iscsi_if.h @@ -80,7 +80,7 @@ struct iscsi_uevent { uint16_t queue_depth; } c_session; struct msg_create_bound_session { - uint32_t host_no; + uint64_t ep_handle; uint32_t initial_cmdsn; uint16_t cmds_max; uint16_t queue_depth; diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index d6b823195563..f5444e033cc9 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -30,6 +30,7 @@ struct scsi_transport_template; struct iscsi_transport; +struct iscsi_endpoint; struct Scsi_Host; struct iscsi_cls_conn; struct iscsi_conn; @@ -85,7 +86,7 @@ struct iscsi_transport { /* LLD sets this to indicate what values it can export to sysfs */ uint64_t param_mask; uint64_t host_param_mask; - struct iscsi_cls_session *(*create_session) (struct Scsi_Host *shost, + struct iscsi_cls_session *(*create_session) (struct iscsi_endpoint *ep, uint16_t cmds_max, uint16_t qdepth, uint32_t sn, uint32_t *hn); void (*destroy_session) (struct iscsi_cls_session *session); @@ -117,10 +118,10 @@ struct iscsi_transport { void (*cleanup_task) (struct iscsi_conn *conn, struct iscsi_task *task); void (*session_recovery_timedout) (struct iscsi_cls_session *session); - int (*ep_connect) (struct sockaddr *dst_addr, int non_blocking, - uint64_t *ep_handle); - int (*ep_poll) (uint64_t ep_handle, int timeout_ms); - void (*ep_disconnect) (uint64_t ep_handle); + struct iscsi_endpoint *(*ep_connect) (struct sockaddr *dst_addr, + int non_blocking); + int (*ep_poll) (struct iscsi_endpoint *ep, int timeout_ms); + void (*ep_disconnect) (struct iscsi_endpoint *ep); int (*tgt_dscvr) (struct Scsi_Host *shost, enum iscsi_tgt_dscvr type, uint32_t enable, struct sockaddr *dst_addr); }; @@ -203,6 +204,11 @@ struct iscsi_cls_host { extern void iscsi_host_for_each_session(struct Scsi_Host *shost, void (*fn)(struct iscsi_cls_session *)); +struct iscsi_endpoint { + void *dd_data; /* LLD private data */ + struct device dev; + unsigned int id; +}; /* * session and connection functions that can be used by HW iSCSI LLDs @@ -233,5 +239,8 @@ extern int iscsi_destroy_conn(struct iscsi_cls_conn *conn); extern void iscsi_unblock_session(struct iscsi_cls_session *session); extern void iscsi_block_session(struct iscsi_cls_session *session); extern int iscsi_scan_finished(struct Scsi_Host *shost, unsigned long time); +extern struct iscsi_endpoint *iscsi_create_endpoint(int dd_size); +extern void iscsi_destroy_endpoint(struct iscsi_endpoint *ep); +extern struct iscsi_endpoint *iscsi_lookup_endpoint(u64 handle); #endif -- cgit v1.2.3 From 88dfd340b9dece8fcaa1a2d4c782338926c017f7 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:16 -0500 Subject: [SCSI] iscsi class: Add session initiatorname and ifacename sysfs attrs. This adds two new attrs used for creating initiator ports and binding sessions to hardware. The session level initiatorname: Since bnx2i does a scsi_host per host device, we need to add the iface initiator port settings on the session, so we can create multiple initiator ports (each with different inames) per device/scsi_host. The current iname reflects that qla4xxx can have one iname per hba, and we are allocating a host per session for software. The iname on the host will remain so we can export and set the hba level qla4xxx setting. The ifacename attr: To bind a session to a some peice of hardware in userspace we maintain some mappings, but during boot or iscsid restart (iscsid contains the user space part of the driver) we need to be able to figure out which of those host mappings abstractions maps to certain sessions. This patch adds a ifacename attr, which userspace can set to id the host side of the endpoint across pivot_roots and iscsid restarts. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 3 +- drivers/scsi/iscsi_tcp.c | 3 +- drivers/scsi/libiscsi.c | 20 ++++++++ drivers/scsi/scsi_transport_iscsi.c | 6 ++- include/scsi/iscsi_if.h | 79 +++++++++++++++++--------------- include/scsi/libiscsi.h | 2 + 6 files changed, 74 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index 42e95b833092..08edbaf89223 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -629,7 +629,8 @@ static struct iscsi_transport iscsi_iser_transport = { ISCSI_USERNAME | ISCSI_PASSWORD | ISCSI_USERNAME_IN | ISCSI_PASSWORD_IN | ISCSI_FAST_ABORT | ISCSI_ABORT_TMO | - ISCSI_PING_TMO | ISCSI_RECV_TMO, + ISCSI_PING_TMO | ISCSI_RECV_TMO | + ISCSI_IFACE_NAME | ISCSI_INITIATOR_NAME, .host_param_mask = ISCSI_HOST_HWADDRESS | ISCSI_HOST_NETDEV_NAME | ISCSI_HOST_INITIATOR_NAME, diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 92d031959002..7552dd8a88f3 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -1957,7 +1957,8 @@ static struct iscsi_transport iscsi_tcp_transport = { ISCSI_USERNAME_IN | ISCSI_PASSWORD_IN | ISCSI_FAST_ABORT | ISCSI_ABORT_TMO | ISCSI_LU_RESET_TMO | - ISCSI_PING_TMO | ISCSI_RECV_TMO, + ISCSI_PING_TMO | ISCSI_RECV_TMO | + ISCSI_IFACE_NAME | ISCSI_INITIATOR_NAME, .host_param_mask = ISCSI_HOST_HWADDRESS | ISCSI_HOST_IPADDRESS | ISCSI_HOST_INITIATOR_NAME | ISCSI_HOST_NETDEV_NAME, diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index e88b726ab2e0..c1af2aa8e4e0 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -1990,6 +1990,8 @@ void iscsi_session_teardown(struct iscsi_cls_session *cls_session) kfree(session->username); kfree(session->username_in); kfree(session->targetname); + kfree(session->initiatorname); + kfree(session->ifacename); iscsi_destroy_session(cls_session); module_put(owner); @@ -2453,6 +2455,14 @@ int iscsi_set_param(struct iscsi_cls_conn *cls_conn, if (!conn->persistent_address) return -ENOMEM; break; + case ISCSI_PARAM_IFACE_NAME: + if (!session->ifacename) + session->ifacename = kstrdup(buf, GFP_KERNEL); + break; + case ISCSI_PARAM_INITIATOR_NAME: + if (!session->initiatorname) + session->initiatorname = kstrdup(buf, GFP_KERNEL); + break; default: return -ENOSYS; } @@ -2519,6 +2529,15 @@ int iscsi_session_get_param(struct iscsi_cls_session *cls_session, case ISCSI_PARAM_PASSWORD_IN: len = sprintf(buf, "%s\n", session->password_in); break; + case ISCSI_PARAM_IFACE_NAME: + len = sprintf(buf, "%s\n", session->ifacename); + break; + case ISCSI_PARAM_INITIATOR_NAME: + if (!session->initiatorname) + len = sprintf(buf, "%s\n", "unknown"); + else + len = sprintf(buf, "%s\n", session->initiatorname); + break; default: return -ENOSYS; } @@ -2606,6 +2625,7 @@ int iscsi_host_get_param(struct Scsi_Host *shost, enum iscsi_host_param param, else len = sprintf(buf, "%s\n", ihost->local_address); + break; default: return -ENOSYS; } diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index c3c07ccccca7..9fd5c6d87ed1 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -30,7 +30,7 @@ #include #include -#define ISCSI_SESSION_ATTRS 19 +#define ISCSI_SESSION_ATTRS 21 #define ISCSI_CONN_ATTRS 13 #define ISCSI_HOST_ATTRS 4 @@ -1634,6 +1634,8 @@ iscsi_session_attr(password_in, ISCSI_PARAM_PASSWORD_IN, 1); iscsi_session_attr(fast_abort, ISCSI_PARAM_FAST_ABORT, 0); iscsi_session_attr(abort_tmo, ISCSI_PARAM_ABORT_TMO, 0); iscsi_session_attr(lu_reset_tmo, ISCSI_PARAM_LU_RESET_TMO, 0); +iscsi_session_attr(ifacename, ISCSI_PARAM_IFACE_NAME, 0); +iscsi_session_attr(initiatorname, ISCSI_PARAM_INITIATOR_NAME, 0) static ssize_t show_priv_session_state(struct device *dev, struct device_attribute *attr, @@ -1875,6 +1877,8 @@ iscsi_register_transport(struct iscsi_transport *tt) SETUP_SESSION_RD_ATTR(fast_abort, ISCSI_FAST_ABORT); SETUP_SESSION_RD_ATTR(abort_tmo, ISCSI_ABORT_TMO); SETUP_SESSION_RD_ATTR(lu_reset_tmo,ISCSI_LU_RESET_TMO); + SETUP_SESSION_RD_ATTR(ifacename, ISCSI_IFACE_NAME); + SETUP_SESSION_RD_ATTR(initiatorname, ISCSI_INITIATOR_NAME); SETUP_PRIV_SESSION_RD_ATTR(recovery_tmo); SETUP_PRIV_SESSION_RD_ATTR(state); diff --git a/include/scsi/iscsi_if.h b/include/scsi/iscsi_if.h index a0f13a280e71..16be12f1cbe8 100644 --- a/include/scsi/iscsi_if.h +++ b/include/scsi/iscsi_if.h @@ -257,42 +257,49 @@ enum iscsi_param { ISCSI_PARAM_PING_TMO, ISCSI_PARAM_RECV_TMO, + + ISCSI_PARAM_IFACE_NAME, + ISCSI_PARAM_ISID, + ISCSI_PARAM_INITIATOR_NAME, /* must always be last */ ISCSI_PARAM_MAX, }; -#define ISCSI_MAX_RECV_DLENGTH (1 << ISCSI_PARAM_MAX_RECV_DLENGTH) -#define ISCSI_MAX_XMIT_DLENGTH (1 << ISCSI_PARAM_MAX_XMIT_DLENGTH) -#define ISCSI_HDRDGST_EN (1 << ISCSI_PARAM_HDRDGST_EN) -#define ISCSI_DATADGST_EN (1 << ISCSI_PARAM_DATADGST_EN) -#define ISCSI_INITIAL_R2T_EN (1 << ISCSI_PARAM_INITIAL_R2T_EN) -#define ISCSI_MAX_R2T (1 << ISCSI_PARAM_MAX_R2T) -#define ISCSI_IMM_DATA_EN (1 << ISCSI_PARAM_IMM_DATA_EN) -#define ISCSI_FIRST_BURST (1 << ISCSI_PARAM_FIRST_BURST) -#define ISCSI_MAX_BURST (1 << ISCSI_PARAM_MAX_BURST) -#define ISCSI_PDU_INORDER_EN (1 << ISCSI_PARAM_PDU_INORDER_EN) -#define ISCSI_DATASEQ_INORDER_EN (1 << ISCSI_PARAM_DATASEQ_INORDER_EN) -#define ISCSI_ERL (1 << ISCSI_PARAM_ERL) -#define ISCSI_IFMARKER_EN (1 << ISCSI_PARAM_IFMARKER_EN) -#define ISCSI_OFMARKER_EN (1 << ISCSI_PARAM_OFMARKER_EN) -#define ISCSI_EXP_STATSN (1 << ISCSI_PARAM_EXP_STATSN) -#define ISCSI_TARGET_NAME (1 << ISCSI_PARAM_TARGET_NAME) -#define ISCSI_TPGT (1 << ISCSI_PARAM_TPGT) -#define ISCSI_PERSISTENT_ADDRESS (1 << ISCSI_PARAM_PERSISTENT_ADDRESS) -#define ISCSI_PERSISTENT_PORT (1 << ISCSI_PARAM_PERSISTENT_PORT) -#define ISCSI_SESS_RECOVERY_TMO (1 << ISCSI_PARAM_SESS_RECOVERY_TMO) -#define ISCSI_CONN_PORT (1 << ISCSI_PARAM_CONN_PORT) -#define ISCSI_CONN_ADDRESS (1 << ISCSI_PARAM_CONN_ADDRESS) -#define ISCSI_USERNAME (1 << ISCSI_PARAM_USERNAME) -#define ISCSI_USERNAME_IN (1 << ISCSI_PARAM_USERNAME_IN) -#define ISCSI_PASSWORD (1 << ISCSI_PARAM_PASSWORD) -#define ISCSI_PASSWORD_IN (1 << ISCSI_PARAM_PASSWORD_IN) -#define ISCSI_FAST_ABORT (1 << ISCSI_PARAM_FAST_ABORT) -#define ISCSI_ABORT_TMO (1 << ISCSI_PARAM_ABORT_TMO) -#define ISCSI_LU_RESET_TMO (1 << ISCSI_PARAM_LU_RESET_TMO) -#define ISCSI_HOST_RESET_TMO (1 << ISCSI_PARAM_HOST_RESET_TMO) -#define ISCSI_PING_TMO (1 << ISCSI_PARAM_PING_TMO) -#define ISCSI_RECV_TMO (1 << ISCSI_PARAM_RECV_TMO) +#define ISCSI_MAX_RECV_DLENGTH (1ULL << ISCSI_PARAM_MAX_RECV_DLENGTH) +#define ISCSI_MAX_XMIT_DLENGTH (1ULL << ISCSI_PARAM_MAX_XMIT_DLENGTH) +#define ISCSI_HDRDGST_EN (1ULL << ISCSI_PARAM_HDRDGST_EN) +#define ISCSI_DATADGST_EN (1ULL << ISCSI_PARAM_DATADGST_EN) +#define ISCSI_INITIAL_R2T_EN (1ULL << ISCSI_PARAM_INITIAL_R2T_EN) +#define ISCSI_MAX_R2T (1ULL << ISCSI_PARAM_MAX_R2T) +#define ISCSI_IMM_DATA_EN (1ULL << ISCSI_PARAM_IMM_DATA_EN) +#define ISCSI_FIRST_BURST (1ULL << ISCSI_PARAM_FIRST_BURST) +#define ISCSI_MAX_BURST (1ULL << ISCSI_PARAM_MAX_BURST) +#define ISCSI_PDU_INORDER_EN (1ULL << ISCSI_PARAM_PDU_INORDER_EN) +#define ISCSI_DATASEQ_INORDER_EN (1ULL << ISCSI_PARAM_DATASEQ_INORDER_EN) +#define ISCSI_ERL (1ULL << ISCSI_PARAM_ERL) +#define ISCSI_IFMARKER_EN (1ULL << ISCSI_PARAM_IFMARKER_EN) +#define ISCSI_OFMARKER_EN (1ULL << ISCSI_PARAM_OFMARKER_EN) +#define ISCSI_EXP_STATSN (1ULL << ISCSI_PARAM_EXP_STATSN) +#define ISCSI_TARGET_NAME (1ULL << ISCSI_PARAM_TARGET_NAME) +#define ISCSI_TPGT (1ULL << ISCSI_PARAM_TPGT) +#define ISCSI_PERSISTENT_ADDRESS (1ULL << ISCSI_PARAM_PERSISTENT_ADDRESS) +#define ISCSI_PERSISTENT_PORT (1ULL << ISCSI_PARAM_PERSISTENT_PORT) +#define ISCSI_SESS_RECOVERY_TMO (1ULL << ISCSI_PARAM_SESS_RECOVERY_TMO) +#define ISCSI_CONN_PORT (1ULL << ISCSI_PARAM_CONN_PORT) +#define ISCSI_CONN_ADDRESS (1ULL << ISCSI_PARAM_CONN_ADDRESS) +#define ISCSI_USERNAME (1ULL << ISCSI_PARAM_USERNAME) +#define ISCSI_USERNAME_IN (1ULL << ISCSI_PARAM_USERNAME_IN) +#define ISCSI_PASSWORD (1ULL << ISCSI_PARAM_PASSWORD) +#define ISCSI_PASSWORD_IN (1ULL << ISCSI_PARAM_PASSWORD_IN) +#define ISCSI_FAST_ABORT (1ULL << ISCSI_PARAM_FAST_ABORT) +#define ISCSI_ABORT_TMO (1ULL << ISCSI_PARAM_ABORT_TMO) +#define ISCSI_LU_RESET_TMO (1ULL << ISCSI_PARAM_LU_RESET_TMO) +#define ISCSI_HOST_RESET_TMO (1ULL << ISCSI_PARAM_HOST_RESET_TMO) +#define ISCSI_PING_TMO (1ULL << ISCSI_PARAM_PING_TMO) +#define ISCSI_RECV_TMO (1ULL << ISCSI_PARAM_RECV_TMO) +#define ISCSI_IFACE_NAME (1ULL << ISCSI_PARAM_IFACE_NAME) +#define ISCSI_ISID (1ULL << ISCSI_PARAM_ISID) +#define ISCSI_INITIATOR_NAME (1ULL << ISCSI_PARAM_INITIATOR_NAME) /* iSCSI HBA params */ enum iscsi_host_param { @@ -303,10 +310,10 @@ enum iscsi_host_param { ISCSI_HOST_PARAM_MAX, }; -#define ISCSI_HOST_HWADDRESS (1 << ISCSI_HOST_PARAM_HWADDRESS) -#define ISCSI_HOST_INITIATOR_NAME (1 << ISCSI_HOST_PARAM_INITIATOR_NAME) -#define ISCSI_HOST_NETDEV_NAME (1 << ISCSI_HOST_PARAM_NETDEV_NAME) -#define ISCSI_HOST_IPADDRESS (1 << ISCSI_HOST_PARAM_IPADDRESS) +#define ISCSI_HOST_HWADDRESS (1ULL << ISCSI_HOST_PARAM_HWADDRESS) +#define ISCSI_HOST_INITIATOR_NAME (1ULL << ISCSI_HOST_PARAM_INITIATOR_NAME) +#define ISCSI_HOST_NETDEV_NAME (1ULL << ISCSI_HOST_PARAM_NETDEV_NAME) +#define ISCSI_HOST_IPADDRESS (1ULL << ISCSI_HOST_PARAM_IPADDRESS) #define iscsi_ptr(_handle) ((void*)(unsigned long)_handle) #define iscsi_handle(_ptr) ((uint64_t)(unsigned long)_ptr) diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index 13c92d7ba969..21cfb1d5483f 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -270,6 +270,8 @@ struct iscsi_session { char *password; char *password_in; char *targetname; + char *ifacename; + char *initiatorname; /* control data */ struct iscsi_transport *tt; struct Scsi_Host *host; -- cgit v1.2.3 From 3cf7b233ffc45d4fc381221f74d24f10e692c4ea Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:17 -0500 Subject: [SCSI] libiscsi: fix cmds_max setting Drivers expect that the cmds_max value they pass to the iscsi layer is the max scsi commands + mgmt tasks. This patch implements that and fixes some checks for nr cmd limits. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/scsi/libiscsi.c | 49 ++++++++++++++++++++++++++++++++++--------------- include/scsi/libiscsi.h | 9 +++++---- 2 files changed, 39 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index c1af2aa8e4e0..c723e60f02b0 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -1893,29 +1893,48 @@ EXPORT_SYMBOL_GPL(iscsi_host_free); * * This can be used by software iscsi_transports that allocate * a session per scsi host. + * + * Callers should set cmds_max to the largest total numer (mgmt + scsi) of + * tasks they support. The iscsi layer reserves ISCSI_MGMT_CMDS_MAX tasks + * for nop handling and login/logout requests. */ struct iscsi_cls_session * iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, - uint16_t scsi_cmds_max, int cmd_task_size, + uint16_t cmds_max, int cmd_task_size, uint32_t initial_cmdsn, unsigned int id) { struct iscsi_session *session; struct iscsi_cls_session *cls_session; - int cmd_i, cmds_max; - + int cmd_i, scsi_cmds, total_cmds = cmds_max; /* - * The iscsi layer needs some tasks for nop handling and tmfs. + * The iscsi layer needs some tasks for nop handling and tmfs, + * so the cmds_max must at least be greater than ISCSI_MGMT_CMDS_MAX + * + 1 command for scsi IO. */ - if (scsi_cmds_max < 1) - scsi_cmds_max = ISCSI_MGMT_CMDS_MAX; - if ((scsi_cmds_max + ISCSI_MGMT_CMDS_MAX) >= ISCSI_MGMT_ITT_OFFSET) { - printk(KERN_ERR "iscsi: invalid can_queue of %d. " - "can_queue must be less than %d.\n", - scsi_cmds_max, - ISCSI_MGMT_ITT_OFFSET - ISCSI_MGMT_CMDS_MAX); - scsi_cmds_max = ISCSI_DEF_XMIT_CMDS_MAX; + if (total_cmds < ISCSI_TOTAL_CMDS_MIN) { + printk(KERN_ERR "iscsi: invalid can_queue of %d. can_queue " + "must be a power of two that is at least %d.\n", + total_cmds, ISCSI_TOTAL_CMDS_MIN); + return NULL; + } + + if (total_cmds > ISCSI_TOTAL_CMDS_MAX) { + printk(KERN_ERR "iscsi: invalid can_queue of %d. can_queue " + "must be a power of 2 less than or equal to %d.\n", + cmds_max, ISCSI_TOTAL_CMDS_MAX); + total_cmds = ISCSI_TOTAL_CMDS_MAX; + } + + if (!is_power_of_2(total_cmds)) { + printk(KERN_ERR "iscsi: invalid can_queue of %d. can_queue " + "must be a power of 2.\n", total_cmds); + total_cmds = rounddown_pow_of_two(total_cmds); + if (total_cmds < ISCSI_TOTAL_CMDS_MIN) + return NULL; + printk(KERN_INFO "iscsi: Rounding can_queue to %d.\n", + total_cmds); } - cmds_max = roundup_pow_of_two(scsi_cmds_max + ISCSI_MGMT_CMDS_MAX); + scsi_cmds = total_cmds - ISCSI_MGMT_CMDS_MAX; cls_session = iscsi_alloc_session(shost, iscsit, sizeof(struct iscsi_session)); @@ -1928,8 +1947,8 @@ iscsi_session_setup(struct iscsi_transport *iscsit, struct Scsi_Host *shost, session->fast_abort = 1; session->lu_reset_timeout = 15; session->abort_timeout = 10; - session->scsi_cmds_max = scsi_cmds_max; - session->cmds_max = cmds_max; + session->scsi_cmds_max = scsi_cmds; + session->cmds_max = total_cmds; session->queued_cmdsn = session->cmdsn = initial_cmdsn; session->exp_cmdsn = initial_cmdsn + 1; session->max_cmdsn = initial_cmdsn + 1; diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index 21cfb1d5483f..5bf0187e7520 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -52,9 +52,7 @@ struct device; #endif #define ISCSI_DEF_XMIT_CMDS_MAX 128 /* must be power of 2 */ -#define ISCSI_MGMT_CMDS_MAX 16 /* must be power of 2 */ - -#define ISCSI_MGMT_ITT_OFFSET 0xa00 +#define ISCSI_MGMT_CMDS_MAX 15 #define ISCSI_DEF_CMD_PER_LUN 32 #define ISCSI_MAX_CMD_PER_LUN 128 @@ -72,7 +70,10 @@ enum { /* Connection suspend "bit" */ #define ISCSI_SUSPEND_BIT 1 -#define ISCSI_ITT_MASK (0xfff) +#define ISCSI_ITT_MASK (0x1fff) +#define ISCSI_TOTAL_CMDS_MAX 4096 +/* this must be a power of two greater than ISCSI_MGMT_CMDS_MAX */ +#define ISCSI_TOTAL_CMDS_MIN 16 #define ISCSI_AGE_SHIFT 28 #define ISCSI_AGE_MASK (0xf << ISCSI_AGE_SHIFT) -- cgit v1.2.3 From 913e5bf435617aa529919a4f7567f849f9f35f9f Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Wed, 21 May 2008 15:54:18 -0500 Subject: [SCSI] libiscsi, iser, tcp: remove recv_lock The recv lock was defined so the iscsi layer could block the recv path from processing IO during recovery. It turns out iser just set a lock to that pointer which was pointless. We now disconnect the transport connection before doing recovery so we do not need the recv lock. For iscsi_tcp we still stop the recv path incase older tools are being used. This patch also has iscsi_itt_to_ctask user grab the session lock and has the caller access the task with the lock or get a ref to it in case the target is broken and sends a tmf success response then sends data or a response for the command that was supposed to be affected bty the tmf. Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 20 ++-- drivers/infiniband/ulp/iser/iscsi_iser.h | 2 - drivers/infiniband/ulp/iser/iser_initiator.c | 6 ++ drivers/scsi/iscsi_tcp.c | 73 +++++++------ drivers/scsi/libiscsi.c | 152 +++++++++++++++------------ include/scsi/libiscsi.h | 8 +- 6 files changed, 144 insertions(+), 117 deletions(-) (limited to 'include') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index 08edbaf89223..c02eabd383a1 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -281,9 +281,6 @@ iscsi_iser_conn_create(struct iscsi_cls_session *cls_session, uint32_t conn_idx) conn->max_recv_dlength = 128; iser_conn = conn->dd_data; - /* currently this is the only field which need to be initiated */ - rwlock_init(&iser_conn->lock); - conn->dd_data = iser_conn; iser_conn->iscsi_conn = conn; @@ -342,9 +339,6 @@ iscsi_iser_conn_bind(struct iscsi_cls_session *cls_session, ib_conn->iser_conn = iser_conn; iser_conn->ib_conn = ib_conn; iser_conn_get(ib_conn); - - conn->recv_lock = &iser_conn->lock; - return 0; } @@ -355,12 +349,18 @@ iscsi_iser_conn_stop(struct iscsi_cls_conn *cls_conn, int flag) struct iscsi_iser_conn *iser_conn = conn->dd_data; struct iser_conn *ib_conn = iser_conn->ib_conn; - iscsi_conn_stop(cls_conn, flag); /* - * There is no unbind event so the stop callback - * must release the ref from the bind. + * Userspace may have goofed up and not bound the connection or + * might have only partially setup the connection. */ - iser_conn_put(ib_conn); + if (ib_conn) { + iscsi_conn_stop(cls_conn, flag); + /* + * There is no unbind event so the stop callback + * must release the ref from the bind. + */ + iser_conn_put(ib_conn); + } iser_conn->ib_conn = NULL; } diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.h b/drivers/infiniband/ulp/iser/iscsi_iser.h index cdf48763b082..a547edeea969 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.h +++ b/drivers/infiniband/ulp/iser/iscsi_iser.h @@ -263,8 +263,6 @@ struct iser_conn { struct iscsi_iser_conn { struct iscsi_conn *iscsi_conn;/* ptr to iscsi conn */ struct iser_conn *ib_conn; /* iSER IB conn */ - - rwlock_t lock; }; struct iscsi_iser_task { diff --git a/drivers/infiniband/ulp/iser/iser_initiator.c b/drivers/infiniband/ulp/iser/iser_initiator.c index 35af60a23c61..c36083922134 100644 --- a/drivers/infiniband/ulp/iser/iser_initiator.c +++ b/drivers/infiniband/ulp/iser/iser_initiator.c @@ -558,7 +558,12 @@ void iser_rcv_completion(struct iser_desc *rx_desc, opcode = hdr->opcode & ISCSI_OPCODE_MASK; if (opcode == ISCSI_OP_SCSI_CMD_RSP) { + spin_lock(&conn->iscsi_conn->session->lock); task = iscsi_itt_to_ctask(conn->iscsi_conn, hdr->itt); + if (task) + __iscsi_get_task(task); + spin_unlock(&conn->iscsi_conn->session->lock); + if (!task) iser_err("itt can't be matched to task!!! " "conn %p opcode %d itt %d\n", @@ -568,6 +573,7 @@ void iser_rcv_completion(struct iser_desc *rx_desc, iser_dbg("itt %d task %p\n",hdr->itt, task); iser_task->status = ISER_TASK_STATUS_COMPLETED; iser_task_rdma_finalize(iser_task); + iscsi_put_task(task); } } iser_dto_buffs_release(dto); diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 7552dd8a88f3..91cb1fd523f0 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -741,7 +741,6 @@ static int iscsi_tcp_hdr_dissect(struct iscsi_conn *conn, struct iscsi_hdr *hdr) { int rc = 0, opcode, ahslen; - struct iscsi_session *session = conn->session; struct iscsi_tcp_conn *tcp_conn = conn->dd_data; struct iscsi_task *task; @@ -770,17 +769,17 @@ iscsi_tcp_hdr_dissect(struct iscsi_conn *conn, struct iscsi_hdr *hdr) switch(opcode) { case ISCSI_OP_SCSI_DATA_IN: + spin_lock(&conn->session->lock); task = iscsi_itt_to_ctask(conn, hdr->itt); if (!task) - return ISCSI_ERR_BAD_ITT; - if (!task->sc) - return ISCSI_ERR_NO_SCSI_CMD; + rc = ISCSI_ERR_BAD_ITT; + else + rc = iscsi_data_rsp(conn, task); + if (rc) { + spin_unlock(&conn->session->lock); + break; + } - spin_lock(&conn->session->lock); - rc = iscsi_data_rsp(conn, task); - spin_unlock(&conn->session->lock); - if (rc) - return rc; if (tcp_conn->in.datalen) { struct iscsi_tcp_task *tcp_task = task->dd_data; struct hash_desc *rx_hash = NULL; @@ -801,15 +800,19 @@ iscsi_tcp_hdr_dissect(struct iscsi_conn *conn, struct iscsi_hdr *hdr) "datalen=%d)\n", tcp_conn, tcp_task->data_offset, tcp_conn->in.datalen); - return iscsi_segment_seek_sg(&tcp_conn->in.segment, - sdb->table.sgl, - sdb->table.nents, - tcp_task->data_offset, - tcp_conn->in.datalen, - iscsi_tcp_process_data_in, - rx_hash); + rc = iscsi_segment_seek_sg(&tcp_conn->in.segment, + sdb->table.sgl, + sdb->table.nents, + tcp_task->data_offset, + tcp_conn->in.datalen, + iscsi_tcp_process_data_in, + rx_hash); + spin_unlock(&conn->session->lock); + return rc; } - /* fall through */ + rc = __iscsi_complete_pdu(conn, hdr, NULL, 0); + spin_unlock(&conn->session->lock); + break; case ISCSI_OP_SCSI_CMD_RSP: if (tcp_conn->in.datalen) { iscsi_tcp_data_recv_prep(tcp_conn); @@ -818,20 +821,17 @@ iscsi_tcp_hdr_dissect(struct iscsi_conn *conn, struct iscsi_hdr *hdr) rc = iscsi_complete_pdu(conn, hdr, NULL, 0); break; case ISCSI_OP_R2T: + spin_lock(&conn->session->lock); task = iscsi_itt_to_ctask(conn, hdr->itt); if (!task) - return ISCSI_ERR_BAD_ITT; - if (!task->sc) - return ISCSI_ERR_NO_SCSI_CMD; - - if (ahslen) + rc = ISCSI_ERR_BAD_ITT; + else if (ahslen) rc = ISCSI_ERR_AHSLEN; - else if (task->sc->sc_data_direction == DMA_TO_DEVICE) { - spin_lock(&session->lock); + else if (task->sc->sc_data_direction == DMA_TO_DEVICE) rc = iscsi_r2t_rsp(conn, task); - spin_unlock(&session->lock); - } else + else rc = ISCSI_ERR_PROTO; + spin_unlock(&conn->session->lock); break; case ISCSI_OP_LOGIN_RSP: case ISCSI_OP_TEXT_RSP: @@ -1553,7 +1553,6 @@ iscsi_tcp_release_conn(struct iscsi_conn *conn) spin_lock_bh(&session->lock); tcp_conn->sock = NULL; - conn->recv_lock = NULL; spin_unlock_bh(&session->lock); sockfd_put(sock); } @@ -1578,6 +1577,19 @@ static void iscsi_tcp_conn_stop(struct iscsi_cls_conn *cls_conn, int flag) { struct iscsi_conn *conn = cls_conn->dd_data; + struct iscsi_tcp_conn *tcp_conn = conn->dd_data; + + /* userspace may have goofed up and not bound us */ + if (!tcp_conn->sock) + return; + /* + * Make sure our recv side is stopped. + * Older tools called conn stop before ep_disconnect + * so IO could still be coming in. + */ + write_lock_bh(&tcp_conn->sock->sk->sk_callback_lock); + set_bit(ISCSI_SUSPEND_BIT, &conn->suspend_rx); + write_unlock_bh(&tcp_conn->sock->sk->sk_callback_lock); iscsi_conn_stop(cls_conn, flag); iscsi_tcp_release_conn(conn); @@ -1671,13 +1683,6 @@ iscsi_tcp_conn_bind(struct iscsi_cls_session *cls_session, sk->sk_sndtimeo = 15 * HZ; /* FIXME: make it configurable */ sk->sk_allocation = GFP_ATOMIC; - /* FIXME: disable Nagle's algorithm */ - - /* - * Intercept TCP callbacks for sendfile like receive - * processing. - */ - conn->recv_lock = &sk->sk_callback_lock; iscsi_conn_set_callbacks(conn); tcp_conn->sendpage = tcp_conn->sock->ops->sendpage; /* diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index c723e60f02b0..9c267b440444 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -362,10 +362,11 @@ static void iscsi_complete_command(struct iscsi_task *task) } } -static void __iscsi_get_task(struct iscsi_task *task) +void __iscsi_get_task(struct iscsi_task *task) { atomic_inc(&task->refcount); } +EXPORT_SYMBOL_GPL(__iscsi_get_task); static void __iscsi_put_task(struct iscsi_task *task) { @@ -403,9 +404,13 @@ static void fail_command(struct iscsi_conn *conn, struct iscsi_task *task, conn->session->queued_cmdsn--; else conn->session->tt->cleanup_task(conn, task); + /* + * Check if cleanup_task dropped the lock and the command completed, + */ + if (!task->sc) + return; sc->result = err; - if (!scsi_bidi_cmnd(sc)) scsi_set_resid(sc, scsi_bufflen(sc)); else { @@ -696,6 +701,31 @@ static int iscsi_handle_reject(struct iscsi_conn *conn, struct iscsi_hdr *hdr, return 0; } +/** + * iscsi_itt_to_task - look up task by itt + * @conn: iscsi connection + * @itt: itt + * + * This should be used for mgmt tasks like login and nops, or if + * the LDD's itt space does not include the session age. + * + * The session lock must be held. + */ +static struct iscsi_task *iscsi_itt_to_task(struct iscsi_conn *conn, itt_t itt) +{ + struct iscsi_session *session = conn->session; + uint32_t i; + + if (itt == RESERVED_ITT) + return NULL; + + i = get_itt(itt); + if (i >= session->cmds_max) + return NULL; + + return session->cmds[i]; +} + /** * __iscsi_complete_pdu - complete pdu * @conn: iscsi conn @@ -707,8 +737,8 @@ static int iscsi_handle_reject(struct iscsi_conn *conn, struct iscsi_hdr *hdr, * queuecommand or send generic. session lock must be held and verify * itt must have been called. */ -static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, - char *data, int datalen) +int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, + char *data, int datalen) { struct iscsi_session *session = conn->session; int opcode = hdr->opcode & ISCSI_OPCODE_MASK, rc = 0; @@ -758,22 +788,36 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, goto out; } - task = session->cmds[itt]; switch(opcode) { case ISCSI_OP_SCSI_CMD_RSP: - if (!task->sc) { - rc = ISCSI_ERR_NO_SCSI_CMD; - break; - } - BUG_ON((void*)task != task->sc->SCp.ptr); + case ISCSI_OP_SCSI_DATA_IN: + task = iscsi_itt_to_ctask(conn, hdr->itt); + if (!task) + return ISCSI_ERR_BAD_ITT; + break; + case ISCSI_OP_R2T: + /* + * LLD handles R2Ts if they need to. + */ + return 0; + case ISCSI_OP_LOGOUT_RSP: + case ISCSI_OP_LOGIN_RSP: + case ISCSI_OP_TEXT_RSP: + case ISCSI_OP_SCSI_TMFUNC_RSP: + case ISCSI_OP_NOOP_IN: + task = iscsi_itt_to_task(conn, hdr->itt); + if (!task) + return ISCSI_ERR_BAD_ITT; + break; + default: + return ISCSI_ERR_BAD_OPCODE; + } + + switch(opcode) { + case ISCSI_OP_SCSI_CMD_RSP: iscsi_scsi_cmd_rsp(conn, hdr, task, data, datalen); break; case ISCSI_OP_SCSI_DATA_IN: - if (!task->sc) { - rc = ISCSI_ERR_NO_SCSI_CMD; - break; - } - BUG_ON((void*)task != task->sc->SCp.ptr); if (hdr->flags & ISCSI_FLAG_DATA_STATUS) { conn->scsirsp_pdus_cnt++; iscsi_update_cmdsn(session, @@ -781,9 +825,6 @@ static int __iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, __iscsi_put_task(task); } break; - case ISCSI_OP_R2T: - /* LLD handles this for now */ - break; case ISCSI_OP_LOGOUT_RSP: iscsi_update_cmdsn(session, (struct iscsi_nopin*)hdr); if (datalen) { @@ -841,6 +882,7 @@ recv_pdu: __iscsi_put_task(task); return rc; } +EXPORT_SYMBOL_GPL(__iscsi_complete_pdu); int iscsi_complete_pdu(struct iscsi_conn *conn, struct iscsi_hdr *hdr, char *data, int datalen) @@ -857,7 +899,6 @@ EXPORT_SYMBOL_GPL(iscsi_complete_pdu); int iscsi_verify_itt(struct iscsi_conn *conn, itt_t itt) { struct iscsi_session *session = conn->session; - struct iscsi_task *task; uint32_t i; if (itt == RESERVED_ITT) @@ -867,8 +908,7 @@ int iscsi_verify_itt(struct iscsi_conn *conn, itt_t itt) (session->age << ISCSI_AGE_SHIFT)) { iscsi_conn_printk(KERN_ERR, conn, "received itt %x expected session age (%x)\n", - (__force u32)itt, - session->age & ISCSI_AGE_MASK); + (__force u32)itt, session->age); return ISCSI_ERR_BAD_ITT; } @@ -879,42 +919,36 @@ int iscsi_verify_itt(struct iscsi_conn *conn, itt_t itt) "%u.\n", i, session->cmds_max); return ISCSI_ERR_BAD_ITT; } - - task = session->cmds[i]; - if (task->sc && task->sc->SCp.phase != session->age) { - iscsi_conn_printk(KERN_ERR, conn, - "iscsi: task's session age %d, " - "expected %d\n", task->sc->SCp.phase, - session->age); - return ISCSI_ERR_SESSION_FAILED; - } return 0; } EXPORT_SYMBOL_GPL(iscsi_verify_itt); -struct iscsi_task * -iscsi_itt_to_ctask(struct iscsi_conn *conn, itt_t itt) +/** + * iscsi_itt_to_ctask - look up ctask by itt + * @conn: iscsi connection + * @itt: itt + * + * This should be used for cmd tasks. + * + * The session lock must be held. + */ +struct iscsi_task *iscsi_itt_to_ctask(struct iscsi_conn *conn, itt_t itt) { - struct iscsi_session *session = conn->session; struct iscsi_task *task; - uint32_t i; if (iscsi_verify_itt(conn, itt)) return NULL; - if (itt == RESERVED_ITT) + task = iscsi_itt_to_task(conn, itt); + if (!task || !task->sc) return NULL; - i = get_itt(itt); - if (i >= session->cmds_max) - return NULL; - - task = session->cmds[i]; - if (!task->sc) - return NULL; - - if (task->sc->SCp.phase != session->age) + if (task->sc->SCp.phase != conn->session->age) { + iscsi_session_printk(KERN_ERR, conn->session, + "task's session age %d, expected %d\n", + task->sc->SCp.phase, conn->session->age); return NULL; + } return task; } @@ -1620,16 +1654,20 @@ int iscsi_eh_abort(struct scsi_cmnd *sc) switch (conn->tmf_state) { case TMF_SUCCESS: spin_unlock_bh(&session->lock); + /* + * stop tx side incase the target had sent a abort rsp but + * the initiator was still writing out data. + */ iscsi_suspend_tx(conn); /* - * clean up task if aborted. grab the recv lock as a writer + * we do not stop the recv side because targets have been + * good and have never sent us a successful tmf response + * then sent more data for the cmd. */ - write_lock_bh(conn->recv_lock); spin_lock(&session->lock); fail_command(conn, task, DID_ABORT << 16); conn->tmf_state = TMF_INITIAL; spin_unlock(&session->lock); - write_unlock_bh(conn->recv_lock); iscsi_start_tx(conn); goto success_unlocked; case TMF_TIMEDOUT: @@ -1729,13 +1767,11 @@ int iscsi_eh_device_reset(struct scsi_cmnd *sc) spin_unlock_bh(&session->lock); iscsi_suspend_tx(conn); - /* need to grab the recv lock then session lock */ - write_lock_bh(conn->recv_lock); + spin_lock(&session->lock); fail_all_commands(conn, sc->device->lun, DID_ERROR); conn->tmf_state = TMF_INITIAL; spin_unlock(&session->lock); - write_unlock_bh(conn->recv_lock); iscsi_start_tx(conn); goto done; @@ -2256,17 +2292,6 @@ static void iscsi_start_session_recovery(struct iscsi_session *session, return; } - /* - * The LLD either freed/unset the lock on us, or userspace called - * stop but did not create a proper connection (connection was never - * bound or it was unbound then stop was called). - */ - if (!conn->recv_lock) { - spin_unlock_bh(&session->lock); - mutex_unlock(&session->eh_mutex); - return; - } - /* * When this is called for the in_login state, we only want to clean * up the login task and connection. We do not need to block and set @@ -2283,11 +2308,6 @@ static void iscsi_start_session_recovery(struct iscsi_session *session, spin_unlock_bh(&session->lock); iscsi_suspend_tx(conn); - - write_lock_bh(conn->recv_lock); - set_bit(ISCSI_SUSPEND_BIT, &conn->suspend_rx); - write_unlock_bh(conn->recv_lock); - /* * for connection level recovery we should not calculate * header digest. conn->hdr_size used for optimization diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index 5bf0187e7520..5e75bb7f311c 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -138,11 +138,6 @@ struct iscsi_conn { struct iscsi_cls_conn *cls_conn; /* ptr to class connection */ void *dd_data; /* iscsi_transport data */ struct iscsi_session *session; /* parent session */ - /* - * LLDs should set this lock. It protects the transport recv - * code - */ - rwlock_t *recv_lock; /* * conn_stop() flag: stop to recover, stop to terminate */ @@ -374,10 +369,13 @@ extern int iscsi_conn_send_pdu(struct iscsi_cls_conn *, struct iscsi_hdr *, char *, uint32_t); extern int iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *, char *, int); +extern int __iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *, + char *, int); extern int iscsi_verify_itt(struct iscsi_conn *, itt_t); extern struct iscsi_task *iscsi_itt_to_ctask(struct iscsi_conn *, itt_t); extern void iscsi_requeue_task(struct iscsi_task *task); extern void iscsi_put_task(struct iscsi_task *task); +extern void __iscsi_get_task(struct iscsi_task *task); /* * generic helpers -- cgit v1.2.3 From 30e9ba9f2001f45960507f1963551311a67d0209 Mon Sep 17 00:00:00 2001 From: Boaz Harrosh Date: Mon, 26 May 2008 11:31:19 +0300 Subject: [SCSI] iscsi_tcp: Enable any size command Let through upto the largest command of 260 defined by the scsi standard. iscsi core supports this already. Now that the scsi-ml supports it we can start using large commands. [jejb:rejections fixed up] Signed-off-by: Boaz Harrosh Acked-by: Mike Christie Signed-off-by: James Bottomley --- drivers/scsi/iscsi_tcp.c | 2 +- include/scsi/iscsi_proto.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 7c4ee39a1c43..0bd8b3dc3c19 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -1864,7 +1864,7 @@ iscsi_tcp_session_create(struct iscsi_endpoint *ep, uint16_t cmds_max, shost->max_lun = iscsi_max_lun; shost->max_id = 0; shost->max_channel = 0; - shost->max_cmd_len = 16; + shost->max_cmd_len = SCSI_MAX_VARLEN_CDB_SIZE; shost->can_queue = cmds_max; if (iscsi_host_add(shost, NULL)) diff --git a/include/scsi/iscsi_proto.h b/include/scsi/iscsi_proto.h index e0593bfae622..f2a2c1169486 100644 --- a/include/scsi/iscsi_proto.h +++ b/include/scsi/iscsi_proto.h @@ -22,6 +22,7 @@ #define ISCSI_PROTO_H #include +#include #define ISCSI_DRAFT20_VERSION 0x00 @@ -156,7 +157,7 @@ struct iscsi_ecdb_ahdr { uint8_t ahstype; uint8_t reserved; /* 4-byte aligned extended CDB spillover */ - uint8_t ecdb[260 - ISCSI_CDB_SIZE]; + uint8_t ecdb[SCSI_MAX_VARLEN_CDB_SIZE - ISCSI_CDB_SIZE]; }; /* SCSI Response Header */ -- cgit v1.2.3 From aa91696e56a0870db5754610e9f9b937e77507e0 Mon Sep 17 00:00:00 2001 From: "Martin K. Petersen" Date: Tue, 17 Jun 2008 12:47:32 -0400 Subject: [SCSI] sd: Move sd.h header file Christoph objected to having sd.h in include/scsi since it is internal to the sd driver. Move it to drivers/scsi/sd.h. Signed-off-by: Martin K. Petersen Signed-off-by: James Bottomley --- drivers/scsi/sd.c | 2 +- drivers/scsi/sd.h | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/scsi/sd.h | 57 ------------------------------------------------------- 3 files changed, 58 insertions(+), 58 deletions(-) create mode 100644 drivers/scsi/sd.h delete mode 100644 include/scsi/sd.h (limited to 'include') diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c index 01cefbb2d539..e19691f880b9 100644 --- a/drivers/scsi/sd.c +++ b/drivers/scsi/sd.c @@ -58,8 +58,8 @@ #include #include #include -#include +#include "sd.h" #include "scsi_logging.h" MODULE_AUTHOR("Eric Youngdale"); diff --git a/drivers/scsi/sd.h b/drivers/scsi/sd.h new file mode 100644 index 000000000000..4f032d48cb6e --- /dev/null +++ b/drivers/scsi/sd.h @@ -0,0 +1,57 @@ +#ifndef _SCSI_DISK_H +#define _SCSI_DISK_H + +/* + * More than enough for everybody ;) The huge number of majors + * is a leftover from 16bit dev_t days, we don't really need that + * much numberspace. + */ +#define SD_MAJORS 16 + +/* + * This is limited by the naming scheme enforced in sd_probe, + * add another character to it if you really need more disks. + */ +#define SD_MAX_DISKS (((26 * 26) + 26 + 1) * 26) + +/* + * Time out in seconds for disks and Magneto-opticals (which are slower). + */ +#define SD_TIMEOUT (30 * HZ) +#define SD_MOD_TIMEOUT (75 * HZ) + +/* + * Number of allowed retries + */ +#define SD_MAX_RETRIES 5 +#define SD_PASSTHROUGH_RETRIES 1 + +/* + * Size of the initial data buffer for mode and read capacity data + */ +#define SD_BUF_SIZE 512 + +struct scsi_disk { + struct scsi_driver *driver; /* always &sd_template */ + struct scsi_device *device; + struct device dev; + struct gendisk *disk; + unsigned int openers; /* protected by BKL for now, yuck */ + sector_t capacity; /* size in 512-byte sectors */ + u32 index; + u8 media_present; + u8 write_prot; + unsigned previous_state : 1; + unsigned WCE : 1; /* state of disk WCE bit */ + unsigned RCD : 1; /* state of disk RCD bit, unused */ + unsigned DPOFUA : 1; /* state of disk DPOFUA bit */ +}; +#define to_scsi_disk(obj) container_of(obj,struct scsi_disk,dev) + +#define sd_printk(prefix, sdsk, fmt, a...) \ + (sdsk)->disk ? \ + sdev_printk(prefix, (sdsk)->device, "[%s] " fmt, \ + (sdsk)->disk->disk_name, ##a) : \ + sdev_printk(prefix, (sdsk)->device, fmt, ##a) + +#endif /* _SCSI_DISK_H */ diff --git a/include/scsi/sd.h b/include/scsi/sd.h deleted file mode 100644 index 4f032d48cb6e..000000000000 --- a/include/scsi/sd.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef _SCSI_DISK_H -#define _SCSI_DISK_H - -/* - * More than enough for everybody ;) The huge number of majors - * is a leftover from 16bit dev_t days, we don't really need that - * much numberspace. - */ -#define SD_MAJORS 16 - -/* - * This is limited by the naming scheme enforced in sd_probe, - * add another character to it if you really need more disks. - */ -#define SD_MAX_DISKS (((26 * 26) + 26 + 1) * 26) - -/* - * Time out in seconds for disks and Magneto-opticals (which are slower). - */ -#define SD_TIMEOUT (30 * HZ) -#define SD_MOD_TIMEOUT (75 * HZ) - -/* - * Number of allowed retries - */ -#define SD_MAX_RETRIES 5 -#define SD_PASSTHROUGH_RETRIES 1 - -/* - * Size of the initial data buffer for mode and read capacity data - */ -#define SD_BUF_SIZE 512 - -struct scsi_disk { - struct scsi_driver *driver; /* always &sd_template */ - struct scsi_device *device; - struct device dev; - struct gendisk *disk; - unsigned int openers; /* protected by BKL for now, yuck */ - sector_t capacity; /* size in 512-byte sectors */ - u32 index; - u8 media_present; - u8 write_prot; - unsigned previous_state : 1; - unsigned WCE : 1; /* state of disk WCE bit */ - unsigned RCD : 1; /* state of disk RCD bit, unused */ - unsigned DPOFUA : 1; /* state of disk DPOFUA bit */ -}; -#define to_scsi_disk(obj) container_of(obj,struct scsi_disk,dev) - -#define sd_printk(prefix, sdsk, fmt, a...) \ - (sdsk)->disk ? \ - sdev_printk(prefix, (sdsk)->device, "[%s] " fmt, \ - (sdsk)->disk->disk_name, ##a) : \ - sdev_printk(prefix, (sdsk)->device, fmt, ##a) - -#endif /* _SCSI_DISK_H */ -- cgit v1.2.3 From f11f594edba7f689af9792a5673ed59d660ad371 Mon Sep 17 00:00:00 2001 From: "Martin K. Petersen" Date: Wed, 25 Jun 2008 11:22:42 -0400 Subject: [SCSI] lib: Add support for the T10 (SCSI) Data Integrity Field CRC The SCSI Block Protocol uses this 16-bit CRC to verify the integrity of each data sector. crc_t10dif() is used by sd_dif.c when performing I/O to or from disks formatted with protection information. Signed-off-by: Martin K. Petersen Signed-off-by: James Bottomley --- include/linux/crc-t10dif.h | 8 ++++++ lib/Kconfig | 7 +++++ lib/Makefile | 1 + lib/crc-t10dif.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 83 insertions(+) create mode 100644 include/linux/crc-t10dif.h create mode 100644 lib/crc-t10dif.c (limited to 'include') diff --git a/include/linux/crc-t10dif.h b/include/linux/crc-t10dif.h new file mode 100644 index 000000000000..a9c96d865ee7 --- /dev/null +++ b/include/linux/crc-t10dif.h @@ -0,0 +1,8 @@ +#ifndef _LINUX_CRC_T10DIF_H +#define _LINUX_CRC_T10DIF_H + +#include + +__u16 crc_t10dif(unsigned char const *, size_t); + +#endif diff --git a/lib/Kconfig b/lib/Kconfig index 8cc8e8722a3f..c7ad7a5b3535 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -29,6 +29,13 @@ config CRC16 the kernel tree does. Such modules that use library CRC16 functions require M here. +config CRC_T10DIF + tristate "CRC calculation for the T10 Data Integrity Field" + help + This option is only needed if a module that's not in the + kernel tree needs to calculate CRC checks for use with the + SCSI data integrity subsystem. + config CRC_ITU_T tristate "CRC ITU-T V.41 functions" help diff --git a/lib/Makefile b/lib/Makefile index 74b0cfb1fcc3..237a8298f8cb 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -45,6 +45,7 @@ endif obj-$(CONFIG_BITREVERSE) += bitrev.o obj-$(CONFIG_CRC_CCITT) += crc-ccitt.o obj-$(CONFIG_CRC16) += crc16.o +obj-$(CONFIG_CRC_T10DIF)+= crc-t10dif.o obj-$(CONFIG_CRC_ITU_T) += crc-itu-t.o obj-$(CONFIG_CRC32) += crc32.o obj-$(CONFIG_CRC7) += crc7.o diff --git a/lib/crc-t10dif.c b/lib/crc-t10dif.c new file mode 100644 index 000000000000..fbbd66ed86cd --- /dev/null +++ b/lib/crc-t10dif.c @@ -0,0 +1,67 @@ +/* + * T10 Data Integrity Field CRC16 calculation + * + * Copyright (c) 2007 Oracle Corporation. All rights reserved. + * Written by Martin K. Petersen + * + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ + +#include +#include +#include + +/* Table generated using the following polynomium: + * x^16 + x^15 + x^11 + x^9 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 + * gt: 0x8bb7 + */ +static const __u16 t10_dif_crc_table[256] = { + 0x0000, 0x8BB7, 0x9CD9, 0x176E, 0xB205, 0x39B2, 0x2EDC, 0xA56B, + 0xEFBD, 0x640A, 0x7364, 0xF8D3, 0x5DB8, 0xD60F, 0xC161, 0x4AD6, + 0x54CD, 0xDF7A, 0xC814, 0x43A3, 0xE6C8, 0x6D7F, 0x7A11, 0xF1A6, + 0xBB70, 0x30C7, 0x27A9, 0xAC1E, 0x0975, 0x82C2, 0x95AC, 0x1E1B, + 0xA99A, 0x222D, 0x3543, 0xBEF4, 0x1B9F, 0x9028, 0x8746, 0x0CF1, + 0x4627, 0xCD90, 0xDAFE, 0x5149, 0xF422, 0x7F95, 0x68FB, 0xE34C, + 0xFD57, 0x76E0, 0x618E, 0xEA39, 0x4F52, 0xC4E5, 0xD38B, 0x583C, + 0x12EA, 0x995D, 0x8E33, 0x0584, 0xA0EF, 0x2B58, 0x3C36, 0xB781, + 0xD883, 0x5334, 0x445A, 0xCFED, 0x6A86, 0xE131, 0xF65F, 0x7DE8, + 0x373E, 0xBC89, 0xABE7, 0x2050, 0x853B, 0x0E8C, 0x19E2, 0x9255, + 0x8C4E, 0x07F9, 0x1097, 0x9B20, 0x3E4B, 0xB5FC, 0xA292, 0x2925, + 0x63F3, 0xE844, 0xFF2A, 0x749D, 0xD1F6, 0x5A41, 0x4D2F, 0xC698, + 0x7119, 0xFAAE, 0xEDC0, 0x6677, 0xC31C, 0x48AB, 0x5FC5, 0xD472, + 0x9EA4, 0x1513, 0x027D, 0x89CA, 0x2CA1, 0xA716, 0xB078, 0x3BCF, + 0x25D4, 0xAE63, 0xB90D, 0x32BA, 0x97D1, 0x1C66, 0x0B08, 0x80BF, + 0xCA69, 0x41DE, 0x56B0, 0xDD07, 0x786C, 0xF3DB, 0xE4B5, 0x6F02, + 0x3AB1, 0xB106, 0xA668, 0x2DDF, 0x88B4, 0x0303, 0x146D, 0x9FDA, + 0xD50C, 0x5EBB, 0x49D5, 0xC262, 0x6709, 0xECBE, 0xFBD0, 0x7067, + 0x6E7C, 0xE5CB, 0xF2A5, 0x7912, 0xDC79, 0x57CE, 0x40A0, 0xCB17, + 0x81C1, 0x0A76, 0x1D18, 0x96AF, 0x33C4, 0xB873, 0xAF1D, 0x24AA, + 0x932B, 0x189C, 0x0FF2, 0x8445, 0x212E, 0xAA99, 0xBDF7, 0x3640, + 0x7C96, 0xF721, 0xE04F, 0x6BF8, 0xCE93, 0x4524, 0x524A, 0xD9FD, + 0xC7E6, 0x4C51, 0x5B3F, 0xD088, 0x75E3, 0xFE54, 0xE93A, 0x628D, + 0x285B, 0xA3EC, 0xB482, 0x3F35, 0x9A5E, 0x11E9, 0x0687, 0x8D30, + 0xE232, 0x6985, 0x7EEB, 0xF55C, 0x5037, 0xDB80, 0xCCEE, 0x4759, + 0x0D8F, 0x8638, 0x9156, 0x1AE1, 0xBF8A, 0x343D, 0x2353, 0xA8E4, + 0xB6FF, 0x3D48, 0x2A26, 0xA191, 0x04FA, 0x8F4D, 0x9823, 0x1394, + 0x5942, 0xD2F5, 0xC59B, 0x4E2C, 0xEB47, 0x60F0, 0x779E, 0xFC29, + 0x4BA8, 0xC01F, 0xD771, 0x5CC6, 0xF9AD, 0x721A, 0x6574, 0xEEC3, + 0xA415, 0x2FA2, 0x38CC, 0xB37B, 0x1610, 0x9DA7, 0x8AC9, 0x017E, + 0x1F65, 0x94D2, 0x83BC, 0x080B, 0xAD60, 0x26D7, 0x31B9, 0xBA0E, + 0xF0D8, 0x7B6F, 0x6C01, 0xE7B6, 0x42DD, 0xC96A, 0xDE04, 0x55B3 +}; + +__u16 crc_t10dif(const unsigned char *buffer, size_t len) +{ + __u16 crc = 0; + unsigned int i; + + for (i = 0 ; i < len ; i++) + crc = (crc << 8) ^ t10_dif_crc_table[((crc >> 8) ^ buffer[i]) & 0xff]; + + return crc; +} +EXPORT_SYMBOL(crc_t10dif); + +MODULE_DESCRIPTION("T10 DIF CRC calculation"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 39120e11705782c77d3a47d7d2927676fd8e3aaa Mon Sep 17 00:00:00 2001 From: Brian King Date: Tue, 1 Jul 2008 13:03:19 -0500 Subject: [SCSI] sg: Add target reset support Adds support for target reset to SG_SCSI_RESET. Signed-off-by: Brian King Acked-by: Douglas Gilbert Signed-off-by: James Bottomley --- drivers/scsi/sg.c | 3 +++ include/scsi/sg.h | 1 + 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c index ea0edd1b2e76..2010fa039cfe 100644 --- a/drivers/scsi/sg.c +++ b/drivers/scsi/sg.c @@ -1026,6 +1026,9 @@ sg_ioctl(struct inode *inode, struct file *filp, case SG_SCSI_RESET_DEVICE: val = SCSI_TRY_RESET_DEVICE; break; + case SG_SCSI_RESET_TARGET: + val = SCSI_TRY_RESET_TARGET; + break; case SG_SCSI_RESET_BUS: val = SCSI_TRY_RESET_BUS; break; diff --git a/include/scsi/sg.h b/include/scsi/sg.h index 519c49a0fc11..934ae389671d 100644 --- a/include/scsi/sg.h +++ b/include/scsi/sg.h @@ -206,6 +206,7 @@ typedef struct sg_req_info { /* used by SG_GET_REQUEST_TABLE ioctl() */ #define SG_SCSI_RESET_DEVICE 1 #define SG_SCSI_RESET_BUS 2 #define SG_SCSI_RESET_HOST 3 +#define SG_SCSI_RESET_TARGET 4 /* synchronous SCSI command ioctl, (only in version 3 interface) */ #define SG_IO 0x2285 /* similar effect as write() followed by read() */ -- cgit v1.2.3 From feac6a07c4a3578bffd6769bb4927e8a7e1f3ffe Mon Sep 17 00:00:00 2001 From: Martin Petermann Date: Wed, 2 Jul 2008 10:56:35 +0200 Subject: [SCSI] zfcp: Move status accessors from zfcp to SCSI include file. Move the accessor functions for the scsi_cmnd status from zfcp to the SCSI include file. Change the interface to the functions to pass the scsi_cmnd pointer instead of the status pointer. Signed-off-by: Martin Petermann Signed-off-by: Christof Schmitt Signed-off-by: James Bottomley --- drivers/s390/scsi/zfcp_ext.h | 2 -- drivers/s390/scsi/zfcp_fsf.c | 20 ++++++++++---------- drivers/s390/scsi/zfcp_scsi.c | 24 +----------------------- include/scsi/scsi.h | 17 +++++++++++++++++ 4 files changed, 28 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/drivers/s390/scsi/zfcp_ext.h b/drivers/s390/scsi/zfcp_ext.h index 368b304d1e3f..f95dc99339fd 100644 --- a/drivers/s390/scsi/zfcp_ext.h +++ b/drivers/s390/scsi/zfcp_ext.h @@ -103,8 +103,6 @@ extern int zfcp_adapter_scsi_register(struct zfcp_adapter *); extern void zfcp_adapter_scsi_unregister(struct zfcp_adapter *); extern void zfcp_set_fcp_dl(struct fcp_cmnd_iu *, fcp_dl_t); extern char *zfcp_get_fcp_rsp_info_ptr(struct fcp_rsp_iu *); -extern void set_host_byte(int *, char); -extern void set_driver_byte(int *, char); extern char *zfcp_get_fcp_sns_info_ptr(struct fcp_rsp_iu *); extern fcp_dl_t zfcp_get_fcp_dl(struct fcp_cmnd_iu *); diff --git a/drivers/s390/scsi/zfcp_fsf.c b/drivers/s390/scsi/zfcp_fsf.c index 243e792f2407..150e78dd00b2 100644 --- a/drivers/s390/scsi/zfcp_fsf.c +++ b/drivers/s390/scsi/zfcp_fsf.c @@ -3040,18 +3040,18 @@ zfcp_fsf_send_fcp_command_task_handler(struct zfcp_fsf_req *fsf_req) * DID_SOFT_ERROR by retrying the request for devices * that allow retries. */ - set_host_byte(&scpnt->result, DID_SOFT_ERROR); - set_driver_byte(&scpnt->result, SUGGEST_RETRY); + set_host_byte(scpnt, DID_SOFT_ERROR); + set_driver_byte(scpnt, SUGGEST_RETRY); goto skip_fsfstatus; } if (unlikely(fsf_req->status & ZFCP_STATUS_FSFREQ_ERROR)) { - set_host_byte(&scpnt->result, DID_ERROR); + set_host_byte(scpnt, DID_ERROR); goto skip_fsfstatus; } /* set message byte of result in SCSI command */ - scpnt->result |= COMMAND_COMPLETE << 8; + set_msg_byte(scpnt, COMMAND_COMPLETE); /* * copy SCSI status code of FCP_STATUS of FCP_RSP IU to status byte @@ -3067,23 +3067,23 @@ zfcp_fsf_send_fcp_command_task_handler(struct zfcp_fsf_req *fsf_req) switch (fcp_rsp_info[3]) { case RSP_CODE_GOOD: /* ok, continue */ - set_host_byte(&scpnt->result, DID_OK); + set_host_byte(scpnt, DID_OK); break; case RSP_CODE_LENGTH_MISMATCH: /* hardware bug */ - set_host_byte(&scpnt->result, DID_ERROR); + set_host_byte(scpnt, DID_ERROR); goto skip_fsfstatus; case RSP_CODE_FIELD_INVALID: /* driver or hardware bug */ - set_host_byte(&scpnt->result, DID_ERROR); + set_host_byte(scpnt, DID_ERROR); goto skip_fsfstatus; case RSP_CODE_RO_MISMATCH: /* hardware bug */ - set_host_byte(&scpnt->result, DID_ERROR); + set_host_byte(scpnt, DID_ERROR); goto skip_fsfstatus; default: /* invalid FCP response code */ - set_host_byte(&scpnt->result, DID_ERROR); + set_host_byte(scpnt, DID_ERROR); goto skip_fsfstatus; } } @@ -3104,7 +3104,7 @@ zfcp_fsf_send_fcp_command_task_handler(struct zfcp_fsf_req *fsf_req) scsi_set_resid(scpnt, fcp_rsp_iu->fcp_resid); if (scsi_bufflen(scpnt) - scsi_get_resid(scpnt) < scpnt->underflow) - set_host_byte(&scpnt->result, DID_ERROR); + set_host_byte(scpnt, DID_ERROR); } skip_fsfstatus: diff --git a/drivers/s390/scsi/zfcp_scsi.c b/drivers/s390/scsi/zfcp_scsi.c index 446fb1da25df..160307382d2c 100644 --- a/drivers/s390/scsi/zfcp_scsi.c +++ b/drivers/s390/scsi/zfcp_scsi.c @@ -107,28 +107,6 @@ zfcp_set_fcp_dl(struct fcp_cmnd_iu *fcp_cmd, fcp_dl_t fcp_dl) *zfcp_get_fcp_dl_ptr(fcp_cmd) = fcp_dl; } -/* - * note: it's a bit-or operation not an assignment - * regarding the specified byte - */ -static inline void -set_byte(int *result, char status, char pos) -{ - *result |= status << (pos * 8); -} - -void -set_host_byte(int *result, char status) -{ - set_byte(result, status, 2); -} - -void -set_driver_byte(int *result, char status) -{ - set_byte(result, status, 3); -} - static int zfcp_scsi_slave_alloc(struct scsi_device *sdp) { @@ -196,7 +174,7 @@ zfcp_scsi_slave_configure(struct scsi_device *sdp) static void zfcp_scsi_command_fail(struct scsi_cmnd *scpnt, int result) { - set_host_byte(&scpnt->result, result); + set_host_byte(scpnt, result); if ((scpnt->device != NULL) && (scpnt->device->host != NULL)) zfcp_scsi_dbf_event_result("fail", 4, (struct zfcp_adapter*) scpnt->device->host->hostdata[0], diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h index 2b5b9356c314..00137a7769ee 100644 --- a/include/scsi/scsi.h +++ b/include/scsi/scsi.h @@ -9,6 +9,7 @@ #define _SCSI_SCSI_H #include +#include /* * The maximum number of SG segments that we will put inside a @@ -425,6 +426,22 @@ struct scsi_lun { #define driver_byte(result) (((result) >> 24) & 0xff) #define suggestion(result) (driver_byte(result) & SUGGEST_MASK) +static inline void set_msg_byte(struct scsi_cmnd *cmd, char status) +{ + cmd->result |= status << 8; +} + +static inline void set_host_byte(struct scsi_cmnd *cmd, char status) +{ + cmd->result |= status << 16; +} + +static inline void set_driver_byte(struct scsi_cmnd *cmd, char status) +{ + cmd->result |= status << 24; +} + + #define sense_class(sense) (((sense) >> 4) & 0x7) #define sense_error(sense) ((sense) & 0xf) #define sense_valid(sense) ((sense) & 0x80); -- cgit v1.2.3 From 02a1e3ce7df624ba91e8ff06e172f448746ad76a Mon Sep 17 00:00:00 2001 From: Alexander Beregalov Date: Sun, 6 Jul 2008 17:01:34 +0400 Subject: [SCSI] scsi_cmnd.h: remove double inclusion of linux/blkdev.h Signed-off-by: Alexander Beregalov Signed-off-by: James Bottomley --- include/scsi/scsi_cmnd.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h index 3e46dfae8194..66c944849d6b 100644 --- a/include/scsi/scsi_cmnd.h +++ b/include/scsi/scsi_cmnd.h @@ -7,7 +7,6 @@ #include #include #include -#include struct Scsi_Host; struct scsi_device; -- cgit v1.2.3 From 2f3804edf971d2080243d2b4552bfd61ddfbf969 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 2 Jul 2008 01:36:15 -0500 Subject: powerpc/85xx: Add support for MPC8536DS Add support for the MPC8536 process and MPC8536DS reference board. The MPC8536 is an e500v2 based SoC which eTSEC, USB, SATA, PCI, and PCIe. The USB and SATA IP blocks are similiar to those on the PQ2 Pro SoCs and thus use the same drivers. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8536ds.dts | 420 ++++++++ arch/powerpc/configs/mpc8536_ds_defconfig | 1637 +++++++++++++++++++++++++++++ arch/powerpc/platforms/85xx/Kconfig | 6 + arch/powerpc/platforms/85xx/Makefile | 1 + arch/powerpc/platforms/85xx/mpc8536_ds.c | 125 +++ arch/powerpc/sysdev/fsl_pci.c | 2 + include/linux/pci_ids.h | 2 + 7 files changed, 2193 insertions(+) create mode 100644 arch/powerpc/boot/dts/mpc8536ds.dts create mode 100644 arch/powerpc/configs/mpc8536_ds_defconfig create mode 100644 arch/powerpc/platforms/85xx/mpc8536_ds.c (limited to 'include') diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts new file mode 100644 index 000000000000..98ad27a2ddee --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8536ds.dts @@ -0,0 +1,420 @@ +/* + * MPC8536 DS Device Tree Source + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "fsl,mpc8536ds"; + compatible = "fsl,mpc8536ds"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + pci3 = &pci3; + }; + + cpus { + #cpus = <1>; + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8536@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <00000000 00000000>; // Filled by U-Boot + }; + + soc@ffe00000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0x0 0xffe00000 0x100000>; + reg = <0xffe00000 0x1000>; + bus-frequency = <0>; // Filled out by uboot. + + memory-controller@2000 { + compatible = "fsl,mpc8536-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 0x2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8536-l2-cache-controller"; + reg = <0x20000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <16 0x2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 0x2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 0x2>; + interrupt-parent = <&mpic>; + dfsrr; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma"; + reg = <0x21300 4>; + ranges = <0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8536-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <14 0x2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8536-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <15 0x2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8536-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <16 0x2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8536-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <17 0x2>; + }; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <10 0x1>; + reg = <0>; + device_type = "ethernet-phy"; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <10 0x1>; + reg = <1>; + device_type = "ethernet-phy"; + }; + }; + + usb@22000 { + compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; + reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&mpic>; + interrupts = <28 0x2>; + phy_type = "ulpi"; + }; + + usb@23000 { + compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&mpic>; + interrupts = <46 0x2>; + phy_type = "ulpi"; + }; + + enet0: ethernet@24000 { + cell-index = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ethernet@26000 { + cell-index = <1>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + usb@2b000 { + compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr"; + reg = <0x2b000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&mpic>; + interrupts = <60 0x2>; + dr_mode = "peripheral"; + phy_type = "ulpi"; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 0x2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 0x2>; + interrupt-parent = <&mpic>; + }; + + sata@18000 { + compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; + reg = <0x18000 0x1000>; + cell-index = <1>; + interrupts = <74 0x2>; + interrupt-parent = <&mpic>; + }; + + sata@19000 { + compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; + reg = <0x19000 0x1000>; + cell-index = <2>; + interrupts = <41 0x2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8548-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + + msi@41600 { + compatible = "fsl,mpc8536-msi", "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + }; + + pci0: pci@ffe08000 { + cell-index = <0>; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + + /* IDSEL 0x11 J17 Slot 1 */ + 0x8800 0 0 1 &mpic 1 1 + 0x8800 0 0 2 &mpic 2 1 + 0x8800 0 0 3 &mpic 3 1 + 0x8800 0 0 4 &mpic 4 1>; + + interrupt-parent = <&mpic>; + interrupts = <24 0x2>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000 + 0x01000000 0 0x00000000 0xffc00000 0 0x00010000>; + clock-frequency = <66666666>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xffe08000 0x1000>; + }; + + pci1: pcie@ffe09000 { + cell-index = <1>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xffe09000 0x1000>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000 + 0x01000000 0 0x00000000 0xffc20000 0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <25 0x2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0x98000000 + 0x02000000 0 0x98000000 + 0 0x08000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci2: pcie@ffe0a000 { + cell-index = <2>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xffe0a000 0x1000>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000 + 0x01000000 0 0x00000000 0xffc10000 0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <26 0x2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 1 + 0000 0 0 4 &mpic 3 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0x90000000 + 0x02000000 0 0x90000000 + 0 0x08000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci3: pcie@ffe0b000 { + cell-index = <3>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xffe0b000 0x1000>; + bus-range = <0 0xff>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 + 0x01000000 0 0x00000000 0xffc30000 0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <27 0x2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 8 1 + 0000 0 0 2 &mpic 9 1 + 0000 0 0 3 &mpic 10 1 + 0000 0 0 4 &mpic 11 1 + >; + + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0 0xa0000000 + 0x02000000 0 0xa0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00100000>; + }; + }; +}; diff --git a/arch/powerpc/configs/mpc8536_ds_defconfig b/arch/powerpc/configs/mpc8536_ds_defconfig new file mode 100644 index 000000000000..f1e2931de5da --- /dev/null +++ b/arch/powerpc/configs/mpc8536_ds_defconfig @@ -0,0 +1,1637 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc8 +# Wed Jul 2 01:34:26 2008 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_6xx is not set +CONFIG_PPC_85xx=y +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_E500=y +# CONFIG_PPC_E500MC is not set +CONFIG_BOOKE=y +CONFIG_FSL_BOOKE=y +CONFIG_FSL_EMB_PERFMON=y +# CONFIG_PHYS_64BIT is not set +CONFIG_SPE=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_PPC_MERGE=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y + +# +# Platform support +# +# CONFIG_PPC_MPC512x is not set +# CONFIG_PPC_MPC5121 is not set +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +CONFIG_MPC85xx=y +# CONFIG_MPC8540_ADS is not set +# CONFIG_MPC8560_ADS is not set +# CONFIG_MPC85xx_CDS is not set +# CONFIG_MPC85xx_MDS is not set +CONFIG_MPC8536_DS=y +# CONFIG_MPC85xx_DS is not set +# CONFIG_KSI8560 is not set +# CONFIG_STX_GP3 is not set +# CONFIG_TQM8540 is not set +# CONFIG_TQM8541 is not set +# CONFIG_TQM8548 is not set +# CONFIG_TQM8555 is not set +# CONFIG_TQM8560 is not set +# CONFIG_SBC8548 is not set +# CONFIG_SBC8560 is not set +# CONFIG_IPIC is not set +CONFIG_MPIC=y +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +# CONFIG_PPC_970_NAP is not set +# CONFIG_PPC_INDIRECT_IO is not set +# CONFIG_GENERIC_IOMAP is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_CPM2 is not set +# CONFIG_FSL_ULI1575 is not set + +# +# Kernel options +# +CONFIG_HIGHMEM=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_MISC=m +CONFIG_MATH_EMULATION=y +# CONFIG_IOMMU_HELPER is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_PROC_DEVICETREE=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_PM is not set +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +CONFIG_ZONE_DMA=y +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_FSL_SOC=y +CONFIG_FSL_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_ARCH_SUPPORTS_MSI=y +# CONFIG_PCI_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HAS_RAPIDIO is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_PHYSICAL_ALIGN=0x10000000 +CONFIG_TASK_SIZE=0xc0000000 + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE=y +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_ARPD=y +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +CONFIG_OF_DEVICE=y +CONFIG_OF_I2C=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=y +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=524288 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +# CONFIG_SATA_AHCI is not set +CONFIG_SATA_SIL24=y +CONFIG_SATA_FSL=y +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +CONFIG_SATA_SIL=y +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# Enable only one of the two stacks, unless you know what you are doing +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +CONFIG_VITESSE_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_E1000E_ENABLED is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +CONFIG_SKGE=y +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKY2=y +# CONFIG_SKY2_DEBUG is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +CONFIG_GIANFAR=y +CONFIG_GFAR_NAPI=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_SFC is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_OF_PLATFORM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +CONFIG_I2C_MPC=y +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +# CONFIG_I2C_PCA_PLATFORM is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_SENSORS_EEPROM=y +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +CONFIG_DVB_CORE=m +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_DVB_CAPTURE_DRIVERS=y + +# +# Supported SAA7146 based PCI Adapters +# +# CONFIG_TTPCI_EEPROM is not set +# CONFIG_DVB_BUDGET_CORE is not set + +# +# Supported USB Adapters +# +# CONFIG_DVB_USB is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +# CONFIG_DVB_CINERGYT2 is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported BT878 Adapters +# + +# +# Supported Pluto2 Adapters +# +# CONFIG_DVB_PLUTO2 is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_TDA10048 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522 is not set +# CONFIG_DVB_S5H1411 is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_AC97_CODEC=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALS4000 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5530 is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +CONFIG_SND_INTEL8X0=y +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_AC97_POWER_SAVE is not set + +# +# ALSA PowerMac devices +# + +# +# ALSA PowerPC devices +# + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_USX2Y is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# ALSA SoC audio for Freescale SOCs +# + +# +# SoC Audio for the Texas Instruments OMAP +# + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_FSL=y +CONFIG_USB_EHCI_HCD_PPC_OF=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PPC_OF=y +CONFIG_USB_OHCI_HCD_PPC_OF_BE=y +CONFIG_USB_OHCI_HCD_PPC_OF_LE=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y +CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PPC is not set +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +CONFIG_FSL_DMA=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_AFFS_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_CRAMFS=y +CONFIG_VXFS_FS=m +# CONFIG_MINIX_FS is not set +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +# CONFIG_ROMFS_FS is not set +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_BIND34 is not set +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUGGER is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_IRQSTACKS is not set +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_PPC_CLOCK is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 9cb8e29987a3..cebea5cadbc1 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -38,6 +38,12 @@ config MPC85xx_MDS help This option enables support for the MPC85xx MDS board +config MPC8536_DS + bool "Freescale MPC8536 DS" + select DEFAULT_UIMAGE + help + This option enables support for the MPC8536 DS board + config MPC85xx_DS bool "Freescale MPC85xx DS" select PPC_I8259 diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 6cea185f62b2..cb3054e1001d 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o +obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o obj-$(CONFIG_STX_GP3) += stx_gp3.o diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c new file mode 100644 index 000000000000..71d7c038961f --- /dev/null +++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c @@ -0,0 +1,125 @@ +/* + * MPC8536 DS Board Setup + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +void __init mpc8536_ds_pic_init(void) +{ + struct mpic *mpic; + struct resource r; + struct device_node *np; + + np = of_find_node_by_type(np, "open-pic"); + if (np == NULL) { + printk(KERN_ERR "Could not find open-pic node\n"); + return; + } + + if (of_address_to_resource(np, 0, &r)) { + printk(KERN_ERR "Failed to map mpic register space\n"); + of_node_put(np); + return; + } + + mpic = mpic_alloc(np, r.start, + MPIC_PRIMARY | MPIC_WANTS_RESET | + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, + 0, 256, " OpenPIC "); + BUG_ON(mpic == NULL); + of_node_put(np); + + mpic_init(mpic); +} + +/* + * Setup the architecture + */ +static void __init mpc8536_ds_setup_arch(void) +{ +#ifdef CONFIG_PCI + struct device_node *np; +#endif + + if (ppc_md.progress) + ppc_md.progress("mpc8536_ds_setup_arch()", 0); + +#ifdef CONFIG_PCI + for_each_node_by_type(np, "pci") { + if (of_device_is_compatible(np, "fsl,mpc8540-pci") || + of_device_is_compatible(np, "fsl,mpc8548-pcie")) { + struct resource rsrc; + of_address_to_resource(np, 0, &rsrc); + if ((rsrc.start & 0xfffff) == 0x8000) + fsl_add_bridge(np, 1); + else + fsl_add_bridge(np, 0); + } + } + +#endif + + printk("MPC8536 DS board from Freescale Semiconductor\n"); +} + +static struct of_device_id __initdata mpc8536_ds_ids[] = { + { .type = "soc", }, + { .compatible = "soc", }, + {}, +}; + +static int __init mpc8536_ds_publish_devices(void) +{ + return of_platform_bus_probe(NULL, mpc8536_ds_ids, NULL); +} +machine_device_initcall(mpc8536_ds, mpc8536_ds_publish_devices); + +/* + * Called very early, device-tree isn't unflattened + */ +static int __init mpc8536_ds_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + return of_flat_dt_is_compatible(root, "fsl,mpc8536ds"); +} + +define_machine(mpc8536_ds) { + .name = "MPC8536 DS", + .probe = mpc8536_ds_probe, + .setup_arch = mpc8536_ds_setup_arch, + .init_IRQ = mpc8536_ds_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 489ca5a397b1..87b0aa13ab48 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -243,6 +243,8 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header); +DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header); +DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 65953822c9cb..1cf4084b51e8 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2171,6 +2171,8 @@ #define PCI_DEVICE_ID_MPC8544 0x0033 #define PCI_DEVICE_ID_MPC8572E 0x0040 #define PCI_DEVICE_ID_MPC8572 0x0041 +#define PCI_DEVICE_ID_MPC8536E 0x0050 +#define PCI_DEVICE_ID_MPC8536 0x0051 #define PCI_DEVICE_ID_MPC8641 0x7010 #define PCI_DEVICE_ID_MPC8641D 0x7011 #define PCI_DEVICE_ID_MPC8610 0x7018 -- cgit v1.2.3 From 4ee6afd34409d296782a5b667d7991b1050e910a Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Wed, 7 May 2008 21:01:30 +0300 Subject: VFS: export sync_sb_inodes This patch exports the 'sync_sb_inodes()' which is needed for UBIFS because it has to force write-back from time to time. Namely, the UBIFS budgeting subsystem forces write-back when its pessimistic callculations show that there is no free space on the media. Signed-off-by: Artem Bityutskiy --- fs/fs-writeback.c | 11 +++++++++-- include/linux/fs.h | 2 ++ 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/fs/fs-writeback.c b/fs/fs-writeback.c index 16519fe1399c..25adfc3c693a 100644 --- a/fs/fs-writeback.c +++ b/fs/fs-writeback.c @@ -439,8 +439,8 @@ __writeback_single_inode(struct inode *inode, struct writeback_control *wbc) * on the writer throttling path, and we get decent balancing between many * throttled threads: we don't want them all piling up on inode_sync_wait. */ -static void -sync_sb_inodes(struct super_block *sb, struct writeback_control *wbc) +void generic_sync_sb_inodes(struct super_block *sb, + struct writeback_control *wbc) { const unsigned long start = jiffies; /* livelock avoidance */ @@ -526,6 +526,13 @@ sync_sb_inodes(struct super_block *sb, struct writeback_control *wbc) spin_unlock(&inode_lock); return; /* Leave any unwritten inodes on s_io */ } +EXPORT_SYMBOL_GPL(generic_sync_sb_inodes); + +static void sync_sb_inodes(struct super_block *sb, + struct writeback_control *wbc) +{ + generic_sync_sb_inodes(sb, wbc); +} /* * Start writeback of dirty pagecache data against all unlocked inodes. diff --git a/include/linux/fs.h b/include/linux/fs.h index d8e2762ed14d..f9d2aab47eda 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1729,6 +1729,8 @@ static inline void invalidate_remote_inode(struct inode *inode) extern int invalidate_inode_pages2(struct address_space *mapping); extern int invalidate_inode_pages2_range(struct address_space *mapping, pgoff_t start, pgoff_t end); +extern void generic_sync_sb_inodes(struct super_block *sb, + struct writeback_control *wbc); extern int write_inode_now(struct inode *, int); extern int filemap_fdatawrite(struct address_space *); extern int filemap_flush(struct address_space *); -- cgit v1.2.3 From 11c3b79218390a139f2d474ee1e983a672d5839a Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Jun 2008 14:00:18 -0700 Subject: configfs: Allow ->make_item() and ->make_group() to return detailed errors. The configfs operations ->make_item() and ->make_group() currently return a new item/group. A return of NULL signifies an error. Because of this, -ENOMEM is the only return code bubbled up the stack. Multiple folks have requested the ability to return specific error codes when these operations fail. This patch adds that ability by changing the ->make_item/group() ops to return an int. Also updated are the in-kernel users of configfs. Signed-off-by: Joel Becker --- Documentation/filesystems/configfs/configfs.txt | 10 +++-- .../filesystems/configfs/configfs_example.c | 14 ++++--- drivers/net/netconsole.c | 10 +++-- fs/configfs/dir.c | 13 +++---- fs/dlm/config.c | 45 ++++++++++++++-------- fs/ocfs2/cluster/heartbeat.c | 17 ++++---- fs/ocfs2/cluster/nodemanager.c | 45 ++++++++++++++-------- include/linux/configfs.h | 4 +- 8 files changed, 94 insertions(+), 64 deletions(-) (limited to 'include') diff --git a/Documentation/filesystems/configfs/configfs.txt b/Documentation/filesystems/configfs/configfs.txt index 44c97e6accb2..15838d706ea2 100644 --- a/Documentation/filesystems/configfs/configfs.txt +++ b/Documentation/filesystems/configfs/configfs.txt @@ -233,10 +233,12 @@ accomplished via the group operations specified on the group's config_item_type. struct configfs_group_operations { - struct config_item *(*make_item)(struct config_group *group, - const char *name); - struct config_group *(*make_group)(struct config_group *group, - const char *name); + int (*make_item)(struct config_group *group, + const char *name, + struct config_item **new_item); + int (*make_group)(struct config_group *group, + const char *name, + struct config_group **new_group); int (*commit_item)(struct config_item *item); void (*disconnect_notify)(struct config_group *group, struct config_item *item); diff --git a/Documentation/filesystems/configfs/configfs_example.c b/Documentation/filesystems/configfs/configfs_example.c index 25151fd5c2c6..0b422acd470c 100644 --- a/Documentation/filesystems/configfs/configfs_example.c +++ b/Documentation/filesystems/configfs/configfs_example.c @@ -273,13 +273,13 @@ static inline struct simple_children *to_simple_children(struct config_item *ite return item ? container_of(to_config_group(item), struct simple_children, group) : NULL; } -static struct config_item *simple_children_make_item(struct config_group *group, const char *name) +static int simple_children_make_item(struct config_group *group, const char *name, struct config_item **new_item) { struct simple_child *simple_child; simple_child = kzalloc(sizeof(struct simple_child), GFP_KERNEL); if (!simple_child) - return NULL; + return -ENOMEM; config_item_init_type_name(&simple_child->item, name, @@ -287,7 +287,8 @@ static struct config_item *simple_children_make_item(struct config_group *group, simple_child->storeme = 0; - return &simple_child->item; + *new_item = &simple_child->item; + return 0; } static struct configfs_attribute simple_children_attr_description = { @@ -359,20 +360,21 @@ static struct configfs_subsystem simple_children_subsys = { * children of its own. */ -static struct config_group *group_children_make_group(struct config_group *group, const char *name) +static int group_children_make_group(struct config_group *group, const char *name, struct config_group **new_group) { struct simple_children *simple_children; simple_children = kzalloc(sizeof(struct simple_children), GFP_KERNEL); if (!simple_children) - return NULL; + return -ENOMEM; config_group_init_type_name(&simple_children->group, name, &simple_children_type); - return &simple_children->group; + *new_group = &simple_children->group; + return 0; } static struct configfs_attribute group_children_attr_description = { diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 665341e43055..387a13395015 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -585,8 +585,9 @@ static struct config_item_type netconsole_target_type = { * Group operations and type for netconsole_subsys. */ -static struct config_item *make_netconsole_target(struct config_group *group, - const char *name) +static int make_netconsole_target(struct config_group *group, + const char *name, + struct config_item **new_item) { unsigned long flags; struct netconsole_target *nt; @@ -598,7 +599,7 @@ static struct config_item *make_netconsole_target(struct config_group *group, nt = kzalloc(sizeof(*nt), GFP_KERNEL); if (!nt) { printk(KERN_ERR "netconsole: failed to allocate memory\n"); - return NULL; + return -ENOMEM; } nt->np.name = "netconsole"; @@ -615,7 +616,8 @@ static struct config_item *make_netconsole_target(struct config_group *group, list_add(&nt->list, &target_list); spin_unlock_irqrestore(&target_list_lock, flags); - return &nt->item; + *new_item = &nt->item; + return 0; } static void drop_netconsole_target(struct config_group *group, diff --git a/fs/configfs/dir.c b/fs/configfs/dir.c index 614e382a6049..0e64312a084c 100644 --- a/fs/configfs/dir.c +++ b/fs/configfs/dir.c @@ -1073,25 +1073,24 @@ static int configfs_mkdir(struct inode *dir, struct dentry *dentry, int mode) group = NULL; item = NULL; if (type->ct_group_ops->make_group) { - group = type->ct_group_ops->make_group(to_config_group(parent_item), name); - if (group) { + ret = type->ct_group_ops->make_group(to_config_group(parent_item), name, &group); + if (!ret) { link_group(to_config_group(parent_item), group); item = &group->cg_item; } } else { - item = type->ct_group_ops->make_item(to_config_group(parent_item), name); - if (item) + ret = type->ct_group_ops->make_item(to_config_group(parent_item), name, &item); + if (!ret) link_obj(parent_item, item); } mutex_unlock(&subsys->su_mutex); kfree(name); - if (!item) { + if (ret) { /* - * If item == NULL, then link_obj() was never called. + * If ret != 0, then link_obj() was never called. * There are no extra references to clean up. */ - ret = -ENOMEM; goto out_put; } diff --git a/fs/dlm/config.c b/fs/dlm/config.c index eac23bd288b2..492d8caaaf25 100644 --- a/fs/dlm/config.c +++ b/fs/dlm/config.c @@ -41,16 +41,20 @@ struct comm; struct nodes; struct node; -static struct config_group *make_cluster(struct config_group *, const char *); +static int make_cluster(struct config_group *, const char *, + struct config_group **); static void drop_cluster(struct config_group *, struct config_item *); static void release_cluster(struct config_item *); -static struct config_group *make_space(struct config_group *, const char *); +static int make_space(struct config_group *, const char *, + struct config_group **); static void drop_space(struct config_group *, struct config_item *); static void release_space(struct config_item *); -static struct config_item *make_comm(struct config_group *, const char *); +static int make_comm(struct config_group *, const char *, + struct config_item **); static void drop_comm(struct config_group *, struct config_item *); static void release_comm(struct config_item *); -static struct config_item *make_node(struct config_group *, const char *); +static int make_node(struct config_group *, const char *, + struct config_item **); static void drop_node(struct config_group *, struct config_item *); static void release_node(struct config_item *); @@ -392,8 +396,8 @@ static struct node *to_node(struct config_item *i) return i ? container_of(i, struct node, item) : NULL; } -static struct config_group *make_cluster(struct config_group *g, - const char *name) +static int make_cluster(struct config_group *g, const char *name, + struct config_group **new_g) { struct cluster *cl = NULL; struct spaces *sps = NULL; @@ -431,14 +435,15 @@ static struct config_group *make_cluster(struct config_group *g, space_list = &sps->ss_group; comm_list = &cms->cs_group; - return &cl->group; + *new_g = &cl->group; + return 0; fail: kfree(cl); kfree(gps); kfree(sps); kfree(cms); - return NULL; + return -ENOMEM; } static void drop_cluster(struct config_group *g, struct config_item *i) @@ -466,7 +471,8 @@ static void release_cluster(struct config_item *i) kfree(cl); } -static struct config_group *make_space(struct config_group *g, const char *name) +static int make_space(struct config_group *g, const char *name, + struct config_group **new_g) { struct space *sp = NULL; struct nodes *nds = NULL; @@ -489,13 +495,14 @@ static struct config_group *make_space(struct config_group *g, const char *name) INIT_LIST_HEAD(&sp->members); mutex_init(&sp->members_lock); sp->members_count = 0; - return &sp->group; + *new_g = &sp->group; + return 0; fail: kfree(sp); kfree(gps); kfree(nds); - return NULL; + return -ENOMEM; } static void drop_space(struct config_group *g, struct config_item *i) @@ -522,19 +529,21 @@ static void release_space(struct config_item *i) kfree(sp); } -static struct config_item *make_comm(struct config_group *g, const char *name) +static int make_comm(struct config_group *g, const char *name, + struct config_item **new_i) { struct comm *cm; cm = kzalloc(sizeof(struct comm), GFP_KERNEL); if (!cm) - return NULL; + return -ENOMEM; config_item_init_type_name(&cm->item, name, &comm_type); cm->nodeid = -1; cm->local = 0; cm->addr_count = 0; - return &cm->item; + *new_i = &cm->item; + return 0; } static void drop_comm(struct config_group *g, struct config_item *i) @@ -554,14 +563,15 @@ static void release_comm(struct config_item *i) kfree(cm); } -static struct config_item *make_node(struct config_group *g, const char *name) +static int make_node(struct config_group *g, const char *name, + struct config_item **new_i) { struct space *sp = to_space(g->cg_item.ci_parent); struct node *nd; nd = kzalloc(sizeof(struct node), GFP_KERNEL); if (!nd) - return NULL; + return -ENOMEM; config_item_init_type_name(&nd->item, name, &node_type); nd->nodeid = -1; @@ -573,7 +583,8 @@ static struct config_item *make_node(struct config_group *g, const char *name) sp->members_count++; mutex_unlock(&sp->members_lock); - return &nd->item; + *new_i = &nd->item; + return 0; } static void drop_node(struct config_group *g, struct config_item *i) diff --git a/fs/ocfs2/cluster/heartbeat.c b/fs/ocfs2/cluster/heartbeat.c index f02ccb34604d..443d108211ab 100644 --- a/fs/ocfs2/cluster/heartbeat.c +++ b/fs/ocfs2/cluster/heartbeat.c @@ -1489,25 +1489,28 @@ static struct o2hb_heartbeat_group *to_o2hb_heartbeat_group(struct config_group : NULL; } -static struct config_item *o2hb_heartbeat_group_make_item(struct config_group *group, - const char *name) +static int o2hb_heartbeat_group_make_item(struct config_group *group, + const char *name, + struct config_item **new_item) { struct o2hb_region *reg = NULL; - struct config_item *ret = NULL; + int ret = 0; reg = kzalloc(sizeof(struct o2hb_region), GFP_KERNEL); - if (reg == NULL) - goto out; /* ENOMEM */ + if (reg == NULL) { + ret = -ENOMEM; + goto out; + } config_item_init_type_name(®->hr_item, name, &o2hb_region_type); - ret = ®->hr_item; + *new_item = ®->hr_item; spin_lock(&o2hb_live_lock); list_add_tail(®->hr_all_item, &o2hb_all_regions); spin_unlock(&o2hb_live_lock); out: - if (ret == NULL) + if (ret) kfree(reg); return ret; diff --git a/fs/ocfs2/cluster/nodemanager.c b/fs/ocfs2/cluster/nodemanager.c index cfdb08b484ed..b364b7052e46 100644 --- a/fs/ocfs2/cluster/nodemanager.c +++ b/fs/ocfs2/cluster/nodemanager.c @@ -644,27 +644,32 @@ out: return ret; } -static struct config_item *o2nm_node_group_make_item(struct config_group *group, - const char *name) +static int o2nm_node_group_make_item(struct config_group *group, + const char *name, + struct config_item **new_item) { struct o2nm_node *node = NULL; - struct config_item *ret = NULL; + int ret = 0; - if (strlen(name) > O2NM_MAX_NAME_LEN) - goto out; /* ENAMETOOLONG */ + if (strlen(name) > O2NM_MAX_NAME_LEN) { + ret = -ENAMETOOLONG; + goto out; + } node = kzalloc(sizeof(struct o2nm_node), GFP_KERNEL); - if (node == NULL) - goto out; /* ENOMEM */ + if (node == NULL) { + ret = -ENOMEM; + goto out; + } strcpy(node->nd_name, name); /* use item.ci_namebuf instead? */ config_item_init_type_name(&node->nd_item, name, &o2nm_node_type); spin_lock_init(&node->nd_lock); - ret = &node->nd_item; + *new_item = &node->nd_item; out: - if (ret == NULL) + if (ret) kfree(node); return ret; @@ -751,25 +756,31 @@ static struct o2nm_cluster_group *to_o2nm_cluster_group(struct config_group *gro } #endif -static struct config_group *o2nm_cluster_group_make_group(struct config_group *group, - const char *name) +static int o2nm_cluster_group_make_group(struct config_group *group, + const char *name, + struct config_group **new_group) { struct o2nm_cluster *cluster = NULL; struct o2nm_node_group *ns = NULL; - struct config_group *o2hb_group = NULL, *ret = NULL; + struct config_group *o2hb_group = NULL; void *defs = NULL; + int ret = 0; /* this runs under the parent dir's i_mutex; there can be only * one caller in here at a time */ - if (o2nm_single_cluster) - goto out; /* ENOSPC */ + if (o2nm_single_cluster) { + ret = -ENOSPC; + goto out; + } cluster = kzalloc(sizeof(struct o2nm_cluster), GFP_KERNEL); ns = kzalloc(sizeof(struct o2nm_node_group), GFP_KERNEL); defs = kcalloc(3, sizeof(struct config_group *), GFP_KERNEL); o2hb_group = o2hb_alloc_hb_set(); - if (cluster == NULL || ns == NULL || o2hb_group == NULL || defs == NULL) + if (cluster == NULL || ns == NULL || o2hb_group == NULL || defs == NULL) { + ret = -ENOMEM; goto out; + } config_group_init_type_name(&cluster->cl_group, name, &o2nm_cluster_type); @@ -786,11 +797,11 @@ static struct config_group *o2nm_cluster_group_make_group(struct config_group *g cluster->cl_idle_timeout_ms = O2NET_IDLE_TIMEOUT_MS_DEFAULT; cluster->cl_keepalive_delay_ms = O2NET_KEEPALIVE_DELAY_MS_DEFAULT; - ret = &cluster->cl_group; + *new_group = &cluster->cl_group; o2nm_single_cluster = cluster; out: - if (ret == NULL) { + if (ret) { kfree(cluster); kfree(ns); o2hb_free_hb_set(o2hb_group); diff --git a/include/linux/configfs.h b/include/linux/configfs.h index 3ae65b1bf90f..0488f937634a 100644 --- a/include/linux/configfs.h +++ b/include/linux/configfs.h @@ -165,8 +165,8 @@ struct configfs_item_operations { }; struct configfs_group_operations { - struct config_item *(*make_item)(struct config_group *group, const char *name); - struct config_group *(*make_group)(struct config_group *group, const char *name); + int (*make_item)(struct config_group *group, const char *name, struct config_item **new_item); + int (*make_group)(struct config_group *group, const char *name, struct config_group **new_group); int (*commit_item)(struct config_item *item); void (*disconnect_notify)(struct config_group *group, struct config_item *item); void (*drop_item)(struct config_group *group, struct config_item *item); -- cgit v1.2.3 From c300bd2fb583afb6d68804afd38bc90b31310d95 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Thu, 10 Jul 2008 02:16:44 +0200 Subject: PCI: include linux/pm_wakeup.h for device_set_wakeup_capable drivers/pci/pci.c needs pm_wakeup.h since it uses device_set_wakup_capable(). The latter also needs to be stubbed out for !CONFIG_PM. Signed-off-by: Stephen Rothwell Signed-off-by: Rafael J. Wysocki Signed-off-by: Jesse Barnes --- drivers/pci/pci.c | 1 + include/linux/pm_wakeup.h | 2 ++ 2 files changed, 3 insertions(+) (limited to 'include') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ace518116cc5..44a46c92b721 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -17,6 +17,7 @@ #include #include #include +#include #include /* isa_dma_bridge_buggy */ #include "pci.h" diff --git a/include/linux/pm_wakeup.h b/include/linux/pm_wakeup.h index 3af0c8d05cdc..0aae7776185e 100644 --- a/include/linux/pm_wakeup.h +++ b/include/linux/pm_wakeup.h @@ -63,6 +63,8 @@ static inline void device_init_wakeup(struct device *dev, int val) dev->power.can_wakeup = !!val; } +static inline void device_set_wakeup_capable(struct device *dev, int val) { } + static inline int device_can_wakeup(struct device *dev) { return dev->power.can_wakeup; -- cgit v1.2.3 From b3fcaaa8a6359e9ed623ed4c1d2d48c79eed4648 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Mon, 14 Jul 2008 19:25:57 +1000 Subject: powerpc: mman.h export fixups Commit ef3d3246a0d06be622867d21af25f997aeeb105f ("powerpc/mm: Add Strong Access Ordering support") in the powerpc/{next,master} tree caused the following in a powerpc allmodconfig build: usr/include/asm/mman.h requires linux/mm.h, which does not exist in exported headers We should not use CONFIG_PPC64 in an unprotected (by __KERNEL__) section of an exported include file and linux/mm.h is not exported. So protect the whole section that is CONFIG_PPC64 with __KERNEL__ and put the two introduced includes in there as well. Signed-off-by: Stephen Rothwell Acked-by: Dave Kleikamp Signed-off-by: Benjamin Herrenschmidt --- include/asm-powerpc/Kbuild | 1 - include/asm-powerpc/mman.h | 8 ++++++-- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild index 34a0a8db0104..04ce8f8a2ee7 100644 --- a/include/asm-powerpc/Kbuild +++ b/include/asm-powerpc/Kbuild @@ -2,7 +2,6 @@ include include/asm-generic/Kbuild.asm header-y += auxvec.h header-y += ioctls.h -header-y += mman.h header-y += sembuf.h header-y += siginfo.h header-y += stat.h diff --git a/include/asm-powerpc/mman.h b/include/asm-powerpc/mman.h index f8a32e20ba04..9209f755763e 100644 --- a/include/asm-powerpc/mman.h +++ b/include/asm-powerpc/mman.h @@ -1,9 +1,7 @@ #ifndef _ASM_POWERPC_MMAN_H #define _ASM_POWERPC_MMAN_H -#include #include -#include /* * This program is free software; you can redistribute it and/or @@ -28,7 +26,12 @@ #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ #define MAP_NONBLOCK 0x10000 /* do not block on IO */ +#ifdef __KERNEL__ #ifdef CONFIG_PPC64 + +#include +#include + /* * This file is included by linux/mman.h, so we can't use cacl_vm_prot_bits() * here. How important is the optimization? @@ -56,4 +59,5 @@ static inline int arch_validate_prot(unsigned long prot) #define arch_validate_prot(prot) arch_validate_prot(prot) #endif /* CONFIG_PPC64 */ +#endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_MMAN_H */ -- cgit v1.2.3 From 0f47331475201c7785454030a9976c8ac902a35d Mon Sep 17 00:00:00 2001 From: Nathan Lynch Date: Thu, 10 Jul 2008 01:06:57 +1000 Subject: powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPAT Background from Maynard Johnson: As of POWER6, a set of 32 common events is defined that must be supported on all future POWER processors. The main impetus for this compat set is the need to support partition migration, especially from processor P(n) to processor P(n+1), where performance software that's running in the new partition may not be knowledgeable about processor P(n+1). If a performance tool determines it does not support the physical processor, but is told (via the PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports the notion of the PMU compat set, then the performance tool can surface just those events to the user of the tool. PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at least this basic subset of events which is compatible across POWER processor lines. Signed-off-by: Nathan Lynch Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/cputable.c | 6 ++++-- include/asm-powerpc/cputable.h | 3 +++ 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 72adb19a204d..f7f3c215d06f 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -70,10 +70,12 @@ extern void __restore_cpu_power7(void); PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP) #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\ PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ - PPC_FEATURE_TRUE_LE) + PPC_FEATURE_TRUE_LE | \ + PPC_FEATURE_PSERIES_PERFMON_COMPAT) #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ - PPC_FEATURE_TRUE_LE) + PPC_FEATURE_TRUE_LE | \ + PPC_FEATURE_PSERIES_PERFMON_COMPAT) #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\ PPC_FEATURE_TRUE_LE | \ PPC_FEATURE_HAS_ALTIVEC_COMP) diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 4fd76898975b..2a3e9075a5a0 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -27,6 +27,9 @@ #define PPC_FEATURE_ARCH_2_06 0x00000100 #define PPC_FEATURE_HAS_VSX 0x00000080 +#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \ + 0x00000040 + #define PPC_FEATURE_TRUE_LE 0x00000002 #define PPC_FEATURE_PPC_LE 0x00000001 -- cgit v1.2.3 From 7c29217096d83f657e6ee70479af09b46f4275f6 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Fri, 11 Jul 2008 16:29:12 +1000 Subject: powerpc: fix giveup_vsx to save registers correctly giveup_vsx didn't save the FPU and VMX regsiters. Change it to be like giveup_fpr/altivec which save these registers. Also update call sites where FPU and VMX are already saved to use the original giveup_vsx (renamed to __giveup_vsx). Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/misc_64.S | 8 ++++---- arch/powerpc/kernel/process.c | 10 +++++++++- arch/powerpc/kernel/signal_32.c | 2 +- arch/powerpc/kernel/signal_64.c | 2 +- include/asm-powerpc/system.h | 1 + 5 files changed, 16 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index 31b9026cf1e3..4dd70cf7bb4e 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S @@ -508,12 +508,12 @@ _GLOBAL(giveup_altivec) #ifdef CONFIG_VSX /* - * giveup_vsx(tsk) - * Disable VSX for the task given as the argument, - * and save the vector registers in its thread_struct. + * __giveup_vsx(tsk) + * Disable VSX for the task given as the argument. + * Does NOT save vsx registers. * Enables the VSX for use in the kernel on return. */ -_GLOBAL(giveup_vsx) +_GLOBAL(__giveup_vsx) mfmsr r5 oris r5,r5,MSR_VSX@h mtmsrd r5 /* enable use of VSX now */ diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 0a4eb0811590..219f3634115e 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -159,6 +159,13 @@ void enable_kernel_vsx(void) EXPORT_SYMBOL(enable_kernel_vsx); #endif +void giveup_vsx(struct task_struct *tsk) +{ + giveup_fpu(tsk); + giveup_altivec(tsk); + __giveup_vsx(tsk); +} + void flush_vsx_to_thread(struct task_struct *tsk) { if (tsk->thread.regs) { @@ -290,7 +297,8 @@ struct task_struct *__switch_to(struct task_struct *prev, #endif /* CONFIG_ALTIVEC */ #ifdef CONFIG_VSX if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) - giveup_vsx(prev); + /* VMX and FPU registers are already save here */ + __giveup_vsx(prev); #endif /* CONFIG_VSX */ #ifdef CONFIG_SPE /* diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index 6f6810db0a74..3e80aa32b8b0 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c @@ -452,7 +452,7 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame, * contains valid data */ if (current->thread.used_vsr) { - flush_vsx_to_thread(current); + __giveup_vsx(current); if (copy_vsx_to_user(&frame->mc_vsregs, current)) return 1; msr |= MSR_VSX; diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c index 5f9d2ef2e24b..65ad925c3a8f 100644 --- a/arch/powerpc/kernel/signal_64.c +++ b/arch/powerpc/kernel/signal_64.c @@ -122,7 +122,7 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, * VMX data. */ if (current->thread.used_vsr) { - flush_vsx_to_thread(current); + __giveup_vsx(current); v_regs += ELF_NVRREG; err |= copy_vsx_to_user(v_regs, current); /* set MSR_VSX in the MSR value in the frame to diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 0c12c66733f6..e6e25e2364eb 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -139,6 +139,7 @@ extern void enable_kernel_altivec(void); extern void giveup_altivec(struct task_struct *); extern void load_up_altivec(struct task_struct *); extern int emulate_altivec(struct pt_regs *); +extern void __giveup_vsx(struct task_struct *); extern void giveup_vsx(struct task_struct *); extern void enable_kernel_spe(void); extern void giveup_spe(struct task_struct *); -- cgit v1.2.3 From 585583d95c5660973bc0cf64add517b040acd8a4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 14 Jul 2008 08:08:45 -0500 Subject: powerpc: Fix pte_update for CONFIG_PTE_64BIT and !PTE_ATOMIC_UPDATES Because the pte is now 64-bits the compiler was optimizing the update to always clear the upper 32-bits of the pte. We need to ensure the clr mask is treated as an unsigned long long to get the proper behavior. Signed-off-by: Kumar Gala Acked-by: Josh Boyer Signed-off-by: Benjamin Herrenschmidt --- include/asm-powerpc/pgtable-ppc32.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h index 11eede4a2906..73015f0139de 100644 --- a/include/asm-powerpc/pgtable-ppc32.h +++ b/include/asm-powerpc/pgtable-ppc32.h @@ -624,7 +624,7 @@ static inline unsigned long long pte_update(pte_t *p, : "cc" ); #else /* PTE_ATOMIC_UPDATES */ unsigned long long old = pte_val(*p); - *p = __pte((old & ~clr) | set); + *p = __pte((old & ~(unsigned long long)clr) | set); #endif /* !PTE_ATOMIC_UPDATES */ #ifdef CONFIG_44x -- cgit v1.2.3 From 4489428ab5a49a6f443d9aa17f1d891417787d7b Mon Sep 17 00:00:00 2001 From: Pierre Ossman Date: Fri, 4 Apr 2008 19:36:59 +0200 Subject: sdhci: support JMicron secondary interface JMicron chips sometimes have two interfaces to work around limitations in Microsoft's sdhci driver. This patch allows us to use either interface. Signed-off-by: Pierre Ossman --- drivers/mmc/host/sdhci-pci.c | 127 ++++++++++++++++++++++++++++++++++++++++++- include/linux/pci_ids.h | 1 + 2 files changed, 126 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c index ef77ed1bd114..5dcb4958e47b 100644 --- a/drivers/mmc/host/sdhci-pci.c +++ b/drivers/mmc/host/sdhci-pci.c @@ -39,12 +39,18 @@ #define MAX_SLOTS 8 struct sdhci_pci_chip; +struct sdhci_pci_slot; struct sdhci_pci_fixes { unsigned int quirks; int (*probe)(struct sdhci_pci_chip*); + int (*probe_slot)(struct sdhci_pci_slot*); + void (*remove_slot)(struct sdhci_pci_slot*); + + int (*suspend)(struct sdhci_pci_chip*, + pm_message_t); int (*resume)(struct sdhci_pci_chip*); }; @@ -132,6 +138,38 @@ static int jmicron_probe(struct sdhci_pci_chip *chip) { int ret; + /* + * JMicron chips can have two interfaces to the same hardware + * in order to work around limitations in Microsoft's driver. + * We need to make sure we only bind to one of them. + * + * This code assumes two things: + * + * 1. The PCI code adds subfunctions in order. + * + * 2. The MMC interface has a lower subfunction number + * than the SD interface. + */ + if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) { + struct pci_dev *sd_dev; + + sd_dev = NULL; + while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, + PCI_DEVICE_ID_JMICRON_JMB38X_MMC, sd_dev)) != NULL) { + if ((PCI_SLOT(chip->pdev->devfn) == + PCI_SLOT(sd_dev->devfn)) && + (chip->pdev->bus == sd_dev->bus)) + break; + } + + if (sd_dev) { + pci_dev_put(sd_dev); + dev_info(&chip->pdev->dev, "Refusing to bind to " + "secondary interface.\n"); + return -ENODEV; + } + } + /* * JMicron chips need a bit of a nudge to enable the power * output pins. @@ -145,9 +183,58 @@ static int jmicron_probe(struct sdhci_pci_chip *chip) return 0; } +static void jmicron_enable_mmc(struct sdhci_host *host, int on) +{ + u8 scratch; + + scratch = readb(host->ioaddr + 0xC0); + + if (on) + scratch |= 0x01; + else + scratch &= ~0x01; + + writeb(scratch, host->ioaddr + 0xC0); +} + +static int jmicron_probe_slot(struct sdhci_pci_slot *slot) +{ + /* + * The secondary interface requires a bit set to get the + * interrupts. + */ + if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) + jmicron_enable_mmc(slot->host, 1); + + return 0; +} + +static void jmicron_remove_slot(struct sdhci_pci_slot *slot) +{ + if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) + jmicron_enable_mmc(slot->host, 0); +} + +static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state) +{ + int i; + + if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) { + for (i = 0;i < chip->num_slots;i++) + jmicron_enable_mmc(chip->slots[i]->host, 0); + } + + return 0; +} + static int jmicron_resume(struct sdhci_pci_chip *chip) { - int ret; + int ret, i; + + if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) { + for (i = 0;i < chip->num_slots;i++) + jmicron_enable_mmc(chip->slots[i]->host, 1); + } ret = jmicron_pmos(chip, 1); if (ret) { @@ -165,6 +252,10 @@ static const struct sdhci_pci_fixes sdhci_jmicron = { .probe = jmicron_probe, + .probe_slot = jmicron_probe_slot, + .remove_slot = jmicron_remove_slot, + + .suspend = jmicron_suspend, .resume = jmicron_resume, }; @@ -225,6 +316,14 @@ static const struct pci_device_id pci_ids[] __devinitdata = { .driver_data = (kernel_ulong_t)&sdhci_jmicron, }, + { + .vendor = PCI_VENDOR_ID_JMICRON, + .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .driver_data = (kernel_ulong_t)&sdhci_jmicron, + }, + { /* Generic SD host controller */ PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) }, @@ -301,6 +400,15 @@ static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state) } } + if (chip->fixes && chip->fixes->suspend) { + ret = chip->fixes->suspend(chip, state); + if (ret) { + for (i = chip->num_slots - 1;i >= 0;i--) + sdhci_resume_host(chip->slots[i]->host); + return ret; + } + } + pci_save_state(pdev); pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); pci_disable_device(pdev); @@ -418,12 +526,22 @@ static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot( goto release; } + if (chip->fixes && chip->fixes->probe_slot) { + ret = chip->fixes->probe_slot(slot); + if (ret) + goto unmap; + } + ret = sdhci_add_host(host); if (ret) - goto unmap; + goto remove; return slot; +remove: + if (chip->fixes && chip->fixes->remove_slot) + chip->fixes->remove_slot(slot); + unmap: iounmap(host->ioaddr); @@ -437,7 +555,12 @@ release: static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) { sdhci_remove_host(slot->host); + + if (slot->chip->fixes && slot->chip->fixes->remove_slot) + slot->chip->fixes->remove_slot(slot); + pci_release_region(slot->chip->pdev, slot->pci_bar); + sdhci_free_host(slot->host); } diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 65953822c9cb..30153473bc37 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2188,6 +2188,7 @@ #define PCI_DEVICE_ID_JMICRON_JMB366 0x2366 #define PCI_DEVICE_ID_JMICRON_JMB368 0x2368 #define PCI_DEVICE_ID_JMICRON_JMB38X_SD 0x2381 +#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382 #define PCI_DEVICE_ID_JMICRON_JMB38X_MS 0x2383 #define PCI_VENDOR_ID_KORENIX 0x1982 -- cgit v1.2.3 From 150a55683b6b0ccb66aae75a10a3a514340c7c03 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Tue, 20 May 2008 00:57:27 +0300 Subject: include/linux/mmc/mmc.h: remove CVS tags This patch removes a CVS tag that wasn't updated for a long time. Signed-off-by: Adrian Bunk Signed-off-by: Pierre Ossman --- include/linux/mmc/mmc.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index 4236fbf0b6fb..14b81f3e5232 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h @@ -16,7 +16,6 @@ * Based strongly on code by: * * Author: Yong-iL Joh - * Date : $Date: 2002/06/18 12:37:30 $ * * Author: Andrew Christian * 15 May 2002 -- cgit v1.2.3 From 28f52482b41edc88cdf575aa6ed414c6e116ce10 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Tue, 17 Jun 2008 18:17:15 +0400 Subject: mmc: add support for card-detection polling Some hosts (and boards that use mmc_spi) do not use interrupts on the CD line, so they can't trigger mmc_detect_change. We want to poll the card and see if there was a change. 1 second poll interval seems resonable. This patch also implements .get_cd() host operation, that could be used by the hosts that are able to report card-detect status without need to talk MMC. Signed-off-by: Anton Vorontsov Signed-off-by: Pierre Ossman --- drivers/mmc/core/core.c | 12 +++++++++--- include/linux/mmc/host.h | 11 +++++++++++ 2 files changed, 20 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 01ced4c5a61d..ede5d1e2e20d 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -638,6 +638,9 @@ void mmc_rescan(struct work_struct *work) */ mmc_bus_put(host); + if (host->ops->get_cd && host->ops->get_cd(host) == 0) + goto out; + mmc_claim_host(host); mmc_power_up(host); @@ -652,7 +655,7 @@ void mmc_rescan(struct work_struct *work) if (!err) { if (mmc_attach_sdio(host, ocr)) mmc_power_off(host); - return; + goto out; } /* @@ -662,7 +665,7 @@ void mmc_rescan(struct work_struct *work) if (!err) { if (mmc_attach_sd(host, ocr)) mmc_power_off(host); - return; + goto out; } /* @@ -672,7 +675,7 @@ void mmc_rescan(struct work_struct *work) if (!err) { if (mmc_attach_mmc(host, ocr)) mmc_power_off(host); - return; + goto out; } mmc_release_host(host); @@ -683,6 +686,9 @@ void mmc_rescan(struct work_struct *work) mmc_bus_put(host); } +out: + if (host->caps & MMC_CAP_NEEDS_POLL) + mmc_schedule_delayed_work(&host->detect, HZ); } void mmc_start_host(struct mmc_host *host) diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 7ab962fa1d73..6188e19d2331 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -51,8 +51,18 @@ struct mmc_ios { struct mmc_host_ops { void (*request)(struct mmc_host *host, struct mmc_request *req); + /* + * Avoid calling these three functions too often or in a "fast path", + * since underlaying controller might implement them in an expensive + * and/or slow way. + * + * Also note that these functions might sleep, so don't call them + * in the atomic contexts! + */ void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); int (*get_ro)(struct mmc_host *host); + int (*get_cd)(struct mmc_host *host); + void (*enable_sdio_irq)(struct mmc_host *host, int enable); }; @@ -94,6 +104,7 @@ struct mmc_host { #define MMC_CAP_SD_HIGHSPEED (1 << 3) /* Can do SD high-speed timing */ #define MMC_CAP_SDIO_IRQ (1 << 4) /* Can signal pending SDIO IRQs */ #define MMC_CAP_SPI (1 << 5) /* Talks only SPI protocols */ +#define MMC_CAP_NEEDS_POLL (1 << 6) /* Needs polling for card-detection */ /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ -- cgit v1.2.3 From 619ef4b42128709de4d89d209b2c874f560deecd Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Tue, 17 Jun 2008 18:17:21 +0400 Subject: mmc_spi: add support for card-detection polling This patch adds new platform data variable "caps", so platforms could pass theirs capabilities into MMC core (for example, platforms without interrupt on the CD line will most probably want to pass MMC_CAP_NEEDS_POLL). New platform get_cd() callback provided to optimize polling. Signed-off-by: Anton Vorontsov Signed-off-by: Pierre Ossman --- drivers/mmc/host/mmc_spi.c | 19 +++++++++++++++++-- include/linux/spi/mmc_spi.h | 9 +++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c index 35508584ac2a..547eb857b1b3 100644 --- a/drivers/mmc/host/mmc_spi.c +++ b/drivers/mmc/host/mmc_spi.c @@ -1131,11 +1131,20 @@ static int mmc_spi_get_ro(struct mmc_host *mmc) return 0; } +static int mmc_spi_get_cd(struct mmc_host *mmc) +{ + struct mmc_spi_host *host = mmc_priv(mmc); + + if (host->pdata && host->pdata->get_cd) + return !!host->pdata->get_cd(mmc->parent); + return -ENOSYS; +} static const struct mmc_host_ops mmc_spi_ops = { .request = mmc_spi_request, .set_ios = mmc_spi_set_ios, .get_ro = mmc_spi_get_ro, + .get_cd = mmc_spi_get_cd, }; @@ -1319,17 +1328,23 @@ static int mmc_spi_probe(struct spi_device *spi) goto fail_glue_init; } + /* pass platform capabilities, if any */ + if (host->pdata) + mmc->caps |= host->pdata->caps; + status = mmc_add_host(mmc); if (status != 0) goto fail_add_host; - dev_info(&spi->dev, "SD/MMC host %s%s%s%s\n", + dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n", mmc->class_dev.bus_id, host->dma_dev ? "" : ", no DMA", (host->pdata && host->pdata->get_ro) ? "" : ", no WP", (host->pdata && host->pdata->setpower) - ? "" : ", no poweroff"); + ? "" : ", no poweroff", + (mmc->caps & MMC_CAP_NEEDS_POLL) + ? ", cd polling" : ""); return 0; fail_add_host: diff --git a/include/linux/spi/mmc_spi.h b/include/linux/spi/mmc_spi.h index d5ca78b93a3b..a3626aedaec9 100644 --- a/include/linux/spi/mmc_spi.h +++ b/include/linux/spi/mmc_spi.h @@ -23,6 +23,15 @@ struct mmc_spi_platform_data { /* sense switch on sd cards */ int (*get_ro)(struct device *); + /* + * If board does not use CD interrupts, driver can optimize polling + * using this function. + */ + int (*get_cd)(struct device *); + + /* Capabilities to pass into mmc core (e.g. MMC_CAP_NEEDS_POLL). */ + unsigned long caps; + /* how long to debounce card detect, in msecs */ u16 detect_delay; -- cgit v1.2.3 From 08f80bb5196517a0dfe50dc7c10f234c0ff2f0e8 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Tue, 17 Jun 2008 18:17:39 +0400 Subject: mmc: change .get_ro() callback semantics Now get_ro() callback must return 0/1 values for its logical states, and negative errno values in case of error. If particular host instance doesn't support RO/WP switch, it should return -ENOSYS. This patch changes some hosts in two ways: 1. Now functions should be smart to not return negative values in "RO asserted" case (particularly gpio_ calls could return negative values for the outermost GPIOs). Also, board code usually passes get_ro() callbacks that directly return gpioreg & bit result, so at91_mci, imxmmc, pxamci and mmc_spi's get_ro() handlers need take special care when returning platform's values to the mmc core. 2. In case of host instance didn't implement get_ro() callback, it should really return -ENOSYS and let the mmc core decide what to do about it (mmc core thinks the same way as the hosts, so it isn't functional change). Signed-off-by: Anton Vorontsov Signed-off-by: Pierre Ossman --- drivers/mmc/core/sd.c | 4 ++-- drivers/mmc/host/at91_mci.c | 18 +++++++----------- drivers/mmc/host/imxmmc.c | 9 ++++++--- drivers/mmc/host/mmc_spi.c | 9 ++++++--- drivers/mmc/host/pxamci.c | 9 ++++++--- drivers/mmc/host/wbsd.c | 2 +- include/linux/mmc/host.h | 12 ++++++++++++ 7 files changed, 40 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 7ef3b15c5e3d..b122eb9ea453 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -494,13 +494,13 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, * Check if read-only switch is active. */ if (!oldcard) { - if (!host->ops->get_ro) { + if (!host->ops->get_ro || host->ops->get_ro(host) < 0) { printk(KERN_WARNING "%s: host does not " "support reading read-only " "switch. assuming write-enable.\n", mmc_hostname(host)); } else { - if (host->ops->get_ro(host)) + if (host->ops->get_ro(host) > 0) mmc_card_set_readonly(card); } } diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 8979ad330a4d..b9d4ed6b29b1 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -793,19 +793,15 @@ static irqreturn_t at91_mmc_det_irq(int irq, void *_host) static int at91_mci_get_ro(struct mmc_host *mmc) { - int read_only = 0; struct at91mci_host *host = mmc_priv(mmc); - if (host->board->wp_pin) { - read_only = gpio_get_value(host->board->wp_pin); - printk(KERN_WARNING "%s: card is %s\n", mmc_hostname(mmc), - (read_only ? "read-only" : "read-write") ); - } - else { - printk(KERN_WARNING "%s: host does not support reading read-only " - "switch. Assuming write-enable.\n", mmc_hostname(mmc)); - } - return read_only; + if (host->board->wp_pin) + return !!gpio_get_value(host->board->wp_pin); + /* + * Board doesn't support read only detection; let the mmc core + * decide what to do. + */ + return -ENOSYS; } static const struct mmc_host_ops at91_mci_ops = { diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c index eed211b2ac70..5e880c0f1349 100644 --- a/drivers/mmc/host/imxmmc.c +++ b/drivers/mmc/host/imxmmc.c @@ -892,9 +892,12 @@ static int imxmci_get_ro(struct mmc_host *mmc) struct imxmci_host *host = mmc_priv(mmc); if (host->pdata && host->pdata->get_ro) - return host->pdata->get_ro(mmc_dev(mmc)); - /* Host doesn't support read only detection so assume writeable */ - return 0; + return !!host->pdata->get_ro(mmc_dev(mmc)); + /* + * Board doesn't support read only detection; let the mmc core + * decide what to do. + */ + return -ENOSYS; } diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c index 547eb857b1b3..4e82f64a96bc 100644 --- a/drivers/mmc/host/mmc_spi.c +++ b/drivers/mmc/host/mmc_spi.c @@ -1126,9 +1126,12 @@ static int mmc_spi_get_ro(struct mmc_host *mmc) struct mmc_spi_host *host = mmc_priv(mmc); if (host->pdata && host->pdata->get_ro) - return host->pdata->get_ro(mmc->parent); - /* board doesn't support read only detection; assume writeable */ - return 0; + return !!host->pdata->get_ro(mmc->parent); + /* + * Board doesn't support read only detection; let the mmc core + * decide what to do. + */ + return -ENOSYS; } static int mmc_spi_get_cd(struct mmc_host *mmc) diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c index d89475d36988..d39f59738866 100644 --- a/drivers/mmc/host/pxamci.c +++ b/drivers/mmc/host/pxamci.c @@ -374,9 +374,12 @@ static int pxamci_get_ro(struct mmc_host *mmc) struct pxamci_host *host = mmc_priv(mmc); if (host->pdata && host->pdata->get_ro) - return host->pdata->get_ro(mmc_dev(mmc)); - /* Host doesn't support read only detection so assume writeable */ - return 0; + return !!host->pdata->get_ro(mmc_dev(mmc)); + /* + * Board doesn't support read only detection; let the mmc core + * decide what to do. + */ + return -ENOSYS; } static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) diff --git a/drivers/mmc/host/wbsd.c b/drivers/mmc/host/wbsd.c index c303e7f57ab4..67e5a9b80f53 100644 --- a/drivers/mmc/host/wbsd.c +++ b/drivers/mmc/host/wbsd.c @@ -939,7 +939,7 @@ static int wbsd_get_ro(struct mmc_host *mmc) spin_unlock_bh(&host->lock); - return csr & WBSD_WRPT; + return !!(csr & WBSD_WRPT); } static const struct mmc_host_ops wbsd_ops = { diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 6188e19d2331..753b7231b887 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -58,6 +58,18 @@ struct mmc_host_ops { * * Also note that these functions might sleep, so don't call them * in the atomic contexts! + * + * Return values for the get_ro callback should be: + * 0 for a read/write card + * 1 for a read-only card + * -ENOSYS when not supported (equal to NULL callback) + * or a negative errno value when something bad happened + * + * Return values for the get_ro callback should be: + * 0 for a absent card + * 1 for a present card + * -ENOSYS when not supported (equal to NULL callback) + * or a negative errno value when something bad happened */ void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); int (*get_ro)(struct mmc_host *host); -- cgit v1.2.3 From c5a89c6c0805959f813e8342d6f4040860f6d7db Mon Sep 17 00:00:00 2001 From: Marc Pignat Date: Fri, 30 May 2008 14:07:47 +0200 Subject: mmc: at91_mci: avoid timeouts The at91 mci controller internal state machine seems to often crash. This can be fixed by resetting the controller after each command for at91rm9200 and by setting the MCI_BLKR register on at91sam926*. Signed-off-by: Marc Pignat Signed-off-by: Hans J Koch Signed-off-by: Nicolas Ferre Signed-off-by: Pierre Ossman --- drivers/mmc/host/at91_mci.c | 48 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91_mci.h | 4 +++ 2 files changed, 52 insertions(+) (limited to 'include') diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index fce171c7c67e..e9242110ce2e 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -130,6 +130,43 @@ struct at91mci_host struct timer_list timer; }; +/* + * Reset the controller and restore most of the state + */ +static void at91_reset_host(struct at91mci_host *host) +{ + unsigned long flags; + u32 mr; + u32 sdcr; + u32 dtor; + u32 imr; + + local_irq_save(flags); + imr = at91_mci_read(host, AT91_MCI_IMR); + + at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); + + /* save current state */ + mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; + sdcr = at91_mci_read(host, AT91_MCI_SDCR); + dtor = at91_mci_read(host, AT91_MCI_DTOR); + + /* reset the controller */ + at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); + + /* restore state */ + at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); + at91_mci_write(host, AT91_MCI_MR, mr); + at91_mci_write(host, AT91_MCI_SDCR, sdcr); + at91_mci_write(host, AT91_MCI_DTOR, dtor); + at91_mci_write(host, AT91_MCI_IER, imr); + + /* make sure sdio interrupts will fire */ + at91_mci_read(host, AT91_MCI_SR); + + local_irq_restore(flags); +} + static void at91_timeout_timer(unsigned long data) { struct at91mci_host *host; @@ -148,6 +185,7 @@ static void at91_timeout_timer(unsigned long data) host->request->cmd->error = -ETIMEDOUT; } + at91_reset_host(host); mmc_request_done(host->mmc, host->request); } } @@ -512,6 +550,11 @@ static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command mr |= AT91_MCI_PDCMODE; at91_mci_write(host, AT91_MCI_MR, mr); + if (!cpu_is_at91rm9200()) + at91_mci_write(host, AT91_MCI_BLKR, + AT91_MCI_BLKR_BCNT(blocks) | + AT91_MCI_BLKR_BLKLEN(block_length)); + /* * Disable the PDC controller */ @@ -584,6 +627,11 @@ static void at91_mci_process_next(struct at91mci_host *host) at91_mci_send_command(host, host->request->stop); } else { del_timer(&host->timer); + /* the at91rm9200 mci controller hangs after some transfers, + * and the workaround is to reset it after each transfer. + */ + if (cpu_is_at91rm9200()) + at91_reset_host(host); mmc_request_done(host->mmc, host->request); } } diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h index 1551fc24eb43..400ec10014b4 100644 --- a/include/asm-arm/arch-at91/at91_mci.h +++ b/include/asm-arm/arch-at91/at91_mci.h @@ -75,6 +75,10 @@ #define AT91_MCI_TRTYP_MULTIPLE (1 << 19) #define AT91_MCI_TRTYP_STREAM (2 << 19) +#define AT91_MCI_BLKR 0x18 /* Block Register */ +#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ +#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ + #define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ #define AT91_MCR_RDR 0x30 /* Receive Data Register */ #define AT91_MCR_TDR 0x34 /* Transmit Data Register */ -- cgit v1.2.3 From c4223c2c91fa9e5addd6eadd804e57a925ac5e5e Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Mon, 9 Jun 2008 08:36:13 +0200 Subject: au1xmmc: remove db1200 board code, rewrite probe. Remove the DB1200 board-specific functions (card present, read-only, activity LED methods) and instead add platform data which is passed to the driver. This also allows for platforms to implement other carddetect schemes (e.g. dedicated irq) without having to pollute the driver code. The poll timer (used for pb1200) is kept for compatibility. With the board-specific stuff gone, the driver's ->probe() code can be cleaned up considerably. Signed-off-by: Manuel Lauss Signed-off-by: Pierre Ossman --- drivers/mmc/host/au1xmmc.c | 573 ++++++++++++++++++------------ drivers/mmc/host/au1xmmc.h | 9 +- include/asm-mips/mach-au1x00/au1100_mmc.h | 18 +- 3 files changed, 354 insertions(+), 246 deletions(-) (limited to 'include') diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index cc5f7bc546af..d8776d61b3cc 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -41,8 +41,9 @@ #include #include #include - +#include #include + #include #include #include @@ -54,6 +55,7 @@ #define DRIVER_NAME "au1xxx-mmc" /* Set this to enable special debugging macros */ +/* #define DEBUG */ #ifdef DEBUG #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args) @@ -61,32 +63,6 @@ #define DBG(fmt, idx, args...) #endif -const struct { - u32 iobase; - u32 tx_devid, rx_devid; - u16 bcsrpwr; - u16 bcsrstatus; - u16 wpstatus; -} au1xmmc_card_table[] = { - { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0, - BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP }, -#ifndef CONFIG_MIPS_DB1200 - { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1, - BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP } -#endif -}; - -#define AU1XMMC_CONTROLLER_COUNT (ARRAY_SIZE(au1xmmc_card_table)) - -/* This array stores pointers for the hosts (used by the IRQ handler) */ -struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT]; -static int dma = 1; - -#ifdef MODULE -module_param(dma, bool, 0); -MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)"); -#endif - static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) { u32 val = au_readl(HOST_CONFIG(host)); @@ -135,26 +111,33 @@ static inline void SEND_STOP(struct au1xmmc_host *host) static void au1xmmc_set_power(struct au1xmmc_host *host, int state) { - - u32 val = au1xmmc_card_table[host->id].bcsrpwr; - - bcsr->board &= ~val; - if (state) bcsr->board |= val; - - au_sync_delay(1); + if (host->platdata && host->platdata->set_power) + host->platdata->set_power(host->mmc, state); } -static inline int au1xmmc_card_inserted(struct au1xmmc_host *host) +static int au1xmmc_card_inserted(struct au1xmmc_host *host) { - return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus) - ? 1 : 0; + int ret; + + if (host->platdata && host->platdata->card_inserted) + ret = host->platdata->card_inserted(host->mmc); + else + ret = 1; /* assume there is a card */ + + return ret; } static int au1xmmc_card_readonly(struct mmc_host *mmc) { struct au1xmmc_host *host = mmc_priv(mmc); - return (bcsr->status & au1xmmc_card_table[host->id].wpstatus) - ? 1 : 0; + int ret; + + if (host->platdata && host->platdata->card_readonly) + ret = host->platdata->card_readonly(mmc); + else + ret = 0; /* assume card is read-write */ + + return ret; } static void au1xmmc_finish_request(struct au1xmmc_host *host) @@ -163,7 +146,7 @@ static void au1xmmc_finish_request(struct au1xmmc_host *host) struct mmc_request *mrq = host->mrq; host->mrq = NULL; - host->flags &= HOST_F_ACTIVE; + host->flags &= HOST_F_ACTIVE | HOST_F_DMA; host->dma.len = 0; host->dma.dir = 0; @@ -174,8 +157,6 @@ static void au1xmmc_finish_request(struct au1xmmc_host *host) host->status = HOST_S_IDLE; - bcsr->disk_leds |= (1 << 8); - mmc_request_done(host->mmc, mrq); } @@ -299,11 +280,13 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) if (!data->error) { if (host->flags & HOST_F_DMA) { +#ifdef CONFIG_SOC_AU1200 /* DBDMA */ u32 chan = DMA_CHANNEL(host); chan_tab_t *c = *((chan_tab_t **) chan); au1x_dma_chan_t *cp = c->chan_ptr; data->bytes_xfered = cp->ddma_bytecnt; +#endif } else data->bytes_xfered = @@ -420,18 +403,18 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) break; if (status & SD_STATUS_RC) { - DBG("RX CRC Error [%d + %d].\n", host->id, + DBG("RX CRC Error [%d + %d].\n", host->pdev->id, host->pio.len, count); break; } if (status & SD_STATUS_RO) { - DBG("RX Overrun [%d + %d]\n", host->id, + DBG("RX Overrun [%d + %d]\n", host->pdev->id, host->pio.len, count); break; } else if (status & SD_STATUS_RU) { - DBG("RX Underrun [%d + %d]\n", host->id, + DBG("RX Underrun [%d + %d]\n", host->pdev->id, host->pio.len, count); break; } @@ -528,6 +511,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) host->status = HOST_S_DATA; if (host->flags & HOST_F_DMA) { +#ifdef CONFIG_SOC_AU1200 /* DBDMA */ u32 channel = DMA_CHANNEL(host); /* Start the DMA as soon as the buffer gets something in it */ @@ -540,6 +524,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) } au1xxx_dbdma_start(channel); +#endif } } @@ -571,12 +556,8 @@ static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) static int au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) { - int datalen = data->blocks * data->blksz; - if (dma != 0) - host->flags |= HOST_F_DMA; - if (data->flags & MMC_DATA_READ) host->flags |= HOST_F_RECV; else @@ -596,6 +577,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) au_writel(data->blksz - 1, HOST_BLKSIZE(host)); if (host->flags & HOST_F_DMA) { +#ifdef CONFIG_SOC_AU1200 /* DBDMA */ int i; u32 channel = DMA_CHANNEL(host); @@ -621,11 +603,12 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) len, flags); } - if (!ret) + if (!ret) goto dataerr; datalen -= len; } +#endif } else { host->pio.index = 0; @@ -641,8 +624,9 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) return 0; - dataerr: - dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir); +dataerr: + dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, + host->dma.dir); return -ETIMEDOUT; } @@ -663,8 +647,6 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) host->mrq = mrq; host->status = HOST_S_CMD; - bcsr->disk_leds &= ~(1 << 8); - if (mrq->data) { FLUSH_FIFO(host); flags = mrq->data->flags; @@ -728,149 +710,145 @@ static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios) } } -static void au1xmmc_dma_callback(int irq, void *dev_id) -{ - struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id; - - /* Avoid spurious interrupts */ - - if (!host->mrq) - return; - - if (host->flags & HOST_F_STOP) - SEND_STOP(host); - - tasklet_schedule(&host->data_task); -} - #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) #define STATUS_DATA_IN (SD_STATUS_NE) #define STATUS_DATA_OUT (SD_STATUS_TH) static irqreturn_t au1xmmc_irq(int irq, void *dev_id) { - + struct au1xmmc_host *host = dev_id; u32 status; - int i, ret = 0; - - disable_irq(AU1100_SD_IRQ); - for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { - struct au1xmmc_host * host = au1xmmc_hosts[i]; - u32 handled = 1; - - status = au_readl(HOST_STATUS(host)); + status = au_readl(HOST_STATUS(host)); - if (host->mrq && (status & STATUS_TIMEOUT)) { - if (status & SD_STATUS_RAT) - host->mrq->cmd->error = -ETIMEDOUT; + if (!(status & SD_STATUS_I)) + return IRQ_NONE; /* not ours */ - else if (status & SD_STATUS_DT) - host->mrq->data->error = -ETIMEDOUT; + if (host->mrq && (status & STATUS_TIMEOUT)) { + if (status & SD_STATUS_RAT) + host->mrq->cmd->error = -ETIMEDOUT; + else if (status & SD_STATUS_DT) + host->mrq->data->error = -ETIMEDOUT; - /* In PIO mode, interrupts might still be enabled */ - IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); + /* In PIO mode, interrupts might still be enabled */ + IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); - //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF); - tasklet_schedule(&host->finish_task); - } + /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */ + tasklet_schedule(&host->finish_task); + } #if 0 - else if (status & SD_STATUS_DD) { - - /* Sometimes we get a DD before a NE in PIO mode */ - - if (!(host->flags & HOST_F_DMA) && - (status & SD_STATUS_NE)) - au1xmmc_receive_pio(host); - else { - au1xmmc_data_complete(host, status); - //tasklet_schedule(&host->data_task); - } - } -#endif - else if (status & (SD_STATUS_CR)) { - if (host->status == HOST_S_CMD) - au1xmmc_cmd_complete(host,status); - } - else if (!(host->flags & HOST_F_DMA)) { - if ((host->flags & HOST_F_XMIT) && - (status & STATUS_DATA_OUT)) - au1xmmc_send_pio(host); - else if ((host->flags & HOST_F_RECV) && - (status & STATUS_DATA_IN)) - au1xmmc_receive_pio(host); - } - else if (status & 0x203FBC70) { - DBG("Unhandled status %8.8x\n", host->id, status); - handled = 0; + else if (status & SD_STATUS_DD) { + /* Sometimes we get a DD before a NE in PIO mode */ + if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE)) + au1xmmc_receive_pio(host); + else { + au1xmmc_data_complete(host, status); + /* tasklet_schedule(&host->data_task); */ } - - au_writel(status, HOST_STATUS(host)); - au_sync(); - - ret |= handled; } - - enable_irq(AU1100_SD_IRQ); - return ret; -} - -static void au1xmmc_poll_event(unsigned long arg) -{ - struct au1xmmc_host *host = (struct au1xmmc_host *) arg; - - int card = au1xmmc_card_inserted(host); - int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0; - - if (card != controller) { - host->flags &= ~HOST_F_ACTIVE; - if (card) host->flags |= HOST_F_ACTIVE; - mmc_detect_change(host->mmc, 0); +#endif + else if (status & SD_STATUS_CR) { + if (host->status == HOST_S_CMD) + au1xmmc_cmd_complete(host, status); + + } else if (!(host->flags & HOST_F_DMA)) { + if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) + au1xmmc_send_pio(host); + else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) + au1xmmc_receive_pio(host); + + } else if (status & 0x203F3C70) { + DBG("Unhandled status %8.8x\n", host->pdev->id, + status); } - if (host->mrq != NULL) { - u32 status = au_readl(HOST_STATUS(host)); - DBG("PENDING - %8.8x\n", host->id, status); - } + au_writel(status, HOST_STATUS(host)); + au_sync(); - mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT); + return IRQ_HANDLED; } -static dbdev_tab_t au1xmmc_mem_dbdev = -{ - DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0 +#ifdef CONFIG_SOC_AU1200 +/* 8bit memory DMA device */ +static dbdev_tab_t au1xmmc_mem_dbdev = { + .dev_id = DSCR_CMD0_ALWAYS, + .dev_flags = DEV_FLAGS_ANYUSE, + .dev_tsize = 0, + .dev_devwidth = 8, + .dev_physaddr = 0x00000000, + .dev_intlevel = 0, + .dev_intpolarity = 0, }; +static int memid; -static void au1xmmc_init_dma(struct au1xmmc_host *host) +static void au1xmmc_dbdma_callback(int irq, void *dev_id) { + struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id; - u32 rxchan, txchan; + /* Avoid spurious interrupts */ + if (!host->mrq) + return; - int txid = au1xmmc_card_table[host->id].tx_devid; - int rxid = au1xmmc_card_table[host->id].rx_devid; + if (host->flags & HOST_F_STOP) + SEND_STOP(host); - /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride - of 8 bits. And since devices are shared, we need to create - our own to avoid freaking out other devices - */ + tasklet_schedule(&host->data_task); +} - int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); +static int au1xmmc_dbdma_init(struct au1xmmc_host *host) +{ + struct resource *res; + int txid, rxid; + + res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0); + if (!res) + return -ENODEV; + txid = res->start; + + res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1); + if (!res) + return -ENODEV; + rxid = res->start; + + if (!memid) + return -ENODEV; + + host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid, + au1xmmc_dbdma_callback, (void *)host); + if (!host->tx_chan) { + dev_err(&host->pdev->dev, "cannot allocate TX DMA\n"); + return -ENODEV; + } + + host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid, + au1xmmc_dbdma_callback, (void *)host); + if (!host->rx_chan) { + dev_err(&host->pdev->dev, "cannot allocate RX DMA\n"); + au1xxx_dbdma_chan_free(host->tx_chan); + return -ENODEV; + } - txchan = au1xxx_dbdma_chan_alloc(memid, txid, - au1xmmc_dma_callback, (void *) host); + au1xxx_dbdma_set_devwidth(host->tx_chan, 8); + au1xxx_dbdma_set_devwidth(host->rx_chan, 8); - rxchan = au1xxx_dbdma_chan_alloc(rxid, memid, - au1xmmc_dma_callback, (void *) host); + au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT); + au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); - au1xxx_dbdma_set_devwidth(txchan, 8); - au1xxx_dbdma_set_devwidth(rxchan, 8); + /* DBDMA is good to go */ + host->flags |= HOST_F_DMA; - au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT); - au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT); + return 0; +} - host->tx_chan = txchan; - host->rx_chan = rxchan; +static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) +{ + if (host->flags & HOST_F_DMA) { + host->flags &= ~HOST_F_DMA; + au1xxx_dbdma_chan_free(host->tx_chan); + au1xxx_dbdma_chan_free(host->rx_chan); + } } +#endif static const struct mmc_host_ops au1xmmc_ops = { .request = au1xmmc_request, @@ -878,116 +856,235 @@ static const struct mmc_host_ops au1xmmc_ops = { .get_ro = au1xmmc_card_readonly, }; -static int __devinit au1xmmc_probe(struct platform_device *pdev) +static void au1xmmc_poll_event(unsigned long arg) { + struct au1xmmc_host *host = (struct au1xmmc_host *)arg; + int card = au1xmmc_card_inserted(host); + int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0; + + if (card != controller) { + host->flags &= ~HOST_F_ACTIVE; + if (card) + host->flags |= HOST_F_ACTIVE; + mmc_detect_change(host->mmc, 0); + } - int i, ret = 0; +#ifdef DEBUG + if (host->mrq != NULL) { + u32 status = au_readl(HOST_STATUS(host)); + DBG("PENDING - %8.8x\n", host->pdev->id, status); + } +#endif + mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT); +} - /* THe interrupt is shared among all controllers */ - ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, IRQF_DISABLED, "MMC", 0); +static void au1xmmc_init_cd_poll_timer(struct au1xmmc_host *host) +{ + init_timer(&host->timer); + host->timer.function = au1xmmc_poll_event; + host->timer.data = (unsigned long)host; + host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT; +} - if (ret) { - printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n", - AU1100_SD_IRQ, ret); - return -ENXIO; +static int __devinit au1xmmc_probe(struct platform_device *pdev) +{ + struct mmc_host *mmc; + struct au1xmmc_host *host; + struct resource *r; + int ret; + + mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); + if (!mmc) { + dev_err(&pdev->dev, "no memory for mmc_host\n"); + ret = -ENOMEM; + goto out0; } - disable_irq(AU1100_SD_IRQ); + host = mmc_priv(mmc); + host->mmc = mmc; + host->platdata = pdev->dev.platform_data; + host->pdev = pdev; - for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { - struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); - struct au1xmmc_host *host = 0; + ret = -ENODEV; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no mmio defined\n"); + goto out1; + } - if (!mmc) { - printk(DRIVER_NAME "ERROR: no mem for host %d\n", i); - au1xmmc_hosts[i] = 0; - continue; - } + host->ioarea = request_mem_region(r->start, r->end - r->start + 1, + pdev->name); + if (!host->ioarea) { + dev_err(&pdev->dev, "mmio already in use\n"); + goto out1; + } - mmc->ops = &au1xmmc_ops; + host->iobase = (unsigned long)ioremap(r->start, 0x3c); + if (!host->iobase) { + dev_err(&pdev->dev, "cannot remap mmio\n"); + goto out2; + } + + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!r) { + dev_err(&pdev->dev, "no IRQ defined\n"); + goto out3; + } - mmc->f_min = 450000; - mmc->f_max = 24000000; + host->irq = r->start; + /* IRQ is shared among both SD controllers */ + ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED, + DRIVER_NAME, host); + if (ret) { + dev_err(&pdev->dev, "cannot grab IRQ\n"); + goto out3; + } - mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; - mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; + mmc->ops = &au1xmmc_ops; - mmc->max_blk_size = 2048; - mmc->max_blk_count = 512; + mmc->f_min = 450000; + mmc->f_max = 24000000; - mmc->ocr_avail = AU1XMMC_OCR; + mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; + mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; - host = mmc_priv(mmc); - host->mmc = mmc; + mmc->max_blk_size = 2048; + mmc->max_blk_count = 512; - host->id = i; - host->iobase = au1xmmc_card_table[host->id].iobase; - host->clock = 0; - host->power_mode = MMC_POWER_OFF; + mmc->ocr_avail = AU1XMMC_OCR; + mmc->caps = 0; - host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0; - host->status = HOST_S_IDLE; + host->status = HOST_S_IDLE; - init_timer(&host->timer); + /* board-specific carddetect setup, if any */ + if (host->platdata && host->platdata->cd_setup) { + ret = host->platdata->cd_setup(mmc, 1); + if (ret) { + dev_err(&pdev->dev, "board CD setup failed\n"); + goto out4; + } + } else { + /* poll the board-specific is-card-in-socket-? method */ + au1xmmc_init_cd_poll_timer(host); + } - host->timer.function = au1xmmc_poll_event; - host->timer.data = (unsigned long) host; - host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT; + tasklet_init(&host->data_task, au1xmmc_tasklet_data, + (unsigned long)host); - tasklet_init(&host->data_task, au1xmmc_tasklet_data, - (unsigned long) host); + tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, + (unsigned long)host); - tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, - (unsigned long) host); +#ifdef CONFIG_SOC_AU1200 + ret = au1xmmc_dbdma_init(host); + if (ret) + printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n"); +#endif - spin_lock_init(&host->lock); +#ifdef CONFIG_LEDS_CLASS + if (host->platdata && host->platdata->led) { + struct led_classdev *led = host->platdata->led; + led->name = mmc_hostname(mmc); + led->brightness = LED_OFF; + led->default_trigger = mmc_hostname(mmc); + ret = led_classdev_register(mmc_dev(mmc), led); + if (ret) + goto out5; + } +#endif - if (dma != 0) - au1xmmc_init_dma(host); + au1xmmc_reset_controller(host); - au1xmmc_reset_controller(host); + ret = mmc_add_host(mmc); + if (ret) { + dev_err(&pdev->dev, "cannot add mmc host\n"); + goto out6; + } - mmc_add_host(mmc); - au1xmmc_hosts[i] = host; + platform_set_drvdata(pdev, mmc); + /* start the carddetect poll timer if necessary */ + if (!(host->platdata && host->platdata->cd_setup)) add_timer(&host->timer); - printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n", - host->id, host->iobase, dma ? "dma" : "pio"); - } + printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X" + " (mode=%s)\n", pdev->id, host->iobase, + host->flags & HOST_F_DMA ? "dma" : "pio"); - enable_irq(AU1100_SD_IRQ); + return 0; /* all ok */ - return 0; +out6: +#ifdef CONFIG_LEDS_CLASS + if (host->platdata && host->platdata->led) + led_classdev_unregister(host->platdata->led); +out5: +#endif + au_writel(0, HOST_ENABLE(host)); + au_writel(0, HOST_CONFIG(host)); + au_writel(0, HOST_CONFIG2(host)); + au_sync(); + +#ifdef CONFIG_SOC_AU1200 + au1xmmc_dbdma_shutdown(host); +#endif + + tasklet_kill(&host->data_task); + tasklet_kill(&host->finish_task); + + if (host->platdata && host->platdata->cd_setup) + host->platdata->cd_setup(mmc, 0); +out4: + free_irq(host->irq, host); +out3: + iounmap((void *)host->iobase); +out2: + release_resource(host->ioarea); + kfree(host->ioarea); +out1: + mmc_free_host(mmc); +out0: + return ret; } static int __devexit au1xmmc_remove(struct platform_device *pdev) { + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct au1xmmc_host *host; + + if (mmc) { + host = mmc_priv(mmc); + + mmc_remove_host(mmc); - int i; +#ifdef CONFIG_LEDS_CLASS + if (host->platdata && host->platdata->led) + led_classdev_unregister(host->platdata->led); +#endif - disable_irq(AU1100_SD_IRQ); + if (host->platdata && host->platdata->cd_setup) + host->platdata->cd_setup(mmc, 0); + else + del_timer_sync(&host->timer); - for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { - struct au1xmmc_host *host = au1xmmc_hosts[i]; - if (!host) continue; + au_writel(0, HOST_ENABLE(host)); + au_writel(0, HOST_CONFIG(host)); + au_writel(0, HOST_CONFIG2(host)); + au_sync(); tasklet_kill(&host->data_task); tasklet_kill(&host->finish_task); - del_timer_sync(&host->timer); +#ifdef CONFIG_SOC_AU1200 + au1xmmc_dbdma_shutdown(host); +#endif au1xmmc_set_power(host, 0); - mmc_remove_host(host->mmc); + free_irq(host->irq, host); + iounmap((void *)host->iobase); + release_resource(host->ioarea); + kfree(host->ioarea); - au1xxx_dbdma_chan_free(host->tx_chan); - au1xxx_dbdma_chan_free(host->rx_chan); - - au_writel(0x0, HOST_ENABLE(host)); - au_sync(); + mmc_free_host(mmc); } - - free_irq(AU1100_SD_IRQ, 0); return 0; } @@ -1004,21 +1101,31 @@ static struct platform_driver au1xmmc_driver = { static int __init au1xmmc_init(void) { +#ifdef CONFIG_SOC_AU1200 + /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride + * of 8 bits. And since devices are shared, we need to create + * our own to avoid freaking out other devices. + */ + memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); + if (!memid) + printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n"); +#endif return platform_driver_register(&au1xmmc_driver); } static void __exit au1xmmc_exit(void) { +#ifdef CONFIG_SOC_AU1200 + if (memid) + au1xxx_ddma_del_device(memid); +#endif platform_driver_unregister(&au1xmmc_driver); } module_init(au1xmmc_init); module_exit(au1xmmc_exit); -#ifdef MODULE MODULE_AUTHOR("Advanced Micro Devices, Inc"); MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:au1xxx-mmc"); -#endif - diff --git a/drivers/mmc/host/au1xmmc.h b/drivers/mmc/host/au1xmmc.h index 341cbdf0baca..3b400654e59c 100644 --- a/drivers/mmc/host/au1xmmc.h +++ b/drivers/mmc/host/au1xmmc.h @@ -49,8 +49,6 @@ struct au1xmmc_host { struct mmc_host *mmc; struct mmc_request *mrq; - u32 id; - u32 flags; u32 iobase; u32 clock; @@ -73,11 +71,14 @@ struct au1xmmc_host { u32 tx_chan; u32 rx_chan; + int irq; + struct timer_list timer; struct tasklet_struct finish_task; struct tasklet_struct data_task; - - spinlock_t lock; + struct au1xmmc_platform_data *platdata; + struct platform_device *pdev; + struct resource *ioarea; }; /* Status flags used by the host structure */ diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h index 9e0028f60a43..c35e20918490 100644 --- a/include/asm-mips/mach-au1x00/au1100_mmc.h +++ b/include/asm-mips/mach-au1x00/au1100_mmc.h @@ -38,15 +38,15 @@ #ifndef __ASM_AU1100_MMC_H #define __ASM_AU1100_MMC_H - -#define NUM_AU1100_MMC_CONTROLLERS 2 - -#if defined(CONFIG_SOC_AU1100) -#define AU1100_SD_IRQ AU1100_SD_INT -#elif defined(CONFIG_SOC_AU1200) -#define AU1100_SD_IRQ AU1200_SD_INT -#endif - +#include + +struct au1xmmc_platform_data { + int(*cd_setup)(void *mmc_host, int on); + int(*card_inserted)(void *mmc_host); + int(*card_readonly)(void *mmc_host); + void(*set_power)(void *mmc_host, int state); + struct led_classdev *led; +}; #define SD0_BASE 0xB0600000 #define SD1_BASE 0xB0680000 -- cgit v1.2.3 From ad3868b2ec96ec14a1549c9e33f5f9a2a3c6ab15 Mon Sep 17 00:00:00 2001 From: Pierre Ossman Date: Sat, 28 Jun 2008 12:52:45 +0200 Subject: mmc,sdio: helper function for transfer padding There are a lot of crappy controllers out there that cannot handle all the request sizes that the MMC/SD/SDIO specifications require. In case the card driver can pad the data to overcome the problems, this commit adds a helper that calculates how much that padding should be. A corresponding helper is also added for SDIO, but it can also deal with all the complexities of splitting up a large transfer efficiently. Signed-off-by: Pierre Ossman --- drivers/mmc/core/core.c | 29 +++++++++- drivers/mmc/core/sdio_io.c | 99 ++++++++++++++++++++++++++++++++- drivers/net/wireless/libertas/if_sdio.c | 20 +++---- include/linux/mmc/core.h | 1 + include/linux/mmc/sdio_func.h | 4 +- 5 files changed, 137 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index ede5d1e2e20d..3ee5b8c3b5ce 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -3,7 +3,7 @@ * * Copyright (C) 2003-2004 Russell King, All Rights Reserved. * SD support Copyright (C) 2004 Ian Molton, All Rights Reserved. - * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved. + * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. * MMCv4 support Copyright (C) 2006 Philip Langdale, All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -294,6 +294,33 @@ void mmc_set_data_timeout(struct mmc_data *data, const struct mmc_card *card) } EXPORT_SYMBOL(mmc_set_data_timeout); +/** + * mmc_align_data_size - pads a transfer size to a more optimal value + * @card: the MMC card associated with the data transfer + * @sz: original transfer size + * + * Pads the original data size with a number of extra bytes in + * order to avoid controller bugs and/or performance hits + * (e.g. some controllers revert to PIO for certain sizes). + * + * Returns the improved size, which might be unmodified. + * + * Note that this function is only relevant when issuing a + * single scatter gather entry. + */ +unsigned int mmc_align_data_size(struct mmc_card *card, unsigned int sz) +{ + /* + * FIXME: We don't have a system for the controller to tell + * the core about its problems yet, so for now we just 32-bit + * align the size. + */ + sz = ((sz + 3) / 4) * 4; + + return sz; +} +EXPORT_SYMBOL(mmc_align_data_size); + /** * __mmc_claim_host - exclusively claim a host * @host: mmc host to claim diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c index 625b92ce9cef..6ee7861fceae 100644 --- a/drivers/mmc/core/sdio_io.c +++ b/drivers/mmc/core/sdio_io.c @@ -1,7 +1,7 @@ /* * linux/drivers/mmc/core/sdio_io.c * - * Copyright 2007 Pierre Ossman + * Copyright 2007-2008 Pierre Ossman * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -189,6 +189,103 @@ int sdio_set_block_size(struct sdio_func *func, unsigned blksz) EXPORT_SYMBOL_GPL(sdio_set_block_size); +/** + * sdio_align_size - pads a transfer size to a more optimal value + * @func: SDIO function + * @sz: original transfer size + * + * Pads the original data size with a number of extra bytes in + * order to avoid controller bugs and/or performance hits + * (e.g. some controllers revert to PIO for certain sizes). + * + * If possible, it will also adjust the size so that it can be + * handled in just a single request. + * + * Returns the improved size, which might be unmodified. + */ +unsigned int sdio_align_size(struct sdio_func *func, unsigned int sz) +{ + unsigned int orig_sz; + unsigned int blk_sz, byte_sz; + unsigned chunk_sz; + + orig_sz = sz; + + /* + * Do a first check with the controller, in case it + * wants to increase the size up to a point where it + * might need more than one block. + */ + sz = mmc_align_data_size(func->card, sz); + + /* + * If we can still do this with just a byte transfer, then + * we're done. + */ + if ((sz <= func->cur_blksize) && (sz <= 512)) + return sz; + + if (func->card->cccr.multi_block) { + /* + * Check if the transfer is already block aligned + */ + if ((sz % func->cur_blksize) == 0) + return sz; + + /* + * Realign it so that it can be done with one request, + * and recheck if the controller still likes it. + */ + blk_sz = ((sz + func->cur_blksize - 1) / + func->cur_blksize) * func->cur_blksize; + blk_sz = mmc_align_data_size(func->card, blk_sz); + + /* + * This value is only good if it is still just + * one request. + */ + if ((blk_sz % func->cur_blksize) == 0) + return blk_sz; + + /* + * We failed to do one request, but at least try to + * pad the remainder properly. + */ + byte_sz = mmc_align_data_size(func->card, + sz % func->cur_blksize); + if ((byte_sz <= func->cur_blksize) && (byte_sz <= 512)) { + blk_sz = sz / func->cur_blksize; + return blk_sz * func->cur_blksize + byte_sz; + } + } else { + /* + * We need multiple requests, so first check that the + * controller can handle the chunk size; + */ + chunk_sz = mmc_align_data_size(func->card, + min(func->cur_blksize, 512u)); + if (chunk_sz == min(func->cur_blksize, 512u)) { + /* + * Fix up the size of the remainder (if any) + */ + byte_sz = orig_sz % chunk_sz; + if (byte_sz) { + byte_sz = mmc_align_data_size(func->card, + byte_sz); + } + + return (orig_sz / chunk_sz) * chunk_sz + byte_sz; + } + } + + /* + * The controller is simply incapable of transferring the size + * we want in decent manner, so just return the original size. + */ + return orig_sz; +} +EXPORT_SYMBOL_GPL(sdio_align_size); + /* Split an arbitrarily sized data transfer into several * IO_RW_EXTENDED commands. */ static int sdio_io_rw_ext_helper(struct sdio_func *func, int write, diff --git a/drivers/net/wireless/libertas/if_sdio.c b/drivers/net/wireless/libertas/if_sdio.c index 3dd537be87d8..b54e2ea8346b 100644 --- a/drivers/net/wireless/libertas/if_sdio.c +++ b/drivers/net/wireless/libertas/if_sdio.c @@ -1,7 +1,7 @@ /* * linux/drivers/net/wireless/libertas/if_sdio.c * - * Copyright 2007 Pierre Ossman + * Copyright 2007-2008 Pierre Ossman * * Inspired by if_cs.c, Copyright 2007 Holger Schurig * @@ -266,13 +266,10 @@ static int if_sdio_card_to_host(struct if_sdio_card *card) /* * The transfer must be in one transaction or the firmware - * goes suicidal. + * goes suicidal. There's no way to guarantee that for all + * controllers, but we can at least try. */ - chunk = size; - if ((chunk > card->func->cur_blksize) || (chunk > 512)) { - chunk = (chunk + card->func->cur_blksize - 1) / - card->func->cur_blksize * card->func->cur_blksize; - } + chunk = sdio_align_size(card->func, size); ret = sdio_readsb(card->func, card->buffer, card->ioport, chunk); if (ret) @@ -696,13 +693,10 @@ static int if_sdio_host_to_card(struct lbs_private *priv, /* * The transfer must be in one transaction or the firmware - * goes suicidal. + * goes suicidal. There's no way to guarantee that for all + * controllers, but we can at least try. */ - size = nb + 4; - if ((size > card->func->cur_blksize) || (size > 512)) { - size = (size + card->func->cur_blksize - 1) / - card->func->cur_blksize * card->func->cur_blksize; - } + size = sdio_align_size(card->func, nb + 4); packet = kzalloc(sizeof(struct if_sdio_packet) + size, GFP_ATOMIC); diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index d0c3abed74c2..143cebf0586f 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -135,6 +135,7 @@ extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *, struct mmc_command *, int); extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *); +extern unsigned int mmc_align_data_size(struct mmc_card *, unsigned int); extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort); extern void mmc_release_host(struct mmc_host *host); diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h index b050f4d7b41f..f57f22b3be88 100644 --- a/include/linux/mmc/sdio_func.h +++ b/include/linux/mmc/sdio_func.h @@ -1,7 +1,7 @@ /* * include/linux/mmc/sdio_func.h * - * Copyright 2007 Pierre Ossman + * Copyright 2007-2008 Pierre Ossman * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -120,6 +120,8 @@ extern int sdio_set_block_size(struct sdio_func *func, unsigned blksz); extern int sdio_claim_irq(struct sdio_func *func, sdio_irq_handler_t *handler); extern int sdio_release_irq(struct sdio_func *func); +extern unsigned int sdio_align_size(struct sdio_func *func, unsigned int sz); + extern unsigned char sdio_readb(struct sdio_func *func, unsigned int addr, int *err_ret); extern unsigned short sdio_readw(struct sdio_func *func, -- cgit v1.2.3 From be518018c6b9224c02284fb243207ef741c31ec6 Mon Sep 17 00:00:00 2001 From: Thomas Kleffel Date: Mon, 30 Jun 2008 22:40:24 +0100 Subject: MMC: S3C24XX MMC/SD driver. This is the latest S3C MMC/SD driver by Thomas Kleffel with cleanups as suggested by AKPM done by Ben Dooks. Signed-off-by: Ben Dooks Signed-off-by: Thomas Kleffel Signed-off-by: Pierre Ossman --- drivers/mmc/host/Kconfig | 11 + drivers/mmc/host/Makefile | 2 +- drivers/mmc/host/s3cmci.c | 1343 +++++++++++++++++++++++++++++++ drivers/mmc/host/s3cmci.h | 69 ++ include/asm-arm/arch-s3c2410/regs-sdi.h | 20 +- 5 files changed, 1441 insertions(+), 4 deletions(-) create mode 100644 drivers/mmc/host/s3cmci.c create mode 100644 drivers/mmc/host/s3cmci.h (limited to 'include') diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index f9cbcb891e99..dc88c03662ab 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -143,3 +143,14 @@ config MMC_SPI If unsure, or if your system has no SPI master driver, say N. +config MMC_S3C + tristate "Samsung S3C SD/MMC Card Interface support" + depends on ARCH_S3C2410 && MMC + help + This selects a driver for the MCI interface found in + Samsung's S3C2410, S3C2412, S3C2440, S3C2442 CPUs. + If you have a board based on one of those and a MMC/SD + slot, say Y or M here. + + If unsure, say N. + diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 3027250b8555..b3e023bf8c78 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -18,4 +18,4 @@ obj-$(CONFIG_MMC_OMAP) += omap.o obj-$(CONFIG_MMC_AT91) += at91_mci.o obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o obj-$(CONFIG_MMC_SPI) += mmc_spi.o - +obj-$(CONFIG_MMC_S3C) += s3cmci.o diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c new file mode 100644 index 000000000000..c6a4d3cadf2b --- /dev/null +++ b/drivers/mmc/host/s3cmci.c @@ -0,0 +1,1343 @@ +/* + * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver + * + * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include "s3cmci.h" + +#define DRIVER_NAME "s3c-mci" + +enum dbg_channels { + dbg_err = (1 << 0), + dbg_debug = (1 << 1), + dbg_info = (1 << 2), + dbg_irq = (1 << 3), + dbg_sg = (1 << 4), + dbg_dma = (1 << 5), + dbg_pio = (1 << 6), + dbg_fail = (1 << 7), + dbg_conf = (1 << 8), +}; + +static const int dbgmap_err = dbg_err | dbg_fail; +static const int dbgmap_info = dbg_info | dbg_conf; +static const int dbgmap_debug = dbg_debug; + +#define dbg(host, channels, args...) \ + do { \ + if (dbgmap_err & channels) \ + dev_err(&host->pdev->dev, args); \ + else if (dbgmap_info & channels) \ + dev_info(&host->pdev->dev, args); \ + else if (dbgmap_debug & channels) \ + dev_dbg(&host->pdev->dev, args); \ + } while (0) + +#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1) + +static struct s3c2410_dma_client s3cmci_dma_client = { + .name = "s3c-mci", +}; + +static void finalize_request(struct s3cmci_host *host); +static void s3cmci_send_request(struct mmc_host *mmc); +static void s3cmci_reset(struct s3cmci_host *host); + +#ifdef CONFIG_MMC_DEBUG + +static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) +{ + u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize; + u32 datcon, datcnt, datsta, fsta, imask; + + con = readl(host->base + S3C2410_SDICON); + pre = readl(host->base + S3C2410_SDIPRE); + cmdarg = readl(host->base + S3C2410_SDICMDARG); + cmdcon = readl(host->base + S3C2410_SDICMDCON); + cmdsta = readl(host->base + S3C2410_SDICMDSTAT); + r0 = readl(host->base + S3C2410_SDIRSP0); + r1 = readl(host->base + S3C2410_SDIRSP1); + r2 = readl(host->base + S3C2410_SDIRSP2); + r3 = readl(host->base + S3C2410_SDIRSP3); + timer = readl(host->base + S3C2410_SDITIMER); + bsize = readl(host->base + S3C2410_SDIBSIZE); + datcon = readl(host->base + S3C2410_SDIDCON); + datcnt = readl(host->base + S3C2410_SDIDCNT); + datsta = readl(host->base + S3C2410_SDIDSTA); + fsta = readl(host->base + S3C2410_SDIFSTA); + imask = readl(host->base + host->sdiimsk); + + dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n", + prefix, con, pre, timer); + + dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n", + prefix, cmdcon, cmdarg, cmdsta); + + dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]" + " DSTA:[%08x] DCNT:[%08x]\n", + prefix, datcon, fsta, datsta, datcnt); + + dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]" + " R2:[%08x] R3:[%08x]\n", + prefix, r0, r1, r2, r3); +} + +static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, + int stop) +{ + snprintf(host->dbgmsg_cmd, 300, + "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u", + host->ccnt, (stop ? " (STOP)" : ""), + cmd->opcode, cmd->arg, cmd->flags, cmd->retries); + + if (cmd->data) { + snprintf(host->dbgmsg_dat, 300, + "#%u bsize:%u blocks:%u bytes:%u", + host->dcnt, cmd->data->blksz, + cmd->data->blocks, + cmd->data->blocks * cmd->data->blksz); + } else { + host->dbgmsg_dat[0] = '\0'; + } +} + +static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd, + int fail) +{ + unsigned int dbglvl = fail ? dbg_fail : dbg_debug; + + if (!cmd) + return; + + if (cmd->error == 0) { + dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n", + host->dbgmsg_cmd, cmd->resp[0]); + } else { + dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n", + cmd->error, host->dbgmsg_cmd, host->status); + } + + if (!cmd->data) + return; + + if (cmd->data->error == 0) { + dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat); + } else { + dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n", + cmd->data->error, host->dbgmsg_dat, + readl(host->base + S3C2410_SDIDCNT)); + } +} +#else +static void dbg_dumpcmd(struct s3cmci_host *host, + struct mmc_command *cmd, int fail) { } + +static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, + int stop) { } + +static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { } + +#endif /* CONFIG_MMC_DEBUG */ + +static inline u32 enable_imask(struct s3cmci_host *host, u32 imask) +{ + u32 newmask; + + newmask = readl(host->base + host->sdiimsk); + newmask |= imask; + + writel(newmask, host->base + host->sdiimsk); + + return newmask; +} + +static inline u32 disable_imask(struct s3cmci_host *host, u32 imask) +{ + u32 newmask; + + newmask = readl(host->base + host->sdiimsk); + newmask &= ~imask; + + writel(newmask, host->base + host->sdiimsk); + + return newmask; +} + +static inline void clear_imask(struct s3cmci_host *host) +{ + writel(0, host->base + host->sdiimsk); +} + +static inline int get_data_buffer(struct s3cmci_host *host, + u32 *words, u32 **pointer) +{ + struct scatterlist *sg; + + if (host->pio_active == XFER_NONE) + return -EINVAL; + + if ((!host->mrq) || (!host->mrq->data)) + return -EINVAL; + + if (host->pio_sgptr >= host->mrq->data->sg_len) { + dbg(host, dbg_debug, "no more buffers (%i/%i)\n", + host->pio_sgptr, host->mrq->data->sg_len); + return -EBUSY; + } + sg = &host->mrq->data->sg[host->pio_sgptr]; + + *words = sg->length >> 2; + *pointer = sg_virt(sg); + + host->pio_sgptr++; + + dbg(host, dbg_sg, "new buffer (%i/%i)\n", + host->pio_sgptr, host->mrq->data->sg_len); + + return 0; +} + +static inline u32 fifo_count(struct s3cmci_host *host) +{ + u32 fifostat = readl(host->base + S3C2410_SDIFSTA); + + fifostat &= S3C2410_SDIFSTA_COUNTMASK; + return fifostat >> 2; +} + +static inline u32 fifo_free(struct s3cmci_host *host) +{ + u32 fifostat = readl(host->base + S3C2410_SDIFSTA); + + fifostat &= S3C2410_SDIFSTA_COUNTMASK; + return (63 - fifostat) >> 2; +} + +static void do_pio_read(struct s3cmci_host *host) +{ + int res; + u32 fifo; + void __iomem *from_ptr; + + /* write real prescaler to host, it might be set slow to fix */ + writel(host->prescaler, host->base + S3C2410_SDIPRE); + + from_ptr = host->base + host->sdidata; + + while ((fifo = fifo_count(host))) { + if (!host->pio_words) { + res = get_data_buffer(host, &host->pio_words, + &host->pio_ptr); + if (res) { + host->pio_active = XFER_NONE; + host->complete_what = COMPLETION_FINALIZE; + + dbg(host, dbg_pio, "pio_read(): " + "complete (no more data).\n"); + return; + } + + dbg(host, dbg_pio, + "pio_read(): new target: [%i]@[%p]\n", + host->pio_words, host->pio_ptr); + } + + dbg(host, dbg_pio, + "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n", + fifo, host->pio_words, + readl(host->base + S3C2410_SDIDCNT)); + + if (fifo > host->pio_words) + fifo = host->pio_words; + + host->pio_words -= fifo; + host->pio_count += fifo; + + while (fifo--) + *(host->pio_ptr++) = readl(from_ptr); + } + + if (!host->pio_words) { + res = get_data_buffer(host, &host->pio_words, &host->pio_ptr); + if (res) { + dbg(host, dbg_pio, + "pio_read(): complete (no more buffers).\n"); + host->pio_active = XFER_NONE; + host->complete_what = COMPLETION_FINALIZE; + + return; + } + } + + enable_imask(host, + S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST); +} + +static void do_pio_write(struct s3cmci_host *host) +{ + void __iomem *to_ptr; + int res; + u32 fifo; + + to_ptr = host->base + host->sdidata; + + while ((fifo = fifo_free(host))) { + if (!host->pio_words) { + res = get_data_buffer(host, &host->pio_words, + &host->pio_ptr); + if (res) { + dbg(host, dbg_pio, + "pio_write(): complete (no more data).\n"); + host->pio_active = XFER_NONE; + + return; + } + + dbg(host, dbg_pio, + "pio_write(): new source: [%i]@[%p]\n", + host->pio_words, host->pio_ptr); + + } + + if (fifo > host->pio_words) + fifo = host->pio_words; + + host->pio_words -= fifo; + host->pio_count += fifo; + + while (fifo--) + writel(*(host->pio_ptr++), to_ptr); + } + + enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); +} + +static void pio_tasklet(unsigned long data) +{ + struct s3cmci_host *host = (struct s3cmci_host *) data; + + + if (host->pio_active == XFER_WRITE) + do_pio_write(host); + + if (host->pio_active == XFER_READ) + do_pio_read(host); + + if (host->complete_what == COMPLETION_FINALIZE) { + clear_imask(host); + if (host->pio_active != XFER_NONE) { + dbg(host, dbg_err, "unfinished %s " + "- pio_count:[%u] pio_words:[%u]\n", + (host->pio_active == XFER_READ) ? "read" : "write", + host->pio_count, host->pio_words); + + host->mrq->data->error = -EINVAL; + } + + disable_irq(host->irq); + finalize_request(host); + } +} + +/* + * ISR for SDI Interface IRQ + * Communication between driver and ISR works as follows: + * host->mrq points to current request + * host->complete_what Indicates when the request is considered done + * COMPLETION_CMDSENT when the command was sent + * COMPLETION_RSPFIN when a response was received + * COMPLETION_XFERFINISH when the data transfer is finished + * COMPLETION_XFERFINISH_RSPFIN both of the above. + * host->complete_request is the completion-object the driver waits for + * + * 1) Driver sets up host->mrq and host->complete_what + * 2) Driver prepares the transfer + * 3) Driver enables interrupts + * 4) Driver starts transfer + * 5) Driver waits for host->complete_rquest + * 6) ISR checks for request status (errors and success) + * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error + * 7) ISR completes host->complete_request + * 8) ISR disables interrupts + * 9) Driver wakes up and takes care of the request + * + * Note: "->error"-fields are expected to be set to 0 before the request + * was issued by mmc.c - therefore they are only set, when an error + * contition comes up + */ + +static irqreturn_t s3cmci_irq(int irq, void *dev_id) +{ + struct s3cmci_host *host = dev_id; + struct mmc_command *cmd; + u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk; + u32 mci_cclear, mci_dclear; + unsigned long iflags; + + spin_lock_irqsave(&host->complete_lock, iflags); + + mci_csta = readl(host->base + S3C2410_SDICMDSTAT); + mci_dsta = readl(host->base + S3C2410_SDIDSTA); + mci_dcnt = readl(host->base + S3C2410_SDIDCNT); + mci_fsta = readl(host->base + S3C2410_SDIFSTA); + mci_imsk = readl(host->base + host->sdiimsk); + mci_cclear = 0; + mci_dclear = 0; + + if ((host->complete_what == COMPLETION_NONE) || + (host->complete_what == COMPLETION_FINALIZE)) { + host->status = "nothing to complete"; + clear_imask(host); + goto irq_out; + } + + if (!host->mrq) { + host->status = "no active mrq"; + clear_imask(host); + goto irq_out; + } + + cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd; + + if (!cmd) { + host->status = "no active cmd"; + clear_imask(host); + goto irq_out; + } + + if (!host->dodma) { + if ((host->pio_active == XFER_WRITE) && + (mci_fsta & S3C2410_SDIFSTA_TFDET)) { + + disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); + tasklet_schedule(&host->pio_tasklet); + host->status = "pio tx"; + } + + if ((host->pio_active == XFER_READ) && + (mci_fsta & S3C2410_SDIFSTA_RFDET)) { + + disable_imask(host, + S3C2410_SDIIMSK_RXFIFOHALF | + S3C2410_SDIIMSK_RXFIFOLAST); + + tasklet_schedule(&host->pio_tasklet); + host->status = "pio rx"; + } + } + + if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) { + cmd->error = -ETIMEDOUT; + host->status = "error: command timeout"; + goto fail_transfer; + } + + if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) { + if (host->complete_what == COMPLETION_CMDSENT) { + host->status = "ok: command sent"; + goto close_transfer; + } + + mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT; + } + + if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) { + if (cmd->flags & MMC_RSP_CRC) { + cmd->error = -EILSEQ; + host->status = "error: bad command crc"; + goto fail_transfer; + } + + mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL; + } + + if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) { + if (host->complete_what == COMPLETION_RSPFIN) { + host->status = "ok: command response received"; + goto close_transfer; + } + + if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) + host->complete_what = COMPLETION_XFERFINISH; + + mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN; + } + + /* errors handled after this point are only relevant + when a data transfer is in progress */ + + if (!cmd->data) + goto clear_status_bits; + + /* Check for FIFO failure */ + if (host->is2440) { + if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) { + host->mrq->data->error = -EILSEQ; + host->status = "error: 2440 fifo failure"; + goto fail_transfer; + } + } else { + if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) { + cmd->data->error = -EILSEQ; + host->status = "error: fifo failure"; + goto fail_transfer; + } + } + + if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) { + cmd->data->error = -EILSEQ; + host->status = "error: bad data crc (outgoing)"; + goto fail_transfer; + } + + if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) { + cmd->data->error = -EILSEQ; + host->status = "error: bad data crc (incoming)"; + goto fail_transfer; + } + + if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) { + cmd->data->error = -ETIMEDOUT; + host->status = "error: data timeout"; + goto fail_transfer; + } + + if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) { + if (host->complete_what == COMPLETION_XFERFINISH) { + host->status = "ok: data transfer completed"; + goto close_transfer; + } + + if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) + host->complete_what = COMPLETION_RSPFIN; + + mci_dclear |= S3C2410_SDIDSTA_XFERFINISH; + } + +clear_status_bits: + writel(mci_cclear, host->base + S3C2410_SDICMDSTAT); + writel(mci_dclear, host->base + S3C2410_SDIDSTA); + + goto irq_out; + +fail_transfer: + host->pio_active = XFER_NONE; + +close_transfer: + host->complete_what = COMPLETION_FINALIZE; + + clear_imask(host); + tasklet_schedule(&host->pio_tasklet); + + goto irq_out; + +irq_out: + dbg(host, dbg_irq, + "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n", + mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status); + + spin_unlock_irqrestore(&host->complete_lock, iflags); + return IRQ_HANDLED; + +} + +/* + * ISR for the CardDetect Pin +*/ + +static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id) +{ + struct s3cmci_host *host = (struct s3cmci_host *)dev_id; + + dbg(host, dbg_irq, "card detect\n"); + + mmc_detect_change(host->mmc, 500); + + return IRQ_HANDLED; +} + +void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch, void *buf_id, + int size, enum s3c2410_dma_buffresult result) +{ + struct s3cmci_host *host = buf_id; + unsigned long iflags; + u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt; + + mci_csta = readl(host->base + S3C2410_SDICMDSTAT); + mci_dsta = readl(host->base + S3C2410_SDIDSTA); + mci_fsta = readl(host->base + S3C2410_SDIFSTA); + mci_dcnt = readl(host->base + S3C2410_SDIDCNT); + + BUG_ON(!host->mrq); + BUG_ON(!host->mrq->data); + BUG_ON(!host->dmatogo); + + spin_lock_irqsave(&host->complete_lock, iflags); + + if (result != S3C2410_RES_OK) { + dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x " + "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n", + mci_csta, mci_dsta, mci_fsta, + mci_dcnt, result, host->dmatogo); + + goto fail_request; + } + + host->dmatogo--; + if (host->dmatogo) { + dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] " + "DCNT:[%08x] toGo:%u\n", + size, mci_dsta, mci_dcnt, host->dmatogo); + + goto out; + } + + dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n", + size, mci_dsta, mci_dcnt); + + host->complete_what = COMPLETION_FINALIZE; + +out: + tasklet_schedule(&host->pio_tasklet); + spin_unlock_irqrestore(&host->complete_lock, iflags); + return; + + +fail_request: + host->mrq->data->error = -EINVAL; + host->complete_what = COMPLETION_FINALIZE; + writel(0, host->base + host->sdiimsk); + goto out; + +} + +static void finalize_request(struct s3cmci_host *host) +{ + struct mmc_request *mrq = host->mrq; + struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; + int debug_as_failure = 0; + + if (host->complete_what != COMPLETION_FINALIZE) + return; + + if (!mrq) + return; + + if (cmd->data && (cmd->error == 0) && + (cmd->data->error == 0)) { + if (host->dodma && (!host->dma_complete)) { + dbg(host, dbg_dma, "DMA Missing!\n"); + return; + } + } + + /* Read response from controller. */ + cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0); + cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1); + cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2); + cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3); + + writel(host->prescaler, host->base + S3C2410_SDIPRE); + + if (cmd->error) + debug_as_failure = 1; + + if (cmd->data && cmd->data->error) + debug_as_failure = 1; + + dbg_dumpcmd(host, cmd, debug_as_failure); + + /* Cleanup controller */ + writel(0, host->base + S3C2410_SDICMDARG); + writel(0, host->base + S3C2410_SDIDCON); + writel(0, host->base + S3C2410_SDICMDCON); + writel(0, host->base + host->sdiimsk); + + if (cmd->data && cmd->error) + cmd->data->error = cmd->error; + + if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) { + host->cmd_is_stop = 1; + s3cmci_send_request(host->mmc); + return; + } + + /* If we have no data transfer we are finished here */ + if (!mrq->data) + goto request_done; + + /* Calulate the amout of bytes transfer if there was no error */ + if (mrq->data->error == 0) { + mrq->data->bytes_xfered = + (mrq->data->blocks * mrq->data->blksz); + } else { + mrq->data->bytes_xfered = 0; + } + + /* If we had an error while transfering data we flush the + * DMA channel and the fifo to clear out any garbage. */ + if (mrq->data->error != 0) { + if (host->dodma) + s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); + + if (host->is2440) { + /* Clear failure register and reset fifo. */ + writel(S3C2440_SDIFSTA_FIFORESET | + S3C2440_SDIFSTA_FIFOFAIL, + host->base + S3C2410_SDIFSTA); + } else { + u32 mci_con; + + /* reset fifo */ + mci_con = readl(host->base + S3C2410_SDICON); + mci_con |= S3C2410_SDICON_FIFORESET; + + writel(mci_con, host->base + S3C2410_SDICON); + } + } + +request_done: + host->complete_what = COMPLETION_NONE; + host->mrq = NULL; + mmc_request_done(host->mmc, mrq); +} + + +void s3cmci_dma_setup(struct s3cmci_host *host, enum s3c2410_dmasrc source) +{ + static enum s3c2410_dmasrc last_source = -1; + static int setup_ok; + + if (last_source == source) + return; + + last_source = source; + + s3c2410_dma_devconfig(host->dma, source, 3, + host->mem->start + host->sdidata); + + if (!setup_ok) { + s3c2410_dma_config(host->dma, 4, + (S3C2410_DCON_HWTRIG | S3C2410_DCON_CH0_SDI)); + s3c2410_dma_set_buffdone_fn(host->dma, + s3cmci_dma_done_callback); + s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART); + setup_ok = 1; + } +} + +static void s3cmci_send_command(struct s3cmci_host *host, + struct mmc_command *cmd) +{ + u32 ccon, imsk; + + imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT | + S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT | + S3C2410_SDIIMSK_RESPONSECRC; + + enable_imask(host, imsk); + + if (cmd->data) + host->complete_what = COMPLETION_XFERFINISH_RSPFIN; + else if (cmd->flags & MMC_RSP_PRESENT) + host->complete_what = COMPLETION_RSPFIN; + else + host->complete_what = COMPLETION_CMDSENT; + + writel(cmd->arg, host->base + S3C2410_SDICMDARG); + + ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX; + ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART; + + if (cmd->flags & MMC_RSP_PRESENT) + ccon |= S3C2410_SDICMDCON_WAITRSP; + + if (cmd->flags & MMC_RSP_136) + ccon |= S3C2410_SDICMDCON_LONGRSP; + + writel(ccon, host->base + S3C2410_SDICMDCON); +} + +static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data) +{ + u32 dcon, imsk, stoptries = 3; + + /* write DCON register */ + + if (!data) { + writel(0, host->base + S3C2410_SDIDCON); + return 0; + } + + while (readl(host->base + S3C2410_SDIDSTA) & + (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) { + + dbg(host, dbg_err, + "mci_setup_data() transfer stillin progress.\n"); + + writel(0, host->base + S3C2410_SDIDCON); + s3cmci_reset(host); + + if ((stoptries--) == 0) { + dbg_dumpregs(host, "DRF"); + return -EINVAL; + } + } + + dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK; + + if (host->dodma) + dcon |= S3C2410_SDIDCON_DMAEN; + + if (host->bus_width == MMC_BUS_WIDTH_4) + dcon |= S3C2410_SDIDCON_WIDEBUS; + + if (!(data->flags & MMC_DATA_STREAM)) + dcon |= S3C2410_SDIDCON_BLOCKMODE; + + if (data->flags & MMC_DATA_WRITE) { + dcon |= S3C2410_SDIDCON_TXAFTERRESP; + dcon |= S3C2410_SDIDCON_XFER_TXSTART; + } + + if (data->flags & MMC_DATA_READ) { + dcon |= S3C2410_SDIDCON_RXAFTERCMD; + dcon |= S3C2410_SDIDCON_XFER_RXSTART; + } + + if (host->is2440) { + dcon |= S3C2440_SDIDCON_DS_WORD; + dcon |= S3C2440_SDIDCON_DATSTART; + } + + writel(dcon, host->base + S3C2410_SDIDCON); + + /* write BSIZE register */ + + writel(data->blksz, host->base + S3C2410_SDIBSIZE); + + /* add to IMASK register */ + imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC | + S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH; + + enable_imask(host, imsk); + + /* write TIMER register */ + + if (host->is2440) { + writel(0x007FFFFF, host->base + S3C2410_SDITIMER); + } else { + writel(0x0000FFFF, host->base + S3C2410_SDITIMER); + + /* FIX: set slow clock to prevent timeouts on read */ + if (data->flags & MMC_DATA_READ) + writel(0xFF, host->base + S3C2410_SDIPRE); + } + + return 0; +} + +#define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ) + +static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data) +{ + int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; + + BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); + + host->pio_sgptr = 0; + host->pio_words = 0; + host->pio_count = 0; + host->pio_active = rw ? XFER_WRITE : XFER_READ; + + if (rw) { + do_pio_write(host); + enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); + } else { + enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF + | S3C2410_SDIIMSK_RXFIFOLAST); + } + + return 0; +} + +static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data) +{ + int dma_len, i; + int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; + + BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); + + s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW); + s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); + + dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, + (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); + + if (dma_len == 0) + return -ENOMEM; + + host->dma_complete = 0; + host->dmatogo = dma_len; + + for (i = 0; i < dma_len; i++) { + int res; + + dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i, + sg_dma_address(&data->sg[i]), + sg_dma_len(&data->sg[i])); + + res = s3c2410_dma_enqueue(host->dma, (void *) host, + sg_dma_address(&data->sg[i]), + sg_dma_len(&data->sg[i])); + + if (res) { + s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); + return -EBUSY; + } + } + + s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START); + + return 0; +} + +static void s3cmci_send_request(struct mmc_host *mmc) +{ + struct s3cmci_host *host = mmc_priv(mmc); + struct mmc_request *mrq = host->mrq; + struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; + + host->ccnt++; + prepare_dbgmsg(host, cmd, host->cmd_is_stop); + + /* Clear command, data and fifo status registers + Fifo clear only necessary on 2440, but doesn't hurt on 2410 + */ + writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT); + writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA); + writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA); + + if (cmd->data) { + int res = s3cmci_setup_data(host, cmd->data); + + host->dcnt++; + + if (res) { + cmd->error = -EINVAL; + cmd->data->error = -EINVAL; + + mmc_request_done(mmc, mrq); + return; + } + + if (host->dodma) + res = s3cmci_prepare_dma(host, cmd->data); + else + res = s3cmci_prepare_pio(host, cmd->data); + + if (res) { + cmd->error = res; + cmd->data->error = res; + + mmc_request_done(mmc, mrq); + return; + } + } + + /* Send command */ + s3cmci_send_command(host, cmd); + + /* Enable Interrupt */ + enable_irq(host->irq); +} + +static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct s3cmci_host *host = mmc_priv(mmc); + + host->status = "mmc request"; + host->cmd_is_stop = 0; + host->mrq = mrq; + + s3cmci_send_request(mmc); +} + +static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct s3cmci_host *host = mmc_priv(mmc); + u32 mci_psc, mci_con; + + /* Set the power state */ + + mci_con = readl(host->base + S3C2410_SDICON); + + switch (ios->power_mode) { + case MMC_POWER_ON: + case MMC_POWER_UP: + s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK); + s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD); + s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0); + s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); + s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2); + s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3); + + if (!host->is2440) + mci_con |= S3C2410_SDICON_FIFORESET; + + break; + + case MMC_POWER_OFF: + default: + s3c2410_gpio_setpin(S3C2410_GPE5, 0); + s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_OUTP); + + if (host->is2440) + mci_con |= S3C2440_SDICON_SDRESET; + + break; + } + + /* Set clock */ + for (mci_psc = 0; mci_psc < 255; mci_psc++) { + host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1)); + + if (host->real_rate <= ios->clock) + break; + } + + if (mci_psc > 255) + mci_psc = 255; + + host->prescaler = mci_psc; + writel(host->prescaler, host->base + S3C2410_SDIPRE); + + /* If requested clock is 0, real_rate will be 0, too */ + if (ios->clock == 0) + host->real_rate = 0; + + /* Set CLOCK_ENABLE */ + if (ios->clock) + mci_con |= S3C2410_SDICON_CLOCKTYPE; + else + mci_con &= ~S3C2410_SDICON_CLOCKTYPE; + + writel(mci_con, host->base + S3C2410_SDICON); + + if ((ios->power_mode == MMC_POWER_ON) || + (ios->power_mode == MMC_POWER_UP)) { + dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n", + host->real_rate/1000, ios->clock/1000); + } else { + dbg(host, dbg_conf, "powered down.\n"); + } + + host->bus_width = ios->bus_width; +} + +static void s3cmci_reset(struct s3cmci_host *host) +{ + u32 con = readl(host->base + S3C2410_SDICON); + + con |= S3C2440_SDICON_SDRESET; + writel(con, host->base + S3C2410_SDICON); +} + +static struct mmc_host_ops s3cmci_ops = { + .request = s3cmci_request, + .set_ios = s3cmci_set_ios, +}; + +static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) +{ + struct s3cmci_host *host; + struct mmc_host *mmc; + int ret; + + mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev); + if (!mmc) { + ret = -ENOMEM; + goto probe_out; + } + + host = mmc_priv(mmc); + host->mmc = mmc; + host->pdev = pdev; + host->is2440 = is2440; + + spin_lock_init(&host->complete_lock); + tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host); + + if (is2440) { + host->sdiimsk = S3C2440_SDIIMSK; + host->sdidata = S3C2440_SDIDATA; + host->clk_div = 1; + } else { + host->sdiimsk = S3C2410_SDIIMSK; + host->sdidata = S3C2410_SDIDATA; + host->clk_div = 2; + } + + host->dodma = 0; + host->complete_what = COMPLETION_NONE; + host->pio_active = XFER_NONE; + + host->dma = S3CMCI_DMA; + host->irq_cd = IRQ_EINT2; + + host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!host->mem) { + dev_err(&pdev->dev, + "failed to get io memory region resouce.\n"); + + ret = -ENOENT; + goto probe_free_host; + } + + host->mem = request_mem_region(host->mem->start, + RESSIZE(host->mem), pdev->name); + + if (!host->mem) { + dev_err(&pdev->dev, "failed to request io memory region.\n"); + ret = -ENOENT; + goto probe_free_host; + } + + host->base = ioremap(host->mem->start, RESSIZE(host->mem)); + if (host->base == 0) { + dev_err(&pdev->dev, "failed to ioremap() io memory region.\n"); + ret = -EINVAL; + goto probe_free_mem_region; + } + + host->irq = platform_get_irq(pdev, 0); + if (host->irq == 0) { + dev_err(&pdev->dev, "failed to get interrupt resouce.\n"); + ret = -EINVAL; + goto probe_iounmap; + } + + if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) { + dev_err(&pdev->dev, "failed to request mci interrupt.\n"); + ret = -ENOENT; + goto probe_iounmap; + } + + /* We get spurious interrupts even when we have set the IMSK + * register to ignore everything, so use disable_irq() to make + * ensure we don't lock the system with un-serviceable requests. */ + + disable_irq(host->irq); + + s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_EINT2); + set_irq_type(host->irq_cd, IRQT_BOTHEDGE); + + if (request_irq(host->irq_cd, s3cmci_irq_cd, 0, DRIVER_NAME, host)) { + dev_err(&pdev->dev, + "failed to request card detect interrupt.\n"); + ret = -ENOENT; + goto probe_free_irq; + } + + if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL)) { + dev_err(&pdev->dev, "unable to get DMA channel.\n"); + ret = -EBUSY; + goto probe_free_irq_cd; + } + + host->clk = clk_get(&pdev->dev, "sdi"); + if (IS_ERR(host->clk)) { + dev_err(&pdev->dev, "failed to find clock source.\n"); + ret = PTR_ERR(host->clk); + host->clk = NULL; + goto probe_free_host; + } + + ret = clk_enable(host->clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable clock source.\n"); + goto clk_free; + } + + host->clk_rate = clk_get_rate(host->clk); + + mmc->ops = &s3cmci_ops; + mmc->ocr_avail = MMC_VDD_32_33; + mmc->caps = MMC_CAP_4_BIT_DATA; + mmc->f_min = host->clk_rate / (host->clk_div * 256); + mmc->f_max = host->clk_rate / host->clk_div; + + mmc->max_blk_count = 4095; + mmc->max_blk_size = 4095; + mmc->max_req_size = 4095 * 512; + mmc->max_seg_size = mmc->max_req_size; + + mmc->max_phys_segs = 128; + mmc->max_hw_segs = 128; + + dbg(host, dbg_debug, + "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n", + (host->is2440?"2440":""), + host->base, host->irq, host->irq_cd, host->dma); + + ret = mmc_add_host(mmc); + if (ret) { + dev_err(&pdev->dev, "failed to add mmc host.\n"); + goto free_dmabuf; + } + + platform_set_drvdata(pdev, mmc); + dev_info(&pdev->dev, "initialisation done.\n"); + + return 0; + + free_dmabuf: + clk_disable(host->clk); + + clk_free: + clk_put(host->clk); + + probe_free_irq_cd: + free_irq(host->irq_cd, host); + + probe_free_irq: + free_irq(host->irq, host); + + probe_iounmap: + iounmap(host->base); + + probe_free_mem_region: + release_mem_region(host->mem->start, RESSIZE(host->mem)); + + probe_free_host: + mmc_free_host(mmc); + probe_out: + return ret; +} + +static int __devexit s3cmci_remove(struct platform_device *pdev) +{ + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct s3cmci_host *host = mmc_priv(mmc); + + mmc_remove_host(mmc); + + clk_disable(host->clk); + clk_put(host->clk); + + tasklet_disable(&host->pio_tasklet); + + free_irq(host->irq_cd, host); + free_irq(host->irq, host); + + iounmap(host->base); + release_mem_region(host->mem->start, RESSIZE(host->mem)); + + mmc_free_host(mmc); + return 0; +} + +static int __devinit s3cmci_probe_2410(struct platform_device *dev) +{ + return s3cmci_probe(dev, 0); +} + +static int __devinit s3cmci_probe_2412(struct platform_device *dev) +{ + return s3cmci_probe(dev, 1); +} + +static int __devinit s3cmci_probe_2440(struct platform_device *dev) +{ + return s3cmci_probe(dev, 1); +} + +#ifdef CONFIG_PM + +static int s3cmci_suspend(struct platform_device *dev, pm_message_t state) +{ + struct mmc_host *mmc = platform_get_drvdata(dev); + + return mmc_suspend_host(mmc, state); +} + +static int s3cmci_resume(struct platform_device *dev) +{ + struct mmc_host *mmc = platform_get_drvdata(dev); + + return mmc_resume_host(mmc); +} + +#else /* CONFIG_PM */ +#define s3cmci_suspend NULL +#define s3cmci_resume NULL +#endif /* CONFIG_PM */ + + +static struct platform_driver s3cmci_driver_2410 = { + .driver.name = "s3c2410-sdi", + .driver.owner = THIS_MODULE, + .probe = s3cmci_probe_2410, + .remove = __devexit_p(s3cmci_remove), + .suspend = s3cmci_suspend, + .resume = s3cmci_resume, +}; + +static struct platform_driver s3cmci_driver_2412 = { + .driver.name = "s3c2412-sdi", + .driver.owner = THIS_MODULE, + .probe = s3cmci_probe_2412, + .remove = __devexit_p(s3cmci_remove), + .suspend = s3cmci_suspend, + .resume = s3cmci_resume, +}; + +static struct platform_driver s3cmci_driver_2440 = { + .driver.name = "s3c2440-sdi", + .driver.owner = THIS_MODULE, + .probe = s3cmci_probe_2440, + .remove = __devexit_p(s3cmci_remove), + .suspend = s3cmci_suspend, + .resume = s3cmci_resume, +}; + + +static int __init s3cmci_init(void) +{ + platform_driver_register(&s3cmci_driver_2410); + platform_driver_register(&s3cmci_driver_2412); + platform_driver_register(&s3cmci_driver_2440); + return 0; +} + +static void __exit s3cmci_exit(void) +{ + platform_driver_unregister(&s3cmci_driver_2410); + platform_driver_unregister(&s3cmci_driver_2412); + platform_driver_unregister(&s3cmci_driver_2440); +} + +module_init(s3cmci_init); +module_exit(s3cmci_exit); + +MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Thomas Kleffel "); diff --git a/drivers/mmc/host/s3cmci.h b/drivers/mmc/host/s3cmci.h new file mode 100644 index 000000000000..90b8af7d8a46 --- /dev/null +++ b/drivers/mmc/host/s3cmci.h @@ -0,0 +1,69 @@ +/* + * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver + * + * Copyright (C) 2004-2006 Thomas Kleffel, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* FIXME: DMA Resource management ?! */ +#define S3CMCI_DMA 0 + +enum s3cmci_waitfor { + COMPLETION_NONE, + COMPLETION_FINALIZE, + COMPLETION_CMDSENT, + COMPLETION_RSPFIN, + COMPLETION_XFERFINISH, + COMPLETION_XFERFINISH_RSPFIN, +}; + +struct s3cmci_host { + struct platform_device *pdev; + struct mmc_host *mmc; + struct resource *mem; + struct clk *clk; + void __iomem *base; + int irq; + int irq_cd; + int dma; + + unsigned long clk_rate; + unsigned long clk_div; + unsigned long real_rate; + u8 prescaler; + + int is2440; + unsigned sdiimsk; + unsigned sdidata; + int dodma; + int dmatogo; + + struct mmc_request *mrq; + int cmd_is_stop; + + spinlock_t complete_lock; + enum s3cmci_waitfor complete_what; + + int dma_complete; + + u32 pio_sgptr; + u32 pio_words; + u32 pio_count; + u32 *pio_ptr; +#define XFER_NONE 0 +#define XFER_READ 1 +#define XFER_WRITE 2 + u32 pio_active; + + int bus_width; + + char dbgmsg_cmd[301]; + char dbgmsg_dat[301]; + char *status; + + unsigned int ccnt, dcnt; + struct tasklet_struct pio_tasklet; +}; diff --git a/include/asm-arm/arch-s3c2410/regs-sdi.h b/include/asm-arm/arch-s3c2410/regs-sdi.h index bb9d30b72952..bfb222fa4abb 100644 --- a/include/asm-arm/arch-s3c2410/regs-sdi.h +++ b/include/asm-arm/arch-s3c2410/regs-sdi.h @@ -28,9 +28,15 @@ #define S3C2410_SDIDCNT (0x30) #define S3C2410_SDIDSTA (0x34) #define S3C2410_SDIFSTA (0x38) + #define S3C2410_SDIDATA (0x3C) #define S3C2410_SDIIMSK (0x40) +#define S3C2440_SDIDATA (0x40) +#define S3C2440_SDIIMSK (0x3C) + +#define S3C2440_SDICON_SDRESET (1<<8) +#define S3C2440_SDICON_MMCCLOCK (1<<5) #define S3C2410_SDICON_BYTEORDER (1<<4) #define S3C2410_SDICON_SDIOIRQ (1<<3) #define S3C2410_SDICON_RWAITEN (1<<2) @@ -42,7 +48,8 @@ #define S3C2410_SDICMDCON_LONGRSP (1<<10) #define S3C2410_SDICMDCON_WAITRSP (1<<9) #define S3C2410_SDICMDCON_CMDSTART (1<<8) -#define S3C2410_SDICMDCON_INDEX (0xff) +#define S3C2410_SDICMDCON_SENDERHOST (1<<6) +#define S3C2410_SDICMDCON_INDEX (0x3f) #define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) #define S3C2410_SDICMDSTAT_CMDSENT (1<<11) @@ -51,6 +58,9 @@ #define S3C2410_SDICMDSTAT_XFERING (1<<8) #define S3C2410_SDICMDSTAT_INDEX (0xff) +#define S3C2440_SDIDCON_DS_BYTE (0<<22) +#define S3C2440_SDIDCON_DS_HALFWORD (1<<22) +#define S3C2440_SDIDCON_DS_WORD (2<<22) #define S3C2410_SDIDCON_IRQPERIOD (1<<21) #define S3C2410_SDIDCON_TXAFTERRESP (1<<20) #define S3C2410_SDIDCON_RXAFTERCMD (1<<19) @@ -59,6 +69,7 @@ #define S3C2410_SDIDCON_WIDEBUS (1<<16) #define S3C2410_SDIDCON_DMAEN (1<<15) #define S3C2410_SDIDCON_STOP (1<<14) +#define S3C2440_SDIDCON_DATSTART (1<<14) #define S3C2410_SDIDCON_DATMODE (3<<12) #define S3C2410_SDIDCON_BLKNUM (0x7ff) @@ -68,6 +79,7 @@ #define S3C2410_SDIDCON_XFER_RXSTART (2<<12) #define S3C2410_SDIDCON_XFER_TXSTART (3<<12) +#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) #define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) #define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) @@ -82,10 +94,12 @@ #define S3C2410_SDIDSTA_TXDATAON (1<<1) #define S3C2410_SDIDSTA_RXDATAON (1<<0) +#define S3C2440_SDIFSTA_FIFORESET (1<<16) +#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ #define S3C2410_SDIFSTA_TFDET (1<<13) #define S3C2410_SDIFSTA_RFDET (1<<12) -#define S3C2410_SDIFSTA_TXHALF (1<<11) -#define S3C2410_SDIFSTA_TXEMPTY (1<<10) +#define S3C2410_SDIFSTA_TFHALF (1<<11) +#define S3C2410_SDIFSTA_TFEMPTY (1<<10) #define S3C2410_SDIFSTA_RFLAST (1<<9) #define S3C2410_SDIFSTA_RFFULL (1<<8) #define S3C2410_SDIFSTA_RFHALF (1<<7) -- cgit v1.2.3 From edb5a98e43682d66c98ddd1dee863d867807546e Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 30 Jun 2008 22:40:29 +0100 Subject: MMC: S3C24XX: Add platform data for MMC/SD driver This patch adds platform data support to the s3mci driver. This allows flexible board-specific configuration of set_power, card detect and read only pins. Signed-off-by: Ben Dooks Signed-off-by: Pierre Ossman --- drivers/mmc/host/s3cmci.c | 44 +++++++++++++++++++++++++++++++++++--- drivers/mmc/host/s3cmci.h | 1 + include/asm-arm/plat-s3c24xx/mci.h | 12 +++++++++++ 3 files changed, 54 insertions(+), 3 deletions(-) create mode 100644 include/asm-arm/plat-s3c24xx/mci.h (limited to 'include') diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index 774af3d7218f..684a10ca2e8f 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c @@ -21,6 +21,8 @@ #include #include +#include + #include "s3cmci.h" #define DRIVER_NAME "s3c-mci" @@ -1011,6 +1013,9 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2); s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3); + if (host->pdata->set_power) + host->pdata->set_power(ios->power_mode, ios->vdd); + if (!host->is2440) mci_con |= S3C2410_SDICON_FIFORESET; @@ -1024,6 +1029,9 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (host->is2440) mci_con |= S3C2440_SDICON_SDRESET; + if (host->pdata->set_power) + host->pdata->set_power(ios->power_mode, ios->vdd); + break; } @@ -1072,9 +1080,25 @@ static void s3cmci_reset(struct s3cmci_host *host) writel(con, host->base + S3C2410_SDICON); } +static int s3cmci_get_ro(struct mmc_host *mmc) +{ + struct s3cmci_host *host = mmc_priv(mmc); + + if (host->pdata->gpio_wprotect == 0) + return 0; + + return s3c2410_gpio_getpin(host->pdata->gpio_wprotect); +} + static struct mmc_host_ops s3cmci_ops = { .request = s3cmci_request, .set_ios = s3cmci_set_ios, + .get_ro = s3cmci_get_ro, +}; + +static struct s3c24xx_mci_pdata s3cmci_def_pdata = { + /* This is currently here to avoid a number of if (host->pdata) + * checks. Any zero fields to ensure reaonable defaults are picked. */ }; static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) @@ -1094,6 +1118,12 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) host->pdev = pdev; host->is2440 = is2440; + host->pdata = pdev->dev.platform_data; + if (!host->pdata) { + pdev->dev.platform_data = &s3cmci_def_pdata; + host->pdata = &s3cmci_def_pdata; + } + spin_lock_init(&host->complete_lock); tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host); @@ -1112,7 +1142,8 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) host->pio_active = XFER_NONE; host->dma = S3CMCI_DMA; - host->irq_cd = IRQ_EINT2; + host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect); + s3c2410_gpio_cfgpin(host->pdata->gpio_detect, S3C2410_GPIO_IRQ); host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!host->mem) { @@ -1158,7 +1189,7 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) disable_irq(host->irq); - s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_EINT2); + s3c2410_gpio_cfgpin(host->pdata->gpio_detect, S3C2410_GPIO_IRQ); set_irq_type(host->irq_cd, IRQT_BOTHEDGE); if (request_irq(host->irq_cd, s3cmci_irq_cd, 0, DRIVER_NAME, host)) { @@ -1168,6 +1199,10 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) goto probe_free_irq; } + if (host->pdata->gpio_wprotect) + s3c2410_gpio_cfgpin(host->pdata->gpio_wprotect, + S3C2410_GPIO_INPUT); + if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL)) { dev_err(&pdev->dev, "unable to get DMA channel.\n"); ret = -EBUSY; @@ -1191,11 +1226,14 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) host->clk_rate = clk_get_rate(host->clk); mmc->ops = &s3cmci_ops; - mmc->ocr_avail = MMC_VDD_32_33; + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; mmc->caps = MMC_CAP_4_BIT_DATA; mmc->f_min = host->clk_rate / (host->clk_div * 256); mmc->f_max = host->clk_rate / host->clk_div; + if (host->pdata->ocr_avail) + mmc->ocr_avail = host->pdata->ocr_avail; + mmc->max_blk_count = 4095; mmc->max_blk_size = 4095; mmc->max_req_size = 4095 * 512; diff --git a/drivers/mmc/host/s3cmci.h b/drivers/mmc/host/s3cmci.h index 90b8af7d8a46..37d9c60010c9 100644 --- a/drivers/mmc/host/s3cmci.h +++ b/drivers/mmc/host/s3cmci.h @@ -22,6 +22,7 @@ enum s3cmci_waitfor { struct s3cmci_host { struct platform_device *pdev; + struct s3c24xx_mci_pdata *pdata; struct mmc_host *mmc; struct resource *mem; struct clk *clk; diff --git a/include/asm-arm/plat-s3c24xx/mci.h b/include/asm-arm/plat-s3c24xx/mci.h new file mode 100644 index 000000000000..5be2c1449c6d --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/mci.h @@ -0,0 +1,12 @@ +#ifndef _ARCH_MCI_H +#define _ARCH_MCI_H + +struct s3c24xx_mci_pdata { + unsigned int gpio_detect; + unsigned int gpio_wprotect; + unsigned long ocr_avail; + void (*set_power)(unsigned char power_mode, + unsigned short vdd); +}; + +#endif /* _ARCH_NCI_H */ -- cgit v1.2.3 From cf0984c8edf63017fcc2ead212ca057877e345df Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 30 Jun 2008 22:40:30 +0100 Subject: MMC: S3C24XX: Add support to invert write protect line Support for inverting the sense of the MMC driver's write protect detection line. Signed-off-by: Ben Dooks Signed-off-by: Pierre Ossman --- drivers/mmc/host/s3cmci.c | 11 +++++++++-- include/asm-arm/plat-s3c24xx/mci.h | 2 ++ 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index 684a10ca2e8f..4fd11d8864eb 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c @@ -1083,11 +1083,18 @@ static void s3cmci_reset(struct s3cmci_host *host) static int s3cmci_get_ro(struct mmc_host *mmc) { struct s3cmci_host *host = mmc_priv(mmc); + struct s3c24xx_mci_pdata *pdata = host->pdata; + int ret; - if (host->pdata->gpio_wprotect == 0) + if (pdata->gpio_wprotect == 0) return 0; - return s3c2410_gpio_getpin(host->pdata->gpio_wprotect); + ret = s3c2410_gpio_getpin(pdata->gpio_wprotect); + + if (pdata->wprotect_invert) + ret = !ret; + + return ret; } static struct mmc_host_ops s3cmci_ops = { diff --git a/include/asm-arm/plat-s3c24xx/mci.h b/include/asm-arm/plat-s3c24xx/mci.h index 5be2c1449c6d..4f4ccd18f0cb 100644 --- a/include/asm-arm/plat-s3c24xx/mci.h +++ b/include/asm-arm/plat-s3c24xx/mci.h @@ -2,6 +2,8 @@ #define _ARCH_MCI_H struct s3c24xx_mci_pdata { + unsigned int wprotect_invert : 1; + unsigned int gpio_detect; unsigned int gpio_wprotect; unsigned long ocr_avail; -- cgit v1.2.3 From 50a845700b3b55f825b0eb901b03d6091f66d9f4 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 30 Jun 2008 22:40:36 +0100 Subject: MMC: S3C24XX: Add media presence test to request handling. Ensure that we have physical media present before attempting to send a request to a card. This ensures that we do not get flooded by errors from commands that can never be completed timing out. Signed-off-by: Ben Dooks Signed-off-by: Pierre Ossman --- drivers/mmc/host/s3cmci.c | 19 ++++++++++++++++++- include/asm-arm/plat-s3c24xx/mci.h | 1 + 2 files changed, 19 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index 6f1b474e33b9..62d73d3497f0 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c @@ -984,6 +984,18 @@ static void s3cmci_send_request(struct mmc_host *mmc) enable_irq(host->irq); } +static int s3cmci_card_present(struct s3cmci_host *host) +{ + struct s3c24xx_mci_pdata *pdata = host->pdata; + int ret; + + if (pdata->gpio_detect == 0) + return -ENOSYS; + + ret = s3c2410_gpio_getpin(pdata->gpio_detect) ? 0 : 1; + return ret ^ pdata->detect_invert; +} + static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq) { struct s3cmci_host *host = mmc_priv(mmc); @@ -992,7 +1004,12 @@ static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq) host->cmd_is_stop = 0; host->mrq = mrq; - s3cmci_send_request(mmc); + if (s3cmci_card_present(host) == 0) { + dbg(host, dbg_err, "%s: no medium present\n", __func__); + host->mrq->cmd->error = -ENOMEDIUM; + mmc_request_done(mmc, mrq); + } else + s3cmci_send_request(mmc); } static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) diff --git a/include/asm-arm/plat-s3c24xx/mci.h b/include/asm-arm/plat-s3c24xx/mci.h index 4f4ccd18f0cb..2d0852ac3b27 100644 --- a/include/asm-arm/plat-s3c24xx/mci.h +++ b/include/asm-arm/plat-s3c24xx/mci.h @@ -3,6 +3,7 @@ struct s3c24xx_mci_pdata { unsigned int wprotect_invert : 1; + unsigned int detect_invert : 1; /* set => detect active high. */ unsigned int gpio_detect; unsigned int gpio_wprotect; -- cgit v1.2.3 From 6d37333163025b46afbcad434ec9a5f2e88e7254 Mon Sep 17 00:00:00 2001 From: Tomas Winkler Date: Mon, 30 Jun 2008 10:50:24 +0300 Subject: mmc: fix sdio_io sparse errors This patch fixes sdio_io sparse errors. This fix changes signature of API functions, changing unsigned char -> u8 unsigned short -> u16 unsigned long -> u32 - this was probably a bug in 64 bit platforms Signed-off-by: Tomas Winkler Signed-off-by: Pierre Ossman --- drivers/mmc/core/sdio_io.c | 42 ++++++++++++++++-------------------------- include/linux/mmc/sdio_func.h | 15 ++++++--------- 2 files changed, 22 insertions(+), 35 deletions(-) mode change 100644 => 100755 drivers/mmc/core/sdio_io.c mode change 100644 => 100755 include/linux/mmc/sdio_func.h (limited to 'include') diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c old mode 100644 new mode 100755 index cc42a41ff6ab..3ccf6919877c --- a/drivers/mmc/core/sdio_io.c +++ b/drivers/mmc/core/sdio_io.c @@ -167,10 +167,8 @@ int sdio_set_block_size(struct sdio_func *func, unsigned blksz) return -EINVAL; if (blksz == 0) { - blksz = min(min( - func->max_blksize, - func->card->host->max_blk_size), - 512u); + blksz = min(func->max_blksize, func->card->host->max_blk_size); + blksz = min(blksz, 512u); } ret = mmc_io_rw_direct(func->card, 1, 0, @@ -311,10 +309,9 @@ static int sdio_io_rw_ext_helper(struct sdio_func *func, int write, /* Blocks per command is limited by host count, host transfer * size (we only use a single sg entry) and the maximum for * IO_RW_EXTENDED of 511 blocks. */ - max_blocks = min(min( - func->card->host->max_blk_count, - func->card->host->max_seg_size / func->cur_blksize), - 511u); + max_blocks = min(func->card->host->max_blk_count, + func->card->host->max_seg_size / func->cur_blksize); + max_blocks = min(max_blocks, 511u); while (remainder > func->cur_blksize) { unsigned blocks; @@ -364,11 +361,10 @@ static int sdio_io_rw_ext_helper(struct sdio_func *func, int write, * function. If there is a problem reading the address, 0xff * is returned and @err_ret will contain the error code. */ -unsigned char sdio_readb(struct sdio_func *func, unsigned int addr, - int *err_ret) +u8 sdio_readb(struct sdio_func *func, unsigned int addr, int *err_ret) { int ret; - unsigned char val; + u8 val; BUG_ON(!func); @@ -397,8 +393,7 @@ EXPORT_SYMBOL_GPL(sdio_readb); * function. @err_ret will contain the status of the actual * transfer. */ -void sdio_writeb(struct sdio_func *func, unsigned char b, unsigned int addr, - int *err_ret) +void sdio_writeb(struct sdio_func *func, u8 b, unsigned int addr, int *err_ret) { int ret; @@ -459,7 +454,6 @@ int sdio_readsb(struct sdio_func *func, void *dst, unsigned int addr, { return sdio_io_rw_ext_helper(func, 0, addr, 0, dst, count); } - EXPORT_SYMBOL_GPL(sdio_readsb); /** @@ -489,8 +483,7 @@ EXPORT_SYMBOL_GPL(sdio_writesb); * function. If there is a problem reading the address, 0xffff * is returned and @err_ret will contain the error code. */ -unsigned short sdio_readw(struct sdio_func *func, unsigned int addr, - int *err_ret) +u16 sdio_readw(struct sdio_func *func, unsigned int addr, int *err_ret) { int ret; @@ -504,7 +497,7 @@ unsigned short sdio_readw(struct sdio_func *func, unsigned int addr, return 0xFFFF; } - return le16_to_cpu(*(u16*)func->tmpbuf); + return le16_to_cpup((__le16 *)func->tmpbuf); } EXPORT_SYMBOL_GPL(sdio_readw); @@ -519,12 +512,11 @@ EXPORT_SYMBOL_GPL(sdio_readw); * function. @err_ret will contain the status of the actual * transfer. */ -void sdio_writew(struct sdio_func *func, unsigned short b, unsigned int addr, - int *err_ret) +void sdio_writew(struct sdio_func *func, u16 b, unsigned int addr, int *err_ret) { int ret; - *(u16*)func->tmpbuf = cpu_to_le16(b); + *(__le16 *)func->tmpbuf = cpu_to_le16(b); ret = sdio_memcpy_toio(func, addr, func->tmpbuf, 2); if (err_ret) @@ -543,8 +535,7 @@ EXPORT_SYMBOL_GPL(sdio_writew); * 0xffffffff is returned and @err_ret will contain the error * code. */ -unsigned long sdio_readl(struct sdio_func *func, unsigned int addr, - int *err_ret) +u32 sdio_readl(struct sdio_func *func, unsigned int addr, int *err_ret) { int ret; @@ -558,7 +549,7 @@ unsigned long sdio_readl(struct sdio_func *func, unsigned int addr, return 0xFFFFFFFF; } - return le32_to_cpu(*(u32*)func->tmpbuf); + return le32_to_cpup((__le32 *)func->tmpbuf); } EXPORT_SYMBOL_GPL(sdio_readl); @@ -573,12 +564,11 @@ EXPORT_SYMBOL_GPL(sdio_readl); * function. @err_ret will contain the status of the actual * transfer. */ -void sdio_writel(struct sdio_func *func, unsigned long b, unsigned int addr, - int *err_ret) +void sdio_writel(struct sdio_func *func, u32 b, unsigned int addr, int *err_ret) { int ret; - *(u32*)func->tmpbuf = cpu_to_le32(b); + *(__le32 *)func->tmpbuf = cpu_to_le32(b); ret = sdio_memcpy_toio(func, addr, func->tmpbuf, 4); if (err_ret) diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h old mode 100644 new mode 100755 index f57f22b3be88..28fb0a33acf8 --- a/include/linux/mmc/sdio_func.h +++ b/include/linux/mmc/sdio_func.h @@ -122,23 +122,20 @@ extern int sdio_release_irq(struct sdio_func *func); extern unsigned int sdio_align_size(struct sdio_func *func, unsigned int sz); -extern unsigned char sdio_readb(struct sdio_func *func, - unsigned int addr, int *err_ret); -extern unsigned short sdio_readw(struct sdio_func *func, - unsigned int addr, int *err_ret); -extern unsigned long sdio_readl(struct sdio_func *func, - unsigned int addr, int *err_ret); +extern u8 sdio_readb(struct sdio_func *func, unsigned int addr, int *err_ret); +extern u16 sdio_readw(struct sdio_func *func, unsigned int addr, int *err_ret); +extern u32 sdio_readl(struct sdio_func *func, unsigned int addr, int *err_ret); extern int sdio_memcpy_fromio(struct sdio_func *func, void *dst, unsigned int addr, int count); extern int sdio_readsb(struct sdio_func *func, void *dst, unsigned int addr, int count); -extern void sdio_writeb(struct sdio_func *func, unsigned char b, +extern void sdio_writeb(struct sdio_func *func, u8 b, unsigned int addr, int *err_ret); -extern void sdio_writew(struct sdio_func *func, unsigned short b, +extern void sdio_writew(struct sdio_func *func, u16 b, unsigned int addr, int *err_ret); -extern void sdio_writel(struct sdio_func *func, unsigned long b, +extern void sdio_writel(struct sdio_func *func, u32 b, unsigned int addr, int *err_ret); extern int sdio_memcpy_toio(struct sdio_func *func, unsigned int addr, -- cgit v1.2.3 From 7d2be0749a59096a334c94dc48f43294193cb8ed Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 30 Jun 2008 18:35:03 +0200 Subject: atmel-mci: Driver for Atmel on-chip MMC controllers This is a driver for the MMC controller on the AP7000 chips from Atmel. It should in theory work on AT91 systems too with some tweaking, but since the DMA interface is quite different, it's not entirely clear if it's worth merging this with the at91_mci driver. This driver has been around for a while in BSPs and kernel sources provided by Atmel, but this particular version uses the generic DMA Engine framework (with the slave extensions) instead of an avr32-only DMA controller framework. This driver can also use PIO transfers when no DMA channels are available, and for transfers where using DMA may be difficult or impractical for some reason (e.g. the DMA setup overhead is usually not worth it for very short transfers, and badly aligned buffers or lengths are difficult to handle.) Currently, the driver only support PIO transfers. DMA support has been split out to a separate patch to hopefully make it easier to review. The driver has been tested using mmc-block and ext3fs on several SD, SDHC and MMC+ cards. Reads and writes work fine, with read transfer rates up to 3.5 MiB/s on fast cards with debugging disabled. The driver has also been tested using the mmc_test module on the same cards. All tests except 7, 9, 15 and 17 succeed. The first two are unsupported by all the cards I have, so I don't know if the driver handles this correctly. The last two fail because the hardware flags a Data CRC Error instead of a Data Timeout error. I'm not sure how to deal with that. Documentation for this controller can be found in many data sheets from Atmel, including the AT32AP7000 data sheet which can be found here: http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 Signed-off-by: Haavard Skinnemoen Signed-off-by: Pierre Ossman --- arch/avr32/boards/atngw100/setup.c | 7 + arch/avr32/boards/atstk1000/atstk1002.c | 3 + arch/avr32/mach-at32ap/at32ap700x.c | 30 +- drivers/mmc/host/Kconfig | 10 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/atmel-mci-regs.h | 91 +++ drivers/mmc/host/atmel-mci.c | 981 ++++++++++++++++++++++++++++++++ include/asm-avr32/arch-at32ap/board.h | 6 +- include/asm-avr32/atmel-mci.h | 9 + 9 files changed, 1132 insertions(+), 6 deletions(-) create mode 100644 drivers/mmc/host/atmel-mci-regs.h create mode 100644 drivers/mmc/host/atmel-mci.c create mode 100644 include/asm-avr32/atmel-mci.h (limited to 'include') diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c index a51bb9fb3c89..c7fe94d03a1e 100644 --- a/arch/avr32/boards/atngw100/setup.c +++ b/arch/avr32/boards/atngw100/setup.c @@ -19,6 +19,7 @@ #include #include +#include #include #include @@ -51,6 +52,11 @@ static struct spi_board_info spi0_board_info[] __initdata = { }, }; +static struct mci_platform_data __initdata mci0_data = { + .detect_pin = GPIO_PIN_PC(25), + .wp_pin = GPIO_PIN_PE(0), +}; + /* * The next two functions should go away as the boot loader is * supposed to initialize the macb address registers with a valid @@ -170,6 +176,7 @@ static int __init atngw100_init(void) set_hw_addr(at32_add_device_eth(1, ð_data[1])); at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info)); + at32_add_device_mci(0, &mci0_data); at32_add_device_usba(0, NULL); for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) { diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c index 86b363c1c25b..e11659b732fa 100644 --- a/arch/avr32/boards/atstk1000/atstk1002.c +++ b/arch/avr32/boards/atstk1000/atstk1002.c @@ -234,6 +234,9 @@ static int __init atstk1002_init(void) #ifdef CONFIG_BOARD_ATSTK100X_SPI1 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info)); #endif +#ifndef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM + at32_add_device_mci(0, NULL); +#endif #ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM set_hw_addr(at32_add_device_eth(1, ð_data[1])); #else diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c index 07b21b121eef..021d51217184 100644 --- a/arch/avr32/mach-at32ap/at32ap700x.c +++ b/arch/avr32/mach-at32ap/at32ap700x.c @@ -14,6 +14,7 @@ #include #include +#include #include #include @@ -1278,20 +1279,32 @@ static struct clk atmel_mci0_pclk = { .index = 9, }; -struct platform_device *__init at32_add_device_mci(unsigned int id) +struct platform_device *__init +at32_add_device_mci(unsigned int id, struct mci_platform_data *data) { - struct platform_device *pdev; + struct mci_platform_data _data; + struct platform_device *pdev; + struct dw_dma_slave *dws; if (id != 0) return NULL; pdev = platform_device_alloc("atmel_mci", id); if (!pdev) - return NULL; + goto fail; if (platform_device_add_resources(pdev, atmel_mci0_resource, ARRAY_SIZE(atmel_mci0_resource))) - goto err_add_resources; + goto fail; + + if (!data) { + data = &_data; + memset(data, 0, sizeof(struct mci_platform_data)); + } + + if (platform_device_add_data(pdev, data, + sizeof(struct mci_platform_data))) + goto fail; select_peripheral(PA(10), PERIPH_A, 0); /* CLK */ select_peripheral(PA(11), PERIPH_A, 0); /* CMD */ @@ -1300,12 +1313,19 @@ struct platform_device *__init at32_add_device_mci(unsigned int id) select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */ select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */ + if (data) { + if (data->detect_pin != GPIO_PIN_NONE) + at32_select_gpio(data->detect_pin, 0); + if (data->wp_pin != GPIO_PIN_NONE) + at32_select_gpio(data->wp_pin, 0); + } + atmel_mci0_pclk.dev = &pdev->dev; platform_device_add(pdev); return pdev; -err_add_resources: +fail: platform_device_put(pdev); return NULL; } diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index dc88c03662ab..198df4234354 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -104,6 +104,16 @@ config MMC_AT91 If unsure, say N. +config MMC_ATMELMCI + tristate "Atmel Multimedia Card Interface support" + depends on AVR32 + help + This selects the Atmel Multimedia Card Interface driver. If + you have an AT32 (AVR32) platform with a Multimedia Card + slot, say Y or M here. + + If unsure, say N. + config MMC_IMX tristate "Motorola i.MX Multimedia Card Interface support" depends on ARCH_IMX diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index b3e023bf8c78..2dc9ff23cfb7 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_MMC_WBSD) += wbsd.o obj-$(CONFIG_MMC_AU1X) += au1xmmc.o obj-$(CONFIG_MMC_OMAP) += omap.o obj-$(CONFIG_MMC_AT91) += at91_mci.o +obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o obj-$(CONFIG_MMC_SPI) += mmc_spi.o obj-$(CONFIG_MMC_S3C) += s3cmci.o diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h new file mode 100644 index 000000000000..a9a5657706c6 --- /dev/null +++ b/drivers/mmc/host/atmel-mci-regs.h @@ -0,0 +1,91 @@ +/* + * Atmel MultiMedia Card Interface driver + * + * Copyright (C) 2004-2006 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DRIVERS_MMC_ATMEL_MCI_H__ +#define __DRIVERS_MMC_ATMEL_MCI_H__ + +/* MCI Register Definitions */ +#define MCI_CR 0x0000 /* Control */ +# define MCI_CR_MCIEN ( 1 << 0) /* MCI Enable */ +# define MCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */ +# define MCI_CR_SWRST ( 1 << 7) /* Software Reset */ +#define MCI_MR 0x0004 /* Mode */ +# define MCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */ +# define MCI_MR_RDPROOF ( 1 << 11) /* Read Proof */ +# define MCI_MR_WRPROOF ( 1 << 12) /* Write Proof */ +#define MCI_DTOR 0x0008 /* Data Timeout */ +# define MCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */ +# define MCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */ +#define MCI_SDCR 0x000c /* SD Card / SDIO */ +# define MCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */ +# define MCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */ +# define MCI_SDCBUS_1BIT ( 0 << 7) /* 1-bit data bus */ +# define MCI_SDCBUS_4BIT ( 1 << 7) /* 4-bit data bus */ +#define MCI_ARGR 0x0010 /* Command Argument */ +#define MCI_CMDR 0x0014 /* Command */ +# define MCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */ +# define MCI_CMDR_RSPTYP_NONE ( 0 << 6) /* No response */ +# define MCI_CMDR_RSPTYP_48BIT ( 1 << 6) /* 48-bit response */ +# define MCI_CMDR_RSPTYP_136BIT ( 2 << 6) /* 136-bit response */ +# define MCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */ +# define MCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */ +# define MCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */ +# define MCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */ +# define MCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */ +# define MCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */ +# define MCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */ +# define MCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */ +# define MCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */ +# define MCI_CMDR_TRDIR_WRITE ( 0 << 18) /* Write data */ +# define MCI_CMDR_TRDIR_READ ( 1 << 18) /* Read data */ +# define MCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */ +# define MCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */ +# define MCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */ +# define MCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */ +# define MCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */ +# define MCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */ +# define MCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */ +#define MCI_BLKR 0x0018 /* Block */ +# define MCI_BCNT(x) ((x) << 0) /* Data Block Count */ +# define MCI_BLKLEN(x) ((x) << 16) /* Data Block Length */ +#define MCI_RSPR 0x0020 /* Response 0 */ +#define MCI_RSPR1 0x0024 /* Response 1 */ +#define MCI_RSPR2 0x0028 /* Response 2 */ +#define MCI_RSPR3 0x002c /* Response 3 */ +#define MCI_RDR 0x0030 /* Receive Data */ +#define MCI_TDR 0x0034 /* Transmit Data */ +#define MCI_SR 0x0040 /* Status */ +#define MCI_IER 0x0044 /* Interrupt Enable */ +#define MCI_IDR 0x0048 /* Interrupt Disable */ +#define MCI_IMR 0x004c /* Interrupt Mask */ +# define MCI_CMDRDY ( 1 << 0) /* Command Ready */ +# define MCI_RXRDY ( 1 << 1) /* Receiver Ready */ +# define MCI_TXRDY ( 1 << 2) /* Transmitter Ready */ +# define MCI_BLKE ( 1 << 3) /* Data Block Ended */ +# define MCI_DTIP ( 1 << 4) /* Data Transfer In Progress */ +# define MCI_NOTBUSY ( 1 << 5) /* Data Not Busy */ +# define MCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */ +# define MCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */ +# define MCI_RINDE ( 1 << 16) /* Response Index Error */ +# define MCI_RDIRE ( 1 << 17) /* Response Direction Error */ +# define MCI_RCRCE ( 1 << 18) /* Response CRC Error */ +# define MCI_RENDE ( 1 << 19) /* Response End Bit Error */ +# define MCI_RTOE ( 1 << 20) /* Response Time-Out Error */ +# define MCI_DCRCE ( 1 << 21) /* Data CRC Error */ +# define MCI_DTOE ( 1 << 22) /* Data Time-Out Error */ +# define MCI_OVRE ( 1 << 30) /* RX Overrun Error */ +# define MCI_UNRE ( 1 << 31) /* TX Underrun Error */ + +/* Register access macros */ +#define mci_readl(port,reg) \ + __raw_readl((port)->regs + MCI_##reg) +#define mci_writel(port,reg,value) \ + __raw_writel((value), (port)->regs + MCI_##reg) + +#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */ diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c new file mode 100644 index 000000000000..25d5324ab7e2 --- /dev/null +++ b/drivers/mmc/host/atmel-mci.c @@ -0,0 +1,981 @@ +/* + * Atmel MultiMedia Card Interface driver + * + * Copyright (C) 2004-2008 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include "atmel-mci-regs.h" + +#define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE) + +enum { + EVENT_CMD_COMPLETE = 0, + EVENT_DATA_ERROR, + EVENT_DATA_COMPLETE, + EVENT_STOP_SENT, + EVENT_STOP_COMPLETE, + EVENT_XFER_COMPLETE, +}; + +struct atmel_mci { + struct mmc_host *mmc; + void __iomem *regs; + + struct scatterlist *sg; + unsigned int pio_offset; + + struct mmc_request *mrq; + struct mmc_command *cmd; + struct mmc_data *data; + + u32 cmd_status; + u32 data_status; + u32 stop_status; + u32 stop_cmdr; + + u32 mode_reg; + u32 sdc_reg; + + struct tasklet_struct tasklet; + unsigned long pending_events; + unsigned long completed_events; + + int present; + int detect_pin; + int wp_pin; + + /* For detect pin debouncing */ + struct timer_list detect_timer; + + unsigned long bus_hz; + unsigned long mapbase; + struct clk *mck; + struct platform_device *pdev; +}; + +#define atmci_is_completed(host, event) \ + test_bit(event, &host->completed_events) +#define atmci_test_and_clear_pending(host, event) \ + test_and_clear_bit(event, &host->pending_events) +#define atmci_test_and_set_completed(host, event) \ + test_and_set_bit(event, &host->completed_events) +#define atmci_set_completed(host, event) \ + set_bit(event, &host->completed_events) +#define atmci_set_pending(host, event) \ + set_bit(event, &host->pending_events) +#define atmci_clear_pending(host, event) \ + clear_bit(event, &host->pending_events) + + +static void atmci_enable(struct atmel_mci *host) +{ + clk_enable(host->mck); + mci_writel(host, CR, MCI_CR_MCIEN); + mci_writel(host, MR, host->mode_reg); + mci_writel(host, SDCR, host->sdc_reg); +} + +static void atmci_disable(struct atmel_mci *host) +{ + mci_writel(host, CR, MCI_CR_SWRST); + + /* Stall until write is complete, then disable the bus clock */ + mci_readl(host, SR); + clk_disable(host->mck); +} + +static inline unsigned int ns_to_clocks(struct atmel_mci *host, + unsigned int ns) +{ + return (ns * (host->bus_hz / 1000000) + 999) / 1000; +} + +static void atmci_set_timeout(struct atmel_mci *host, + struct mmc_data *data) +{ + static unsigned dtomul_to_shift[] = { + 0, 4, 7, 8, 10, 12, 16, 20 + }; + unsigned timeout; + unsigned dtocyc; + unsigned dtomul; + + timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks; + + for (dtomul = 0; dtomul < 8; dtomul++) { + unsigned shift = dtomul_to_shift[dtomul]; + dtocyc = (timeout + (1 << shift) - 1) >> shift; + if (dtocyc < 15) + break; + } + + if (dtomul >= 8) { + dtomul = 7; + dtocyc = 15; + } + + dev_vdbg(&host->mmc->class_dev, "setting timeout to %u cycles\n", + dtocyc << dtomul_to_shift[dtomul]); + mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc))); +} + +/* + * Return mask with command flags to be enabled for this command. + */ +static u32 atmci_prepare_command(struct mmc_host *mmc, + struct mmc_command *cmd) +{ + struct mmc_data *data; + u32 cmdr; + + cmd->error = -EINPROGRESS; + + cmdr = MCI_CMDR_CMDNB(cmd->opcode); + + if (cmd->flags & MMC_RSP_PRESENT) { + if (cmd->flags & MMC_RSP_136) + cmdr |= MCI_CMDR_RSPTYP_136BIT; + else + cmdr |= MCI_CMDR_RSPTYP_48BIT; + } + + /* + * This should really be MAXLAT_5 for CMD2 and ACMD41, but + * it's too difficult to determine whether this is an ACMD or + * not. Better make it 64. + */ + cmdr |= MCI_CMDR_MAXLAT_64CYC; + + if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) + cmdr |= MCI_CMDR_OPDCMD; + + data = cmd->data; + if (data) { + cmdr |= MCI_CMDR_START_XFER; + if (data->flags & MMC_DATA_STREAM) + cmdr |= MCI_CMDR_STREAM; + else if (data->blocks > 1) + cmdr |= MCI_CMDR_MULTI_BLOCK; + else + cmdr |= MCI_CMDR_BLOCK; + + if (data->flags & MMC_DATA_READ) + cmdr |= MCI_CMDR_TRDIR_READ; + } + + return cmdr; +} + +static void atmci_start_command(struct atmel_mci *host, + struct mmc_command *cmd, + u32 cmd_flags) +{ + /* Must read host->cmd after testing event flags */ + smp_rmb(); + WARN_ON(host->cmd); + host->cmd = cmd; + + dev_vdbg(&host->mmc->class_dev, + "start command: ARGR=0x%08x CMDR=0x%08x\n", + cmd->arg, cmd_flags); + + mci_writel(host, ARGR, cmd->arg); + mci_writel(host, CMDR, cmd_flags); +} + +static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data) +{ + struct atmel_mci *host = mmc_priv(mmc); + + atmci_start_command(host, data->stop, host->stop_cmdr); + mci_writel(host, IER, MCI_CMDRDY); +} + +static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct atmel_mci *host = mmc_priv(mmc); + + WARN_ON(host->cmd || host->data); + host->mrq = NULL; + + atmci_disable(host); + + mmc_request_done(mmc, mrq); +} + +/* + * Returns a mask of interrupt flags to be enabled after the whole + * request has been prepared. + */ +static u32 atmci_submit_data(struct mmc_host *mmc, struct mmc_data *data) +{ + struct atmel_mci *host = mmc_priv(mmc); + u32 iflags; + + data->error = -EINPROGRESS; + + WARN_ON(host->data); + host->sg = NULL; + host->data = data; + + mci_writel(host, BLKR, MCI_BCNT(data->blocks) + | MCI_BLKLEN(data->blksz)); + dev_vdbg(&mmc->class_dev, "BLKR=0x%08x\n", + MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz)); + + iflags = ATMCI_DATA_ERROR_FLAGS; + host->sg = data->sg; + host->pio_offset = 0; + if (data->flags & MMC_DATA_READ) + iflags |= MCI_RXRDY; + else + iflags |= MCI_TXRDY; + + return iflags; +} + +static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct atmel_mci *host = mmc_priv(mmc); + struct mmc_data *data; + struct mmc_command *cmd; + u32 iflags; + u32 cmdflags = 0; + + iflags = mci_readl(host, IMR); + if (iflags) + dev_warn(&mmc->class_dev, "WARNING: IMR=0x%08x\n", + mci_readl(host, IMR)); + + WARN_ON(host->mrq != NULL); + + /* + * We may "know" the card is gone even though there's still an + * electrical connection. If so, we really need to communicate + * this to the MMC core since there won't be any more + * interrupts as the card is completely removed. Otherwise, + * the MMC core might believe the card is still there even + * though the card was just removed very slowly. + */ + if (!host->present) { + mrq->cmd->error = -ENOMEDIUM; + mmc_request_done(mmc, mrq); + return; + } + + host->mrq = mrq; + host->pending_events = 0; + host->completed_events = 0; + + atmci_enable(host); + + /* We don't support multiple blocks of weird lengths. */ + data = mrq->data; + if (data) { + if (data->blocks > 1 && data->blksz & 3) + goto fail; + atmci_set_timeout(host, data); + } + + iflags = MCI_CMDRDY; + cmd = mrq->cmd; + cmdflags = atmci_prepare_command(mmc, cmd); + atmci_start_command(host, cmd, cmdflags); + + if (data) + iflags |= atmci_submit_data(mmc, data); + + if (mrq->stop) { + host->stop_cmdr = atmci_prepare_command(mmc, mrq->stop); + host->stop_cmdr |= MCI_CMDR_STOP_XFER; + if (!(data->flags & MMC_DATA_WRITE)) + host->stop_cmdr |= MCI_CMDR_TRDIR_READ; + if (data->flags & MMC_DATA_STREAM) + host->stop_cmdr |= MCI_CMDR_STREAM; + else + host->stop_cmdr |= MCI_CMDR_MULTI_BLOCK; + } + + /* + * We could have enabled interrupts earlier, but I suspect + * that would open up a nice can of interesting race + * conditions (e.g. command and data complete, but stop not + * prepared yet.) + */ + mci_writel(host, IER, iflags); + + return; + +fail: + atmci_disable(host); + host->mrq = NULL; + mrq->cmd->error = -EINVAL; + mmc_request_done(mmc, mrq); +} + +static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct atmel_mci *host = mmc_priv(mmc); + + if (ios->clock) { + u32 clkdiv; + + /* Set clock rate */ + clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * ios->clock) - 1; + if (clkdiv > 255) { + dev_warn(&mmc->class_dev, + "clock %u too slow; using %lu\n", + ios->clock, host->bus_hz / (2 * 256)); + clkdiv = 255; + } + + host->mode_reg = MCI_MR_CLKDIV(clkdiv) | MCI_MR_WRPROOF + | MCI_MR_RDPROOF; + } + + switch (ios->bus_width) { + case MMC_BUS_WIDTH_1: + host->sdc_reg = 0; + break; + case MMC_BUS_WIDTH_4: + host->sdc_reg = MCI_SDCBUS_4BIT; + break; + } + + switch (ios->power_mode) { + case MMC_POWER_ON: + /* Send init sequence (74 clock cycles) */ + atmci_enable(host); + mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT); + while (!(mci_readl(host, SR) & MCI_CMDRDY)) + cpu_relax(); + atmci_disable(host); + break; + default: + /* + * TODO: None of the currently available AVR32-based + * boards allow MMC power to be turned off. Implement + * power control when this can be tested properly. + */ + break; + } +} + +static int atmci_get_ro(struct mmc_host *mmc) +{ + int read_only = 0; + struct atmel_mci *host = mmc_priv(mmc); + + if (host->wp_pin >= 0) { + read_only = gpio_get_value(host->wp_pin); + dev_dbg(&mmc->class_dev, "card is %s\n", + read_only ? "read-only" : "read-write"); + } else { + dev_dbg(&mmc->class_dev, + "no pin for checking read-only switch." + " Assuming write-enable.\n"); + } + + return read_only; +} + +static struct mmc_host_ops atmci_ops = { + .request = atmci_request, + .set_ios = atmci_set_ios, + .get_ro = atmci_get_ro, +}; + +static void atmci_command_complete(struct atmel_mci *host, + struct mmc_command *cmd, u32 status) +{ + /* Read the response from the card (up to 16 bytes) */ + cmd->resp[0] = mci_readl(host, RSPR); + cmd->resp[1] = mci_readl(host, RSPR); + cmd->resp[2] = mci_readl(host, RSPR); + cmd->resp[3] = mci_readl(host, RSPR); + + if (status & MCI_RTOE) + cmd->error = -ETIMEDOUT; + else if ((cmd->flags & MMC_RSP_CRC) && (status & MCI_RCRCE)) + cmd->error = -EILSEQ; + else if (status & (MCI_RINDE | MCI_RDIRE | MCI_RENDE)) + cmd->error = -EIO; + else + cmd->error = 0; + + if (cmd->error) { + dev_dbg(&host->mmc->class_dev, + "command error: status=0x%08x\n", status); + + if (cmd->data) { + host->data = NULL; + mci_writel(host, IDR, MCI_NOTBUSY + | MCI_TXRDY | MCI_RXRDY + | ATMCI_DATA_ERROR_FLAGS); + } + } +} + +static void atmci_detect_change(unsigned long data) +{ + struct atmel_mci *host = (struct atmel_mci *)data; + struct mmc_request *mrq = host->mrq; + int present; + + /* + * atmci_remove() sets detect_pin to -1 before freeing the + * interrupt. We must not re-enable the interrupt if it has + * been freed. + */ + smp_rmb(); + if (host->detect_pin < 0) + return; + + enable_irq(gpio_to_irq(host->detect_pin)); + present = !gpio_get_value(host->detect_pin); + + dev_vdbg(&host->pdev->dev, "detect change: %d (was %d)\n", + present, host->present); + + if (present != host->present) { + dev_dbg(&host->mmc->class_dev, "card %s\n", + present ? "inserted" : "removed"); + host->present = present; + + /* Reset controller if card is gone */ + if (!present) { + mci_writel(host, CR, MCI_CR_SWRST); + mci_writel(host, IDR, ~0UL); + mci_writel(host, CR, MCI_CR_MCIEN); + } + + /* Clean up queue if present */ + if (mrq) { + /* + * Reset controller to terminate any ongoing + * commands or data transfers. + */ + mci_writel(host, CR, MCI_CR_SWRST); + + if (!atmci_is_completed(host, EVENT_CMD_COMPLETE)) + mrq->cmd->error = -ENOMEDIUM; + + if (mrq->data && !atmci_is_completed(host, + EVENT_DATA_COMPLETE)) { + host->data = NULL; + mrq->data->error = -ENOMEDIUM; + } + if (mrq->stop && !atmci_is_completed(host, + EVENT_STOP_COMPLETE)) + mrq->stop->error = -ENOMEDIUM; + + host->cmd = NULL; + atmci_request_end(host->mmc, mrq); + } + + mmc_detect_change(host->mmc, 0); + } +} + +static void atmci_tasklet_func(unsigned long priv) +{ + struct mmc_host *mmc = (struct mmc_host *)priv; + struct atmel_mci *host = mmc_priv(mmc); + struct mmc_request *mrq = host->mrq; + struct mmc_data *data = host->data; + + dev_vdbg(&mmc->class_dev, + "tasklet: pending/completed/mask %lx/%lx/%x\n", + host->pending_events, host->completed_events, + mci_readl(host, IMR)); + + if (atmci_test_and_clear_pending(host, EVENT_CMD_COMPLETE)) { + /* + * host->cmd must be set to NULL before the interrupt + * handler sees EVENT_CMD_COMPLETE + */ + host->cmd = NULL; + smp_wmb(); + atmci_set_completed(host, EVENT_CMD_COMPLETE); + atmci_command_complete(host, mrq->cmd, host->cmd_status); + + if (!mrq->cmd->error && mrq->stop + && atmci_is_completed(host, EVENT_XFER_COMPLETE) + && !atmci_test_and_set_completed(host, + EVENT_STOP_SENT)) + send_stop_cmd(host->mmc, mrq->data); + } + if (atmci_test_and_clear_pending(host, EVENT_STOP_COMPLETE)) { + /* + * host->cmd must be set to NULL before the interrupt + * handler sees EVENT_STOP_COMPLETE + */ + host->cmd = NULL; + smp_wmb(); + atmci_set_completed(host, EVENT_STOP_COMPLETE); + atmci_command_complete(host, mrq->stop, host->stop_status); + } + if (atmci_test_and_clear_pending(host, EVENT_DATA_ERROR)) { + u32 status = host->data_status; + + dev_vdbg(&mmc->class_dev, "data error: status=%08x\n", status); + + atmci_set_completed(host, EVENT_DATA_ERROR); + atmci_set_completed(host, EVENT_DATA_COMPLETE); + + if (status & MCI_DTOE) { + dev_dbg(&mmc->class_dev, + "data timeout error\n"); + data->error = -ETIMEDOUT; + } else if (status & MCI_DCRCE) { + dev_dbg(&mmc->class_dev, "data CRC error\n"); + data->error = -EILSEQ; + } else { + dev_dbg(&mmc->class_dev, + "data FIFO error (status=%08x)\n", + status); + data->error = -EIO; + } + + if (host->present && data->stop + && atmci_is_completed(host, EVENT_CMD_COMPLETE) + && !atmci_test_and_set_completed( + host, EVENT_STOP_SENT)) + send_stop_cmd(host->mmc, data); + + host->data = NULL; + } + if (atmci_test_and_clear_pending(host, EVENT_DATA_COMPLETE)) { + atmci_set_completed(host, EVENT_DATA_COMPLETE); + + if (!atmci_is_completed(host, EVENT_DATA_ERROR)) { + data->bytes_xfered = data->blocks * data->blksz; + data->error = 0; + } + + host->data = NULL; + } + + if (host->mrq && !host->cmd && !host->data) + atmci_request_end(mmc, host->mrq); +} + +static void atmci_read_data_pio(struct atmel_mci *host) +{ + struct scatterlist *sg = host->sg; + void *buf = sg_virt(sg); + unsigned int offset = host->pio_offset; + struct mmc_data *data = host->data; + u32 value; + u32 status; + unsigned int nbytes = 0; + + do { + value = mci_readl(host, RDR); + if (likely(offset + 4 <= sg->length)) { + put_unaligned(value, (u32 *)(buf + offset)); + + offset += 4; + nbytes += 4; + + if (offset == sg->length) { + host->sg = sg = sg_next(sg); + if (!sg) + goto done; + + offset = 0; + buf = sg_virt(sg); + } + } else { + unsigned int remaining = sg->length - offset; + memcpy(buf + offset, &value, remaining); + nbytes += remaining; + + flush_dcache_page(sg_page(sg)); + host->sg = sg = sg_next(sg); + if (!sg) + goto done; + + offset = 4 - remaining; + buf = sg_virt(sg); + memcpy(buf, (u8 *)&value + remaining, offset); + nbytes += offset; + } + + status = mci_readl(host, SR); + if (status & ATMCI_DATA_ERROR_FLAGS) { + mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY + | ATMCI_DATA_ERROR_FLAGS)); + host->data_status = status; + atmci_set_pending(host, EVENT_DATA_ERROR); + tasklet_schedule(&host->tasklet); + break; + } + } while (status & MCI_RXRDY); + + host->pio_offset = offset; + data->bytes_xfered += nbytes; + + return; + +done: + mci_writel(host, IDR, MCI_RXRDY); + mci_writel(host, IER, MCI_NOTBUSY); + data->bytes_xfered += nbytes; + atmci_set_completed(host, EVENT_XFER_COMPLETE); + if (data->stop && atmci_is_completed(host, EVENT_CMD_COMPLETE) + && !atmci_test_and_set_completed(host, EVENT_STOP_SENT)) + send_stop_cmd(host->mmc, data); +} + +static void atmci_write_data_pio(struct atmel_mci *host) +{ + struct scatterlist *sg = host->sg; + void *buf = sg_virt(sg); + unsigned int offset = host->pio_offset; + struct mmc_data *data = host->data; + u32 value; + u32 status; + unsigned int nbytes = 0; + + do { + if (likely(offset + 4 <= sg->length)) { + value = get_unaligned((u32 *)(buf + offset)); + mci_writel(host, TDR, value); + + offset += 4; + nbytes += 4; + if (offset == sg->length) { + host->sg = sg = sg_next(sg); + if (!sg) + goto done; + + offset = 0; + buf = sg_virt(sg); + } + } else { + unsigned int remaining = sg->length - offset; + + value = 0; + memcpy(&value, buf + offset, remaining); + nbytes += remaining; + + host->sg = sg = sg_next(sg); + if (!sg) { + mci_writel(host, TDR, value); + goto done; + } + + offset = 4 - remaining; + buf = sg_virt(sg); + memcpy((u8 *)&value + remaining, buf, offset); + mci_writel(host, TDR, value); + nbytes += offset; + } + + status = mci_readl(host, SR); + if (status & ATMCI_DATA_ERROR_FLAGS) { + mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY + | ATMCI_DATA_ERROR_FLAGS)); + host->data_status = status; + atmci_set_pending(host, EVENT_DATA_ERROR); + tasklet_schedule(&host->tasklet); + break; + } + } while (status & MCI_TXRDY); + + host->pio_offset = offset; + data->bytes_xfered += nbytes; + + return; + +done: + mci_writel(host, IDR, MCI_TXRDY); + mci_writel(host, IER, MCI_NOTBUSY); + data->bytes_xfered += nbytes; + atmci_set_completed(host, EVENT_XFER_COMPLETE); + if (data->stop && atmci_is_completed(host, EVENT_CMD_COMPLETE) + && !atmci_test_and_set_completed(host, EVENT_STOP_SENT)) + send_stop_cmd(host->mmc, data); +} + +static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status) +{ + struct atmel_mci *host = mmc_priv(mmc); + + mci_writel(host, IDR, MCI_CMDRDY); + + if (atmci_is_completed(host, EVENT_STOP_SENT)) { + host->stop_status = status; + atmci_set_pending(host, EVENT_STOP_COMPLETE); + } else { + host->cmd_status = status; + atmci_set_pending(host, EVENT_CMD_COMPLETE); + } + + tasklet_schedule(&host->tasklet); +} + +static irqreturn_t atmci_interrupt(int irq, void *dev_id) +{ + struct mmc_host *mmc = dev_id; + struct atmel_mci *host = mmc_priv(mmc); + u32 status, mask, pending; + unsigned int pass_count = 0; + + spin_lock(&mmc->lock); + + do { + status = mci_readl(host, SR); + mask = mci_readl(host, IMR); + pending = status & mask; + if (!pending) + break; + + if (pending & ATMCI_DATA_ERROR_FLAGS) { + mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS + | MCI_RXRDY | MCI_TXRDY); + pending &= mci_readl(host, IMR); + host->data_status = status; + atmci_set_pending(host, EVENT_DATA_ERROR); + tasklet_schedule(&host->tasklet); + } + if (pending & MCI_NOTBUSY) { + mci_writel(host, IDR, (MCI_NOTBUSY + | ATMCI_DATA_ERROR_FLAGS)); + atmci_set_pending(host, EVENT_DATA_COMPLETE); + tasklet_schedule(&host->tasklet); + } + if (pending & MCI_RXRDY) + atmci_read_data_pio(host); + if (pending & MCI_TXRDY) + atmci_write_data_pio(host); + + if (pending & MCI_CMDRDY) + atmci_cmd_interrupt(mmc, status); + } while (pass_count++ < 5); + + spin_unlock(&mmc->lock); + + return pass_count ? IRQ_HANDLED : IRQ_NONE; +} + +static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) +{ + struct mmc_host *mmc = dev_id; + struct atmel_mci *host = mmc_priv(mmc); + + /* + * Disable interrupts until the pin has stabilized and check + * the state then. Use mod_timer() since we may be in the + * middle of the timer routine when this interrupt triggers. + */ + disable_irq_nosync(irq); + mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20)); + + return IRQ_HANDLED; +} + +static int __init atmci_probe(struct platform_device *pdev) +{ + struct mci_platform_data *pdata; + struct atmel_mci *host; + struct mmc_host *mmc; + struct resource *regs; + int irq; + int ret; + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!regs) + return -ENXIO; + pdata = pdev->dev.platform_data; + if (!pdata) + return -ENXIO; + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev); + if (!mmc) + return -ENOMEM; + + host = mmc_priv(mmc); + host->pdev = pdev; + host->mmc = mmc; + host->detect_pin = pdata->detect_pin; + host->wp_pin = pdata->wp_pin; + + host->mck = clk_get(&pdev->dev, "mci_clk"); + if (IS_ERR(host->mck)) { + ret = PTR_ERR(host->mck); + goto err_clk_get; + } + + ret = -ENOMEM; + host->regs = ioremap(regs->start, regs->end - regs->start + 1); + if (!host->regs) + goto err_ioremap; + + clk_enable(host->mck); + mci_writel(host, CR, MCI_CR_SWRST); + host->bus_hz = clk_get_rate(host->mck); + clk_disable(host->mck); + + host->mapbase = regs->start; + + mmc->ops = &atmci_ops; + mmc->f_min = (host->bus_hz + 511) / 512; + mmc->f_max = host->bus_hz / 2; + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE; + + mmc->max_hw_segs = 64; + mmc->max_phys_segs = 64; + mmc->max_req_size = 32768 * 512; + mmc->max_blk_size = 32768; + mmc->max_blk_count = 512; + + tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc); + + ret = request_irq(irq, atmci_interrupt, 0, pdev->dev.bus_id, mmc); + if (ret) + goto err_request_irq; + + /* Assume card is present if we don't have a detect pin */ + host->present = 1; + if (host->detect_pin >= 0) { + if (gpio_request(host->detect_pin, "mmc_detect")) { + dev_dbg(&mmc->class_dev, "no detect pin available\n"); + host->detect_pin = -1; + } else { + host->present = !gpio_get_value(host->detect_pin); + } + } + if (host->wp_pin >= 0) { + if (gpio_request(host->wp_pin, "mmc_wp")) { + dev_dbg(&mmc->class_dev, "no WP pin available\n"); + host->wp_pin = -1; + } + } + + platform_set_drvdata(pdev, host); + + mmc_add_host(mmc); + + if (host->detect_pin >= 0) { + setup_timer(&host->detect_timer, atmci_detect_change, + (unsigned long)host); + + ret = request_irq(gpio_to_irq(host->detect_pin), + atmci_detect_interrupt, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "mmc-detect", mmc); + if (ret) { + dev_dbg(&mmc->class_dev, + "could not request IRQ %d for detect pin\n", + gpio_to_irq(host->detect_pin)); + gpio_free(host->detect_pin); + host->detect_pin = -1; + } + } + + dev_info(&mmc->class_dev, + "Atmel MCI controller at 0x%08lx irq %d\n", + host->mapbase, irq); + + return 0; + +err_request_irq: + iounmap(host->regs); +err_ioremap: + clk_put(host->mck); +err_clk_get: + mmc_free_host(mmc); + return ret; +} + +static int __exit atmci_remove(struct platform_device *pdev) +{ + struct atmel_mci *host = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + if (host) { + if (host->detect_pin >= 0) { + int pin = host->detect_pin; + + /* Make sure the timer doesn't enable the interrupt */ + host->detect_pin = -1; + smp_wmb(); + + free_irq(gpio_to_irq(pin), host->mmc); + del_timer_sync(&host->detect_timer); + gpio_free(pin); + } + + mmc_remove_host(host->mmc); + + clk_enable(host->mck); + mci_writel(host, IDR, ~0UL); + mci_writel(host, CR, MCI_CR_MCIDIS); + mci_readl(host, SR); + clk_disable(host->mck); + + if (host->wp_pin >= 0) + gpio_free(host->wp_pin); + + free_irq(platform_get_irq(pdev, 0), host->mmc); + iounmap(host->regs); + + clk_put(host->mck); + + mmc_free_host(host->mmc); + } + return 0; +} + +static struct platform_driver atmci_driver = { + .remove = __exit_p(atmci_remove), + .driver = { + .name = "atmel_mci", + }, +}; + +static int __init atmci_init(void) +{ + return platform_driver_probe(&atmci_driver, atmci_probe); +} + +static void __exit atmci_exit(void) +{ + platform_driver_unregister(&atmci_driver); +} + +module_init(atmci_init); +module_exit(atmci_exit); + +MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); +MODULE_AUTHOR("Haavard Skinnemoen "); +MODULE_LICENSE("GPL v2"); diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h index b4cddfaca90e..a3783861cdd2 100644 --- a/include/asm-avr32/arch-at32ap/board.h +++ b/include/asm-avr32/arch-at32ap/board.h @@ -77,7 +77,11 @@ struct i2c_board_info; struct platform_device *at32_add_device_twi(unsigned int id, struct i2c_board_info *b, unsigned int n); -struct platform_device *at32_add_device_mci(unsigned int id); + +struct mci_platform_data; +struct platform_device * +at32_add_device_mci(unsigned int id, struct mci_platform_data *data); + struct platform_device *at32_add_device_ac97c(unsigned int id); struct platform_device *at32_add_device_abdac(unsigned int id); struct platform_device *at32_add_device_psif(unsigned int id); diff --git a/include/asm-avr32/atmel-mci.h b/include/asm-avr32/atmel-mci.h new file mode 100644 index 000000000000..c2ea6e1c9aa1 --- /dev/null +++ b/include/asm-avr32/atmel-mci.h @@ -0,0 +1,9 @@ +#ifndef __ASM_AVR32_ATMEL_MCI_H +#define __ASM_AVR32_ATMEL_MCI_H + +struct mci_platform_data { + int detect_pin; + int wp_pin; +}; + +#endif /* __ASM_AVR32_ATMEL_MCI_H */ -- cgit v1.2.3 From 23af60398af2f5033e2f53665538a09f498dbc03 Mon Sep 17 00:00:00 2001 From: Pierre Ossman Date: Sun, 6 Jul 2008 01:10:27 +0200 Subject: mmc: remove multiwrite capability Relax requirements on host controllers and only require that they do not report a transfer count than is larger than the actual one (i.e. a lower value is okay). This is how many other parts of the kernel behaves so upper layers should already be prepared to handle that scenario. This gives us a performance boost on MMC cards. Signed-off-by: Pierre Ossman --- drivers/mmc/card/block.c | 47 ++++++++++++++++++-------------------------- drivers/mmc/host/at91_mci.c | 2 +- drivers/mmc/host/atmel-mci.c | 2 +- drivers/mmc/host/mmc_spi.c | 5 +---- drivers/mmc/host/mmci.c | 1 - drivers/mmc/host/omap.c | 2 +- drivers/mmc/host/tifm_sd.c | 2 +- drivers/mmc/host/wbsd.c | 2 +- include/linux/mmc/host.h | 11 +++++------ 9 files changed, 30 insertions(+), 44 deletions(-) (limited to 'include') diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c index 4b0f8220f153..66e5a5487c20 100644 --- a/drivers/mmc/card/block.c +++ b/drivers/mmc/card/block.c @@ -237,17 +237,6 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) if (brq.data.blocks > card->host->max_blk_count) brq.data.blocks = card->host->max_blk_count; - /* - * If the host doesn't support multiple block writes, force - * block writes to single block. SD cards are excepted from - * this rule as they support querying the number of - * successfully written sectors. - */ - if (rq_data_dir(req) != READ && - !(card->host->caps & MMC_CAP_MULTIWRITE) && - !mmc_card_sd(card)) - brq.data.blocks = 1; - if (brq.data.blocks > 1) { /* SPI multiblock writes terminate using a special * token, not a STOP_TRANSMISSION request. @@ -367,30 +356,32 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) * mark the known good sectors as ok. * * If the card is not SD, we can still ok written sectors - * if the controller can do proper error reporting. + * as reported by the controller (which might be less than + * the real number of written sectors, but never more). * * For reads we just fail the entire chunk as that should * be safe in all cases. */ - if (rq_data_dir(req) != READ && mmc_card_sd(card)) { - u32 blocks; - unsigned int bytes; - - blocks = mmc_sd_num_wr_blocks(card); - if (blocks != (u32)-1) { - if (card->csd.write_partial) - bytes = blocks << md->block_bits; - else - bytes = blocks << 9; + if (rq_data_dir(req) != READ) { + if (mmc_card_sd(card)) { + u32 blocks; + unsigned int bytes; + + blocks = mmc_sd_num_wr_blocks(card); + if (blocks != (u32)-1) { + if (card->csd.write_partial) + bytes = blocks << md->block_bits; + else + bytes = blocks << 9; + spin_lock_irq(&md->lock); + ret = __blk_end_request(req, 0, bytes); + spin_unlock_irq(&md->lock); + } + } else { spin_lock_irq(&md->lock); - ret = __blk_end_request(req, 0, bytes); + ret = __blk_end_request(req, 0, brq.data.bytes_xfered); spin_unlock_irq(&md->lock); } - } else if (rq_data_dir(req) != READ && - (card->host->caps & MMC_CAP_MULTIWRITE)) { - spin_lock_irq(&md->lock); - ret = __blk_end_request(req, 0, brq.data.bytes_xfered); - spin_unlock_irq(&md->lock); } mmc_release_host(card->host); diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 16df235fcc2e..f15e2064305c 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -995,7 +995,7 @@ static int __init at91_mci_probe(struct platform_device *pdev) mmc->f_min = 375000; mmc->f_max = 25000000; mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ; + mmc->caps = MMC_CAP_SDIO_IRQ; mmc->max_blk_size = 4095; mmc->max_blk_count = mmc->max_req_size; diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c index 25d5324ab7e2..cce873c5a149 100644 --- a/drivers/mmc/host/atmel-mci.c +++ b/drivers/mmc/host/atmel-mci.c @@ -849,7 +849,7 @@ static int __init atmci_probe(struct platform_device *pdev) mmc->f_min = (host->bus_hz + 511) / 512; mmc->f_max = host->bus_hz / 2; mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE; + mmc->caps |= MMC_CAP_4_BIT_DATA; mmc->max_hw_segs = 64; mmc->max_phys_segs = 64; diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c index 4e82f64a96bc..41cc63360e43 100644 --- a/drivers/mmc/host/mmc_spi.c +++ b/drivers/mmc/host/mmc_spi.c @@ -1252,10 +1252,7 @@ static int mmc_spi_probe(struct spi_device *spi) mmc->ops = &mmc_spi_ops; mmc->max_blk_size = MMC_SPI_BLOCKSIZE; - /* As long as we keep track of the number of successfully - * transmitted blocks, we're good for multiwrite. - */ - mmc->caps = MMC_CAP_SPI | MMC_CAP_MULTIWRITE; + mmc->caps = MMC_CAP_SPI; /* SPI doesn't need the lowspeed device identification thing for * MMC or SD cards, since it never comes up in open drain mode. diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index da5fecad74d9..696cf3647ceb 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -535,7 +535,6 @@ static int mmci_probe(struct amba_device *dev, void *id) mmc->f_min = (host->mclk + 511) / 512; mmc->f_max = min(host->mclk, fmax); mmc->ocr_avail = plat->ocr_mask; - mmc->caps = MMC_CAP_MULTIWRITE; /* * We can do SGIO diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index 549517c35675..dbc26eb6a89e 100644 --- a/drivers/mmc/host/omap.c +++ b/drivers/mmc/host/omap.c @@ -1317,7 +1317,7 @@ static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id) host->slots[id] = slot; - mmc->caps = MMC_CAP_MULTIWRITE; + mmc->caps = 0; if (host->pdata->conf.wire4) mmc->caps |= MMC_CAP_4_BIT_DATA; diff --git a/drivers/mmc/host/tifm_sd.c b/drivers/mmc/host/tifm_sd.c index 1c14a186f000..13844843e8de 100644 --- a/drivers/mmc/host/tifm_sd.c +++ b/drivers/mmc/host/tifm_sd.c @@ -973,7 +973,7 @@ static int tifm_sd_probe(struct tifm_dev *sock) mmc->ops = &tifm_sd_ops; mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE; + mmc->caps = MMC_CAP_4_BIT_DATA; mmc->f_min = 20000000 / 60; mmc->f_max = 24000000; diff --git a/drivers/mmc/host/wbsd.c b/drivers/mmc/host/wbsd.c index f7dcd8ec0d7f..adda37952032 100644 --- a/drivers/mmc/host/wbsd.c +++ b/drivers/mmc/host/wbsd.c @@ -1219,7 +1219,7 @@ static int __devinit wbsd_alloc_mmc(struct device *dev) mmc->f_min = 375000; mmc->f_max = 24000000; mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE; + mmc->caps = MMC_CAP_4_BIT_DATA; spin_lock_init(&host->lock); diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 753b7231b887..10a2080086ca 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -111,12 +111,11 @@ struct mmc_host { unsigned long caps; /* Host capabilities */ #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ -#define MMC_CAP_MULTIWRITE (1 << 1) /* Can accurately report bytes sent to card on error */ -#define MMC_CAP_MMC_HIGHSPEED (1 << 2) /* Can do MMC high-speed timing */ -#define MMC_CAP_SD_HIGHSPEED (1 << 3) /* Can do SD high-speed timing */ -#define MMC_CAP_SDIO_IRQ (1 << 4) /* Can signal pending SDIO IRQs */ -#define MMC_CAP_SPI (1 << 5) /* Talks only SPI protocols */ -#define MMC_CAP_NEEDS_POLL (1 << 6) /* Needs polling for card-detection */ +#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ +#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ +#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ +#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ +#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ -- cgit v1.2.3 From 62a7573ee9f31d4fdb330b3e68ebf6efaba1d57c Mon Sep 17 00:00:00 2001 From: Benzi Zbit Date: Thu, 10 Jul 2008 02:41:43 +0300 Subject: sdio: fix the use of hard coded timeout value. This adds reading and using of enable_timeout from the CIS Signed-off-by: Benzi Zbit Signed-off-by: Tomas Winkler Signed-off-by: Pierre Ossman --- drivers/mmc/core/sdio_cis.c | 6 ++++++ drivers/mmc/core/sdio_io.c | 6 +----- include/linux/mmc/sdio_func.h | 2 ++ 3 files changed, 9 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/mmc/core/sdio_cis.c b/drivers/mmc/core/sdio_cis.c index d5e51b1c7b3f..956bd7677502 100644 --- a/drivers/mmc/core/sdio_cis.c +++ b/drivers/mmc/core/sdio_cis.c @@ -129,6 +129,12 @@ static int cistpl_funce_func(struct sdio_func *func, /* TPLFE_MAX_BLK_SIZE */ func->max_blksize = buf[12] | (buf[13] << 8); + /* TPLFE_ENABLE_TIMEOUT_VAL, present in ver 1.1 and above */ + if (vsn > SDIO_SDIO_REV_1_00) + func->enable_timeout = (buf[28] | (buf[29] << 8)) * 10; + else + func->enable_timeout = jiffies_to_msecs(HZ); + return 0; } diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c index 3ccf6919877c..0888df64581f 100755 --- a/drivers/mmc/core/sdio_io.c +++ b/drivers/mmc/core/sdio_io.c @@ -76,11 +76,7 @@ int sdio_enable_func(struct sdio_func *func) if (ret) goto err; - /* - * FIXME: This should timeout based on information in the CIS, - * but we don't have card to parse that yet. - */ - timeout = jiffies + HZ; + timeout = jiffies + msecs_to_jiffies(func->enable_timeout); while (1) { ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IORx, 0, ®); diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h index 28fb0a33acf8..07bee4a0d457 100755 --- a/include/linux/mmc/sdio_func.h +++ b/include/linux/mmc/sdio_func.h @@ -46,6 +46,8 @@ struct sdio_func { unsigned max_blksize; /* maximum block size */ unsigned cur_blksize; /* current block size */ + unsigned enable_timeout; /* max enable timeout in msec */ + unsigned int state; /* function state */ #define SDIO_STATE_PRESENT (1<<0) /* present in sysfs */ -- cgit v1.2.3 From fe9233fb6914a0eb20166c967e3020f7f0fba2c9 Mon Sep 17 00:00:00 2001 From: Chandra Seetharaman Date: Fri, 23 May 2008 18:16:40 -0700 Subject: [SCSI] scsi_dh: fix kconfig related build errors Do not automatically "select" SCSI_DH for dm-multipath. If SCSI_DH doesn't exist,just do not allow hardware handlers to be used. Handle SCSI_DH being a module also. Make sure it doesn't allow DM_MULTIPATH to be compiled in when SCSI_DH is a module. [jejb: added comment for Kconfig syntax] Signed-off-by: Chandra Seetharaman Reported-by: Randy Dunlap Reported-by: Andrew Morton Signed-off-by: James Bottomley --- drivers/md/Kconfig | 6 +++++- drivers/md/dm-mpath.c | 2 ++ include/scsi/scsi_dh.h | 12 +++++++++++- 3 files changed, 18 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/md/Kconfig b/drivers/md/Kconfig index b4a3c7d1451d..07d92c11b5d8 100644 --- a/drivers/md/Kconfig +++ b/drivers/md/Kconfig @@ -252,7 +252,11 @@ config DM_ZERO config DM_MULTIPATH tristate "Multipath target" depends on BLK_DEV_DM - select SCSI_DH + # nasty syntax but means make DM_MULTIPATH independent + # of SCSI_DH if the latter isn't defined but if + # it is, DM_MULTIPATH must depend on it. We get a build + # error if SCSI_DH=m and DM_MULTIPATH=y + depends on SCSI_DH || !SCSI_DH ---help--- Allow volume managers to support multipath hardware. diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index e8f704aa46f2..9f7302d4878d 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -664,6 +664,8 @@ static int parse_hw_handler(struct arg_set *as, struct multipath *m) request_module("scsi_dh_%s", m->hw_handler_name); if (scsi_dh_handler_exist(m->hw_handler_name) == 0) { ti->error = "unknown hardware handler type"; + kfree(m->hw_handler_name); + m->hw_handler_name = NULL; return -EINVAL; } consume(as, hw_argc - 1); diff --git a/include/scsi/scsi_dh.h b/include/scsi/scsi_dh.h index 04d0d8495c83..3ad2303d1a16 100644 --- a/include/scsi/scsi_dh.h +++ b/include/scsi/scsi_dh.h @@ -54,6 +54,16 @@ enum { SCSI_DH_NOSYS, SCSI_DH_DRIVER_MAX, }; - +#if defined(CONFIG_SCSI_DH) || defined(CONFIG_SCSI_DH_MODULE) extern int scsi_dh_activate(struct request_queue *); extern int scsi_dh_handler_exist(const char *); +#else +static inline int scsi_dh_activate(struct request_queue *req) +{ + return 0; +} +static inline int scsi_dh_handler_exist(const char *name) +{ + return 0; +} +#endif -- cgit v1.2.3 From 2954c02a884dc0ba9e91882c0aba13bcb9d22e6c Mon Sep 17 00:00:00 2001 From: "Chen, Huacai" Date: Tue, 10 Jun 2008 09:05:08 +0800 Subject: [MIPS] modify the MIPS CPU classfication Signed-off-by: Huacai Chen Signed-off-by: Ralf Baechle --- include/asm-mips/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 1c35cac6f35b..229a786101d9 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -66,8 +66,10 @@ #define PRID_IMP_RM7000 0x2700 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ #define PRID_IMP_RM9000 0x3400 +#define PRID_IMP_LOONGSON1 0x4200 #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 +#define PRID_IMP_LOONGSON2 0x6300 #define PRID_IMP_UNKNOWN 0xff00 @@ -90,8 +92,6 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 -#define PRID_IMP_LOONGSON1 0x4200 -#define PRID_IMP_LOONGSON2 0x6300 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE -- cgit v1.2.3 From cb11dfa0247df479e384c4a7ab6846f3a6bf1570 Mon Sep 17 00:00:00 2001 From: David Daney Date: Mon, 9 Jun 2008 16:30:03 -0700 Subject: [MIPS] Remove board_watchpoint_handler It is not used anywhere in tree. Signed-off-by: David Daney Signed-off-by: Andrew Morton Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 6 ------ include/asm-mips/traps.h | 1 - 2 files changed, 7 deletions(-) (limited to 'include') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index f9165d1a17bf..6e7e4a2775f6 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -71,7 +71,6 @@ extern asmlinkage void handle_reserved(void); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu); -void (*board_watchpoint_handler)(struct pt_regs *regs); void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); void (*board_nmi_handler_setup)(void); @@ -892,11 +891,6 @@ asmlinkage void do_mdmx(struct pt_regs *regs) asmlinkage void do_watch(struct pt_regs *regs) { - if (board_watchpoint_handler) { - (*board_watchpoint_handler)(regs); - return; - } - /* * We use the watch exception where available to detect stack * overflows. diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h index e5dbde625ec2..90ff2f497c50 100644 --- a/include/asm-mips/traps.h +++ b/include/asm-mips/traps.h @@ -24,6 +24,5 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); extern void (*board_nmi_handler_setup)(void); extern void (*board_ejtag_handler_setup)(void); extern void (*board_bind_eic_interrupt)(int irq, int regset); -extern void (*board_watchpoint_handler)(struct pt_regs *regs); #endif /* _ASM_TRAPS_H */ -- cgit v1.2.3 From c88a8b4ab0e1a1f06938939d9ba42e9da6144ccb Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 9 Jun 2008 17:19:53 +0100 Subject: [MIPS] Remove obsolete isa_slot_offset The isa_slot_offset variable and its __ISA_IO_base macro is not used anywhere anymore. It does not look like a decent interface per today's standards either. Remove both including all places of initialization. Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle --- arch/mips/jazz/setup.c | 1 - arch/mips/kernel/setup.c | 7 ------- arch/mips/pci/pci-bcm1480.c | 2 -- arch/mips/pci/pci-sb1250.c | 3 --- arch/mips/sni/setup.c | 1 - include/asm-mips/io.h | 17 ----------------- 6 files changed, 31 deletions(-) (limited to 'include') diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index a7947199c99b..f136c8a8591c 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -79,7 +79,6 @@ void __init plat_mem_setup(void) if (mips_machtype == MACH_MIPS_MAGNUM_4000) EISA_bus = 1; #endif - isa_slot_offset = 0xe3000000; /* request I/O space for devices used on all i[345]86 PCs */ for (i = 0; i < ARRAY_SIZE(jazz_io_resources); i++) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index c6a063b2a0d9..c04e4e3afede 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -68,13 +68,6 @@ static char command_line[CL_SIZE]; const unsigned long mips_io_port_base __read_mostly = -1; EXPORT_SYMBOL(mips_io_port_base); -/* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. - */ -unsigned long isa_slot_offset; -EXPORT_SYMBOL(isa_slot_offset); - static struct resource code_resource = { .name = "Kernel code", }; static struct resource data_resource = { .name = "Kernel data", }; diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index 87e2c8f54e2d..d19d262157f2 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -254,8 +254,6 @@ static int __init bcm1480_pcibios_init(void) ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536); bcm1480_controller.io_map_base -= bcm1480_controller.io_offset; set_io_port_base(bcm1480_controller.io_map_base); - isa_slot_offset = (unsigned long) - ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024); register_pci_controller(&bcm1480_controller); diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 2a09ad91ec8c..9bc102a1380e 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -254,9 +254,6 @@ static int __init sb1250_pcibios_init(void) * works correctly with most of Linux's drivers. * XXX ehs: Should this happen in PCI Device mode? */ - isa_slot_offset = (unsigned long) - ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024); - io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024); sb1250_controller.io_map_base = io_map_base; set_io_port_base((unsigned long)io_map_base); diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 5484e1c62054..a49272ce7ef5 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -116,7 +116,6 @@ void __init plat_mem_setup(void) /* * Setup (E)ISA I/O memory access stuff */ - isa_slot_offset = CKSEG1ADDR(0xb0000000); #ifdef CONFIG_EISA EISA_bus = 1; #endif diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index f18d2816cbec..501a40b9f18d 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -160,13 +160,6 @@ static inline void * isa_bus_to_virt(unsigned long address) #define virt_to_bus virt_to_phys #define bus_to_virt phys_to_virt -/* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. This implies the assumption that there is only - * one of these busses. - */ -extern unsigned long isa_slot_offset; - /* * Change "struct page" to physical address. */ @@ -527,16 +520,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int memcpy((void __force *) dst, src, count); } -/* - * ISA space is 'always mapped' on currently supported MIPS systems, no need - * to explicitly ioremap() it. The fact that the ISA IO space is mapped - * to PAGE_OFFSET is pure coincidence - it does not mean ISA values - * are physical addresses. The following constant pointer can be - * used as the IO-area pointer (it can be iounmapped as well, so the - * analogy with PCI is quite large): - */ -#define __ISA_IO_base ((char *)(isa_slot_offset)) - /* * The caches on some architectures aren't dma-coherent and have need to * handle this in software. There are three types of operations that -- cgit v1.2.3 From 07cdb78436d52416a582e645b9afb6e26f986bc9 Mon Sep 17 00:00:00 2001 From: Dmitri Vorobiev Date: Thu, 29 May 2008 17:57:08 +0300 Subject: [MIPS] fix sparse warning about setup_early_printk() This patch fixes the following sparse warning: <<<<<<<< arch/mips/kernel/early_printk.c:35:13: warning: symbol 'setup_early_printk' was not declared. Should it be static? <<<<<<<< The fix is to define a prototype of the setup_early_printk() function and to include the appropriate header into arch/mips/kernel/early_printk.c. [Ralf: Sorted includes again] Signed-off-by: Dmitri Vorobiev Signed-off-by: Ralf Baechle --- arch/mips/kernel/early_printk.c | 2 ++ arch/mips/kernel/setup.c | 6 +----- include/asm-mips/setup.h | 2 ++ 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c index 9dccfa4752b2..9ae813eb782e 100644 --- a/arch/mips/kernel/early_printk.c +++ b/arch/mips/kernel/early_printk.c @@ -10,6 +10,8 @@ #include #include +#include + extern void prom_putchar(char); static void __init diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index c04e4e3afede..8af84867e74d 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -550,11 +550,7 @@ void __init setup_arch(char **cmdline_p) prom_init(); #ifdef CONFIG_EARLY_PRINTK - { - extern void setup_early_printk(void); - - setup_early_printk(); - } + setup_early_printk(); #endif cpu_report(); check_bugs_early(); diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h index 70009a902639..883f59bfa097 100644 --- a/include/asm-mips/setup.h +++ b/include/asm-mips/setup.h @@ -3,4 +3,6 @@ #define COMMAND_LINE_SIZE 256 +extern void setup_early_printk(void); + #endif /* __SETUP_H */ -- cgit v1.2.3 From 997288517ec839b7639fcba77111256b13a66000 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Mon, 9 Jun 2008 08:39:58 +0200 Subject: [MIPS] Alchemy: remove unused MMC macros from db1x00 header. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- include/asm-mips/mach-db1x00/db1x00.h | 45 ----------------------------------- 1 file changed, 45 deletions(-) (limited to 'include') diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h index 612ae90dbcb8..1a515b8c870f 100644 --- a/include/asm-mips/mach-db1x00/db1x00.h +++ b/include/asm-mips/mach-db1x00/db1x00.h @@ -145,51 +145,6 @@ typedef volatile struct #define SET_VCC_VPP(VCC, VPP, SLOT)\ ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) -/* - * SD controller macros - */ - -/* Detect card. */ -#define mmc_card_inserted(_n_, _res_) \ - do { \ - BCSR * const bcsr = (BCSR *)0xAE000000; \ - unsigned long mmc_wp, board_specific; \ - if ((_n_)) { \ - mmc_wp = BCSR_BOARD_SD1_WP; \ - } else { \ - mmc_wp = BCSR_BOARD_SD0_WP; \ - } \ - board_specific = au_readl((unsigned long)(&bcsr->specific)); \ - if (!(board_specific & mmc_wp)) {/* low means card present */ \ - *(int *)(_res_) = 1; \ - } else { \ - *(int *)(_res_) = 0; \ - } \ - } while (0) - -/* - * Apply power to card slot(s). - */ -#define mmc_power_on(_n_) \ - do { \ - BCSR * const bcsr = (BCSR *)0xAE000000; \ - unsigned long mmc_pwr, mmc_wp, board_specific; \ - if ((_n_)) { \ - mmc_pwr = BCSR_BOARD_SD1_PWR; \ - mmc_wp = BCSR_BOARD_SD1_WP; \ - } else { \ - mmc_pwr = BCSR_BOARD_SD0_PWR; \ - mmc_wp = BCSR_BOARD_SD0_WP; \ - } \ - board_specific = au_readl((unsigned long)(&bcsr->specific)); \ - if (!(board_specific & mmc_wp)) {/* low means card present */ \ - board_specific |= mmc_pwr; \ - au_writel(board_specific, (int)(&bcsr->specific)); \ - au_sync(); \ - } \ - } while (0) - - /* * NAND defines * -- cgit v1.2.3 From 2957c9e61ee9c37e7ebf2c8acab03e073fe942fd Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 15 Jul 2008 18:44:30 +0100 Subject: [MIPS] IRIX: Goodbye and thanks for all the fish Never terribly functional or popular, plagued by hard to fix bugs the time to say goodbye has more than arrived. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 4 - arch/mips/kernel/Makefile | 4 - arch/mips/kernel/irix5sys.S | 1041 ------------------- arch/mips/kernel/irixelf.c | 1361 ------------------------- arch/mips/kernel/irixinv.c | 78 -- arch/mips/kernel/irixioctl.c | 213 ---- arch/mips/kernel/irixsig.c | 888 ----------------- arch/mips/kernel/process.c | 7 - arch/mips/kernel/scall32-o32.S | 19 - arch/mips/kernel/sysirix.c | 2140 ---------------------------------------- include/asm-mips/inventory.h | 24 - include/asm-mips/namei.h | 25 +- include/asm-mips/prctl.h | 41 - include/asm-mips/signal.h | 3 - 14 files changed, 5 insertions(+), 5843 deletions(-) delete mode 100644 arch/mips/kernel/irix5sys.S delete mode 100644 arch/mips/kernel/irixelf.c delete mode 100644 arch/mips/kernel/irixinv.c delete mode 100644 arch/mips/kernel/irixioctl.c delete mode 100644 arch/mips/kernel/irixsig.c delete mode 100644 arch/mips/kernel/sysirix.c delete mode 100644 include/asm-mips/inventory.h delete mode 100644 include/asm-mips/prctl.h (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 24c5dee91768..21d6ec1e5368 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2064,10 +2064,6 @@ source "fs/Kconfig.binfmt" config TRAD_SIGNALS bool -config BINFMT_IRIX - bool "Include IRIX binary compatibility" - depends on CPU_BIG_ENDIAN && 32BIT && BROKEN - config MIPS32_COMPAT bool "Kernel support for Linux/MIPS 32-bit binary compatibility" depends on 64BIT diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 65e46a6d4178..48ae915b38e0 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -20,9 +20,6 @@ obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o -binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ - irix5sys.o sysirix.o - obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += mips_ksyms.o module.o @@ -70,7 +67,6 @@ obj-$(CONFIG_IRQ_GIC) += irq-gic.o obj-$(CONFIG_32BIT) += scall32-o32.o obj-$(CONFIG_64BIT) += scall64-64.o -obj-$(CONFIG_BINFMT_IRIX) += binfmt_irix.o obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o diff --git a/arch/mips/kernel/irix5sys.S b/arch/mips/kernel/irix5sys.S deleted file mode 100644 index eeef891093ed..000000000000 --- a/arch/mips/kernel/irix5sys.S +++ /dev/null @@ -1,1041 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * 32-bit IRIX5 ABI system call table derived from original file 'irix5sys.h' - * created by David S. Miller. - * - * Copyright (C) 1996 - 2004 David S. Miller - * Copyright (C) 2004 Steven J. Hill - */ -#include - - /* - * Key: - * V == Valid and should work as expected for most cases. - * HV == Half Valid, some things will work, some likely will not - * IV == InValid, certainly will not work at all yet - * ?V == ?'ably Valid, I have not done enough looking into it - * DC == Don't Care, a rats ass we couldn't give - */ - - .macro irix5syscalltable - - sys sys_syscall 0 /* 1000 sysindir() V*/ - sys sys_exit 1 /* 1001 exit() V*/ - sys sys_fork 0 /* 1002 fork() V*/ - sys sys_read 3 /* 1003 read() V*/ - sys sys_write 3 /* 1004 write() V*/ - sys sys_open 3 /* 1005 open() V*/ - sys sys_close 1 /* 1006 close() V*/ - sys irix_unimp 0 /* 1007 (XXX IRIX 4 wait) V*/ - sys sys_creat 2 /* 1008 creat() V*/ - sys sys_link 2 /* 1009 link() V*/ - sys sys_unlink 1 /* 1010 unlink() V*/ - sys irix_exec 0 /* 1011 exec() V*/ - sys sys_chdir 1 /* 1012 chdir() V*/ - sys irix_gtime 0 /* 1013 time() V*/ - sys irix_unimp 0 /* 1014 (XXX IRIX 4 mknod) V*/ - sys sys_chmod 2 /* 1015 chmod() V*/ - sys sys_chown 3 /* 1016 chown() V*/ - sys irix_brk 1 /* 1017 break() V*/ - sys irix_unimp 0 /* 1018 (XXX IRIX 4 stat) V*/ - sys sys_lseek 3 /* 1019 lseek() XXX64bit HV*/ - sys irix_getpid 0 /* 1020 getpid() V*/ - sys irix_mount 6 /* 1021 mount() IV*/ - sys sys_umount 1 /* 1022 umount() V*/ - sys sys_setuid 1 /* 1023 setuid() V*/ - sys irix_getuid 0 /* 1024 getuid() V*/ - sys irix_stime 1 /* 1025 stime() V*/ - sys irix_unimp 4 /* 1026 XXX ptrace() IV*/ - sys irix_alarm 1 /* 1027 alarm() V*/ - sys irix_unimp 0 /* 1028 (XXX IRIX 4 fstat) V*/ - sys irix_pause 0 /* 1029 pause() V*/ - sys sys_utime 2 /* 1030 utime() V*/ - sys irix_unimp 0 /* 1031 nuthin' V*/ - sys irix_unimp 0 /* 1032 nobody home man... V*/ - sys sys_access 2 /* 1033 access() V*/ - sys sys_nice 1 /* 1034 nice() V*/ - sys irix_statfs 2 /* 1035 statfs() V*/ - sys sys_sync 0 /* 1036 sync() V*/ - sys sys_kill 2 /* 1037 kill() V*/ - sys irix_fstatfs 2 /* 1038 fstatfs() V*/ - sys irix_setpgrp 1 /* 1039 setpgrp() V*/ - sys irix_syssgi 0 /* 1040 syssgi() HV*/ - sys sys_dup 1 /* 1041 dup() V*/ - sys sys_pipe 0 /* 1042 pipe() V*/ - sys irix_times 1 /* 1043 times() V*/ - sys irix_unimp 0 /* 1044 XXX profil() IV*/ - sys irix_unimp 0 /* 1045 XXX lock() IV*/ - sys sys_setgid 1 /* 1046 setgid() V*/ - sys irix_getgid 0 /* 1047 getgid() V*/ - sys irix_unimp 0 /* 1048 (XXX IRIX 4 ssig) V*/ - sys irix_msgsys 6 /* 1049 sys_msgsys V*/ - sys sys_sysmips 4 /* 1050 sysmips() HV*/ - sys irix_unimp 0 /* 1051 XXX sysacct() IV*/ - sys irix_shmsys 5 /* 1052 sys_shmsys V*/ - sys irix_semsys 0 /* 1053 sys_semsys V*/ - sys irix_ioctl 3 /* 1054 ioctl() HV*/ - sys irix_uadmin 0 /* 1055 XXX sys_uadmin() HC*/ - sys irix_sysmp 0 /* 1056 sysmp() HV*/ - sys irix_utssys 4 /* 1057 sys_utssys() HV*/ - sys irix_unimp 0 /* 1058 nada enchilada V*/ - sys irix_exece 0 /* 1059 exece() V*/ - sys sys_umask 1 /* 1060 umask() V*/ - sys sys_chroot 1 /* 1061 chroot() V*/ - sys irix_fcntl 3 /* 1062 fcntl() ?V*/ - sys irix_ulimit 2 /* 1063 ulimit() HV*/ - sys irix_unimp 0 /* 1064 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1065 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1066 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1067 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1068 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1069 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1070 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1071 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1072 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1073 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1074 nuttin' V*/ - sys irix_unimp 0 /* 1075 XXX sys_getrlimit64()IV*/ - sys irix_unimp 0 /* 1076 XXX sys_setrlimit64()IV*/ - sys sys_nanosleep 2 /* 1077 nanosleep() V*/ - sys irix_lseek64 5 /* 1078 lseek64() ?V*/ - sys sys_rmdir 1 /* 1079 rmdir() V*/ - sys sys_mkdir 2 /* 1080 mkdir() V*/ - sys sys_getdents 3 /* 1081 getdents() V*/ - sys irix_sginap 1 /* 1082 sys_sginap() V*/ - sys irix_sgikopt 3 /* 1083 sys_sgikopt() DC*/ - sys sys_sysfs 3 /* 1084 sysfs() ?V*/ - sys irix_unimp 0 /* 1085 XXX sys_getmsg() DC*/ - sys irix_unimp 0 /* 1086 XXX sys_putmsg() DC*/ - sys sys_poll 3 /* 1087 poll() V*/ - sys irix_sigreturn 0 /* 1088 sigreturn() ?V*/ - sys sys_accept 3 /* 1089 accept() V*/ - sys sys_bind 3 /* 1090 bind() V*/ - sys sys_connect 3 /* 1091 connect() V*/ - sys irix_gethostid 0 /* 1092 sys_gethostid() ?V*/ - sys sys_getpeername 3 /* 1093 getpeername() V*/ - sys sys_getsockname 3 /* 1094 getsockname() V*/ - sys sys_getsockopt 5 /* 1095 getsockopt() V*/ - sys sys_listen 2 /* 1096 listen() V*/ - sys sys_recv 4 /* 1097 recv() V*/ - sys sys_recvfrom 6 /* 1098 recvfrom() V*/ - sys sys_recvmsg 3 /* 1099 recvmsg() V*/ - sys sys_select 5 /* 1100 select() V*/ - sys sys_send 4 /* 1101 send() V*/ - sys sys_sendmsg 3 /* 1102 sendmsg() V*/ - sys sys_sendto 6 /* 1103 sendto() V*/ - sys irix_sethostid 1 /* 1104 sys_sethostid() ?V*/ - sys sys_setsockopt 5 /* 1105 setsockopt() V*/ - sys sys_shutdown 2 /* 1106 shutdown() ?V*/ - sys irix_socket 3 /* 1107 socket() V*/ - sys sys_gethostname 2 /* 1108 sys_gethostname() ?V*/ - sys sys_sethostname 2 /* 1109 sethostname() ?V*/ - sys irix_getdomainname 2 /* 1110 sys_getdomainname() ?V*/ - sys sys_setdomainname 2 /* 1111 setdomainname() ?V*/ - sys sys_truncate 2 /* 1112 truncate() V*/ - sys sys_ftruncate 2 /* 1113 ftruncate() V*/ - sys sys_rename 2 /* 1114 rename() V*/ - sys sys_symlink 2 /* 1115 symlink() V*/ - sys sys_readlink 3 /* 1116 readlink() V*/ - sys irix_unimp 0 /* 1117 XXX IRIX 4 lstat() DC*/ - sys irix_unimp 0 /* 1118 nothin' V*/ - sys irix_unimp 0 /* 1119 XXX nfs_svc() DC*/ - sys irix_unimp 0 /* 1120 XXX nfs_getfh() DC*/ - sys irix_unimp 0 /* 1121 XXX async_daemon() DC*/ - sys irix_unimp 0 /* 1122 XXX exportfs() DC*/ - sys sys_setregid 2 /* 1123 setregid() V*/ - sys sys_setreuid 2 /* 1124 setreuid() V*/ - sys sys_getitimer 2 /* 1125 getitimer() V*/ - sys sys_setitimer 3 /* 1126 setitimer() V*/ - sys irix_unimp 1 /* 1127 XXX adjtime() IV*/ - sys irix_gettimeofday 1 /* 1128 gettimeofday() V*/ - sys irix_unimp 0 /* 1129 XXX sproc() IV*/ - sys irix_prctl 0 /* 1130 prctl() HV*/ - sys irix_unimp 0 /* 1131 XXX procblk() IV*/ - sys irix_unimp 0 /* 1132 XXX sprocsp() IV*/ - sys irix_unimp 0 /* 1133 XXX sgigsc() IV*/ - sys irix_mmap32 6 /* 1134 mmap() XXXflags? ?V*/ - sys sys_munmap 2 /* 1135 munmap() V*/ - sys sys_mprotect 3 /* 1136 mprotect() V*/ - sys sys_msync 4 /* 1137 msync() V*/ - sys irix_madvise 3 /* 1138 madvise() DC*/ - sys irix_pagelock 3 /* 1139 pagelock() IV*/ - sys irix_getpagesize 0 /* 1140 getpagesize() V*/ - sys irix_quotactl 0 /* 1141 quotactl() V*/ - sys irix_unimp 0 /* 1142 nobody home man V*/ - sys sys_getpgid 1 /* 1143 BSD getpgrp() V*/ - sys irix_BSDsetpgrp 2 /* 1143 BSD setpgrp() V*/ - sys sys_vhangup 0 /* 1144 vhangup() V*/ - sys sys_fsync 1 /* 1145 fsync() V*/ - sys sys_fchdir 1 /* 1146 fchdir() V*/ - sys sys_getrlimit 2 /* 1147 getrlimit() ?V*/ - sys sys_setrlimit 2 /* 1148 setrlimit() ?V*/ - sys sys_cacheflush 3 /* 1150 cacheflush() HV*/ - sys sys_cachectl 3 /* 1151 cachectl() HV*/ - sys sys_fchown 3 /* 1152 fchown() ?V*/ - sys sys_fchmod 2 /* 1153 fchmod() ?V*/ - sys irix_unimp 0 /* 1154 XXX IRIX 4 wait3() V*/ - sys sys_socketpair 4 /* 1155 socketpair() V*/ - sys irix_systeminfo 3 /* 1156 systeminfo() IV*/ - sys irix_uname 1 /* 1157 uname() IV*/ - sys irix_xstat 3 /* 1158 xstat() V*/ - sys irix_lxstat 3 /* 1159 lxstat() V*/ - sys irix_fxstat 3 /* 1160 fxstat() V*/ - sys irix_xmknod 0 /* 1161 xmknod() ?V*/ - sys irix_sigaction 4 /* 1162 sigaction() ?V*/ - sys irix_sigpending 1 /* 1163 sigpending() ?V*/ - sys irix_sigprocmask 3 /* 1164 sigprocmask() ?V*/ - sys irix_sigsuspend 0 /* 1165 sigsuspend() ?V*/ - sys irix_sigpoll_sys 3 /* 1166 sigpoll_sys() IV*/ - sys irix_swapctl 2 /* 1167 swapctl() IV*/ - sys irix_getcontext 0 /* 1168 getcontext() HV*/ - sys irix_setcontext 0 /* 1169 setcontext() HV*/ - sys irix_waitsys 5 /* 1170 waitsys() IV*/ - sys irix_sigstack 2 /* 1171 sigstack() HV*/ - sys irix_sigaltstack 2 /* 1172 sigaltstack() HV*/ - sys irix_sigsendset 2 /* 1173 sigsendset() IV*/ - sys irix_statvfs 2 /* 1174 statvfs() V*/ - sys irix_fstatvfs 2 /* 1175 fstatvfs() V*/ - sys irix_unimp 0 /* 1176 XXX getpmsg() DC*/ - sys irix_unimp 0 /* 1177 XXX putpmsg() DC*/ - sys sys_lchown 3 /* 1178 lchown() V*/ - sys irix_priocntl 0 /* 1179 priocntl() DC*/ - sys irix_sigqueue 4 /* 1180 sigqueue() IV*/ - sys sys_readv 3 /* 1181 readv() V*/ - sys sys_writev 3 /* 1182 writev() V*/ - sys irix_truncate64 4 /* 1183 truncate64() XX32bit HV*/ - sys irix_ftruncate64 4 /* 1184 ftruncate64()XX32bit HV*/ - sys irix_mmap64 0 /* 1185 mmap64() XX32bit HV*/ - sys irix_dmi 0 /* 1186 dmi() DC*/ - sys irix_pread 6 /* 1187 pread() IV*/ - sys irix_pwrite 6 /* 1188 pwrite() IV*/ - sys sys_fsync 1 /* 1189 fdatasync() XXPOSIX HV*/ - sys irix_sgifastpath 7 /* 1190 sgifastpath() WHEEE IV*/ - sys irix_unimp 0 /* 1191 XXX attr_get() DC*/ - sys irix_unimp 0 /* 1192 XXX attr_getf() DC*/ - sys irix_unimp 0 /* 1193 XXX attr_set() DC*/ - sys irix_unimp 0 /* 1194 XXX attr_setf() DC*/ - sys irix_unimp 0 /* 1195 XXX attr_remove() DC*/ - sys irix_unimp 0 /* 1196 XXX attr_removef() DC*/ - sys irix_unimp 0 /* 1197 XXX attr_list() DC*/ - sys irix_unimp 0 /* 1198 XXX attr_listf() DC*/ - sys irix_unimp 0 /* 1199 XXX attr_multi() DC*/ - sys irix_unimp 0 /* 1200 XXX attr_multif() DC*/ - sys irix_statvfs64 2 /* 1201 statvfs64() V*/ - sys irix_fstatvfs64 2 /* 1202 fstatvfs64() V*/ - sys irix_getmountid 2 /* 1203 getmountid()XXXfsids HV*/ - sys irix_nsproc 5 /* 1204 nsproc() IV*/ - sys irix_getdents64 3 /* 1205 getdents64() HV*/ - sys irix_unimp 0 /* 1206 XXX DFS garbage DC*/ - sys irix_ngetdents 4 /* 1207 ngetdents() XXXeop HV*/ - sys irix_ngetdents64 4 /* 1208 ngetdents64() XXXeop HV*/ - sys irix_unimp 0 /* 1209 nothin' V*/ - sys irix_unimp 0 /* 1210 XXX pidsprocsp() */ - sys irix_unimp 0 /* 1211 XXX rexec() */ - sys irix_unimp 0 /* 1212 XXX timer_create() */ - sys irix_unimp 0 /* 1213 XXX timer_delete() */ - sys irix_unimp 0 /* 1214 XXX timer_settime() */ - sys irix_unimp 0 /* 1215 XXX timer_gettime() */ - sys irix_unimp 0 /* 1216 XXX timer_setoverrun() */ - sys sys_sched_rr_get_interval 2 /* 1217 sched_rr_get_interval()V*/ - sys sys_sched_yield 0 /* 1218 sched_yield() V*/ - sys sys_sched_getscheduler 1 /* 1219 sched_getscheduler() V*/ - sys sys_sched_setscheduler 3 /* 1220 sched_setscheduler() V*/ - sys sys_sched_getparam 2 /* 1221 sched_getparam() V*/ - sys sys_sched_setparam 2 /* 1222 sched_setparam() V*/ - sys irix_unimp 0 /* 1223 XXX usync_cntl() */ - sys irix_unimp 0 /* 1224 XXX psema_cntl() */ - sys irix_unimp 0 /* 1225 XXX restartreturn() */ - - /* Just to pad things out nicely. */ - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - 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sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - - .endm - - /* - * Pre-compute the number of _instruction_ bytes needed to load - * or store the arguments 6-8. Negative values are ignored. - */ - .macro sys function, nargs - PTR \function - LONG (\nargs << 2) - (5 << 2) - .endm - - .align 4 -EXPORT(sys_call_table_irix5) - irix5syscalltable diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c deleted file mode 100644 index 469c7237e5ba..000000000000 --- a/arch/mips/kernel/irixelf.c +++ /dev/null @@ -1,1361 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * irixelf.c: Code to load IRIX ELF executables conforming to the MIPS ABI. - * Based off of work by Eric Youngdale. - * - * Copyright (C) 1993 - 1994 Eric Youngdale - * Copyright (C) 1996 - 2004 David S. Miller - * Copyright (C) 2004 - 2005 Steven J. Hill - */ -#undef DEBUG - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define DLINFO_ITEMS 12 - -#include - -static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs); -static int load_irix_library(struct file *); -static int irix_core_dump(long signr, struct pt_regs * regs, - struct file *file, unsigned long limit); - -static struct linux_binfmt irix_format = { - .module = THIS_MODULE, - .load_binary = load_irix_binary, - .load_shlib = load_irix_library, - .core_dump = irix_core_dump, - .min_coredump = PAGE_SIZE, -}; - -/* Debugging routines. */ -static char *get_elf_p_type(Elf32_Word p_type) -{ -#ifdef DEBUG - switch (p_type) { - case PT_NULL: - return "PT_NULL"; - break; - - case PT_LOAD: - return "PT_LOAD"; - break; - - case PT_DYNAMIC: - return "PT_DYNAMIC"; - break; - - case PT_INTERP: - return "PT_INTERP"; - break; - - case PT_NOTE: - return "PT_NOTE"; - break; - - case PT_SHLIB: - return "PT_SHLIB"; - break; - - case PT_PHDR: - return "PT_PHDR"; - break; - - case PT_LOPROC: - return "PT_LOPROC/REGINFO"; - break; - - case PT_HIPROC: - return "PT_HIPROC"; - break; - - default: - return "PT_BOGUS"; - break; - } -#endif -} - -static void print_elfhdr(struct elfhdr *ehp) -{ - int i; - - pr_debug("ELFHDR: e_ident<"); - for (i = 0; i < (EI_NIDENT - 1); i++) - pr_debug("%x ", ehp->e_ident[i]); - pr_debug("%x>\n", ehp->e_ident[i]); - pr_debug(" e_type[%04x] e_machine[%04x] e_version[%08lx]\n", - (unsigned short) ehp->e_type, (unsigned short) ehp->e_machine, - (unsigned long) ehp->e_version); - pr_debug(" e_entry[%08lx] e_phoff[%08lx] e_shoff[%08lx] " - "e_flags[%08lx]\n", - (unsigned long) ehp->e_entry, (unsigned long) ehp->e_phoff, - (unsigned long) ehp->e_shoff, (unsigned long) ehp->e_flags); - pr_debug(" e_ehsize[%04x] e_phentsize[%04x] e_phnum[%04x]\n", - (unsigned short) ehp->e_ehsize, - (unsigned short) ehp->e_phentsize, - (unsigned short) ehp->e_phnum); - pr_debug(" e_shentsize[%04x] e_shnum[%04x] e_shstrndx[%04x]\n", - (unsigned short) ehp->e_shentsize, - (unsigned short) ehp->e_shnum, - (unsigned short) ehp->e_shstrndx); -} - -static void print_phdr(int i, struct elf_phdr *ep) -{ - pr_debug("PHDR[%d]: p_type[%s] p_offset[%08lx] p_vaddr[%08lx] " - "p_paddr[%08lx]\n", i, get_elf_p_type(ep->p_type), - (unsigned long) ep->p_offset, (unsigned long) ep->p_vaddr, - (unsigned long) ep->p_paddr); - pr_debug(" p_filesz[%08lx] p_memsz[%08lx] p_flags[%08lx] " - "p_align[%08lx]\n", (unsigned long) ep->p_filesz, - (unsigned long) ep->p_memsz, (unsigned long) ep->p_flags, - (unsigned long) ep->p_align); -} - -static void dump_phdrs(struct elf_phdr *ep, int pnum) -{ - int i; - - for (i = 0; i < pnum; i++, ep++) { - if ((ep->p_type == PT_LOAD) || - (ep->p_type == PT_INTERP) || - (ep->p_type == PT_PHDR)) - print_phdr(i, ep); - } -} - -static void set_brk(unsigned long start, unsigned long end) -{ - start = PAGE_ALIGN(start); - end = PAGE_ALIGN(end); - if (end <= start) - return; - down_write(¤t->mm->mmap_sem); - do_brk(start, end - start); - up_write(¤t->mm->mmap_sem); -} - - -/* We need to explicitly zero any fractional pages - * after the data section (i.e. bss). This would - * contain the junk from the file that should not - * be in memory. - */ -static void padzero(unsigned long elf_bss) -{ - unsigned long nbyte; - - nbyte = elf_bss & (PAGE_SIZE-1); - if (nbyte) { - nbyte = PAGE_SIZE - nbyte; - clear_user((void __user *) elf_bss, nbyte); - } -} - -static unsigned long * create_irix_tables(char * p, int argc, int envc, - struct elfhdr * exec, unsigned int load_addr, - unsigned int interp_load_addr, struct pt_regs *regs, - struct elf_phdr *ephdr) -{ - elf_addr_t *argv; - elf_addr_t *envp; - elf_addr_t *sp, *csp; - - pr_debug("create_irix_tables: p[%p] argc[%d] envc[%d] " - "load_addr[%08x] interp_load_addr[%08x]\n", - p, argc, envc, load_addr, interp_load_addr); - - sp = (elf_addr_t *) (~15UL & (unsigned long) p); - csp = sp; - csp -= exec ? DLINFO_ITEMS*2 : 2; - csp -= envc+1; - csp -= argc+1; - csp -= 1; /* argc itself */ - if ((unsigned long)csp & 15UL) { - sp -= (16UL - ((unsigned long)csp & 15UL)) / sizeof(*sp); - } - - /* - * Put the ELF interpreter info on the stack - */ -#define NEW_AUX_ENT(nr, id, val) \ - __put_user((id), sp+(nr*2)); \ - __put_user((val), sp+(nr*2+1)); \ - - sp -= 2; - NEW_AUX_ENT(0, AT_NULL, 0); - - if (exec) { - sp -= 11*2; - - NEW_AUX_ENT(0, AT_PHDR, load_addr + exec->e_phoff); - NEW_AUX_ENT(1, AT_PHENT, sizeof(struct elf_phdr)); - NEW_AUX_ENT(2, AT_PHNUM, exec->e_phnum); - NEW_AUX_ENT(3, AT_PAGESZ, ELF_EXEC_PAGESIZE); - NEW_AUX_ENT(4, AT_BASE, interp_load_addr); - NEW_AUX_ENT(5, AT_FLAGS, 0); - NEW_AUX_ENT(6, AT_ENTRY, (elf_addr_t) exec->e_entry); - NEW_AUX_ENT(7, AT_UID, (elf_addr_t) current->uid); - NEW_AUX_ENT(8, AT_EUID, (elf_addr_t) current->euid); - NEW_AUX_ENT(9, AT_GID, (elf_addr_t) current->gid); - NEW_AUX_ENT(10, AT_EGID, (elf_addr_t) current->egid); - } -#undef NEW_AUX_ENT - - sp -= envc+1; - envp = sp; - sp -= argc+1; - argv = sp; - - __put_user((elf_addr_t)argc, --sp); - current->mm->arg_start = (unsigned long) p; - while (argc-->0) { - __put_user((unsigned long)p, argv++); - p += strlen_user(p); - } - __put_user((unsigned long) NULL, argv); - current->mm->arg_end = current->mm->env_start = (unsigned long) p; - while (envc-->0) { - __put_user((unsigned long)p, envp++); - p += strlen_user(p); - } - __put_user((unsigned long) NULL, envp); - current->mm->env_end = (unsigned long) p; - return sp; -} - - -/* This is much more generalized than the library routine read function, - * so we keep this separate. Technically the library read function - * is only provided so that we can read a.out libraries that have - * an ELF header. - */ -static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex, - struct file * interpreter, - unsigned int *interp_load_addr) -{ - struct elf_phdr *elf_phdata = NULL; - struct elf_phdr *eppnt; - unsigned int len; - unsigned int load_addr; - int elf_bss; - int retval; - unsigned int last_bss; - int error; - int i; - unsigned int k; - - elf_bss = 0; - last_bss = 0; - error = load_addr = 0; - - print_elfhdr(interp_elf_ex); - - /* First of all, some simple consistency checks */ - if ((interp_elf_ex->e_type != ET_EXEC && - interp_elf_ex->e_type != ET_DYN) || - !interpreter->f_op->mmap) { - printk("IRIX interp has bad e_type %d\n", interp_elf_ex->e_type); - return 0xffffffff; - } - - /* Now read in all of the header information */ - if (sizeof(struct elf_phdr) * interp_elf_ex->e_phnum > PAGE_SIZE) { - printk("IRIX interp header bigger than a page (%d)\n", - (sizeof(struct elf_phdr) * interp_elf_ex->e_phnum)); - return 0xffffffff; - } - - elf_phdata = kmalloc(sizeof(struct elf_phdr) * interp_elf_ex->e_phnum, - GFP_KERNEL); - - if (!elf_phdata) { - printk("Cannot kmalloc phdata for IRIX interp.\n"); - return 0xffffffff; - } - - /* If the size of this structure has changed, then punt, since - * we will be doing the wrong thing. - */ - if (interp_elf_ex->e_phentsize != 32) { - printk("IRIX interp e_phentsize == %d != 32 ", - interp_elf_ex->e_phentsize); - kfree(elf_phdata); - return 0xffffffff; - } - - retval = kernel_read(interpreter, interp_elf_ex->e_phoff, - (char *) elf_phdata, - sizeof(struct elf_phdr) * interp_elf_ex->e_phnum); - - dump_phdrs(elf_phdata, interp_elf_ex->e_phnum); - - eppnt = elf_phdata; - for (i = 0; i < interp_elf_ex->e_phnum; i++, eppnt++) { - if (eppnt->p_type == PT_LOAD) { - int elf_type = MAP_PRIVATE | MAP_DENYWRITE; - int elf_prot = 0; - unsigned long vaddr = 0; - if (eppnt->p_flags & PF_R) - elf_prot = PROT_READ; - if (eppnt->p_flags & PF_W) - elf_prot |= PROT_WRITE; - if (eppnt->p_flags & PF_X) - elf_prot |= PROT_EXEC; - elf_type |= MAP_FIXED; - vaddr = eppnt->p_vaddr; - - pr_debug("INTERP do_mmap" - "(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ", - interpreter, vaddr, - (unsigned long) - (eppnt->p_filesz + (eppnt->p_vaddr & 0xfff)), - (unsigned long) - elf_prot, (unsigned long) elf_type, - (unsigned long) - (eppnt->p_offset & 0xfffff000)); - - down_write(¤t->mm->mmap_sem); - error = do_mmap(interpreter, vaddr, - eppnt->p_filesz + (eppnt->p_vaddr & 0xfff), - elf_prot, elf_type, - eppnt->p_offset & 0xfffff000); - up_write(¤t->mm->mmap_sem); - - if (error < 0 && error > -1024) { - printk("Aieee IRIX interp mmap error=%d\n", - error); - break; /* Real error */ - } - pr_debug("error=%08lx ", (unsigned long) error); - if (!load_addr && interp_elf_ex->e_type == ET_DYN) { - load_addr = error; - pr_debug("load_addr = error "); - } - - /* - * Find the end of the file mapping for this phdr, and - * keep track of the largest address we see for this. - */ - k = eppnt->p_vaddr + eppnt->p_filesz; - if (k > elf_bss) - elf_bss = k; - - /* Do the same thing for the memory mapping - between - * elf_bss and last_bss is the bss section. - */ - k = eppnt->p_memsz + eppnt->p_vaddr; - if (k > last_bss) - last_bss = k; - pr_debug("\n"); - } - } - - /* Now use mmap to map the library into memory. */ - if (error < 0 && error > -1024) { - pr_debug("got error %d\n", error); - kfree(elf_phdata); - return 0xffffffff; - } - - /* Now fill out the bss section. First pad the last page up - * to the page boundary, and then perform a mmap to make sure - * that there are zero-mapped pages up to and including the - * last bss page. - */ - pr_debug("padzero(%08lx) ", (unsigned long) (elf_bss)); - padzero(elf_bss); - len = (elf_bss + 0xfff) & 0xfffff000; /* What we have mapped so far */ - - pr_debug("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss, - (unsigned long) len); - - /* Map the last of the bss segment */ - if (last_bss > len) { - down_write(¤t->mm->mmap_sem); - do_brk(len, (last_bss - len)); - up_write(¤t->mm->mmap_sem); - } - kfree(elf_phdata); - - *interp_load_addr = load_addr; - return ((unsigned int) interp_elf_ex->e_entry); -} - -/* Check sanity of IRIX elf executable header. */ -static int verify_binary(struct elfhdr *ehp, struct linux_binprm *bprm) -{ - if (memcmp(ehp->e_ident, ELFMAG, SELFMAG) != 0) - return -ENOEXEC; - - /* First of all, some simple consistency checks */ - if ((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) || - !bprm->file->f_op->mmap) { - return -ENOEXEC; - } - - /* XXX Don't support N32 or 64bit binaries yet because they can - * XXX and do execute 64 bit instructions and expect all registers - * XXX to be 64 bit as well. We need to make the kernel save - * XXX all registers as 64bits on cpu's capable of this at - * XXX exception time plus frob the XTLB exception vector. - */ - if ((ehp->e_flags & EF_MIPS_ABI2)) - return -ENOEXEC; - - return 0; -} - -/* - * This is where the detailed check is performed. Irix binaries - * use interpreters with 'libc.so' in the name, so this function - * can differentiate between Linux and Irix binaries. - */ -static inline int look_for_irix_interpreter(char **name, - struct file **interpreter, - struct elfhdr *interp_elf_ex, - struct elf_phdr *epp, - struct linux_binprm *bprm, int pnum) -{ - int i; - int retval = -EINVAL; - struct file *file = NULL; - - *name = NULL; - for (i = 0; i < pnum; i++, epp++) { - if (epp->p_type != PT_INTERP) - continue; - - /* It is illegal to have two interpreters for one executable. */ - if (*name != NULL) - goto out; - - *name = kmalloc(epp->p_filesz + strlen(IRIX_EMUL), GFP_KERNEL); - if (!*name) - return -ENOMEM; - - strcpy(*name, IRIX_EMUL); - retval = kernel_read(bprm->file, epp->p_offset, (*name + 16), - epp->p_filesz); - if (retval < 0) - goto out; - - file = open_exec(*name); - if (IS_ERR(file)) { - retval = PTR_ERR(file); - goto out; - } - retval = kernel_read(file, 0, bprm->buf, 128); - if (retval < 0) - goto dput_and_out; - - *interp_elf_ex = *(struct elfhdr *) bprm->buf; - } - *interpreter = file; - return 0; - -dput_and_out: - fput(file); -out: - kfree(*name); - return retval; -} - -static inline int verify_irix_interpreter(struct elfhdr *ihp) -{ - if (memcmp(ihp->e_ident, ELFMAG, SELFMAG) != 0) - return -ELIBBAD; - return 0; -} - -#define EXEC_MAP_FLAGS (MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE) - -static inline void map_executable(struct file *fp, struct elf_phdr *epp, int pnum, - unsigned int *estack, unsigned int *laddr, - unsigned int *scode, unsigned int *ebss, - unsigned int *ecode, unsigned int *edata, - unsigned int *ebrk) -{ - unsigned int tmp; - int i, prot; - - for (i = 0; i < pnum; i++, epp++) { - if (epp->p_type != PT_LOAD) - continue; - - /* Map it. */ - prot = (epp->p_flags & PF_R) ? PROT_READ : 0; - prot |= (epp->p_flags & PF_W) ? PROT_WRITE : 0; - prot |= (epp->p_flags & PF_X) ? PROT_EXEC : 0; - down_write(¤t->mm->mmap_sem); - (void) do_mmap(fp, (epp->p_vaddr & 0xfffff000), - (epp->p_filesz + (epp->p_vaddr & 0xfff)), - prot, EXEC_MAP_FLAGS, - (epp->p_offset & 0xfffff000)); - up_write(¤t->mm->mmap_sem); - - /* Fixup location tracking vars. */ - if ((epp->p_vaddr & 0xfffff000) < *estack) - *estack = (epp->p_vaddr & 0xfffff000); - if (!*laddr) - *laddr = epp->p_vaddr - epp->p_offset; - if (epp->p_vaddr < *scode) - *scode = epp->p_vaddr; - - tmp = epp->p_vaddr + epp->p_filesz; - if (tmp > *ebss) - *ebss = tmp; - if ((epp->p_flags & PF_X) && *ecode < tmp) - *ecode = tmp; - if (*edata < tmp) - *edata = tmp; - - tmp = epp->p_vaddr + epp->p_memsz; - if (tmp > *ebrk) - *ebrk = tmp; - } - -} - -static inline int map_interpreter(struct elf_phdr *epp, struct elfhdr *ihp, - struct file *interp, unsigned int *iladdr, - int pnum, mm_segment_t old_fs, - unsigned int *eentry) -{ - int i; - - *eentry = 0xffffffff; - for (i = 0; i < pnum; i++, epp++) { - if (epp->p_type != PT_INTERP) - continue; - - /* We should have fielded this error elsewhere... */ - if (*eentry != 0xffffffff) - return -1; - - set_fs(old_fs); - *eentry = load_irix_interp(ihp, interp, iladdr); - old_fs = get_fs(); - set_fs(get_ds()); - - fput(interp); - - if (*eentry == 0xffffffff) - return -1; - } - return 0; -} - -/* - * IRIX maps a page at 0x200000 that holds information about the - * process and the system, here we map the page and fill the - * structure - */ -static int irix_map_prda_page(void) -{ - unsigned long v; - struct prda *pp; - - down_write(¤t->mm->mmap_sem); - v = do_brk(PRDA_ADDRESS, PAGE_SIZE); - up_write(¤t->mm->mmap_sem); - - if (v != PRDA_ADDRESS) - return v; /* v must be an error code */ - - pp = (struct prda *) v; - pp->prda_sys.t_pid = task_pid_vnr(current); - pp->prda_sys.t_prid = read_c0_prid(); - pp->prda_sys.t_rpid = task_pid_vnr(current); - - /* We leave the rest set to zero */ - - return 0; -} - - - -/* These are the functions used to load ELF style executables and shared - * libraries. There is no binary dependent code anywhere else. - */ -static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs) -{ - struct elfhdr elf_ex, interp_elf_ex; - struct file *interpreter; - struct elf_phdr *elf_phdata, *elf_ihdr, *elf_ephdr; - unsigned int load_addr, elf_bss, elf_brk; - unsigned int elf_entry, interp_load_addr = 0; - unsigned int start_code, end_code, end_data, elf_stack; - int retval, has_interp, has_ephdr, size, i; - char *elf_interpreter; - mm_segment_t old_fs; - - load_addr = 0; - has_interp = has_ephdr = 0; - elf_ihdr = elf_ephdr = NULL; - elf_ex = *((struct elfhdr *) bprm->buf); - retval = -ENOEXEC; - - if (verify_binary(&elf_ex, bprm)) - goto out; - - /* - * Telling -o32 static binaries from Linux and Irix apart from each - * other is difficult. There are 2 differences to be noted for static - * binaries from the 2 operating systems: - * - * 1) Irix binaries have their .text section before their .init - * section. Linux binaries are just the opposite. - * - * 2) Irix binaries usually have <= 12 sections and Linux - * binaries have > 20. - * - * We will use Method #2 since Method #1 would require us to read in - * the section headers which is way too much overhead. This appears - * to work for everything we have ran into so far. If anyone has a - * better method to tell the binaries apart, I'm listening. - */ - if (elf_ex.e_shnum > 20) - goto out; - - print_elfhdr(&elf_ex); - - /* Now read in all of the header information */ - size = elf_ex.e_phentsize * elf_ex.e_phnum; - if (size > 65536) - goto out; - elf_phdata = kmalloc(size, GFP_KERNEL); - if (elf_phdata == NULL) { - retval = -ENOMEM; - goto out; - } - - retval = kernel_read(bprm->file, elf_ex.e_phoff, (char *)elf_phdata, size); - if (retval < 0) - goto out_free_ph; - - dump_phdrs(elf_phdata, elf_ex.e_phnum); - - /* Set some things for later. */ - for (i = 0; i < elf_ex.e_phnum; i++) { - switch (elf_phdata[i].p_type) { - case PT_INTERP: - has_interp = 1; - elf_ihdr = &elf_phdata[i]; - break; - case PT_PHDR: - has_ephdr = 1; - elf_ephdr = &elf_phdata[i]; - break; - }; - } - - pr_debug("\n"); - - elf_bss = 0; - elf_brk = 0; - - elf_stack = 0xffffffff; - elf_interpreter = NULL; - start_code = 0xffffffff; - end_code = 0; - end_data = 0; - - /* - * If we get a return value, we change the value to be ENOEXEC - * so that we can exit gracefully and the main binary format - * search loop in 'fs/exec.c' will move onto the next handler - * which should be the normal ELF binary handler. - */ - retval = look_for_irix_interpreter(&elf_interpreter, &interpreter, - &interp_elf_ex, elf_phdata, bprm, - elf_ex.e_phnum); - if (retval) { - retval = -ENOEXEC; - goto out_free_file; - } - - if (elf_interpreter) { - retval = verify_irix_interpreter(&interp_elf_ex); - if (retval) - goto out_free_interp; - } - - /* OK, we are done with that, now set up the arg stuff, - * and then start this sucker up. - */ - retval = -E2BIG; - if (!bprm->sh_bang && !bprm->p) - goto out_free_interp; - - /* Flush all traces of the currently running executable */ - retval = flush_old_exec(bprm); - if (retval) - goto out_free_dentry; - - /* OK, This is the point of no return */ - current->mm->end_data = 0; - current->mm->end_code = 0; - current->mm->mmap = NULL; - current->flags &= ~PF_FORKNOEXEC; - elf_entry = (unsigned int) elf_ex.e_entry; - - /* Do this so that we can load the interpreter, if need be. We will - * change some of these later. - */ - setup_arg_pages(bprm, STACK_TOP, EXSTACK_DEFAULT); - current->mm->start_stack = bprm->p; - - /* At this point, we assume that the image should be loaded at - * fixed address, not at a variable address. - */ - old_fs = get_fs(); - set_fs(get_ds()); - - map_executable(bprm->file, elf_phdata, elf_ex.e_phnum, &elf_stack, - &load_addr, &start_code, &elf_bss, &end_code, - &end_data, &elf_brk); - - if (elf_interpreter) { - retval = map_interpreter(elf_phdata, &interp_elf_ex, - interpreter, &interp_load_addr, - elf_ex.e_phnum, old_fs, &elf_entry); - kfree(elf_interpreter); - if (retval) { - set_fs(old_fs); - printk("Unable to load IRIX ELF interpreter\n"); - send_sig(SIGSEGV, current, 0); - retval = 0; - goto out_free_file; - } - } - - set_fs(old_fs); - - kfree(elf_phdata); - set_personality(PER_IRIX32); - set_binfmt(&irix_format); - compute_creds(bprm); - current->flags &= ~PF_FORKNOEXEC; - bprm->p = (unsigned long) - create_irix_tables((char *)bprm->p, bprm->argc, bprm->envc, - (elf_interpreter ? &elf_ex : NULL), - load_addr, interp_load_addr, regs, elf_ephdr); - current->mm->start_brk = current->mm->brk = elf_brk; - current->mm->end_code = end_code; - current->mm->start_code = start_code; - current->mm->end_data = end_data; - current->mm->start_stack = bprm->p; - - /* Calling set_brk effectively mmaps the pages that we need for the - * bss and break sections. - */ - set_brk(elf_bss, elf_brk); - - /* - * IRIX maps a page at 0x200000 which holds some system - * information. Programs depend on this. - */ - if (irix_map_prda_page()) - goto out_free_dentry; - - padzero(elf_bss); - - pr_debug("(start_brk) %lx\n" , (long) current->mm->start_brk); - pr_debug("(end_code) %lx\n" , (long) current->mm->end_code); - pr_debug("(start_code) %lx\n" , (long) current->mm->start_code); - pr_debug("(end_data) %lx\n" , (long) current->mm->end_data); - pr_debug("(start_stack) %lx\n" , (long) current->mm->start_stack); - pr_debug("(brk) %lx\n" , (long) current->mm->brk); - -#if 0 /* XXX No fucking way dude... */ - /* Why this, you ask??? Well SVr4 maps page 0 as read-only, - * and some applications "depend" upon this behavior. - * Since we do not have the power to recompile these, we - * emulate the SVr4 behavior. Sigh. - */ - down_write(¤t->mm->mmap_sem); - (void) do_mmap(NULL, 0, 4096, PROT_READ | PROT_EXEC, - MAP_FIXED | MAP_PRIVATE, 0); - up_write(¤t->mm->mmap_sem); -#endif - - start_thread(regs, elf_entry, bprm->p); - if (current->ptrace & PT_PTRACED) - send_sig(SIGTRAP, current, 0); - return 0; -out: - return retval; - -out_free_dentry: - allow_write_access(interpreter); - fput(interpreter); -out_free_interp: - kfree(elf_interpreter); -out_free_file: -out_free_ph: - kfree(elf_phdata); - goto out; -} - -/* This is really simpleminded and specialized - we are loading an - * a.out library that is given an ELF header. - */ -static int load_irix_library(struct file *file) -{ - struct elfhdr elf_ex; - struct elf_phdr *elf_phdata = NULL; - unsigned int len = 0; - int elf_bss = 0; - int retval; - unsigned int bss; - int error; - int i, j, k; - - error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex)); - if (error != sizeof(elf_ex)) - return -ENOEXEC; - - if (memcmp(elf_ex.e_ident, ELFMAG, SELFMAG) != 0) - return -ENOEXEC; - - /* First of all, some simple consistency checks. */ - if (elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 || - !file->f_op->mmap) - return -ENOEXEC; - - /* Now read in all of the header information. */ - if (sizeof(struct elf_phdr) * elf_ex.e_phnum > PAGE_SIZE) - return -ENOEXEC; - - elf_phdata = kmalloc(sizeof(struct elf_phdr) * elf_ex.e_phnum, GFP_KERNEL); - if (elf_phdata == NULL) - return -ENOMEM; - - retval = kernel_read(file, elf_ex.e_phoff, (char *) elf_phdata, - sizeof(struct elf_phdr) * elf_ex.e_phnum); - - j = 0; - for (i=0; ip_type == PT_LOAD) j++; - - if (j != 1) { - kfree(elf_phdata); - return -ENOEXEC; - } - - while (elf_phdata->p_type != PT_LOAD) elf_phdata++; - - /* Now use mmap to map the library into memory. */ - down_write(¤t->mm->mmap_sem); - error = do_mmap(file, - elf_phdata->p_vaddr & 0xfffff000, - elf_phdata->p_filesz + (elf_phdata->p_vaddr & 0xfff), - PROT_READ | PROT_WRITE | PROT_EXEC, - MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE, - elf_phdata->p_offset & 0xfffff000); - up_write(¤t->mm->mmap_sem); - - k = elf_phdata->p_vaddr + elf_phdata->p_filesz; - if (k > elf_bss) elf_bss = k; - - if (error != (elf_phdata->p_vaddr & 0xfffff000)) { - kfree(elf_phdata); - return error; - } - - padzero(elf_bss); - - len = (elf_phdata->p_filesz + elf_phdata->p_vaddr+ 0xfff) & 0xfffff000; - bss = elf_phdata->p_memsz + elf_phdata->p_vaddr; - if (bss > len) { - down_write(¤t->mm->mmap_sem); - do_brk(len, bss-len); - up_write(¤t->mm->mmap_sem); - } - kfree(elf_phdata); - return 0; -} - -/* Called through irix_syssgi() to map an elf image given an FD, - * a phdr ptr USER_PHDRP in userspace, and a count CNT telling how many - * phdrs there are in the USER_PHDRP array. We return the vaddr the - * first phdr was successfully mapped to. - */ -unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt) -{ - unsigned long type, vaddr, filesz, offset, flags; - struct elf_phdr __user *hp; - struct file *filp; - int i, retval; - - pr_debug("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n", - fd, user_phdrp, cnt); - - /* First get the verification out of the way. */ - hp = user_phdrp; - if (!access_ok(VERIFY_READ, hp, (sizeof(struct elf_phdr) * cnt))) { - pr_debug("irix_mapelf: bad pointer to ELF PHDR!\n"); - - return -EFAULT; - } - - dump_phdrs(user_phdrp, cnt); - - for (i = 0; i < cnt; i++, hp++) { - if (__get_user(type, &hp->p_type)) - return -EFAULT; - if (type != PT_LOAD) { - printk("irix_mapelf: One section is not PT_LOAD!\n"); - return -ENOEXEC; - } - } - - filp = fget(fd); - if (!filp) - return -EACCES; - if (!filp->f_op) { - printk("irix_mapelf: Bogon filp!\n"); - fput(filp); - return -EACCES; - } - - hp = user_phdrp; - for (i = 0; i < cnt; i++, hp++) { - int prot; - - retval = __get_user(vaddr, &hp->p_vaddr); - retval |= __get_user(filesz, &hp->p_filesz); - retval |= __get_user(offset, &hp->p_offset); - retval |= __get_user(flags, &hp->p_flags); - if (retval) - return retval; - - prot = (flags & PF_R) ? PROT_READ : 0; - prot |= (flags & PF_W) ? PROT_WRITE : 0; - prot |= (flags & PF_X) ? PROT_EXEC : 0; - - down_write(¤t->mm->mmap_sem); - retval = do_mmap(filp, (vaddr & 0xfffff000), - (filesz + (vaddr & 0xfff)), - prot, (MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE), - (offset & 0xfffff000)); - up_write(¤t->mm->mmap_sem); - - if (retval != (vaddr & 0xfffff000)) { - printk("irix_mapelf: do_mmap fails with %d!\n", retval); - fput(filp); - return retval; - } - } - - pr_debug("irix_mapelf: Success, returning %08lx\n", - (unsigned long) user_phdrp->p_vaddr); - - fput(filp); - - if (__get_user(vaddr, &user_phdrp->p_vaddr)) - return -EFAULT; - - return vaddr; -} - -/* - * ELF core dumper - * - * Modelled on fs/exec.c:aout_core_dump() - * Jeremy Fitzhardinge - */ - -/* These are the only things you should do on a core-file: use only these - * functions to write out all the necessary info. - */ -static int dump_write(struct file *file, const void __user *addr, int nr) -{ - return file->f_op->write(file, (const char __user *) addr, nr, &file->f_pos) == nr; -} - -static int dump_seek(struct file *file, off_t off) -{ - if (file->f_op->llseek) { - if (file->f_op->llseek(file, off, 0) != off) - return 0; - } else - file->f_pos = off; - return 1; -} - -/* Decide whether a segment is worth dumping; default is yes to be - * sure (missing info is worse than too much; etc). - * Personally I'd include everything, and use the coredump limit... - * - * I think we should skip something. But I am not sure how. H.J. - */ -static inline int maydump(struct vm_area_struct *vma) -{ - if (!(vma->vm_flags & (VM_READ|VM_WRITE|VM_EXEC))) - return 0; -#if 1 - if (vma->vm_flags & (VM_WRITE|VM_GROWSUP|VM_GROWSDOWN)) - return 1; - if (vma->vm_flags & (VM_READ|VM_EXEC|VM_EXECUTABLE|VM_SHARED)) - return 0; -#endif - return 1; -} - -/* An ELF note in memory. */ -struct memelfnote -{ - const char *name; - int type; - unsigned int datasz; - void *data; -}; - -static int notesize(struct memelfnote *en) -{ - int sz; - - sz = sizeof(struct elf_note); - sz += roundup(strlen(en->name) + 1, 4); - sz += roundup(en->datasz, 4); - - return sz; -} - -#define DUMP_WRITE(addr, nr) \ - if (!dump_write(file, (addr), (nr))) \ - goto end_coredump; -#define DUMP_SEEK(off) \ - if (!dump_seek(file, (off))) \ - goto end_coredump; - -static int writenote(struct memelfnote *men, struct file *file) -{ - struct elf_note en; - - en.n_namesz = strlen(men->name) + 1; - en.n_descsz = men->datasz; - en.n_type = men->type; - - DUMP_WRITE(&en, sizeof(en)); - DUMP_WRITE(men->name, en.n_namesz); - /* XXX - cast from long long to long to avoid need for libgcc.a */ - DUMP_SEEK(roundup((unsigned long)file->f_pos, 4)); /* XXX */ - DUMP_WRITE(men->data, men->datasz); - DUMP_SEEK(roundup((unsigned long)file->f_pos, 4)); /* XXX */ - - return 1; - -end_coredump: - return 0; -} -#undef DUMP_WRITE -#undef DUMP_SEEK - -#define DUMP_WRITE(addr, nr) \ - if (!dump_write(file, (addr), (nr))) \ - goto end_coredump; -#define DUMP_SEEK(off) \ - if (!dump_seek(file, (off))) \ - goto end_coredump; - -/* Actual dumper. - * - * This is a two-pass process; first we find the offsets of the bits, - * and then they are actually written out. If we run out of core limit - * we just truncate. - */ -static int irix_core_dump(long signr, struct pt_regs *regs, struct file *file, unsigned long limit) -{ - int has_dumped = 0; - mm_segment_t fs; - int segs; - int i; - size_t size; - struct vm_area_struct *vma; - struct elfhdr elf; - off_t offset = 0, dataoff; - int numnote = 3; - struct memelfnote notes[3]; - struct elf_prstatus prstatus; /* NT_PRSTATUS */ - elf_fpregset_t fpu; /* NT_PRFPREG */ - struct elf_prpsinfo psinfo; /* NT_PRPSINFO */ - - /* Count what's needed to dump, up to the limit of coredump size. */ - segs = 0; - size = 0; - for (vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) { - if (maydump(vma)) - { - int sz = vma->vm_end-vma->vm_start; - - if (size+sz >= limit) - break; - else - size += sz; - } - - segs++; - } - pr_debug("irix_core_dump: %d segs taking %d bytes\n", segs, size); - - /* Set up header. */ - memcpy(elf.e_ident, ELFMAG, SELFMAG); - elf.e_ident[EI_CLASS] = ELFCLASS32; - elf.e_ident[EI_DATA] = ELFDATA2LSB; - elf.e_ident[EI_VERSION] = EV_CURRENT; - elf.e_ident[EI_OSABI] = ELF_OSABI; - memset(elf.e_ident+EI_PAD, 0, EI_NIDENT-EI_PAD); - - elf.e_type = ET_CORE; - elf.e_machine = ELF_ARCH; - elf.e_version = EV_CURRENT; - elf.e_entry = 0; - elf.e_phoff = sizeof(elf); - elf.e_shoff = 0; - elf.e_flags = 0; - elf.e_ehsize = sizeof(elf); - elf.e_phentsize = sizeof(struct elf_phdr); - elf.e_phnum = segs+1; /* Include notes. */ - elf.e_shentsize = 0; - elf.e_shnum = 0; - elf.e_shstrndx = 0; - - fs = get_fs(); - set_fs(KERNEL_DS); - - has_dumped = 1; - current->flags |= PF_DUMPCORE; - - DUMP_WRITE(&elf, sizeof(elf)); - offset += sizeof(elf); /* Elf header. */ - offset += (segs+1) * sizeof(struct elf_phdr); /* Program headers. */ - - /* Set up the notes in similar form to SVR4 core dumps made - * with info from their /proc. - */ - memset(&psinfo, 0, sizeof(psinfo)); - memset(&prstatus, 0, sizeof(prstatus)); - - notes[0].name = "CORE"; - notes[0].type = NT_PRSTATUS; - notes[0].datasz = sizeof(prstatus); - notes[0].data = &prstatus; - prstatus.pr_info.si_signo = prstatus.pr_cursig = signr; - prstatus.pr_sigpend = current->pending.signal.sig[0]; - prstatus.pr_sighold = current->blocked.sig[0]; - psinfo.pr_pid = prstatus.pr_pid = task_pid_vnr(current); - psinfo.pr_ppid = prstatus.pr_ppid = task_pid_vnr(current->parent); - psinfo.pr_pgrp = prstatus.pr_pgrp = task_pgrp_vnr(current); - psinfo.pr_sid = prstatus.pr_sid = task_session_vnr(current); - if (thread_group_leader(current)) { - /* - * This is the record for the group leader. Add in the - * cumulative times of previous dead threads. This total - * won't include the time of each live thread whose state - * is included in the core dump. The final total reported - * to our parent process when it calls wait4 will include - * those sums as well as the little bit more time it takes - * this and each other thread to finish dying after the - * core dump synchronization phase. - */ - jiffies_to_timeval(current->utime + current->signal->utime, - &prstatus.pr_utime); - jiffies_to_timeval(current->stime + current->signal->stime, - &prstatus.pr_stime); - } else { - jiffies_to_timeval(current->utime, &prstatus.pr_utime); - jiffies_to_timeval(current->stime, &prstatus.pr_stime); - } - jiffies_to_timeval(current->signal->cutime, &prstatus.pr_cutime); - jiffies_to_timeval(current->signal->cstime, &prstatus.pr_cstime); - - if (sizeof(elf_gregset_t) != sizeof(struct pt_regs)) { - printk("sizeof(elf_gregset_t) (%d) != sizeof(struct pt_regs) " - "(%d)\n", sizeof(elf_gregset_t), sizeof(struct pt_regs)); - } else { - *(struct pt_regs *)&prstatus.pr_reg = *regs; - } - - notes[1].name = "CORE"; - notes[1].type = NT_PRPSINFO; - notes[1].datasz = sizeof(psinfo); - notes[1].data = &psinfo; - i = current->state ? ffz(~current->state) + 1 : 0; - psinfo.pr_state = i; - psinfo.pr_sname = (i < 0 || i > 5) ? '.' : "RSDZTD"[i]; - psinfo.pr_zomb = psinfo.pr_sname == 'Z'; - psinfo.pr_nice = task_nice(current); - psinfo.pr_flag = current->flags; - psinfo.pr_uid = current->uid; - psinfo.pr_gid = current->gid; - { - int i, len; - - set_fs(fs); - - len = current->mm->arg_end - current->mm->arg_start; - len = len >= ELF_PRARGSZ ? ELF_PRARGSZ : len; - (void *) copy_from_user(&psinfo.pr_psargs, - (const char __user *)current->mm->arg_start, len); - for (i = 0; i < len; i++) - if (psinfo.pr_psargs[i] == 0) - psinfo.pr_psargs[i] = ' '; - psinfo.pr_psargs[len] = 0; - - set_fs(KERNEL_DS); - } - strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname)); - - /* Try to dump the FPU. */ - prstatus.pr_fpvalid = dump_fpu(regs, &fpu); - if (!prstatus.pr_fpvalid) { - numnote--; - } else { - notes[2].name = "CORE"; - notes[2].type = NT_PRFPREG; - notes[2].datasz = sizeof(fpu); - notes[2].data = &fpu; - } - - /* Write notes phdr entry. */ - { - struct elf_phdr phdr; - int sz = 0; - - for (i = 0; i < numnote; i++) - sz += notesize(¬es[i]); - - phdr.p_type = PT_NOTE; - phdr.p_offset = offset; - phdr.p_vaddr = 0; - phdr.p_paddr = 0; - phdr.p_filesz = sz; - phdr.p_memsz = 0; - phdr.p_flags = 0; - phdr.p_align = 0; - - offset += phdr.p_filesz; - DUMP_WRITE(&phdr, sizeof(phdr)); - } - - /* Page-align dumped data. */ - dataoff = offset = roundup(offset, PAGE_SIZE); - - /* Write program headers for segments dump. */ - for (vma = current->mm->mmap, i = 0; - i < segs && vma != NULL; vma = vma->vm_next) { - struct elf_phdr phdr; - size_t sz; - - i++; - - sz = vma->vm_end - vma->vm_start; - - phdr.p_type = PT_LOAD; - phdr.p_offset = offset; - phdr.p_vaddr = vma->vm_start; - phdr.p_paddr = 0; - phdr.p_filesz = maydump(vma) ? sz : 0; - phdr.p_memsz = sz; - offset += phdr.p_filesz; - phdr.p_flags = vma->vm_flags & VM_READ ? PF_R : 0; - if (vma->vm_flags & VM_WRITE) - phdr.p_flags |= PF_W; - if (vma->vm_flags & VM_EXEC) - phdr.p_flags |= PF_X; - phdr.p_align = PAGE_SIZE; - - DUMP_WRITE(&phdr, sizeof(phdr)); - } - - for (i = 0; i < numnote; i++) - if (!writenote(¬es[i], file)) - goto end_coredump; - - set_fs(fs); - - DUMP_SEEK(dataoff); - - for (i = 0, vma = current->mm->mmap; - i < segs && vma != NULL; - vma = vma->vm_next) { - unsigned long addr = vma->vm_start; - unsigned long len = vma->vm_end - vma->vm_start; - - if (!maydump(vma)) - continue; - i++; - pr_debug("elf_core_dump: writing %08lx %lx\n", addr, len); - DUMP_WRITE((void __user *)addr, len); - } - - if ((off_t) file->f_pos != offset) { - /* Sanity check. */ - printk("elf_core_dump: file->f_pos (%ld) != offset (%ld)\n", - (off_t) file->f_pos, offset); - } - -end_coredump: - set_fs(fs); - return has_dumped; -} - -static int __init init_irix_binfmt(void) -{ - extern int init_inventory(void); - extern asmlinkage unsigned long sys_call_table; - extern asmlinkage unsigned long sys_call_table_irix5; - - init_inventory(); - - /* - * Copy the IRIX5 syscall table (8000 bytes) into the main syscall - * table. The IRIX5 calls are located by an offset of 8000 bytes - * from the beginning of the main table. - */ - memcpy((void *) ((unsigned long) &sys_call_table + 8000), - &sys_call_table_irix5, 8000); - - return register_binfmt(&irix_format); -} - -static void __exit exit_irix_binfmt(void) -{ - /* - * Remove the Irix ELF loader. - */ - unregister_binfmt(&irix_format); -} - -module_init(init_irix_binfmt) -module_exit(exit_irix_binfmt) diff --git a/arch/mips/kernel/irixinv.c b/arch/mips/kernel/irixinv.c deleted file mode 100644 index cf2dcd3d6a93..000000000000 --- a/arch/mips/kernel/irixinv.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Support the inventory interface for IRIX binaries - * This is invoked before the mm layer is working, so we do not - * use the linked lists for the inventory yet. - * - * Miguel de Icaza, 1997. - */ -#include -#include -#include - -#define MAX_INVENTORY 50 -int inventory_items = 0; - -static inventory_t inventory [MAX_INVENTORY]; - -void add_to_inventory(int class, int type, int controller, int unit, int state) -{ - inventory_t *ni = &inventory [inventory_items]; - - if (inventory_items == MAX_INVENTORY) - return; - - ni->inv_class = class; - ni->inv_type = type; - ni->inv_controller = controller; - ni->inv_unit = unit; - ni->inv_state = state; - ni->inv_next = ni; - inventory_items++; -} - -int dump_inventory_to_user(void __user *userbuf, int size) -{ - inventory_t *inv = &inventory [0]; - inventory_t __user *user = userbuf; - int v; - - if (!access_ok(VERIFY_WRITE, userbuf, size)) - return -EFAULT; - - for (v = 0; v < inventory_items; v++){ - inv = &inventory [v]; - if (copy_to_user (user, inv, sizeof (inventory_t))) - return -EFAULT; - user++; - } - return inventory_items * sizeof(inventory_t); -} - -int __init init_inventory(void) -{ - /* - * gross hack while we put the right bits all over the kernel - * most likely this will not let just anyone run the X server - * until we put the right values all over the place - */ - add_to_inventory(10, 3, 0, 0, 16400); - add_to_inventory(1, 1, 150, -1, 12); - add_to_inventory(1, 3, 0, 0, 8976); - add_to_inventory(1, 2, 0, 0, 8976); - add_to_inventory(4, 8, 0, 0, 2); - add_to_inventory(5, 5, 0, 0, 1); - add_to_inventory(3, 3, 0, 0, 32768); - add_to_inventory(3, 4, 0, 0, 32768); - add_to_inventory(3, 8, 0, 0, 524288); - add_to_inventory(3, 9, 0, 0, 64); - add_to_inventory(3, 1, 0, 0, 67108864); - add_to_inventory(12, 3, 0, 0, 16); - add_to_inventory(8, 7, 17, 0, 16777472); - add_to_inventory(8, 0, 0, 0, 1); - add_to_inventory(2, 1, 0, 13, 2); - add_to_inventory(2, 2, 0, 2, 0); - add_to_inventory(2, 2, 0, 1, 0); - add_to_inventory(7, 14, 0, 0, 6); - - return 0; -} diff --git a/arch/mips/kernel/irixioctl.c b/arch/mips/kernel/irixioctl.c deleted file mode 100644 index b39bdba82e02..000000000000 --- a/arch/mips/kernel/irixioctl.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * irixioctl.c: A fucking mess... - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#undef DEBUG_IOCTLS -#undef DEBUG_MISSING_IOCTL - -struct irix_termios { - tcflag_t c_iflag, c_oflag, c_cflag, c_lflag; - cc_t c_cc[NCCS]; -}; - -asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg) -{ - struct tty_struct *tp, *rtp; - mm_segment_t old_fs; - int i, error = 0; - -#ifdef DEBUG_IOCTLS - printk("[%s:%d] irix_ioctl(%d, ", current->comm, current->pid, fd); -#endif - switch(cmd) { - case 0x00005401: -#ifdef DEBUG_IOCTLS - printk("TCGETA, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TCGETA, arg); - break; - - case 0x0000540d: { - struct termios kt; - struct irix_termios __user *it = - (struct irix_termios __user *) arg; - -#ifdef DEBUG_IOCTLS - printk("TCGETS, %08lx) ", arg); -#endif - if (!access_ok(VERIFY_WRITE, it, sizeof(*it))) { - error = -EFAULT; - break; - } - old_fs = get_fs(); set_fs(get_ds()); - error = sys_ioctl(fd, TCGETS, (unsigned long) &kt); - set_fs(old_fs); - if (error) - break; - - error = __put_user(kt.c_iflag, &it->c_iflag); - error |= __put_user(kt.c_oflag, &it->c_oflag); - error |= __put_user(kt.c_cflag, &it->c_cflag); - error |= __put_user(kt.c_lflag, &it->c_lflag); - - for (i = 0; i < NCCS; i++) - error |= __put_user(kt.c_cc[i], &it->c_cc[i]); - break; - } - - case 0x0000540e: { - struct termios kt; - struct irix_termios *it = (struct irix_termios *) arg; - -#ifdef DEBUG_IOCTLS - printk("TCSETS, %08lx) ", arg); -#endif - if (!access_ok(VERIFY_READ, it, sizeof(*it))) { - error = -EFAULT; - break; - } - old_fs = get_fs(); set_fs(get_ds()); - error = sys_ioctl(fd, TCGETS, (unsigned long) &kt); - set_fs(old_fs); - if (error) - break; - - error = __get_user(kt.c_iflag, &it->c_iflag); - error |= __get_user(kt.c_oflag, &it->c_oflag); - error |= __get_user(kt.c_cflag, &it->c_cflag); - error |= __get_user(kt.c_lflag, &it->c_lflag); - - for (i = 0; i < NCCS; i++) - error |= __get_user(kt.c_cc[i], &it->c_cc[i]); - - if (error) - break; - old_fs = get_fs(); set_fs(get_ds()); - error = sys_ioctl(fd, TCSETS, (unsigned long) &kt); - set_fs(old_fs); - break; - } - - case 0x0000540f: -#ifdef DEBUG_IOCTLS - printk("TCSETSW, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TCSETSW, arg); - break; - - case 0x00005471: -#ifdef DEBUG_IOCTLS - printk("TIOCNOTTY, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TIOCNOTTY, arg); - break; - - case 0x00007416: { - pid_t pid; -#ifdef DEBUG_IOCTLS - printk("TIOCGSID, %08lx) ", arg); -#endif - old_fs = get_fs(); set_fs(get_ds()); - error = sys_ioctl(fd, TIOCGSID, (unsigned long)&pid); - set_fs(old_fs); - if (!error) - error = put_user(pid, (unsigned long __user *) arg); - break; - } - case 0x746e: - /* TIOCSTART, same effect as hitting ^Q */ -#ifdef DEBUG_IOCTLS - printk("TIOCSTART, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TCXONC, TCOON); - break; - - case 0x20006968: -#ifdef DEBUG_IOCTLS - printk("SIOCGETLABEL, %08lx) ", arg); -#endif - error = -ENOPKG; - break; - - case 0x40047477: -#ifdef DEBUG_IOCTLS - printk("TIOCGPGRP, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TIOCGPGRP, arg); -#ifdef DEBUG_IOCTLS - printk("arg=%d ", *(int *)arg); -#endif - break; - - case 0x40087468: -#ifdef DEBUG_IOCTLS - printk("TIOCGWINSZ, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TIOCGWINSZ, arg); - break; - - case 0x8004667e: - error = sys_ioctl(fd, FIONBIO, arg); - break; - - case 0x80047476: - error = sys_ioctl(fd, TIOCSPGRP, arg); - break; - - case 0x8020690c: - error = sys_ioctl(fd, SIOCSIFADDR, arg); - break; - - case 0x80206910: - error = sys_ioctl(fd, SIOCSIFFLAGS, arg); - break; - - case 0xc0206911: - error = sys_ioctl(fd, SIOCGIFFLAGS, arg); - break; - - case 0xc020691b: - error = sys_ioctl(fd, SIOCGIFMETRIC, arg); - break; - - default: { -#ifdef DEBUG_MISSING_IOCTL - char *msg = "Unimplemented IOCTL cmd tell linux-mips@linux-mips.org\n"; - -#ifdef DEBUG_IOCTLS - printk("UNIMP_IOCTL, %08lx)\n", arg); -#endif - old_fs = get_fs(); set_fs(get_ds()); - sys_write(2, msg, strlen(msg)); - set_fs(old_fs); - printk("[%s:%d] Does unimplemented IRIX ioctl cmd %08lx\n", - current->comm, current->pid, cmd); - do_exit(255); -#else - error = sys_ioctl(fd, cmd, arg); -#endif - } - - }; -#ifdef DEBUG_IOCTLS - printk("error=%d\n", error); -#endif - return error; -} diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c deleted file mode 100644 index 0215c805a592..000000000000 --- a/arch/mips/kernel/irixsig.c +++ /dev/null @@ -1,888 +0,0 @@ -/* - * irixsig.c: WHEEE, IRIX signals! YOW, am I compatible or what?!?! - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997 - 2000 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 2000 Silicon Graphics, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#undef DEBUG_SIG - -#define _S(nr) (1<<((nr)-1)) - -#define _BLOCKABLE (~(_S(SIGKILL) | _S(SIGSTOP))) - -#define _IRIX_NSIG 128 -#define _IRIX_NSIG_BPW BITS_PER_LONG -#define _IRIX_NSIG_WORDS (_IRIX_NSIG / _IRIX_NSIG_BPW) - -typedef struct { - unsigned long sig[_IRIX_NSIG_WORDS]; -} irix_sigset_t; - -struct sigctx_irix5 { - u32 rmask, cp0_status; - u64 pc; - u64 regs[32]; - u64 fpregs[32]; - u32 usedfp, fpcsr, fpeir, sstk_flags; - u64 hi, lo; - u64 cp0_cause, cp0_badvaddr, _unused0; - irix_sigset_t sigset; - u64 weird_fpu_thing; - u64 _unused1[31]; -}; - -#ifdef DEBUG_SIG -/* Debugging */ -static inline void dump_irix5_sigctx(struct sigctx_irix5 *c) -{ - int i; - - printk("misc: rmask[%08lx] status[%08lx] pc[%08lx]\n", - (unsigned long) c->rmask, - (unsigned long) c->cp0_status, - (unsigned long) c->pc); - printk("regs: "); - for(i = 0; i < 16; i++) - printk("[%d]<%08lx> ", i, (unsigned long) c->regs[i]); - printk("\nregs: "); - for(i = 16; i < 32; i++) - printk("[%d]<%08lx> ", i, (unsigned long) c->regs[i]); - printk("\nfpregs: "); - for(i = 0; i < 16; i++) - printk("[%d]<%08lx> ", i, (unsigned long) c->fpregs[i]); - printk("\nfpregs: "); - for(i = 16; i < 32; i++) - printk("[%d]<%08lx> ", i, (unsigned long) c->fpregs[i]); - printk("misc: usedfp[%d] fpcsr[%08lx] fpeir[%08lx] stk_flgs[%08lx]\n", - (int) c->usedfp, (unsigned long) c->fpcsr, - (unsigned long) c->fpeir, (unsigned long) c->sstk_flags); - printk("misc: hi[%08lx] lo[%08lx] cause[%08lx] badvaddr[%08lx]\n", - (unsigned long) c->hi, (unsigned long) c->lo, - (unsigned long) c->cp0_cause, (unsigned long) c->cp0_badvaddr); - printk("misc: sigset<0>[%08lx] sigset<1>[%08lx] sigset<2>[%08lx] " - "sigset<3>[%08lx]\n", (unsigned long) c->sigset.sig[0], - (unsigned long) c->sigset.sig[1], - (unsigned long) c->sigset.sig[2], - (unsigned long) c->sigset.sig[3]); -} -#endif - -static int setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs, - int signr, sigset_t *oldmask) -{ - struct sigctx_irix5 __user *ctx; - unsigned long sp; - int error, i; - - sp = regs->regs[29]; - sp -= sizeof(struct sigctx_irix5); - sp &= ~(0xf); - ctx = (struct sigctx_irix5 __user *) sp; - if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) - goto segv_and_exit; - - error = __put_user(0, &ctx->weird_fpu_thing); - error |= __put_user(~(0x00000001), &ctx->rmask); - error |= __put_user(0, &ctx->regs[0]); - for(i = 1; i < 32; i++) - error |= __put_user((u64) regs->regs[i], &ctx->regs[i]); - - error |= __put_user((u64) regs->hi, &ctx->hi); - error |= __put_user((u64) regs->lo, &ctx->lo); - error |= __put_user((u64) regs->cp0_epc, &ctx->pc); - error |= __put_user(!!used_math(), &ctx->usedfp); - error |= __put_user((u64) regs->cp0_cause, &ctx->cp0_cause); - error |= __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr); - - error |= __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */ - - error |= __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t)) ? -EFAULT : 0; - - if (error) - goto segv_and_exit; - -#ifdef DEBUG_SIG - dump_irix5_sigctx(ctx); -#endif - - regs->regs[4] = (unsigned long) signr; - regs->regs[5] = 0; /* XXX sigcode XXX */ - regs->regs[6] = regs->regs[29] = sp; - regs->regs[7] = (unsigned long) ka->sa.sa_handler; - regs->regs[25] = regs->cp0_epc = (unsigned long) ka->sa_restorer; - - return 1; - -segv_and_exit: - force_sigsegv(signr, current); - return 0; -} - -static int inline -setup_irix_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *oldmask, siginfo_t *info) -{ - printk("Aiee: setup_tr_frame wants to be written"); - do_exit(SIGSEGV); -} - -static inline int handle_signal(unsigned long sig, siginfo_t *info, - struct k_sigaction *ka, sigset_t *oldset, struct pt_regs * regs) -{ - int ret; - - switch(regs->regs[0]) { - case ERESTARTNOHAND: - regs->regs[2] = EINTR; - break; - case ERESTARTSYS: - if(!(ka->sa.sa_flags & SA_RESTART)) { - regs->regs[2] = EINTR; - break; - } - /* fallthrough */ - case ERESTARTNOINTR: /* Userland will reload $v0. */ - regs->cp0_epc -= 8; - } - - regs->regs[0] = 0; /* Don't deal with this again. */ - - if (ka->sa.sa_flags & SA_SIGINFO) - ret = setup_irix_rt_frame(ka, regs, sig, oldset, info); - else - ret = setup_irix_frame(ka, regs, sig, oldset); - - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked, sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - return ret; -} - -void do_irix_signal(struct pt_regs *regs) -{ - struct k_sigaction ka; - siginfo_t info; - int signr; - sigset_t *oldset; - - /* - * We want the common case to go fast, which is why we may in certain - * cases get here from kernel mode. Just return without doing anything - * if so. - */ - if (!user_mode(regs)) - return; - - if (test_thread_flag(TIF_RESTORE_SIGMASK)) - oldset = ¤t->saved_sigmask; - else - oldset = ¤t->blocked; - - signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - /* Whee! Actually deliver the signal. */ - if (handle_signal(signr, &info, &ka, oldset, regs) == 0) { - /* a signal was successfully delivered; the saved - * sigmask will have been stored in the signal frame, - * and will be restored by sigreturn, so we can simply - * clear the TIF_RESTORE_SIGMASK flag */ - if (test_thread_flag(TIF_RESTORE_SIGMASK)) - clear_thread_flag(TIF_RESTORE_SIGMASK); - } - - return; - } - - /* - * Who's code doesn't conform to the restartable syscall convention - * dies here!!! The li instruction, a single machine instruction, - * must directly be followed by the syscall instruction. - */ - if (regs->regs[0]) { - if (regs->regs[2] == ERESTARTNOHAND || - regs->regs[2] == ERESTARTSYS || - regs->regs[2] == ERESTARTNOINTR) { - regs->cp0_epc -= 8; - } - if (regs->regs[2] == ERESTART_RESTARTBLOCK) { - regs->regs[2] = __NR_restart_syscall; - regs->regs[7] = regs->regs[26]; - regs->cp0_epc -= 4; - } - regs->regs[0] = 0; /* Don't deal with this again. */ - } - - /* - * If there's no signal to deliver, we just put the saved sigmask - * back - */ - if (test_thread_flag(TIF_RESTORE_SIGMASK)) { - clear_thread_flag(TIF_RESTORE_SIGMASK); - sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); - } -} - -asmlinkage void -irix_sigreturn(struct pt_regs *regs) -{ - struct sigctx_irix5 __user *context, *magic; - unsigned long umask, mask; - u64 *fregs; - u32 usedfp; - int error, sig, i, base = 0; - sigset_t blocked; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - if (regs->regs[2] == 1000) - base = 1; - - context = (struct sigctx_irix5 __user *) regs->regs[base + 4]; - magic = (struct sigctx_irix5 __user *) regs->regs[base + 5]; - sig = (int) regs->regs[base + 6]; -#ifdef DEBUG_SIG - printk("[%s:%d] IRIX sigreturn(scp[%p],ucp[%p],sig[%d])\n", - current->comm, current->pid, context, magic, sig); -#endif - if (!context) - context = magic; - if (!access_ok(VERIFY_READ, context, sizeof(struct sigctx_irix5))) - goto badframe; - -#ifdef DEBUG_SIG - dump_irix5_sigctx(context); -#endif - - error = __get_user(regs->cp0_epc, &context->pc); - error |= __get_user(umask, &context->rmask); - - mask = 2; - for (i = 1; i < 32; i++, mask <<= 1) { - if (umask & mask) - error |= __get_user(regs->regs[i], &context->regs[i]); - } - error |= __get_user(regs->hi, &context->hi); - error |= __get_user(regs->lo, &context->lo); - - error |= __get_user(usedfp, &context->usedfp); - if ((umask & 1) && usedfp) { - fregs = (u64 *) ¤t->thread.fpu; - - for(i = 0; i < 32; i++) - error |= __get_user(fregs[i], &context->fpregs[i]); - error |= __get_user(current->thread.fpu.fcr31, &context->fpcsr); - } - - /* XXX do sigstack crapola here... XXX */ - - error |= __copy_from_user(&blocked, &context->sigset, sizeof(blocked)) ? -EFAULT : 0; - - if (error) - goto badframe; - - sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = blocked; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - /* - * Don't let your children do this ... - */ - __asm__ __volatile__( - "move\t$29,%0\n\t" - "j\tsyscall_exit" - :/* no outputs */ - :"r" (®s)); - /* Unreached */ - -badframe: - force_sig(SIGSEGV, current); -} - -struct sigact_irix5 { - int flags; - void (*handler)(int); - u32 sigset[4]; - int _unused0[2]; -}; - -#define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility: - set only the low 32 bit of the sigset. */ - -#ifdef DEBUG_SIG -static inline void dump_sigact_irix5(struct sigact_irix5 *p) -{ - printk("", p->flags, - (unsigned long) p->handler, - (unsigned long) p->sigset[0]); -} -#endif - -asmlinkage int -irix_sigaction(int sig, const struct sigaction __user *act, - struct sigaction __user *oact, void __user *trampoline) -{ - struct k_sigaction new_ka, old_ka; - int ret; - -#ifdef DEBUG_SIG - printk(" (%d,%s,%s,%08lx) ", sig, (!new ? "0" : "NEW"), - (!old ? "0" : "OLD"), trampoline); - if(new) { - dump_sigact_irix5(new); printk(" "); - } -#endif - if (act) { - sigset_t mask; - int err; - - if (!access_ok(VERIFY_READ, act, sizeof(*act))) - return -EFAULT; - err = __get_user(new_ka.sa.sa_handler, &act->sa_handler); - err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); - - err |= __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t)) ? -EFAULT : 0; - if (err) - return err; - - /* - * Hmmm... methinks IRIX libc always passes a valid trampoline - * value for all invocations of sigaction. Will have to - * investigate. POSIX POSIX, die die die... - */ - new_ka.sa_restorer = trampoline; - } - -/* XXX Implement SIG_SETMASK32 for IRIX compatibility */ - ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); - - if (!ret && oact) { - int err; - - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact))) - return -EFAULT; - - err = __put_user(old_ka.sa.sa_handler, &oact->sa_handler); - err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); - err |= __copy_to_user(&oact->sa_mask, &old_ka.sa.sa_mask, - sizeof(sigset_t)) ? -EFAULT : 0; - if (err) - return -EFAULT; - } - - return ret; -} - -asmlinkage int irix_sigpending(irix_sigset_t __user *set) -{ - return do_sigpending(set, sizeof(*set)); -} - -asmlinkage int irix_sigprocmask(int how, irix_sigset_t __user *new, - irix_sigset_t __user *old) -{ - sigset_t oldbits, newbits; - - if (new) { - if (!access_ok(VERIFY_READ, new, sizeof(*new))) - return -EFAULT; - if (__copy_from_user(&newbits, new, sizeof(unsigned long)*4)) - return -EFAULT; - sigdelsetmask(&newbits, ~_BLOCKABLE); - - spin_lock_irq(¤t->sighand->siglock); - oldbits = current->blocked; - - switch(how) { - case 1: - sigorsets(&newbits, &oldbits, &newbits); - break; - - case 2: - sigandsets(&newbits, &oldbits, &newbits); - break; - - case 3: - break; - - case 256: - siginitset(&newbits, newbits.sig[0]); - break; - - default: - spin_unlock_irq(¤t->sighand->siglock); - return -EINVAL; - } - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - } - if (old) - return copy_to_user(old, ¤t->blocked, - sizeof(unsigned long)*4) ? -EFAULT : 0; - - return 0; -} - -asmlinkage int irix_sigsuspend(struct pt_regs *regs) -{ - sigset_t newset; - sigset_t __user *uset; - - uset = (sigset_t __user *) regs->regs[4]; - if (copy_from_user(&newset, uset, sizeof(sigset_t))) - return -EFAULT; - sigdelsetmask(&newset, ~_BLOCKABLE); - - spin_lock_irq(¤t->sighand->siglock); - current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - current->state = TASK_INTERRUPTIBLE; - schedule(); - set_thread_flag(TIF_RESTORE_SIGMASK); - return -ERESTARTNOHAND; -} - -/* hate hate hate... */ -struct irix5_siginfo { - int sig, code, error; - union { - char unused[128 - (3 * 4)]; /* Safety net. */ - struct { - int pid; - union { - int uid; - struct { - int utime, status, stime; - } child; - } procdata; - } procinfo; - - unsigned long fault_addr; - - struct { - int fd; - long band; - } fileinfo; - - unsigned long sigval; - } stuff; -}; - -asmlinkage int irix_sigpoll_sys(unsigned long __user *set, - struct irix5_siginfo __user *info, struct timespec __user *tp) -{ - long expire = MAX_SCHEDULE_TIMEOUT; - sigset_t kset; - int i, sig, error, timeo = 0; - struct timespec ktp; - -#ifdef DEBUG_SIG - printk("[%s:%d] irix_sigpoll_sys(%p,%p,%p)\n", - current->comm, current->pid, set, info, tp); -#endif - - /* Must always specify the signal set. */ - if (!set) - return -EINVAL; - - if (copy_from_user(&kset, set, sizeof(set))) - return -EFAULT; - - if (info && clear_user(info, sizeof(*info))) { - error = -EFAULT; - goto out; - } - - if (tp) { - if (copy_from_user(&ktp, tp, sizeof(*tp))) - return -EFAULT; - - if (!ktp.tv_sec && !ktp.tv_nsec) - return -EINVAL; - - expire = timespec_to_jiffies(&ktp) + - (ktp.tv_sec || ktp.tv_nsec); - } - - while(1) { - long tmp = 0; - - expire = schedule_timeout_interruptible(expire); - - for (i=0; i < _IRIX_NSIG_WORDS; i++) - tmp |= (current->pending.signal.sig[i] & kset.sig[i]); - - if (tmp) - break; - if (!expire) { - timeo = 1; - break; - } - if (signal_pending(current)) - return -EINTR; - } - if (timeo) - return -EAGAIN; - - for (sig = 1; i <= 65 /* IRIX_NSIG */; sig++) { - if (sigismember (&kset, sig)) - continue; - if (sigismember (¤t->pending.signal, sig)) { - /* XXX need more than this... */ - if (info) - return copy_to_user(&info->sig, &sig, sizeof(sig)); - return 0; - } - } - - /* Should not get here, but do something sane if we do. */ - error = -EINTR; - -out: - return error; -} - -/* This is here because of irix5_siginfo definition. */ -#define IRIX_P_PID 0 -#define IRIX_P_PGID 2 -#define IRIX_P_ALL 7 - -#define W_EXITED 1 -#define W_TRAPPED 2 -#define W_STOPPED 4 -#define W_CONT 8 -#define W_NOHANG 64 - -#define W_MASK (W_EXITED | W_TRAPPED | W_STOPPED | W_CONT | W_NOHANG) - -asmlinkage int irix_waitsys(int type, int upid, - struct irix5_siginfo __user *info, int options, - struct rusage __user *ru) -{ - struct pid *pid = NULL; - int flag, retval; - DECLARE_WAITQUEUE(wait, current); - struct task_struct *tsk; - struct task_struct *p; - struct list_head *_p; - - if (!info) - return -EINVAL; - - if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) - return -EFAULT; - - if (ru) - if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru))) - return -EFAULT; - - if (options & ~W_MASK) - return -EINVAL; - - if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL) - return -EINVAL; - - if (type != IRIX_P_ALL) - pid = find_get_pid(upid); - add_wait_queue(¤t->signal->wait_chldexit, &wait); -repeat: - flag = 0; - current->state = TASK_INTERRUPTIBLE; - read_lock(&tasklist_lock); - tsk = current; - list_for_each(_p, &tsk->children) { - p = list_entry(_p, struct task_struct, sibling); - if ((type == IRIX_P_PID) && task_pid(p) != pid) - continue; - if ((type == IRIX_P_PGID) && task_pgrp(p) != pid) - continue; - if ((p->exit_signal != SIGCHLD)) - continue; - flag = 1; - switch (p->state) { - case TASK_STOPPED: - if (!p->exit_code) - continue; - if (!(options & (W_TRAPPED|W_STOPPED)) && - !(p->ptrace & PT_PTRACED)) - continue; - read_unlock(&tasklist_lock); - - /* move to end of parent's list to avoid starvation */ - write_lock_irq(&tasklist_lock); - remove_parent(p); - add_parent(p); - write_unlock_irq(&tasklist_lock); - retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0; - if (retval) - goto end_waitsys; - - retval = __put_user(SIGCHLD, &info->sig); - retval |= __put_user(0, &info->code); - retval |= __put_user(task_pid_vnr(p), &info->stuff.procinfo.pid); - retval |= __put_user((p->exit_code >> 8) & 0xff, - &info->stuff.procinfo.procdata.child.status); - retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); - retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); - if (retval) - goto end_waitsys; - - p->exit_code = 0; - goto end_waitsys; - - case EXIT_ZOMBIE: - current->signal->cutime += p->utime + p->signal->cutime; - current->signal->cstime += p->stime + p->signal->cstime; - if (ru != NULL) - getrusage(p, RUSAGE_BOTH, ru); - retval = __put_user(SIGCHLD, &info->sig); - retval |= __put_user(1, &info->code); /* CLD_EXITED */ - retval |= __put_user(task_pid_vnr(p), &info->stuff.procinfo.pid); - retval |= __put_user((p->exit_code >> 8) & 0xff, - &info->stuff.procinfo.procdata.child.status); - retval |= __put_user(p->utime, - &info->stuff.procinfo.procdata.child.utime); - retval |= __put_user(p->stime, - &info->stuff.procinfo.procdata.child.stime); - if (retval) - goto end_waitsys; - - if (p->real_parent != p->parent) { - write_lock_irq(&tasklist_lock); - remove_parent(p); - p->parent = p->real_parent; - add_parent(p); - do_notify_parent(p, SIGCHLD); - write_unlock_irq(&tasklist_lock); - } else - release_task(p); - goto end_waitsys; - default: - continue; - } - tsk = next_thread(tsk); - } - read_unlock(&tasklist_lock); - if (flag) { - retval = 0; - if (options & W_NOHANG) - goto end_waitsys; - retval = -ERESTARTSYS; - if (signal_pending(current)) - goto end_waitsys; - current->state = TASK_INTERRUPTIBLE; - schedule(); - goto repeat; - } - retval = -ECHILD; -end_waitsys: - current->state = TASK_RUNNING; - remove_wait_queue(¤t->signal->wait_chldexit, &wait); - put_pid(pid); - - return retval; -} - -struct irix5_context { - u32 flags; - u32 link; - u32 sigmask[4]; - struct { u32 sp, size, flags; } stack; - int regs[36]; - u32 fpregs[32]; - u32 fpcsr; - u32 _unused0; - u32 _unused1[47]; - u32 weird_graphics_thing; -}; - -asmlinkage int irix_getcontext(struct pt_regs *regs) -{ - int error, i, base = 0; - struct irix5_context __user *ctx; - unsigned long flags; - - if (regs->regs[2] == 1000) - base = 1; - ctx = (struct irix5_context __user *) regs->regs[base + 4]; - -#ifdef DEBUG_SIG - printk("[%s:%d] irix_getcontext(%p)\n", - current->comm, current->pid, ctx); -#endif - - if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) - return -EFAULT; - - error = __put_user(current->thread.irix_oldctx, &ctx->link); - - error |= __copy_to_user(&ctx->sigmask, ¤t->blocked, sizeof(irix_sigset_t)) ? -EFAULT : 0; - - /* XXX Do sigstack stuff someday... */ - error |= __put_user(0, &ctx->stack.sp); - error |= __put_user(0, &ctx->stack.size); - error |= __put_user(0, &ctx->stack.flags); - - error |= __put_user(0, &ctx->weird_graphics_thing); - error |= __put_user(0, &ctx->regs[0]); - for (i = 1; i < 32; i++) - error |= __put_user(regs->regs[i], &ctx->regs[i]); - error |= __put_user(regs->lo, &ctx->regs[32]); - error |= __put_user(regs->hi, &ctx->regs[33]); - error |= __put_user(regs->cp0_cause, &ctx->regs[34]); - error |= __put_user(regs->cp0_epc, &ctx->regs[35]); - - flags = 0x0f; - if (!used_math()) { - flags &= ~(0x08); - } else { - /* XXX wheee... */ - printk("Wheee, no code for saving IRIX FPU context yet.\n"); - } - error |= __put_user(flags, &ctx->flags); - - return error; -} - -asmlinkage void irix_setcontext(struct pt_regs *regs) -{ - struct irix5_context __user *ctx; - int err, base = 0; - u32 flags; - - if (regs->regs[2] == 1000) - base = 1; - ctx = (struct irix5_context __user *) regs->regs[base + 4]; - -#ifdef DEBUG_SIG - printk("[%s:%d] irix_setcontext(%p)\n", - current->comm, current->pid, ctx); -#endif - - if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))) - goto segv_and_exit; - - err = __get_user(flags, &ctx->flags); - if (flags & 0x02) { - /* XXX sigstack garbage, todo... */ - printk("Wheee, cannot do sigstack stuff in setcontext\n"); - } - - if (flags & 0x04) { - int i; - - /* XXX extra control block stuff... todo... */ - for (i = 1; i < 32; i++) - err |= __get_user(regs->regs[i], &ctx->regs[i]); - err |= __get_user(regs->lo, &ctx->regs[32]); - err |= __get_user(regs->hi, &ctx->regs[33]); - err |= __get_user(regs->cp0_epc, &ctx->regs[35]); - } - - if (flags & 0x08) - /* XXX fpu context, blah... */ - printk(KERN_ERR "Wheee, cannot restore FPU context yet...\n"); - - err |= __get_user(current->thread.irix_oldctx, &ctx->link); - if (err) - goto segv_and_exit; - - /* - * Don't let your children do this ... - */ - __asm__ __volatile__( - "move\t$29,%0\n\t" - "j\tsyscall_exit" - :/* no outputs */ - :"r" (®s)); - /* Unreached */ - -segv_and_exit: - force_sigsegv(SIGSEGV, current); -} - -struct irix_sigstack { - unsigned long sp; - int status; -}; - -asmlinkage int irix_sigstack(struct irix_sigstack __user *new, - struct irix_sigstack __user *old) -{ -#ifdef DEBUG_SIG - printk("[%s:%d] irix_sigstack(%p,%p)\n", - current->comm, current->pid, new, old); -#endif - if (new) { - if (!access_ok(VERIFY_READ, new, sizeof(*new))) - return -EFAULT; - } - - if (old) { - if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - return -EFAULT; - } - - return 0; -} - -struct irix_sigaltstack { unsigned long sp; int size; int status; }; - -asmlinkage int irix_sigaltstack(struct irix_sigaltstack __user *new, - struct irix_sigaltstack __user *old) -{ -#ifdef DEBUG_SIG - printk("[%s:%d] irix_sigaltstack(%p,%p)\n", - current->comm, current->pid, new, old); -#endif - if (new) - if (!access_ok(VERIFY_READ, new, sizeof(*new))) - return -EFAULT; - - if (old) { - if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - return -EFAULT; - } - - return 0; -} - -struct irix_procset { - int cmd, ltype, lid, rtype, rid; -}; - -asmlinkage int irix_sigsendset(struct irix_procset __user *pset, int sig) -{ - if (!access_ok(VERIFY_READ, pset, sizeof(*pset))) - return -EFAULT; -#ifdef DEBUG_SIG - printk("[%s:%d] irix_sigsendset([%d,%d,%d,%d,%d],%d)\n", - current->comm, current->pid, - pset->cmd, pset->ltype, pset->lid, pset->rtype, pset->rid, - sig); -#endif - return -EINVAL; -} diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 2c09a442e5e5..c06f5b5d764c 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -125,13 +125,6 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, *childregs = *regs; childregs->regs[7] = 0; /* Clear error flag */ -#if defined(CONFIG_BINFMT_IRIX) - if (current->personality != PER_LINUX) { - /* Under IRIX things are a little different. */ - childregs->regs[3] = 1; - regs->regs[3] = 0; - } -#endif childregs->regs[2] = 0; /* Child gets zero as return value */ regs->regs[2] = p->pid; diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 08a9c5070ea8..c058c0b61a2a 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -34,12 +34,8 @@ NESTED(handle_sys, PT_SIZE, sp) lw t1, PT_EPC(sp) # skip syscall on return -#if defined(CONFIG_BINFMT_IRIX) - sltiu t0, v0, MAX_SYSCALL_NO + 1 # check syscall number -#else subu v0, v0, __NR_O32_Linux # check syscall number sltiu t0, v0, __NR_O32_Linux_syscalls + 1 -#endif addiu t1, 4 # skip to next instruction sw t1, PT_EPC(sp) beqz t0, illegal_syscall @@ -264,22 +260,14 @@ bad_alignment: END(sys_sysmips) LEAF(sys_syscall) -#if defined(CONFIG_BINFMT_IRIX) - sltiu v0, a0, MAX_SYSCALL_NO + 1 # check syscall number -#else subu t0, a0, __NR_O32_Linux # check syscall number sltiu v0, t0, __NR_O32_Linux_syscalls + 1 -#endif sll t1, t0, 3 beqz v0, einval lw t2, sys_call_table(t1) # syscall routine -#if defined(CONFIG_BINFMT_IRIX) - li v1, 4000 # nr of sys_syscall -#else li v1, 4000 - __NR_O32_Linux # index of sys_syscall -#endif beq t0, v1, einval # do not recurse /* Some syscalls like execve get their arguments from struct pt_regs @@ -324,13 +312,6 @@ einval: li v0, -EINVAL .endm .macro syscalltable -#if defined(CONFIG_BINFMT_IRIX) - mille sys_ni_syscall 0 /* 0 - 999 SVR4 flavour */ - mille sys_ni_syscall 0 /* 1000 - 1999 32-bit IRIX */ - mille sys_ni_syscall 0 /* 2000 - 2999 BSD43 flavour */ - mille sys_ni_syscall 0 /* 3000 - 3999 POSIX flavour */ -#endif - sys sys_syscall 8 /* 4000 */ sys sys_exit 1 sys sys_fork 0 diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c deleted file mode 100644 index c357762b8012..000000000000 --- a/arch/mips/kernel/sysirix.c +++ /dev/null @@ -1,2140 +0,0 @@ -/* - * sysirix.c: IRIX system call emulation. - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1997 Miguel de Icaza - * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* 2,191 lines of complete and utter shit coming up... */ - -extern int max_threads; - -/* The sysmp commands supported thus far. */ -#define MP_NPROCS 1 /* # processor in complex */ -#define MP_NAPROCS 2 /* # active processors in complex */ -#define MP_PGSIZE 14 /* Return system page size in v1. */ - -asmlinkage int irix_sysmp(struct pt_regs *regs) -{ - unsigned long cmd; - int base = 0; - int error = 0; - - if(regs->regs[2] == 1000) - base = 1; - cmd = regs->regs[base + 4]; - switch(cmd) { - case MP_PGSIZE: - error = PAGE_SIZE; - break; - case MP_NPROCS: - case MP_NAPROCS: - error = num_online_cpus(); - break; - default: - printk("SYSMP[%s:%d]: Unsupported opcode %d\n", - current->comm, current->pid, (int)cmd); - error = -EINVAL; - break; - } - - return error; -} - -/* The prctl commands. */ -#define PR_MAXPROCS 1 /* Tasks/user. */ -#define PR_ISBLOCKED 2 /* If blocked, return 1. */ -#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */ -#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */ -#define PR_MAXPPROCS 5 /* Num parallel tasks. */ -#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */ -#define PR_SETEXITSIG 8 /* When task exit's, set signal. */ -#define PR_RESIDENT 9 /* Make task unswappable. */ -#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */ -#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */ -#define PR_TERMCHILD 12 /* Kill child if the parent dies. */ -#define PR_GETSHMASK 13 /* Get the sproc() share mask. */ -#define PR_GETNSHARE 14 /* Number of share group members. */ -#define PR_COREPID 15 /* Add task pid to name when it core. */ -#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */ -#define PR_PTHREADEXIT 17 /* Kill a pthread, only for IRIX 6.[234] */ - -asmlinkage int irix_prctl(unsigned option, ...) -{ - va_list args; - int error = 0; - - va_start(args, option); - switch (option) { - case PR_MAXPROCS: - printk("irix_prctl[%s:%d]: Wants PR_MAXPROCS\n", - current->comm, current->pid); - error = max_threads; - break; - - case PR_ISBLOCKED: { - struct task_struct *task; - - printk("irix_prctl[%s:%d]: Wants PR_ISBLOCKED\n", - current->comm, current->pid); - read_lock(&tasklist_lock); - task = find_task_by_vpid(va_arg(args, pid_t)); - error = -ESRCH; - if (error) - error = (task->run_list.next != NULL); - read_unlock(&tasklist_lock); - /* Can _your_ OS find this out that fast? */ - break; - } - - case PR_SETSTACKSIZE: { - long value = va_arg(args, long); - - printk("irix_prctl[%s:%d]: Wants PR_SETSTACKSIZE<%08lx>\n", - current->comm, current->pid, (unsigned long) value); - if (value > RLIM_INFINITY) - value = RLIM_INFINITY; - if (capable(CAP_SYS_ADMIN)) { - task_lock(current->group_leader); - current->signal->rlim[RLIMIT_STACK].rlim_max = - current->signal->rlim[RLIMIT_STACK].rlim_cur = value; - task_unlock(current->group_leader); - error = value; - break; - } - task_lock(current->group_leader); - if (value > current->signal->rlim[RLIMIT_STACK].rlim_max) { - error = -EINVAL; - task_unlock(current->group_leader); - break; - } - current->signal->rlim[RLIMIT_STACK].rlim_cur = value; - task_unlock(current->group_leader); - error = value; - break; - } - - case PR_GETSTACKSIZE: - printk("irix_prctl[%s:%d]: Wants PR_GETSTACKSIZE\n", - current->comm, current->pid); - error = current->signal->rlim[RLIMIT_STACK].rlim_cur; - break; - - case PR_MAXPPROCS: - printk("irix_prctl[%s:%d]: Wants PR_MAXPROCS\n", - current->comm, current->pid); - error = 1; - break; - - case PR_UNBLKONEXEC: - printk("irix_prctl[%s:%d]: Wants PR_UNBLKONEXEC\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_SETEXITSIG: - printk("irix_prctl[%s:%d]: Wants PR_SETEXITSIG\n", - current->comm, current->pid); - - /* We can probably play some game where we set the task - * exit_code to some non-zero value when this is requested, - * and check whether exit_code is already set in do_exit(). - */ - error = -EINVAL; - break; - - case PR_RESIDENT: - printk("irix_prctl[%s:%d]: Wants PR_RESIDENT\n", - current->comm, current->pid); - error = 0; /* Compatibility indeed. */ - break; - - case PR_ATTACHADDR: - printk("irix_prctl[%s:%d]: Wants PR_ATTACHADDR\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_DETACHADDR: - printk("irix_prctl[%s:%d]: Wants PR_DETACHADDR\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_TERMCHILD: - printk("irix_prctl[%s:%d]: Wants PR_TERMCHILD\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_GETSHMASK: - printk("irix_prctl[%s:%d]: Wants PR_GETSHMASK\n", - current->comm, current->pid); - error = -EINVAL; /* Until I have the sproc() stuff in. */ - break; - - case PR_GETNSHARE: - error = 0; /* Until I have the sproc() stuff in. */ - break; - - case PR_COREPID: - printk("irix_prctl[%s:%d]: Wants PR_COREPID\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_ATTACHADDRPERM: - printk("irix_prctl[%s:%d]: Wants PR_ATTACHADDRPERM\n", - current->comm, current->pid); - error = -EINVAL; - break; - - default: - printk("irix_prctl[%s:%d]: Non-existant opcode %d\n", - current->comm, current->pid, option); - error = -EINVAL; - break; - } - va_end(args); - - return error; -} - -#undef DEBUG_PROCGRPS - -extern unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt); -extern char *prom_getenv(char *name); -extern long prom_setenv(char *name, char *value); - -/* The syssgi commands supported thus far. */ -#define SGI_SYSID 1 /* Return unique per-machine identifier. */ -#define SGI_INVENT 5 /* Fetch inventory */ -# define SGI_INV_SIZEOF 1 -# define SGI_INV_READ 2 -#define SGI_RDNAME 6 /* Return string name of a process. */ -#define SGI_SETNVRAM 8 /* Set PROM variable. */ -#define SGI_GETNVRAM 9 /* Get PROM variable. */ -#define SGI_SETPGID 21 /* Set process group id. */ -#define SGI_SYSCONF 22 /* POSIX sysconf garbage. */ -#define SGI_PATHCONF 24 /* POSIX sysconf garbage. */ -#define SGI_SETGROUPS 40 /* POSIX sysconf garbage. */ -#define SGI_GETGROUPS 41 /* POSIX sysconf garbage. */ -#define SGI_RUSAGE 56 /* BSD style rusage(). */ -#define SGI_SSYNC 62 /* Synchronous fs sync. */ -#define SGI_GETSID 65 /* SysVr4 get session id. */ -#define SGI_ELFMAP 68 /* Map an elf image. */ -#define SGI_TOSSTSAVE 108 /* Toss saved vma's. */ -#define SGI_FP_BCOPY 129 /* Should FPU bcopy be used on this machine? */ -#define SGI_PHYSP 1011 /* Translate virtual into physical page. */ - -asmlinkage int irix_syssgi(struct pt_regs *regs) -{ - unsigned long cmd; - int retval, base = 0; - - if (regs->regs[2] == 1000) - base = 1; - - cmd = regs->regs[base + 4]; - switch(cmd) { - case SGI_SYSID: { - char __user *buf = (char __user *) regs->regs[base + 5]; - - /* XXX Use ethernet addr.... */ - retval = clear_user(buf, 64) ? -EFAULT : 0; - break; - } -#if 0 - case SGI_RDNAME: { - int pid = (int) regs->regs[base + 5]; - char __user *buf = (char __user *) regs->regs[base + 6]; - struct task_struct *p; - char tcomm[sizeof(current->comm)]; - - read_lock(&tasklist_lock); - p = find_task_by_pid(pid); - if (!p) { - read_unlock(&tasklist_lock); - retval = -ESRCH; - break; - } - get_task_comm(tcomm, p); - read_unlock(&tasklist_lock); - - /* XXX Need to check sizes. */ - retval = copy_to_user(buf, tcomm, sizeof(tcomm)) ? -EFAULT : 0; - break; - } - - case SGI_GETNVRAM: { - char __user *name = (char __user *) regs->regs[base+5]; - char __user *buf = (char __user *) regs->regs[base+6]; - char *value; - return -EINVAL; /* til I fix it */ - value = prom_getenv(name); /* PROM lock? */ - if (!value) { - retval = -EINVAL; - break; - } - /* Do I strlen() for the length? */ - retval = copy_to_user(buf, value, 128) ? -EFAULT : 0; - break; - } - - case SGI_SETNVRAM: { - char __user *name = (char __user *) regs->regs[base+5]; - char __user *value = (char __user *) regs->regs[base+6]; - return -EINVAL; /* til I fix it */ - retval = prom_setenv(name, value); - /* XXX make sure retval conforms to syssgi(2) */ - printk("[%s:%d] setnvram(\"%s\", \"%s\"): retval %d", - current->comm, current->pid, name, value, retval); -/* if (retval == PROM_ENOENT) - retval = -ENOENT; */ - break; - } -#endif - - case SGI_SETPGID: { -#ifdef DEBUG_PROCGRPS - printk("[%s:%d] setpgid(%d, %d) ", - current->comm, current->pid, - (int) regs->regs[base + 5], (int)regs->regs[base + 6]); -#endif - retval = sys_setpgid(regs->regs[base + 5], regs->regs[base + 6]); - -#ifdef DEBUG_PROCGRPS - printk("retval=%d\n", retval); -#endif - } - - case SGI_SYSCONF: { - switch(regs->regs[base + 5]) { - case 1: - retval = (MAX_ARG_PAGES >> 4); /* XXX estimate... */ - goto out; - case 2: - retval = max_threads; - goto out; - case 3: - retval = HZ; - goto out; - case 4: - retval = NGROUPS_MAX; - goto out; - case 5: - retval = sysctl_nr_open; - goto out; - case 6: - retval = 1; - goto out; - case 7: - retval = 1; - goto out; - case 8: - retval = 199009; - goto out; - case 11: - retval = PAGE_SIZE; - goto out; - case 12: - retval = 4; - goto out; - case 25: - case 26: - case 27: - case 28: - case 29: - case 30: - retval = 0; - goto out; - case 31: - retval = 32; - goto out; - default: - retval = -EINVAL; - goto out; - }; - } - - case SGI_SETGROUPS: - retval = sys_setgroups((int) regs->regs[base + 5], - (gid_t __user *) regs->regs[base + 6]); - break; - - case SGI_GETGROUPS: - retval = sys_getgroups((int) regs->regs[base + 5], - (gid_t __user *) regs->regs[base + 6]); - break; - - case SGI_RUSAGE: { - struct rusage __user *ru = (struct rusage __user *) regs->regs[base + 6]; - - switch((int) regs->regs[base + 5]) { - case 0: - /* rusage self */ - retval = getrusage(current, RUSAGE_SELF, ru); - goto out; - - case -1: - /* rusage children */ - retval = getrusage(current, RUSAGE_CHILDREN, ru); - goto out; - - default: - retval = -EINVAL; - goto out; - }; - } - - case SGI_SSYNC: - sys_sync(); - retval = 0; - break; - - case SGI_GETSID: -#ifdef DEBUG_PROCGRPS - printk("[%s:%d] getsid(%d) ", current->comm, current->pid, - (int) regs->regs[base + 5]); -#endif - retval = sys_getsid(regs->regs[base + 5]); -#ifdef DEBUG_PROCGRPS - printk("retval=%d\n", retval); -#endif - break; - - case SGI_ELFMAP: - retval = irix_mapelf((int) regs->regs[base + 5], - (struct elf_phdr __user *) regs->regs[base + 6], - (int) regs->regs[base + 7]); - break; - - case SGI_TOSSTSAVE: - /* XXX We don't need to do anything? */ - retval = 0; - break; - - case SGI_FP_BCOPY: - retval = 0; - break; - - case SGI_PHYSP: { - unsigned long addr = regs->regs[base + 5]; - int __user *pageno = (int __user *) (regs->regs[base + 6]); - struct mm_struct *mm = current->mm; - pgd_t *pgdp; - pud_t *pudp; - pmd_t *pmdp; - pte_t *ptep; - - down_read(&mm->mmap_sem); - pgdp = pgd_offset(mm, addr); - pudp = pud_offset(pgdp, addr); - pmdp = pmd_offset(pudp, addr); - ptep = pte_offset(pmdp, addr); - retval = -EINVAL; - if (ptep) { - pte_t pte = *ptep; - - if (pte_val(pte) & (_PAGE_VALID | _PAGE_PRESENT)) { - /* b0rked on 64-bit */ - retval = put_user((pte_val(pte) & PAGE_MASK) >> - PAGE_SHIFT, pageno); - } - } - up_read(&mm->mmap_sem); - break; - } - - case SGI_INVENT: { - int arg1 = (int) regs->regs [base + 5]; - void __user *buffer = (void __user *) regs->regs [base + 6]; - int count = (int) regs->regs [base + 7]; - - switch (arg1) { - case SGI_INV_SIZEOF: - retval = sizeof(inventory_t); - break; - case SGI_INV_READ: - retval = dump_inventory_to_user(buffer, count); - break; - default: - retval = -EINVAL; - } - break; - } - - default: - printk("irix_syssgi: Unsupported command %d\n", (int)cmd); - retval = -EINVAL; - break; - }; - -out: - return retval; -} - -asmlinkage int irix_gtime(struct pt_regs *regs) -{ - return get_seconds(); -} - -/* - * IRIX is completely broken... it returns 0 on success, otherwise - * ENOMEM. - */ -asmlinkage int irix_brk(unsigned long brk) -{ - unsigned long rlim; - unsigned long newbrk, oldbrk; - struct mm_struct *mm = current->mm; - int ret; - - down_write(&mm->mmap_sem); - if (brk < mm->end_code) { - ret = -ENOMEM; - goto out; - } - - newbrk = PAGE_ALIGN(brk); - oldbrk = PAGE_ALIGN(mm->brk); - if (oldbrk == newbrk) { - mm->brk = brk; - ret = 0; - goto out; - } - - /* - * Always allow shrinking brk - */ - if (brk <= mm->brk) { - mm->brk = brk; - do_munmap(mm, newbrk, oldbrk-newbrk); - ret = 0; - goto out; - } - /* - * Check against rlimit and stack.. - */ - rlim = current->signal->rlim[RLIMIT_DATA].rlim_cur; - if (rlim >= RLIM_INFINITY) - rlim = ~0; - if (brk - mm->end_code > rlim) { - ret = -ENOMEM; - goto out; - } - - /* - * Check against existing mmap mappings. - */ - if (find_vma_intersection(mm, oldbrk, newbrk+PAGE_SIZE)) { - ret = -ENOMEM; - goto out; - } - - /* - * Ok, looks good - let it rip. - */ - if (do_brk(oldbrk, newbrk-oldbrk) != oldbrk) { - ret = -ENOMEM; - goto out; - } - mm->brk = brk; - ret = 0; - -out: - up_write(&mm->mmap_sem); - return ret; -} - -asmlinkage int irix_getpid(struct pt_regs *regs) -{ - regs->regs[3] = task_pid_vnr(current->real_parent); - return task_pid_vnr(current); -} - -asmlinkage int irix_getuid(struct pt_regs *regs) -{ - regs->regs[3] = current->euid; - return current->uid; -} - -asmlinkage int irix_getgid(struct pt_regs *regs) -{ - regs->regs[3] = current->egid; - return current->gid; -} - -asmlinkage int irix_stime(int value) -{ - int err; - struct timespec tv; - - tv.tv_sec = value; - tv.tv_nsec = 0; - err = security_settime(&tv, NULL); - if (err) - return err; - - write_seqlock_irq(&xtime_lock); - xtime.tv_sec = value; - xtime.tv_nsec = 0; - ntp_clear(); - write_sequnlock_irq(&xtime_lock); - - return 0; -} - -static inline void jiffiestotv(unsigned long jiffies, struct timeval *value) -{ - value->tv_usec = (jiffies % HZ) * (1000000 / HZ); - value->tv_sec = jiffies / HZ; -} - -static inline void getitimer_real(struct itimerval *value) -{ - register unsigned long val, interval; - - interval = current->it_real_incr; - val = 0; - if (del_timer(¤t->real_timer)) { - unsigned long now = jiffies; - val = current->real_timer.expires; - add_timer(¤t->real_timer); - /* look out for negative/zero itimer.. */ - if (val <= now) - val = now+1; - val -= now; - } - jiffiestotv(val, &value->it_value); - jiffiestotv(interval, &value->it_interval); -} - -asmlinkage unsigned int irix_alarm(unsigned int seconds) -{ - return alarm_setitimer(seconds); -} - -asmlinkage int irix_pause(void) -{ - current->state = TASK_INTERRUPTIBLE; - schedule(); - - return -EINTR; -} - -/* XXX need more than this... */ -asmlinkage int irix_mount(char __user *dev_name, char __user *dir_name, - unsigned long flags, char __user *type, void __user *data, int datalen) -{ - printk("[%s:%d] irix_mount(%p,%p,%08lx,%p,%p,%d)\n", - current->comm, current->pid, - dev_name, dir_name, flags, type, data, datalen); - - return sys_mount(dev_name, dir_name, type, flags, data); -} - -struct irix_statfs { - short f_type; - long f_bsize, f_frsize, f_blocks, f_bfree, f_files, f_ffree; - char f_fname[6], f_fpack[6]; -}; - -asmlinkage int irix_statfs(const char __user *path, - struct irix_statfs __user *buf, int len, int fs_type) -{ - struct nameidata nd; - struct kstatfs kbuf; - int error, i; - - /* We don't support this feature yet. */ - if (fs_type) { - error = -EINVAL; - goto out; - } - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statfs))) { - error = -EFAULT; - goto out; - } - - error = user_path_walk(path, &nd); - if (error) - goto out; - - error = vfs_statfs(nd.path.dentry, &kbuf); - if (error) - goto dput_and_out; - - error = __put_user(kbuf.f_type, &buf->f_type); - error |= __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - for (i = 0; i < 6; i++) { - error |= __put_user(0, &buf->f_fname[i]); - error |= __put_user(0, &buf->f_fpack[i]); - } - -dput_and_out: - path_put(&nd.path); -out: - return error; -} - -asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs __user *buf) -{ - struct kstatfs kbuf; - struct file *file; - int error, i; - - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statfs))) { - error = -EFAULT; - goto out; - } - - if (!(file = fget(fd))) { - error = -EBADF; - goto out; - } - - error = vfs_statfs(file->f_path.dentry, &kbuf); - if (error) - goto out_f; - - error = __put_user(kbuf.f_type, &buf->f_type); - error |= __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - - for (i = 0; i < 6; i++) { - error |= __put_user(0, &buf->f_fname[i]); - error |= __put_user(0, &buf->f_fpack[i]); - } - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_setpgrp(int flags) -{ - int error; - -#ifdef DEBUG_PROCGRPS - printk("[%s:%d] setpgrp(%d) ", current->comm, current->pid, flags); -#endif - if(!flags) - error = task_pgrp_vnr(current); - else - error = sys_setsid(); -#ifdef DEBUG_PROCGRPS - printk("returning %d\n", error); -#endif - - return error; -} - -asmlinkage int irix_times(struct tms __user *tbuf) -{ - int err = 0; - - if (tbuf) { - if (!access_ok(VERIFY_WRITE, tbuf, sizeof *tbuf)) - return -EFAULT; - - err = __put_user(current->utime, &tbuf->tms_utime); - err |= __put_user(current->stime, &tbuf->tms_stime); - err |= __put_user(current->signal->cutime, &tbuf->tms_cutime); - err |= __put_user(current->signal->cstime, &tbuf->tms_cstime); - } - - return err; -} - -asmlinkage int irix_exec(struct pt_regs *regs) -{ - int error, base = 0; - char *filename; - - if(regs->regs[2] == 1000) - base = 1; - filename = getname((char __user *) (long)regs->regs[base + 4]); - error = PTR_ERR(filename); - if (IS_ERR(filename)) - return error; - - error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5], - NULL, regs); - putname(filename); - - return error; -} - -asmlinkage int irix_exece(struct pt_regs *regs) -{ - int error, base = 0; - char *filename; - - if (regs->regs[2] == 1000) - base = 1; - filename = getname((char __user *) (long)regs->regs[base + 4]); - error = PTR_ERR(filename); - if (IS_ERR(filename)) - return error; - error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5], - (char __user * __user *) (long)regs->regs[base + 6], regs); - putname(filename); - - return error; -} - -asmlinkage unsigned long irix_gethostid(void) -{ - printk("[%s:%d]: irix_gethostid() called...\n", - current->comm, current->pid); - - return -EINVAL; -} - -asmlinkage unsigned long irix_sethostid(unsigned long val) -{ - printk("[%s:%d]: irix_sethostid(%08lx) called...\n", - current->comm, current->pid, val); - - return -EINVAL; -} - -asmlinkage int irix_socket(int family, int type, int protocol) -{ - switch(type) { - case 1: - type = SOCK_DGRAM; - break; - - case 2: - type = SOCK_STREAM; - break; - - case 3: - type = 9; /* Invalid... */ - break; - - case 4: - type = SOCK_RAW; - break; - - case 5: - type = SOCK_RDM; - break; - - case 6: - type = SOCK_SEQPACKET; - break; - - default: - break; - } - - return sys_socket(family, type, protocol); -} - -asmlinkage int irix_getdomainname(char __user *name, int len) -{ - int err; - - down_read(&uts_sem); - if (len > __NEW_UTS_LEN) - len = __NEW_UTS_LEN; - err = copy_to_user(name, utsname()->domainname, len) ? -EFAULT : 0; - up_read(&uts_sem); - - return err; -} - -asmlinkage unsigned long irix_getpagesize(void) -{ - return PAGE_SIZE; -} - -asmlinkage int irix_msgsys(int opcode, unsigned long arg0, unsigned long arg1, - unsigned long arg2, unsigned long arg3, - unsigned long arg4) -{ - switch (opcode) { - case 0: - return sys_msgget((key_t) arg0, (int) arg1); - case 1: - return sys_msgctl((int) arg0, (int) arg1, - (struct msqid_ds __user *)arg2); - case 2: - return sys_msgrcv((int) arg0, (struct msgbuf __user *) arg1, - (size_t) arg2, (long) arg3, (int) arg4); - case 3: - return sys_msgsnd((int) arg0, (struct msgbuf __user *) arg1, - (size_t) arg2, (int) arg3); - default: - return -EINVAL; - } -} - -asmlinkage int irix_shmsys(int opcode, unsigned long arg0, unsigned long arg1, - unsigned long arg2, unsigned long arg3) -{ - switch (opcode) { - case 0: - return do_shmat((int) arg0, (char __user *) arg1, (int) arg2, - (unsigned long *) arg3); - case 1: - return sys_shmctl((int)arg0, (int)arg1, - (struct shmid_ds __user *)arg2); - case 2: - return sys_shmdt((char __user *)arg0); - case 3: - return sys_shmget((key_t) arg0, (int) arg1, (int) arg2); - default: - return -EINVAL; - } -} - -asmlinkage int irix_semsys(int opcode, unsigned long arg0, unsigned long arg1, - unsigned long arg2, int arg3) -{ - switch (opcode) { - case 0: - return sys_semctl((int) arg0, (int) arg1, (int) arg2, - (union semun) arg3); - case 1: - return sys_semget((key_t) arg0, (int) arg1, (int) arg2); - case 2: - return sys_semop((int) arg0, (struct sembuf __user *)arg1, - (unsigned int) arg2); - default: - return -EINVAL; - } -} - -static inline loff_t llseek(struct file *file, loff_t offset, int origin) -{ - loff_t (*fn)(struct file *, loff_t, int); - loff_t retval; - - fn = default_llseek; - if (file->f_op && file->f_op->llseek) - fn = file->f_op->llseek; - lock_kernel(); - retval = fn(file, offset, origin); - unlock_kernel(); - - return retval; -} - -asmlinkage int irix_lseek64(int fd, int _unused, int offhi, int offlow, - int origin) -{ - struct file * file; - loff_t offset; - int retval; - - retval = -EBADF; - file = fget(fd); - if (!file) - goto bad; - retval = -EINVAL; - if (origin > 2) - goto out_putf; - - offset = llseek(file, ((loff_t) offhi << 32) | offlow, origin); - retval = (int) offset; - -out_putf: - fput(file); -bad: - return retval; -} - -asmlinkage int irix_sginap(int ticks) -{ - schedule_timeout_interruptible(ticks); - return 0; -} - -asmlinkage int irix_sgikopt(char __user *istring, char __user *ostring, int len) -{ - return -EINVAL; -} - -asmlinkage int irix_gettimeofday(struct timeval __user *tv) -{ - time_t sec; - long nsec, seq; - int err; - - if (!access_ok(VERIFY_WRITE, tv, sizeof(struct timeval))) - return -EFAULT; - - do { - seq = read_seqbegin(&xtime_lock); - sec = xtime.tv_sec; - nsec = xtime.tv_nsec; - } while (read_seqretry(&xtime_lock, seq)); - - err = __put_user(sec, &tv->tv_sec); - err |= __put_user((nsec / 1000), &tv->tv_usec); - - return err; -} - -#define IRIX_MAP_AUTOGROW 0x40 - -asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot, - int flags, int fd, off_t offset) -{ - struct file *file = NULL; - unsigned long retval; - - if (!(flags & MAP_ANONYMOUS)) { - if (!(file = fget(fd))) - return -EBADF; - - /* Ok, bad taste hack follows, try to think in something else - * when reading this. */ - if (flags & IRIX_MAP_AUTOGROW) { - unsigned long old_pos; - long max_size = offset + len; - - if (max_size > file->f_path.dentry->d_inode->i_size) { - old_pos = sys_lseek(fd, max_size - 1, 0); - sys_write(fd, (void __user *) "", 1); - sys_lseek(fd, old_pos, 0); - } - } - } - - flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); - - down_write(¤t->mm->mmap_sem); - retval = do_mmap(file, addr, len, prot, flags, offset); - up_write(¤t->mm->mmap_sem); - if (file) - fput(file); - - return retval; -} - -asmlinkage int irix_madvise(unsigned long addr, int len, int behavior) -{ - printk("[%s:%d] Wheee.. irix_madvise(%08lx,%d,%d)\n", - current->comm, current->pid, addr, len, behavior); - - return -EINVAL; -} - -asmlinkage int irix_pagelock(char __user *addr, int len, int op) -{ - printk("[%s:%d] Wheee.. irix_pagelock(%p,%d,%d)\n", - current->comm, current->pid, addr, len, op); - - return -EINVAL; -} - -asmlinkage int irix_quotactl(struct pt_regs *regs) -{ - printk("[%s:%d] Wheee.. irix_quotactl()\n", - current->comm, current->pid); - - return -EINVAL; -} - -asmlinkage int irix_BSDsetpgrp(int pid, int pgrp) -{ - int error; - -#ifdef DEBUG_PROCGRPS - printk("[%s:%d] BSDsetpgrp(%d, %d) ", current->comm, current->pid, - pid, pgrp); -#endif - if(!pid) - pid = task_pid_vnr(current); - - /* Wheee, weird sysv thing... */ - if ((pgrp == 0) && (pid == task_pid_vnr(current))) - error = sys_setsid(); - else - error = sys_setpgid(pid, pgrp); - -#ifdef DEBUG_PROCGRPS - printk("error = %d\n", error); -#endif - - return error; -} - -asmlinkage int irix_systeminfo(int cmd, char __user *buf, int cnt) -{ - printk("[%s:%d] Wheee.. irix_systeminfo(%d,%p,%d)\n", - current->comm, current->pid, cmd, buf, cnt); - - return -EINVAL; -} - -struct iuname { - char sysname[257], nodename[257], release[257]; - char version[257], machine[257]; - char m_type[257], base_rel[257]; - char _unused0[257], _unused1[257], _unused2[257]; - char _unused3[257], _unused4[257], _unused5[257]; -}; - -asmlinkage int irix_uname(struct iuname __user *buf) -{ - down_read(&uts_sem); - if (copy_from_user(utsname()->sysname, buf->sysname, 65) - || copy_from_user(utsname()->nodename, buf->nodename, 65) - || copy_from_user(utsname()->release, buf->release, 65) - || copy_from_user(utsname()->version, buf->version, 65) - || copy_from_user(utsname()->machine, buf->machine, 65)) { - return -EFAULT; - } - up_read(&uts_sem); - - return 1; -} - -#undef DEBUG_XSTAT - -static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf) -{ - struct xstat32 { - u32 st_dev, st_pad1[3], st_ino, st_mode, st_nlink, st_uid, st_gid; - u32 st_rdev, st_pad2[2], st_size, st_pad3; - u32 st_atime0, st_atime1; - u32 st_mtime0, st_mtime1; - u32 st_ctime0, st_ctime1; - u32 st_blksize, st_blocks; - char st_fstype[16]; - u32 st_pad4[8]; - } ub; - - if (!sysv_valid_dev(stat->dev) || !sysv_valid_dev(stat->rdev)) - return -EOVERFLOW; - ub.st_dev = sysv_encode_dev(stat->dev); - ub.st_ino = stat->ino; - ub.st_mode = stat->mode; - ub.st_nlink = stat->nlink; - SET_UID(ub.st_uid, stat->uid); - SET_GID(ub.st_gid, stat->gid); - ub.st_rdev = sysv_encode_dev(stat->rdev); -#if BITS_PER_LONG == 32 - if (stat->size > MAX_NON_LFS) - return -EOVERFLOW; -#endif - ub.st_size = stat->size; - ub.st_atime0 = stat->atime.tv_sec; - ub.st_atime1 = stat->atime.tv_nsec; - ub.st_mtime0 = stat->mtime.tv_sec; - ub.st_mtime1 = stat->atime.tv_nsec; - ub.st_ctime0 = stat->ctime.tv_sec; - ub.st_ctime1 = stat->atime.tv_nsec; - ub.st_blksize = stat->blksize; - ub.st_blocks = stat->blocks; - strcpy(ub.st_fstype, "efs"); - - return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0; -} - -static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf) -{ - struct xstat64 { - u32 st_dev; s32 st_pad1[3]; - unsigned long long st_ino; - u32 st_mode; - u32 st_nlink; s32 st_uid; s32 st_gid; u32 st_rdev; - s32 st_pad2[2]; - long long st_size; - s32 st_pad3; - struct { s32 tv_sec, tv_nsec; } st_atime, st_mtime, st_ctime; - s32 st_blksize; - long long st_blocks; - char st_fstype[16]; - s32 st_pad4[8]; - } ks; - - if (!sysv_valid_dev(stat->dev) || !sysv_valid_dev(stat->rdev)) - return -EOVERFLOW; - - ks.st_dev = sysv_encode_dev(stat->dev); - ks.st_pad1[0] = ks.st_pad1[1] = ks.st_pad1[2] = 0; - ks.st_ino = (unsigned long long) stat->ino; - ks.st_mode = (u32) stat->mode; - ks.st_nlink = (u32) stat->nlink; - ks.st_uid = (s32) stat->uid; - ks.st_gid = (s32) stat->gid; - ks.st_rdev = sysv_encode_dev(stat->rdev); - ks.st_pad2[0] = ks.st_pad2[1] = 0; - ks.st_size = (long long) stat->size; - ks.st_pad3 = 0; - - /* XXX hackety hack... */ - ks.st_atime.tv_sec = (s32) stat->atime.tv_sec; - ks.st_atime.tv_nsec = stat->atime.tv_nsec; - ks.st_mtime.tv_sec = (s32) stat->mtime.tv_sec; - ks.st_mtime.tv_nsec = stat->mtime.tv_nsec; - ks.st_ctime.tv_sec = (s32) stat->ctime.tv_sec; - ks.st_ctime.tv_nsec = stat->ctime.tv_nsec; - - ks.st_blksize = (s32) stat->blksize; - ks.st_blocks = (long long) stat->blocks; - memset(ks.st_fstype, 0, 16); - ks.st_pad4[0] = ks.st_pad4[1] = ks.st_pad4[2] = ks.st_pad4[3] = 0; - ks.st_pad4[4] = ks.st_pad4[5] = ks.st_pad4[6] = ks.st_pad4[7] = 0; - - /* Now write it all back. */ - return copy_to_user(ubuf, &ks, sizeof(ks)) ? -EFAULT : 0; -} - -asmlinkage int irix_xstat(int version, char __user *filename, struct stat __user *statbuf) -{ - int retval; - struct kstat stat; - -#ifdef DEBUG_XSTAT - printk("[%s:%d] Wheee.. irix_xstat(%d,%s,%p) ", - current->comm, current->pid, version, filename, statbuf); -#endif - - retval = vfs_stat(filename, &stat); - if (!retval) { - switch(version) { - case 2: - retval = irix_xstat32_xlate(&stat, statbuf); - break; - case 3: - retval = irix_xstat64_xlate(&stat, statbuf); - break; - default: - retval = -EINVAL; - } - } - return retval; -} - -asmlinkage int irix_lxstat(int version, char __user *filename, struct stat __user *statbuf) -{ - int error; - struct kstat stat; - -#ifdef DEBUG_XSTAT - printk("[%s:%d] Wheee.. irix_lxstat(%d,%s,%p) ", - current->comm, current->pid, version, filename, statbuf); -#endif - - error = vfs_lstat(filename, &stat); - - if (!error) { - switch (version) { - case 2: - error = irix_xstat32_xlate(&stat, statbuf); - break; - case 3: - error = irix_xstat64_xlate(&stat, statbuf); - break; - default: - error = -EINVAL; - } - } - return error; -} - -asmlinkage int irix_fxstat(int version, int fd, struct stat __user *statbuf) -{ - int error; - struct kstat stat; - -#ifdef DEBUG_XSTAT - printk("[%s:%d] Wheee.. irix_fxstat(%d,%d,%p) ", - current->comm, current->pid, version, fd, statbuf); -#endif - - error = vfs_fstat(fd, &stat); - if (!error) { - switch (version) { - case 2: - error = irix_xstat32_xlate(&stat, statbuf); - break; - case 3: - error = irix_xstat64_xlate(&stat, statbuf); - break; - default: - error = -EINVAL; - } - } - return error; -} - -asmlinkage int irix_xmknod(int ver, char __user *filename, int mode, unsigned dev) -{ - int retval; - printk("[%s:%d] Wheee.. irix_xmknod(%d,%s,%x,%x)\n", - current->comm, current->pid, ver, filename, mode, dev); - - switch(ver) { - case 2: - /* shouldn't we convert here as well as on stat()? */ - retval = sys_mknod(filename, mode, dev); - break; - - default: - retval = -EINVAL; - break; - }; - - return retval; -} - -asmlinkage int irix_swapctl(int cmd, char __user *arg) -{ - printk("[%s:%d] Wheee.. irix_swapctl(%d,%p)\n", - current->comm, current->pid, cmd, arg); - - return -EINVAL; -} - -struct irix_statvfs { - u32 f_bsize; u32 f_frsize; u32 f_blocks; - u32 f_bfree; u32 f_bavail; u32 f_files; u32 f_ffree; u32 f_favail; - u32 f_fsid; char f_basetype[16]; - u32 f_flag; u32 f_namemax; - char f_fstr[32]; u32 f_filler[16]; -}; - -asmlinkage int irix_statvfs(char __user *fname, struct irix_statvfs __user *buf) -{ - struct nameidata nd; - struct kstatfs kbuf; - int error, i; - - printk("[%s:%d] Wheee.. irix_statvfs(%s,%p)\n", - current->comm, current->pid, fname, buf); - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) - return -EFAULT; - - error = user_path_walk(fname, &nd); - if (error) - goto out; - error = vfs_statfs(nd.path.dentry, &kbuf); - if (error) - goto dput_and_out; - - error |= __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ -#ifdef __MIPSEB__ - error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); -#else - error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); -#endif - for (i = 0; i < 16; i++) - error |= __put_user(0, &buf->f_basetype[i]); - error |= __put_user(0, &buf->f_flag); - error |= __put_user(kbuf.f_namelen, &buf->f_namemax); - for (i = 0; i < 32; i++) - error |= __put_user(0, &buf->f_fstr[i]); - -dput_and_out: - path_put(&nd.path); -out: - return error; -} - -asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs __user *buf) -{ - struct kstatfs kbuf; - struct file *file; - int error, i; - - printk("[%s:%d] Wheee.. irix_fstatvfs(%d,%p)\n", - current->comm, current->pid, fd, buf); - - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) - return -EFAULT; - - if (!(file = fget(fd))) { - error = -EBADF; - goto out; - } - error = vfs_statfs(file->f_path.dentry, &kbuf); - if (error) - goto out_f; - - error = __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ -#ifdef __MIPSEB__ - error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); -#else - error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); -#endif - for(i = 0; i < 16; i++) - error |= __put_user(0, &buf->f_basetype[i]); - error |= __put_user(0, &buf->f_flag); - error |= __put_user(kbuf.f_namelen, &buf->f_namemax); - error |= __clear_user(&buf->f_fstr, sizeof(buf->f_fstr)) ? -EFAULT : 0; - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_priocntl(struct pt_regs *regs) -{ - printk("[%s:%d] Wheee.. irix_priocntl()\n", - current->comm, current->pid); - - return -EINVAL; -} - -asmlinkage int irix_sigqueue(int pid, int sig, int code, int val) -{ - printk("[%s:%d] Wheee.. irix_sigqueue(%d,%d,%d,%d)\n", - current->comm, current->pid, pid, sig, code, val); - - return -EINVAL; -} - -asmlinkage int irix_truncate64(char __user *name, int pad, int size1, int size2) -{ - int retval; - - if (size1) { - retval = -EINVAL; - goto out; - } - retval = sys_truncate(name, size2); - -out: - return retval; -} - -asmlinkage int irix_ftruncate64(int fd, int pad, int size1, int size2) -{ - int retval; - - if (size1) { - retval = -EINVAL; - goto out; - } - retval = sys_ftruncate(fd, size2); - -out: - return retval; -} - -asmlinkage int irix_mmap64(struct pt_regs *regs) -{ - int len, prot, flags, fd, off1, off2, error, base = 0; - unsigned long addr, pgoff, *sp; - struct file *file = NULL; - int err; - - if (regs->regs[2] == 1000) - base = 1; - sp = (unsigned long *) (regs->regs[29] + 16); - addr = regs->regs[base + 4]; - len = regs->regs[base + 5]; - prot = regs->regs[base + 6]; - if (!base) { - flags = regs->regs[base + 7]; - if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long)))) - return -EFAULT; - fd = sp[0]; - err = __get_user(off1, &sp[1]); - err |= __get_user(off2, &sp[2]); - } else { - if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long)))) - return -EFAULT; - err = __get_user(flags, &sp[0]); - err |= __get_user(fd, &sp[1]); - err |= __get_user(off1, &sp[2]); - err |= __get_user(off2, &sp[3]); - } - - if (err) - return err; - - if (off1 & PAGE_MASK) - return -EOVERFLOW; - - pgoff = (off1 << (32 - PAGE_SHIFT)) | (off2 >> PAGE_SHIFT); - - if (!(flags & MAP_ANONYMOUS)) { - if (!(file = fget(fd))) - return -EBADF; - - /* Ok, bad taste hack follows, try to think in something else - when reading this */ - if (flags & IRIX_MAP_AUTOGROW) { - unsigned long old_pos; - long max_size = off2 + len; - - if (max_size > file->f_path.dentry->d_inode->i_size) { - old_pos = sys_lseek(fd, max_size - 1, 0); - sys_write(fd, (void __user *) "", 1); - sys_lseek(fd, old_pos, 0); - } - } - } - - flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); - - down_write(¤t->mm->mmap_sem); - error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff); - up_write(¤t->mm->mmap_sem); - - if (file) - fput(file); - - return error; -} - -asmlinkage int irix_dmi(struct pt_regs *regs) -{ - printk("[%s:%d] Wheee.. irix_dmi()\n", - current->comm, current->pid); - - return -EINVAL; -} - -asmlinkage int irix_pread(int fd, char __user *buf, int cnt, int off64, - int off1, int off2) -{ - printk("[%s:%d] Wheee.. irix_pread(%d,%p,%d,%d,%d,%d)\n", - current->comm, current->pid, fd, buf, cnt, off64, off1, off2); - - return -EINVAL; -} - -asmlinkage int irix_pwrite(int fd, char __user *buf, int cnt, int off64, - int off1, int off2) -{ - printk("[%s:%d] Wheee.. irix_pwrite(%d,%p,%d,%d,%d,%d)\n", - current->comm, current->pid, fd, buf, cnt, off64, off1, off2); - - return -EINVAL; -} - -asmlinkage int irix_sgifastpath(int cmd, unsigned long arg0, unsigned long arg1, - unsigned long arg2, unsigned long arg3, - unsigned long arg4, unsigned long arg5) -{ - printk("[%s:%d] Wheee.. irix_fastpath(%d,%08lx,%08lx,%08lx,%08lx," - "%08lx,%08lx)\n", - current->comm, current->pid, cmd, arg0, arg1, arg2, - arg3, arg4, arg5); - - return -EINVAL; -} - -struct irix_statvfs64 { - u32 f_bsize; u32 f_frsize; - u64 f_blocks; u64 f_bfree; u64 f_bavail; - u64 f_files; u64 f_ffree; u64 f_favail; - u32 f_fsid; - char f_basetype[16]; - u32 f_flag; u32 f_namemax; - char f_fstr[32]; - u32 f_filler[16]; -}; - -asmlinkage int irix_statvfs64(char __user *fname, struct irix_statvfs64 __user *buf) -{ - struct nameidata nd; - struct kstatfs kbuf; - int error, i; - - printk("[%s:%d] Wheee.. irix_statvfs64(%s,%p)\n", - current->comm, current->pid, fname, buf); - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs64))) { - error = -EFAULT; - goto out; - } - - error = user_path_walk(fname, &nd); - if (error) - goto out; - error = vfs_statfs(nd.path.dentry, &kbuf); - if (error) - goto dput_and_out; - - error = __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ -#ifdef __MIPSEB__ - error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); -#else - error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); -#endif - for(i = 0; i < 16; i++) - error |= __put_user(0, &buf->f_basetype[i]); - error |= __put_user(0, &buf->f_flag); - error |= __put_user(kbuf.f_namelen, &buf->f_namemax); - for(i = 0; i < 32; i++) - error |= __put_user(0, &buf->f_fstr[i]); - -dput_and_out: - path_put(&nd.path); -out: - return error; -} - -asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs __user *buf) -{ - struct kstatfs kbuf; - struct file *file; - int error, i; - - printk("[%s:%d] Wheee.. irix_fstatvfs64(%d,%p)\n", - current->comm, current->pid, fd, buf); - - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) { - error = -EFAULT; - goto out; - } - if (!(file = fget(fd))) { - error = -EBADF; - goto out; - } - error = vfs_statfs(file->f_path.dentry, &kbuf); - if (error) - goto out_f; - - error = __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ -#ifdef __MIPSEB__ - error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); -#else - error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); -#endif - for(i = 0; i < 16; i++) - error |= __put_user(0, &buf->f_basetype[i]); - error |= __put_user(0, &buf->f_flag); - error |= __put_user(kbuf.f_namelen, &buf->f_namemax); - error |= __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i])) ? -EFAULT : 0; - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_getmountid(char __user *fname, unsigned long __user *midbuf) -{ - int err; - - printk("[%s:%d] irix_getmountid(%s, %p)\n", - current->comm, current->pid, fname, midbuf); - if (!access_ok(VERIFY_WRITE, midbuf, (sizeof(unsigned long) * 4))) - return -EFAULT; - - /* - * The idea with this system call is that when trying to determine - * 'pwd' and it's a toss-up for some reason, userland can use the - * fsid of the filesystem to try and make the right decision, but - * we don't have this so for now. XXX - */ - err = __put_user(0, &midbuf[0]); - err |= __put_user(0, &midbuf[1]); - err |= __put_user(0, &midbuf[2]); - err |= __put_user(0, &midbuf[3]); - - return err; -} - -asmlinkage int irix_nsproc(unsigned long entry, unsigned long mask, - unsigned long arg, unsigned long sp, int slen) -{ - printk("[%s:%d] Wheee.. irix_nsproc(%08lx,%08lx,%08lx,%08lx,%d)\n", - current->comm, current->pid, entry, mask, arg, sp, slen); - - return -EINVAL; -} - -#undef DEBUG_GETDENTS - -struct irix_dirent32 { - u32 d_ino; - u32 d_off; - unsigned short d_reclen; - char d_name[1]; -}; - -struct irix_dirent32_callback { - struct irix_dirent32 __user *current_dir; - struct irix_dirent32 __user *previous; - int count; - int error; -}; - -#define NAME_OFFSET32(de) ((int) ((de)->d_name - (char *) (de))) -#define ROUND_UP32(x) (((x)+sizeof(u32)-1) & ~(sizeof(u32)-1)) - -static int irix_filldir32(void *__buf, const char *name, - int namlen, loff_t offset, u64 ino, unsigned int d_type) -{ - struct irix_dirent32 __user *dirent; - struct irix_dirent32_callback *buf = __buf; - unsigned short reclen = ROUND_UP32(NAME_OFFSET32(dirent) + namlen + 1); - int err = 0; - u32 d_ino; - -#ifdef DEBUG_GETDENTS - printk("\nirix_filldir32[reclen<%d>namlen<%d>count<%d>]", - reclen, namlen, buf->count); -#endif - buf->error = -EINVAL; /* only used if we fail.. */ - if (reclen > buf->count) - return -EINVAL; - d_ino = ino; - if (sizeof(d_ino) < sizeof(ino) && d_ino != ino) - return -EOVERFLOW; - dirent = buf->previous; - if (dirent) - err = __put_user(offset, &dirent->d_off); - dirent = buf->current_dir; - err |= __put_user(dirent, &buf->previous); - err |= __put_user(d_ino, &dirent->d_ino); - err |= __put_user(reclen, &dirent->d_reclen); - err |= copy_to_user((char __user *)dirent->d_name, name, namlen) ? -EFAULT : 0; - err |= __put_user(0, &dirent->d_name[namlen]); - dirent = (struct irix_dirent32 __user *) ((char __user *) dirent + reclen); - - buf->current_dir = dirent; - buf->count -= reclen; - - return err; -} - -asmlinkage int irix_ngetdents(unsigned int fd, void __user * dirent, - unsigned int count, int __user *eob) -{ - struct file *file; - struct irix_dirent32 __user *lastdirent; - struct irix_dirent32_callback buf; - int error; - -#ifdef DEBUG_GETDENTS - printk("[%s:%d] ngetdents(%d, %p, %d, %p) ", current->comm, - current->pid, fd, dirent, count, eob); -#endif - error = -EBADF; - file = fget(fd); - if (!file) - goto out; - - buf.current_dir = (struct irix_dirent32 __user *) dirent; - buf.previous = NULL; - buf.count = count; - buf.error = 0; - - error = vfs_readdir(file, irix_filldir32, &buf); - if (error < 0) - goto out_putf; - - error = buf.error; - lastdirent = buf.previous; - if (lastdirent) { - put_user(file->f_pos, &lastdirent->d_off); - error = count - buf.count; - } - - if (put_user(0, eob) < 0) { - error = -EFAULT; - goto out_putf; - } - -#ifdef DEBUG_GETDENTS - printk("eob=%d returning %d\n", *eob, count - buf.count); -#endif - error = count - buf.count; - -out_putf: - fput(file); -out: - return error; -} - -struct irix_dirent64 { - u64 d_ino; - u64 d_off; - unsigned short d_reclen; - char d_name[1]; -}; - -struct irix_dirent64_callback { - struct irix_dirent64 __user *curr; - struct irix_dirent64 __user *previous; - int count; - int error; -}; - -#define NAME_OFFSET64(de) ((int) ((de)->d_name - (char *) (de))) -#define ROUND_UP64(x) (((x)+sizeof(u64)-1) & ~(sizeof(u64)-1)) - -static int irix_filldir64(void *__buf, const char *name, - int namlen, loff_t offset, u64 ino, unsigned int d_type) -{ - struct irix_dirent64 __user *dirent; - struct irix_dirent64_callback * buf = __buf; - unsigned short reclen = ROUND_UP64(NAME_OFFSET64(dirent) + namlen + 1); - int err = 0; - - if (!access_ok(VERIFY_WRITE, buf, sizeof(*buf))) - return -EFAULT; - - if (__put_user(-EINVAL, &buf->error)) /* only used if we fail.. */ - return -EFAULT; - if (reclen > buf->count) - return -EINVAL; - dirent = buf->previous; - if (dirent) - err = __put_user(offset, &dirent->d_off); - dirent = buf->curr; - buf->previous = dirent; - err |= __put_user(ino, &dirent->d_ino); - err |= __put_user(reclen, &dirent->d_reclen); - err |= __copy_to_user((char __user *)dirent->d_name, name, namlen) - ? -EFAULT : 0; - err |= __put_user(0, &dirent->d_name[namlen]); - - dirent = (struct irix_dirent64 __user *) ((char __user *) dirent + reclen); - - buf->curr = dirent; - buf->count -= reclen; - - return err; -} - -asmlinkage int irix_getdents64(int fd, void __user *dirent, int cnt) -{ - struct file *file; - struct irix_dirent64 __user *lastdirent; - struct irix_dirent64_callback buf; - int error; - -#ifdef DEBUG_GETDENTS - printk("[%s:%d] getdents64(%d, %p, %d) ", current->comm, - current->pid, fd, dirent, cnt); -#endif - error = -EBADF; - if (!(file = fget(fd))) - goto out; - - error = -EFAULT; - if (!access_ok(VERIFY_WRITE, dirent, cnt)) - goto out_f; - - error = -EINVAL; - if (cnt < (sizeof(struct irix_dirent64) + 255)) - goto out_f; - - buf.curr = (struct irix_dirent64 __user *) dirent; - buf.previous = NULL; - buf.count = cnt; - buf.error = 0; - error = vfs_readdir(file, irix_filldir64, &buf); - if (error < 0) - goto out_f; - lastdirent = buf.previous; - if (!lastdirent) { - error = buf.error; - goto out_f; - } - if (put_user(file->f_pos, &lastdirent->d_off)) - return -EFAULT; -#ifdef DEBUG_GETDENTS - printk("returning %d\n", cnt - buf.count); -#endif - error = cnt - buf.count; - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_ngetdents64(int fd, void __user *dirent, int cnt, int *eob) -{ - struct file *file; - struct irix_dirent64 __user *lastdirent; - struct irix_dirent64_callback buf; - int error; - -#ifdef DEBUG_GETDENTS - printk("[%s:%d] ngetdents64(%d, %p, %d) ", current->comm, - current->pid, fd, dirent, cnt); -#endif - error = -EBADF; - if (!(file = fget(fd))) - goto out; - - error = -EFAULT; - if (!access_ok(VERIFY_WRITE, dirent, cnt) || - !access_ok(VERIFY_WRITE, eob, sizeof(*eob))) - goto out_f; - - error = -EINVAL; - if (cnt < (sizeof(struct irix_dirent64) + 255)) - goto out_f; - - *eob = 0; - buf.curr = (struct irix_dirent64 __user *) dirent; - buf.previous = NULL; - buf.count = cnt; - buf.error = 0; - error = vfs_readdir(file, irix_filldir64, &buf); - if (error < 0) - goto out_f; - lastdirent = buf.previous; - if (!lastdirent) { - error = buf.error; - goto out_f; - } - if (put_user(file->f_pos, &lastdirent->d_off)) - return -EFAULT; -#ifdef DEBUG_GETDENTS - printk("eob=%d returning %d\n", *eob, cnt - buf.count); -#endif - error = cnt - buf.count; - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_uadmin(unsigned long op, unsigned long func, unsigned long arg) -{ - int retval; - - switch (op) { - case 1: - /* Reboot */ - printk("[%s:%d] irix_uadmin: Wants to reboot...\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 2: - /* Shutdown */ - printk("[%s:%d] irix_uadmin: Wants to shutdown...\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 4: - /* Remount-root */ - printk("[%s:%d] irix_uadmin: Wants to remount root...\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 8: - /* Kill all tasks. */ - printk("[%s:%d] irix_uadmin: Wants to kill all tasks...\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 256: - /* Set magic mushrooms... */ - printk("[%s:%d] irix_uadmin: Wants to set magic mushroom[%d]...\n", - current->comm, current->pid, (int) func); - retval = -EINVAL; - goto out; - - default: - printk("[%s:%d] irix_uadmin: Unknown operation [%d]...\n", - current->comm, current->pid, (int) op); - retval = -EINVAL; - goto out; - }; - -out: - return retval; -} - -asmlinkage int irix_utssys(char __user *inbuf, int arg, int type, char __user *outbuf) -{ - int retval; - - switch(type) { - case 0: - /* uname() */ - retval = irix_uname((struct iuname __user *)inbuf); - goto out; - - case 2: - /* ustat() */ - printk("[%s:%d] irix_utssys: Wants to do ustat()\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 3: - /* fusers() */ - printk("[%s:%d] irix_utssys: Wants to do fusers()\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - default: - printk("[%s:%d] irix_utssys: Wants to do unknown type[%d]\n", - current->comm, current->pid, (int) type); - retval = -EINVAL; - goto out; - } - -out: - return retval; -} - -#undef DEBUG_FCNTL - -#define IRIX_F_ALLOCSP 10 - -asmlinkage int irix_fcntl(int fd, int cmd, int arg) -{ - int retval; - -#ifdef DEBUG_FCNTL - printk("[%s:%d] irix_fcntl(%d, %d, %d) ", current->comm, - current->pid, fd, cmd, arg); -#endif - if (cmd == IRIX_F_ALLOCSP){ - return 0; - } - retval = sys_fcntl(fd, cmd, arg); -#ifdef DEBUG_FCNTL - printk("%d\n", retval); -#endif - return retval; -} - -asmlinkage int irix_ulimit(int cmd, int arg) -{ - int retval; - - switch(cmd) { - case 1: - printk("[%s:%d] irix_ulimit: Wants to get file size limit.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 2: - printk("[%s:%d] irix_ulimit: Wants to set file size limit.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 3: - printk("[%s:%d] irix_ulimit: Wants to get brk limit.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 4: -#if 0 - printk("[%s:%d] irix_ulimit: Wants to get fd limit.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; -#endif - retval = current->signal->rlim[RLIMIT_NOFILE].rlim_cur; - goto out; - - case 5: - printk("[%s:%d] irix_ulimit: Wants to get txt offset.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - default: - printk("[%s:%d] irix_ulimit: Unknown command [%d].\n", - current->comm, current->pid, cmd); - retval = -EINVAL; - goto out; - } -out: - return retval; -} - -asmlinkage int irix_unimp(struct pt_regs *regs) -{ - printk("irix_unimp [%s:%d] v0=%d v1=%d a0=%08lx a1=%08lx a2=%08lx " - "a3=%08lx\n", current->comm, current->pid, - (int) regs->regs[2], (int) regs->regs[3], - regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); - - return -ENOSYS; -} diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h deleted file mode 100644 index cc88aed23f0f..000000000000 --- a/include/asm-mips/inventory.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Miguel de Icaza - */ -#ifndef __ASM_INVENTORY_H -#define __ASM_INVENTORY_H - -#include - -typedef struct inventory_s { - struct inventory_s *inv_next; - int inv_class; - int inv_type; - int inv_controller; - int inv_unit; - int inv_state; -} inventory_t; - -extern int inventory_items; - -extern void add_to_inventory(int class, int type, int controller, int unit, int state); -extern int dump_inventory_to_user(void __user *userbuf, int size); -extern int __init init_inventory(void); - -#endif /* __ASM_INVENTORY_H */ diff --git a/include/asm-mips/namei.h b/include/asm-mips/namei.h index c94d12d1f868..a6605a752469 100644 --- a/include/asm-mips/namei.h +++ b/include/asm-mips/namei.h @@ -1,26 +1,11 @@ #ifndef _ASM_NAMEI_H #define _ASM_NAMEI_H -#include -#include +/* + * This dummy routine maybe changed to something useful + * for /usr/gnemul/ emulation stuff. + */ -#define IRIX_EMUL "/usr/gnemul/irix/" -#define RISCOS_EMUL "/usr/gnemul/riscos/" - -static inline char *__emul_prefix(void) -{ - switch (current->personality) { - case PER_IRIX32: - case PER_IRIXN32: - case PER_IRIX64: - return IRIX_EMUL; - - case PER_RISCOS: - return RISCOS_EMUL; - - default: - return NULL; - } -} +#define __emul_prefix() NULL #endif /* _ASM_NAMEI_H */ diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h deleted file mode 100644 index 8121a9a75bfd..000000000000 --- a/include/asm-mips/prctl.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * IRIX prctl interface - * - * The IRIX kernel maps a page at PRDA_ADDRESS with the - * contents of prda and fills it the bits on prda_sys. - */ - -#ifndef __PRCTL_H__ -#define __PRCTL_H__ - -#define PRDA_ADDRESS 0x200000L -#define PRDA ((struct prda *) PRDA_ADDRESS) - -struct prda_sys { - pid_t t_pid; - u32 t_hint; - u32 t_dlactseq; - u32 t_fpflags; - u32 t_prid; /* processor type, $prid CP0 register */ - u32 t_dlendseq; - u64 t_unused1[5]; - pid_t t_rpid; - s32 t_resched; - u32 t_unused[8]; - u32 t_cpu; /* current/last cpu */ - - /* FIXME: The signal information, not supported by Linux now */ - u32 t_flags; /* if true, then the sigprocmask is in userspace */ - u32 t_sigprocmask [1]; /* the sigprocmask */ -}; - -struct prda { - char fill [0xe00]; - struct prda_sys prda_sys; -}; - -#define t_sys prda_sys - -ptrdiff_t prctl(int op, int v1, int v2); - -#endif diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h index 7a28989f7ee3..bee5153aca48 100644 --- a/include/asm-mips/signal.h +++ b/include/asm-mips/signal.h @@ -119,9 +119,6 @@ struct sigaction { struct k_sigaction { struct sigaction sa; -#ifdef CONFIG_BINFMT_IRIX - void (*sa_restorer)(void); -#endif }; /* IRIX compatible stack_t */ -- cgit v1.2.3 From 043ebd6c9de7500a399017643bbc5cafd4e37060 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Fri, 13 Jun 2008 00:25:36 +0100 Subject: [MIPS] DECstation: Document more MB ASIC register bits Document a few more register bits provided by the MB ASIC used on R4000SC (KN04) and R4400SC (KN05) CPU daughtercards with the DECstation. Reverse-engineered and not documented anywhere else to the best of my knowledge. Bit names appended to the last underscore the same as reported by the firmware in register dumps. Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle --- include/asm-mips/dec/kn05.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h index 15fe8f881e60..56d22dc8803a 100644 --- a/include/asm-mips/dec/kn05.h +++ b/include/asm-mips/dec/kn05.h @@ -6,7 +6,7 @@ * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC * definitions. * - * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -54,11 +54,11 @@ */ #define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ #define KN4K_MB_INT_RTC (1<<1) /* RTC? */ -#define KN4K_MB_INT_MT (1<<3) /* ??? */ +#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */ /* * Bits for the MB control & status register. - * Set to 0x00bf8001 on my system by the ROM. + * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware. */ #define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ #define KN4K_MB_CSR_F (1<<1) /* ??? */ @@ -69,7 +69,8 @@ #define KN4K_MB_CSR_IM (1<<13) /* ??? */ #define KN4K_MB_CSR_NC (1<<14) /* ??? */ #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ -#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */ +#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ #define KN4K_MB_CSR_FW (1<<21) /* ??? */ +#define KN4K_MB_CSR_W (1<<31) /* ??? */ #endif /* __ASM_MIPS_DEC_KN05_H */ -- cgit v1.2.3 From 94daeb90698c56a85ed219eeb18d4a8cddde7b03 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 11 Jun 2008 10:04:25 -0700 Subject: [MIPS] Fix asm constraints for 'ins' instructions. The third operand to 'ins' must be a constant int, not a register. [Ralf: The bug was actually intensional. Some versions used to throw an error under certain circumstances for code like: static inline void f(unsigned nr, unsigned *p) { unsigned short bit = nr & 5; if (__builtin_constant_p(bit)) { __asm__ __volatile__ (" foo %0, %1" : "=m" (*p) : "i" (bit)); } else { /* Do something else. */ } } because gcc was not able to figure out that the "i" constraint was possibly at the early stage when the constraint are getting verified. The solution was using "ri" instead of "i". The "ri" would keep gcc happy but in the end for code generation always the "i" constraint would be satisfied. The problem afair originally appeared in the i386 io.h and also hit it's mips equivalent. From there the workaround spread to many of the inline assembler functions.] Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 642724734eba..9a7274ba6a0b 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m), "r" (~0)); + : "i" (bit), "m" (*m), "r" (~0)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( @@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m)); + : "i" (bit), "m" (*m)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( @@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr, "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m), "=&r" (res) - : "ri" (bit), "m" (*m) + : "i" (bit), "m" (*m) : "memory"); #endif } else if (cpu_has_llsc) { -- cgit v1.2.3 From 7a2852e49fe2d19296812c0f0f833b0ee3043bbb Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Tue, 18 Mar 2008 22:47:56 +0100 Subject: [MIPS] IP28: switch to "normal" mode after PROM no longer needed SGI-IP28 is running in so called slow mode, when kernel is started from the PROM. PROM calls must be done in slow mode otherwise the PROM will issue an error. To get better memory performance we now switch to normal mode, when the PROM is no longer needed. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/sgi-ip22/ip22-mc.c | 26 ++++++++++++++++++++++++++ include/asm-mips/barrier.h | 14 ++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'include') diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c index 3f35d6367bec..5268ac187bbd 100644 --- a/arch/mips/sgi-ip22/ip22-mc.c +++ b/arch/mips/sgi-ip22/ip22-mc.c @@ -208,4 +208,30 @@ void __init sgimc_init(void) void __init prom_meminit(void) {} void __init prom_free_prom_memory(void) { +#ifdef CONFIG_SGI_IP28 + u32 mconfig1; + unsigned long flags; + spinlock_t lock; + + /* + * because ARCS accesses memory uncached we wait until ARCS + * isn't needed any longer, before we switch from slow to + * normal mode + */ + spin_lock_irqsave(&lock, flags); + mconfig1 = sgimc->mconfig1; + /* map ECC register */ + sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060; + iob(); + /* switch to normal mode */ + *(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0; + iob(); + /* reduce WR_COL */ + sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4; + iob(); + /* restore old config */ + sgimc->mconfig1 = mconfig1; + iob(); + spin_unlock_irqrestore(&lock, flags); +#endif } diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h index 9d8cfbb5e796..8e9ac313ca3b 100644 --- a/include/asm-mips/barrier.h +++ b/include/asm-mips/barrier.h @@ -92,11 +92,25 @@ #define fast_wmb() __sync() #define fast_rmb() __sync() #define fast_mb() __sync() +#ifdef CONFIG_SGI_IP28 +#define fast_iob() \ + __asm__ __volatile__( \ + ".set push\n\t" \ + ".set noreorder\n\t" \ + "lw $0,%0\n\t" \ + "sync\n\t" \ + "lw $0,%0\n\t" \ + ".set pop" \ + : /* no output */ \ + : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \ + : "memory") +#else #define fast_iob() \ do { \ __sync(); \ __fast_iob(); \ } while (0) +#endif #ifdef CONFIG_CPU_HAS_WB -- cgit v1.2.3 From af3e69cfc9644c742a22647a5091779b9dfb9653 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 4 Jul 2008 00:59:40 +0900 Subject: [MIPS] Declare some pci variables in header file Declare pci_probe_only, etc. in asm-mips/pci.h file. This will fix some sparse warnings. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/pci/fixup-vr4133.c | 1 - arch/mips/pci/pci-bcm1480.c | 1 - arch/mips/pci/pci-ip27.c | 1 - arch/mips/pci/pci-sb1250.c | 1 - include/asm-mips/pci.h | 3 +++ 5 files changed, 3 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c index de5e5f6bbf4c..34e651bd2b5e 100644 --- a/arch/mips/pci/fixup-vr4133.c +++ b/arch/mips/pci/fixup-vr4133.c @@ -171,7 +171,6 @@ void i8259_init(void) int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - extern int pci_probe_only; pci_probe_only = 1; #ifdef CONFIG_ROCKHOPPER diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index d19d262157f2..a9060c771840 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -202,7 +202,6 @@ static int __init bcm1480_pcibios_init(void) { uint32_t cmdreg; uint64_t reg; - extern int pci_probe_only; /* CFE will assign PCI resources */ pci_probe_only = 1; diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index a18516925cdd..ce92f82b16d2 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -47,7 +47,6 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) static int num_bridges = 0; bridge_t *bridge; int slot; - extern int pci_probe_only; pci_probe_only = 1; diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 9bc102a1380e..bf639590b8b2 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -210,7 +210,6 @@ static int __init sb1250_pcibios_init(void) void __iomem *io_map_base; uint32_t cmdreg; uint64_t reg; - extern int pci_probe_only; /* CFE will assign PCI resources */ pci_probe_only = 1; diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 301ff2f28012..d3be83436070 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -172,4 +172,7 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) return channel ? 15 : 14; } +extern int pci_probe_only; +extern unsigned int pcibios_max_latency; + #endif /* _ASM_PCI_H */ -- cgit v1.2.3 From b29eee4935d9e5952a7ea8543ea499f06fb86808 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Wed, 16 Apr 2008 02:00:45 +0900 Subject: [MIPS] rbtx4927: misc cleanups * Merge tx4927_pci.h into tx4927.h * Kill (broken) external PCI clock frequency reporting * Kill unnecessary wbflush() * Kill unnecessary includes * Kill debug garbages Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/pci/fixup-rbtx4927.c | 1 - arch/mips/pci/ops-tx4927.c | 5 +- arch/mips/tx4927/common/tx4927_dbgio.c | 5 +- arch/mips/tx4927/common/tx4927_prom.c | 8 +- .../tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 234 +-------------- .../toshiba_rbtx4927/toshiba_rbtx4927_prom.c | 7 +- .../toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 322 +-------------------- include/asm-mips/tx4927/toshiba_rbtx4927.h | 4 - include/asm-mips/tx4927/tx4927.h | 240 ++++++++++++++- include/asm-mips/tx4927/tx4927_pci.h | 268 ----------------- 10 files changed, 266 insertions(+), 828 deletions(-) delete mode 100644 include/asm-mips/tx4927/tx4927_pci.h (limited to 'include') diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 7450c335b387..2d234ca017db 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -38,7 +38,6 @@ #include #include -#include #undef DEBUG #ifdef DEBUG diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 150419c8b414..1bbafeb4a774 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -40,10 +40,7 @@ #include #include #include - -#include -#include -#include +#include /* initialize in setup */ struct resource pci_io_resource = { diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c index d8423e001b2d..ea1ff23f4b72 100644 --- a/arch/mips/tx4927/common/tx4927_dbgio.c +++ b/arch/mips/tx4927/common/tx4927_dbgio.c @@ -28,9 +28,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include -#include +#include u8 getDebugChar(void) { @@ -38,7 +36,6 @@ u8 getDebugChar(void) return (txx9_sio_kdbg_rd()); } - int putDebugChar(u8 byte) { extern int txx9_sio_kdbg_wr( u8 ch ); diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c index 6eed53d8f386..cc2aa9d63e82 100644 --- a/arch/mips/tx4927/common/tx4927_prom.c +++ b/arch/mips/tx4927/common/tx4927_prom.c @@ -30,12 +30,8 @@ */ #include -#include -#include -#include - -#include -#include +#include +#include #include static unsigned int __init tx4927_process_sdccr(unsigned long addr) diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 6d31f2a98abf..c18901a75cc4 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -28,8 +28,6 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ - - /* IRQ Device 00 RBTX4927-ISA/00 @@ -112,76 +110,14 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB */ #include -#include #include -#include -#include -#include -#include #include -#include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include #ifdef CONFIG_TOSHIBA_FPCIB0 #include -#include #endif #include - -#undef TOSHIBA_RBTX4927_IRQ_DEBUG - -#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG -#define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000 - -#define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 ) -#define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 ) -#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 ) - -#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) -#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) -#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) - -#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff -#endif - - -#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG -static const u32 toshiba_rbtx4927_irq_debug_flag = - (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | - TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR -// | TOSHIBA_RBTX4927_IRQ_IOC_INIT -// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE - ); -#endif - - -#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG -#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \ - if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \ - { \ - char tmp[100]; \ - sprintf( tmp, str ); \ - printk( "%s(%s:%u)::%s", __func__, __FILE__, __LINE__, tmp ); \ - } -#else -#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag, str...) -#endif - - - - #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 @@ -207,39 +143,22 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { #define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL #define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL - -u32 bit2num(u32 num) -{ - u32 i; - - for (i = 0; i < (sizeof(num) * 8); i++) { - if (num & (1 << i)) { - return (i); - } - } - return (0); -} - int toshiba_rbtx4927_irq_nested(int sw_irq) { - u32 level3; + u8 level3; level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; if (level3) { - sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); - if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { - goto RETURN; - } - } + sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; #ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) { - int irq = i8259_irq(); - if (irq >= 0) - sw_irq = irq; - } + if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && + tx4927_using_backplane) { + int irq = i8259_irq(); + if (irq >= 0) + sw_irq = irq; + } #endif - - RETURN: + } return (sw_irq); } @@ -250,21 +169,10 @@ static struct irqaction toshiba_rbtx4927_irq_ioc_action = { .name = TOSHIBA_RBTX4927_IOC_NAME }; - -/**********************************************************************************/ -/* Functions for ioc */ -/**********************************************************************************/ - - static void __init toshiba_rbtx4927_irq_ioc_init(void) { int i; - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT, - "beg=%d end=%d\n", - TOSHIBA_RBTX4927_IRQ_IOC_BEG, - TOSHIBA_RBTX4927_IRQ_IOC_END); - for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, @@ -276,37 +184,16 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void) static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) { - volatile unsigned char v; - - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG - || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } + unsigned char v; v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); } - static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) { - volatile unsigned char v; - - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG - || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } + unsigned char v; v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); @@ -314,7 +201,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) mmiowb(); } - void __init arch_init_irq(void) { extern void tx4927_irq_init(void); @@ -327,102 +213,4 @@ void __init arch_init_irq(void) #endif /* Onboard 10M Ether: High Active */ set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); - - wbflush(); -} - -void toshiba_rbtx4927_irq_dump(char *key) -{ -#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG - { - u32 i, j = 0; - for (i = 0; i < NR_IRQS; i++) { - if (strcmp(irq_desc[i].chip->name, "none") - == 0) - continue; - - if ((i >= 1) - && (irq_desc[i - 1].chip->name == - irq_desc[i].chip->name)) { - j++; - } else { - j = 0; - } - TOSHIBA_RBTX4927_IRQ_DPRINTK - (TOSHIBA_RBTX4927_IRQ_INFO, - "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n", - key, i, i, irq_desc[i].status, - (u32) irq_desc[i].chip, - (u32) irq_desc[i].action, - (u32) (irq_desc[i].action ? irq_desc[i]. - action->handler : 0), - irq_desc[i].depth, - irq_desc[i].chip->name, j); - } - } -#endif -} - -void toshiba_rbtx4927_irq_dump_pics(char *s) -{ - u32 level0_m; - u32 level0_s; - u32 level1_m; - u32 level1_s; - u32 level2; - u32 level2_p; - u32 level2_s; - u32 level3_m; - u32 level3_s; - u32 level4_m; - u32 level4_s; - u32 level5_m; - u32 level5_s; - - if (s == NULL) - s = "null"; - - level0_m = (read_c0_status() & 0x0000ff00) >> 8; - level0_s = (read_c0_cause() & 0x0000ff00) >> 8; - - level1_m = level0_m; - level1_s = level0_s & 0x87; - - level2 = __raw_readl((void __iomem *)0xff1ff6a0UL); - level2_p = (((level2 & 0x10000)) ? 0 : 1); - level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); - - level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; - level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; - - level4_m = inb(0x21); - outb(0x0A, 0x20); - level4_s = inb(0x20); - - level5_m = inb(0xa1); - outb(0x0A, 0xa0); - level5_s = inb(0xa0); - - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "dump_raw_pic() "); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "cp0:m=0x%02x/s=0x%02x ", level0_m, - level0_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "cp0:m=0x%02x/s=0x%02x ", level1_m, - level1_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "pic:e=0x%02x/s=0x%02x ", level2_p, - level2_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "ioc:m=0x%02x/s=0x%02x ", level3_m, - level3_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "sbm:m=0x%02x/s=0x%02x ", level4_m, - level4_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "sbs:m=0x%02x/s=0x%02x ", level5_m, - level5_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", - s); } diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c index f3f86857beae..fdbad4bc6021 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c @@ -30,13 +30,10 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include -#include -#include - -#include +#include #include #include +#include #include void __init prom_init_cmdline(void) diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 2203c77b2ce2..185f303c0e2a 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -62,43 +62,10 @@ #include #endif #include -#ifdef CONFIG_PCI -#include -#endif #ifdef CONFIG_SERIAL_TXX9 #include #endif -#undef TOSHIBA_RBTX4927_SETUP_DEBUG - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG -#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 ) -#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 ) -#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 ) -#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 ) - -#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff -#endif - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG -static const u32 toshiba_rbtx4927_setup_debug_flag = - (TOSHIBA_RBTX4927_SETUP_SETUP | - | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 | - TOSHIBA_RBTX4927_SETUP_PCI2); -#endif - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG -#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \ - if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \ - { \ - char tmp[100]; \ - sprintf( tmp, str ); \ - printk( "%s(%s:%u)::%s", __func__, __FILE__, __LINE__, tmp ); \ - } -#else -#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...) -#endif - /* These functions are used for rebooting or halting the machine*/ extern void toshiba_rbtx4927_restart(char *command); extern void toshiba_rbtx4927_halt(void); @@ -124,7 +91,6 @@ unsigned long mips_memory_upper; static int tx4927_ccfg_toeon = 1; static int tx4927_pcic_trdyto = 0; /* default: disabled */ unsigned long tx4927_ce_base[8]; -void tx4927_reset_pci_pcic(void); int tx4927_pci66 = 0; /* 0:auto */ #endif @@ -172,9 +138,6 @@ static int __init tx4927_pcibios_init(void) int busno = 0; /* One bus on the Toshiba */ struct pci_controller *hose = &tx4927_controller; - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, - "-\n"); - for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { early_read_config_dword(hose, busno, busno, pci_devfn, PCI_VENDOR_ID, &id); @@ -187,13 +150,6 @@ static int __init tx4927_pcibios_init(void) u8 v08_64; u32 v32_b0; u8 v08_e1; -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG - char *s = " sb/isa --"; -#endif - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", - s); early_read_config_byte(hose, busno, busno, pci_devfn, 0x64, &v08_64); @@ -202,16 +158,6 @@ static int __init tx4927_pcibios_init(void) early_read_config_byte(hose, busno, busno, pci_devfn, 0xe1, &v08_e1); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x64 = 0x%02x\n", s, v08_64); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0xb0 = 0x%02x\n", s, v32_b0); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0xe1 = 0x%02x\n", s, v08_e1); - /* serial irq control */ v08_64 = 0xd0; @@ -222,50 +168,12 @@ static int __init tx4927_pcibios_init(void) v08_e1 &= 0xf0; v08_e1 |= 0x0d; - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x64 = 0x%02x\n", s, v08_64); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0xb0 = 0x%02x\n", s, v32_b0); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0xe1 = 0x%02x\n", s, v08_e1); - early_write_config_byte(hose, busno, busno, pci_devfn, 0x64, v08_64); early_write_config_dword(hose, busno, busno, pci_devfn, 0xb0, v32_b0); early_write_config_byte(hose, busno, busno, pci_devfn, 0xe1, v08_e1); - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG - { - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x64, - &v08_64); - early_read_config_dword(hose, busno, busno, - pci_devfn, 0xb0, - &v32_b0); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0xe1, - &v08_e1); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x64 = 0x%02x\n", s, v08_64); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0xb0 = 0x%02x\n", s, v32_b0); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0xe1 = 0x%02x\n", s, v08_e1); - } -#endif - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", - s); } if (id == 0x91301055) { @@ -274,13 +182,6 @@ static int __init tx4927_pcibios_init(void) u8 v08_41; u8 v08_43; u8 v08_5c; -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG - char *s = " sb/ide --"; -#endif - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", - s); early_read_config_byte(hose, busno, busno, pci_devfn, 0x04, &v08_04); @@ -293,22 +194,6 @@ static int __init tx4927_pcibios_init(void) early_read_config_byte(hose, busno, busno, pci_devfn, 0x5c, &v08_5c); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x04 = 0x%02x\n", s, v08_04); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x09 = 0x%02x\n", s, v08_09); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x41 = 0x%02x\n", s, v08_41); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x43 = 0x%02x\n", s, v08_43); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x5c = 0x%02x\n", s, v08_5c); - /* enable ide master/io */ v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); @@ -332,22 +217,6 @@ static int __init tx4927_pcibios_init(void) */ v08_5c |= 0x01; - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x04 = 0x%02x\n", s, v08_04); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x09 = 0x%02x\n", s, v08_09); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x41 = 0x%02x\n", s, v08_41); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x43 = 0x%02x\n", s, v08_43); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x5c = 0x%02x\n", s, v08_5c); - early_write_config_byte(hose, busno, busno, pci_devfn, 0x5c, v08_5c); early_write_config_byte(hose, busno, busno, @@ -358,54 +227,11 @@ static int __init tx4927_pcibios_init(void) pci_devfn, 0x41, v08_41); early_write_config_byte(hose, busno, busno, pci_devfn, 0x43, v08_43); - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG - { - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x04, - &v08_04); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x09, - &v08_09); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x41, - &v08_41); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x43, - &v08_43); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x5c, - &v08_5c); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x04 = 0x%02x\n", s, v08_04); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x09 = 0x%02x\n", s, v08_09); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x41 = 0x%02x\n", s, v08_41); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x43 = 0x%02x\n", s, v08_43); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x5c = 0x%02x\n", s, v08_5c); - } -#endif - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", - s); } } register_pci_controller(&tx4927_controller); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, - "+\n"); - return 0; } @@ -419,45 +245,13 @@ void __init tx4927_pci_setup(void) static int called = 0; extern unsigned int tx4927_get_mem_size(void); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n"); - mips_memory_upper = tx4927_get_mem_size() << 20; mips_memory_upper += KSEG0; - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_memory_upper\n", - mips_memory_upper); mips_pci_io_base = TX4927_PCIIO; mips_pci_io_size = TX4927_PCIIO_SIZE; mips_pci_mem_base = TX4927_PCIMEM; mips_pci_mem_size = TX4927_PCIMEM_SIZE; - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_pci_io_base\n", - mips_pci_io_base); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_pci_io_size\n", - mips_pci_io_size); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_pci_mem_base\n", - mips_pci_mem_base); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_pci_mem_size\n", - mips_pci_mem_size); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=pci_io_resource.start\n", - pci_io_resource.start); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=pci_io_resource.end\n", - pci_io_resource.end); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=pci_mem_resource.start\n", - pci_mem_resource.start); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=pci_mem_resource.end\n", - pci_mem_resource.end); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_io_port_base", - mips_io_port_base); if (!called) { printk ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", @@ -521,29 +315,10 @@ void __init tx4927_pci_setup(void) } printk("Internal(%dMHz)", pciclk / 1000000); - } else { - int pciclk = 0; - int pciclk_setting = *tx4927_pci_clk_ptr; - switch (pciclk_setting & TX4927_PCI_CLK_MASK) { - case TX4927_PCI_CLK_33: - pciclk = 33333333; - break; - case TX4927_PCI_CLK_25: - pciclk = 25000000; - break; - case TX4927_PCI_CLK_66: - pciclk = 66666666; - break; - case TX4927_PCI_CLK_50: - pciclk = 50000000; - break; - } - printk("External(%dMHz)", pciclk / 1000000); - } + } else + printk("External"); printk("\n"); - - /* GB->PCI mappings */ tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; tx4927_pcicptr->g2piogbase = mips_pci_io_base | @@ -644,12 +419,7 @@ void __init tx4927_pci_setup(void) tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - ":pci setup complete:\n"); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n"); } - #endif /* CONFIG_PCI */ static void __noreturn wait_forever(void) @@ -679,7 +449,6 @@ void toshiba_rbtx4927_restart(char *command) /* no return */ } - void toshiba_rbtx4927_halt(void) { printk(KERN_NOTICE "System Halted\n"); @@ -702,33 +471,19 @@ void __init plat_mem_setup(void) printk("CPU is %s\n", toshiba_name); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - "-\n"); - /* f/w leaves this on at startup */ - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":Clearing STO_ERL.\n"); clear_c0_status(ST0_ERL); /* enable caches -- HCP5 does this, pmon does not */ - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n"); cp0_config = read_c0_config(); cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); write_c0_config(cp0_config); set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":mips_io_port_base=0x%08lx\n", - mips_io_port_base); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":Resource\n"); ioport_resource.end = 0xffffffff; iomem_resource.end = 0xffffffff; - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":ResetRoutines\n"); _machine_restart = toshiba_rbtx4927_restart; _machine_halt = toshiba_rbtx4927_halt; pm_power_off = toshiba_rbtx4927_power_off; @@ -761,23 +516,6 @@ void __init plat_mem_setup(void) * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) * */ - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, - "ccfg is %lx, PCIDIVMODE is %x\n", - (unsigned long) tx4927_ccfgptr->ccfg, - (unsigned long) tx4927_ccfgptr->ccfg & - (mips_machtype == MACH_TOSHIBA_RBTX4937 ? - TX4937_CCFG_PCIDIVMODE_MASK : - TX4927_CCFG_PCIDIVMODE_MASK)); - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, - "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n", - (unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCI66, - (unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIMIDE, - (unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIXARB); - if (mips_machtype == MACH_TOSHIBA_RBTX4937) switch ((unsigned long)tx4927_ccfgptr-> ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { @@ -818,49 +556,18 @@ void __init plat_mem_setup(void) /* this is on ISA bus behind PCI bus, so need PCI up first */ #ifdef CONFIG_TOSHIBA_FPCIB0 - { - if (tx4927_using_backplane) { - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":fpcibo=yes\n"); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_init()\n"); - smsc_fdc37m81x_init(0x3f0); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_config_beg()\n"); - smsc_fdc37m81x_config_beg(); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_config_set(KBD)\n"); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, - SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, - 1); - - smsc_fdc37m81x_config_end(); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_config_end()\n"); - } else { - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":fpcibo=not_found\n"); - } - } -#else - { - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n"); + if (tx4927_using_backplane) { + smsc_fdc37m81x_init(0x3f0); + smsc_fdc37m81x_config_beg(); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + smsc_fdc37m81x_config_end(); } #endif - #endif /* CONFIG_PCI */ #ifdef CONFIG_SERIAL_TXX9 @@ -894,17 +601,12 @@ void __init plat_mem_setup(void) } #endif - #ifdef CONFIG_IP_PNP argptr = prom_getcmdline(); if (strstr(argptr, "ip=") == NULL) { strcat(argptr, " ip=any"); } #endif - - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - "+\n"); } void __init plat_time_init(void) diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h index b188a659ce02..d6b32acd6b7b 100644 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h @@ -28,9 +28,6 @@ #define __ASM_TX4927_TOSHIBA_RBTX4927_H #include -#ifdef CONFIG_PCI -#include -#endif #ifdef CONFIG_PCI #define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO @@ -44,7 +41,6 @@ #define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL #define RBTX4927_SW_RESET_ENABLE_SET 0x01 - #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) #define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 193e80a17c12..1d4816f3266f 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -36,11 +36,245 @@ #define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) -#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) -#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) +#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) +#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) #define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) -#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) +#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) #define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) +#define TX4927_CCFG_TOE 0x00004000 +#define TX4927_CCFG_WR 0x00008000 +#define TX4927_CCFG_TINTDIS 0x01000000 + +#define TX4927_PCIMEM 0x08000000 +#define TX4927_PCIMEM_SIZE 0x08000000 +#define TX4927_PCIIO 0x16000000 +#define TX4927_PCIIO_SIZE 0x01000000 + +#define TX4927_SDRAMC_REG 0xff1f8000 +#define TX4927_EBUSC_REG 0xff1f9000 +#define TX4927_PCIC_REG 0xff1fd000 +#define TX4927_CCFG_REG 0xff1fe000 +#define TX4927_IRC_REG 0xff1ff600 +#define TX4927_NR_TMR 3 +#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) + +/* bits for ISTAT3/IMASK3/IMSTAT3 */ +#define TX4927_INT3B_PCID 0 +#define TX4927_INT3B_PCIC 1 +#define TX4927_INT3B_PCIB 2 +#define TX4927_INT3B_PCIA 3 +#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) +#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) +#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) +#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) + +#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG +#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ + +#define TX4927_IR_PCIC 16 +#define TX4927_IR_PCIERR 22 +#define TX4927_IR_PCIPMA 23 +#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) +#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) +#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) +#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) +#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) +#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) +#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) + +#ifdef _LANGUAGE_ASSEMBLY +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include + +struct tx4927_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; +}; + +struct tx4927_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4927_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; +}; + +struct tx4927_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmcut; + volatile unsigned long long pdmcnt; /* +220 */ + volatile unsigned long long pdmsts; + volatile unsigned long long unused8[2]; + volatile unsigned long long pdmdb[4]; /* +240 */ + volatile unsigned long long pdmtdh; /* +260 */ + volatile unsigned long long pdmdms; +}; + +#endif /* _LANGUAGE_ASSEMBLY */ + +/* + * PCIC + */ + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4927_PCIC_PBACFG_RPBA 0x00000004 +#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc + +/* bits for PCICCFG */ +#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 +#define TX4927_PCIC_PCICCFG_HRST 0x00000800 +#define TX4927_PCIC_PCICCFG_SRST 0x00000400 +#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 +#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 +#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 +#define TX4927_PCIC_PCICCFG_IISE 0x00000020 +#define TX4927_PCIC_PCICCFG_ATR 0x00000010 +#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4927_CCFG_PCI66 0x00800000 +#define TX4927_CCFG_PCIMIDE 0x00400000 +#define TX4927_CCFG_PCIXARB 0x00002000 +#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 +#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 +#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 +#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 +#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 + +#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 +#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 +#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 +#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 +#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 +#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 +#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 +#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 + +/* PCFG : Pin Configuration */ +#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) + +/* CLKCTR : Clock Control */ +#define TX4927_CLKCTR_PCICKD 0x00400000 +#define TX4927_CLKCTR_PCIRST 0x00000040 + +#ifndef _LANGUAGE_ASSEMBLY + +#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) +#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) +#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) +#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) + +#endif /* _LANGUAGE_ASSEMBLY */ + #endif /* __ASM_TX4927_TX4927_H */ diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h deleted file mode 100644 index 0be77df70f2b..000000000000 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - */ -#ifndef __ASM_TX4927_TX4927_PCI_H -#define __ASM_TX4927_TX4927_PCI_H - -#define TX4927_CCFG_TOE 0x00004000 -#define TX4927_CCFG_WR 0x00008000 -#define TX4927_CCFG_TINTDIS 0x01000000 - -#define TX4927_PCIMEM 0x08000000 -#define TX4927_PCIMEM_SIZE 0x08000000 -#define TX4927_PCIIO 0x16000000 -#define TX4927_PCIIO_SIZE 0x01000000 - -#define TX4927_SDRAMC_REG 0xff1f8000 -#define TX4927_EBUSC_REG 0xff1f9000 -#define TX4927_PCIC_REG 0xff1fd000 -#define TX4927_CCFG_REG 0xff1fe000 -#define TX4927_IRC_REG 0xff1ff600 -#define TX4927_NR_TMR 3 -#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) -#define TX4927_CE3 0x17f00000 /* 1M */ -#define TX4927_PCIRESET_ADDR 0xbc00f006 -#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020) - -#define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n)) -#define tx4927_imstat_ptr(n) \ - ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n)) - -/* bits for ISTAT3/IMASK3/IMSTAT3 */ -#define TX4927_INT3B_PCID 0 -#define TX4927_INT3B_PCIC 1 -#define TX4927_INT3B_PCIB 2 -#define TX4927_INT3B_PCIA 3 -#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) -#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) -#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) -#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) - -/* bits for PCI_CLK (S6) */ -#define TX4927_PCI_CLK_HOST 0x80 -#define TX4927_PCI_CLK_MASK (0x0f << 3) -#define TX4927_PCI_CLK_33 (0x01 << 3) -#define TX4927_PCI_CLK_25 (0x04 << 3) -#define TX4927_PCI_CLK_66 (0x09 << 3) -#define TX4927_PCI_CLK_50 (0x0c << 3) -#define TX4927_PCI_CLK_ACK 0x04 -#define TX4927_PCI_CLK_ACE 0x02 -#define TX4927_PCI_CLK_ENDIAN 0x01 -#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG -#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ - -#define TX4927_IR_PCIC 16 -#define TX4927_IR_PCIERR 22 -#define TX4927_IR_PCIPMA 23 -#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) -#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) -#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) -#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) -#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) -#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) -#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) - -#ifdef _LANGUAGE_ASSEMBLY -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include - -#define tx4927_pcireset_ptr \ - ((volatile unsigned char *)TX4927_PCIRESET_ADDR) -#define tx4927_pci_clk_ptr \ - ((volatile unsigned char *)TX4927_PCI_CLK_ADDR) - -struct tx4927_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; -}; - -struct tx4927_ebusc_reg { - volatile unsigned long long cr[8]; -}; - -struct tx4927_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; -}; - -struct tx4927_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmcut; - volatile unsigned long long pdmcnt; /* +220 */ - volatile unsigned long long pdmsts; - volatile unsigned long long unused8[2]; - volatile unsigned long long pdmdb[4]; /* +240 */ - volatile unsigned long long pdmtdh; /* +260 */ - volatile unsigned long long pdmdms; -}; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* - * PCIC - */ - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4927_PCIC_PBACFG_RPBA 0x00000004 -#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc - -/* bits for PCICCFG */ -#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 -#define TX4927_PCIC_PCICCFG_HRST 0x00000800 -#define TX4927_PCIC_PCICCFG_SRST 0x00000400 -#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 -#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 -#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 -#define TX4927_PCIC_PCICCFG_IISE 0x00000020 -#define TX4927_PCIC_PCICCFG_ATR 0x00000010 -#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4927_CCFG_PCI66 0x00800000 -#define TX4927_CCFG_PCIMIDE 0x00400000 -#define TX4927_CCFG_PCIXARB 0x00002000 -#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 -#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 -#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 -#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 -#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 - -#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 -#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 -#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 -#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 -#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 -#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 -#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 -#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 - -/* PCFG : Pin Configuration */ -#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) - -/* CLKCTR : Clock Control */ -#define TX4927_CLKCTR_PCICKD 0x00400000 -#define TX4927_CLKCTR_PCIRST 0x00000040 - - -#ifndef _LANGUAGE_ASSEMBLY - -#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) -#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) -#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) -#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) - -#endif /* _LANGUAGE_ASSEMBLY */ - -#endif /* __ASM_TX4927_TX4927_PCI_H */ -- cgit v1.2.3 From 2157bc68711bf0e69f9aca4d310bd863298fbb3f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 15 Jul 2008 18:44:33 +0100 Subject: [MIPS] Atlas: Remove support code. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 32 - arch/mips/Makefile | 9 - arch/mips/configs/atlas_defconfig | 1472 ---------------------------- arch/mips/configs/bcm47xx_defconfig | 1 - arch/mips/configs/bigsur_defconfig | 1 - arch/mips/configs/capcella_defconfig | 1 - arch/mips/configs/cobalt_defconfig | 1 - arch/mips/configs/db1000_defconfig | 1 - arch/mips/configs/db1100_defconfig | 1 - arch/mips/configs/db1200_defconfig | 1 - arch/mips/configs/db1500_defconfig | 1 - arch/mips/configs/db1550_defconfig | 1 - arch/mips/configs/decstation_defconfig | 1 - arch/mips/configs/e55_defconfig | 1 - arch/mips/configs/emma2rh_defconfig | 1 - arch/mips/configs/excite_defconfig | 1 - arch/mips/configs/fulong_defconfig | 1 - arch/mips/configs/ip22_defconfig | 1 - arch/mips/configs/ip27_defconfig | 1 - arch/mips/configs/ip28_defconfig | 1 - arch/mips/configs/ip32_defconfig | 1 - arch/mips/configs/jazz_defconfig | 1 - arch/mips/configs/jmr3927_defconfig | 1 - arch/mips/configs/lasat_defconfig | 1 - arch/mips/configs/malta_defconfig | 1 - arch/mips/configs/mipssim_defconfig | 1 - arch/mips/configs/mpc30x_defconfig | 1 - arch/mips/configs/msp71xx_defconfig | 1 - arch/mips/configs/mtx1_defconfig | 1 - arch/mips/configs/pb1100_defconfig | 1 - arch/mips/configs/pb1500_defconfig | 1 - arch/mips/configs/pb1550_defconfig | 1 - arch/mips/configs/pnx8550-jbs_defconfig | 1 - arch/mips/configs/pnx8550-stb810_defconfig | 1 - arch/mips/configs/rbhma4200_defconfig | 1 - arch/mips/configs/rbhma4500_defconfig | 1 - arch/mips/configs/rm200_defconfig | 1 - arch/mips/configs/sb1250-swarm_defconfig | 1 - arch/mips/configs/sead_defconfig | 1 - arch/mips/configs/tb0219_defconfig | 1 - arch/mips/configs/tb0226_defconfig | 1 - arch/mips/configs/tb0287_defconfig | 1 - arch/mips/configs/workpad_defconfig | 1 - arch/mips/configs/wrppmc_defconfig | 1 - arch/mips/configs/yosemite_defconfig | 1 - arch/mips/mips-boards/atlas/Makefile | 22 - arch/mips/mips-boards/atlas/atlas_gdb.c | 97 -- arch/mips/mips-boards/atlas/atlas_int.c | 272 ----- arch/mips/mips-boards/atlas/atlas_setup.c | 82 -- arch/mips/mips-boards/generic/console.c | 11 +- arch/mips/mips-boards/generic/init.c | 8 - arch/mips/mips-boards/generic/reset.c | 17 - arch/mips/mips-boards/generic/time.c | 5 +- arch/mips/pci/Makefile | 1 - arch/mips/pci/fixup-atlas.c | 91 -- include/asm-mips/mach-atlas/mc146818rtc.h | 60 -- 56 files changed, 2 insertions(+), 2219 deletions(-) delete mode 100644 arch/mips/configs/atlas_defconfig delete mode 100644 arch/mips/mips-boards/atlas/Makefile delete mode 100644 arch/mips/mips-boards/atlas/atlas_gdb.c delete mode 100644 arch/mips/mips-boards/atlas/atlas_int.c delete mode 100644 arch/mips/mips-boards/atlas/atlas_setup.c delete mode 100644 arch/mips/pci/fixup-atlas.c delete mode 100644 include/asm-mips/mach-atlas/mc146818rtc.h (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 21d6ec1e5368..6383c700686c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -181,38 +181,6 @@ config LEMOTE_FULONG Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and an FPGA northbridge -config MIPS_ATLAS - bool "MIPS Atlas board" - select BOOT_ELF32 - select BOOT_RAW - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select SYS_HAS_EARLY_PRINTK - select IRQ_CPU - select HW_HAS_PCI - select MIPS_BOARDS_GEN - select MIPS_BONITO64 - select PCI_GT64XXX_PCI0 - select MIPS_MSC - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_HAS_CPU_MIPS64_R1 - select SYS_HAS_CPU_NEVADA - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL - select SYS_SUPPORTS_SMARTMIPS - select GENERIC_HARDIRQS_NO__DO_IRQ - help - This enables support for the MIPS Technologies Atlas evaluation - board. - config MIPS_MALTA bool "MIPS Malta board" select ARCH_MAY_HAVE_PC_FDC diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0b8d82d55c66..9bc2c763909f 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -309,15 +309,6 @@ cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote # core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ -# -# MIPS Atlas board -# -core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/ -cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas -cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips -load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 -all-$(CONFIG_MIPS_ATLAS) := vmlinux.bin - # # MIPS Malta board # diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig deleted file mode 100644 index 3443f6cd57bb..000000000000 --- a/arch/mips/configs/atlas_defconfig +++ /dev/null @@ -1,1472 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Sun Feb 18 21:27:35 2007 -# -CONFIG_MIPS=y - -# -# Machine selection -# -CONFIG_ZONE_DMA=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -CONFIG_MIPS_ATLAS=y -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_MIPS_BONITO64=y -CONFIG_MIPS_MSC=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_MIPS_BOARDS_GEN=y -CONFIG_MIPS_GT64120=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_CPU_MIPS64_R1=y -CONFIG_SYS_HAS_CPU_NEVADA=y -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPSR1=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -# CONFIG_CPU_HAS_SMARTMIPS is not set -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_SMARTMIPS=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -# CONFIG_HZ_48 is not set -CONFIG_HZ_100=y -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -# CONFIG_HZ_1000 is not set -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=100 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -# CONFIG_KEXEC is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_RELAY=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y - -# -# IP: Virtual Server Configuration -# -CONFIG_IP_VS=m -# CONFIG_IP_VS_DEBUG is not set -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m -CONFIG_IPV6=m -CONFIG_IPV6_PRIVACY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=y -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETWORK_SECMARK=y -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_BRIDGE_NETFILTER=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK_SUPPORT=y -# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -# CONFIG_IP_NF_TARGET_CLUSTERIP is not set -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# IPv6: Netfilter Configuration (EXPERIMENTAL) -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_OWNER=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_RAW=m - -# -# Bridge: Netfilter Configuration -# -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_ULOG=m - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -CONFIG_IP_SCTP=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -CONFIG_SCTP_HMAC_MD5=y - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -# CONFIG_DECNET is not set -CONFIG_LLC=m -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=m -CONFIG_IPDDP=m -CONFIG_IPDDP_ENCAP=y -CONFIG_IPDDP_DECAP=y -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_FIFO=y -CONFIG_NET_SCH_CLK_JIFFIES=y -# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set -# CONFIG_NET_SCH_CLK_CPU is not set - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_INGRESS=m - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -# CONFIG_CLS_U32_PERF is not set -# CONFIG_CLS_U32_MARK is not set -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_CLS_POLICE=y -CONFIG_NET_CLS_IND=y -CONFIG_NET_ESTIMATOR=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y -CONFIG_FIB_RULES=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_UMEM=m -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=m - -# -# Misc devices -# -CONFIG_SGI_IOC4=m -# CONFIG_TIFM_CORE is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_IDE_ARM is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_SCSI_TGT=m -CONFIG_SCSI_NETLINK=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=m -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=m -CONFIG_CHR_DEV_SCH=m - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y - -# -# SCSI Transports -# -CONFIG_SCSI_SPI_ATTRS=y -CONFIG_SCSI_FC_ATTRS=y -CONFIG_SCSI_ISCSI_ATTRS=m -CONFIG_SCSI_SAS_ATTRS=m -CONFIG_SCSI_SAS_LIBSAS=m -CONFIG_SCSI_SAS_LIBSAS_DEBUG=y - -# -# SCSI low-level drivers -# -CONFIG_ISCSI_TCP=m -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -CONFIG_SCSI_AIC94XX=m -# CONFIG_AIC94XX_DEBUG is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_STEX is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -CONFIG_SCSI_SYM53C8XX_MMIO=y -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_SRP is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# -# CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID5_RESHAPE=y -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_EMC=m - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m -# CONFIG_BROADCOM_PHY is not set -# CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -# CONFIG_PCNET32_NAPI is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -CONFIG_LAN_SAA9730=y -# CONFIG_SC92031 is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_QLA3XXX=m -# CONFIG_ATL1 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -CONFIG_CHELSIO_T3=m -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -CONFIG_NETXEN_NIC=m - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=m -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -CONFIG_INPUT_MOUSE=y -# CONFIG_MOUSE_PS2 is not set -CONFIG_MOUSE_SERIAL=m -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=m -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# HID Devices -# -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -CONFIG_XFS_QUOTA=y -CONFIG_XFS_SECURITY=y -CONFIG_XFS_POSIX_ACL=y -# CONFIG_XFS_RT is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -CONFIG_MINIX_FS=m -CONFIG_ROMFS_FS=m -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -CONFIG_DNOTIFY=y -CONFIG_AUTOFS_FS=y -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m -CONFIG_GENERIC_ACL=y - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -CONFIG_AFFS_FS=m -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_CRAMFS=m -CONFIG_VXFS_FS=m -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -# CONFIG_NFSD_V3_ACL is not set -# CONFIG_NFSD_V4 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=m -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# -CONFIG_DLM=m -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=m -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=m -CONFIG_CRC32=y -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index c0e42e74dfbd..10d83e4aca58 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -16,7 +16,6 @@ CONFIG_BCM47XX=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 2b4ad5f3e959..a9926861f14c 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index a94f14b5c8fa..ee8a7fc99f54 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index b7295e988381..ce31a47f1a15 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS_COBALT=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 36578968d386..f99b6f8c9788 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1000=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 5a90740c363a..0d6ba9e65ff5 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1100=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 76f37a1159fe..0c6f2a469f09 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1200=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 508c91944f30..02db28f5dc03 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1500=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 0c2c70d21db9..a0f19f2e7d59 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1550=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index 58c2cd68c3a7..c1ab8a21bb07 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set CONFIG_MACH_DECSTATION=y # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 90d81f5dcebc..88c2420bc627 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig index f9a003c2b3a1..03f0baad1b67 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/emma2rh_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig index 15efacc75d73..873597a4aaf1 100644 --- a/arch/mips/configs/excite_defconfig +++ b/arch/mips/configs/excite_defconfig @@ -27,7 +27,6 @@ CONFIG_BASLER_EXCITE=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig index 5887a1735fba..13e1ef2240ea 100644 --- a/arch/mips/configs/fulong_defconfig +++ b/arch/mips/configs/fulong_defconfig @@ -14,7 +14,6 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 4f5e56c9335e..7daf203c1481 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -15,7 +15,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index f40e437bd9e5..83d769f941d6 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index ec188be9a67a..3c5090a248b7 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index 2c5c624c5d42..f8d1cf3e8749 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 56148745e8f2..72ff710c878f 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set CONFIG_MACH_JAZZ=y -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index a7cd67753aac..8dc8bef471b4 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig index e6aef999854c..a8fa2055c071 100644 --- a/arch/mips/configs/lasat_defconfig +++ b/arch/mips/configs/lasat_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set CONFIG_LASAT=y # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 3d0da952811c..9a8ed74cc1a9 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -15,7 +15,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set CONFIG_MIPS_MALTA=y # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 4f6bce99d5cf..1d205446ee70 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set CONFIG_MIPS_SIM=y diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 27e23fc9363a..0c7f35acb702 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig index b12b73f6d74f..2dd2a4f38fbe 100644 --- a/arch/mips/configs/msp71xx_defconfig +++ b/arch/mips/configs/msp71xx_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index fa3aa3919448..17d66526fa48 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -14,7 +14,6 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 1d0157d3a5bb..eaf608ca65a6 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_PB1100=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index d0491a05ee58..62c5a7098ab1 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_PB1500=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 16d78d3cd2aa..29c8548b68f7 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_PB1550=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 780c7fc24b82..c714f43e7dc8 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig index 267f21ed1d0f..c1adcfac6c54 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550-stb810_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig index 470f6f4d3ea2..9e1083626292 100644 --- a/arch/mips/configs/rbhma4200_defconfig +++ b/arch/mips/configs/rbhma4200_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index 5a39f56b175e..462a652ee022 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 56371b860eb0..2562f355dbf1 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 4b8799802788..ff89765f87f7 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 3ee75b15c0b0..d3db59bf399b 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set CONFIG_MIPS_SEAD=y # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index 8dd3ae39bcad..34ce11de5367 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index 2ba240e897c6..e5ae6b1839b2 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index a5d0f3c55ed1..2fdfd6659ef1 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index edf90b321fe6..ee411216d373 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index 2e3c683b2052..66d3c11a0382 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set CONFIG_WR_PPMC=y diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index b6178ffbc523..daa4e48a7232 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/mips-boards/atlas/Makefile b/arch/mips/mips-boards/atlas/Makefile deleted file mode 100644 index f71c2dd1041a..000000000000 --- a/arch/mips/mips-boards/atlas/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# - -obj-y := atlas_int.o atlas_setup.o -obj-$(CONFIG_KGDB) += atlas_gdb.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/atlas/atlas_gdb.c b/arch/mips/mips-boards/atlas/atlas_gdb.c deleted file mode 100644 index 00c98cff62dc..000000000000 --- a/arch/mips/mips-boards/atlas/atlas_gdb.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * This is the interface to the remote debugger stub. - */ -#include -#include -#include - -#define INB(a) inb((unsigned long)a) -#define OUTB(x, a) outb(x, (unsigned long)a) - -/* - * This is the interface to the remote debugger stub - * if the Philips part is used for the debug port, - * called from the platform setup code. - */ -void *saa9730_base = (void *)ATLAS_SAA9730_REG; - -static int saa9730_kgdb_active = 0; - -#define SAA9730_BAUDCLOCK(baud) (((ATLAS_SAA9730_BAUDCLOCK/(baud))/16)-1) - -int saa9730_kgdb_hook(int speed) -{ - int baudclock; - t_uart_saa9730_regmap *kgdb_uart = (t_uart_saa9730_regmap *)(saa9730_base + SAA9730_UART_REGS_ADDR); - - /* - * Clear all interrupts - */ - (void) INB(&kgdb_uart->Lsr); - (void) INB(&kgdb_uart->Msr); - (void) INB(&kgdb_uart->Thr_Rbr); - (void) INB(&kgdb_uart->Iir_Fcr); - - /* - * Now, initialize the UART - */ - /* 8 data bits, one stop bit, no parity */ - OUTB(SAA9730_LCR_DATA8, &kgdb_uart->Lcr); - - baudclock = SAA9730_BAUDCLOCK(speed); - - OUTB((baudclock >> 16) & 0xff, &kgdb_uart->BaudDivMsb); - OUTB( baudclock & 0xff, &kgdb_uart->BaudDivLsb); - - /* Set RTS/DTR active */ - OUTB(SAA9730_MCR_DTR | SAA9730_MCR_RTS, &kgdb_uart->Mcr); - saa9730_kgdb_active = 1; - - return speed; -} - -int saa9730_putDebugChar(char c) -{ - t_uart_saa9730_regmap *kgdb_uart = (t_uart_saa9730_regmap *)(saa9730_base + SAA9730_UART_REGS_ADDR); - - if (!saa9730_kgdb_active) { /* need to init device first */ - return 0; - } - - while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_THRE)) - ; - OUTB(c, &kgdb_uart->Thr_Rbr); - - return 1; -} - -char saa9730_getDebugChar(void) -{ - t_uart_saa9730_regmap *kgdb_uart = (t_uart_saa9730_regmap *)(saa9730_base + SAA9730_UART_REGS_ADDR); - char c; - - if (!saa9730_kgdb_active) { /* need to init device first */ - return 0; - } - while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_DR)) - ; - - c = INB(&kgdb_uart->Thr_Rbr); - return(c); -} diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c deleted file mode 100644 index 6fb29c3ff62d..000000000000 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2006 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Routines for generic manipulation of the interrupts found on the MIPS - * Atlas board. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -static struct atlas_ictrl_regs *atlas_hw0_icregs; - -#if 0 -#define DEBUG_INT(x...) printk(x) -#else -#define DEBUG_INT(x...) -#endif - -void disable_atlas_irq(unsigned int irq_nr) -{ - atlas_hw0_icregs->intrsten = 1 << (irq_nr - ATLAS_INT_BASE); - iob(); -} - -void enable_atlas_irq(unsigned int irq_nr) -{ - atlas_hw0_icregs->intseten = 1 << (irq_nr - ATLAS_INT_BASE); - iob(); -} - -static void end_atlas_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_atlas_irq(irq); -} - -static struct irq_chip atlas_irq_type = { - .name = "Atlas", - .ack = disable_atlas_irq, - .mask = disable_atlas_irq, - .mask_ack = disable_atlas_irq, - .unmask = enable_atlas_irq, - .eoi = enable_atlas_irq, - .end = end_atlas_irq, -}; - -static inline int ls1bit32(unsigned int x) -{ - int b = 31, s; - - s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; - s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; - s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; - s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; - s = 1; if (x << 1 == 0) s = 0; b -= s; - - return b; -} - -static inline void atlas_hw0_irqdispatch(void) -{ - unsigned long int_status; - int irq; - - int_status = atlas_hw0_icregs->intstatus; - - /* if int_status == 0, then the interrupt has already been cleared */ - if (unlikely(int_status == 0)) - return; - - irq = ATLAS_INT_BASE + ls1bit32(int_status); - - DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq); - - do_IRQ(irq); -} - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = s0 & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0x8000; - t0 = t0 < 1; - //t0 = t0 << 2; - a0 = a0 - t0; - //s0 = s0 << t0; - - return a0; -#endif -} - -/* - * IRQs on the Atlas board look basically like (all external interrupt - * sources are combined together on hardware interrupt 0 (MIPS IRQ 2)): - * - * MIPS IRQ Source - * -------- ------ - * 0 Software 0 (reschedule IPI on MT) - * 1 Software 1 (remote call IPI on MT) - * 2 Combined Atlas hardware interrupt (hw0) - * 3 Hardware (ignored) - * 4 Hardware (ignored) - * 5 Hardware (ignored) - * 6 Hardware (ignored) - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Lowest ---- Software 0 - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq == MIPSCPU_INT_ATLAS) - atlas_hw0_irqdispatch(); - else if (irq >= 0) - do_IRQ(MIPS_CPU_IRQ_BASE + irq); - else - spurious_interrupt(); -} - -static inline void init_atlas_irqs(int base) -{ - int i; - - atlas_hw0_icregs = (struct atlas_ictrl_regs *) - ioremap(ATLAS_ICTRL_REGS_BASE, - sizeof(struct atlas_ictrl_regs *)); - - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. - */ - atlas_hw0_icregs->intrsten = 0xffffffff; - - for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) - set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq); -} - -static struct irqaction atlasirq = { - .handler = no_action, - .name = "Atlas cascade" -}; - -msc_irqmap_t __initdata msc_irqmap[] = { - {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, - {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, -}; -int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); - -msc_irqmap_t __initdata msc_eicirqmap[] = { - {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_ATLAS, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, - {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} -}; -int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); - -void __init arch_init_irq(void) -{ - init_atlas_irqs(ATLAS_INT_BASE); - - if (!cpu_has_veic) - mips_cpu_irq_init(); - - switch(mips_revision_corid) { - case MIPS_REVISION_CORID_CORE_MSC: - case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_FPGA3: - case MIPS_REVISION_CORID_CORE_FPGA4: - case MIPS_REVISION_CORID_CORE_24K: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: - if (cpu_has_veic) - init_msc_irqs(MSC01E_INT_BASE, MSC01E_INT_BASE, - msc_eicirqmap, msc_nr_eicirqs); - else - init_msc_irqs(MSC01E_INT_BASE, MSC01C_INT_BASE, - msc_irqmap, msc_nr_irqs); - } - - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_ATLAS, atlas_hw0_irqdispatch); - setup_irq(MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq); - } else if (cpu_has_vint) { - set_vi_handler(MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch); -#ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, - &atlasirq, (0x100 << MIPSCPU_INT_ATLAS)); -#else /* Not SMTC */ - setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); -#endif /* CONFIG_MIPS_MT_SMTC */ - } else - setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); -} diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c deleted file mode 100644 index 5c500802271e..000000000000 --- a/arch/mips/mips-boards/atlas/atlas_setup.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void __init serial_init(void); - -const char *get_system_type(void) -{ - return "MIPS Atlas"; -} - -const char display_string[] = " LINUX ON ATLAS "; - -void __init plat_mem_setup(void) -{ - mips_pcibios_init(); - - ioport_resource.end = 0x7fffffff; - - serial_init(); - -#ifdef CONFIG_KGDB - kgdb_config(); -#endif - mips_reboot_setup(); -} - -static void __init serial_init(void) -{ -#ifdef CONFIG_SERIAL_8250 - struct uart_port s; - - memset(&s, 0, sizeof(s)); - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - s.iobase = ATLAS_UART_REGS_BASE; -#else - s.iobase = ATLAS_UART_REGS_BASE+3; -#endif - s.irq = ATLAS_INT_UART; - s.uartclk = ATLAS_BASE_BAUD * 16; - s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ; - s.iotype = UPIO_PORT; - s.regshift = 3; - - if (early_serial_setup(&s) != 0) { - printk(KERN_ERR "Serial setup failed!\n"); - } -#endif -} diff --git a/arch/mips/mips-boards/generic/console.c b/arch/mips/mips-boards/generic/console.c index 4d8ab99e4155..4a2aecc6da1b 100644 --- a/arch/mips/mips-boards/generic/console.c +++ b/arch/mips/mips-boards/generic/console.c @@ -22,16 +22,7 @@ #include #include -#ifdef CONFIG_MIPS_ATLAS -#include - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define PORT(offset) (ATLAS_UART_REGS_BASE + ((offset)<<3)) -#else -#define PORT(offset) (ATLAS_UART_REGS_BASE + 3 + ((offset)<<3)) -#endif - -#elif defined(CONFIG_MIPS_SEAD) +#if defined(CONFIG_MIPS_SEAD) #include diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 83b9dc739203..bac23b5fbf3f 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -197,14 +197,6 @@ void __init kgdb_config(void) while ((c = *++argptr) && ('0' <= c && c <= '9')) speed = speed * 10 + c - '0'; } -#ifdef CONFIG_MIPS_ATLAS - if (line == 1) { - speed = saa9730_kgdb_hook(speed); - generic_putDebugChar = saa9730_putDebugChar; - generic_getDebugChar = saa9730_getDebugChar; - } - else -#endif { speed = rs_kgdb_hook(line, speed); generic_putDebugChar = rs_putDebugChar; diff --git a/arch/mips/mips-boards/generic/reset.c b/arch/mips/mips-boards/generic/reset.c index 583d468d98a9..5f73ff6180eb 100644 --- a/arch/mips/mips-boards/generic/reset.c +++ b/arch/mips/mips-boards/generic/reset.c @@ -27,15 +27,9 @@ #include #include #include -#if defined(CONFIG_MIPS_ATLAS) -#include -#endif static void mips_machine_restart(char *command); static void mips_machine_halt(void); -#if defined(CONFIG_MIPS_ATLAS) -static void atlas_machine_power_off(void); -#endif static void mips_machine_restart(char *command) { @@ -53,22 +47,11 @@ static void mips_machine_halt(void) __raw_writel(GORESET, softres_reg); } -#if defined(CONFIG_MIPS_ATLAS) -static void atlas_machine_power_off(void) -{ - unsigned int __iomem *psustby_reg = ioremap(ATLAS_PSUSTBY_REG, sizeof(unsigned int)); - - writew(ATLAS_GOSTBY, psustby_reg); -} -#endif void mips_reboot_setup(void) { _machine_restart = mips_machine_restart; _machine_halt = mips_machine_halt; -#if defined(CONFIG_MIPS_ATLAS) - pm_power_off = atlas_machine_power_off; -#endif #if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_SEAD) pm_power_off = mips_machine_halt; #endif diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index fe2cac1b4514..d224267846b0 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -42,9 +42,6 @@ #include #include -#ifdef CONFIG_MIPS_ATLAS -#include -#endif #ifdef CONFIG_MIPS_MALTA #include #endif @@ -89,7 +86,7 @@ static unsigned int __init estimate_cpu_frequency(void) else count = 6000000; #endif -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) +#ifdef CONFIG_MIPS_MALTA unsigned long flags; unsigned int start; diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index ed0c07622baa..80fa5abb25d4 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -21,7 +21,6 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o # obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o obj-$(CONFIG_LASAT) += pci-lasat.o -obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c deleted file mode 100644 index 506e883a8c71..000000000000 --- a/arch/mips/pci/fixup-atlas.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * Author: Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include - -#include - -#define PCIA ATLAS_INT_PCIA -#define PCIB ATLAS_INT_PCIB -#define PCIC ATLAS_INT_PCIC -#define PCID ATLAS_INT_PCID -#define INTA ATLAS_INT_INTA -#define INTB ATLAS_INT_INTB -#define ETH ATLAS_INT_ETH -#define INTC ATLAS_INT_INTC -#define SCSI ATLAS_INT_SCSI -#define INTD ATLAS_INT_INTD - -static char irq_tab[][5] __initdata = { - /* INTA INTB INTC INTD */ - {0, 0, 0, 0, 0 }, /* 0: Unused */ - {0, 0, 0, 0, 0 }, /* 1: Unused */ - {0, 0, 0, 0, 0 }, /* 2: Unused */ - {0, 0, 0, 0, 0 }, /* 3: Unused */ - {0, 0, 0, 0, 0 }, /* 4: Unused */ - {0, 0, 0, 0, 0 }, /* 5: Unused */ - {0, 0, 0, 0, 0 }, /* 6: Unused */ - {0, 0, 0, 0, 0 }, /* 7: Unused */ - {0, 0, 0, 0, 0 }, /* 8: Unused */ - {0, 0, 0, 0, 0 }, /* 9: Unused */ - {0, 0, 0, 0, 0 }, /* 10: Unused */ - {0, 0, 0, 0, 0 }, /* 11: Unused */ - {0, 0, 0, 0, 0 }, /* 12: Unused */ - {0, 0, 0, 0, 0 }, /* 13: Unused */ - {0, 0, 0, 0, 0 }, /* 14: Unused */ - {0, PCIA, PCIB, PCIC, PCID }, /* 15: cPCI (behind 21150) */ - {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */ - {0, 0, 0, 0, 0 }, /* 17: Core */ - {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot */ - {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Eth. et al. */ - {0, 0, 0, 0, 0 }, /* 20: Unused */ - {0, 0, 0, 0, 0 } /* 21: Unused */ -}; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_tab[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -#ifdef CONFIG_KGDB -/* - * The PCI scan may have moved the saa9730 I/O address, so reread - * the address here. - * This does mean that it's not possible to debug the PCI bus configuration - * code, but it is better than nothing... - */ - -static void atlas_saa9730_base_fixup(struct pci_dev *pdev) -{ - extern void *saa9730_base; - if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19) - (void) pci_read_config_dword(pdev, 0x14, (u32 *)&saa9730_base); - printk("saa9730_base = %x\n", saa9730_base); -} - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730, - atlas_saa9730_base_fixup); - -#endif diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h deleted file mode 100644 index 51d337e1bbd1..000000000000 --- a/include/asm-mips/mach-atlas/mc146818rtc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * Copyright (C) 2003, 05 Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef __ASM_MACH_ATLAS_MC146818RTC_H -#define __ASM_MACH_ATLAS_MC146818RTC_H - -#include - -#include - -#include -#include - -#define ARCH_RTC_LOCATION - -#define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x) * 8) -#define RTC_IO_EXTENT 0x100 -#define RTC_IOMAPPED 0 -#define RTC_IRQ ATLAS_INT_RTC - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0)); - volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1)); - - *ireg = addr; - return *dreg; -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0)); - volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1)); - - *ireg = addr; - *dreg = data; -} - -#define RTC_ALWAYS_BCD 0 - -#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) - -#endif /* __ASM_MACH_ATLAS_MC146818RTC_H */ -- cgit v1.2.3 From 1398ddb2ebdb41e8efe6ba42505fd452704c8405 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 15 Jul 2008 18:44:33 +0100 Subject: [MIPS] SEAD: Remove support code. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 20 - arch/mips/Makefile | 8 - arch/mips/configs/bcm47xx_defconfig | 1 - arch/mips/configs/bigsur_defconfig | 1 - arch/mips/configs/capcella_defconfig | 1 - arch/mips/configs/cobalt_defconfig | 1 - arch/mips/configs/db1000_defconfig | 1 - arch/mips/configs/db1100_defconfig | 1 - arch/mips/configs/db1200_defconfig | 1 - arch/mips/configs/db1500_defconfig | 1 - arch/mips/configs/db1550_defconfig | 1 - arch/mips/configs/decstation_defconfig | 1 - arch/mips/configs/e55_defconfig | 1 - arch/mips/configs/emma2rh_defconfig | 1 - arch/mips/configs/excite_defconfig | 1 - arch/mips/configs/fulong_defconfig | 1 - arch/mips/configs/ip22_defconfig | 1 - arch/mips/configs/ip27_defconfig | 1 - arch/mips/configs/ip28_defconfig | 1 - arch/mips/configs/ip32_defconfig | 1 - arch/mips/configs/jazz_defconfig | 1 - arch/mips/configs/jmr3927_defconfig | 1 - arch/mips/configs/lasat_defconfig | 1 - arch/mips/configs/malta_defconfig | 1 - arch/mips/configs/mipssim_defconfig | 1 - arch/mips/configs/mpc30x_defconfig | 1 - arch/mips/configs/msp71xx_defconfig | 1 - arch/mips/configs/mtx1_defconfig | 1 - arch/mips/configs/pb1100_defconfig | 1 - arch/mips/configs/pb1500_defconfig | 1 - arch/mips/configs/pb1550_defconfig | 1 - arch/mips/configs/pnx8550-jbs_defconfig | 1 - arch/mips/configs/pnx8550-stb810_defconfig | 1 - arch/mips/configs/rbhma4200_defconfig | 1 - arch/mips/configs/rbhma4500_defconfig | 1 - arch/mips/configs/rm200_defconfig | 1 - arch/mips/configs/sb1250-swarm_defconfig | 1 - arch/mips/configs/sead_defconfig | 641 ----------------------------- arch/mips/configs/tb0219_defconfig | 1 - arch/mips/configs/tb0226_defconfig | 1 - arch/mips/configs/tb0287_defconfig | 1 - arch/mips/configs/workpad_defconfig | 1 - arch/mips/configs/wrppmc_defconfig | 1 - arch/mips/configs/yosemite_defconfig | 1 - arch/mips/mips-boards/generic/console.c | 12 - arch/mips/mips-boards/generic/init.c | 4 - arch/mips/mips-boards/generic/reset.c | 2 +- arch/mips/mips-boards/generic/time.c | 5 +- arch/mips/mips-boards/sead/Makefile | 28 -- arch/mips/mips-boards/sead/sead_int.c | 117 ------ arch/mips/mips-boards/sead/sead_setup.c | 77 ---- include/asm-mips/mips-boards/generic.h | 9 - 52 files changed, 2 insertions(+), 962 deletions(-) delete mode 100644 arch/mips/configs/sead_defconfig delete mode 100644 arch/mips/mips-boards/sead/Makefile delete mode 100644 arch/mips/mips-boards/sead/sead_int.c delete mode 100644 arch/mips/mips-boards/sead/sead_setup.c (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6383c700686c..a0381427ec5c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -217,26 +217,6 @@ config MIPS_MALTA This enables support for the MIPS Technologies Malta evaluation board. -config MIPS_SEAD - bool "MIPS SEAD board" - select CEVT_R4K - select CSRC_R4K - select IRQ_CPU - select DMA_NONCOHERENT - select SYS_HAS_EARLY_PRINTK - select MIPS_BOARDS_GEN - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_HAS_CPU_MIPS64_R1 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_SMARTMIPS - help - This enables support for the MIPS Technologies SEAD evaluation - board. - config MIPS_SIM bool 'MIPS simulator (MIPSsim)' select CEVT_R4K diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 9bc2c763909f..800a73db822a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -317,14 +317,6 @@ cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 all-$(CONFIG_MIPS_MALTA) := vmlinux.bin -# -# MIPS SEAD board -# -core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/ -cflags-$(CONFIG_MIPS_SEAD) += -Iinclude/asm-mips/mach-mips -load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 -all-$(CONFIG_MIPS_SEAD) := vmlinux.srec - # # MIPS SIM # diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index 10d83e4aca58..d8694332b344 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -17,7 +17,6 @@ CONFIG_BCM47XX=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index a9926861f14c..a3bbbf067a3b 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index ee8a7fc99f54..185df23fd460 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index ce31a47f1a15..2678b7ec3351 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS_COBALT=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index f99b6f8c9788..ebb8ad62b3a3 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1000=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 0d6ba9e65ff5..ad4e5ef65592 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1100=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 0c6f2a469f09..d0dc2e83ad35 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1200=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 02db28f5dc03..9155082313c8 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1500=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index a0f19f2e7d59..e4e324422cd9 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1550=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index c1ab8a21bb07..9e65e6a2dcb3 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y CONFIG_MACH_DECSTATION=y # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 88c2420bc627..1bd84d42b14f 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig index 03f0baad1b67..634bb4eaf132 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/emma2rh_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig index 873597a4aaf1..3572e80356d2 100644 --- a/arch/mips/configs/excite_defconfig +++ b/arch/mips/configs/excite_defconfig @@ -28,7 +28,6 @@ CONFIG_BASLER_EXCITE=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig index 13e1ef2240ea..620980081a30 100644 --- a/arch/mips/configs/fulong_defconfig +++ b/arch/mips/configs/fulong_defconfig @@ -15,7 +15,6 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_PNX8550_JBS is not set diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 7daf203c1481..cc8e6bf2b245 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -16,7 +16,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 83d769f941d6..138c575a0151 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 3c5090a248b7..822b01f643e3 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index f8d1cf3e8749..fe4699df9626 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 72ff710c878f..bbacc35d804f 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set CONFIG_MACH_JAZZ=y # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index 8dc8bef471b4..92000a3a871d 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig index a8fa2055c071..bc9159fda728 100644 --- a/arch/mips/configs/lasat_defconfig +++ b/arch/mips/configs/lasat_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y CONFIG_LASAT=y # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 9a8ed74cc1a9..55288cf50b72 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -16,7 +16,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set CONFIG_MIPS_MALTA=y -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 1d205446ee70..2c0a6314e901 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set CONFIG_MIPS_SIM=y # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 0c7f35acb702..8c720e51795b 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig index 2dd2a4f38fbe..59d19472b161 100644 --- a/arch/mips/configs/msp71xx_defconfig +++ b/arch/mips/configs/msp71xx_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 17d66526fa48..bacf0dd0e345 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -15,7 +15,6 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index eaf608ca65a6..6dfe6f793cef 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_PB1100=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 62c5a7098ab1..c965a87e6a96 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_PB1500=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 29c8548b68f7..0778996c682f 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_PB1550=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index c714f43e7dc8..37c7b5ffd474 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig index c1adcfac6c54..893e5c4ab66d 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550-stb810_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig index 9e1083626292..f89482a2aa6b 100644 --- a/arch/mips/configs/rbhma4200_defconfig +++ b/arch/mips/configs/rbhma4200_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index 462a652ee022..70cf69761673 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 2562f355dbf1..0f4da0325ea4 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index ff89765f87f7..1ea97865f2ce 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig deleted file mode 100644 index d3db59bf399b..000000000000 --- a/arch/mips/configs/sead_defconfig +++ /dev/null @@ -1,641 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Sun Feb 18 21:28:10 2007 -# -CONFIG_MIPS=y - -# -# Machine selection -# -CONFIG_ZONE_DMA=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_SEAD=y -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_MIPS_BOARDS_GEN=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_CPU_MIPS64_R1=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPSR1=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -# CONFIG_CPU_HAS_SMARTMIPS is not set -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_SMARTMIPS=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -# CONFIG_KEXEC is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_UTS_NS is not set -# CONFIG_IKCONFIG is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_HOTPLUG is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set - -# -# Networking -# -# CONFIG_NET is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=18432 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CDROM_PKTCDVD is not set - -# -# Misc devices -# - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set -# CONFIG_SCSI_NETLINK is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# -# CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# ISDN subsystem -# - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MSDOS_PARTITION is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index 34ce11de5367..b5059881bc7e 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index e5ae6b1839b2..b06a716bf23f 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index 2fdfd6659ef1..46512cf7ce04 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index ee411216d373..b437eb7f8672 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index 66d3c11a0382..fc2c56731b98 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set CONFIG_WR_PPMC=y # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index daa4e48a7232..7f86c43d1bda 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/mips-boards/generic/console.c b/arch/mips/mips-boards/generic/console.c index 4a2aecc6da1b..43bcfb4f8167 100644 --- a/arch/mips/mips-boards/generic/console.c +++ b/arch/mips/mips-boards/generic/console.c @@ -22,21 +22,9 @@ #include #include -#if defined(CONFIG_MIPS_SEAD) - -#include - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define PORT(offset) (SEAD_UART0_REGS_BASE + ((offset)<<3)) -#else -#define PORT(offset) (SEAD_UART0_REGS_BASE + 3 + ((offset)<<3)) -#endif - -#else #define PORT(offset) (0x3f8 + (offset)) -#endif static inline unsigned int serial_in(int offset) { diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index bac23b5fbf3f..c0653021a171 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -252,9 +252,6 @@ void __init prom_init(void) mips_display_message("LINUX"); -#ifdef CONFIG_MIPS_SEAD - set_io_port_base(KSEG1); -#else /* * early setup of _pcictrl_bonito so that we can determine * the system controller on a CORE_EMUL board @@ -406,7 +403,6 @@ void __init prom_init(void) mips_display_message("SC Error"); while (1); /* We die here... */ } -#endif board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; diff --git a/arch/mips/mips-boards/generic/reset.c b/arch/mips/mips-boards/generic/reset.c index 5f73ff6180eb..ea932b843962 100644 --- a/arch/mips/mips-boards/generic/reset.c +++ b/arch/mips/mips-boards/generic/reset.c @@ -52,7 +52,7 @@ void mips_reboot_setup(void) { _machine_restart = mips_machine_restart; _machine_halt = mips_machine_halt; -#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_SEAD) +#ifdef CONFIG_MIPS_MALTA pm_power_off = mips_machine_halt; #endif } diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index d224267846b0..637897e8e4fb 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -45,9 +45,6 @@ #ifdef CONFIG_MIPS_MALTA #include #endif -#ifdef CONFIG_MIPS_SEAD -#include -#endif unsigned long cpu_khz; @@ -73,7 +70,7 @@ static unsigned int __init estimate_cpu_frequency(void) unsigned int prid = read_c0_prid() & 0xffff00; unsigned int count; -#if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM) +#ifdef CONFIG_MIPS_SIM /* * The SEAD board doesn't have a real time clock, so we can't * really calculate the timer frequency diff --git a/arch/mips/mips-boards/sead/Makefile b/arch/mips/mips-boards/sead/Makefile deleted file mode 100644 index 3682fe217bd5..000000000000 --- a/arch/mips/mips-boards/sead/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. -# -# ######################################################################## -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# ####################################################################### -# -# Makefile for the MIPS SEAD specific kernel interface routines -# under Linux. -# - -obj-y := sead_int.o sead_setup.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c deleted file mode 100644 index ec6dd194c14a..000000000000 --- a/arch/mips/mips-boards/sead/sead_int.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2004 Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Routines for generic manipulation of the interrupts found on the MIPS - * Sead board. - */ -#include -#include - -#include -#include -#include - -#include - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = s0 & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0x8000; - t0 = t0 < 1; - //t0 = t0 << 2; - a0 = a0 - t0; - //s0 = s0 << t0; - - return a0; -#endif -} - -/* - * IRQs on the SEAD board look basically are combined together on hardware - * interrupt 0 (MIPS IRQ 2)) like: - * - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 UART0 (hw0) - * 3 UART1 (hw1) - * 4 Hardware (ignored) - * 5 Hardware (ignored) - * 6 Hardware (ignored) - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Lowest ---- Combined hardware interrupt - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq >= 0) - do_IRQ(MIPS_CPU_IRQ_BASE + irq); - else - spurious_interrupt(); -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(); -} diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c deleted file mode 100644 index 8aa8e5b7b074..000000000000 --- a/arch/mips/mips-boards/sead/sead_setup.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * SEAD specific setup. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -static void __init serial_init(void); - -const char *get_system_type(void) -{ - return "MIPS SEAD"; -} - -const char display_string[] = " LINUX ON SEAD "; - -void __init plat_mem_setup(void) -{ - ioport_resource.end = 0x7fffffff; - - serial_init(); - - mips_reboot_setup(); -} - -static void __init serial_init(void) -{ -#ifdef CONFIG_SERIAL_8250 - struct uart_port s; - - memset(&s, 0, sizeof(s)); - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - s.iobase = SEAD_UART0_REGS_BASE; -#else - s.iobase = SEAD_UART0_REGS_BASE+3; -#endif - s.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_UART0; - s.uartclk = SEAD_BASE_BAUD * 16; - s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ; - s.iotype = UPIO_PORT; - s.regshift = 3; - - if (early_serial_setup(&s) != 0) { - printk(KERN_ERR "Serial setup failed!\n"); - } -#endif -} diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index 33407bee4e73..7f0b034dd9a5 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -27,12 +27,8 @@ /* * Display register base. */ -#ifdef CONFIG_MIPS_SEAD -#define ASCII_DISPLAY_POS_BASE 0x1f0005c0 -#else #define ASCII_DISPLAY_WORD_BASE 0x1f000410 #define ASCII_DISPLAY_POS_BASE 0x1f000418 -#endif /* @@ -44,13 +40,8 @@ /* * Reset register. */ -#ifdef CONFIG_MIPS_SEAD -#define SOFTRES_REG 0x1e800050 -#define GORESET 0x4d -#else #define SOFTRES_REG 0x1f000500 #define GORESET 0x42 -#endif /* * Revision register. -- cgit v1.2.3 From 315806cb19f9d375dccbc2d60fa14e16afdcd5ac Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 15 Jul 2008 18:44:34 +0100 Subject: [MIPS] Malta: Cleanup organization of code into directories. Signed-off-by: Ralf Baechle --- arch/mips/Makefile | 5 +- arch/mips/mips-boards/generic/Makefile | 29 - arch/mips/mips-boards/generic/amon.c | 80 --- arch/mips/mips-boards/generic/cmdline.c | 59 -- arch/mips/mips-boards/generic/console.c | 47 -- arch/mips/mips-boards/generic/display.c | 64 -- arch/mips/mips-boards/generic/gdb_hook.c | 133 ---- arch/mips/mips-boards/generic/init.c | 424 ------------ arch/mips/mips-boards/generic/memory.c | 177 ----- arch/mips/mips-boards/generic/pci.c | 243 ------- arch/mips/mips-boards/generic/reset.c | 56 -- arch/mips/mips-boards/generic/time.c | 163 ----- arch/mips/mips-boards/malta/Makefile | 27 - arch/mips/mips-boards/malta/malta_int.c | 712 --------------------- arch/mips/mips-boards/malta/malta_mtd.c | 63 -- arch/mips/mips-boards/malta/malta_platform.c | 65 -- arch/mips/mips-boards/malta/malta_setup.c | 229 ------- arch/mips/mips-boards/malta/malta_smtc.c | 154 ----- arch/mips/mti-malta/Makefile | 21 + arch/mips/mti-malta/malta-amon.c | 80 +++ arch/mips/mti-malta/malta-cmdline.c | 59 ++ arch/mips/mti-malta/malta-console.c | 47 ++ arch/mips/mti-malta/malta-display.c | 64 ++ arch/mips/mti-malta/malta-init.c | 424 ++++++++++++ arch/mips/mti-malta/malta-int.c | 712 +++++++++++++++++++++ arch/mips/mti-malta/malta-kgdb.c | 133 ++++ arch/mips/mti-malta/malta-memory.c | 177 +++++ arch/mips/mti-malta/malta-mtd.c | 63 ++ arch/mips/mti-malta/malta-pci.c | 243 +++++++ arch/mips/mti-malta/malta-platform.c | 65 ++ arch/mips/mti-malta/malta-reset.c | 56 ++ arch/mips/mti-malta/malta-setup.c | 229 +++++++ arch/mips/mti-malta/malta-smtc.c | 154 +++++ arch/mips/mti-malta/malta-time.c | 163 +++++ .../asm-mips/mach-malta/cpu-feature-overrides.h | 72 +++ include/asm-mips/mach-malta/irq.h | 9 + include/asm-mips/mach-malta/kernel-entry-init.h | 52 ++ include/asm-mips/mach-malta/mach-gt64120.h | 19 + include/asm-mips/mach-malta/mc146818rtc.h | 48 ++ include/asm-mips/mach-malta/war.h | 25 + include/asm-mips/mach-mips/cpu-feature-overrides.h | 72 --- include/asm-mips/mach-mips/irq.h | 9 - include/asm-mips/mach-mips/kernel-entry-init.h | 52 -- include/asm-mips/mach-mips/mach-gt64120.h | 19 - include/asm-mips/mach-mips/mc146818rtc.h | 48 -- include/asm-mips/mach-mips/war.h | 25 - 46 files changed, 2917 insertions(+), 2953 deletions(-) delete mode 100644 arch/mips/mips-boards/generic/Makefile delete mode 100644 arch/mips/mips-boards/generic/amon.c delete mode 100644 arch/mips/mips-boards/generic/cmdline.c delete mode 100644 arch/mips/mips-boards/generic/console.c delete mode 100644 arch/mips/mips-boards/generic/display.c delete mode 100644 arch/mips/mips-boards/generic/gdb_hook.c delete mode 100644 arch/mips/mips-boards/generic/init.c delete mode 100644 arch/mips/mips-boards/generic/memory.c delete mode 100644 arch/mips/mips-boards/generic/pci.c delete mode 100644 arch/mips/mips-boards/generic/reset.c delete mode 100644 arch/mips/mips-boards/generic/time.c delete mode 100644 arch/mips/mips-boards/malta/Makefile delete mode 100644 arch/mips/mips-boards/malta/malta_int.c delete mode 100644 arch/mips/mips-boards/malta/malta_mtd.c delete mode 100644 arch/mips/mips-boards/malta/malta_platform.c delete mode 100644 arch/mips/mips-boards/malta/malta_setup.c delete mode 100644 arch/mips/mips-boards/malta/malta_smtc.c create mode 100644 arch/mips/mti-malta/Makefile create mode 100644 arch/mips/mti-malta/malta-amon.c create mode 100644 arch/mips/mti-malta/malta-cmdline.c create mode 100644 arch/mips/mti-malta/malta-console.c create mode 100644 arch/mips/mti-malta/malta-display.c create mode 100644 arch/mips/mti-malta/malta-init.c create mode 100644 arch/mips/mti-malta/malta-int.c create mode 100644 arch/mips/mti-malta/malta-kgdb.c create mode 100644 arch/mips/mti-malta/malta-memory.c create mode 100644 arch/mips/mti-malta/malta-mtd.c create mode 100644 arch/mips/mti-malta/malta-pci.c create mode 100644 arch/mips/mti-malta/malta-platform.c create mode 100644 arch/mips/mti-malta/malta-reset.c create mode 100644 arch/mips/mti-malta/malta-setup.c create mode 100644 arch/mips/mti-malta/malta-smtc.c create mode 100644 arch/mips/mti-malta/malta-time.c create mode 100644 include/asm-mips/mach-malta/cpu-feature-overrides.h create mode 100644 include/asm-mips/mach-malta/irq.h create mode 100644 include/asm-mips/mach-malta/kernel-entry-init.h create mode 100644 include/asm-mips/mach-malta/mach-gt64120.h create mode 100644 include/asm-mips/mach-malta/mc146818rtc.h create mode 100644 include/asm-mips/mach-malta/war.h delete mode 100644 include/asm-mips/mach-mips/cpu-feature-overrides.h delete mode 100644 include/asm-mips/mach-mips/irq.h delete mode 100644 include/asm-mips/mach-mips/kernel-entry-init.h delete mode 100644 include/asm-mips/mach-mips/mach-gt64120.h delete mode 100644 include/asm-mips/mach-mips/mc146818rtc.h delete mode 100644 include/asm-mips/mach-mips/war.h (limited to 'include') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index ed8821ac8a8e..36aa690484c8 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -307,9 +307,8 @@ cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote # # MIPS Malta board # -core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/generic/ \ - arch/mips/mips-boards/malta/ -cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips +core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/ +cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-malta load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 all-$(CONFIG_MIPS_MALTA) := vmlinux.bin diff --git a/arch/mips/mips-boards/generic/Makefile b/arch/mips/mips-boards/generic/Makefile deleted file mode 100644 index f7f87fc09d1e..000000000000 --- a/arch/mips/mips-boards/generic/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# Makefile for the MIPS boards generic routines under Linux. -# - -obj-y := reset.o display.o init.o memory.o \ - cmdline.o time.o -obj-y += amon.o - -obj-$(CONFIG_EARLY_PRINTK) += console.o -obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_KGDB) += gdb_hook.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/generic/amon.c b/arch/mips/mips-boards/generic/amon.c deleted file mode 100644 index 96236bf33838..000000000000 --- a/arch/mips/mips-boards/generic/amon.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2007 MIPS Technologies, Inc. - * All rights reserved. - - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Arbitrary Monitor interface - */ - -#include -#include -#include - -#include -#include -#include - -int amon_cpu_avail(int cpu) -{ - struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); - - if (cpu < 0 || cpu >= NCPULAUNCH) { - pr_debug("avail: cpu%d is out of range\n", cpu); - return 0; - } - - launch += cpu; - if (!(launch->flags & LAUNCH_FREADY)) { - pr_debug("avail: cpu%d is not ready\n", cpu); - return 0; - } - if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) { - pr_debug("avail: too late.. cpu%d is already gone\n", cpu); - return 0; - } - - return 1; -} - -void amon_cpu_start(int cpu, - unsigned long pc, unsigned long sp, - unsigned long gp, unsigned long a0) -{ - volatile struct cpulaunch *launch = - (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); - - if (!amon_cpu_avail(cpu)) - return; - if (cpu == smp_processor_id()) { - pr_debug("launch: I am cpu%d!\n", cpu); - return; - } - launch += cpu; - - pr_debug("launch: starting cpu%d\n", cpu); - - launch->pc = pc; - launch->gp = gp; - launch->sp = sp; - launch->a0 = a0; - - /* Make sure target sees parameters before the go bit */ - smp_mb(); - - launch->flags |= LAUNCH_FGO; - while ((launch->flags & LAUNCH_FGONE) == 0) - ; - pr_debug("launch: cpu%d gone!\n", cpu); -} diff --git a/arch/mips/mips-boards/generic/cmdline.c b/arch/mips/mips-boards/generic/cmdline.c deleted file mode 100644 index 1871c30ed2eb..000000000000 --- a/arch/mips/mips-boards/generic/cmdline.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Kernel command line creation using the prom monitor (YAMON) argc/argv. - */ -#include -#include - -#include - -extern int prom_argc; -extern int *_prom_argv; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension. - */ -#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv(actr)); - cp += strlen(prom_argv(actr)); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) { - /* get rid of trailing space */ - --cp; - *cp = '\0'; - } -} diff --git a/arch/mips/mips-boards/generic/console.c b/arch/mips/mips-boards/generic/console.c deleted file mode 100644 index 43bcfb4f8167..000000000000 --- a/arch/mips/mips-boards/generic/console.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Putting things on the screen/serial line using YAMONs facilities. - */ -#include -#include -#include -#include - - -#define PORT(offset) (0x3f8 + (offset)) - - -static inline unsigned int serial_in(int offset) -{ - return inb(PORT(offset)); -} - -static inline void serial_out(int offset, int value) -{ - outb(value, PORT(offset)); -} - -int prom_putchar(char c) -{ - while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(UART_TX, c); - - return 1; -} diff --git a/arch/mips/mips-boards/generic/display.c b/arch/mips/mips-boards/generic/display.c deleted file mode 100644 index 7c8828fcb0ad..000000000000 --- a/arch/mips/mips-boards/generic/display.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Display routines for display messages in MIPS boards ascii display. - */ - -#include -#include -#include -#include -#include - -extern const char display_string[]; -static unsigned int display_count; -static unsigned int max_display_count; - -void mips_display_message(const char *str) -{ - static unsigned int __iomem *display = NULL; - int i; - - if (unlikely(display == NULL)) - display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int)); - - for (i = 0; i <= 14; i=i+2) { - if (*str) - __raw_writel(*str++, display + i); - else - __raw_writel(' ', display + i); - } -} - -static void scroll_display_message(unsigned long data); -static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0); - -static void scroll_display_message(unsigned long data) -{ - mips_display_message(&display_string[display_count++]); - if (display_count == max_display_count) - display_count = 0; - - mod_timer(&mips_scroll_timer, jiffies + HZ); -} - -void mips_scroll_message(void) -{ - del_timer_sync(&mips_scroll_timer); - max_display_count = strlen(display_string) + 1 - 8; - mod_timer(&mips_scroll_timer, jiffies + 1); -} diff --git a/arch/mips/mips-boards/generic/gdb_hook.c b/arch/mips/mips-boards/generic/gdb_hook.c deleted file mode 100644 index 6a1854de4579..000000000000 --- a/arch/mips/mips-boards/generic/gdb_hook.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * This is the interface to the remote debugger stub. - */ -#include -#include -#include -#include - -#include -#include - -static struct serial_state rs_table[] = { - SERIAL_PORT_DFNS /* Defined in serial.h */ -}; - -static struct async_struct kdb_port_info = {0}; - -int (*generic_putDebugChar)(char); -char (*generic_getDebugChar)(void); - -static __inline__ unsigned int serial_in(struct async_struct *info, int offset) -{ - return inb(info->port + offset); -} - -static __inline__ void serial_out(struct async_struct *info, int offset, - int value) -{ - outb(value, info->port+offset); -} - -int rs_kgdb_hook(int tty_no, int speed) { - int t; - struct serial_state *ser = &rs_table[tty_no]; - - kdb_port_info.state = ser; - kdb_port_info.magic = SERIAL_MAGIC; - kdb_port_info.port = ser->port; - kdb_port_info.flags = ser->flags; - - /* - * Clear all interrupts - */ - serial_in(&kdb_port_info, UART_LSR); - serial_in(&kdb_port_info, UART_RX); - serial_in(&kdb_port_info, UART_IIR); - serial_in(&kdb_port_info, UART_MSR); - - /* - * Now, initialize the UART - */ - serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ - if (kdb_port_info.flags & ASYNC_FOURPORT) { - kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS; - t = UART_MCR_DTR | UART_MCR_OUT1; - } else { - kdb_port_info.MCR - = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; - t = UART_MCR_DTR | UART_MCR_RTS; - } - - kdb_port_info.MCR = t; /* no interrupts, please */ - serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR); - - /* - * and set the speed of the serial port - */ - if (speed == 0) - speed = 9600; - - t = kdb_port_info.state->baud_base / speed; - /* set DLAB */ - serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB); - serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */ - serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */ - /* reset DLAB */ - serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); - - return speed; -} - -int putDebugChar(char c) -{ - return generic_putDebugChar(c); -} - -char getDebugChar(void) -{ - return generic_getDebugChar(); -} - -int rs_putDebugChar(char c) -{ - - if (!kdb_port_info.state) { /* need to init device first */ - return 0; - } - - while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(&kdb_port_info, UART_TX, c); - - return 1; -} - -char rs_getDebugChar(void) -{ - if (!kdb_port_info.state) { /* need to init device first */ - return 0; - } - - while (!(serial_in(&kdb_port_info, UART_LSR) & 1)) - ; - - return serial_in(&kdb_port_info, UART_RX); -} diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c deleted file mode 100644 index c0653021a171..000000000000 --- a/arch/mips/mips-boards/generic/init.c +++ /dev/null @@ -1,424 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * PROM library initialisation code. - */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_KGDB -extern int rs_kgdb_hook(int, int); -extern int rs_putDebugChar(char); -extern char rs_getDebugChar(void); -extern int saa9730_kgdb_hook(int); -extern int saa9730_putDebugChar(char); -extern char saa9730_getDebugChar(void); -#endif - -int prom_argc; -int *_prom_argv, *_prom_envp; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension, if running in 64-bit mode. - */ -#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) - -int init_debug = 0; - -int mips_revision_corid; -int mips_revision_sconid; - -/* Bonito64 system controller register base. */ -unsigned long _pcictrl_bonito; -unsigned long _pcictrl_bonito_pcicfg; - -/* GT64120 system controller register base */ -unsigned long _pcictrl_gt64120; - -/* MIPS System controller register base */ -unsigned long _pcictrl_msc; - -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - * In 64-bit mode: we're using 64-bit pointers, but all pointers - * in the PROM structures are only 32-bit, so we need some - * workarounds, if we are running in 64-bit mode. - */ - int i, index=0; - - i = strlen(envname); - - while (prom_envp(index)) { - if(strncmp(envname, prom_envp(index), i) == 0) { - return(prom_envp(index+1)); - } - index += 2; - } - - return NULL; -} - -static inline unsigned char str2hexnum(unsigned char c) -{ - if (c >= '0' && c <= '9') - return c - '0'; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return 0; /* foo */ -} - -static inline void str2eaddr(unsigned char *ea, unsigned char *str) -{ - int i; - - for (i = 0; i < 6; i++) { - unsigned char num; - - if((*str == '.') || (*str == ':')) - str++; - num = str2hexnum(*str++) << 4; - num |= (str2hexnum(*str++)); - ea[i] = num; - } -} - -int get_ethernet_addr(char *ethernet_addr) -{ - char *ethaddr_str; - - ethaddr_str = prom_getenv("ethaddr"); - if (!ethaddr_str) { - printk("ethaddr not set in boot prom\n"); - return -1; - } - str2eaddr(ethernet_addr, ethaddr_str); - - if (init_debug > 1) { - int i; - printk("get_ethernet_addr: "); - for (i=0; i<5; i++) - printk("%02x:", (unsigned char)*(ethernet_addr+i)); - printk("%02x\n", *(ethernet_addr+i)); - } - - return 0; -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static void __init console_config(void) -{ - char console_string[40]; - int baud = 0; - char parity = '\0', bits = '\0', flow = '\0'; - char *s; - - if ((strstr(prom_getcmdline(), "console=")) == NULL) { - s = prom_getenv("modetty0"); - if (s) { - while (*s >= '0' && *s <= '9') - baud = baud*10 + *s++ - '0'; - if (*s == ',') s++; - if (*s) parity = *s++; - if (*s == ',') s++; - if (*s) bits = *s++; - if (*s == ',') s++; - if (*s == 'h') flow = 'r'; - } - if (baud == 0) - baud = 38400; - if (parity != 'n' && parity != 'o' && parity != 'e') - parity = 'n'; - if (bits != '7' && bits != '8') - bits = '8'; - if (flow == '\0') - flow = 'r'; - sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); - strcat(prom_getcmdline(), console_string); - pr_info("Config serial console:%s\n", console_string); - } -} -#endif - -#ifdef CONFIG_KGDB -void __init kgdb_config(void) -{ - extern int (*generic_putDebugChar)(char); - extern char (*generic_getDebugChar)(void); - char *argptr; - int line, speed; - - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { - argptr += strlen("kgdb=ttyS"); - if (*argptr != '0' && *argptr != '1') - printk("KGDB: Unknown serial line /dev/ttyS%c, " - "falling back to /dev/ttyS1\n", *argptr); - line = *argptr == '0' ? 0 : 1; - printk("KGDB: Using serial line /dev/ttyS%d for session\n", line); - - speed = 0; - if (*++argptr == ',') - { - int c; - while ((c = *++argptr) && ('0' <= c && c <= '9')) - speed = speed * 10 + c - '0'; - } - { - speed = rs_kgdb_hook(line, speed); - generic_putDebugChar = rs_putDebugChar; - generic_getDebugChar = rs_getDebugChar; - } - - pr_info("KGDB: Using serial line /dev/ttyS%d at %d for " - "session, please connect your debugger\n", - line ? 1 : 0, speed); - - { - char *s; - for (s = "Please connect GDB to this port\r\n"; *s; ) - generic_putDebugChar(*s++); - } - - /* Breakpoint is invoked after interrupts are initialised */ - } -} -#endif - -static void __init mips_nmi_setup(void) -{ - void *base; - extern char except_vec_nmi; - - base = cpu_has_veic ? - (void *)(CAC_BASE + 0xa80) : - (void *)(CAC_BASE + 0x380); - memcpy(base, &except_vec_nmi, 0x80); - flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); -} - -static void __init mips_ejtag_setup(void) -{ - void *base; - extern char except_vec_ejtag_debug; - - base = cpu_has_veic ? - (void *)(CAC_BASE + 0xa00) : - (void *)(CAC_BASE + 0x300); - memcpy(base, &except_vec_ejtag_debug, 0x80); - flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); -} - -extern struct plat_smp_ops msmtc_smp_ops; - -void __init prom_init(void) -{ - prom_argc = fw_arg0; - _prom_argv = (int *) fw_arg1; - _prom_envp = (int *) fw_arg2; - - mips_display_message("LINUX"); - - /* - * early setup of _pcictrl_bonito so that we can determine - * the system controller on a CORE_EMUL board - */ - _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); - - mips_revision_corid = MIPS_REVISION_CORID; - - if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { - if (BONITO_PCIDID == 0x0001df53 || - BONITO_PCIDID == 0x0003df53) - mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; - else - mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; - } - - mips_revision_sconid = MIPS_REVISION_SCONID; - if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { - switch (mips_revision_corid) { - case MIPS_REVISION_CORID_QED_RM5261: - case MIPS_REVISION_CORID_CORE_LV: - case MIPS_REVISION_CORID_CORE_FPGA: - case MIPS_REVISION_CORID_CORE_FPGAR2: - mips_revision_sconid = MIPS_REVISION_SCON_GT64120; - break; - case MIPS_REVISION_CORID_CORE_EMUL_BON: - case MIPS_REVISION_CORID_BONITO64: - case MIPS_REVISION_CORID_CORE_20K: - mips_revision_sconid = MIPS_REVISION_SCON_BONITO; - break; - case MIPS_REVISION_CORID_CORE_MSC: - case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_24K: - /* - * SOCit/ROCit support is essentially identical - * but make an attempt to distinguish them - */ - mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; - break; - case MIPS_REVISION_CORID_CORE_FPGA3: - case MIPS_REVISION_CORID_CORE_FPGA4: - case MIPS_REVISION_CORID_CORE_FPGA5: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: - default: - /* See above */ - mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; - break; - } - } - - switch (mips_revision_sconid) { - u32 start, map, mask, data; - - case MIPS_REVISION_SCON_GT64120: - /* - * Setup the North bridge to do Master byte-lane swapping - * when running in bigendian. - */ - _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | - GT_PCI0_CMD_SBYTESWAP_BIT); -#else - GT_WRITE(GT_PCI0_CMD_OFS, 0); -#endif - /* Fix up PCI I/O mapping if necessary (for Atlas). */ - start = GT_READ(GT_PCI0IOLD_OFS); - map = GT_READ(GT_PCI0IOREMAP_OFS); - if ((start & map) != 0) { - map &= ~start; - GT_WRITE(GT_PCI0IOREMAP_OFS, map); - } - - set_io_port_base(MALTA_GT_PORT_BASE); - break; - - case MIPS_REVISION_SCON_BONITO: - _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); - - /* - * Disable Bonito IOBC. - */ - BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & - ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - - /* - * Setup the North bridge to do Master byte-lane swapping - * when running in bigendian. - */ -#ifdef CONFIG_CPU_LITTLE_ENDIAN - BONITO_BONGENCFG = BONITO_BONGENCFG & - ~(BONITO_BONGENCFG_MSTRBYTESWAP | - BONITO_BONGENCFG_BYTESWAP); -#else - BONITO_BONGENCFG = BONITO_BONGENCFG | - BONITO_BONGENCFG_MSTRBYTESWAP | - BONITO_BONGENCFG_BYTESWAP; -#endif - - set_io_port_base(MALTA_BONITO_PORT_BASE); - break; - - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); - mips_pci_controller: - mb(); - MSC_READ(MSC01_PCI_CFG, data); - MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); - wmb(); - - /* Fix up lane swapping. */ -#ifdef CONFIG_CPU_LITTLE_ENDIAN - MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); -#else - MSC_WRITE(MSC01_PCI_SWAP, - MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | - MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | - MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); -#endif - /* Fix up target memory mapping. */ - MSC_READ(MSC01_PCI_BAR0, mask); - MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); - - /* Don't handle target retries indefinitely. */ - if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == - MSC01_PCI_CFG_MAXRTRY_MSK) - data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << - MSC01_PCI_CFG_MAXRTRY_SHF)) | - ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << - MSC01_PCI_CFG_MAXRTRY_SHF); - - wmb(); - MSC_WRITE(MSC01_PCI_CFG, data); - mb(); - - set_io_port_base(MALTA_MSC_PORT_BASE); - break; - - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); - goto mips_pci_controller; - - default: - /* Unknown system controller */ - mips_display_message("SC Error"); - while (1); /* We die here... */ - } - board_nmi_handler_setup = mips_nmi_setup; - board_ejtag_handler_setup = mips_ejtag_setup; - - pr_info("\nLINUX started...\n"); - prom_init_cmdline(); - prom_meminit(); -#ifdef CONFIG_SERIAL_8250_CONSOLE - console_config(); -#endif -#ifdef CONFIG_MIPS_CMP - register_smp_ops(&cmp_smp_ops); -#endif -#ifdef CONFIG_MIPS_MT_SMP - register_smp_ops(&vsmp_smp_ops); -#endif -#ifdef CONFIG_MIPS_MT_SMTC - register_smp_ops(&msmtc_smp_ops); -#endif -} diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c deleted file mode 100644 index 61888ff72c87..000000000000 --- a/arch/mips/mips-boards/generic/memory.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * PROM library functions for acquiring/using memory descriptors given to - * us from the YAMON. - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -/*#define DEBUG*/ - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; -static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -#ifdef DEBUG -static char *mtypes[3] = { - "Dont use memory", - "YAMON PROM memory", - "Free memmory", -}; -#endif - -/* determined physical memory size, not overridden by command line args */ -unsigned long physical_memsize = 0L; - -static struct prom_pmemblock * __init prom_getmdesc(void) -{ - char *memsize_str; - unsigned int memsize; - char cmdline[CL_SIZE], *ptr; - - /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - printk(KERN_WARNING - "memsize not set in boot prom, set to default (32Mb)\n"); - physical_memsize = 0x02000000; - } else { -#ifdef DEBUG - pr_debug("prom_memsize = %s\n", memsize_str); -#endif - physical_memsize = simple_strtol(memsize_str, NULL, 0); - } - -#ifdef CONFIG_CPU_BIG_ENDIAN - /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last - word of physical memory */ - physical_memsize -= PAGE_SIZE; -#endif - - /* Check the command line for a memsize directive that overrides - the physical/default amount */ - strcpy(cmdline, arcs_cmdline); - ptr = strstr(cmdline, "memsize="); - if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) - ptr = strstr(ptr, " memsize="); - - if (ptr) - memsize = memparse(ptr + 8, &ptr); - else - memsize = physical_memsize; - - memset(mdesc, 0, sizeof(mdesc)); - - mdesc[0].type = yamon_dontuse; - mdesc[0].base = 0x00000000; - mdesc[0].size = 0x00001000; - - mdesc[1].type = yamon_prom; - mdesc[1].base = 0x00001000; - mdesc[1].size = 0x000ef000; - - /* - * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the - * south bridge and PCI access always forwarded to the ISA Bus and - * BIOSCS# is always generated. - * This mean that this area can't be used as DMA memory for PCI - * devices. - */ - mdesc[2].type = yamon_dontuse; - mdesc[2].base = 0x000f0000; - mdesc[2].size = 0x00010000; - - mdesc[3].type = yamon_dontuse; - mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; - - mdesc[4].type = yamon_free; - mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); - mdesc[4].size = memsize - mdesc[4].base; - - return &mdesc[0]; -} - -static int __init prom_memtype_classify(unsigned int type) -{ - switch (type) { - case yamon_free: - return BOOT_MEM_RAM; - case yamon_prom: - return BOOT_MEM_ROM_DATA; - default: - return BOOT_MEM_RESERVED; - } -} - -void __init prom_meminit(void) -{ - struct prom_pmemblock *p; - -#ifdef DEBUG - pr_debug("YAMON MEMORY DESCRIPTOR dump:\n"); - p = prom_getmdesc(); - while (p->size) { - int i = 0; - pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", - i, p, p->base, p->size, mtypes[p->type]); - p++; - i++; - } -#endif - p = prom_getmdesc(); - - while (p->size) { - long type; - unsigned long base, size; - - type = prom_memtype_classify(p->type); - base = p->base; - size = p->size; - - add_memory_region(base, size, type); - p++; - } -} - -void __init prom_free_prom_memory(void) -{ - unsigned long addr; - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c deleted file mode 100644 index b9743190609a..000000000000 --- a/arch/mips/mips-boards/generic/pci.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * MIPS boards specific PCI support. - */ -#include -#include -#include -#include - -#include - -#include -#include -#include - -static struct resource bonito64_mem_resource = { - .name = "Bonito PCI MEM", - .flags = IORESOURCE_MEM, -}; - -static struct resource bonito64_io_resource = { - .name = "Bonito PCI I/O", - .start = 0x00000000UL, - .end = 0x000fffffUL, - .flags = IORESOURCE_IO, -}; - -static struct resource gt64120_mem_resource = { - .name = "GT-64120 PCI MEM", - .flags = IORESOURCE_MEM, -}; - -static struct resource gt64120_io_resource = { - .name = "GT-64120 PCI I/O", - .flags = IORESOURCE_IO, -}; - -static struct resource msc_mem_resource = { - .name = "MSC PCI MEM", - .flags = IORESOURCE_MEM, -}; - -static struct resource msc_io_resource = { - .name = "MSC PCI I/O", - .flags = IORESOURCE_IO, -}; - -extern struct pci_ops bonito64_pci_ops; -extern struct pci_ops gt64xxx_pci0_ops; -extern struct pci_ops msc_pci_ops; - -static struct pci_controller bonito64_controller = { - .pci_ops = &bonito64_pci_ops, - .io_resource = &bonito64_io_resource, - .mem_resource = &bonito64_mem_resource, - .io_offset = 0x00000000UL, -}; - -static struct pci_controller gt64120_controller = { - .pci_ops = >64xxx_pci0_ops, - .io_resource = >64120_io_resource, - .mem_resource = >64120_mem_resource, -}; - -static struct pci_controller msc_controller = { - .pci_ops = &msc_pci_ops, - .io_resource = &msc_io_resource, - .mem_resource = &msc_mem_resource, -}; - -void __init mips_pcibios_init(void) -{ - struct pci_controller *controller; - resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; - - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_GT64120: - /* - * Due to a bug in the Galileo system controller, we need - * to setup the PCI BAR for the Galileo internal registers. - * This should be done in the bios/bootprom and will be - * fixed in a later revision of YAMON (the MIPS boards - * boot prom). - */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ - (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ - ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ - GT_PCI0_CFGADDR_CONFIGEN_BIT); - - /* Perform the write */ - GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); - - /* Set up resource ranges from the controller's registers. */ - start = GT_READ(GT_PCI0M0LD_OFS); - end = GT_READ(GT_PCI0M0HD_OFS); - map = GT_READ(GT_PCI0M0REMAP_OFS); - end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); - start1 = GT_READ(GT_PCI0M1LD_OFS); - end1 = GT_READ(GT_PCI0M1HD_OFS); - map1 = GT_READ(GT_PCI0M1REMAP_OFS); - end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); - /* Cannot support multiple windows, use the wider. */ - if (end1 - start1 > end - start) { - start = start1; - end = end1; - map = map1; - } - mask = ~(start ^ end); - /* We don't support remapping with a discontiguous mask. */ - BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && - mask != ~((mask & -mask) - 1)); - gt64120_mem_resource.start = start; - gt64120_mem_resource.end = end; - gt64120_controller.mem_offset = (start & mask) - (map & mask); - /* Addresses are 36-bit, so do shifts in the destinations. */ - gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; - gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; - gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; - gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; - - start = GT_READ(GT_PCI0IOLD_OFS); - end = GT_READ(GT_PCI0IOHD_OFS); - map = GT_READ(GT_PCI0IOREMAP_OFS); - end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); - mask = ~(start ^ end); - /* We don't support remapping with a discontiguous mask. */ - BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && - mask != ~((mask & -mask) - 1)); - gt64120_io_resource.start = map & mask; - gt64120_io_resource.end = (map & mask) | ~mask; - gt64120_controller.io_offset = 0; - /* Addresses are 36-bit, so do shifts in the destinations. */ - gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; - gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; - gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; - - controller = >64120_controller; - break; - - case MIPS_REVISION_SCON_BONITO: - /* Set up resource ranges from the controller's registers. */ - map = BONITO_PCIMAP; - map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> - BONITO_PCIMAP_PCIMAP_LO0_SHIFT; - map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> - BONITO_PCIMAP_PCIMAP_LO1_SHIFT; - map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> - BONITO_PCIMAP_PCIMAP_LO2_SHIFT; - /* Combine as many adjacent windows as possible. */ - map = map1; - start = BONITO_PCILO0_BASE; - end = 1; - if (map3 == map2 + 1) { - map = map2; - start = BONITO_PCILO1_BASE; - end++; - } - if (map2 == map1 + 1) { - map = map1; - start = BONITO_PCILO0_BASE; - end++; - } - bonito64_mem_resource.start = start; - bonito64_mem_resource.end = start + - BONITO_PCIMAP_WINBASE(end) - 1; - bonito64_controller.mem_offset = start - - BONITO_PCIMAP_WINBASE(map); - - controller = &bonito64_controller; - break; - - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - /* Set up resource ranges from the controller's registers. */ - MSC_READ(MSC01_PCI_SC2PMBASL, start); - MSC_READ(MSC01_PCI_SC2PMMSKL, mask); - MSC_READ(MSC01_PCI_SC2PMMAPL, map); - msc_mem_resource.start = start & mask; - msc_mem_resource.end = (start & mask) | ~mask; - msc_controller.mem_offset = (start & mask) - (map & mask); - - MSC_READ(MSC01_PCI_SC2PIOBASL, start); - MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); - MSC_READ(MSC01_PCI_SC2PIOMAPL, map); - msc_io_resource.start = map & mask; - msc_io_resource.end = (map & mask) | ~mask; - msc_controller.io_offset = 0; - ioport_resource.end = ~mask; - - /* If ranges overlap I/O takes precedence. */ - start = start & mask; - end = start | ~mask; - if ((start >= msc_mem_resource.start && - start <= msc_mem_resource.end) || - (end >= msc_mem_resource.start && - end <= msc_mem_resource.end)) { - /* Use the larger space. */ - start = max(start, msc_mem_resource.start); - end = min(end, msc_mem_resource.end); - if (start - msc_mem_resource.start >= - msc_mem_resource.end - end) - msc_mem_resource.end = start - 1; - else - msc_mem_resource.start = end + 1; - } - - controller = &msc_controller; - break; - default: - return; - } - - if (controller->io_resource->start < 0x00001000UL) /* FIXME */ - controller->io_resource->start = 0x00001000UL; - - iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ - ioport_resource.end = controller->io_resource->end; - - register_pci_controller(controller); -} diff --git a/arch/mips/mips-boards/generic/reset.c b/arch/mips/mips-boards/generic/reset.c deleted file mode 100644 index 42dee4da37ba..000000000000 --- a/arch/mips/mips-boards/generic/reset.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Reset the MIPS boards. - * - */ -#include - -#include -#include -#include - -static void mips_machine_restart(char *command); -static void mips_machine_halt(void); - -static void mips_machine_restart(char *command) -{ - unsigned int __iomem *softres_reg = - ioremap(SOFTRES_REG, sizeof(unsigned int)); - - __raw_writel(GORESET, softres_reg); -} - -static void mips_machine_halt(void) -{ - unsigned int __iomem *softres_reg = - ioremap(SOFTRES_REG, sizeof(unsigned int)); - - __raw_writel(GORESET, softres_reg); -} - - -void mips_reboot_setup(void) -{ - _machine_restart = mips_machine_restart; - _machine_halt = mips_machine_halt; - pm_power_off = mips_machine_halt; -} diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c deleted file mode 100644 index 0b97d47691fc..000000000000 --- a/arch/mips/mips-boards/generic/time.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Setting up the clock on the MIPS boards. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -unsigned long cpu_khz; - -static int mips_cpu_timer_irq; -static int mips_cpu_perf_irq; -extern int cp0_perfcount_irq; - -static void mips_timer_dispatch(void) -{ - do_IRQ(mips_cpu_timer_irq); -} - -static void mips_perf_dispatch(void) -{ - do_IRQ(mips_cpu_perf_irq); -} - -/* - * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect - */ -static unsigned int __init estimate_cpu_frequency(void) -{ - unsigned int prid = read_c0_prid() & 0xffff00; - unsigned int count; - - unsigned long flags; - unsigned int start; - - local_irq_save(flags); - - /* Start counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - /* Start r4k counter. */ - start = read_c0_count(); - - /* Read counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - count = read_c0_count() - start; - - /* restore interrupts */ - local_irq_restore(flags); - - mips_hpt_frequency = count; - if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && - (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) - count *= 2; - - count += 5000; /* round */ - count -= count%10000; - - return count; -} - -unsigned long read_persistent_clock(void) -{ - return mc146818_get_cmos_time(); -} - -static void __init plat_perf_setup(void) -{ -#ifdef MSC01E_INT_BASE - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); - mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; - } else -#endif - if (cp0_perfcount_irq >= 0) { - if (cpu_has_vint) - set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); - mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; -#ifdef CONFIG_SMP - set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); -#endif - } -} - -unsigned int __cpuinit get_c0_compare_int(void) -{ -#ifdef MSC01E_INT_BASE - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); - mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; - } else -#endif - { - if (cpu_has_vint) - set_vi_handler(cp0_compare_irq, mips_timer_dispatch); - mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; - } - - return mips_cpu_timer_irq; -} - -void __init plat_time_init(void) -{ - unsigned int est_freq; - - /* Set Data mode - binary. */ - CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - - est_freq = estimate_cpu_frequency(); - - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, - (est_freq%1000000)*100/1000000); - - cpu_khz = est_freq / 1000; - - mips_scroll_message(); -#ifdef CONFIG_I8253 /* Only Malta has a PIT */ - setup_pit_timer(); -#endif - - plat_perf_setup(); -} diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile deleted file mode 100644 index db4ad654a6d3..000000000000 --- a/arch/mips/mips-boards/malta/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# Makefile for the MIPS Malta specific kernel interface routines -# under Linux. -# - -obj-y := malta_int.o malta_mtd.o malta_platform.o malta_setup.o - -# FIXME FIXME FIXME -obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c deleted file mode 100644 index ea176113fea9..000000000000 --- a/arch/mips/mips-boards/malta/malta_int.c +++ /dev/null @@ -1,712 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. - * Copyright (C) 2001 Ralf Baechle - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Routines for generic manipulation of the interrupts found on the MIPS - * Malta board. - * The interrupt controller is located in the South Bridge a PIIX4 device - * with two internal 82C95 interrupt controllers. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int gcmp_present = -1; -int gic_present; -static unsigned long _msc01_biu_base; -static unsigned long _gcmp_base; -static unsigned int ipi_map[NR_CPUS]; - -static DEFINE_SPINLOCK(mips_irq_lock); - -static inline int mips_pcibios_iack(void) -{ - int irq; - u32 dummy; - - /* - * Determine highest priority pending interrupt by performing - * a PCI Interrupt Acknowledge cycle. - */ - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - MSC_READ(MSC01_PCI_IACK, irq); - irq &= 0xff; - break; - case MIPS_REVISION_SCON_GT64120: - irq = GT_READ(GT_PCI0_IACK_OFS); - irq &= 0xff; - break; - case MIPS_REVISION_SCON_BONITO: - /* The following will generate a PCI IACK cycle on the - * Bonito controller. It's a little bit kludgy, but it - * was the easiest way to implement it in hardware at - * the given time. - */ - BONITO_PCIMAP_CFG = 0x20000; - - /* Flush Bonito register block */ - dummy = BONITO_PCIMAP_CFG; - iob(); /* sync */ - - irq = readl((u32 *)_pcictrl_bonito_pcicfg); - iob(); /* sync */ - irq &= 0xff; - BONITO_PCIMAP_CFG = 0; - break; - default: - printk(KERN_WARNING "Unknown system controller.\n"); - return -1; - } - return irq; -} - -static inline int get_int(void) -{ - unsigned long flags; - int irq; - spin_lock_irqsave(&mips_irq_lock, flags); - - irq = mips_pcibios_iack(); - - /* - * The only way we can decide if an interrupt is spurious - * is by checking the 8259 registers. This needs a spinlock - * on an SMP system, so leave it up to the generic code... - */ - - spin_unlock_irqrestore(&mips_irq_lock, flags); - - return irq; -} - -static void malta_hw0_irqdispatch(void) -{ - int irq; - - irq = get_int(); - if (irq < 0) { - /* interrupt has already been cleared */ - return; - } - - do_IRQ(MALTA_INT_BASE + irq); -} - -static void malta_ipi_irqdispatch(void) -{ - int irq; - - irq = gic_get_int(); - if (irq < 0) - return; /* interrupt has already been cleared */ - - do_IRQ(MIPS_GIC_IRQ_BASE + irq); -} - -static void corehi_irqdispatch(void) -{ - unsigned int intedge, intsteer, pcicmd, pcibadaddr; - unsigned int pcimstat, intisr, inten, intpol; - unsigned int intrcause, datalo, datahi; - struct pt_regs *regs = get_irq_regs(); - - printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); - printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" - "Cause : %08lx\nbadVaddr : %08lx\n", - regs->cp0_epc, regs->cp0_status, - regs->cp0_cause, regs->cp0_badvaddr); - - /* Read all the registers and then print them as there is a - problem with interspersed printk's upsetting the Bonito controller. - Do it for the others too. - */ - - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - ll_msc_irq(); - break; - case MIPS_REVISION_SCON_GT64120: - intrcause = GT_READ(GT_INTRCAUSE_OFS); - datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); - datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); - printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); - printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", - datahi, datalo); - break; - case MIPS_REVISION_SCON_BONITO: - pcibadaddr = BONITO_PCIBADADDR; - pcimstat = BONITO_PCIMSTAT; - intisr = BONITO_INTISR; - inten = BONITO_INTEN; - intpol = BONITO_INTPOL; - intedge = BONITO_INTEDGE; - intsteer = BONITO_INTSTEER; - pcicmd = BONITO_PCICMD; - printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); - printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); - printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); - printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); - printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); - printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); - printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); - printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); - break; - } - - die("CoreHi interrupt", regs); -} - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = pending & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - pending = pending << t0; - - t0 = pending & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - pending = pending << t0; - - t0 = pending & 0x8000; - t0 = t0 < 1; - /* t0 = t0 << 2; */ - a0 = a0 - t0; - /* pending = pending << t0; */ - - return a0; -#endif -} - -/* - * IRQs on the Malta board look basically (barring software IRQs which we - * don't use at all and all external interrupt sources are combined together - * on hardware interrupt 0 (MIPS IRQ 2)) like: - * - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 Combined hardware interrupt (hw0) - * 3 Hardware (ignored) - * 4 Hardware (ignored) - * 5 Hardware (ignored) - * 6 Hardware (ignored) - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Lowest ---- Combined hardware interrupt - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq == MIPSCPU_INT_I8259A) - malta_hw0_irqdispatch(); - else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()])) - malta_ipi_irqdispatch(); - else if (irq >= 0) - do_IRQ(MIPS_CPU_IRQ_BASE + irq); - else - spurious_interrupt(); -} - -#ifdef CONFIG_MIPS_MT_SMP - - -#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3 -#define GIC_MIPS_CPU_IPI_CALL_IRQ 4 - -#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ -#define C_RESCHED C_SW0 -#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ -#define C_CALL C_SW1 -static int cpu_ipi_resched_irq, cpu_ipi_call_irq; - -static void ipi_resched_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); -} - -static void ipi_call_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); -} - -static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) -{ - return IRQ_HANDLED; -} - -static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) -{ - smp_call_function_interrupt(); - - return IRQ_HANDLED; -} - -static struct irqaction irq_resched = { - .handler = ipi_resched_interrupt, - .flags = IRQF_DISABLED|IRQF_PERCPU, - .name = "IPI_resched" -}; - -static struct irqaction irq_call = { - .handler = ipi_call_interrupt, - .flags = IRQF_DISABLED|IRQF_PERCPU, - .name = "IPI_call" -}; -#endif /* CONFIG_MIPS_MT_SMP */ - -static struct irqaction i8259irq = { - .handler = no_action, - .name = "XT-PIC cascade" -}; - -static struct irqaction corehi_irqaction = { - .handler = no_action, - .name = "CoreHi" -}; - -static msc_irqmap_t __initdata msc_irqmap[] = { - {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, - {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, -}; -static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); - -static msc_irqmap_t __initdata msc_eicirqmap[] = { - {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, - {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} -}; - -static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); - -#if defined(CONFIG_MIPS_MT_SMP) -/* - * This GIC specific tabular array defines the association between External - * Interrupts and CPUs/Core Interrupts. The nature of the External - * Interrupts is also defined here - polarity/trigger. - */ -static struct gic_intr_map gic_intr_map[] = { - { GIC_EXT_INTR(0), X, X, X, X, 0 }, - { GIC_EXT_INTR(1), X, X, X, X, 0 }, - { GIC_EXT_INTR(2), X, X, X, X, 0 }, - { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(10), X, X, X, X, 0 }, - { GIC_EXT_INTR(11), X, X, X, X, 0 }, - { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(15), X, X, X, X, 0 }, - { GIC_EXT_INTR(16), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(17), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(18), 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(19), 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(20), 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(21), 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(22), 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(23), 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, -}; -#endif - -/* - * GCMP needs to be detected before any SMP initialisation - */ -static int __init gcmp_probe(unsigned long addr, unsigned long size) -{ - if (gcmp_present >= 0) - return gcmp_present; - - _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); - gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; - - if (gcmp_present) - printk(KERN_DEBUG "GCMP present\n"); - return gcmp_present; -} - -#if defined(CONFIG_MIPS_MT_SMP) -static void __init fill_ipi_map(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) { - if (gic_intr_map[i].ipiflag && (gic_intr_map[i].cpunum != X)) - ipi_map[gic_intr_map[i].cpunum] |= - (1 << (gic_intr_map[i].pin + 2)); - } -} -#endif - -void __init arch_init_irq(void) -{ - int gic_present, gcmp_present; - - init_i8259_irqs(); - - if (!cpu_has_veic) - mips_cpu_irq_init(); - - gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); - if (gcmp_present) { - GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; - gic_present = 1; - } else { - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); - gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & - MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; - } - if (gic_present) - printk(KERN_DEBUG "GIC present\n"); - - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - if (cpu_has_veic) - init_msc_irqs(MIPS_MSC01_IC_REG_BASE, - MSC01E_INT_BASE, msc_eicirqmap, - msc_nr_eicirqs); - else - init_msc_irqs(MIPS_MSC01_IC_REG_BASE, - MSC01C_INT_BASE, msc_irqmap, - msc_nr_irqs); - break; - - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - if (cpu_has_veic) - init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, - MSC01E_INT_BASE, msc_eicirqmap, - msc_nr_eicirqs); - else - init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, - MSC01C_INT_BASE, msc_irqmap, - msc_nr_irqs); - } - - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); - set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); - setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); - setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); - } else if (cpu_has_vint) { - set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); - set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); -#ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, - (0x100 << MIPSCPU_INT_I8259A)); - setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, - &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); - /* - * Temporary hack to ensure that the subsidiary device - * interrupts coing in via the i8259A, but associated - * with low IRQ numbers, will restore the Status.IM - * value associated with the i8259A. - */ - { - int i; - - for (i = 0; i < 16; i++) - irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); - } -#else /* Not SMTC */ - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, - &corehi_irqaction); -#endif /* CONFIG_MIPS_MT_SMTC */ - } else { - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, - &corehi_irqaction); - } - -#if defined(CONFIG_MIPS_MT_SMP) - if (gic_present) { - /* FIXME */ - int i; - struct { - unsigned int resched; - unsigned int call; - } ipiirq[] = { - { - .resched = GIC_IPI_EXT_INTR_RESCHED_VPE0, - .call = GIC_IPI_EXT_INTR_CALLFNC_VPE0}, - { - .resched = GIC_IPI_EXT_INTR_RESCHED_VPE1, - .call = GIC_IPI_EXT_INTR_CALLFNC_VPE1 - }, { - .resched = GIC_IPI_EXT_INTR_RESCHED_VPE2, - .call = GIC_IPI_EXT_INTR_CALLFNC_VPE2 - }, { - .resched = GIC_IPI_EXT_INTR_RESCHED_VPE3, - .call = GIC_IPI_EXT_INTR_CALLFNC_VPE3 - } - }; - fill_ipi_map(); - gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); - if (!gcmp_present) { - /* Enable the GIC */ - i = REG(_msc01_biu_base, MSC01_SC_CFG); - REG(_msc01_biu_base, MSC01_SC_CFG) = - (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); - pr_debug("GIC Enabled\n"); - } - - /* set up ipi interrupts */ - if (cpu_has_vint) { - set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); - set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); - } - /* Argh.. this really needs sorting out.. */ - printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status()); - write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); - printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); - write_c0_status(0x1100dc00); - printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); - for (i = 0; i < ARRAY_SIZE(ipiirq); i++) { - setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched); - setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call); - - set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, handle_percpu_irq); - set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].call, handle_percpu_irq); - } - } else { - /* set up ipi interrupts */ - if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); - set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); - cpu_ipi_resched_irq = MSC01E_INT_SW0; - cpu_ipi_call_irq = MSC01E_INT_SW1; - } else { - if (cpu_has_vint) { - set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); - set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); - } - cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; - cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; - } - - setup_irq(cpu_ipi_resched_irq, &irq_resched); - setup_irq(cpu_ipi_call_irq, &irq_call); - - set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); - set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); - } -#endif -} - -void malta_be_init(void) -{ - if (gcmp_present) { - /* Could change CM error mask register */ - } -} - - -static char *tr[8] = { - "mem", "gcr", "gic", "mmio", - "0x04", "0x05", "0x06", "0x07" -}; - -static char *mcmd[32] = { - [0x00] = "0x00", - [0x01] = "Legacy Write", - [0x02] = "Legacy Read", - [0x03] = "0x03", - [0x04] = "0x04", - [0x05] = "0x05", - [0x06] = "0x06", - [0x07] = "0x07", - [0x08] = "Coherent Read Own", - [0x09] = "Coherent Read Share", - [0x0a] = "Coherent Read Discard", - [0x0b] = "Coherent Ready Share Always", - [0x0c] = "Coherent Upgrade", - [0x0d] = "Coherent Writeback", - [0x0e] = "0x0e", - [0x0f] = "0x0f", - [0x10] = "Coherent Copyback", - [0x11] = "Coherent Copyback Invalidate", - [0x12] = "Coherent Invalidate", - [0x13] = "Coherent Write Invalidate", - [0x14] = "Coherent Completion Sync", - [0x15] = "0x15", - [0x16] = "0x16", - [0x17] = "0x17", - [0x18] = "0x18", - [0x19] = "0x19", - [0x1a] = "0x1a", - [0x1b] = "0x1b", - [0x1c] = "0x1c", - [0x1d] = "0x1d", - [0x1e] = "0x1e", - [0x1f] = "0x1f" -}; - -static char *core[8] = { - "Invalid/OK", "Invalid/Data", - "Shared/OK", "Shared/Data", - "Modified/OK", "Modified/Data", - "Exclusive/OK", "Exclusive/Data" -}; - -static char *causes[32] = { - "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR", - "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07", - "0x08", "0x09", "0x0a", "0x0b", - "0x0c", "0x0d", "0x0e", "0x0f", - "0x10", "0x11", "0x12", "0x13", - "0x14", "0x15", "0x16", "INTVN_WR_ERR", - "INTVN_RD_ERR", "0x19", "0x1a", "0x1b", - "0x1c", "0x1d", "0x1e", "0x1f" -}; - -int malta_be_handler(struct pt_regs *regs, int is_fixup) -{ - /* This duplicates the handling in do_be which seems wrong */ - int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; - - if (gcmp_present) { - unsigned long cm_error = GCMPGCB(GCMEC); - unsigned long cm_addr = GCMPGCB(GCMEA); - unsigned long cm_other = GCMPGCB(GCMEO); - unsigned long cause, ocause; - char buf[256]; - - cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK); - if (cause != 0) { - cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF; - if (cause < 16) { - unsigned long cca_bits = (cm_error >> 15) & 7; - unsigned long tr_bits = (cm_error >> 12) & 7; - unsigned long mcmd_bits = (cm_error >> 7) & 0x1f; - unsigned long stag_bits = (cm_error >> 3) & 15; - unsigned long sport_bits = (cm_error >> 0) & 7; - - snprintf(buf, sizeof(buf), - "CCA=%lu TR=%s MCmd=%s STag=%lu " - "SPort=%lu\n", - cca_bits, tr[tr_bits], mcmd[mcmd_bits], - stag_bits, sport_bits); - } else { - /* glob state & sresp together */ - unsigned long c3_bits = (cm_error >> 18) & 7; - unsigned long c2_bits = (cm_error >> 15) & 7; - unsigned long c1_bits = (cm_error >> 12) & 7; - unsigned long c0_bits = (cm_error >> 9) & 7; - unsigned long sc_bit = (cm_error >> 8) & 1; - unsigned long mcmd_bits = (cm_error >> 3) & 0x1f; - unsigned long sport_bits = (cm_error >> 0) & 7; - snprintf(buf, sizeof(buf), - "C3=%s C2=%s C1=%s C0=%s SC=%s " - "MCmd=%s SPort=%lu\n", - core[c3_bits], core[c2_bits], - core[c1_bits], core[c0_bits], - sc_bit ? "True" : "False", - mcmd[mcmd_bits], sport_bits); - } - - ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> - GCMP_GCB_GMEO_ERROR_2ND_SHF; - - printk("CM_ERROR=%08lx %s <%s>\n", cm_error, - causes[cause], buf); - printk("CM_ADDR =%08lx\n", cm_addr); - printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); - - /* reprime cause register */ - GCMPGCB(GCMEC) = 0; - } - } - - return retval; -} diff --git a/arch/mips/mips-boards/malta/malta_mtd.c b/arch/mips/mips-boards/malta/malta_mtd.c deleted file mode 100644 index 8ad9bdf25dce..000000000000 --- a/arch/mips/mips-boards/malta/malta_mtd.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 MIPS Technologies, Inc. - * written by Ralf Baechle - */ - -#include -#include -#include -#include -#include - -static struct mtd_partition malta_mtd_partitions[] = { - { - .name = "YAMON", - .offset = 0x0, - .size = 0x100000, - .mask_flags = MTD_WRITEABLE - }, { - .name = "User FS", - .offset = 0x100000, - .size = 0x2e0000 - }, { - .name = "Board Config", - .offset = 0x3e0000, - .size = 0x020000, - .mask_flags = MTD_WRITEABLE - } -}; - -static struct physmap_flash_data malta_flash_data = { - .width = 4, - .nr_parts = ARRAY_SIZE(malta_mtd_partitions), - .parts = malta_mtd_partitions -}; - -static struct resource malta_flash_resource = { - .start = 0x1e000000, - .end = 0x1e3fffff, - .flags = IORESOURCE_MEM -}; - -static struct platform_device malta_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &malta_flash_data, - }, - .num_resources = 1, - .resource = &malta_flash_resource, -}; - -static int __init malta_mtd_init(void) -{ - platform_device_register(&malta_flash); - - return 0; -} - -module_init(malta_mtd_init) diff --git a/arch/mips/mips-boards/malta/malta_platform.c b/arch/mips/mips-boards/malta/malta_platform.c deleted file mode 100644 index 83b9bab3cd3f..000000000000 --- a/arch/mips/mips-boards/malta/malta_platform.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 MIPS Technologies, Inc. - * written by Ralf Baechle (ralf@linux-mips.org) - * - * Probe driver for the Malta's UART ports: - * - * o 2 ports in the SMC SuperIO - * o 1 port in the CBUS UART, a discrete 16550 which normally is only used - * for bringups. - * - * We don't use 8250_platform.c on Malta as it would result in the CBUS - * UART becoming ttyS0. - */ -#include -#include -#include - -#define SMC_PORT(base, int) \ -{ \ - .iobase = base, \ - .irq = int, \ - .uartclk = 1843200, \ - .iotype = UPIO_PORT, \ - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ - .regshift = 0, \ -} - -#define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) - -static struct plat_serial8250_port uart8250_data[] = { - SMC_PORT(0x3F8, 4), - SMC_PORT(0x2F8, 3), - { - .mapbase = 0x1f000900, /* The CBUS UART */ - .irq = MIPS_CPU_IRQ_BASE + 2, - .uartclk = 3686400, /* Twice the usual clk! */ - .iotype = UPIO_MEM32, - .flags = CBUS_UART_FLAGS, - .regshift = 3, - }, - { }, -}; - -static struct platform_device uart8250_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = uart8250_data, - }, -}; - -static int __init uart8250_init(void) -{ - return platform_device_register(&uart8250_device); -} - -module_init(uart8250_init); - -MODULE_AUTHOR("Ralf Baechle "); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("8250 UART probe driver for the Malta CBUS UART"); diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c deleted file mode 100644 index e7cad54936ca..000000000000 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2008 Dmitri Vorobiev - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_VT -#include -#endif - -extern void malta_be_init(void); -extern int malta_be_handler(struct pt_regs *regs, int is_fixup); - -static struct resource standard_io_resources[] = { - { - .name = "dma1", - .start = 0x00, - .end = 0x1f, - .flags = IORESOURCE_BUSY - }, - { - .name = "timer", - .start = 0x40, - .end = 0x5f, - .flags = IORESOURCE_BUSY - }, - { - .name = "keyboard", - .start = 0x60, - .end = 0x6f, - .flags = IORESOURCE_BUSY - }, - { - .name = "dma page reg", - .start = 0x80, - .end = 0x8f, - .flags = IORESOURCE_BUSY - }, - { - .name = "dma2", - .start = 0xc0, - .end = 0xdf, - .flags = IORESOURCE_BUSY - }, -}; - -const char *get_system_type(void) -{ - return "MIPS Malta"; -} - -#if defined(CONFIG_MIPS_MT_SMTC) -const char display_string[] = " SMTC LINUX ON MALTA "; -#else -const char display_string[] = " LINUX ON MALTA "; -#endif /* CONFIG_MIPS_MT_SMTC */ - -#ifdef CONFIG_BLK_DEV_FD -static void __init fd_activate(void) -{ - /* - * Activate Floppy Controller in the SMSC FDC37M817 Super I/O - * Controller. - * Done by YAMON 2.00 onwards - */ - /* Entering config state. */ - SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); - - /* Activate floppy controller. */ - SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); - SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); - SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); - SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); - - /* Exit config state. */ - SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); -} -#endif - -#ifdef CONFIG_BLK_DEV_IDE -static void __init pci_clock_check(void) -{ - unsigned int __iomem *jmpr_p = - (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); - int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; - static const int pciclocks[] __initdata = { - 33, 20, 25, 30, 12, 16, 37, 10 - }; - int pciclock = pciclocks[jmpr]; - char *argptr = prom_getcmdline(); - - if (pciclock != 33 && !strstr(argptr, "idebus=")) { - printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " - "setting idebus\n", pciclock); - argptr += strlen(argptr); - sprintf(argptr, " idebus=%d", pciclock); - if (pciclock < 20 || pciclock > 66) - printk(KERN_WARNING "WARNING: IDE timing " - "calculations will be incorrect\n"); - } -} -#endif - -#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) -static void __init screen_info_setup(void) -{ - screen_info = (struct screen_info) { - .orig_x = 0, - .orig_y = 25, - .ext_mem_k = 0, - .orig_video_page = 0, - .orig_video_mode = 0, - .orig_video_cols = 80, - .unused2 = 0, - .orig_video_ega_bx = 0, - .unused3 = 0, - .orig_video_lines = 25, - .orig_video_isVGA = VIDEO_TYPE_VGAC, - .orig_video_points = 16 - }; -} -#endif - -static void __init bonito_quirks_setup(void) -{ - char *argptr; - - argptr = prom_getcmdline(); - if (strstr(argptr, "debug")) { - BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; - printk(KERN_INFO "Enabled Bonito debug mode\n"); - } else - BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; - -#ifdef CONFIG_DMA_COHERENT - if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { - BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; - printk(KERN_INFO "Enabled Bonito CPU coherency\n"); - - argptr = prom_getcmdline(); - if (strstr(argptr, "iobcuncached")) { - BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & - ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Disabled Bonito IOBC coherency\n"); - } else { - BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG |= - (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Enabled Bonito IOBC coherency\n"); - } - } else - panic("Hardware DMA cache coherency not supported"); -#endif -} - -void __init plat_mem_setup(void) -{ - unsigned int i; - - mips_pcibios_init(); - - /* Request I/O space for devices used on the Malta board. */ - for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) - request_resource(&ioport_resource, standard_io_resources+i); - - /* - * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. - */ - enable_dma(4); - -#ifdef CONFIG_KGDB - kgdb_config(); -#endif - -#ifdef CONFIG_DMA_COHERENT - if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) - panic("Hardware DMA cache coherency not supported"); -#endif - - if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) - bonito_quirks_setup(); - -#ifdef CONFIG_BLK_DEV_IDE - pci_clock_check(); -#endif - -#ifdef CONFIG_BLK_DEV_FD - fd_activate(); -#endif - -#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) - screen_info_setup(); -#endif - mips_reboot_setup(); - - board_be_init = malta_be_init; - board_be_handler = malta_be_handler; -} diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c deleted file mode 100644 index 5ea705e49454..000000000000 --- a/arch/mips/mips-boards/malta/malta_smtc.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Malta Platform-specific hooks for SMP operation - */ -#include -#include - -#include -#include -#include -#include - -/* VPE/SMP Prototype implements platform interfaces directly */ - -/* - * Cause the specified action to be performed on a targeted "CPU" - */ - -static void msmtc_send_ipi_single(int cpu, unsigned int action) -{ - /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ - smtc_send_ipi(cpu, LINUX_SMP_IPI, action); -} - -static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; - - for_each_cpu_mask(i, mask) - msmtc_send_ipi_single(i, action); -} - -/* - * Post-config but pre-boot cleanup entry point - */ -static void __cpuinit msmtc_init_secondary(void) -{ - void smtc_init_secondary(void); - int myvpe; - - /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ - myvpe = read_c0_tcbind() & TCBIND_CURVPE; - if (myvpe != 0) { - /* Ideally, this should be done only once per VPE, but... */ - clear_c0_status(ST0_IM); - set_c0_status((0x100 << cp0_compare_irq) - | (0x100 << MIPS_CPU_IPI_IRQ)); - if (cp0_perfcount_irq >= 0) - set_c0_status(0x100 << cp0_perfcount_irq); - } - - smtc_init_secondary(); -} - -/* - * Platform "CPU" startup hook - */ -static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle) -{ - smtc_boot_secondary(cpu, idle); -} - -/* - * SMP initialization finalization entry point - */ -static void __cpuinit msmtc_smp_finish(void) -{ - smtc_smp_finish(); -} - -/* - * Hook for after all CPUs are online - */ - -static void msmtc_cpus_done(void) -{ -} - -/* - * Platform SMP pre-initialization - * - * As noted above, we can assume a single CPU for now - * but it may be multithreaded. - */ - -static void __init msmtc_smp_setup(void) -{ - mipsmt_build_cpu_map(0); -} - -static void __init msmtc_prepare_cpus(unsigned int max_cpus) -{ - mipsmt_prepare_cpus(); -} - -struct plat_smp_ops msmtc_smp_ops = { - .send_ipi_single = msmtc_send_ipi_single, - .send_ipi_mask = msmtc_send_ipi_mask, - .init_secondary = msmtc_init_secondary, - .smp_finish = msmtc_smp_finish, - .cpus_done = msmtc_cpus_done, - .boot_secondary = msmtc_boot_secondary, - .smp_setup = msmtc_smp_setup, - .prepare_cpus = msmtc_prepare_cpus, -}; - -#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF -/* - * IRQ affinity hook - */ - - -void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity) -{ - cpumask_t tmask = affinity; - int cpu = 0; - void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); - - /* - * On the legacy Malta development board, all I/O interrupts - * are routed through the 8259 and combined in a single signal - * to the CPU daughterboard, and on the CoreFPGA2/3 34K models, - * that signal is brought to IP2 of both VPEs. To avoid racing - * concurrent interrupt service events, IP2 is enabled only on - * one VPE, by convention VPE0. So long as no bits are ever - * cleared in the affinity mask, there will never be any - * interrupt forwarding. But as soon as a program or operator - * sets affinity for one of the related IRQs, we need to make - * sure that we don't ever try to forward across the VPE boundry, - * at least not until we engineer a system where the interrupt - * _ack() or _end() function can somehow know that it corresponds - * to an interrupt taken on another VPE, and perform the appropriate - * restoration of Status.IM state using MFTR/MTTR instead of the - * normal local behavior. We also ensure that no attempt will - * be made to forward to an offline "CPU". - */ - - for_each_cpu_mask(cpu, affinity) { - if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) - cpu_clear(cpu, tmask); - } - irq_desc[irq].affinity = tmask; - - if (cpus_empty(tmask)) - /* - * We could restore a default mask here, but the - * runtime code can anyway deal with the null set - */ - printk(KERN_WARNING - "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); - - /* Do any generic SMTC IRQ affinity setup */ - smtc_set_irq_affinity(irq, tmask); -} -#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile new file mode 100644 index 000000000000..f8064446e812 --- /dev/null +++ b/arch/mips/mti-malta/Makefile @@ -0,0 +1,21 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# Copyright (C) 2008 Wind River Systems, Inc. +# written by Ralf Baechle +# +obj-y := malta-amon.o malta-cmdline.o \ + malta-display.o malta-init.o malta-int.o \ + malta-memory.o malta-mtd.o \ + malta-platform.o malta-reset.o \ + malta-setup.o malta-time.o + +obj-$(CONFIG_EARLY_PRINTK) += malta-console.o +obj-$(CONFIG_PCI) += malta-pci.o +obj-$(CONFIG_KGDB) += malta-kgdb.o + +# FIXME FIXME FIXME +obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c new file mode 100644 index 000000000000..96236bf33838 --- /dev/null +++ b/arch/mips/mti-malta/malta-amon.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2007 MIPS Technologies, Inc. + * All rights reserved. + + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Arbitrary Monitor interface + */ + +#include +#include +#include + +#include +#include +#include + +int amon_cpu_avail(int cpu) +{ + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); + + if (cpu < 0 || cpu >= NCPULAUNCH) { + pr_debug("avail: cpu%d is out of range\n", cpu); + return 0; + } + + launch += cpu; + if (!(launch->flags & LAUNCH_FREADY)) { + pr_debug("avail: cpu%d is not ready\n", cpu); + return 0; + } + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) { + pr_debug("avail: too late.. cpu%d is already gone\n", cpu); + return 0; + } + + return 1; +} + +void amon_cpu_start(int cpu, + unsigned long pc, unsigned long sp, + unsigned long gp, unsigned long a0) +{ + volatile struct cpulaunch *launch = + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); + + if (!amon_cpu_avail(cpu)) + return; + if (cpu == smp_processor_id()) { + pr_debug("launch: I am cpu%d!\n", cpu); + return; + } + launch += cpu; + + pr_debug("launch: starting cpu%d\n", cpu); + + launch->pc = pc; + launch->gp = gp; + launch->sp = sp; + launch->a0 = a0; + + /* Make sure target sees parameters before the go bit */ + smp_mb(); + + launch->flags |= LAUNCH_FGO; + while ((launch->flags & LAUNCH_FGONE) == 0) + ; + pr_debug("launch: cpu%d gone!\n", cpu); +} diff --git a/arch/mips/mti-malta/malta-cmdline.c b/arch/mips/mti-malta/malta-cmdline.c new file mode 100644 index 000000000000..1871c30ed2eb --- /dev/null +++ b/arch/mips/mti-malta/malta-cmdline.c @@ -0,0 +1,59 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Kernel command line creation using the prom monitor (YAMON) argc/argv. + */ +#include +#include + +#include + +extern int prom_argc; +extern int *_prom_argv; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) { + /* get rid of trailing space */ + --cp; + *cp = '\0'; + } +} diff --git a/arch/mips/mti-malta/malta-console.c b/arch/mips/mti-malta/malta-console.c new file mode 100644 index 000000000000..43bcfb4f8167 --- /dev/null +++ b/arch/mips/mti-malta/malta-console.c @@ -0,0 +1,47 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Putting things on the screen/serial line using YAMONs facilities. + */ +#include +#include +#include +#include + + +#define PORT(offset) (0x3f8 + (offset)) + + +static inline unsigned int serial_in(int offset) +{ + return inb(PORT(offset)); +} + +static inline void serial_out(int offset, int value) +{ + outb(value, PORT(offset)); +} + +int prom_putchar(char c) +{ + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c); + + return 1; +} diff --git a/arch/mips/mti-malta/malta-display.c b/arch/mips/mti-malta/malta-display.c new file mode 100644 index 000000000000..7c8828fcb0ad --- /dev/null +++ b/arch/mips/mti-malta/malta-display.c @@ -0,0 +1,64 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Display routines for display messages in MIPS boards ascii display. + */ + +#include +#include +#include +#include +#include + +extern const char display_string[]; +static unsigned int display_count; +static unsigned int max_display_count; + +void mips_display_message(const char *str) +{ + static unsigned int __iomem *display = NULL; + int i; + + if (unlikely(display == NULL)) + display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int)); + + for (i = 0; i <= 14; i=i+2) { + if (*str) + __raw_writel(*str++, display + i); + else + __raw_writel(' ', display + i); + } +} + +static void scroll_display_message(unsigned long data); +static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0); + +static void scroll_display_message(unsigned long data) +{ + mips_display_message(&display_string[display_count++]); + if (display_count == max_display_count) + display_count = 0; + + mod_timer(&mips_scroll_timer, jiffies + HZ); +} + +void mips_scroll_message(void) +{ + del_timer_sync(&mips_scroll_timer); + max_display_count = strlen(display_string) + 1 - 8; + mod_timer(&mips_scroll_timer, jiffies + 1); +} diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c new file mode 100644 index 000000000000..c0653021a171 --- /dev/null +++ b/arch/mips/mti-malta/malta-init.c @@ -0,0 +1,424 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library initialisation code. + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_KGDB +extern int rs_kgdb_hook(int, int); +extern int rs_putDebugChar(char); +extern char rs_getDebugChar(void); +extern int saa9730_kgdb_hook(int); +extern int saa9730_putDebugChar(char); +extern char saa9730_getDebugChar(void); +#endif + +int prom_argc; +int *_prom_argv, *_prom_envp; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension, if running in 64-bit mode. + */ +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +int init_debug = 0; + +int mips_revision_corid; +int mips_revision_sconid; + +/* Bonito64 system controller register base. */ +unsigned long _pcictrl_bonito; +unsigned long _pcictrl_bonito_pcicfg; + +/* GT64120 system controller register base */ +unsigned long _pcictrl_gt64120; + +/* MIPS System controller register base */ +unsigned long _pcictrl_msc; + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index=0; + + i = strlen(envname); + + while (prom_envp(index)) { + if(strncmp(envname, prom_envp(index), i) == 0) { + return(prom_envp(index+1)); + } + index += 2; + } + + return NULL; +} + +static inline unsigned char str2hexnum(unsigned char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return 0; /* foo */ +} + +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + + if (init_debug > 1) { + int i; + printk("get_ethernet_addr: "); + for (i=0; i<5; i++) + printk("%02x:", (unsigned char)*(ethernet_addr+i)); + printk("%02x\n", *(ethernet_addr+i)); + } + + return 0; +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static void __init console_config(void) +{ + char console_string[40]; + int baud = 0; + char parity = '\0', bits = '\0', flow = '\0'; + char *s; + + if ((strstr(prom_getcmdline(), "console=")) == NULL) { + s = prom_getenv("modetty0"); + if (s) { + while (*s >= '0' && *s <= '9') + baud = baud*10 + *s++ - '0'; + if (*s == ',') s++; + if (*s) parity = *s++; + if (*s == ',') s++; + if (*s) bits = *s++; + if (*s == ',') s++; + if (*s == 'h') flow = 'r'; + } + if (baud == 0) + baud = 38400; + if (parity != 'n' && parity != 'o' && parity != 'e') + parity = 'n'; + if (bits != '7' && bits != '8') + bits = '8'; + if (flow == '\0') + flow = 'r'; + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + strcat(prom_getcmdline(), console_string); + pr_info("Config serial console:%s\n", console_string); + } +} +#endif + +#ifdef CONFIG_KGDB +void __init kgdb_config(void) +{ + extern int (*generic_putDebugChar)(char); + extern char (*generic_getDebugChar)(void); + char *argptr; + int line, speed; + + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { + argptr += strlen("kgdb=ttyS"); + if (*argptr != '0' && *argptr != '1') + printk("KGDB: Unknown serial line /dev/ttyS%c, " + "falling back to /dev/ttyS1\n", *argptr); + line = *argptr == '0' ? 0 : 1; + printk("KGDB: Using serial line /dev/ttyS%d for session\n", line); + + speed = 0; + if (*++argptr == ',') + { + int c; + while ((c = *++argptr) && ('0' <= c && c <= '9')) + speed = speed * 10 + c - '0'; + } + { + speed = rs_kgdb_hook(line, speed); + generic_putDebugChar = rs_putDebugChar; + generic_getDebugChar = rs_getDebugChar; + } + + pr_info("KGDB: Using serial line /dev/ttyS%d at %d for " + "session, please connect your debugger\n", + line ? 1 : 0, speed); + + { + char *s; + for (s = "Please connect GDB to this port\r\n"; *s; ) + generic_putDebugChar(*s++); + } + + /* Breakpoint is invoked after interrupts are initialised */ + } +} +#endif + +static void __init mips_nmi_setup(void) +{ + void *base; + extern char except_vec_nmi; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); + memcpy(base, &except_vec_nmi, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +static void __init mips_ejtag_setup(void) +{ + void *base; + extern char except_vec_ejtag_debug; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); + memcpy(base, &except_vec_ejtag_debug, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +extern struct plat_smp_ops msmtc_smp_ops; + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + _prom_argv = (int *) fw_arg1; + _prom_envp = (int *) fw_arg2; + + mips_display_message("LINUX"); + + /* + * early setup of _pcictrl_bonito so that we can determine + * the system controller on a CORE_EMUL board + */ + _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); + + mips_revision_corid = MIPS_REVISION_CORID; + + if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { + if (BONITO_PCIDID == 0x0001df53 || + BONITO_PCIDID == 0x0003df53) + mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; + else + mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; + } + + mips_revision_sconid = MIPS_REVISION_SCONID; + if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { + switch (mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_FPGAR2: + mips_revision_sconid = MIPS_REVISION_SCON_GT64120; + break; + case MIPS_REVISION_CORID_CORE_EMUL_BON: + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + mips_revision_sconid = MIPS_REVISION_SCON_BONITO; + break; + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_24K: + /* + * SOCit/ROCit support is essentially identical + * but make an attempt to distinguish them + */ + mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; + break; + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_FPGA4: + case MIPS_REVISION_CORID_CORE_FPGA5: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: + default: + /* See above */ + mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; + break; + } + } + + switch (mips_revision_sconid) { + u32 start, map, mask, data; + + case MIPS_REVISION_SCON_GT64120: + /* + * Setup the North bridge to do Master byte-lane swapping + * when running in bigendian. + */ + _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); + +#ifdef CONFIG_CPU_LITTLE_ENDIAN + GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | + GT_PCI0_CMD_SBYTESWAP_BIT); +#else + GT_WRITE(GT_PCI0_CMD_OFS, 0); +#endif + /* Fix up PCI I/O mapping if necessary (for Atlas). */ + start = GT_READ(GT_PCI0IOLD_OFS); + map = GT_READ(GT_PCI0IOREMAP_OFS); + if ((start & map) != 0) { + map &= ~start; + GT_WRITE(GT_PCI0IOREMAP_OFS, map); + } + + set_io_port_base(MALTA_GT_PORT_BASE); + break; + + case MIPS_REVISION_SCON_BONITO: + _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); + + /* + * Disable Bonito IOBC. + */ + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + + /* + * Setup the North bridge to do Master byte-lane swapping + * when running in bigendian. + */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN + BONITO_BONGENCFG = BONITO_BONGENCFG & + ~(BONITO_BONGENCFG_MSTRBYTESWAP | + BONITO_BONGENCFG_BYTESWAP); +#else + BONITO_BONGENCFG = BONITO_BONGENCFG | + BONITO_BONGENCFG_MSTRBYTESWAP | + BONITO_BONGENCFG_BYTESWAP; +#endif + + set_io_port_base(MALTA_BONITO_PORT_BASE); + break; + + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); + mips_pci_controller: + mb(); + MSC_READ(MSC01_PCI_CFG, data); + MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); + wmb(); + + /* Fix up lane swapping. */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN + MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); +#else + MSC_WRITE(MSC01_PCI_SWAP, + MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | + MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | + MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); +#endif + /* Fix up target memory mapping. */ + MSC_READ(MSC01_PCI_BAR0, mask); + MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); + + /* Don't handle target retries indefinitely. */ + if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == + MSC01_PCI_CFG_MAXRTRY_MSK) + data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << + MSC01_PCI_CFG_MAXRTRY_SHF)) | + ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << + MSC01_PCI_CFG_MAXRTRY_SHF); + + wmb(); + MSC_WRITE(MSC01_PCI_CFG, data); + mb(); + + set_io_port_base(MALTA_MSC_PORT_BASE); + break; + + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); + goto mips_pci_controller; + + default: + /* Unknown system controller */ + mips_display_message("SC Error"); + while (1); /* We die here... */ + } + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + + pr_info("\nLINUX started...\n"); + prom_init_cmdline(); + prom_meminit(); +#ifdef CONFIG_SERIAL_8250_CONSOLE + console_config(); +#endif +#ifdef CONFIG_MIPS_CMP + register_smp_ops(&cmp_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMP + register_smp_ops(&vsmp_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&msmtc_smp_ops); +#endif +} diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c new file mode 100644 index 000000000000..ea176113fea9 --- /dev/null +++ b/arch/mips/mti-malta/malta-int.c @@ -0,0 +1,712 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines for generic manipulation of the interrupts found on the MIPS + * Malta board. + * The interrupt controller is located in the South Bridge a PIIX4 device + * with two internal 82C95 interrupt controllers. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int gcmp_present = -1; +int gic_present; +static unsigned long _msc01_biu_base; +static unsigned long _gcmp_base; +static unsigned int ipi_map[NR_CPUS]; + +static DEFINE_SPINLOCK(mips_irq_lock); + +static inline int mips_pcibios_iack(void) +{ + int irq; + u32 dummy; + + /* + * Determine highest priority pending interrupt by performing + * a PCI Interrupt Acknowledge cycle. + */ + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + MSC_READ(MSC01_PCI_IACK, irq); + irq &= 0xff; + break; + case MIPS_REVISION_SCON_GT64120: + irq = GT_READ(GT_PCI0_IACK_OFS); + irq &= 0xff; + break; + case MIPS_REVISION_SCON_BONITO: + /* The following will generate a PCI IACK cycle on the + * Bonito controller. It's a little bit kludgy, but it + * was the easiest way to implement it in hardware at + * the given time. + */ + BONITO_PCIMAP_CFG = 0x20000; + + /* Flush Bonito register block */ + dummy = BONITO_PCIMAP_CFG; + iob(); /* sync */ + + irq = readl((u32 *)_pcictrl_bonito_pcicfg); + iob(); /* sync */ + irq &= 0xff; + BONITO_PCIMAP_CFG = 0; + break; + default: + printk(KERN_WARNING "Unknown system controller.\n"); + return -1; + } + return irq; +} + +static inline int get_int(void) +{ + unsigned long flags; + int irq; + spin_lock_irqsave(&mips_irq_lock, flags); + + irq = mips_pcibios_iack(); + + /* + * The only way we can decide if an interrupt is spurious + * is by checking the 8259 registers. This needs a spinlock + * on an SMP system, so leave it up to the generic code... + */ + + spin_unlock_irqrestore(&mips_irq_lock, flags); + + return irq; +} + +static void malta_hw0_irqdispatch(void) +{ + int irq; + + irq = get_int(); + if (irq < 0) { + /* interrupt has already been cleared */ + return; + } + + do_IRQ(MALTA_INT_BASE + irq); +} + +static void malta_ipi_irqdispatch(void) +{ + int irq; + + irq = gic_get_int(); + if (irq < 0) + return; /* interrupt has already been cleared */ + + do_IRQ(MIPS_GIC_IRQ_BASE + irq); +} + +static void corehi_irqdispatch(void) +{ + unsigned int intedge, intsteer, pcicmd, pcibadaddr; + unsigned int pcimstat, intisr, inten, intpol; + unsigned int intrcause, datalo, datahi; + struct pt_regs *regs = get_irq_regs(); + + printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); + printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" + "Cause : %08lx\nbadVaddr : %08lx\n", + regs->cp0_epc, regs->cp0_status, + regs->cp0_cause, regs->cp0_badvaddr); + + /* Read all the registers and then print them as there is a + problem with interspersed printk's upsetting the Bonito controller. + Do it for the others too. + */ + + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + ll_msc_irq(); + break; + case MIPS_REVISION_SCON_GT64120: + intrcause = GT_READ(GT_INTRCAUSE_OFS); + datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); + datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); + printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); + printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", + datahi, datalo); + break; + case MIPS_REVISION_SCON_BONITO: + pcibadaddr = BONITO_PCIBADADDR; + pcimstat = BONITO_PCIMSTAT; + intisr = BONITO_INTISR; + inten = BONITO_INTEN; + intpol = BONITO_INTPOL; + intedge = BONITO_INTEDGE; + intsteer = BONITO_INTSTEER; + pcicmd = BONITO_PCICMD; + printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); + printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); + printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); + printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); + printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); + printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); + printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); + printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); + break; + } + + die("CoreHi interrupt", regs); +} + +static inline int clz(unsigned long x) +{ + __asm__( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (x) + : "r" (x)); + + return x; +} + +/* + * Version of ffs that only looks at bits 12..15. + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + return -clz(pending) + 31 - CAUSEB_IP; +#else + unsigned int a0 = 7; + unsigned int t0; + + t0 = pending & 0xf000; + t0 = t0 < 1; + t0 = t0 << 2; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0xc000; + t0 = t0 < 1; + t0 = t0 << 1; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0x8000; + t0 = t0 < 1; + /* t0 = t0 << 2; */ + a0 = a0 - t0; + /* pending = pending << t0; */ + + return a0; +#endif +} + +/* + * IRQs on the Malta board look basically (barring software IRQs which we + * don't use at all and all external interrupt sources are combined together + * on hardware interrupt 0 (MIPS IRQ 2)) like: + * + * MIPS IRQ Source + * -------- ------ + * 0 Software (ignored) + * 1 Software (ignored) + * 2 Combined hardware interrupt (hw0) + * 3 Hardware (ignored) + * 4 Hardware (ignored) + * 5 Hardware (ignored) + * 6 Hardware (ignored) + * 7 R4k timer (what we use) + * + * We handle the IRQ according to _our_ priority which is: + * + * Highest ---- R4k Timer + * Lowest ---- Combined hardware interrupt + * + * then we just return, if multiple IRQs are pending then we will just take + * another exception, big deal. + */ + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = irq_ffs(pending); + + if (irq == MIPSCPU_INT_I8259A) + malta_hw0_irqdispatch(); + else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()])) + malta_ipi_irqdispatch(); + else if (irq >= 0) + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + else + spurious_interrupt(); +} + +#ifdef CONFIG_MIPS_MT_SMP + + +#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3 +#define GIC_MIPS_CPU_IPI_CALL_IRQ 4 + +#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ +#define C_RESCHED C_SW0 +#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ +#define C_CALL C_SW1 +static int cpu_ipi_resched_irq, cpu_ipi_call_irq; + +static void ipi_resched_dispatch(void) +{ + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); +} + +static void ipi_call_dispatch(void) +{ + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); +} + +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) +{ + smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +static struct irqaction irq_resched = { + .handler = ipi_resched_interrupt, + .flags = IRQF_DISABLED|IRQF_PERCPU, + .name = "IPI_resched" +}; + +static struct irqaction irq_call = { + .handler = ipi_call_interrupt, + .flags = IRQF_DISABLED|IRQF_PERCPU, + .name = "IPI_call" +}; +#endif /* CONFIG_MIPS_MT_SMP */ + +static struct irqaction i8259irq = { + .handler = no_action, + .name = "XT-PIC cascade" +}; + +static struct irqaction corehi_irqaction = { + .handler = no_action, + .name = "CoreHi" +}; + +static msc_irqmap_t __initdata msc_irqmap[] = { + {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, + {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, +}; +static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); + +static msc_irqmap_t __initdata msc_eicirqmap[] = { + {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, + {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} +}; + +static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); + +#if defined(CONFIG_MIPS_MT_SMP) +/* + * This GIC specific tabular array defines the association between External + * Interrupts and CPUs/Core Interrupts. The nature of the External + * Interrupts is also defined here - polarity/trigger. + */ +static struct gic_intr_map gic_intr_map[] = { + { GIC_EXT_INTR(0), X, X, X, X, 0 }, + { GIC_EXT_INTR(1), X, X, X, X, 0 }, + { GIC_EXT_INTR(2), X, X, X, X, 0 }, + { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(10), X, X, X, X, 0 }, + { GIC_EXT_INTR(11), X, X, X, X, 0 }, + { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(15), X, X, X, X, 0 }, + { GIC_EXT_INTR(16), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(17), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(18), 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(19), 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(20), 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(21), 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(22), 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(23), 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, +}; +#endif + +/* + * GCMP needs to be detected before any SMP initialisation + */ +static int __init gcmp_probe(unsigned long addr, unsigned long size) +{ + if (gcmp_present >= 0) + return gcmp_present; + + _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); + _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); + gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; + + if (gcmp_present) + printk(KERN_DEBUG "GCMP present\n"); + return gcmp_present; +} + +#if defined(CONFIG_MIPS_MT_SMP) +static void __init fill_ipi_map(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) { + if (gic_intr_map[i].ipiflag && (gic_intr_map[i].cpunum != X)) + ipi_map[gic_intr_map[i].cpunum] |= + (1 << (gic_intr_map[i].pin + 2)); + } +} +#endif + +void __init arch_init_irq(void) +{ + int gic_present, gcmp_present; + + init_i8259_irqs(); + + if (!cpu_has_veic) + mips_cpu_irq_init(); + + gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); + if (gcmp_present) { + GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; + gic_present = 1; + } else { + _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); + gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & + MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; + } + if (gic_present) + printk(KERN_DEBUG "GIC present\n"); + + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + if (cpu_has_veic) + init_msc_irqs(MIPS_MSC01_IC_REG_BASE, + MSC01E_INT_BASE, msc_eicirqmap, + msc_nr_eicirqs); + else + init_msc_irqs(MIPS_MSC01_IC_REG_BASE, + MSC01C_INT_BASE, msc_irqmap, + msc_nr_irqs); + break; + + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + if (cpu_has_veic) + init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, + MSC01E_INT_BASE, msc_eicirqmap, + msc_nr_eicirqs); + else + init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, + MSC01C_INT_BASE, msc_irqmap, + msc_nr_irqs); + } + + if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); + setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); + setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); + } else if (cpu_has_vint) { + set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); +#ifdef CONFIG_MIPS_MT_SMTC + setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, + (0x100 << MIPSCPU_INT_I8259A)); + setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, + &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); + /* + * Temporary hack to ensure that the subsidiary device + * interrupts coing in via the i8259A, but associated + * with low IRQ numbers, will restore the Status.IM + * value associated with the i8259A. + */ + { + int i; + + for (i = 0; i < 16; i++) + irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); + } +#else /* Not SMTC */ + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, + &corehi_irqaction); +#endif /* CONFIG_MIPS_MT_SMTC */ + } else { + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, + &corehi_irqaction); + } + +#if defined(CONFIG_MIPS_MT_SMP) + if (gic_present) { + /* FIXME */ + int i; + struct { + unsigned int resched; + unsigned int call; + } ipiirq[] = { + { + .resched = GIC_IPI_EXT_INTR_RESCHED_VPE0, + .call = GIC_IPI_EXT_INTR_CALLFNC_VPE0}, + { + .resched = GIC_IPI_EXT_INTR_RESCHED_VPE1, + .call = GIC_IPI_EXT_INTR_CALLFNC_VPE1 + }, { + .resched = GIC_IPI_EXT_INTR_RESCHED_VPE2, + .call = GIC_IPI_EXT_INTR_CALLFNC_VPE2 + }, { + .resched = GIC_IPI_EXT_INTR_RESCHED_VPE3, + .call = GIC_IPI_EXT_INTR_CALLFNC_VPE3 + } + }; + fill_ipi_map(); + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); + if (!gcmp_present) { + /* Enable the GIC */ + i = REG(_msc01_biu_base, MSC01_SC_CFG); + REG(_msc01_biu_base, MSC01_SC_CFG) = + (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); + pr_debug("GIC Enabled\n"); + } + + /* set up ipi interrupts */ + if (cpu_has_vint) { + set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); + set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); + } + /* Argh.. this really needs sorting out.. */ + printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status()); + write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); + printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); + write_c0_status(0x1100dc00); + printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); + for (i = 0; i < ARRAY_SIZE(ipiirq); i++) { + setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched); + setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call); + + set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, handle_percpu_irq); + set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].call, handle_percpu_irq); + } + } else { + /* set up ipi interrupts */ + if (cpu_has_veic) { + set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); + set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); + cpu_ipi_resched_irq = MSC01E_INT_SW0; + cpu_ipi_call_irq = MSC01E_INT_SW1; + } else { + if (cpu_has_vint) { + set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); + set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); + } + cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; + cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; + } + + setup_irq(cpu_ipi_resched_irq, &irq_resched); + setup_irq(cpu_ipi_call_irq, &irq_call); + + set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); + set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); + } +#endif +} + +void malta_be_init(void) +{ + if (gcmp_present) { + /* Could change CM error mask register */ + } +} + + +static char *tr[8] = { + "mem", "gcr", "gic", "mmio", + "0x04", "0x05", "0x06", "0x07" +}; + +static char *mcmd[32] = { + [0x00] = "0x00", + [0x01] = "Legacy Write", + [0x02] = "Legacy Read", + [0x03] = "0x03", + [0x04] = "0x04", + [0x05] = "0x05", + [0x06] = "0x06", + [0x07] = "0x07", + [0x08] = "Coherent Read Own", + [0x09] = "Coherent Read Share", + [0x0a] = "Coherent Read Discard", + [0x0b] = "Coherent Ready Share Always", + [0x0c] = "Coherent Upgrade", + [0x0d] = "Coherent Writeback", + [0x0e] = "0x0e", + [0x0f] = "0x0f", + [0x10] = "Coherent Copyback", + [0x11] = "Coherent Copyback Invalidate", + [0x12] = "Coherent Invalidate", + [0x13] = "Coherent Write Invalidate", + [0x14] = "Coherent Completion Sync", + [0x15] = "0x15", + [0x16] = "0x16", + [0x17] = "0x17", + [0x18] = "0x18", + [0x19] = "0x19", + [0x1a] = "0x1a", + [0x1b] = "0x1b", + [0x1c] = "0x1c", + [0x1d] = "0x1d", + [0x1e] = "0x1e", + [0x1f] = "0x1f" +}; + +static char *core[8] = { + "Invalid/OK", "Invalid/Data", + "Shared/OK", "Shared/Data", + "Modified/OK", "Modified/Data", + "Exclusive/OK", "Exclusive/Data" +}; + +static char *causes[32] = { + "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR", + "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07", + "0x08", "0x09", "0x0a", "0x0b", + "0x0c", "0x0d", "0x0e", "0x0f", + "0x10", "0x11", "0x12", "0x13", + "0x14", "0x15", "0x16", "INTVN_WR_ERR", + "INTVN_RD_ERR", "0x19", "0x1a", "0x1b", + "0x1c", "0x1d", "0x1e", "0x1f" +}; + +int malta_be_handler(struct pt_regs *regs, int is_fixup) +{ + /* This duplicates the handling in do_be which seems wrong */ + int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; + + if (gcmp_present) { + unsigned long cm_error = GCMPGCB(GCMEC); + unsigned long cm_addr = GCMPGCB(GCMEA); + unsigned long cm_other = GCMPGCB(GCMEO); + unsigned long cause, ocause; + char buf[256]; + + cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK); + if (cause != 0) { + cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF; + if (cause < 16) { + unsigned long cca_bits = (cm_error >> 15) & 7; + unsigned long tr_bits = (cm_error >> 12) & 7; + unsigned long mcmd_bits = (cm_error >> 7) & 0x1f; + unsigned long stag_bits = (cm_error >> 3) & 15; + unsigned long sport_bits = (cm_error >> 0) & 7; + + snprintf(buf, sizeof(buf), + "CCA=%lu TR=%s MCmd=%s STag=%lu " + "SPort=%lu\n", + cca_bits, tr[tr_bits], mcmd[mcmd_bits], + stag_bits, sport_bits); + } else { + /* glob state & sresp together */ + unsigned long c3_bits = (cm_error >> 18) & 7; + unsigned long c2_bits = (cm_error >> 15) & 7; + unsigned long c1_bits = (cm_error >> 12) & 7; + unsigned long c0_bits = (cm_error >> 9) & 7; + unsigned long sc_bit = (cm_error >> 8) & 1; + unsigned long mcmd_bits = (cm_error >> 3) & 0x1f; + unsigned long sport_bits = (cm_error >> 0) & 7; + snprintf(buf, sizeof(buf), + "C3=%s C2=%s C1=%s C0=%s SC=%s " + "MCmd=%s SPort=%lu\n", + core[c3_bits], core[c2_bits], + core[c1_bits], core[c0_bits], + sc_bit ? "True" : "False", + mcmd[mcmd_bits], sport_bits); + } + + ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> + GCMP_GCB_GMEO_ERROR_2ND_SHF; + + printk("CM_ERROR=%08lx %s <%s>\n", cm_error, + causes[cause], buf); + printk("CM_ADDR =%08lx\n", cm_addr); + printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); + + /* reprime cause register */ + GCMPGCB(GCMEC) = 0; + } + } + + return retval; +} diff --git a/arch/mips/mti-malta/malta-kgdb.c b/arch/mips/mti-malta/malta-kgdb.c new file mode 100644 index 000000000000..6a1854de4579 --- /dev/null +++ b/arch/mips/mti-malta/malta-kgdb.c @@ -0,0 +1,133 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * This is the interface to the remote debugger stub. + */ +#include +#include +#include +#include + +#include +#include + +static struct serial_state rs_table[] = { + SERIAL_PORT_DFNS /* Defined in serial.h */ +}; + +static struct async_struct kdb_port_info = {0}; + +int (*generic_putDebugChar)(char); +char (*generic_getDebugChar)(void); + +static __inline__ unsigned int serial_in(struct async_struct *info, int offset) +{ + return inb(info->port + offset); +} + +static __inline__ void serial_out(struct async_struct *info, int offset, + int value) +{ + outb(value, info->port+offset); +} + +int rs_kgdb_hook(int tty_no, int speed) { + int t; + struct serial_state *ser = &rs_table[tty_no]; + + kdb_port_info.state = ser; + kdb_port_info.magic = SERIAL_MAGIC; + kdb_port_info.port = ser->port; + kdb_port_info.flags = ser->flags; + + /* + * Clear all interrupts + */ + serial_in(&kdb_port_info, UART_LSR); + serial_in(&kdb_port_info, UART_RX); + serial_in(&kdb_port_info, UART_IIR); + serial_in(&kdb_port_info, UART_MSR); + + /* + * Now, initialize the UART + */ + serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ + if (kdb_port_info.flags & ASYNC_FOURPORT) { + kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS; + t = UART_MCR_DTR | UART_MCR_OUT1; + } else { + kdb_port_info.MCR + = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; + t = UART_MCR_DTR | UART_MCR_RTS; + } + + kdb_port_info.MCR = t; /* no interrupts, please */ + serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR); + + /* + * and set the speed of the serial port + */ + if (speed == 0) + speed = 9600; + + t = kdb_port_info.state->baud_base / speed; + /* set DLAB */ + serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB); + serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */ + serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */ + /* reset DLAB */ + serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); + + return speed; +} + +int putDebugChar(char c) +{ + return generic_putDebugChar(c); +} + +char getDebugChar(void) +{ + return generic_getDebugChar(); +} + +int rs_putDebugChar(char c) +{ + + if (!kdb_port_info.state) { /* need to init device first */ + return 0; + } + + while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(&kdb_port_info, UART_TX, c); + + return 1; +} + +char rs_getDebugChar(void) +{ + if (!kdb_port_info.state) { /* need to init device first */ + return 0; + } + + while (!(serial_in(&kdb_port_info, UART_LSR) & 1)) + ; + + return serial_in(&kdb_port_info, UART_RX); +} diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c new file mode 100644 index 000000000000..61888ff72c87 --- /dev/null +++ b/arch/mips/mti-malta/malta-memory.c @@ -0,0 +1,177 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library functions for acquiring/using memory descriptors given to + * us from the YAMON. + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/*#define DEBUG*/ + +enum yamon_memtypes { + yamon_dontuse, + yamon_prom, + yamon_free, +}; +static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +#ifdef DEBUG +static char *mtypes[3] = { + "Dont use memory", + "YAMON PROM memory", + "Free memmory", +}; +#endif + +/* determined physical memory size, not overridden by command line args */ +unsigned long physical_memsize = 0L; + +static struct prom_pmemblock * __init prom_getmdesc(void) +{ + char *memsize_str; + unsigned int memsize; + char cmdline[CL_SIZE], *ptr; + + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + printk(KERN_WARNING + "memsize not set in boot prom, set to default (32Mb)\n"); + physical_memsize = 0x02000000; + } else { +#ifdef DEBUG + pr_debug("prom_memsize = %s\n", memsize_str); +#endif + physical_memsize = simple_strtol(memsize_str, NULL, 0); + } + +#ifdef CONFIG_CPU_BIG_ENDIAN + /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last + word of physical memory */ + physical_memsize -= PAGE_SIZE; +#endif + + /* Check the command line for a memsize directive that overrides + the physical/default amount */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) + memsize = memparse(ptr + 8, &ptr); + else + memsize = physical_memsize; + + memset(mdesc, 0, sizeof(mdesc)); + + mdesc[0].type = yamon_dontuse; + mdesc[0].base = 0x00000000; + mdesc[0].size = 0x00001000; + + mdesc[1].type = yamon_prom; + mdesc[1].base = 0x00001000; + mdesc[1].size = 0x000ef000; + + /* + * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the + * south bridge and PCI access always forwarded to the ISA Bus and + * BIOSCS# is always generated. + * This mean that this area can't be used as DMA memory for PCI + * devices. + */ + mdesc[2].type = yamon_dontuse; + mdesc[2].base = 0x000f0000; + mdesc[2].size = 0x00010000; + + mdesc[3].type = yamon_dontuse; + mdesc[3].base = 0x00100000; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; + + mdesc[4].type = yamon_free; + mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[4].size = memsize - mdesc[4].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify(unsigned int type) +{ + switch (type) { + case yamon_free: + return BOOT_MEM_RAM; + case yamon_prom: + return BOOT_MEM_ROM_DATA; + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + +#ifdef DEBUG + pr_debug("YAMON MEMORY DESCRIPTOR dump:\n"); + p = prom_getmdesc(); + while (p->size) { + int i = 0; + pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", + i, p, p->base, p->size, mtypes[p->type]); + p++; + i++; + } +#endif + p = prom_getmdesc(); + + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify(p->type); + base = p->base; + size = p->size; + + add_memory_region(base, size, type); + p++; + } +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/mti-malta/malta-mtd.c b/arch/mips/mti-malta/malta-mtd.c new file mode 100644 index 000000000000..8ad9bdf25dce --- /dev/null +++ b/arch/mips/mti-malta/malta-mtd.c @@ -0,0 +1,63 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 MIPS Technologies, Inc. + * written by Ralf Baechle + */ + +#include +#include +#include +#include +#include + +static struct mtd_partition malta_mtd_partitions[] = { + { + .name = "YAMON", + .offset = 0x0, + .size = 0x100000, + .mask_flags = MTD_WRITEABLE + }, { + .name = "User FS", + .offset = 0x100000, + .size = 0x2e0000 + }, { + .name = "Board Config", + .offset = 0x3e0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE + } +}; + +static struct physmap_flash_data malta_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(malta_mtd_partitions), + .parts = malta_mtd_partitions +}; + +static struct resource malta_flash_resource = { + .start = 0x1e000000, + .end = 0x1e3fffff, + .flags = IORESOURCE_MEM +}; + +static struct platform_device malta_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &malta_flash_data, + }, + .num_resources = 1, + .resource = &malta_flash_resource, +}; + +static int __init malta_mtd_init(void) +{ + platform_device_register(&malta_flash); + + return 0; +} + +module_init(malta_mtd_init) diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c new file mode 100644 index 000000000000..b9743190609a --- /dev/null +++ b/arch/mips/mti-malta/malta-pci.c @@ -0,0 +1,243 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * MIPS boards specific PCI support. + */ +#include +#include +#include +#include + +#include + +#include +#include +#include + +static struct resource bonito64_mem_resource = { + .name = "Bonito PCI MEM", + .flags = IORESOURCE_MEM, +}; + +static struct resource bonito64_io_resource = { + .name = "Bonito PCI I/O", + .start = 0x00000000UL, + .end = 0x000fffffUL, + .flags = IORESOURCE_IO, +}; + +static struct resource gt64120_mem_resource = { + .name = "GT-64120 PCI MEM", + .flags = IORESOURCE_MEM, +}; + +static struct resource gt64120_io_resource = { + .name = "GT-64120 PCI I/O", + .flags = IORESOURCE_IO, +}; + +static struct resource msc_mem_resource = { + .name = "MSC PCI MEM", + .flags = IORESOURCE_MEM, +}; + +static struct resource msc_io_resource = { + .name = "MSC PCI I/O", + .flags = IORESOURCE_IO, +}; + +extern struct pci_ops bonito64_pci_ops; +extern struct pci_ops gt64xxx_pci0_ops; +extern struct pci_ops msc_pci_ops; + +static struct pci_controller bonito64_controller = { + .pci_ops = &bonito64_pci_ops, + .io_resource = &bonito64_io_resource, + .mem_resource = &bonito64_mem_resource, + .io_offset = 0x00000000UL, +}; + +static struct pci_controller gt64120_controller = { + .pci_ops = >64xxx_pci0_ops, + .io_resource = >64120_io_resource, + .mem_resource = >64120_mem_resource, +}; + +static struct pci_controller msc_controller = { + .pci_ops = &msc_pci_ops, + .io_resource = &msc_io_resource, + .mem_resource = &msc_mem_resource, +}; + +void __init mips_pcibios_init(void) +{ + struct pci_controller *controller; + resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; + + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_GT64120: + /* + * Due to a bug in the Galileo system controller, we need + * to setup the PCI BAR for the Galileo internal registers. + * This should be done in the bios/bootprom and will be + * fixed in a later revision of YAMON (the MIPS boards + * boot prom). + */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ + (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ + ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + /* Perform the write */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); + + /* Set up resource ranges from the controller's registers. */ + start = GT_READ(GT_PCI0M0LD_OFS); + end = GT_READ(GT_PCI0M0HD_OFS); + map = GT_READ(GT_PCI0M0REMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + start1 = GT_READ(GT_PCI0M1LD_OFS); + end1 = GT_READ(GT_PCI0M1HD_OFS); + map1 = GT_READ(GT_PCI0M1REMAP_OFS); + end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); + /* Cannot support multiple windows, use the wider. */ + if (end1 - start1 > end - start) { + start = start1; + end = end1; + map = map1; + } + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_mem_resource.start = start; + gt64120_mem_resource.end = end; + gt64120_controller.mem_offset = (start & mask) - (map & mask); + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; + + start = GT_READ(GT_PCI0IOLD_OFS); + end = GT_READ(GT_PCI0IOHD_OFS); + map = GT_READ(GT_PCI0IOREMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_io_resource.start = map & mask; + gt64120_io_resource.end = (map & mask) | ~mask; + gt64120_controller.io_offset = 0; + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + + controller = >64120_controller; + break; + + case MIPS_REVISION_SCON_BONITO: + /* Set up resource ranges from the controller's registers. */ + map = BONITO_PCIMAP; + map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> + BONITO_PCIMAP_PCIMAP_LO0_SHIFT; + map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> + BONITO_PCIMAP_PCIMAP_LO1_SHIFT; + map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> + BONITO_PCIMAP_PCIMAP_LO2_SHIFT; + /* Combine as many adjacent windows as possible. */ + map = map1; + start = BONITO_PCILO0_BASE; + end = 1; + if (map3 == map2 + 1) { + map = map2; + start = BONITO_PCILO1_BASE; + end++; + } + if (map2 == map1 + 1) { + map = map1; + start = BONITO_PCILO0_BASE; + end++; + } + bonito64_mem_resource.start = start; + bonito64_mem_resource.end = start + + BONITO_PCIMAP_WINBASE(end) - 1; + bonito64_controller.mem_offset = start - + BONITO_PCIMAP_WINBASE(map); + + controller = &bonito64_controller; + break; + + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + /* Set up resource ranges from the controller's registers. */ + MSC_READ(MSC01_PCI_SC2PMBASL, start); + MSC_READ(MSC01_PCI_SC2PMMSKL, mask); + MSC_READ(MSC01_PCI_SC2PMMAPL, map); + msc_mem_resource.start = start & mask; + msc_mem_resource.end = (start & mask) | ~mask; + msc_controller.mem_offset = (start & mask) - (map & mask); + + MSC_READ(MSC01_PCI_SC2PIOBASL, start); + MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); + MSC_READ(MSC01_PCI_SC2PIOMAPL, map); + msc_io_resource.start = map & mask; + msc_io_resource.end = (map & mask) | ~mask; + msc_controller.io_offset = 0; + ioport_resource.end = ~mask; + + /* If ranges overlap I/O takes precedence. */ + start = start & mask; + end = start | ~mask; + if ((start >= msc_mem_resource.start && + start <= msc_mem_resource.end) || + (end >= msc_mem_resource.start && + end <= msc_mem_resource.end)) { + /* Use the larger space. */ + start = max(start, msc_mem_resource.start); + end = min(end, msc_mem_resource.end); + if (start - msc_mem_resource.start >= + msc_mem_resource.end - end) + msc_mem_resource.end = start - 1; + else + msc_mem_resource.start = end + 1; + } + + controller = &msc_controller; + break; + default: + return; + } + + if (controller->io_resource->start < 0x00001000UL) /* FIXME */ + controller->io_resource->start = 0x00001000UL; + + iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ + ioport_resource.end = controller->io_resource->end; + + register_pci_controller(controller); +} diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c new file mode 100644 index 000000000000..83b9bab3cd3f --- /dev/null +++ b/arch/mips/mti-malta/malta-platform.c @@ -0,0 +1,65 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 MIPS Technologies, Inc. + * written by Ralf Baechle (ralf@linux-mips.org) + * + * Probe driver for the Malta's UART ports: + * + * o 2 ports in the SMC SuperIO + * o 1 port in the CBUS UART, a discrete 16550 which normally is only used + * for bringups. + * + * We don't use 8250_platform.c on Malta as it would result in the CBUS + * UART becoming ttyS0. + */ +#include +#include +#include + +#define SMC_PORT(base, int) \ +{ \ + .iobase = base, \ + .irq = int, \ + .uartclk = 1843200, \ + .iotype = UPIO_PORT, \ + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ + .regshift = 0, \ +} + +#define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) + +static struct plat_serial8250_port uart8250_data[] = { + SMC_PORT(0x3F8, 4), + SMC_PORT(0x2F8, 3), + { + .mapbase = 0x1f000900, /* The CBUS UART */ + .irq = MIPS_CPU_IRQ_BASE + 2, + .uartclk = 3686400, /* Twice the usual clk! */ + .iotype = UPIO_MEM32, + .flags = CBUS_UART_FLAGS, + .regshift = 3, + }, + { }, +}; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Ralf Baechle "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for the Malta CBUS UART"); diff --git a/arch/mips/mti-malta/malta-reset.c b/arch/mips/mti-malta/malta-reset.c new file mode 100644 index 000000000000..42dee4da37ba --- /dev/null +++ b/arch/mips/mti-malta/malta-reset.c @@ -0,0 +1,56 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Reset the MIPS boards. + * + */ +#include + +#include +#include +#include + +static void mips_machine_restart(char *command); +static void mips_machine_halt(void); + +static void mips_machine_restart(char *command) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + +static void mips_machine_halt(void) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + + +void mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; + _machine_halt = mips_machine_halt; + pm_power_off = mips_machine_halt; +} diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c new file mode 100644 index 000000000000..e7cad54936ca --- /dev/null +++ b/arch/mips/mti-malta/malta-setup.c @@ -0,0 +1,229 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2008 Dmitri Vorobiev + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_VT +#include +#endif + +extern void malta_be_init(void); +extern int malta_be_handler(struct pt_regs *regs, int is_fixup); + +static struct resource standard_io_resources[] = { + { + .name = "dma1", + .start = 0x00, + .end = 0x1f, + .flags = IORESOURCE_BUSY + }, + { + .name = "timer", + .start = 0x40, + .end = 0x5f, + .flags = IORESOURCE_BUSY + }, + { + .name = "keyboard", + .start = 0x60, + .end = 0x6f, + .flags = IORESOURCE_BUSY + }, + { + .name = "dma page reg", + .start = 0x80, + .end = 0x8f, + .flags = IORESOURCE_BUSY + }, + { + .name = "dma2", + .start = 0xc0, + .end = 0xdf, + .flags = IORESOURCE_BUSY + }, +}; + +const char *get_system_type(void) +{ + return "MIPS Malta"; +} + +#if defined(CONFIG_MIPS_MT_SMTC) +const char display_string[] = " SMTC LINUX ON MALTA "; +#else +const char display_string[] = " LINUX ON MALTA "; +#endif /* CONFIG_MIPS_MT_SMTC */ + +#ifdef CONFIG_BLK_DEV_FD +static void __init fd_activate(void) +{ + /* + * Activate Floppy Controller in the SMSC FDC37M817 Super I/O + * Controller. + * Done by YAMON 2.00 onwards + */ + /* Entering config state. */ + SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); + + /* Activate floppy controller. */ + SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); + SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); + SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); + SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); + + /* Exit config state. */ + SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); +} +#endif + +#ifdef CONFIG_BLK_DEV_IDE +static void __init pci_clock_check(void) +{ + unsigned int __iomem *jmpr_p = + (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); + int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; + static const int pciclocks[] __initdata = { + 33, 20, 25, 30, 12, 16, 37, 10 + }; + int pciclock = pciclocks[jmpr]; + char *argptr = prom_getcmdline(); + + if (pciclock != 33 && !strstr(argptr, "idebus=")) { + printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " + "setting idebus\n", pciclock); + argptr += strlen(argptr); + sprintf(argptr, " idebus=%d", pciclock); + if (pciclock < 20 || pciclock > 66) + printk(KERN_WARNING "WARNING: IDE timing " + "calculations will be incorrect\n"); + } +} +#endif + +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) +static void __init screen_info_setup(void) +{ + screen_info = (struct screen_info) { + .orig_x = 0, + .orig_y = 25, + .ext_mem_k = 0, + .orig_video_page = 0, + .orig_video_mode = 0, + .orig_video_cols = 80, + .unused2 = 0, + .orig_video_ega_bx = 0, + .unused3 = 0, + .orig_video_lines = 25, + .orig_video_isVGA = VIDEO_TYPE_VGAC, + .orig_video_points = 16 + }; +} +#endif + +static void __init bonito_quirks_setup(void) +{ + char *argptr; + + argptr = prom_getcmdline(); + if (strstr(argptr, "debug")) { + BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; + printk(KERN_INFO "Enabled Bonito debug mode\n"); + } else + BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; + +#ifdef CONFIG_DMA_COHERENT + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + printk(KERN_INFO "Enabled Bonito CPU coherency\n"); + + argptr = prom_getcmdline(); + if (strstr(argptr, "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + printk(KERN_INFO "Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + printk(KERN_INFO "Enabled Bonito IOBC coherency\n"); + } + } else + panic("Hardware DMA cache coherency not supported"); +#endif +} + +void __init plat_mem_setup(void) +{ + unsigned int i; + + mips_pcibios_init(); + + /* Request I/O space for devices used on the Malta board. */ + for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) + request_resource(&ioport_resource, standard_io_resources+i); + + /* + * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. + */ + enable_dma(4); + +#ifdef CONFIG_KGDB + kgdb_config(); +#endif + +#ifdef CONFIG_DMA_COHERENT + if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) + panic("Hardware DMA cache coherency not supported"); +#endif + + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) + bonito_quirks_setup(); + +#ifdef CONFIG_BLK_DEV_IDE + pci_clock_check(); +#endif + +#ifdef CONFIG_BLK_DEV_FD + fd_activate(); +#endif + +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) + screen_info_setup(); +#endif + mips_reboot_setup(); + + board_be_init = malta_be_init; + board_be_handler = malta_be_handler; +} diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c new file mode 100644 index 000000000000..5ea705e49454 --- /dev/null +++ b/arch/mips/mti-malta/malta-smtc.c @@ -0,0 +1,154 @@ +/* + * Malta Platform-specific hooks for SMP operation + */ +#include +#include + +#include +#include +#include +#include + +/* VPE/SMP Prototype implements platform interfaces directly */ + +/* + * Cause the specified action to be performed on a targeted "CPU" + */ + +static void msmtc_send_ipi_single(int cpu, unsigned int action) +{ + /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ + smtc_send_ipi(cpu, LINUX_SMP_IPI, action); +} + +static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + msmtc_send_ipi_single(i, action); +} + +/* + * Post-config but pre-boot cleanup entry point + */ +static void __cpuinit msmtc_init_secondary(void) +{ + void smtc_init_secondary(void); + int myvpe; + + /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ + myvpe = read_c0_tcbind() & TCBIND_CURVPE; + if (myvpe != 0) { + /* Ideally, this should be done only once per VPE, but... */ + clear_c0_status(ST0_IM); + set_c0_status((0x100 << cp0_compare_irq) + | (0x100 << MIPS_CPU_IPI_IRQ)); + if (cp0_perfcount_irq >= 0) + set_c0_status(0x100 << cp0_perfcount_irq); + } + + smtc_init_secondary(); +} + +/* + * Platform "CPU" startup hook + */ +static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle) +{ + smtc_boot_secondary(cpu, idle); +} + +/* + * SMP initialization finalization entry point + */ +static void __cpuinit msmtc_smp_finish(void) +{ + smtc_smp_finish(); +} + +/* + * Hook for after all CPUs are online + */ + +static void msmtc_cpus_done(void) +{ +} + +/* + * Platform SMP pre-initialization + * + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. + */ + +static void __init msmtc_smp_setup(void) +{ + mipsmt_build_cpu_map(0); +} + +static void __init msmtc_prepare_cpus(unsigned int max_cpus) +{ + mipsmt_prepare_cpus(); +} + +struct plat_smp_ops msmtc_smp_ops = { + .send_ipi_single = msmtc_send_ipi_single, + .send_ipi_mask = msmtc_send_ipi_mask, + .init_secondary = msmtc_init_secondary, + .smp_finish = msmtc_smp_finish, + .cpus_done = msmtc_cpus_done, + .boot_secondary = msmtc_boot_secondary, + .smp_setup = msmtc_smp_setup, + .prepare_cpus = msmtc_prepare_cpus, +}; + +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * IRQ affinity hook + */ + + +void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity) +{ + cpumask_t tmask = affinity; + int cpu = 0; + void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); + + /* + * On the legacy Malta development board, all I/O interrupts + * are routed through the 8259 and combined in a single signal + * to the CPU daughterboard, and on the CoreFPGA2/3 34K models, + * that signal is brought to IP2 of both VPEs. To avoid racing + * concurrent interrupt service events, IP2 is enabled only on + * one VPE, by convention VPE0. So long as no bits are ever + * cleared in the affinity mask, there will never be any + * interrupt forwarding. But as soon as a program or operator + * sets affinity for one of the related IRQs, we need to make + * sure that we don't ever try to forward across the VPE boundry, + * at least not until we engineer a system where the interrupt + * _ack() or _end() function can somehow know that it corresponds + * to an interrupt taken on another VPE, and perform the appropriate + * restoration of Status.IM state using MFTR/MTTR instead of the + * normal local behavior. We also ensure that no attempt will + * be made to forward to an offline "CPU". + */ + + for_each_cpu_mask(cpu, affinity) { + if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) + cpu_clear(cpu, tmask); + } + irq_desc[irq].affinity = tmask; + + if (cpus_empty(tmask)) + /* + * We could restore a default mask here, but the + * runtime code can anyway deal with the null set + */ + printk(KERN_WARNING + "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); + + /* Do any generic SMTC IRQ affinity setup */ + smtc_set_irq_affinity(irq, tmask); +} +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c new file mode 100644 index 000000000000..0b97d47691fc --- /dev/null +++ b/arch/mips/mti-malta/malta-time.c @@ -0,0 +1,163 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Setting up the clock on the MIPS boards. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +unsigned long cpu_khz; + +static int mips_cpu_timer_irq; +static int mips_cpu_perf_irq; +extern int cp0_perfcount_irq; + +static void mips_timer_dispatch(void) +{ + do_IRQ(mips_cpu_timer_irq); +} + +static void mips_perf_dispatch(void) +{ + do_IRQ(mips_cpu_perf_irq); +} + +/* + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect + */ +static unsigned int __init estimate_cpu_frequency(void) +{ + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int count; + + unsigned long flags; + unsigned int start; + + local_irq_save(flags); + + /* Start counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + /* Start r4k counter. */ + start = read_c0_count(); + + /* Read counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + count = read_c0_count() - start; + + /* restore interrupts */ + local_irq_restore(flags); + + mips_hpt_frequency = count; + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + count *= 2; + + count += 5000; /* round */ + count -= count%10000; + + return count; +} + +unsigned long read_persistent_clock(void) +{ + return mc146818_get_cmos_time(); +} + +static void __init plat_perf_setup(void) +{ +#ifdef MSC01E_INT_BASE + if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); + mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; + } else +#endif + if (cp0_perfcount_irq >= 0) { + if (cpu_has_vint) + set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); + mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; +#ifdef CONFIG_SMP + set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); +#endif + } +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ +#ifdef MSC01E_INT_BASE + if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; + } else +#endif + { + if (cpu_has_vint) + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; + } + + return mips_cpu_timer_irq; +} + +void __init plat_time_init(void) +{ + unsigned int est_freq; + + /* Set Data mode - binary. */ + CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); + + est_freq = estimate_cpu_frequency(); + + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + (est_freq%1000000)*100/1000000); + + cpu_khz = est_freq / 1000; + + mips_scroll_message(); +#ifdef CONFIG_I8253 /* Only Malta has a PIT */ + setup_pit_timer(); +#endif + + plat_perf_setup(); +} diff --git a/include/asm-mips/mach-malta/cpu-feature-overrides.h b/include/asm-mips/mach-malta/cpu-feature-overrides.h new file mode 100644 index 000000000000..7f3e3f9bd23a --- /dev/null +++ b/include/asm-mips/mach-malta/cpu-feature-overrides.h @@ -0,0 +1,72 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Chris Dearman + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H + + +/* + * CPU feature overrides for MIPS boards + */ +#ifdef CONFIG_CPU_MIPS32 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#ifdef CONFIG_CPU_HAS_LLSC +#define cpu_has_llsc 1 +#else +#define cpu_has_llsc 0 +#endif +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#ifdef CONFIG_CPU_MIPS64 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#define cpu_has_llsc 1 +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-malta/irq.h b/include/asm-mips/mach-malta/irq.h new file mode 100644 index 000000000000..9b9da26683c2 --- /dev/null +++ b/include/asm-mips/mach-malta/irq.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_MIPS_IRQ_H +#define __ASM_MACH_MIPS_IRQ_H + + +#define NR_IRQS 256 + +#include_next + +#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/include/asm-mips/mach-malta/kernel-entry-init.h b/include/asm-mips/mach-malta/kernel-entry-init.h new file mode 100644 index 000000000000..0b793e7bf67e --- /dev/null +++ b/include/asm-mips/mach-malta/kernel-entry-init.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Chris Dearman (chris@mips.com) + * Copyright (C) 2007 Mips Technologies, Inc. + */ +#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H +#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H + + .macro kernel_entry_setup +#ifdef CONFIG_MIPS_MT_SMTC + mfc0 t0, CP0_CONFIG + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 1 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 2 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 3 + and t0, 1<<2 + bnez t0, 0f +9: + /* Assume we came from YAMON... */ + PTR_LA v0, 0x9fc00534 /* YAMON print */ + lw v0, (v0) + move a0, zero + PTR_LA a1, nonmt_processor + jal v0 + + PTR_LA v0, 0x9fc00520 /* YAMON exit */ + lw v0, (v0) + li a0, 1 + jal v0 + +1: b 1b + + __INITDATA +nonmt_processor: + .asciz "SMTC kernel requires the MT ASE to run\n" + __FINIT +0: +#endif + .endm + +/* + * Do SMP slave processor setup necessary before we can safely execute C code. + */ + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/include/asm-mips/mach-malta/mach-gt64120.h b/include/asm-mips/mach-malta/mach-gt64120.h new file mode 100644 index 000000000000..0f863148f3b6 --- /dev/null +++ b/include/asm-mips/mach-malta/mach-gt64120.h @@ -0,0 +1,19 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H +#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H + +#define MIPS_GT_BASE 0x1be00000 + +extern unsigned long _pcictrl_gt64120; +/* + * GT64120 config space base address + */ +#define GT64120_BASE _pcictrl_gt64120 + +#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-malta/mc146818rtc.h b/include/asm-mips/mach-malta/mc146818rtc.h new file mode 100644 index 000000000000..ea612f37f614 --- /dev/null +++ b/include/asm-mips/mach-malta/mc146818rtc.h @@ -0,0 +1,48 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2003 by Ralf Baechle + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * RTC routines for Malta style attached PIIX4 device, which contains a + * Motorola MC146818A-compatible Real Time Clock. + */ +#ifndef __ASM_MACH_MALTA_MC146818RTC_H +#define __ASM_MACH_MALTA_MC146818RTC_H + +#include +#include +#include + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb(addr, MALTA_RTC_ADR_REG); + return inb(MALTA_RTC_DAT_REG); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb(addr, MALTA_RTC_ADR_REG); + outb(data, MALTA_RTC_DAT_REG); +} + +#define RTC_ALWAYS_BCD 0 + +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) + +#endif /* __ASM_MACH_MALTA_MC146818RTC_H */ diff --git a/include/asm-mips/mach-malta/war.h b/include/asm-mips/mach-malta/war.h new file mode 100644 index 000000000000..7c6931d5f45f --- /dev/null +++ b/include/asm-mips/mach-malta/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h deleted file mode 100644 index 7f3e3f9bd23a..000000000000 --- a/include/asm-mips/mach-mips/cpu-feature-overrides.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Chris Dearman - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H - - -/* - * CPU feature overrides for MIPS boards - */ -#ifdef CONFIG_CPU_MIPS32 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -/* #define cpu_has_fpu ? */ -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#ifdef CONFIG_CPU_HAS_LLSC -#define cpu_has_llsc 1 -#else -#define cpu_has_llsc 0 -#endif -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#define cpu_icache_snoops_remote_store 1 -#endif - -#ifdef CONFIG_CPU_MIPS64 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -/* #define cpu_has_fpu ? */ -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#define cpu_has_llsc 1 -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#define cpu_icache_snoops_remote_store 1 -#endif - -#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-mips/irq.h deleted file mode 100644 index 9b9da26683c2..000000000000 --- a/include/asm-mips/mach-mips/irq.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __ASM_MACH_MIPS_IRQ_H -#define __ASM_MACH_MIPS_IRQ_H - - -#define NR_IRQS 256 - -#include_next - -#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-mips/kernel-entry-init.h deleted file mode 100644 index 0b793e7bf67e..000000000000 --- a/include/asm-mips/mach-mips/kernel-entry-init.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Chris Dearman (chris@mips.com) - * Copyright (C) 2007 Mips Technologies, Inc. - */ -#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H -#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H - - .macro kernel_entry_setup -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 t0, CP0_CONFIG - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 1 - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 2 - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 3 - and t0, 1<<2 - bnez t0, 0f -9: - /* Assume we came from YAMON... */ - PTR_LA v0, 0x9fc00534 /* YAMON print */ - lw v0, (v0) - move a0, zero - PTR_LA a1, nonmt_processor - jal v0 - - PTR_LA v0, 0x9fc00520 /* YAMON exit */ - lw v0, (v0) - li a0, 1 - jal v0 - -1: b 1b - - __INITDATA -nonmt_processor: - .asciz "SMTC kernel requires the MT ASE to run\n" - __FINIT -0: -#endif - .endm - -/* - * Do SMP slave processor setup necessary before we can safely execute C code. - */ - .macro smp_slave_setup - .endm - -#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-mips/mach-gt64120.h deleted file mode 100644 index 0f863148f3b6..000000000000 --- a/include/asm-mips/mach-mips/mach-gt64120.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H -#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H - -#define MIPS_GT_BASE 0x1be00000 - -extern unsigned long _pcictrl_gt64120; -/* - * GT64120 config space base address - */ -#define GT64120_BASE _pcictrl_gt64120 - -#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-mips/mc146818rtc.h b/include/asm-mips/mach-mips/mc146818rtc.h deleted file mode 100644 index ea612f37f614..000000000000 --- a/include/asm-mips/mach-mips/mc146818rtc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2003 by Ralf Baechle - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * RTC routines for Malta style attached PIIX4 device, which contains a - * Motorola MC146818A-compatible Real Time Clock. - */ -#ifndef __ASM_MACH_MALTA_MC146818RTC_H -#define __ASM_MACH_MALTA_MC146818RTC_H - -#include -#include -#include - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - outb(addr, MALTA_RTC_ADR_REG); - return inb(MALTA_RTC_DAT_REG); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - outb(addr, MALTA_RTC_ADR_REG); - outb(data, MALTA_RTC_DAT_REG); -} - -#define RTC_ALWAYS_BCD 0 - -#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) - -#endif /* __ASM_MACH_MALTA_MC146818RTC_H */ diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-mips/war.h deleted file mode 100644 index 7c6931d5f45f..000000000000 --- a/include/asm-mips/mach-mips/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MACH_MIPS_WAR_H -#define __ASM_MIPS_MACH_MIPS_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 1 -#define MIPS_CACHE_SYNC_WAR 1 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ -- cgit v1.2.3 From 22b1d707ffc99faebd86257ad19d5bb9fc624734 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 11 Jul 2008 00:31:36 +0900 Subject: [MIPS] TXx9: Reorganize code Move arch/mips/{jmr3927,tx4927,tx4938} into arch/mips/txx9/ tree. This will help more code sharing and maintainance. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 3 +- arch/mips/Makefile | 12 +- arch/mips/jmr3927/common/Makefile | 7 - arch/mips/jmr3927/common/prom.c | 72 -- arch/mips/jmr3927/common/puts.c | 60 -- arch/mips/jmr3927/rbhma3100/Makefile | 8 - arch/mips/jmr3927/rbhma3100/init.c | 57 - arch/mips/jmr3927/rbhma3100/irq.c | 174 --- arch/mips/jmr3927/rbhma3100/kgdb_io.c | 105 -- arch/mips/jmr3927/rbhma3100/setup.c | 445 -------- arch/mips/pci/Makefile | 2 +- arch/mips/pci/fixup-jmr3927.c | 2 +- arch/mips/pci/fixup-rbtx4927.c | 2 +- arch/mips/pci/fixup-rbtx4938.c | 92 ++ arch/mips/pci/fixup-tx4938.c | 92 -- arch/mips/pci/ops-tx3927.c | 2 +- arch/mips/pci/ops-tx4927.c | 2 +- arch/mips/pci/ops-tx4938.c | 2 +- arch/mips/pci/pci-jmr3927.c | 2 +- arch/mips/tx4927/Kconfig | 3 - arch/mips/tx4927/common/Makefile | 10 - arch/mips/tx4927/common/smsc_fdc37m81x.c | 172 --- arch/mips/tx4927/common/tx4927_dbgio.c | 43 - arch/mips/tx4927/common/tx4927_irq.c | 65 -- arch/mips/tx4927/common/tx4927_prom.c | 142 --- arch/mips/tx4927/toshiba_rbtx4927/Makefile | 5 - .../tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 216 ---- .../toshiba_rbtx4927/toshiba_rbtx4927_prom.c | 91 -- .../toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 703 ------------ arch/mips/tx4938/Kconfig | 24 - arch/mips/tx4938/common/Makefile | 8 - arch/mips/tx4938/common/dbgio.c | 48 - arch/mips/tx4938/common/irq.c | 48 - arch/mips/tx4938/common/prom.c | 124 --- arch/mips/tx4938/toshiba_rbtx4938/Makefile | 7 - arch/mips/tx4938/toshiba_rbtx4938/irq.c | 161 --- arch/mips/tx4938/toshiba_rbtx4938/prom.c | 74 -- arch/mips/tx4938/toshiba_rbtx4938/setup.c | 1124 -------------------- arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c | 99 -- arch/mips/txx9/Kconfig | 28 + arch/mips/txx9/generic/Makefile | 10 + arch/mips/txx9/generic/dbgio.c | 48 + arch/mips/txx9/generic/irq_tx4927.c | 64 ++ arch/mips/txx9/generic/irq_tx4938.c | 48 + arch/mips/txx9/generic/mem_tx4927.c | 141 +++ arch/mips/txx9/generic/mem_tx4938.c | 124 +++ arch/mips/txx9/generic/smsc_fdc37m81x.c | 172 +++ arch/mips/txx9/jmr3927/Makefile | 8 + arch/mips/txx9/jmr3927/init.c | 57 + arch/mips/txx9/jmr3927/irq.c | 174 +++ arch/mips/txx9/jmr3927/kgdb_io.c | 105 ++ arch/mips/txx9/jmr3927/prom.c | 98 ++ arch/mips/txx9/jmr3927/setup.c | 445 ++++++++ arch/mips/txx9/rbtx4927/Makefile | 3 + arch/mips/txx9/rbtx4927/irq.c | 214 ++++ arch/mips/txx9/rbtx4927/prom.c | 91 ++ arch/mips/txx9/rbtx4927/setup.c | 703 ++++++++++++ arch/mips/txx9/rbtx4938/Makefile | 3 + arch/mips/txx9/rbtx4938/irq.c | 159 +++ arch/mips/txx9/rbtx4938/prom.c | 72 ++ arch/mips/txx9/rbtx4938/setup.c | 1122 +++++++++++++++++++ arch/mips/txx9/rbtx4938/spi_eeprom.c | 99 ++ include/asm-mips/jmr3927/jmr3927.h | 177 --- include/asm-mips/jmr3927/tx3927.h | 319 ------ include/asm-mips/jmr3927/txx927.h | 121 --- include/asm-mips/tx4927/smsc_fdc37m81x.h | 69 -- include/asm-mips/tx4927/toshiba_rbtx4927.h | 49 - include/asm-mips/tx4927/tx4927.h | 280 ----- include/asm-mips/tx4938/rbtx4938.h | 168 --- include/asm-mips/tx4938/spi.h | 20 - include/asm-mips/tx4938/tx4938.h | 628 ----------- include/asm-mips/txx9/jmr3927.h | 177 +++ include/asm-mips/txx9/rbtx4927.h | 49 + include/asm-mips/txx9/rbtx4938.h | 167 +++ include/asm-mips/txx9/smsc_fdc37m81x.h | 67 ++ include/asm-mips/txx9/spi.h | 19 + include/asm-mips/txx9/tx3927.h | 319 ++++++ include/asm-mips/txx9/tx4927.h | 280 +++++ include/asm-mips/txx9/tx4938.h | 627 +++++++++++ include/asm-mips/txx9/txx927.h | 121 +++ 80 files changed, 5920 insertions(+), 6033 deletions(-) delete mode 100644 arch/mips/jmr3927/common/Makefile delete mode 100644 arch/mips/jmr3927/common/prom.c delete mode 100644 arch/mips/jmr3927/common/puts.c delete mode 100644 arch/mips/jmr3927/rbhma3100/Makefile delete mode 100644 arch/mips/jmr3927/rbhma3100/init.c delete mode 100644 arch/mips/jmr3927/rbhma3100/irq.c delete mode 100644 arch/mips/jmr3927/rbhma3100/kgdb_io.c delete mode 100644 arch/mips/jmr3927/rbhma3100/setup.c create mode 100644 arch/mips/pci/fixup-rbtx4938.c delete mode 100644 arch/mips/pci/fixup-tx4938.c delete mode 100644 arch/mips/tx4927/Kconfig delete mode 100644 arch/mips/tx4927/common/Makefile delete mode 100644 arch/mips/tx4927/common/smsc_fdc37m81x.c delete mode 100644 arch/mips/tx4927/common/tx4927_dbgio.c delete mode 100644 arch/mips/tx4927/common/tx4927_irq.c delete mode 100644 arch/mips/tx4927/common/tx4927_prom.c delete mode 100644 arch/mips/tx4927/toshiba_rbtx4927/Makefile delete mode 100644 arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c delete mode 100644 arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c delete mode 100644 arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c delete mode 100644 arch/mips/tx4938/Kconfig delete mode 100644 arch/mips/tx4938/common/Makefile delete mode 100644 arch/mips/tx4938/common/dbgio.c delete mode 100644 arch/mips/tx4938/common/irq.c delete mode 100644 arch/mips/tx4938/common/prom.c delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/Makefile delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/irq.c delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/prom.c delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/setup.c delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c create mode 100644 arch/mips/txx9/Kconfig create mode 100644 arch/mips/txx9/generic/Makefile create mode 100644 arch/mips/txx9/generic/dbgio.c create mode 100644 arch/mips/txx9/generic/irq_tx4927.c create mode 100644 arch/mips/txx9/generic/irq_tx4938.c create mode 100644 arch/mips/txx9/generic/mem_tx4927.c create mode 100644 arch/mips/txx9/generic/mem_tx4938.c create mode 100644 arch/mips/txx9/generic/smsc_fdc37m81x.c create mode 100644 arch/mips/txx9/jmr3927/Makefile create mode 100644 arch/mips/txx9/jmr3927/init.c create mode 100644 arch/mips/txx9/jmr3927/irq.c create mode 100644 arch/mips/txx9/jmr3927/kgdb_io.c create mode 100644 arch/mips/txx9/jmr3927/prom.c create mode 100644 arch/mips/txx9/jmr3927/setup.c create mode 100644 arch/mips/txx9/rbtx4927/Makefile create mode 100644 arch/mips/txx9/rbtx4927/irq.c create mode 100644 arch/mips/txx9/rbtx4927/prom.c create mode 100644 arch/mips/txx9/rbtx4927/setup.c create mode 100644 arch/mips/txx9/rbtx4938/Makefile create mode 100644 arch/mips/txx9/rbtx4938/irq.c create mode 100644 arch/mips/txx9/rbtx4938/prom.c create mode 100644 arch/mips/txx9/rbtx4938/setup.c create mode 100644 arch/mips/txx9/rbtx4938/spi_eeprom.c delete mode 100644 include/asm-mips/jmr3927/jmr3927.h delete mode 100644 include/asm-mips/jmr3927/tx3927.h delete mode 100644 include/asm-mips/jmr3927/txx927.h delete mode 100644 include/asm-mips/tx4927/smsc_fdc37m81x.h delete mode 100644 include/asm-mips/tx4927/toshiba_rbtx4927.h delete mode 100644 include/asm-mips/tx4927/tx4927.h delete mode 100644 include/asm-mips/tx4938/rbtx4938.h delete mode 100644 include/asm-mips/tx4938/spi.h delete mode 100644 include/asm-mips/tx4938/tx4938.h create mode 100644 include/asm-mips/txx9/jmr3927.h create mode 100644 include/asm-mips/txx9/rbtx4927.h create mode 100644 include/asm-mips/txx9/rbtx4938.h create mode 100644 include/asm-mips/txx9/smsc_fdc37m81x.h create mode 100644 include/asm-mips/txx9/spi.h create mode 100644 include/asm-mips/txx9/tx3927.h create mode 100644 include/asm-mips/txx9/tx4927.h create mode 100644 include/asm-mips/txx9/tx4938.h create mode 100644 include/asm-mips/txx9/txx927.h (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a0381427ec5c..3202960f7597 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -642,8 +642,7 @@ source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" -source "arch/mips/tx4927/Kconfig" -source "arch/mips/tx4938/Kconfig" +source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 36aa690484c8..8e1e49c5186b 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -553,8 +553,8 @@ all-$(CONFIG_SNI_RM) := vmlinux.ecoff # # Toshiba JMR-TX3927 board # -core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/jmr3927/rbhma3100/ \ - arch/mips/jmr3927/common/ +core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ \ + arch/mips/txx9/generic/ cflags-$(CONFIG_TOSHIBA_JMR3927) += -Iinclude/asm-mips/mach-jmr3927 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 @@ -562,16 +562,16 @@ load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 # Toshiba RBTX4927 board or # Toshiba RBTX4937 board # -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/ -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ +core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ +core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/generic/ cflags-$(CONFIG_TOSHIBA_RBTX4927) += -Iinclude/asm-mips/mach-tx49xx load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 # # Toshiba RBTX4938 board # -core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/ -core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/ +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/generic/ cflags-$(CONFIG_TOSHIBA_RBTX4938) += -Iinclude/asm-mips/mach-tx49xx load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000 diff --git a/arch/mips/jmr3927/common/Makefile b/arch/mips/jmr3927/common/Makefile deleted file mode 100644 index 8fd4fcccf10e..000000000000 --- a/arch/mips/jmr3927/common/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for the common code of TOSHIBA JMR-TX3927 board -# - -obj-y += prom.o puts.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jmr3927/common/prom.c b/arch/mips/jmr3927/common/prom.c deleted file mode 100644 index 5398813e50e6..000000000000 --- a/arch/mips/jmr3927/common/prom.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * PROM library initialisation code, assuming a version of - * pmon is the boot code. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * Based on arch/mips/au1000/common/prom.c - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/xx files. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -#include - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - int prom_argc = fw_arg0; - char **prom_argv = (char **) fw_arg1; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/jmr3927/common/puts.c b/arch/mips/jmr3927/common/puts.c deleted file mode 100644 index c611ab497888..000000000000 --- a/arch/mips/jmr3927/common/puts.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Low level uart routines to directly access a TX[34]927 SIO. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com or source@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * Based on arch/mips/au1000/common/puts.c - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -#define TIMEOUT 0xffffff - -void -prom_putchar(char c) -{ - int i = 0; - - do { - i++; - if (i>TIMEOUT) - break; - } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); - tx3927_sioptr(1)->tfifo = c; - return; -} - -void -puts(const char *cp) -{ - while (*cp) - prom_putchar(*cp++); - prom_putchar('\r'); - prom_putchar('\n'); -} diff --git a/arch/mips/jmr3927/rbhma3100/Makefile b/arch/mips/jmr3927/rbhma3100/Makefile deleted file mode 100644 index d86e30dca8f3..000000000000 --- a/arch/mips/jmr3927/rbhma3100/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for TOSHIBA JMR-TX3927 board -# - -obj-y += init.o irq.o setup.o -obj-$(CONFIG_KGDB) += kgdb_io.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jmr3927/rbhma3100/init.c b/arch/mips/jmr3927/rbhma3100/init.c deleted file mode 100644 index 700b9cf8eb9d..000000000000 --- a/arch/mips/jmr3927/rbhma3100/init.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * arch/mips/jmr3927/common/init.c - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -extern void __init prom_init_cmdline(void); - -const char *get_system_type(void) -{ - return "Toshiba" -#ifdef CONFIG_TOSHIBA_JMR3927 - " JMR_TX3927" -#endif - ; -} - -extern void puts(const char *cp); - -void __init prom_init(void) -{ -#ifdef CONFIG_TOSHIBA_JMR3927 - /* CCFG */ - if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) - puts("Warning: TX3927 TLB off\n"); -#endif - - prom_init_cmdline(); - add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); -} diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c deleted file mode 100644 index 3a47e8ce1196..000000000000 --- a/arch/mips/jmr3927/rbhma3100/irq.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#if JMR3927_IRQ_END > NR_IRQS -#error JMR3927_IRQ_END > NR_IRQS -#endif - -static unsigned char irc_level[TX3927_NUM_IR] = { - 5, 5, 5, 5, 5, 5, /* INT[5:0] */ - 7, 7, /* SIO */ - 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ - 6, 6, 6 /* TMR */ -}; - -/* - * CP0_STATUS is a thread's resource (saved/restored on context switch). - * So disable_irq/enable_irq MUST handle IOC/IRC registers. - */ -static void mask_irq_ioc(unsigned int irq) -{ - /* 0: mask */ - unsigned int irq_nr = irq - JMR3927_IRQ_IOC; - unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); - unsigned int bit = 1 << irq_nr; - jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); - /* flush write buffer */ - (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); -} -static void unmask_irq_ioc(unsigned int irq) -{ - /* 0: mask */ - unsigned int irq_nr = irq - JMR3927_IRQ_IOC; - unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); - unsigned int bit = 1 << irq_nr; - jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); - /* flush write buffer */ - (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long cp0_cause = read_c0_cause(); - int irq; - - if ((cp0_cause & CAUSEF_IP7) == 0) - return; - irq = (cp0_cause >> CAUSEB_IP2) & 0x0f; - - do_IRQ(irq + JMR3927_IRQ_IRC); -} - -static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) -{ - unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); - int i; - - for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { - if (istat & (1 << i)) { - irq = JMR3927_IRQ_IOC + i; - do_IRQ(irq); - } - } - return IRQ_HANDLED; -} - -static struct irqaction ioc_action = { - .handler = jmr3927_ioc_interrupt, - .mask = CPU_MASK_NONE, - .name = "IOC", -}; - -static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) -{ - printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); - printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", - tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); - - return IRQ_HANDLED; -} -static struct irqaction pcierr_action = { - .handler = jmr3927_pcierr_interrupt, - .mask = CPU_MASK_NONE, - .name = "PCI error", -}; - -static void __init jmr3927_irq_init(void); - -void __init arch_init_irq(void) -{ - /* Now, interrupt control disabled, */ - /* all IRC interrupts are masked, */ - /* all IRC interrupt mode are Low Active. */ - - /* mask all IOC interrupts */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR); - /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */ - jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR); - - /* clear PCI Soft interrupts */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR); - /* clear PCI Reset interrupts */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - - jmr3927_irq_init(); - - /* setup IOC interrupt 1 (PCI, MODEM) */ - setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); - -#ifdef CONFIG_PCI - setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); -#endif - - /* enable all CPU interrupt bits. */ - set_c0_status(ST0_IM); /* IE bit is still 0. */ -} - -static struct irq_chip jmr3927_irq_ioc = { - .name = "jmr3927_ioc", - .ack = mask_irq_ioc, - .mask = mask_irq_ioc, - .mask_ack = mask_irq_ioc, - .unmask = unmask_irq_ioc, -}; - -static void __init jmr3927_irq_init(void) -{ - u32 i; - - txx9_irq_init(TX3927_IRC_REG); - for (i = 0; i < TXx9_MAX_IR; i++) - txx9_irq_set_pri(i, irc_level[i]); - for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) - set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); -} diff --git a/arch/mips/jmr3927/rbhma3100/kgdb_io.c b/arch/mips/jmr3927/rbhma3100/kgdb_io.c deleted file mode 100644 index 342579cfdc01..000000000000 --- a/arch/mips/jmr3927/rbhma3100/kgdb_io.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Low level uart routines to directly access a TX[34]927 SIO. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com or source@mvista.com - * - * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -#define TIMEOUT 0xffffff - -static int remoteDebugInitialized = 0; -static void debugInit(int baud); - -int putDebugChar(unsigned char c) -{ - int i = 0; - - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(38400); - } - - do { - slow_down(); - i++; - if (i>TIMEOUT) { - break; - } - } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS)); - tx3927_sioptr(0)->tfifo = c; - - return 1; -} - -unsigned char getDebugChar(void) -{ - int i = 0; - int dicr; - char c; - - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(38400); - } - - /* diable RX int. */ - dicr = tx3927_sioptr(0)->dicr; - tx3927_sioptr(0)->dicr = 0; - - do { - slow_down(); - i++; - if (i>TIMEOUT) { - break; - } - } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID) - ; - c = tx3927_sioptr(0)->rfifo; - - /* clear RX int. status */ - tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS; - /* enable RX int. */ - tx3927_sioptr(0)->dicr = dicr; - - return c; -} - -static void debugInit(int baud) -{ - tx3927_sioptr(0)->lcr = 0x020; - tx3927_sioptr(0)->dicr = 0; - tx3927_sioptr(0)->disr = 0x4100; - tx3927_sioptr(0)->cisr = 0x014; - tx3927_sioptr(0)->fcr = 0; - tx3927_sioptr(0)->flcr = 0x02; - tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) | - TXx927_SIBGR_BCLK_T0; -} diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c deleted file mode 100644 index f39c444e42d4..000000000000 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif - -#include -#include -#include -#include -#include - -extern void puts(const char *cp); - -/* don't enable - see errata */ -static int jmr3927_ccfg_toeon; - -static inline void do_reset(void) -{ -#if 1 /* Resetting PCI bus */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); - (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ - mdelay(1); - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); -#endif - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); -} - -static void jmr3927_machine_restart(char *command) -{ - local_irq_disable(); - puts("Rebooting..."); - do_reset(); -} - -static void jmr3927_machine_halt(void) -{ - puts("JMR-TX3927 halted.\n"); - while (1); -} - -static void jmr3927_machine_power_off(void) -{ - puts("JMR-TX3927 halted. Please turn off the power.\n"); - while (1); -} - -void __init plat_time_init(void) -{ - txx9_clockevent_init(TX3927_TMR_REG(0), - TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0), - JMR3927_IMCLK); - txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK); -} - -#define DO_WRITE_THROUGH -#define DO_ENABLE_CACHE - -extern char * __init prom_getcmdline(void); -static void jmr3927_board_init(void); -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; - -void __init plat_mem_setup(void) -{ - char *argptr; - - set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); - - _machine_restart = jmr3927_machine_restart; - _machine_halt = jmr3927_machine_halt; - pm_power_off = jmr3927_machine_power_off; - - /* - * IO/MEM resources. - */ - ioport_resource.start = pci_io_resource.start; - ioport_resource.end = pci_io_resource.end; - iomem_resource.start = 0; - iomem_resource.end = 0xffffffff; - - /* Reboot on panic */ - panic_timeout = 180; - - /* cache setup */ - { - unsigned int conf; -#ifdef DO_ENABLE_CACHE - int mips_ic_disable = 0, mips_dc_disable = 0; -#else - int mips_ic_disable = 1, mips_dc_disable = 1; -#endif -#ifdef DO_WRITE_THROUGH - int mips_config_cwfon = 0; - int mips_config_wbon = 0; -#else - int mips_config_cwfon = 1; - int mips_config_wbon = 1; -#endif - - conf = read_c0_conf(); - conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); - conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; - conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; - conf |= mips_config_wbon ? TX39_CONF_WBON : 0; - conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; - - write_c0_conf(conf); - write_c0_cache(0); - } - - /* initialize board */ - jmr3927_board_init(); - - argptr = prom_getcmdline(); - - if ((argptr = strstr(argptr, "toeon")) != NULL) - jmr3927_ccfg_toeon = 1; - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "ip=")) == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " ip=bootp"); - } - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - int i; - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i); - req.mapbase = TX3927_SIO_REG(i); - req.irq = i == 0 ? - JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; - if (i == 0) - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = JMR3927_IMCLK; - early_serial_txx9_setup(&req); - } - } -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "console=")) == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS1,115200"); - } -#endif -#endif -} - -static void tx3927_setup(void); - -static void __init jmr3927_board_init(void) -{ - tx3927_setup(); - - /* SIO0 DTR on */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); - - jmr3927_led_set(0); - - printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", - jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, - jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, - jmr3927_dipsw1(), jmr3927_dipsw2(), - jmr3927_dipsw3(), jmr3927_dipsw4()); -} - -static void __init tx3927_setup(void) -{ - int i; -#ifdef CONFIG_PCI - unsigned long mips_pci_io_base = JMR3927_PCIIO; - unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; - unsigned long mips_pci_mem_base = JMR3927_PCIMEM; - unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; - /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ - unsigned long mips_pci_io_pciaddr = 0; -#endif - - /* SDRAMC are configured by PROM */ - - /* ROMC */ - tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; - tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; - tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; - tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; - - /* CCFG */ - /* enable Timeout BusError */ - if (jmr3927_ccfg_toeon) - tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; - - /* clear BusErrorOnWrite flag */ - tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; - /* Disable PCI snoop */ - tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; - /* do reset on watchdog */ - tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; - -#ifdef DO_WRITE_THROUGH - /* Enable PCI SNOOP - with write through only */ - tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; -#endif - - /* Pin selection */ - tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; - tx3927_ccfgptr->pcfg |= - TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | - (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); - - printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", - tx3927_ccfgptr->crir, - tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); - - /* TMR */ - for (i = 0; i < TX3927_NR_TMR; i++) - txx9_tmr_init(TX3927_TMR_REG(i)); - - /* DMA */ - tx3927_dmaptr->mcr = 0; - for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { - /* reset channel */ - tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; - tx3927_dmaptr->ch[i].ccr = 0; - } - /* enable DMA */ -#ifdef __BIG_ENDIAN - tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; -#else - tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; -#endif - -#ifdef CONFIG_PCI - /* PCIC */ - printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", - tx3927_pcicptr->did, tx3927_pcicptr->vid, - tx3927_pcicptr->rid); - if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { - printk("External\n"); - /* XXX */ - } else { - printk("Internal\n"); - - /* Reset PCI Bus */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, - JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - - - /* Disable External PCI Config. Access */ - tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; -#ifdef __BIG_ENDIAN - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | - TX3927_PCIC_LBC_TIBSE | - TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; -#endif - /* LB->PCI mappings */ - tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); - tx3927_pcicptr->ilbioma = mips_pci_io_base; - tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; - tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->ilbmma = mips_pci_mem_base; - tx3927_pcicptr->ipbmma = mips_pci_mem_base; - /* PCI->LB mappings */ - tx3927_pcicptr->iobas = 0xffffffff; - tx3927_pcicptr->ioba = 0; - tx3927_pcicptr->tlbioma = 0; - tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->mba = 0; - tx3927_pcicptr->tlbmma = 0; - /* Enable Direct mapping Address Space Decoder */ - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; - - /* Clear All Local Bus Status */ - tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; - /* Enable All Local Bus Interrupts */ - tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; - /* Clear All PCI Status Error */ - tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; - /* Enable All PCI Status Error Interrupts */ - tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; - - /* PCIC Int => IRC IRQ10 */ - tx3927_pcicptr->il = TX3927_IR_PCI; - /* Target Control (per errata) */ - tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; - - /* Enable Bus Arbiter */ - tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; - - tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - } -#endif /* CONFIG_PCI */ - - /* PIO */ - /* PIO[15:12] connected to LEDs */ - __raw_writel(0x0000f000, &tx3927_pioptr->dir); - __raw_writel(0, &tx3927_pioptr->maskcpu); - __raw_writel(0, &tx3927_pioptr->maskext); - txx9_gpio_init(TX3927_PIO_REG, 0, 16); - gpio_request(11, "dipsw1"); - gpio_request(10, "dipsw2"); - { - unsigned int conf; - - conf = read_c0_conf(); - if (!(conf & TX39_CONF_ICE)) - printk("TX3927 I-Cache disabled.\n"); - if (!(conf & TX39_CONF_DCE)) - printk("TX3927 D-Cache disabled.\n"); - else if (!(conf & TX39_CONF_WBON)) - printk("TX3927 D-Cache WriteThrough.\n"); - else if (!(conf & TX39_CONF_CWFON)) - printk("TX3927 D-Cache WriteBack.\n"); - else - printk("TX3927 D-Cache WriteBack (CWF) .\n"); - } -} - -/* This trick makes rtc-ds1742 driver usable as is. */ -unsigned long __swizzle_addr_b(unsigned long port) -{ - if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR) - return port; - port = (port & 0xffff0000) | (port & 0x7fff << 1); -#ifdef __BIG_ENDIAN - return port; -#else - return port | 1; -#endif -} -EXPORT_SYMBOL(__swizzle_addr_b); - -static int __init jmr3927_rtc_init(void) -{ - static struct resource __initdata res = { - .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, - .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev; - dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(jmr3927_rtc_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init jmr3927_wdt_init(void) -{ - return txx9_wdt_init(TX3927_TMR_REG(2)); -} -device_initcall(jmr3927_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)JMR3927_IMCLK; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 80fa5abb25d4..4608e43de28c 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o ops-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index e974394be7bc..41dcd6a3aae5 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -31,7 +31,7 @@ #include #include -#include +#include int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 2d234ca017db..26013badfe1f 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -37,7 +37,7 @@ #include #include -#include +#include #undef DEBUG #ifdef DEBUG diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c new file mode 100644 index 000000000000..64d4510c0265 --- /dev/null +++ b/arch/mips/pci/fixup-rbtx4938.c @@ -0,0 +1,92 @@ +/* + * Toshiba rbtx4938 pci routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include + +#include + +extern struct pci_controller tx4938_pci_controller[]; + +static int pci_get_irq(const struct pci_dev *dev, int pin) +{ + int irq = pin; + u8 slot = PCI_SLOT(dev->devfn); + struct pci_controller *controller = (struct pci_controller *)dev->sysdata; + + if (controller == &tx4938_pci_controller[1]) { + /* TX4938 PCIC1 */ + switch (slot) { + case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; + break; + case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; + break; + } + return 0; + } + + /* IRQ rotation */ + irq--; /* 0-3 */ + if (dev->bus->parent == NULL && + (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { + /* PCI CardSlot (IDSEL=A23) */ + /* PCIA => PCIA (IDSEL=A23) */ + irq = (irq + 0 + slot) % 4; + } else { + /* PCI Backplane */ + irq = (irq + 33 - slot) % 4; + } + irq++; /* 1-4 */ + + switch (irq) { + case 1: + irq = RBTX4938_IRQ_IOC_PCIA; + break; + case 2: + irq = RBTX4938_IRQ_IOC_PCIB; + break; + case 3: + irq = RBTX4938_IRQ_IOC_PCIC; + break; + case 4: + irq = RBTX4938_IRQ_IOC_PCID; + break; + } + return irq; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + unsigned char irq = 0; + + irq = pci_get_irq(dev, pin); + + printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", + dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), irq); + + return irq; +} + +/* + * Do platform specific device initialization at pci_enable_device() time + */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c deleted file mode 100644 index f2ba06ee0c10..000000000000 --- a/arch/mips/pci/fixup-tx4938.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Toshiba rbtx4938 pci routines - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include - -#include - -extern struct pci_controller tx4938_pci_controller[]; - -static int pci_get_irq(const struct pci_dev *dev, int pin) -{ - int irq = pin; - u8 slot = PCI_SLOT(dev->devfn); - struct pci_controller *controller = (struct pci_controller *)dev->sysdata; - - if (controller == &tx4938_pci_controller[1]) { - /* TX4938 PCIC1 */ - switch (slot) { - case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; - break; - case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; - break; - } - return 0; - } - - /* IRQ rotation */ - irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { - /* PCI CardSlot (IDSEL=A23) */ - /* PCIA => PCIA (IDSEL=A23) */ - irq = (irq + 0 + slot) % 4; - } else { - /* PCI Backplane */ - irq = (irq + 33 - slot) % 4; - } - irq++; /* 1-4 */ - - switch (irq) { - case 1: - irq = RBTX4938_IRQ_IOC_PCIA; - break; - case 2: - irq = RBTX4938_IRQ_IOC_PCIB; - break; - case 3: - irq = RBTX4938_IRQ_IOC_PCIC; - break; - case 4: - irq = RBTX4938_IRQ_IOC_PCID; - break; - } - return irq; -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char irq = 0; - - irq = pci_get_irq(dev, pin); - - printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", - dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), irq); - - return irq; -} - -/* - * Do platform specific device initialization at pci_enable_device() time - */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c index aa698bd0d5e3..5d398f694682 100644 --- a/arch/mips/pci/ops-tx3927.c +++ b/arch/mips/pci/ops-tx3927.c @@ -39,7 +39,7 @@ #include #include -#include +#include static inline int mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where) diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 1bbafeb4a774..54730eee451b 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -40,7 +40,7 @@ #include #include #include -#include +#include /* initialize in setup */ struct resource pci_io_resource = { diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c index a450c4062031..34494b82cb22 100644 --- a/arch/mips/pci/ops-tx4938.c +++ b/arch/mips/pci/ops-tx4938.c @@ -15,7 +15,7 @@ #include #include -#include +#include /* initialize in setup */ struct resource pci_io_resource = { diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c index cb84f4e8ccae..7fb6bd71901a 100644 --- a/arch/mips/pci/pci-jmr3927.c +++ b/arch/mips/pci/pci-jmr3927.c @@ -31,7 +31,7 @@ #include #include -#include +#include #include struct resource pci_io_resource = { diff --git a/arch/mips/tx4927/Kconfig b/arch/mips/tx4927/Kconfig deleted file mode 100644 index 5fbbe12e0fc1..000000000000 --- a/arch/mips/tx4927/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config TOSHIBA_FPCIB0 - bool "FPCIB0 Backplane Support" - depends on TOSHIBA_RBTX4927 diff --git a/arch/mips/tx4927/common/Makefile b/arch/mips/tx4927/common/Makefile deleted file mode 100644 index a7fe76a64964..000000000000 --- a/arch/mips/tx4927/common/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile for common code for Toshiba TX4927 based systems -# - -obj-y += tx4927_prom.o tx4927_irq.o - -obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o -obj-$(CONFIG_KGDB) += tx4927_dbgio.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4927/common/smsc_fdc37m81x.c b/arch/mips/tx4927/common/smsc_fdc37m81x.c deleted file mode 100644 index 33f517bc9a08..000000000000 --- a/arch/mips/tx4927/common/smsc_fdc37m81x.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Interface for smsc fdc48m81x Super IO chip - * - * Author: MontaVista Software, Inc. source@mvista.com - * - * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright 2004 (c) MontaVista Software, Inc. - */ -#include -#include -#include -#include - -#define DEBUG - -/* Common Registers */ -#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 -#define SMSC_FDC37M81X_CONFIG_DATA 0x01 -#define SMSC_FDC37M81X_CONF 0x02 -#define SMSC_FDC37M81X_INDEX 0x03 -#define SMSC_FDC37M81X_DNUM 0x07 -#define SMSC_FDC37M81X_DID 0x20 -#define SMSC_FDC37M81X_DREV 0x21 -#define SMSC_FDC37M81X_PCNT 0x22 -#define SMSC_FDC37M81X_PMGT 0x23 -#define SMSC_FDC37M81X_OSC 0x24 -#define SMSC_FDC37M81X_CONFPA0 0x26 -#define SMSC_FDC37M81X_CONFPA1 0x27 -#define SMSC_FDC37M81X_TEST4 0x2B -#define SMSC_FDC37M81X_TEST5 0x2C -#define SMSC_FDC37M81X_TEST1 0x2D -#define SMSC_FDC37M81X_TEST2 0x2E -#define SMSC_FDC37M81X_TEST3 0x2F - -/* Logical device numbers */ -#define SMSC_FDC37M81X_FDD 0x00 -#define SMSC_FDC37M81X_SERIAL1 0x04 -#define SMSC_FDC37M81X_SERIAL2 0x05 -#define SMSC_FDC37M81X_KBD 0x07 - -/* Logical device Config Registers */ -#define SMSC_FDC37M81X_ACTIVE 0x30 -#define SMSC_FDC37M81X_BASEADDR0 0x60 -#define SMSC_FDC37M81X_BASEADDR1 0x61 -#define SMSC_FDC37M81X_INT 0x70 -#define SMSC_FDC37M81X_INT2 0x72 -#define SMSC_FDC37M81X_MODE 0xF0 - -/* Chip Config Values */ -#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 -#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa -#define SMSC_FDC37M81X_CHIP_ID 0x4d - -static unsigned long g_smsc_fdc37m81x_base = 0; - -static inline unsigned char smsc_fdc37m81x_rd(unsigned char index) -{ - outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); - - return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); -} - -static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data) -{ - outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); - outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); -} - -void smsc_fdc37m81x_config_beg(void) -{ - if (g_smsc_fdc37m81x_base) { - outb(SMSC_FDC37M81X_CONFIG_ENTER, - g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); - } -} - -void smsc_fdc37m81x_config_end(void) -{ - if (g_smsc_fdc37m81x_base) - outb(SMSC_FDC37M81X_CONFIG_EXIT, - g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); -} - -u8 smsc_fdc37m81x_config_get(u8 reg) -{ - u8 val = 0; - - if (g_smsc_fdc37m81x_base) - val = smsc_fdc37m81x_rd(reg); - - return val; -} - -void smsc_fdc37m81x_config_set(u8 reg, u8 val) -{ - if (g_smsc_fdc37m81x_base) - smsc_dc37m81x_wr(reg, val); -} - -unsigned long __init smsc_fdc37m81x_init(unsigned long port) -{ - const int field = sizeof(unsigned long) * 2; - u8 chip_id; - - if (g_smsc_fdc37m81x_base) - printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n", - field, g_smsc_fdc37m81x_base); - - g_smsc_fdc37m81x_base = port; - - smsc_fdc37m81x_config_beg(); - - chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID); - if (chip_id == SMSC_FDC37M81X_CHIP_ID) - smsc_fdc37m81x_config_end(); - else { - printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n", - chip_id); - g_smsc_fdc37m81x_base = 0; - } - - return g_smsc_fdc37m81x_base; -} - -#ifdef DEBUG -void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg) -{ - printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, - smsc_fdc37m81x_rd(reg)); -} - -void smsc_fdc37m81x_config_dump(void) -{ - u8 orig; - char *fname = "smsc_fdc37m81x_config_dump()"; - - smsc_fdc37m81x_config_beg(); - - orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); - - printk("%s: common\n", fname); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_DNUM); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_DID); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_DREV); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_PCNT); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_PMGT); - - printk("%s: keyboard\n", fname); - smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_ACTIVE); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_INT); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_INT2); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_LDCR_F0); - - smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig); - - smsc_fdc37m81x_config_end(); -} -#endif diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c deleted file mode 100644 index ea1ff23f4b72..000000000000 --- a/arch/mips/tx4927/common/tx4927_dbgio.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * linux/arch/mips/tx4927/common/tx4927_dbgio.c - * - * kgdb interface for gdb - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include - -u8 getDebugChar(void) -{ - extern u8 txx9_sio_kdbg_rd(void); - return (txx9_sio_kdbg_rd()); -} - -int putDebugChar(u8 byte) -{ - extern int txx9_sio_kdbg_wr( u8 ch ); - return (txx9_sio_kdbg_wr(byte)); -} diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c deleted file mode 100644 index 0aabd57fdad2..000000000000 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Common tx4927 irq handler - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#ifdef CONFIG_TOSHIBA_RBTX4927 -#include -#endif - -void __init tx4927_irq_init(void) -{ - mips_cpu_irq_init(); - txx9_irq_init(TX4927_IRC_REG); - set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) /* cpu timer */ - do_IRQ(TX4927_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { /* tx4927 pic */ - int irq = txx9_irq(); -#ifdef CONFIG_TOSHIBA_RBTX4927 - if (irq == TX4927_IRQ_NEST_EXT_ON_PIC) - irq = toshiba_rbtx4927_irq_nested(irq); -#endif - if (unlikely(irq < 0)) { - spurious_interrupt(); - return; - } - do_IRQ(irq); - } else if (pending & STATUSF_IP0) /* user line 0 */ - do_IRQ(TX4927_IRQ_USER0); - else if (pending & STATUSF_IP1) /* user line 1 */ - do_IRQ(TX4927_IRQ_USER1); - else - spurious_interrupt(); -} diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c deleted file mode 100644 index cc2aa9d63e82..000000000000 --- a/arch/mips/tx4927/common/tx4927_prom.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * linux/arch/mips/tx4927/common/tx4927_prom.c - * - * common tx4927 memory interface - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include - -static unsigned int __init tx4927_process_sdccr(unsigned long addr) -{ - u64 val; - unsigned int sdccr_ce; - unsigned int sdccr_bs; - unsigned int sdccr_rs; - unsigned int sdccr_cs; - unsigned int sdccr_mw; - unsigned int bs = 0; - unsigned int rs = 0; - unsigned int cs = 0; - unsigned int mw = 0; - unsigned int msize = 0; - - val = __raw_readq((void __iomem *)addr); - - /* MVMCP -- need #defs for these bits masks */ - sdccr_ce = ((val & (1 << 10)) >> 10); - sdccr_bs = ((val & (1 << 8)) >> 8); - sdccr_rs = ((val & (3 << 5)) >> 5); - sdccr_cs = ((val & (3 << 2)) >> 2); - sdccr_mw = ((val & (1 << 0)) >> 0); - - if (sdccr_ce) { - switch (sdccr_bs) { - case 0:{ - bs = 2; - break; - } - case 1:{ - bs = 4; - break; - } - } - switch (sdccr_rs) { - case 0:{ - rs = 2048; - break; - } - case 1:{ - rs = 4096; - break; - } - case 2:{ - rs = 8192; - break; - } - case 3:{ - rs = 0; - break; - } - } - switch (sdccr_cs) { - case 0:{ - cs = 256; - break; - } - case 1:{ - cs = 512; - break; - } - case 2:{ - cs = 1024; - break; - } - case 3:{ - cs = 2048; - break; - } - } - switch (sdccr_mw) { - case 0:{ - mw = 8; - break; - } /* 8 bytes = 64 bits */ - case 1:{ - mw = 4; - break; - } /* 4 bytes = 32 bits */ - } - } - - /* bytes per chip MB per chip num chips */ - msize = (((rs * cs * mw) / (1024 * 1024)) * bs); - - return (msize); -} - - -unsigned int __init tx4927_get_mem_size(void) -{ - unsigned int c0; - unsigned int c1; - unsigned int c2; - unsigned int c3; - unsigned int total; - - /* MVMCP -- need #defs for these registers */ - c0 = tx4927_process_sdccr(0xff1f8000); - c1 = tx4927_process_sdccr(0xff1f8008); - c2 = tx4927_process_sdccr(0xff1f8010); - c3 = tx4927_process_sdccr(0xff1f8018); - total = c0 + c1 + c2 + c3; - - return (total); -} diff --git a/arch/mips/tx4927/toshiba_rbtx4927/Makefile b/arch/mips/tx4927/toshiba_rbtx4927/Makefile deleted file mode 100644 index 13f96725d772..000000000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -obj-y += toshiba_rbtx4927_prom.o -obj-y += toshiba_rbtx4927_setup.o -obj-y += toshiba_rbtx4927_irq.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c deleted file mode 100644 index c18901a75cc4..000000000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c - * - * Toshiba RBTX4927 specific interrupt handlers - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -/* -IRQ Device -00 RBTX4927-ISA/00 -01 RBTX4927-ISA/01 PS2/Keyboard -02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) -03 RBTX4927-ISA/03 -04 RBTX4927-ISA/04 -05 RBTX4927-ISA/05 -06 RBTX4927-ISA/06 -07 RBTX4927-ISA/07 -08 RBTX4927-ISA/08 -09 RBTX4927-ISA/09 -10 RBTX4927-ISA/10 -11 RBTX4927-ISA/11 -12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) -13 RBTX4927-ISA/13 -14 RBTX4927-ISA/14 IDE -15 RBTX4927-ISA/15 - -16 TX4927-CP0/00 Software 0 -17 TX4927-CP0/01 Software 1 -18 TX4927-CP0/02 Cascade TX4927-CP0 -19 TX4927-CP0/03 Multiplexed -- do not use -20 TX4927-CP0/04 Multiplexed -- do not use -21 TX4927-CP0/05 Multiplexed -- do not use -22 TX4927-CP0/06 Multiplexed -- do not use -23 TX4927-CP0/07 CPU TIMER - -24 TX4927-PIC/00 -25 TX4927-PIC/01 -26 TX4927-PIC/02 -27 TX4927-PIC/03 Cascade RBTX4927-IOC -28 TX4927-PIC/04 -29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet -30 TX4927-PIC/06 -31 TX4927-PIC/07 -32 TX4927-PIC/08 TX4927 SerialIO Channel 0 -33 TX4927-PIC/09 TX4927 SerialIO Channel 1 -34 TX4927-PIC/10 -35 TX4927-PIC/11 -36 TX4927-PIC/12 -37 TX4927-PIC/13 -38 TX4927-PIC/14 -39 TX4927-PIC/15 -40 TX4927-PIC/16 TX4927 PCI PCI-C -41 TX4927-PIC/17 -42 TX4927-PIC/18 -43 TX4927-PIC/19 -44 TX4927-PIC/20 -45 TX4927-PIC/21 -46 TX4927-PIC/22 TX4927 PCI PCI-ERR -47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) -48 TX4927-PIC/24 -49 TX4927-PIC/25 -50 TX4927-PIC/26 -51 TX4927-PIC/27 -52 TX4927-PIC/28 -53 TX4927-PIC/29 -54 TX4927-PIC/30 -55 TX4927-PIC/31 - -56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] -57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] -58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] -59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] -60 RBTX4927-IOC/04 -61 RBTX4927-IOC/05 -62 RBTX4927-IOC/06 -63 RBTX4927-IOC/07 - -NOTES: -SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 -SouthBridge/ISA/pin=0 no pci irq used by this device -SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 -SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 -SouthBridge/PMC/pin=0 no pci irq used by this device -SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 -SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) -JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 -*/ - -#include -#include -#include -#include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif -#include - -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ - -#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC -#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) - -extern int tx4927_using_backplane; - -static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); -static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); - -#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" -static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { - .name = TOSHIBA_RBTX4927_IOC_NAME, - .ack = toshiba_rbtx4927_irq_ioc_disable, - .mask = toshiba_rbtx4927_irq_ioc_disable, - .mask_ack = toshiba_rbtx4927_irq_ioc_disable, - .unmask = toshiba_rbtx4927_irq_ioc_enable, -}; -#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL -#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL - -int toshiba_rbtx4927_irq_nested(int sw_irq) -{ - u8 level3; - - level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; - if (level3) { - sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && - tx4927_using_backplane) { - int irq = i8259_irq(); - if (irq >= 0) - sw_irq = irq; - } -#endif - } - return (sw_irq); -} - -static struct irqaction toshiba_rbtx4927_irq_ioc_action = { - .handler = no_action, - .flags = IRQF_SHARED, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4927_IOC_NAME -}; - -static void __init toshiba_rbtx4927_irq_ioc_init(void) -{ - int i; - - for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) - set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, - handle_level_irq); - - setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, - &toshiba_rbtx4927_irq_ioc_action); -} - -static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) -{ - unsigned char v; - - v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); -} - -static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) -{ - unsigned char v; - - v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); - mmiowb(); -} - -void __init arch_init_irq(void) -{ - extern void tx4927_irq_init(void); - - tx4927_irq_init(); - toshiba_rbtx4927_irq_ioc_init(); -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) - init_i8259_irqs(); -#endif - /* Onboard 10M Ether: High Active */ - set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); -} diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c deleted file mode 100644 index fdbad4bc6021..000000000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * rbtx4927 specific prom routines - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include - -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; /* Always ignore the "-c" at argv[0] */ - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} - -void __init prom_init(void) -{ - extern int tx4927_get_mem_size(void); - extern char* toshiba_name; - int msize; - - prom_init_cmdline(); - - if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { - mips_machtype = MACH_TOSHIBA_RBTX4927; - toshiba_name = "TX4927"; - } else { - mips_machtype = MACH_TOSHIBA_RBTX4937; - toshiba_name = "TX4937"; - } - - msize = tx4927_get_mem_size(); - add_memory_region(0, msize << 20, BOOT_MEM_RAM); -} - -void __init prom_free_prom_memory(void) -{ -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4927/RBTX4937"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c deleted file mode 100644 index 185f303c0e2a..000000000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ /dev/null @@ -1,703 +0,0 @@ -/* - * Toshiba rbtx4927 specific setup - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2002 MontaVista Software Inc. - * Author: Michael Pruznick, michael_pruznick@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif -#include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif - -/* These functions are used for rebooting or halting the machine*/ -extern void toshiba_rbtx4927_restart(char *command); -extern void toshiba_rbtx4927_halt(void); -extern void toshiba_rbtx4927_power_off(void); - -int tx4927_using_backplane = 0; - -extern void toshiba_rbtx4927_irq_setup(void); - -char *prom_getcmdline(void); - -#ifdef CONFIG_PCI -#undef TX4927_SUPPORT_COMMAND_IO -#undef TX4927_SUPPORT_PCI_66 -int tx4927_cpu_clock = 100000000; /* 100MHz */ -unsigned long mips_pci_io_base; -unsigned long mips_pci_io_size; -unsigned long mips_pci_mem_base; -unsigned long mips_pci_mem_size; -/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ -unsigned long mips_pci_io_pciaddr = 0; -unsigned long mips_memory_upper; -static int tx4927_ccfg_toeon = 1; -static int tx4927_pcic_trdyto = 0; /* default: disabled */ -unsigned long tx4927_ce_base[8]; -int tx4927_pci66 = 0; /* 0:auto */ -#endif - -char *toshiba_name = ""; - -#ifdef CONFIG_PCI -extern struct pci_controller tx4927_controller; - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; - - dev.sysdata = (void *)hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, dword, u32) - -static int __init tx4927_pcibios_init(void) -{ - unsigned int id; - u32 pci_devfn; - int devfn_start = 0; - int devfn_stop = 0xff; - int busno = 0; /* One bus on the Toshiba */ - struct pci_controller *hose = &tx4927_controller; - - for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { - early_read_config_dword(hose, busno, busno, pci_devfn, - PCI_VENDOR_ID, &id); - - if (id == 0xffffffff) { - continue; - } - - if (id == 0x94601055) { - u8 v08_64; - u32 v32_b0; - u8 v08_e1; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x64, &v08_64); - early_read_config_dword(hose, busno, busno, - pci_devfn, 0xb0, &v32_b0); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0xe1, &v08_e1); - - /* serial irq control */ - v08_64 = 0xd0; - - /* serial irq pin */ - v32_b0 |= 0x00010000; - - /* ide irq on isa14 */ - v08_e1 &= 0xf0; - v08_e1 |= 0x0d; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x64, v08_64); - early_write_config_dword(hose, busno, busno, - pci_devfn, 0xb0, v32_b0); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0xe1, v08_e1); - } - - if (id == 0x91301055) { - u8 v08_04; - u8 v08_09; - u8 v08_41; - u8 v08_43; - u8 v08_5c; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x04, &v08_04); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x09, &v08_09); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x41, &v08_41); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x43, &v08_43); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x5c, &v08_5c); - - /* enable ide master/io */ - v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); - - /* enable ide native mode */ - v08_09 |= 0x05; - - /* enable primary ide */ - v08_41 |= 0x80; - - /* enable secondary ide */ - v08_43 |= 0x80; - - /* - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - * - * This line of code is intended to provide the user with a work - * around solution to the anomalies cited in SMSC's anomaly sheet - * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". - * - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - */ - v08_5c |= 0x01; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x5c, v08_5c); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x04, v08_04); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x09, v08_09); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x41, v08_41); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x43, v08_43); - } - - } - - register_pci_controller(&tx4927_controller); - return 0; -} - -arch_initcall(tx4927_pcibios_init); - -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; - -void __init tx4927_pci_setup(void) -{ - static int called = 0; - extern unsigned int tx4927_get_mem_size(void); - - mips_memory_upper = tx4927_get_mem_size() << 20; - mips_memory_upper += KSEG0; - mips_pci_io_base = TX4927_PCIIO; - mips_pci_io_size = TX4927_PCIIO_SIZE; - mips_pci_mem_base = TX4927_PCIMEM; - mips_pci_mem_size = TX4927_PCIMEM_SIZE; - - if (!called) { - printk - ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - toshiba_name, - (unsigned short) (tx4927_pcicptr->pciid >> 16), - (unsigned short) (tx4927_pcicptr->pciid & 0xffff), - (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), - (!(tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIXARB)) ? "External" : - "Internal"); - called = 1; - } - printk("%s PCIC --%s PCICLK:", toshiba_name, - (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); - if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { - int pciclk = 0; - if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_4: - pciclk = tx4927_cpu_clock / 4; - break; - case TX4937_CCFG_PCIDIVMODE_4_5: - pciclk = tx4927_cpu_clock * 2 / 9; - break; - case TX4937_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4937_CCFG_PCIDIVMODE_5_5: - pciclk = tx4927_cpu_clock * 2 / 11; - break; - case TX4937_CCFG_PCIDIVMODE_8: - pciclk = tx4927_cpu_clock / 8; - break; - case TX4937_CCFG_PCIDIVMODE_9: - pciclk = tx4927_cpu_clock / 9; - break; - case TX4937_CCFG_PCIDIVMODE_10: - pciclk = tx4927_cpu_clock / 10; - break; - case TX4937_CCFG_PCIDIVMODE_11: - pciclk = tx4927_cpu_clock / 11; - break; - } - - else - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - pciclk = tx4927_cpu_clock * 2 / 5; - break; - case TX4927_CCFG_PCIDIVMODE_3: - pciclk = tx4927_cpu_clock / 3; - break; - case TX4927_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4927_CCFG_PCIDIVMODE_6: - pciclk = tx4927_cpu_clock / 6; - break; - } - - printk("Internal(%dMHz)", pciclk / 1000000); - } else - printk("External"); - printk("\n"); - - /* GB->PCI mappings */ - tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; - tx4927_pcicptr->g2piogbase = mips_pci_io_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PIOGBASE_ECHG -#else - TX4927_PCIC_G2PIOGBASE_BSDIS -#endif - ; - - tx4927_pcicptr->g2piopbase = 0; - - tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; - tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PMnGBASE_ECHG -#else - TX4927_PCIC_G2PMnGBASE_BSDIS -#endif - ; - tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; - - tx4927_pcicptr->g2pmmask[1] = 0; - tx4927_pcicptr->g2pmgbase[1] = 0; - tx4927_pcicptr->g2pmpbase[1] = 0; - tx4927_pcicptr->g2pmmask[2] = 0; - tx4927_pcicptr->g2pmgbase[2] = 0; - tx4927_pcicptr->g2pmpbase[2] = 0; - - - /* PCI->GB mappings (I/O 256B) */ - tx4927_pcicptr->p2giopbase = 0; /* 256B */ - - /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ - tx4927_pcicptr->p2gm0plbase = 0; - tx4927_pcicptr->p2gm0pubase = 0; - tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4927_PCIC_P2GMnGBASE_TECHG -#else - TX4927_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - - /* PCI->GB mappings (MEM 16MB) -not used */ - tx4927_pcicptr->p2gm1plbase = 0xffffffff; - tx4927_pcicptr->p2gm1pubase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[1] = 0; - - /* PCI->GB mappings (MEM 1MB) -not used */ - tx4927_pcicptr->p2gm2pbase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[2] = 0; - - - /* Enable Initiator Memory 0 Space, I/O Space, Config */ - tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; - tx4927_pcicptr->pciccfg |= - TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | - TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; - - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - tx4927_pcicptr->pcicfg1 = 0; - - if (tx4927_pcic_trdyto >= 0) { - tx4927_pcicptr->g2ptocnt &= ~0xff; - tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); - } - - /* Clear All Local Bus Status */ - tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr->pcistatus & 0x0000ffff) | - (TX4927_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; - - /* PCIC Int => IRC IRQ16 */ - tx4927_pcicptr->pcicfg2 = - (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; - - if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { - /* XXX */ - } else { - /* Reset Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; - /* Enable Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; - } - - tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; -} -#endif /* CONFIG_PCI */ - -static void __noreturn wait_forever(void) -{ - while (1) - if (cpu_wait) - (*cpu_wait)(); -} - -void toshiba_rbtx4927_restart(char *command) -{ - printk(KERN_NOTICE "System Rebooting...\n"); - - /* enable the s/w reset register */ - writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); - - /* wait for enable to be seen */ - while ((readb(RBTX4927_SW_RESET_ENABLE) & - RBTX4927_SW_RESET_ENABLE_SET) == 0x00); - - /* do a s/w reset */ - writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); - - /* do something passive while waiting for reset */ - local_irq_disable(); - wait_forever(); - /* no return */ -} - -void toshiba_rbtx4927_halt(void) -{ - printk(KERN_NOTICE "System Halted\n"); - local_irq_disable(); - wait_forever(); - /* no return */ -} - -void toshiba_rbtx4927_power_off(void) -{ - toshiba_rbtx4927_halt(); - /* no return */ -} - -void __init plat_mem_setup(void) -{ - int i; - u32 cp0_config; - char *argptr; - - printk("CPU is %s\n", toshiba_name); - - /* f/w leaves this on at startup */ - clear_c0_status(ST0_ERL); - - /* enable caches -- HCP5 does this, pmon does not */ - cp0_config = read_c0_config(); - cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); - write_c0_config(cp0_config); - - set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); - - ioport_resource.end = 0xffffffff; - iomem_resource.end = 0xffffffff; - - _machine_restart = toshiba_rbtx4927_restart; - _machine_halt = toshiba_rbtx4927_halt; - pm_power_off = toshiba_rbtx4927_power_off; - - for (i = 0; i < TX4927_NR_TMR; i++) - txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); - -#ifdef CONFIG_PCI - - /* PCIC */ - /* - * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. - * - * For TX4927: - * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). - * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) - * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) - * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) - * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) - * i.e. S9[3]: ON (83MHz), OFF (100MHz) - * - * For TX4937: - * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) - * PCIDIVMODE[10] is 0. - * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) - * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) - * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) - * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) - * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) - * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) - * - */ - if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_8: - case TX4937_CCFG_PCIDIVMODE_4: - tx4927_cpu_clock = 266666666; /* 266MHz */ - break; - case TX4937_CCFG_PCIDIVMODE_9: - case TX4937_CCFG_PCIDIVMODE_4_5: - tx4927_cpu_clock = 300000000; /* 300MHz */ - break; - default: - tx4927_cpu_clock = 333333333; /* 333MHz */ - } - else - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - case TX4927_CCFG_PCIDIVMODE_5: - tx4927_cpu_clock = 166666666; /* 166MHz */ - break; - default: - tx4927_cpu_clock = 200000000; /* 200MHz */ - } - - /* CCFG */ - /* do reset on watchdog */ - tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; - /* enable Timeout BusError */ - if (tx4927_ccfg_toeon) - tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; - - tx4927_pci_setup(); - if (tx4927_using_backplane == 1) - printk("backplane board IS installed\n"); - else - printk("No Backplane \n"); - - /* this is on ISA bus behind PCI bus, so need PCI up first */ -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) { - smsc_fdc37m81x_init(0x3f0); - smsc_fdc37m81x_config_beg(); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, - SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, - 1); - smsc_fdc37m81x_config_end(); - } -#endif -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (char *)(0xff1ff300 + i * 0x100); - req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = TX4927_IRQ_PIC_BEG + 8 + i; - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = 50000000; - early_serial_txx9_setup(&req); - } - } -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (strstr(argptr, "console=") == NULL) { - strcat(argptr, " console=ttyS0,38400"); - } -#endif -#endif - -#ifdef CONFIG_ROOT_NFS - argptr = prom_getcmdline(); - if (strstr(argptr, "root=") == NULL) { - strcat(argptr, " root=/dev/nfs rw"); - } -#endif - -#ifdef CONFIG_IP_PNP - argptr = prom_getcmdline(); - if (strstr(argptr, "ip=") == NULL) { - strcat(argptr, " ip=any"); - } -#endif -} - -void __init plat_time_init(void) -{ - mips_hpt_frequency = tx4927_cpu_clock / 2; - if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) - txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, - TXX9_IRQ_BASE + 17, - 50000000); -} - -static int __init toshiba_rbtx4927_rtc_init(void) -{ - static struct resource __initdata res = { - .start = 0x1c010000, - .end = 0x1c010000 + 0x800 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("rtc-ds1742", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(toshiba_rbtx4927_rtc_init); - -static int __init rbtx4927_ne_init(void) -{ - static struct resource __initdata res[] = { - { - .start = RBTX4927_RTL_8019_BASE, - .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, - .flags = IORESOURCE_IO, - }, { - .start = RBTX4927_RTL_8019_IRQ, - .flags = IORESOURCE_IRQ, - } - }; - struct platform_device *dev = - platform_device_register_simple("ne", -1, - res, ARRAY_SIZE(res)); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(rbtx4927_ne_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init rbtx4927_wdt_init(void) -{ - return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); -} -device_initcall(rbtx4927_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)50000000; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/tx4938/Kconfig b/arch/mips/tx4938/Kconfig deleted file mode 100644 index d90e9cd85138..000000000000 --- a/arch/mips/tx4938/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -if TOSHIBA_RBTX4938 - -comment "Multiplex Pin Select" -choice - prompt "PIO[58:61]" - default TOSHIBA_RBTX4938_MPLEX_PIO58_61 - -config TOSHIBA_RBTX4938_MPLEX_PIO58_61 - bool "PIO" -config TOSHIBA_RBTX4938_MPLEX_NAND - bool "NAND" -config TOSHIBA_RBTX4938_MPLEX_ATA - bool "ATA" - -endchoice - -config TX4938_NAND_BOOT - depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND - bool "NAND Boot Support (EXPERIMENTAL)" - help - This is only for Toshiba RBTX4938 reference board, which has NAND IPL. - Select this option if you need to use NAND boot. - -endif diff --git a/arch/mips/tx4938/common/Makefile b/arch/mips/tx4938/common/Makefile deleted file mode 100644 index 56aa1ed1ee0c..000000000000 --- a/arch/mips/tx4938/common/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for common code for Toshiba TX4927 based systems -# - -obj-y += prom.o irq.o -obj-$(CONFIG_KGDB) += dbgio.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4938/common/dbgio.c b/arch/mips/tx4938/common/dbgio.c deleted file mode 100644 index 33b9c672a322..000000000000 --- a/arch/mips/tx4938/common/dbgio.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/dbgio.c - * - * kgdb interface for gdb - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Support for TX4938 in 2.6 - Hiroshi DOYU - */ - -#include - -extern u8 txx9_sio_kdbg_rd(void); -extern int txx9_sio_kdbg_wr( u8 ch ); - -u8 getDebugChar(void) -{ - return (txx9_sio_kdbg_rd()); -} - -int putDebugChar(u8 byte) -{ - return (txx9_sio_kdbg_wr(byte)); -} - diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c deleted file mode 100644 index c059b899d120..000000000000 --- a/arch/mips/tx4938/common/irq.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/irq.c - * - * Common tx4938 irq handler - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include - -void __init -tx4938_irq_init(void) -{ - mips_cpu_irq_init(); - txx9_irq_init(TX4938_IRC_REG); - set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -int toshiba_rbtx4938_irq_nested(int irq); - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP7) - do_IRQ(TX4938_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { - int irq = txx9_irq(); - if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0)) - irq = toshiba_rbtx4938_irq_nested(irq); - if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); - } else if (pending & STATUSF_IP1) - do_IRQ(TX4938_IRQ_USER1); - else if (pending & STATUSF_IP0) - do_IRQ(TX4938_IRQ_USER0); -} diff --git a/arch/mips/tx4938/common/prom.c b/arch/mips/tx4938/common/prom.c deleted file mode 100644 index 20baeaeba4cd..000000000000 --- a/arch/mips/tx4938/common/prom.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/prom.c - * - * common tx4938 memory interface - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -#include -#include -#include - -static unsigned int __init -tx4938_process_sdccr(u64 * addr) -{ - u64 val; - unsigned int sdccr_ce; - unsigned int sdccr_rs; - unsigned int sdccr_cs; - unsigned int sdccr_mw; - unsigned int rs = 0; - unsigned int cs = 0; - unsigned int mw = 0; - unsigned int bc = 4; - unsigned int msize = 0; - - val = ____raw_readq((void __iomem *)addr); - - /* MVMCP -- need #defs for these bits masks */ - sdccr_ce = ((val & (1 << 10)) >> 10); - sdccr_rs = ((val & (3 << 5)) >> 5); - sdccr_cs = ((val & (7 << 2)) >> 2); - sdccr_mw = ((val & (1 << 0)) >> 0); - - if (sdccr_ce) { - switch (sdccr_rs) { - case 0:{ - rs = 2048; - break; - } - case 1:{ - rs = 4096; - break; - } - case 2:{ - rs = 8192; - break; - } - default:{ - rs = 0; - break; - } - } - switch (sdccr_cs) { - case 0:{ - cs = 256; - break; - } - case 1:{ - cs = 512; - break; - } - case 2:{ - cs = 1024; - break; - } - case 3:{ - cs = 2048; - break; - } - case 4:{ - cs = 4096; - break; - } - default:{ - cs = 0; - break; - } - } - switch (sdccr_mw) { - case 0:{ - mw = 8; - break; - } /* 8 bytes = 64 bits */ - case 1:{ - mw = 4; - break; - } /* 4 bytes = 32 bits */ - } - } - - /* bytes per chip MB per chip bank count */ - msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); - - /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ - /* boad supports bc=2 but no way to detect */ - - return (msize); -} - -unsigned int __init -tx4938_get_mem_size(void) -{ - unsigned int c0; - unsigned int c1; - unsigned int c2; - unsigned int c3; - unsigned int total; - - /* MVMCP -- need #defs for these registers */ - c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); - c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); - c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); - c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); - total = c0 + c1 + c2 + c3; - - return (total); -} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/Makefile b/arch/mips/tx4938/toshiba_rbtx4938/Makefile deleted file mode 100644 index 2316dd7dd1bd..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for common code for Toshiba TX4927 based systems -# - -obj-y += prom.o setup.o irq.o spi_eeprom.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c deleted file mode 100644 index 4d6a8dc46c76..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c - * - * Toshiba RBTX4938 specific interrupt handlers - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -/* -IRQ Device - -16 TX4938-CP0/00 Software 0 -17 TX4938-CP0/01 Software 1 -18 TX4938-CP0/02 Cascade TX4938-CP0 -19 TX4938-CP0/03 Multiplexed -- do not use -20 TX4938-CP0/04 Multiplexed -- do not use -21 TX4938-CP0/05 Multiplexed -- do not use -22 TX4938-CP0/06 Multiplexed -- do not use -23 TX4938-CP0/07 CPU TIMER - -24 TX4938-PIC/00 -25 TX4938-PIC/01 -26 TX4938-PIC/02 Cascade RBTX4938-IOC -27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet -28 TX4938-PIC/04 -29 TX4938-PIC/05 TX4938 ETH1 -30 TX4938-PIC/06 TX4938 ETH0 -31 TX4938-PIC/07 -32 TX4938-PIC/08 TX4938 SIO 0 -33 TX4938-PIC/09 TX4938 SIO 1 -34 TX4938-PIC/10 TX4938 DMA0 -35 TX4938-PIC/11 TX4938 DMA1 -36 TX4938-PIC/12 TX4938 DMA2 -37 TX4938-PIC/13 TX4938 DMA3 -38 TX4938-PIC/14 -39 TX4938-PIC/15 -40 TX4938-PIC/16 TX4938 PCIC -41 TX4938-PIC/17 TX4938 TMR0 -42 TX4938-PIC/18 TX4938 TMR1 -43 TX4938-PIC/19 TX4938 TMR2 -44 TX4938-PIC/20 -45 TX4938-PIC/21 -46 TX4938-PIC/22 TX4938 PCIERR -47 TX4938-PIC/23 -48 TX4938-PIC/24 -49 TX4938-PIC/25 -50 TX4938-PIC/26 -51 TX4938-PIC/27 -52 TX4938-PIC/28 -53 TX4938-PIC/29 -54 TX4938-PIC/30 -55 TX4938-PIC/31 TX4938 SPI - -56 RBTX4938-IOC/00 PCI-D -57 RBTX4938-IOC/01 PCI-C -58 RBTX4938-IOC/02 PCI-B -59 RBTX4938-IOC/03 PCI-A -60 RBTX4938-IOC/04 RTC -61 RBTX4938-IOC/05 ATA -62 RBTX4938-IOC/06 MODEM -63 RBTX4938-IOC/07 SWINT -*/ -#include -#include -#include - -static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); -static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); - -#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" -static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { - .name = TOSHIBA_RBTX4938_IOC_NAME, - .ack = toshiba_rbtx4938_irq_ioc_disable, - .mask = toshiba_rbtx4938_irq_ioc_disable, - .mask_ack = toshiba_rbtx4938_irq_ioc_disable, - .unmask = toshiba_rbtx4938_irq_ioc_enable, -}; - -int -toshiba_rbtx4938_irq_nested(int sw_irq) -{ - u8 level3; - - level3 = readb(rbtx4938_imstat_addr); - if (level3) - /* must use fls so onboard ATA has priority */ - sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; - - return sw_irq; -} - -static struct irqaction toshiba_rbtx4938_irq_ioc_action = { - .handler = no_action, - .flags = 0, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4938_IOC_NAME, -}; - -/**********************************************************************************/ -/* Functions for ioc */ -/**********************************************************************************/ -static void __init -toshiba_rbtx4938_irq_ioc_init(void) -{ - int i; - - for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) - set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, - handle_level_irq); - - setup_irq(RBTX4938_IRQ_IOCINT, - &toshiba_rbtx4938_irq_ioc_action); -} - -static void -toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) -{ - unsigned char v; - - v = readb(rbtx4938_imask_addr); - v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); - writeb(v, rbtx4938_imask_addr); - mmiowb(); -} - -static void -toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) -{ - unsigned char v; - - v = readb(rbtx4938_imask_addr); - v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); - writeb(v, rbtx4938_imask_addr); - mmiowb(); -} - -void __init arch_init_irq(void) -{ - extern void tx4938_irq_init(void); - - /* Now, interrupt control disabled, */ - /* all IRC interrupts are masked, */ - /* all IRC interrupt mode are Low Active. */ - - /* mask all IOC interrupts */ - writeb(0, rbtx4938_imask_addr); - - /* clear SoftInt interrupts */ - writeb(0, rbtx4938_softint_addr); - tx4938_irq_init(); - toshiba_rbtx4938_irq_ioc_init(); - /* Onboard 10M Ether: High Active */ - set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); -} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c deleted file mode 100644 index 1644bffa501a..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/prom.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c - * - * rbtx4938 specific prom routines - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -#include -#include -#include -#include - -#include -#include -#include - -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} - -void __init prom_init(void) -{ - extern int tx4938_get_mem_size(void); - int msize; -#ifndef CONFIG_TX4938_NAND_BOOT - prom_init_cmdline(); -#endif - - msize = tx4938_get_mem_size(); - add_memory_region(0, msize << 20, BOOT_MEM_RAM); - - return; -} - -void __init prom_free_prom_memory(void) -{ -} - -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ - return; -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4938"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c deleted file mode 100644 index 3a3659e8633a..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ /dev/null @@ -1,1124 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c - * - * Setup pointers to hardware-dependent routines. - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif -#include -#include -#include - -extern char * __init prom_getcmdline(void); -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); - -/* These functions are used for rebooting or halting the machine*/ -extern void rbtx4938_machine_restart(char *command); -extern void rbtx4938_machine_halt(void); -extern void rbtx4938_machine_power_off(void); - -/* clocks */ -unsigned int txx9_master_clock; -unsigned int txx9_cpu_clock; -unsigned int txx9_gbus_clock; - -unsigned long rbtx4938_ce_base[8]; -unsigned long rbtx4938_ce_size[8]; -int txboard_pci66_mode; -static int tx4938_pcic_trdyto; /* default: disabled */ -static int tx4938_pcic_retryto; /* default: disabled */ -static int tx4938_ccfg_toeon = 1; - -struct tx4938_pcic_reg *pcicptrs[4] = { - tx4938_pcicptr /* default setting for TX4938 */ -}; - -static struct { - unsigned long base; - unsigned long size; -} phys_regions[16] __initdata; -static int num_phys_regions __initdata; - -#define PHYS_REGION_MINSIZE 0x10000 - -void rbtx4938_machine_halt(void) -{ - printk(KERN_NOTICE "System Halted\n"); - local_irq_disable(); - - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void rbtx4938_machine_power_off(void) -{ - rbtx4938_machine_halt(); - /* no return */ -} - -void rbtx4938_machine_restart(char *command) -{ - local_irq_disable(); - - printk("Rebooting..."); - writeb(1, rbtx4938_softresetlock_addr); - writeb(1, rbtx4938_sfvol_addr); - writeb(1, rbtx4938_softreset_addr); - while(1) - ; -} - -void __init -txboard_add_phys_region(unsigned long base, unsigned long size) -{ - if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { - printk("phys_region overflow\n"); - return; - } - phys_regions[num_phys_regions].base = base; - phys_regions[num_phys_regions].size = size; - num_phys_regions++; -} -unsigned long __init -txboard_find_free_phys_region(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - int i; - - for (base = begin / size * size; base < end; base += size) { - for (i = 0; i < num_phys_regions; i++) { - if (phys_regions[i].size && - base <= phys_regions[i].base + (phys_regions[i].size - 1) && - base + (size - 1) >= phys_regions[i].base) - break; - } - if (i == num_phys_regions) - return base; - } - return 0; -} -unsigned long __init -txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, - unsigned long *size) -{ - unsigned long sz, base; - for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { - base = txboard_find_free_phys_region(begin, end, sz); - if (base) { - *size = sz; - return base; - } - } - return 0; -} -unsigned long __init -txboard_request_phys_region_range(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region(unsigned long size) -{ - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region_shrink(unsigned long *size) -{ - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region_shrink(begin, end, size); - if (base) - txboard_add_phys_region(base, *size); - return base; -} - -#ifdef CONFIG_PCI -void __init -tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, - struct pci_controller *channel, - unsigned long pci_io_base, - int extarb) -{ - int i; - - /* Disable All Initiator Space */ - pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| - TX4938_PCIC_PCICCFG_G2PMEN(1)| - TX4938_PCIC_PCICCFG_G2PMEN(2)| - TX4938_PCIC_PCICCFG_G2PIOEN); - - /* GB->PCI mappings */ - pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; - pcicptr->g2piogbase = pci_io_base | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PIOGBASE_ECHG -#else - TX4938_PCIC_G2PIOGBASE_BSDIS -#endif - ; - pcicptr->g2piopbase = 0; - for (i = 0; i < 3; i++) { - pcicptr->g2pmmask[i] = 0; - pcicptr->g2pmgbase[i] = 0; - pcicptr->g2pmpbase[i] = 0; - } - if (channel->mem_resource->end) { - pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; - pcicptr->g2pmgbase[0] = channel->mem_resource->start | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PMnGBASE_ECHG -#else - TX4938_PCIC_G2PMnGBASE_BSDIS -#endif - ; - pcicptr->g2pmpbase[0] = channel->mem_resource->start; - } - /* PCI->GB mappings (I/O 256B) */ - pcicptr->p2giopbase = 0; /* 256B */ - pcicptr->p2giogbase = 0; - /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ - pcicptr->p2gm0plbase = 0; - pcicptr->p2gm0pubase = 0; - pcicptr->p2gmgbase[0] = 0 | - TX4938_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4938_PCIC_P2GMnGBASE_TECHG -#else - TX4938_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - /* PCI->GB mappings (MEM 16MB) */ - pcicptr->p2gm1plbase = 0xffffffff; - pcicptr->p2gm1pubase = 0xffffffff; - pcicptr->p2gmgbase[1] = 0; - /* PCI->GB mappings (MEM 1MB) */ - pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ - pcicptr->p2gmgbase[2] = 0; - - pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; - /* Enable Initiator Memory Space */ - if (channel->mem_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); - /* Enable Initiator I/O Space */ - if (channel->io_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; - /* Enable Initiator Config */ - pcicptr->pciccfg |= - TX4938_PCIC_PCICCFG_ICAEN | - TX4938_PCIC_PCICCFG_TCAR; - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - pcicptr->pcicfg1 = 0; - - pcicptr->g2ptocnt &= ~0xffff; - - if (tx4938_pcic_trdyto >= 0) { - pcicptr->g2ptocnt &= ~0xff; - pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); - } - - if (tx4938_pcic_retryto >= 0) { - pcicptr->g2ptocnt &= ~0xff00; - pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); - } - - /* Clear All Local Bus Status */ - pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - pcicptr->pcistatus = - (pcicptr->pcistatus & 0x0000ffff) | - (TX4938_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; - - if (!extarb) { - /* Reset Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; - pcicptr->pbabm = 0; - /* Enable Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; - } - - /* PCIC Int => IRC IRQ16 */ - pcicptr->pcicfg2 = - (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; - - pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; -} - -int __init -tx4938_report_pciclk(void) -{ - unsigned long pcode = TX4938_REV_PCODE(); - int pciclk = 0; - printk("TX%lx PCIC --%s PCICLK:", - pcode, - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - - switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { - case TX4938_CCFG_PCIDIVMODE_4: - pciclk = txx9_cpu_clock / 4; break; - case TX4938_CCFG_PCIDIVMODE_4_5: - pciclk = txx9_cpu_clock * 2 / 9; break; - case TX4938_CCFG_PCIDIVMODE_5: - pciclk = txx9_cpu_clock / 5; break; - case TX4938_CCFG_PCIDIVMODE_5_5: - pciclk = txx9_cpu_clock * 2 / 11; break; - case TX4938_CCFG_PCIDIVMODE_8: - pciclk = txx9_cpu_clock / 8; break; - case TX4938_CCFG_PCIDIVMODE_9: - pciclk = txx9_cpu_clock / 9; break; - case TX4938_CCFG_PCIDIVMODE_10: - pciclk = txx9_cpu_clock / 10; break; - case TX4938_CCFG_PCIDIVMODE_11: - pciclk = txx9_cpu_clock / 11; break; - } - printk("Internal(%dMHz)", pciclk / 1000000); - } else { - printk("External"); - pciclk = -1; - } - printk("\n"); - return pciclk; -} - -void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) -{ - pcicptrs[ch] = pcicptr; -} - -struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) -{ - return pcicptrs[ch]; -} - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; - - dev.sysdata = bus.sysdata = hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, word, u16 *) - -int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) -{ - u32 pci_devfn; - unsigned short vid; - int devfn_start = 0; - int devfn_stop = 0xff; - int cap66 = -1; - u16 stat; - - printk("PCI: Checking 66MHz capabilities...\n"); - - for (pci_devfn=devfn_start; pci_devfn 0; -} - -int __init -tx4938_pciclk66_setup(void) -{ - int pciclk; - - /* Assert M66EN */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; - /* Double PCICLK (if possible) */ - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - unsigned int pcidivmode = - tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; - switch (pcidivmode) { - case TX4938_CCFG_PCIDIVMODE_8: - case TX4938_CCFG_PCIDIVMODE_4: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4; - pciclk = txx9_cpu_clock / 4; - break; - case TX4938_CCFG_PCIDIVMODE_9: - case TX4938_CCFG_PCIDIVMODE_4_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; - pciclk = txx9_cpu_clock * 2 / 9; - break; - case TX4938_CCFG_PCIDIVMODE_10: - case TX4938_CCFG_PCIDIVMODE_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5; - pciclk = txx9_cpu_clock / 5; - break; - case TX4938_CCFG_PCIDIVMODE_11: - case TX4938_CCFG_PCIDIVMODE_5_5: - default: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; - pciclk = txx9_cpu_clock * 2 / 11; - break; - } - tx4938_ccfgptr->ccfg = - (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) - | pcidivmode; - printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", - (unsigned long)tx4938_ccfgptr->ccfg); - } else { - pciclk = -1; - } - return pciclk; -} - -extern struct pci_controller tx4938_pci_controller[]; -static int __init tx4938_pcibios_init(void) -{ - unsigned long mem_base[2]; - unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ - unsigned long io_base[2]; - unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ - /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ - int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); - - PCIBIOS_MIN_IO = 0x00001000UL; - - mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); - io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); - - printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - (unsigned short)(tx4938_pcicptr->pciid >> 16), - (unsigned short)(tx4938_pcicptr->pciid & 0xffff), - (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), - extarb ? "External" : "Internal"); - - /* setup PCI area */ - tx4938_pci_controller[0].io_resource->start = io_base[0]; - tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; - tx4938_pci_controller[0].mem_resource->start = mem_base[0]; - tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; - - set_tx4938_pcicptr(0, tx4938_pcicptr); - - register_pci_controller(&tx4938_pci_controller[0]); - - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { - printk("TX4938_CCFG_PCI66 already configured\n"); - txboard_pci66_mode = -1; /* already configured */ - } - - /* Reset PCI Bus */ - writeb(0, rbtx4938_pcireset_addr); - /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; - if (txboard_pci66_mode > 0) - tx4938_pciclk66_setup(); - mdelay(10); - /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; - writeb(1, rbtx4938_pcireset_addr); - mmiowb(); - tx4938_report_pcic_status1(tx4938_pcicptr); - - tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); - if (txboard_pci66_mode == 0 && - txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { - /* Reset PCI Bus */ - writeb(0, rbtx4938_pcireset_addr); - /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; - tx4938_pciclk66_setup(); - mdelay(10); - /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; - writeb(1, rbtx4938_pcireset_addr); - mmiowb(); - /* Reinitialize PCIC */ - tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); - } - - mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); - io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); - /* Reset PCIC1 */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; - /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; - else - tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; - mdelay(10); - /* clear PCIC1 reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; - tx4938_report_pcic_status1(tx4938_pcic1ptr); - - printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", - (unsigned short)(tx4938_pcic1ptr->pciid >> 16), - (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), - (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); - printk("%s PCICLK:%dMHz\n", - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", - txx9_gbus_clock / - ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / - 1000000); - - /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ - tx4938_pci_controller[1].io_resource->start = - io_base[1] - io_base[0]; - tx4938_pci_controller[1].io_resource->end = - io_base[1] - io_base[0] + io_size[1] - 1; - tx4938_pci_controller[1].mem_resource->start = mem_base[1]; - tx4938_pci_controller[1].mem_resource->end = - mem_base[1] + mem_size[1] - 1; - set_tx4938_pcicptr(1, tx4938_pcic1ptr); - - register_pci_controller(&tx4938_pci_controller[1]); - - tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); - - /* map ioport 0 to PCI I/O space address 0 */ - set_io_port_base(KSEG1 + io_base[0]); - - return 0; -} - -arch_initcall(tx4938_pcibios_init); - -#endif /* CONFIG_PCI */ - -/* SPI support */ - -/* chip select for SPI devices */ -#define SEEPROM1_CS 7 /* PIO7 */ -#define SEEPROM2_CS 0 /* IOC */ -#define SEEPROM3_CS 1 /* IOC */ -#define SRTC_CS 2 /* IOC */ - -#ifdef CONFIG_PCI -static int __init rbtx4938_ethaddr_init(void) -{ - unsigned char dat[17]; - unsigned char sum; - int i; - - /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ - if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) { - printk(KERN_ERR "seeprom: read error.\n"); - return -ENODEV; - } else { - if (strcmp(dat, "MAC") != 0) - printk(KERN_WARNING "seeprom: bad signature.\n"); - for (i = 0, sum = 0; i < sizeof(dat); i++) - sum += dat[i]; - if (sum) - printk(KERN_WARNING "seeprom: bad checksum.\n"); - } - for (i = 0; i < 2; i++) { - unsigned int id = - TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); - struct platform_device *pdev; - if (!(tx4938_ccfgptr->pcfg & - (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) - continue; - pdev = platform_device_alloc("tc35815-mac", id); - if (!pdev || - platform_device_add_data(pdev, &dat[4 + 6 * i], 6) || - platform_device_add(pdev)) - platform_device_put(pdev); - } - return 0; -} -device_initcall(rbtx4938_ethaddr_init); -#endif /* CONFIG_PCI */ - -static void __init rbtx4938_spi_setup(void) -{ - /* set SPI_SEL */ - tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; -} - -static struct resource rbtx4938_fpga_resource; - -static char pcode_str[8]; -static struct resource tx4938_reg_resource = { - .start = TX4938_REG_BASE, - .end = TX4938_REG_BASE + TX4938_REG_SIZE, - .name = pcode_str, - .flags = IORESOURCE_MEM -}; - -void __init tx4938_board_setup(void) -{ - int i; - unsigned long divmode; - int cpuclk = 0; - unsigned long pcode = TX4938_REV_PCODE(); - - ioport_resource.start = 0x1000; - ioport_resource.end = 0xffffffff; - iomem_resource.start = 0x1000; - iomem_resource.end = 0xffffffff; /* expand to 4GB */ - - sprintf(pcode_str, "TX%lx", pcode); - /* SDRAMC,EBUSC are configured by PROM */ - for (i = 0; i < 8; i++) { - if (!(tx4938_ebuscptr->cr[i] & 0x8)) - continue; /* disabled */ - rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); - txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); - } - - /* clocks */ - if (txx9_master_clock) { - /* calculate gbus_clock and cpu_clock_freq from master_clock */ - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; - switch (divmode) { - case TX4938_CCFG_DIVMODE_8: - case TX4938_CCFG_DIVMODE_10: - case TX4938_CCFG_DIVMODE_12: - case TX4938_CCFG_DIVMODE_16: - case TX4938_CCFG_DIVMODE_18: - txx9_gbus_clock = txx9_master_clock * 4; break; - default: - txx9_gbus_clock = txx9_master_clock; - } - switch (divmode) { - case TX4938_CCFG_DIVMODE_2: - case TX4938_CCFG_DIVMODE_8: - cpuclk = txx9_gbus_clock * 2; break; - case TX4938_CCFG_DIVMODE_2_5: - case TX4938_CCFG_DIVMODE_10: - cpuclk = txx9_gbus_clock * 5 / 2; break; - case TX4938_CCFG_DIVMODE_3: - case TX4938_CCFG_DIVMODE_12: - cpuclk = txx9_gbus_clock * 3; break; - case TX4938_CCFG_DIVMODE_4: - case TX4938_CCFG_DIVMODE_16: - cpuclk = txx9_gbus_clock * 4; break; - case TX4938_CCFG_DIVMODE_4_5: - case TX4938_CCFG_DIVMODE_18: - cpuclk = txx9_gbus_clock * 9 / 2; break; - } - txx9_cpu_clock = cpuclk; - } else { - if (txx9_cpu_clock == 0) { - txx9_cpu_clock = 300000000; /* 300MHz */ - } - /* calculate gbus_clock and master_clock from cpu_clock_freq */ - cpuclk = txx9_cpu_clock; - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; - switch (divmode) { - case TX4938_CCFG_DIVMODE_2: - case TX4938_CCFG_DIVMODE_8: - txx9_gbus_clock = cpuclk / 2; break; - case TX4938_CCFG_DIVMODE_2_5: - case TX4938_CCFG_DIVMODE_10: - txx9_gbus_clock = cpuclk * 2 / 5; break; - case TX4938_CCFG_DIVMODE_3: - case TX4938_CCFG_DIVMODE_12: - txx9_gbus_clock = cpuclk / 3; break; - case TX4938_CCFG_DIVMODE_4: - case TX4938_CCFG_DIVMODE_16: - txx9_gbus_clock = cpuclk / 4; break; - case TX4938_CCFG_DIVMODE_4_5: - case TX4938_CCFG_DIVMODE_18: - txx9_gbus_clock = cpuclk * 2 / 9; break; - } - switch (divmode) { - case TX4938_CCFG_DIVMODE_8: - case TX4938_CCFG_DIVMODE_10: - case TX4938_CCFG_DIVMODE_12: - case TX4938_CCFG_DIVMODE_16: - case TX4938_CCFG_DIVMODE_18: - txx9_master_clock = txx9_gbus_clock / 4; break; - default: - txx9_master_clock = txx9_gbus_clock; - } - } - /* change default value to udelay/mdelay take reasonable time */ - loops_per_jiffy = txx9_cpu_clock / HZ / 2; - - /* CCFG */ - /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; - /* do reset on watchdog */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; - /* clear PCIC1 reset */ - if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; - - /* enable Timeout BusError */ - if (tx4938_ccfg_toeon) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; - - /* DMA selection */ - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; - - /* Use external clock for external arbiter */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; - - printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", - pcode_str, - cpuclk / 1000000, txx9_master_clock / 1000000, - (unsigned long)tx4938_ccfgptr->crir, - tx4938_ccfgptr->ccfg, - tx4938_ccfgptr->pcfg); - - printk("%s SDRAMC --", pcode_str); - for (i = 0; i < 4; i++) { - unsigned long long cr = tx4938_sdramcptr->cr[i]; - unsigned long ram_base, ram_size; - if (!((unsigned long)cr & 0x00000400)) - continue; /* disabled */ - ram_base = (unsigned long)(cr >> 49) << 21; - ram_size = ((unsigned long)(cr >> 33) + 1) << 21; - if (ram_base >= 0x20000000) - continue; /* high memory (ignore) */ - printk(" CR%d:%016Lx", i, cr); - txboard_add_phys_region(ram_base, ram_size); - } - printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); - - /* SRAM */ - if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { - unsigned int size = 0x800; - unsigned long base = - (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); - txboard_add_phys_region(base, size); - } - - /* TMR */ - for (i = 0; i < TX4938_NR_TMR; i++) - txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); - - /* enable DMA */ - for (i = 0; i < 2; i++) - ____raw_writeq(TX4938_DMA_MCR_MSTEN, - (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); - - /* PIO */ - __raw_writel(0, &tx4938_pioptr->maskcpu); - __raw_writel(0, &tx4938_pioptr->maskext); - - /* TX4938 internal registers */ - if (request_resource(&iomem_resource, &tx4938_reg_resource)) - printk("request resource for internal registers failed\n"); -} - -#ifdef CONFIG_PCI -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) -{ - unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); - unsigned long g2pstatus = pcicptr->g2pstatus; - unsigned long pcicstatus = pcicptr->pcicstatus; - static struct { - unsigned long flag; - const char *str; - } pcistat_tbl[] = { - { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, - { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, - { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, - { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, - { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, - { PCI_STATUS_PARITY, "MasterParityError" }, - }, g2pstat_tbl[] = { - { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, - { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, - }, pcicstat_tbl[] = { - { TX4938_PCIC_PCICSTATUS_PME, "PME" }, - { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, - { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, - { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, - { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, - { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, - { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, - { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, - }; - int i; - - printk("pcistat:%04x(", pcistatus); - for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) - if (pcistatus & pcistat_tbl[i].flag) - printk("%s ", pcistat_tbl[i].str); - printk("), g2pstatus:%08lx(", g2pstatus); - for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) - if (g2pstatus & g2pstat_tbl[i].flag) - printk("%s ", g2pstat_tbl[i].str); - printk("), pcicstatus:%08lx(", pcicstatus); - for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) - if (pcicstatus & pcicstat_tbl[i].flag) - printk("%s ", pcicstat_tbl[i].str); - printk(")\n"); -} - -void tx4938_report_pcic_status(void) -{ - int i; - struct tx4938_pcic_reg *pcicptr; - for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) - tx4938_report_pcic_status1(pcicptr); -} - -#endif /* CONFIG_PCI */ - -void __init plat_time_init(void) -{ - mips_hpt_frequency = txx9_cpu_clock / 2; - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) - txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, - TXX9_IRQ_BASE + TX4938_IR_TMR(0), - txx9_gbus_clock / 2); -} - -void __init plat_mem_setup(void) -{ - unsigned long long pcfg; - char *argptr; - - iomem_resource.end = 0xffffffff; /* 4GB */ - - if (txx9_master_clock == 0) - txx9_master_clock = 25000000; /* 25MHz */ - tx4938_board_setup(); -#ifndef CONFIG_PCI - set_io_port_base(RBTX4938_ETHER_BASE); -#endif - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - int i; - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (char *)(0xff1ff300 + i * 0x100); - req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = RBTX4938_IRQ_IRC_SIO(i); - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = 50000000; - early_serial_txx9_setup(&req); - } - } -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (strstr(argptr, "console=") == NULL) { - strcat(argptr, " console=ttyS0,38400"); - } -#endif -#endif - -#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 - printk("PIOSEL: disabling both ata and nand selection\n"); - local_irq_disable(); - tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); -#endif - -#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND - printk("PIOSEL: enabling nand selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; -#endif - -#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA - printk("PIOSEL: enabling ata selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; -#endif - -#ifdef CONFIG_IP_PNP - argptr = prom_getcmdline(); - if (strstr(argptr, "ip=") == NULL) { - strcat(argptr, " ip=any"); - } -#endif - - -#ifdef CONFIG_FB - { - conswitchp = &dummy_con; - } -#endif - - rbtx4938_spi_setup(); - pcfg = tx4938_ccfgptr->pcfg; /* updated */ - /* fixup piosel */ - if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == - TX4938_PCFG_ATA_SEL) - writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, - rbtx4938_piosel_addr); - else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == - TX4938_PCFG_NDF_SEL) - writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, - rbtx4938_piosel_addr); - else - writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04), - rbtx4938_piosel_addr); - - rbtx4938_fpga_resource.name = "FPGA Registers"; - rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); - rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; - rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; - if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) - printk("request resource for fpga failed\n"); - - _machine_restart = rbtx4938_machine_restart; - _machine_halt = rbtx4938_machine_halt; - pm_power_off = rbtx4938_machine_power_off; - - writeb(0xff, rbtx4938_led_addr); - printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", - readb(rbtx4938_fpga_rev_addr), - readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); -} - -static int __init rbtx4938_ne_init(void) -{ - struct resource res[] = { - { - .start = RBTX4938_RTL_8019_BASE, - .end = RBTX4938_RTL_8019_BASE + 0x20 - 1, - .flags = IORESOURCE_IO, - }, { - .start = RBTX4938_RTL_8019_IRQ, - .flags = IORESOURCE_IRQ, - } - }; - struct platform_device *dev = - platform_device_register_simple("ne", -1, - res, ARRAY_SIZE(res)); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(rbtx4938_ne_init); - -/* GPIO support */ - -int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} - -static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); - -static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) -{ - u8 val; - unsigned long flags; - spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags); - val = readb(rbtx4938_spics_addr); - if (value) - val |= 1 << offset; - else - val &= ~(1 << offset); - writeb(val, rbtx4938_spics_addr); - mmiowb(); - spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags); -} - -static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip, - unsigned int offset, int value) -{ - rbtx4938_spi_gpio_set(chip, offset, value); - return 0; -} - -static struct gpio_chip rbtx4938_spi_gpio_chip = { - .set = rbtx4938_spi_gpio_set, - .direction_output = rbtx4938_spi_gpio_dir_out, - .label = "RBTX4938-SPICS", - .base = 16, - .ngpio = 3, -}; - -/* SPI support */ - -static void __init txx9_spi_init(unsigned long base, int irq) -{ - struct resource res[] = { - { - .start = base, - .end = base + 0x20 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .flags = IORESOURCE_IRQ, - }, - }; - platform_device_register_simple("spi_txx9", 0, - res, ARRAY_SIZE(res)); -} - -static int __init rbtx4938_spi_init(void) -{ - struct spi_board_info srtc_info = { - .modalias = "rtc-rs5c348", - .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */ - .bus_num = 0, - .chip_select = 16 + SRTC_CS, - /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */ - .mode = SPI_MODE_1 | SPI_CS_HIGH, - }; - spi_register_board_info(&srtc_info, 1); - spi_eeprom_register(SEEPROM1_CS); - spi_eeprom_register(16 + SEEPROM2_CS); - spi_eeprom_register(16 + SEEPROM3_CS); - gpio_request(16 + SRTC_CS, "rtc-rs5c348"); - gpio_direction_output(16 + SRTC_CS, 0); - gpio_request(SEEPROM1_CS, "seeprom1"); - gpio_direction_output(SEEPROM1_CS, 1); - gpio_request(16 + SEEPROM2_CS, "seeprom2"); - gpio_direction_output(16 + SEEPROM2_CS, 1); - gpio_request(16 + SEEPROM3_CS, "seeprom3"); - gpio_direction_output(16 + SEEPROM3_CS, 1); - txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI); - return 0; -} - -static int __init rbtx4938_arch_init(void) -{ - txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); - gpiochip_add(&rbtx4938_spi_gpio_chip); - return rbtx4938_spi_init(); -} -arch_initcall(rbtx4938_arch_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init rbtx4938_wdt_init(void) -{ - return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); -} -device_initcall(rbtx4938_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "spi-baseclk")) - return (struct clk *)(txx9_gbus_clock / 2 / 4); - if (!strcmp(id, "imbus_clk")) - return (struct clk *)(txx9_gbus_clock / 2); - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c deleted file mode 100644 index 4d6b4ade5e8c..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include - -#define AT250X0_PAGE_SIZE 8 - -/* register board information for at25 driver */ -int __init spi_eeprom_register(int chipid) -{ - static struct spi_eeprom eeprom = { - .name = "at250x0", - .byte_len = 128, - .page_size = AT250X0_PAGE_SIZE, - .flags = EE_ADDR1, - }; - struct spi_board_info info = { - .modalias = "at25", - .max_speed_hz = 1500000, /* 1.5Mbps */ - .bus_num = 0, - .chip_select = chipid, - .platform_data = &eeprom, - /* Mode 0: High-Active, Sample-Then-Shift */ - }; - - return spi_register_board_info(&info, 1); -} - -/* simple temporary spi driver to provide early access to seeprom. */ - -static struct read_param { - int chipid; - int address; - unsigned char *buf; - int len; -} *read_param; - -static int __init early_seeprom_probe(struct spi_device *spi) -{ - int stat = 0; - u8 cmd[2]; - int len = read_param->len; - char *buf = read_param->buf; - int address = read_param->address; - - dev_info(&spi->dev, "spiclk %u KHz.\n", - (spi->max_speed_hz + 500) / 1000); - if (read_param->chipid != spi->chip_select) - return -ENODEV; - while (len > 0) { - /* spi_write_then_read can only work with small chunk */ - int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE; - cmd[0] = 0x03; /* AT25_READ */ - cmd[1] = address; - stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c); - buf += c; - len -= c; - address += c; - } - return stat; -} - -static struct spi_driver early_seeprom_driver __initdata = { - .driver = { - .name = "at25", - .owner = THIS_MODULE, - }, - .probe = early_seeprom_probe, -}; - -int __init spi_eeprom_read(int chipid, int address, - unsigned char *buf, int len) -{ - int ret; - struct read_param param = { - .chipid = chipid, - .address = address, - .buf = buf, - .len = len - }; - - read_param = ¶m; - ret = spi_register_driver(&early_seeprom_driver); - if (!ret) - spi_unregister_driver(&early_seeprom_driver); - return ret; -} diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig new file mode 100644 index 000000000000..98d103402b10 --- /dev/null +++ b/arch/mips/txx9/Kconfig @@ -0,0 +1,28 @@ +config TOSHIBA_FPCIB0 + bool "FPCIB0 Backplane Support" + depends on TOSHIBA_RBTX4927 + +if TOSHIBA_RBTX4938 + +comment "Multiplex Pin Select" +choice + prompt "PIO[58:61]" + default TOSHIBA_RBTX4938_MPLEX_PIO58_61 + +config TOSHIBA_RBTX4938_MPLEX_PIO58_61 + bool "PIO" +config TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND" +config TOSHIBA_RBTX4938_MPLEX_ATA + bool "ATA" + +endchoice + +config TX4938_NAND_BOOT + depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND Boot Support (EXPERIMENTAL)" + help + This is only for Toshiba RBTX4938 reference board, which has NAND IPL. + Select this option if you need to use NAND boot. + +endif diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile new file mode 100644 index 000000000000..8cb4a7e81473 --- /dev/null +++ b/arch/mips/txx9/generic/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for common code for TXx9 based systems +# + +obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o +obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o +obj-$(CONFIG_KGDB) += dbgio.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/generic/dbgio.c b/arch/mips/txx9/generic/dbgio.c new file mode 100644 index 000000000000..33b9c672a322 --- /dev/null +++ b/arch/mips/txx9/generic/dbgio.c @@ -0,0 +1,48 @@ +/* + * linux/arch/mips/tx4938/common/dbgio.c + * + * kgdb interface for gdb + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Support for TX4938 in 2.6 - Hiroshi DOYU + */ + +#include + +extern u8 txx9_sio_kdbg_rd(void); +extern int txx9_sio_kdbg_wr( u8 ch ); + +u8 getDebugChar(void) +{ + return (txx9_sio_kdbg_rd()); +} + +int putDebugChar(u8 byte) +{ + return (txx9_sio_kdbg_wr(byte)); +} + diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c new file mode 100644 index 000000000000..685ecc2ed551 --- /dev/null +++ b/arch/mips/txx9/generic/irq_tx4927.c @@ -0,0 +1,64 @@ +/* + * Common tx4927 irq handler + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_RBTX4927 +#include +#endif + +void __init tx4927_irq_init(void) +{ + mips_cpu_irq_init(); + txx9_irq_init(TX4927_IRC_REG); + set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) /* cpu timer */ + do_IRQ(TX4927_IRQ_CPU_TIMER); + else if (pending & STATUSF_IP2) { /* tx4927 pic */ + int irq = txx9_irq(); +#ifdef CONFIG_TOSHIBA_RBTX4927 + if (irq == TX4927_IRQ_NEST_EXT_ON_PIC) + irq = toshiba_rbtx4927_irq_nested(irq); +#endif + if (unlikely(irq < 0)) { + spurious_interrupt(); + return; + } + do_IRQ(irq); + } else if (pending & STATUSF_IP0) /* user line 0 */ + do_IRQ(TX4927_IRQ_USER0); + else if (pending & STATUSF_IP1) /* user line 1 */ + do_IRQ(TX4927_IRQ_USER1); + else + spurious_interrupt(); +} diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c new file mode 100644 index 000000000000..0886d9138818 --- /dev/null +++ b/arch/mips/txx9/generic/irq_tx4938.c @@ -0,0 +1,48 @@ +/* + * linux/arch/mips/tx4938/common/irq.c + * + * Common tx4938 irq handler + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +void __init +tx4938_irq_init(void) +{ + mips_cpu_irq_init(); + txx9_irq_init(TX4938_IRC_REG); + set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); +} + +int toshiba_rbtx4938_irq_nested(int irq); + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status(); + + if (pending & STATUSF_IP7) + do_IRQ(TX4938_IRQ_CPU_TIMER); + else if (pending & STATUSF_IP2) { + int irq = txx9_irq(); + if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0)) + irq = toshiba_rbtx4938_irq_nested(irq); + if (irq >= 0) + do_IRQ(irq); + else + spurious_interrupt(); + } else if (pending & STATUSF_IP1) + do_IRQ(TX4938_IRQ_USER1); + else if (pending & STATUSF_IP0) + do_IRQ(TX4938_IRQ_USER0); +} diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c new file mode 100644 index 000000000000..12dfc377bf2f --- /dev/null +++ b/arch/mips/txx9/generic/mem_tx4927.c @@ -0,0 +1,141 @@ +/* + * linux/arch/mips/tx4927/common/tx4927_prom.c + * + * common tx4927 memory interface + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +static unsigned int __init tx4927_process_sdccr(unsigned long addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_bs; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int bs = 0; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int msize = 0; + + val = __raw_readq((void __iomem *)addr); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_bs = ((val & (1 << 8)) >> 8); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (3 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_bs) { + case 0:{ + bs = 2; + break; + } + case 1:{ + bs = 4; + break; + } + } + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + case 3:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip num chips */ + msize = (((rs * cs * mw) / (1024 * 1024)) * bs); + + return (msize); +} + + +unsigned int __init tx4927_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4927_process_sdccr(0xff1f8000); + c1 = tx4927_process_sdccr(0xff1f8008); + c2 = tx4927_process_sdccr(0xff1f8010); + c3 = tx4927_process_sdccr(0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} diff --git a/arch/mips/txx9/generic/mem_tx4938.c b/arch/mips/txx9/generic/mem_tx4938.c new file mode 100644 index 000000000000..20baeaeba4cd --- /dev/null +++ b/arch/mips/txx9/generic/mem_tx4938.c @@ -0,0 +1,124 @@ +/* + * linux/arch/mips/tx4938/common/prom.c + * + * common tx4938 memory interface + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include +#include +#include + +static unsigned int __init +tx4938_process_sdccr(u64 * addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int bc = 4; + unsigned int msize = 0; + + val = ____raw_readq((void __iomem *)addr); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (7 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + default:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + case 4:{ + cs = 4096; + break; + } + default:{ + cs = 0; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip bank count */ + msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); + + /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ + /* boad supports bc=2 but no way to detect */ + + return (msize); +} + +unsigned int __init +tx4938_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); + c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); + c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); + c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} diff --git a/arch/mips/txx9/generic/smsc_fdc37m81x.c b/arch/mips/txx9/generic/smsc_fdc37m81x.c new file mode 100644 index 000000000000..69e487467fa5 --- /dev/null +++ b/arch/mips/txx9/generic/smsc_fdc37m81x.c @@ -0,0 +1,172 @@ +/* + * Interface for smsc fdc48m81x Super IO chip + * + * Author: MontaVista Software, Inc. source@mvista.com + * + * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright 2004 (c) MontaVista Software, Inc. + */ +#include +#include +#include +#include + +#define DEBUG + +/* Common Registers */ +#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 +#define SMSC_FDC37M81X_CONFIG_DATA 0x01 +#define SMSC_FDC37M81X_CONF 0x02 +#define SMSC_FDC37M81X_INDEX 0x03 +#define SMSC_FDC37M81X_DNUM 0x07 +#define SMSC_FDC37M81X_DID 0x20 +#define SMSC_FDC37M81X_DREV 0x21 +#define SMSC_FDC37M81X_PCNT 0x22 +#define SMSC_FDC37M81X_PMGT 0x23 +#define SMSC_FDC37M81X_OSC 0x24 +#define SMSC_FDC37M81X_CONFPA0 0x26 +#define SMSC_FDC37M81X_CONFPA1 0x27 +#define SMSC_FDC37M81X_TEST4 0x2B +#define SMSC_FDC37M81X_TEST5 0x2C +#define SMSC_FDC37M81X_TEST1 0x2D +#define SMSC_FDC37M81X_TEST2 0x2E +#define SMSC_FDC37M81X_TEST3 0x2F + +/* Logical device numbers */ +#define SMSC_FDC37M81X_FDD 0x00 +#define SMSC_FDC37M81X_SERIAL1 0x04 +#define SMSC_FDC37M81X_SERIAL2 0x05 +#define SMSC_FDC37M81X_KBD 0x07 + +/* Logical device Config Registers */ +#define SMSC_FDC37M81X_ACTIVE 0x30 +#define SMSC_FDC37M81X_BASEADDR0 0x60 +#define SMSC_FDC37M81X_BASEADDR1 0x61 +#define SMSC_FDC37M81X_INT 0x70 +#define SMSC_FDC37M81X_INT2 0x72 +#define SMSC_FDC37M81X_MODE 0xF0 + +/* Chip Config Values */ +#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 +#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa +#define SMSC_FDC37M81X_CHIP_ID 0x4d + +static unsigned long g_smsc_fdc37m81x_base = 0; + +static inline unsigned char smsc_fdc37m81x_rd(unsigned char index) +{ + outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); + + return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); +} + +static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data) +{ + outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); + outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); +} + +void smsc_fdc37m81x_config_beg(void) +{ + if (g_smsc_fdc37m81x_base) { + outb(SMSC_FDC37M81X_CONFIG_ENTER, + g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); + } +} + +void smsc_fdc37m81x_config_end(void) +{ + if (g_smsc_fdc37m81x_base) + outb(SMSC_FDC37M81X_CONFIG_EXIT, + g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); +} + +u8 smsc_fdc37m81x_config_get(u8 reg) +{ + u8 val = 0; + + if (g_smsc_fdc37m81x_base) + val = smsc_fdc37m81x_rd(reg); + + return val; +} + +void smsc_fdc37m81x_config_set(u8 reg, u8 val) +{ + if (g_smsc_fdc37m81x_base) + smsc_dc37m81x_wr(reg, val); +} + +unsigned long __init smsc_fdc37m81x_init(unsigned long port) +{ + const int field = sizeof(unsigned long) * 2; + u8 chip_id; + + if (g_smsc_fdc37m81x_base) + printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n", + field, g_smsc_fdc37m81x_base); + + g_smsc_fdc37m81x_base = port; + + smsc_fdc37m81x_config_beg(); + + chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID); + if (chip_id == SMSC_FDC37M81X_CHIP_ID) + smsc_fdc37m81x_config_end(); + else { + printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n", + chip_id); + g_smsc_fdc37m81x_base = 0; + } + + return g_smsc_fdc37m81x_base; +} + +#ifdef DEBUG +void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg) +{ + printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, + smsc_fdc37m81x_rd(reg)); +} + +void smsc_fdc37m81x_config_dump(void) +{ + u8 orig; + char *fname = "smsc_fdc37m81x_config_dump()"; + + smsc_fdc37m81x_config_beg(); + + orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); + + printk("%s: common\n", fname); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_DNUM); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_DID); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_DREV); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_PCNT); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_PMGT); + + printk("%s: keyboard\n", fname); + smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_ACTIVE); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_INT); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_INT2); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_LDCR_F0); + + smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig); + + smsc_fdc37m81x_config_end(); +} +#endif diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile new file mode 100644 index 000000000000..5f83ea375225 --- /dev/null +++ b/arch/mips/txx9/jmr3927/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for TOSHIBA JMR-TX3927 board +# + +obj-y += prom.o init.o irq.o setup.o +obj-$(CONFIG_KGDB) += kgdb_io.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/jmr3927/init.c b/arch/mips/txx9/jmr3927/init.c new file mode 100644 index 000000000000..1bbb5343baf4 --- /dev/null +++ b/arch/mips/txx9/jmr3927/init.c @@ -0,0 +1,57 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * arch/mips/jmr3927/common/init.c + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +extern void __init prom_init_cmdline(void); + +const char *get_system_type(void) +{ + return "Toshiba" +#ifdef CONFIG_TOSHIBA_JMR3927 + " JMR_TX3927" +#endif + ; +} + +extern void puts(const char *cp); + +void __init prom_init(void) +{ +#ifdef CONFIG_TOSHIBA_JMR3927 + /* CCFG */ + if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) + puts("Warning: TX3927 TLB off\n"); +#endif + + prom_init_cmdline(); + add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); +} diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c new file mode 100644 index 000000000000..85e1daf15c7b --- /dev/null +++ b/arch/mips/txx9/jmr3927/irq.c @@ -0,0 +1,174 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#if JMR3927_IRQ_END > NR_IRQS +#error JMR3927_IRQ_END > NR_IRQS +#endif + +static unsigned char irc_level[TX3927_NUM_IR] = { + 5, 5, 5, 5, 5, 5, /* INT[5:0] */ + 7, 7, /* SIO */ + 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ + 6, 6, 6 /* TMR */ +}; + +/* + * CP0_STATUS is a thread's resource (saved/restored on context switch). + * So disable_irq/enable_irq MUST handle IOC/IRC registers. + */ +static void mask_irq_ioc(unsigned int irq) +{ + /* 0: mask */ + unsigned int irq_nr = irq - JMR3927_IRQ_IOC; + unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} +static void unmask_irq_ioc(unsigned int irq) +{ + /* 0: mask */ + unsigned int irq_nr = irq - JMR3927_IRQ_IOC; + unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long cp0_cause = read_c0_cause(); + int irq; + + if ((cp0_cause & CAUSEF_IP7) == 0) + return; + irq = (cp0_cause >> CAUSEB_IP2) & 0x0f; + + do_IRQ(irq + JMR3927_IRQ_IRC); +} + +static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) +{ + unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); + int i; + + for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { + if (istat & (1 << i)) { + irq = JMR3927_IRQ_IOC + i; + do_IRQ(irq); + } + } + return IRQ_HANDLED; +} + +static struct irqaction ioc_action = { + .handler = jmr3927_ioc_interrupt, + .mask = CPU_MASK_NONE, + .name = "IOC", +}; + +static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) +{ + printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); + printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", + tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); + + return IRQ_HANDLED; +} +static struct irqaction pcierr_action = { + .handler = jmr3927_pcierr_interrupt, + .mask = CPU_MASK_NONE, + .name = "PCI error", +}; + +static void __init jmr3927_irq_init(void); + +void __init arch_init_irq(void) +{ + /* Now, interrupt control disabled, */ + /* all IRC interrupts are masked, */ + /* all IRC interrupt mode are Low Active. */ + + /* mask all IOC interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR); + /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */ + jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR); + + /* clear PCI Soft interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR); + /* clear PCI Reset interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + + jmr3927_irq_init(); + + /* setup IOC interrupt 1 (PCI, MODEM) */ + setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); + +#ifdef CONFIG_PCI + setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); +#endif + + /* enable all CPU interrupt bits. */ + set_c0_status(ST0_IM); /* IE bit is still 0. */ +} + +static struct irq_chip jmr3927_irq_ioc = { + .name = "jmr3927_ioc", + .ack = mask_irq_ioc, + .mask = mask_irq_ioc, + .mask_ack = mask_irq_ioc, + .unmask = unmask_irq_ioc, +}; + +static void __init jmr3927_irq_init(void) +{ + u32 i; + + txx9_irq_init(TX3927_IRC_REG); + for (i = 0; i < TXx9_MAX_IR; i++) + txx9_irq_set_pri(i, irc_level[i]); + for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) + set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); +} diff --git a/arch/mips/txx9/jmr3927/kgdb_io.c b/arch/mips/txx9/jmr3927/kgdb_io.c new file mode 100644 index 000000000000..5bd757e56f79 --- /dev/null +++ b/arch/mips/txx9/jmr3927/kgdb_io.c @@ -0,0 +1,105 @@ +/* + * BRIEF MODULE DESCRIPTION + * Low level uart routines to directly access a TX[34]927 SIO. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com or source@mvista.com + * + * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#define TIMEOUT 0xffffff + +static int remoteDebugInitialized = 0; +static void debugInit(int baud); + +int putDebugChar(unsigned char c) +{ + int i = 0; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(0)->tfifo = c; + + return 1; +} + +unsigned char getDebugChar(void) +{ + int i = 0; + int dicr; + char c; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + /* diable RX int. */ + dicr = tx3927_sioptr(0)->dicr; + tx3927_sioptr(0)->dicr = 0; + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID) + ; + c = tx3927_sioptr(0)->rfifo; + + /* clear RX int. status */ + tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS; + /* enable RX int. */ + tx3927_sioptr(0)->dicr = dicr; + + return c; +} + +static void debugInit(int baud) +{ + tx3927_sioptr(0)->lcr = 0x020; + tx3927_sioptr(0)->dicr = 0; + tx3927_sioptr(0)->disr = 0x4100; + tx3927_sioptr(0)->cisr = 0x014; + tx3927_sioptr(0)->fcr = 0; + tx3927_sioptr(0)->flcr = 0x02; + tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) | + TXx927_SIBGR_BCLK_T0; +} diff --git a/arch/mips/txx9/jmr3927/prom.c b/arch/mips/txx9/jmr3927/prom.c new file mode 100644 index 000000000000..8bc1049b622e --- /dev/null +++ b/arch/mips/txx9/jmr3927/prom.c @@ -0,0 +1,98 @@ +/* + * BRIEF MODULE DESCRIPTION + * PROM library initialisation code, assuming a version of + * pmon is the boot code. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Based on arch/mips/au1000/common/prom.c + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/xx files. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +#include +#include + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + int prom_argc = fw_arg0; + char **prom_argv = (char **) fw_arg1; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv[actr]); + cp += strlen(prom_argv[actr]); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ + --cp; + *cp = '\0'; +} + +void __init prom_free_prom_memory(void) +{ +} + +#define TIMEOUT 0xffffff + +void +prom_putchar(char c) +{ + int i = 0; + + do { + i++; + if (i>TIMEOUT) + break; + } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(1)->tfifo = c; + return; +} + +void +puts(const char *cp) +{ + while (*cp) + prom_putchar(*cp++); + prom_putchar('\r'); + prom_putchar('\n'); +} diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c new file mode 100644 index 000000000000..41e0f3b3af2c --- /dev/null +++ b/arch/mips/txx9/jmr3927/setup.c @@ -0,0 +1,445 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif + +#include +#include +#include +#include +#include + +extern void puts(const char *cp); + +/* don't enable - see errata */ +static int jmr3927_ccfg_toeon; + +static inline void do_reset(void) +{ +#if 1 /* Resetting PCI bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); + (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ + mdelay(1); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); +#endif + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); +} + +static void jmr3927_machine_restart(char *command) +{ + local_irq_disable(); + puts("Rebooting..."); + do_reset(); +} + +static void jmr3927_machine_halt(void) +{ + puts("JMR-TX3927 halted.\n"); + while (1); +} + +static void jmr3927_machine_power_off(void) +{ + puts("JMR-TX3927 halted. Please turn off the power.\n"); + while (1); +} + +void __init plat_time_init(void) +{ + txx9_clockevent_init(TX3927_TMR_REG(0), + TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0), + JMR3927_IMCLK); + txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK); +} + +#define DO_WRITE_THROUGH +#define DO_ENABLE_CACHE + +extern char * __init prom_getcmdline(void); +static void jmr3927_board_init(void); +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +void __init plat_mem_setup(void) +{ + char *argptr; + + set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); + + _machine_restart = jmr3927_machine_restart; + _machine_halt = jmr3927_machine_halt; + pm_power_off = jmr3927_machine_power_off; + + /* + * IO/MEM resources. + */ + ioport_resource.start = pci_io_resource.start; + ioport_resource.end = pci_io_resource.end; + iomem_resource.start = 0; + iomem_resource.end = 0xffffffff; + + /* Reboot on panic */ + panic_timeout = 180; + + /* cache setup */ + { + unsigned int conf; +#ifdef DO_ENABLE_CACHE + int mips_ic_disable = 0, mips_dc_disable = 0; +#else + int mips_ic_disable = 1, mips_dc_disable = 1; +#endif +#ifdef DO_WRITE_THROUGH + int mips_config_cwfon = 0; + int mips_config_wbon = 0; +#else + int mips_config_cwfon = 1; + int mips_config_wbon = 1; +#endif + + conf = read_c0_conf(); + conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); + conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; + conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; + conf |= mips_config_wbon ? TX39_CONF_WBON : 0; + conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; + + write_c0_conf(conf); + write_c0_cache(0); + } + + /* initialize board */ + jmr3927_board_init(); + + argptr = prom_getcmdline(); + + if ((argptr = strstr(argptr, "toeon")) != NULL) + jmr3927_ccfg_toeon = 1; + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "ip=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " ip=bootp"); + } + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i); + req.mapbase = TX3927_SIO_REG(i); + req.irq = i == 0 ? + JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; + if (i == 0) + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = JMR3927_IMCLK; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS1,115200"); + } +#endif +#endif +} + +static void tx3927_setup(void); + +static void __init jmr3927_board_init(void) +{ + tx3927_setup(); + + /* SIO0 DTR on */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); + + jmr3927_led_set(0); + + printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", + jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, + jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, + jmr3927_dipsw1(), jmr3927_dipsw2(), + jmr3927_dipsw3(), jmr3927_dipsw4()); +} + +static void __init tx3927_setup(void) +{ + int i; +#ifdef CONFIG_PCI + unsigned long mips_pci_io_base = JMR3927_PCIIO; + unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; + unsigned long mips_pci_mem_base = JMR3927_PCIMEM; + unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; + /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ + unsigned long mips_pci_io_pciaddr = 0; +#endif + + /* SDRAMC are configured by PROM */ + + /* ROMC */ + tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; + tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; + tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; + tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; + + /* CCFG */ + /* enable Timeout BusError */ + if (jmr3927_ccfg_toeon) + tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; + + /* clear BusErrorOnWrite flag */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; + /* Disable PCI snoop */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; + /* do reset on watchdog */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; + +#ifdef DO_WRITE_THROUGH + /* Enable PCI SNOOP - with write through only */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; +#endif + + /* Pin selection */ + tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; + tx3927_ccfgptr->pcfg |= + TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | + (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); + + printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", + tx3927_ccfgptr->crir, + tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); + + /* TMR */ + for (i = 0; i < TX3927_NR_TMR; i++) + txx9_tmr_init(TX3927_TMR_REG(i)); + + /* DMA */ + tx3927_dmaptr->mcr = 0; + for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { + /* reset channel */ + tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; + tx3927_dmaptr->ch[i].ccr = 0; + } + /* enable DMA */ +#ifdef __BIG_ENDIAN + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; +#else + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; +#endif + +#ifdef CONFIG_PCI + /* PCIC */ + printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", + tx3927_pcicptr->did, tx3927_pcicptr->vid, + tx3927_pcicptr->rid); + if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { + printk("External\n"); + /* XXX */ + } else { + printk("Internal\n"); + + /* Reset PCI Bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, + JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + + + /* Disable External PCI Config. Access */ + tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; +#ifdef __BIG_ENDIAN + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | + TX3927_PCIC_LBC_TIBSE | + TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; +#endif + /* LB->PCI mappings */ + tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); + tx3927_pcicptr->ilbioma = mips_pci_io_base; + tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; + tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); + tx3927_pcicptr->ilbmma = mips_pci_mem_base; + tx3927_pcicptr->ipbmma = mips_pci_mem_base; + /* PCI->LB mappings */ + tx3927_pcicptr->iobas = 0xffffffff; + tx3927_pcicptr->ioba = 0; + tx3927_pcicptr->tlbioma = 0; + tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); + tx3927_pcicptr->mba = 0; + tx3927_pcicptr->tlbmma = 0; + /* Enable Direct mapping Address Space Decoder */ + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; + + /* Clear All Local Bus Status */ + tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; + /* Enable All Local Bus Interrupts */ + tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; + /* Clear All PCI Status Error */ + tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; + /* Enable All PCI Status Error Interrupts */ + tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; + + /* PCIC Int => IRC IRQ10 */ + tx3927_pcicptr->il = TX3927_IR_PCI; + /* Target Control (per errata) */ + tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; + + /* Enable Bus Arbiter */ + tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; + + tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_IO | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + } +#endif /* CONFIG_PCI */ + + /* PIO */ + /* PIO[15:12] connected to LEDs */ + __raw_writel(0x0000f000, &tx3927_pioptr->dir); + __raw_writel(0, &tx3927_pioptr->maskcpu); + __raw_writel(0, &tx3927_pioptr->maskext); + txx9_gpio_init(TX3927_PIO_REG, 0, 16); + gpio_request(11, "dipsw1"); + gpio_request(10, "dipsw2"); + { + unsigned int conf; + + conf = read_c0_conf(); + if (!(conf & TX39_CONF_ICE)) + printk("TX3927 I-Cache disabled.\n"); + if (!(conf & TX39_CONF_DCE)) + printk("TX3927 D-Cache disabled.\n"); + else if (!(conf & TX39_CONF_WBON)) + printk("TX3927 D-Cache WriteThrough.\n"); + else if (!(conf & TX39_CONF_CWFON)) + printk("TX3927 D-Cache WriteBack.\n"); + else + printk("TX3927 D-Cache WriteBack (CWF) .\n"); + } +} + +/* This trick makes rtc-ds1742 driver usable as is. */ +unsigned long __swizzle_addr_b(unsigned long port) +{ + if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR) + return port; + port = (port & 0xffff0000) | (port & 0x7fff << 1); +#ifdef __BIG_ENDIAN + return port; +#else + return port | 1; +#endif +} +EXPORT_SYMBOL(__swizzle_addr_b); + +static int __init jmr3927_rtc_init(void) +{ + static struct resource __initdata res = { + .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, + .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev; + dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(jmr3927_rtc_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init jmr3927_wdt_init(void) +{ + return txx9_wdt_init(TX3927_TMR_REG(2)); +} +device_initcall(jmr3927_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "imbus_clk")) + return (struct clk *)JMR3927_IMCLK; + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/txx9/rbtx4927/Makefile b/arch/mips/txx9/rbtx4927/Makefile new file mode 100644 index 000000000000..f3e1f597b4f1 --- /dev/null +++ b/arch/mips/txx9/rbtx4927/Makefile @@ -0,0 +1,3 @@ +obj-y += prom.o setup.o irq.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c new file mode 100644 index 000000000000..936e50e91d95 --- /dev/null +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -0,0 +1,214 @@ +/* + * Toshiba RBTX4927 specific interrupt handlers + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* +IRQ Device +00 RBTX4927-ISA/00 +01 RBTX4927-ISA/01 PS2/Keyboard +02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) +03 RBTX4927-ISA/03 +04 RBTX4927-ISA/04 +05 RBTX4927-ISA/05 +06 RBTX4927-ISA/06 +07 RBTX4927-ISA/07 +08 RBTX4927-ISA/08 +09 RBTX4927-ISA/09 +10 RBTX4927-ISA/10 +11 RBTX4927-ISA/11 +12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) +13 RBTX4927-ISA/13 +14 RBTX4927-ISA/14 IDE +15 RBTX4927-ISA/15 + +16 TX4927-CP0/00 Software 0 +17 TX4927-CP0/01 Software 1 +18 TX4927-CP0/02 Cascade TX4927-CP0 +19 TX4927-CP0/03 Multiplexed -- do not use +20 TX4927-CP0/04 Multiplexed -- do not use +21 TX4927-CP0/05 Multiplexed -- do not use +22 TX4927-CP0/06 Multiplexed -- do not use +23 TX4927-CP0/07 CPU TIMER + +24 TX4927-PIC/00 +25 TX4927-PIC/01 +26 TX4927-PIC/02 +27 TX4927-PIC/03 Cascade RBTX4927-IOC +28 TX4927-PIC/04 +29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet +30 TX4927-PIC/06 +31 TX4927-PIC/07 +32 TX4927-PIC/08 TX4927 SerialIO Channel 0 +33 TX4927-PIC/09 TX4927 SerialIO Channel 1 +34 TX4927-PIC/10 +35 TX4927-PIC/11 +36 TX4927-PIC/12 +37 TX4927-PIC/13 +38 TX4927-PIC/14 +39 TX4927-PIC/15 +40 TX4927-PIC/16 TX4927 PCI PCI-C +41 TX4927-PIC/17 +42 TX4927-PIC/18 +43 TX4927-PIC/19 +44 TX4927-PIC/20 +45 TX4927-PIC/21 +46 TX4927-PIC/22 TX4927 PCI PCI-ERR +47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) +48 TX4927-PIC/24 +49 TX4927-PIC/25 +50 TX4927-PIC/26 +51 TX4927-PIC/27 +52 TX4927-PIC/28 +53 TX4927-PIC/29 +54 TX4927-PIC/30 +55 TX4927-PIC/31 + +56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] +57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] +58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] +59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] +60 RBTX4927-IOC/04 +61 RBTX4927-IOC/05 +62 RBTX4927-IOC/06 +63 RBTX4927-IOC/07 + +NOTES: +SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 +SouthBridge/ISA/pin=0 no pci irq used by this device +SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 +SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 +SouthBridge/PMC/pin=0 no pci irq used by this device +SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 +SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) +JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 +*/ + +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#endif +#include + +#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 +#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 + +#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ +#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ + +#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC +#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) + +extern int tx4927_using_backplane; + +static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); + +#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" +static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { + .name = TOSHIBA_RBTX4927_IOC_NAME, + .ack = toshiba_rbtx4927_irq_ioc_disable, + .mask = toshiba_rbtx4927_irq_ioc_disable, + .mask_ack = toshiba_rbtx4927_irq_ioc_disable, + .unmask = toshiba_rbtx4927_irq_ioc_enable, +}; +#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL +#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL + +int toshiba_rbtx4927_irq_nested(int sw_irq) +{ + u8 level3; + + level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + if (level3) { + sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && + tx4927_using_backplane) { + int irq = i8259_irq(); + if (irq >= 0) + sw_irq = irq; + } +#endif + } + return (sw_irq); +} + +static struct irqaction toshiba_rbtx4927_irq_ioc_action = { + .handler = no_action, + .flags = IRQF_SHARED, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4927_IOC_NAME +}; + +static void __init toshiba_rbtx4927_irq_ioc_init(void) +{ + int i; + + for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; + i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) + set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, + handle_level_irq); + + setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, + &toshiba_rbtx4927_irq_ioc_action); +} + +static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) +{ + unsigned char v; + + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); +} + +static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) +{ + unsigned char v; + + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); + mmiowb(); +} + +void __init arch_init_irq(void) +{ + extern void tx4927_irq_init(void); + + tx4927_irq_init(); + toshiba_rbtx4927_irq_ioc_init(); +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (tx4927_using_backplane) + init_i8259_irqs(); +#endif + /* Onboard 10M Ether: High Active */ + set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); +} diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c new file mode 100644 index 000000000000..0020bbee838b --- /dev/null +++ b/arch/mips/txx9/rbtx4927/prom.c @@ -0,0 +1,91 @@ +/* + * rbtx4927 specific prom routines + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = (int) fw_arg0; + char **argv = (char **) fw_arg1; + int i; /* Always ignore the "-c" at argv[0] */ + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + extern int tx4927_get_mem_size(void); + extern char* toshiba_name; + int msize; + + prom_init_cmdline(); + + if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { + mips_machtype = MACH_TOSHIBA_RBTX4927; + toshiba_name = "TX4927"; + } else { + mips_machtype = MACH_TOSHIBA_RBTX4937; + toshiba_name = "TX4937"; + } + + msize = tx4927_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4927/RBTX4937"; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c new file mode 100644 index 000000000000..df1b6e99b666 --- /dev/null +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -0,0 +1,703 @@ +/* + * Toshiba rbtx4927 specific setup + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2002 MontaVista Software Inc. + * Author: Michael Pruznick, michael_pruznick@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#endif +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif + +/* These functions are used for rebooting or halting the machine*/ +extern void toshiba_rbtx4927_restart(char *command); +extern void toshiba_rbtx4927_halt(void); +extern void toshiba_rbtx4927_power_off(void); + +int tx4927_using_backplane = 0; + +extern void toshiba_rbtx4927_irq_setup(void); + +char *prom_getcmdline(void); + +#ifdef CONFIG_PCI +#undef TX4927_SUPPORT_COMMAND_IO +#undef TX4927_SUPPORT_PCI_66 +int tx4927_cpu_clock = 100000000; /* 100MHz */ +unsigned long mips_pci_io_base; +unsigned long mips_pci_io_size; +unsigned long mips_pci_mem_base; +unsigned long mips_pci_mem_size; +/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ +unsigned long mips_pci_io_pciaddr = 0; +unsigned long mips_memory_upper; +static int tx4927_ccfg_toeon = 1; +static int tx4927_pcic_trdyto = 0; /* default: disabled */ +unsigned long tx4927_ce_base[8]; +int tx4927_pci66 = 0; /* 0:auto */ +#endif + +char *toshiba_name = ""; + +#ifdef CONFIG_PCI +extern struct pci_controller tx4927_controller; + +static struct pci_dev *fake_pci_dev(struct pci_controller *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.sysdata = (void *)hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + bus.parent = NULL; + dev.bus = &bus; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_controller *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, byte, u8 *) +EARLY_PCI_OP(read, dword, u32 *) +EARLY_PCI_OP(write, byte, u8) +EARLY_PCI_OP(write, dword, u32) + +static int __init tx4927_pcibios_init(void) +{ + unsigned int id; + u32 pci_devfn; + int devfn_start = 0; + int devfn_stop = 0xff; + int busno = 0; /* One bus on the Toshiba */ + struct pci_controller *hose = &tx4927_controller; + + for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { + early_read_config_dword(hose, busno, busno, pci_devfn, + PCI_VENDOR_ID, &id); + + if (id == 0xffffffff) { + continue; + } + + if (id == 0x94601055) { + u8 v08_64; + u32 v32_b0; + u8 v08_e1; + + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x64, &v08_64); + early_read_config_dword(hose, busno, busno, + pci_devfn, 0xb0, &v32_b0); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0xe1, &v08_e1); + + /* serial irq control */ + v08_64 = 0xd0; + + /* serial irq pin */ + v32_b0 |= 0x00010000; + + /* ide irq on isa14 */ + v08_e1 &= 0xf0; + v08_e1 |= 0x0d; + + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x64, v08_64); + early_write_config_dword(hose, busno, busno, + pci_devfn, 0xb0, v32_b0); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0xe1, v08_e1); + } + + if (id == 0x91301055) { + u8 v08_04; + u8 v08_09; + u8 v08_41; + u8 v08_43; + u8 v08_5c; + + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x04, &v08_04); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x09, &v08_09); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x41, &v08_41); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x43, &v08_43); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x5c, &v08_5c); + + /* enable ide master/io */ + v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + /* enable ide native mode */ + v08_09 |= 0x05; + + /* enable primary ide */ + v08_41 |= 0x80; + + /* enable secondary ide */ + v08_43 |= 0x80; + + /* + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + * + * This line of code is intended to provide the user with a work + * around solution to the anomalies cited in SMSC's anomaly sheet + * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". + * + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + */ + v08_5c |= 0x01; + + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x5c, v08_5c); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x04, v08_04); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x09, v08_09); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x41, v08_41); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x43, v08_43); + } + + } + + register_pci_controller(&tx4927_controller); + return 0; +} + +arch_initcall(tx4927_pcibios_init); + +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +void __init tx4927_pci_setup(void) +{ + static int called = 0; + extern unsigned int tx4927_get_mem_size(void); + + mips_memory_upper = tx4927_get_mem_size() << 20; + mips_memory_upper += KSEG0; + mips_pci_io_base = TX4927_PCIIO; + mips_pci_io_size = TX4927_PCIIO_SIZE; + mips_pci_mem_base = TX4927_PCIMEM; + mips_pci_mem_size = TX4927_PCIMEM_SIZE; + + if (!called) { + printk + ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + toshiba_name, + (unsigned short) (tx4927_pcicptr->pciid >> 16), + (unsigned short) (tx4927_pcicptr->pciid & 0xffff), + (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), + (!(tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIXARB)) ? "External" : + "Internal"); + called = 1; + } + printk("%s PCIC --%s PCICLK:", toshiba_name, + (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); + if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { + int pciclk = 0; + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { + case TX4937_CCFG_PCIDIVMODE_4: + pciclk = tx4927_cpu_clock / 4; + break; + case TX4937_CCFG_PCIDIVMODE_4_5: + pciclk = tx4927_cpu_clock * 2 / 9; + break; + case TX4937_CCFG_PCIDIVMODE_5: + pciclk = tx4927_cpu_clock / 5; + break; + case TX4937_CCFG_PCIDIVMODE_5_5: + pciclk = tx4927_cpu_clock * 2 / 11; + break; + case TX4937_CCFG_PCIDIVMODE_8: + pciclk = tx4927_cpu_clock / 8; + break; + case TX4937_CCFG_PCIDIVMODE_9: + pciclk = tx4927_cpu_clock / 9; + break; + case TX4937_CCFG_PCIDIVMODE_10: + pciclk = tx4927_cpu_clock / 10; + break; + case TX4937_CCFG_PCIDIVMODE_11: + pciclk = tx4927_cpu_clock / 11; + break; + } + + else + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + pciclk = tx4927_cpu_clock * 2 / 5; + break; + case TX4927_CCFG_PCIDIVMODE_3: + pciclk = tx4927_cpu_clock / 3; + break; + case TX4927_CCFG_PCIDIVMODE_5: + pciclk = tx4927_cpu_clock / 5; + break; + case TX4927_CCFG_PCIDIVMODE_6: + pciclk = tx4927_cpu_clock / 6; + break; + } + + printk("Internal(%dMHz)", pciclk / 1000000); + } else + printk("External"); + printk("\n"); + + /* GB->PCI mappings */ + tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; + tx4927_pcicptr->g2piogbase = mips_pci_io_base | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PIOGBASE_ECHG +#else + TX4927_PCIC_G2PIOGBASE_BSDIS +#endif + ; + + tx4927_pcicptr->g2piopbase = 0; + + tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; + tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PMnGBASE_ECHG +#else + TX4927_PCIC_G2PMnGBASE_BSDIS +#endif + ; + tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; + + tx4927_pcicptr->g2pmmask[1] = 0; + tx4927_pcicptr->g2pmgbase[1] = 0; + tx4927_pcicptr->g2pmpbase[1] = 0; + tx4927_pcicptr->g2pmmask[2] = 0; + tx4927_pcicptr->g2pmgbase[2] = 0; + tx4927_pcicptr->g2pmpbase[2] = 0; + + + /* PCI->GB mappings (I/O 256B) */ + tx4927_pcicptr->p2giopbase = 0; /* 256B */ + + /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ + tx4927_pcicptr->p2gm0plbase = 0; + tx4927_pcicptr->p2gm0pubase = 0; + tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4927_PCIC_P2GMnGBASE_TECHG +#else + TX4927_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + + /* PCI->GB mappings (MEM 16MB) -not used */ + tx4927_pcicptr->p2gm1plbase = 0xffffffff; + tx4927_pcicptr->p2gm1pubase = 0xffffffff; + tx4927_pcicptr->p2gmgbase[1] = 0; + + /* PCI->GB mappings (MEM 1MB) -not used */ + tx4927_pcicptr->p2gm2pbase = 0xffffffff; + tx4927_pcicptr->p2gmgbase[2] = 0; + + + /* Enable Initiator Memory 0 Space, I/O Space, Config */ + tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; + tx4927_pcicptr->pciccfg |= + TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | + TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; + + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + tx4927_pcicptr->pcicfg1 = 0; + + if (tx4927_pcic_trdyto >= 0) { + tx4927_pcicptr->g2ptocnt &= ~0xff; + tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); + } + + /* Clear All Local Bus Status */ + tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + tx4927_pcicptr->pcistatus = + (tx4927_pcicptr->pcistatus & 0x0000ffff) | + (TX4927_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; + + /* PCIC Int => IRC IRQ16 */ + tx4927_pcicptr->pcicfg2 = + (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; + + if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { + /* XXX */ + } else { + /* Reset Bus Arbiter */ + tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; + /* Enable Bus Arbiter */ + tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; + } + + tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; +} +#endif /* CONFIG_PCI */ + +static void __noreturn wait_forever(void) +{ + while (1) + if (cpu_wait) + (*cpu_wait)(); +} + +void toshiba_rbtx4927_restart(char *command) +{ + printk(KERN_NOTICE "System Rebooting...\n"); + + /* enable the s/w reset register */ + writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); + + /* wait for enable to be seen */ + while ((readb(RBTX4927_SW_RESET_ENABLE) & + RBTX4927_SW_RESET_ENABLE_SET) == 0x00); + + /* do a s/w reset */ + writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); + + /* do something passive while waiting for reset */ + local_irq_disable(); + wait_forever(); + /* no return */ +} + +void toshiba_rbtx4927_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + wait_forever(); + /* no return */ +} + +void toshiba_rbtx4927_power_off(void) +{ + toshiba_rbtx4927_halt(); + /* no return */ +} + +void __init plat_mem_setup(void) +{ + int i; + u32 cp0_config; + char *argptr; + + printk("CPU is %s\n", toshiba_name); + + /* f/w leaves this on at startup */ + clear_c0_status(ST0_ERL); + + /* enable caches -- HCP5 does this, pmon does not */ + cp0_config = read_c0_config(); + cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); + write_c0_config(cp0_config); + + set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); + + ioport_resource.end = 0xffffffff; + iomem_resource.end = 0xffffffff; + + _machine_restart = toshiba_rbtx4927_restart; + _machine_halt = toshiba_rbtx4927_halt; + pm_power_off = toshiba_rbtx4927_power_off; + + for (i = 0; i < TX4927_NR_TMR; i++) + txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); + +#ifdef CONFIG_PCI + + /* PCIC */ + /* + * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. + * + * For TX4927: + * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). + * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) + * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) + * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) + * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) + * i.e. S9[3]: ON (83MHz), OFF (100MHz) + * + * For TX4937: + * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) + * PCIDIVMODE[10] is 0. + * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) + * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) + * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) + * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) + * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) + * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) + * + */ + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + switch ((unsigned long)tx4927_ccfgptr-> + ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { + case TX4937_CCFG_PCIDIVMODE_8: + case TX4937_CCFG_PCIDIVMODE_4: + tx4927_cpu_clock = 266666666; /* 266MHz */ + break; + case TX4937_CCFG_PCIDIVMODE_9: + case TX4937_CCFG_PCIDIVMODE_4_5: + tx4927_cpu_clock = 300000000; /* 300MHz */ + break; + default: + tx4927_cpu_clock = 333333333; /* 333MHz */ + } + else + switch ((unsigned long)tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + case TX4927_CCFG_PCIDIVMODE_5: + tx4927_cpu_clock = 166666666; /* 166MHz */ + break; + default: + tx4927_cpu_clock = 200000000; /* 200MHz */ + } + + /* CCFG */ + /* do reset on watchdog */ + tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; + /* enable Timeout BusError */ + if (tx4927_ccfg_toeon) + tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; + + tx4927_pci_setup(); + if (tx4927_using_backplane == 1) + printk("backplane board IS installed\n"); + else + printk("No Backplane \n"); + + /* this is on ISA bus behind PCI bus, so need PCI up first */ +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (tx4927_using_backplane) { + smsc_fdc37m81x_init(0x3f0); + smsc_fdc37m81x_config_beg(); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + smsc_fdc37m81x_config_end(); + } +#endif +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = TX4927_IRQ_PIC_BEG + 8 + i; + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif +#endif + +#ifdef CONFIG_ROOT_NFS + argptr = prom_getcmdline(); + if (strstr(argptr, "root=") == NULL) { + strcat(argptr, " root=/dev/nfs rw"); + } +#endif + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = tx4927_cpu_clock / 2; + if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) + txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, + TXX9_IRQ_BASE + 17, + 50000000); +} + +static int __init toshiba_rbtx4927_rtc_init(void) +{ + static struct resource __initdata res = { + .start = 0x1c010000, + .end = 0x1c010000 + 0x800 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("rtc-ds1742", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(toshiba_rbtx4927_rtc_init); + +static int __init rbtx4927_ne_init(void) +{ + static struct resource __initdata res[] = { + { + .start = RBTX4927_RTL_8019_BASE, + .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, + .flags = IORESOURCE_IO, + }, { + .start = RBTX4927_RTL_8019_IRQ, + .flags = IORESOURCE_IRQ, + } + }; + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(rbtx4927_ne_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init rbtx4927_wdt_init(void) +{ + return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); +} +device_initcall(rbtx4927_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "imbus_clk")) + return (struct clk *)50000000; + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/txx9/rbtx4938/Makefile b/arch/mips/txx9/rbtx4938/Makefile new file mode 100644 index 000000000000..9dcc52ae5b9d --- /dev/null +++ b/arch/mips/txx9/rbtx4938/Makefile @@ -0,0 +1,3 @@ +obj-y += prom.o setup.o irq.o spi_eeprom.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c new file mode 100644 index 000000000000..f4984820251a --- /dev/null +++ b/arch/mips/txx9/rbtx4938/irq.c @@ -0,0 +1,159 @@ +/* + * Toshiba RBTX4938 specific interrupt handlers + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +/* +IRQ Device + +16 TX4938-CP0/00 Software 0 +17 TX4938-CP0/01 Software 1 +18 TX4938-CP0/02 Cascade TX4938-CP0 +19 TX4938-CP0/03 Multiplexed -- do not use +20 TX4938-CP0/04 Multiplexed -- do not use +21 TX4938-CP0/05 Multiplexed -- do not use +22 TX4938-CP0/06 Multiplexed -- do not use +23 TX4938-CP0/07 CPU TIMER + +24 TX4938-PIC/00 +25 TX4938-PIC/01 +26 TX4938-PIC/02 Cascade RBTX4938-IOC +27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet +28 TX4938-PIC/04 +29 TX4938-PIC/05 TX4938 ETH1 +30 TX4938-PIC/06 TX4938 ETH0 +31 TX4938-PIC/07 +32 TX4938-PIC/08 TX4938 SIO 0 +33 TX4938-PIC/09 TX4938 SIO 1 +34 TX4938-PIC/10 TX4938 DMA0 +35 TX4938-PIC/11 TX4938 DMA1 +36 TX4938-PIC/12 TX4938 DMA2 +37 TX4938-PIC/13 TX4938 DMA3 +38 TX4938-PIC/14 +39 TX4938-PIC/15 +40 TX4938-PIC/16 TX4938 PCIC +41 TX4938-PIC/17 TX4938 TMR0 +42 TX4938-PIC/18 TX4938 TMR1 +43 TX4938-PIC/19 TX4938 TMR2 +44 TX4938-PIC/20 +45 TX4938-PIC/21 +46 TX4938-PIC/22 TX4938 PCIERR +47 TX4938-PIC/23 +48 TX4938-PIC/24 +49 TX4938-PIC/25 +50 TX4938-PIC/26 +51 TX4938-PIC/27 +52 TX4938-PIC/28 +53 TX4938-PIC/29 +54 TX4938-PIC/30 +55 TX4938-PIC/31 TX4938 SPI + +56 RBTX4938-IOC/00 PCI-D +57 RBTX4938-IOC/01 PCI-C +58 RBTX4938-IOC/02 PCI-B +59 RBTX4938-IOC/03 PCI-A +60 RBTX4938-IOC/04 RTC +61 RBTX4938-IOC/05 ATA +62 RBTX4938-IOC/06 MODEM +63 RBTX4938-IOC/07 SWINT +*/ +#include +#include +#include + +static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); + +#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" +static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { + .name = TOSHIBA_RBTX4938_IOC_NAME, + .ack = toshiba_rbtx4938_irq_ioc_disable, + .mask = toshiba_rbtx4938_irq_ioc_disable, + .mask_ack = toshiba_rbtx4938_irq_ioc_disable, + .unmask = toshiba_rbtx4938_irq_ioc_enable, +}; + +int +toshiba_rbtx4938_irq_nested(int sw_irq) +{ + u8 level3; + + level3 = readb(rbtx4938_imstat_addr); + if (level3) + /* must use fls so onboard ATA has priority */ + sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; + + return sw_irq; +} + +static struct irqaction toshiba_rbtx4938_irq_ioc_action = { + .handler = no_action, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4938_IOC_NAME, +}; + +/**********************************************************************************/ +/* Functions for ioc */ +/**********************************************************************************/ +static void __init +toshiba_rbtx4938_irq_ioc_init(void) +{ + int i; + + for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; + i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) + set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, + handle_level_irq); + + setup_irq(RBTX4938_IRQ_IOCINT, + &toshiba_rbtx4938_irq_ioc_action); +} + +static void +toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) +{ + unsigned char v; + + v = readb(rbtx4938_imask_addr); + v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + writeb(v, rbtx4938_imask_addr); + mmiowb(); +} + +static void +toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) +{ + unsigned char v; + + v = readb(rbtx4938_imask_addr); + v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + writeb(v, rbtx4938_imask_addr); + mmiowb(); +} + +void __init arch_init_irq(void) +{ + extern void tx4938_irq_init(void); + + /* Now, interrupt control disabled, */ + /* all IRC interrupts are masked, */ + /* all IRC interrupt mode are Low Active. */ + + /* mask all IOC interrupts */ + writeb(0, rbtx4938_imask_addr); + + /* clear SoftInt interrupts */ + writeb(0, rbtx4938_softint_addr); + tx4938_irq_init(); + toshiba_rbtx4938_irq_ioc_init(); + /* Onboard 10M Ether: High Active */ + set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); +} diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c new file mode 100644 index 000000000000..134fcc2dc7d2 --- /dev/null +++ b/arch/mips/txx9/rbtx4938/prom.c @@ -0,0 +1,72 @@ +/* + * rbtx4938 specific prom routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include +#include +#include +#include + +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = (int) fw_arg0; + char **argv = (char **) fw_arg1; + int i; + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + extern int tx4938_get_mem_size(void); + int msize; +#ifndef CONFIG_TX4938_NAND_BOOT + prom_init_cmdline(); +#endif + + msize = tx4938_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); + + return; +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ + return; +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4938"; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c new file mode 100644 index 000000000000..bbd572c9675b --- /dev/null +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -0,0 +1,1122 @@ +/* + * Setup pointers to hardware-dependent routines. + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif +#include +#include +#include + +extern char * __init prom_getcmdline(void); +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); + +/* These functions are used for rebooting or halting the machine*/ +extern void rbtx4938_machine_restart(char *command); +extern void rbtx4938_machine_halt(void); +extern void rbtx4938_machine_power_off(void); + +/* clocks */ +unsigned int txx9_master_clock; +unsigned int txx9_cpu_clock; +unsigned int txx9_gbus_clock; + +unsigned long rbtx4938_ce_base[8]; +unsigned long rbtx4938_ce_size[8]; +int txboard_pci66_mode; +static int tx4938_pcic_trdyto; /* default: disabled */ +static int tx4938_pcic_retryto; /* default: disabled */ +static int tx4938_ccfg_toeon = 1; + +struct tx4938_pcic_reg *pcicptrs[4] = { + tx4938_pcicptr /* default setting for TX4938 */ +}; + +static struct { + unsigned long base; + unsigned long size; +} phys_regions[16] __initdata; +static int num_phys_regions __initdata; + +#define PHYS_REGION_MINSIZE 0x10000 + +void rbtx4938_machine_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void rbtx4938_machine_power_off(void) +{ + rbtx4938_machine_halt(); + /* no return */ +} + +void rbtx4938_machine_restart(char *command) +{ + local_irq_disable(); + + printk("Rebooting..."); + writeb(1, rbtx4938_softresetlock_addr); + writeb(1, rbtx4938_sfvol_addr); + writeb(1, rbtx4938_softreset_addr); + while(1) + ; +} + +void __init +txboard_add_phys_region(unsigned long base, unsigned long size) +{ + if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { + printk("phys_region overflow\n"); + return; + } + phys_regions[num_phys_regions].base = base; + phys_regions[num_phys_regions].size = size; + num_phys_regions++; +} +unsigned long __init +txboard_find_free_phys_region(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + int i; + + for (base = begin / size * size; base < end; base += size) { + for (i = 0; i < num_phys_regions; i++) { + if (phys_regions[i].size && + base <= phys_regions[i].base + (phys_regions[i].size - 1) && + base + (size - 1) >= phys_regions[i].base) + break; + } + if (i == num_phys_regions) + return base; + } + return 0; +} +unsigned long __init +txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, + unsigned long *size) +{ + unsigned long sz, base; + for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { + base = txboard_find_free_phys_region(begin, end, sz); + if (base) { + *size = sz; + return base; + } + } + return 0; +} +unsigned long __init +txboard_request_phys_region_range(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region(unsigned long size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region_shrink(unsigned long *size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region_shrink(begin, end, size); + if (base) + txboard_add_phys_region(base, *size); + return base; +} + +#ifdef CONFIG_PCI +void __init +tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, + struct pci_controller *channel, + unsigned long pci_io_base, + int extarb) +{ + int i; + + /* Disable All Initiator Space */ + pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| + TX4938_PCIC_PCICCFG_G2PMEN(1)| + TX4938_PCIC_PCICCFG_G2PMEN(2)| + TX4938_PCIC_PCICCFG_G2PIOEN); + + /* GB->PCI mappings */ + pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; + pcicptr->g2piogbase = pci_io_base | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PIOGBASE_ECHG +#else + TX4938_PCIC_G2PIOGBASE_BSDIS +#endif + ; + pcicptr->g2piopbase = 0; + for (i = 0; i < 3; i++) { + pcicptr->g2pmmask[i] = 0; + pcicptr->g2pmgbase[i] = 0; + pcicptr->g2pmpbase[i] = 0; + } + if (channel->mem_resource->end) { + pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; + pcicptr->g2pmgbase[0] = channel->mem_resource->start | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PMnGBASE_ECHG +#else + TX4938_PCIC_G2PMnGBASE_BSDIS +#endif + ; + pcicptr->g2pmpbase[0] = channel->mem_resource->start; + } + /* PCI->GB mappings (I/O 256B) */ + pcicptr->p2giopbase = 0; /* 256B */ + pcicptr->p2giogbase = 0; + /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ + pcicptr->p2gm0plbase = 0; + pcicptr->p2gm0pubase = 0; + pcicptr->p2gmgbase[0] = 0 | + TX4938_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4938_PCIC_P2GMnGBASE_TECHG +#else + TX4938_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + /* PCI->GB mappings (MEM 16MB) */ + pcicptr->p2gm1plbase = 0xffffffff; + pcicptr->p2gm1pubase = 0xffffffff; + pcicptr->p2gmgbase[1] = 0; + /* PCI->GB mappings (MEM 1MB) */ + pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ + pcicptr->p2gmgbase[2] = 0; + + pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; + /* Enable Initiator Memory Space */ + if (channel->mem_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); + /* Enable Initiator I/O Space */ + if (channel->io_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; + /* Enable Initiator Config */ + pcicptr->pciccfg |= + TX4938_PCIC_PCICCFG_ICAEN | + TX4938_PCIC_PCICCFG_TCAR; + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + pcicptr->pcicfg1 = 0; + + pcicptr->g2ptocnt &= ~0xffff; + + if (tx4938_pcic_trdyto >= 0) { + pcicptr->g2ptocnt &= ~0xff; + pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); + } + + if (tx4938_pcic_retryto >= 0) { + pcicptr->g2ptocnt &= ~0xff00; + pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); + } + + /* Clear All Local Bus Status */ + pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + pcicptr->pcistatus = + (pcicptr->pcistatus & 0x0000ffff) | + (TX4938_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; + + if (!extarb) { + /* Reset Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; + pcicptr->pbabm = 0; + /* Enable Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; + } + + /* PCIC Int => IRC IRQ16 */ + pcicptr->pcicfg2 = + (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; + + pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; +} + +int __init +tx4938_report_pciclk(void) +{ + unsigned long pcode = TX4938_REV_PCODE(); + int pciclk = 0; + printk("TX%lx PCIC --%s PCICLK:", + pcode, + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + + switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_4: + pciclk = txx9_cpu_clock / 4; break; + case TX4938_CCFG_PCIDIVMODE_4_5: + pciclk = txx9_cpu_clock * 2 / 9; break; + case TX4938_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4938_CCFG_PCIDIVMODE_5_5: + pciclk = txx9_cpu_clock * 2 / 11; break; + case TX4938_CCFG_PCIDIVMODE_8: + pciclk = txx9_cpu_clock / 8; break; + case TX4938_CCFG_PCIDIVMODE_9: + pciclk = txx9_cpu_clock / 9; break; + case TX4938_CCFG_PCIDIVMODE_10: + pciclk = txx9_cpu_clock / 10; break; + case TX4938_CCFG_PCIDIVMODE_11: + pciclk = txx9_cpu_clock / 11; break; + } + printk("Internal(%dMHz)", pciclk / 1000000); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) +{ + pcicptrs[ch] = pcicptr; +} + +struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) +{ + return pcicptrs[ch]; +} + +static struct pci_dev *fake_pci_dev(struct pci_controller *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.sysdata = bus.sysdata = hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + bus.parent = NULL; + dev.bus = &bus; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_controller *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, word, u16 *) + +int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int devfn_start = 0; + int devfn_stop = 0xff; + int cap66 = -1; + u16 stat; + + printk("PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn=devfn_start; pci_devfn 0; +} + +int __init +tx4938_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; + /* Double PCICLK (if possible) */ + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = + tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4; + pciclk = txx9_cpu_clock / 4; + break; + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; + pciclk = txx9_cpu_clock * 2 / 9; + break; + case TX4938_CCFG_PCIDIVMODE_10: + case TX4938_CCFG_PCIDIVMODE_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5; + pciclk = txx9_cpu_clock / 5; + break; + case TX4938_CCFG_PCIDIVMODE_11: + case TX4938_CCFG_PCIDIVMODE_5_5: + default: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; + pciclk = txx9_cpu_clock * 2 / 11; + break; + } + tx4938_ccfgptr->ccfg = + (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) + | pcidivmode; + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)tx4938_ccfgptr->ccfg); + } else { + pciclk = -1; + } + return pciclk; +} + +extern struct pci_controller tx4938_pci_controller[]; +static int __init tx4938_pcibios_init(void) +{ + unsigned long mem_base[2]; + unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ + unsigned long io_base[2]; + unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ + /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ + int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); + + PCIBIOS_MIN_IO = 0x00001000UL; + + mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); + io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); + + printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + (unsigned short)(tx4938_pcicptr->pciid >> 16), + (unsigned short)(tx4938_pcicptr->pciid & 0xffff), + (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), + extarb ? "External" : "Internal"); + + /* setup PCI area */ + tx4938_pci_controller[0].io_resource->start = io_base[0]; + tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; + tx4938_pci_controller[0].mem_resource->start = mem_base[0]; + tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; + + set_tx4938_pcicptr(0, tx4938_pcicptr); + + register_pci_controller(&tx4938_pci_controller[0]); + + if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { + printk("TX4938_CCFG_PCI66 already configured\n"); + txboard_pci66_mode = -1; /* already configured */ + } + + /* Reset PCI Bus */ + writeb(0, rbtx4938_pcireset_addr); + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + if (txboard_pci66_mode > 0) + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + writeb(1, rbtx4938_pcireset_addr); + mmiowb(); + tx4938_report_pcic_status1(tx4938_pcicptr); + + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + if (txboard_pci66_mode == 0 && + txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { + /* Reset PCI Bus */ + writeb(0, rbtx4938_pcireset_addr); + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + writeb(1, rbtx4938_pcireset_addr); + mmiowb(); + /* Reinitialize PCIC */ + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + } + + mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); + io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); + /* Reset PCIC1 */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; + /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; + else + tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; + mdelay(10); + /* clear PCIC1 reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + tx4938_report_pcic_status1(tx4938_pcic1ptr); + + printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", + (unsigned short)(tx4938_pcic1ptr->pciid >> 16), + (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), + (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); + printk("%s PCICLK:%dMHz\n", + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", + txx9_gbus_clock / + ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / + 1000000); + + /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ + tx4938_pci_controller[1].io_resource->start = + io_base[1] - io_base[0]; + tx4938_pci_controller[1].io_resource->end = + io_base[1] - io_base[0] + io_size[1] - 1; + tx4938_pci_controller[1].mem_resource->start = mem_base[1]; + tx4938_pci_controller[1].mem_resource->end = + mem_base[1] + mem_size[1] - 1; + set_tx4938_pcicptr(1, tx4938_pcic1ptr); + + register_pci_controller(&tx4938_pci_controller[1]); + + tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); + + /* map ioport 0 to PCI I/O space address 0 */ + set_io_port_base(KSEG1 + io_base[0]); + + return 0; +} + +arch_initcall(tx4938_pcibios_init); + +#endif /* CONFIG_PCI */ + +/* SPI support */ + +/* chip select for SPI devices */ +#define SEEPROM1_CS 7 /* PIO7 */ +#define SEEPROM2_CS 0 /* IOC */ +#define SEEPROM3_CS 1 /* IOC */ +#define SRTC_CS 2 /* IOC */ + +#ifdef CONFIG_PCI +static int __init rbtx4938_ethaddr_init(void) +{ + unsigned char dat[17]; + unsigned char sum; + int i; + + /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ + if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) { + printk(KERN_ERR "seeprom: read error.\n"); + return -ENODEV; + } else { + if (strcmp(dat, "MAC") != 0) + printk(KERN_WARNING "seeprom: bad signature.\n"); + for (i = 0, sum = 0; i < sizeof(dat); i++) + sum += dat[i]; + if (sum) + printk(KERN_WARNING "seeprom: bad checksum.\n"); + } + for (i = 0; i < 2; i++) { + unsigned int id = + TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); + struct platform_device *pdev; + if (!(tx4938_ccfgptr->pcfg & + (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) + continue; + pdev = platform_device_alloc("tc35815-mac", id); + if (!pdev || + platform_device_add_data(pdev, &dat[4 + 6 * i], 6) || + platform_device_add(pdev)) + platform_device_put(pdev); + } + return 0; +} +device_initcall(rbtx4938_ethaddr_init); +#endif /* CONFIG_PCI */ + +static void __init rbtx4938_spi_setup(void) +{ + /* set SPI_SEL */ + tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; +} + +static struct resource rbtx4938_fpga_resource; + +static char pcode_str[8]; +static struct resource tx4938_reg_resource = { + .start = TX4938_REG_BASE, + .end = TX4938_REG_BASE + TX4938_REG_SIZE, + .name = pcode_str, + .flags = IORESOURCE_MEM +}; + +void __init tx4938_board_setup(void) +{ + int i; + unsigned long divmode; + int cpuclk = 0; + unsigned long pcode = TX4938_REV_PCODE(); + + ioport_resource.start = 0x1000; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x1000; + iomem_resource.end = 0xffffffff; /* expand to 4GB */ + + sprintf(pcode_str, "TX%lx", pcode); + /* SDRAMC,EBUSC are configured by PROM */ + for (i = 0; i < 8; i++) { + if (!(tx4938_ebuscptr->cr[i] & 0x8)) + continue; /* disabled */ + rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); + txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); + } + + /* clocks */ + if (txx9_master_clock) { + /* calculate gbus_clock and cpu_clock_freq from master_clock */ + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = txx9_master_clock * 4; break; + default: + txx9_gbus_clock = txx9_master_clock; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + cpuclk = txx9_gbus_clock * 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + cpuclk = txx9_gbus_clock * 5 / 2; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + cpuclk = txx9_gbus_clock * 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + cpuclk = txx9_gbus_clock * 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + cpuclk = txx9_gbus_clock * 9 / 2; break; + } + txx9_cpu_clock = cpuclk; + } else { + if (txx9_cpu_clock == 0) { + txx9_cpu_clock = 300000000; /* 300MHz */ + } + /* calculate gbus_clock and master_clock from cpu_clock_freq */ + cpuclk = txx9_cpu_clock; + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + txx9_gbus_clock = cpuclk / 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + txx9_gbus_clock = cpuclk * 2 / 5; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + txx9_gbus_clock = cpuclk / 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + txx9_gbus_clock = cpuclk / 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = cpuclk * 2 / 9; break; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_master_clock = txx9_gbus_clock / 4; break; + default: + txx9_master_clock = txx9_gbus_clock; + } + } + /* change default value to udelay/mdelay take reasonable time */ + loops_per_jiffy = txx9_cpu_clock / HZ / 2; + + /* CCFG */ + /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; + /* do reset on watchdog */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; + /* clear PCIC1 reset */ + if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + + /* enable Timeout BusError */ + if (tx4938_ccfg_toeon) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; + + /* DMA selection */ + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; + + /* Use external clock for external arbiter */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; + + printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", + pcode_str, + cpuclk / 1000000, txx9_master_clock / 1000000, + (unsigned long)tx4938_ccfgptr->crir, + tx4938_ccfgptr->ccfg, + tx4938_ccfgptr->pcfg); + + printk("%s SDRAMC --", pcode_str); + for (i = 0; i < 4; i++) { + unsigned long long cr = tx4938_sdramcptr->cr[i]; + unsigned long ram_base, ram_size; + if (!((unsigned long)cr & 0x00000400)) + continue; /* disabled */ + ram_base = (unsigned long)(cr >> 49) << 21; + ram_size = ((unsigned long)(cr >> 33) + 1) << 21; + if (ram_base >= 0x20000000) + continue; /* high memory (ignore) */ + printk(" CR%d:%016Lx", i, cr); + txboard_add_phys_region(ram_base, ram_size); + } + printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); + + /* SRAM */ + if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { + unsigned int size = 0x800; + unsigned long base = + (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); + txboard_add_phys_region(base, size); + } + + /* TMR */ + for (i = 0; i < TX4938_NR_TMR; i++) + txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); + + /* enable DMA */ + for (i = 0; i < 2; i++) + ____raw_writeq(TX4938_DMA_MCR_MSTEN, + (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); + + /* PIO */ + __raw_writel(0, &tx4938_pioptr->maskcpu); + __raw_writel(0, &tx4938_pioptr->maskext); + + /* TX4938 internal registers */ + if (request_resource(&iomem_resource, &tx4938_reg_resource)) + printk("request resource for internal registers failed\n"); +} + +#ifdef CONFIG_PCI +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) +{ + unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); + unsigned long g2pstatus = pcicptr->g2pstatus; + unsigned long pcicstatus = pcicptr->pcicstatus; + static struct { + unsigned long flag; + const char *str; + } pcistat_tbl[] = { + { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, + { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, + { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, + { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, + { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, + { PCI_STATUS_PARITY, "MasterParityError" }, + }, g2pstat_tbl[] = { + { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, + { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, + }, pcicstat_tbl[] = { + { TX4938_PCIC_PCICSTATUS_PME, "PME" }, + { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, + { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, + { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, + { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, + { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, + { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, + { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, + }; + int i; + + printk("pcistat:%04x(", pcistatus); + for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) + if (pcistatus & pcistat_tbl[i].flag) + printk("%s ", pcistat_tbl[i].str); + printk("), g2pstatus:%08lx(", g2pstatus); + for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) + if (g2pstatus & g2pstat_tbl[i].flag) + printk("%s ", g2pstat_tbl[i].str); + printk("), pcicstatus:%08lx(", pcicstatus); + for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) + if (pcicstatus & pcicstat_tbl[i].flag) + printk("%s ", pcicstat_tbl[i].str); + printk(")\n"); +} + +void tx4938_report_pcic_status(void) +{ + int i; + struct tx4938_pcic_reg *pcicptr; + for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) + tx4938_report_pcic_status1(pcicptr); +} + +#endif /* CONFIG_PCI */ + +void __init plat_time_init(void) +{ + mips_hpt_frequency = txx9_cpu_clock / 2; + if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) + txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, + TXX9_IRQ_BASE + TX4938_IR_TMR(0), + txx9_gbus_clock / 2); +} + +void __init plat_mem_setup(void) +{ + unsigned long long pcfg; + char *argptr; + + iomem_resource.end = 0xffffffff; /* 4GB */ + + if (txx9_master_clock == 0) + txx9_master_clock = 25000000; /* 25MHz */ + tx4938_board_setup(); +#ifndef CONFIG_PCI + set_io_port_base(RBTX4938_ETHER_BASE); +#endif + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = RBTX4938_IRQ_IRC_SIO(i); + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 + printk("PIOSEL: disabling both ata and nand selection\n"); + local_irq_disable(); + tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND + printk("PIOSEL: enabling nand selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA + printk("PIOSEL: enabling ata selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; +#endif + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif + + +#ifdef CONFIG_FB + { + conswitchp = &dummy_con; + } +#endif + + rbtx4938_spi_setup(); + pcfg = tx4938_ccfgptr->pcfg; /* updated */ + /* fixup piosel */ + if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_ATA_SEL) + writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, + rbtx4938_piosel_addr); + else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_NDF_SEL) + writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, + rbtx4938_piosel_addr); + else + writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04), + rbtx4938_piosel_addr); + + rbtx4938_fpga_resource.name = "FPGA Registers"; + rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); + rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; + rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) + printk("request resource for fpga failed\n"); + + _machine_restart = rbtx4938_machine_restart; + _machine_halt = rbtx4938_machine_halt; + pm_power_off = rbtx4938_machine_power_off; + + writeb(0xff, rbtx4938_led_addr); + printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", + readb(rbtx4938_fpga_rev_addr), + readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); +} + +static int __init rbtx4938_ne_init(void) +{ + struct resource res[] = { + { + .start = RBTX4938_RTL_8019_BASE, + .end = RBTX4938_RTL_8019_BASE + 0x20 - 1, + .flags = IORESOURCE_IO, + }, { + .start = RBTX4938_RTL_8019_IRQ, + .flags = IORESOURCE_IRQ, + } + }; + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(rbtx4938_ne_init); + +/* GPIO support */ + +int gpio_to_irq(unsigned gpio) +{ + return -EINVAL; +} + +int irq_to_gpio(unsigned irq) +{ + return -EINVAL; +} + +static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); + +static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + u8 val; + unsigned long flags; + spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags); + val = readb(rbtx4938_spics_addr); + if (value) + val |= 1 << offset; + else + val &= ~(1 << offset); + writeb(val, rbtx4938_spics_addr); + mmiowb(); + spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags); +} + +static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip, + unsigned int offset, int value) +{ + rbtx4938_spi_gpio_set(chip, offset, value); + return 0; +} + +static struct gpio_chip rbtx4938_spi_gpio_chip = { + .set = rbtx4938_spi_gpio_set, + .direction_output = rbtx4938_spi_gpio_dir_out, + .label = "RBTX4938-SPICS", + .base = 16, + .ngpio = 3, +}; + +/* SPI support */ + +static void __init txx9_spi_init(unsigned long base, int irq) +{ + struct resource res[] = { + { + .start = base, + .end = base + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .flags = IORESOURCE_IRQ, + }, + }; + platform_device_register_simple("spi_txx9", 0, + res, ARRAY_SIZE(res)); +} + +static int __init rbtx4938_spi_init(void) +{ + struct spi_board_info srtc_info = { + .modalias = "rtc-rs5c348", + .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */ + .bus_num = 0, + .chip_select = 16 + SRTC_CS, + /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */ + .mode = SPI_MODE_1 | SPI_CS_HIGH, + }; + spi_register_board_info(&srtc_info, 1); + spi_eeprom_register(SEEPROM1_CS); + spi_eeprom_register(16 + SEEPROM2_CS); + spi_eeprom_register(16 + SEEPROM3_CS); + gpio_request(16 + SRTC_CS, "rtc-rs5c348"); + gpio_direction_output(16 + SRTC_CS, 0); + gpio_request(SEEPROM1_CS, "seeprom1"); + gpio_direction_output(SEEPROM1_CS, 1); + gpio_request(16 + SEEPROM2_CS, "seeprom2"); + gpio_direction_output(16 + SEEPROM2_CS, 1); + gpio_request(16 + SEEPROM3_CS, "seeprom3"); + gpio_direction_output(16 + SEEPROM3_CS, 1); + txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI); + return 0; +} + +static int __init rbtx4938_arch_init(void) +{ + txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); + gpiochip_add(&rbtx4938_spi_gpio_chip); + return rbtx4938_spi_init(); +} +arch_initcall(rbtx4938_arch_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init rbtx4938_wdt_init(void) +{ + return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); +} +device_initcall(rbtx4938_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "spi-baseclk")) + return (struct clk *)(txx9_gbus_clock / 2 / 4); + if (!strcmp(id, "imbus_clk")) + return (struct clk *)(txx9_gbus_clock / 2); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/txx9/rbtx4938/spi_eeprom.c b/arch/mips/txx9/rbtx4938/spi_eeprom.c new file mode 100644 index 000000000000..a7ea8b041c1d --- /dev/null +++ b/arch/mips/txx9/rbtx4938/spi_eeprom.c @@ -0,0 +1,99 @@ +/* + * spi_eeprom.c + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +#define AT250X0_PAGE_SIZE 8 + +/* register board information for at25 driver */ +int __init spi_eeprom_register(int chipid) +{ + static struct spi_eeprom eeprom = { + .name = "at250x0", + .byte_len = 128, + .page_size = AT250X0_PAGE_SIZE, + .flags = EE_ADDR1, + }; + struct spi_board_info info = { + .modalias = "at25", + .max_speed_hz = 1500000, /* 1.5Mbps */ + .bus_num = 0, + .chip_select = chipid, + .platform_data = &eeprom, + /* Mode 0: High-Active, Sample-Then-Shift */ + }; + + return spi_register_board_info(&info, 1); +} + +/* simple temporary spi driver to provide early access to seeprom. */ + +static struct read_param { + int chipid; + int address; + unsigned char *buf; + int len; +} *read_param; + +static int __init early_seeprom_probe(struct spi_device *spi) +{ + int stat = 0; + u8 cmd[2]; + int len = read_param->len; + char *buf = read_param->buf; + int address = read_param->address; + + dev_info(&spi->dev, "spiclk %u KHz.\n", + (spi->max_speed_hz + 500) / 1000); + if (read_param->chipid != spi->chip_select) + return -ENODEV; + while (len > 0) { + /* spi_write_then_read can only work with small chunk */ + int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE; + cmd[0] = 0x03; /* AT25_READ */ + cmd[1] = address; + stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c); + buf += c; + len -= c; + address += c; + } + return stat; +} + +static struct spi_driver early_seeprom_driver __initdata = { + .driver = { + .name = "at25", + .owner = THIS_MODULE, + }, + .probe = early_seeprom_probe, +}; + +int __init spi_eeprom_read(int chipid, int address, + unsigned char *buf, int len) +{ + int ret; + struct read_param param = { + .chipid = chipid, + .address = address, + .buf = buf, + .len = len + }; + + read_param = ¶m; + ret = spi_register_driver(&early_seeprom_driver); + if (!ret) + spi_unregister_driver(&early_seeprom_driver); + return ret; +} diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h deleted file mode 100644 index a162268f17df..000000000000 --- a/include/asm-mips/jmr3927/jmr3927.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Defines for the TJSYS JMR-TX3927 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - */ -#ifndef __ASM_TX3927_JMR3927_H -#define __ASM_TX3927_JMR3927_H - -#include -#include -#include -#include - -/* CS */ -#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ -#define JMR3927_ROMCE1 0x1e000000 /* 4M */ -#define JMR3927_ROMCE2 0x14000000 /* 16M */ -#define JMR3927_ROMCE3 0x10000000 /* 64M */ -#define JMR3927_ROMCE5 0x1d000000 /* 4M */ -#define JMR3927_SDCS0 0x00000000 /* 32M */ -#define JMR3927_SDCS1 0x02000000 /* 32M */ -/* PCI Direct Mappings */ - -#define JMR3927_PCIMEM 0x08000000 -#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ -#define JMR3927_PCIIO 0x15000000 -#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ - -#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ -#define JMR3927_PORT_BASE KSEG1 - -/* Address map (virtual address) */ -#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) -#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) -#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) -#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) -#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) - -#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) -#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) -#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) -#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) -#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) -#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) -#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) -#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) -#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) -#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) -#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) - -/* Flash ROM */ -#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) -#define JMR3927_FLASH_SIZE 0x00400000 - -/* bits for IOC_REV/IOC_BREV (high byte) */ -#define JMR3927_IDT_MASK 0xfc -#define JMR3927_REV_MASK 0x03 -#define JMR3927_IOC_IDT 0xe0 - -/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ -#define JMR3927_IOC_INTB_PCIA 0 -#define JMR3927_IOC_INTB_PCIB 1 -#define JMR3927_IOC_INTB_PCIC 2 -#define JMR3927_IOC_INTB_PCID 3 -#define JMR3927_IOC_INTB_MODEM 4 -#define JMR3927_IOC_INTB_INT6 5 -#define JMR3927_IOC_INTB_INT7 6 -#define JMR3927_IOC_INTB_SOFT 7 -#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) -#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) -#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) -#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) -#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) -#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) -#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) -#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) - -/* bits for IOC_RESET (high byte) */ -#define JMR3927_IOC_RESET_CPU 1 -#define JMR3927_IOC_RESET_PCI 2 - -#if defined(__BIG_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) -#elif defined(__LITTLE_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) -#else -#error "No Endian" -#endif - -/* LED macro */ -#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) - -#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) - -/* DIPSW4 macro */ -#define jmr3927_dipsw1() (gpio_get_value(11) == 0) -#define jmr3927_dipsw2() (gpio_get_value(10) == 0) -#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) -#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) - -/* - * IRQ mappings - */ - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an JMR machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ -#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ - -#define JMR3927_IRQ_IRC TXX9_IRQ_BASE -#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) -#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) - -#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) -#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) -#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) -#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) -#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) -#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) -#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) -#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) -#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) -#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) -#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) -#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) -#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) -#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) -#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) -#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) -#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) -#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) -#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) -#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) -#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) - -/* IOC (PCI, MODEM) */ -#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 -/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ -#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 - -/* Clocks */ -#define JMR3927_CORECLK 132710400 /* 132.7MHz */ -#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ -#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ - -/* - * TX3927 Pin Configuration: - * - * PCFG bits Avail Dead - * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] - * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] - * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, - * GDBGE* PIO[2:1] - * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] - * SELTMR[2:0]:000 TIMER[1:0] - * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], - * DMAREQ[1],DMAACK[1] - * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] - * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] - * SELDONE:1 DMADONE PIO[7] - * - * Usable pins are: - * RXD[1;0],TXD[1:0],CTS[0],RTS[0], - * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] - * INT[3:0] - */ - -#endif /* __ASM_TX3927_JMR3927_H */ diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h deleted file mode 100644 index fb580333c102..000000000000 --- a/include/asm-mips/jmr3927/tx3927.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Toshiba Corporation - */ -#ifndef __ASM_TX3927_H -#define __ASM_TX3927_H - -#include - -#define TX3927_SDRAMC_REG 0xfffe8000 -#define TX3927_ROMC_REG 0xfffe9000 -#define TX3927_DMA_REG 0xfffeb000 -#define TX3927_IRC_REG 0xfffec000 -#define TX3927_PCIC_REG 0xfffed000 -#define TX3927_CCFG_REG 0xfffee000 -#define TX3927_NR_TMR 3 -#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) -#define TX3927_NR_SIO 2 -#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) -#define TX3927_PIO_REG 0xfffef500 - -struct tx3927_sdramc_reg { - volatile unsigned long cr[8]; - volatile unsigned long tr[3]; - volatile unsigned long cmd; - volatile unsigned long smrs[2]; -}; - -struct tx3927_romc_reg { - volatile unsigned long cr[8]; -}; - -struct tx3927_dma_reg { - struct tx3927_dma_ch_reg { - volatile unsigned long cha; - volatile unsigned long sar; - volatile unsigned long dar; - volatile unsigned long cntr; - volatile unsigned long sair; - volatile unsigned long dair; - volatile unsigned long ccr; - volatile unsigned long csr; - } ch[4]; - volatile unsigned long dbr[8]; - volatile unsigned long tdhr; - volatile unsigned long mcr; - volatile unsigned long unused0; -}; - -#include - -#ifdef __BIG_ENDIAN -#define endian_def_s2(e1, e2) \ - volatile unsigned short e1, e2 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned short e1;volatile unsigned char e2, e3 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned char e1, e2;volatile unsigned short e3 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e1, e2, e3, e4 -#else -#define endian_def_s2(e1, e2) \ - volatile unsigned short e2, e1 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned char e3, e2;volatile unsigned short e1 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned short e3;volatile unsigned char e2, e1 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e4, e3, e2, e1 -#endif - -struct tx3927_pcic_reg { - endian_def_s2(did, vid); - endian_def_s2(pcistat, pcicmd); - endian_def_b4(cc, scc, rpli, rid); - endian_def_b4(unused0, ht, mlt, cls); - volatile unsigned long ioba; /* +10 */ - volatile unsigned long mba; - volatile unsigned long unused1[5]; - endian_def_s2(svid, ssvid); - volatile unsigned long unused2; /* +30 */ - endian_def_sb2(unused3, unused4, capptr); - volatile unsigned long unused5; - endian_def_b4(ml, mg, ip, il); - volatile unsigned long unused6; /* +40 */ - volatile unsigned long istat; - volatile unsigned long iim; - volatile unsigned long rrt; - volatile unsigned long unused7[3]; /* +50 */ - volatile unsigned long ipbmma; - volatile unsigned long ipbioma; /* +60 */ - volatile unsigned long ilbmma; - volatile unsigned long ilbioma; - volatile unsigned long unused8[9]; - volatile unsigned long tc; /* +90 */ - volatile unsigned long tstat; - volatile unsigned long tim; - volatile unsigned long tccmd; - volatile unsigned long pcirrt; /* +a0 */ - volatile unsigned long pcirrt_cmd; - volatile unsigned long pcirrdt; - volatile unsigned long unused9[3]; - volatile unsigned long tlboap; - volatile unsigned long tlbiap; - volatile unsigned long tlbmma; /* +c0 */ - volatile unsigned long tlbioma; - volatile unsigned long sc_msg; - volatile unsigned long sc_be; - volatile unsigned long tbl; /* +d0 */ - volatile unsigned long unused10[3]; - volatile unsigned long pwmng; /* +e0 */ - volatile unsigned long pwmngs; - volatile unsigned long unused11[6]; - volatile unsigned long req_trace; /* +100 */ - volatile unsigned long pbapmc; - volatile unsigned long pbapms; - volatile unsigned long pbapmim; - volatile unsigned long bm; /* +110 */ - volatile unsigned long cpcibrs; - volatile unsigned long cpcibgs; - volatile unsigned long pbacs; - volatile unsigned long iobas; /* +120 */ - volatile unsigned long mbas; - volatile unsigned long lbc; - volatile unsigned long lbstat; - volatile unsigned long lbim; /* +130 */ - volatile unsigned long pcistatim; - volatile unsigned long ica; - volatile unsigned long icd; - volatile unsigned long iiadp; /* +140 */ - volatile unsigned long iscdp; - volatile unsigned long mmas; - volatile unsigned long iomas; - volatile unsigned long ipciaddr; /* +150 */ - volatile unsigned long ipcidata; - volatile unsigned long ipcibe; -}; - -struct tx3927_ccfg_reg { - volatile unsigned long ccfg; - volatile unsigned long crir; - volatile unsigned long pcfg; - volatile unsigned long tear; - volatile unsigned long pdcr; -}; - -/* - * SDRAMC - */ - -/* - * ROMC - */ - -/* - * DMA - */ -/* bits for MCR */ -#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) -#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) -#define TX3927_DMA_MCR_RSFIF 0x00000080 -#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) -#define TX3927_DMA_MCR_LE 0x00000004 -#define TX3927_DMA_MCR_RPRT 0x00000002 -#define TX3927_DMA_MCR_MSTEN 0x00000001 - -/* bits for CCRn */ -#define TX3927_DMA_CCR_DBINH 0x04000000 -#define TX3927_DMA_CCR_SBINH 0x02000000 -#define TX3927_DMA_CCR_CHRST 0x01000000 -#define TX3927_DMA_CCR_RVBYTE 0x00800000 -#define TX3927_DMA_CCR_ACKPOL 0x00400000 -#define TX3927_DMA_CCR_REQPL 0x00200000 -#define TX3927_DMA_CCR_EGREQ 0x00100000 -#define TX3927_DMA_CCR_CHDN 0x00080000 -#define TX3927_DMA_CCR_DNCTL 0x00060000 -#define TX3927_DMA_CCR_EXTRQ 0x00010000 -#define TX3927_DMA_CCR_INTRQD 0x0000e000 -#define TX3927_DMA_CCR_INTENE 0x00001000 -#define TX3927_DMA_CCR_INTENC 0x00000800 -#define TX3927_DMA_CCR_INTENT 0x00000400 -#define TX3927_DMA_CCR_CHNEN 0x00000200 -#define TX3927_DMA_CCR_XFACT 0x00000100 -#define TX3927_DMA_CCR_SNOP 0x00000080 -#define TX3927_DMA_CCR_DSTINC 0x00000040 -#define TX3927_DMA_CCR_SRCINC 0x00000020 -#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) -#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) -#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) -#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) -#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) -#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) -#define TX3927_DMA_CCR_MEMIO 0x00000002 -#define TX3927_DMA_CCR_ONEAD 0x00000001 - -/* bits for CSRn */ -#define TX3927_DMA_CSR_CHNACT 0x00000100 -#define TX3927_DMA_CSR_ABCHC 0x00000080 -#define TX3927_DMA_CSR_NCHNC 0x00000040 -#define TX3927_DMA_CSR_NTRNFC 0x00000020 -#define TX3927_DMA_CSR_EXTDN 0x00000010 -#define TX3927_DMA_CSR_CFERR 0x00000008 -#define TX3927_DMA_CSR_CHERR 0x00000004 -#define TX3927_DMA_CSR_DESERR 0x00000002 -#define TX3927_DMA_CSR_SORERR 0x00000001 - -/* - * IRC - */ -#define TX3927_IR_INT0 0 -#define TX3927_IR_INT1 1 -#define TX3927_IR_INT2 2 -#define TX3927_IR_INT3 3 -#define TX3927_IR_INT4 4 -#define TX3927_IR_INT5 5 -#define TX3927_IR_SIO0 6 -#define TX3927_IR_SIO1 7 -#define TX3927_IR_SIO(ch) (6 + (ch)) -#define TX3927_IR_DMA 8 -#define TX3927_IR_PIO 9 -#define TX3927_IR_PCI 10 -#define TX3927_IR_TMR(ch) (13 + (ch)) -#define TX3927_NUM_IR 16 - -/* - * PCIC - */ -/* bits for PCICMD */ -/* see PCI_COMMAND_XXX in linux/pci.h */ - -/* bits for PCISTAT */ -/* see PCI_STATUS_XXX in linux/pci.h */ -#define PCI_STATUS_NEW_CAP 0x0010 - -/* bits for TC */ -#define TX3927_PCIC_TC_OF16E 0x00000020 -#define TX3927_PCIC_TC_IF8E 0x00000010 -#define TX3927_PCIC_TC_OF8E 0x00000008 - -/* bits for IOBA/MBA */ -/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ - -/* bits for PBAPMC */ -#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 -#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 -#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 - -/* bits for LBSTAT/LBIM */ -#define TX3927_PCIC_LBIM_ALL 0x0000003e - -/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900 - -/* bits for LBC */ -#define TX3927_PCIC_LBC_IBSE 0x00004000 -#define TX3927_PCIC_LBC_TIBSE 0x00002000 -#define TX3927_PCIC_LBC_TMFBSE 0x00001000 -#define TX3927_PCIC_LBC_HRST 0x00000800 -#define TX3927_PCIC_LBC_SRST 0x00000400 -#define TX3927_PCIC_LBC_EPCAD 0x00000200 -#define TX3927_PCIC_LBC_MSDSE 0x00000100 -#define TX3927_PCIC_LBC_CRR 0x00000080 -#define TX3927_PCIC_LBC_ILMDE 0x00000040 -#define TX3927_PCIC_LBC_ILIDE 0x00000020 - -#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX3927_CCFG_TLBOFF 0x00020000 -#define TX3927_CCFG_BEOW 0x00010000 -#define TX3927_CCFG_WR 0x00008000 -#define TX3927_CCFG_TOE 0x00004000 -#define TX3927_CCFG_PCIXARB 0x00002000 -#define TX3927_CCFG_PCI3 0x00001000 -#define TX3927_CCFG_PSNP 0x00000800 -#define TX3927_CCFG_PPRI 0x00000400 -#define TX3927_CCFG_PLLM 0x00000030 -#define TX3927_CCFG_ENDIAN 0x00000004 -#define TX3927_CCFG_HALT 0x00000002 -#define TX3927_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX3927_PCFG_SYSCLKEN 0x08000000 -#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000 -#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) -#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000 -#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) -#define TX3927_PCFG_SELALL 0x0003ffff -#define TX3927_PCFG_SELCS 0x00020000 -#define TX3927_PCFG_SELDSF 0x00010000 -#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 -#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) -#define TX3927_PCFG_SELSIO_ALL 0x00003000 -#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) -#define TX3927_PCFG_SELTMR_ALL 0x00000e00 -#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch)) -#define TX3927_PCFG_SELDONE 0x00000100 -#define TX3927_PCFG_INTDMA_ALL 0x000000f0 -#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch)) -#define TX3927_PCFG_SELDMA_ALL 0x0000000f -#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) - -#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) -#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) -#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) -#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) -#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) -#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) -#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) -#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) - -#endif /* __ASM_TX3927_H */ diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h deleted file mode 100644 index 25dcf2feb095..000000000000 --- a/include/asm-mips/jmr3927/txx927.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Common definitions for TX3927/TX4927 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Toshiba Corporation - */ -#ifndef __ASM_TXX927_H -#define __ASM_TXX927_H - -struct txx927_sio_reg { - volatile unsigned long lcr; - volatile unsigned long dicr; - volatile unsigned long disr; - volatile unsigned long cisr; - volatile unsigned long fcr; - volatile unsigned long flcr; - volatile unsigned long bgr; - volatile unsigned long tfifo; - volatile unsigned long rfifo; -}; - -/* - * SIO - */ -/* SILCR : Line Control */ -#define TXx927_SILCR_SCS_MASK 0x00000060 -#define TXx927_SILCR_SCS_IMCLK 0x00000000 -#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020 -#define TXx927_SILCR_SCS_SCLK 0x00000040 -#define TXx927_SILCR_SCS_SCLK_BG 0x00000060 -#define TXx927_SILCR_UEPS 0x00000010 -#define TXx927_SILCR_UPEN 0x00000008 -#define TXx927_SILCR_USBL_MASK 0x00000004 -#define TXx927_SILCR_USBL_1BIT 0x00000004 -#define TXx927_SILCR_USBL_2BIT 0x00000000 -#define TXx927_SILCR_UMODE_MASK 0x00000003 -#define TXx927_SILCR_UMODE_8BIT 0x00000000 -#define TXx927_SILCR_UMODE_7BIT 0x00000001 - -/* SIDICR : DMA/Int. Control */ -#define TXx927_SIDICR_TDE 0x00008000 -#define TXx927_SIDICR_RDE 0x00004000 -#define TXx927_SIDICR_TIE 0x00002000 -#define TXx927_SIDICR_RIE 0x00001000 -#define TXx927_SIDICR_SPIE 0x00000800 -#define TXx927_SIDICR_CTSAC 0x00000600 -#define TXx927_SIDICR_STIE_MASK 0x0000003f -#define TXx927_SIDICR_STIE_OERS 0x00000020 -#define TXx927_SIDICR_STIE_CTSS 0x00000010 -#define TXx927_SIDICR_STIE_RBRKD 0x00000008 -#define TXx927_SIDICR_STIE_TRDY 0x00000004 -#define TXx927_SIDICR_STIE_TXALS 0x00000002 -#define TXx927_SIDICR_STIE_UBRKD 0x00000001 - -/* SIDISR : DMA/Int. Status */ -#define TXx927_SIDISR_UBRK 0x00008000 -#define TXx927_SIDISR_UVALID 0x00004000 -#define TXx927_SIDISR_UFER 0x00002000 -#define TXx927_SIDISR_UPER 0x00001000 -#define TXx927_SIDISR_UOER 0x00000800 -#define TXx927_SIDISR_ERI 0x00000400 -#define TXx927_SIDISR_TOUT 0x00000200 -#define TXx927_SIDISR_TDIS 0x00000100 -#define TXx927_SIDISR_RDIS 0x00000080 -#define TXx927_SIDISR_STIS 0x00000040 -#define TXx927_SIDISR_RFDN_MASK 0x0000001f - -/* SICISR : Change Int. Status */ -#define TXx927_SICISR_OERS 0x00000020 -#define TXx927_SICISR_CTSS 0x00000010 -#define TXx927_SICISR_RBRKD 0x00000008 -#define TXx927_SICISR_TRDY 0x00000004 -#define TXx927_SICISR_TXALS 0x00000002 -#define TXx927_SICISR_UBRKD 0x00000001 - -/* SIFCR : FIFO Control */ -#define TXx927_SIFCR_SWRST 0x00008000 -#define TXx927_SIFCR_RDIL_MASK 0x00000180 -#define TXx927_SIFCR_RDIL_1 0x00000000 -#define TXx927_SIFCR_RDIL_4 0x00000080 -#define TXx927_SIFCR_RDIL_8 0x00000100 -#define TXx927_SIFCR_RDIL_12 0x00000180 -#define TXx927_SIFCR_RDIL_MAX 0x00000180 -#define TXx927_SIFCR_TDIL_MASK 0x00000018 -#define TXx927_SIFCR_TDIL_MASK 0x00000018 -#define TXx927_SIFCR_TDIL_1 0x00000000 -#define TXx927_SIFCR_TDIL_4 0x00000001 -#define TXx927_SIFCR_TDIL_8 0x00000010 -#define TXx927_SIFCR_TDIL_MAX 0x00000010 -#define TXx927_SIFCR_TFRST 0x00000004 -#define TXx927_SIFCR_RFRST 0x00000002 -#define TXx927_SIFCR_FRSTE 0x00000001 -#define TXx927_SIO_TX_FIFO 8 -#define TXx927_SIO_RX_FIFO 16 - -/* SIFLCR : Flow Control */ -#define TXx927_SIFLCR_RCS 0x00001000 -#define TXx927_SIFLCR_TES 0x00000800 -#define TXx927_SIFLCR_RTSSC 0x00000200 -#define TXx927_SIFLCR_RSDE 0x00000100 -#define TXx927_SIFLCR_TSDE 0x00000080 -#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e -#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e -#define TXx927_SIFLCR_TBRK 0x00000001 - -/* SIBGR : Baudrate Control */ -#define TXx927_SIBGR_BCLK_MASK 0x00000300 -#define TXx927_SIBGR_BCLK_T0 0x00000000 -#define TXx927_SIBGR_BCLK_T2 0x00000100 -#define TXx927_SIBGR_BCLK_T4 0x00000200 -#define TXx927_SIBGR_BCLK_T6 0x00000300 -#define TXx927_SIBGR_BRD_MASK 0x000000ff - -/* - * PIO - */ - -#endif /* __ASM_TXX927_H */ diff --git a/include/asm-mips/tx4927/smsc_fdc37m81x.h b/include/asm-mips/tx4927/smsc_fdc37m81x.h deleted file mode 100644 index 5d93bab51254..000000000000 --- a/include/asm-mips/tx4927/smsc_fdc37m81x.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h - * - * Interface for smsc fdc48m81x Super IO chip - * - * Author: MontaVista Software, Inc. source@mvista.com - * - * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Manish Lachwani, mlachwani@mvista.com - */ - -#ifndef _SMSC_FDC37M81X_H_ -#define _SMSC_FDC37M81X_H_ - -/* Common Registers */ -#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 -#define SMSC_FDC37M81X_CONFIG_DATA 0x01 -#define SMSC_FDC37M81X_CONF 0x02 -#define SMSC_FDC37M81X_INDEX 0x03 -#define SMSC_FDC37M81X_DNUM 0x07 -#define SMSC_FDC37M81X_DID 0x20 -#define SMSC_FDC37M81X_DREV 0x21 -#define SMSC_FDC37M81X_PCNT 0x22 -#define SMSC_FDC37M81X_PMGT 0x23 -#define SMSC_FDC37M81X_OSC 0x24 -#define SMSC_FDC37M81X_CONFPA0 0x26 -#define SMSC_FDC37M81X_CONFPA1 0x27 -#define SMSC_FDC37M81X_TEST4 0x2B -#define SMSC_FDC37M81X_TEST5 0x2C -#define SMSC_FDC37M81X_TEST1 0x2D -#define SMSC_FDC37M81X_TEST2 0x2E -#define SMSC_FDC37M81X_TEST3 0x2F - -/* Logical device numbers */ -#define SMSC_FDC37M81X_FDD 0x00 -#define SMSC_FDC37M81X_PARALLEL 0x03 -#define SMSC_FDC37M81X_SERIAL1 0x04 -#define SMSC_FDC37M81X_SERIAL2 0x05 -#define SMSC_FDC37M81X_KBD 0x07 -#define SMSC_FDC37M81X_AUXIO 0x08 -#define SMSC_FDC37M81X_NONE 0xff - -/* Logical device Config Registers */ -#define SMSC_FDC37M81X_ACTIVE 0x30 -#define SMSC_FDC37M81X_BASEADDR0 0x60 -#define SMSC_FDC37M81X_BASEADDR1 0x61 -#define SMSC_FDC37M81X_INT 0x70 -#define SMSC_FDC37M81X_INT2 0x72 -#define SMSC_FDC37M81X_LDCR_F0 0xF0 - -/* Chip Config Values */ -#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 -#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa -#define SMSC_FDC37M81X_CHIP_ID 0x4d - -unsigned long __init smsc_fdc37m81x_init(unsigned long port); - -void smsc_fdc37m81x_config_beg(void); - -void smsc_fdc37m81x_config_end(void); - -void smsc_fdc37m81x_config_set(u8 reg, u8 val); - -#endif diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h deleted file mode 100644 index d6b32acd6b7b..000000000000 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H -#define __ASM_TX4927_TOSHIBA_RBTX4927_H - -#include - -#ifdef CONFIG_PCI -#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO -#else -#define TBTX4927_ISA_IO_OFFSET 0 -#endif - -#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL -#define RBTX4927_SW_RESET_DO_SET 0x01 - -#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL -#define RBTX4927_SW_RESET_ENABLE_SET 0x01 - -#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) -#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) - -int toshiba_rbtx4927_irq_nested(int sw_irq); - -#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */ diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h deleted file mode 100644 index 1d4816f3266f..000000000000 --- a/include/asm-mips/tx4927/tx4927.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2006 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TX4927_H -#define __ASM_TX4927_TX4927_H - -#include - -#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) - - -#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) -#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) -#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) -#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) - -#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) - -#define TX4927_CCFG_TOE 0x00004000 -#define TX4927_CCFG_WR 0x00008000 -#define TX4927_CCFG_TINTDIS 0x01000000 - -#define TX4927_PCIMEM 0x08000000 -#define TX4927_PCIMEM_SIZE 0x08000000 -#define TX4927_PCIIO 0x16000000 -#define TX4927_PCIIO_SIZE 0x01000000 - -#define TX4927_SDRAMC_REG 0xff1f8000 -#define TX4927_EBUSC_REG 0xff1f9000 -#define TX4927_PCIC_REG 0xff1fd000 -#define TX4927_CCFG_REG 0xff1fe000 -#define TX4927_IRC_REG 0xff1ff600 -#define TX4927_NR_TMR 3 -#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) - -/* bits for ISTAT3/IMASK3/IMSTAT3 */ -#define TX4927_INT3B_PCID 0 -#define TX4927_INT3B_PCIC 1 -#define TX4927_INT3B_PCIB 2 -#define TX4927_INT3B_PCIA 3 -#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) -#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) -#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) -#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) - -#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG -#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ - -#define TX4927_IR_PCIC 16 -#define TX4927_IR_PCIERR 22 -#define TX4927_IR_PCIPMA 23 -#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) -#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) -#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) -#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) -#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) -#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) -#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) - -#ifdef _LANGUAGE_ASSEMBLY -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include - -struct tx4927_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; -}; - -struct tx4927_ebusc_reg { - volatile unsigned long long cr[8]; -}; - -struct tx4927_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; -}; - -struct tx4927_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmcut; - volatile unsigned long long pdmcnt; /* +220 */ - volatile unsigned long long pdmsts; - volatile unsigned long long unused8[2]; - volatile unsigned long long pdmdb[4]; /* +240 */ - volatile unsigned long long pdmtdh; /* +260 */ - volatile unsigned long long pdmdms; -}; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* - * PCIC - */ - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4927_PCIC_PBACFG_RPBA 0x00000004 -#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc - -/* bits for PCICCFG */ -#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 -#define TX4927_PCIC_PCICCFG_HRST 0x00000800 -#define TX4927_PCIC_PCICCFG_SRST 0x00000400 -#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 -#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 -#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 -#define TX4927_PCIC_PCICCFG_IISE 0x00000020 -#define TX4927_PCIC_PCICCFG_ATR 0x00000010 -#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4927_CCFG_PCI66 0x00800000 -#define TX4927_CCFG_PCIMIDE 0x00400000 -#define TX4927_CCFG_PCIXARB 0x00002000 -#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 -#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 -#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 -#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 -#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 - -#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 -#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 -#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 -#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 -#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 -#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 -#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 -#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 - -/* PCFG : Pin Configuration */ -#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) - -/* CLKCTR : Clock Control */ -#define TX4927_CLKCTR_PCICKD 0x00400000 -#define TX4927_CLKCTR_PCIRST 0x00000040 - -#ifndef _LANGUAGE_ASSEMBLY - -#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) -#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) -#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) -#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) - -#endif /* _LANGUAGE_ASSEMBLY */ - -#endif /* __ASM_TX4927_TX4927_H */ diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h deleted file mode 100644 index dfed7beb533f..000000000000 --- a/include/asm-mips/tx4938/rbtx4938.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/rbtx4938.h - * Definitions for TX4937/TX4938 - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TX_BOARDS_RBTX4938_H -#define __ASM_TX_BOARDS_RBTX4938_H - -#include -#include -#include - -/* CS */ -#define RBTX4938_CE0 0x1c000000 /* 64M */ -#define RBTX4938_CE2 0x17f00000 /* 1M */ - -/* Address map */ -#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) -#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) -#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) -#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) -#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) -#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) -#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) -#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) -#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) -#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) -#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) -#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) -#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) -#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) -#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) -#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) -#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) -#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) -#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) -#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) -#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) -#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) -#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) -#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) - -/* Ethernet port address (Jumperless Mode (W12:Open)) */ -#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) - -/* bits for ISTAT/IMASK/IMSTAT */ -#define RBTX4938_INTB_PCID 0 -#define RBTX4938_INTB_PCIC 1 -#define RBTX4938_INTB_PCIB 2 -#define RBTX4938_INTB_PCIA 3 -#define RBTX4938_INTB_RTC 4 -#define RBTX4938_INTB_ATA 5 -#define RBTX4938_INTB_MODEM 6 -#define RBTX4938_INTB_SWINT 7 -#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) -#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) -#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) -#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) -#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) -#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) -#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) -#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) - -#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) -#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) -#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) -#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) -#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) -#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) -#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) -#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) -#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) -#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) -#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) -#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) -#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) -#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) -#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) -#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) -#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) -#define rbtx4938_softresetlock_addr \ - ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) -#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) - -/* - * IRQ mappings - */ - -#define RBTX4938_SOFT_INT0 0 /* not used */ -#define RBTX4938_SOFT_INT1 1 /* not used */ -#define RBTX4938_IRC_INT 2 -#define RBTX4938_TIMER_INT 7 - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define RBTX4938_NR_IRQ_LOCAL 8 -#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ -#define RBTX4938_NR_IRQ_IOC 8 - -#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) -#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) -#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) -#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) -#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) -#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) - -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ -#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG -#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) -#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) -#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) - -#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) -#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) -#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) -#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) -#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) -#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) -#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) -#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) -#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) -#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) -#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) -#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) -#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) -#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) -#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) -#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) -#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) -#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) -#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) -#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) -#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) -#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) -#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) -#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) -#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) -#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) -#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) -#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) - - -/* IOC (PCI, etc) */ -#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) -/* Onboard 10M Ether */ -#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) - -#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) -#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) - -#endif /* __ASM_TX_BOARDS_RBTX4938_H */ diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h deleted file mode 100644 index 6a60c83e152b..000000000000 --- a/include/asm-mips/tx4938/spi.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/spi.h - * Definitions for TX4937/TX4938 SPI - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TX_BOARDS_TX4938_SPI_H -#define __ASM_TX_BOARDS_TX4938_SPI_H - -extern int spi_eeprom_register(int chipid); -extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); - -#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h deleted file mode 100644 index e8807f5c61e9..000000000000 --- a/include/asm-mips/tx4938/tx4938.h +++ /dev/null @@ -1,628 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/tx4938.h - * Definitions for TX4937/TX4938 - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TX_BOARDS_TX4938_H -#define __ASM_TX_BOARDS_TX4938_H - -#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) -#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) - -#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG - -#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) -#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) - -#define TX4938_PCIIO_0 0x10000000 -#define TX4938_PCIIO_1 0x01010000 -#define TX4938_PCIMEM_0 0x08000000 -#define TX4938_PCIMEM_1 0x11000000 - -#define TX4938_PCIIO_SIZE_0 0x01000000 -#define TX4938_PCIIO_SIZE_1 0x00010000 -#define TX4938_PCIMEM_SIZE_0 0x08000000 -#define TX4938_PCIMEM_SIZE_1 0x00010000 - -#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */ -#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ - -/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ -#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) -#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000) -#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000) -#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000) -#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000) -#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) -#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000) -#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000) -#define TX4938_NR_TMR 3 -#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) -#define TX4938_NR_SIO 2 -#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) -#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500) -#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600) -#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) -#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) - -#ifdef __ASSEMBLY__ -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include - -#ifdef __BIG_ENDIAN -#define endian_def_l2(e1, e2) \ - volatile unsigned long e1, e2 -#define endian_def_s2(e1, e2) \ - volatile unsigned short e1, e2 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned short e1;volatile unsigned char e2, e3 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned char e1, e2;volatile unsigned short e3 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e1, e2, e3, e4 -#else -#define endian_def_l2(e1, e2) \ - volatile unsigned long e2, e1 -#define endian_def_s2(e1, e2) \ - volatile unsigned short e2, e1 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned char e3, e2;volatile unsigned short e1 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned short e3;volatile unsigned char e2, e1 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e4, e3, e2, e1 -#endif - - -struct tx4938_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; - volatile unsigned long long sfcmd; -}; - -struct tx4938_ebusc_reg { - volatile unsigned long long cr[8]; -}; - -struct tx4938_dma_reg { - struct tx4938_dma_ch_reg { - volatile unsigned long long cha; - volatile unsigned long long sar; - volatile unsigned long long dar; - endian_def_l2(unused0, cntr); - endian_def_l2(unused1, sair); - endian_def_l2(unused2, dair); - endian_def_l2(unused3, ccr); - endian_def_l2(unused4, csr); - } ch[4]; - volatile unsigned long long dbr[8]; - volatile unsigned long long tdhr; - volatile unsigned long long midr; - endian_def_l2(unused0, mcr); -}; - -struct tx4938_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmctr; - volatile unsigned long long pdmcfg; /* +220 */ - volatile unsigned long long pdmsts; -}; - -struct tx4938_aclc_reg { - volatile unsigned long acctlen; - volatile unsigned long acctldis; - volatile unsigned long acregacc; - volatile unsigned long unused0; - volatile unsigned long acintsts; - volatile unsigned long acintmsts; - volatile unsigned long acinten; - volatile unsigned long acintdis; - volatile unsigned long acsemaph; - volatile unsigned long unused1[7]; - volatile unsigned long acgpidat; - volatile unsigned long acgpodat; - volatile unsigned long acslten; - volatile unsigned long acsltdis; - volatile unsigned long acfifosts; - volatile unsigned long unused2[11]; - volatile unsigned long acdmasts; - volatile unsigned long acdmasel; - volatile unsigned long unused3[6]; - volatile unsigned long acaudodat; - volatile unsigned long acsurrdat; - volatile unsigned long accentdat; - volatile unsigned long aclfedat; - volatile unsigned long acaudiat; - volatile unsigned long unused4; - volatile unsigned long acmodoat; - volatile unsigned long acmodidat; - volatile unsigned long unused5[15]; - volatile unsigned long acrevid; -}; - - -struct tx4938_tmr_reg { - volatile unsigned long tcr; - volatile unsigned long tisr; - volatile unsigned long cpra; - volatile unsigned long cprb; - volatile unsigned long itmr; - volatile unsigned long unused0[3]; - volatile unsigned long ccdr; - volatile unsigned long unused1[3]; - volatile unsigned long pgmr; - volatile unsigned long unused2[3]; - volatile unsigned long wtmr; - volatile unsigned long unused3[43]; - volatile unsigned long trr; -}; - -struct tx4938_sio_reg { - volatile unsigned long lcr; - volatile unsigned long dicr; - volatile unsigned long disr; - volatile unsigned long cisr; - volatile unsigned long fcr; - volatile unsigned long flcr; - volatile unsigned long bgr; - volatile unsigned long tfifo; - volatile unsigned long rfifo; -}; - -struct tx4938_ndfmc_reg { - endian_def_l2(unused0, dtr); - endian_def_l2(unused1, mcr); - endian_def_l2(unused2, sr); - endian_def_l2(unused3, isr); - endian_def_l2(unused4, imr); - endian_def_l2(unused5, spr); - endian_def_l2(unused6, rstr); -}; - -struct tx4938_spi_reg { - volatile unsigned long mcr; - volatile unsigned long cr0; - volatile unsigned long cr1; - volatile unsigned long fs; - volatile unsigned long unused1; - volatile unsigned long sr; - volatile unsigned long dr; - volatile unsigned long unused2; -}; - -struct tx4938_sramc_reg { - volatile unsigned long long cr; -}; - -struct tx4938_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; - volatile unsigned long long unused3; - volatile unsigned long long jmpadr; -}; - -#undef endian_def_l2 -#undef endian_def_s2 -#undef endian_def_sb2 -#undef endian_def_b2s -#undef endian_def_b4 - -#endif /* __ASSEMBLY__ */ - -/* - * NDFMC - */ - -/* NDFMCR : NDFMC Mode Control */ -#define TX4938_NDFMCR_WE 0x80 -#define TX4938_NDFMCR_ECC_ALL 0x60 -#define TX4938_NDFMCR_ECC_RESET 0x60 -#define TX4938_NDFMCR_ECC_READ 0x40 -#define TX4938_NDFMCR_ECC_ON 0x20 -#define TX4938_NDFMCR_ECC_OFF 0x00 -#define TX4938_NDFMCR_CE 0x10 -#define TX4938_NDFMCR_BSPRT 0x04 -#define TX4938_NDFMCR_ALE 0x02 -#define TX4938_NDFMCR_CLE 0x01 - -/* NDFMCR : NDFMC Status */ -#define TX4938_NDFSR_BUSY 0x80 - -/* NDFMCR : NDFMC Reset */ -#define TX4938_NDFRSTR_RST 0x01 - -/* - * IRC - */ - -#define TX4938_IR_ECCERR 0 -#define TX4938_IR_WTOERR 1 -#define TX4938_NUM_IR_INT 6 -#define TX4938_IR_INT(n) (2 + (n)) -#define TX4938_NUM_IR_SIO 2 -#define TX4938_IR_SIO(n) (8 + (n)) -#define TX4938_NUM_IR_DMA 4 -#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ -#define TX4938_IR_PIO 14 -#define TX4938_IR_PDMAC 15 -#define TX4938_IR_PCIC 16 -#define TX4938_NUM_IR_TMR 3 -#define TX4938_IR_TMR(n) (17 + (n)) -#define TX4938_IR_NDFMC 21 -#define TX4938_IR_PCIERR 22 -#define TX4938_IR_PCIPME 23 -#define TX4938_IR_ACLC 24 -#define TX4938_IR_ACLCPME 25 -#define TX4938_IR_PCIC1 26 -#define TX4938_IR_SPI 31 -#define TX4938_NUM_IR 32 -/* multiplex */ -#define TX4938_IR_ETH0 TX4938_IR_INT(4) -#define TX4938_IR_ETH1 TX4938_IR_INT(3) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) -#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) -#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) -#define TX4938_CCFG_TINTDIS 0x01000000 -#define TX4938_CCFG_PCI66 0x00800000 -#define TX4938_CCFG_PCIMODE 0x00400000 -#define TX4938_CCFG_PCI1_66 0x00200000 -#define TX4938_CCFG_DIVMODE_MASK 0x001e0000 -#define TX4938_CCFG_DIVMODE_2 (0x4 << 17) -#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) -#define TX4938_CCFG_DIVMODE_3 (0x5 << 17) -#define TX4938_CCFG_DIVMODE_4 (0x6 << 17) -#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) -#define TX4938_CCFG_DIVMODE_8 (0x0 << 17) -#define TX4938_CCFG_DIVMODE_10 (0xb << 17) -#define TX4938_CCFG_DIVMODE_12 (0x1 << 17) -#define TX4938_CCFG_DIVMODE_16 (0x2 << 17) -#define TX4938_CCFG_DIVMODE_18 (0x9 << 17) -#define TX4938_CCFG_BEOW 0x00010000 -#define TX4938_CCFG_WR 0x00008000 -#define TX4938_CCFG_TOE 0x00004000 -#define TX4938_CCFG_PCIXARB 0x00002000 -#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) -#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) -#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10) -#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10) -#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10) -#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10) -#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10) -#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10) -#define TX4938_CCFG_PCI1DMD 0x00000100 -#define TX4938_CCFG_SYSSP_MASK 0x000000c0 -#define TX4938_CCFG_ENDIAN 0x00000004 -#define TX4938_CCFG_HALT 0x00000002 -#define TX4938_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) -#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) -#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) -#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) -#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) -#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) -#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 -#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) -#define TX4938_PCFG_SYSCLKEN 0x08000000 -#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 -#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) -#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) -#define TX4938_PCFG_SEL2 0x00000200 -#define TX4938_PCFG_SEL1 0x00000100 -#define TX4938_PCFG_DMASEL_ALL 0x0000000f -#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000 -#define TX4938_PCFG_DMASEL0_SIO1 0x00000001 -#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000 -#define TX4938_PCFG_DMASEL1_SIO1 0x00000002 -#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000 -#define TX4938_PCFG_DMASEL2_SIO0 0x00000004 -#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000 -#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 - -/* CLKCTR : Clock Control */ -#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) -#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) -#define TX4938_CLKCTR_ETH1CKD 0x80000000 -#define TX4938_CLKCTR_ETH0CKD 0x40000000 -#define TX4938_CLKCTR_SPICKD 0x20000000 -#define TX4938_CLKCTR_SRAMCKD 0x10000000 -#define TX4938_CLKCTR_PCIC1CKD 0x08000000 -#define TX4938_CLKCTR_DMA1CKD 0x04000000 -#define TX4938_CLKCTR_ACLCKD 0x02000000 -#define TX4938_CLKCTR_PIOCKD 0x01000000 -#define TX4938_CLKCTR_DMACKD 0x00800000 -#define TX4938_CLKCTR_PCICKD 0x00400000 -#define TX4938_CLKCTR_TM0CKD 0x00100000 -#define TX4938_CLKCTR_TM1CKD 0x00080000 -#define TX4938_CLKCTR_TM2CKD 0x00040000 -#define TX4938_CLKCTR_SIO0CKD 0x00020000 -#define TX4938_CLKCTR_SIO1CKD 0x00010000 -#define TX4938_CLKCTR_ETH1RST 0x00008000 -#define TX4938_CLKCTR_ETH0RST 0x00004000 -#define TX4938_CLKCTR_SPIRST 0x00002000 -#define TX4938_CLKCTR_SRAMRST 0x00001000 -#define TX4938_CLKCTR_PCIC1RST 0x00000800 -#define TX4938_CLKCTR_DMA1RST 0x00000400 -#define TX4938_CLKCTR_ACLRST 0x00000200 -#define TX4938_CLKCTR_PIORST 0x00000100 -#define TX4938_CLKCTR_DMARST 0x00000080 -#define TX4938_CLKCTR_PCIRST 0x00000040 -#define TX4938_CLKCTR_TM0RST 0x00000010 -#define TX4938_CLKCTR_TM1RST 0x00000008 -#define TX4938_CLKCTR_TM2RST 0x00000004 -#define TX4938_CLKCTR_SIO0RST 0x00000002 -#define TX4938_CLKCTR_SIO1RST 0x00000001 - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 -#define TX4938_PCIC_PBACFG_RPBA 0x00000004 -#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 -#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 -#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 -#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 -#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 -#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 -#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 -#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 -#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 -#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 - -/* bits for PCICCFG */ -#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 -#define TX4938_PCIC_PCICCFG_HRST 0x00000800 -#define TX4938_PCIC_PCICCFG_SRST 0x00000400 -#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) -#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 -#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 -#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 -#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 -#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 -#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) - -/* bits for PDMCFG */ -#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 -#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 -#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 -#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) -#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 -#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 -#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 -#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 -#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 -#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 -#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c -#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 -#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 -#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 -#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 -#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 - -/* bits for PDMSTS */ -#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 -#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 -#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 -#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 -#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 -#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 -#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 -#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 -#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 -#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 -#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 -#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 -#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 -#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 -#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 -#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 -#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f - -/* - * DMA - */ -/* bits for MCR */ -#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) -#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) -#define TX4938_DMA_MCR_RSFIF 0x00000080 -#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) -#define TX4938_DMA_MCR_RPRT 0x00000002 -#define TX4938_DMA_MCR_MSTEN 0x00000001 - -/* bits for CCRn */ -#define TX4938_DMA_CCR_IMMCHN 0x20000000 -#define TX4938_DMA_CCR_USEXFSZ 0x10000000 -#define TX4938_DMA_CCR_LE 0x08000000 -#define TX4938_DMA_CCR_DBINH 0x04000000 -#define TX4938_DMA_CCR_SBINH 0x02000000 -#define TX4938_DMA_CCR_CHRST 0x01000000 -#define TX4938_DMA_CCR_RVBYTE 0x00800000 -#define TX4938_DMA_CCR_ACKPOL 0x00400000 -#define TX4938_DMA_CCR_REQPL 0x00200000 -#define TX4938_DMA_CCR_EGREQ 0x00100000 -#define TX4938_DMA_CCR_CHDN 0x00080000 -#define TX4938_DMA_CCR_DNCTL 0x00060000 -#define TX4938_DMA_CCR_EXTRQ 0x00010000 -#define TX4938_DMA_CCR_INTRQD 0x0000e000 -#define TX4938_DMA_CCR_INTENE 0x00001000 -#define TX4938_DMA_CCR_INTENC 0x00000800 -#define TX4938_DMA_CCR_INTENT 0x00000400 -#define TX4938_DMA_CCR_CHNEN 0x00000200 -#define TX4938_DMA_CCR_XFACT 0x00000100 -#define TX4938_DMA_CCR_SMPCHN 0x00000020 -#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) -#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2) -#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) -#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) -#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) -#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) -#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) -#define TX4938_DMA_CCR_MEMIO 0x00000002 -#define TX4938_DMA_CCR_SNGAD 0x00000001 - -/* bits for CSRn */ -#define TX4938_DMA_CSR_CHNEN 0x00000400 -#define TX4938_DMA_CSR_STLXFER 0x00000200 -#define TX4938_DMA_CSR_CHNACT 0x00000100 -#define TX4938_DMA_CSR_ABCHC 0x00000080 -#define TX4938_DMA_CSR_NCHNC 0x00000040 -#define TX4938_DMA_CSR_NTRNFC 0x00000020 -#define TX4938_DMA_CSR_EXTDN 0x00000010 -#define TX4938_DMA_CSR_CFERR 0x00000008 -#define TX4938_DMA_CSR_CHERR 0x00000004 -#define TX4938_DMA_CSR_DESERR 0x00000002 -#define TX4938_DMA_CSR_SORERR 0x00000001 - -#ifndef __ASSEMBLY__ - -#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) -#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) -#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) -#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) -#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) -#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) -#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) -#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) -#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) -#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) -#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) -#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) - - -#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) -#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) - -#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) -#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) - -#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) -#define TX4938_EBUSC_SIZE(ch) \ - (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) - - -#endif /* !__ASSEMBLY__ */ - -#endif diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h new file mode 100644 index 000000000000..29e54981a86e --- /dev/null +++ b/include/asm-mips/txx9/jmr3927.h @@ -0,0 +1,177 @@ +/* + * Defines for the TJSYS JMR-TX3927 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2001 Toshiba Corporation + */ +#ifndef __ASM_TXX9_JMR3927_H +#define __ASM_TXX9_JMR3927_H + +#include +#include +#include +#include + +/* CS */ +#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ +#define JMR3927_ROMCE1 0x1e000000 /* 4M */ +#define JMR3927_ROMCE2 0x14000000 /* 16M */ +#define JMR3927_ROMCE3 0x10000000 /* 64M */ +#define JMR3927_ROMCE5 0x1d000000 /* 4M */ +#define JMR3927_SDCS0 0x00000000 /* 32M */ +#define JMR3927_SDCS1 0x02000000 /* 32M */ +/* PCI Direct Mappings */ + +#define JMR3927_PCIMEM 0x08000000 +#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ +#define JMR3927_PCIIO 0x15000000 +#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ + +#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ +#define JMR3927_PORT_BASE KSEG1 + +/* Address map (virtual address) */ +#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) +#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) +#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) +#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) +#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) + +#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) +#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) +#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) +#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) +#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) +#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) +#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) +#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) +#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) +#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) +#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) + +/* Flash ROM */ +#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) +#define JMR3927_FLASH_SIZE 0x00400000 + +/* bits for IOC_REV/IOC_BREV (high byte) */ +#define JMR3927_IDT_MASK 0xfc +#define JMR3927_REV_MASK 0x03 +#define JMR3927_IOC_IDT 0xe0 + +/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ +#define JMR3927_IOC_INTB_PCIA 0 +#define JMR3927_IOC_INTB_PCIB 1 +#define JMR3927_IOC_INTB_PCIC 2 +#define JMR3927_IOC_INTB_PCID 3 +#define JMR3927_IOC_INTB_MODEM 4 +#define JMR3927_IOC_INTB_INT6 5 +#define JMR3927_IOC_INTB_INT7 6 +#define JMR3927_IOC_INTB_SOFT 7 +#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) +#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) +#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) +#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) +#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) +#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) +#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) +#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) + +/* bits for IOC_RESET (high byte) */ +#define JMR3927_IOC_RESET_CPU 1 +#define JMR3927_IOC_RESET_PCI 2 + +#if defined(__BIG_ENDIAN) +#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) +#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) +#elif defined(__LITTLE_ENDIAN) +#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) +#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) +#else +#error "No Endian" +#endif + +/* LED macro */ +#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) + +#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) + +/* DIPSW4 macro */ +#define jmr3927_dipsw1() (gpio_get_value(11) == 0) +#define jmr3927_dipsw2() (gpio_get_value(10) == 0) +#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) +#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) + +/* + * IRQ mappings + */ + +/* These are the virtual IRQ numbers, we divide all IRQ's into + * 'spaces', the 'space' determines where and how to enable/disable + * that particular IRQ on an JMR machine. Add new 'spaces' as new + * IRQ hardware is supported. + */ +#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ +#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ + +#define JMR3927_IRQ_IRC TXX9_IRQ_BASE +#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) +#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) + +#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) +#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) +#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) +#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) +#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) +#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) +#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) +#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) +#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) +#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) +#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) +#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) +#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) +#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) +#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) +#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) +#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) +#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) +#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) +#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) +#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) + +/* IOC (PCI, MODEM) */ +#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 +/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ +#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 + +/* Clocks */ +#define JMR3927_CORECLK 132710400 /* 132.7MHz */ +#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ +#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ + +/* + * TX3927 Pin Configuration: + * + * PCFG bits Avail Dead + * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] + * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] + * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, + * GDBGE* PIO[2:1] + * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] + * SELTMR[2:0]:000 TIMER[1:0] + * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], + * DMAREQ[1],DMAACK[1] + * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] + * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] + * SELDONE:1 DMADONE PIO[7] + * + * Usable pins are: + * RXD[1;0],TXD[1:0],CTS[0],RTS[0], + * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] + * INT[3:0] + */ + +#endif /* __ASM_TXX9_JMR3927_H */ diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h new file mode 100644 index 000000000000..5531342bcc01 --- /dev/null +++ b/include/asm-mips/txx9/rbtx4927.h @@ -0,0 +1,49 @@ +/* + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_TXX9_RBTX4927_H +#define __ASM_TXX9_RBTX4927_H + +#include + +#ifdef CONFIG_PCI +#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO +#else +#define TBTX4927_ISA_IO_OFFSET 0 +#endif + +#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL +#define RBTX4927_SW_RESET_DO_SET 0x01 + +#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL +#define RBTX4927_SW_RESET_ENABLE_SET 0x01 + +#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) +#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) + +int toshiba_rbtx4927_irq_nested(int sw_irq); + +#endif /* __ASM_TXX9_RBTX4927_H */ diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h new file mode 100644 index 000000000000..8450f735d056 --- /dev/null +++ b/include/asm-mips/txx9/rbtx4938.h @@ -0,0 +1,167 @@ +/* + * Definitions for TX4937/TX4938 + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TXX9_RBTX4938_H +#define __ASM_TXX9_RBTX4938_H + +#include +#include +#include + +/* CS */ +#define RBTX4938_CE0 0x1c000000 /* 64M */ +#define RBTX4938_CE2 0x17f00000 /* 1M */ + +/* Address map */ +#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) +#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) +#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) +#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) +#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) +#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) +#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) +#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) +#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) +#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) +#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) +#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) +#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) +#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) +#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) +#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) +#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) +#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) +#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) +#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) +#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) +#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) +#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) +#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) + +/* Ethernet port address (Jumperless Mode (W12:Open)) */ +#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) + +/* bits for ISTAT/IMASK/IMSTAT */ +#define RBTX4938_INTB_PCID 0 +#define RBTX4938_INTB_PCIC 1 +#define RBTX4938_INTB_PCIB 2 +#define RBTX4938_INTB_PCIA 3 +#define RBTX4938_INTB_RTC 4 +#define RBTX4938_INTB_ATA 5 +#define RBTX4938_INTB_MODEM 6 +#define RBTX4938_INTB_SWINT 7 +#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) +#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) +#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) +#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) +#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) +#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) +#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) +#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) + +#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) +#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) +#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) +#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) +#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) +#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) +#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) +#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) +#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) +#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) +#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) +#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) +#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) +#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) +#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) +#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) +#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) +#define rbtx4938_softresetlock_addr \ + ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) +#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) + +/* + * IRQ mappings + */ + +#define RBTX4938_SOFT_INT0 0 /* not used */ +#define RBTX4938_SOFT_INT1 1 /* not used */ +#define RBTX4938_IRC_INT 2 +#define RBTX4938_TIMER_INT 7 + +/* These are the virtual IRQ numbers, we divide all IRQ's into + * 'spaces', the 'space' determines where and how to enable/disable + * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new + * IRQ hardware is supported. + */ +#define RBTX4938_NR_IRQ_LOCAL 8 +#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ +#define RBTX4938_NR_IRQ_IOC 8 + +#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) + +#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) +#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) +#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) +#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) +#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) +#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) + +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 + +#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ +#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ +#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG +#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) +#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) +#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) + +#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) +#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) +#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) +#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) +#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) +#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) +#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) +#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) +#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) +#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) +#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) +#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) +#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) +#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) +#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) +#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) +#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) +#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) +#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) +#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) +#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) +#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) +#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) +#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) +#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) +#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) +#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) +#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) + + +/* IOC (PCI, etc) */ +#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) +/* Onboard 10M Ether */ +#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) + +#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) +#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) + +#endif /* __ASM_TXX9_RBTX4938_H */ diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h new file mode 100644 index 000000000000..9375e4fc2289 --- /dev/null +++ b/include/asm-mips/txx9/smsc_fdc37m81x.h @@ -0,0 +1,67 @@ +/* + * Interface for smsc fdc48m81x Super IO chip + * + * Author: MontaVista Software, Inc. source@mvista.com + * + * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Manish Lachwani, mlachwani@mvista.com + */ + +#ifndef _SMSC_FDC37M81X_H_ +#define _SMSC_FDC37M81X_H_ + +/* Common Registers */ +#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 +#define SMSC_FDC37M81X_CONFIG_DATA 0x01 +#define SMSC_FDC37M81X_CONF 0x02 +#define SMSC_FDC37M81X_INDEX 0x03 +#define SMSC_FDC37M81X_DNUM 0x07 +#define SMSC_FDC37M81X_DID 0x20 +#define SMSC_FDC37M81X_DREV 0x21 +#define SMSC_FDC37M81X_PCNT 0x22 +#define SMSC_FDC37M81X_PMGT 0x23 +#define SMSC_FDC37M81X_OSC 0x24 +#define SMSC_FDC37M81X_CONFPA0 0x26 +#define SMSC_FDC37M81X_CONFPA1 0x27 +#define SMSC_FDC37M81X_TEST4 0x2B +#define SMSC_FDC37M81X_TEST5 0x2C +#define SMSC_FDC37M81X_TEST1 0x2D +#define SMSC_FDC37M81X_TEST2 0x2E +#define SMSC_FDC37M81X_TEST3 0x2F + +/* Logical device numbers */ +#define SMSC_FDC37M81X_FDD 0x00 +#define SMSC_FDC37M81X_PARALLEL 0x03 +#define SMSC_FDC37M81X_SERIAL1 0x04 +#define SMSC_FDC37M81X_SERIAL2 0x05 +#define SMSC_FDC37M81X_KBD 0x07 +#define SMSC_FDC37M81X_AUXIO 0x08 +#define SMSC_FDC37M81X_NONE 0xff + +/* Logical device Config Registers */ +#define SMSC_FDC37M81X_ACTIVE 0x30 +#define SMSC_FDC37M81X_BASEADDR0 0x60 +#define SMSC_FDC37M81X_BASEADDR1 0x61 +#define SMSC_FDC37M81X_INT 0x70 +#define SMSC_FDC37M81X_INT2 0x72 +#define SMSC_FDC37M81X_LDCR_F0 0xF0 + +/* Chip Config Values */ +#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 +#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa +#define SMSC_FDC37M81X_CHIP_ID 0x4d + +unsigned long __init smsc_fdc37m81x_init(unsigned long port); + +void smsc_fdc37m81x_config_beg(void); + +void smsc_fdc37m81x_config_end(void); + +void smsc_fdc37m81x_config_set(u8 reg, u8 val); + +#endif diff --git a/include/asm-mips/txx9/spi.h b/include/asm-mips/txx9/spi.h new file mode 100644 index 000000000000..ddfb2a0dc432 --- /dev/null +++ b/include/asm-mips/txx9/spi.h @@ -0,0 +1,19 @@ +/* + * Definitions for TX4937/TX4938 SPI + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TXX9_SPI_H +#define __ASM_TXX9_SPI_H + +extern int spi_eeprom_register(int chipid); +extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); + +#endif /* __ASM_TXX9_SPI_H */ diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h new file mode 100644 index 000000000000..63b62d6061f5 --- /dev/null +++ b/include/asm-mips/txx9/tx3927.h @@ -0,0 +1,319 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Toshiba Corporation + */ +#ifndef __ASM_TXX9_TX3927_H +#define __ASM_TXX9_TX3927_H + +#include + +#define TX3927_SDRAMC_REG 0xfffe8000 +#define TX3927_ROMC_REG 0xfffe9000 +#define TX3927_DMA_REG 0xfffeb000 +#define TX3927_IRC_REG 0xfffec000 +#define TX3927_PCIC_REG 0xfffed000 +#define TX3927_CCFG_REG 0xfffee000 +#define TX3927_NR_TMR 3 +#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) +#define TX3927_NR_SIO 2 +#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) +#define TX3927_PIO_REG 0xfffef500 + +struct tx3927_sdramc_reg { + volatile unsigned long cr[8]; + volatile unsigned long tr[3]; + volatile unsigned long cmd; + volatile unsigned long smrs[2]; +}; + +struct tx3927_romc_reg { + volatile unsigned long cr[8]; +}; + +struct tx3927_dma_reg { + struct tx3927_dma_ch_reg { + volatile unsigned long cha; + volatile unsigned long sar; + volatile unsigned long dar; + volatile unsigned long cntr; + volatile unsigned long sair; + volatile unsigned long dair; + volatile unsigned long ccr; + volatile unsigned long csr; + } ch[4]; + volatile unsigned long dbr[8]; + volatile unsigned long tdhr; + volatile unsigned long mcr; + volatile unsigned long unused0; +}; + +#include + +#ifdef __BIG_ENDIAN +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 +#else +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 +#endif + +struct tx3927_pcic_reg { + endian_def_s2(did, vid); + endian_def_s2(pcistat, pcicmd); + endian_def_b4(cc, scc, rpli, rid); + endian_def_b4(unused0, ht, mlt, cls); + volatile unsigned long ioba; /* +10 */ + volatile unsigned long mba; + volatile unsigned long unused1[5]; + endian_def_s2(svid, ssvid); + volatile unsigned long unused2; /* +30 */ + endian_def_sb2(unused3, unused4, capptr); + volatile unsigned long unused5; + endian_def_b4(ml, mg, ip, il); + volatile unsigned long unused6; /* +40 */ + volatile unsigned long istat; + volatile unsigned long iim; + volatile unsigned long rrt; + volatile unsigned long unused7[3]; /* +50 */ + volatile unsigned long ipbmma; + volatile unsigned long ipbioma; /* +60 */ + volatile unsigned long ilbmma; + volatile unsigned long ilbioma; + volatile unsigned long unused8[9]; + volatile unsigned long tc; /* +90 */ + volatile unsigned long tstat; + volatile unsigned long tim; + volatile unsigned long tccmd; + volatile unsigned long pcirrt; /* +a0 */ + volatile unsigned long pcirrt_cmd; + volatile unsigned long pcirrdt; + volatile unsigned long unused9[3]; + volatile unsigned long tlboap; + volatile unsigned long tlbiap; + volatile unsigned long tlbmma; /* +c0 */ + volatile unsigned long tlbioma; + volatile unsigned long sc_msg; + volatile unsigned long sc_be; + volatile unsigned long tbl; /* +d0 */ + volatile unsigned long unused10[3]; + volatile unsigned long pwmng; /* +e0 */ + volatile unsigned long pwmngs; + volatile unsigned long unused11[6]; + volatile unsigned long req_trace; /* +100 */ + volatile unsigned long pbapmc; + volatile unsigned long pbapms; + volatile unsigned long pbapmim; + volatile unsigned long bm; /* +110 */ + volatile unsigned long cpcibrs; + volatile unsigned long cpcibgs; + volatile unsigned long pbacs; + volatile unsigned long iobas; /* +120 */ + volatile unsigned long mbas; + volatile unsigned long lbc; + volatile unsigned long lbstat; + volatile unsigned long lbim; /* +130 */ + volatile unsigned long pcistatim; + volatile unsigned long ica; + volatile unsigned long icd; + volatile unsigned long iiadp; /* +140 */ + volatile unsigned long iscdp; + volatile unsigned long mmas; + volatile unsigned long iomas; + volatile unsigned long ipciaddr; /* +150 */ + volatile unsigned long ipcidata; + volatile unsigned long ipcibe; +}; + +struct tx3927_ccfg_reg { + volatile unsigned long ccfg; + volatile unsigned long crir; + volatile unsigned long pcfg; + volatile unsigned long tear; + volatile unsigned long pdcr; +}; + +/* + * SDRAMC + */ + +/* + * ROMC + */ + +/* + * DMA + */ +/* bits for MCR */ +#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) +#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) +#define TX3927_DMA_MCR_RSFIF 0x00000080 +#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) +#define TX3927_DMA_MCR_LE 0x00000004 +#define TX3927_DMA_MCR_RPRT 0x00000002 +#define TX3927_DMA_MCR_MSTEN 0x00000001 + +/* bits for CCRn */ +#define TX3927_DMA_CCR_DBINH 0x04000000 +#define TX3927_DMA_CCR_SBINH 0x02000000 +#define TX3927_DMA_CCR_CHRST 0x01000000 +#define TX3927_DMA_CCR_RVBYTE 0x00800000 +#define TX3927_DMA_CCR_ACKPOL 0x00400000 +#define TX3927_DMA_CCR_REQPL 0x00200000 +#define TX3927_DMA_CCR_EGREQ 0x00100000 +#define TX3927_DMA_CCR_CHDN 0x00080000 +#define TX3927_DMA_CCR_DNCTL 0x00060000 +#define TX3927_DMA_CCR_EXTRQ 0x00010000 +#define TX3927_DMA_CCR_INTRQD 0x0000e000 +#define TX3927_DMA_CCR_INTENE 0x00001000 +#define TX3927_DMA_CCR_INTENC 0x00000800 +#define TX3927_DMA_CCR_INTENT 0x00000400 +#define TX3927_DMA_CCR_CHNEN 0x00000200 +#define TX3927_DMA_CCR_XFACT 0x00000100 +#define TX3927_DMA_CCR_SNOP 0x00000080 +#define TX3927_DMA_CCR_DSTINC 0x00000040 +#define TX3927_DMA_CCR_SRCINC 0x00000020 +#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) +#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) +#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) +#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) +#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) +#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) +#define TX3927_DMA_CCR_MEMIO 0x00000002 +#define TX3927_DMA_CCR_ONEAD 0x00000001 + +/* bits for CSRn */ +#define TX3927_DMA_CSR_CHNACT 0x00000100 +#define TX3927_DMA_CSR_ABCHC 0x00000080 +#define TX3927_DMA_CSR_NCHNC 0x00000040 +#define TX3927_DMA_CSR_NTRNFC 0x00000020 +#define TX3927_DMA_CSR_EXTDN 0x00000010 +#define TX3927_DMA_CSR_CFERR 0x00000008 +#define TX3927_DMA_CSR_CHERR 0x00000004 +#define TX3927_DMA_CSR_DESERR 0x00000002 +#define TX3927_DMA_CSR_SORERR 0x00000001 + +/* + * IRC + */ +#define TX3927_IR_INT0 0 +#define TX3927_IR_INT1 1 +#define TX3927_IR_INT2 2 +#define TX3927_IR_INT3 3 +#define TX3927_IR_INT4 4 +#define TX3927_IR_INT5 5 +#define TX3927_IR_SIO0 6 +#define TX3927_IR_SIO1 7 +#define TX3927_IR_SIO(ch) (6 + (ch)) +#define TX3927_IR_DMA 8 +#define TX3927_IR_PIO 9 +#define TX3927_IR_PCI 10 +#define TX3927_IR_TMR(ch) (13 + (ch)) +#define TX3927_NUM_IR 16 + +/* + * PCIC + */ +/* bits for PCICMD */ +/* see PCI_COMMAND_XXX in linux/pci.h */ + +/* bits for PCISTAT */ +/* see PCI_STATUS_XXX in linux/pci.h */ +#define PCI_STATUS_NEW_CAP 0x0010 + +/* bits for TC */ +#define TX3927_PCIC_TC_OF16E 0x00000020 +#define TX3927_PCIC_TC_IF8E 0x00000010 +#define TX3927_PCIC_TC_OF8E 0x00000008 + +/* bits for IOBA/MBA */ +/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ + +/* bits for PBAPMC */ +#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 +#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 +#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 + +/* bits for LBSTAT/LBIM */ +#define TX3927_PCIC_LBIM_ALL 0x0000003e + +/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900 + +/* bits for LBC */ +#define TX3927_PCIC_LBC_IBSE 0x00004000 +#define TX3927_PCIC_LBC_TIBSE 0x00002000 +#define TX3927_PCIC_LBC_TMFBSE 0x00001000 +#define TX3927_PCIC_LBC_HRST 0x00000800 +#define TX3927_PCIC_LBC_SRST 0x00000400 +#define TX3927_PCIC_LBC_EPCAD 0x00000200 +#define TX3927_PCIC_LBC_MSDSE 0x00000100 +#define TX3927_PCIC_LBC_CRR 0x00000080 +#define TX3927_PCIC_LBC_ILMDE 0x00000040 +#define TX3927_PCIC_LBC_ILIDE 0x00000020 + +#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX3927_CCFG_TLBOFF 0x00020000 +#define TX3927_CCFG_BEOW 0x00010000 +#define TX3927_CCFG_WR 0x00008000 +#define TX3927_CCFG_TOE 0x00004000 +#define TX3927_CCFG_PCIXARB 0x00002000 +#define TX3927_CCFG_PCI3 0x00001000 +#define TX3927_CCFG_PSNP 0x00000800 +#define TX3927_CCFG_PPRI 0x00000400 +#define TX3927_CCFG_PLLM 0x00000030 +#define TX3927_CCFG_ENDIAN 0x00000004 +#define TX3927_CCFG_HALT 0x00000002 +#define TX3927_CCFG_ACEHOLD 0x00000001 + +/* PCFG : Pin Configuration */ +#define TX3927_PCFG_SYSCLKEN 0x08000000 +#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000 +#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) +#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000 +#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) +#define TX3927_PCFG_SELALL 0x0003ffff +#define TX3927_PCFG_SELCS 0x00020000 +#define TX3927_PCFG_SELDSF 0x00010000 +#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 +#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) +#define TX3927_PCFG_SELSIO_ALL 0x00003000 +#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) +#define TX3927_PCFG_SELTMR_ALL 0x00000e00 +#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch)) +#define TX3927_PCFG_SELDONE 0x00000100 +#define TX3927_PCFG_INTDMA_ALL 0x000000f0 +#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch)) +#define TX3927_PCFG_SELDMA_ALL 0x0000000f +#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) + +#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) +#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) +#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) +#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) +#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) +#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) +#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) +#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) + +#endif /* __ASM_TXX9_TX3927_H */ diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h new file mode 100644 index 000000000000..f21a7b1831e5 --- /dev/null +++ b/include/asm-mips/txx9/tx4927.h @@ -0,0 +1,280 @@ +/* + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2006 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_TXX9_TX4927_H +#define __ASM_TXX9_TX4927_H + +#include + +#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) + +#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) + + +#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) +#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) +#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) +#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) + +#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) + +#define TX4927_CCFG_TOE 0x00004000 +#define TX4927_CCFG_WR 0x00008000 +#define TX4927_CCFG_TINTDIS 0x01000000 + +#define TX4927_PCIMEM 0x08000000 +#define TX4927_PCIMEM_SIZE 0x08000000 +#define TX4927_PCIIO 0x16000000 +#define TX4927_PCIIO_SIZE 0x01000000 + +#define TX4927_SDRAMC_REG 0xff1f8000 +#define TX4927_EBUSC_REG 0xff1f9000 +#define TX4927_PCIC_REG 0xff1fd000 +#define TX4927_CCFG_REG 0xff1fe000 +#define TX4927_IRC_REG 0xff1ff600 +#define TX4927_NR_TMR 3 +#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) + +/* bits for ISTAT3/IMASK3/IMSTAT3 */ +#define TX4927_INT3B_PCID 0 +#define TX4927_INT3B_PCIC 1 +#define TX4927_INT3B_PCIB 2 +#define TX4927_INT3B_PCIA 3 +#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) +#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) +#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) +#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) + +#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG +#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ + +#define TX4927_IR_PCIC 16 +#define TX4927_IR_PCIERR 22 +#define TX4927_IR_PCIPMA 23 +#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) +#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) +#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) +#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) +#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) +#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) +#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) + +#ifdef _LANGUAGE_ASSEMBLY +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include + +struct tx4927_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; +}; + +struct tx4927_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4927_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; +}; + +struct tx4927_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmcut; + volatile unsigned long long pdmcnt; /* +220 */ + volatile unsigned long long pdmsts; + volatile unsigned long long unused8[2]; + volatile unsigned long long pdmdb[4]; /* +240 */ + volatile unsigned long long pdmtdh; /* +260 */ + volatile unsigned long long pdmdms; +}; + +#endif /* _LANGUAGE_ASSEMBLY */ + +/* + * PCIC + */ + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4927_PCIC_PBACFG_RPBA 0x00000004 +#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc + +/* bits for PCICCFG */ +#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 +#define TX4927_PCIC_PCICCFG_HRST 0x00000800 +#define TX4927_PCIC_PCICCFG_SRST 0x00000400 +#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 +#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 +#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 +#define TX4927_PCIC_PCICCFG_IISE 0x00000020 +#define TX4927_PCIC_PCICCFG_ATR 0x00000010 +#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4927_CCFG_PCI66 0x00800000 +#define TX4927_CCFG_PCIMIDE 0x00400000 +#define TX4927_CCFG_PCIXARB 0x00002000 +#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 +#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 +#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 +#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 +#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 + +#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 +#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 +#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 +#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 +#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 +#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 +#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 +#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 + +/* PCFG : Pin Configuration */ +#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) + +/* CLKCTR : Clock Control */ +#define TX4927_CLKCTR_PCICKD 0x00400000 +#define TX4927_CLKCTR_PCIRST 0x00000040 + +#ifndef _LANGUAGE_ASSEMBLY + +#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) +#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) +#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) +#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) + +#endif /* _LANGUAGE_ASSEMBLY */ + +#endif /* __ASM_TXX9_TX4927_H */ diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h new file mode 100644 index 000000000000..7f9cfef1c6d2 --- /dev/null +++ b/include/asm-mips/txx9/tx4938.h @@ -0,0 +1,627 @@ +/* + * Definitions for TX4937/TX4938 + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TXX9_TX4938_H +#define __ASM_TXX9_TX4938_H + +#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) +#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) + +#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG + +#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) +#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) + +#define TX4938_PCIIO_0 0x10000000 +#define TX4938_PCIIO_1 0x01010000 +#define TX4938_PCIMEM_0 0x08000000 +#define TX4938_PCIMEM_1 0x11000000 + +#define TX4938_PCIIO_SIZE_0 0x01000000 +#define TX4938_PCIIO_SIZE_1 0x00010000 +#define TX4938_PCIMEM_SIZE_0 0x08000000 +#define TX4938_PCIMEM_SIZE_1 0x00010000 + +#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */ +#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ + +/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ +#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) +#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000) +#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000) +#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000) +#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000) +#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) +#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000) +#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000) +#define TX4938_NR_TMR 3 +#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) +#define TX4938_NR_SIO 2 +#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) +#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500) +#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600) +#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) +#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) + +#ifdef __ASSEMBLY__ +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include + +#ifdef __BIG_ENDIAN +#define endian_def_l2(e1, e2) \ + volatile unsigned long e1, e2 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 +#else +#define endian_def_l2(e1, e2) \ + volatile unsigned long e2, e1 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 +#endif + + +struct tx4938_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; + volatile unsigned long long sfcmd; +}; + +struct tx4938_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4938_dma_reg { + struct tx4938_dma_ch_reg { + volatile unsigned long long cha; + volatile unsigned long long sar; + volatile unsigned long long dar; + endian_def_l2(unused0, cntr); + endian_def_l2(unused1, sair); + endian_def_l2(unused2, dair); + endian_def_l2(unused3, ccr); + endian_def_l2(unused4, csr); + } ch[4]; + volatile unsigned long long dbr[8]; + volatile unsigned long long tdhr; + volatile unsigned long long midr; + endian_def_l2(unused0, mcr); +}; + +struct tx4938_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmctr; + volatile unsigned long long pdmcfg; /* +220 */ + volatile unsigned long long pdmsts; +}; + +struct tx4938_aclc_reg { + volatile unsigned long acctlen; + volatile unsigned long acctldis; + volatile unsigned long acregacc; + volatile unsigned long unused0; + volatile unsigned long acintsts; + volatile unsigned long acintmsts; + volatile unsigned long acinten; + volatile unsigned long acintdis; + volatile unsigned long acsemaph; + volatile unsigned long unused1[7]; + volatile unsigned long acgpidat; + volatile unsigned long acgpodat; + volatile unsigned long acslten; + volatile unsigned long acsltdis; + volatile unsigned long acfifosts; + volatile unsigned long unused2[11]; + volatile unsigned long acdmasts; + volatile unsigned long acdmasel; + volatile unsigned long unused3[6]; + volatile unsigned long acaudodat; + volatile unsigned long acsurrdat; + volatile unsigned long accentdat; + volatile unsigned long aclfedat; + volatile unsigned long acaudiat; + volatile unsigned long unused4; + volatile unsigned long acmodoat; + volatile unsigned long acmodidat; + volatile unsigned long unused5[15]; + volatile unsigned long acrevid; +}; + + +struct tx4938_tmr_reg { + volatile unsigned long tcr; + volatile unsigned long tisr; + volatile unsigned long cpra; + volatile unsigned long cprb; + volatile unsigned long itmr; + volatile unsigned long unused0[3]; + volatile unsigned long ccdr; + volatile unsigned long unused1[3]; + volatile unsigned long pgmr; + volatile unsigned long unused2[3]; + volatile unsigned long wtmr; + volatile unsigned long unused3[43]; + volatile unsigned long trr; +}; + +struct tx4938_sio_reg { + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; +}; + +struct tx4938_ndfmc_reg { + endian_def_l2(unused0, dtr); + endian_def_l2(unused1, mcr); + endian_def_l2(unused2, sr); + endian_def_l2(unused3, isr); + endian_def_l2(unused4, imr); + endian_def_l2(unused5, spr); + endian_def_l2(unused6, rstr); +}; + +struct tx4938_spi_reg { + volatile unsigned long mcr; + volatile unsigned long cr0; + volatile unsigned long cr1; + volatile unsigned long fs; + volatile unsigned long unused1; + volatile unsigned long sr; + volatile unsigned long dr; + volatile unsigned long unused2; +}; + +struct tx4938_sramc_reg { + volatile unsigned long long cr; +}; + +struct tx4938_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; + volatile unsigned long long unused3; + volatile unsigned long long jmpadr; +}; + +#undef endian_def_l2 +#undef endian_def_s2 +#undef endian_def_sb2 +#undef endian_def_b2s +#undef endian_def_b4 + +#endif /* __ASSEMBLY__ */ + +/* + * NDFMC + */ + +/* NDFMCR : NDFMC Mode Control */ +#define TX4938_NDFMCR_WE 0x80 +#define TX4938_NDFMCR_ECC_ALL 0x60 +#define TX4938_NDFMCR_ECC_RESET 0x60 +#define TX4938_NDFMCR_ECC_READ 0x40 +#define TX4938_NDFMCR_ECC_ON 0x20 +#define TX4938_NDFMCR_ECC_OFF 0x00 +#define TX4938_NDFMCR_CE 0x10 +#define TX4938_NDFMCR_BSPRT 0x04 +#define TX4938_NDFMCR_ALE 0x02 +#define TX4938_NDFMCR_CLE 0x01 + +/* NDFMCR : NDFMC Status */ +#define TX4938_NDFSR_BUSY 0x80 + +/* NDFMCR : NDFMC Reset */ +#define TX4938_NDFRSTR_RST 0x01 + +/* + * IRC + */ + +#define TX4938_IR_ECCERR 0 +#define TX4938_IR_WTOERR 1 +#define TX4938_NUM_IR_INT 6 +#define TX4938_IR_INT(n) (2 + (n)) +#define TX4938_NUM_IR_SIO 2 +#define TX4938_IR_SIO(n) (8 + (n)) +#define TX4938_NUM_IR_DMA 4 +#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ +#define TX4938_IR_PIO 14 +#define TX4938_IR_PDMAC 15 +#define TX4938_IR_PCIC 16 +#define TX4938_NUM_IR_TMR 3 +#define TX4938_IR_TMR(n) (17 + (n)) +#define TX4938_IR_NDFMC 21 +#define TX4938_IR_PCIERR 22 +#define TX4938_IR_PCIPME 23 +#define TX4938_IR_ACLC 24 +#define TX4938_IR_ACLCPME 25 +#define TX4938_IR_PCIC1 26 +#define TX4938_IR_SPI 31 +#define TX4938_NUM_IR 32 +/* multiplex */ +#define TX4938_IR_ETH0 TX4938_IR_INT(4) +#define TX4938_IR_ETH1 TX4938_IR_INT(3) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) +#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) +#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) +#define TX4938_CCFG_TINTDIS 0x01000000 +#define TX4938_CCFG_PCI66 0x00800000 +#define TX4938_CCFG_PCIMODE 0x00400000 +#define TX4938_CCFG_PCI1_66 0x00200000 +#define TX4938_CCFG_DIVMODE_MASK 0x001e0000 +#define TX4938_CCFG_DIVMODE_2 (0x4 << 17) +#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) +#define TX4938_CCFG_DIVMODE_3 (0x5 << 17) +#define TX4938_CCFG_DIVMODE_4 (0x6 << 17) +#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) +#define TX4938_CCFG_DIVMODE_8 (0x0 << 17) +#define TX4938_CCFG_DIVMODE_10 (0xb << 17) +#define TX4938_CCFG_DIVMODE_12 (0x1 << 17) +#define TX4938_CCFG_DIVMODE_16 (0x2 << 17) +#define TX4938_CCFG_DIVMODE_18 (0x9 << 17) +#define TX4938_CCFG_BEOW 0x00010000 +#define TX4938_CCFG_WR 0x00008000 +#define TX4938_CCFG_TOE 0x00004000 +#define TX4938_CCFG_PCIXARB 0x00002000 +#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) +#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) +#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10) +#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10) +#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10) +#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10) +#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10) +#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10) +#define TX4938_CCFG_PCI1DMD 0x00000100 +#define TX4938_CCFG_SYSSP_MASK 0x000000c0 +#define TX4938_CCFG_ENDIAN 0x00000004 +#define TX4938_CCFG_HALT 0x00000002 +#define TX4938_CCFG_ACEHOLD 0x00000001 + +/* PCFG : Pin Configuration */ +#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) +#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) +#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) +#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) +#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) +#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) +#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 +#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) +#define TX4938_PCFG_SYSCLKEN 0x08000000 +#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 +#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) +#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) +#define TX4938_PCFG_SEL2 0x00000200 +#define TX4938_PCFG_SEL1 0x00000100 +#define TX4938_PCFG_DMASEL_ALL 0x0000000f +#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000 +#define TX4938_PCFG_DMASEL0_SIO1 0x00000001 +#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000 +#define TX4938_PCFG_DMASEL1_SIO1 0x00000002 +#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000 +#define TX4938_PCFG_DMASEL2_SIO0 0x00000004 +#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000 +#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 + +/* CLKCTR : Clock Control */ +#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) +#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) +#define TX4938_CLKCTR_ETH1CKD 0x80000000 +#define TX4938_CLKCTR_ETH0CKD 0x40000000 +#define TX4938_CLKCTR_SPICKD 0x20000000 +#define TX4938_CLKCTR_SRAMCKD 0x10000000 +#define TX4938_CLKCTR_PCIC1CKD 0x08000000 +#define TX4938_CLKCTR_DMA1CKD 0x04000000 +#define TX4938_CLKCTR_ACLCKD 0x02000000 +#define TX4938_CLKCTR_PIOCKD 0x01000000 +#define TX4938_CLKCTR_DMACKD 0x00800000 +#define TX4938_CLKCTR_PCICKD 0x00400000 +#define TX4938_CLKCTR_TM0CKD 0x00100000 +#define TX4938_CLKCTR_TM1CKD 0x00080000 +#define TX4938_CLKCTR_TM2CKD 0x00040000 +#define TX4938_CLKCTR_SIO0CKD 0x00020000 +#define TX4938_CLKCTR_SIO1CKD 0x00010000 +#define TX4938_CLKCTR_ETH1RST 0x00008000 +#define TX4938_CLKCTR_ETH0RST 0x00004000 +#define TX4938_CLKCTR_SPIRST 0x00002000 +#define TX4938_CLKCTR_SRAMRST 0x00001000 +#define TX4938_CLKCTR_PCIC1RST 0x00000800 +#define TX4938_CLKCTR_DMA1RST 0x00000400 +#define TX4938_CLKCTR_ACLRST 0x00000200 +#define TX4938_CLKCTR_PIORST 0x00000100 +#define TX4938_CLKCTR_DMARST 0x00000080 +#define TX4938_CLKCTR_PCIRST 0x00000040 +#define TX4938_CLKCTR_TM0RST 0x00000010 +#define TX4938_CLKCTR_TM1RST 0x00000008 +#define TX4938_CLKCTR_TM2RST 0x00000004 +#define TX4938_CLKCTR_SIO0RST 0x00000002 +#define TX4938_CLKCTR_SIO1RST 0x00000001 + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 +#define TX4938_PCIC_PBACFG_RPBA 0x00000004 +#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 +#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 +#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 +#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 +#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 +#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 +#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 +#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 +#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 +#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 + +/* bits for PCICCFG */ +#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 +#define TX4938_PCIC_PCICCFG_HRST 0x00000800 +#define TX4938_PCIC_PCICCFG_SRST 0x00000400 +#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) +#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 +#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 +#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 +#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 +#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 +#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) + +/* bits for PDMCFG */ +#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 +#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 +#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 +#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) +#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 +#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 +#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 +#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 +#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 +#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 +#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c +#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 +#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 +#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 +#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 +#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 + +/* bits for PDMSTS */ +#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 +#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 +#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 +#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 +#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 +#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 +#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 +#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 +#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 +#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 +#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 +#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 +#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 +#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 +#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 +#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 +#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f + +/* + * DMA + */ +/* bits for MCR */ +#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) +#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) +#define TX4938_DMA_MCR_RSFIF 0x00000080 +#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) +#define TX4938_DMA_MCR_RPRT 0x00000002 +#define TX4938_DMA_MCR_MSTEN 0x00000001 + +/* bits for CCRn */ +#define TX4938_DMA_CCR_IMMCHN 0x20000000 +#define TX4938_DMA_CCR_USEXFSZ 0x10000000 +#define TX4938_DMA_CCR_LE 0x08000000 +#define TX4938_DMA_CCR_DBINH 0x04000000 +#define TX4938_DMA_CCR_SBINH 0x02000000 +#define TX4938_DMA_CCR_CHRST 0x01000000 +#define TX4938_DMA_CCR_RVBYTE 0x00800000 +#define TX4938_DMA_CCR_ACKPOL 0x00400000 +#define TX4938_DMA_CCR_REQPL 0x00200000 +#define TX4938_DMA_CCR_EGREQ 0x00100000 +#define TX4938_DMA_CCR_CHDN 0x00080000 +#define TX4938_DMA_CCR_DNCTL 0x00060000 +#define TX4938_DMA_CCR_EXTRQ 0x00010000 +#define TX4938_DMA_CCR_INTRQD 0x0000e000 +#define TX4938_DMA_CCR_INTENE 0x00001000 +#define TX4938_DMA_CCR_INTENC 0x00000800 +#define TX4938_DMA_CCR_INTENT 0x00000400 +#define TX4938_DMA_CCR_CHNEN 0x00000200 +#define TX4938_DMA_CCR_XFACT 0x00000100 +#define TX4938_DMA_CCR_SMPCHN 0x00000020 +#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) +#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2) +#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) +#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) +#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) +#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) +#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) +#define TX4938_DMA_CCR_MEMIO 0x00000002 +#define TX4938_DMA_CCR_SNGAD 0x00000001 + +/* bits for CSRn */ +#define TX4938_DMA_CSR_CHNEN 0x00000400 +#define TX4938_DMA_CSR_STLXFER 0x00000200 +#define TX4938_DMA_CSR_CHNACT 0x00000100 +#define TX4938_DMA_CSR_ABCHC 0x00000080 +#define TX4938_DMA_CSR_NCHNC 0x00000040 +#define TX4938_DMA_CSR_NTRNFC 0x00000020 +#define TX4938_DMA_CSR_EXTDN 0x00000010 +#define TX4938_DMA_CSR_CFERR 0x00000008 +#define TX4938_DMA_CSR_CHERR 0x00000004 +#define TX4938_DMA_CSR_DESERR 0x00000002 +#define TX4938_DMA_CSR_SORERR 0x00000001 + +#ifndef __ASSEMBLY__ + +#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) +#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) +#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) +#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) +#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) +#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) +#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) +#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) +#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) +#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) +#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) +#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) + + +#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) +#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) + +#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) +#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) + +#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) +#define TX4938_EBUSC_SIZE(ch) \ + (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) + + +#endif /* !__ASSEMBLY__ */ + +#endif diff --git a/include/asm-mips/txx9/txx927.h b/include/asm-mips/txx9/txx927.h new file mode 100644 index 000000000000..97dd7ad1a890 --- /dev/null +++ b/include/asm-mips/txx9/txx927.h @@ -0,0 +1,121 @@ +/* + * Common definitions for TX3927/TX4927 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Toshiba Corporation + */ +#ifndef __ASM_TXX9_TXX927_H +#define __ASM_TXX9_TXX927_H + +struct txx927_sio_reg { + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; +}; + +/* + * SIO + */ +/* SILCR : Line Control */ +#define TXx927_SILCR_SCS_MASK 0x00000060 +#define TXx927_SILCR_SCS_IMCLK 0x00000000 +#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020 +#define TXx927_SILCR_SCS_SCLK 0x00000040 +#define TXx927_SILCR_SCS_SCLK_BG 0x00000060 +#define TXx927_SILCR_UEPS 0x00000010 +#define TXx927_SILCR_UPEN 0x00000008 +#define TXx927_SILCR_USBL_MASK 0x00000004 +#define TXx927_SILCR_USBL_1BIT 0x00000004 +#define TXx927_SILCR_USBL_2BIT 0x00000000 +#define TXx927_SILCR_UMODE_MASK 0x00000003 +#define TXx927_SILCR_UMODE_8BIT 0x00000000 +#define TXx927_SILCR_UMODE_7BIT 0x00000001 + +/* SIDICR : DMA/Int. Control */ +#define TXx927_SIDICR_TDE 0x00008000 +#define TXx927_SIDICR_RDE 0x00004000 +#define TXx927_SIDICR_TIE 0x00002000 +#define TXx927_SIDICR_RIE 0x00001000 +#define TXx927_SIDICR_SPIE 0x00000800 +#define TXx927_SIDICR_CTSAC 0x00000600 +#define TXx927_SIDICR_STIE_MASK 0x0000003f +#define TXx927_SIDICR_STIE_OERS 0x00000020 +#define TXx927_SIDICR_STIE_CTSS 0x00000010 +#define TXx927_SIDICR_STIE_RBRKD 0x00000008 +#define TXx927_SIDICR_STIE_TRDY 0x00000004 +#define TXx927_SIDICR_STIE_TXALS 0x00000002 +#define TXx927_SIDICR_STIE_UBRKD 0x00000001 + +/* SIDISR : DMA/Int. Status */ +#define TXx927_SIDISR_UBRK 0x00008000 +#define TXx927_SIDISR_UVALID 0x00004000 +#define TXx927_SIDISR_UFER 0x00002000 +#define TXx927_SIDISR_UPER 0x00001000 +#define TXx927_SIDISR_UOER 0x00000800 +#define TXx927_SIDISR_ERI 0x00000400 +#define TXx927_SIDISR_TOUT 0x00000200 +#define TXx927_SIDISR_TDIS 0x00000100 +#define TXx927_SIDISR_RDIS 0x00000080 +#define TXx927_SIDISR_STIS 0x00000040 +#define TXx927_SIDISR_RFDN_MASK 0x0000001f + +/* SICISR : Change Int. Status */ +#define TXx927_SICISR_OERS 0x00000020 +#define TXx927_SICISR_CTSS 0x00000010 +#define TXx927_SICISR_RBRKD 0x00000008 +#define TXx927_SICISR_TRDY 0x00000004 +#define TXx927_SICISR_TXALS 0x00000002 +#define TXx927_SICISR_UBRKD 0x00000001 + +/* SIFCR : FIFO Control */ +#define TXx927_SIFCR_SWRST 0x00008000 +#define TXx927_SIFCR_RDIL_MASK 0x00000180 +#define TXx927_SIFCR_RDIL_1 0x00000000 +#define TXx927_SIFCR_RDIL_4 0x00000080 +#define TXx927_SIFCR_RDIL_8 0x00000100 +#define TXx927_SIFCR_RDIL_12 0x00000180 +#define TXx927_SIFCR_RDIL_MAX 0x00000180 +#define TXx927_SIFCR_TDIL_MASK 0x00000018 +#define TXx927_SIFCR_TDIL_MASK 0x00000018 +#define TXx927_SIFCR_TDIL_1 0x00000000 +#define TXx927_SIFCR_TDIL_4 0x00000001 +#define TXx927_SIFCR_TDIL_8 0x00000010 +#define TXx927_SIFCR_TDIL_MAX 0x00000010 +#define TXx927_SIFCR_TFRST 0x00000004 +#define TXx927_SIFCR_RFRST 0x00000002 +#define TXx927_SIFCR_FRSTE 0x00000001 +#define TXx927_SIO_TX_FIFO 8 +#define TXx927_SIO_RX_FIFO 16 + +/* SIFLCR : Flow Control */ +#define TXx927_SIFLCR_RCS 0x00001000 +#define TXx927_SIFLCR_TES 0x00000800 +#define TXx927_SIFLCR_RTSSC 0x00000200 +#define TXx927_SIFLCR_RSDE 0x00000100 +#define TXx927_SIFLCR_TSDE 0x00000080 +#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e +#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e +#define TXx927_SIFLCR_TBRK 0x00000001 + +/* SIBGR : Baudrate Control */ +#define TXx927_SIBGR_BCLK_MASK 0x00000300 +#define TXx927_SIBGR_BCLK_T0 0x00000000 +#define TXx927_SIBGR_BCLK_T2 0x00000100 +#define TXx927_SIBGR_BCLK_T4 0x00000200 +#define TXx927_SIBGR_BCLK_T6 0x00000300 +#define TXx927_SIBGR_BRD_MASK 0x000000ff + +/* + * PIO + */ + +#endif /* __ASM_TXX9_TXX927_H */ -- cgit v1.2.3 From 89d63fe179520b11f54de1f26755b7444c79e73a Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 11 Jul 2008 00:33:08 +0900 Subject: [MIPS] TXx9: Reorganize PCI code Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 3 +- arch/mips/pci/Makefile | 8 +- arch/mips/pci/fixup-jmr3927.c | 25 +- arch/mips/pci/fixup-rbtx4927.c | 112 ++----- arch/mips/pci/fixup-rbtx4938.c | 52 +-- arch/mips/pci/ops-tx3927.c | 87 ++++- arch/mips/pci/ops-tx4927.c | 514 +++++++++++++++++++--------- arch/mips/pci/ops-tx4938.c | 214 ------------ arch/mips/pci/pci-jmr3927.c | 58 ---- arch/mips/pci/pci-tx4927.c | 83 +++++ arch/mips/pci/pci-tx4938.c | 134 ++++++++ arch/mips/txx9/Kconfig | 11 +- arch/mips/txx9/generic/Makefile | 2 + arch/mips/txx9/generic/pci.c | 377 +++++++++++++++++++++ arch/mips/txx9/generic/setup.c | 51 +++ arch/mips/txx9/jmr3927/irq.c | 2 + arch/mips/txx9/jmr3927/setup.c | 108 ++---- arch/mips/txx9/rbtx4927/irq.c | 20 +- arch/mips/txx9/rbtx4927/setup.c | 499 +++++++-------------------- arch/mips/txx9/rbtx4938/setup.c | 667 ++++++------------------------------- include/asm-mips/txx9/generic.h | 23 ++ include/asm-mips/txx9/pci.h | 36 ++ include/asm-mips/txx9/rbtx4927.h | 29 +- include/asm-mips/txx9/tx3927.h | 4 + include/asm-mips/txx9/tx4927.h | 318 ++++++++---------- include/asm-mips/txx9/tx4927pcic.h | 199 +++++++++++ include/asm-mips/txx9/tx4938.h | 226 ++----------- 27 files changed, 1851 insertions(+), 2011 deletions(-) delete mode 100644 arch/mips/pci/ops-tx4938.c delete mode 100644 arch/mips/pci/pci-jmr3927.c create mode 100644 arch/mips/pci/pci-tx4927.c create mode 100644 arch/mips/pci/pci-tx4938.c create mode 100644 arch/mips/txx9/generic/pci.c create mode 100644 arch/mips/txx9/generic/setup.c create mode 100644 include/asm-mips/txx9/generic.h create mode 100644 include/asm-mips/txx9/pci.h create mode 100644 include/asm-mips/txx9/tx4927pcic.h (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3202960f7597..2ea6fff88811 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -575,7 +575,7 @@ config TOSHIBA_RBTX4927 select HW_HAS_PCI select IRQ_CPU select IRQ_TXX9 - select I8259 if TOSHIBA_FPCIB0 + select PCI_TX4927 select SWAP_IO_SPACE select SYS_HAS_CPU_TX49XX select SYS_SUPPORTS_32BIT_KERNEL @@ -598,6 +598,7 @@ config TOSHIBA_RBTX4938 select HW_HAS_PCI select IRQ_CPU select IRQ_TXX9 + select PCI_TX4927 select SWAP_IO_SPACE select SYS_HAS_CPU_TX49XX select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 4608e43de28c..908764878ac8 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -15,6 +15,8 @@ obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o +obj-$(CONFIG_PCI_TX3927) += ops-tx3927.o +obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o # # These are still pretty much in the old state, watch, go blind. @@ -41,9 +43,9 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o -obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o -obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o ops-tx4938.o +obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o +obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o pci-tx4927.o pci-tx4938.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o pci-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index 41dcd6a3aae5..d5edaf21e088 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -28,36 +28,31 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include -#include - +#include #include int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; - /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ - if (dev->vendor == PCI_VENDOR_ID_EFAR && - dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1) - return irq; /* IRQ rotation (PICMG) */ irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) { + if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) { /* PCI CardSlot (IDSEL=A23, DevNu=12) */ /* PCIA => PCIC (IDSEL=A23) */ /* NOTE: JMR3927 JP1 must be set to OPEN */ irq = (irq + 2) % 4; - } else if (dev->bus->parent == NULL && - slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) { + } else if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) { /* PCI CardSlot (IDSEL=A22, DevNu=11) */ /* PCIA => PCIA (IDSEL=A22) */ /* NOTE: JMR3927 JP1 must be set to OPEN */ irq = (irq + 0) % 4; } else { /* PCI Backplane */ - irq = (irq + 3 + slot) % 4; + if (txx9_pci_option & TXX9_PCI_OPT_PICMG) + irq = (irq + 33 - slot) % 4; + else + irq = (irq + 3 + slot) % 4; } irq++; /* 1-4 */ @@ -66,15 +61,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) irq = JMR3927_IRQ_IOC_PCIA; break; case 2: - // wrong for backplane irq = JMR3927_IRQ_IOC_PCIB; - irq = JMR3927_IRQ_IOC_PCID; + irq = JMR3927_IRQ_IOC_PCIB; break; case 3: irq = JMR3927_IRQ_IOC_PCIC; break; case 4: - // wrong for backplane irq = JMR3927_IRQ_IOC_PCID; - irq = JMR3927_IRQ_IOC_PCIB; + irq = JMR3927_IRQ_IOC_PCID; break; } diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 26013badfe1f..abab4852d158 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -33,102 +33,42 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include -#include -#include +#include +#include -#include - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -/* look up table for backplane pci irq for slots 17-20 by pin # */ -static unsigned char backplane_pci_irq[4][4] = { - /* PJ6 SLOT: 17, PIN: 1 */ {TX4927_IRQ_IOC_PCIA, - /* PJ6 SLOT: 17, PIN: 2 */ - TX4927_IRQ_IOC_PCIB, - /* PJ6 SLOT: 17, PIN: 3 */ - TX4927_IRQ_IOC_PCIC, - /* PJ6 SLOT: 17, PIN: 4 */ - TX4927_IRQ_IOC_PCID}, - /* SB SLOT: 18, PIN: 1 */ {TX4927_IRQ_IOC_PCIB, - /* SB SLOT: 18, PIN: 2 */ - TX4927_IRQ_IOC_PCIC, - /* SB SLOT: 18, PIN: 3 */ - TX4927_IRQ_IOC_PCID, - /* SB SLOT: 18, PIN: 4 */ - TX4927_IRQ_IOC_PCIA}, - /* PJ5 SLOT: 19, PIN: 1 */ {TX4927_IRQ_IOC_PCIC, - /* PJ5 SLOT: 19, PIN: 2 */ - TX4927_IRQ_IOC_PCID, - /* PJ5 SLOT: 19, PIN: 3 */ - TX4927_IRQ_IOC_PCIA, - /* PJ5 SLOT: 19, PIN: 4 */ - TX4927_IRQ_IOC_PCIB}, - /* PJ4 SLOT: 20, PIN: 1 */ {TX4927_IRQ_IOC_PCID, - /* PJ4 SLOT: 20, PIN: 2 */ - TX4927_IRQ_IOC_PCIA, - /* PJ4 SLOT: 20, PIN: 3 */ - TX4927_IRQ_IOC_PCIB, - /* PJ4 SLOT: 20, PIN: 4 */ - TX4927_IRQ_IOC_PCIC} -}; - -static int pci_get_irq(const struct pci_dev *dev, int pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; - DBG("pci_get_irq: pin is %d\n", pin); /* IRQ rotation */ irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - PCI_SLOT(dev->devfn) == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { - printk("Onboard PCI_SLOT(dev->devfn) is %d\n", - PCI_SLOT(dev->devfn)); - /* IDSEL=A23 is tx4927 onboard pci slot */ - irq = (irq + PCI_SLOT(dev->devfn)) % 4; - irq++; /* 1-4 */ - DBG("irq is now %d\n", irq); - - switch (irq) { - case 1: - irq = TX4927_IRQ_IOC_PCIA; - break; - case 2: - irq = TX4927_IRQ_IOC_PCIB; - break; - case 3: - irq = TX4927_IRQ_IOC_PCIC; - break; - case 4: - irq = TX4927_IRQ_IOC_PCID; - break; - } + if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { + /* PCI CardSlot (IDSEL=A23) */ + /* PCIA => PCIA */ + irq = (irq + 0 + slot) % 4; } else { /* PCI Backplane */ - DBG("PCI Backplane PCI_SLOT(dev->devfn) is %d\n", - PCI_SLOT(dev->devfn)); - irq = backplane_pci_irq[PCI_SLOT(dev->devfn) - 17][irq]; + if (txx9_pci_option & TXX9_PCI_OPT_PICMG) + irq = (irq + 33 - slot) % 4; + else + irq = (irq + 3 + slot) % 4; } - DBG("assigned irq %d\n", irq); - return irq; -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char irq; - - printk("PCI Setup for pin %d \n", pin); - - if (dev->device == 0x9130) /* IDE */ - irq = 14; - else - irq = pci_get_irq(dev, pin); + irq++; /* 1-4 */ + switch (irq) { + case 1: + irq = RBTX4927_IRQ_IOC_PCIA; + break; + case 2: + irq = RBTX4927_IRQ_IOC_PCIB; + break; + case 3: + irq = RBTX4927_IRQ_IOC_PCIC; + break; + case 4: + irq = RBTX4927_IRQ_IOC_PCID; + break; + } return irq; } diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c index 64d4510c0265..39c995830384 100644 --- a/arch/mips/pci/fixup-rbtx4938.c +++ b/arch/mips/pci/fixup-rbtx4938.c @@ -10,45 +10,28 @@ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) */ #include -#include -#include -#include - +#include #include -extern struct pci_controller tx4938_pci_controller[]; - -static int pci_get_irq(const struct pci_dev *dev, int pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - int irq = pin; - u8 slot = PCI_SLOT(dev->devfn); - struct pci_controller *controller = (struct pci_controller *)dev->sysdata; - - if (controller == &tx4938_pci_controller[1]) { - /* TX4938 PCIC1 */ - switch (slot) { - case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; - break; - case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; - break; - } - return 0; - } + int irq = tx4938_pcic1_map_irq(dev, slot); + if (irq >= 0) + return irq; + irq = pin; /* IRQ rotation */ irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { + if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { /* PCI CardSlot (IDSEL=A23) */ /* PCIA => PCIA (IDSEL=A23) */ irq = (irq + 0 + slot) % 4; } else { /* PCI Backplane */ - irq = (irq + 33 - slot) % 4; + if (txx9_pci_option & TXX9_PCI_OPT_PICMG) + irq = (irq + 33 - slot) % 4; + else + irq = (irq + 3 + slot) % 4; } irq++; /* 1-4 */ @@ -69,19 +52,6 @@ static int pci_get_irq(const struct pci_dev *dev, int pin) return irq; } -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char irq = 0; - - irq = pci_get_irq(dev, pin); - - printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", - dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), irq); - - return irq; -} - /* * Do platform specific device initialization at pci_enable_device() time */ diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c index 5d398f694682..8a17a39e5bf2 100644 --- a/arch/mips/pci/ops-tx3927.c +++ b/arch/mips/pci/ops-tx3927.c @@ -8,7 +8,7 @@ * * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c * - * Define the pci_ops for JMR3927. + * Define the pci_ops for TX3927. * * Much of the code is derived from the original DDB5074 port by * Geert Uytterhoeven @@ -39,7 +39,7 @@ #include #include -#include +#include static inline int mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where) @@ -68,7 +68,7 @@ static inline int check_abort(void) return PCIBIOS_SUCCESSFUL; } -static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, +static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) { int ret; @@ -94,7 +94,7 @@ static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, return check_abort(); } -static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, +static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { int ret; @@ -125,7 +125,80 @@ static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, return check_abort(); } -struct pci_ops jmr3927_pci_ops = { - jmr3927_pci_read_config, - jmr3927_pci_write_config, +static struct pci_ops tx3927_pci_ops = { + .read = tx3927_pci_read_config, + .write = tx3927_pci_write_config, }; + +void __init tx3927_pcic_setup(struct pci_controller *channel, + unsigned long sdram_size, int extarb) +{ + unsigned long flags; + unsigned long io_base = + channel->io_resource->start + mips_io_port_base - IO_BASE; + unsigned long io_size = + channel->io_resource->end - channel->io_resource->start; + unsigned long io_pciaddr = + channel->io_resource->start - channel->io_offset; + unsigned long mem_base = + channel->mem_resource->start; + unsigned long mem_size = + channel->mem_resource->end - channel->mem_resource->start; + unsigned long mem_pciaddr = + channel->mem_resource->start - channel->mem_offset; + + printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s", + tx3927_pcicptr->did, tx3927_pcicptr->vid, + tx3927_pcicptr->rid, + extarb ? "External" : "Internal"); + channel->pci_ops = &tx3927_pci_ops; + + local_irq_save(flags); + /* Disable External PCI Config. Access */ + tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; +#ifdef __BIG_ENDIAN + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | + TX3927_PCIC_LBC_TIBSE | + TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; +#endif + /* LB->PCI mappings */ + tx3927_pcicptr->iomas = ~(io_size - 1); + tx3927_pcicptr->ilbioma = io_base; + tx3927_pcicptr->ipbioma = io_pciaddr; + tx3927_pcicptr->mmas = ~(mem_size - 1); + tx3927_pcicptr->ilbmma = mem_base; + tx3927_pcicptr->ipbmma = mem_pciaddr; + /* PCI->LB mappings */ + tx3927_pcicptr->iobas = 0xffffffff; + tx3927_pcicptr->ioba = 0; + tx3927_pcicptr->tlbioma = 0; + tx3927_pcicptr->mbas = ~(sdram_size - 1); + tx3927_pcicptr->mba = 0; + tx3927_pcicptr->tlbmma = 0; + /* Enable Direct mapping Address Space Decoder */ + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; + + /* Clear All Local Bus Status */ + tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; + /* Enable All Local Bus Interrupts */ + tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; + /* Clear All PCI Status Error */ + tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; + /* Enable All PCI Status Error Interrupts */ + tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; + + /* PCIC Int => IRC IRQ10 */ + tx3927_pcicptr->il = TX3927_IR_PCI; + /* Target Control (per errata) */ + tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; + + /* Enable Bus Arbiter */ + if (!extarb) + tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; + + tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_IO | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + local_irq_restore(flags); +} diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 54730eee451b..c6b49bccd274 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -1,206 +1,408 @@ /* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com + * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc. * - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c - * - * Define the pci_ops for the Toshiba rbtx4927 - * - * Much of the code is derived from the original DDB5074 port by - * Geert Uytterhoeven - * - * Copyright 2004 MontaVista Software Inc. - * Author: Manish Lachwani (mlachwani@mvista.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Based on linux/arch/mips/pci/ops-tx4938.c, + * linux/arch/mips/pci/fixup-rbtx4938.c, + * linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * 2003-2005 (c) MontaVista Software, Inc. + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. */ -#include -#include #include -#include -#include - -/* initialize in setup */ -struct resource pci_io_resource = { - .name = "TX4927 PCI IO SPACE", - .start = 0x1000, - .end = (0x1000 + (TX4927_PCIIO_SIZE)) - 1, - .flags = IORESOURCE_IO -}; +#include -/* initialize in setup */ -struct resource pci_mem_resource = { - .name = "TX4927 PCI MEM SPACE", - .start = TX4927_PCIMEM, - .end = TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; +static struct { + struct pci_controller *channel; + struct tx4927_pcic_reg __iomem *pcicptr; +} pcicptrs[2]; /* TX4938 has 2 pcic */ + +static void __init set_tx4927_pcicptr(struct pci_controller *channel, + struct tx4927_pcic_reg __iomem *pcicptr) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (pcicptrs[i].channel == channel) { + pcicptrs[i].pcicptr = pcicptr; + return; + } + } + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (!pcicptrs[i].channel) { + pcicptrs[i].channel = channel; + pcicptrs[i].pcicptr = pcicptr; + return; + } + } + BUG(); +} -static int mkaddr(int bus, int dev_fn, int where, int *flagsp) +struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( + struct pci_controller *channel) { - if (bus > 0) { - /* Type 1 configuration */ - tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; - } else { - if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) - return -1; + int i; - /* Type 0 configuration */ - tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc); + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (pcicptrs[i].channel == channel) + return pcicptrs[i].pcicptr; } + return NULL; +} + +static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where, + struct tx4927_pcic_reg __iomem *pcicptr) +{ + if (bus->parent == NULL && + devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) + return -1; + __raw_writel(((bus->number & 0xff) << 0x10) + | ((devfn & 0xff) << 0x08) | (where & 0xfc) + | (bus->parent ? 1 : 0), + &pcicptr->g2pcfgadrs); /* clear M_ABORT and Disable M_ABORT Int. */ - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr->pcistatus & 0x0000ffff) | - (PCI_STATUS_REC_MASTER_ABORT << 16); - tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; + __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) + | (PCI_STATUS_REC_MASTER_ABORT << 16), + &pcicptr->pcistatus); return 0; } -static int check_abort(int flags) +static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr) { int code = PCIBIOS_SUCCESSFUL; - if (tx4927_pcicptr-> - pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr-> - pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT - << 16); - tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; + + /* wait write cycle completion before checking error status */ + while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) + ; + if (__raw_readl(&pcicptr->pcistatus) + & (PCI_STATUS_REC_MASTER_ABORT << 16)) { + __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) + | (PCI_STATUS_REC_MASTER_ABORT << 16), + &pcicptr->pcistatus); code = PCIBIOS_DEVICE_NOT_FOUND; } return code; } -static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 * val) +static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 3; +#endif + return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 2; +#endif + return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr) +{ + return __raw_readl(&pcicptr->g2pcfgdata); +} +static void icd_writeb(u8 val, int offset, + struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 3; +#endif + __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static void icd_writew(u16 val, int offset, + struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 2; +#endif + __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr) { - int flags, retval, dev, busno, func; + __raw_writel(val, &pcicptr->g2pcfgdata); +} - busno = bus->number; - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); +static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus) +{ + struct pci_controller *channel = bus->sysdata; + return get_tx4927_pcicptr(channel); +} - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busno = bus->number; - } else { - busno = 0; - } +static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); - if (mkaddr(busno, devfn, where, &flags)) + if (mkaddr(bus, devfn, where, pcicptr)) { + *val = 0xffffffff; return -1; - + } switch (size) { case 1: - *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)); -#else - ((where & 0x3) ^ 0x3)); -#endif + *val = icd_readb(where & 3, pcicptr); break; case 2: - *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)); -#else - ((where & 0x3) ^ 0x2)); -#endif - break; - case 4: - *val = tx4927_pcicptr->g2pcfgdata; + *val = icd_readw(where & 3, pcicptr); break; + default: + *val = icd_readl(pcicptr); } + return check_abort(pcicptr); +} - retval = check_abort(flags); - if (retval == PCIBIOS_DEVICE_NOT_FOUND) - *val = 0xffffffff; +static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); - return retval; + if (mkaddr(bus, devfn, where, pcicptr)) + return -1; + switch (size) { + case 1: + icd_writeb(val, where & 3, pcicptr); + break; + case 2: + icd_writew(val, where & 3, pcicptr); + break; + default: + icd_writel(val, pcicptr); + } + return check_abort(pcicptr); } -static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) +static struct pci_ops tx4927_pci_ops = { + .read = tx4927_pci_config_read, + .write = tx4927_pci_config_write, +}; + +static struct { + u8 trdyto; + u8 retryto; + u16 gbwc; +} tx4927_pci_opts __devinitdata = { + .trdyto = 0, + .retryto = 0, + .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ +}; + +void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, + struct pci_controller *channel, int extarb) { - int flags, dev, busno, func; - busno = bus->number; - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); + int i; + unsigned long flags; - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busno = bus->number; - } else { - busno = 0; - } + set_tx4927_pcicptr(channel, pcicptr); - if (mkaddr(busno, devfn, where, &flags)) - return -1; + if (!channel->pci_ops) + printk(KERN_INFO + "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + __raw_readl(&pcicptr->pciid) >> 16, + __raw_readl(&pcicptr->pciid) & 0xffff, + __raw_readl(&pcicptr->pciccrev) & 0xff, + extarb ? "External" : "Internal"); + channel->pci_ops = &tx4927_pci_ops; - switch (size) { - case 1: - *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)) = val; + local_irq_save(flags); + + /* Disable All Initiator Space */ + __raw_writel(__raw_readl(&pcicptr->pciccfg) + & ~(TX4927_PCIC_PCICCFG_G2PMEN(0) + | TX4927_PCIC_PCICCFG_G2PMEN(1) + | TX4927_PCIC_PCICCFG_G2PMEN(2) + | TX4927_PCIC_PCICCFG_G2PIOEN), + &pcicptr->pciccfg); + + /* GB->PCI mappings */ + __raw_writel((channel->io_resource->end - channel->io_resource->start) + >> 4, + &pcicptr->g2piomask); + ____raw_writeq((channel->io_resource->start + + channel->io_map_base - IO_BASE) | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PIOGBASE_ECHG #else - ((where & 0x3) ^ 0x3)) = val; + TX4927_PCIC_G2PIOGBASE_BSDIS #endif - break; - - case 2: - *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)) = val; + , &pcicptr->g2piogbase); + ____raw_writeq(channel->io_resource->start - channel->io_offset, + &pcicptr->g2piopbase); + for (i = 0; i < 3; i++) { + __raw_writel(0, &pcicptr->g2pmmask[i]); + ____raw_writeq(0, &pcicptr->g2pmgbase[i]); + ____raw_writeq(0, &pcicptr->g2pmpbase[i]); + } + if (channel->mem_resource->end) { + __raw_writel((channel->mem_resource->end + - channel->mem_resource->start) >> 4, + &pcicptr->g2pmmask[0]); + ____raw_writeq(channel->mem_resource->start | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PMnGBASE_ECHG #else - ((where & 0x3) ^ 0x2)) = val; + TX4927_PCIC_G2PMnGBASE_BSDIS #endif - break; - case 4: - tx4927_pcicptr->g2pcfgdata = val; - break; + , &pcicptr->g2pmgbase[0]); + ____raw_writeq(channel->mem_resource->start - + channel->mem_offset, + &pcicptr->g2pmpbase[0]); + } + /* PCI->GB mappings (I/O 256B) */ + __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ + ____raw_writeq(0, &pcicptr->p2giogbase); + /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ + __raw_writel(0, &pcicptr->p2gm0plbase); + __raw_writel(0, &pcicptr->p2gm0pubase); + ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4927_PCIC_P2GMnGBASE_TECHG +#else + TX4927_PCIC_P2GMnGBASE_TBSDIS +#endif + , &pcicptr->p2gmgbase[0]); + /* PCI->GB mappings (MEM 16MB) */ + __raw_writel(0xffffffff, &pcicptr->p2gm1plbase); + __raw_writel(0xffffffff, &pcicptr->p2gm1pubase); + ____raw_writeq(0, &pcicptr->p2gmgbase[1]); + /* PCI->GB mappings (MEM 1MB) */ + __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */ + ____raw_writeq(0, &pcicptr->p2gmgbase[2]); + + /* Clear all (including IRBER) except for GBWC */ + __raw_writel((tx4927_pci_opts.gbwc << 16) + & TX4927_PCIC_PCICCFG_GBWC_MASK, + &pcicptr->pciccfg); + /* Enable Initiator Memory Space */ + if (channel->mem_resource->end) + __raw_writel(__raw_readl(&pcicptr->pciccfg) + | TX4927_PCIC_PCICCFG_G2PMEN(0), + &pcicptr->pciccfg); + /* Enable Initiator I/O Space */ + if (channel->io_resource->end) + __raw_writel(__raw_readl(&pcicptr->pciccfg) + | TX4927_PCIC_PCICCFG_G2PIOEN, + &pcicptr->pciccfg); + /* Enable Initiator Config */ + __raw_writel(__raw_readl(&pcicptr->pciccfg) + | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR, + &pcicptr->pciccfg); + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + __raw_writel(0, &pcicptr->pcicfg1); + + __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff) + | (tx4927_pci_opts.trdyto & 0xff) + | ((tx4927_pci_opts.retryto & 0xff) << 8), + &pcicptr->g2ptocnt); + + /* Clear All Local Bus Status */ + __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); + /* Enable All Local Bus Interrupts */ + __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask); + /* Clear All Initiator Status */ + __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); + /* Enable All Initiator Interrupts */ + __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask); + /* Clear All PCI Status Error */ + __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) + | (TX4927_PCIC_PCISTATUS_ALL << 16), + &pcicptr->pcistatus); + /* Enable All PCI Status Error Interrupts */ + __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask); + + if (!extarb) { + /* Reset Bus Arbiter */ + __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); + __raw_writel(0, &pcicptr->pbabm); + /* Enable Bus Arbiter */ + __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg); } - return check_abort(flags); + __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY + | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, + &pcicptr->pcistatus); + local_irq_restore(flags); + + printk(KERN_DEBUG + "PCI: COMMAND=%04x,PCIMASK=%04x," + "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n", + __raw_readl(&pcicptr->pcistatus) & 0xffff, + __raw_readl(&pcicptr->pcimask) & 0xffff, + __raw_readl(&pcicptr->g2ptocnt) & 0xff, + (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8, + (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff); } -struct pci_ops tx4927_pci_ops = { - tx4927_pcibios_read_config, - tx4927_pcibios_write_config -}; +static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr) +{ + __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16); + __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus); + __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus); + static struct { + __u32 flag; + const char *str; + } pcistat_tbl[] = { + { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, + { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, + { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, + { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, + { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, + { PCI_STATUS_PARITY, "MasterParityError" }, + }, g2pstat_tbl[] = { + { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" }, + { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" }, + }, pcicstat_tbl[] = { + { TX4927_PCIC_PCICSTATUS_PME, "PME" }, + { TX4927_PCIC_PCICSTATUS_TLB, "TLB" }, + { TX4927_PCIC_PCICSTATUS_NIB, "NIB" }, + { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" }, + { TX4927_PCIC_PCICSTATUS_PERR, "PERR" }, + { TX4927_PCIC_PCICSTATUS_SERR, "SERR" }, + { TX4927_PCIC_PCICSTATUS_GBE, "GBE" }, + { TX4927_PCIC_PCICSTATUS_IWB, "IWB" }, + }; + int i, cont; -/* - * h/w only supports devices 0x00 to 0x14 - */ -struct pci_controller tx4927_controller = { - .pci_ops = &tx4927_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, -}; + printk(KERN_ERR ""); + if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) { + printk(KERN_CONT "pcistat:%04x(", pcistatus); + for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++) + if (pcistatus & pcistat_tbl[i].flag) + printk(KERN_CONT "%s%s", + cont++ ? " " : "", pcistat_tbl[i].str); + printk(KERN_CONT ") "); + } + if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) { + printk(KERN_CONT "g2pstatus:%08x(", g2pstatus); + for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) + if (g2pstatus & g2pstat_tbl[i].flag) + printk(KERN_CONT "%s%s", + cont++ ? " " : "", g2pstat_tbl[i].str); + printk(KERN_CONT ") "); + } + if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) { + printk(KERN_CONT "pcicstatus:%08x(", pcicstatus); + for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) + if (pcicstatus & pcicstat_tbl[i].flag) + printk(KERN_CONT "%s%s", + cont++ ? " " : "", pcicstat_tbl[i].str); + printk(KERN_CONT ")"); + } + printk(KERN_CONT "\n"); +} + +void tx4927_report_pcic_status(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (pcicptrs[i].pcicptr) + tx4927_report_pcic_status1(pcicptrs[i].pcicptr); + } +} diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c deleted file mode 100644 index 34494b82cb22..000000000000 --- a/arch/mips/pci/ops-tx4938.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Define the pci_ops for the Toshiba rbtx4938 - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include - -#include -#include - -/* initialize in setup */ -struct resource pci_io_resource = { - .name = "pci IO space", - .start = 0, - .end = 0, - .flags = IORESOURCE_IO -}; - -/* initialize in setup */ -struct resource pci_mem_resource = { - .name = "pci memory space", - .start = 0, - .end = 0, - .flags = IORESOURCE_MEM -}; - -struct resource tx4938_pcic1_pci_io_resource = { - .name = "PCI1 IO", - .start = 0, - .end = 0, - .flags = IORESOURCE_IO -}; -struct resource tx4938_pcic1_pci_mem_resource = { - .name = "PCI1 mem", - .start = 0, - .end = 0, - .flags = IORESOURCE_MEM -}; - -static int mkaddr(int bus, int dev_fn, int where, - struct tx4938_pcic_reg *pcicptr) -{ - if (bus > 0) { - /* Type 1 configuration */ - pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; - } else { - if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0)) - return -1; - - /* Type 0 configuration */ - pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc); - } - /* clear M_ABORT and Disable M_ABORT Int. */ - pcicptr->pcistatus = - (pcicptr->pcistatus & 0x0000ffff) | - (PCI_STATUS_REC_MASTER_ABORT << 16); - pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; - - return 0; -} - -static int check_abort(struct tx4938_pcic_reg *pcicptr) -{ - int code = PCIBIOS_SUCCESSFUL; - /* wait write cycle completion before checking error status */ - while (pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB) - ; - if (pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { - pcicptr->pcistatus = - (pcicptr-> - pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT - << 16); - pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; - code = PCIBIOS_DEVICE_NOT_FOUND; - } - return code; -} - -extern struct pci_controller tx4938_pci_controller[]; -extern struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch); - -static struct tx4938_pcic_reg *pci_bus_to_pcicptr(struct pci_bus *bus) -{ - struct pci_controller *channel = bus->sysdata; - return get_tx4938_pcicptr(channel - &tx4938_pci_controller[0]); -} - -static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - int retval, dev, busno, func; - struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus); - void __iomem *cfgdata = - (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata; - - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); - - /* check if the bus is top-level */ - if (bus->parent != NULL) - busno = bus->number; - else { - busno = 0; - } - - if (mkaddr(busno, devfn, where, pcicptr)) - return -1; - - switch (size) { - case 1: -#ifdef __BIG_ENDIAN - cfgdata += (where & 3) ^ 3; -#else - cfgdata += where & 3; -#endif - *val = __raw_readb(cfgdata); - break; - case 2: -#ifdef __BIG_ENDIAN - cfgdata += (where & 2) ^ 2; -#else - cfgdata += where & 2; -#endif - *val = __raw_readw(cfgdata); - break; - case 4: - *val = __raw_readl(cfgdata); - break; - } - - retval = check_abort(pcicptr); - if (retval == PCIBIOS_DEVICE_NOT_FOUND) - *val = 0xffffffff; - - return retval; -} - -static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - int dev, busno, func; - struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus); - void __iomem *cfgdata = - (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata; - - busno = bus->number; - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); - - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busno = bus->number; - } else { - busno = 0; - } - - if (mkaddr(busno, devfn, where, pcicptr)) - return -1; - - switch (size) { - case 1: -#ifdef __BIG_ENDIAN - cfgdata += (where & 3) ^ 3; -#else - cfgdata += where & 3; -#endif - __raw_writeb(val, cfgdata); - break; - case 2: -#ifdef __BIG_ENDIAN - cfgdata += (where & 2) ^ 2; -#else - cfgdata += where & 2; -#endif - __raw_writew(val, cfgdata); - break; - case 4: - __raw_writel(val, cfgdata); - break; - } - - return check_abort(pcicptr); -} - -struct pci_ops tx4938_pci_ops = { - tx4938_pcibios_read_config, - tx4938_pcibios_write_config -}; - -struct pci_controller tx4938_pci_controller[] = { - /* h/w only supports devices 0x00 to 0x14 */ - { - .pci_ops = &tx4938_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, - }, - /* h/w only supports devices 0x00 to 0x14 */ - { - .pci_ops = &tx4938_pci_ops, - .io_resource = &tx4938_pcic1_pci_io_resource, - .mem_resource = &tx4938_pcic1_pci_mem_resource, - } -}; diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c deleted file mode 100644 index 7fb6bd71901a..000000000000 --- a/arch/mips/pci/pci-jmr3927.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include - -struct resource pci_io_resource = { - .name = "IO MEM", - .start = 0x1000, /* reserve regacy I/O space */ - .end = 0x1000 + JMR3927_PCIIO_SIZE - 1, - .flags = IORESOURCE_IO -}; - -struct resource pci_mem_resource = { - .name = "PCI MEM", - .start = JMR3927_PCIMEM, - .end = JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops jmr3927_pci_ops; - -struct pci_controller jmr3927_controller = { - .pci_ops = &jmr3927_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, - .mem_offset = JMR3927_PCIMEM -}; diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c new file mode 100644 index 000000000000..27e86a09dd41 --- /dev/null +++ b/arch/mips/pci/pci-tx4927.c @@ -0,0 +1,83 @@ +/* + * linux/arch/mips/pci/pci-tx4927.c + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * Copyright 2001, 2003-2005 MontaVista Software Inc. + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +int __init tx4927_report_pciclk(void) +{ + int pciclk = 0; + + printk(KERN_INFO "PCIC --%s PCICLK:", + (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ? + " PCI66" : ""); + if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) { + u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg); + switch ((unsigned long)ccfg & + TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + pciclk = txx9_cpu_clock * 2 / 5; break; + case TX4927_CCFG_PCIDIVMODE_3: + pciclk = txx9_cpu_clock / 3; break; + case TX4927_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4927_CCFG_PCIDIVMODE_6: + pciclk = txx9_cpu_clock / 6; break; + } + printk("Internal(%u.%uMHz)", + (pciclk + 50000) / 1000000, + ((pciclk + 50000) / 100000) % 10); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +int __init tx4927_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4927_ccfg_set(TX4927_CCFG_PCI66); + /* Double PCICLK (if possible) */ + if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = 0; + u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg); + pcidivmode = (unsigned long)ccfg & + TX4927_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4927_CCFG_PCIDIVMODE_5: + case TX4927_CCFG_PCIDIVMODE_2_5: + pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5; + pciclk = txx9_cpu_clock * 2 / 5; + break; + case TX4927_CCFG_PCIDIVMODE_6: + case TX4927_CCFG_PCIDIVMODE_3: + default: + pcidivmode = TX4927_CCFG_PCIDIVMODE_3; + pciclk = txx9_cpu_clock / 3; + } + tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK, + pcidivmode); + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg)); + } else + pciclk = -1; + return pciclk; +} diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c new file mode 100644 index 000000000000..e5375511c2b7 --- /dev/null +++ b/arch/mips/pci/pci-tx4938.c @@ -0,0 +1,134 @@ +/* + * linux/arch/mips/pci/pci-tx4938.c + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * Copyright 2001, 2003-2005 MontaVista Software Inc. + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +int __init tx4938_report_pciclk(void) +{ + int pciclk = 0; + + printk(KERN_INFO "PCIC --%s PCICLK:", + (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ? + " PCI66" : ""); + if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) { + u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); + switch ((unsigned long)ccfg & + TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_4: + pciclk = txx9_cpu_clock / 4; break; + case TX4938_CCFG_PCIDIVMODE_4_5: + pciclk = txx9_cpu_clock * 2 / 9; break; + case TX4938_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4938_CCFG_PCIDIVMODE_5_5: + pciclk = txx9_cpu_clock * 2 / 11; break; + case TX4938_CCFG_PCIDIVMODE_8: + pciclk = txx9_cpu_clock / 8; break; + case TX4938_CCFG_PCIDIVMODE_9: + pciclk = txx9_cpu_clock / 9; break; + case TX4938_CCFG_PCIDIVMODE_10: + pciclk = txx9_cpu_clock / 10; break; + case TX4938_CCFG_PCIDIVMODE_11: + pciclk = txx9_cpu_clock / 11; break; + } + printk("Internal(%u.%uMHz)", + (pciclk + 50000) / 1000000, + ((pciclk + 50000) / 100000) % 10); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +void __init tx4938_report_pci1clk(void) +{ + __u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); + unsigned int pciclk = + txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2); + + printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n", + (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "", + (pciclk + 50000) / 1000000, + ((pciclk + 50000) / 100000) % 10); +} + +int __init tx4938_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4938_ccfg_set(TX4938_CCFG_PCI66); + /* Double PCICLK (if possible) */ + if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = 0; + u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); + pcidivmode = (unsigned long)ccfg & + TX4938_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4; + pciclk = txx9_cpu_clock / 4; + break; + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; + pciclk = txx9_cpu_clock * 2 / 9; + break; + case TX4938_CCFG_PCIDIVMODE_10: + case TX4938_CCFG_PCIDIVMODE_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5; + pciclk = txx9_cpu_clock / 5; + break; + case TX4938_CCFG_PCIDIVMODE_11: + case TX4938_CCFG_PCIDIVMODE_5_5: + default: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; + pciclk = txx9_cpu_clock * 2 / 11; + break; + } + tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK, + pcidivmode); + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg)); + } else + pciclk = -1; + return pciclk; +} + +int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot) +{ + if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) { + switch (slot) { + case TX4927_PCIC_IDSEL_AD_TO_SLOT(31): + if (__raw_readq(&tx4938_ccfgptr->pcfg) & + TX4938_PCFG_ETH0_SEL) + return TXX9_IRQ_BASE + TX4938_IR_ETH0; + break; + case TX4927_PCIC_IDSEL_AD_TO_SLOT(30): + if (__raw_readq(&tx4938_ccfgptr->pcfg) & + TX4938_PCFG_ETH1_SEL) + return TXX9_IRQ_BASE + TX4938_IR_ETH1; + break; + } + return 0; + } + return -1; +} diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig index 98d103402b10..b8cdb192543a 100644 --- a/arch/mips/txx9/Kconfig +++ b/arch/mips/txx9/Kconfig @@ -1,6 +1,12 @@ config TOSHIBA_FPCIB0 bool "FPCIB0 Backplane Support" - depends on TOSHIBA_RBTX4927 + depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + select I8259 + +config PICMG_PCI_BACKPLANE_DEFAULT + bool "Support for PICMG PCI Backplane" + depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + default y if !TOSHIBA_FPCIB0 if TOSHIBA_RBTX4938 @@ -26,3 +32,6 @@ config TX4938_NAND_BOOT Select this option if you need to use NAND boot. endif + +config PCI_TX4927 + bool diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile index 8cb4a7e81473..b80b6e072284 100644 --- a/arch/mips/txx9/generic/Makefile +++ b/arch/mips/txx9/generic/Makefile @@ -2,6 +2,8 @@ # Makefile for common code for TXx9 based systems # +obj-y += setup.o +obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c new file mode 100644 index 000000000000..8173faab99bb --- /dev/null +++ b/arch/mips/txx9/generic/pci.c @@ -0,0 +1,377 @@ +/* + * linux/arch/mips/txx9/pci.c + * + * Based on linux/arch/mips/txx9/rbtx4927/setup.c, + * linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * Copyright 2001-2005 MontaVista Software Inc. + * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#include +#include +#endif + +static int __init +early_read_config_word(struct pci_controller *hose, + int top_bus, int bus, int devfn, int offset, u16 *value) +{ + struct pci_dev fake_dev; + struct pci_bus fake_bus; + + fake_dev.bus = &fake_bus; + fake_dev.sysdata = hose; + fake_dev.devfn = devfn; + fake_bus.number = bus; + fake_bus.sysdata = hose; + fake_bus.ops = hose->pci_ops; + + if (bus != top_bus) + /* Fake a parent bus structure. */ + fake_bus.parent = &fake_bus; + else + fake_bus.parent = NULL; + + return pci_read_config_word(&fake_dev, offset, value); +} + +int __init txx9_pci66_check(struct pci_controller *hose, int top_bus, + int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int cap66 = -1; + u16 stat; + + /* It seems SLC90E66 needs some time after PCI reset... */ + mdelay(80); + + printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { + if (PCI_FUNC(pci_devfn)) + continue; + if (early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_VENDOR_ID, &vid) != + PCIBIOS_SUCCESSFUL) + continue; + if (vid == 0xffff) + continue; + + /* check 66MHz capability */ + if (cap66 < 0) + cap66 = 1; + if (cap66) { + early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_STATUS, &stat); + if (!(stat & PCI_STATUS_66MHZ)) { + printk(KERN_DEBUG + "PCI: %02x:%02x not 66MHz capable.\n", + current_bus, pci_devfn); + cap66 = 0; + break; + } + } + } + return cap66 > 0; +} + +static struct resource primary_pci_mem_res[2] = { + { .name = "PCI MEM" }, + { .name = "PCI MMIO" }, +}; +static struct resource primary_pci_io_res = { .name = "PCI IO" }; +struct pci_controller txx9_primary_pcic = { + .mem_resource = &primary_pci_mem_res[0], + .io_resource = &primary_pci_io_res, +}; + +#ifdef CONFIG_64BIT +int txx9_pci_mem_high __initdata = 1; +#else +int txx9_pci_mem_high __initdata; +#endif + +/* + * allocate pci_controller and resources. + * mem_base, io_base: physical addresss. 0 for auto assignment. + * mem_size and io_size means max size on auto assignment. + * pcic must be &txx9_primary_pcic or NULL. + */ +struct pci_controller *__init +txx9_alloc_pci_controller(struct pci_controller *pcic, + unsigned long mem_base, unsigned long mem_size, + unsigned long io_base, unsigned long io_size) +{ + struct pcic { + struct pci_controller c; + struct resource r_mem[2]; + struct resource r_io; + } *new = NULL; + int min_size = 0x10000; + + if (!pcic) { + new = kzalloc(sizeof(*new), GFP_KERNEL); + if (!new) + return NULL; + new->r_mem[0].name = "PCI mem"; + new->r_mem[1].name = "PCI mmio"; + new->r_io.name = "PCI io"; + new->c.mem_resource = new->r_mem; + new->c.io_resource = &new->r_io; + pcic = &new->c; + } else + BUG_ON(pcic != &txx9_primary_pcic); + pcic->io_resource->flags = IORESOURCE_IO; + + /* + * for auto assignment, first search a (big) region for PCI + * MEM, then search a region for PCI IO. + */ + if (mem_base) { + pcic->mem_resource[0].start = mem_base; + pcic->mem_resource[0].end = mem_base + mem_size - 1; + if (request_resource(&iomem_resource, &pcic->mem_resource[0])) + goto free_and_exit; + } else { + unsigned long min = 0, max = 0x20000000; /* low 512MB */ + if (!mem_size) { + /* default size for auto assignment */ + if (txx9_pci_mem_high) + mem_size = 0x20000000; /* mem:512M(max) */ + else + mem_size = 0x08000000; /* mem:128M(max) */ + } + if (txx9_pci_mem_high) { + min = 0x20000000; + max = 0xe0000000; + } + /* search free region for PCI MEM */ + for (; mem_size >= min_size; mem_size /= 2) { + if (allocate_resource(&iomem_resource, + &pcic->mem_resource[0], + mem_size, min, max, + mem_size, NULL, NULL) == 0) + break; + } + if (mem_size < min_size) + goto free_and_exit; + } + + pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY; + if (io_base) { + pcic->mem_resource[1].start = io_base; + pcic->mem_resource[1].end = io_base + io_size - 1; + if (request_resource(&iomem_resource, &pcic->mem_resource[1])) + goto release_and_exit; + } else { + if (!io_size) + /* default size for auto assignment */ + io_size = 0x01000000; /* io:16M(max) */ + /* search free region for PCI IO in low 512MB */ + for (; io_size >= min_size; io_size /= 2) { + if (allocate_resource(&iomem_resource, + &pcic->mem_resource[1], + io_size, 0, 0x20000000, + io_size, NULL, NULL) == 0) + break; + } + if (io_size < min_size) + goto release_and_exit; + io_base = pcic->mem_resource[1].start; + } + + pcic->mem_resource[0].flags = IORESOURCE_MEM; + if (pcic == &txx9_primary_pcic && + mips_io_port_base == (unsigned long)-1) { + /* map ioport 0 to PCI I/O space address 0 */ + set_io_port_base(IO_BASE + pcic->mem_resource[1].start); + pcic->io_resource->start = 0; + pcic->io_offset = 0; /* busaddr == ioaddr */ + pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start; + } else { + /* physaddr to ioaddr */ + pcic->io_resource->start = + io_base - (mips_io_port_base - IO_BASE); + pcic->io_offset = io_base - (mips_io_port_base - IO_BASE); + pcic->io_map_base = mips_io_port_base; + } + pcic->io_resource->end = pcic->io_resource->start + io_size - 1; + + pcic->mem_offset = 0; /* busaddr == physaddr */ + + printk(KERN_INFO "PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n", + (unsigned long long)pcic->mem_resource[1].start, + (unsigned long long)pcic->mem_resource[1].end, + (unsigned long long)pcic->mem_resource[0].start, + (unsigned long long)pcic->mem_resource[0].end); + + /* register_pci_controller() will request MEM resource */ + release_resource(&pcic->mem_resource[0]); + return pcic; + release_and_exit: + release_resource(&pcic->mem_resource[0]); + free_and_exit: + kfree(new); + printk(KERN_ERR "PCI: Failed to allocate resources.\n"); + return NULL; +} + +static int __init +txx9_arch_pci_init(void) +{ + PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */ + return 0; +} +arch_initcall(txx9_arch_pci_init); + +/* IRQ/IDSEL mapping */ +int txx9_pci_option = +#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT + TXX9_PCI_OPT_PICMG | +#endif + TXX9_PCI_OPT_CLK_AUTO; + +enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT; + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static irqreturn_t i8259_interrupt(int irq, void *dev_id) +{ + int isairq; + + isairq = i8259_irq(); + if (unlikely(isairq <= I8259A_IRQ_BASE)) + return IRQ_NONE; + generic_handle_irq(isairq); + return IRQ_HANDLED; +} + +static int __init +txx9_i8259_irq_setup(int irq) +{ + int err; + + init_i8259_irqs(); + err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED, + "cascade(i8259)", (void *)(long)irq); + if (!err) + printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq); + return err; +} + +static void __init quirk_slc90e66_bridge(struct pci_dev *dev) +{ + int irq; /* PCI/ISA Bridge interrupt */ + u8 reg_64; + u32 reg_b0; + u8 reg_e1; + irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */ + if (!irq) + return; + txx9_i8259_irq_setup(irq); + pci_read_config_byte(dev, 0x64, ®_64); + pci_read_config_dword(dev, 0xb0, ®_b0); + pci_read_config_byte(dev, 0xe1, ®_e1); + /* serial irq control */ + reg_64 = 0xd0; + /* serial irq pin */ + reg_b0 |= 0x00010000; + /* ide irq on isa14 */ + reg_e1 &= 0xf0; + reg_e1 |= 0x0d; + pci_write_config_byte(dev, 0x64, reg_64); + pci_write_config_dword(dev, 0xb0, reg_b0); + pci_write_config_byte(dev, 0xe1, reg_e1); + + smsc_fdc37m81x_init(0x3f0); + smsc_fdc37m81x_config_beg(); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + smsc_fdc37m81x_config_end(); +} + +static void quirk_slc90e66_ide(struct pci_dev *dev) +{ + unsigned char dat; + int regs[2] = {0x41, 0x43}; + int i; + + /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14); + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat); + printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat); + /* enable SMSC SLC90E66 IDE */ + for (i = 0; i < ARRAY_SIZE(regs); i++) { + pci_read_config_byte(dev, regs[i], &dat); + pci_write_config_byte(dev, regs[i], dat | 0x80); + pci_read_config_byte(dev, regs[i], &dat); + printk(KERN_CONT " IDETIM%d %02x", i, dat); + } + pci_read_config_byte(dev, 0x5c, &dat); + /* + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + * + * This line of code is intended to provide the user with a work + * around solution to the anomalies cited in SMSC's anomaly sheet + * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". + * + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + */ + dat |= 0x01; + pci_write_config_byte(dev, regs[i], dat); + pci_read_config_byte(dev, 0x5c, &dat); + printk(KERN_CONT " REG5C %02x", dat); + printk(KERN_CONT "\n"); +} +#endif /* CONFIG_TOSHIBA_FPCIB0 */ + +static void final_fixup(struct pci_dev *dev) +{ + unsigned char bist; + + /* Do build-in self test */ + if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL && + (bist & PCI_BIST_CAPABLE)) { + unsigned long timeout; + pci_set_power_state(dev, PCI_D0); + printk(KERN_INFO "PCI: %s BIST...", pci_name(dev)); + pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START); + timeout = jiffies + HZ * 2; /* timeout after 2 sec */ + do { + pci_read_config_byte(dev, PCI_BIST, &bist); + if (time_after(jiffies, timeout)) + break; + } while (bist & PCI_BIST_START); + if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START)) + printk(KERN_CONT "failed. (0x%x)\n", bist); + else + printk(KERN_CONT "OK.\n"); + } +} + +#ifdef CONFIG_TOSHIBA_FPCIB0 +#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0, + quirk_slc90e66_bridge); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, + quirk_slc90e66_ide); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, + quirk_slc90e66_ide); +#endif +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup); +DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup); diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c new file mode 100644 index 000000000000..46a631177757 --- /dev/null +++ b/arch/mips/txx9/generic/setup.c @@ -0,0 +1,51 @@ +/* + * linux/arch/mips/txx9/generic/setup.c + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * 2003-2005 (c) MontaVista Software, Inc. + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include + +/* EBUSC settings of TX4927, etc. */ +struct resource txx9_ce_res[8]; +static char txx9_ce_res_name[8][4]; /* "CEn" */ + +/* pcode, internal register */ +char txx9_pcode_str[8]; +static struct resource txx9_reg_res = { + .name = txx9_pcode_str, + .flags = IORESOURCE_MEM, +}; +void __init +txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) { + sprintf(txx9_ce_res_name[i], "CE%d", i); + txx9_ce_res[i].flags = IORESOURCE_MEM; + txx9_ce_res[i].name = txx9_ce_res_name[i]; + } + + sprintf(txx9_pcode_str, "TX%x", pcode); + if (base) { + txx9_reg_res.start = base & 0xfffffffffULL; + txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1); + request_resource(&iomem_resource, &txx9_reg_res); + } +} + +/* clocks */ +unsigned int txx9_master_clock; +unsigned int txx9_cpu_clock; +unsigned int txx9_gbus_clock; diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c index 85e1daf15c7b..b97d22e15da6 100644 --- a/arch/mips/txx9/jmr3927/irq.c +++ b/arch/mips/txx9/jmr3927/irq.c @@ -109,6 +109,7 @@ static struct irqaction ioc_action = { .name = "IOC", }; +#ifdef CONFIG_PCI static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) { printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); @@ -122,6 +123,7 @@ static struct irqaction pcierr_action = { .mask = CPU_MASK_NONE, .name = "PCI error", }; +#endif static void __init jmr3927_irq_init(void); diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 41e0f3b3af2c..baa8c8db9a94 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -44,6 +43,7 @@ #include #include #include +#include #include #include @@ -96,8 +96,6 @@ void __init plat_time_init(void) extern char * __init prom_getcmdline(void); static void jmr3927_board_init(void); -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; void __init plat_mem_setup(void) { @@ -112,8 +110,8 @@ void __init plat_mem_setup(void) /* * IO/MEM resources. */ - ioport_resource.start = pci_io_resource.start; - ioport_resource.end = pci_io_resource.end; + ioport_resource.start = 0; + ioport_resource.end = 0xffffffff; iomem_resource.start = 0; iomem_resource.end = 0xffffffff; @@ -191,9 +189,33 @@ void __init plat_mem_setup(void) static void tx3927_setup(void); +static void __init jmr3927_pci_setup(void) +{ +#ifdef CONFIG_PCI + int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB); + struct pci_controller *c; + + c = txx9_alloc_pci_controller(&txx9_primary_pcic, + JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE, + JMR3927_PCIIO, JMR3927_PCIIO_SIZE); + register_pci_controller(c); + if (!extarb) { + /* Reset PCI Bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, + JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + } + tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb); +#endif /* CONFIG_PCI */ +} + static void __init jmr3927_board_init(void) { tx3927_setup(); + jmr3927_pci_setup(); /* SIO0 DTR on */ jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); @@ -210,14 +232,6 @@ static void __init jmr3927_board_init(void) static void __init tx3927_setup(void) { int i; -#ifdef CONFIG_PCI - unsigned long mips_pci_io_base = JMR3927_PCIIO; - unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; - unsigned long mips_pci_mem_base = JMR3927_PCIMEM; - unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; - /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ - unsigned long mips_pci_io_pciaddr = 0; -#endif /* SDRAMC are configured by PROM */ @@ -272,74 +286,6 @@ static void __init tx3927_setup(void) tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; #endif -#ifdef CONFIG_PCI - /* PCIC */ - printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", - tx3927_pcicptr->did, tx3927_pcicptr->vid, - tx3927_pcicptr->rid); - if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { - printk("External\n"); - /* XXX */ - } else { - printk("Internal\n"); - - /* Reset PCI Bus */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, - JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - - - /* Disable External PCI Config. Access */ - tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; -#ifdef __BIG_ENDIAN - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | - TX3927_PCIC_LBC_TIBSE | - TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; -#endif - /* LB->PCI mappings */ - tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); - tx3927_pcicptr->ilbioma = mips_pci_io_base; - tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; - tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->ilbmma = mips_pci_mem_base; - tx3927_pcicptr->ipbmma = mips_pci_mem_base; - /* PCI->LB mappings */ - tx3927_pcicptr->iobas = 0xffffffff; - tx3927_pcicptr->ioba = 0; - tx3927_pcicptr->tlbioma = 0; - tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->mba = 0; - tx3927_pcicptr->tlbmma = 0; - /* Enable Direct mapping Address Space Decoder */ - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; - - /* Clear All Local Bus Status */ - tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; - /* Enable All Local Bus Interrupts */ - tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; - /* Clear All PCI Status Error */ - tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; - /* Enable All PCI Status Error Interrupts */ - tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; - - /* PCIC Int => IRC IRQ10 */ - tx3927_pcicptr->il = TX3927_IR_PCI; - /* Target Control (per errata) */ - tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; - - /* Enable Bus Arbiter */ - tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; - - tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - } -#endif /* CONFIG_PCI */ - /* PIO */ /* PIO[15:12] connected to LEDs */ __raw_writel(0x0000f000, &tx3927_pioptr->dir); diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c index 936e50e91d95..bef1447aeed2 100644 --- a/arch/mips/txx9/rbtx4927/irq.c +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -111,9 +111,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #include #include #include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif #include #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 @@ -125,8 +122,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) -extern int tx4927_using_backplane; - static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); @@ -146,17 +141,8 @@ int toshiba_rbtx4927_irq_nested(int sw_irq) u8 level3; level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; - if (level3) { + if (level3) sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && - tx4927_using_backplane) { - int irq = i8259_irq(); - if (irq >= 0) - sw_irq = irq; - } -#endif - } return (sw_irq); } @@ -205,10 +191,6 @@ void __init arch_init_irq(void) tx4927_irq_init(); toshiba_rbtx4927_irq_ioc_init(); -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) - init_i8259_irqs(); -#endif /* Onboard 10M Ether: High Active */ set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); } diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index df1b6e99b666..86b870abc319 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -47,10 +47,10 @@ #include #include #include -#include #include #include #include +#include #include #include @@ -58,10 +58,10 @@ #include #include #include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif +#include +#include #include +#include /* for TX4937 */ #ifdef CONFIG_SERIAL_TXX9 #include #endif @@ -70,356 +70,116 @@ extern void toshiba_rbtx4927_restart(char *command); extern void toshiba_rbtx4927_halt(void); extern void toshiba_rbtx4927_power_off(void); - -int tx4927_using_backplane = 0; - extern void toshiba_rbtx4927_irq_setup(void); char *prom_getcmdline(void); -#ifdef CONFIG_PCI -#undef TX4927_SUPPORT_COMMAND_IO -#undef TX4927_SUPPORT_PCI_66 -int tx4927_cpu_clock = 100000000; /* 100MHz */ -unsigned long mips_pci_io_base; -unsigned long mips_pci_io_size; -unsigned long mips_pci_mem_base; -unsigned long mips_pci_mem_size; -/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ -unsigned long mips_pci_io_pciaddr = 0; -unsigned long mips_memory_upper; static int tx4927_ccfg_toeon = 1; -static int tx4927_pcic_trdyto = 0; /* default: disabled */ -unsigned long tx4927_ce_base[8]; -int tx4927_pci66 = 0; /* 0:auto */ -#endif char *toshiba_name = ""; #ifdef CONFIG_PCI -extern struct pci_controller tx4927_controller; - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) +static void __init tx4927_pci_setup(void) { - static struct pci_dev dev; - static struct pci_bus bus; - - dev.sysdata = (void *)hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ + int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB); + struct pci_controller *c = &txx9_primary_pcic; + + register_pci_controller(c); + + if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) + txx9_pci_option = + (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | + TXX9_PCI_OPT_CLK_66; /* already configured */ + + /* Reset PCI Bus */ + writeb(1, rbtx4927_pcireset_addr); + /* Reset PCIC */ + txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_66) + tx4927_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + writeb(0, rbtx4927_pcireset_addr); + iob(); + + tx4927_report_pciclk(); + tx4927_pcic_setup(tx4927_pcicptr, c, extarb); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_AUTO && + txx9_pci66_check(c, 0, 0)) { + /* Reset PCI Bus */ + writeb(1, rbtx4927_pcireset_addr); + /* Reset PCIC */ + txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + tx4927_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + writeb(0, rbtx4927_pcireset_addr); + iob(); + /* Reinitialize PCIC */ + tx4927_report_pciclk(); + tx4927_pcic_setup(tx4927_pcicptr, c, extarb); + } } -EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, dword, u32) - -static int __init tx4927_pcibios_init(void) +static void __init tx4937_pci_setup(void) { - unsigned int id; - u32 pci_devfn; - int devfn_start = 0; - int devfn_stop = 0xff; - int busno = 0; /* One bus on the Toshiba */ - struct pci_controller *hose = &tx4927_controller; - - for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { - early_read_config_dword(hose, busno, busno, pci_devfn, - PCI_VENDOR_ID, &id); - - if (id == 0xffffffff) { - continue; - } - - if (id == 0x94601055) { - u8 v08_64; - u32 v32_b0; - u8 v08_e1; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x64, &v08_64); - early_read_config_dword(hose, busno, busno, - pci_devfn, 0xb0, &v32_b0); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0xe1, &v08_e1); - - /* serial irq control */ - v08_64 = 0xd0; - - /* serial irq pin */ - v32_b0 |= 0x00010000; - - /* ide irq on isa14 */ - v08_e1 &= 0xf0; - v08_e1 |= 0x0d; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x64, v08_64); - early_write_config_dword(hose, busno, busno, - pci_devfn, 0xb0, v32_b0); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0xe1, v08_e1); - } - - if (id == 0x91301055) { - u8 v08_04; - u8 v08_09; - u8 v08_41; - u8 v08_43; - u8 v08_5c; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x04, &v08_04); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x09, &v08_09); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x41, &v08_41); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x43, &v08_43); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x5c, &v08_5c); - - /* enable ide master/io */ - v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); - - /* enable ide native mode */ - v08_09 |= 0x05; - - /* enable primary ide */ - v08_41 |= 0x80; - - /* enable secondary ide */ - v08_43 |= 0x80; - - /* - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - * - * This line of code is intended to provide the user with a work - * around solution to the anomalies cited in SMSC's anomaly sheet - * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". - * - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - */ - v08_5c |= 0x01; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x5c, v08_5c); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x04, v08_04); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x09, v08_09); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x41, v08_41); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x43, v08_43); - } - + int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB); + struct pci_controller *c = &txx9_primary_pcic; + + register_pci_controller(c); + + if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) + txx9_pci_option = + (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | + TXX9_PCI_OPT_CLK_66; /* already configured */ + + /* Reset PCI Bus */ + writeb(1, rbtx4927_pcireset_addr); + /* Reset PCIC */ + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_66) + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + writeb(0, rbtx4927_pcireset_addr); + iob(); + + tx4938_report_pciclk(); + tx4927_pcic_setup(tx4938_pcicptr, c, extarb); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_AUTO && + txx9_pci66_check(c, 0, 0)) { + /* Reset PCI Bus */ + writeb(1, rbtx4927_pcireset_addr); + /* Reset PCIC */ + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + writeb(0, rbtx4927_pcireset_addr); + iob(); + /* Reinitialize PCIC */ + tx4938_report_pciclk(); + tx4927_pcic_setup(tx4938_pcicptr, c, extarb); } - - register_pci_controller(&tx4927_controller); - return 0; } -arch_initcall(tx4927_pcibios_init); - -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; - -void __init tx4927_pci_setup(void) +static int __init rbtx4927_arch_init(void) { - static int called = 0; - extern unsigned int tx4927_get_mem_size(void); - - mips_memory_upper = tx4927_get_mem_size() << 20; - mips_memory_upper += KSEG0; - mips_pci_io_base = TX4927_PCIIO; - mips_pci_io_size = TX4927_PCIIO_SIZE; - mips_pci_mem_base = TX4927_PCIMEM; - mips_pci_mem_size = TX4927_PCIMEM_SIZE; - - if (!called) { - printk - ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - toshiba_name, - (unsigned short) (tx4927_pcicptr->pciid >> 16), - (unsigned short) (tx4927_pcicptr->pciid & 0xffff), - (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), - (!(tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIXARB)) ? "External" : - "Internal"); - called = 1; - } - printk("%s PCIC --%s PCICLK:", toshiba_name, - (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); - if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { - int pciclk = 0; - if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_4: - pciclk = tx4927_cpu_clock / 4; - break; - case TX4937_CCFG_PCIDIVMODE_4_5: - pciclk = tx4927_cpu_clock * 2 / 9; - break; - case TX4937_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4937_CCFG_PCIDIVMODE_5_5: - pciclk = tx4927_cpu_clock * 2 / 11; - break; - case TX4937_CCFG_PCIDIVMODE_8: - pciclk = tx4927_cpu_clock / 8; - break; - case TX4937_CCFG_PCIDIVMODE_9: - pciclk = tx4927_cpu_clock / 9; - break; - case TX4937_CCFG_PCIDIVMODE_10: - pciclk = tx4927_cpu_clock / 10; - break; - case TX4937_CCFG_PCIDIVMODE_11: - pciclk = tx4927_cpu_clock / 11; - break; - } - - else - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - pciclk = tx4927_cpu_clock * 2 / 5; - break; - case TX4927_CCFG_PCIDIVMODE_3: - pciclk = tx4927_cpu_clock / 3; - break; - case TX4927_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4927_CCFG_PCIDIVMODE_6: - pciclk = tx4927_cpu_clock / 6; - break; - } - - printk("Internal(%dMHz)", pciclk / 1000000); - } else - printk("External"); - printk("\n"); - - /* GB->PCI mappings */ - tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; - tx4927_pcicptr->g2piogbase = mips_pci_io_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PIOGBASE_ECHG -#else - TX4927_PCIC_G2PIOGBASE_BSDIS -#endif - ; - - tx4927_pcicptr->g2piopbase = 0; - - tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; - tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PMnGBASE_ECHG -#else - TX4927_PCIC_G2PMnGBASE_BSDIS -#endif - ; - tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; - - tx4927_pcicptr->g2pmmask[1] = 0; - tx4927_pcicptr->g2pmgbase[1] = 0; - tx4927_pcicptr->g2pmpbase[1] = 0; - tx4927_pcicptr->g2pmmask[2] = 0; - tx4927_pcicptr->g2pmgbase[2] = 0; - tx4927_pcicptr->g2pmpbase[2] = 0; - - - /* PCI->GB mappings (I/O 256B) */ - tx4927_pcicptr->p2giopbase = 0; /* 256B */ - - /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ - tx4927_pcicptr->p2gm0plbase = 0; - tx4927_pcicptr->p2gm0pubase = 0; - tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4927_PCIC_P2GMnGBASE_TECHG -#else - TX4927_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - - /* PCI->GB mappings (MEM 16MB) -not used */ - tx4927_pcicptr->p2gm1plbase = 0xffffffff; - tx4927_pcicptr->p2gm1pubase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[1] = 0; - - /* PCI->GB mappings (MEM 1MB) -not used */ - tx4927_pcicptr->p2gm2pbase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[2] = 0; - - - /* Enable Initiator Memory 0 Space, I/O Space, Config */ - tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; - tx4927_pcicptr->pciccfg |= - TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | - TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; - - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - tx4927_pcicptr->pcicfg1 = 0; - - if (tx4927_pcic_trdyto >= 0) { - tx4927_pcicptr->g2ptocnt &= ~0xff; - tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); - } - - /* Clear All Local Bus Status */ - tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr->pcistatus & 0x0000ffff) | - (TX4927_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; - - /* PCIC Int => IRC IRQ16 */ - tx4927_pcicptr->pcicfg2 = - (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; - - if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { - /* XXX */ - } else { - /* Reset Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; - /* Enable Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; - } - - tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + tx4937_pci_setup(); + else + tx4927_pci_setup(); + return 0; } +arch_initcall(rbtx4927_arch_init); #endif /* CONFIG_PCI */ static void __noreturn wait_forever(void) @@ -479,8 +239,6 @@ void __init plat_mem_setup(void) cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); write_c0_config(cp0_config); - set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); - ioport_resource.end = 0xffffffff; iomem_resource.end = 0xffffffff; @@ -492,8 +250,13 @@ void __init plat_mem_setup(void) txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); #ifdef CONFIG_PCI + txx9_alloc_pci_controller(&txx9_primary_pcic, + RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, + RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); +#else + set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); +#endif - /* PCIC */ /* * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. * @@ -517,58 +280,38 @@ void __init plat_mem_setup(void) * */ if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_8: - case TX4937_CCFG_PCIDIVMODE_4: - tx4927_cpu_clock = 266666666; /* 266MHz */ + switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & + TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + txx9_cpu_clock = 266666666; /* 266MHz */ break; - case TX4937_CCFG_PCIDIVMODE_9: - case TX4937_CCFG_PCIDIVMODE_4_5: - tx4927_cpu_clock = 300000000; /* 300MHz */ + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + txx9_cpu_clock = 300000000; /* 300MHz */ break; default: - tx4927_cpu_clock = 333333333; /* 333MHz */ + txx9_cpu_clock = 333333333; /* 333MHz */ } else - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & + TX4927_CCFG_PCIDIVMODE_MASK) { case TX4927_CCFG_PCIDIVMODE_2_5: case TX4927_CCFG_PCIDIVMODE_5: - tx4927_cpu_clock = 166666666; /* 166MHz */ + txx9_cpu_clock = 166666666; /* 166MHz */ break; default: - tx4927_cpu_clock = 200000000; /* 200MHz */ + txx9_cpu_clock = 200000000; /* 200MHz */ } + /* change default value to udelay/mdelay take reasonable time */ + loops_per_jiffy = txx9_cpu_clock / HZ / 2; /* CCFG */ /* do reset on watchdog */ - tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; + tx4927_ccfg_set(TX4927_CCFG_WR); /* enable Timeout BusError */ if (tx4927_ccfg_toeon) - tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; - - tx4927_pci_setup(); - if (tx4927_using_backplane == 1) - printk("backplane board IS installed\n"); - else - printk("No Backplane \n"); - - /* this is on ISA bus behind PCI bus, so need PCI up first */ -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) { - smsc_fdc37m81x_init(0x3f0); - smsc_fdc37m81x_config_beg(); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, - SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, - 1); - smsc_fdc37m81x_config_end(); - } -#endif -#endif /* CONFIG_PCI */ + tx4927_ccfg_set(TX4927_CCFG_TOE); #ifdef CONFIG_SERIAL_TXX9 { @@ -611,8 +354,8 @@ void __init plat_mem_setup(void) void __init plat_time_init(void) { - mips_hpt_frequency = tx4927_cpu_clock / 2; - if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) + mips_hpt_frequency = txx9_cpu_clock / 2; + if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, TXX9_IRQ_BASE + 17, 50000000); diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index bbd572c9675b..144d2cada820 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -26,6 +25,8 @@ #include #include #include +#include +#include #include #ifdef CONFIG_SERIAL_TXX9 #include @@ -35,37 +36,13 @@ #include extern char * __init prom_getcmdline(void); -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); - /* These functions are used for rebooting or halting the machine*/ extern void rbtx4938_machine_restart(char *command); extern void rbtx4938_machine_halt(void); extern void rbtx4938_machine_power_off(void); -/* clocks */ -unsigned int txx9_master_clock; -unsigned int txx9_cpu_clock; -unsigned int txx9_gbus_clock; - -unsigned long rbtx4938_ce_base[8]; -unsigned long rbtx4938_ce_size[8]; -int txboard_pci66_mode; -static int tx4938_pcic_trdyto; /* default: disabled */ -static int tx4938_pcic_retryto; /* default: disabled */ static int tx4938_ccfg_toeon = 1; -struct tx4938_pcic_reg *pcicptrs[4] = { - tx4938_pcicptr /* default setting for TX4938 */ -}; - -static struct { - unsigned long base; - unsigned long size; -} phys_regions[16] __initdata; -static int num_phys_regions __initdata; - -#define PHYS_REGION_MINSIZE 0x10000 - void rbtx4938_machine_halt(void) { printk(KERN_NOTICE "System Halted\n"); @@ -95,473 +72,72 @@ void rbtx4938_machine_restart(char *command) ; } -void __init -txboard_add_phys_region(unsigned long base, unsigned long size) -{ - if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { - printk("phys_region overflow\n"); - return; - } - phys_regions[num_phys_regions].base = base; - phys_regions[num_phys_regions].size = size; - num_phys_regions++; -} -unsigned long __init -txboard_find_free_phys_region(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - int i; - - for (base = begin / size * size; base < end; base += size) { - for (i = 0; i < num_phys_regions; i++) { - if (phys_regions[i].size && - base <= phys_regions[i].base + (phys_regions[i].size - 1) && - base + (size - 1) >= phys_regions[i].base) - break; - } - if (i == num_phys_regions) - return base; - } - return 0; -} -unsigned long __init -txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, - unsigned long *size) -{ - unsigned long sz, base; - for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { - base = txboard_find_free_phys_region(begin, end, sz); - if (base) { - *size = sz; - return base; - } - } - return 0; -} -unsigned long __init -txboard_request_phys_region_range(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region(unsigned long size) +static void __init rbtx4938_pci_setup(void) { - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region_shrink(unsigned long *size) -{ - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region_shrink(begin, end, size); - if (base) - txboard_add_phys_region(base, *size); - return base; -} - #ifdef CONFIG_PCI -void __init -tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, - struct pci_controller *channel, - unsigned long pci_io_base, - int extarb) -{ - int i; + int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB); + struct pci_controller *c = &txx9_primary_pcic; - /* Disable All Initiator Space */ - pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| - TX4938_PCIC_PCICCFG_G2PMEN(1)| - TX4938_PCIC_PCICCFG_G2PMEN(2)| - TX4938_PCIC_PCICCFG_G2PIOEN); - - /* GB->PCI mappings */ - pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; - pcicptr->g2piogbase = pci_io_base | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PIOGBASE_ECHG -#else - TX4938_PCIC_G2PIOGBASE_BSDIS -#endif - ; - pcicptr->g2piopbase = 0; - for (i = 0; i < 3; i++) { - pcicptr->g2pmmask[i] = 0; - pcicptr->g2pmgbase[i] = 0; - pcicptr->g2pmpbase[i] = 0; - } - if (channel->mem_resource->end) { - pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; - pcicptr->g2pmgbase[0] = channel->mem_resource->start | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PMnGBASE_ECHG -#else - TX4938_PCIC_G2PMnGBASE_BSDIS -#endif - ; - pcicptr->g2pmpbase[0] = channel->mem_resource->start; - } - /* PCI->GB mappings (I/O 256B) */ - pcicptr->p2giopbase = 0; /* 256B */ - pcicptr->p2giogbase = 0; - /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ - pcicptr->p2gm0plbase = 0; - pcicptr->p2gm0pubase = 0; - pcicptr->p2gmgbase[0] = 0 | - TX4938_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4938_PCIC_P2GMnGBASE_TECHG -#else - TX4938_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - /* PCI->GB mappings (MEM 16MB) */ - pcicptr->p2gm1plbase = 0xffffffff; - pcicptr->p2gm1pubase = 0xffffffff; - pcicptr->p2gmgbase[1] = 0; - /* PCI->GB mappings (MEM 1MB) */ - pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ - pcicptr->p2gmgbase[2] = 0; - - pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; - /* Enable Initiator Memory Space */ - if (channel->mem_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); - /* Enable Initiator I/O Space */ - if (channel->io_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; - /* Enable Initiator Config */ - pcicptr->pciccfg |= - TX4938_PCIC_PCICCFG_ICAEN | - TX4938_PCIC_PCICCFG_TCAR; - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - pcicptr->pcicfg1 = 0; - - pcicptr->g2ptocnt &= ~0xffff; - - if (tx4938_pcic_trdyto >= 0) { - pcicptr->g2ptocnt &= ~0xff; - pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); - } - - if (tx4938_pcic_retryto >= 0) { - pcicptr->g2ptocnt &= ~0xff00; - pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); - } - - /* Clear All Local Bus Status */ - pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - pcicptr->pcistatus = - (pcicptr->pcistatus & 0x0000ffff) | - (TX4938_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; - - if (!extarb) { - /* Reset Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; - pcicptr->pbabm = 0; - /* Enable Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; - } - - /* PCIC Int => IRC IRQ16 */ - pcicptr->pcicfg2 = - (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; - - pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; -} - -int __init -tx4938_report_pciclk(void) -{ - unsigned long pcode = TX4938_REV_PCODE(); - int pciclk = 0; - printk("TX%lx PCIC --%s PCICLK:", - pcode, - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - - switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { - case TX4938_CCFG_PCIDIVMODE_4: - pciclk = txx9_cpu_clock / 4; break; - case TX4938_CCFG_PCIDIVMODE_4_5: - pciclk = txx9_cpu_clock * 2 / 9; break; - case TX4938_CCFG_PCIDIVMODE_5: - pciclk = txx9_cpu_clock / 5; break; - case TX4938_CCFG_PCIDIVMODE_5_5: - pciclk = txx9_cpu_clock * 2 / 11; break; - case TX4938_CCFG_PCIDIVMODE_8: - pciclk = txx9_cpu_clock / 8; break; - case TX4938_CCFG_PCIDIVMODE_9: - pciclk = txx9_cpu_clock / 9; break; - case TX4938_CCFG_PCIDIVMODE_10: - pciclk = txx9_cpu_clock / 10; break; - case TX4938_CCFG_PCIDIVMODE_11: - pciclk = txx9_cpu_clock / 11; break; - } - printk("Internal(%dMHz)", pciclk / 1000000); - } else { - printk("External"); - pciclk = -1; - } - printk("\n"); - return pciclk; -} - -void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) -{ - pcicptrs[ch] = pcicptr; -} - -struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) -{ - return pcicptrs[ch]; -} - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; + register_pci_controller(c); - dev.sysdata = bus.sysdata = hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, word, u16 *) - -int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) -{ - u32 pci_devfn; - unsigned short vid; - int devfn_start = 0; - int devfn_stop = 0xff; - int cap66 = -1; - u16 stat; - - printk("PCI: Checking 66MHz capabilities...\n"); - - for (pci_devfn=devfn_start; pci_devfn 0; -} - -int __init -tx4938_pciclk66_setup(void) -{ - int pciclk; - - /* Assert M66EN */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; - /* Double PCICLK (if possible) */ - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - unsigned int pcidivmode = - tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; - switch (pcidivmode) { - case TX4938_CCFG_PCIDIVMODE_8: - case TX4938_CCFG_PCIDIVMODE_4: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4; - pciclk = txx9_cpu_clock / 4; - break; - case TX4938_CCFG_PCIDIVMODE_9: - case TX4938_CCFG_PCIDIVMODE_4_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; - pciclk = txx9_cpu_clock * 2 / 9; - break; - case TX4938_CCFG_PCIDIVMODE_10: - case TX4938_CCFG_PCIDIVMODE_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5; - pciclk = txx9_cpu_clock / 5; - break; - case TX4938_CCFG_PCIDIVMODE_11: - case TX4938_CCFG_PCIDIVMODE_5_5: - default: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; - pciclk = txx9_cpu_clock * 2 / 11; - break; - } - tx4938_ccfgptr->ccfg = - (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) - | pcidivmode; - printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", - (unsigned long)tx4938_ccfgptr->ccfg); - } else { - pciclk = -1; - } - return pciclk; -} - -extern struct pci_controller tx4938_pci_controller[]; -static int __init tx4938_pcibios_init(void) -{ - unsigned long mem_base[2]; - unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ - unsigned long io_base[2]; - unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ - /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ - int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); - - PCIBIOS_MIN_IO = 0x00001000UL; - - mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); - io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); - - printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - (unsigned short)(tx4938_pcicptr->pciid >> 16), - (unsigned short)(tx4938_pcicptr->pciid & 0xffff), - (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), - extarb ? "External" : "Internal"); - - /* setup PCI area */ - tx4938_pci_controller[0].io_resource->start = io_base[0]; - tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; - tx4938_pci_controller[0].mem_resource->start = mem_base[0]; - tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; - - set_tx4938_pcicptr(0, tx4938_pcicptr); - - register_pci_controller(&tx4938_pci_controller[0]); - - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { - printk("TX4938_CCFG_PCI66 already configured\n"); - txboard_pci66_mode = -1; /* already configured */ - } + if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) + txx9_pci_option = + (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | + TXX9_PCI_OPT_CLK_66; /* already configured */ /* Reset PCI Bus */ writeb(0, rbtx4938_pcireset_addr); /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; - if (txboard_pci66_mode > 0) + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_66) tx4938_pciclk66_setup(); mdelay(10); /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); writeb(1, rbtx4938_pcireset_addr); - mmiowb(); - tx4938_report_pcic_status1(tx4938_pcicptr); + iob(); tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); - if (txboard_pci66_mode == 0 && - txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { + tx4927_pcic_setup(tx4938_pcicptr, c, extarb); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_AUTO && + txx9_pci66_check(c, 0, 0)) { /* Reset PCI Bus */ writeb(0, rbtx4938_pcireset_addr); /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); tx4938_pciclk66_setup(); mdelay(10); /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); writeb(1, rbtx4938_pcireset_addr); - mmiowb(); + iob(); /* Reinitialize PCIC */ tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + tx4927_pcic_setup(tx4938_pcicptr, c, extarb); } - mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); - io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); - /* Reset PCIC1 */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; - /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; - else - tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; - mdelay(10); - /* clear PCIC1 reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; - tx4938_report_pcic_status1(tx4938_pcic1ptr); - - printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", - (unsigned short)(tx4938_pcic1ptr->pciid >> 16), - (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), - (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); - printk("%s PCICLK:%dMHz\n", - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", - txx9_gbus_clock / - ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / - 1000000); - - /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ - tx4938_pci_controller[1].io_resource->start = - io_base[1] - io_base[0]; - tx4938_pci_controller[1].io_resource->end = - io_base[1] - io_base[0] + io_size[1] - 1; - tx4938_pci_controller[1].mem_resource->start = mem_base[1]; - tx4938_pci_controller[1].mem_resource->end = - mem_base[1] + mem_size[1] - 1; - set_tx4938_pcicptr(1, tx4938_pcic1ptr); - - register_pci_controller(&tx4938_pci_controller[1]); - - tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); - - /* map ioport 0 to PCI I/O space address 0 */ - set_io_port_base(KSEG1 + io_base[0]); - - return 0; -} - -arch_initcall(tx4938_pcibios_init); - + if (__raw_readq(&tx4938_ccfgptr->pcfg) & + (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) { + /* Reset PCIC1 */ + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); + /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ + if (!(__raw_readq(&tx4938_ccfgptr->ccfg) + & TX4938_CCFG_PCI1DMD)) + tx4938_ccfg_set(TX4938_CCFG_PCI1_66); + mdelay(10); + /* clear PCIC1 reset */ + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); + tx4938_report_pci1clk(); + + /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */ + c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000); + register_pci_controller(c); + tx4927_pcic_setup(tx4938_pcic1ptr, c, 0); + } #endif /* CONFIG_PCI */ +} /* SPI support */ @@ -594,7 +170,7 @@ static int __init rbtx4938_ethaddr_init(void) unsigned int id = TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); struct platform_device *pdev; - if (!(tx4938_ccfgptr->pcfg & + if (!(__raw_readq(&tx4938_ccfgptr->pcfg) & (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) continue; pdev = platform_device_alloc("tc35815-mac", id); @@ -611,18 +187,12 @@ device_initcall(rbtx4938_ethaddr_init); static void __init rbtx4938_spi_setup(void) { /* set SPI_SEL */ - tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; + txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL); } static struct resource rbtx4938_fpga_resource; - -static char pcode_str[8]; -static struct resource tx4938_reg_resource = { - .start = TX4938_REG_BASE, - .end = TX4938_REG_BASE + TX4938_REG_SIZE, - .name = pcode_str, - .flags = IORESOURCE_MEM -}; +static struct resource tx4938_sdram_resource[4]; +static struct resource tx4938_sram_resource; void __init tx4938_board_setup(void) { @@ -631,24 +201,28 @@ void __init tx4938_board_setup(void) int cpuclk = 0; unsigned long pcode = TX4938_REV_PCODE(); - ioport_resource.start = 0x1000; + ioport_resource.start = 0; ioport_resource.end = 0xffffffff; - iomem_resource.start = 0x1000; + iomem_resource.start = 0; iomem_resource.end = 0xffffffff; /* expand to 4GB */ - sprintf(pcode_str, "TX%lx", pcode); + txx9_reg_res_init(pcode, TX4938_REG_BASE, + TX4938_REG_SIZE); /* SDRAMC,EBUSC are configured by PROM */ for (i = 0; i < 8; i++) { - if (!(tx4938_ebuscptr->cr[i] & 0x8)) + if (!(TX4938_EBUSC_CR(i) & 0x8)) continue; /* disabled */ - rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); - txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); + txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i); + txx9_ce_res[i].end = + txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1; + request_resource(&iomem_resource, &txx9_ce_res[i]); } /* clocks */ if (txx9_master_clock) { + u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); /* calculate gbus_clock and cpu_clock_freq from master_clock */ - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; switch (divmode) { case TX4938_CCFG_DIVMODE_8: case TX4938_CCFG_DIVMODE_10: @@ -678,12 +252,13 @@ void __init tx4938_board_setup(void) } txx9_cpu_clock = cpuclk; } else { + u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); if (txx9_cpu_clock == 0) { txx9_cpu_clock = 300000000; /* 300MHz */ } /* calculate gbus_clock and master_clock from cpu_clock_freq */ cpuclk = txx9_cpu_clock; - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; switch (divmode) { case TX4938_CCFG_DIVMODE_2: case TX4938_CCFG_DIVMODE_8: @@ -717,32 +292,32 @@ void __init tx4938_board_setup(void) /* CCFG */ /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; + tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW); /* do reset on watchdog */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; + tx4938_ccfg_set(TX4938_CCFG_WR); /* clear PCIC1 reset */ - if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); /* enable Timeout BusError */ if (tx4938_ccfg_toeon) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; + tx4938_ccfg_set(TX4938_CCFG_TOE); /* DMA selection */ - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL); /* Use external clock for external arbiter */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; - - printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", - pcode_str, - cpuclk / 1000000, txx9_master_clock / 1000000, - (unsigned long)tx4938_ccfgptr->crir, - tx4938_ccfgptr->ccfg, - tx4938_ccfgptr->pcfg); - - printk("%s SDRAMC --", pcode_str); + if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB)) + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL); + + printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", + txx9_pcode_str, + (cpuclk + 500000) / 1000000, + (txx9_master_clock + 500000) / 1000000, + (__u32)____raw_readq(&tx4938_ccfgptr->crir), + (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), + (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg)); + + printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); for (i = 0; i < 4; i++) { unsigned long long cr = tx4938_sdramcptr->cr[i]; unsigned long ram_base, ram_size; @@ -753,16 +328,24 @@ void __init tx4938_board_setup(void) if (ram_base >= 0x20000000) continue; /* high memory (ignore) */ printk(" CR%d:%016Lx", i, cr); - txboard_add_phys_region(ram_base, ram_size); + tx4938_sdram_resource[i].name = "SDRAM"; + tx4938_sdram_resource[i].start = ram_base; + tx4938_sdram_resource[i].end = ram_base + ram_size - 1; + tx4938_sdram_resource[i].flags = IORESOURCE_MEM; + request_resource(&iomem_resource, &tx4938_sdram_resource[i]); } printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); /* SRAM */ - if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { + if (tx4938_sramcptr->cr & 1) { unsigned int size = 0x800; unsigned long base = (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); - txboard_add_phys_region(base, size); + tx4938_sram_resource.name = "SRAM"; + tx4938_sram_resource.start = base; + tx4938_sram_resource.end = base + size - 1; + tx4938_sram_resource.flags = IORESOURCE_MEM; + request_resource(&iomem_resource, &tx4938_sram_resource); } /* TMR */ @@ -778,71 +361,15 @@ void __init tx4938_board_setup(void) __raw_writel(0, &tx4938_pioptr->maskcpu); __raw_writel(0, &tx4938_pioptr->maskext); - /* TX4938 internal registers */ - if (request_resource(&iomem_resource, &tx4938_reg_resource)) - printk("request resource for internal registers failed\n"); -} - #ifdef CONFIG_PCI -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) -{ - unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); - unsigned long g2pstatus = pcicptr->g2pstatus; - unsigned long pcicstatus = pcicptr->pcicstatus; - static struct { - unsigned long flag; - const char *str; - } pcistat_tbl[] = { - { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, - { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, - { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, - { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, - { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, - { PCI_STATUS_PARITY, "MasterParityError" }, - }, g2pstat_tbl[] = { - { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, - { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, - }, pcicstat_tbl[] = { - { TX4938_PCIC_PCICSTATUS_PME, "PME" }, - { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, - { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, - { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, - { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, - { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, - { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, - { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, - }; - int i; - - printk("pcistat:%04x(", pcistatus); - for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) - if (pcistatus & pcistat_tbl[i].flag) - printk("%s ", pcistat_tbl[i].str); - printk("), g2pstatus:%08lx(", g2pstatus); - for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) - if (g2pstatus & g2pstat_tbl[i].flag) - printk("%s ", g2pstat_tbl[i].str); - printk("), pcicstatus:%08lx(", pcicstatus); - for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) - if (pcicstatus & pcicstat_tbl[i].flag) - printk("%s ", pcicstat_tbl[i].str); - printk(")\n"); -} - -void tx4938_report_pcic_status(void) -{ - int i; - struct tx4938_pcic_reg *pcicptr; - for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) - tx4938_report_pcic_status1(pcicptr); + txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); +#endif } -#endif /* CONFIG_PCI */ - void __init plat_time_init(void) { mips_hpt_frequency = txx9_cpu_clock / 2; - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) + if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS) txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, TXX9_IRQ_BASE + TX4938_IR_TMR(0), txx9_gbus_clock / 2); @@ -890,19 +417,20 @@ void __init plat_mem_setup(void) #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 printk("PIOSEL: disabling both ata and nand selection\n"); local_irq_disable(); - tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); + txx9_clear64(&tx4938_ccfgptr->pcfg, + TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND printk("PIOSEL: enabling nand selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; + txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA printk("PIOSEL: enabling ata selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; + txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); #endif #ifdef CONFIG_IP_PNP @@ -920,7 +448,7 @@ void __init plat_mem_setup(void) #endif rbtx4938_spi_setup(); - pcfg = tx4938_ccfgptr->pcfg; /* updated */ + pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */ /* fixup piosel */ if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == TX4938_PCFG_ATA_SEL) @@ -1063,6 +591,7 @@ static int __init rbtx4938_arch_init(void) { txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); gpiochip_add(&rbtx4938_spi_gpio_chip); + rbtx4938_pci_setup(); return rbtx4938_spi_init(); } arch_initcall(rbtx4938_arch_init); diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h new file mode 100644 index 000000000000..2ff6c2002204 --- /dev/null +++ b/include/asm-mips/txx9/generic.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm-mips/txx9/generic.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_TXX9_GENERIC_H +#define __ASM_TXX9_GENERIC_H + +#include +#include /* for struct resource */ + +extern struct resource txx9_ce_res[]; +extern char txx9_pcode_str[8]; +void txx9_reg_res_init(unsigned int pcode, unsigned long base, + unsigned long size); + +extern unsigned int txx9_master_clock; +extern unsigned int txx9_cpu_clock; +extern unsigned int txx9_gbus_clock; + +#endif /* __ASM_TXX9_GENERIC_H */ diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h new file mode 100644 index 000000000000..d89a45091e24 --- /dev/null +++ b/include/asm-mips/txx9/pci.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_TXX9_PCI_H +#define __ASM_TXX9_PCI_H + +#include + +extern struct pci_controller txx9_primary_pcic; +struct pci_controller * +txx9_alloc_pci_controller(struct pci_controller *pcic, + unsigned long mem_base, unsigned long mem_size, + unsigned long io_base, unsigned long io_size); + +int txx9_pci66_check(struct pci_controller *hose, int top_bus, + int current_bus); +extern int txx9_pci_mem_high __initdata; + +extern int txx9_pci_option; +#define TXX9_PCI_OPT_PICMG 0x0002 +#define TXX9_PCI_OPT_CLK_33 0x0008 +#define TXX9_PCI_OPT_CLK_66 0x0010 +#define TXX9_PCI_OPT_CLK_MASK \ + (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66) +#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK + +enum txx9_pci_err_action { + TXX9_PCI_ERR_REPORT, + TXX9_PCI_ERR_IGNORE, + TXX9_PCI_ERR_PANIC, +}; +extern enum txx9_pci_err_action txx9_pci_err_action; + +#endif /* __ASM_TXX9_PCI_H */ diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h index 5531342bcc01..5b6f488b1b3c 100644 --- a/include/asm-mips/txx9/rbtx4927.h +++ b/include/asm-mips/txx9/rbtx4927.h @@ -29,10 +29,33 @@ #include +#define RBTX4927_PCIMEM 0x08000000 +#define RBTX4927_PCIMEM_SIZE 0x08000000 +#define RBTX4927_PCIIO 0x16000000 +#define RBTX4927_PCIIO_SIZE 0x01000000 + +#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL) + +/* bits for ISTAT/IMASK/IMSTAT */ +#define RBTX4927_INTB_PCID 0 +#define RBTX4927_INTB_PCIC 1 +#define RBTX4927_INTB_PCIB 2 +#define RBTX4927_INTB_PCIA 3 +#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID) +#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC) +#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB) +#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA) + +#define RBTX4927_IRQ_IOC (TX4927_IRQ_PIC_BEG + TX4927_NUM_IR) +#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID) +#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC) +#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB) +#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA) + #ifdef CONFIG_PCI -#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO +#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO #else -#define TBTX4927_ISA_IO_OFFSET 0 +#define RBTX4927_ISA_IO_OFFSET 0 #endif #define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL @@ -41,7 +64,7 @@ #define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL #define RBTX4927_SW_RESET_ENABLE_SET 0x01 -#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) +#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET) #define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) int toshiba_rbtx4927_irq_nested(int sw_irq); diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h index 63b62d6061f5..ca414c7624e1 100644 --- a/include/asm-mips/txx9/tx3927.h +++ b/include/asm-mips/txx9/tx3927.h @@ -316,4 +316,8 @@ struct tx3927_ccfg_reg { #define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) #define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) +struct pci_controller; +void __init tx3927_pcic_setup(struct pci_controller *channel, + unsigned long sdram_size, int extarb); + #endif /* __ASM_TXX9_TX3927_H */ diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h index f21a7b1831e5..c0382fd2ae7f 100644 --- a/include/asm-mips/txx9/tx4927.h +++ b/include/asm-mips/txx9/tx4927.h @@ -27,7 +27,10 @@ #ifndef __ASM_TXX9_TX4927_H #define __ASM_TXX9_TX4927_H +#include +#include #include +#include #define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE #define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) @@ -43,15 +46,6 @@ #define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) -#define TX4927_CCFG_TOE 0x00004000 -#define TX4927_CCFG_WR 0x00008000 -#define TX4927_CCFG_TINTDIS 0x01000000 - -#define TX4927_PCIMEM 0x08000000 -#define TX4927_PCIMEM_SIZE 0x08000000 -#define TX4927_PCIIO 0x16000000 -#define TX4927_PCIIO_SIZE 0x01000000 - #define TX4927_SDRAMC_REG 0xff1f8000 #define TX4927_EBUSC_REG 0xff1f9000 #define TX4927_PCIC_REG 0xff1fd000 @@ -60,36 +54,9 @@ #define TX4927_NR_TMR 3 #define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) -/* bits for ISTAT3/IMASK3/IMSTAT3 */ -#define TX4927_INT3B_PCID 0 -#define TX4927_INT3B_PCIC 1 -#define TX4927_INT3B_PCIB 2 -#define TX4927_INT3B_PCIA 3 -#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) -#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) -#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) -#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) - -#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG -#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ - #define TX4927_IR_PCIC 16 #define TX4927_IR_PCIERR 22 -#define TX4927_IR_PCIPMA 23 -#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) -#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) -#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) -#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) -#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) -#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) -#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) - -#ifdef _LANGUAGE_ASSEMBLY -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include +#define TX4927_NUM_IR 32 struct tx4927_sdramc_reg { volatile unsigned long long cr[4]; @@ -104,177 +71,158 @@ struct tx4927_ebusc_reg { }; struct tx4927_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; -}; - -struct tx4927_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmcut; - volatile unsigned long long pdmcnt; /* +220 */ - volatile unsigned long long pdmsts; - volatile unsigned long long unused8[2]; - volatile unsigned long long pdmdb[4]; /* +240 */ - volatile unsigned long long pdmtdh; /* +260 */ - volatile unsigned long long pdmdms; + u64 ccfg; + u64 crir; + u64 pcfg; + u64 toea; + u64 clkctr; + u64 unused0; + u64 garbc; + u64 unused1; + u64 unused2; + u64 ramp; }; -#endif /* _LANGUAGE_ASSEMBLY */ - -/* - * PCIC - */ - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4927_PCIC_PBACFG_RPBA 0x00000004 -#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc - -/* bits for PCICCFG */ -#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 -#define TX4927_PCIC_PCICCFG_HRST 0x00000800 -#define TX4927_PCIC_PCICCFG_SRST 0x00000400 -#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 -#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 -#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 -#define TX4927_PCIC_PCICCFG_IISE 0x00000020 -#define TX4927_PCIC_PCICCFG_ATR 0x00000010 -#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) - /* * CCFG */ /* CCFG : Chip Configuration */ +#define TX4927_CCFG_WDRST 0x0000020000000000ULL +#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL +#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL +#define TX4927_CCFG_TINTDIS 0x01000000 #define TX4927_CCFG_PCI66 0x00800000 -#define TX4927_CCFG_PCIMIDE 0x00400000 -#define TX4927_CCFG_PCIXARB 0x00002000 +#define TX4927_CCFG_PCIMODE 0x00400000 +#define TX4927_CCFG_DIVMODE_MASK 0x000e0000 +#define TX4927_CCFG_DIVMODE_8 (0x0 << 17) +#define TX4927_CCFG_DIVMODE_12 (0x1 << 17) +#define TX4927_CCFG_DIVMODE_16 (0x2 << 17) +#define TX4927_CCFG_DIVMODE_10 (0x3 << 17) +#define TX4927_CCFG_DIVMODE_2 (0x4 << 17) +#define TX4927_CCFG_DIVMODE_3 (0x5 << 17) +#define TX4927_CCFG_DIVMODE_4 (0x6 << 17) +#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17) +#define TX4927_CCFG_BEOW 0x00010000 +#define TX4927_CCFG_WR 0x00008000 +#define TX4927_CCFG_TOE 0x00004000 +#define TX4927_CCFG_PCIARB 0x00002000 #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 #define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 #define TX4927_CCFG_PCIDIVMODE_3 0x00000800 #define TX4927_CCFG_PCIDIVMODE_5 0x00001000 #define TX4927_CCFG_PCIDIVMODE_6 0x00001800 - -#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 -#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 -#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 -#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 -#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 -#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 -#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 -#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 +#define TX4927_CCFG_SYSSP_MASK 0x000000c0 +#define TX4927_CCFG_ENDIAN 0x00000004 +#define TX4927_CCFG_HALT 0x00000002 +#define TX4927_CCFG_ACEHOLD 0x00000001 +#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW) /* PCFG : Pin Configuration */ +#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000 +#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28) +#define TX4927_PCFG_SYSCLKEN 0x08000000 +#define TX4927_PCFG_SDCLKEN_ALL 0x07800000 +#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) +#define TX4927_PCFG_SEL2 0x00000200 +#define TX4927_PCFG_SEL1 0x00000100 +#define TX4927_PCFG_DMASEL_ALL 0x000000ff +#define TX4927_PCFG_DMASEL0_MASK 0x00000003 +#define TX4927_PCFG_DMASEL1_MASK 0x0000000c +#define TX4927_PCFG_DMASEL2_MASK 0x00000030 +#define TX4927_PCFG_DMASEL3_MASK 0x000000c0 +#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000 +#define TX4927_PCFG_DMASEL0_SIO1 0x00000001 +#define TX4927_PCFG_DMASEL0_ACL0 0x00000002 +#define TX4927_PCFG_DMASEL0_ACL2 0x00000003 +#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000 +#define TX4927_PCFG_DMASEL1_SIO1 0x00000004 +#define TX4927_PCFG_DMASEL1_ACL1 0x00000008 +#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c +#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */ +#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */ +#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */ +#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */ +#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */ +#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000 +#define TX4927_PCFG_DMASEL3_SIO0 0x00000040 +#define TX4927_PCFG_DMASEL3_ACL3 0x00000080 +#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0 /* CLKCTR : Clock Control */ +#define TX4927_CLKCTR_ACLCKD 0x02000000 +#define TX4927_CLKCTR_PIOCKD 0x01000000 +#define TX4927_CLKCTR_DMACKD 0x00800000 #define TX4927_CLKCTR_PCICKD 0x00400000 +#define TX4927_CLKCTR_TM0CKD 0x00100000 +#define TX4927_CLKCTR_TM1CKD 0x00080000 +#define TX4927_CLKCTR_TM2CKD 0x00040000 +#define TX4927_CLKCTR_SIO0CKD 0x00020000 +#define TX4927_CLKCTR_SIO1CKD 0x00010000 +#define TX4927_CLKCTR_ACLRST 0x00000200 +#define TX4927_CLKCTR_PIORST 0x00000100 +#define TX4927_CLKCTR_DMARST 0x00000080 #define TX4927_CLKCTR_PCIRST 0x00000040 - -#ifndef _LANGUAGE_ASSEMBLY +#define TX4927_CLKCTR_TM0RST 0x00000010 +#define TX4927_CLKCTR_TM1RST 0x00000008 +#define TX4927_CLKCTR_TM2RST 0x00000004 +#define TX4927_CLKCTR_SIO0RST 0x00000002 +#define TX4927_CLKCTR_SIO1RST 0x00000001 #define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) -#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) -#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) +#define tx4927_pcicptr \ + ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG) +#define tx4927_ccfgptr \ + ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) #define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) -#endif /* _LANGUAGE_ASSEMBLY */ +/* utilities */ +static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) +{ +#ifdef CONFIG_32BIT + unsigned long flags; + local_irq_save(flags); +#endif + ____raw_writeq(____raw_readq(adr) & ~bits, adr); +#ifdef CONFIG_32BIT + local_irq_restore(flags); +#endif +} +static inline void txx9_set64(__u64 __iomem *adr, __u64 bits) +{ +#ifdef CONFIG_32BIT + unsigned long flags; + local_irq_save(flags); +#endif + ____raw_writeq(____raw_readq(adr) | bits, adr); +#ifdef CONFIG_32BIT + local_irq_restore(flags); +#endif +} + +/* These functions are not interrupt safe. */ +static inline void tx4927_ccfg_clear(__u64 bits) +{ + ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg) + & ~(TX4927_CCFG_W1CBITS | bits), + &tx4927_ccfgptr->ccfg); +} +static inline void tx4927_ccfg_set(__u64 bits) +{ + ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) + & ~TX4927_CCFG_W1CBITS) | bits, + &tx4927_ccfgptr->ccfg); +} +static inline void tx4927_ccfg_change(__u64 change, __u64 new) +{ + ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) + & ~(TX4927_CCFG_W1CBITS | change)) | + new, + &tx4927_ccfgptr->ccfg); +} + +int tx4927_report_pciclk(void); +int tx4927_pciclk66_setup(void); #endif /* __ASM_TXX9_TX4927_H */ diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h new file mode 100644 index 000000000000..d61c3d09c4a2 --- /dev/null +++ b/include/asm-mips/txx9/tx4927pcic.h @@ -0,0 +1,199 @@ +/* + * include/asm-mips/txx9/tx4927pcic.h + * TX4927 PCI controller definitions. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_TXX9_TX4927PCIC_H +#define __ASM_TXX9_TX4927PCIC_H + +#include + +struct tx4927_pcic_reg { + u32 pciid; + u32 pcistatus; + u32 pciccrev; + u32 pcicfg1; + u32 p2gm0plbase; /* +10 */ + u32 p2gm0pubase; + u32 p2gm1plbase; + u32 p2gm1pubase; + u32 p2gm2pbase; /* +20 */ + u32 p2giopbase; + u32 unused0; + u32 pcisid; + u32 unused1; /* +30 */ + u32 pcicapptr; + u32 unused2; + u32 pcicfg2; + u32 g2ptocnt; /* +40 */ + u32 unused3[15]; + u32 g2pstatus; /* +80 */ + u32 g2pmask; + u32 pcisstatus; + u32 pcimask; + u32 p2gcfg; /* +90 */ + u32 p2gstatus; + u32 p2gmask; + u32 p2gccmd; + u32 unused4[24]; /* +a0 */ + u32 pbareqport; /* +100 */ + u32 pbacfg; + u32 pbastatus; + u32 pbamask; + u32 pbabm; /* +110 */ + u32 pbacreq; + u32 pbacgnt; + u32 pbacstate; + u64 g2pmgbase[3]; /* +120 */ + u64 g2piogbase; + u32 g2pmmask[3]; /* +140 */ + u32 g2piomask; + u64 g2pmpbase[3]; /* +150 */ + u64 g2piopbase; + u32 pciccfg; /* +170 */ + u32 pcicstatus; + u32 pcicmask; + u32 unused5; + u64 p2gmgbase[3]; /* +180 */ + u64 p2giogbase; + u32 g2pcfgadrs; /* +1a0 */ + u32 g2pcfgdata; + u32 unused6[8]; + u32 g2pintack; + u32 g2pspc; + u32 unused7[12]; /* +1d0 */ + u64 pdmca; /* +200 */ + u64 pdmga; + u64 pdmpa; + u64 pdmctr; + u64 pdmcfg; /* +220 */ + u64 pdmsts; +}; + +/* bits for PCICMD */ +/* see PCI_COMMAND_XXX in linux/pci_regs.h */ + +/* bits for PCISTAT */ +/* see PCI_STATUS_XXX in linux/pci_regs.h */ + +/* bits for IOBA/MBA */ +/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */ + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */ +#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4927_PCIC_PBACFG_FIXPA 0x00000008 +#define TX4927_PCIC_PBACFG_RPBA 0x00000004 +#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for PBASTATUS/PBAMASK */ +#define TX4927_PCIC_PBASTATUS_ALL 0x00000001 +#define TX4927_PCIC_PBASTATUS_BM 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL +#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL + +/* bits for G2PIOGBASE */ +#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL +#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8 +#define TX4927_PCIC_PCICSTATUS_PME 0x00000400 +#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200 +#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100 +#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080 +#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020 +#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010 +#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008 +#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002 +#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001 + +/* bits for PCICCFG */ +#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 +#define TX4927_PCIC_PCICCFG_HRST 0x00000800 +#define TX4927_PCIC_PCICCFG_SRST 0x00000400 +#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) +#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100 +#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080 +#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040 +#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020 +#define TX4927_PCIC_PCICCFG_TCAR 0x00000010 +#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL +#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL +#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL + +/* bits for P2GIOGBASE */ +#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL +#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL +#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL + +#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* bits for PDMCFG */ +#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000 +#define TX4927_PCIC_PDMCFG_EXFER 0x00100000 +#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800 +#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11) +#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400 +#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200 +#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100 +#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080 +#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040 +#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020 +#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c +#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 +#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 +#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 +#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002 +#define TX4927_PCIC_PDMCFG_CHRST 0x00000001 + +/* bits for PDMSTS */ +#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 +#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 +#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 +#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000 +#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800 +#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400 +#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200 +#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100 +#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080 +#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040 +#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020 +#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008 +#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004 +#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002 +#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001 +#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0 +#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f + +struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( + struct pci_controller *channel); +void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, + struct pci_controller *channel, int extarb); +void tx4927_report_pcic_status(void); + +#endif /* __ASM_TXX9_TX4927PCIC_H */ diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h index 7f9cfef1c6d2..0bb891993b08 100644 --- a/include/asm-mips/txx9/tx4938.h +++ b/include/asm-mips/txx9/tx4938.h @@ -12,6 +12,9 @@ #ifndef __ASM_TXX9_TX4938_H #define __ASM_TXX9_TX4938_H +/* some controllers are compatible with 4927 */ +#include + #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) #define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) @@ -51,9 +54,6 @@ #define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) #define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) -#ifdef __ASSEMBLY__ -#define _CONST64(c) c -#else #define _CONST64(c) c##ull #include @@ -113,68 +113,6 @@ struct tx4938_dma_reg { endian_def_l2(unused0, mcr); }; -struct tx4938_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmctr; - volatile unsigned long long pdmcfg; /* +220 */ - volatile unsigned long long pdmsts; -}; - struct tx4938_aclc_reg { volatile unsigned long acctlen; volatile unsigned long acctldis; @@ -262,18 +200,18 @@ struct tx4938_sramc_reg { }; struct tx4938_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; - volatile unsigned long long unused3; - volatile unsigned long long jmpadr; + u64 ccfg; + u64 crir; + u64 pcfg; + u64 toea; + u64 clkctr; + u64 unused0; + u64 garbc; + u64 unused1; + u64 unused2; + u64 ramp; + u64 unused3; + u64 jmpadr; }; #undef endian_def_l2 @@ -282,8 +220,6 @@ struct tx4938_ccfg_reg { #undef endian_def_b2s #undef endian_def_b4 -#endif /* __ASSEMBLY__ */ - /* * NDFMC */ @@ -360,7 +296,7 @@ struct tx4938_ccfg_reg { #define TX4938_CCFG_BEOW 0x00010000 #define TX4938_CCFG_WR 0x00008000 #define TX4938_CCFG_TOE 0x00004000 -#define TX4938_CCFG_PCIXARB 0x00002000 +#define TX4938_CCFG_PCIARB 0x00002000 #define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 #define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) #define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) @@ -436,110 +372,6 @@ struct tx4938_ccfg_reg { #define TX4938_CLKCTR_SIO0RST 0x00000002 #define TX4938_CLKCTR_SIO1RST 0x00000001 -/* bits for G2PSTATUS/G2PMASK */ -#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 -#define TX4938_PCIC_PBACFG_RPBA 0x00000004 -#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 -#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 -#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 -#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 -#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 -#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 -#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 -#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 -#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 -#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 - -/* bits for PCICCFG */ -#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 -#define TX4938_PCIC_PCICCFG_HRST 0x00000800 -#define TX4938_PCIC_PCICCFG_SRST 0x00000400 -#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) -#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 -#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 -#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 -#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 -#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 -#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) - -/* bits for PDMCFG */ -#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 -#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 -#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 -#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) -#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 -#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 -#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 -#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 -#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 -#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 -#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c -#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 -#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 -#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 -#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 -#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 - -/* bits for PDMSTS */ -#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 -#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 -#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 -#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 -#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 -#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 -#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 -#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 -#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 -#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 -#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 -#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 -#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 -#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 -#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 -#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 -#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f - /* * DMA */ @@ -595,15 +427,15 @@ struct tx4938_ccfg_reg { #define TX4938_DMA_CSR_DESERR 0x00000002 #define TX4938_DMA_CSR_SORERR 0x00000001 -#ifndef __ASSEMBLY__ - #define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) #define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) #define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) #define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) -#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) -#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) -#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) +#define tx4938_pcicptr tx4927_pcicptr +#define tx4938_pcic1ptr \ + ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG) +#define tx4938_ccfgptr \ + ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG) #define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) #define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) #define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) @@ -611,17 +443,25 @@ struct tx4938_ccfg_reg { #define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) -#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) -#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) +#define TX4938_REV_PCODE() \ + ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16) + +#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits) +#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits) +#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) #define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) #define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) +#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)]) #define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) #define TX4938_EBUSC_SIZE(ch) \ (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) - -#endif /* !__ASSEMBLY__ */ +int tx4938_report_pciclk(void); +void tx4938_report_pci1clk(void); +int tx4938_pciclk66_setup(void); +struct pci_dev; +int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); #endif -- cgit v1.2.3 From edcaf1a6a77315562e9781245cc8e028c9a921dc Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 11 Jul 2008 23:27:54 +0900 Subject: [MIPS] TXx9: Make single kernel can support multiple boards Make single kernel can be used on RBTX4927/37/38. Also make some SoC-specific code independent from board-specific code. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 67 +------------- arch/mips/Makefile | 21 ++--- arch/mips/pci/Makefile | 9 +- arch/mips/pci/fixup-jmr3927.c | 8 +- arch/mips/pci/fixup-rbtx4927.c | 8 +- arch/mips/pci/fixup-rbtx4938.c | 11 +-- arch/mips/txx9/Kconfig | 82 ++++++++++++++++- arch/mips/txx9/generic/Makefile | 4 +- arch/mips/txx9/generic/irq_tx4927.c | 33 +------ arch/mips/txx9/generic/irq_tx4938.c | 31 +------ arch/mips/txx9/generic/pci.c | 11 +++ arch/mips/txx9/generic/setup.c | 169 ++++++++++++++++++++++++++++++++++++ arch/mips/txx9/jmr3927/Makefile | 2 +- arch/mips/txx9/jmr3927/init.c | 57 ------------ arch/mips/txx9/jmr3927/irq.c | 45 +++++----- arch/mips/txx9/jmr3927/prom.c | 46 +++------- arch/mips/txx9/jmr3927/setup.c | 54 +++++------- arch/mips/txx9/rbtx4927/irq.c | 57 ++++++------ arch/mips/txx9/rbtx4927/prom.c | 52 +---------- arch/mips/txx9/rbtx4927/setup.c | 78 ++++++++--------- arch/mips/txx9/rbtx4938/irq.c | 48 ++++++---- arch/mips/txx9/rbtx4938/prom.c | 49 +---------- arch/mips/txx9/rbtx4938/setup.c | 64 +++++--------- include/asm-mips/txx9/generic.h | 18 ++++ include/asm-mips/txx9/jmr3927.h | 5 ++ include/asm-mips/txx9/rbtx4927.h | 13 ++- include/asm-mips/txx9/rbtx4938.h | 36 ++------ include/asm-mips/txx9/tx4927.h | 19 ++-- include/asm-mips/txx9/tx4938.h | 8 +- 29 files changed, 520 insertions(+), 585 deletions(-) delete mode 100644 arch/mips/txx9/jmr3927/init.c (limited to 'include') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2ea6fff88811..72baa1a70fcb 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -550,66 +550,11 @@ config SNI_RM Technology and now in turn merged with Fujitsu. Say Y here to support this machine type. -config TOSHIBA_JMR3927 - bool "Toshiba JMR-TX3927 board" - select CEVT_TXX9 - select DMA_NONCOHERENT - select HW_HAS_PCI - select MIPS_TX3927 - select IRQ_TXX9 - select SWAP_IO_SPACE - select SYS_HAS_CPU_TX39XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_BIG_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ - select GPIO_TXX9 +config MACH_TX39XX + bool "Toshiba TX39 series based machines" -config TOSHIBA_RBTX4927 - bool "Toshiba RBTX49[23]7 board" - select CEVT_R4K - select CSRC_R4K - select CEVT_TXX9 - select DMA_NONCOHERENT - select HAS_TXX9_SERIAL - select HW_HAS_PCI - select IRQ_CPU - select IRQ_TXX9 - select PCI_TX4927 - select SWAP_IO_SPACE - select SYS_HAS_CPU_TX49XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_KGDB - select GENERIC_HARDIRQS_NO__DO_IRQ - help - This Toshiba board is based on the TX4927 processor. Say Y here to - support this machine type - -config TOSHIBA_RBTX4938 - bool "Toshiba RBTX4938 board" - select CEVT_R4K - select CSRC_R4K - select CEVT_TXX9 - select DMA_NONCOHERENT - select HAS_TXX9_SERIAL - select HW_HAS_PCI - select IRQ_CPU - select IRQ_TXX9 - select PCI_TX4927 - select SWAP_IO_SPACE - select SYS_HAS_CPU_TX49XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_KGDB - select GENERIC_HARDIRQS_NO__DO_IRQ - select GPIO_TXX9 - help - This Toshiba board is based on the TX4938 processor. Say Y here to - support this machine type +config MACH_TX49XX + bool "Toshiba TX49 series based machines" config WR_PPMC bool "Wind River PPMC board" @@ -887,10 +832,6 @@ config PCI_GT64XXX_PCI0 config NO_EXCEPT_FILL bool -config MIPS_TX3927 - bool - select HAS_TXX9_SERIAL - config MIPS_RM9122 bool select SERIAL_RM9000 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 8e1e49c5186b..d319cd624135 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -550,30 +550,31 @@ load-$(CONFIG_SNI_RM) += 0xffffffff80030000 endif all-$(CONFIG_SNI_RM) := vmlinux.ecoff +# +# Common TXx9 +# +core-$(CONFIG_MACH_TX39XX) += arch/mips/txx9/generic/ +cflags-$(CONFIG_MACH_TX39XX) += -Iinclude/asm-mips/mach-jmr3927 +load-$(CONFIG_MACH_TX39XX) += 0xffffffff80050000 +core-$(CONFIG_MACH_TX49XX) += arch/mips/txx9/generic/ +cflags-$(CONFIG_MACH_TX49XX) += -Iinclude/asm-mips/mach-tx49xx +load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000 + # # Toshiba JMR-TX3927 board # -core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ \ - arch/mips/txx9/generic/ -cflags-$(CONFIG_TOSHIBA_JMR3927) += -Iinclude/asm-mips/mach-jmr3927 -load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 +core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ # # Toshiba RBTX4927 board or # Toshiba RBTX4937 board # core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/generic/ -cflags-$(CONFIG_TOSHIBA_RBTX4927) += -Iinclude/asm-mips/mach-tx49xx -load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 # # Toshiba RBTX4938 board # core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ -core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/generic/ -cflags-$(CONFIG_TOSHIBA_RBTX4938) += -Iinclude/asm-mips/mach-tx49xx -load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000 cflags-y += -Iinclude/asm-mips/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 908764878ac8..875b643438c0 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -11,11 +11,10 @@ obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o obj-$(CONFIG_MIPS_MSC) += ops-msc.o obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o -obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o +obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o -obj-$(CONFIG_PCI_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o # @@ -44,8 +43,10 @@ obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o -obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o pci-tx4927.o pci-tx4938.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o pci-tx4938.o +obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o +obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o +obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index d5edaf21e088..0f1069527cba 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -31,7 +31,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; @@ -77,9 +77,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) irq = JMR3927_IRQ_ETHER0; return irq; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index abab4852d158..321db265829c 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -36,7 +36,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; @@ -71,9 +71,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } return irq; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c index 39c995830384..a80579af609b 100644 --- a/arch/mips/pci/fixup-rbtx4938.c +++ b/arch/mips/pci/fixup-rbtx4938.c @@ -13,7 +13,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { int irq = tx4938_pcic1_map_irq(dev, slot); @@ -51,12 +51,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } return irq; } - -/* - * Do platform specific device initialization at pci_enable_device() time - */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig index b8cdb192543a..b92a134ef124 100644 --- a/arch/mips/txx9/Kconfig +++ b/arch/mips/txx9/Kconfig @@ -1,11 +1,89 @@ +config TOSHIBA_JMR3927 + bool "Toshiba JMR-TX3927 board" + depends on MACH_TX39XX + select SOC_TX3927 + +config TOSHIBA_RBTX4927 + bool "Toshiba RBTX49[23]7 board" + depends on MACH_TX49XX + select SOC_TX4927 + help + This Toshiba board is based on the TX4927 processor. Say Y here to + support this machine type + +config TOSHIBA_RBTX4938 + bool "Toshiba RBTX4938 board" + depends on MACH_TX49XX + select SOC_TX4938 + help + This Toshiba board is based on the TX4938 processor. Say Y here to + support this machine type + +config SOC_TX3927 + bool + select CEVT_TXX9 + select DMA_NONCOHERENT + select HAS_TXX9_SERIAL + select HW_HAS_PCI + select IRQ_TXX9 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX39XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + select GPIO_TXX9 + +config SOC_TX4927 + bool + select CEVT_R4K + select CSRC_R4K + select CEVT_TXX9 + select DMA_NONCOHERENT + select HAS_TXX9_SERIAL + select HW_HAS_PCI + select IRQ_CPU + select IRQ_TXX9 + select PCI_TX4927 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX49XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_KGDB + select GENERIC_HARDIRQS_NO__DO_IRQ + select GPIO_TXX9 + +config SOC_TX4938 + bool + select CEVT_R4K + select CSRC_R4K + select CEVT_TXX9 + select DMA_NONCOHERENT + select HAS_TXX9_SERIAL + select HW_HAS_PCI + select IRQ_CPU + select IRQ_TXX9 + select PCI_TX4927 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX49XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_KGDB + select GENERIC_HARDIRQS_NO__DO_IRQ + select GPIO_TXX9 + config TOSHIBA_FPCIB0 bool "FPCIB0 Backplane Support" - depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + depends on PCI && (MACH_TX39XX || MACH_TX49XX) select I8259 config PICMG_PCI_BACKPLANE_DEFAULT bool "Support for PICMG PCI Backplane" - depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + depends on PCI && (MACH_TX39XX || MACH_TX49XX) default y if !TOSHIBA_FPCIB0 if TOSHIBA_RBTX4938 diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile index b80b6e072284..668fdaad6448 100644 --- a/arch/mips/txx9/generic/Makefile +++ b/arch/mips/txx9/generic/Makefile @@ -4,8 +4,8 @@ obj-y += setup.o obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o +obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o +obj-$(CONFIG_SOC_TX4938) += mem_tx4938.o irq_tx4938.o obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o obj-$(CONFIG_KGDB) += dbgio.o diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c index 685ecc2ed551..6377bd8a9050 100644 --- a/arch/mips/txx9/generic/irq_tx4927.c +++ b/arch/mips/txx9/generic/irq_tx4927.c @@ -26,39 +26,12 @@ #include #include #include -#include -#ifdef CONFIG_TOSHIBA_RBTX4927 -#include -#endif +#include void __init tx4927_irq_init(void) { mips_cpu_irq_init(); txx9_irq_init(TX4927_IRC_REG); - set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) /* cpu timer */ - do_IRQ(TX4927_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { /* tx4927 pic */ - int irq = txx9_irq(); -#ifdef CONFIG_TOSHIBA_RBTX4927 - if (irq == TX4927_IRQ_NEST_EXT_ON_PIC) - irq = toshiba_rbtx4927_irq_nested(irq); -#endif - if (unlikely(irq < 0)) { - spurious_interrupt(); - return; - } - do_IRQ(irq); - } else if (pending & STATUSF_IP0) /* user line 0 */ - do_IRQ(TX4927_IRQ_USER0); - else if (pending & STATUSF_IP1) /* user line 1 */ - do_IRQ(TX4927_IRQ_USER1); - else - spurious_interrupt(); + set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, + handle_simple_irq); } diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c index 0886d9138818..5fc86c9c9d2f 100644 --- a/arch/mips/txx9/generic/irq_tx4938.c +++ b/arch/mips/txx9/generic/irq_tx4938.c @@ -14,35 +14,12 @@ #include #include #include -#include -#include +#include -void __init -tx4938_irq_init(void) +void __init tx4938_irq_init(void) { mips_cpu_irq_init(); txx9_irq_init(TX4938_IRC_REG); - set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -int toshiba_rbtx4938_irq_nested(int irq); - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP7) - do_IRQ(TX4938_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { - int irq = txx9_irq(); - if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0)) - irq = toshiba_rbtx4938_irq_nested(irq); - if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); - } else if (pending & STATUSF_IP1) - do_IRQ(TX4938_IRQ_USER1); - else if (pending & STATUSF_IP0) - do_IRQ(TX4938_IRQ_USER0); + set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, + handle_simple_irq); } diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c index 8173faab99bb..0b92d8c13208 100644 --- a/arch/mips/txx9/generic/pci.c +++ b/arch/mips/txx9/generic/pci.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #ifdef CONFIG_TOSHIBA_FPCIB0 #include @@ -375,3 +376,13 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, #endif DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup); DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup); + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return txx9_board_vec->pci_map_irq(dev, slot, pin); +} diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 46a631177757..66ff74f80c6b 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -14,7 +14,16 @@ #include #include #include +#include +#include +#include +#include +#include +#include #include +#ifdef CONFIG_CPU_TX49XX +#include +#endif /* EBUSC settings of TX4927, etc. */ struct resource txx9_ce_res[8]; @@ -49,3 +58,163 @@ txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size) unsigned int txx9_master_clock; unsigned int txx9_cpu_clock; unsigned int txx9_gbus_clock; + + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "spi-baseclk")) + return (struct clk *)(txx9_gbus_clock / 2 / 4); + if (!strcmp(id, "imbus_clk")) + return (struct clk *)(txx9_gbus_clock / 2); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +extern struct txx9_board_vec jmr3927_vec; +extern struct txx9_board_vec rbtx4927_vec; +extern struct txx9_board_vec rbtx4937_vec; +extern struct txx9_board_vec rbtx4938_vec; + +/* board definitions */ +static struct txx9_board_vec *board_vecs[] __initdata = { +#ifdef CONFIG_TOSHIBA_JMR3927 + &jmr3927_vec, +#endif +#ifdef CONFIG_TOSHIBA_RBTX4927 + &rbtx4927_vec, + &rbtx4937_vec, +#endif +#ifdef CONFIG_TOSHIBA_RBTX4938 + &rbtx4938_vec, +#endif +}; +struct txx9_board_vec *txx9_board_vec __initdata; +static char txx9_system_type[32]; + +void __init prom_init_cmdline(void) +{ + int argc = (int)fw_arg0; + char **argv = (char **)fw_arg1; + int i; /* Always ignore the "-c" at argv[0] */ + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) + *arcs_cmdline = '\0'; + + for (i = 1; i < argc; i++) { + if (i != 1) + strcat(arcs_cmdline, " "); + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + int i; + +#ifdef CONFIG_CPU_TX39XX + mips_machtype = MACH_TOSHIBA_JMR3927; +#endif +#ifdef CONFIG_CPU_TX49XX + switch (TX4938_REV_PCODE()) { + case 0x4927: + mips_machtype = MACH_TOSHIBA_RBTX4927; + break; + case 0x4937: + mips_machtype = MACH_TOSHIBA_RBTX4937; + break; + case 0x4938: + mips_machtype = MACH_TOSHIBA_RBTX4938; + break; + } +#endif + for (i = 0; i < ARRAY_SIZE(board_vecs); i++) { + if (board_vecs[i]->type == mips_machtype) { + txx9_board_vec = board_vecs[i]; + strcpy(txx9_system_type, txx9_board_vec->system); + return txx9_board_vec->prom_init(); + } + } +} + +void __init prom_free_prom_memory(void) +{ +} + +const char *get_system_type(void) +{ + return txx9_system_type; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +/* wrappers */ +void __init plat_mem_setup(void) +{ + txx9_board_vec->mem_setup(); +} + +void __init arch_init_irq(void) +{ + txx9_board_vec->irq_setup(); +} + +void __init plat_time_init(void) +{ + txx9_board_vec->time_init(); +} + +static int __init _txx9_arch_init(void) +{ + if (txx9_board_vec->arch_init) + txx9_board_vec->arch_init(); + return 0; +} +arch_initcall(_txx9_arch_init); + +static int __init _txx9_device_init(void) +{ + if (txx9_board_vec->device_init) + txx9_board_vec->device_init(); + return 0; +} +device_initcall(_txx9_device_init); + +int (*txx9_irq_dispatch)(int pending); +asmlinkage void plat_irq_dispatch(void) +{ + int pending = read_c0_status() & read_c0_cause() & ST0_IM; + int irq = txx9_irq_dispatch(pending); + + if (likely(irq >= 0)) + do_IRQ(irq); + else + spurious_interrupt(); +} diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile index 5f83ea375225..ba292c945669 100644 --- a/arch/mips/txx9/jmr3927/Makefile +++ b/arch/mips/txx9/jmr3927/Makefile @@ -2,7 +2,7 @@ # Makefile for TOSHIBA JMR-TX3927 board # -obj-y += prom.o init.o irq.o setup.o +obj-y += prom.o irq.o setup.o obj-$(CONFIG_KGDB) += kgdb_io.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/jmr3927/init.c b/arch/mips/txx9/jmr3927/init.c deleted file mode 100644 index 1bbb5343baf4..000000000000 --- a/arch/mips/txx9/jmr3927/init.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * arch/mips/jmr3927/common/init.c - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -extern void __init prom_init_cmdline(void); - -const char *get_system_type(void) -{ - return "Toshiba" -#ifdef CONFIG_TOSHIBA_JMR3927 - " JMR_TX3927" -#endif - ; -} - -extern void puts(const char *cp); - -void __init prom_init(void) -{ -#ifdef CONFIG_TOSHIBA_JMR3927 - /* CCFG */ - if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) - puts("Warning: TX3927 TLB off\n"); -#endif - - prom_init_cmdline(); - add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); -} diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c index b97d22e15da6..070c9a115e57 100644 --- a/arch/mips/txx9/jmr3927/irq.c +++ b/arch/mips/txx9/jmr3927/irq.c @@ -39,6 +39,7 @@ #include #include +#include #include #if JMR3927_IRQ_END > NR_IRQS @@ -77,37 +78,30 @@ static void unmask_irq_ioc(unsigned int irq) (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); } -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long cp0_cause = read_c0_cause(); - int irq; - - if ((cp0_cause & CAUSEF_IP7) == 0) - return; - irq = (cp0_cause >> CAUSEB_IP2) & 0x0f; - - do_IRQ(irq + JMR3927_IRQ_IRC); -} - -static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) +static int jmr3927_ioc_irqroute(void) { unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); int i; for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { - if (istat & (1 << i)) { - irq = JMR3927_IRQ_IOC + i; - do_IRQ(irq); - } + if (istat & (1 << i)) + return JMR3927_IRQ_IOC + i; } - return IRQ_HANDLED; + return -1; } -static struct irqaction ioc_action = { - .handler = jmr3927_ioc_interrupt, - .mask = CPU_MASK_NONE, - .name = "IOC", -}; +static int jmr3927_irq_dispatch(int pending) +{ + int irq; + + if ((pending & CAUSEF_IP7) == 0) + return -1; + irq = (pending >> CAUSEB_IP2) & 0x0f; + irq += JMR3927_IRQ_IRC; + if (irq == JMR3927_IRQ_IOCINT) + irq = jmr3927_ioc_irqroute(); + return irq; +} #ifdef CONFIG_PCI static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) @@ -127,8 +121,9 @@ static struct irqaction pcierr_action = { static void __init jmr3927_irq_init(void); -void __init arch_init_irq(void) +void __init jmr3927_irq_setup(void) { + txx9_irq_dispatch = jmr3927_irq_dispatch; /* Now, interrupt control disabled, */ /* all IRC interrupts are masked, */ /* all IRC interrupt mode are Low Active. */ @@ -146,7 +141,7 @@ void __init arch_init_irq(void) jmr3927_irq_init(); /* setup IOC interrupt 1 (PCI, MODEM) */ - setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); + set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); #ifdef CONFIG_PCI setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); diff --git a/arch/mips/txx9/jmr3927/prom.c b/arch/mips/txx9/jmr3927/prom.c index 8bc1049b622e..2cadb423face 100644 --- a/arch/mips/txx9/jmr3927/prom.c +++ b/arch/mips/txx9/jmr3927/prom.c @@ -35,42 +35,10 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include #include -#include - #include -#include - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - int prom_argc = fw_arg0; - char **prom_argv = (char **) fw_arg1; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; -} - -void __init prom_free_prom_memory(void) -{ -} +#include +#include #define TIMEOUT 0xffffff @@ -96,3 +64,13 @@ puts(const char *cp) prom_putchar('\r'); prom_putchar('\n'); } + +void __init jmr3927_prom_init(void) +{ + /* CCFG */ + if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) + puts("Warning: TX3927 TLB off\n"); + + prom_init_cmdline(); + add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); +} diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index baa8c8db9a94..128a4ae3e72e 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -34,15 +34,16 @@ #include #include #include -#include #include #ifdef CONFIG_SERIAL_TXX9 #include #endif +#include #include #include #include +#include #include #include #include @@ -83,7 +84,7 @@ static void jmr3927_machine_power_off(void) while (1); } -void __init plat_time_init(void) +static void __init jmr3927_time_init(void) { txx9_clockevent_init(TX3927_TMR_REG(0), TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0), @@ -97,7 +98,7 @@ void __init plat_time_init(void) extern char * __init prom_getcmdline(void); static void jmr3927_board_init(void); -void __init plat_mem_setup(void) +static void __init jmr3927_mem_setup(void) { char *argptr; @@ -233,6 +234,8 @@ static void __init tx3927_setup(void) { int i; + txx9_cpu_clock = JMR3927_CORECLK; + txx9_gbus_clock = JMR3927_GBUSCLK; /* SDRAMC are configured by PROM */ /* ROMC */ @@ -336,7 +339,6 @@ static int __init jmr3927_rtc_init(void) dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1); return IS_ERR(dev) ? PTR_ERR(dev) : 0; } -device_initcall(jmr3927_rtc_init); /* Watchdog support */ @@ -356,36 +358,22 @@ static int __init jmr3927_wdt_init(void) { return txx9_wdt_init(TX3927_TMR_REG(2)); } -device_initcall(jmr3927_wdt_init); -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)JMR3927_IMCLK; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) +static void __init jmr3927_device_init(void) { + jmr3927_rtc_init(); + jmr3927_wdt_init(); } -EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); +struct txx9_board_vec jmr3927_vec __initdata = { + .type = MACH_TOSHIBA_JMR3927, + .system = "Toshiba JMR_TX3927", + .prom_init = jmr3927_prom_init, + .mem_setup = jmr3927_mem_setup, + .irq_setup = jmr3927_irq_setup, + .time_init = jmr3927_time_init, + .device_init = jmr3927_device_init, +#ifdef CONFIG_PCI + .pci_map_irq = jmr3927_pci_map_irq, +#endif +}; diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c index bef1447aeed2..70f13211bc2a 100644 --- a/arch/mips/txx9/rbtx4927/irq.c +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -111,17 +111,10 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #include #include #include +#include +#include #include -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ - -#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC -#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) - static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); @@ -136,34 +129,25 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { #define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL #define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL -int toshiba_rbtx4927_irq_nested(int sw_irq) +static int toshiba_rbtx4927_irq_nested(int sw_irq) { u8 level3; level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; if (level3) - sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; + sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; return (sw_irq); } -static struct irqaction toshiba_rbtx4927_irq_ioc_action = { - .handler = no_action, - .flags = IRQF_SHARED, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4927_IOC_NAME -}; - static void __init toshiba_rbtx4927_irq_ioc_init(void) { int i; - for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) + for (i = RBTX4927_IRQ_IOC; + i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, handle_level_irq); - - setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, - &toshiba_rbtx4927_irq_ioc_action); + set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq); } static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) @@ -171,7 +155,7 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) unsigned char v; v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + v |= (1 << (irq - RBTX4927_IRQ_IOC)); writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); } @@ -180,15 +164,34 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) unsigned char v; v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + v &= ~(1 << (irq - RBTX4927_IRQ_IOC)); writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); mmiowb(); } -void __init arch_init_irq(void) + +static int rbtx4927_irq_dispatch(int pending) { - extern void tx4927_irq_init(void); + int irq; + + if (pending & STATUSF_IP7) /* cpu timer */ + irq = MIPS_CPU_IRQ_BASE + 7; + else if (pending & STATUSF_IP2) { /* tx4927 pic */ + irq = txx9_irq(); + if (irq == RBTX4927_IRQ_IOCINT) + irq = toshiba_rbtx4927_irq_nested(irq); + } else if (pending & STATUSF_IP0) /* user line 0 */ + irq = MIPS_CPU_IRQ_BASE + 0; + else if (pending & STATUSF_IP1) /* user line 1 */ + irq = MIPS_CPU_IRQ_BASE + 1; + else + irq = -1; + return irq; +} +void __init rbtx4927_irq_setup(void) +{ + txx9_irq_dispatch = rbtx4927_irq_dispatch; tx4927_irq_init(); toshiba_rbtx4927_irq_ioc_init(); /* Onboard 10M Ether: High Active */ diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c index 0020bbee838b..942e627d2dc1 100644 --- a/arch/mips/txx9/rbtx4927/prom.c +++ b/arch/mips/txx9/rbtx4927/prom.c @@ -30,62 +30,16 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include #include -#include -#include -#include +#include +#include -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; /* Always ignore the "-c" at argv[0] */ - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} - -void __init prom_init(void) +void __init rbtx4927_prom_init(void) { extern int tx4927_get_mem_size(void); - extern char* toshiba_name; int msize; prom_init_cmdline(); - - if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { - mips_machtype = MACH_TOSHIBA_RBTX4927; - toshiba_name = "TX4927"; - } else { - mips_machtype = MACH_TOSHIBA_RBTX4937; - toshiba_name = "TX4937"; - } - msize = tx4927_get_mem_size(); add_memory_region(0, msize << 20, BOOT_MEM_RAM); } - -void __init prom_free_prom_memory(void) -{ -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4927/RBTX4937"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index 86b870abc319..c3566c39c26c 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -49,7 +49,6 @@ #include #include #include -#include #include #include @@ -76,8 +75,6 @@ char *prom_getcmdline(void); static int tx4927_ccfg_toeon = 1; -char *toshiba_name = ""; - #ifdef CONFIG_PCI static void __init tx4927_pci_setup(void) { @@ -171,15 +168,15 @@ static void __init tx4937_pci_setup(void) } } -static int __init rbtx4927_arch_init(void) +static void __init rbtx4927_arch_init(void) { if (mips_machtype == MACH_TOSHIBA_RBTX4937) tx4937_pci_setup(); else tx4927_pci_setup(); - return 0; } -arch_initcall(rbtx4927_arch_init); +#else +#define rbtx4927_arch_init NULL #endif /* CONFIG_PCI */ static void __noreturn wait_forever(void) @@ -223,14 +220,12 @@ void toshiba_rbtx4927_power_off(void) /* no return */ } -void __init plat_mem_setup(void) +static void __init rbtx4927_mem_setup(void) { int i; u32 cp0_config; char *argptr; - printk("CPU is %s\n", toshiba_name); - /* f/w leaves this on at startup */ clear_c0_status(ST0_ERL); @@ -323,7 +318,7 @@ void __init plat_mem_setup(void) req.iotype = UPIO_MEM; req.membase = (char *)(0xff1ff300 + i * 0x100); req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = TX4927_IRQ_PIC_BEG + 8 + i; + req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i); req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; req.uartclk = 50000000; early_serial_txx9_setup(&req); @@ -352,7 +347,7 @@ void __init plat_mem_setup(void) #endif } -void __init plat_time_init(void) +static void __init rbtx4927_time_init(void) { mips_hpt_frequency = txx9_cpu_clock / 2; if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) @@ -372,7 +367,6 @@ static int __init toshiba_rbtx4927_rtc_init(void) platform_device_register_simple("rtc-ds1742", -1, &res, 1); return IS_ERR(dev) ? PTR_ERR(dev) : 0; } -device_initcall(toshiba_rbtx4927_rtc_init); static int __init rbtx4927_ne_init(void) { @@ -391,7 +385,6 @@ static int __init rbtx4927_ne_init(void) res, ARRAY_SIZE(res)); return IS_ERR(dev) ? PTR_ERR(dev) : 0; } -device_initcall(rbtx4927_ne_init); /* Watchdog support */ @@ -411,36 +404,37 @@ static int __init rbtx4927_wdt_init(void) { return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); } -device_initcall(rbtx4927_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)50000000; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); -void clk_disable(struct clk *clk) +static void __init rbtx4927_device_init(void) { + toshiba_rbtx4927_rtc_init(); + rbtx4927_ne_init(); + rbtx4927_wdt_init(); } -EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); +struct txx9_board_vec rbtx4927_vec __initdata = { + .type = MACH_TOSHIBA_RBTX4927, + .system = "Toshiba RBTX4927", + .prom_init = rbtx4927_prom_init, + .mem_setup = rbtx4927_mem_setup, + .irq_setup = rbtx4927_irq_setup, + .time_init = rbtx4927_time_init, + .device_init = rbtx4927_device_init, + .arch_init = rbtx4927_arch_init, +#ifdef CONFIG_PCI + .pci_map_irq = rbtx4927_pci_map_irq, +#endif +}; +struct txx9_board_vec rbtx4937_vec __initdata = { + .type = MACH_TOSHIBA_RBTX4937, + .system = "Toshiba RBTX4937", + .prom_init = rbtx4927_prom_init, + .mem_setup = rbtx4927_mem_setup, + .irq_setup = rbtx4927_irq_setup, + .time_init = rbtx4927_time_init, + .device_init = rbtx4927_device_init, + .arch_init = rbtx4927_arch_init, +#ifdef CONFIG_PCI + .pci_map_irq = rbtx4927_pci_map_irq, +#endif +}; diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c index f4984820251a..3971a061657a 100644 --- a/arch/mips/txx9/rbtx4938/irq.c +++ b/arch/mips/txx9/rbtx4938/irq.c @@ -66,6 +66,8 @@ IRQ Device */ #include #include +#include +#include #include static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); @@ -80,26 +82,17 @@ static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { .unmask = toshiba_rbtx4938_irq_ioc_enable, }; -int -toshiba_rbtx4938_irq_nested(int sw_irq) +static int toshiba_rbtx4938_irq_nested(int sw_irq) { u8 level3; level3 = readb(rbtx4938_imstat_addr); if (level3) /* must use fls so onboard ATA has priority */ - sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; - + sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1; return sw_irq; } -static struct irqaction toshiba_rbtx4938_irq_ioc_action = { - .handler = no_action, - .flags = 0, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4938_IOC_NAME, -}; - /**********************************************************************************/ /* Functions for ioc */ /**********************************************************************************/ @@ -108,13 +101,12 @@ toshiba_rbtx4938_irq_ioc_init(void) { int i; - for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) + for (i = RBTX4938_IRQ_IOC; + i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++) set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, handle_level_irq); - setup_irq(RBTX4938_IRQ_IOCINT, - &toshiba_rbtx4938_irq_ioc_action); + set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq); } static void @@ -123,7 +115,7 @@ toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) unsigned char v; v = readb(rbtx4938_imask_addr); - v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + v |= (1 << (irq - RBTX4938_IRQ_IOC)); writeb(v, rbtx4938_imask_addr); mmiowb(); } @@ -134,15 +126,33 @@ toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) unsigned char v; v = readb(rbtx4938_imask_addr); - v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + v &= ~(1 << (irq - RBTX4938_IRQ_IOC)); writeb(v, rbtx4938_imask_addr); mmiowb(); } -void __init arch_init_irq(void) +static int rbtx4938_irq_dispatch(int pending) { - extern void tx4938_irq_init(void); + int irq; + + if (pending & STATUSF_IP7) + irq = MIPS_CPU_IRQ_BASE + 7; + else if (pending & STATUSF_IP2) { + irq = txx9_irq(); + if (irq == RBTX4938_IRQ_IOCINT) + irq = toshiba_rbtx4938_irq_nested(irq); + } else if (pending & STATUSF_IP1) + irq = MIPS_CPU_IRQ_BASE + 0; + else if (pending & STATUSF_IP0) + irq = MIPS_CPU_IRQ_BASE + 1; + else + irq = -1; + return irq; +} +void __init rbtx4938_irq_setup(void) +{ + txx9_irq_dispatch = rbtx4938_irq_dispatch; /* Now, interrupt control disabled, */ /* all IRC interrupts are masked, */ /* all IRC interrupt mode are Low Active. */ diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c index 134fcc2dc7d2..fbb37458ddb2 100644 --- a/arch/mips/txx9/rbtx4938/prom.c +++ b/arch/mips/txx9/rbtx4938/prom.c @@ -11,34 +11,12 @@ */ #include -#include -#include #include - -#include #include -#include - -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} +#include +#include -void __init prom_init(void) +void __init rbtx4938_prom_init(void) { extern int tx4938_get_mem_size(void); int msize; @@ -48,25 +26,4 @@ void __init prom_init(void) msize = tx4938_get_mem_size(); add_memory_region(0, msize << 20, BOOT_MEM_RAM); - - return; -} - -void __init prom_free_prom_memory(void) -{ -} - -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ - return; -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4938"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); } diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index 144d2cada820..8306ba333dda 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -147,9 +146,9 @@ static void __init rbtx4938_pci_setup(void) #define SEEPROM3_CS 1 /* IOC */ #define SRTC_CS 2 /* IOC */ -#ifdef CONFIG_PCI static int __init rbtx4938_ethaddr_init(void) { +#ifdef CONFIG_PCI unsigned char dat[17]; unsigned char sum; int i; @@ -179,10 +178,9 @@ static int __init rbtx4938_ethaddr_init(void) platform_device_add(pdev)) platform_device_put(pdev); } +#endif /* CONFIG_PCI */ return 0; } -device_initcall(rbtx4938_ethaddr_init); -#endif /* CONFIG_PCI */ static void __init rbtx4938_spi_setup(void) { @@ -366,7 +364,7 @@ void __init tx4938_board_setup(void) #endif } -void __init plat_time_init(void) +static void __init rbtx4938_time_init(void) { mips_hpt_frequency = txx9_cpu_clock / 2; if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS) @@ -375,7 +373,7 @@ void __init plat_time_init(void) txx9_gbus_clock / 2); } -void __init plat_mem_setup(void) +static void __init rbtx4938_mem_setup(void) { unsigned long long pcfg; char *argptr; @@ -496,7 +494,6 @@ static int __init rbtx4938_ne_init(void) res, ARRAY_SIZE(res)); return IS_ERR(dev) ? PTR_ERR(dev) : 0; } -device_initcall(rbtx4938_ne_init); /* GPIO support */ @@ -587,14 +584,13 @@ static int __init rbtx4938_spi_init(void) return 0; } -static int __init rbtx4938_arch_init(void) +static void __init rbtx4938_arch_init(void) { txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); gpiochip_add(&rbtx4938_spi_gpio_chip); rbtx4938_pci_setup(); - return rbtx4938_spi_init(); + rbtx4938_spi_init(); } -arch_initcall(rbtx4938_arch_init); /* Watchdog support */ @@ -614,38 +610,24 @@ static int __init rbtx4938_wdt_init(void) { return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); } -device_initcall(rbtx4938_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "spi-baseclk")) - return (struct clk *)(txx9_gbus_clock / 2 / 4); - if (!strcmp(id, "imbus_clk")) - return (struct clk *)(txx9_gbus_clock / 2); - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) +static void __init rbtx4938_device_init(void) { - return (unsigned long)clk; + rbtx4938_ethaddr_init(); + rbtx4938_ne_init(); + rbtx4938_wdt_init(); } -EXPORT_SYMBOL(clk_get_rate); -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); +struct txx9_board_vec rbtx4938_vec __initdata = { + .type = MACH_TOSHIBA_RBTX4938, + .system = "Toshiba RBTX4938", + .prom_init = rbtx4938_prom_init, + .mem_setup = rbtx4938_mem_setup, + .irq_setup = rbtx4938_irq_setup, + .time_init = rbtx4938_time_init, + .device_init = rbtx4938_device_init, + .arch_init = rbtx4938_arch_init, +#ifdef CONFIG_PCI + .pci_map_irq = rbtx4938_pci_map_irq, +#endif +}; diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h index 2ff6c2002204..6cd147764f19 100644 --- a/include/asm-mips/txx9/generic.h +++ b/include/asm-mips/txx9/generic.h @@ -20,4 +20,22 @@ extern unsigned int txx9_master_clock; extern unsigned int txx9_cpu_clock; extern unsigned int txx9_gbus_clock; +struct pci_dev; +struct txx9_board_vec { + unsigned long type; + const char *system; + void (*prom_init)(void); + void (*mem_setup)(void); + void (*irq_setup)(void); + void (*time_init)(void); + void (*arch_init)(void); + void (*device_init)(void); +#ifdef CONFIG_PCI + int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); +#endif +}; +extern struct txx9_board_vec *txx9_board_vec; +extern int (*txx9_irq_dispatch)(int pending); +void prom_init_cmdline(void); + #endif /* __ASM_TXX9_GENERIC_H */ diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h index 29e54981a86e..d6eb1b6a54eb 100644 --- a/include/asm-mips/txx9/jmr3927.h +++ b/include/asm-mips/txx9/jmr3927.h @@ -174,4 +174,9 @@ * INT[3:0] */ +void jmr3927_prom_init(void); +void jmr3927_irq_setup(void); +struct pci_dev; +int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); + #endif /* __ASM_TXX9_JMR3927_H */ diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h index 5b6f488b1b3c..bf194589216f 100644 --- a/include/asm-mips/txx9/rbtx4927.h +++ b/include/asm-mips/txx9/rbtx4927.h @@ -46,12 +46,16 @@ #define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB) #define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA) -#define RBTX4927_IRQ_IOC (TX4927_IRQ_PIC_BEG + TX4927_NUM_IR) +#define RBTX4927_NR_IRQ_IOC 8 /* IOC */ + +#define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR) #define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID) #define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC) #define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB) #define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA) +#define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1)) + #ifdef CONFIG_PCI #define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO #else @@ -65,8 +69,11 @@ #define RBTX4927_SW_RESET_ENABLE_SET 0x01 #define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET) -#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) +#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) -int toshiba_rbtx4927_irq_nested(int sw_irq); +void rbtx4927_prom_init(void); +void rbtx4927_irq_setup(void); +struct pci_dev; +int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); #endif /* __ASM_TXX9_RBTX4927_H */ diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h index 8450f735d056..2f5d5e705a41 100644 --- a/include/asm-mips/txx9/rbtx4938.h +++ b/include/asm-mips/txx9/rbtx4938.h @@ -101,35 +101,12 @@ * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new * IRQ hardware is supported. */ -#define RBTX4938_NR_IRQ_LOCAL 8 -#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ #define RBTX4938_NR_IRQ_IOC 8 -#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) -#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) -#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) -#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) -#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) -#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) - -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ -#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG -#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) -#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) +#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE +#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR) #define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) -#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) -#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) -#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) -#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) #define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) #define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) #define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) @@ -157,11 +134,16 @@ /* IOC (PCI, etc) */ -#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) +#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0)) /* Onboard 10M Ether */ -#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) +#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1)) #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) #define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) +void rbtx4938_prom_init(void); +void rbtx4938_irq_setup(void); +struct pci_dev; +int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); + #endif /* __ASM_TXX9_RBTX4938_H */ diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h index c0382fd2ae7f..46d60afc038b 100644 --- a/include/asm-mips/txx9/tx4927.h +++ b/include/asm-mips/txx9/tx4927.h @@ -32,20 +32,6 @@ #include #include -#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) - - -#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) -#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) -#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) -#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) - -#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) - #define TX4927_SDRAMC_REG 0xff1f8000 #define TX4927_EBUSC_REG 0xff1f9000 #define TX4927_PCIC_REG 0xff1fd000 @@ -54,10 +40,14 @@ #define TX4927_NR_TMR 3 #define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) +#define TX4927_IR_INT(n) (2 + (n)) +#define TX4927_IR_SIO(n) (8 + (n)) #define TX4927_IR_PCIC 16 #define TX4927_IR_PCIERR 22 #define TX4927_NUM_IR 32 +#define TX4927_IRC_INT 2 /* IP[2] in Status register */ + struct tx4927_sdramc_reg { volatile unsigned long long cr[4]; volatile unsigned long long unused0[4]; @@ -224,5 +214,6 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new) int tx4927_report_pciclk(void); int tx4927_pciclk66_setup(void); +void tx4927_irq_init(void); #endif /* __ASM_TXX9_TX4927_H */ diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h index 0bb891993b08..12de68a4c10a 100644 --- a/include/asm-mips/txx9/tx4938.h +++ b/include/asm-mips/txx9/tx4938.h @@ -18,11 +18,6 @@ #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) #define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) -#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG - -#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) -#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) - #define TX4938_PCIIO_0 0x10000000 #define TX4938_PCIIO_1 0x01010000 #define TX4938_PCIMEM_0 0x08000000 @@ -271,6 +266,8 @@ struct tx4938_ccfg_reg { #define TX4938_IR_ETH0 TX4938_IR_INT(4) #define TX4938_IR_ETH1 TX4938_IR_INT(3) +#define TX4938_IRC_INT 2 /* IP[2] in Status register */ + /* * CCFG */ @@ -463,5 +460,6 @@ void tx4938_report_pci1clk(void); int tx4938_pciclk66_setup(void); struct pci_dev; int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); +void tx4938_irq_init(void); #endif -- cgit v1.2.3 From efff4ae259b8f750ea426d3084007f85c0a15a85 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Fri, 11 Jul 2008 22:45:21 +0900 Subject: [MIPS] cmbvr4133: Remove support It cannot be built for a long time and nobody maintains it. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- arch/mips/Makefile | 6 - arch/mips/pci/Makefile | 1 - arch/mips/pci/fixup-vr4133.c | 194 ---------------------- arch/mips/vr41xx/Kconfig | 17 -- arch/mips/vr41xx/nec-cmbvr4133/Makefile | 8 - arch/mips/vr41xx/nec-cmbvr4133/init.c | 65 -------- arch/mips/vr41xx/nec-cmbvr4133/irq.c | 46 ------ arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c | 249 ----------------------------- arch/mips/vr41xx/nec-cmbvr4133/setup.c | 89 ----------- include/asm-mips/mach-vr41xx/irq.h | 3 - include/asm-mips/vr41xx/cmbvr4133.h | 56 ------- 11 files changed, 734 deletions(-) delete mode 100644 arch/mips/pci/fixup-vr4133.c delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/Makefile delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/init.c delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/irq.c delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/setup.c delete mode 100644 include/asm-mips/vr41xx/cmbvr4133.h (limited to 'include') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index d319cd624135..c4a3098a58c6 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -354,12 +354,6 @@ load-$(CONFIG_LASAT) += 0xffffffff80000000 core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ cflags-$(CONFIG_MACH_VR41XX) += -Iinclude/asm-mips/mach-vr41xx -# -# NEC VR4133 -# -core-$(CONFIG_NEC_CMBVR4133) += arch/mips/vr41xx/nec-cmbvr4133/ -load-$(CONFIG_NEC_CMBVR4133) += 0xffffffff80100000 - # # ZAO Networks Capcella (VR4131) # diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 875b643438c0..57e34cafa497 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_MIPS_MSC) += ops-msc.o obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o -obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c deleted file mode 100644 index 34e651bd2b5e..000000000000 --- a/arch/mips/pci/fixup-vr4133.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * arch/mips/pci/fixup-vr4133.c - * - * The NEC CMB-VR4133 Board specific PCI fixups. - * - * Author: Yoichi Yuasa and - * Alex Sapkov - * - * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Modified for support in 2.6 - * Author: Manish Lachwani (mlachwani@mvista.com) - * - */ -#include -#include -#include - -#include -#include -#include - -extern int vr4133_rockhopper; -extern void ali_m1535plus_init(struct pci_dev *dev); -extern void ali_m5229_init(struct pci_dev *dev); - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - /* - * We have to reset AMD PCnet adapter on Rockhopper since - * PMON leaves it enabled and generating interrupts. This leads - * to a lock if some PCI device driver later enables the IRQ line - * shared with PCnet and there is no AMD PCnet driver to catch its - * interrupts. - */ -#ifdef CONFIG_ROCKHOPPER - if (dev->vendor == PCI_VENDOR_ID_AMD && - dev->device == PCI_DEVICE_ID_AMD_LANCE) { - inl(pci_resource_start(dev, 0) + 0x18); - } -#endif - - /* - * we have to open the bridges' windows down to 0 because otherwise - * we cannot access ISA south bridge I/O registers that get mapped from - * 0. for example, 8259 PIC would be unaccessible without that - */ - if(dev->vendor == PCI_VENDOR_ID_INTEL && dev->device == PCI_DEVICE_ID_INTEL_S21152BB) { - pci_write_config_byte(dev, PCI_IO_BASE, 0); - if(dev->bus->number == 0) { - pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0); - } else { - pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 1); - } - } - - return 0; -} - -/* - * M1535 IRQ mapping - * Feel free to change this, although it shouldn't be needed - */ -#define M1535_IRQ_INTA 7 -#define M1535_IRQ_INTB 9 -#define M1535_IRQ_INTC 10 -#define M1535_IRQ_INTD 11 - -#define M1535_IRQ_USB 9 -#define M1535_IRQ_IDE 14 -#define M1535_IRQ_IDE2 15 -#define M1535_IRQ_PS2 12 -#define M1535_IRQ_RTC 8 -#define M1535_IRQ_FDC 6 -#define M1535_IRQ_AUDIO 5 -#define M1535_IRQ_COM1 4 -#define M1535_IRQ_COM2 4 -#define M1535_IRQ_IRDA 3 -#define M1535_IRQ_KBD 1 -#define M1535_IRQ_TMR 0 - -/* Rockhopper "slots" assignment; this is hard-coded ... */ -#define ROCKHOPPER_M5451_SLOT 1 -#define ROCKHOPPER_M1535_SLOT 2 -#define ROCKHOPPER_M5229_SLOT 11 -#define ROCKHOPPER_M5237_SLOT 15 -#define ROCKHOPPER_PMU_SLOT 12 -/* ... and hard-wired. */ -#define ROCKHOPPER_PCI1_SLOT 3 -#define ROCKHOPPER_PCI2_SLOT 4 -#define ROCKHOPPER_PCI3_SLOT 5 -#define ROCKHOPPER_PCI4_SLOT 6 -#define ROCKHOPPER_PCNET_SLOT 1 - -#define M1535_IRQ_MASK(n) (1 << (n)) - -#define M1535_IRQ_EDGE (M1535_IRQ_MASK(M1535_IRQ_TMR) | \ - M1535_IRQ_MASK(M1535_IRQ_KBD) | \ - M1535_IRQ_MASK(M1535_IRQ_COM1) | \ - M1535_IRQ_MASK(M1535_IRQ_COM2) | \ - M1535_IRQ_MASK(M1535_IRQ_IRDA) | \ - M1535_IRQ_MASK(M1535_IRQ_RTC) | \ - M1535_IRQ_MASK(M1535_IRQ_FDC) | \ - M1535_IRQ_MASK(M1535_IRQ_PS2)) - -#define M1535_IRQ_LEVEL (M1535_IRQ_MASK(M1535_IRQ_IDE) | \ - M1535_IRQ_MASK(M1535_IRQ_USB) | \ - M1535_IRQ_MASK(M1535_IRQ_INTA) | \ - M1535_IRQ_MASK(M1535_IRQ_INTB) | \ - M1535_IRQ_MASK(M1535_IRQ_INTC) | \ - M1535_IRQ_MASK(M1535_IRQ_INTD)) - -struct irq_map_entry { - u16 bus; - u8 slot; - u8 irq; -}; -static struct irq_map_entry int_map[] = { - {1, ROCKHOPPER_M5451_SLOT, M1535_IRQ_AUDIO}, /* Audio controller */ - {1, ROCKHOPPER_PCI1_SLOT, M1535_IRQ_INTD}, /* PCI slot #1 */ - {1, ROCKHOPPER_PCI2_SLOT, M1535_IRQ_INTC}, /* PCI slot #2 */ - {1, ROCKHOPPER_M5237_SLOT, M1535_IRQ_USB}, /* USB host controller */ - {1, ROCKHOPPER_M5229_SLOT, IDE_PRIMARY_IRQ}, /* IDE controller */ - {2, ROCKHOPPER_PCNET_SLOT, M1535_IRQ_INTD}, /* AMD Am79c973 on-board - ethernet */ - {2, ROCKHOPPER_PCI3_SLOT, M1535_IRQ_INTB}, /* PCI slot #3 */ - {2, ROCKHOPPER_PCI4_SLOT, M1535_IRQ_INTC} /* PCI slot #4 */ -}; - -static int pci_intlines[] = - { M1535_IRQ_INTA, M1535_IRQ_INTB, M1535_IRQ_INTC, M1535_IRQ_INTD }; - -/* Determine the Rockhopper IRQ line number for the PCI device */ -int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot) -{ - struct pci_bus *bus; - int i; - - bus = dev->bus; - if (bus == NULL) - return -1; - - for (i = 0; i < ARRAY_SIZE(int_map); i++) { - if (int_map[i].bus == bus->number && int_map[i].slot == slot) { - int line; - for (line = 0; line < 4; line++) - if (pci_intlines[line] == int_map[i].irq) - break; - if (line < 4) - return pci_intlines[(line + (pin - 1)) % 4]; - else - return int_map[i].irq; - } - } - return -1; -} - -#ifdef CONFIG_ROCKHOPPER -void i8259_init(void) -{ - init_i8259_irqs(); - - outb(0x00, 0x4d0); - outb(0x02, 0x4d1); /* USB IRQ9 is level */ -} -#endif - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - pci_probe_only = 1; - -#ifdef CONFIG_ROCKHOPPER - if( dev->bus->number == 1 && vr4133_rockhopper ) { - if(slot == ROCKHOPPER_PCI1_SLOT || slot == ROCKHOPPER_PCI2_SLOT) - dev->irq = CMBVR41XX_INTA_IRQ; - else - dev->irq = rockhopper_get_irq(dev, pin, slot); - } else - dev->irq = CMBVR41XX_INTA_IRQ; -#else - dev->irq = CMBVR41XX_INTA_IRQ; -#endif - - return dev->irq; -} - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, ali_m1535plus_init); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, ali_m5229_init); - - diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig index 559acc09c819..c1be6b37fb2a 100644 --- a/arch/mips/vr41xx/Kconfig +++ b/arch/mips/vr41xx/Kconfig @@ -23,16 +23,6 @@ config IBM_WORKPAD select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN -config NEC_CMBVR4133 - bool "NEC CMB-VR4133" - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select IRQ_CPU - select HW_HAS_PCI - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - config TANBAC_TB022X bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM" select CEVT_R4K @@ -73,13 +63,6 @@ config ZAO_CAPCELLA endchoice -config ROCKHOPPER - bool "Support for Rockhopper base board" - depends on NEC_CMBVR4133 - select PCI_VR41XX - select I8259 - select HAVE_STD_PC_SERIAL_PORT - choice prompt "Base board type" depends on TANBAC_TB022X diff --git a/arch/mips/vr41xx/nec-cmbvr4133/Makefile b/arch/mips/vr41xx/nec-cmbvr4133/Makefile deleted file mode 100644 index 5835cae54aca..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the NEC-CMBVR4133 -# - -obj-y := init.o setup.o - -obj-$(CONFIG_PCI) += m1535plus.o -obj-$(CONFIG_ROCKHOPPER) += irq.o diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c deleted file mode 100644 index 7c5e18ee2231..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/init.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * arch/mips/vr41xx/nec-cmbvr4133/init.c - * - * PROM library initialisation code for NEC CMB-VR4133 board. - * - * Author: Yoichi Yuasa and - * Jun Sun and - * Alex Sapkov - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for NEC-CMBVR4133 in 2.6 - * Manish Lachwani (mlachwani@mvista.com) - */ - -#ifdef CONFIG_ROCKHOPPER -#include -#include - -#define PCICONFDREG 0xaf000c14 -#define PCICONFAREG 0xaf000c18 - -void disable_pcnet(void) -{ - u32 data; - - /* - * Workaround for the bug in PMON on VR4133. PMON leaves - * AMD PCNet controller (on Rockhopper) initialized and running in - * bus master mode. We have do disable it before doing any - * further initialization. Or we get problems with PCI bus 2 - * and random lockups and crashes. - */ - - writel((2 << 16) | - (PCI_DEVFN(1, 0) << 8) | - (0 & 0xfc) | - 1UL, - PCICONFAREG); - - data = readl(PCICONFDREG); - - writel((2 << 16) | - (PCI_DEVFN(1, 0) << 8) | - (4 & 0xfc) | - 1UL, - PCICONFAREG); - - data = readl(PCICONFDREG); - - writel((2 << 16) | - (PCI_DEVFN(1, 0) << 8) | - (4 & 0xfc) | - 1UL, - PCICONFAREG); - - data &= ~4; - - writel(data, PCICONFDREG); -} -#endif - diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c deleted file mode 100644 index 7d2d076b0f54..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/mips/vr41xx/nec-cmbvr4133/irq.c - * - * Interrupt routines for the NEC CMB-VR4133 board. - * - * Author: Yoichi Yuasa and - * Alex Sapkov - * - * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for NEC-CMBVR4133 in 2.6 - * Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -extern int vr4133_rockhopper; - -static int i8259_get_irq_number(int irq) -{ - return i8259_irq(); -} - -void __init rockhopper_init_irq(void) -{ - int i; - - if(!vr4133_rockhopper) { - printk(KERN_ERR "Not a Rockhopper Board \n"); - return; - } - - vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH); - vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH); - vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number); -} diff --git a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c deleted file mode 100644 index 1341f3287d04..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c - * - * Initialize for ALi M1535+(included M5229 and M5237). - * - * Author: Yoichi Yuasa and - * Alex Sapkov - * - * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for NEC-CMBVR4133 in 2.6 - * Author: Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include - -#include -#include -#include - -#define CONFIG_PORT(port) ((port) ? 0x3f0 : 0x370) -#define DATA_PORT(port) ((port) ? 0x3f1 : 0x371) -#define INDEX_PORT(port) CONFIG_PORT(port) - -#define ENTER_CONFIG_MODE(port) \ - do { \ - outb_p(0x51, CONFIG_PORT(port)); \ - outb_p(0x23, CONFIG_PORT(port)); \ - } while(0) - -#define SELECT_LOGICAL_DEVICE(port, dev_no) \ - do { \ - outb_p(0x07, INDEX_PORT(port)); \ - outb_p((dev_no), DATA_PORT(port)); \ - } while(0) - -#define WRITE_CONFIG_DATA(port, index, data) \ - do { \ - outb_p((index), INDEX_PORT(port)); \ - outb_p((data), DATA_PORT(port)); \ - } while(0) - -#define EXIT_CONFIG_MODE(port) outb(0xbb, CONFIG_PORT(port)) - -#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18) -#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14) - -#ifdef CONFIG_BLK_DEV_FD - -void __devinit ali_m1535plus_fdc_init(int port) -{ - ENTER_CONFIG_MODE(port); - SELECT_LOGICAL_DEVICE(port, 0); /* FDC */ - WRITE_CONFIG_DATA(port, 0x30, 0x01); /* FDC: enable */ - WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x3f0 */ - WRITE_CONFIG_DATA(port, 0x61, 0xf0); - WRITE_CONFIG_DATA(port, 0x70, 0x06); /* IRQ: 6 */ - WRITE_CONFIG_DATA(port, 0x74, 0x02); /* DMA: channel 2 */ - WRITE_CONFIG_DATA(port, 0xf0, 0x08); - WRITE_CONFIG_DATA(port, 0xf1, 0x00); - WRITE_CONFIG_DATA(port, 0xf2, 0xff); - WRITE_CONFIG_DATA(port, 0xf4, 0x00); - EXIT_CONFIG_MODE(port); -} - -#endif - -void __devinit ali_m1535plus_parport_init(int port) -{ - ENTER_CONFIG_MODE(port); - SELECT_LOGICAL_DEVICE(port, 3); /* Parallel Port */ - WRITE_CONFIG_DATA(port, 0x30, 0x01); - WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x378 */ - WRITE_CONFIG_DATA(port, 0x61, 0x78); - WRITE_CONFIG_DATA(port, 0x70, 0x07); /* IRQ: 7 */ - WRITE_CONFIG_DATA(port, 0x74, 0x04); /* DMA: None */ - WRITE_CONFIG_DATA(port, 0xf0, 0x8c); /* IRQ polarity: Active Low */ - WRITE_CONFIG_DATA(port, 0xf1, 0xc5); - EXIT_CONFIG_MODE(port); -} - -void __devinit ali_m1535plus_keyboard_init(int port) -{ - ENTER_CONFIG_MODE(port); - SELECT_LOGICAL_DEVICE(port, 7); /* KEYBOARD */ - WRITE_CONFIG_DATA(port, 0x30, 0x01); /* KEYBOARD: eable */ - WRITE_CONFIG_DATA(port, 0x70, 0x01); /* IRQ: 1 */ - WRITE_CONFIG_DATA(port, 0x72, 0x0c); /* PS/2 Mouse IRQ: 12 */ - WRITE_CONFIG_DATA(port, 0xf0, 0x00); - EXIT_CONFIG_MODE(port); -} - -void __devinit ali_m1535plus_hotkey_init(int port) -{ - ENTER_CONFIG_MODE(port); - SELECT_LOGICAL_DEVICE(port, 0xc); /* HOTKEY */ - WRITE_CONFIG_DATA(port, 0x30, 0x00); - WRITE_CONFIG_DATA(port, 0xf0, 0x35); - WRITE_CONFIG_DATA(port, 0xf1, 0x14); - WRITE_CONFIG_DATA(port, 0xf2, 0x11); - WRITE_CONFIG_DATA(port, 0xf3, 0x71); - WRITE_CONFIG_DATA(port, 0xf5, 0x05); - EXIT_CONFIG_MODE(port); -} - -void ali_m1535plus_init(struct pci_dev *dev) -{ - pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */ - pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */ - pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */ - pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */ - pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */ - pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */ - pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */ - - /* IRQ routing */ - pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */ - pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */ - pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */ - pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */ - - pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */ - pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */ - pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */ - pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */ - - pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */ - pci_write_config_byte(dev, 0x5a, 0x00); - pci_write_config_byte(dev, 0x5b, 0x00); - pci_write_config_word(dev, 0x5c, 0x0000); - pci_write_config_byte(dev, 0x5e, 0x00); - pci_write_config_byte(dev, 0x5f, 0x00); - pci_write_config_word(dev, 0x60, 0x0000); - - pci_write_config_byte(dev, 0x6c, 0x00); - pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */ - pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */ - - pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */ - pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */ - pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */ - pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */ - - /* - * IRQ setup ALi M5237 USB Host Controller - * IRQ: 9 - */ - pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */ - - pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15 */ - pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */ - pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */ - pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */ - pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */ - pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */ - pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */ - pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */ - -#ifdef CONFIG_BLK_DEV_FD - ali_m1535plus_fdc_init(1); -#endif - - ali_m1535plus_keyboard_init(1); - ali_m1535plus_hotkey_init(1); -} - -static inline void ali_config_writeb(u8 reg, u8 val, int devfn) -{ - u32 data; - int shift; - - writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); - data = readl(PCI_CONFIG_DATA); - - shift = (reg & 3) << 3; - data &= ~(0xff << shift); - data |= (((u32)val) << shift); - - writel(data, PCI_CONFIG_DATA); -} - -static inline u8 ali_config_readb(u8 reg, int devfn) -{ - u32 data; - - writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); - data = readl(PCI_CONFIG_DATA); - - return (u8)(data >> ((reg & 3) << 3)); -} - -static inline u16 ali_config_readw(u8 reg, int devfn) -{ - u32 data; - - writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); - data = readl(PCI_CONFIG_DATA); - - return (u16)(data >> ((reg & 2) << 3)); -} - -int vr4133_rockhopper = 0; -void __init ali_m5229_preinit(void) -{ - if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL && - ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) { - printk(KERN_INFO "Found an NEC Rockhopper \n"); - vr4133_rockhopper = 1; - /* - * Enable ALi M5229 IDE Controller (both channels) - * IDSEL: A27 - */ - ali_config_writeb(0x58, 0x4c, 16); - } -} - -void __init ali_m5229_init(struct pci_dev *dev) -{ - /* - * Enable Primary/Secondary Channel Cable Detect 40-Pin - */ - pci_write_config_word(dev, 0x4a, 0xc023); - - /* - * Set only the 3rd byteis for the master IDE's cycle and - * enable Internal IDE Function - */ - pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */ - - pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */ - pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */ - pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */ - pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */ - pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */ - pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */ - pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */ - pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */ - pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */ - pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */ - pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); - pci_write_config_word(dev, PCI_COMMAND, - PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | - PCI_COMMAND_IO); -} - diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c deleted file mode 100644 index 7723d2011b08..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/setup.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * arch/mips/vr41xx/nec-cmbvr4133/setup.c - * - * Setup for the NEC CMB-VR4133. - * - * Author: Yoichi Yuasa and - * Alex Sapkov - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for CMBVR4133 board in 2.6 - * Author: Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_MTD -#include -#include -#include -#include - -static struct mtd_partition cmbvr4133_mtd_parts[] = { - { - .name = "User FS", - .size = 0x1be0000, - .offset = 0, - .mask_flags = 0, - }, - { - .name = "PMON", - .size = 0x140000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "User FS2", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - .mask_flags = 0, - } -}; - -#define number_partitions ARRAY_SIZE(cmbvr4133_mtd_parts) -#endif - -extern void i8259_init(void); - -static void __init nec_cmbvr4133_setup(void) -{ -#ifdef CONFIG_ROCKHOPPER - extern void disable_pcnet(void); - - disable_pcnet(); -#endif - set_io_port_base(KSEG1ADDR(0x16000000)); - -#ifdef CONFIG_PCI -#ifdef CONFIG_ROCKHOPPER - ali_m5229_preinit(); -#endif -#endif - -#ifdef CONFIG_ROCKHOPPER - rockhopper_init_irq(); -#endif - -#ifdef CONFIG_MTD - /* we use generic physmap mapping driver and we use partitions */ - physmap_configure(0x1C000000, 0x02000000, 4, NULL); - physmap_set_partitions(cmbvr4133_mtd_parts, number_partitions); -#endif - - /* 128 MB memory support */ - add_memory_region(0, 0x08000000, BOOT_MEM_RAM); - -#ifdef CONFIG_ROCKHOPPER - i8259_init(); -#endif -} diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h index 848812296052..862058d3f81b 100644 --- a/include/asm-mips/mach-vr41xx/irq.h +++ b/include/asm-mips/mach-vr41xx/irq.h @@ -2,9 +2,6 @@ #define __ASM_MACH_VR41XX_IRQ_H #include /* for MIPS_CPU_IRQ_BASE */ -#ifdef CONFIG_NEC_CMBVR4133 -#include /* for I8259A_IRQ_BASE */ -#endif #include_next diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h deleted file mode 100644 index 42300037d593..000000000000 --- a/include/asm-mips/vr41xx/cmbvr4133.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * include/asm-mips/vr41xx/cmbvr4133.h - * - * Include file for NEC CMB-VR4133. - * - * Author: Yoichi Yuasa and - * Jun Sun and - * Alex Sapkov - * - * 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __NEC_CMBVR4133_H -#define __NEC_CMBVR4133_H - -#include - -/* - * General-Purpose I/O Pin Number - */ -#define CMBVR41XX_INTA_PIN 1 -#define CMBVR41XX_INTB_PIN 1 -#define CMBVR41XX_INTC_PIN 3 -#define CMBVR41XX_INTD_PIN 1 -#define CMBVR41XX_INTE_PIN 1 - -/* - * Interrupt Number - */ -#define CMBVR41XX_INTA_IRQ GIU_IRQ(CMBVR41XX_INTA_PIN) -#define CMBVR41XX_INTB_IRQ GIU_IRQ(CMBVR41XX_INTB_PIN) -#define CMBVR41XX_INTC_IRQ GIU_IRQ(CMBVR41XX_INTC_PIN) -#define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) -#define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) - -#define I8259A_IRQ_BASE 72 -#define I8259_IRQ(x) (I8259A_IRQ_BASE + (x)) -#define TIMER_IRQ I8259_IRQ(0) -#define KEYBOARD_IRQ I8259_IRQ(1) -#define I8259_SLAVE_IRQ I8259_IRQ(2) -#define UART3_IRQ I8259_IRQ(3) -#define UART1_IRQ I8259_IRQ(4) -#define UART2_IRQ I8259_IRQ(5) -#define FDC_IRQ I8259_IRQ(6) -#define PARPORT_IRQ I8259_IRQ(7) -#define RTC_IRQ I8259_IRQ(8) -#define USB_IRQ I8259_IRQ(9) -#define I8259_INTA_IRQ I8259_IRQ(10) -#define AUDIO_IRQ I8259_IRQ(11) -#define AUX_IRQ I8259_IRQ(12) -#define IDE_PRIMARY_IRQ I8259_IRQ(14) -#define IDE_SECONDARY_IRQ I8259_IRQ(15) - -#endif /* __NEC_CMBVR4133_H */ -- cgit v1.2.3 From 6e68665e51b9937b132a990b9ae7f04118e64688 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sun, 13 Jul 2008 20:04:18 +0900 Subject: [MIPS] remove machtype for group Toshiba Signed-off-by: Yoichi Yuasa Acked-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/jmr3927/setup.c | 1 - arch/mips/txx9/rbtx4927/setup.c | 2 -- arch/mips/txx9/rbtx4938/setup.c | 1 - include/asm-mips/bootinfo.h | 11 ----------- include/asm-mips/txx9/generic.h | 1 - 5 files changed, 16 deletions(-) (limited to 'include') diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 128a4ae3e72e..43a8dad22ef7 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -366,7 +366,6 @@ static void __init jmr3927_device_init(void) } struct txx9_board_vec jmr3927_vec __initdata = { - .type = MACH_TOSHIBA_JMR3927, .system = "Toshiba JMR_TX3927", .prom_init = jmr3927_prom_init, .mem_setup = jmr3927_mem_setup, diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index adc91c0bbb95..aba11f376a51 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -428,7 +428,6 @@ static void __init rbtx4927_device_init(void) } struct txx9_board_vec rbtx4927_vec __initdata = { - .type = MACH_TOSHIBA_RBTX4927, .system = "Toshiba RBTX4927", .prom_init = rbtx4927_prom_init, .mem_setup = rbtx4927_mem_setup, @@ -441,7 +440,6 @@ struct txx9_board_vec rbtx4927_vec __initdata = { #endif }; struct txx9_board_vec rbtx4937_vec __initdata = { - .type = MACH_TOSHIBA_RBTX4937, .system = "Toshiba RBTX4937", .prom_init = rbtx4927_prom_init, .mem_setup = rbtx4927_mem_setup, diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index 8306ba333dda..2ef71adea827 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -619,7 +619,6 @@ static void __init rbtx4938_device_init(void) } struct txx9_board_vec rbtx4938_vec __initdata = { - .type = MACH_TOSHIBA_RBTX4938, .system = "Toshiba RBTX4938", .prom_init = rbtx4938_prom_init, .mem_setup = rbtx4938_mem_setup, diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index e031bdff9920..c70848d4f632 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -61,17 +61,6 @@ #define MACH_SGI_IP32 3 /* O2 */ #define MACH_SGI_IP30 4 /* Octane, Octane2 */ -/* - * Valid machtypes for group Toshiba - */ -#define MACH_PALLAS 0 -#define MACH_TOPAS 1 -#define MACH_JMR 2 -#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ -#define MACH_TOSHIBA_RBTX4927 4 -#define MACH_TOSHIBA_RBTX4937 5 -#define MACH_TOSHIBA_RBTX4938 6 - /* * Valid machtype for group LASAT */ diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h index 6cd147764f19..715d7c8ade5c 100644 --- a/include/asm-mips/txx9/generic.h +++ b/include/asm-mips/txx9/generic.h @@ -22,7 +22,6 @@ extern unsigned int txx9_gbus_clock; struct pci_dev; struct txx9_board_vec { - unsigned long type; const char *system; void (*prom_init)(void); void (*mem_setup)(void); -- cgit v1.2.3 From 4c642f3f5e9f3f1a2fcce2c3fa1a94bf80142202 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sun, 13 Jul 2008 23:37:56 +0900 Subject: [MIPS] TXx9: rename asm-mips/mach-jmr3927 to asm-mips/mach-tx39xx Rename mach-jmr3927 directory to more proper name to make adding other platforms easier. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Makefile | 2 +- arch/mips/txx9/generic/setup.c | 10 ++++++++ arch/mips/txx9/jmr3927/setup.c | 4 +-- include/asm-mips/mach-jmr3927/ioremap.h | 38 ----------------------------- include/asm-mips/mach-jmr3927/mangle-port.h | 18 -------------- include/asm-mips/mach-jmr3927/war.h | 25 ------------------- include/asm-mips/mach-tx39xx/ioremap.h | 38 +++++++++++++++++++++++++++++ include/asm-mips/mach-tx39xx/mangle-port.h | 23 +++++++++++++++++ include/asm-mips/mach-tx39xx/war.h | 25 +++++++++++++++++++ 9 files changed, 99 insertions(+), 84 deletions(-) delete mode 100644 include/asm-mips/mach-jmr3927/ioremap.h delete mode 100644 include/asm-mips/mach-jmr3927/mangle-port.h delete mode 100644 include/asm-mips/mach-jmr3927/war.h create mode 100644 include/asm-mips/mach-tx39xx/ioremap.h create mode 100644 include/asm-mips/mach-tx39xx/mangle-port.h create mode 100644 include/asm-mips/mach-tx39xx/war.h (limited to 'include') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index c4a3098a58c6..356453322b49 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -548,7 +548,7 @@ all-$(CONFIG_SNI_RM) := vmlinux.ecoff # Common TXx9 # core-$(CONFIG_MACH_TX39XX) += arch/mips/txx9/generic/ -cflags-$(CONFIG_MACH_TX39XX) += -Iinclude/asm-mips/mach-jmr3927 +cflags-$(CONFIG_MACH_TX39XX) += -Iinclude/asm-mips/mach-tx39xx load-$(CONFIG_MACH_TX39XX) += 0xffffffff80050000 core-$(CONFIG_MACH_TX49XX) += arch/mips/txx9/generic/ cflags-$(CONFIG_MACH_TX49XX) += -Iinclude/asm-mips/mach-tx49xx diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 517828e1ec92..452cb9ea12c0 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -200,3 +200,13 @@ asmlinkage void plat_irq_dispatch(void) else spurious_interrupt(); } + +/* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */ +#ifdef NEEDS_TXX9_SWIZZLE_ADDR_B +static unsigned long __swizzle_addr_none(unsigned long port) +{ + return port; +} +unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none; +EXPORT_SYMBOL(__swizzle_addr_b); +#endif diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 43a8dad22ef7..61edc4ac1dbc 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -315,7 +315,7 @@ static void __init tx3927_setup(void) } /* This trick makes rtc-ds1742 driver usable as is. */ -unsigned long __swizzle_addr_b(unsigned long port) +static unsigned long jmr3927_swizzle_addr_b(unsigned long port) { if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR) return port; @@ -326,7 +326,6 @@ unsigned long __swizzle_addr_b(unsigned long port) return port | 1; #endif } -EXPORT_SYMBOL(__swizzle_addr_b); static int __init jmr3927_rtc_init(void) { @@ -361,6 +360,7 @@ static int __init jmr3927_wdt_init(void) static void __init jmr3927_device_init(void) { + __swizzle_addr_b = jmr3927_swizzle_addr_b; jmr3927_rtc_init(); jmr3927_wdt_init(); } diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-jmr3927/ioremap.h deleted file mode 100644 index 29989ff10d66..000000000000 --- a/include/asm-mips/mach-jmr3927/ioremap.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * include/asm-mips/mach-jmr3927/ioremap.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MACH_JMR3927_IOREMAP_H -#define __ASM_MACH_JMR3927_IOREMAP_H - -#include - -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, - unsigned long flags) -{ -#define TXX9_DIRECTMAP_BASE 0xff000000ul - if (offset >= TXX9_DIRECTMAP_BASE && - offset < TXX9_DIRECTMAP_BASE + 0xff0000) - return (void __iomem *)offset; - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return (unsigned long)addr >= TXX9_DIRECTMAP_BASE; -} - -#endif /* __ASM_MACH_JMR3927_IOREMAP_H */ diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-jmr3927/mangle-port.h deleted file mode 100644 index 11bffcd1043b..000000000000 --- a/include/asm-mips/mach-jmr3927/mangle-port.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __ASM_MACH_JMR3927_MANGLE_PORT_H -#define __ASM_MACH_JMR3927_MANGLE_PORT_H - -extern unsigned long __swizzle_addr_b(unsigned long port); -#define __swizzle_addr_w(port) (port) -#define __swizzle_addr_l(port) (port) -#define __swizzle_addr_q(port) (port) - -#define ioswabb(a, x) (x) -#define __mem_ioswabb(a, x) (x) -#define ioswabw(a, x) le16_to_cpu(x) -#define __mem_ioswabw(a, x) (x) -#define ioswabl(a, x) le32_to_cpu(x) -#define __mem_ioswabl(a, x) (x) -#define ioswabq(a, x) le64_to_cpu(x) -#define __mem_ioswabq(a, x) (x) - -#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-jmr3927/war.h deleted file mode 100644 index 1ff55fb3fbcb..000000000000 --- a/include/asm-mips/mach-jmr3927/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H -#define __ASM_MIPS_MACH_JMR3927_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */ diff --git a/include/asm-mips/mach-tx39xx/ioremap.h b/include/asm-mips/mach-tx39xx/ioremap.h new file mode 100644 index 000000000000..93c6c04ffda3 --- /dev/null +++ b/include/asm-mips/mach-tx39xx/ioremap.h @@ -0,0 +1,38 @@ +/* + * include/asm-mips/mach-tx39xx/ioremap.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_MACH_TX39XX_IOREMAP_H +#define __ASM_MACH_TX39XX_IOREMAP_H + +#include + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} + +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ +#define TXX9_DIRECTMAP_BASE 0xff000000ul + if (offset >= TXX9_DIRECTMAP_BASE && + offset < TXX9_DIRECTMAP_BASE + 0xff0000) + return (void __iomem *)offset; + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return (unsigned long)addr >= TXX9_DIRECTMAP_BASE; +} + +#endif /* __ASM_MACH_TX39XX_IOREMAP_H */ diff --git a/include/asm-mips/mach-tx39xx/mangle-port.h b/include/asm-mips/mach-tx39xx/mangle-port.h new file mode 100644 index 000000000000..ef0b502fd8b7 --- /dev/null +++ b/include/asm-mips/mach-tx39xx/mangle-port.h @@ -0,0 +1,23 @@ +#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H +#define __ASM_MACH_TX39XX_MANGLE_PORT_H + +#if defined(CONFIG_TOSHIBA_JMR3927) +extern unsigned long (*__swizzle_addr_b)(unsigned long port); +#define NEEDS_TXX9_SWIZZLE_ADDR_B +#else +#define __swizzle_addr_b(port) (port) +#endif +#define __swizzle_addr_w(port) (port) +#define __swizzle_addr_l(port) (port) +#define __swizzle_addr_q(port) (port) + +#define ioswabb(a, x) (x) +#define __mem_ioswabb(a, x) (x) +#define ioswabw(a, x) le16_to_cpu(x) +#define __mem_ioswabw(a, x) (x) +#define ioswabl(a, x) le32_to_cpu(x) +#define __mem_ioswabl(a, x) (x) +#define ioswabq(a, x) le64_to_cpu(x) +#define __mem_ioswabq(a, x) (x) + +#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-tx39xx/war.h b/include/asm-mips/mach-tx39xx/war.h new file mode 100644 index 000000000000..433814616359 --- /dev/null +++ b/include/asm-mips/mach-tx39xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H +#define __ASM_MIPS_MACH_TX39XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */ -- cgit v1.2.3 From 7b22609442a32050e37cec5f6735376af61e68a1 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 14 Jul 2008 00:15:04 +0900 Subject: [MIPS] TXx9: cleanup and fix some sparse warnings * Do not return void value * Make some functions static * Do not include unnecessary bootinfo.h Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/generic/setup.c | 2 +- arch/mips/txx9/jmr3927/setup.c | 3 --- arch/mips/txx9/rbtx4927/setup.c | 16 +++------------- arch/mips/txx9/rbtx4938/setup.c | 13 +++---------- include/asm-mips/txx9/generic.h | 1 + 5 files changed, 8 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 452cb9ea12c0..5afc5d5cab03 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -140,7 +140,7 @@ void __init prom_init(void) strcpy(txx9_system_type, txx9_board_vec->system); - return txx9_board_vec->prom_init(); + txx9_board_vec->prom_init(); } void __init prom_free_prom_memory(void) diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 61edc4ac1dbc..5e35ef73c5a5 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -38,8 +38,6 @@ #ifdef CONFIG_SERIAL_TXX9 #include #endif - -#include #include #include #include @@ -95,7 +93,6 @@ static void __init jmr3927_time_init(void) #define DO_WRITE_THROUGH #define DO_ENABLE_CACHE -extern char * __init prom_getcmdline(void); static void jmr3927_board_init(void); static void __init jmr3927_mem_setup(void) diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index aba11f376a51..1657fd935da8 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -50,8 +50,6 @@ #include #include #include - -#include #include #include #include @@ -65,14 +63,6 @@ #include #endif -/* These functions are used for rebooting or halting the machine*/ -extern void toshiba_rbtx4927_restart(char *command); -extern void toshiba_rbtx4927_halt(void); -extern void toshiba_rbtx4927_power_off(void); -extern void toshiba_rbtx4927_irq_setup(void); - -char *prom_getcmdline(void); - static int tx4927_ccfg_toeon = 1; #ifdef CONFIG_PCI @@ -189,7 +179,7 @@ static void __noreturn wait_forever(void) (*cpu_wait)(); } -void toshiba_rbtx4927_restart(char *command) +static void toshiba_rbtx4927_restart(char *command) { printk(KERN_NOTICE "System Rebooting...\n"); @@ -209,7 +199,7 @@ void toshiba_rbtx4927_restart(char *command) /* no return */ } -void toshiba_rbtx4927_halt(void) +static void toshiba_rbtx4927_halt(void) { printk(KERN_NOTICE "System Halted\n"); local_irq_disable(); @@ -217,7 +207,7 @@ void toshiba_rbtx4927_halt(void) /* no return */ } -void toshiba_rbtx4927_power_off(void) +static void toshiba_rbtx4927_power_off(void) { toshiba_rbtx4927_halt(); /* no return */ diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index 2ef71adea827..aaa987ae0f83 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -34,15 +33,9 @@ #include #include -extern char * __init prom_getcmdline(void); -/* These functions are used for rebooting or halting the machine*/ -extern void rbtx4938_machine_restart(char *command); -extern void rbtx4938_machine_halt(void); -extern void rbtx4938_machine_power_off(void); - static int tx4938_ccfg_toeon = 1; -void rbtx4938_machine_halt(void) +static void rbtx4938_machine_halt(void) { printk(KERN_NOTICE "System Halted\n"); local_irq_disable(); @@ -53,13 +46,13 @@ void rbtx4938_machine_halt(void) ".set\tmips0"); } -void rbtx4938_machine_power_off(void) +static void rbtx4938_machine_power_off(void) { rbtx4938_machine_halt(); /* no return */ } -void rbtx4938_machine_restart(char *command) +static void rbtx4938_machine_restart(char *command) { local_irq_disable(); diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h index 715d7c8ade5c..d8756660523d 100644 --- a/include/asm-mips/txx9/generic.h +++ b/include/asm-mips/txx9/generic.h @@ -36,5 +36,6 @@ struct txx9_board_vec { extern struct txx9_board_vec *txx9_board_vec; extern int (*txx9_irq_dispatch)(int pending); void prom_init_cmdline(void); +char *prom_getcmdline(void); #endif /* __ASM_TXX9_GENERIC_H */ -- cgit v1.2.3 From c660729501894e0b88054ad4b66a5f98a1a2a37e Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 14 Jul 2008 15:11:40 +0200 Subject: [MIPS] Remove mips_machtype from ARC based machines This is the ARC part of the mips_machtype removal. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/fw/arc/identify.c | 11 ----------- arch/mips/jazz/setup.c | 3 +-- include/asm-mips/bootinfo.h | 21 --------------------- 3 files changed, 1 insertion(+), 34 deletions(-) (limited to 'include') diff --git a/arch/mips/fw/arc/identify.c b/arch/mips/fw/arc/identify.c index 23066985a734..0ce9acf10c39 100644 --- a/arch/mips/fw/arc/identify.c +++ b/arch/mips/fw/arc/identify.c @@ -22,7 +22,6 @@ struct smatch { char *arcname; char *liname; - int type; int flags; }; @@ -30,47 +29,38 @@ static struct smatch mach_table[] = { { .arcname = "SGI-IP22", .liname = "SGI Indy", - .type = MACH_SGI_IP22, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP27", .liname = "SGI Origin", - .type = MACH_SGI_IP27, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP28", .liname = "SGI IP28", - .type = MACH_SGI_IP28, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP30", .liname = "SGI Octane", - .type = MACH_SGI_IP30, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP32", .liname = "SGI O2", - .type = MACH_SGI_IP32, .flags = PROM_FLAG_ARCS, }, { .arcname = "Microsoft-Jazz", .liname = "Jazz MIPS_Magnum_4000", - .type = MACH_MIPS_MAGNUM_4000, .flags = 0, }, { .arcname = "PICA-61", .liname = "Jazz Acer_PICA_61", - .type = MACH_ACER_PICA_61, .flags = 0, }, { .arcname = "RM200PCI", .liname = "SNI RM200_PCI", - .type = MACH_SNI_RM200_PCI, .flags = PROM_FLAG_DONT_FREE_TEMP, }, { .arcname = "RM200PCI-R5K", .liname = "SNI RM200_PCI-R5K", - .type = MACH_SNI_RM200_PCI, .flags = PROM_FLAG_DONT_FREE_TEMP, } }; @@ -121,6 +111,5 @@ void __init prom_identify_arch(void) mach = string_to_mach(iname); system_type = mach->liname; - mips_machtype = mach->type; prom_flags = mach->flags; } diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index f136c8a8591c..f60524e8bc44 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -76,8 +76,7 @@ void __init plat_mem_setup(void) set_io_port_base(JAZZ_PORT_BASE); #ifdef CONFIG_EISA - if (mips_machtype == MACH_MIPS_MAGNUM_4000) - EISA_bus = 1; + EISA_bus = 1; #endif /* request I/O space for devices used on all i[345]86 PCs */ diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index c70848d4f632..653096a69d16 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -25,13 +25,6 @@ */ #define MACH_UNKNOWN 0 /* whatever... */ -/* - * Valid machtype values for group JAZZ - */ -#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ -#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ -#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ - /* * Valid machtype for group DEC */ @@ -47,20 +40,6 @@ #define MACH_DS5800 9 /* DECsystem 5800 */ #define MACH_DS5900 10 /* DECsystem 5900 */ -/* - * Valid machtype for group SNI_RM - */ -#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ - -/* - * Valid machtype for group SGI - */ -#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ -#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ -#define MACH_SGI_IP28 2 /* Indigo2 Impact */ -#define MACH_SGI_IP32 3 /* O2 */ -#define MACH_SGI_IP30 4 /* Octane, Octane2 */ - /* * Valid machtype for group LASAT */ -- cgit v1.2.3 From 0b56fd8c7abbf85baeecb77be25c54d3c7d11587 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 14 Jul 2008 15:54:30 +0200 Subject: [MIPS] Remove mips_machtype from EMMA2RH machines This is the EMMA2RH part of the mips_machtype removal. [Ralf: Fixed to the #error statements] Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/emma2rh/common/prom.c | 15 +++++++-------- include/asm-mips/bootinfo.h | 5 ----- 2 files changed, 7 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma2rh/common/prom.c index 0f791eb6bb66..5e92b3a9c5b8 100644 --- a/arch/mips/emma2rh/common/prom.c +++ b/arch/mips/emma2rh/common/prom.c @@ -34,12 +34,11 @@ const char *get_system_type(void) { - switch (mips_machtype) { - case MACH_NEC_MARKEINS: - return "NEC EMMA2RH Mark-eins"; - default: - return "Unknown NEC board"; - } +#if defined(CONFIG_MARKEINS) + return "NEC EMMA2RH Mark-eins"; +#else +#error Unknown NEC board +#endif } /* [jsun@junsun.net] PMON passes arguments in C main() style */ @@ -63,10 +62,10 @@ void __init prom_init(void) } #if defined(CONFIG_MARKEINS) - mips_machtype = MACH_NEC_MARKEINS; add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); +#else +#error Unknown NEC board #endif - } void __init prom_free_prom_memory(void) diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 653096a69d16..51dbec9dabfd 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -46,11 +46,6 @@ #define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ #define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ -/* - * Valid machtype for group NEC EMMA2RH - */ -#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ - /* * Valid machtype for group PMC-MSP */ -- cgit v1.2.3 From b27418aa551a153e8bf1bd16cf93e5786f9590a9 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 14 Jul 2008 16:58:47 +0200 Subject: [MIPS] Remove mips_machtype for LASAT machines This is the LASAT part of the mips_machtype removal. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/lasat/interrupt.c | 21 ++++++++------------- arch/mips/lasat/lasat_board.c | 3 +-- arch/mips/lasat/prom.c | 8 +++----- arch/mips/lasat/serial.c | 3 +-- arch/mips/lasat/setup.c | 8 +++++--- arch/mips/pci/pci-lasat.c | 14 ++++---------- include/asm-mips/bootinfo.h | 6 ------ include/asm-mips/lasat/lasat.h | 2 ++ 8 files changed, 24 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index a56c15026965..d1ac7a25c856 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -22,8 +22,8 @@ #include #include -#include #include +#include #include #include @@ -112,23 +112,18 @@ void __init arch_init_irq(void) { int i; - switch (mips_machtype) { - case MACH_LASAT_100: - lasat_int_status = (void *)LASAT_INT_STATUS_REG_100; - lasat_int_mask = (void *)LASAT_INT_MASK_REG_100; - lasat_int_mask_shift = LASATINT_MASK_SHIFT_100; - get_int_status = get_int_status_100; - *lasat_int_mask = 0; - break; - case MACH_LASAT_200: + if (IS_LASAT_200()) { lasat_int_status = (void *)LASAT_INT_STATUS_REG_200; lasat_int_mask = (void *)LASAT_INT_MASK_REG_200; lasat_int_mask_shift = LASATINT_MASK_SHIFT_200; get_int_status = get_int_status_200; *lasat_int_mask &= 0xffff; - break; - default: - panic("arch_init_irq: mips_machtype incorrect"); + } else { + lasat_int_status = (void *)LASAT_INT_STATUS_REG_100; + lasat_int_mask = (void *)LASAT_INT_MASK_REG_100; + lasat_int_mask_shift = LASATINT_MASK_SHIFT_100; + get_int_status = get_int_status_100; + *lasat_int_mask = 0; } mips_cpu_irq_init(); diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c index 31e328b3814d..577bb463a871 100644 --- a/arch/mips/lasat/lasat_board.c +++ b/arch/mips/lasat/lasat_board.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include "at93c.h" /* New model description table */ @@ -66,7 +65,7 @@ static void init_flash_sizes(void) ls[LASAT_MTD_SERVICE] = 0xC0000; ls[LASAT_MTD_NORMAL] = 0x100000; - if (mips_machtype == MACH_LASAT_100) { + if (!IS_LASAT_200()) { lasat_board_info.li_flash_base = 0x1e000000; lb[LASAT_MTD_BOOTLOADER] = 0x1e400000; diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c index 209edcc26f07..6acc6cb85f0a 100644 --- a/arch/mips/lasat/prom.c +++ b/arch/mips/lasat/prom.c @@ -86,18 +86,16 @@ void __init prom_init(void) setup_prom_vectors(); - if (current_cpu_data.cputype == CPU_R5000) { + if (IS_LASAT_200()) { printk(KERN_INFO "LASAT 200 board\n"); - mips_machtype = MACH_LASAT_200; lasat_ndelay_divider = LASAT_200_DIVIDER; + at93c = &at93c_defs[1]; } else { printk(KERN_INFO "LASAT 100 board\n"); - mips_machtype = MACH_LASAT_100; lasat_ndelay_divider = LASAT_100_DIVIDER; + at93c = &at93c_defs[0]; } - at93c = &at93c_defs[mips_machtype]; - lasat_init_board_info(); /* Read info from EEPROM */ /* Get the command line */ diff --git a/arch/mips/lasat/serial.c b/arch/mips/lasat/serial.c index 205bd397d75b..5bcb6e89ab78 100644 --- a/arch/mips/lasat/serial.c +++ b/arch/mips/lasat/serial.c @@ -23,7 +23,6 @@ #include #include -#include #include #include @@ -47,7 +46,7 @@ static __init int lasat_uart_add(void) if (!pdev) return -ENOMEM; - if (mips_machtype == MACH_LASAT_100) { + if (!IS_LASAT_200()) { lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_100); lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_100 * 8 - 1; lasat_serial_res[0].flags = IORESOURCE_MEM; diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c index e072da4ff3b3..dbd3163a85c2 100644 --- a/arch/mips/lasat/setup.c +++ b/arch/mips/lasat/setup.c @@ -127,9 +127,11 @@ void __init plat_time_init(void) void __init plat_mem_setup(void) { int i; - lasat_misc = &lasat_misc_info[mips_machtype]; + int lasat_type = IS_LASAT_200() ? 1 : 0; + + lasat_misc = &lasat_misc_info[lasat_type]; #ifdef CONFIG_PICVUE - picvue = &pvc_defs[mips_machtype]; + picvue = &pvc_defs[lasat_type]; #endif /* Set up panic notifier */ @@ -140,7 +142,7 @@ void __init plat_mem_setup(void) lasat_reboot_setup(); #ifdef CONFIG_DS1603 - ds1603 = &ds_defs[mips_machtype]; + ds1603 = &ds_defs[lasat_type]; #endif #ifdef DYNAMIC_SERIAL_INIT diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c index e70ae3236e0b..a98e543a514a 100644 --- a/arch/mips/pci/pci-lasat.c +++ b/arch/mips/pci/pci-lasat.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include @@ -39,16 +39,10 @@ static int __init lasat_pci_setup(void) { printk(KERN_DEBUG "PCI: starting\n"); - switch (mips_machtype) { - case MACH_LASAT_100: - lasat_pci_controller.pci_ops = >64xxx_pci0_ops; - break; - case MACH_LASAT_200: + if (IS_LASAT_200()) lasat_pci_controller.pci_ops = &nile4_pci_ops; - break; - default: - panic("pcibios_init: mips_machtype incorrect"); - } + else + lasat_pci_controller.pci_ops = >64xxx_pci0_ops; register_pci_controller(&lasat_pci_controller); diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 51dbec9dabfd..d39e143b4a3c 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -40,12 +40,6 @@ #define MACH_DS5800 9 /* DECsystem 5800 */ #define MACH_DS5900 10 /* DECsystem 5900 */ -/* - * Valid machtype for group LASAT - */ -#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ -#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ - /* * Valid machtype for group PMC-MSP */ diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h index ea04d9262edc..caeba1e302a2 100644 --- a/include/asm-mips/lasat/lasat.h +++ b/include/asm-mips/lasat/lasat.h @@ -240,6 +240,8 @@ static inline void lasat_ndelay(unsigned int ns) __delay(ns / lasat_ndelay_divider); } +#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000) + #endif /* !defined (_LANGUAGE_ASSEMBLY) */ #define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef -- cgit v1.2.3 From c2e1b09ff237c0a3687b9a804cc8bf489743cffc Mon Sep 17 00:00:00 2001 From: Chuck Lever Date: Mon, 14 Jul 2008 16:03:30 -0400 Subject: SUNRPC: Support registering IPv6 interfaces with local rpcbind daemon Introduce a new API to register RPC services on IPv6 interfaces to allow the NFS server and lockd to advertise on IPv6 networks. Unlike rpcb_register(), the new rpcb_v4_register() function uses rpcbind protocol version 4 to contact the local rpcbind daemon. The version 4 SET/UNSET procedures allow services to register address families besides AF_INET, register at specific network interfaces, and register transport protocols besides UDP and TCP. All of this functionality is exposed via the new rpcb_v4_register() kernel API. A user-space rpcbind daemon implementation that supports version 4 of the rpcbind protocol is required in order to make use of this new API. Note that rpcbind version 3 is sufficient to support the new rpcbind facilities listed above, but most extant implementations use version 4. Signed-off-by: Chuck Lever Signed-off-by: J. Bruce Fields Signed-off-by: Trond Myklebust --- include/linux/sunrpc/clnt.h | 3 + net/sunrpc/rpcb_clnt.c | 178 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 177 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index 764fd4c286e0..e5bfe01ee305 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -125,6 +125,9 @@ void rpc_shutdown_client(struct rpc_clnt *); void rpc_release_client(struct rpc_clnt *); int rpcb_register(u32, u32, int, unsigned short, int *); +int rpcb_v4_register(const u32 program, const u32 version, + const struct sockaddr *address, + const char *netid, int *result); int rpcb_getport_sync(struct sockaddr_in *, u32, u32, int); void rpcb_getport_async(struct rpc_task *); diff --git a/net/sunrpc/rpcb_clnt.c b/net/sunrpc/rpcb_clnt.c index 8b75c306e661..24db2b4d12d3 100644 --- a/net/sunrpc/rpcb_clnt.c +++ b/net/sunrpc/rpcb_clnt.c @@ -87,6 +87,7 @@ struct rpcbind_args { static struct rpc_procinfo rpcb_procedures2[]; static struct rpc_procinfo rpcb_procedures3[]; +static struct rpc_procinfo rpcb_procedures4[]; struct rpcb_info { u32 rpc_vers; @@ -122,6 +123,12 @@ static const struct sockaddr_in rpcb_inaddr_loopback = { .sin_port = htons(RPCBIND_PORT), }; +static const struct sockaddr_in6 rpcb_in6addr_loopback = { + .sin6_family = AF_INET6, + .sin6_addr = IN6ADDR_LOOPBACK_INIT, + .sin6_port = htons(RPCBIND_PORT), +}; + static struct rpc_clnt *rpcb_create_local(struct sockaddr *addr, size_t addrlen, u32 version) { @@ -196,13 +203,38 @@ static int rpcb_register_call(struct sockaddr *addr, size_t addrlen, * rpcb_register - set or unset a port registration with the local rpcbind svc * @prog: RPC program number to bind * @vers: RPC version number to bind - * @prot: transport protocol to use to make this request + * @prot: transport protocol to register * @port: port value to register - * @okay: result code + * @okay: OUT: result code + * + * RPC services invoke this function to advertise their contact + * information via the system's rpcbind daemon. RPC services + * invoke this function once for each [program, version, transport] + * tuple they wish to advertise. + * + * Callers may also unregister RPC services that are no longer + * available by setting the passed-in port to zero. This removes + * all registered transports for [program, version] from the local + * rpcbind database. + * + * Returns zero if the registration request was dispatched + * successfully and a reply was received. The rpcbind daemon's + * boolean result code is stored in *okay. * - * port == 0 means unregister, port != 0 means register. + * Returns an errno value and sets *result to zero if there was + * some problem that prevented the rpcbind request from being + * dispatched, or if the rpcbind daemon did not respond within + * the timeout. * - * This routine supports only rpcbind version 2. + * This function uses rpcbind protocol version 2 to contact the + * local rpcbind daemon. + * + * Registration works over both AF_INET and AF_INET6, and services + * registered via this function are advertised as available for any + * address. If the local rpcbind daemon is listening on AF_INET6, + * services registered via this function will be advertised on + * IN6ADDR_ANY (ie available for all AF_INET and AF_INET6 + * addresses). */ int rpcb_register(u32 prog, u32 vers, int prot, unsigned short port, int *okay) { @@ -230,6 +262,144 @@ int rpcb_register(u32 prog, u32 vers, int prot, unsigned short port, int *okay) RPCBVERS_2, &msg, okay); } +/* + * Fill in AF_INET family-specific arguments to register + */ +static int rpcb_register_netid4(struct sockaddr_in *address_to_register, + struct rpc_message *msg) +{ + struct rpcbind_args *map = msg->rpc_argp; + unsigned short port = ntohs(address_to_register->sin_port); + char buf[32]; + + /* Construct AF_INET universal address */ + snprintf(buf, sizeof(buf), + NIPQUAD_FMT".%u.%u", + NIPQUAD(address_to_register->sin_addr.s_addr), + port >> 8, port & 0xff); + map->r_addr = buf; + + dprintk("RPC: %sregistering [%u, %u, %s, '%s'] with " + "local rpcbind\n", (port ? "" : "un"), + map->r_prog, map->r_vers, + map->r_addr, map->r_netid); + + msg->rpc_proc = &rpcb_procedures4[RPCBPROC_UNSET]; + if (port) + msg->rpc_proc = &rpcb_procedures4[RPCBPROC_SET]; + + return rpcb_register_call((struct sockaddr *)&rpcb_inaddr_loopback, + sizeof(rpcb_inaddr_loopback), + RPCBVERS_4, msg, msg->rpc_resp); +} + +/* + * Fill in AF_INET6 family-specific arguments to register + */ +static int rpcb_register_netid6(struct sockaddr_in6 *address_to_register, + struct rpc_message *msg) +{ + struct rpcbind_args *map = msg->rpc_argp; + unsigned short port = ntohs(address_to_register->sin6_port); + char buf[64]; + + /* Construct AF_INET6 universal address */ + snprintf(buf, sizeof(buf), + NIP6_FMT".%u.%u", + NIP6(address_to_register->sin6_addr), + port >> 8, port & 0xff); + map->r_addr = buf; + + dprintk("RPC: %sregistering [%u, %u, %s, '%s'] with " + "local rpcbind\n", (port ? "" : "un"), + map->r_prog, map->r_vers, + map->r_addr, map->r_netid); + + msg->rpc_proc = &rpcb_procedures4[RPCBPROC_UNSET]; + if (port) + msg->rpc_proc = &rpcb_procedures4[RPCBPROC_SET]; + + return rpcb_register_call((struct sockaddr *)&rpcb_in6addr_loopback, + sizeof(rpcb_in6addr_loopback), + RPCBVERS_4, msg, msg->rpc_resp); +} + +/** + * rpcb_v4_register - set or unset a port registration with the local rpcbind + * @program: RPC program number of service to (un)register + * @version: RPC version number of service to (un)register + * @address: address family, IP address, and port to (un)register + * @netid: netid of transport protocol to (un)register + * @result: result code from rpcbind RPC call + * + * RPC services invoke this function to advertise their contact + * information via the system's rpcbind daemon. RPC services + * invoke this function once for each [program, version, address, + * netid] tuple they wish to advertise. + * + * Callers may also unregister RPC services that are no longer + * available by setting the port number in the passed-in address + * to zero. Callers pass a netid of "" to unregister all + * transport netids associated with [program, version, address]. + * + * Returns zero if the registration request was dispatched + * successfully and a reply was received. The rpcbind daemon's + * result code is stored in *result. + * + * Returns an errno value and sets *result to zero if there was + * some problem that prevented the rpcbind request from being + * dispatched, or if the rpcbind daemon did not respond within + * the timeout. + * + * This function uses rpcbind protocol version 4 to contact the + * local rpcbind daemon. The local rpcbind daemon must support + * version 4 of the rpcbind protocol in order for these functions + * to register a service successfully. + * + * Supported netids include "udp" and "tcp" for UDP and TCP over + * IPv4, and "udp6" and "tcp6" for UDP and TCP over IPv6, + * respectively. + * + * The contents of @address determine the address family and the + * port to be registered. The usual practice is to pass INADDR_ANY + * as the raw address, but specifying a non-zero address is also + * supported by this API if the caller wishes to advertise an RPC + * service on a specific network interface. + * + * Note that passing in INADDR_ANY does not create the same service + * registration as IN6ADDR_ANY. The former advertises an RPC + * service on any IPv4 address, but not on IPv6. The latter + * advertises the service on all IPv4 and IPv6 addresses. + */ +int rpcb_v4_register(const u32 program, const u32 version, + const struct sockaddr *address, const char *netid, + int *result) +{ + struct rpcbind_args map = { + .r_prog = program, + .r_vers = version, + .r_netid = netid, + .r_owner = RPCB_OWNER_STRING, + }; + struct rpc_message msg = { + .rpc_argp = &map, + .rpc_resp = result, + }; + + *result = 0; + + switch (address->sa_family) { + case AF_INET: + return rpcb_register_netid4((struct sockaddr_in *)address, + &msg); + case AF_INET6: + return rpcb_register_netid6((struct sockaddr_in6 *)address, + &msg); + } + + return -EAFNOSUPPORT; +} + /** * rpcb_getport_sync - obtain the port for an RPC service on a given host * @sin: address of remote peer -- cgit v1.2.3 From 3be53f3f213223f50d8e29b5e1869685bf040a1e Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 16 Jul 2008 20:33:36 +0200 Subject: ide: move some bits from ide-timing.h to Move struct ide_timing and IDE_TIMING_* defines to from drivers/ide/ide-timing.h. While at it: - use u8/u16 instead of short for struct ide_timing fields - use enum for IDE_TIMING_* There should be no functional changes caused by this patch. Acked-by: Sergei Shtylyov Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/ide-timing.h | 23 ----------------------- include/linux/ide.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/drivers/ide/ide-timing.h b/drivers/ide/ide-timing.h index ebe884d76881..724879910ac8 100644 --- a/drivers/ide/ide-timing.h +++ b/drivers/ide/ide-timing.h @@ -28,18 +28,6 @@ #include #include -struct ide_timing { - u8 mode; - short setup; /* t1 */ - short act8b; /* t2 for 8-bit io */ - short rec8b; /* t2i for 8-bit io */ - short cyc8b; /* t0 for 8-bit io */ - short active; /* t2 or tD */ - short recover; /* t2i or tK */ - short cycle; /* t0 */ - short udma; /* t2CYCTYP/2 */ -}; - /* * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds). * These were taken from ATA/ATAPI-6 standard, rev 0a, except @@ -79,17 +67,6 @@ static struct ide_timing ide_timing[] = { { 0xff } }; -#define IDE_TIMING_SETUP 0x01 -#define IDE_TIMING_ACT8B 0x02 -#define IDE_TIMING_REC8B 0x04 -#define IDE_TIMING_CYC8B 0x08 -#define IDE_TIMING_8BIT 0x0e -#define IDE_TIMING_ACTIVE 0x10 -#define IDE_TIMING_RECOVER 0x20 -#define IDE_TIMING_CYCLE 0x40 -#define IDE_TIMING_UDMA 0x80 -#define IDE_TIMING_ALL 0xff - #define ENOUGH(v,unit) (((v)-1)/(unit)+1) #define EZ(v,unit) ((v)?ENOUGH(v,unit):0) diff --git a/include/linux/ide.h b/include/linux/ide.h index ac4eeb2932ef..81c6ea436beb 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1271,6 +1271,34 @@ static inline int ide_dev_is_sata(struct hd_driveid *id) u64 ide_get_lba_addr(struct ide_taskfile *, int); u8 ide_dump_status(ide_drive_t *, const char *, u8); +struct ide_timing { + u8 mode; + u8 setup; /* t1 */ + u16 act8b; /* t2 for 8-bit io */ + u16 rec8b; /* t2i for 8-bit io */ + u16 cyc8b; /* t0 for 8-bit io */ + u16 active; /* t2 or tD */ + u16 recover; /* t2i or tK */ + u16 cycle; /* t0 */ + u16 udma; /* t2CYCTYP/2 */ +}; + +enum { + IDE_TIMING_SETUP = (1 << 0), + IDE_TIMING_ACT8B = (1 << 1), + IDE_TIMING_REC8B = (1 << 2), + IDE_TIMING_CYC8B = (1 << 3), + IDE_TIMING_8BIT = IDE_TIMING_ACT8B | IDE_TIMING_REC8B | + IDE_TIMING_CYC8B, + IDE_TIMING_ACTIVE = (1 << 4), + IDE_TIMING_RECOVER = (1 << 5), + IDE_TIMING_CYCLE = (1 << 6), + IDE_TIMING_UDMA = (1 << 7), + IDE_TIMING_ALL = IDE_TIMING_SETUP | IDE_TIMING_8BIT | + IDE_TIMING_ACTIVE | IDE_TIMING_RECOVER | + IDE_TIMING_CYCLE | IDE_TIMING_UDMA, +}; + typedef struct ide_pio_timings_s { int setup_time; /* Address setup (ns) minimum */ int active_time; /* Active pulse (ns) minimum */ -- cgit v1.2.3 From f06ab3402aa2d6de060442c1053ea10b24b65076 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 16 Jul 2008 20:33:37 +0200 Subject: ide: convert ide-timing.h to ide-timings.c library (take 2) * Don't include ide-timing.h in cs5535 and sis5513 host drivers (they don't need it currently). * Convert ide-timing.h to ide-timings.c library and add CONFIG_IDE_TIMINGS config option to be selected by host drivers using the library. While at it: - fix ide_timing_find_mode() placement v2: * Add missing EXPORT_SYMBOLs. (Stephen Rothwell ) There should be no functional changes caused by this patch. Cc: Stephen Rothwell Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/Kconfig | 7 ++ drivers/ide/Makefile | 1 + drivers/ide/arm/palm_bk3710.c | 2 - drivers/ide/ide-timing.h | 183 ------------------------------------------ drivers/ide/ide-timings.c | 183 ++++++++++++++++++++++++++++++++++++++++++ drivers/ide/pci/amd74xx.c | 2 - drivers/ide/pci/cs5535.c | 2 - drivers/ide/pci/sis5513.c | 3 - drivers/ide/pci/via82cxxx.c | 2 - drivers/ide/ppc/pmac.c | 2 - include/linux/ide.h | 5 ++ 11 files changed, 196 insertions(+), 196 deletions(-) delete mode 100644 drivers/ide/ide-timing.h create mode 100644 drivers/ide/ide-timings.c (limited to 'include') diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index cd08dba8261b..994b6d39b559 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig @@ -98,6 +98,9 @@ if BLK_DEV_IDE comment "Please see Documentation/ide/ide.txt for help/info on IDE drives" +config IDE_TIMINGS + bool + config IDE_ATAPI bool @@ -469,6 +472,7 @@ config BLK_DEV_ALI15X3 config BLK_DEV_AMD74XX tristate "AMD and nVidia IDE support" depends on !ARM + select IDE_TIMINGS select BLK_DEV_IDEDMA_PCI help This driver adds explicit support for AMD-7xx and AMD-8111 chips @@ -725,6 +729,7 @@ config BLK_DEV_TRM290 config BLK_DEV_VIA82CXXX tristate "VIA82CXXX chipset support" + select IDE_TIMINGS select BLK_DEV_IDEDMA_PCI help This driver adds explicit support for VIA BusMastering IDE chips. @@ -751,6 +756,7 @@ endif config BLK_DEV_IDE_PMAC tristate "PowerMac on-board IDE support" depends on PPC_PMAC && IDE=y && BLK_DEV_IDE=y + select IDE_TIMINGS help This driver provides support for the on-board IDE controller on most of the recent Apple Power Macintoshes and PowerBooks. @@ -912,6 +918,7 @@ config BLK_DEV_Q40IDE config BLK_DEV_PALMCHIP_BK3710 tristate "Palmchip bk3710 IDE controller support" depends on ARCH_DAVINCI + select IDE_TIMINGS select BLK_DEV_IDEDMA_SFF help Say Y here if you want to support the onchip IDE controller on the diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile index a2b3f84d710d..cb1350684c9a 100644 --- a/drivers/ide/Makefile +++ b/drivers/ide/Makefile @@ -14,6 +14,7 @@ EXTRA_CFLAGS += -Idrivers/ide ide-core-y += ide.o ide-io.o ide-iops.o ide-lib.o ide-probe.o ide-taskfile.o # core IDE code +ide-core-$(CONFIG_IDE_TIMINGS) += ide-timings.o ide-core-$(CONFIG_IDE_ATAPI) += ide-atapi.o ide-core-$(CONFIG_BLK_DEV_IDEPCI) += setup-pci.o ide-core-$(CONFIG_BLK_DEV_IDEDMA) += ide-dma.o diff --git a/drivers/ide/arm/palm_bk3710.c b/drivers/ide/arm/palm_bk3710.c index 3839f5722985..9b8a45d2cf17 100644 --- a/drivers/ide/arm/palm_bk3710.c +++ b/drivers/ide/arm/palm_bk3710.c @@ -74,8 +74,6 @@ struct palm_bk3710_udmatiming { #define BK3710_IORDYTMP 0x78 #define BK3710_IORDYTMS 0x7C -#include "../ide-timing.h" - static unsigned ideclk_period; /* in nanoseconds */ static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = { diff --git a/drivers/ide/ide-timing.h b/drivers/ide/ide-timing.h deleted file mode 100644 index 98e05f545450..000000000000 --- a/drivers/ide/ide-timing.h +++ /dev/null @@ -1,183 +0,0 @@ -#ifndef _IDE_TIMING_H -#define _IDE_TIMING_H - -/* - * Copyright (c) 1999-2001 Vojtech Pavlik - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Should you need to contact me, the author, you can do so either by - * e-mail - mail your message to , or by paper mail: - * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic - */ - -#include -#include - -/* - * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds). - * These were taken from ATA/ATAPI-6 standard, rev 0a, except - * for PIO 5, which is a nonstandard extension and UDMA6, which - * is currently supported only by Maxtor drives. - */ - -static struct ide_timing ide_timing[] = { - - { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 }, - { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 }, - { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 }, - { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 }, - - { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 }, - { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, - { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, - - { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, - { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, - { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, - - { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, - { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, - { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, - - { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, - { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 }, - { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 }, - - { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 }, - { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 }, - { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 }, - - { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, - - { 0xff } -}; - -#define ENOUGH(v, unit) (((v) - 1) / (unit) + 1) -#define EZ(v, unit) ((v) ? ENOUGH(v, unit) : 0) - -static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, - int T, int UT) -{ - q->setup = EZ(t->setup * 1000, T); - q->act8b = EZ(t->act8b * 1000, T); - q->rec8b = EZ(t->rec8b * 1000, T); - q->cyc8b = EZ(t->cyc8b * 1000, T); - q->active = EZ(t->active * 1000, T); - q->recover = EZ(t->recover * 1000, T); - q->cycle = EZ(t->cycle * 1000, T); - q->udma = EZ(t->udma * 1000, UT); -} - -static void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, - struct ide_timing *m, unsigned int what) -{ - if (what & IDE_TIMING_SETUP) - m->setup = max(a->setup, b->setup); - if (what & IDE_TIMING_ACT8B) - m->act8b = max(a->act8b, b->act8b); - if (what & IDE_TIMING_REC8B) - m->rec8b = max(a->rec8b, b->rec8b); - if (what & IDE_TIMING_CYC8B) - m->cyc8b = max(a->cyc8b, b->cyc8b); - if (what & IDE_TIMING_ACTIVE) - m->active = max(a->active, b->active); - if (what & IDE_TIMING_RECOVER) - m->recover = max(a->recover, b->recover); - if (what & IDE_TIMING_CYCLE) - m->cycle = max(a->cycle, b->cycle); - if (what & IDE_TIMING_UDMA) - m->udma = max(a->udma, b->udma); -} - -static struct ide_timing *ide_timing_find_mode(u8 speed) -{ - struct ide_timing *t; - - for (t = ide_timing; t->mode != speed; t++) - if (t->mode == 0xff) - return NULL; - return t; -} - -static int ide_timing_compute(ide_drive_t *drive, u8 speed, - struct ide_timing *t, int T, int UT) -{ - struct hd_driveid *id = drive->id; - struct ide_timing *s, p; - - /* - * Find the mode. - */ - s = ide_timing_find_mode(speed); - if (s == NULL) - return -EINVAL; - - /* - * Copy the timing from the table. - */ - *t = *s; - - /* - * If the drive is an EIDE drive, it can tell us it needs extended - * PIO/MWDMA cycle timing. - */ - if (id && id->field_valid & 2) { /* EIDE drive */ - - memset(&p, 0, sizeof(p)); - - if (speed <= XFER_PIO_2) - p.cycle = p.cyc8b = id->eide_pio; - else if (speed <= XFER_PIO_5) - p.cycle = p.cyc8b = id->eide_pio_iordy; - else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) - p.cycle = id->eide_dma_min; - - ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B); - } - - /* - * Convert the timing to bus clock counts. - */ - ide_timing_quantize(t, t, T, UT); - - /* - * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, - * S.M.A.R.T and some other commands. We have to ensure that the - * DMA cycle timing is slower/equal than the fastest PIO timing. - */ - if (speed >= XFER_SW_DMA_0) { - u8 pio = ide_get_best_pio_mode(drive, 255, 5); - ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT); - ide_timing_merge(&p, t, t, IDE_TIMING_ALL); - } - - /* - * Lengthen active & recovery time so that cycle time is correct. - */ - if (t->act8b + t->rec8b < t->cyc8b) { - t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2; - t->rec8b = t->cyc8b - t->act8b; - } - - if (t->active + t->recover < t->cycle) { - t->active += (t->cycle - (t->active + t->recover)) / 2; - t->recover = t->cycle - t->active; - } - - return 0; -} - -#endif diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c new file mode 100644 index 000000000000..ebef6d4e3f63 --- /dev/null +++ b/drivers/ide/ide-timings.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 1999-2001 Vojtech Pavlik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Should you need to contact me, the author, you can do so either by + * e-mail - mail your message to , or by paper mail: + * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic + */ + +#include +#include +#include +#include + +/* + * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds). + * These were taken from ATA/ATAPI-6 standard, rev 0a, except + * for PIO 5, which is a nonstandard extension and UDMA6, which + * is currently supported only by Maxtor drives. + */ + +static struct ide_timing ide_timing[] = { + + { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 }, + { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 }, + { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 }, + { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 }, + + { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 }, + { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, + { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, + + { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, + { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, + { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, + + { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, + { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, + { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, + + { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, + { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 }, + { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 }, + + { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 }, + { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 }, + { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 }, + + { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, + + { 0xff } +}; + +struct ide_timing *ide_timing_find_mode(u8 speed) +{ + struct ide_timing *t; + + for (t = ide_timing; t->mode != speed; t++) + if (t->mode == 0xff) + return NULL; + return t; +} +EXPORT_SYMBOL_GPL(ide_timing_find_mode); + +#define ENOUGH(v, unit) (((v) - 1) / (unit) + 1) +#define EZ(v, unit) ((v) ? ENOUGH(v, unit) : 0) + +static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, + int T, int UT) +{ + q->setup = EZ(t->setup * 1000, T); + q->act8b = EZ(t->act8b * 1000, T); + q->rec8b = EZ(t->rec8b * 1000, T); + q->cyc8b = EZ(t->cyc8b * 1000, T); + q->active = EZ(t->active * 1000, T); + q->recover = EZ(t->recover * 1000, T); + q->cycle = EZ(t->cycle * 1000, T); + q->udma = EZ(t->udma * 1000, UT); +} + +void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, + struct ide_timing *m, unsigned int what) +{ + if (what & IDE_TIMING_SETUP) + m->setup = max(a->setup, b->setup); + if (what & IDE_TIMING_ACT8B) + m->act8b = max(a->act8b, b->act8b); + if (what & IDE_TIMING_REC8B) + m->rec8b = max(a->rec8b, b->rec8b); + if (what & IDE_TIMING_CYC8B) + m->cyc8b = max(a->cyc8b, b->cyc8b); + if (what & IDE_TIMING_ACTIVE) + m->active = max(a->active, b->active); + if (what & IDE_TIMING_RECOVER) + m->recover = max(a->recover, b->recover); + if (what & IDE_TIMING_CYCLE) + m->cycle = max(a->cycle, b->cycle); + if (what & IDE_TIMING_UDMA) + m->udma = max(a->udma, b->udma); +} +EXPORT_SYMBOL_GPL(ide_timing_merge); + +int ide_timing_compute(ide_drive_t *drive, u8 speed, + struct ide_timing *t, int T, int UT) +{ + struct hd_driveid *id = drive->id; + struct ide_timing *s, p; + + /* + * Find the mode. + */ + s = ide_timing_find_mode(speed); + if (s == NULL) + return -EINVAL; + + /* + * Copy the timing from the table. + */ + *t = *s; + + /* + * If the drive is an EIDE drive, it can tell us it needs extended + * PIO/MWDMA cycle timing. + */ + if (id && id->field_valid & 2) { /* EIDE drive */ + + memset(&p, 0, sizeof(p)); + + if (speed <= XFER_PIO_2) + p.cycle = p.cyc8b = id->eide_pio; + else if (speed <= XFER_PIO_5) + p.cycle = p.cyc8b = id->eide_pio_iordy; + else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) + p.cycle = id->eide_dma_min; + + ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B); + } + + /* + * Convert the timing to bus clock counts. + */ + ide_timing_quantize(t, t, T, UT); + + /* + * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, + * S.M.A.R.T and some other commands. We have to ensure that the + * DMA cycle timing is slower/equal than the fastest PIO timing. + */ + if (speed >= XFER_SW_DMA_0) { + u8 pio = ide_get_best_pio_mode(drive, 255, 5); + ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT); + ide_timing_merge(&p, t, t, IDE_TIMING_ALL); + } + + /* + * Lengthen active & recovery time so that cycle time is correct. + */ + if (t->act8b + t->rec8b < t->cyc8b) { + t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2; + t->rec8b = t->cyc8b - t->act8b; + } + + if (t->active + t->recover < t->cycle) { + t->active += (t->cycle - (t->active + t->recover)) / 2; + t->recover = t->cycle - t->active; + } + + return 0; +} +EXPORT_SYMBOL_GPL(ide_timing_compute); diff --git a/drivers/ide/pci/amd74xx.c b/drivers/ide/pci/amd74xx.c index ad222206a429..0bfcdd0e77b3 100644 --- a/drivers/ide/pci/amd74xx.c +++ b/drivers/ide/pci/amd74xx.c @@ -21,8 +21,6 @@ #include #include -#include "ide-timing.h" - enum { AMD_IDE_CONFIG = 0x41, AMD_CABLE_DETECT = 0x42, diff --git a/drivers/ide/pci/cs5535.c b/drivers/ide/pci/cs5535.c index 2a2cb4911905..dc97c48623f3 100644 --- a/drivers/ide/pci/cs5535.c +++ b/drivers/ide/pci/cs5535.c @@ -26,8 +26,6 @@ #include #include -#include "ide-timing.h" - #define MSR_ATAC_BASE 0x51300000 #define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0) #define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01) diff --git a/drivers/ide/pci/sis5513.c b/drivers/ide/pci/sis5513.c index e127eb25ab63..2389945ca95d 100644 --- a/drivers/ide/pci/sis5513.c +++ b/drivers/ide/pci/sis5513.c @@ -52,8 +52,6 @@ #include #include -#include "ide-timing.h" - /* registers layout and init values are chipset family dependant */ #define ATA_16 0x01 @@ -616,7 +614,6 @@ MODULE_LICENSE("GPL"); /* * TODO: * - CLEANUP - * - Use drivers/ide/ide-timing.h ! * - More checks in the config registers (force values instead of * relying on the BIOS setting them correctly). * - Further optimisations ? diff --git a/drivers/ide/pci/via82cxxx.c b/drivers/ide/pci/via82cxxx.c index 3ed9728abd24..e47384c70c40 100644 --- a/drivers/ide/pci/via82cxxx.c +++ b/drivers/ide/pci/via82cxxx.c @@ -35,8 +35,6 @@ #include #endif -#include "ide-timing.h" - #define VIA_IDE_ENABLE 0x40 #define VIA_IDE_CONFIG 0x41 #define VIA_FIFO_CONFIG 0x43 diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c index dcb2c466bb97..5b91d23269d3 100644 --- a/drivers/ide/ppc/pmac.c +++ b/drivers/ide/ppc/pmac.c @@ -48,8 +48,6 @@ #include #endif -#include "../ide-timing.h" - #undef IDE_PMAC_DEBUG #define DMA_WAIT_TIMEOUT 50 diff --git a/include/linux/ide.h b/include/linux/ide.h index 81c6ea436beb..057001f6b1dc 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1299,6 +1299,11 @@ enum { IDE_TIMING_CYCLE | IDE_TIMING_UDMA, }; +struct ide_timing *ide_timing_find_mode(u8); +void ide_timing_merge(struct ide_timing *, struct ide_timing *, + struct ide_timing *, unsigned int); +int ide_timing_compute(ide_drive_t *, u8, struct ide_timing *, int, int); + typedef struct ide_pio_timings_s { int setup_time; /* Address setup (ns) minimum */ int active_time; /* Active pulse (ns) minimum */ -- cgit v1.2.3 From c9d6c1a2379373219bb3271bdcbdc0ab2edf349d Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 16 Jul 2008 20:33:39 +0200 Subject: ide: move ide_pio_cycle_time() to ide-timings.c All ide_pio_cycle_time() users already select CONFIG_IDE_TIMINGS so move the function from ide-lib.c to ide-timings.c. While at it: - convert ide_pio_cycle_time() to use ide_timing_find_mode() - cleanup ide_pio_cycle_time() a bit There should be no functional changes caused by this patch. Acked-by: Sergei Shtylyov Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/ide-lib.c | 23 ----------------------- drivers/ide/ide-timings.c | 22 ++++++++++++++++++++++ include/linux/ide.h | 2 +- 3 files changed, 23 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/drivers/ide/ide-lib.c b/drivers/ide/ide-lib.c index 7e053d217732..efa5bfa64d01 100644 --- a/drivers/ide/ide-lib.c +++ b/drivers/ide/ide-lib.c @@ -188,29 +188,6 @@ static int ide_scan_pio_blacklist (char *model) return -1; } -unsigned int ide_pio_cycle_time(ide_drive_t *drive, u8 pio) -{ - struct hd_driveid *id = drive->id; - int cycle_time = 0; - - if (id->field_valid & 2) { - if (id->capability & 8) - cycle_time = id->eide_pio_iordy; - else - cycle_time = id->eide_pio; - } - - /* conservative "downgrade" for all pre-ATA2 drives */ - if (pio < 3) { - if (cycle_time && cycle_time < ide_pio_timings[pio].cycle_time) - cycle_time = 0; /* use standard timing */ - } - - return cycle_time ? cycle_time : ide_pio_timings[pio].cycle_time; -} - -EXPORT_SYMBOL_GPL(ide_pio_cycle_time); - /** * ide_get_best_pio_mode - get PIO mode from drive * @drive: drive to consider diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c index ebef6d4e3f63..8c2f8327f487 100644 --- a/drivers/ide/ide-timings.c +++ b/drivers/ide/ide-timings.c @@ -1,5 +1,6 @@ /* * Copyright (c) 1999-2001 Vojtech Pavlik + * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,6 +76,27 @@ struct ide_timing *ide_timing_find_mode(u8 speed) } EXPORT_SYMBOL_GPL(ide_timing_find_mode); +u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio) +{ + struct hd_driveid *id = drive->id; + struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); + u16 cycle = 0; + + if (id->field_valid & 2) { + if (id->capability & 8) + cycle = id->eide_pio_iordy; + else + cycle = id->eide_pio; + + /* conservative "downgrade" for all pre-ATA2 drives */ + if (pio < 3 && cycle < t->cycle) + cycle = 0; /* use standard timing */ + } + + return cycle ? cycle : t->cycle; +} +EXPORT_SYMBOL_GPL(ide_pio_cycle_time); + #define ENOUGH(v, unit) (((v) - 1) / (unit) + 1) #define EZ(v, unit) ((v) ? ENOUGH(v, unit) : 0) diff --git a/include/linux/ide.h b/include/linux/ide.h index 057001f6b1dc..3899c761b302 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1300,6 +1300,7 @@ enum { }; struct ide_timing *ide_timing_find_mode(u8); +u16 ide_pio_cycle_time(ide_drive_t *, u8); void ide_timing_merge(struct ide_timing *, struct ide_timing *, struct ide_timing *, unsigned int); int ide_timing_compute(ide_drive_t *, u8, struct ide_timing *, int, int); @@ -1311,7 +1312,6 @@ typedef struct ide_pio_timings_s { /* active + recovery (+ setup for some chips) */ } ide_pio_timings_t; -unsigned int ide_pio_cycle_time(ide_drive_t *, u8); u8 ide_get_best_pio_mode(ide_drive_t *, u8, u8); extern const ide_pio_timings_t ide_pio_timings[6]; -- cgit v1.2.3 From 3e153cfb5e38ae237ff27a10a833946ac95db8a4 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 16 Jul 2008 20:33:39 +0200 Subject: ide: remove no longer used ide_pio_timings[] Acked-by: Sergei Shtylyov Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/ide-lib.c | 17 ----------------- include/linux/ide.h | 8 -------- 2 files changed, 25 deletions(-) (limited to 'include') diff --git a/drivers/ide/ide-lib.c b/drivers/ide/ide-lib.c index efa5bfa64d01..3e12f229bd5f 100644 --- a/drivers/ide/ide-lib.c +++ b/drivers/ide/ide-lib.c @@ -75,23 +75,6 @@ static u8 ide_rate_filter(ide_drive_t *drive, u8 speed) return min(speed, mode); } -/* - * Standard (generic) timings for PIO modes, from ATA2 specification. - * These timings are for access to the IDE data port register *only*. - * Some drives may specify a mode, while also specifying a different - * value for cycle_time (from drive identification data). - */ -const ide_pio_timings_t ide_pio_timings[6] = { - { 70, 165, 600 }, /* PIO Mode 0 */ - { 50, 125, 383 }, /* PIO Mode 1 */ - { 30, 100, 240 }, /* PIO Mode 2 */ - { 30, 80, 180 }, /* PIO Mode 3 with IORDY */ - { 25, 70, 120 }, /* PIO Mode 4 with IORDY */ - { 20, 50, 100 } /* PIO Mode 5 with IORDY (nonstandard) */ -}; - -EXPORT_SYMBOL_GPL(ide_pio_timings); - /* * Shared data/functions for determining best PIO mode for an IDE drive. * Most of this stuff originally lived in cmd640.c, and changes to the diff --git a/include/linux/ide.h b/include/linux/ide.h index 3899c761b302..4e44525fa5ca 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1305,15 +1305,7 @@ void ide_timing_merge(struct ide_timing *, struct ide_timing *, struct ide_timing *, unsigned int); int ide_timing_compute(ide_drive_t *, u8, struct ide_timing *, int, int); -typedef struct ide_pio_timings_s { - int setup_time; /* Address setup (ns) minimum */ - int active_time; /* Active pulse (ns) minimum */ - int cycle_time; /* Cycle time (ns) minimum = */ - /* active + recovery (+ setup for some chips) */ -} ide_pio_timings_t; - u8 ide_get_best_pio_mode(ide_drive_t *, u8, u8); -extern const ide_pio_timings_t ide_pio_timings[6]; int ide_set_pio_mode(ide_drive_t *, u8); int ide_set_dma_mode(ide_drive_t *, u8); -- cgit v1.2.3 From 9ad540937554a3779c5fe7af13aa390b1d2aeb3e Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 16 Jul 2008 20:33:39 +0200 Subject: ide: move PIO blacklist to ide-pio-blacklist.c Move PIO blacklist to ide-pio-blacklist.c. While at it: - fix comment - fix whitespace damage There should be no functional changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/Makefile | 3 +- drivers/ide/ide-lib.c | 96 ----------------------------------------- drivers/ide/ide-pio-blacklist.c | 94 ++++++++++++++++++++++++++++++++++++++++ include/linux/ide.h | 2 + 4 files changed, 98 insertions(+), 97 deletions(-) create mode 100644 drivers/ide/ide-pio-blacklist.c (limited to 'include') diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile index cb1350684c9a..8605536ea18f 100644 --- a/drivers/ide/Makefile +++ b/drivers/ide/Makefile @@ -11,7 +11,8 @@ EXTRA_CFLAGS += -Idrivers/ide -ide-core-y += ide.o ide-io.o ide-iops.o ide-lib.o ide-probe.o ide-taskfile.o +ide-core-y += ide.o ide-io.o ide-iops.o ide-lib.o ide-probe.o ide-taskfile.o \ + ide-pio-blacklist.o # core IDE code ide-core-$(CONFIG_IDE_TIMINGS) += ide-timings.o diff --git a/drivers/ide/ide-lib.c b/drivers/ide/ide-lib.c index 3e12f229bd5f..13af72f09ec4 100644 --- a/drivers/ide/ide-lib.c +++ b/drivers/ide/ide-lib.c @@ -75,102 +75,6 @@ static u8 ide_rate_filter(ide_drive_t *drive, u8 speed) return min(speed, mode); } -/* - * Shared data/functions for determining best PIO mode for an IDE drive. - * Most of this stuff originally lived in cmd640.c, and changes to the - * ide_pio_blacklist[] table should be made with EXTREME CAUTION to avoid - * breaking the fragile cmd640.c support. - */ - -/* - * Black list. Some drives incorrectly report their maximal PIO mode, - * at least in respect to CMD640. Here we keep info on some known drives. - */ -static struct ide_pio_info { - const char *name; - int pio; -} ide_pio_blacklist [] = { - { "Conner Peripherals 540MB - CFS540A", 3 }, - - { "WDC AC2700", 3 }, - { "WDC AC2540", 3 }, - { "WDC AC2420", 3 }, - { "WDC AC2340", 3 }, - { "WDC AC2250", 0 }, - { "WDC AC2200", 0 }, - { "WDC AC21200", 4 }, - { "WDC AC2120", 0 }, - { "WDC AC2850", 3 }, - { "WDC AC1270", 3 }, - { "WDC AC1170", 1 }, - { "WDC AC1210", 1 }, - { "WDC AC280", 0 }, - { "WDC AC31000", 3 }, - { "WDC AC31200", 3 }, - - { "Maxtor 7131 AT", 1 }, - { "Maxtor 7171 AT", 1 }, - { "Maxtor 7213 AT", 1 }, - { "Maxtor 7245 AT", 1 }, - { "Maxtor 7345 AT", 1 }, - { "Maxtor 7546 AT", 3 }, - { "Maxtor 7540 AV", 3 }, - - { "SAMSUNG SHD-3121A", 1 }, - { "SAMSUNG SHD-3122A", 1 }, - { "SAMSUNG SHD-3172A", 1 }, - - { "ST5660A", 3 }, - { "ST3660A", 3 }, - { "ST3630A", 3 }, - { "ST3655A", 3 }, - { "ST3391A", 3 }, - { "ST3390A", 1 }, - { "ST3600A", 1 }, - { "ST3290A", 0 }, - { "ST3144A", 0 }, - { "ST3491A", 1 }, /* reports 3, should be 1 or 2 (depending on */ - /* drive) according to Seagates FIND-ATA program */ - - { "QUANTUM ELS127A", 0 }, - { "QUANTUM ELS170A", 0 }, - { "QUANTUM LPS240A", 0 }, - { "QUANTUM LPS210A", 3 }, - { "QUANTUM LPS270A", 3 }, - { "QUANTUM LPS365A", 3 }, - { "QUANTUM LPS540A", 3 }, - { "QUANTUM LIGHTNING 540A", 3 }, - { "QUANTUM LIGHTNING 730A", 3 }, - - { "QUANTUM FIREBALL_540", 3 }, /* Older Quantum Fireballs don't work */ - { "QUANTUM FIREBALL_640", 3 }, - { "QUANTUM FIREBALL_1080", 3 }, - { "QUANTUM FIREBALL_1280", 3 }, - { NULL, 0 } -}; - -/** - * ide_scan_pio_blacklist - check for a blacklisted drive - * @model: Drive model string - * - * This routine searches the ide_pio_blacklist for an entry - * matching the start/whole of the supplied model name. - * - * Returns -1 if no match found. - * Otherwise returns the recommended PIO mode from ide_pio_blacklist[]. - */ - -static int ide_scan_pio_blacklist (char *model) -{ - struct ide_pio_info *p; - - for (p = ide_pio_blacklist; p->name != NULL; p++) { - if (strncmp(p->name, model, strlen(p->name)) == 0) - return p->pio; - } - return -1; -} - /** * ide_get_best_pio_mode - get PIO mode from drive * @drive: drive to consider diff --git a/drivers/ide/ide-pio-blacklist.c b/drivers/ide/ide-pio-blacklist.c new file mode 100644 index 000000000000..a8c2c8f8660a --- /dev/null +++ b/drivers/ide/ide-pio-blacklist.c @@ -0,0 +1,94 @@ +/* + * PIO blacklist. Some drives incorrectly report their maximal PIO mode, + * at least in respect to CMD640. Here we keep info on some known drives. + * + * Changes to the ide_pio_blacklist[] should be made with EXTREME CAUTION + * to avoid breaking the fragile cmd640.c support. + */ + +#include + +static struct ide_pio_info { + const char *name; + int pio; +} ide_pio_blacklist [] = { + { "Conner Peripherals 540MB - CFS540A", 3 }, + + { "WDC AC2700", 3 }, + { "WDC AC2540", 3 }, + { "WDC AC2420", 3 }, + { "WDC AC2340", 3 }, + { "WDC AC2250", 0 }, + { "WDC AC2200", 0 }, + { "WDC AC21200", 4 }, + { "WDC AC2120", 0 }, + { "WDC AC2850", 3 }, + { "WDC AC1270", 3 }, + { "WDC AC1170", 1 }, + { "WDC AC1210", 1 }, + { "WDC AC280", 0 }, + { "WDC AC31000", 3 }, + { "WDC AC31200", 3 }, + + { "Maxtor 7131 AT", 1 }, + { "Maxtor 7171 AT", 1 }, + { "Maxtor 7213 AT", 1 }, + { "Maxtor 7245 AT", 1 }, + { "Maxtor 7345 AT", 1 }, + { "Maxtor 7546 AT", 3 }, + { "Maxtor 7540 AV", 3 }, + + { "SAMSUNG SHD-3121A", 1 }, + { "SAMSUNG SHD-3122A", 1 }, + { "SAMSUNG SHD-3172A", 1 }, + + { "ST5660A", 3 }, + { "ST3660A", 3 }, + { "ST3630A", 3 }, + { "ST3655A", 3 }, + { "ST3391A", 3 }, + { "ST3390A", 1 }, + { "ST3600A", 1 }, + { "ST3290A", 0 }, + { "ST3144A", 0 }, + { "ST3491A", 1 }, /* reports 3, should be 1 or 2 (depending on drive) + according to Seagate's FIND-ATA program */ + + { "QUANTUM ELS127A", 0 }, + { "QUANTUM ELS170A", 0 }, + { "QUANTUM LPS240A", 0 }, + { "QUANTUM LPS210A", 3 }, + { "QUANTUM LPS270A", 3 }, + { "QUANTUM LPS365A", 3 }, + { "QUANTUM LPS540A", 3 }, + { "QUANTUM LIGHTNING 540A", 3 }, + { "QUANTUM LIGHTNING 730A", 3 }, + + { "QUANTUM FIREBALL_540", 3 }, /* Older Quantum Fireballs don't work */ + { "QUANTUM FIREBALL_640", 3 }, + { "QUANTUM FIREBALL_1080", 3 }, + { "QUANTUM FIREBALL_1280", 3 }, + { NULL, 0 } +}; + +/** + * ide_scan_pio_blacklist - check for a blacklisted drive + * @model: Drive model string + * + * This routine searches the ide_pio_blacklist for an entry + * matching the start/whole of the supplied model name. + * + * Returns -1 if no match found. + * Otherwise returns the recommended PIO mode from ide_pio_blacklist[]. + */ + +int ide_scan_pio_blacklist(char *model) +{ + struct ide_pio_info *p; + + for (p = ide_pio_blacklist; p->name != NULL; p++) { + if (strncmp(p->name, model, strlen(p->name)) == 0) + return p->pio; + } + return -1; +} diff --git a/include/linux/ide.h b/include/linux/ide.h index 4e44525fa5ca..535c439fd8f0 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1305,6 +1305,8 @@ void ide_timing_merge(struct ide_timing *, struct ide_timing *, struct ide_timing *, unsigned int); int ide_timing_compute(ide_drive_t *, u8, struct ide_timing *, int, int); +int ide_scan_pio_blacklist(char *); + u8 ide_get_best_pio_mode(ide_drive_t *, u8, u8); int ide_set_pio_mode(ide_drive_t *, u8); -- cgit v1.2.3 From 63b51c6d1d63276fd320615c042f1ff5d94ebab8 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 16 Jul 2008 20:33:40 +0200 Subject: ide: make ide_hwifs[] static Move ide_hwifs[] from ide.c to ide-probe.c and make it static. Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/ide-probe.c | 2 ++ drivers/ide/ide.c | 2 -- include/linux/ide.h | 12 ------------ 3 files changed, 2 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c index 592d424412ea..97dda05914a1 100644 --- a/drivers/ide/ide-probe.c +++ b/drivers/ide/ide-probe.c @@ -39,6 +39,8 @@ #include #include +static ide_hwif_t ide_hwifs[MAX_HWIFS]; /* master data repository */ + /** * generic_id - add a generic drive id * @drive: drive to make an ID block for diff --git a/drivers/ide/ide.c b/drivers/ide/ide.c index 32d8ee281d56..b7855a13f0ef 100644 --- a/drivers/ide/ide.c +++ b/drivers/ide/ide.c @@ -91,8 +91,6 @@ DEFINE_MUTEX(ide_cfg_mtx); __cacheline_aligned_in_smp DEFINE_SPINLOCK(ide_lock); EXPORT_SYMBOL(ide_lock); -ide_hwif_t ide_hwifs[MAX_HWIFS]; /* master data repository */ - static void ide_port_init_devices_data(ide_hwif_t *); /* diff --git a/include/linux/ide.h b/include/linux/ide.h index 535c439fd8f0..15d5668198a6 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -801,18 +801,6 @@ struct ide_driver_s { int generic_ide_ioctl(ide_drive_t *, struct file *, struct block_device *, unsigned, unsigned long); -/* - * ide_hwifs[] is the master data structure used to keep track - * of just about everything in ide.c. Whenever possible, routines - * should be using pointers to a drive (ide_drive_t *) or - * pointers to a hwif (ide_hwif_t *), rather than indexing this - * structure directly (the allocation/layout may change!). - * - */ -#ifndef _IDE_C -extern ide_hwif_t ide_hwifs[]; /* master data repository */ -#endif - extern int ide_vlb_clk; extern int ide_pci_clk; -- cgit v1.2.3 From c56c5648a3bd15ff14c50f284b261140cd5b5472 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 16 Jul 2008 20:33:40 +0200 Subject: ide: set hwif->dev in ide_init_port_hw() (take 2) * Add 'parent' field to hw_regs_t for optional parent device pointer (needed by macio PMAC IDE controllers) and set hwif->dev in ide_init_port_hw(). * Update au1xxx-ide.c, sgiioc4.c, pmac.c and setup-pci.c accordingly. v2: * Update scc_pata.c. There should be no functional changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/ide.c | 3 ++- drivers/ide/mips/au1xxx-ide.c | 2 -- drivers/ide/pci/scc_pata.c | 1 - drivers/ide/pci/sgiioc4.c | 2 -- drivers/ide/ppc/pmac.c | 6 ++---- drivers/ide/setup-pci.c | 2 -- include/linux/ide.h | 2 +- 7 files changed, 5 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/drivers/ide/ide.c b/drivers/ide/ide.c index b7855a13f0ef..9240888e5efd 100644 --- a/drivers/ide/ide.c +++ b/drivers/ide/ide.c @@ -297,7 +297,8 @@ void ide_init_port_hw(ide_hwif_t *hwif, hw_regs_t *hw) memcpy(&hwif->io_ports, &hw->io_ports, sizeof(hwif->io_ports)); hwif->irq = hw->irq; hwif->chipset = hw->chipset; - hwif->gendev.parent = hw->dev; + hwif->dev = hw->dev; + hwif->gendev.parent = hw->parent ? hw->parent : hw->dev; hwif->ack_intr = hw->ack_intr; } EXPORT_SYMBOL_GPL(ide_init_port_hw); diff --git a/drivers/ide/mips/au1xxx-ide.c b/drivers/ide/mips/au1xxx-ide.c index 1a6c27b32498..08c46c36b7e7 100644 --- a/drivers/ide/mips/au1xxx-ide.c +++ b/drivers/ide/mips/au1xxx-ide.c @@ -600,8 +600,6 @@ static int au_ide_probe(struct device *dev) ide_init_port_hw(hwif, &hw); - hwif->dev = dev; - /* If the user has selected DDMA assisted copies, then set up a few local I/O function entry points */ diff --git a/drivers/ide/pci/scc_pata.c b/drivers/ide/pci/scc_pata.c index 1584ebb6a185..71bff3131b96 100644 --- a/drivers/ide/pci/scc_pata.c +++ b/drivers/ide/pci/scc_pata.c @@ -572,7 +572,6 @@ static int scc_ide_setup_pci_device(struct pci_dev *dev, hw.dev = &dev->dev; hw.chipset = ide_pci; ide_init_port_hw(hwif, &hw); - hwif->dev = &dev->dev; idx[0] = hwif->index; diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c index 24513e3dcd6b..af91cc525789 100644 --- a/drivers/ide/pci/sgiioc4.c +++ b/drivers/ide/pci/sgiioc4.c @@ -625,8 +625,6 @@ sgiioc4_ide_setup_pci_device(struct pci_dev *dev) hw.dev = &dev->dev; ide_init_port_hw(hwif, &hw); - hwif->dev = &dev->dev; - /* The IOC4 uses MMIO rather than Port IO. */ default_hwif_mmiops(hwif); diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c index cfa103a51b31..93fb9067c043 100644 --- a/drivers/ide/ppc/pmac.c +++ b/drivers/ide/ppc/pmac.c @@ -1148,8 +1148,6 @@ pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match) base = ioremap(macio_resource_start(mdev, 0), 0x400); regbase = (unsigned long) base; - hwif->dev = &mdev->bus->pdev->dev; - pmif->mdev = mdev; pmif->node = mdev->ofdev.node; pmif->regbase = regbase; @@ -1171,7 +1169,8 @@ pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match) memset(&hw, 0, sizeof(hw)); pmac_ide_init_ports(&hw, pmif->regbase); hw.irq = irq; - hw.dev = &mdev->ofdev.dev; + hw.dev = &mdev->bus->pdev->dev; + hw.parent = &mdev->ofdev.dev; rc = pmac_ide_setup_device(pmif, hwif, &hw); if (rc != 0) { @@ -1271,7 +1270,6 @@ pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id) goto out_free_pmif; } - hwif->dev = &pdev->dev; pmif->mdev = NULL; pmif->node = np; diff --git a/drivers/ide/setup-pci.c b/drivers/ide/setup-pci.c index abcfb1739d4d..3dea5a59626e 100644 --- a/drivers/ide/setup-pci.c +++ b/drivers/ide/setup-pci.c @@ -346,8 +346,6 @@ static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, ide_init_port_hw(hwif, &hw); - hwif->dev = &dev->dev; - return hwif; } diff --git a/include/linux/ide.h b/include/linux/ide.h index 15d5668198a6..a6a2eccb6526 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -171,7 +171,7 @@ typedef struct hw_regs_s { int irq; /* our irq number */ ide_ack_intr_t *ack_intr; /* acknowledge interrupt */ hwif_chipset_t chipset; - struct device *dev; + struct device *dev, *parent; } hw_regs_t; void ide_init_port_data(struct hwif_s *, unsigned int); -- cgit v1.2.3 From e6d95bd14928926d6658b5e4ace905e8b83ed27a Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 16 Jul 2008 20:33:42 +0200 Subject: ide: ->port_init_devs -> ->init_dev Change ->port_init_devs method to take 'ide_drive_t *' as an argument instead of 'ide_hwif_t *' and rename it to ->init_dev. There should be no functional changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/ide-probe.c | 6 +++--- drivers/ide/legacy/ht6560b.c | 8 ++++---- drivers/ide/legacy/ide-4drives.c | 10 ++++------ drivers/ide/legacy/qd65xx.c | 16 ++++++++-------- include/linux/ide.h | 4 ++-- 5 files changed, 21 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c index 97dda05914a1..c5dc18849303 100644 --- a/drivers/ide/ide-probe.c +++ b/drivers/ide/ide-probe.c @@ -1320,10 +1320,10 @@ static void ide_port_init_devices(ide_hwif_t *hwif) drive->unmask = 1; if (hwif->host_flags & IDE_HFLAG_NO_UNMASK_IRQS) drive->no_unmask = 1; - } - if (port_ops && port_ops->port_init_devs) - port_ops->port_init_devs(hwif); + if (port_ops && port_ops->init_dev) + port_ops->init_dev(drive); + } } static void ide_init_port(ide_hwif_t *hwif, unsigned int port, diff --git a/drivers/ide/legacy/ht6560b.c b/drivers/ide/legacy/ht6560b.c index bd2f579946fa..7bc8fd59ea9e 100644 --- a/drivers/ide/legacy/ht6560b.c +++ b/drivers/ide/legacy/ht6560b.c @@ -310,16 +310,16 @@ static void ht6560b_set_pio_mode(ide_drive_t *drive, const u8 pio) #endif } -static void __init ht6560b_port_init_devs(ide_hwif_t *hwif) +static void __init ht6560b_init_dev(ide_drive_t *drive) { + ide_hwif_t *hwif = drive->hwif; /* Setting default configurations for drives. */ int t = (HT_CONFIG_DEFAULT << 8) | HT_TIMING_DEFAULT; if (hwif->channel) t |= (HT_SECONDARY_IF << 8); - hwif->drives[0].drive_data = t; - hwif->drives[1].drive_data = t; + drive->drive_data = t; } static int probe_ht6560b; @@ -328,7 +328,7 @@ module_param_named(probe, probe_ht6560b, bool, 0); MODULE_PARM_DESC(probe, "probe for HT6560B chipset"); static const struct ide_port_ops ht6560b_port_ops = { - .port_init_devs = ht6560b_port_init_devs, + .init_dev = ht6560b_init_dev, .set_pio_mode = ht6560b_set_pio_mode, .selectproc = ht6560b_selectproc, }; diff --git a/drivers/ide/legacy/ide-4drives.c b/drivers/ide/legacy/ide-4drives.c index 5cd6ce537eea..89c8ff0a4d08 100644 --- a/drivers/ide/legacy/ide-4drives.c +++ b/drivers/ide/legacy/ide-4drives.c @@ -11,16 +11,14 @@ static int probe_4drives; module_param_named(probe, probe_4drives, bool, 0); MODULE_PARM_DESC(probe, "probe for generic IDE chipset with 4 drives/port"); -static void ide_4drives_port_init_devs(ide_hwif_t *hwif) +static void ide_4drives_init_dev(ide_drive_t *drive) { - if (hwif->channel) { - hwif->drives[0].select.all ^= 0x20; - hwif->drives[1].select.all ^= 0x20; - } + if (drive->hwif->channel) + drive->select.all ^= 0x20; } static const struct ide_port_ops ide_4drives_port_ops = { - .port_init_devs = ide_4drives_port_init_devs, + .init_dev = ide_4drives_init_dev, }; static const struct ide_port_info ide_4drives_port_info = { diff --git a/drivers/ide/legacy/qd65xx.c b/drivers/ide/legacy/qd65xx.c index 63f6c31d16ea..2338f344ea24 100644 --- a/drivers/ide/legacy/qd65xx.c +++ b/drivers/ide/legacy/qd65xx.c @@ -282,17 +282,18 @@ static int __init qd_testreg(int port) return (readreg != QD_TESTVAL); } -static void __init qd6500_port_init_devs(ide_hwif_t *hwif) +static void __init qd6500_init_dev(ide_drive_t *drive) { + ide_hwif_t *hwif = drive->hwif; u8 base = (hwif->config_data & 0xff00) >> 8; u8 config = QD_CONFIG(hwif); - hwif->drives[0].drive_data = QD6500_DEF_DATA; - hwif->drives[1].drive_data = QD6500_DEF_DATA; + drive->drive_data = QD6500_DEF_DATA; } -static void __init qd6580_port_init_devs(ide_hwif_t *hwif) +static void __init qd6580_init_dev(ide_drive_t *drive) { + ide_hwif_t *hwif = drive->hwif; u16 t1, t2; u8 base = (hwif->config_data & 0xff00) >> 8; u8 config = QD_CONFIG(hwif); @@ -303,18 +304,17 @@ static void __init qd6580_port_init_devs(ide_hwif_t *hwif) } else t2 = t1 = hwif->channel ? QD6580_DEF_DATA2 : QD6580_DEF_DATA; - hwif->drives[0].drive_data = t1; - hwif->drives[1].drive_data = t2; + drive->drive_data = drive->select.b.unit ? t2 : t1; } static const struct ide_port_ops qd6500_port_ops = { - .port_init_devs = qd6500_port_init_devs, + .init_dev = qd6500_init_dev, .set_pio_mode = qd6500_set_pio_mode, .selectproc = qd65xx_select, }; static const struct ide_port_ops qd6580_port_ops = { - .port_init_devs = qd6580_port_init_devs, + .init_dev = qd6580_init_dev, .set_pio_mode = qd6580_set_pio_mode, .selectproc = qd65xx_select, }; diff --git a/include/linux/ide.h b/include/linux/ide.h index a6a2eccb6526..f9cbe9350cad 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -405,8 +405,8 @@ typedef struct ide_drive_s { struct ide_port_info; struct ide_port_ops { - /* host specific initialization of devices on a port */ - void (*port_init_devs)(struct hwif_s *); + /* host specific initialization of a device */ + void (*init_dev)(ide_drive_t *); /* routine to program host for PIO mode */ void (*set_pio_mode)(ide_drive_t *, const u8); /* routine to program host for DMA mode */ -- cgit v1.2.3 From 79e36a9f54aaf4a52eb2d9520953aa3960e99294 Mon Sep 17 00:00:00 2001 From: Elias Oltmanns Date: Wed, 16 Jul 2008 20:33:48 +0200 Subject: IDE: Fix HDIO_DRIVE_RESET handling Currently, the code path executing an HDIO_DRIVE_RESET ioctl is broken in various ways. Most importantly, it is treated as an out of band request in an illegal way which may very likely lead to system lock ups. Use the drive's request queue to avoid this problem (and fix a locking issue for free along the way). Signed-off-by: Elias Oltmanns Cc: "Alan Cox" Cc: "Randy Dunlap" Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/ide-io.c | 23 ++++++++++++++++++++++- drivers/ide/ide-iops.c | 18 +++++++++++++----- drivers/ide/ide.c | 41 +++++++++++++++-------------------------- include/linux/ide.h | 6 ++++++ 4 files changed, 56 insertions(+), 32 deletions(-) (limited to 'include') diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c index 28057747c1f8..2b33c129740b 100644 --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -766,6 +766,18 @@ static ide_startstop_t execute_drive_cmd (ide_drive_t *drive, return ide_stopped; } +static ide_startstop_t ide_special_rq(ide_drive_t *drive, struct request *rq) +{ + switch (rq->cmd[0]) { + case REQ_DRIVE_RESET: + return ide_do_reset(drive); + default: + blk_dump_rq_flags(rq, "ide_special_rq - bad request"); + ide_end_request(drive, 0, 0); + return ide_stopped; + } +} + static void ide_check_pm_state(ide_drive_t *drive, struct request *rq) { struct request_pm_state *pm = rq->data; @@ -869,7 +881,16 @@ static ide_startstop_t start_request (ide_drive_t *drive, struct request *rq) pm->pm_step == ide_pm_state_completed) ide_complete_pm_request(drive, rq); return startstop; - } + } else if (!rq->rq_disk && blk_special_request(rq)) + /* + * TODO: Once all ULDs have been modified to + * check for specific op codes rather than + * blindly accepting any special request, the + * check for ->rq_disk above may be replaced + * by a more suitable mechanism or even + * dropped entirely. + */ + return ide_special_rq(drive, rq); drv = *(ide_driver_t **)rq->rq_disk->private_data; return drv->do_request(drive, rq, block); diff --git a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c index 80ad4f234f3f..96f63eb12092 100644 --- a/drivers/ide/ide-iops.c +++ b/drivers/ide/ide-iops.c @@ -905,6 +905,14 @@ void ide_execute_pkt_cmd(ide_drive_t *drive) } EXPORT_SYMBOL_GPL(ide_execute_pkt_cmd); +static inline void ide_complete_drive_reset(ide_drive_t *drive) +{ + struct request *rq = drive->hwif->hwgroup->rq; + + if (rq && blk_special_request(rq) && rq->cmd[0] == REQ_DRIVE_RESET) + ide_end_request(drive, 1, 0); +} + /* needed below */ static ide_startstop_t do_reset1 (ide_drive_t *, int); @@ -940,7 +948,7 @@ static ide_startstop_t atapi_reset_pollfunc (ide_drive_t *drive) } /* done polling */ hwgroup->polling = 0; - hwgroup->resetting = 0; + ide_complete_drive_reset(drive); return ide_stopped; } @@ -961,7 +969,7 @@ static ide_startstop_t reset_pollfunc (ide_drive_t *drive) if (port_ops->reset_poll(drive)) { printk(KERN_ERR "%s: host reset_poll failure for %s.\n", hwif->name, drive->name); - return ide_stopped; + goto out; } } @@ -1004,7 +1012,8 @@ static ide_startstop_t reset_pollfunc (ide_drive_t *drive) } } hwgroup->polling = 0; /* done polling */ - hwgroup->resetting = 0; /* done reset attempt */ +out: + ide_complete_drive_reset(drive); return ide_stopped; } @@ -1090,7 +1099,6 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi) /* For an ATAPI device, first try an ATAPI SRST. */ if (drive->media != ide_disk && !do_not_try_atapi) { - hwgroup->resetting = 1; pre_reset(drive); SELECT_DRIVE(drive); udelay (20); @@ -1112,10 +1120,10 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi) if (io_ports->ctl_addr == 0) { spin_unlock_irqrestore(&ide_lock, flags); + ide_complete_drive_reset(drive); return ide_stopped; } - hwgroup->resetting = 1; /* * Note that we also set nIEN while resetting the device, * to mask unwanted interrupts from the interface during the reset. diff --git a/drivers/ide/ide.c b/drivers/ide/ide.c index 90ae00d4aaf5..1ec983b00511 100644 --- a/drivers/ide/ide.c +++ b/drivers/ide/ide.c @@ -529,6 +529,19 @@ static int generic_ide_resume(struct device *dev) return err; } +static void generic_drive_reset(ide_drive_t *drive) +{ + struct request *rq; + + rq = blk_get_request(drive->queue, READ, __GFP_WAIT); + rq->cmd_type = REQ_TYPE_SPECIAL; + rq->cmd_len = 1; + rq->cmd[0] = REQ_DRIVE_RESET; + rq->cmd_flags |= REQ_SOFTBARRIER; + blk_execute_rq(drive->queue, NULL, rq, 1); + blk_put_request(rq); +} + int generic_ide_ioctl(ide_drive_t *drive, struct file *file, struct block_device *bdev, unsigned int cmd, unsigned long arg) { @@ -603,33 +616,9 @@ int generic_ide_ioctl(ide_drive_t *drive, struct file *file, struct block_device if (!capable(CAP_SYS_ADMIN)) return -EACCES; - /* - * Abort the current command on the - * group if there is one, taking - * care not to allow anything else - * to be queued and to die on the - * spot if we miss one somehow - */ - - spin_lock_irqsave(&ide_lock, flags); - - if (HWGROUP(drive)->resetting) { - spin_unlock_irqrestore(&ide_lock, flags); - return -EBUSY; - } - - ide_abort(drive, "drive reset"); - - BUG_ON(HWGROUP(drive)->handler); - - /* Ensure nothing gets queued after we - drop the lock. Reset will clear the busy */ - - HWGROUP(drive)->busy = 1; - spin_unlock_irqrestore(&ide_lock, flags); - (void) ide_do_reset(drive); - + generic_drive_reset(drive); return 0; + case HDIO_GET_BUSSTATE: if (!capable(CAP_SYS_ADMIN)) return -EACCES; diff --git a/include/linux/ide.h b/include/linux/ide.h index f9cbe9350cad..021710cc1b1c 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -138,6 +138,12 @@ struct ide_io_ports { #define WAIT_CMD (10*HZ) /* 10sec - maximum wait for an IRQ to happen */ #define WAIT_MIN_SLEEP (2*HZ/100) /* 20msec - minimum sleep time */ +/* + * Op codes for special requests to be handled by ide_special_rq(). + * Values should be in the range of 0x20 to 0x3f. + */ +#define REQ_DRIVE_RESET 0x20 + /* * Check for an interrupt and acknowledge the interrupt status */ -- cgit v1.2.3 From 3ef5eb424ebf0cd981192a416358fd707a9f959b Mon Sep 17 00:00:00 2001 From: Elias Oltmanns Date: Wed, 16 Jul 2008 20:33:48 +0200 Subject: IDE: Remove unused code Remove some code which has been made obsolete and hasn't worked properly before anyway. Part of the infrastructure may be reintroduced in a follow up patch to implement a working command aborting facility. Signed-off-by: Elias Oltmanns Cc: "Alan Cox" Cc: "Randy Dunlap" Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/ide-cd.c | 1 - drivers/ide/ide-disk.c | 1 - drivers/ide/ide-floppy.c | 1 - drivers/ide/ide-io.c | 49 ------------------------------------------------ drivers/ide/ide-tape.c | 1 - drivers/scsi/ide-scsi.c | 14 -------------- include/linux/ide.h | 7 ------- 7 files changed, 74 deletions(-) (limited to 'include') diff --git a/drivers/ide/ide-cd.c b/drivers/ide/ide-cd.c index 2b3c69d1f53f..6e29dd532090 100644 --- a/drivers/ide/ide-cd.c +++ b/drivers/ide/ide-cd.c @@ -1952,7 +1952,6 @@ static ide_driver_t ide_cdrom_driver = { .do_request = ide_cd_do_request, .end_request = ide_end_request, .error = __ide_error, - .abort = __ide_abort, #ifdef CONFIG_IDE_PROC_FS .proc = idecd_proc, #endif diff --git a/drivers/ide/ide-disk.c b/drivers/ide/ide-disk.c index 5f49a4ae9dd8..3a2e80237c10 100644 --- a/drivers/ide/ide-disk.c +++ b/drivers/ide/ide-disk.c @@ -985,7 +985,6 @@ static ide_driver_t idedisk_driver = { .do_request = ide_do_rw_disk, .end_request = ide_end_request, .error = __ide_error, - .abort = __ide_abort, #ifdef CONFIG_IDE_PROC_FS .proc = idedisk_proc, #endif diff --git a/drivers/ide/ide-floppy.c b/drivers/ide/ide-floppy.c index c7e4433fcbcf..011d72011cc4 100644 --- a/drivers/ide/ide-floppy.c +++ b/drivers/ide/ide-floppy.c @@ -1129,7 +1129,6 @@ static ide_driver_t idefloppy_driver = { .do_request = idefloppy_do_request, .end_request = idefloppy_end_request, .error = __ide_error, - .abort = __ide_abort, #ifdef CONFIG_IDE_PROC_FS .proc = idefloppy_proc, #endif diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c index 2b33c129740b..661b75a89d4d 100644 --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -504,55 +504,6 @@ ide_startstop_t ide_error (ide_drive_t *drive, const char *msg, u8 stat) EXPORT_SYMBOL_GPL(ide_error); -ide_startstop_t __ide_abort(ide_drive_t *drive, struct request *rq) -{ - if (drive->media != ide_disk) - rq->errors |= ERROR_RESET; - - ide_kill_rq(drive, rq); - - return ide_stopped; -} - -EXPORT_SYMBOL_GPL(__ide_abort); - -/** - * ide_abort - abort pending IDE operations - * @drive: drive the error occurred on - * @msg: message to report - * - * ide_abort kills and cleans up when we are about to do a - * host initiated reset on active commands. Longer term we - * want handlers to have sensible abort handling themselves - * - * This differs fundamentally from ide_error because in - * this case the command is doing just fine when we - * blow it away. - */ - -ide_startstop_t ide_abort(ide_drive_t *drive, const char *msg) -{ - struct request *rq; - - if (drive == NULL || (rq = HWGROUP(drive)->rq) == NULL) - return ide_stopped; - - /* retry only "normal" I/O: */ - if (!blk_fs_request(rq)) { - rq->errors = 1; - ide_end_drive_cmd(drive, BUSY_STAT, 0); - return ide_stopped; - } - - if (rq->rq_disk) { - ide_driver_t *drv; - - drv = *(ide_driver_t **)rq->rq_disk->private_data; - return drv->abort(drive, rq); - } else - return __ide_abort(drive, rq); -} - static void ide_tf_set_specify_cmd(ide_drive_t *drive, struct ide_taskfile *tf) { tf->nsect = drive->sect; diff --git a/drivers/ide/ide-tape.c b/drivers/ide/ide-tape.c index f9cf1670e4e1..b711ab96e287 100644 --- a/drivers/ide/ide-tape.c +++ b/drivers/ide/ide-tape.c @@ -2591,7 +2591,6 @@ static ide_driver_t idetape_driver = { .do_request = idetape_do_request, .end_request = idetape_end_request, .error = __ide_error, - .abort = __ide_abort, #ifdef CONFIG_IDE_PROC_FS .proc = idetape_proc, #endif diff --git a/drivers/scsi/ide-scsi.c b/drivers/scsi/ide-scsi.c index 683bce375c74..f843c1383a4b 100644 --- a/drivers/scsi/ide-scsi.c +++ b/drivers/scsi/ide-scsi.c @@ -258,19 +258,6 @@ idescsi_atapi_error(ide_drive_t *drive, struct request *rq, u8 stat, u8 err) return ide_stopped; } -static ide_startstop_t -idescsi_atapi_abort(ide_drive_t *drive, struct request *rq) -{ - debug_log("%s called for %lu\n", __func__, - ((struct ide_atapi_pc *) rq->special)->scsi_cmd->serial_number); - - rq->errors |= ERROR_MAX; - - idescsi_end_request(drive, 0, 0); - - return ide_stopped; -} - static int idescsi_end_request (ide_drive_t *drive, int uptodate, int nrsecs) { idescsi_scsi_t *scsi = drive_to_idescsi(drive); @@ -524,7 +511,6 @@ static ide_driver_t idescsi_driver = { .do_request = idescsi_do_request, .end_request = idescsi_end_request, .error = idescsi_atapi_error, - .abort = idescsi_atapi_abort, #ifdef CONFIG_IDE_PROC_FS .proc = idescsi_proc, #endif diff --git a/include/linux/ide.h b/include/linux/ide.h index 021710cc1b1c..4726126f5a59 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -571,8 +571,6 @@ typedef struct hwgroup_s { unsigned int sleeping : 1; /* BOOL: polling active & poll_timeout field valid */ unsigned int polling : 1; - /* BOOL: in a polling reset situation. Must not trigger another reset yet */ - unsigned int resetting : 1; /* current drive */ ide_drive_t *drive; @@ -792,7 +790,6 @@ struct ide_driver_s { ide_startstop_t (*do_request)(ide_drive_t *, struct request *, sector_t); int (*end_request)(ide_drive_t *, int, int); ide_startstop_t (*error)(ide_drive_t *, struct request *rq, u8, u8); - ide_startstop_t (*abort)(ide_drive_t *, struct request *rq); struct device_driver gen_driver; int (*probe)(ide_drive_t *); void (*remove)(ide_drive_t *); @@ -834,10 +831,6 @@ ide_startstop_t __ide_error(ide_drive_t *, struct request *, u8, u8); ide_startstop_t ide_error (ide_drive_t *drive, const char *msg, byte stat); -ide_startstop_t __ide_abort(ide_drive_t *, struct request *); - -extern ide_startstop_t ide_abort(ide_drive_t *, const char *); - extern void ide_fix_driveid(struct hd_driveid *); extern void ide_fixstring(u8 *, const int, const int); -- cgit v1.2.3 From 706546d02384b64e083bd9130c56eaa599c66038 Mon Sep 17 00:00:00 2001 From: Mike Travis Date: Mon, 9 Jun 2008 16:22:23 -0700 Subject: ACPI: change processors from array to per_cpu variable Change processors from an array sized by NR_CPUS to a per_cpu variable. Signed-off-by: Mike Travis Signed-off-by: Andrew Morton Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- drivers/acpi/processor_core.c | 20 +++++++++----------- drivers/acpi/processor_idle.c | 8 ++++---- drivers/acpi/processor_perflib.c | 18 +++++++++--------- drivers/acpi/processor_throttling.c | 14 +++++++------- include/acpi/processor.h | 2 +- 5 files changed, 30 insertions(+), 32 deletions(-) (limited to 'include') diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index feddc8ed870a..9a803f85ccfe 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -118,7 +118,7 @@ static const struct file_operations acpi_processor_info_fops = { .release = single_release, }; -struct acpi_processor *processors[NR_CPUS]; +DEFINE_PER_CPU(struct acpi_processor *, processors); struct acpi_processor_errata errata __read_mostly; /* -------------------------------------------------------------------------- @@ -614,7 +614,7 @@ static int acpi_processor_get_info(struct acpi_processor *pr, unsigned has_uid) return 0; } -static void *processor_device_array[NR_CPUS]; +static DEFINE_PER_CPU(void *, processor_device_array); static int __cpuinit acpi_processor_start(struct acpi_device *device) { @@ -638,15 +638,15 @@ static int __cpuinit acpi_processor_start(struct acpi_device *device) * ACPI id of processors can be reported wrongly by the BIOS. * Don't trust it blindly */ - if (processor_device_array[pr->id] != NULL && - processor_device_array[pr->id] != device) { + if (per_cpu(processor_device_array, pr->id) != NULL && + per_cpu(processor_device_array, pr->id) != device) { printk(KERN_WARNING "BIOS reported wrong ACPI id " "for the processor\n"); return -ENODEV; } - processor_device_array[pr->id] = device; + per_cpu(processor_device_array, pr->id) = device; - processors[pr->id] = pr; + per_cpu(processors, pr->id) = pr; result = acpi_processor_add_fs(device); if (result) @@ -753,7 +753,7 @@ static int acpi_cpu_soft_notify(struct notifier_block *nfb, unsigned long action, void *hcpu) { unsigned int cpu = (unsigned long)hcpu; - struct acpi_processor *pr = processors[cpu]; + struct acpi_processor *pr = per_cpu(processors, cpu); if (action == CPU_ONLINE && pr) { acpi_processor_ppc_has_changed(pr); @@ -825,8 +825,8 @@ static int acpi_processor_remove(struct acpi_device *device, int type) pr->cdev = NULL; } - processors[pr->id] = NULL; - processor_device_array[pr->id] = NULL; + per_cpu(processors, pr->id) = NULL; + per_cpu(processor_device_array, pr->id) = NULL; kfree(pr); return 0; @@ -1074,8 +1074,6 @@ static int __init acpi_processor_init(void) { int result = 0; - - memset(&processors, 0, sizeof(processors)); memset(&errata, 0, sizeof(errata)); #ifdef CONFIG_SMP diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 4976e5db2b3f..0fc310e7dfd6 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -401,7 +401,7 @@ static void acpi_processor_idle(void) */ local_irq_disable(); - pr = processors[smp_processor_id()]; + pr = __get_cpu_var(processors); if (!pr) { local_irq_enable(); return; @@ -1431,7 +1431,7 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev, struct acpi_processor *pr; struct acpi_processor_cx *cx = cpuidle_get_statedata(state); - pr = processors[smp_processor_id()]; + pr = __get_cpu_var(processors); if (unlikely(!pr)) return 0; @@ -1471,7 +1471,7 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev, u32 t1, t2; int sleep_ticks = 0; - pr = processors[smp_processor_id()]; + pr = __get_cpu_var(processors); if (unlikely(!pr)) return 0; @@ -1549,7 +1549,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev, u32 t1, t2; int sleep_ticks = 0; - pr = processors[smp_processor_id()]; + pr = __get_cpu_var(processors); if (unlikely(!pr)) return 0; diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c index d80b2d1441af..b4749969c6b4 100644 --- a/drivers/acpi/processor_perflib.c +++ b/drivers/acpi/processor_perflib.c @@ -89,7 +89,7 @@ static int acpi_processor_ppc_notifier(struct notifier_block *nb, if (event != CPUFREQ_INCOMPATIBLE) goto out; - pr = processors[policy->cpu]; + pr = per_cpu(processors, policy->cpu); if (!pr || !pr->performance) goto out; @@ -572,7 +572,7 @@ int acpi_processor_preregister_performance( /* Call _PSD for all CPUs */ for_each_possible_cpu(i) { - pr = processors[i]; + pr = per_cpu(processors, i); if (!pr) { /* Look only at processors in ACPI namespace */ continue; @@ -603,7 +603,7 @@ int acpi_processor_preregister_performance( * domain info. */ for_each_possible_cpu(i) { - pr = processors[i]; + pr = per_cpu(processors, i); if (!pr) continue; @@ -624,7 +624,7 @@ int acpi_processor_preregister_performance( cpus_clear(covered_cpus); for_each_possible_cpu(i) { - pr = processors[i]; + pr = per_cpu(processors, i); if (!pr) continue; @@ -651,7 +651,7 @@ int acpi_processor_preregister_performance( if (i == j) continue; - match_pr = processors[j]; + match_pr = per_cpu(processors, j); if (!match_pr) continue; @@ -680,7 +680,7 @@ int acpi_processor_preregister_performance( if (i == j) continue; - match_pr = processors[j]; + match_pr = per_cpu(processors, j); if (!match_pr) continue; @@ -697,7 +697,7 @@ int acpi_processor_preregister_performance( err_ret: for_each_possible_cpu(i) { - pr = processors[i]; + pr = per_cpu(processors, i); if (!pr || !pr->performance) continue; @@ -728,7 +728,7 @@ acpi_processor_register_performance(struct acpi_processor_performance mutex_lock(&performance_mutex); - pr = processors[cpu]; + pr = per_cpu(processors, cpu); if (!pr) { mutex_unlock(&performance_mutex); return -ENODEV; @@ -766,7 +766,7 @@ acpi_processor_unregister_performance(struct acpi_processor_performance mutex_lock(&performance_mutex); - pr = processors[cpu]; + pr = per_cpu(processors, cpu); if (!pr) { mutex_unlock(&performance_mutex); return; diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c index bb06738860c4..8728782aad3b 100644 --- a/drivers/acpi/processor_throttling.c +++ b/drivers/acpi/processor_throttling.c @@ -71,7 +71,7 @@ static int acpi_processor_update_tsd_coord(void) * coordination between all CPUs. */ for_each_possible_cpu(i) { - pr = processors[i]; + pr = per_cpu(processors, i); if (!pr) continue; @@ -93,7 +93,7 @@ static int acpi_processor_update_tsd_coord(void) cpus_clear(covered_cpus); for_each_possible_cpu(i) { - pr = processors[i]; + pr = per_cpu(processors, i); if (!pr) continue; @@ -119,7 +119,7 @@ static int acpi_processor_update_tsd_coord(void) if (i == j) continue; - match_pr = processors[j]; + match_pr = per_cpu(processors, j); if (!match_pr) continue; @@ -152,7 +152,7 @@ static int acpi_processor_update_tsd_coord(void) if (i == j) continue; - match_pr = processors[j]; + match_pr = per_cpu(processors, j); if (!match_pr) continue; @@ -172,7 +172,7 @@ static int acpi_processor_update_tsd_coord(void) err_ret: for_each_possible_cpu(i) { - pr = processors[i]; + pr = per_cpu(processors, i); if (!pr) continue; @@ -214,7 +214,7 @@ static int acpi_processor_throttling_notifier(unsigned long event, void *data) struct acpi_processor_throttling *p_throttling; cpu = p_tstate->cpu; - pr = processors[cpu]; + pr = per_cpu(processors, cpu); if (!pr) { ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Invalid pr pointer\n")); return 0; @@ -1035,7 +1035,7 @@ int acpi_processor_set_throttling(struct acpi_processor *pr, int state) * cpus. */ for_each_cpu_mask(i, online_throttling_cpus) { - match_pr = processors[i]; + match_pr = per_cpu(processors, i); /* * If the pointer is invalid, we will report the * error message and continue. diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 06ebb6ef72aa..3795590e152a 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -255,7 +255,7 @@ extern void acpi_processor_unregister_performance(struct int acpi_processor_notify_smm(struct module *calling_module); /* for communication between multiple parts of the processor kernel module */ -extern struct acpi_processor *processors[NR_CPUS]; +DECLARE_PER_CPU(struct acpi_processor *, processors); extern struct acpi_processor_errata errata; void arch_acpi_processor_init_pdc(struct acpi_processor *pr); -- cgit v1.2.3 From e38e8a0743b0e996a8a3fbea8908fe75a84f02c7 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Fri, 13 Jun 2008 08:28:55 +0800 Subject: Make GPE disable more robust Implemented another change for the GPE disable. We now perform a read-change-write of the enable register instead of simply writing out the cached enable mask. This will prevent inadvertent enabling of GPEs if a rogue GPE is received during initialization (before GPE handlers are installed.) http://bugzilla.kernel.org/show_bug.cgi?id=6217 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- drivers/acpi/events/evgpe.c | 18 ++++++++++++---- drivers/acpi/hardware/hwgpe.c | 50 ++++++++++++++++++++++++++++++++++++++++++- include/acpi/achware.h | 2 ++ 3 files changed, 65 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/acpi/events/evgpe.c b/drivers/acpi/events/evgpe.c index 5354be44f876..e0339d4139a4 100644 --- a/drivers/acpi/events/evgpe.c +++ b/drivers/acpi/events/evgpe.c @@ -256,7 +256,7 @@ acpi_status acpi_ev_disable_gpe(struct acpi_gpe_event_info *gpe_event_info) return_ACPI_STATUS(status); } - /* Mark wake-disabled or HW disable, or both */ + /* Clear the appropriate enabled flags for this GPE */ switch (gpe_event_info->flags & ACPI_GPE_TYPE_MASK) { case ACPI_GPE_TYPE_WAKE: @@ -273,13 +273,23 @@ acpi_status acpi_ev_disable_gpe(struct acpi_gpe_event_info *gpe_event_info) /* Disable the requested runtime GPE */ ACPI_CLEAR_BIT(gpe_event_info->flags, ACPI_GPE_RUN_ENABLED); - - /* fallthrough */ + break; default: - acpi_hw_write_gpe_enable_reg(gpe_event_info); + break; } + /* + * Even if we don't know the GPE type, make sure that we always + * disable it. low_disable_gpe will just clear the enable bit for this + * GPE and write it. It will not write out the current GPE enable mask, + * since this may inadvertently enable GPEs too early, if a rogue GPE has + * come in during ACPICA initialization - possibly as a result of AML or + * other code that has enabled the GPE. + */ + status = acpi_hw_low_disable_gpe(gpe_event_info); + return_ACPI_STATUS(status); + return_ACPI_STATUS(AE_OK); } diff --git a/drivers/acpi/hardware/hwgpe.c b/drivers/acpi/hardware/hwgpe.c index 14bc4f456ae8..58347d6c43f8 100644 --- a/drivers/acpi/hardware/hwgpe.c +++ b/drivers/acpi/hardware/hwgpe.c @@ -53,6 +53,54 @@ static acpi_status acpi_hw_enable_wakeup_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info, struct acpi_gpe_block_info *gpe_block); +/****************************************************************************** + * + * FUNCTION: acpi_hw_low_disable_gpe + * + * PARAMETERS: gpe_event_info - Info block for the GPE to be disabled + * + * RETURN: Status + * + * DESCRIPTION: Disable a single GPE in the enable register. + * + ******************************************************************************/ + +acpi_status acpi_hw_low_disable_gpe(struct acpi_gpe_event_info *gpe_event_info) +{ + struct acpi_gpe_register_info *gpe_register_info; + acpi_status status; + u32 enable_mask; + + /* Get the info block for the entire GPE register */ + + gpe_register_info = gpe_event_info->register_info; + if (!gpe_register_info) { + return (AE_NOT_EXIST); + } + + /* Get current value of the enable register that contains this GPE */ + + status = acpi_hw_low_level_read(ACPI_GPE_REGISTER_WIDTH, &enable_mask, + &gpe_register_info->enable_address); + if (ACPI_FAILURE(status)) { + return (status); + } + + /* Clear just the bit that corresponds to this GPE */ + + ACPI_CLEAR_BIT(enable_mask, + ((u32) 1 << + (gpe_event_info->gpe_number - + gpe_register_info->base_gpe_number))); + + /* Write the updated enable mask */ + + status = acpi_hw_low_level_write(ACPI_GPE_REGISTER_WIDTH, enable_mask, + &gpe_register_info->enable_address); + + return (status); +} + /****************************************************************************** * * FUNCTION: acpi_hw_write_gpe_enable_reg @@ -68,7 +116,7 @@ acpi_hw_enable_wakeup_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info, ******************************************************************************/ acpi_status -acpi_hw_write_gpe_enable_reg(struct acpi_gpe_event_info *gpe_event_info) +acpi_hw_write_gpe_enable_reg(struct acpi_gpe_event_info * gpe_event_info) { struct acpi_gpe_register_info *gpe_register_info; acpi_status status; diff --git a/include/acpi/achware.h b/include/acpi/achware.h index d4fb9bbc903c..45e985961f4c 100644 --- a/include/acpi/achware.h +++ b/include/acpi/achware.h @@ -87,6 +87,8 @@ acpi_status acpi_hw_clear_acpi_status(void); /* * hwgpe - GPE support */ +acpi_status acpi_hw_low_disable_gpe(struct acpi_gpe_event_info *gpe_event_info); + acpi_status acpi_hw_write_gpe_enable_reg(struct acpi_gpe_event_info *gpe_event_info); -- cgit v1.2.3 From 47c00d2bc2ef2cf8a608688144fe2093a2aa9507 Mon Sep 17 00:00:00 2001 From: Vegard Nossum Date: Fri, 20 Jun 2008 13:56:56 +0200 Subject: ACPICA: fix mutex names in debug code. Reorder the mutex names to match the preceding #defines Signed-off-by: Vegard Nossum Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- include/acpi/aclocal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/acpi/aclocal.h b/include/acpi/aclocal.h index c5cdc32ac2f8..62d7468ed3f9 100644 --- a/include/acpi/aclocal.h +++ b/include/acpi/aclocal.h @@ -98,8 +98,8 @@ union acpi_parse_object; static char *acpi_gbl_mutex_names[ACPI_NUM_MUTEX] = { "ACPI_MTX_Interpreter", - "ACPI_MTX_Tables", "ACPI_MTX_Namespace", + "ACPI_MTX_Tables", "ACPI_MTX_Events", "ACPI_MTX_Caches", "ACPI_MTX_Memory", -- cgit v1.2.3 From 2fe2de5f6c283a7d2a82c1b99a19012079cee555 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 5 Jun 2008 01:15:40 +0200 Subject: ACPI PM: acpi_pm_device_sleep_state() cleanup Get rid of a superfluous acpi_pm_device_sleep_state() parameter. The only legitimate value of that parameter must be derived from the first parameter, which is what all the callers already do. (However, this does not address the fact that ACPI still doesn't set up those flags.) Signed-off-by: David Brownell Signed-off-by: Andi Kleen Acked-by: Pavel Machek Signed-off-by: Rafael J. Wysocki Signed-off-by: Len Brown --- drivers/acpi/sleep/main.c | 8 ++++---- drivers/pci/pci-acpi.c | 3 +-- drivers/pnp/pnpacpi/core.c | 4 +--- include/acpi/acpi_bus.h | 4 ++-- 4 files changed, 8 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/drivers/acpi/sleep/main.c b/drivers/acpi/sleep/main.c index 495c63a3e0af..b45806d77288 100644 --- a/drivers/acpi/sleep/main.c +++ b/drivers/acpi/sleep/main.c @@ -368,8 +368,8 @@ int acpi_suspend(u32 acpi_state) /** * acpi_pm_device_sleep_state - return preferred power state of ACPI device * in the system sleep state given by %acpi_target_sleep_state - * @dev: device to examine - * @wake: if set, the device should be able to wake up the system + * @dev: device to examine; its driver model wakeup flags control + * whether it should be able to wake up the system * @d_min_p: used to store the upper limit of allowed states range * Return value: preferred power state of the device on success, -ENODEV on * failure (ie. if there's no 'struct acpi_device' for @dev) @@ -387,7 +387,7 @@ int acpi_suspend(u32 acpi_state) * via @wake. */ -int acpi_pm_device_sleep_state(struct device *dev, int wake, int *d_min_p) +int acpi_pm_device_sleep_state(struct device *dev, int *d_min_p) { acpi_handle handle = DEVICE_ACPI_HANDLE(dev); struct acpi_device *adev; @@ -426,7 +426,7 @@ int acpi_pm_device_sleep_state(struct device *dev, int wake, int *d_min_p) * can wake the system. _S0W may be valid, too. */ if (acpi_target_sleep_state == ACPI_STATE_S0 || - (wake && adev->wakeup.state.enabled && + (device_may_wakeup(dev) && adev->wakeup.state.enabled && adev->wakeup.sleep_state <= acpi_target_sleep_state)) { acpi_status status; diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 9d6fc8e6285d..caabf0573c3d 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -298,8 +298,7 @@ static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev, { int acpi_state; - acpi_state = acpi_pm_device_sleep_state(&pdev->dev, - device_may_wakeup(&pdev->dev), NULL); + acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL); if (acpi_state < 0) return PCI_POWER_ERROR; diff --git a/drivers/pnp/pnpacpi/core.c b/drivers/pnp/pnpacpi/core.c index 50902773beaf..c1b9ea34977b 100644 --- a/drivers/pnp/pnpacpi/core.c +++ b/drivers/pnp/pnpacpi/core.c @@ -117,9 +117,7 @@ static int pnpacpi_suspend(struct pnp_dev *dev, pm_message_t state) { int power_state; - power_state = acpi_pm_device_sleep_state(&dev->dev, - device_may_wakeup(&dev->dev), - NULL); + power_state = acpi_pm_device_sleep_state(&dev->dev, NULL); if (power_state < 0) power_state = (state.event == PM_EVENT_ON) ? ACPI_STATE_D0 : ACPI_STATE_D3; diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 2f1c68c7a727..db90a74f8714 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -376,9 +376,9 @@ acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int); #define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)((dev)->archdata.acpi_handle)) #ifdef CONFIG_PM_SLEEP -int acpi_pm_device_sleep_state(struct device *, int, int *); +int acpi_pm_device_sleep_state(struct device *, int *); #else /* !CONFIG_PM_SLEEP */ -static inline int acpi_pm_device_sleep_state(struct device *d, int w, int *p) +static inline int acpi_pm_device_sleep_state(struct device *d, int *p) { if (p) *p = ACPI_STATE_D0; -- cgit v1.2.3 From ebb12db51f6c13b30752fcf506baad4c617b153c Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Wed, 11 Jun 2008 22:04:29 +0200 Subject: Freezer: Introduce PF_FREEZER_NOSIG The freezer currently attempts to distinguish kernel threads from user space tasks by checking if their mm pointer is unset and it does not send fake signals to kernel threads. However, there are kernel threads, mostly related to networking, that behave like user space tasks and may want to be sent a fake signal to be frozen. Introduce the new process flag PF_FREEZER_NOSIG that will be set by default for all kernel threads and make the freezer only send fake signals to the tasks having PF_FREEZER_NOSIG unset. Provide the set_freezable_with_signal() function to be called by the kernel threads that want to be sent a fake signal for freezing. This patch should not change the freezer's observable behavior. Signed-off-by: Rafael J. Wysocki Signed-off-by: Andi Kleen Acked-by: Pavel Machek Signed-off-by: Len Brown --- include/linux/freezer.h | 10 +++++ include/linux/sched.h | 1 + kernel/kthread.c | 2 +- kernel/power/process.c | 97 +++++++++++++++++++++---------------------------- 4 files changed, 54 insertions(+), 56 deletions(-) (limited to 'include') diff --git a/include/linux/freezer.h b/include/linux/freezer.h index 08934995c7ab..deddeedf3257 100644 --- a/include/linux/freezer.h +++ b/include/linux/freezer.h @@ -127,6 +127,15 @@ static inline void set_freezable(void) current->flags &= ~PF_NOFREEZE; } +/* + * Tell the freezer that the current task should be frozen by it and that it + * should send a fake signal to the task to freeze it. + */ +static inline void set_freezable_with_signal(void) +{ + current->flags &= ~(PF_NOFREEZE | PF_FREEZER_NOSIG); +} + /* * Freezer-friendly wrappers around wait_event_interruptible() and * wait_event_interruptible_timeout(), originally defined in @@ -174,6 +183,7 @@ static inline void freezer_do_not_count(void) {} static inline void freezer_count(void) {} static inline int freezer_should_skip(struct task_struct *p) { return 0; } static inline void set_freezable(void) {} +static inline void set_freezable_with_signal(void) {} #define wait_event_freezable(wq, condition) \ wait_event_interruptible(wq, condition) diff --git a/include/linux/sched.h b/include/linux/sched.h index 21349173d148..ba2f859c6e4f 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1494,6 +1494,7 @@ static inline void put_task_struct(struct task_struct *t) #define PF_MEMPOLICY 0x10000000 /* Non-default NUMA mempolicy */ #define PF_MUTEX_TESTER 0x20000000 /* Thread belongs to the rt mutex tester */ #define PF_FREEZER_SKIP 0x40000000 /* Freezer should not count it as freezeable */ +#define PF_FREEZER_NOSIG 0x80000000 /* Freezer won't send signals to it */ /* * Only the _current_ task can read/write to tsk->flags, but other diff --git a/kernel/kthread.c b/kernel/kthread.c index 97747cdd37c9..ac3fb7326641 100644 --- a/kernel/kthread.c +++ b/kernel/kthread.c @@ -235,7 +235,7 @@ int kthreadd(void *unused) set_user_nice(tsk, KTHREAD_NICE_LEVEL); set_cpus_allowed(tsk, CPU_MASK_ALL); - current->flags |= PF_NOFREEZE; + current->flags |= PF_NOFREEZE | PF_FREEZER_NOSIG; for (;;) { set_current_state(TASK_INTERRUPTIBLE); diff --git a/kernel/power/process.c b/kernel/power/process.c index f1d0b345c9ba..5fb87652f214 100644 --- a/kernel/power/process.c +++ b/kernel/power/process.c @@ -19,9 +19,6 @@ */ #define TIMEOUT (20 * HZ) -#define FREEZER_KERNEL_THREADS 0 -#define FREEZER_USER_SPACE 1 - static inline int freezeable(struct task_struct * p) { if ((p == current) || @@ -84,63 +81,53 @@ static void fake_signal_wake_up(struct task_struct *p) spin_unlock_irqrestore(&p->sighand->siglock, flags); } -static int has_mm(struct task_struct *p) +static inline bool should_send_signal(struct task_struct *p) { - return (p->mm && !(p->flags & PF_BORROWED_MM)); + return !(p->flags & PF_FREEZER_NOSIG); } /** * freeze_task - send a freeze request to given task * @p: task to send the request to - * @with_mm_only: if set, the request will only be sent if the task has its - * own mm - * Return value: 0, if @with_mm_only is set and the task has no mm of its - * own or the task is frozen, 1, otherwise + * @sig_only: if set, the request will only be sent if the task has the + * PF_FREEZER_NOSIG flag unset + * Return value: 'false', if @sig_only is set and the task has + * PF_FREEZER_NOSIG set or the task is frozen, 'true', otherwise * - * The freeze request is sent by seting the tasks's TIF_FREEZE flag and + * The freeze request is sent by setting the tasks's TIF_FREEZE flag and * either sending a fake signal to it or waking it up, depending on whether - * or not it has its own mm (ie. it is a user land task). If @with_mm_only - * is set and the task has no mm of its own (ie. it is a kernel thread), - * its TIF_FREEZE flag should not be set. - * - * The task_lock() is necessary to prevent races with exit_mm() or - * use_mm()/unuse_mm() from occuring. + * or not it has PF_FREEZER_NOSIG set. If @sig_only is set and the task + * has PF_FREEZER_NOSIG set (ie. it is a typical kernel thread), its + * TIF_FREEZE flag will not be set. */ -static int freeze_task(struct task_struct *p, int with_mm_only) +static bool freeze_task(struct task_struct *p, bool sig_only) { - int ret = 1; + /* + * We first check if the task is freezing and next if it has already + * been frozen to avoid the race with frozen_process() which first marks + * the task as frozen and next clears its TIF_FREEZE. + */ + if (!freezing(p)) { + rmb(); + if (frozen(p)) + return false; - task_lock(p); - if (freezing(p)) { - if (has_mm(p)) { - if (!signal_pending(p)) - fake_signal_wake_up(p); - } else { - if (with_mm_only) - ret = 0; - else - wake_up_state(p, TASK_INTERRUPTIBLE); - } + if (!sig_only || should_send_signal(p)) + set_freeze_flag(p); + else + return false; + } + + if (should_send_signal(p)) { + if (!signal_pending(p)) + fake_signal_wake_up(p); + } else if (sig_only) { + return false; } else { - rmb(); - if (frozen(p)) { - ret = 0; - } else { - if (has_mm(p)) { - set_freeze_flag(p); - fake_signal_wake_up(p); - } else { - if (with_mm_only) { - ret = 0; - } else { - set_freeze_flag(p); - wake_up_state(p, TASK_INTERRUPTIBLE); - } - } - } + wake_up_state(p, TASK_INTERRUPTIBLE); } - task_unlock(p); - return ret; + + return true; } static void cancel_freezing(struct task_struct *p) @@ -156,7 +143,7 @@ static void cancel_freezing(struct task_struct *p) } } -static int try_to_freeze_tasks(int freeze_user_space) +static int try_to_freeze_tasks(bool sig_only) { struct task_struct *g, *p; unsigned long end_time; @@ -175,7 +162,7 @@ static int try_to_freeze_tasks(int freeze_user_space) if (frozen(p) || !freezeable(p)) continue; - if (!freeze_task(p, freeze_user_space)) + if (!freeze_task(p, sig_only)) continue; /* @@ -235,13 +222,13 @@ int freeze_processes(void) int error; printk("Freezing user space processes ... "); - error = try_to_freeze_tasks(FREEZER_USER_SPACE); + error = try_to_freeze_tasks(true); if (error) goto Exit; printk("done.\n"); printk("Freezing remaining freezable tasks ... "); - error = try_to_freeze_tasks(FREEZER_KERNEL_THREADS); + error = try_to_freeze_tasks(false); if (error) goto Exit; printk("done."); @@ -251,7 +238,7 @@ int freeze_processes(void) return error; } -static void thaw_tasks(int thaw_user_space) +static void thaw_tasks(bool nosig_only) { struct task_struct *g, *p; @@ -260,7 +247,7 @@ static void thaw_tasks(int thaw_user_space) if (!freezeable(p)) continue; - if (!p->mm == thaw_user_space) + if (nosig_only && should_send_signal(p)) continue; thaw_process(p); @@ -271,8 +258,8 @@ static void thaw_tasks(int thaw_user_space) void thaw_processes(void) { printk("Restarting tasks ... "); - thaw_tasks(FREEZER_KERNEL_THREADS); - thaw_tasks(FREEZER_USER_SPACE); + thaw_tasks(true); + thaw_tasks(false); schedule(); printk("done.\n"); } -- cgit v1.2.3 From f3454ae8104efb2dbf0d08ec42c6f5d0fe9225bc Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 12:25:42 +0800 Subject: ACPICA: Add argument count checking to control method invocation via acpi_evaluate_object Error if too few arguments, warning if too many. This applies only to external programmatic control method execution, not method-to-method calls within the AML. Signed-off-by: Lin Ming Signed-off-by: Bob Moore Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- drivers/acpi/namespace/nseval.c | 35 +++++++++++++++++++++++++++++++++++ include/acpi/acexcep.h | 6 ++++-- include/acpi/acstruct.h | 1 + 3 files changed, 40 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/acpi/namespace/nseval.c b/drivers/acpi/namespace/nseval.c index 14bdfa92bea0..d369164e00b0 100644 --- a/drivers/acpi/namespace/nseval.c +++ b/drivers/acpi/namespace/nseval.c @@ -138,6 +138,41 @@ acpi_status acpi_ns_evaluate(struct acpi_evaluate_info * info) return_ACPI_STATUS(AE_NULL_OBJECT); } + /* + * Calculate the number of arguments being passed to the method + */ + + info->param_count = 0; + if (info->parameters) { + while (info->parameters[info->param_count]) + info->param_count++; + } + + /* Error if too few arguments were passed in */ + + if (info->param_count < info->obj_desc->method.param_count) { + ACPI_ERROR((AE_INFO, + "Insufficient arguments - " + "method [%4.4s] needs %d, found %d", + acpi_ut_get_node_name(info->resolved_node), + info->obj_desc->method.param_count, + info->param_count)); + return_ACPI_STATUS(AE_MISSING_ARGUMENTS); + } + + /* Just a warning if too many arguments */ + + else if (info->param_count > + info->obj_desc->method.param_count) { + ACPI_WARNING((AE_INFO, + "Excess arguments - " + "method [%4.4s] needs %d, found %d", + acpi_ut_get_node_name(info-> + resolved_node), + info->obj_desc->method.param_count, + info->param_count)); + } + ACPI_DUMP_PATHNAME(info->resolved_node, "Execute Method:", ACPI_LV_INFO, _COMPONENT); diff --git a/include/acpi/acexcep.h b/include/acpi/acexcep.h index 1f591171bf31..ea627ed2420d 100644 --- a/include/acpi/acexcep.h +++ b/include/acpi/acexcep.h @@ -108,8 +108,9 @@ #define AE_BAD_HEX_CONSTANT (acpi_status) (0x0007 | AE_CODE_PROGRAMMER) #define AE_BAD_OCTAL_CONSTANT (acpi_status) (0x0008 | AE_CODE_PROGRAMMER) #define AE_BAD_DECIMAL_CONSTANT (acpi_status) (0x0009 | AE_CODE_PROGRAMMER) +#define AE_MISSING_ARGUMENTS (acpi_status) (0x000A | AE_CODE_PROGRAMMER) -#define AE_CODE_PGM_MAX 0x0009 +#define AE_CODE_PGM_MAX 0x000A /* * Acpi table exceptions @@ -233,7 +234,8 @@ char const *acpi_gbl_exception_names_pgm[] = { "AE_ALIGNMENT", "AE_BAD_HEX_CONSTANT", "AE_BAD_OCTAL_CONSTANT", - "AE_BAD_DECIMAL_CONSTANT" + "AE_BAD_DECIMAL_CONSTANT", + "AE_MISSING_ARGUMENTS" }; char const *acpi_gbl_exception_names_tbl[] = { diff --git a/include/acpi/acstruct.h b/include/acpi/acstruct.h index a907c67d651e..1cc74504f1c4 100644 --- a/include/acpi/acstruct.h +++ b/include/acpi/acstruct.h @@ -189,6 +189,7 @@ struct acpi_evaluate_info { union acpi_operand_object **parameters; struct acpi_namespace_node *resolved_node; union acpi_operand_object *return_object; + u8 param_count; u8 pass_number; u8 parameter_type; u8 return_object_type; -- cgit v1.2.3 From c91d924e3af08d4f98eab6ebf81f2b8ce132448f Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 12:38:10 +0800 Subject: ACPICA: Fix for hang on GPE method invocation Fixes problem where the new method argument count validation mechanism will enter an infinite loop when a GPE method is dispatched. Problem fixed be removing the obsolete code that passes GPE block information to the notify handler via the control method parameter pointer. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- drivers/acpi/dispatcher/dsmethod.c | 1 - drivers/acpi/dispatcher/dswstate.c | 10 ++-------- drivers/acpi/events/evgpe.c | 4 ---- drivers/acpi/events/evregion.c | 1 - drivers/acpi/namespace/nsinit.c | 1 - drivers/acpi/namespace/nsxfeval.c | 1 - drivers/acpi/parser/psxface.c | 2 +- drivers/acpi/resources/rsutils.c | 1 - drivers/acpi/utilities/uteval.c | 1 - include/acpi/acstruct.h | 7 ------- 10 files changed, 3 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/drivers/acpi/dispatcher/dsmethod.c b/drivers/acpi/dispatcher/dsmethod.c index 2509809a36cf..4613b9ca5792 100644 --- a/drivers/acpi/dispatcher/dsmethod.c +++ b/drivers/acpi/dispatcher/dsmethod.c @@ -377,7 +377,6 @@ acpi_ds_call_control_method(struct acpi_thread_state *thread, } info->parameters = &this_walk_state->operands[0]; - info->parameter_type = ACPI_PARAM_ARGS; status = acpi_ds_init_aml_walk(next_walk_state, NULL, method_node, obj_desc->method.aml_start, diff --git a/drivers/acpi/dispatcher/dswstate.c b/drivers/acpi/dispatcher/dswstate.c index 1386ced332ec..bda23ed60645 100644 --- a/drivers/acpi/dispatcher/dswstate.c +++ b/drivers/acpi/dispatcher/dswstate.c @@ -615,14 +615,8 @@ acpi_ds_init_aml_walk(struct acpi_walk_state *walk_state, walk_state->pass_number = pass_number; if (info) { - if (info->parameter_type == ACPI_PARAM_GPE) { - walk_state->gpe_event_info = - ACPI_CAST_PTR(struct acpi_gpe_event_info, - info->parameters); - } else { - walk_state->params = info->parameters; - walk_state->caller_return_desc = &info->return_object; - } + walk_state->params = info->parameters; + walk_state->caller_return_desc = &info->return_object; } status = acpi_ps_init_scope(&walk_state->parser_state, op); diff --git a/drivers/acpi/events/evgpe.c b/drivers/acpi/events/evgpe.c index e0339d4139a4..ca356e5ae2c3 100644 --- a/drivers/acpi/events/evgpe.c +++ b/drivers/acpi/events/evgpe.c @@ -565,10 +565,6 @@ static void ACPI_SYSTEM_XFACE acpi_ev_asynch_execute_gpe_method(void *context) */ info->prefix_node = local_gpe_event_info.dispatch.method_node; - info->parameters = - ACPI_CAST_PTR(union acpi_operand_object *, - gpe_event_info); - info->parameter_type = ACPI_PARAM_GPE; info->flags = ACPI_IGNORE_RETURN_VALUE; status = acpi_ns_evaluate(info); diff --git a/drivers/acpi/events/evregion.c b/drivers/acpi/events/evregion.c index 1628f5934752..5ab4c01417df 100644 --- a/drivers/acpi/events/evregion.c +++ b/drivers/acpi/events/evregion.c @@ -219,7 +219,6 @@ acpi_ev_execute_reg_method(union acpi_operand_object *region_obj, u32 function) info->prefix_node = region_obj2->extra.method_REG; info->pathname = NULL; info->parameters = args; - info->parameter_type = ACPI_PARAM_ARGS; info->flags = ACPI_IGNORE_RETURN_VALUE; /* diff --git a/drivers/acpi/namespace/nsinit.c b/drivers/acpi/namespace/nsinit.c index 6d6d930c8e18..e4c57510d798 100644 --- a/drivers/acpi/namespace/nsinit.c +++ b/drivers/acpi/namespace/nsinit.c @@ -542,7 +542,6 @@ acpi_ns_init_one_device(acpi_handle obj_handle, info->prefix_node = device_node; info->pathname = METHOD_NAME__INI; info->parameters = NULL; - info->parameter_type = ACPI_PARAM_ARGS; info->flags = ACPI_IGNORE_RETURN_VALUE; /* diff --git a/drivers/acpi/namespace/nsxfeval.c b/drivers/acpi/namespace/nsxfeval.c index a8d549187c84..b4e135eab7c7 100644 --- a/drivers/acpi/namespace/nsxfeval.c +++ b/drivers/acpi/namespace/nsxfeval.c @@ -182,7 +182,6 @@ acpi_evaluate_object(acpi_handle handle, } info->pathname = pathname; - info->parameter_type = ACPI_PARAM_ARGS; /* Convert and validate the device handle */ diff --git a/drivers/acpi/parser/psxface.c b/drivers/acpi/parser/psxface.c index 52581454c47c..5ee09e1245e3 100644 --- a/drivers/acpi/parser/psxface.c +++ b/drivers/acpi/parser/psxface.c @@ -335,7 +335,7 @@ acpi_ps_update_parameter_list(struct acpi_evaluate_info *info, u16 action) { acpi_native_uint i; - if ((info->parameter_type == ACPI_PARAM_ARGS) && (info->parameters)) { + if (info->parameters) { /* Update reference count for each parameter */ diff --git a/drivers/acpi/resources/rsutils.c b/drivers/acpi/resources/rsutils.c index befe2302f41b..90ed83d05375 100644 --- a/drivers/acpi/resources/rsutils.c +++ b/drivers/acpi/resources/rsutils.c @@ -679,7 +679,6 @@ acpi_rs_set_srs_method_data(struct acpi_namespace_node *node, info->prefix_node = node; info->pathname = METHOD_NAME__SRS; info->parameters = args; - info->parameter_type = ACPI_PARAM_ARGS; info->flags = ACPI_IGNORE_RETURN_VALUE; /* diff --git a/drivers/acpi/utilities/uteval.c b/drivers/acpi/utilities/uteval.c index 05e61be267d5..7f1f6341242d 100644 --- a/drivers/acpi/utilities/uteval.c +++ b/drivers/acpi/utilities/uteval.c @@ -217,7 +217,6 @@ acpi_ut_evaluate_object(struct acpi_namespace_node *prefix_node, info->prefix_node = prefix_node; info->pathname = path; - info->parameter_type = ACPI_PARAM_ARGS; /* Evaluate the object/method */ diff --git a/include/acpi/acstruct.h b/include/acpi/acstruct.h index 1cc74504f1c4..818c24d7d2d1 100644 --- a/include/acpi/acstruct.h +++ b/include/acpi/acstruct.h @@ -108,7 +108,6 @@ struct acpi_walk_state { union acpi_operand_object **caller_return_desc; union acpi_generic_state *control_state; /* List of control states (nested IFs) */ struct acpi_namespace_node *deferred_node; /* Used when executing deferred opcodes */ - struct acpi_gpe_event_info *gpe_event_info; /* Info for GPE (_Lxx/_Exx methods only */ union acpi_operand_object *implicit_return_obj; struct acpi_namespace_node *method_call_node; /* Called method Node */ union acpi_parse_object *method_call_op; /* method_call Op if running a method */ @@ -191,16 +190,10 @@ struct acpi_evaluate_info { union acpi_operand_object *return_object; u8 param_count; u8 pass_number; - u8 parameter_type; u8 return_object_type; u8 flags; }; -/* Types for parameter_type above */ - -#define ACPI_PARAM_ARGS 0 -#define ACPI_PARAM_GPE 1 - /* Values for Flags above */ #define ACPI_IGNORE_RETURN_VALUE 1 -- cgit v1.2.3 From 6719561f9b4281491f58ed9f0bbc179dc7db95b7 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Tue, 10 Jun 2008 12:49:56 +0800 Subject: ACPICA: Update tracking macros to reduce code/data size Changed ACPI_MODULE_NAME and ACPI_FUNCTION_NAME to use arrays of strings instead of pointers to static strings. Jan Beulich and Bob Moore. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- include/acpi/acmacros.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h index fb41a3b802fc..5ad6e3992304 100644 --- a/include/acpi/acmacros.h +++ b/include/acpi/acmacros.h @@ -414,7 +414,7 @@ struct acpi_integer_overlay { * error messages. The __FILE__ macro is not very useful for this, because it * often includes the entire pathname to the module */ -#define ACPI_MODULE_NAME(name) static char ACPI_UNUSED_VAR *_acpi_module_name = name; +#define ACPI_MODULE_NAME(name) static char ACPI_UNUSED_VAR _acpi_module_name[] = name; #else #define ACPI_MODULE_NAME(name) #endif @@ -467,19 +467,17 @@ struct acpi_integer_overlay { /* * If ACPI_GET_FUNCTION_NAME was not defined in the compiler-dependent header, * define it now. This is the case where there the compiler does not support - * a __FUNCTION__ macro or equivalent. We save the function name on the - * local stack. + * a __FUNCTION__ macro or equivalent. */ #ifndef ACPI_GET_FUNCTION_NAME #define ACPI_GET_FUNCTION_NAME _acpi_function_name /* * The Name parameter should be the procedure name as a quoted string. - * This is declared as a local string ("MyFunctionName") so that it can - * be also used by the function exit macros below. + * The function name is also used by the function exit macros below. * Note: (const char) is used to be compatible with the debug interfaces * and macros such as __FUNCTION__. */ -#define ACPI_FUNCTION_NAME(name) const char *_acpi_function_name = #name; +#define ACPI_FUNCTION_NAME(name) static const char _acpi_function_name[] = #name; #else /* Compiler supports __FUNCTION__ (or equivalent) -- Ignore this macro */ -- cgit v1.2.3 From 11f2a61ab418305167f9a3f3a31a50449222f64b Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 12:53:01 +0800 Subject: ACPICA: Fix possible negative array index in acpi_ut_validate_exception Added NULL fields to the exception string arrays to eliminate the -1 subtraction on the SubStatus field. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- drivers/acpi/utilities/utmisc.c | 14 +++++--------- include/acpi/acexcep.h | 4 ++++ 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/drivers/acpi/utilities/utmisc.c b/drivers/acpi/utilities/utmisc.c index 1f057b71db1a..47354d9b0e56 100644 --- a/drivers/acpi/utilities/utmisc.c +++ b/drivers/acpi/utilities/utmisc.c @@ -64,7 +64,7 @@ ACPI_MODULE_NAME("utmisc") ******************************************************************************/ const char *acpi_ut_validate_exception(acpi_status status) { - acpi_status sub_status; + u32 sub_status; const char *exception = NULL; ACPI_FUNCTION_ENTRY(); @@ -85,32 +85,28 @@ const char *acpi_ut_validate_exception(acpi_status status) case AE_CODE_PROGRAMMER: if (sub_status <= AE_CODE_PGM_MAX) { - exception = - acpi_gbl_exception_names_pgm[sub_status - 1]; + exception = acpi_gbl_exception_names_pgm[sub_status]; } break; case AE_CODE_ACPI_TABLES: if (sub_status <= AE_CODE_TBL_MAX) { - exception = - acpi_gbl_exception_names_tbl[sub_status - 1]; + exception = acpi_gbl_exception_names_tbl[sub_status]; } break; case AE_CODE_AML: if (sub_status <= AE_CODE_AML_MAX) { - exception = - acpi_gbl_exception_names_aml[sub_status - 1]; + exception = acpi_gbl_exception_names_aml[sub_status]; } break; case AE_CODE_CONTROL: if (sub_status <= AE_CODE_CTRL_MAX) { - exception = - acpi_gbl_exception_names_ctrl[sub_status - 1]; + exception = acpi_gbl_exception_names_ctrl[sub_status]; } break; diff --git a/include/acpi/acexcep.h b/include/acpi/acexcep.h index ea627ed2420d..e5a890ffeb02 100644 --- a/include/acpi/acexcep.h +++ b/include/acpi/acexcep.h @@ -226,6 +226,7 @@ char const *acpi_gbl_exception_names_env[] = { }; char const *acpi_gbl_exception_names_pgm[] = { + NULL, "AE_BAD_PARAMETER", "AE_BAD_CHARACTER", "AE_BAD_PATHNAME", @@ -239,6 +240,7 @@ char const *acpi_gbl_exception_names_pgm[] = { }; char const *acpi_gbl_exception_names_tbl[] = { + NULL, "AE_BAD_SIGNATURE", "AE_BAD_HEADER", "AE_BAD_CHECKSUM", @@ -248,6 +250,7 @@ char const *acpi_gbl_exception_names_tbl[] = { }; char const *acpi_gbl_exception_names_aml[] = { + NULL, "AE_AML_ERROR", "AE_AML_PARSE", "AE_AML_BAD_OPCODE", @@ -285,6 +288,7 @@ char const *acpi_gbl_exception_names_aml[] = { }; char const *acpi_gbl_exception_names_ctrl[] = { + NULL, "AE_CTRL_RETURN_VALUE", "AE_CTRL_PENDING", "AE_CTRL_TERMINATE", -- cgit v1.2.3 From 67a119f990063f5662574f6d6414fe9bc5ece86a Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 13:42:13 +0800 Subject: ACPICA: Eliminate acpi_native_uint type v2 No longer needed; replaced mostly with u32, but also acpi_size where a type that changes 32/64 bit on 32/64-bit platforms is required. v2: Fix a cast of a 32-bit int to a pointer in ACPI to avoid a compiler warning. from David Howells Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- drivers/acpi/bus.c | 2 +- drivers/acpi/dispatcher/dsinit.c | 2 +- drivers/acpi/dispatcher/dsopcode.c | 2 +- drivers/acpi/dispatcher/dswstate.c | 10 +++++----- drivers/acpi/events/evevent.c | 6 +++--- drivers/acpi/events/evgpe.c | 14 ++++---------- drivers/acpi/events/evgpeblk.c | 18 ++++++++++-------- drivers/acpi/events/evmisc.c | 4 ++-- drivers/acpi/events/evregion.c | 4 ++-- drivers/acpi/events/evrgnini.c | 2 +- drivers/acpi/executer/exconfig.c | 17 +++++++++-------- drivers/acpi/executer/exconvrt.c | 12 ++++++------ drivers/acpi/executer/exdump.c | 2 +- drivers/acpi/executer/exfldio.c | 9 +++++---- drivers/acpi/executer/exmisc.c | 8 ++++---- drivers/acpi/executer/exregion.c | 2 +- drivers/acpi/namespace/nsdump.c | 2 +- drivers/acpi/namespace/nsload.c | 3 +-- drivers/acpi/namespace/nsparse.c | 15 +++++++-------- drivers/acpi/namespace/nsutils.c | 26 ++++++++++++-------------- drivers/acpi/namespace/nsxfeval.c | 2 +- drivers/acpi/parser/psargs.c | 4 ++-- drivers/acpi/parser/psxface.c | 2 +- drivers/acpi/resources/rscalc.c | 4 ++-- drivers/acpi/resources/rsmisc.c | 2 +- drivers/acpi/resources/rsutils.c | 12 ++++++------ drivers/acpi/tables/tbfadt.c | 6 +++--- drivers/acpi/tables/tbfind.c | 5 ++--- drivers/acpi/tables/tbinstal.c | 30 ++++++++++++++---------------- drivers/acpi/tables/tbutils.c | 15 +++++++-------- drivers/acpi/tables/tbxface.c | 28 +++++++++++++--------------- drivers/acpi/tables/tbxfroot.c | 4 ++-- drivers/acpi/utilities/utcopy.c | 4 ++-- drivers/acpi/utilities/utdebug.c | 28 +++++++++++++++++----------- drivers/acpi/utilities/utdelete.c | 2 +- drivers/acpi/utilities/uteval.c | 4 ++-- drivers/acpi/utilities/utmisc.c | 14 +++++++------- drivers/acpi/utilities/utobject.c | 4 ++-- include/acpi/acdispat.h | 2 +- include/acpi/acglobal.h | 2 +- include/acpi/acmacros.h | 24 ++++++++++++------------ include/acpi/acnamesp.h | 10 ++++------ include/acpi/acpiosxf.h | 2 +- include/acpi/acpixf.h | 8 ++++---- include/acpi/acstruct.h | 2 +- include/acpi/actables.h | 27 ++++++++++++--------------- include/acpi/actypes.h | 16 ++++++---------- include/acpi/acutils.h | 4 ++-- 48 files changed, 206 insertions(+), 221 deletions(-) (limited to 'include') diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index a6dbcf4d9ef5..afb34387d5f2 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -612,7 +612,7 @@ static int __init acpi_bus_init_irq(void) return 0; } -acpi_native_uint acpi_gbl_permanent_mmap; +u8 acpi_gbl_permanent_mmap; void __init acpi_early_init(void) diff --git a/drivers/acpi/dispatcher/dsinit.c b/drivers/acpi/dispatcher/dsinit.c index 610b1ee102b0..949f7c75029e 100644 --- a/drivers/acpi/dispatcher/dsinit.c +++ b/drivers/acpi/dispatcher/dsinit.c @@ -151,7 +151,7 @@ acpi_ds_init_one_object(acpi_handle obj_handle, ******************************************************************************/ acpi_status -acpi_ds_initialize_objects(acpi_native_uint table_index, +acpi_ds_initialize_objects(u32 table_index, struct acpi_namespace_node * start_node) { acpi_status status; diff --git a/drivers/acpi/dispatcher/dsopcode.c b/drivers/acpi/dispatcher/dsopcode.c index a818e0ddb996..ac0bfb1b16fe 100644 --- a/drivers/acpi/dispatcher/dsopcode.c +++ b/drivers/acpi/dispatcher/dsopcode.c @@ -848,7 +848,7 @@ acpi_ds_eval_table_region_operands(struct acpi_walk_state *walk_state, union acpi_operand_object **operand; struct acpi_namespace_node *node; union acpi_parse_object *next_op; - acpi_native_uint table_index; + u32 table_index; struct acpi_table_header *table; ACPI_FUNCTION_TRACE_PTR(ds_eval_table_region_operands, op); diff --git a/drivers/acpi/dispatcher/dswstate.c b/drivers/acpi/dispatcher/dswstate.c index bda23ed60645..b00d4af791aa 100644 --- a/drivers/acpi/dispatcher/dswstate.c +++ b/drivers/acpi/dispatcher/dswstate.c @@ -70,7 +70,7 @@ acpi_status acpi_ds_result_pop(union acpi_operand_object **object, struct acpi_walk_state *walk_state) { - acpi_native_uint index; + u32 index; union acpi_generic_state *state; acpi_status status; @@ -122,7 +122,7 @@ acpi_ds_result_pop(union acpi_operand_object **object, ACPI_DEBUG_PRINT((ACPI_DB_EXEC, "Obj=%p [%s] Index=%X State=%p Num=%X\n", *object, acpi_ut_get_object_type_name(*object), - (u32) index, walk_state, walk_state->result_count)); + index, walk_state, walk_state->result_count)); return (AE_OK); } @@ -146,7 +146,7 @@ acpi_ds_result_push(union acpi_operand_object * object, { union acpi_generic_state *state; acpi_status status; - acpi_native_uint index; + u32 index; ACPI_FUNCTION_NAME(ds_result_push); @@ -400,7 +400,7 @@ void acpi_ds_obj_stack_pop_and_delete(u32 pop_count, struct acpi_walk_state *walk_state) { - acpi_native_int i; + s32 i; union acpi_operand_object *obj_desc; ACPI_FUNCTION_NAME(ds_obj_stack_pop_and_delete); @@ -409,7 +409,7 @@ acpi_ds_obj_stack_pop_and_delete(u32 pop_count, return; } - for (i = (acpi_native_int) (pop_count - 1); i >= 0; i--) { + for (i = (s32) pop_count - 1; i >= 0; i--) { if (walk_state->num_operands == 0) { return; } diff --git a/drivers/acpi/events/evevent.c b/drivers/acpi/events/evevent.c index 5d30e5be1b1c..c56c5c6ea77b 100644 --- a/drivers/acpi/events/evevent.c +++ b/drivers/acpi/events/evevent.c @@ -188,7 +188,7 @@ acpi_status acpi_ev_install_xrupt_handlers(void) static acpi_status acpi_ev_fixed_event_initialize(void) { - acpi_native_uint i; + u32 i; acpi_status status; /* @@ -231,7 +231,7 @@ u32 acpi_ev_fixed_event_detect(void) u32 int_status = ACPI_INTERRUPT_NOT_HANDLED; u32 fixed_status; u32 fixed_enable; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_NAME(ev_fixed_event_detect); @@ -260,7 +260,7 @@ u32 acpi_ev_fixed_event_detect(void) /* Found an active (signalled) event */ acpi_os_fixed_event_count(i); - int_status |= acpi_ev_fixed_event_dispatch((u32) i); + int_status |= acpi_ev_fixed_event_dispatch(i); } } diff --git a/drivers/acpi/events/evgpe.c b/drivers/acpi/events/evgpe.c index ca356e5ae2c3..c5e53aae86f7 100644 --- a/drivers/acpi/events/evgpe.c +++ b/drivers/acpi/events/evgpe.c @@ -315,7 +315,7 @@ struct acpi_gpe_event_info *acpi_ev_get_gpe_event_info(acpi_handle gpe_device, { union acpi_operand_object *obj_desc; struct acpi_gpe_block_info *gpe_block; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_ENTRY(); @@ -389,8 +389,8 @@ u32 acpi_ev_gpe_detect(struct acpi_gpe_xrupt_info * gpe_xrupt_list) u32 status_reg; u32 enable_reg; acpi_cpu_flags flags; - acpi_native_uint i; - acpi_native_uint j; + u32 i; + u32 j; ACPI_FUNCTION_NAME(ev_gpe_detect); @@ -472,13 +472,7 @@ u32 acpi_ev_gpe_detect(struct acpi_gpe_xrupt_info * gpe_xrupt_list) */ int_status |= acpi_ev_gpe_dispatch(&gpe_block-> - event_info[(i * - ACPI_GPE_REGISTER_WIDTH) - + - j], - (u32) j + - gpe_register_info-> - base_gpe_number); + event_info[((acpi_size) i * ACPI_GPE_REGISTER_WIDTH) + j], j + gpe_register_info->base_gpe_number); } } } diff --git a/drivers/acpi/events/evgpeblk.c b/drivers/acpi/events/evgpeblk.c index e6c4d4c49e79..73c058e2f5c2 100644 --- a/drivers/acpi/events/evgpeblk.c +++ b/drivers/acpi/events/evgpeblk.c @@ -189,8 +189,8 @@ acpi_ev_delete_gpe_handlers(struct acpi_gpe_xrupt_info *gpe_xrupt_info, struct acpi_gpe_block_info *gpe_block) { struct acpi_gpe_event_info *gpe_event_info; - acpi_native_uint i; - acpi_native_uint j; + u32 i; + u32 j; ACPI_FUNCTION_TRACE(ev_delete_gpe_handlers); @@ -203,7 +203,8 @@ acpi_ev_delete_gpe_handlers(struct acpi_gpe_xrupt_info *gpe_xrupt_info, for (j = 0; j < ACPI_GPE_REGISTER_WIDTH; j++) { gpe_event_info = &gpe_block-> - event_info[(i * ACPI_GPE_REGISTER_WIDTH) + j]; + event_info[((acpi_size) i * + ACPI_GPE_REGISTER_WIDTH) + j]; if ((gpe_event_info->flags & ACPI_GPE_DISPATCH_MASK) == ACPI_GPE_DISPATCH_HANDLER) { @@ -744,8 +745,8 @@ acpi_ev_create_gpe_info_blocks(struct acpi_gpe_block_info *gpe_block) struct acpi_gpe_event_info *gpe_event_info = NULL; struct acpi_gpe_event_info *this_event; struct acpi_gpe_register_info *this_register; - acpi_native_uint i; - acpi_native_uint j; + u32 i; + u32 j; acpi_status status; ACPI_FUNCTION_TRACE(ev_create_gpe_info_blocks); @@ -983,8 +984,8 @@ acpi_ev_initialize_gpe_block(struct acpi_namespace_node *gpe_device, struct acpi_gpe_walk_info gpe_info; u32 wake_gpe_count; u32 gpe_enabled_count; - acpi_native_uint i; - acpi_native_uint j; + u32 i; + u32 j; ACPI_FUNCTION_TRACE(ev_initialize_gpe_block); @@ -1033,7 +1034,8 @@ acpi_ev_initialize_gpe_block(struct acpi_namespace_node *gpe_device, gpe_event_info = &gpe_block-> - event_info[(i * ACPI_GPE_REGISTER_WIDTH) + j]; + event_info[((acpi_size) i * + ACPI_GPE_REGISTER_WIDTH) + j]; if (((gpe_event_info->flags & ACPI_GPE_DISPATCH_MASK) == ACPI_GPE_DISPATCH_METHOD) diff --git a/drivers/acpi/events/evmisc.c b/drivers/acpi/events/evmisc.c index 2113e58e2221..1d5670be729a 100644 --- a/drivers/acpi/events/evmisc.c +++ b/drivers/acpi/events/evmisc.c @@ -575,7 +575,7 @@ acpi_status acpi_ev_release_global_lock(void) void acpi_ev_terminate(void) { - acpi_native_uint i; + u32 i; acpi_status status; ACPI_FUNCTION_TRACE(ev_terminate); @@ -589,7 +589,7 @@ void acpi_ev_terminate(void) /* Disable all fixed events */ for (i = 0; i < ACPI_NUM_FIXED_EVENTS; i++) { - status = acpi_disable_event((u32) i, 0); + status = acpi_disable_event(i, 0); if (ACPI_FAILURE(status)) { ACPI_ERROR((AE_INFO, "Could not disable fixed event %d", diff --git a/drivers/acpi/events/evregion.c b/drivers/acpi/events/evregion.c index 5ab4c01417df..236fbd1ca438 100644 --- a/drivers/acpi/events/evregion.c +++ b/drivers/acpi/events/evregion.c @@ -81,7 +81,7 @@ acpi_ev_install_handler(acpi_handle obj_handle, acpi_status acpi_ev_install_region_handlers(void) { acpi_status status; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_TRACE(ev_install_region_handlers); @@ -151,7 +151,7 @@ acpi_status acpi_ev_install_region_handlers(void) acpi_status acpi_ev_initialize_op_regions(void) { acpi_status status; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_TRACE(ev_initialize_op_regions); diff --git a/drivers/acpi/events/evrgnini.c b/drivers/acpi/events/evrgnini.c index 2e3d2c5e4f4d..6b94b38df07d 100644 --- a/drivers/acpi/events/evrgnini.c +++ b/drivers/acpi/events/evrgnini.c @@ -380,7 +380,7 @@ static u8 acpi_ev_is_pci_root_bridge(struct acpi_namespace_node *node) acpi_status status; struct acpica_device_id hid; struct acpi_compatible_id_list *cid; - acpi_native_uint i; + u32 i; /* * Get the _HID and check for a PCI Root Bridge diff --git a/drivers/acpi/executer/exconfig.c b/drivers/acpi/executer/exconfig.c index 39d742190584..2a32c843cb4a 100644 --- a/drivers/acpi/executer/exconfig.c +++ b/drivers/acpi/executer/exconfig.c @@ -53,7 +53,7 @@ ACPI_MODULE_NAME("exconfig") /* Local prototypes */ static acpi_status -acpi_ex_add_table(acpi_native_uint table_index, +acpi_ex_add_table(u32 table_index, struct acpi_namespace_node *parent_node, union acpi_operand_object **ddb_handle); @@ -73,7 +73,7 @@ acpi_ex_add_table(acpi_native_uint table_index, ******************************************************************************/ static acpi_status -acpi_ex_add_table(acpi_native_uint table_index, +acpi_ex_add_table(u32 table_index, struct acpi_namespace_node *parent_node, union acpi_operand_object **ddb_handle) { @@ -96,7 +96,8 @@ acpi_ex_add_table(acpi_native_uint table_index, /* Install the new table into the local data structures */ - obj_desc->reference.object = ACPI_CAST_PTR(void, table_index); + obj_desc->reference.object = ACPI_CAST_PTR(void, + (unsigned long)table_index); /* Add the table to the namespace */ @@ -128,12 +129,12 @@ acpi_ex_load_table_op(struct acpi_walk_state *walk_state, { acpi_status status; union acpi_operand_object **operand = &walk_state->operands[0]; - acpi_native_uint table_index; struct acpi_namespace_node *parent_node; struct acpi_namespace_node *start_node; struct acpi_namespace_node *parameter_node = NULL; union acpi_operand_object *ddb_handle; struct acpi_table_header *table; + u32 table_index; ACPI_FUNCTION_TRACE(ex_load_table_op); @@ -280,7 +281,7 @@ acpi_ex_load_op(union acpi_operand_object *obj_desc, { union acpi_operand_object *ddb_handle; struct acpi_table_desc table_desc; - acpi_native_uint table_index; + u32 table_index; acpi_status status; u32 length; @@ -437,7 +438,7 @@ acpi_status acpi_ex_unload_table(union acpi_operand_object *ddb_handle) { acpi_status status = AE_OK; union acpi_operand_object *table_desc = ddb_handle; - acpi_native_uint table_index; + u32 table_index; struct acpi_table_header *table; ACPI_FUNCTION_TRACE(ex_unload_table); @@ -454,9 +455,9 @@ acpi_status acpi_ex_unload_table(union acpi_operand_object *ddb_handle) return_ACPI_STATUS(AE_BAD_PARAMETER); } - /* Get the table index from the ddb_handle */ + /* Get the table index from the ddb_handle (acpi_size for 64-bit case) */ - table_index = (acpi_native_uint) table_desc->reference.object; + table_index = (u32) (acpi_size) table_desc->reference.object; /* Invoke table handler if present */ diff --git a/drivers/acpi/executer/exconvrt.c b/drivers/acpi/executer/exconvrt.c index fd954b4ed83d..261d97516d9b 100644 --- a/drivers/acpi/executer/exconvrt.c +++ b/drivers/acpi/executer/exconvrt.c @@ -288,11 +288,11 @@ acpi_ex_convert_to_ascii(acpi_integer integer, u16 base, u8 * string, u8 data_width) { acpi_integer digit; - acpi_native_uint i; - acpi_native_uint j; - acpi_native_uint k = 0; - acpi_native_uint hex_length; - acpi_native_uint decimal_length; + u32 i; + u32 j; + u32 k = 0; + u32 hex_length; + u32 decimal_length; u32 remainder; u8 supress_zeros; @@ -348,7 +348,7 @@ acpi_ex_convert_to_ascii(acpi_integer integer, /* hex_length: 2 ascii hex chars per data byte */ - hex_length = (acpi_native_uint) ACPI_MUL_2(data_width); + hex_length = ACPI_MUL_2(data_width); for (i = 0, j = (hex_length - 1); i < hex_length; i++, j--) { /* Get one hex digit, most significant digits first */ diff --git a/drivers/acpi/executer/exdump.c b/drivers/acpi/executer/exdump.c index 74f1b22601b3..976016fda66a 100644 --- a/drivers/acpi/executer/exdump.c +++ b/drivers/acpi/executer/exdump.c @@ -775,7 +775,7 @@ acpi_ex_dump_operands(union acpi_operand_object **operands, u32 num_levels, char *note, char *module_name, u32 line_number) { - acpi_native_uint i; + u32 i; ACPI_FUNCTION_NAME(ex_dump_operands); diff --git a/drivers/acpi/executer/exfldio.c b/drivers/acpi/executer/exfldio.c index e336b5dc7a50..9ff9d1f4615d 100644 --- a/drivers/acpi/executer/exfldio.c +++ b/drivers/acpi/executer/exfldio.c @@ -153,14 +153,15 @@ acpi_ex_setup_region(union acpi_operand_object *obj_desc, /* * Slack mode only: We will go ahead and allow access to this * field if it is within the region length rounded up to the next - * access width boundary. + * access width boundary. acpi_size cast for 64-bit compile. */ if (ACPI_ROUND_UP(rgn_desc->region.length, obj_desc->common_field. access_byte_width) >= - (obj_desc->common_field.base_byte_offset + - (acpi_native_uint) obj_desc->common_field. - access_byte_width + field_datum_byte_offset)) { + ((acpi_size) obj_desc->common_field. + base_byte_offset + + obj_desc->common_field.access_byte_width + + field_datum_byte_offset)) { return_ACPI_STATUS(AE_OK); } } diff --git a/drivers/acpi/executer/exmisc.c b/drivers/acpi/executer/exmisc.c index cc956a5b5267..731414a581a6 100644 --- a/drivers/acpi/executer/exmisc.c +++ b/drivers/acpi/executer/exmisc.c @@ -329,8 +329,8 @@ acpi_ex_do_concatenate(union acpi_operand_object *operand0, /* Result of two Strings is a String */ - return_desc = acpi_ut_create_string_object((acpi_size) - (operand0->string. + return_desc = acpi_ut_create_string_object(((acpi_size) + operand0->string. length + local_operand1-> string.length)); @@ -352,8 +352,8 @@ acpi_ex_do_concatenate(union acpi_operand_object *operand0, /* Result of two Buffers is a Buffer */ - return_desc = acpi_ut_create_buffer_object((acpi_size) - (operand0->buffer. + return_desc = acpi_ut_create_buffer_object(((acpi_size) + operand0->buffer. length + local_operand1-> buffer.length)); diff --git a/drivers/acpi/executer/exregion.c b/drivers/acpi/executer/exregion.c index 7cd8bb54fa01..7a41c409ae4d 100644 --- a/drivers/acpi/executer/exregion.c +++ b/drivers/acpi/executer/exregion.c @@ -156,7 +156,7 @@ acpi_ex_system_memory_space_handler(u32 function, /* Create a new mapping starting at the address given */ mem_info->mapped_logical_address = - acpi_os_map_memory((acpi_native_uint) address, window_size); + acpi_os_map_memory((acpi_physical_address) address, window_size); if (!mem_info->mapped_logical_address) { ACPI_ERROR((AE_INFO, "Could not map memory at %8.8X%8.8X, size %X", diff --git a/drivers/acpi/namespace/nsdump.c b/drivers/acpi/namespace/nsdump.c index 5445751b8a3e..904f9510c0e2 100644 --- a/drivers/acpi/namespace/nsdump.c +++ b/drivers/acpi/namespace/nsdump.c @@ -73,7 +73,7 @@ acpi_ns_dump_one_device(acpi_handle obj_handle, void acpi_ns_print_pathname(u32 num_segments, char *pathname) { - acpi_native_uint i; + u32 i; ACPI_FUNCTION_NAME(ns_print_pathname); diff --git a/drivers/acpi/namespace/nsload.c b/drivers/acpi/namespace/nsload.c index 2c92f6cf5ce1..a4a412b7c029 100644 --- a/drivers/acpi/namespace/nsload.c +++ b/drivers/acpi/namespace/nsload.c @@ -71,8 +71,7 @@ static acpi_status acpi_ns_delete_subtree(acpi_handle start_handle); ******************************************************************************/ acpi_status -acpi_ns_load_table(acpi_native_uint table_index, - struct acpi_namespace_node *node) +acpi_ns_load_table(u32 table_index, struct acpi_namespace_node *node) { acpi_status status; diff --git a/drivers/acpi/namespace/nsparse.c b/drivers/acpi/namespace/nsparse.c index 46a79b0103b6..a82271a9dbb3 100644 --- a/drivers/acpi/namespace/nsparse.c +++ b/drivers/acpi/namespace/nsparse.c @@ -63,13 +63,13 @@ ACPI_MODULE_NAME("nsparse") * ******************************************************************************/ acpi_status -acpi_ns_one_complete_parse(acpi_native_uint pass_number, - acpi_native_uint table_index, - struct acpi_namespace_node * start_node) +acpi_ns_one_complete_parse(u32 pass_number, + u32 table_index, + struct acpi_namespace_node *start_node) { union acpi_parse_object *parse_root; acpi_status status; - acpi_native_uint aml_length; + u32 aml_length; u8 *aml_start; struct acpi_walk_state *walk_state; struct acpi_table_header *table; @@ -112,8 +112,8 @@ acpi_ns_one_complete_parse(acpi_native_uint pass_number, aml_start = (u8 *) table + sizeof(struct acpi_table_header); aml_length = table->length - sizeof(struct acpi_table_header); status = acpi_ds_init_aml_walk(walk_state, parse_root, NULL, - aml_start, (u32) aml_length, - NULL, (u8) pass_number); + aml_start, aml_length, NULL, + (u8) pass_number); } if (ACPI_FAILURE(status)) { @@ -158,8 +158,7 @@ acpi_ns_one_complete_parse(acpi_native_uint pass_number, ******************************************************************************/ acpi_status -acpi_ns_parse_table(acpi_native_uint table_index, - struct acpi_namespace_node *start_node) +acpi_ns_parse_table(u32 table_index, struct acpi_namespace_node *start_node) { acpi_status status; diff --git a/drivers/acpi/namespace/nsutils.c b/drivers/acpi/namespace/nsutils.c index 64c039843ed2..5b5619c54594 100644 --- a/drivers/acpi/namespace/nsutils.c +++ b/drivers/acpi/namespace/nsutils.c @@ -365,7 +365,7 @@ acpi_status acpi_ns_build_internal_name(struct acpi_namestring_info *info) char *internal_name = info->internal_name; char *external_name = info->next_external_char; char *result = NULL; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_TRACE(ns_build_internal_name); @@ -400,12 +400,11 @@ acpi_status acpi_ns_build_internal_name(struct acpi_namestring_info *info) result = &internal_name[i]; } else if (num_segments == 2) { internal_name[i] = AML_DUAL_NAME_PREFIX; - result = &internal_name[(acpi_native_uint) (i + 1)]; + result = &internal_name[(acpi_size) i + 1]; } else { internal_name[i] = AML_MULTI_NAME_PREFIX_OP; - internal_name[(acpi_native_uint) (i + 1)] = - (char)num_segments; - result = &internal_name[(acpi_native_uint) (i + 2)]; + internal_name[(acpi_size) i + 1] = (char)num_segments; + result = &internal_name[(acpi_size) i + 2]; } } @@ -531,12 +530,12 @@ acpi_ns_externalize_name(u32 internal_name_length, char *internal_name, u32 * converted_name_length, char **converted_name) { - acpi_native_uint names_index = 0; - acpi_native_uint num_segments = 0; - acpi_native_uint required_length; - acpi_native_uint prefix_length = 0; - acpi_native_uint i = 0; - acpi_native_uint j = 0; + u32 names_index = 0; + u32 num_segments = 0; + u32 required_length; + u32 prefix_length = 0; + u32 i = 0; + u32 j = 0; ACPI_FUNCTION_TRACE(ns_externalize_name); @@ -582,9 +581,8 @@ acpi_ns_externalize_name(u32 internal_name_length, /* 4-byte names */ names_index = prefix_length + 2; - num_segments = (acpi_native_uint) (u8) - internal_name[(acpi_native_uint) - (prefix_length + 1)]; + num_segments = (u8) + internal_name[(acpi_size) prefix_length + 1]; break; case AML_DUAL_NAME_PREFIX: diff --git a/drivers/acpi/namespace/nsxfeval.c b/drivers/acpi/namespace/nsxfeval.c index b4e135eab7c7..38be5865d95d 100644 --- a/drivers/acpi/namespace/nsxfeval.c +++ b/drivers/acpi/namespace/nsxfeval.c @@ -441,7 +441,7 @@ acpi_ns_get_device_callback(acpi_handle obj_handle, u32 flags; struct acpica_device_id hid; struct acpi_compatible_id_list *cid; - acpi_native_uint i; + u32 i; int found; status = acpi_ut_acquire_mutex(ACPI_MTX_NAMESPACE); diff --git a/drivers/acpi/parser/psargs.c b/drivers/acpi/parser/psargs.c index e94463778845..d830b29b85b1 100644 --- a/drivers/acpi/parser/psargs.c +++ b/drivers/acpi/parser/psargs.c @@ -76,7 +76,7 @@ acpi_ps_get_next_package_length(struct acpi_parse_state *parser_state) { u8 *aml = parser_state->aml; u32 package_length = 0; - acpi_native_uint byte_count; + u32 byte_count; u8 byte_zero_mask = 0x3F; /* Default [0:5] */ ACPI_FUNCTION_TRACE(ps_get_next_package_length); @@ -86,7 +86,7 @@ acpi_ps_get_next_package_length(struct acpi_parse_state *parser_state) * used to encode the package length, either 0,1,2, or 3 */ byte_count = (aml[0] >> 6); - parser_state->aml += (byte_count + 1); + parser_state->aml += ((acpi_size) byte_count + 1); /* Get bytes 3, 2, 1 as needed */ diff --git a/drivers/acpi/parser/psxface.c b/drivers/acpi/parser/psxface.c index 5ee09e1245e3..270469aae842 100644 --- a/drivers/acpi/parser/psxface.c +++ b/drivers/acpi/parser/psxface.c @@ -333,7 +333,7 @@ acpi_status acpi_ps_execute_method(struct acpi_evaluate_info *info) static void acpi_ps_update_parameter_list(struct acpi_evaluate_info *info, u16 action) { - acpi_native_uint i; + u32 i; if (info->parameters) { diff --git a/drivers/acpi/resources/rscalc.c b/drivers/acpi/resources/rscalc.c index 8a112d11d491..f61ebc679e66 100644 --- a/drivers/acpi/resources/rscalc.c +++ b/drivers/acpi/resources/rscalc.c @@ -73,7 +73,7 @@ acpi_rs_stream_option_length(u32 resource_length, u32 minimum_total_length); static u8 acpi_rs_count_set_bits(u16 bit_field) { - acpi_native_uint bits_set; + u8 bits_set; ACPI_FUNCTION_ENTRY(); @@ -84,7 +84,7 @@ static u8 acpi_rs_count_set_bits(u16 bit_field) bit_field &= (u16) (bit_field - 1); } - return ((u8) bits_set); + return bits_set; } /******************************************************************************* diff --git a/drivers/acpi/resources/rsmisc.c b/drivers/acpi/resources/rsmisc.c index de1ac3881b22..96a6c0353255 100644 --- a/drivers/acpi/resources/rsmisc.c +++ b/drivers/acpi/resources/rsmisc.c @@ -82,7 +82,7 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource, ACPI_FUNCTION_TRACE(rs_convert_aml_to_resource); - if (((acpi_native_uint) resource) & 0x3) { + if (((acpi_size) resource) & 0x3) { /* Each internal resource struct is expected to be 32-bit aligned */ diff --git a/drivers/acpi/resources/rsutils.c b/drivers/acpi/resources/rsutils.c index 90ed83d05375..f7b3bcd59ba7 100644 --- a/drivers/acpi/resources/rsutils.c +++ b/drivers/acpi/resources/rsutils.c @@ -62,7 +62,7 @@ ACPI_MODULE_NAME("rsutils") ******************************************************************************/ u8 acpi_rs_decode_bitmask(u16 mask, u8 * list) { - acpi_native_uint i; + u8 i; u8 bit_count; ACPI_FUNCTION_ENTRY(); @@ -71,7 +71,7 @@ u8 acpi_rs_decode_bitmask(u16 mask, u8 * list) for (i = 0, bit_count = 0; mask; i++) { if (mask & 0x0001) { - list[bit_count] = (u8) i; + list[bit_count] = i; bit_count++; } @@ -96,8 +96,8 @@ u8 acpi_rs_decode_bitmask(u16 mask, u8 * list) u16 acpi_rs_encode_bitmask(u8 * list, u8 count) { - acpi_native_uint i; - acpi_native_uint mask; + u32 i; + u16 mask; ACPI_FUNCTION_ENTRY(); @@ -107,7 +107,7 @@ u16 acpi_rs_encode_bitmask(u8 * list, u8 count) mask |= (0x1 << list[i]); } - return ((u16) mask); + return mask; } /******************************************************************************* @@ -130,7 +130,7 @@ u16 acpi_rs_encode_bitmask(u8 * list, u8 count) void acpi_rs_move_data(void *destination, void *source, u16 item_count, u8 move_type) { - acpi_native_uint i; + u32 i; ACPI_FUNCTION_ENTRY(); diff --git a/drivers/acpi/tables/tbfadt.c b/drivers/acpi/tables/tbfadt.c index 949d4114eb9f..a4a41ba2484b 100644 --- a/drivers/acpi/tables/tbfadt.c +++ b/drivers/acpi/tables/tbfadt.c @@ -155,7 +155,7 @@ acpi_tb_init_generic_address(struct acpi_generic_address *generic_address, * ******************************************************************************/ -void acpi_tb_parse_fadt(acpi_native_uint table_index, u8 flags) +void acpi_tb_parse_fadt(u32 table_index, u8 flags) { u32 length; struct acpi_table_header *table; @@ -280,7 +280,7 @@ static void acpi_tb_convert_fadt(void) { u8 pm1_register_length; struct acpi_generic_address *target; - acpi_native_uint i; + u32 i; /* Update the local FADT table header length */ @@ -396,7 +396,7 @@ static void acpi_tb_validate_fadt(void) u32 *address32; struct acpi_generic_address *address64; u8 length; - acpi_native_uint i; + u32 i; /* Examine all of the 64-bit extended address fields (X fields) */ diff --git a/drivers/acpi/tables/tbfind.c b/drivers/acpi/tables/tbfind.c index 9ca3afc98c80..531584defbb8 100644 --- a/drivers/acpi/tables/tbfind.c +++ b/drivers/acpi/tables/tbfind.c @@ -65,10 +65,9 @@ ACPI_MODULE_NAME("tbfind") ******************************************************************************/ acpi_status acpi_tb_find_table(char *signature, - char *oem_id, - char *oem_table_id, acpi_native_uint * table_index) + char *oem_id, char *oem_table_id, u32 *table_index) { - acpi_native_uint i; + u32 i; acpi_status status; struct acpi_table_header header; diff --git a/drivers/acpi/tables/tbinstal.c b/drivers/acpi/tables/tbinstal.c index 5336ce88f89f..b22185f55a16 100644 --- a/drivers/acpi/tables/tbinstal.c +++ b/drivers/acpi/tables/tbinstal.c @@ -107,11 +107,10 @@ acpi_status acpi_tb_verify_table(struct acpi_table_desc *table_desc) ******************************************************************************/ acpi_status -acpi_tb_add_table(struct acpi_table_desc *table_desc, - acpi_native_uint * table_index) +acpi_tb_add_table(struct acpi_table_desc *table_desc, u32 *table_index) { - acpi_native_uint i; - acpi_native_uint length; + u32 i; + u32 length; acpi_status status = AE_OK; ACPI_FUNCTION_TRACE(tb_add_table); @@ -207,8 +206,8 @@ acpi_status acpi_tb_resize_root_table_list(void) /* Increase the Table Array size */ - tables = ACPI_ALLOCATE_ZEROED((acpi_gbl_root_table_list.size + - ACPI_ROOT_TABLE_SIZE_INCREMENT) + tables = ACPI_ALLOCATE_ZEROED(((acpi_size) acpi_gbl_root_table_list. + size + ACPI_ROOT_TABLE_SIZE_INCREMENT) * sizeof(struct acpi_table_desc)); if (!tables) { ACPI_ERROR((AE_INFO, @@ -220,7 +219,7 @@ acpi_status acpi_tb_resize_root_table_list(void) if (acpi_gbl_root_table_list.tables) { ACPI_MEMCPY(tables, acpi_gbl_root_table_list.tables, - acpi_gbl_root_table_list.size * + (acpi_size) acpi_gbl_root_table_list.size * sizeof(struct acpi_table_desc)); if (acpi_gbl_root_table_list.flags & ACPI_ROOT_ORIGIN_ALLOCATED) { @@ -253,7 +252,7 @@ acpi_status acpi_tb_resize_root_table_list(void) acpi_status acpi_tb_store_table(acpi_physical_address address, struct acpi_table_header *table, - u32 length, u8 flags, acpi_native_uint * table_index) + u32 length, u8 flags, u32 *table_index) { acpi_status status = AE_OK; @@ -334,7 +333,7 @@ void acpi_tb_delete_table(struct acpi_table_desc *table_desc) void acpi_tb_terminate(void) { - acpi_native_uint i; + u32 i; ACPI_FUNCTION_TRACE(tb_terminate); @@ -374,7 +373,7 @@ void acpi_tb_terminate(void) * ******************************************************************************/ -void acpi_tb_delete_namespace_by_owner(acpi_native_uint table_index) +void acpi_tb_delete_namespace_by_owner(u32 table_index) { acpi_owner_id owner_id; @@ -403,7 +402,7 @@ void acpi_tb_delete_namespace_by_owner(acpi_native_uint table_index) * ******************************************************************************/ -acpi_status acpi_tb_allocate_owner_id(acpi_native_uint table_index) +acpi_status acpi_tb_allocate_owner_id(u32 table_index) { acpi_status status = AE_BAD_PARAMETER; @@ -431,7 +430,7 @@ acpi_status acpi_tb_allocate_owner_id(acpi_native_uint table_index) * ******************************************************************************/ -acpi_status acpi_tb_release_owner_id(acpi_native_uint table_index) +acpi_status acpi_tb_release_owner_id(u32 table_index) { acpi_status status = AE_BAD_PARAMETER; @@ -462,8 +461,7 @@ acpi_status acpi_tb_release_owner_id(acpi_native_uint table_index) * ******************************************************************************/ -acpi_status -acpi_tb_get_owner_id(acpi_native_uint table_index, acpi_owner_id * owner_id) +acpi_status acpi_tb_get_owner_id(u32 table_index, acpi_owner_id *owner_id) { acpi_status status = AE_BAD_PARAMETER; @@ -490,7 +488,7 @@ acpi_tb_get_owner_id(acpi_native_uint table_index, acpi_owner_id * owner_id) * ******************************************************************************/ -u8 acpi_tb_is_table_loaded(acpi_native_uint table_index) +u8 acpi_tb_is_table_loaded(u32 table_index) { u8 is_loaded = FALSE; @@ -518,7 +516,7 @@ u8 acpi_tb_is_table_loaded(acpi_native_uint table_index) * ******************************************************************************/ -void acpi_tb_set_table_loaded_flag(acpi_native_uint table_index, u8 is_loaded) +void acpi_tb_set_table_loaded_flag(u32 table_index, u8 is_loaded) { (void)acpi_ut_acquire_mutex(ACPI_MTX_TABLES); diff --git a/drivers/acpi/tables/tbutils.c b/drivers/acpi/tables/tbutils.c index bc019b9b6a68..0cc92ef5236f 100644 --- a/drivers/acpi/tables/tbutils.c +++ b/drivers/acpi/tables/tbutils.c @@ -49,8 +49,8 @@ ACPI_MODULE_NAME("tbutils") /* Local prototypes */ static acpi_physical_address -acpi_tb_get_root_table_entry(u8 * table_entry, - acpi_native_uint table_entry_size); +acpi_tb_get_root_table_entry(u8 *table_entry, u32 table_entry_size); + /******************************************************************************* * * FUNCTION: acpi_tb_check_xsdt @@ -238,7 +238,7 @@ acpi_status acpi_tb_verify_checksum(struct acpi_table_header *table, u32 length) * ******************************************************************************/ -u8 acpi_tb_checksum(u8 * buffer, acpi_native_uint length) +u8 acpi_tb_checksum(u8 *buffer, u32 length) { u8 sum = 0; u8 *end = buffer + length; @@ -268,7 +268,7 @@ u8 acpi_tb_checksum(u8 * buffer, acpi_native_uint length) void acpi_tb_install_table(acpi_physical_address address, - u8 flags, char *signature, acpi_native_uint table_index) + u8 flags, char *signature, u32 table_index) { struct acpi_table_header *table; @@ -336,8 +336,7 @@ acpi_tb_install_table(acpi_physical_address address, ******************************************************************************/ static acpi_physical_address -acpi_tb_get_root_table_entry(u8 * table_entry, - acpi_native_uint table_entry_size) +acpi_tb_get_root_table_entry(u8 *table_entry, u32 table_entry_size) { u64 address64; @@ -395,8 +394,8 @@ acpi_status __init acpi_tb_parse_root_table(acpi_physical_address rsdp_address, u8 flags) { struct acpi_table_rsdp *rsdp; - acpi_native_uint table_entry_size; - acpi_native_uint i; + u32 table_entry_size; + u32 i; u32 table_count; struct acpi_table_header *table; acpi_physical_address address; diff --git a/drivers/acpi/tables/tbxface.c b/drivers/acpi/tables/tbxface.c index 0e319604d3e7..fd7770aa1061 100644 --- a/drivers/acpi/tables/tbxface.c +++ b/drivers/acpi/tables/tbxface.c @@ -125,7 +125,7 @@ acpi_initialize_tables(struct acpi_table_desc * initial_table_array, /* Root Table Array has been statically allocated by the host */ ACPI_MEMSET(initial_table_array, 0, - initial_table_count * + (acpi_size) initial_table_count * sizeof(struct acpi_table_desc)); acpi_gbl_root_table_list.tables = initial_table_array; @@ -183,9 +183,9 @@ acpi_status acpi_reallocate_root_table(void) return_ACPI_STATUS(AE_SUPPORT); } - new_size = - (acpi_gbl_root_table_list.count + - ACPI_ROOT_TABLE_SIZE_INCREMENT) * sizeof(struct acpi_table_desc); + new_size = ((acpi_size) acpi_gbl_root_table_list.count + + ACPI_ROOT_TABLE_SIZE_INCREMENT) * + sizeof(struct acpi_table_desc); /* Create new array and copy the old array */ @@ -222,7 +222,7 @@ acpi_status acpi_reallocate_root_table(void) acpi_status acpi_load_table(struct acpi_table_header *table_ptr) { acpi_status status; - acpi_native_uint table_index; + u32 table_index; struct acpi_table_desc table_desc; if (!table_ptr) @@ -264,11 +264,10 @@ ACPI_EXPORT_SYMBOL(acpi_load_table) *****************************************************************************/ acpi_status acpi_get_table_header(char *signature, - acpi_native_uint instance, - struct acpi_table_header * out_table_header) + u32 instance, struct acpi_table_header *out_table_header) { - acpi_native_uint i; - acpi_native_uint j; + u32 i; + u32 j; struct acpi_table_header *header; /* Parameter validation */ @@ -378,10 +377,10 @@ ACPI_EXPORT_SYMBOL(acpi_unload_table_id) *****************************************************************************/ acpi_status acpi_get_table(char *signature, - acpi_native_uint instance, struct acpi_table_header **out_table) + u32 instance, struct acpi_table_header **out_table) { - acpi_native_uint i; - acpi_native_uint j; + u32 i; + u32 j; acpi_status status; /* Parameter validation */ @@ -435,8 +434,7 @@ ACPI_EXPORT_SYMBOL(acpi_get_table) * ******************************************************************************/ acpi_status -acpi_get_table_by_index(acpi_native_uint table_index, - struct acpi_table_header ** table) +acpi_get_table_by_index(u32 table_index, struct acpi_table_header **table) { acpi_status status; @@ -493,7 +491,7 @@ static acpi_status acpi_tb_load_namespace(void) { acpi_status status; struct acpi_table_header *table; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_TRACE(tb_load_namespace); diff --git a/drivers/acpi/tables/tbxfroot.c b/drivers/acpi/tables/tbxfroot.c index b8c0dfa084f6..2d157e0f98d2 100644 --- a/drivers/acpi/tables/tbxfroot.c +++ b/drivers/acpi/tables/tbxfroot.c @@ -118,7 +118,7 @@ static acpi_status acpi_tb_validate_rsdp(struct acpi_table_rsdp *rsdp) * ******************************************************************************/ -acpi_status acpi_find_root_pointer(acpi_native_uint * table_address) +acpi_status acpi_find_root_pointer(acpi_size *table_address) { u8 *table_ptr; u8 *mem_rover; @@ -153,7 +153,7 @@ acpi_status acpi_find_root_pointer(acpi_native_uint * table_address) * 1b) Search EBDA paragraphs (EBDA is required to be a * minimum of 1_k length) */ - table_ptr = acpi_os_map_memory((acpi_native_uint) + table_ptr = acpi_os_map_memory((acpi_physical_address) physical_address, ACPI_EBDA_WINDOW_SIZE); if (!table_ptr) { diff --git a/drivers/acpi/utilities/utcopy.c b/drivers/acpi/utilities/utcopy.c index 655c290aca7b..53499ac90988 100644 --- a/drivers/acpi/utilities/utcopy.c +++ b/drivers/acpi/utilities/utcopy.c @@ -572,7 +572,7 @@ acpi_ut_copy_epackage_to_ipackage(union acpi_object *external_object, acpi_status status = AE_OK; union acpi_operand_object *package_object; union acpi_operand_object **package_elements; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_TRACE(ut_copy_epackage_to_ipackage); @@ -599,7 +599,7 @@ acpi_ut_copy_epackage_to_ipackage(union acpi_object *external_object, /* Truncate package and delete it */ - package_object->package.count = (u32) i; + package_object->package.count = i; package_elements[i] = NULL; acpi_ut_remove_reference(package_object); return_ACPI_STATUS(status); diff --git a/drivers/acpi/utilities/utdebug.c b/drivers/acpi/utilities/utdebug.c index f938f465efa4..3919fe599f94 100644 --- a/drivers/acpi/utilities/utdebug.c +++ b/drivers/acpi/utilities/utdebug.c @@ -519,8 +519,8 @@ acpi_ut_ptr_exit(u32 line_number, void acpi_ut_dump_buffer2(u8 * buffer, u32 count, u32 display) { - acpi_native_uint i = 0; - acpi_native_uint j; + u32 i = 0; + u32 j; u32 temp32; u8 buf_char; @@ -539,7 +539,7 @@ void acpi_ut_dump_buffer2(u8 * buffer, u32 count, u32 display) /* Print current offset */ - acpi_os_printf("%6.4X: ", (u32) i); + acpi_os_printf("%6.4X: ", i); /* Print 16 hex chars */ @@ -549,7 +549,7 @@ void acpi_ut_dump_buffer2(u8 * buffer, u32 count, u32 display) /* Dump fill spaces */ acpi_os_printf("%*s", ((display * 2) + 1), " "); - j += (acpi_native_uint) display; + j += display; continue; } @@ -557,32 +557,38 @@ void acpi_ut_dump_buffer2(u8 * buffer, u32 count, u32 display) case DB_BYTE_DISPLAY: default: /* Default is BYTE display */ - acpi_os_printf("%02X ", buffer[i + j]); + acpi_os_printf("%02X ", + buffer[(acpi_size) i + j]); break; case DB_WORD_DISPLAY: - ACPI_MOVE_16_TO_32(&temp32, &buffer[i + j]); + ACPI_MOVE_16_TO_32(&temp32, + &buffer[(acpi_size) i + j]); acpi_os_printf("%04X ", temp32); break; case DB_DWORD_DISPLAY: - ACPI_MOVE_32_TO_32(&temp32, &buffer[i + j]); + ACPI_MOVE_32_TO_32(&temp32, + &buffer[(acpi_size) i + j]); acpi_os_printf("%08X ", temp32); break; case DB_QWORD_DISPLAY: - ACPI_MOVE_32_TO_32(&temp32, &buffer[i + j]); + ACPI_MOVE_32_TO_32(&temp32, + &buffer[(acpi_size) i + j]); acpi_os_printf("%08X", temp32); - ACPI_MOVE_32_TO_32(&temp32, &buffer[i + j + 4]); + ACPI_MOVE_32_TO_32(&temp32, + &buffer[(acpi_size) i + j + + 4]); acpi_os_printf("%08X ", temp32); break; } - j += (acpi_native_uint) display; + j += display; } /* @@ -596,7 +602,7 @@ void acpi_ut_dump_buffer2(u8 * buffer, u32 count, u32 display) return; } - buf_char = buffer[i + j]; + buf_char = buffer[(acpi_size) i + j]; if (ACPI_IS_PRINT(buf_char)) { acpi_os_printf("%c", buf_char); } else { diff --git a/drivers/acpi/utilities/utdelete.c b/drivers/acpi/utilities/utdelete.c index 1fbc35139e84..c5c791a575c9 100644 --- a/drivers/acpi/utilities/utdelete.c +++ b/drivers/acpi/utilities/utdelete.c @@ -442,7 +442,7 @@ acpi_ut_update_object_reference(union acpi_operand_object *object, u16 action) union acpi_generic_state *state_list = NULL; union acpi_operand_object *next_object = NULL; union acpi_generic_state *state; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_TRACE_PTR(ut_update_object_reference, object); diff --git a/drivers/acpi/utilities/uteval.c b/drivers/acpi/utilities/uteval.c index 7f1f6341242d..352747e49c7a 100644 --- a/drivers/acpi/utilities/uteval.c +++ b/drivers/acpi/utilities/uteval.c @@ -97,7 +97,7 @@ acpi_status acpi_ut_osi_implementation(struct acpi_walk_state *walk_state) acpi_status status; union acpi_operand_object *string_desc; union acpi_operand_object *return_desc; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_TRACE(ut_osi_implementation); @@ -513,7 +513,7 @@ acpi_ut_execute_CID(struct acpi_namespace_node * device_node, u32 count; u32 size; struct acpi_compatible_id_list *cid_list; - acpi_native_uint i; + u32 i; ACPI_FUNCTION_TRACE(ut_execute_CID); diff --git a/drivers/acpi/utilities/utmisc.c b/drivers/acpi/utilities/utmisc.c index 47354d9b0e56..6175ca5d73bf 100644 --- a/drivers/acpi/utilities/utmisc.c +++ b/drivers/acpi/utilities/utmisc.c @@ -161,9 +161,9 @@ u8 acpi_ut_is_aml_table(struct acpi_table_header *table) acpi_status acpi_ut_allocate_owner_id(acpi_owner_id * owner_id) { - acpi_native_uint i; - acpi_native_uint j; - acpi_native_uint k; + u32 i; + u32 j; + u32 k; acpi_status status; ACPI_FUNCTION_TRACE(ut_allocate_owner_id); @@ -269,7 +269,7 @@ void acpi_ut_release_owner_id(acpi_owner_id * owner_id_ptr) { acpi_owner_id owner_id = *owner_id_ptr; acpi_status status; - acpi_native_uint index; + u32 index; u32 bit; ACPI_FUNCTION_TRACE_U32(ut_release_owner_id, owner_id); @@ -589,7 +589,7 @@ acpi_ut_display_init_pathname(u8 type, * ******************************************************************************/ -u8 acpi_ut_valid_acpi_char(char character, acpi_native_uint position) +u8 acpi_ut_valid_acpi_char(char character, u32 position) { if (!((character >= 'A' && character <= 'Z') || @@ -624,7 +624,7 @@ u8 acpi_ut_valid_acpi_char(char character, acpi_native_uint position) u8 acpi_ut_valid_acpi_name(u32 name) { - acpi_native_uint i; + u32 i; ACPI_FUNCTION_ENTRY(); @@ -653,7 +653,7 @@ u8 acpi_ut_valid_acpi_name(u32 name) acpi_name acpi_ut_repair_name(char *name) { - acpi_native_uint i; + u32 i; char new_name[ACPI_NAME_SIZE]; for (i = 0; i < ACPI_NAME_SIZE; i++) { diff --git a/drivers/acpi/utilities/utobject.c b/drivers/acpi/utilities/utobject.c index e68466de8044..ede6a80837df 100644 --- a/drivers/acpi/utilities/utobject.c +++ b/drivers/acpi/utilities/utobject.c @@ -175,8 +175,8 @@ union acpi_operand_object *acpi_ut_create_package_object(u32 count) * Create the element array. Count+1 allows the array to be null * terminated. */ - package_elements = ACPI_ALLOCATE_ZEROED((acpi_size) - (count + 1) * sizeof(void *)); + package_elements = ACPI_ALLOCATE_ZEROED(((acpi_size) count + + 1) * sizeof(void *)); if (!package_elements) { acpi_ut_remove_reference(package_desc); return_PTR(NULL); diff --git a/include/acpi/acdispat.h b/include/acpi/acdispat.h index 910f018d92c7..21a73a105d0a 100644 --- a/include/acpi/acdispat.h +++ b/include/acpi/acdispat.h @@ -221,7 +221,7 @@ acpi_ds_method_error(acpi_status status, struct acpi_walk_state *walk_state); * dsinit */ acpi_status -acpi_ds_initialize_objects(acpi_native_uint table_index, +acpi_ds_initialize_objects(u32 table_index, struct acpi_namespace_node *start_node); /* diff --git a/include/acpi/acglobal.h b/include/acpi/acglobal.h index 74ad971241db..15dda46b70d1 100644 --- a/include/acpi/acglobal.h +++ b/include/acpi/acglobal.h @@ -140,7 +140,7 @@ ACPI_EXTERN u32 acpi_gbl_trace_flags; */ ACPI_EXTERN struct acpi_internal_rsdt acpi_gbl_root_table_list; ACPI_EXTERN struct acpi_table_fadt acpi_gbl_FADT; -extern acpi_native_uint acpi_gbl_permanent_mmap; +extern u8 acpi_gbl_permanent_mmap; /* These addresses are calculated from FADT address values */ diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h index 5ad6e3992304..d0494ea74b22 100644 --- a/include/acpi/acmacros.h +++ b/include/acpi/acmacros.h @@ -80,12 +80,12 @@ */ #define ACPI_CAST_PTR(t, p) ((t *) (acpi_uintptr_t) (p)) #define ACPI_CAST_INDIRECT_PTR(t, p) ((t **) (acpi_uintptr_t) (p)) -#define ACPI_ADD_PTR(t,a,b) ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8,(a)) + (acpi_native_uint)(b))) -#define ACPI_PTR_DIFF(a,b) (acpi_native_uint) (ACPI_CAST_PTR (u8,(a)) - ACPI_CAST_PTR (u8,(b))) +#define ACPI_ADD_PTR(t, a, b) ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8,(a)) + (acpi_size)(b))) +#define ACPI_PTR_DIFF(a, b) (acpi_size) (ACPI_CAST_PTR (u8,(a)) - ACPI_CAST_PTR (u8,(b))) /* Pointer/Integer type conversions */ -#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void,(void *) NULL,(acpi_native_uint) i) +#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void, (void *) NULL, (acpi_size) i) #define ACPI_TO_INTEGER(p) ACPI_PTR_DIFF (p,(void *) NULL) #define ACPI_OFFSET(d,f) (acpi_size) ACPI_PTR_DIFF (&(((d *)0)->f),(void *) NULL) #define ACPI_PHYSADDR_TO_PTR(i) ACPI_TO_POINTER(i) @@ -296,22 +296,22 @@ struct acpi_integer_overlay { /* * Rounding macros (Power of two boundaries only) */ -#define ACPI_ROUND_DOWN(value,boundary) (((acpi_native_uint)(value)) & \ - (~(((acpi_native_uint) boundary)-1))) +#define ACPI_ROUND_DOWN(value, boundary) (((acpi_size)(value)) & \ + (~(((acpi_size) boundary)-1))) -#define ACPI_ROUND_UP(value,boundary) ((((acpi_native_uint)(value)) + \ - (((acpi_native_uint) boundary)-1)) & \ - (~(((acpi_native_uint) boundary)-1))) +#define ACPI_ROUND_UP(value, boundary) ((((acpi_size)(value)) + \ + (((acpi_size) boundary)-1)) & \ + (~(((acpi_size) boundary)-1))) -/* Note: sizeof(acpi_native_uint) evaluates to either 2, 4, or 8 */ +/* Note: sizeof(acpi_size) evaluates to either 4 or 8 (32- vs 64-bit mode) */ #define ACPI_ROUND_DOWN_TO_32BIT(a) ACPI_ROUND_DOWN(a,4) #define ACPI_ROUND_DOWN_TO_64BIT(a) ACPI_ROUND_DOWN(a,8) -#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a) ACPI_ROUND_DOWN(a,sizeof(acpi_native_uint)) +#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a) ACPI_ROUND_DOWN(a,sizeof(acpi_size)) #define ACPI_ROUND_UP_TO_32BIT(a) ACPI_ROUND_UP(a,4) #define ACPI_ROUND_UP_TO_64BIT(a) ACPI_ROUND_UP(a,8) -#define ACPI_ROUND_UP_TO_NATIVE_WORD(a) ACPI_ROUND_UP(a,sizeof(acpi_native_uint)) +#define ACPI_ROUND_UP_TO_NATIVE_WORD(a) ACPI_ROUND_UP(a,sizeof(acpi_size)) #define ACPI_ROUND_BITS_UP_TO_BYTES(a) ACPI_DIV_8((a) + 7) #define ACPI_ROUND_BITS_DOWN_TO_BYTES(a) ACPI_DIV_8((a)) @@ -322,7 +322,7 @@ struct acpi_integer_overlay { #define ACPI_ROUND_UP_TO(value,boundary) (((value) + ((boundary)-1)) / (boundary)) -#define ACPI_IS_MISALIGNED(value) (((acpi_native_uint)value) & (sizeof(acpi_native_uint)-1)) +#define ACPI_IS_MISALIGNED(value) (((acpi_size)value) & (sizeof(acpi_size)-1)) /* * Bitmask creation diff --git a/include/acpi/acnamesp.h b/include/acpi/acnamesp.h index 713b30903fe5..d622c309002e 100644 --- a/include/acpi/acnamesp.h +++ b/include/acpi/acnamesp.h @@ -86,8 +86,7 @@ acpi_status acpi_ns_initialize_devices(void); acpi_status acpi_ns_load_namespace(void); acpi_status -acpi_ns_load_table(acpi_native_uint table_index, - struct acpi_namespace_node *node); +acpi_ns_load_table(u32 table_index, struct acpi_namespace_node *node); /* * nswalk - walk the namespace @@ -108,12 +107,11 @@ struct acpi_namespace_node *acpi_ns_get_next_node(acpi_object_type type, struct * nsparse - table parsing */ acpi_status -acpi_ns_parse_table(acpi_native_uint table_index, - struct acpi_namespace_node *start_node); +acpi_ns_parse_table(u32 table_index, struct acpi_namespace_node *start_node); acpi_status -acpi_ns_one_complete_parse(acpi_native_uint pass_number, - acpi_native_uint table_index, +acpi_ns_one_complete_parse(u32 pass_number, + u32 table_index, struct acpi_namespace_node *start_node); /* diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h index d4a560d2deb6..3f93a6b4e17f 100644 --- a/include/acpi/acpiosxf.h +++ b/include/acpi/acpiosxf.h @@ -144,7 +144,7 @@ void acpi_os_release_mutex(acpi_mutex handle); void *acpi_os_allocate(acpi_size size); void __iomem *acpi_os_map_memory(acpi_physical_address where, - acpi_native_uint length); + acpi_size length); void acpi_os_unmap_memory(void __iomem * logical_address, acpi_size size); diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index 2c3806e6546f..bd95ecc6e0fa 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -98,7 +98,7 @@ void acpi_free(void *address); */ acpi_status acpi_reallocate_root_table(void); -acpi_status acpi_find_root_pointer(acpi_native_uint * rsdp_address); +acpi_status acpi_find_root_pointer(acpi_size *rsdp_address); acpi_status acpi_load_tables(void); @@ -108,15 +108,15 @@ acpi_status acpi_unload_table_id(acpi_owner_id id); acpi_status acpi_get_table_header(acpi_string signature, - acpi_native_uint instance, + u32 instance, struct acpi_table_header *out_table_header); acpi_status acpi_get_table(acpi_string signature, - acpi_native_uint instance, struct acpi_table_header **out_table); + u32 instance, struct acpi_table_header **out_table); acpi_status -acpi_get_table_by_index(acpi_native_uint table_index, +acpi_get_table_by_index(u32 table_index, struct acpi_table_header **out_table); acpi_status diff --git a/include/acpi/acstruct.h b/include/acpi/acstruct.h index 818c24d7d2d1..7980a26bad35 100644 --- a/include/acpi/acstruct.h +++ b/include/acpi/acstruct.h @@ -142,7 +142,7 @@ struct acpi_init_walk_info { u16 package_init; u16 object_count; acpi_owner_id owner_id; - acpi_native_uint table_index; + u32 table_index; }; struct acpi_get_devices_info { diff --git a/include/acpi/actables.h b/include/acpi/actables.h index 4b36a55b0b3b..0cbe1b9ab522 100644 --- a/include/acpi/actables.h +++ b/include/acpi/actables.h @@ -49,7 +49,7 @@ acpi_status acpi_allocate_root_table(u32 initial_table_count); /* * tbfadt - FADT parse/convert/validate */ -void acpi_tb_parse_fadt(acpi_native_uint table_index, u8 flags); +void acpi_tb_parse_fadt(u32 table_index, u8 flags); void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length); @@ -58,8 +58,7 @@ void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length); */ acpi_status acpi_tb_find_table(char *signature, - char *oem_id, - char *oem_table_id, acpi_native_uint * table_index); + char *oem_id, char *oem_table_id, u32 *table_index); /* * tbinstal - Table removal and deletion @@ -69,30 +68,28 @@ acpi_status acpi_tb_resize_root_table_list(void); acpi_status acpi_tb_verify_table(struct acpi_table_desc *table_desc); acpi_status -acpi_tb_add_table(struct acpi_table_desc *table_desc, - acpi_native_uint * table_index); +acpi_tb_add_table(struct acpi_table_desc *table_desc, u32 *table_index); acpi_status acpi_tb_store_table(acpi_physical_address address, struct acpi_table_header *table, - u32 length, u8 flags, acpi_native_uint * table_index); + u32 length, u8 flags, u32 *table_index); void acpi_tb_delete_table(struct acpi_table_desc *table_desc); void acpi_tb_terminate(void); -void acpi_tb_delete_namespace_by_owner(acpi_native_uint table_index); +void acpi_tb_delete_namespace_by_owner(u32 table_index); -acpi_status acpi_tb_allocate_owner_id(acpi_native_uint table_index); +acpi_status acpi_tb_allocate_owner_id(u32 table_index); -acpi_status acpi_tb_release_owner_id(acpi_native_uint table_index); +acpi_status acpi_tb_release_owner_id(u32 table_index); -acpi_status -acpi_tb_get_owner_id(acpi_native_uint table_index, acpi_owner_id * owner_id); +acpi_status acpi_tb_get_owner_id(u32 table_index, acpi_owner_id *owner_id); -u8 acpi_tb_is_table_loaded(acpi_native_uint table_index); +u8 acpi_tb_is_table_loaded(u32 table_index); -void acpi_tb_set_table_loaded_flag(acpi_native_uint table_index, u8 is_loaded); +void acpi_tb_set_table_loaded_flag(u32 table_index, u8 is_loaded); /* * tbutils - table manager utilities @@ -103,14 +100,14 @@ void acpi_tb_print_table_header(acpi_physical_address address, struct acpi_table_header *header); -u8 acpi_tb_checksum(u8 * buffer, acpi_native_uint length); +u8 acpi_tb_checksum(u8 *buffer, u32 length); acpi_status acpi_tb_verify_checksum(struct acpi_table_header *table, u32 length); void acpi_tb_install_table(acpi_physical_address address, - u8 flags, char *signature, acpi_native_uint table_index); + u8 flags, char *signature, u32 table_index); acpi_status acpi_tb_parse_root_table(acpi_physical_address rsdp_address, u8 flags); diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index dfea2d440488..4ea4f40bf894 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -110,10 +110,10 @@ * usually used for memory allocation, efficient loop counters, and array * indexes. The types are similar to the size_t type in the C library and are * required because there is no C type that consistently represents the native - * data width. + * data width. ACPI_SIZE is needed because there is no guarantee that a + * kernel-level C library is present. * * ACPI_SIZE 16/32/64-bit unsigned value - * ACPI_NATIVE_UINT 16/32/64-bit unsigned value * ACPI_NATIVE_INT 16/32/64-bit signed value * */ @@ -147,9 +147,9 @@ typedef int INT32; /*! [End] no source code translation !*/ -typedef u64 acpi_native_uint; typedef s64 acpi_native_int; +typedef u64 acpi_size; typedef u64 acpi_io_address; typedef u64 acpi_physical_address; @@ -186,9 +186,9 @@ typedef int INT32; /*! [End] no source code translation !*/ -typedef u32 acpi_native_uint; typedef s32 acpi_native_int; +typedef u32 acpi_size; typedef u32 acpi_io_address; typedef u32 acpi_physical_address; @@ -202,10 +202,6 @@ typedef u32 acpi_physical_address; #error unknown ACPI_MACHINE_WIDTH #endif -/* Variable-width type, used instead of clib size_t */ - -typedef acpi_native_uint acpi_size; - /******************************************************************************* * * OS-dependent and compiler-dependent types @@ -219,7 +215,7 @@ typedef acpi_native_uint acpi_size; /* Value returned by acpi_os_get_thread_id */ #ifndef acpi_thread_id -#define acpi_thread_id acpi_native_uint +#define acpi_thread_id acpi_size #endif /* Object returned from acpi_os_create_lock */ @@ -231,7 +227,7 @@ typedef acpi_native_uint acpi_size; /* Flags for acpi_os_acquire_lock/acpi_os_release_lock */ #ifndef acpi_cpu_flags -#define acpi_cpu_flags acpi_native_uint +#define acpi_cpu_flags acpi_size #endif /* Object returned from acpi_os_create_cache */ diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h index b42cadf07302..3f663a0077be 100644 --- a/include/acpi/acutils.h +++ b/include/acpi/acutils.h @@ -172,7 +172,7 @@ char *acpi_ut_strstr(char *string1, char *string2); void *acpi_ut_memcpy(void *dest, const void *src, acpi_size count); -void *acpi_ut_memset(void *dest, acpi_native_uint value, acpi_size count); +void *acpi_ut_memset(void *dest, u8 value, acpi_size count); int acpi_ut_to_upper(int c); @@ -476,7 +476,7 @@ u8 acpi_ut_valid_acpi_name(u32 name); acpi_name acpi_ut_repair_name(char *name); -u8 acpi_ut_valid_acpi_char(char character, acpi_native_uint position); +u8 acpi_ut_valid_acpi_char(char character, u32 position); acpi_status acpi_ut_strtoul64(char *string, u32 base, acpi_integer * ret_integer); -- cgit v1.2.3 From 4b8ed631679070c183c8ae7519d2bdb9df124ae4 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 13:55:53 +0800 Subject: ACPICA: Add const qualifier for appropriate string constants Mostly MODULE_NAME and printf format strings. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- drivers/acpi/executer/exdump.c | 5 +-- drivers/acpi/namespace/nsutils.c | 24 +++++++------- drivers/acpi/utilities/utalloc.c | 5 +-- drivers/acpi/utilities/utdebug.c | 26 +++++++++------ drivers/acpi/utilities/utmisc.c | 11 ++++--- drivers/acpi/utilities/utobject.c | 5 +-- include/acpi/acinterp.h | 5 +-- include/acpi/aclocal.h | 4 +-- include/acpi/acmacros.h | 2 +- include/acpi/acnamesp.h | 20 ++++++------ include/acpi/acutils.h | 66 ++++++++++++++++++++++----------------- 11 files changed, 99 insertions(+), 74 deletions(-) (limited to 'include') diff --git a/drivers/acpi/executer/exdump.c b/drivers/acpi/executer/exdump.c index 976016fda66a..c94638dc42e5 100644 --- a/drivers/acpi/executer/exdump.c +++ b/drivers/acpi/executer/exdump.c @@ -771,9 +771,10 @@ void acpi_ex_dump_operand(union acpi_operand_object *obj_desc, u32 depth) void acpi_ex_dump_operands(union acpi_operand_object **operands, acpi_interpreter_mode interpreter_mode, - char *ident, + const char *ident, u32 num_levels, - char *note, char *module_name, u32 line_number) + const char *note, + const char *module_name, u32 line_number) { u32 i; diff --git a/drivers/acpi/namespace/nsutils.c b/drivers/acpi/namespace/nsutils.c index 5b5619c54594..b0817e1127b1 100644 --- a/drivers/acpi/namespace/nsutils.c +++ b/drivers/acpi/namespace/nsutils.c @@ -73,9 +73,9 @@ acpi_name acpi_ns_find_parent_name(struct acpi_namespace_node *node_to_search); ******************************************************************************/ void -acpi_ns_report_error(char *module_name, +acpi_ns_report_error(const char *module_name, u32 line_number, - char *internal_name, acpi_status lookup_status) + const char *internal_name, acpi_status lookup_status) { acpi_status status; u32 bad_name; @@ -130,11 +130,11 @@ acpi_ns_report_error(char *module_name, ******************************************************************************/ void -acpi_ns_report_method_error(char *module_name, +acpi_ns_report_method_error(const char *module_name, u32 line_number, - char *message, + const char *message, struct acpi_namespace_node *prefix_node, - char *path, acpi_status method_status) + const char *path, acpi_status method_status) { acpi_status status; struct acpi_namespace_node *node = prefix_node; @@ -167,7 +167,8 @@ acpi_ns_report_method_error(char *module_name, ******************************************************************************/ void -acpi_ns_print_node_pathname(struct acpi_namespace_node *node, char *message) +acpi_ns_print_node_pathname(struct acpi_namespace_node *node, + const char *message) { struct acpi_buffer buffer; acpi_status status; @@ -296,7 +297,7 @@ u32 acpi_ns_local(acpi_object_type type) void acpi_ns_get_internal_name_length(struct acpi_namestring_info *info) { - char *next_external_char; + const char *next_external_char; u32 i; ACPI_FUNCTION_ENTRY(); @@ -363,7 +364,7 @@ acpi_status acpi_ns_build_internal_name(struct acpi_namestring_info *info) { u32 num_segments = info->num_segments; char *internal_name = info->internal_name; - char *external_name = info->next_external_char; + const char *external_name = info->next_external_char; char *result = NULL; u32 i; @@ -471,7 +472,8 @@ acpi_status acpi_ns_build_internal_name(struct acpi_namestring_info *info) * *******************************************************************************/ -acpi_status acpi_ns_internalize_name(char *external_name, char **converted_name) +acpi_status +acpi_ns_internalize_name(const char *external_name, char **converted_name) { char *internal_name; struct acpi_namestring_info info; @@ -527,7 +529,7 @@ acpi_status acpi_ns_internalize_name(char *external_name, char **converted_name) acpi_status acpi_ns_externalize_name(u32 internal_name_length, - char *internal_name, + const char *internal_name, u32 * converted_name_length, char **converted_name) { u32 names_index = 0; @@ -821,7 +823,7 @@ u32 acpi_ns_opens_scope(acpi_object_type type) acpi_status acpi_ns_get_node(struct acpi_namespace_node *prefix_node, - char *pathname, + const char *pathname, u32 flags, struct acpi_namespace_node **return_node) { union acpi_generic_state scope_info; diff --git a/drivers/acpi/utilities/utalloc.c b/drivers/acpi/utilities/utalloc.c index ede084829a70..3dfb8a442b26 100644 --- a/drivers/acpi/utilities/utalloc.c +++ b/drivers/acpi/utilities/utalloc.c @@ -309,7 +309,8 @@ acpi_ut_initialize_buffer(struct acpi_buffer * buffer, * ******************************************************************************/ -void *acpi_ut_allocate(acpi_size size, u32 component, char *module, u32 line) +void *acpi_ut_allocate(acpi_size size, + u32 component, const char *module, u32 line) { void *allocation; @@ -353,7 +354,7 @@ void *acpi_ut_allocate(acpi_size size, u32 component, char *module, u32 line) ******************************************************************************/ void *acpi_ut_allocate_zeroed(acpi_size size, - u32 component, char *module, u32 line) + u32 component, const char *module, u32 line) { void *allocation; diff --git a/drivers/acpi/utilities/utdebug.c b/drivers/acpi/utilities/utdebug.c index 3919fe599f94..fd66ecb6741e 100644 --- a/drivers/acpi/utilities/utdebug.c +++ b/drivers/acpi/utilities/utdebug.c @@ -157,7 +157,8 @@ void ACPI_INTERNAL_VAR_XFACE acpi_ut_debug_print(u32 requested_debug_level, u32 line_number, const char *function_name, - char *module_name, u32 component_id, char *format, ...) + const char *module_name, + u32 component_id, const char *format, ...) { acpi_thread_id thread_id; va_list args; @@ -228,7 +229,8 @@ void ACPI_INTERNAL_VAR_XFACE acpi_ut_debug_print_raw(u32 requested_debug_level, u32 line_number, const char *function_name, - char *module_name, u32 component_id, char *format, ...) + const char *module_name, + u32 component_id, const char *format, ...) { va_list args; @@ -261,7 +263,8 @@ ACPI_EXPORT_SYMBOL(acpi_ut_debug_print_raw) ******************************************************************************/ void acpi_ut_trace(u32 line_number, - const char *function_name, char *module_name, u32 component_id) + const char *function_name, + const char *module_name, u32 component_id) { acpi_gbl_nesting_level++; @@ -293,7 +296,7 @@ ACPI_EXPORT_SYMBOL(acpi_ut_trace) void acpi_ut_trace_ptr(u32 line_number, const char *function_name, - char *module_name, u32 component_id, void *pointer) + const char *module_name, u32 component_id, void *pointer) { acpi_gbl_nesting_level++; acpi_ut_track_stack_ptr(); @@ -324,7 +327,7 @@ acpi_ut_trace_ptr(u32 line_number, void acpi_ut_trace_str(u32 line_number, const char *function_name, - char *module_name, u32 component_id, char *string) + const char *module_name, u32 component_id, char *string) { acpi_gbl_nesting_level++; @@ -356,7 +359,7 @@ acpi_ut_trace_str(u32 line_number, void acpi_ut_trace_u32(u32 line_number, const char *function_name, - char *module_name, u32 component_id, u32 integer) + const char *module_name, u32 component_id, u32 integer) { acpi_gbl_nesting_level++; @@ -386,7 +389,8 @@ acpi_ut_trace_u32(u32 line_number, void acpi_ut_exit(u32 line_number, - const char *function_name, char *module_name, u32 component_id) + const char *function_name, + const char *module_name, u32 component_id) { acpi_ut_debug_print(ACPI_LV_FUNCTIONS, @@ -417,7 +421,8 @@ ACPI_EXPORT_SYMBOL(acpi_ut_exit) void acpi_ut_status_exit(u32 line_number, const char *function_name, - char *module_name, u32 component_id, acpi_status status) + const char *module_name, + u32 component_id, acpi_status status) { if (ACPI_SUCCESS(status)) { @@ -458,7 +463,8 @@ ACPI_EXPORT_SYMBOL(acpi_ut_status_exit) void acpi_ut_value_exit(u32 line_number, const char *function_name, - char *module_name, u32 component_id, acpi_integer value) + const char *module_name, + u32 component_id, acpi_integer value) { acpi_ut_debug_print(ACPI_LV_FUNCTIONS, @@ -490,7 +496,7 @@ ACPI_EXPORT_SYMBOL(acpi_ut_value_exit) void acpi_ut_ptr_exit(u32 line_number, const char *function_name, - char *module_name, u32 component_id, u8 * ptr) + const char *module_name, u32 component_id, u8 *ptr) { acpi_ut_debug_print(ACPI_LV_FUNCTIONS, diff --git a/drivers/acpi/utilities/utmisc.c b/drivers/acpi/utilities/utmisc.c index 6175ca5d73bf..f34be6773556 100644 --- a/drivers/acpi/utilities/utmisc.c +++ b/drivers/acpi/utilities/utmisc.c @@ -1020,7 +1020,7 @@ acpi_ut_walk_package_tree(union acpi_operand_object * source_object, ******************************************************************************/ void ACPI_INTERNAL_VAR_XFACE -acpi_ut_error(char *module_name, u32 line_number, char *format, ...) +acpi_ut_error(const char *module_name, u32 line_number, const char *format, ...) { va_list args; @@ -1033,8 +1033,8 @@ acpi_ut_error(char *module_name, u32 line_number, char *format, ...) } void ACPI_INTERNAL_VAR_XFACE -acpi_ut_exception(char *module_name, - u32 line_number, acpi_status status, char *format, ...) +acpi_ut_exception(const char *module_name, + u32 line_number, acpi_status status, const char *format, ...) { va_list args; @@ -1050,7 +1050,8 @@ acpi_ut_exception(char *module_name, EXPORT_SYMBOL(acpi_ut_exception); void ACPI_INTERNAL_VAR_XFACE -acpi_ut_warning(char *module_name, u32 line_number, char *format, ...) +acpi_ut_warning(const char *module_name, + u32 line_number, const char *format, ...) { va_list args; @@ -1063,7 +1064,7 @@ acpi_ut_warning(char *module_name, u32 line_number, char *format, ...) } void ACPI_INTERNAL_VAR_XFACE -acpi_ut_info(char *module_name, u32 line_number, char *format, ...) +acpi_ut_info(const char *module_name, u32 line_number, const char *format, ...) { va_list args; diff --git a/drivers/acpi/utilities/utobject.c b/drivers/acpi/utilities/utobject.c index ede6a80837df..e25484495e65 100644 --- a/drivers/acpi/utilities/utobject.c +++ b/drivers/acpi/utilities/utobject.c @@ -83,7 +83,8 @@ acpi_ut_get_element_length(u8 object_type, * ******************************************************************************/ -union acpi_operand_object *acpi_ut_create_internal_object_dbg(char *module_name, +union acpi_operand_object *acpi_ut_create_internal_object_dbg(const char + *module_name, u32 line_number, u32 component_id, acpi_object_type @@ -347,7 +348,7 @@ u8 acpi_ut_valid_internal_object(void *object) * ******************************************************************************/ -void *acpi_ut_allocate_object_desc_dbg(char *module_name, +void *acpi_ut_allocate_object_desc_dbg(const char *module_name, u32 line_number, u32 component_id) { union acpi_operand_object *object; diff --git a/include/acpi/acinterp.h b/include/acpi/acinterp.h index e249ce5d3300..accd1208dfe3 100644 --- a/include/acpi/acinterp.h +++ b/include/acpi/acinterp.h @@ -367,9 +367,10 @@ void acpi_ex_dump_operand(union acpi_operand_object *obj_desc, u32 depth); void acpi_ex_dump_operands(union acpi_operand_object **operands, acpi_interpreter_mode interpreter_mode, - char *ident, + const char *ident, u32 num_levels, - char *note, char *module_name, u32 line_number); + const char *note, + const char *module_name, u32 line_number); #ifdef ACPI_FUTURE_USAGE void diff --git a/include/acpi/aclocal.h b/include/acpi/aclocal.h index 62d7468ed3f9..b221c8583ddd 100644 --- a/include/acpi/aclocal.h +++ b/include/acpi/aclocal.h @@ -282,8 +282,8 @@ struct acpi_predefined_names { /* Info structure used to convert external<->internal namestrings */ struct acpi_namestring_info { - char *external_name; - char *next_external_char; + const char *external_name; + const char *next_external_char; char *internal_name; u32 length; u32 num_segments; diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h index d0494ea74b22..77439df4632b 100644 --- a/include/acpi/acmacros.h +++ b/include/acpi/acmacros.h @@ -414,7 +414,7 @@ struct acpi_integer_overlay { * error messages. The __FILE__ macro is not very useful for this, because it * often includes the entire pathname to the module */ -#define ACPI_MODULE_NAME(name) static char ACPI_UNUSED_VAR _acpi_module_name[] = name; +#define ACPI_MODULE_NAME(name) static const char ACPI_UNUSED_VAR _acpi_module_name[] = name; #else #define ACPI_MODULE_NAME(name) #endif diff --git a/include/acpi/acnamesp.h b/include/acpi/acnamesp.h index d622c309002e..9ed70a050580 100644 --- a/include/acpi/acnamesp.h +++ b/include/acpi/acnamesp.h @@ -199,7 +199,7 @@ acpi_ns_pattern_match(struct acpi_namespace_node *obj_node, char *search_for); acpi_status acpi_ns_get_node(struct acpi_namespace_node *prefix_node, - char *external_pathname, + const char *external_pathname, u32 flags, struct acpi_namespace_node **out_node); acpi_size acpi_ns_get_pathname_length(struct acpi_namespace_node *node); @@ -263,28 +263,30 @@ acpi_object_type acpi_ns_get_type(struct acpi_namespace_node *node); u32 acpi_ns_local(acpi_object_type type); void -acpi_ns_report_error(char *module_name, +acpi_ns_report_error(const char *module_name, u32 line_number, - char *internal_name, acpi_status lookup_status); + const char *internal_name, acpi_status lookup_status); void -acpi_ns_report_method_error(char *module_name, +acpi_ns_report_method_error(const char *module_name, u32 line_number, - char *message, + const char *message, struct acpi_namespace_node *node, - char *path, acpi_status lookup_status); + const char *path, acpi_status lookup_status); -void acpi_ns_print_node_pathname(struct acpi_namespace_node *node, char *msg); +void +acpi_ns_print_node_pathname(struct acpi_namespace_node *node, const char *msg); acpi_status acpi_ns_build_internal_name(struct acpi_namestring_info *info); void acpi_ns_get_internal_name_length(struct acpi_namestring_info *info); -acpi_status acpi_ns_internalize_name(char *dotted_name, char **converted_name); +acpi_status +acpi_ns_internalize_name(const char *dotted_name, char **converted_name); acpi_status acpi_ns_externalize_name(u32 internal_name_length, - char *internal_name, + const char *internal_name, u32 * converted_name_length, char **converted_name); struct acpi_namespace_node *acpi_ns_map_handle_to_node(acpi_handle handle); diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h index 3f663a0077be..69f8888771ff 100644 --- a/include/acpi/acutils.h +++ b/include/acpi/acutils.h @@ -245,41 +245,45 @@ void acpi_ut_track_stack_ptr(void); void acpi_ut_trace(u32 line_number, - const char *function_name, char *module_name, u32 component_id); + const char *function_name, + const char *module_name, u32 component_id); void acpi_ut_trace_ptr(u32 line_number, const char *function_name, - char *module_name, u32 component_id, void *pointer); + const char *module_name, u32 component_id, void *pointer); void acpi_ut_trace_u32(u32 line_number, const char *function_name, - char *module_name, u32 component_id, u32 integer); + const char *module_name, u32 component_id, u32 integer); void acpi_ut_trace_str(u32 line_number, const char *function_name, - char *module_name, u32 component_id, char *string); + const char *module_name, u32 component_id, char *string); void acpi_ut_exit(u32 line_number, - const char *function_name, char *module_name, u32 component_id); + const char *function_name, + const char *module_name, u32 component_id); void acpi_ut_status_exit(u32 line_number, const char *function_name, - char *module_name, u32 component_id, acpi_status status); + const char *module_name, + u32 component_id, acpi_status status); void acpi_ut_value_exit(u32 line_number, const char *function_name, - char *module_name, u32 component_id, acpi_integer value); + const char *module_name, + u32 component_id, acpi_integer value); void acpi_ut_ptr_exit(u32 line_number, const char *function_name, - char *module_name, u32 component_id, u8 * ptr); + const char *module_name, u32 component_id, u8 *ptr); void acpi_ut_dump_buffer(u8 * buffer, u32 count, u32 display, u32 component_id); @@ -297,33 +301,35 @@ void ACPI_INTERNAL_VAR_XFACE acpi_ut_debug_print(u32 requested_debug_level, u32 line_number, const char *function_name, - char *module_name, - u32 component_id, char *format, ...) ACPI_PRINTF_LIKE(6); + const char *module_name, + u32 component_id, + const char *format, ...) ACPI_PRINTF_LIKE(6); void ACPI_INTERNAL_VAR_XFACE acpi_ut_debug_print_raw(u32 requested_debug_level, u32 line_number, const char *function_name, - char *module_name, + const char *module_name, u32 component_id, - char *format, ...) ACPI_PRINTF_LIKE(6); + const char *format, ...) ACPI_PRINTF_LIKE(6); void ACPI_INTERNAL_VAR_XFACE -acpi_ut_error(char *module_name, - u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3); +acpi_ut_error(const char *module_name, + u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3); void ACPI_INTERNAL_VAR_XFACE -acpi_ut_exception(char *module_name, +acpi_ut_exception(const char *module_name, u32 line_number, - acpi_status status, char *format, ...) ACPI_PRINTF_LIKE(4); + acpi_status status, + const char *format, ...) ACPI_PRINTF_LIKE(4); void ACPI_INTERNAL_VAR_XFACE -acpi_ut_warning(char *module_name, - u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3); +acpi_ut_warning(const char *module_name, + u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3); void ACPI_INTERNAL_VAR_XFACE -acpi_ut_info(char *module_name, - u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3); +acpi_ut_info(const char *module_name, + u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3); /* * utdelete - Object deletion and reference counts @@ -376,13 +382,14 @@ acpi_ut_execute_sxds(struct acpi_namespace_node *device_node, u8 * highest); /* * utobject - internal object create/delete/cache routines */ -union acpi_operand_object *acpi_ut_create_internal_object_dbg(char *module_name, +union acpi_operand_object *acpi_ut_create_internal_object_dbg(const char + *module_name, u32 line_number, u32 component_id, acpi_object_type type); -void *acpi_ut_allocate_object_desc_dbg(char *module_name, +void *acpi_ut_allocate_object_desc_dbg(const char *module_name, u32 line_number, u32 component_id); #define acpi_ut_create_internal_object(t) acpi_ut_create_internal_object_dbg (_acpi_module_name,__LINE__,_COMPONENT,t) @@ -543,26 +550,29 @@ acpi_status acpi_ut_initialize_buffer(struct acpi_buffer *buffer, acpi_size required_length); -void *acpi_ut_allocate(acpi_size size, u32 component, char *module, u32 line); +void *acpi_ut_allocate(acpi_size size, + u32 component, const char *module, u32 line); void *acpi_ut_allocate_zeroed(acpi_size size, - u32 component, char *module, u32 line); + u32 component, const char *module, u32 line); #ifdef ACPI_DBG_TRACK_ALLOCATIONS void *acpi_ut_allocate_and_track(acpi_size size, - u32 component, char *module, u32 line); + u32 component, const char *module, u32 line); void *acpi_ut_allocate_zeroed_and_track(acpi_size size, - u32 component, char *module, u32 line); + u32 component, + const char *module, u32 line); void -acpi_ut_free_and_track(void *address, u32 component, char *module, u32 line); +acpi_ut_free_and_track(void *address, + u32 component, const char *module, u32 line); #ifdef ACPI_FUTURE_USAGE void acpi_ut_dump_allocation_info(void); #endif /* ACPI_FUTURE_USAGE */ -void acpi_ut_dump_allocations(u32 component, char *module); +void acpi_ut_dump_allocations(u32 component, const char *module); acpi_status acpi_ut_create_list(char *list_name, -- cgit v1.2.3 From b25d2a470bc9ffef4c34248952d914bd6fc0fcf6 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 14:15:05 +0800 Subject: ACPICA: Update version to 20080514 Update version to 20080514 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- include/acpi/acconfig.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/acpi/acconfig.h b/include/acpi/acconfig.h index 28fe8bae1037..f81ba6041d34 100644 --- a/include/acpi/acconfig.h +++ b/include/acpi/acconfig.h @@ -63,7 +63,7 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20080321 +#define ACPI_CA_VERSION 0x20080514 /* * OS name, used for the _OS object. The _OS object is essentially obsolete, -- cgit v1.2.3 From 19d0cfe9ddfdf7afa8d1765ab0bd2a7dd30e47c9 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 15:54:40 +0800 Subject: ACPICA: Update DMAR and SRAT table definitions Synchronized tables with current specifications. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- arch/x86/mm/srat_32.c | 3 +-- drivers/acpi/numa.c | 4 ++-- include/acpi/actbl1.h | 19 +++++++++++++++++-- 3 files changed, 20 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/arch/x86/mm/srat_32.c b/arch/x86/mm/srat_32.c index f41d67f8f831..1eb2973a301c 100644 --- a/arch/x86/mm/srat_32.c +++ b/arch/x86/mm/srat_32.c @@ -156,10 +156,9 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *memory_affinity) num_memory_chunks++; - printk(KERN_DEBUG "Memory range %08lx to %08lx (type %x)" + printk(KERN_DEBUG "Memory range %08lx to %08lx" " in proximity domain %02x %s\n", start_pfn, end_pfn, - memory_affinity->memory_type, pxm, ((memory_affinity->flags & ACPI_SRAT_MEM_HOT_PLUGGABLE) ? "enabled and removable" : "enabled" ) ); diff --git a/drivers/acpi/numa.c b/drivers/acpi/numa.c index 658e5f3abae0..cb9864e39bae 100644 --- a/drivers/acpi/numa.c +++ b/drivers/acpi/numa.c @@ -120,10 +120,10 @@ acpi_table_print_srat_entry(struct acpi_subtable_header *header) struct acpi_srat_mem_affinity *p = (struct acpi_srat_mem_affinity *)header; ACPI_DEBUG_PRINT((ACPI_DB_INFO, - "SRAT Memory (0x%lx length 0x%lx type 0x%x) in proximity domain %d %s%s\n", + "SRAT Memory (0x%lx length 0x%lx) in proximity domain %d %s%s\n", (unsigned long)p->base_address, (unsigned long)p->length, - p->memory_type, p->proximity_domain, + p->proximity_domain, (p->flags & ACPI_SRAT_MEM_ENABLED)? "enabled" : "disabled", (p->flags & ACPI_SRAT_MEM_HOT_PLUGGABLE)? diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 9af239bd1153..dfb0fb577d97 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -300,6 +300,7 @@ struct acpi_table_dbgp { /******************************************************************************* * * DMAR - DMA Remapping table + * From "Intel Virtualization Technology for Directed I/O", Sept. 2007 * ******************************************************************************/ @@ -382,6 +383,20 @@ struct acpi_dmar_reserved_memory { #define ACPI_DMAR_ALLOW_ALL (1) + +/* 2: Root Port ATS Capability Reporting Structure */ + +struct acpi_dmar_atsr { + struct acpi_dmar_header header; + u8 flags; + u8 reserved; + u16 segment; +}; + +/* Flags */ + +#define ACPI_DMAR_ALL_PORTS (1) + /******************************************************************************* * * ECDT - Embedded Controller Boot Resources Table @@ -1156,9 +1171,9 @@ struct acpi_srat_mem_affinity { u16 reserved; /* Reserved, must be zero */ u64 base_address; u64 length; - u32 memory_type; /* See acpi_address_range_id */ + u32 reserved1; u32 flags; - u64 reserved1; /* Reserved, must be zero */ + u64 reserved2; /* Reserved, must be zero */ }; /* Flags */ -- cgit v1.2.3 From 75e5b5fb778646a93d98adb1ca697435362d2856 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 14:19:32 +0800 Subject: ACPICA: Update disassembler for DMAR table changes Now supports the 2007 intel Virtualization Technology for Directed I/O specification. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- include/acpi/acdisasm.h | 1 + include/acpi/actbl1.h | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/acpi/acdisasm.h b/include/acpi/acdisasm.h index 788f88782012..f53faca8ec80 100644 --- a/include/acpi/acdisasm.h +++ b/include/acpi/acdisasm.h @@ -162,6 +162,7 @@ extern struct acpi_dmtable_info acpi_dm_table_info_dmar_hdr[]; extern struct acpi_dmtable_info acpi_dm_table_info_dmar_scope[]; extern struct acpi_dmtable_info acpi_dm_table_info_dmar0[]; extern struct acpi_dmtable_info acpi_dm_table_info_dmar1[]; +extern struct acpi_dmtable_info acpi_dm_table_info_dmar2[]; extern struct acpi_dmtable_info acpi_dm_table_info_ecdt[]; extern struct acpi_dmtable_info acpi_dm_table_info_einj[]; extern struct acpi_dmtable_info acpi_dm_table_info_einj0[]; diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index dfb0fb577d97..d38f9be2f6ee 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -311,6 +311,10 @@ struct acpi_table_dmar { u8 reserved[10]; }; +/* Flags */ + +#define ACPI_DMAR_INTR_REMAP (1) + /* DMAR subtable header */ struct acpi_dmar_header { -- cgit v1.2.3 From 71d993e115706a4108bdc7e3cb3cf25309f17aa6 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 14:25:05 +0800 Subject: ACPICA: Cleanup debug operand dump mechanism Eliminated unnecessary operands; eliminated use of negative index in loop. Operands now displayed in correct order, not backwards. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- drivers/acpi/dispatcher/dsopcode.c | 20 ++--------- drivers/acpi/dispatcher/dswexec.c | 8 ----- drivers/acpi/executer/exdump.c | 68 +++++++++++++++----------------------- drivers/acpi/executer/exresop.c | 4 +++ drivers/acpi/executer/exstore.c | 6 ---- drivers/acpi/namespace/nsdump.c | 4 +-- include/acpi/acinterp.h | 6 +--- include/acpi/acmacros.h | 4 +-- 8 files changed, 37 insertions(+), 83 deletions(-) (limited to 'include') diff --git a/drivers/acpi/dispatcher/dsopcode.c b/drivers/acpi/dispatcher/dsopcode.c index ac0bfb1b16fe..6a81c4400edf 100644 --- a/drivers/acpi/dispatcher/dsopcode.c +++ b/drivers/acpi/dispatcher/dsopcode.c @@ -691,12 +691,6 @@ acpi_ds_eval_buffer_field_operands(struct acpi_walk_state *walk_state, status = acpi_ex_resolve_operands(op->common.aml_opcode, ACPI_WALK_OPERANDS, walk_state); - - ACPI_DUMP_OPERANDS(ACPI_WALK_OPERANDS, ACPI_IMODE_EXECUTE, - acpi_ps_get_opcode_name(op->common.aml_opcode), - walk_state->num_operands, - "after AcpiExResolveOperands"); - if (ACPI_FAILURE(status)) { ACPI_ERROR((AE_INFO, "(%s) bad operand(s) (%X)", acpi_ps_get_opcode_name(op->common.aml_opcode), @@ -785,10 +779,6 @@ acpi_ds_eval_region_operands(struct acpi_walk_state *walk_state, return_ACPI_STATUS(status); } - ACPI_DUMP_OPERANDS(ACPI_WALK_OPERANDS, ACPI_IMODE_EXECUTE, - acpi_ps_get_opcode_name(op->common.aml_opcode), - 1, "after AcpiExResolveOperands"); - obj_desc = acpi_ns_get_attached_object(node); if (!obj_desc) { return_ACPI_STATUS(AE_NOT_EXIST); @@ -882,10 +872,6 @@ acpi_ds_eval_table_region_operands(struct acpi_walk_state *walk_state, return_ACPI_STATUS(status); } - ACPI_DUMP_OPERANDS(ACPI_WALK_OPERANDS, ACPI_IMODE_EXECUTE, - acpi_ps_get_opcode_name(op->common.aml_opcode), - 1, "after AcpiExResolveOperands"); - operand = &walk_state->operands[0]; /* Find the ACPI table */ @@ -1091,10 +1077,8 @@ acpi_ds_eval_bank_field_operands(struct acpi_walk_state *walk_state, return_ACPI_STATUS(status); } - ACPI_DUMP_OPERANDS(ACPI_WALK_OPERANDS, ACPI_IMODE_EXECUTE, - acpi_ps_get_opcode_name(op->common.aml_opcode), - 1, "after AcpiExResolveOperands"); - + ACPI_DUMP_OPERANDS(ACPI_WALK_OPERANDS, + acpi_ps_get_opcode_name(op->common.aml_opcode), 1); /* * Get the bank_value operand and save it * (at Top of stack) diff --git a/drivers/acpi/dispatcher/dswexec.c b/drivers/acpi/dispatcher/dswexec.c index b246b9657ead..b5072fa9c920 100644 --- a/drivers/acpi/dispatcher/dswexec.c +++ b/drivers/acpi/dispatcher/dswexec.c @@ -408,14 +408,6 @@ acpi_status acpi_ds_exec_end_op(struct acpi_walk_state *walk_state) [walk_state-> num_operands - 1]), walk_state); - if (ACPI_SUCCESS(status)) { - ACPI_DUMP_OPERANDS(ACPI_WALK_OPERANDS, - ACPI_IMODE_EXECUTE, - acpi_ps_get_opcode_name - (walk_state->opcode), - walk_state->num_operands, - "after ExResolveOperands"); - } } if (ACPI_SUCCESS(status)) { diff --git a/drivers/acpi/executer/exdump.c b/drivers/acpi/executer/exdump.c index f337c3f73e0c..2be2e2bf95bf 100644 --- a/drivers/acpi/executer/exdump.c +++ b/drivers/acpi/executer/exdump.c @@ -580,25 +580,22 @@ void acpi_ex_dump_operand(union acpi_operand_object *obj_desc, u32 depth) case ACPI_TYPE_BUFFER: - acpi_os_printf("Buffer len %X @ %p\n", + acpi_os_printf("Buffer length %.2X @ %p\n", obj_desc->buffer.length, obj_desc->buffer.pointer); - length = obj_desc->buffer.length; - if (length > 64) { - length = 64; - } - /* Debug only -- dump the buffer contents */ if (obj_desc->buffer.pointer) { - acpi_os_printf("Buffer Contents: "); - - for (index = 0; index < length; index++) { - acpi_os_printf(" %02x", - obj_desc->buffer.pointer[index]); + length = obj_desc->buffer.length; + if (length > 128) { + length = 128; } - acpi_os_printf("\n"); + + acpi_os_printf + ("Buffer Contents: (displaying length 0x%.2X)\n", + length); + ACPI_DUMP_BUFFER(obj_desc->buffer.pointer, length); } break; @@ -756,55 +753,42 @@ void acpi_ex_dump_operand(union acpi_operand_object *obj_desc, u32 depth) * * FUNCTION: acpi_ex_dump_operands * - * PARAMETERS: Operands - Operand list - * interpreter_mode - Load or Exec - * Ident - Identification - * num_levels - # of stack entries to dump above line - * Note - Output notation - * module_name - Caller's module name - * line_number - Caller's invocation line number + * PARAMETERS: Operands - A list of Operand objects + * opcode_name - AML opcode name + * num_operands - Operand count for this opcode * - * DESCRIPTION: Dump the object stack + * DESCRIPTION: Dump the operands associated with the opcode * ******************************************************************************/ void acpi_ex_dump_operands(union acpi_operand_object **operands, - acpi_interpreter_mode interpreter_mode, - const char *ident, - u32 num_levels, - const char *note, - const char *module_name, u32 line_number) + const char *opcode_name, u32 num_operands) { - s32 i; - ACPI_FUNCTION_NAME(ex_dump_operands); - if (!ident) { - ident = "?"; - } - - if (!note) { - note = "?"; + if (!opcode_name) { + opcode_name = "UNKNOWN"; } ACPI_DEBUG_PRINT((ACPI_DB_EXEC, - "************* Operand Stack Contents (Opcode [%s], %d Operands)\n", - ident, num_levels)); + "**** Start operand dump for opcode [%s], %d operands\n", + opcode_name, num_operands)); - if (num_levels == 0) { - num_levels = 1; + if (num_operands == 0) { + num_operands = 1; } - /* Dump the operand stack starting at the top */ + /* Dump the individual operands */ - for (i = 0; num_levels > 0; i--, num_levels--) { - acpi_ex_dump_operand(operands[i], 0); + while (num_operands) { + acpi_ex_dump_operand(*operands, 0); + operands++; + num_operands--; } ACPI_DEBUG_PRINT((ACPI_DB_EXEC, - "************* Operand Stack dump from %s(%d), %s\n", - module_name, line_number, note)); + "**** End operand dump for [%s]\n", opcode_name)); return; } diff --git a/drivers/acpi/executer/exresop.c b/drivers/acpi/executer/exresop.c index 73e29e566a70..54085f16ec28 100644 --- a/drivers/acpi/executer/exresop.c +++ b/drivers/acpi/executer/exresop.c @@ -698,5 +698,9 @@ acpi_ex_resolve_operands(u16 opcode, } } + ACPI_DUMP_OPERANDS(walk_state->operands, + acpi_ps_get_opcode_name(opcode), + walk_state->num_operands); + return_ACPI_STATUS(status); } diff --git a/drivers/acpi/executer/exstore.c b/drivers/acpi/executer/exstore.c index 76c875bc3154..38b55e352495 100644 --- a/drivers/acpi/executer/exstore.c +++ b/drivers/acpi/executer/exstore.c @@ -343,12 +343,6 @@ acpi_ex_store(union acpi_operand_object *source_desc, acpi_ut_get_object_type_name(dest_desc), dest_desc)); - ACPI_DUMP_STACK_ENTRY(source_desc); - ACPI_DUMP_STACK_ENTRY(dest_desc); - ACPI_DUMP_OPERANDS(&dest_desc, ACPI_IMODE_EXECUTE, "ExStore", - 2, - "Target is not a Reference or Constant object"); - return_ACPI_STATUS(AE_AML_OPERAND_TYPE); } diff --git a/drivers/acpi/namespace/nsdump.c b/drivers/acpi/namespace/nsdump.c index 904f9510c0e2..0ab22004728a 100644 --- a/drivers/acpi/namespace/nsdump.c +++ b/drivers/acpi/namespace/nsdump.c @@ -515,12 +515,12 @@ acpi_ns_dump_one_object(acpi_handle obj_handle, if (obj_type > ACPI_TYPE_LOCAL_MAX) { acpi_os_printf - ("(Ptr to ACPI Object type %X [UNKNOWN])\n", + ("(Pointer to ACPI Object type %.2X [UNKNOWN])\n", obj_type); bytes_to_dump = 32; } else { acpi_os_printf - ("(Ptr to ACPI Object type %X [%s])\n", + ("(Pointer to ACPI Object type %.2X [%s])\n", obj_type, acpi_ut_get_type_name(obj_type)); bytes_to_dump = sizeof(union acpi_operand_object); diff --git a/include/acpi/acinterp.h b/include/acpi/acinterp.h index accd1208dfe3..e8db7a3143a5 100644 --- a/include/acpi/acinterp.h +++ b/include/acpi/acinterp.h @@ -366,11 +366,7 @@ void acpi_ex_dump_operand(union acpi_operand_object *obj_desc, u32 depth); void acpi_ex_dump_operands(union acpi_operand_object **operands, - acpi_interpreter_mode interpreter_mode, - const char *ident, - u32 num_levels, - const char *note, - const char *module_name, u32 line_number); + const char *opcode_name, u32 num_opcodes); #ifdef ACPI_FUTURE_USAGE void diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h index 77439df4632b..57ab9e9d7593 100644 --- a/include/acpi/acmacros.h +++ b/include/acpi/acmacros.h @@ -597,7 +597,7 @@ struct acpi_integer_overlay { /* Stack and buffer dumping */ #define ACPI_DUMP_STACK_ENTRY(a) acpi_ex_dump_operand((a),0) -#define ACPI_DUMP_OPERANDS(a,b,c,d,e) acpi_ex_dump_operands(a,b,c,d,e,_acpi_module_name,__LINE__) +#define ACPI_DUMP_OPERANDS(a,b,c) acpi_ex_dump_operands(a,b,c) #define ACPI_DUMP_ENTRY(a,b) acpi_ns_dump_entry (a,b) #define ACPI_DUMP_PATHNAME(a,b,c,d) acpi_ns_dump_pathname(a,b,c,d) @@ -633,7 +633,7 @@ struct acpi_integer_overlay { #define ACPI_FUNCTION_VALUE_EXIT(s) do { } while(0) #define ACPI_FUNCTION_ENTRY() do { } while(0) #define ACPI_DUMP_STACK_ENTRY(a) do { } while(0) -#define ACPI_DUMP_OPERANDS(a,b,c,d,e) do { } while(0) +#define ACPI_DUMP_OPERANDS(a,b,c) do { } while(0) #define ACPI_DUMP_ENTRY(a,b) do { } while(0) #define ACPI_DUMP_TABLES(a,b) do { } while(0) #define ACPI_DUMP_PATHNAME(a,b,c,d) do { } while(0) -- cgit v1.2.3 From 9c9f6d052dc6f469431461a97d49cf9c5558b8ad Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 10 Jun 2008 14:37:53 +0800 Subject: ACPICA: Update version to 20080609 Update version to 20080609. Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- include/acpi/acconfig.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/acpi/acconfig.h b/include/acpi/acconfig.h index f81ba6041d34..4eb75a88795a 100644 --- a/include/acpi/acconfig.h +++ b/include/acpi/acconfig.h @@ -63,7 +63,7 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20080514 +#define ACPI_CA_VERSION 0x20080609 /* * OS name, used for the _OS object. The _OS object is essentially obsolete, -- cgit v1.2.3 From 71b58cbb0c30d1f78636a48c4721529449d6ea37 Mon Sep 17 00:00:00 2001 From: Zhang Rui Date: Fri, 20 Jun 2008 09:42:47 +0800 Subject: ACPI: Enhance /sys/firmware/interrupts to allow enable/disable/clear from user-space Allow users to enable/disable/clear a specific & valid GPE/Fixed Event in user space. This is useful for debugging, especially for some interrupt storm issues. All wakeup GPEs are disabled and they can not be enabled at runtime, and we mark them as invalid. All GPEs that don't have a _Lxx/_Exx method are marked as invalid. All Fixed Events that don't have an event handler are marked as invalid and they can't be enabled until an event handler is registered. Signed-off-by: Zhang Rui Signed-off-by: Ling Ming Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- Documentation/ABI/testing/sysfs-firmware-acpi | 127 +++++++++++++------ drivers/acpi/events/evxfevnt.c | 18 ++- drivers/acpi/hardware/hwgpe.c | 2 - drivers/acpi/system.c | 169 ++++++++++++++++++++++++-- include/acpi/achware.h | 2 - include/acpi/acpixf.h | 4 - 6 files changed, 258 insertions(+), 64 deletions(-) (limited to 'include') diff --git a/Documentation/ABI/testing/sysfs-firmware-acpi b/Documentation/ABI/testing/sysfs-firmware-acpi index 9470ed9afcc0..f27be7d1a49f 100644 --- a/Documentation/ABI/testing/sysfs-firmware-acpi +++ b/Documentation/ABI/testing/sysfs-firmware-acpi @@ -29,46 +29,46 @@ Description: $ cd /sys/firmware/acpi/interrupts $ grep . * - error:0 - ff_gbl_lock:0 - ff_pmtimer:0 - ff_pwr_btn:0 - ff_rt_clk:0 - ff_slp_btn:0 - gpe00:0 - gpe01:0 - gpe02:0 - gpe03:0 - gpe04:0 - gpe05:0 - gpe06:0 - gpe07:0 - gpe08:0 - gpe09:174 - gpe0A:0 - gpe0B:0 - gpe0C:0 - gpe0D:0 - gpe0E:0 - gpe0F:0 - gpe10:0 - gpe11:60 - gpe12:0 - gpe13:0 - gpe14:0 - gpe15:0 - gpe16:0 - gpe17:0 - gpe18:0 - gpe19:7 - gpe1A:0 - gpe1B:0 - gpe1C:0 - gpe1D:0 - gpe1E:0 - gpe1F:0 - gpe_all:241 - sci:241 + error: 0 + ff_gbl_lock: 0 enable + ff_pmtimer: 0 invalid + ff_pwr_btn: 0 enable + ff_rt_clk: 2 disable + ff_slp_btn: 0 invalid + gpe00: 0 invalid + gpe01: 0 enable + gpe02: 108 enable + gpe03: 0 invalid + gpe04: 0 invalid + gpe05: 0 invalid + gpe06: 0 enable + gpe07: 0 enable + gpe08: 0 invalid + gpe09: 0 invalid + gpe0A: 0 invalid + gpe0B: 0 invalid + gpe0C: 0 invalid + gpe0D: 0 invalid + gpe0E: 0 invalid + gpe0F: 0 invalid + gpe10: 0 invalid + gpe11: 0 invalid + gpe12: 0 invalid + gpe13: 0 invalid + gpe14: 0 invalid + gpe15: 0 invalid + gpe16: 0 invalid + gpe17: 1084 enable + gpe18: 0 enable + gpe19: 0 invalid + gpe1A: 0 invalid + gpe1B: 0 invalid + gpe1C: 0 invalid + gpe1D: 0 invalid + gpe1E: 0 invalid + gpe1F: 0 invalid + gpe_all: 1192 + sci: 1194 sci - The total number of times the ACPI SCI has claimed an interrupt. @@ -89,6 +89,13 @@ Description: error - an interrupt that can't be accounted for above. + invalid: it's either a wakeup GPE or a GPE/Fixed Event that + doesn't have an event handler. + + disable: the GPE/Fixed Event is valid but disabled. + + enable: the GPE/Fixed Event is valid and enabled. + Root has permission to clear any of these counters. Eg. # echo 0 > gpe11 @@ -97,3 +104,43 @@ Description: None of these counters has an effect on the function of the system, they are simply statistics. + + Besides this, user can also write specific strings to these files + to enable/disable/clear ACPI interrupts in user space, which can be + used to debug some ACPI interrupt storm issues. + + Note that only writting to VALID GPE/Fixed Event is allowed, + i.e. user can only change the status of runtime GPE and + Fixed Event with event handler installed. + + Let's take power button fixed event for example, please kill acpid + and other user space applications so that the machine won't shutdown + when pressing the power button. + # cat ff_pwr_btn + 0 + # press the power button for 3 times; + # cat ff_pwr_btn + 3 + # echo disable > ff_pwr_btn + # cat ff_pwr_btn + disable + # press the power button for 3 times; + # cat ff_pwr_btn + disable + # echo enable > ff_pwr_btn + # cat ff_pwr_btn + 4 + /* + * this is because the status bit is set even if the enable bit is cleared, + * and it triggers an ACPI fixed event when the enable bit is set again + */ + # press the power button for 3 times; + # cat ff_pwr_btn + 7 + # echo disable > ff_pwr_btn + # press the power button for 3 times; + # echo clear > ff_pwr_btn /* clear the status bit */ + # echo disable > ff_pwr_btn + # cat ff_pwr_btn + 7 + diff --git a/drivers/acpi/events/evxfevnt.c b/drivers/acpi/events/evxfevnt.c index 99a7502e6a87..73bfd6bf962f 100644 --- a/drivers/acpi/events/evxfevnt.c +++ b/drivers/acpi/events/evxfevnt.c @@ -472,7 +472,6 @@ acpi_status acpi_clear_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags) } ACPI_EXPORT_SYMBOL(acpi_clear_gpe) -#ifdef ACPI_FUTURE_USAGE /******************************************************************************* * * FUNCTION: acpi_get_event_status @@ -489,6 +488,7 @@ ACPI_EXPORT_SYMBOL(acpi_clear_gpe) acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status) { acpi_status status = AE_OK; + u32 value; ACPI_FUNCTION_TRACE(acpi_get_event_status); @@ -506,7 +506,20 @@ acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status) status = acpi_get_register(acpi_gbl_fixed_event_info[event]. - status_register_id, event_status); + enable_register_id, &value); + if (ACPI_FAILURE(status)) + return_ACPI_STATUS(status); + + *event_status = value; + + status = + acpi_get_register(acpi_gbl_fixed_event_info[event]. + status_register_id, &value); + if (ACPI_FAILURE(status)) + return_ACPI_STATUS(status); + + if (value) + *event_status |= ACPI_EVENT_FLAG_SET; return_ACPI_STATUS(status); } @@ -566,7 +579,6 @@ acpi_get_gpe_status(acpi_handle gpe_device, } ACPI_EXPORT_SYMBOL(acpi_get_gpe_status) -#endif /* ACPI_FUTURE_USAGE */ /******************************************************************************* * * FUNCTION: acpi_install_gpe_block diff --git a/drivers/acpi/hardware/hwgpe.c b/drivers/acpi/hardware/hwgpe.c index 58347d6c43f8..0b80db9d9197 100644 --- a/drivers/acpi/hardware/hwgpe.c +++ b/drivers/acpi/hardware/hwgpe.c @@ -186,7 +186,6 @@ acpi_status acpi_hw_clear_gpe(struct acpi_gpe_event_info * gpe_event_info) * ******************************************************************************/ -#ifdef ACPI_FUTURE_USAGE acpi_status acpi_hw_get_gpe_status(struct acpi_gpe_event_info * gpe_event_info, acpi_event_status * event_status) @@ -246,7 +245,6 @@ acpi_hw_get_gpe_status(struct acpi_gpe_event_info * gpe_event_info, unlock_and_exit: return (status); } -#endif /* ACPI_FUTURE_USAGE */ /****************************************************************************** * diff --git a/drivers/acpi/system.c b/drivers/acpi/system.c index 5bd2dec9a7ac..d8e3f153b295 100644 --- a/drivers/acpi/system.c +++ b/drivers/acpi/system.c @@ -167,7 +167,13 @@ static int acpi_system_sysfs_init(void) #define COUNT_ERROR 2 /* other */ #define NUM_COUNTERS_EXTRA 3 -static u32 *all_counters; +#define ACPI_EVENT_VALID 0x01 +struct event_counter { + u32 count; + u32 flags; +}; + +static struct event_counter *all_counters; static u32 num_gpes; static u32 num_counters; static struct attribute **all_attrs; @@ -202,9 +208,44 @@ static int count_num_gpes(void) return count; } +static int get_gpe_device(int index, acpi_handle *handle) +{ + struct acpi_gpe_xrupt_info *gpe_xrupt_info; + struct acpi_gpe_block_info *gpe_block; + acpi_cpu_flags flags; + struct acpi_namespace_node *node; + + flags = acpi_os_acquire_lock(acpi_gbl_gpe_lock); + + gpe_xrupt_info = acpi_gbl_gpe_xrupt_list_head; + while (gpe_xrupt_info) { + gpe_block = gpe_xrupt_info->gpe_block_list_head; + node = gpe_block->node; + while (gpe_block) { + index -= gpe_block->register_count * + ACPI_GPE_REGISTER_WIDTH; + if (index < 0) { + acpi_os_release_lock(acpi_gbl_gpe_lock, flags); + /* return NULL if it's FADT GPE */ + if (node->type != ACPI_TYPE_DEVICE) + *handle = NULL; + else + *handle = node; + return 0; + } + node = gpe_block->node; + gpe_block = gpe_block->next; + } + gpe_xrupt_info = gpe_xrupt_info->next; + } + acpi_os_release_lock(acpi_gbl_gpe_lock, flags); + + return -ENODEV; +} + static void delete_gpe_attr_array(void) { - u32 *tmp = all_counters; + struct event_counter *tmp = all_counters; all_counters = NULL; kfree(tmp); @@ -230,9 +271,10 @@ void acpi_os_gpe_count(u32 gpe_number) return; if (gpe_number < num_gpes) - all_counters[gpe_number]++; + all_counters[gpe_number].count++; else - all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS + COUNT_ERROR]++; + all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS + COUNT_ERROR]. + count++; return; } @@ -243,44 +285,144 @@ void acpi_os_fixed_event_count(u32 event_number) return; if (event_number < ACPI_NUM_FIXED_EVENTS) - all_counters[num_gpes + event_number]++; + all_counters[num_gpes + event_number].count++; else - all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS + COUNT_ERROR]++; + all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS + COUNT_ERROR]. + count++; return; } +static int get_status(u32 index, acpi_event_status *status, acpi_handle *handle) +{ + int result = 0; + + if (index >= num_gpes + ACPI_NUM_FIXED_EVENTS) + goto end; + + if (index < num_gpes) { + result = get_gpe_device(index, handle); + if (result) { + ACPI_EXCEPTION((AE_INFO, AE_NOT_FOUND, + "Invalid GPE 0x%x\n", index)); + goto end; + } + result = acpi_get_gpe_status(*handle, index, + ACPI_NOT_ISR, status); + } else if (index < (num_gpes + ACPI_NUM_FIXED_EVENTS)) + result = acpi_get_event_status(index - num_gpes, status); + + /* + * sleep/power button GPE/Fixed Event is enabled after acpi_system_init, + * check the status at runtime and mark it as valid once it's enabled + */ + if (!result && (*status & ACPI_EVENT_FLAG_ENABLED)) + all_counters[index].flags |= ACPI_EVENT_VALID; +end: + return result; +} + static ssize_t counter_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { - all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS + COUNT_SCI] = + int index = attr - counter_attrs; + int size; + acpi_handle handle; + acpi_event_status status; + int result = 0; + + all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS + COUNT_SCI].count = acpi_irq_handled; - all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS + COUNT_GPE] = + all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS + COUNT_GPE].count = acpi_gpe_count; - return sprintf(buf, "%d\n", all_counters[attr - counter_attrs]); + size = sprintf(buf, "%8d", all_counters[index].count); + + /* "gpe_all" or "sci" */ + if (index >= num_gpes + ACPI_NUM_FIXED_EVENTS) + goto end; + + result = get_status(index, &status, &handle); + if (result) + goto end; + + if (!(all_counters[index].flags & ACPI_EVENT_VALID)) + size += sprintf(buf + size, " invalid"); + else if (status & ACPI_EVENT_FLAG_ENABLED) + size += sprintf(buf + size, " enable"); + else + size += sprintf(buf + size, " disable"); + +end: + size += sprintf(buf + size, "\n"); + return result ? result : size; } /* * counter_set() sets the specified counter. * setting the total "sci" file to any value clears all counters. + * enable/disable/clear a gpe/fixed event in user space. */ static ssize_t counter_set(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t size) { int index = attr - counter_attrs; + acpi_event_status status; + acpi_handle handle; + int result = 0; if (index == num_gpes + ACPI_NUM_FIXED_EVENTS + COUNT_SCI) { int i; for (i = 0; i < num_counters; ++i) - all_counters[i] = 0; + all_counters[i].count = 0; acpi_gpe_count = 0; acpi_irq_handled = 0; + goto end; + } + /* show the event status for both GPEs and Fixed Events */ + result = get_status(index, &status, &handle); + if (result) + goto end; + + if (!(all_counters[index].flags & ACPI_EVENT_VALID)) { + ACPI_DEBUG_PRINT((ACPI_DB_WARN, + "Can not change Invalid GPE/Fixed Event status\n")); + return -EINVAL; + } + + if (index < num_gpes) { + if (!strcmp(buf, "disable\n") && + (status & ACPI_EVENT_FLAG_ENABLED)) + result = acpi_disable_gpe(handle, index, ACPI_NOT_ISR); + else if (!strcmp(buf, "enable\n") && + !(status & ACPI_EVENT_FLAG_ENABLED)) + result = acpi_enable_gpe(handle, index, ACPI_NOT_ISR); + else if (!strcmp(buf, "clear\n") && + (status & ACPI_EVENT_FLAG_SET)) + result = acpi_clear_gpe(handle, index, ACPI_NOT_ISR); + else + all_counters[index].count = strtoul(buf, NULL, 0); + } else if (index < num_gpes + ACPI_NUM_FIXED_EVENTS) { + int event = index - num_gpes; + if (!strcmp(buf, "disable\n") && + (status & ACPI_EVENT_FLAG_ENABLED)) + result = acpi_disable_event(event, ACPI_NOT_ISR); + else if (!strcmp(buf, "enable\n") && + !(status & ACPI_EVENT_FLAG_ENABLED)) + result = acpi_enable_event(event, ACPI_NOT_ISR); + else if (!strcmp(buf, "clear\n") && + (status & ACPI_EVENT_FLAG_SET)) + result = acpi_clear_event(event); + else + all_counters[index].count = strtoul(buf, NULL, 0); } else - all_counters[index] = strtoul(buf, NULL, 0); + all_counters[index].count = strtoul(buf, NULL, 0); - return size; + if (ACPI_FAILURE(result)) + result = -EINVAL; +end: + return result ? result : size; } void acpi_irq_stats_init(void) @@ -298,7 +440,8 @@ void acpi_irq_stats_init(void) if (all_attrs == NULL) return; - all_counters = kzalloc(sizeof(u32) * (num_counters), GFP_KERNEL); + all_counters = kzalloc(sizeof(struct event_counter) * (num_counters), + GFP_KERNEL); if (all_counters == NULL) goto fail; diff --git a/include/acpi/achware.h b/include/acpi/achware.h index 45e985961f4c..97a72b193276 100644 --- a/include/acpi/achware.h +++ b/include/acpi/achware.h @@ -102,11 +102,9 @@ acpi_status acpi_hw_clear_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info, struct acpi_gpe_block_info *gpe_block); -#ifdef ACPI_FUTURE_USAGE acpi_status acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info, acpi_event_status * event_status); -#endif /* ACPI_FUTURE_USAGE */ acpi_status acpi_hw_disable_all_gpes(void); diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index bd95ecc6e0fa..94d94e126e9f 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -248,9 +248,7 @@ acpi_status acpi_disable_event(u32 event, u32 flags); acpi_status acpi_clear_event(u32 event); -#ifdef ACPI_FUTURE_USAGE acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status); -#endif /* ACPI_FUTURE_USAGE */ acpi_status acpi_set_gpe_type(acpi_handle gpe_device, u32 gpe_number, u8 type); @@ -260,12 +258,10 @@ acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags); acpi_status acpi_clear_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags); -#ifdef ACPI_FUTURE_USAGE acpi_status acpi_get_gpe_status(acpi_handle gpe_device, u32 gpe_number, u32 flags, acpi_event_status * event_status); -#endif /* ACPI_FUTURE_USAGE */ acpi_status acpi_install_gpe_block(acpi_handle gpe_device, -- cgit v1.2.3 From c1e3b377ad48febba6f91b8ae42c44ee4d4ab45e Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Tue, 24 Jun 2008 17:58:53 +0800 Subject: ACPI: Create "idle=halt" bootparam "idle=halt" limits the idle loop to using the halt instruction. No MWAIT, no IO accesses, no C-states deeper than C1. If something is broken in the idle code, "idle=halt" is a less severe workaround than "idle=poll" which disables all power savings. Signed-off-by: Zhao Yakui Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- Documentation/kernel-parameters.txt | 4 +++- arch/ia64/kernel/process.c | 2 ++ arch/x86/kernel/process.c | 17 ++++++++++++++++- drivers/acpi/processor_idle.c | 22 ++++++++++++++++++++++ include/asm-ia64/processor.h | 1 + include/asm-x86/processor.h | 1 + 6 files changed, 45 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 312fe77764a4..65db7f4711aa 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -818,7 +818,7 @@ and is between 256 and 4096 characters. It is defined in the file See Documentation/ide/ide.txt. idle= [X86] - Format: idle=poll or idle=mwait + Format: idle=poll or idle=mwait, idle=halt Poll forces a polling idle loop that can slightly improves the performance of waking up a idle CPU, but will use a lot of power and make the system run hot. Not recommended. @@ -826,6 +826,8 @@ and is between 256 and 4096 characters. It is defined in the file to not use it because it doesn't save as much power as a normal idle loop use the MONITOR/MWAIT idle loop anyways. Performance should be the same as idle=poll. + idle=halt. Halt is forced to be used for CPU idle. + In such case C2/C3 won't be used again. ide-pci-generic.all-generic-ide [HW] (E)IDE subsystem Claim all unknown PCI IDE storage controllers. diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c index fabaf08d9a69..612b3c4a0603 100644 --- a/arch/ia64/kernel/process.c +++ b/arch/ia64/kernel/process.c @@ -55,6 +55,8 @@ void (*ia64_mark_idle)(int); unsigned long boot_option_idle_override = 0; EXPORT_SYMBOL(boot_option_idle_override); +unsigned long idle_halt; +EXPORT_SYMBOL(idle_halt); void ia64_do_show_stack (struct unw_frame_info *info, void *arg) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 7dceea947232..7fc729498760 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -7,6 +7,10 @@ #include #include #include +#include + +unsigned long idle_halt; +EXPORT_SYMBOL(idle_halt); struct kmem_cache *task_xstate_cachep; @@ -325,7 +329,18 @@ static int __init idle_setup(char *str) pm_idle = poll_idle; } else if (!strcmp(str, "mwait")) force_mwait = 1; - else + else if (!strcmp(str, "halt")) { + /* + * When the boot option of idle=halt is added, halt is + * forced to be used for CPU idle. In such case CPU C2/C3 + * won't be used again. + * To continue to load the CPU idle driver, don't touch + * the boot_option_idle_override. + */ + pm_idle = default_idle; + idle_halt = 1; + return 0; + } else return -1; boot_option_idle_override = 1; diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 0fc310e7dfd6..c75c7ace8c13 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -41,6 +41,7 @@ #include #include #include +#include /* * Include the apic definitions for x86 to have the APIC timer related defines @@ -57,6 +58,7 @@ #include #include +#include #define ACPI_PROCESSOR_COMPONENT 0x01000000 #define ACPI_PROCESSOR_CLASS "processor" @@ -955,6 +957,17 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) } else { continue; } + if (cx.type == ACPI_STATE_C1 && idle_halt) { + /* + * In most cases the C1 space_id obtained from + * _CST object is FIXED_HARDWARE access mode. + * But when the option of idle=halt is added, + * the entry_method type should be changed from + * CSTATE_FFH to CSTATE_HALT. + */ + cx.entry_method = ACPI_CSTATE_HALT; + snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); + } } else { snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", cx.address); @@ -1780,6 +1793,15 @@ int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, return 0; if (!first_run) { + if (idle_halt) { + /* + * When the boot option of "idle=halt" is added, halt + * is used for CPU IDLE. + * In such case C2/C3 is meaningless. So the max_cstate + * is set to one. + */ + max_cstate = 1; + } dmi_check_system(processor_power_dmi_table); max_cstate = acpi_processor_cstate_check(max_cstate); if (max_cstate < ACPI_C_STATES_MAX) diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index 6aff126fc07e..f36e28a5f61e 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -763,6 +763,7 @@ prefetchw (const void *x) #define spin_lock_prefetch(x) prefetchw(x) extern unsigned long boot_option_idle_override; +extern unsigned long idle_halt; #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h index 7f7382704592..bc221623248e 100644 --- a/include/asm-x86/processor.h +++ b/include/asm-x86/processor.h @@ -727,6 +727,7 @@ extern int force_mwait; extern void select_idle_routine(const struct cpuinfo_x86 *c); extern unsigned long boot_option_idle_override; +extern unsigned long idle_halt; extern void enable_sep_cpu(void); extern int sysenter_setup(void); -- cgit v1.2.3 From da5e09a1b3e5a9fc0b15a3feb64e921ccc55ba74 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Tue, 24 Jun 2008 18:01:09 +0800 Subject: ACPI : Create "idle=nomwait" bootparam "idle=nomwait" disables the use of the MWAIT instruction from both C1 (C1_FFH) and deeper (C2C3_FFH) C-states. When MWAIT is unavailable, the BIOS and OS generally negotiate to use the HALT instruction for C1, and use IO accesses for deeper C-states. This option is useful for power and performance comparisons, and also to work around BIOS bugs where broken MWAIT support is advertised. http://bugzilla.kernel.org/show_bug.cgi?id=10807 http://bugzilla.kernel.org/show_bug.cgi?id=10914 Signed-off-by: Zhao Yakui Signed-off-by: Li Shaohua Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- Documentation/kernel-parameters.txt | 3 ++- arch/ia64/kernel/process.c | 2 ++ arch/x86/kernel/process.c | 11 +++++++++++ drivers/acpi/processor_core.c | 13 +++++++++++++ drivers/acpi/processor_idle.c | 6 +++++- include/asm-ia64/processor.h | 1 + include/asm-x86/processor.h | 1 + 7 files changed, 35 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 65db7f4711aa..5e497d16fb51 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -818,7 +818,7 @@ and is between 256 and 4096 characters. It is defined in the file See Documentation/ide/ide.txt. idle= [X86] - Format: idle=poll or idle=mwait, idle=halt + Format: idle=poll or idle=mwait, idle=halt, idle=nomwait Poll forces a polling idle loop that can slightly improves the performance of waking up a idle CPU, but will use a lot of power and make the system run hot. Not recommended. @@ -828,6 +828,7 @@ and is between 256 and 4096 characters. It is defined in the file as idle=poll. idle=halt. Halt is forced to be used for CPU idle. In such case C2/C3 won't be used again. + idle=nomwait. Disable mwait for CPU C-states ide-pci-generic.all-generic-ide [HW] (E)IDE subsystem Claim all unknown PCI IDE storage controllers. diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c index 612b3c4a0603..3ab8373103ec 100644 --- a/arch/ia64/kernel/process.c +++ b/arch/ia64/kernel/process.c @@ -57,6 +57,8 @@ unsigned long boot_option_idle_override = 0; EXPORT_SYMBOL(boot_option_idle_override); unsigned long idle_halt; EXPORT_SYMBOL(idle_halt); +unsigned long idle_nomwait; +EXPORT_SYMBOL(idle_nomwait); void ia64_do_show_stack (struct unw_frame_info *info, void *arg) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 7fc729498760..4d629c62f4f8 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -11,6 +11,8 @@ unsigned long idle_halt; EXPORT_SYMBOL(idle_halt); +unsigned long idle_nomwait; +EXPORT_SYMBOL(idle_nomwait); struct kmem_cache *task_xstate_cachep; @@ -340,6 +342,15 @@ static int __init idle_setup(char *str) pm_idle = default_idle; idle_halt = 1; return 0; + } else if (!strcmp(str, "nomwait")) { + /* + * If the boot option of "idle=nomwait" is added, + * it means that mwait will be disabled for CPU C2/C3 + * states. In such case it won't touch the variable + * of boot_option_idle_override. + */ + idle_nomwait = 1; + return 0; } else return -1; diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 9a803f85ccfe..4e1bb89fd6c3 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -265,7 +265,20 @@ static int acpi_processor_set_pdc(struct acpi_processor *pr) if (!pdc_in) return status; + if (idle_nomwait) { + /* + * If mwait is disabled for CPU C-states, the C2C3_FFH access + * mode will be disabled in the parameter of _PDC object. + * Of course C1_FFH access mode will also be disabled. + */ + union acpi_object *obj; + u32 *buffer = NULL; + obj = pdc_in->pointer; + buffer = (u32 *)(obj->buffer.pointer); + buffer[2] &= ~(ACPI_PDC_C_C2C3_FFH | ACPI_PDC_C_C1_FFH); + + } status = acpi_evaluate_object(pr->handle, "_PDC", pdc_in, NULL); if (ACPI_FAILURE(status)) diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index c75c7ace8c13..d592dbb1d12a 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -957,13 +957,17 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) } else { continue; } - if (cx.type == ACPI_STATE_C1 && idle_halt) { + if (cx.type == ACPI_STATE_C1 && + (idle_halt || idle_nomwait)) { /* * In most cases the C1 space_id obtained from * _CST object is FIXED_HARDWARE access mode. * But when the option of idle=halt is added, * the entry_method type should be changed from * CSTATE_FFH to CSTATE_HALT. + * When the option of idle=nomwait is added, + * the C1 entry_method type should be + * CSTATE_HALT. */ cx.entry_method = ACPI_CSTATE_HALT; snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index f36e28a5f61e..f88fa054d01d 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -764,6 +764,7 @@ prefetchw (const void *x) extern unsigned long boot_option_idle_override; extern unsigned long idle_halt; +extern unsigned long idle_nomwait; #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h index bc221623248e..55402d2ab938 100644 --- a/include/asm-x86/processor.h +++ b/include/asm-x86/processor.h @@ -728,6 +728,7 @@ extern void select_idle_routine(const struct cpuinfo_x86 *c); extern unsigned long boot_option_idle_override; extern unsigned long idle_halt; +extern unsigned long idle_nomwait; extern void enable_sep_cpu(void); extern int sysenter_setup(void); -- cgit v1.2.3 From 20bfdbba7212d19613b93dcea93f26cb65af91fe Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 27 Jun 2008 16:56:56 -0600 Subject: PNP: make pnp_{port,mem,etc}_start(), et al work for invalid resources Some callers use pnp_port_start() and similar functions without making sure the resource is valid. This patch makes us fall back to returning the initial values if the resource is not valid or not even present. This mostly preserves the previous behavior, where we would just return the initial values set by pnp_init_resource_table(). The original 2.6.25 code didn't range-check the "bar", so it would return garbage if the bar exceeded the table size. This code returns sensible values instead. Signed-off-by: Bjorn Helgaas Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- include/linux/pnp.h | 72 ++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 60 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/linux/pnp.h b/include/linux/pnp.h index 63b128d512fb..8b607aecd959 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -40,19 +40,31 @@ static inline resource_size_t pnp_resource_len(struct resource *res) static inline resource_size_t pnp_port_start(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_IO, bar)->start; + struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar); + + if (pnp_resource_valid(res)) + return res->start; + return 0; } static inline resource_size_t pnp_port_end(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_IO, bar)->end; + struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar); + + if (pnp_resource_valid(res)) + return res->end; + return 0; } static inline unsigned long pnp_port_flags(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_IO, bar)->flags; + struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar); + + if (pnp_resource_valid(res)) + return res->flags; + return IORESOURCE_IO | IORESOURCE_AUTO | IORESOURCE_UNSET; } static inline int pnp_port_valid(struct pnp_dev *dev, unsigned int bar) @@ -63,25 +75,41 @@ static inline int pnp_port_valid(struct pnp_dev *dev, unsigned int bar) static inline resource_size_t pnp_port_len(struct pnp_dev *dev, unsigned int bar) { - return pnp_resource_len(pnp_get_resource(dev, IORESOURCE_IO, bar)); + struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar); + + if (pnp_resource_valid(res)) + return pnp_resource_len(res); + return 0; } static inline resource_size_t pnp_mem_start(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_MEM, bar)->start; + struct resource *res = pnp_get_resource(dev, IORESOURCE_MEM, bar); + + if (pnp_resource_valid(res)) + return res->start; + return 0; } static inline resource_size_t pnp_mem_end(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_MEM, bar)->end; + struct resource *res = pnp_get_resource(dev, IORESOURCE_MEM, bar); + + if (pnp_resource_valid(res)) + return res->end; + return 0; } static inline unsigned long pnp_mem_flags(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_MEM, bar)->flags; + struct resource *res = pnp_get_resource(dev, IORESOURCE_MEM, bar); + + if (pnp_resource_valid(res)) + return res->flags; + return IORESOURCE_MEM | IORESOURCE_AUTO | IORESOURCE_UNSET; } static inline int pnp_mem_valid(struct pnp_dev *dev, unsigned int bar) @@ -92,18 +120,30 @@ static inline int pnp_mem_valid(struct pnp_dev *dev, unsigned int bar) static inline resource_size_t pnp_mem_len(struct pnp_dev *dev, unsigned int bar) { - return pnp_resource_len(pnp_get_resource(dev, IORESOURCE_MEM, bar)); + struct resource *res = pnp_get_resource(dev, IORESOURCE_MEM, bar); + + if (pnp_resource_valid(res)) + return pnp_resource_len(res); + return 0; } static inline resource_size_t pnp_irq(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_IRQ, bar)->start; + struct resource *res = pnp_get_resource(dev, IORESOURCE_IRQ, bar); + + if (pnp_resource_valid(res)) + return res->start; + return -1; } static inline unsigned long pnp_irq_flags(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_IRQ, bar)->flags; + struct resource *res = pnp_get_resource(dev, IORESOURCE_IRQ, bar); + + if (pnp_resource_valid(res)) + return res->flags; + return IORESOURCE_IRQ | IORESOURCE_AUTO | IORESOURCE_UNSET; } static inline int pnp_irq_valid(struct pnp_dev *dev, unsigned int bar) @@ -114,12 +154,20 @@ static inline int pnp_irq_valid(struct pnp_dev *dev, unsigned int bar) static inline resource_size_t pnp_dma(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_DMA, bar)->start; + struct resource *res = pnp_get_resource(dev, IORESOURCE_DMA, bar); + + if (pnp_resource_valid(res)) + return res->start; + return -1; } static inline unsigned long pnp_dma_flags(struct pnp_dev *dev, unsigned int bar) { - return pnp_get_resource(dev, IORESOURCE_DMA, bar)->flags; + struct resource *res = pnp_get_resource(dev, IORESOURCE_DMA, bar); + + if (pnp_resource_valid(res)) + return res->flags; + return IORESOURCE_DMA | IORESOURCE_AUTO | IORESOURCE_UNSET; } static inline int pnp_dma_valid(struct pnp_dev *dev, unsigned int bar) -- cgit v1.2.3 From aee3ad815dd291a7193ab01da0f1a30c84d00061 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 27 Jun 2008 16:56:57 -0600 Subject: PNP: replace pnp_resource_table with dynamically allocated resources PNP used to have a fixed-size pnp_resource_table for tracking the resources used by a device. This table often overflowed, so we've had to increase the table size, which wastes memory because most devices have very few resources. This patch replaces the table with a linked list of resources where the entries are allocated on demand. This removes messages like these: pnpacpi: exceeded the max number of IO resources 00:01: too many I/O port resources References: http://bugzilla.kernel.org/show_bug.cgi?id=9535 http://bugzilla.kernel.org/show_bug.cgi?id=9740 http://lkml.org/lkml/2007/11/30/110 This patch also changes the way PNP uses the IORESOURCE_UNSET, IORESOURCE_AUTO, and IORESOURCE_DISABLED flags. Prior to this patch, the pnp_resource_table entries used the flags like this: IORESOURCE_UNSET This table entry is unused and available for use. When this flag is set, we shouldn't look at anything else in the resource structure. This flag is set when a resource table entry is initialized. IORESOURCE_AUTO This resource was assigned automatically by pnp_assign_{io,mem,etc}(). This flag is set when a resource table entry is initialized and cleared whenever we discover a resource setting by reading an ISAPNP config register, parsing a PNPBIOS resource data stream, parsing an ACPI _CRS list, or interpreting a sysfs "set" command. Resources marked IORESOURCE_AUTO are reinitialized and marked as IORESOURCE_UNSET by pnp_clean_resource_table() in these cases: - before we attempt to assign resources automatically, - if we fail to assign resources automatically, - after disabling a device IORESOURCE_DISABLED Set by pnp_assign_{io,mem,etc}() when automatic assignment fails. Also set by PNPBIOS and PNPACPI for: - invalid IRQs or GSI registration failures - invalid DMA channels - I/O ports above 0x10000 - mem ranges with negative length After this patch, there is no pnp_resource_table, and the resource list entries use the flags like this: IORESOURCE_UNSET This flag is no longer used in PNP. Instead of keeping IORESOURCE_UNSET entries in the resource list, we remove entries from the list and free them. IORESOURCE_AUTO No change in meaning: it still means the resource was assigned automatically by pnp_assign_{port,mem,etc}(), but these functions now set the bit explicitly. We still "clean" a device's resource list in the same places, but rather than reinitializing IORESOURCE_AUTO entries, we just remove them from the list. Note that IORESOURCE_AUTO entries are always at the end of the list, so removing them doesn't reorder other list entries. This is because non-IORESOURCE_AUTO entries are added by the ISAPNP, PNPBIOS, or PNPACPI "get resources" methods and by the sysfs "set" command. In each of these cases, we completely free the resource list first. IORESOURCE_DISABLED In addition to the cases where we used to set this flag, ISAPNP now adds an IORESOURCE_DISABLED resource when it reads a configuration register with a "disabled" value. Signed-off-by: Bjorn Helgaas Signed-off-by: Len Brown Signed-off-by: Andi Kleen --- drivers/pnp/base.h | 18 +--- drivers/pnp/core.c | 25 +++-- drivers/pnp/interface.c | 60 +++++------ drivers/pnp/isapnp/core.c | 12 +-- drivers/pnp/manager.c | 220 +++++++++++------------------------------ drivers/pnp/pnpacpi/rsparser.c | 131 ++++++++++++++++-------- drivers/pnp/pnpbios/rsparser.c | 95 +++++++++++++----- drivers/pnp/quirks.c | 3 +- drivers/pnp/resource.c | 86 ++++------------ drivers/pnp/support.c | 79 +++++++-------- drivers/pnp/system.c | 4 +- include/linux/pnp.h | 20 ++-- 12 files changed, 331 insertions(+), 422 deletions(-) (limited to 'include') diff --git a/drivers/pnp/base.h b/drivers/pnp/base.h index c91315826da2..1667ac3ca45b 100644 --- a/drivers/pnp/base.h +++ b/drivers/pnp/base.h @@ -46,27 +46,15 @@ int pnp_check_dma(struct pnp_dev *dev, struct resource *res); char *pnp_resource_type_name(struct resource *res); void dbg_pnp_show_resources(struct pnp_dev *dev, char *desc); -void pnp_init_resource(struct resource *res); +void pnp_free_resources(struct pnp_dev *dev); int pnp_resource_type(struct resource *res); -struct pnp_resource *pnp_get_pnp_resource(struct pnp_dev *dev, - unsigned int type, unsigned int num); - -#define PNP_MAX_PORT 40 -#define PNP_MAX_MEM 24 -#define PNP_MAX_IRQ 2 -#define PNP_MAX_DMA 2 - struct pnp_resource { + struct list_head list; struct resource res; }; -struct pnp_resource_table { - struct pnp_resource port[PNP_MAX_PORT]; - struct pnp_resource mem[PNP_MAX_MEM]; - struct pnp_resource dma[PNP_MAX_DMA]; - struct pnp_resource irq[PNP_MAX_IRQ]; -}; +void pnp_free_resource(struct pnp_resource *pnp_res); struct pnp_resource *pnp_add_irq_resource(struct pnp_dev *dev, int irq, int flags); diff --git a/drivers/pnp/core.c b/drivers/pnp/core.c index 20771b7d4482..7182da92aec3 100644 --- a/drivers/pnp/core.c +++ b/drivers/pnp/core.c @@ -99,6 +99,21 @@ static void pnp_free_ids(struct pnp_dev *dev) } } +void pnp_free_resource(struct pnp_resource *pnp_res) +{ + list_del(&pnp_res->list); + kfree(pnp_res); +} + +void pnp_free_resources(struct pnp_dev *dev) +{ + struct pnp_resource *pnp_res, *tmp; + + list_for_each_entry_safe(pnp_res, tmp, &dev->resources, list) { + pnp_free_resource(pnp_res); + } +} + static void pnp_release_device(struct device *dmdev) { struct pnp_dev *dev = to_pnp_dev(dmdev); @@ -106,7 +121,7 @@ static void pnp_release_device(struct device *dmdev) pnp_free_option(dev->independent); pnp_free_option(dev->dependent); pnp_free_ids(dev); - kfree(dev->res); + pnp_free_resources(dev); kfree(dev); } @@ -119,12 +134,7 @@ struct pnp_dev *pnp_alloc_dev(struct pnp_protocol *protocol, int id, char *pnpid if (!dev) return NULL; - dev->res = kzalloc(sizeof(struct pnp_resource_table), GFP_KERNEL); - if (!dev->res) { - kfree(dev); - return NULL; - } - + INIT_LIST_HEAD(&dev->resources); dev->protocol = protocol; dev->number = id; dev->dma_mask = DMA_24BIT_MASK; @@ -140,7 +150,6 @@ struct pnp_dev *pnp_alloc_dev(struct pnp_protocol *protocol, int id, char *pnpid dev_id = pnp_add_id(dev, pnpid); if (!dev_id) { - kfree(dev->res); kfree(dev); return NULL; } diff --git a/drivers/pnp/interface.c b/drivers/pnp/interface.c index 3f8007ab94e3..7fc86bbed88e 100644 --- a/drivers/pnp/interface.c +++ b/drivers/pnp/interface.c @@ -269,46 +269,38 @@ static ssize_t pnp_show_current_resources(struct device *dmdev, pnp_printf(buffer, "disabled\n"); for (i = 0; (res = pnp_get_resource(dev, IORESOURCE_IO, i)); i++) { - if (pnp_resource_valid(res)) { - pnp_printf(buffer, "io"); - if (res->flags & IORESOURCE_DISABLED) - pnp_printf(buffer, " disabled\n"); - else - pnp_printf(buffer, " 0x%llx-0x%llx\n", - (unsigned long long) res->start, - (unsigned long long) res->end); - } + pnp_printf(buffer, "io"); + if (res->flags & IORESOURCE_DISABLED) + pnp_printf(buffer, " disabled\n"); + else + pnp_printf(buffer, " 0x%llx-0x%llx\n", + (unsigned long long) res->start, + (unsigned long long) res->end); } for (i = 0; (res = pnp_get_resource(dev, IORESOURCE_MEM, i)); i++) { - if (pnp_resource_valid(res)) { - pnp_printf(buffer, "mem"); - if (res->flags & IORESOURCE_DISABLED) - pnp_printf(buffer, " disabled\n"); - else - pnp_printf(buffer, " 0x%llx-0x%llx\n", - (unsigned long long) res->start, - (unsigned long long) res->end); - } + pnp_printf(buffer, "mem"); + if (res->flags & IORESOURCE_DISABLED) + pnp_printf(buffer, " disabled\n"); + else + pnp_printf(buffer, " 0x%llx-0x%llx\n", + (unsigned long long) res->start, + (unsigned long long) res->end); } for (i = 0; (res = pnp_get_resource(dev, IORESOURCE_IRQ, i)); i++) { - if (pnp_resource_valid(res)) { - pnp_printf(buffer, "irq"); - if (res->flags & IORESOURCE_DISABLED) - pnp_printf(buffer, " disabled\n"); - else - pnp_printf(buffer, " %lld\n", - (unsigned long long) res->start); - } + pnp_printf(buffer, "irq"); + if (res->flags & IORESOURCE_DISABLED) + pnp_printf(buffer, " disabled\n"); + else + pnp_printf(buffer, " %lld\n", + (unsigned long long) res->start); } for (i = 0; (res = pnp_get_resource(dev, IORESOURCE_DMA, i)); i++) { - if (pnp_resource_valid(res)) { - pnp_printf(buffer, "dma"); - if (res->flags & IORESOURCE_DISABLED) - pnp_printf(buffer, " disabled\n"); - else - pnp_printf(buffer, " %lld\n", - (unsigned long long) res->start); - } + pnp_printf(buffer, "dma"); + if (res->flags & IORESOURCE_DISABLED) + pnp_printf(buffer, " disabled\n"); + else + pnp_printf(buffer, " %lld\n", + (unsigned long long) res->start); } ret = (buffer->curr - buf); kfree(buffer); diff --git a/drivers/pnp/isapnp/core.c b/drivers/pnp/isapnp/core.c index 752b51fbaa6c..ca4457ec403b 100644 --- a/drivers/pnp/isapnp/core.c +++ b/drivers/pnp/isapnp/core.c @@ -973,8 +973,7 @@ static int isapnp_set_resources(struct pnp_dev *dev) dev->active = 1; for (tmp = 0; tmp < ISAPNP_MAX_PORT; tmp++) { res = pnp_get_resource(dev, IORESOURCE_IO, tmp); - if (res && pnp_resource_valid(res) && - !(res->flags & IORESOURCE_DISABLED)) { + if (pnp_resource_enabled(res)) { dev_dbg(&dev->dev, " set io %d to %#llx\n", tmp, (unsigned long long) res->start); isapnp_write_word(ISAPNP_CFG_PORT + (tmp << 1), @@ -983,8 +982,7 @@ static int isapnp_set_resources(struct pnp_dev *dev) } for (tmp = 0; tmp < ISAPNP_MAX_IRQ; tmp++) { res = pnp_get_resource(dev, IORESOURCE_IRQ, tmp); - if (res && pnp_resource_valid(res) && - !(res->flags & IORESOURCE_DISABLED)) { + if (pnp_resource_enabled(res)) { int irq = res->start; if (irq == 2) irq = 9; @@ -994,8 +992,7 @@ static int isapnp_set_resources(struct pnp_dev *dev) } for (tmp = 0; tmp < ISAPNP_MAX_DMA; tmp++) { res = pnp_get_resource(dev, IORESOURCE_DMA, tmp); - if (res && pnp_resource_valid(res) && - !(res->flags & IORESOURCE_DISABLED)) { + if (pnp_resource_enabled(res)) { dev_dbg(&dev->dev, " set dma %d to %lld\n", tmp, (unsigned long long) res->start); isapnp_write_byte(ISAPNP_CFG_DMA + tmp, res->start); @@ -1003,8 +1000,7 @@ static int isapnp_set_resources(struct pnp_dev *dev) } for (tmp = 0; tmp < ISAPNP_MAX_MEM; tmp++) { res = pnp_get_resource(dev, IORESOURCE_MEM, tmp); - if (res && pnp_resource_valid(res) && - !(res->flags & IORESOURCE_DISABLED)) { + if (pnp_resource_enabled(res)) { dev_dbg(&dev->dev, " set mem %d to %#llx\n", tmp, (unsigned long long) res->start); isapnp_write_word(ISAPNP_CFG_MEM + (tmp << 3), diff --git a/drivers/pnp/manager.c b/drivers/pnp/manager.c index 90bd9cb65563..165b624081ad 100644 --- a/drivers/pnp/manager.c +++ b/drivers/pnp/manager.c @@ -19,40 +19,30 @@ DEFINE_MUTEX(pnp_res_mutex); static int pnp_assign_port(struct pnp_dev *dev, struct pnp_port *rule, int idx) { - struct pnp_resource *pnp_res; - struct resource *res; + struct resource *res, local_res; - pnp_res = pnp_get_pnp_resource(dev, IORESOURCE_IO, idx); - if (!pnp_res) { - dev_err(&dev->dev, "too many I/O port resources\n"); - /* pretend we were successful so at least the manager won't try again */ - return 1; - } - - res = &pnp_res->res; - - /* check if this resource has been manually set, if so skip */ - if (!(res->flags & IORESOURCE_AUTO)) { + res = pnp_get_resource(dev, IORESOURCE_IO, idx); + if (res) { dev_dbg(&dev->dev, " io %d already set to %#llx-%#llx " "flags %#lx\n", idx, (unsigned long long) res->start, (unsigned long long) res->end, res->flags); return 1; } - /* set the initial values */ - res->flags |= rule->flags | IORESOURCE_IO; - res->flags &= ~IORESOURCE_UNSET; + res = &local_res; + res->flags = rule->flags | IORESOURCE_AUTO; + res->start = 0; + res->end = 0; if (!rule->size) { res->flags |= IORESOURCE_DISABLED; dev_dbg(&dev->dev, " io %d disabled\n", idx); - return 1; /* skip disabled resource requests */ + goto __add; } res->start = rule->min; res->end = res->start + rule->size - 1; - /* run through until pnp_check_port is happy */ while (!pnp_check_port(dev, res)) { res->start += rule->align; res->end = res->start + rule->size - 1; @@ -61,38 +51,29 @@ static int pnp_assign_port(struct pnp_dev *dev, struct pnp_port *rule, int idx) return 0; } } - dev_dbg(&dev->dev, " assign io %d %#llx-%#llx\n", idx, - (unsigned long long) res->start, (unsigned long long) res->end); + +__add: + pnp_add_io_resource(dev, res->start, res->end, res->flags); return 1; } static int pnp_assign_mem(struct pnp_dev *dev, struct pnp_mem *rule, int idx) { - struct pnp_resource *pnp_res; - struct resource *res; + struct resource *res, local_res; - pnp_res = pnp_get_pnp_resource(dev, IORESOURCE_MEM, idx); - if (!pnp_res) { - dev_err(&dev->dev, "too many memory resources\n"); - /* pretend we were successful so at least the manager won't try again */ - return 1; - } - - res = &pnp_res->res; - - /* check if this resource has been manually set, if so skip */ - if (!(res->flags & IORESOURCE_AUTO)) { + res = pnp_get_resource(dev, IORESOURCE_MEM, idx); + if (res) { dev_dbg(&dev->dev, " mem %d already set to %#llx-%#llx " "flags %#lx\n", idx, (unsigned long long) res->start, (unsigned long long) res->end, res->flags); return 1; } - /* set the initial values */ - res->flags |= rule->flags | IORESOURCE_MEM; - res->flags &= ~IORESOURCE_UNSET; + res = &local_res; + res->flags = rule->flags | IORESOURCE_AUTO; + res->start = 0; + res->end = 0; - /* convert pnp flags to standard Linux flags */ if (!(rule->flags & IORESOURCE_MEM_WRITEABLE)) res->flags |= IORESOURCE_READONLY; if (rule->flags & IORESOURCE_MEM_CACHEABLE) @@ -105,13 +86,12 @@ static int pnp_assign_mem(struct pnp_dev *dev, struct pnp_mem *rule, int idx) if (!rule->size) { res->flags |= IORESOURCE_DISABLED; dev_dbg(&dev->dev, " mem %d disabled\n", idx); - return 1; /* skip disabled resource requests */ + goto __add; } res->start = rule->min; res->end = res->start + rule->size - 1; - /* run through until pnp_check_mem is happy */ while (!pnp_check_mem(dev, res)) { res->start += rule->align; res->end = res->start + rule->size - 1; @@ -120,15 +100,15 @@ static int pnp_assign_mem(struct pnp_dev *dev, struct pnp_mem *rule, int idx) return 0; } } - dev_dbg(&dev->dev, " assign mem %d %#llx-%#llx\n", idx, - (unsigned long long) res->start, (unsigned long long) res->end); + +__add: + pnp_add_mem_resource(dev, res->start, res->end, res->flags); return 1; } static int pnp_assign_irq(struct pnp_dev *dev, struct pnp_irq *rule, int idx) { - struct pnp_resource *pnp_res; - struct resource *res; + struct resource *res, local_res; int i; /* IRQ priority: this table is good for i386 */ @@ -136,58 +116,48 @@ static int pnp_assign_irq(struct pnp_dev *dev, struct pnp_irq *rule, int idx) 5, 10, 11, 12, 9, 14, 15, 7, 3, 4, 13, 0, 1, 6, 8, 2 }; - pnp_res = pnp_get_pnp_resource(dev, IORESOURCE_IRQ, idx); - if (!pnp_res) { - dev_err(&dev->dev, "too many IRQ resources\n"); - /* pretend we were successful so at least the manager won't try again */ - return 1; - } - - res = &pnp_res->res; - - /* check if this resource has been manually set, if so skip */ - if (!(res->flags & IORESOURCE_AUTO)) { + res = pnp_get_resource(dev, IORESOURCE_IRQ, idx); + if (res) { dev_dbg(&dev->dev, " irq %d already set to %d flags %#lx\n", idx, (int) res->start, res->flags); return 1; } - /* set the initial values */ - res->flags |= rule->flags | IORESOURCE_IRQ; - res->flags &= ~IORESOURCE_UNSET; + res = &local_res; + res->flags = rule->flags | IORESOURCE_AUTO; + res->start = -1; + res->end = -1; if (bitmap_empty(rule->map, PNP_IRQ_NR)) { res->flags |= IORESOURCE_DISABLED; dev_dbg(&dev->dev, " irq %d disabled\n", idx); - return 1; /* skip disabled resource requests */ + goto __add; } /* TBD: need check for >16 IRQ */ res->start = find_next_bit(rule->map, PNP_IRQ_NR, 16); if (res->start < PNP_IRQ_NR) { res->end = res->start; - dev_dbg(&dev->dev, " assign irq %d %d\n", idx, - (int) res->start); - return 1; + goto __add; } for (i = 0; i < 16; i++) { if (test_bit(xtab[i], rule->map)) { res->start = res->end = xtab[i]; - if (pnp_check_irq(dev, res)) { - dev_dbg(&dev->dev, " assign irq %d %d\n", idx, - (int) res->start); - return 1; - } + if (pnp_check_irq(dev, res)) + goto __add; } } dev_dbg(&dev->dev, " couldn't assign irq %d\n", idx); return 0; + +__add: + pnp_add_irq_resource(dev, res->start, res->flags); + return 1; } static void pnp_assign_dma(struct pnp_dev *dev, struct pnp_dma *rule, int idx) { - struct pnp_resource *pnp_res; - struct resource *res; + struct resource *res, local_res; int i; /* DMA priority: this table is good for i386 */ @@ -195,127 +165,47 @@ static void pnp_assign_dma(struct pnp_dev *dev, struct pnp_dma *rule, int idx) 1, 3, 5, 6, 7, 0, 2, 4 }; - pnp_res = pnp_get_pnp_resource(dev, IORESOURCE_DMA, idx); - if (!pnp_res) { - dev_err(&dev->dev, "too many DMA resources\n"); - return; - } - - res = &pnp_res->res; - - /* check if this resource has been manually set, if so skip */ - if (!(res->flags & IORESOURCE_AUTO)) { + res = pnp_get_resource(dev, IORESOURCE_DMA, idx); + if (res) { dev_dbg(&dev->dev, " dma %d already set to %d flags %#lx\n", idx, (int) res->start, res->flags); return; } - /* set the initial values */ - res->flags |= rule->flags | IORESOURCE_DMA; - res->flags &= ~IORESOURCE_UNSET; + res = &local_res; + res->flags = rule->flags | IORESOURCE_AUTO; + res->start = -1; + res->end = -1; for (i = 0; i < 8; i++) { if (rule->map & (1 << xtab[i])) { res->start = res->end = xtab[i]; - if (pnp_check_dma(dev, res)) { - dev_dbg(&dev->dev, " assign dma %d %d\n", idx, - (int) res->start); - return; - } + if (pnp_check_dma(dev, res)) + goto __add; } } #ifdef MAX_DMA_CHANNELS res->start = res->end = MAX_DMA_CHANNELS; #endif - res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; + res->flags |= IORESOURCE_DISABLED; dev_dbg(&dev->dev, " disable dma %d\n", idx); -} -void pnp_init_resource(struct resource *res) -{ - unsigned long type; - - type = res->flags & (IORESOURCE_IO | IORESOURCE_MEM | - IORESOURCE_IRQ | IORESOURCE_DMA); - - res->name = NULL; - res->flags = type | IORESOURCE_AUTO | IORESOURCE_UNSET; - if (type == IORESOURCE_IRQ || type == IORESOURCE_DMA) { - res->start = -1; - res->end = -1; - } else { - res->start = 0; - res->end = 0; - } +__add: + pnp_add_dma_resource(dev, res->start, res->flags); } -/** - * pnp_init_resources - Resets a resource table to default values. - * @table: pointer to the desired resource table - */ void pnp_init_resources(struct pnp_dev *dev) { - struct resource *res; - int idx; - - for (idx = 0; idx < PNP_MAX_IRQ; idx++) { - res = &dev->res->irq[idx].res; - res->flags = IORESOURCE_IRQ; - pnp_init_resource(res); - } - for (idx = 0; idx < PNP_MAX_DMA; idx++) { - res = &dev->res->dma[idx].res; - res->flags = IORESOURCE_DMA; - pnp_init_resource(res); - } - for (idx = 0; idx < PNP_MAX_PORT; idx++) { - res = &dev->res->port[idx].res; - res->flags = IORESOURCE_IO; - pnp_init_resource(res); - } - for (idx = 0; idx < PNP_MAX_MEM; idx++) { - res = &dev->res->mem[idx].res; - res->flags = IORESOURCE_MEM; - pnp_init_resource(res); - } + pnp_free_resources(dev); } -/** - * pnp_clean_resources - clears resources that were not manually set - * @res: the resources to clean - */ static void pnp_clean_resource_table(struct pnp_dev *dev) { - struct resource *res; - int idx; - - for (idx = 0; idx < PNP_MAX_IRQ; idx++) { - res = &dev->res->irq[idx].res; - if (res->flags & IORESOURCE_AUTO) { - res->flags = IORESOURCE_IRQ; - pnp_init_resource(res); - } - } - for (idx = 0; idx < PNP_MAX_DMA; idx++) { - res = &dev->res->dma[idx].res; - if (res->flags & IORESOURCE_AUTO) { - res->flags = IORESOURCE_DMA; - pnp_init_resource(res); - } - } - for (idx = 0; idx < PNP_MAX_PORT; idx++) { - res = &dev->res->port[idx].res; - if (res->flags & IORESOURCE_AUTO) { - res->flags = IORESOURCE_IO; - pnp_init_resource(res); - } - } - for (idx = 0; idx < PNP_MAX_MEM; idx++) { - res = &dev->res->mem[idx].res; - if (res->flags & IORESOURCE_AUTO) { - res->flags = IORESOURCE_MEM; - pnp_init_resource(res); - } + struct pnp_resource *pnp_res, *tmp; + + list_for_each_entry_safe(pnp_res, tmp, &dev->resources, list) { + if (pnp_res->res.flags & IORESOURCE_AUTO) + pnp_free_resource(pnp_res); } } diff --git a/drivers/pnp/pnpacpi/rsparser.c b/drivers/pnp/pnpacpi/rsparser.c index 46c791adb894..9a45c25b46d2 100644 --- a/drivers/pnp/pnpacpi/rsparser.c +++ b/drivers/pnp/pnpacpi/rsparser.c @@ -806,6 +806,13 @@ static void pnpacpi_encode_irq(struct pnp_dev *dev, struct acpi_resource_irq *irq = &resource->data.irq; int triggering, polarity, shareable; + if (!pnp_resource_enabled(p)) { + irq->interrupt_count = 0; + dev_dbg(&dev->dev, " encode irq (%s)\n", + p ? "disabled" : "missing"); + return; + } + decode_irq_flags(dev, p->flags, &triggering, &polarity, &shareable); irq->triggering = triggering; irq->polarity = polarity; @@ -828,6 +835,13 @@ static void pnpacpi_encode_ext_irq(struct pnp_dev *dev, struct acpi_resource_extended_irq *extended_irq = &resource->data.extended_irq; int triggering, polarity, shareable; + if (!pnp_resource_enabled(p)) { + extended_irq->interrupt_count = 0; + dev_dbg(&dev->dev, " encode extended irq (%s)\n", + p ? "disabled" : "missing"); + return; + } + decode_irq_flags(dev, p->flags, &triggering, &polarity, &shareable); extended_irq->producer_consumer = ACPI_CONSUMER; extended_irq->triggering = triggering; @@ -848,6 +862,13 @@ static void pnpacpi_encode_dma(struct pnp_dev *dev, { struct acpi_resource_dma *dma = &resource->data.dma; + if (!pnp_resource_enabled(p)) { + dma->channel_count = 0; + dev_dbg(&dev->dev, " encode dma (%s)\n", + p ? "disabled" : "missing"); + return; + } + /* Note: pnp_assign_dma will copy pnp_dma->flags into p->flags */ switch (p->flags & IORESOURCE_DMA_SPEED_MASK) { case IORESOURCE_DMA_TYPEA: @@ -889,17 +910,21 @@ static void pnpacpi_encode_io(struct pnp_dev *dev, { struct acpi_resource_io *io = &resource->data.io; - /* Note: pnp_assign_port will copy pnp_port->flags into p->flags */ - io->io_decode = (p->flags & PNP_PORT_FLAG_16BITADDR) ? - ACPI_DECODE_16 : ACPI_DECODE_10; - io->minimum = p->start; - io->maximum = p->end; - io->alignment = 0; /* Correct? */ - io->address_length = p->end - p->start + 1; - - dev_dbg(&dev->dev, " encode io %#llx-%#llx decode %#x\n", - (unsigned long long) p->start, (unsigned long long) p->end, - io->io_decode); + if (pnp_resource_enabled(p)) { + /* Note: pnp_assign_port copies pnp_port->flags into p->flags */ + io->io_decode = (p->flags & PNP_PORT_FLAG_16BITADDR) ? + ACPI_DECODE_16 : ACPI_DECODE_10; + io->minimum = p->start; + io->maximum = p->end; + io->alignment = 0; /* Correct? */ + io->address_length = p->end - p->start + 1; + } else { + io->minimum = 0; + io->address_length = 0; + } + + dev_dbg(&dev->dev, " encode io %#x-%#x decode %#x\n", io->minimum, + io->minimum + io->address_length - 1, io->io_decode); } static void pnpacpi_encode_fixed_io(struct pnp_dev *dev, @@ -908,11 +933,16 @@ static void pnpacpi_encode_fixed_io(struct pnp_dev *dev, { struct acpi_resource_fixed_io *fixed_io = &resource->data.fixed_io; - fixed_io->address = p->start; - fixed_io->address_length = p->end - p->start + 1; + if (pnp_resource_enabled(p)) { + fixed_io->address = p->start; + fixed_io->address_length = p->end - p->start + 1; + } else { + fixed_io->address = 0; + fixed_io->address_length = 0; + } - dev_dbg(&dev->dev, " encode fixed_io %#llx-%#llx\n", - (unsigned long long) p->start, (unsigned long long) p->end); + dev_dbg(&dev->dev, " encode fixed_io %#x-%#x\n", fixed_io->address, + fixed_io->address + fixed_io->address_length - 1); } static void pnpacpi_encode_mem24(struct pnp_dev *dev, @@ -921,17 +951,22 @@ static void pnpacpi_encode_mem24(struct pnp_dev *dev, { struct acpi_resource_memory24 *memory24 = &resource->data.memory24; - /* Note: pnp_assign_mem will copy pnp_mem->flags into p->flags */ - memory24->write_protect = - (p->flags & IORESOURCE_MEM_WRITEABLE) ? - ACPI_READ_WRITE_MEMORY : ACPI_READ_ONLY_MEMORY; - memory24->minimum = p->start; - memory24->maximum = p->end; - memory24->alignment = 0; - memory24->address_length = p->end - p->start + 1; - - dev_dbg(&dev->dev, " encode mem24 %#llx-%#llx write_protect %#x\n", - (unsigned long long) p->start, (unsigned long long) p->end, + if (pnp_resource_enabled(p)) { + /* Note: pnp_assign_mem copies pnp_mem->flags into p->flags */ + memory24->write_protect = p->flags & IORESOURCE_MEM_WRITEABLE ? + ACPI_READ_WRITE_MEMORY : ACPI_READ_ONLY_MEMORY; + memory24->minimum = p->start; + memory24->maximum = p->end; + memory24->alignment = 0; + memory24->address_length = p->end - p->start + 1; + } else { + memory24->minimum = 0; + memory24->address_length = 0; + } + + dev_dbg(&dev->dev, " encode mem24 %#x-%#x write_protect %#x\n", + memory24->minimum, + memory24->minimum + memory24->address_length - 1, memory24->write_protect); } @@ -941,16 +976,21 @@ static void pnpacpi_encode_mem32(struct pnp_dev *dev, { struct acpi_resource_memory32 *memory32 = &resource->data.memory32; - memory32->write_protect = - (p->flags & IORESOURCE_MEM_WRITEABLE) ? - ACPI_READ_WRITE_MEMORY : ACPI_READ_ONLY_MEMORY; - memory32->minimum = p->start; - memory32->maximum = p->end; - memory32->alignment = 0; - memory32->address_length = p->end - p->start + 1; + if (pnp_resource_enabled(p)) { + memory32->write_protect = p->flags & IORESOURCE_MEM_WRITEABLE ? + ACPI_READ_WRITE_MEMORY : ACPI_READ_ONLY_MEMORY; + memory32->minimum = p->start; + memory32->maximum = p->end; + memory32->alignment = 0; + memory32->address_length = p->end - p->start + 1; + } else { + memory32->minimum = 0; + memory32->alignment = 0; + } - dev_dbg(&dev->dev, " encode mem32 %#llx-%#llx write_protect %#x\n", - (unsigned long long) p->start, (unsigned long long) p->end, + dev_dbg(&dev->dev, " encode mem32 %#x-%#x write_protect %#x\n", + memory32->minimum, + memory32->minimum + memory32->address_length - 1, memory32->write_protect); } @@ -960,15 +1000,20 @@ static void pnpacpi_encode_fixed_mem32(struct pnp_dev *dev, { struct acpi_resource_fixed_memory32 *fixed_memory32 = &resource->data.fixed_memory32; - fixed_memory32->write_protect = - (p->flags & IORESOURCE_MEM_WRITEABLE) ? - ACPI_READ_WRITE_MEMORY : ACPI_READ_ONLY_MEMORY; - fixed_memory32->address = p->start; - fixed_memory32->address_length = p->end - p->start + 1; + if (pnp_resource_enabled(p)) { + fixed_memory32->write_protect = + p->flags & IORESOURCE_MEM_WRITEABLE ? + ACPI_READ_WRITE_MEMORY : ACPI_READ_ONLY_MEMORY; + fixed_memory32->address = p->start; + fixed_memory32->address_length = p->end - p->start + 1; + } else { + fixed_memory32->address = 0; + fixed_memory32->address_length = 0; + } - dev_dbg(&dev->dev, " encode fixed_mem32 %#llx-%#llx " - "write_protect %#x\n", - (unsigned long long) p->start, (unsigned long long) p->end, + dev_dbg(&dev->dev, " encode fixed_mem32 %#x-%#x write_protect %#x\n", + fixed_memory32->address, + fixed_memory32->address + fixed_memory32->address_length - 1, fixed_memory32->write_protect); } diff --git a/drivers/pnp/pnpbios/rsparser.c b/drivers/pnp/pnpbios/rsparser.c index 5ff9a4c0447e..01f0c3dd1b08 100644 --- a/drivers/pnp/pnpbios/rsparser.c +++ b/drivers/pnp/pnpbios/rsparser.c @@ -526,8 +526,16 @@ len_err: static void pnpbios_encode_mem(struct pnp_dev *dev, unsigned char *p, struct resource *res) { - unsigned long base = res->start; - unsigned long len = res->end - res->start + 1; + unsigned long base; + unsigned long len; + + if (pnp_resource_enabled(res)) { + base = res->start; + len = res->end - res->start + 1; + } else { + base = 0; + len = 0; + } p[4] = (base >> 8) & 0xff; p[5] = ((base >> 8) >> 8) & 0xff; @@ -536,15 +544,22 @@ static void pnpbios_encode_mem(struct pnp_dev *dev, unsigned char *p, p[10] = (len >> 8) & 0xff; p[11] = ((len >> 8) >> 8) & 0xff; - dev_dbg(&dev->dev, " encode mem %#llx-%#llx\n", - (unsigned long long) res->start, (unsigned long long) res->end); + dev_dbg(&dev->dev, " encode mem %#lx-%#lx\n", base, base + len - 1); } static void pnpbios_encode_mem32(struct pnp_dev *dev, unsigned char *p, struct resource *res) { - unsigned long base = res->start; - unsigned long len = res->end - res->start + 1; + unsigned long base; + unsigned long len; + + if (pnp_resource_enabled(res)) { + base = res->start; + len = res->end - res->start + 1; + } else { + base = 0; + len = 0; + } p[4] = base & 0xff; p[5] = (base >> 8) & 0xff; @@ -559,15 +574,22 @@ static void pnpbios_encode_mem32(struct pnp_dev *dev, unsigned char *p, p[18] = (len >> 16) & 0xff; p[19] = (len >> 24) & 0xff; - dev_dbg(&dev->dev, " encode mem32 %#llx-%#llx\n", - (unsigned long long) res->start, (unsigned long long) res->end); + dev_dbg(&dev->dev, " encode mem32 %#lx-%#lx\n", base, base + len - 1); } static void pnpbios_encode_fixed_mem32(struct pnp_dev *dev, unsigned char *p, struct resource *res) { - unsigned long base = res->start; - unsigned long len = res->end - res->start + 1; + unsigned long base; + unsigned long len; + + if (pnp_resource_enabled(res)) { + base = res->start; + len = res->end - res->start + 1; + } else { + base = 0; + len = 0; + } p[4] = base & 0xff; p[5] = (base >> 8) & 0xff; @@ -578,40 +600,54 @@ static void pnpbios_encode_fixed_mem32(struct pnp_dev *dev, unsigned char *p, p[10] = (len >> 16) & 0xff; p[11] = (len >> 24) & 0xff; - dev_dbg(&dev->dev, " encode fixed_mem32 %#llx-%#llx\n", - (unsigned long long) res->start, (unsigned long long) res->end); + dev_dbg(&dev->dev, " encode fixed_mem32 %#lx-%#lx\n", base, + base + len - 1); } static void pnpbios_encode_irq(struct pnp_dev *dev, unsigned char *p, struct resource *res) { - unsigned long map = 0; + unsigned long map; + + if (pnp_resource_enabled(res)) + map = 1 << res->start; + else + map = 0; - map = 1 << res->start; p[1] = map & 0xff; p[2] = (map >> 8) & 0xff; - dev_dbg(&dev->dev, " encode irq %llu\n", - (unsigned long long)res->start); + dev_dbg(&dev->dev, " encode irq mask %#lx\n", map); } static void pnpbios_encode_dma(struct pnp_dev *dev, unsigned char *p, struct resource *res) { - unsigned long map = 0; + unsigned long map; + + if (pnp_resource_enabled(res)) + map = 1 << res->start; + else + map = 0; - map = 1 << res->start; p[1] = map & 0xff; - dev_dbg(&dev->dev, " encode dma %llu\n", - (unsigned long long)res->start); + dev_dbg(&dev->dev, " encode dma mask %#lx\n", map); } static void pnpbios_encode_port(struct pnp_dev *dev, unsigned char *p, struct resource *res) { - unsigned long base = res->start; - unsigned long len = res->end - res->start + 1; + unsigned long base; + unsigned long len; + + if (pnp_resource_enabled(res)) { + base = res->start; + len = res->end - res->start + 1; + } else { + base = 0; + len = 0; + } p[2] = base & 0xff; p[3] = (base >> 8) & 0xff; @@ -619,8 +655,7 @@ static void pnpbios_encode_port(struct pnp_dev *dev, unsigned char *p, p[5] = (base >> 8) & 0xff; p[7] = len & 0xff; - dev_dbg(&dev->dev, " encode io %#llx-%#llx\n", - (unsigned long long) res->start, (unsigned long long) res->end); + dev_dbg(&dev->dev, " encode io %#lx-%#lx\n", base, base + len - 1); } static void pnpbios_encode_fixed_port(struct pnp_dev *dev, unsigned char *p, @@ -629,12 +664,20 @@ static void pnpbios_encode_fixed_port(struct pnp_dev *dev, unsigned char *p, unsigned long base = res->start; unsigned long len = res->end - res->start + 1; + if (pnp_resource_enabled(res)) { + base = res->start; + len = res->end - res->start + 1; + } else { + base = 0; + len = 0; + } + p[1] = base & 0xff; p[2] = (base >> 8) & 0xff; p[3] = len & 0xff; - dev_dbg(&dev->dev, " encode fixed_io %#llx-%#llx\n", - (unsigned long long) res->start, (unsigned long long) res->end); + dev_dbg(&dev->dev, " encode fixed_io %#lx-%#lx\n", base, + base + len - 1); } static unsigned char *pnpbios_encode_allocated_resource_data(struct pnp_dev diff --git a/drivers/pnp/quirks.c b/drivers/pnp/quirks.c index 1ff3bb585ab2..21acb54eff6d 100644 --- a/drivers/pnp/quirks.c +++ b/drivers/pnp/quirks.c @@ -248,8 +248,7 @@ static void quirk_system_pci_resources(struct pnp_dev *dev) for (j = 0; (res = pnp_get_resource(dev, IORESOURCE_MEM, j)); j++) { - if (res->flags & IORESOURCE_UNSET || - (res->start == 0 && res->end == 0)) + if (res->start == 0 && res->end == 0) continue; pnp_start = res->start; diff --git a/drivers/pnp/resource.c b/drivers/pnp/resource.c index cce341f743d4..0797a77bd042 100644 --- a/drivers/pnp/resource.c +++ b/drivers/pnp/resource.c @@ -237,7 +237,7 @@ void pnp_free_option(struct pnp_option *option) !((*(enda) < *(startb)) || (*(endb) < *(starta))) #define cannot_compare(flags) \ -((flags) & (IORESOURCE_UNSET | IORESOURCE_DISABLED)) +((flags) & IORESOURCE_DISABLED) int pnp_check_port(struct pnp_dev *dev, struct resource *res) { @@ -505,81 +505,31 @@ int pnp_resource_type(struct resource *res) IORESOURCE_IRQ | IORESOURCE_DMA); } -struct pnp_resource *pnp_get_pnp_resource(struct pnp_dev *dev, - unsigned int type, unsigned int num) -{ - struct pnp_resource_table *res = dev->res; - - switch (type) { - case IORESOURCE_IO: - if (num >= PNP_MAX_PORT) - return NULL; - return &res->port[num]; - case IORESOURCE_MEM: - if (num >= PNP_MAX_MEM) - return NULL; - return &res->mem[num]; - case IORESOURCE_IRQ: - if (num >= PNP_MAX_IRQ) - return NULL; - return &res->irq[num]; - case IORESOURCE_DMA: - if (num >= PNP_MAX_DMA) - return NULL; - return &res->dma[num]; - } - return NULL; -} - struct resource *pnp_get_resource(struct pnp_dev *dev, unsigned int type, unsigned int num) { struct pnp_resource *pnp_res; + struct resource *res; - pnp_res = pnp_get_pnp_resource(dev, type, num); - if (pnp_res) - return &pnp_res->res; - + list_for_each_entry(pnp_res, &dev->resources, list) { + res = &pnp_res->res; + if (pnp_resource_type(res) == type && num-- == 0) + return res; + } return NULL; } EXPORT_SYMBOL(pnp_get_resource); -static struct pnp_resource *pnp_new_resource(struct pnp_dev *dev, int type) +static struct pnp_resource *pnp_new_resource(struct pnp_dev *dev) { struct pnp_resource *pnp_res; - int i; - switch (type) { - case IORESOURCE_IO: - for (i = 0; i < PNP_MAX_PORT; i++) { - pnp_res = pnp_get_pnp_resource(dev, IORESOURCE_IO, i); - if (pnp_res && !pnp_resource_valid(&pnp_res->res)) - return pnp_res; - } - break; - case IORESOURCE_MEM: - for (i = 0; i < PNP_MAX_MEM; i++) { - pnp_res = pnp_get_pnp_resource(dev, IORESOURCE_MEM, i); - if (pnp_res && !pnp_resource_valid(&pnp_res->res)) - return pnp_res; - } - break; - case IORESOURCE_IRQ: - for (i = 0; i < PNP_MAX_IRQ; i++) { - pnp_res = pnp_get_pnp_resource(dev, IORESOURCE_IRQ, i); - if (pnp_res && !pnp_resource_valid(&pnp_res->res)) - return pnp_res; - } - break; - case IORESOURCE_DMA: - for (i = 0; i < PNP_MAX_DMA; i++) { - pnp_res = pnp_get_pnp_resource(dev, IORESOURCE_DMA, i); - if (pnp_res && !pnp_resource_valid(&pnp_res->res)) - return pnp_res; - } - break; - } - return NULL; + pnp_res = kzalloc(sizeof(struct pnp_resource), GFP_KERNEL); + if (!pnp_res) + return NULL; + + list_add_tail(&pnp_res->list, &dev->resources); + return pnp_res; } struct pnp_resource *pnp_add_irq_resource(struct pnp_dev *dev, int irq, @@ -589,7 +539,7 @@ struct pnp_resource *pnp_add_irq_resource(struct pnp_dev *dev, int irq, struct resource *res; static unsigned char warned; - pnp_res = pnp_new_resource(dev, IORESOURCE_IRQ); + pnp_res = pnp_new_resource(dev); if (!pnp_res) { if (!warned) { dev_err(&dev->dev, "can't add resource for IRQ %d\n", @@ -615,7 +565,7 @@ struct pnp_resource *pnp_add_dma_resource(struct pnp_dev *dev, int dma, struct resource *res; static unsigned char warned; - pnp_res = pnp_new_resource(dev, IORESOURCE_DMA); + pnp_res = pnp_new_resource(dev); if (!pnp_res) { if (!warned) { dev_err(&dev->dev, "can't add resource for DMA %d\n", @@ -642,7 +592,7 @@ struct pnp_resource *pnp_add_io_resource(struct pnp_dev *dev, struct resource *res; static unsigned char warned; - pnp_res = pnp_new_resource(dev, IORESOURCE_IO); + pnp_res = pnp_new_resource(dev); if (!pnp_res) { if (!warned) { dev_err(&dev->dev, "can't add resource for IO " @@ -671,7 +621,7 @@ struct pnp_resource *pnp_add_mem_resource(struct pnp_dev *dev, struct resource *res; static unsigned char warned; - pnp_res = pnp_new_resource(dev, IORESOURCE_MEM); + pnp_res = pnp_new_resource(dev); if (!pnp_res) { if (!warned) { dev_err(&dev->dev, "can't add resource for MEM " diff --git a/drivers/pnp/support.c b/drivers/pnp/support.c index eb07345f5cf7..1566e4a73849 100644 --- a/drivers/pnp/support.c +++ b/drivers/pnp/support.c @@ -16,6 +16,10 @@ */ int pnp_is_active(struct pnp_dev *dev) { + /* + * I don't think this is very reliable because pnp_disable_dev() + * only clears out auto-assigned resources. + */ if (!pnp_port_start(dev, 0) && pnp_port_len(dev, 0) <= 1 && !pnp_mem_start(dev, 0) && pnp_mem_len(dev, 0) <= 1 && pnp_irq(dev, 0) == -1 && pnp_dma(dev, 0) == -1) @@ -70,54 +74,41 @@ char *pnp_resource_type_name(struct resource *res) void dbg_pnp_show_resources(struct pnp_dev *dev, char *desc) { #ifdef DEBUG + char buf[128]; + int len = 0; + struct pnp_resource *pnp_res; struct resource *res; - int i; dev_dbg(&dev->dev, "current resources: %s\n", desc); + list_for_each_entry(pnp_res, &dev->resources, list) { + res = &pnp_res->res; - for (i = 0; i < PNP_MAX_IRQ; i++) { - res = pnp_get_resource(dev, IORESOURCE_IRQ, i); - if (res && !(res->flags & IORESOURCE_UNSET)) - dev_dbg(&dev->dev, " irq %lld flags %#lx%s%s\n", - (unsigned long long) res->start, res->flags, - res->flags & IORESOURCE_DISABLED ? - " DISABLED" : "", - res->flags & IORESOURCE_AUTO ? - " AUTO" : ""); - } - for (i = 0; i < PNP_MAX_DMA; i++) { - res = pnp_get_resource(dev, IORESOURCE_DMA, i); - if (res && !(res->flags & IORESOURCE_UNSET)) - dev_dbg(&dev->dev, " dma %lld flags %#lx%s%s\n", - (unsigned long long) res->start, res->flags, - res->flags & IORESOURCE_DISABLED ? - " DISABLED" : "", - res->flags & IORESOURCE_AUTO ? - " AUTO" : ""); - } - for (i = 0; i < PNP_MAX_PORT; i++) { - res = pnp_get_resource(dev, IORESOURCE_IO, i); - if (res && !(res->flags & IORESOURCE_UNSET)) - dev_dbg(&dev->dev, " io %#llx-%#llx flags %#lx" - "%s%s\n", - (unsigned long long) res->start, - (unsigned long long) res->end, res->flags, - res->flags & IORESOURCE_DISABLED ? - " DISABLED" : "", - res->flags & IORESOURCE_AUTO ? - " AUTO" : ""); - } - for (i = 0; i < PNP_MAX_MEM; i++) { - res = pnp_get_resource(dev, IORESOURCE_MEM, i); - if (res && !(res->flags & IORESOURCE_UNSET)) - dev_dbg(&dev->dev, " mem %#llx-%#llx flags %#lx" - "%s%s\n", - (unsigned long long) res->start, - (unsigned long long) res->end, res->flags, - res->flags & IORESOURCE_DISABLED ? - " DISABLED" : "", - res->flags & IORESOURCE_AUTO ? - " AUTO" : ""); + len += snprintf(buf + len, sizeof(buf) - len, " %-3s ", + pnp_resource_type_name(res)); + + if (res->flags & IORESOURCE_DISABLED) { + dev_dbg(&dev->dev, "%sdisabled\n", buf); + continue; + } + + switch (pnp_resource_type(res)) { + case IORESOURCE_IO: + case IORESOURCE_MEM: + len += snprintf(buf + len, sizeof(buf) - len, + "%#llx-%#llx flags %#lx", + (unsigned long long) res->start, + (unsigned long long) res->end, + res->flags); + break; + case IORESOURCE_IRQ: + case IORESOURCE_DMA: + len += snprintf(buf + len, sizeof(buf) - len, + "%lld flags %#lx", + (unsigned long long) res->start, + res->flags); + break; + } + dev_dbg(&dev->dev, "%s\n", buf); } #endif } diff --git a/drivers/pnp/system.c b/drivers/pnp/system.c index cf4e07b01d48..764f3a310685 100644 --- a/drivers/pnp/system.c +++ b/drivers/pnp/system.c @@ -60,7 +60,7 @@ static void reserve_resources_of_dev(struct pnp_dev *dev) int i; for (i = 0; (res = pnp_get_resource(dev, IORESOURCE_IO, i)); i++) { - if (res->flags & IORESOURCE_UNSET) + if (res->flags & IORESOURCE_DISABLED) continue; if (res->start == 0) continue; /* disabled */ @@ -81,7 +81,7 @@ static void reserve_resources_of_dev(struct pnp_dev *dev) } for (i = 0; (res = pnp_get_resource(dev, IORESOURCE_MEM, i)); i++) { - if (res->flags & (IORESOURCE_UNSET | IORESOURCE_DISABLED)) + if (res->flags & IORESOURCE_DISABLED) continue; reserve_range(dev, res->start, res->end, 0); diff --git a/include/linux/pnp.h b/include/linux/pnp.h index 8b607aecd959..dfaa567e04a8 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -15,7 +15,6 @@ struct pnp_protocol; struct pnp_dev; -struct pnp_resource_table; /* * Resource Management @@ -24,7 +23,14 @@ struct resource *pnp_get_resource(struct pnp_dev *, unsigned int, unsigned int); static inline int pnp_resource_valid(struct resource *res) { - if (res && !(res->flags & IORESOURCE_UNSET)) + if (res) + return 1; + return 0; +} + +static inline int pnp_resource_enabled(struct resource *res) +{ + if (res && !(res->flags & IORESOURCE_DISABLED)) return 1; return 0; } @@ -64,7 +70,7 @@ static inline unsigned long pnp_port_flags(struct pnp_dev *dev, if (pnp_resource_valid(res)) return res->flags; - return IORESOURCE_IO | IORESOURCE_AUTO | IORESOURCE_UNSET; + return IORESOURCE_IO | IORESOURCE_AUTO; } static inline int pnp_port_valid(struct pnp_dev *dev, unsigned int bar) @@ -109,7 +115,7 @@ static inline unsigned long pnp_mem_flags(struct pnp_dev *dev, unsigned int bar) if (pnp_resource_valid(res)) return res->flags; - return IORESOURCE_MEM | IORESOURCE_AUTO | IORESOURCE_UNSET; + return IORESOURCE_MEM | IORESOURCE_AUTO; } static inline int pnp_mem_valid(struct pnp_dev *dev, unsigned int bar) @@ -143,7 +149,7 @@ static inline unsigned long pnp_irq_flags(struct pnp_dev *dev, unsigned int bar) if (pnp_resource_valid(res)) return res->flags; - return IORESOURCE_IRQ | IORESOURCE_AUTO | IORESOURCE_UNSET; + return IORESOURCE_IRQ | IORESOURCE_AUTO; } static inline int pnp_irq_valid(struct pnp_dev *dev, unsigned int bar) @@ -167,7 +173,7 @@ static inline unsigned long pnp_dma_flags(struct pnp_dev *dev, unsigned int bar) if (pnp_resource_valid(res)) return res->flags; - return IORESOURCE_DMA | IORESOURCE_AUTO | IORESOURCE_UNSET; + return IORESOURCE_DMA | IORESOURCE_AUTO; } static inline int pnp_dma_valid(struct pnp_dev *dev, unsigned int bar) @@ -296,7 +302,7 @@ struct pnp_dev { int capabilities; struct pnp_option *independent; struct pnp_option *dependent; - struct pnp_resource_table *res; + struct list_head resources; char name[PNP_NAME_LEN]; /* contains a human-readable name */ int flags; /* used by protocols */ -- cgit v1.2.3 From 57fd51a8be26921b56747ddd09d1d9e01c11c9e0 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 27 Jun 2008 16:57:01 -0600 Subject: PNP: add pnp_possible_config() -- can a device could be configured this way? As part of a heuristic to identify modem devices, 8250_pnp.c checks to see whether a device can be configured at any of the legacy COM port addresses. This patch moves the code that traverses the PNP "possible resource options" from 8250_pnp.c to the PNP subsystem. This encapsulation is important because a future patch will change the implementation of those resource options. Signed-off-by: Bjorn Helgaas Signed-off-by: Andi Kleen Acked-by: Rene Herman Signed-off-by: Len Brown --- drivers/pnp/resource.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/serial/8250_pnp.c | 24 ++++++------------ include/linux/pnp.h | 5 ++++ 3 files changed, 74 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/drivers/pnp/resource.c b/drivers/pnp/resource.c index ff79aa6168cf..786fd356916d 100644 --- a/drivers/pnp/resource.c +++ b/drivers/pnp/resource.c @@ -624,6 +624,68 @@ struct pnp_resource *pnp_add_mem_resource(struct pnp_dev *dev, return pnp_res; } +static int pnp_possible_option(struct pnp_option *option, int type, + resource_size_t start, resource_size_t size) +{ + struct pnp_option *tmp; + struct pnp_port *port; + struct pnp_mem *mem; + struct pnp_irq *irq; + struct pnp_dma *dma; + + if (!option) + return 0; + + for (tmp = option; tmp; tmp = tmp->next) { + switch (type) { + case IORESOURCE_IO: + for (port = tmp->port; port; port = port->next) { + if (port->min == start && port->size == size) + return 1; + } + break; + case IORESOURCE_MEM: + for (mem = tmp->mem; mem; mem = mem->next) { + if (mem->min == start && mem->size == size) + return 1; + } + break; + case IORESOURCE_IRQ: + for (irq = tmp->irq; irq; irq = irq->next) { + if (start < PNP_IRQ_NR && + test_bit(start, irq->map)) + return 1; + } + break; + case IORESOURCE_DMA: + for (dma = tmp->dma; dma; dma = dma->next) { + if (dma->map & (1 << start)) + return 1; + } + break; + } + } + + return 0; +} + +/* + * Determine whether the specified resource is a possible configuration + * for this device. + */ +int pnp_possible_config(struct pnp_dev *dev, int type, resource_size_t start, + resource_size_t size) +{ + if (pnp_possible_option(dev->independent, type, start, size)) + return 1; + + if (pnp_possible_option(dev->dependent, type, start, size)) + return 1; + + return 0; +} +EXPORT_SYMBOL(pnp_possible_config); + /* format is: pnp_reserve_irq=irq1[,irq2] .... */ static int __init pnp_setup_reserve_irq(char *str) { diff --git a/drivers/serial/8250_pnp.c b/drivers/serial/8250_pnp.c index 97c68d021d28..638b68649e79 100644 --- a/drivers/serial/8250_pnp.c +++ b/drivers/serial/8250_pnp.c @@ -383,21 +383,14 @@ static int __devinit check_name(char *name) return 0; } -static int __devinit check_resources(struct pnp_option *option) +static int __devinit check_resources(struct pnp_dev *dev) { - struct pnp_option *tmp; - if (!option) - return 0; + resource_size_t base[] = {0x2f8, 0x3f8, 0x2e8, 0x3e8}; + int i; - for (tmp = option; tmp; tmp = tmp->next) { - struct pnp_port *port; - for (port = tmp->port; port; port = port->next) - if ((port->size == 8) && - ((port->min == 0x2f8) || - (port->min == 0x3f8) || - (port->min == 0x2e8) || - (port->min == 0x3e8))) - return 1; + for (i = 0; i < ARRAY_SIZE(base); i++) { + if (pnp_possible_config(dev, IORESOURCE_IO, base[i], 8)) + return 1; } return 0; @@ -420,10 +413,7 @@ static int __devinit serial_pnp_guess_board(struct pnp_dev *dev, int *flags) (dev->card && check_name(dev->card->name)))) return -ENODEV; - if (check_resources(dev->independent)) - return 0; - - if (check_resources(dev->dependent)) + if (check_resources(dev)) return 0; return -ENODEV; diff --git a/include/linux/pnp.h b/include/linux/pnp.h index dfaa567e04a8..e033e1b14c27 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -479,6 +479,8 @@ void pnp_unregister_card_driver(struct pnp_card_driver *drv); extern struct list_head pnp_cards; /* resource management */ +int pnp_possible_config(struct pnp_dev *dev, int type, resource_size_t base, + resource_size_t size); int pnp_auto_config_dev(struct pnp_dev *dev); int pnp_start_dev(struct pnp_dev *dev); int pnp_stop_dev(struct pnp_dev *dev); @@ -506,6 +508,9 @@ static inline int pnp_register_card_driver(struct pnp_card_driver *drv) { return static inline void pnp_unregister_card_driver(struct pnp_card_driver *drv) { } /* resource management */ +static inline int pnp_possible_config(struct pnp_dev *dev, int type, + resource_size_t base, + resource_size_t size) { return 0; } static inline int pnp_auto_config_dev(struct pnp_dev *dev) { return -ENODEV; } static inline int pnp_start_dev(struct pnp_dev *dev) { return -ENODEV; } static inline int pnp_stop_dev(struct pnp_dev *dev) { return -ENODEV; } -- cgit v1.2.3 From 08c9f262f268f7948be13bf3a5bda1d635c649b4 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 27 Jun 2008 16:57:03 -0600 Subject: PNP: define PNP-specific IORESOURCE_IO_* flags alongside IRQ, DMA, MEM PNP previously defined PNP_PORT_FLAG_16BITADDR and PNP_PORT_FLAG_FIXED in a private header file, but put those flags in struct resource.flags fields. Better to make them IORESOURCE_IO_* flags like the existing IRQ, DMA, and MEM flags. Signed-off-by: Bjorn Helgaas Signed-off-by: Andi Kleen Acked-by: Rene Herman Signed-off-by: Len Brown --- drivers/pnp/interface.c | 2 +- drivers/pnp/isapnp/core.c | 4 ++-- drivers/pnp/pnpacpi/rsparser.c | 10 +++++----- drivers/pnp/pnpbios/rsparser.c | 4 ++-- include/linux/ioport.h | 4 ++++ include/linux/pnp.h | 3 --- 6 files changed, 14 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/drivers/pnp/interface.c b/drivers/pnp/interface.c index 239923a300cd..c172b6de6b71 100644 --- a/drivers/pnp/interface.c +++ b/drivers/pnp/interface.c @@ -57,7 +57,7 @@ static void pnp_print_port(pnp_info_buffer_t * buffer, char *space, "%sport 0x%x-0x%x, align 0x%x, size 0x%x, %i-bit address decoding\n", space, port->min, port->max, port->align ? (port->align - 1) : 0, port->size, - port->flags & PNP_PORT_FLAG_16BITADDR ? 16 : 10); + port->flags & IORESOURCE_IO_16BIT_ADDR ? 16 : 10); } static void pnp_print_irq(pnp_info_buffer_t * buffer, char *space, diff --git a/drivers/pnp/isapnp/core.c b/drivers/pnp/isapnp/core.c index ca4457ec403b..c5b92526963b 100644 --- a/drivers/pnp/isapnp/core.c +++ b/drivers/pnp/isapnp/core.c @@ -486,7 +486,7 @@ static void __init isapnp_parse_port_resource(struct pnp_dev *dev, port->max = (tmp[4] << 8) | tmp[3]; port->align = tmp[5]; port->size = tmp[6]; - port->flags = tmp[0] ? PNP_PORT_FLAG_16BITADDR : 0; + port->flags = tmp[0] ? IORESOURCE_IO_16BIT_ADDR : 0; pnp_register_port_resource(dev, option, port); } @@ -507,7 +507,7 @@ static void __init isapnp_parse_fixed_port_resource(struct pnp_dev *dev, port->min = port->max = (tmp[1] << 8) | tmp[0]; port->size = tmp[2]; port->align = 0; - port->flags = PNP_PORT_FLAG_FIXED; + port->flags = IORESOURCE_IO_FIXED; pnp_register_port_resource(dev, option, port); } diff --git a/drivers/pnp/pnpacpi/rsparser.c b/drivers/pnp/pnpacpi/rsparser.c index 595252b65205..46069e64a6b2 100644 --- a/drivers/pnp/pnpacpi/rsparser.c +++ b/drivers/pnp/pnpacpi/rsparser.c @@ -180,7 +180,7 @@ static void pnpacpi_parse_allocated_ioresource(struct pnp_dev *dev, u64 start, u64 end = start + len - 1; if (io_decode == ACPI_DECODE_16) - flags |= PNP_PORT_FLAG_16BITADDR; + flags |= IORESOURCE_IO_16BIT_ADDR; if (len == 0 || end >= 0x10003) flags |= IORESOURCE_DISABLED; @@ -485,7 +485,7 @@ static __init void pnpacpi_parse_port_option(struct pnp_dev *dev, port->align = io->alignment; port->size = io->address_length; port->flags = ACPI_DECODE_16 == io->io_decode ? - PNP_PORT_FLAG_16BITADDR : 0; + IORESOURCE_IO_16BIT_ADDR : 0; pnp_register_port_resource(dev, option, port); } @@ -503,7 +503,7 @@ static __init void pnpacpi_parse_fixed_port_option(struct pnp_dev *dev, port->min = port->max = io->address; port->size = io->address_length; port->align = 0; - port->flags = PNP_PORT_FLAG_FIXED; + port->flags = IORESOURCE_IO_FIXED; pnp_register_port_resource(dev, option, port); } @@ -609,7 +609,7 @@ static __init void pnpacpi_parse_address_option(struct pnp_dev *dev, port->min = port->max = p->minimum; port->size = p->address_length; port->align = 0; - port->flags = PNP_PORT_FLAG_FIXED; + port->flags = IORESOURCE_IO_FIXED; pnp_register_port_resource(dev, option, port); } } @@ -946,7 +946,7 @@ static void pnpacpi_encode_io(struct pnp_dev *dev, if (pnp_resource_enabled(p)) { /* Note: pnp_assign_port copies pnp_port->flags into p->flags */ - io->io_decode = (p->flags & PNP_PORT_FLAG_16BITADDR) ? + io->io_decode = (p->flags & IORESOURCE_IO_16BIT_ADDR) ? ACPI_DECODE_16 : ACPI_DECODE_10; io->minimum = p->start; io->maximum = p->end; diff --git a/drivers/pnp/pnpbios/rsparser.c b/drivers/pnp/pnpbios/rsparser.c index 01f0c3dd1b08..489fec3b7974 100644 --- a/drivers/pnp/pnpbios/rsparser.c +++ b/drivers/pnp/pnpbios/rsparser.c @@ -310,7 +310,7 @@ static __init void pnpbios_parse_port_option(struct pnp_dev *dev, port->max = (p[5] << 8) | p[4]; port->align = p[6]; port->size = p[7]; - port->flags = p[1] ? PNP_PORT_FLAG_16BITADDR : 0; + port->flags = p[1] ? IORESOURCE_IO_16BIT_ADDR : 0; pnp_register_port_resource(dev, option, port); } @@ -326,7 +326,7 @@ static __init void pnpbios_parse_fixed_port_option(struct pnp_dev *dev, port->min = port->max = (p[2] << 8) | p[1]; port->size = p[3]; port->align = 0; - port->flags = PNP_PORT_FLAG_FIXED; + port->flags = IORESOURCE_IO_FIXED; pnp_register_port_resource(dev, option, port); } diff --git a/include/linux/ioport.h b/include/linux/ioport.h index c6801bffe76d..39db059ffb8b 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -88,6 +88,10 @@ struct resource_list { #define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */ #define IORESOURCE_MEM_EXPANSIONROM (1<<6) +/* PnP I/O specific bits (IORESOURCE_BITS) */ +#define IORESOURCE_IO_16BIT_ADDR (1<<0) +#define IORESOURCE_IO_FIXED (1<<1) + /* PCI ROM control bits (IORESOURCE_BITS) */ #define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */ #define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */ diff --git a/include/linux/pnp.h b/include/linux/pnp.h index e033e1b14c27..e1454dabde10 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -182,9 +182,6 @@ static inline int pnp_dma_valid(struct pnp_dev *dev, unsigned int bar) } -#define PNP_PORT_FLAG_16BITADDR (1<<0) -#define PNP_PORT_FLAG_FIXED (1<<1) - struct pnp_port { unsigned short min; /* min base number */ unsigned short max; /* max base number */ -- cgit v1.2.3 From a1802c42950403657d07e64558eff612d550ce16 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 27 Jun 2008 16:57:04 -0600 Subject: PNP: make resource option structures private to PNP subsystem Nothing outside the PNP subsystem should need access to a device's resource options, so this patch moves the option structure declarations to a private header file. Signed-off-by: Bjorn Helgaas Signed-off-by: Andi Kleen Acked-by: Rene Herman Signed-off-by: Len Brown --- drivers/pnp/base.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pnp.h | 48 ------------------------------------------------ 2 files changed, 48 insertions(+), 48 deletions(-) (limited to 'include') diff --git a/drivers/pnp/base.h b/drivers/pnp/base.h index 1667ac3ca45b..3126e4582008 100644 --- a/drivers/pnp/base.h +++ b/drivers/pnp/base.h @@ -19,6 +19,54 @@ void pnp_remove_card(struct pnp_card *card); int pnp_add_card_device(struct pnp_card *card, struct pnp_dev *dev); void pnp_remove_card_device(struct pnp_dev *dev); +struct pnp_port { + unsigned short min; /* min base number */ + unsigned short max; /* max base number */ + unsigned char align; /* align boundary */ + unsigned char size; /* size of range */ + unsigned char flags; /* port flags */ + unsigned char pad; /* pad */ + struct pnp_port *next; /* next port */ +}; + +#define PNP_IRQ_NR 256 +struct pnp_irq { + DECLARE_BITMAP(map, PNP_IRQ_NR); /* bitmask for IRQ lines */ + unsigned char flags; /* IRQ flags */ + unsigned char pad; /* pad */ + struct pnp_irq *next; /* next IRQ */ +}; + +struct pnp_dma { + unsigned char map; /* bitmask for DMA channels */ + unsigned char flags; /* DMA flags */ + struct pnp_dma *next; /* next port */ +}; + +struct pnp_mem { + unsigned int min; /* min base number */ + unsigned int max; /* max base number */ + unsigned int align; /* align boundary */ + unsigned int size; /* size of range */ + unsigned char flags; /* memory flags */ + unsigned char pad; /* pad */ + struct pnp_mem *next; /* next memory resource */ +}; + +#define PNP_RES_PRIORITY_PREFERRED 0 +#define PNP_RES_PRIORITY_ACCEPTABLE 1 +#define PNP_RES_PRIORITY_FUNCTIONAL 2 +#define PNP_RES_PRIORITY_INVALID 65535 + +struct pnp_option { + unsigned short priority; /* priority */ + struct pnp_port *port; /* first port */ + struct pnp_irq *irq; /* first IRQ */ + struct pnp_dma *dma; /* first DMA */ + struct pnp_mem *mem; /* first memory resource */ + struct pnp_option *next; /* used to chain dependent resources */ +}; + struct pnp_option *pnp_build_option(int priority); struct pnp_option *pnp_register_independent_option(struct pnp_dev *dev); struct pnp_option *pnp_register_dependent_option(struct pnp_dev *dev, diff --git a/include/linux/pnp.h b/include/linux/pnp.h index e1454dabde10..785126ffcc11 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -182,54 +182,6 @@ static inline int pnp_dma_valid(struct pnp_dev *dev, unsigned int bar) } -struct pnp_port { - unsigned short min; /* min base number */ - unsigned short max; /* max base number */ - unsigned char align; /* align boundary */ - unsigned char size; /* size of range */ - unsigned char flags; /* port flags */ - unsigned char pad; /* pad */ - struct pnp_port *next; /* next port */ -}; - -#define PNP_IRQ_NR 256 -struct pnp_irq { - DECLARE_BITMAP(map, PNP_IRQ_NR); /* bitmask for IRQ lines */ - unsigned char flags; /* IRQ flags */ - unsigned char pad; /* pad */ - struct pnp_irq *next; /* next IRQ */ -}; - -struct pnp_dma { - unsigned char map; /* bitmask for DMA channels */ - unsigned char flags; /* DMA flags */ - struct pnp_dma *next; /* next port */ -}; - -struct pnp_mem { - unsigned int min; /* min base number */ - unsigned int max; /* max base number */ - unsigned int align; /* align boundary */ - unsigned int size; /* size of range */ - unsigned char flags; /* memory flags */ - unsigned char pad; /* pad */ - struct pnp_mem *next; /* next memory resource */ -}; - -#define PNP_RES_PRIORITY_PREFERRED 0 -#define PNP_RES_PRIORITY_ACCEPTABLE 1 -#define PNP_RES_PRIORITY_FUNCTIONAL 2 -#define PNP_RES_PRIORITY_INVALID 65535 - -struct pnp_option { - unsigned short priority; /* priority */ - struct pnp_port *port; /* first port */ - struct pnp_irq *irq; /* first IRQ */ - struct pnp_dma *dma; /* first DMA */ - struct pnp_mem *mem; /* first memory resource */ - struct pnp_option *next; /* used to chain dependent resources */ -}; - /* * Device Management */ -- cgit v1.2.3 From d5ebde6ef5c2d51828f975a81d7d0e58bccfd833 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 27 Jun 2008 16:57:14 -0600 Subject: PNP: support optional IRQ resources This patch adds an IORESOURCE_IRQ_OPTIONAL flag for use when assigning resources to a device. If the flag is set and we are unable to assign an IRQ to the device, we can leave the IRQ disabled but allow the overall resource allocation to succeed. Some devices request an IRQ, but can run without an IRQ (possibly with degraded performance). This flag lets us run the device without the IRQ instead of just leaving the device disabled. This is a reimplementation of this previous change by Rene Herman : http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=3b73a223661ed137c5d3d2635f954382e94f5a43 I reimplemented this for two reasons: - to prepare for converting all resource options into a single linked list, as opposed to the per-resource-type lists we have now, and - to preserve the order and number of resource options. In PNPBIOS and ACPI, we configure a device by giving firmware a list of resource assignments. It is important that this list has exactly the same number of resources, in the same order, as the "template" list we got from the firmware in the first place. The problem of a sound card MPU401 being left disabled for want of an IRQ was reported by Uwe Bugla . Signed-off-by: Bjorn Helgaas Signed-off-by: Andi Kleen Acked-by: Rene Herman Signed-off-by: Len Brown --- drivers/pnp/interface.c | 2 ++ drivers/pnp/manager.c | 9 +++++++ drivers/pnp/quirks.c | 71 +++++++++++++++++++------------------------------ include/linux/ioport.h | 1 + 4 files changed, 39 insertions(+), 44 deletions(-) (limited to 'include') diff --git a/drivers/pnp/interface.c b/drivers/pnp/interface.c index b09f67de13d0..7a9fb5544b80 100644 --- a/drivers/pnp/interface.c +++ b/drivers/pnp/interface.c @@ -90,6 +90,8 @@ static void pnp_print_irq(pnp_info_buffer_t * buffer, char *space, pnp_printf(buffer, " High-Level"); if (irq->flags & IORESOURCE_IRQ_LOWLEVEL) pnp_printf(buffer, " Low-Level"); + if (irq->flags & IORESOURCE_IRQ_OPTIONAL) + pnp_printf(buffer, " (optional)"); pnp_printf(buffer, "\n"); } diff --git a/drivers/pnp/manager.c b/drivers/pnp/manager.c index 7ea9e1e28003..a20accb5ef8f 100644 --- a/drivers/pnp/manager.c +++ b/drivers/pnp/manager.c @@ -153,6 +153,15 @@ static int pnp_assign_irq(struct pnp_dev *dev, struct pnp_irq *rule, int idx) goto __add; } } + + if (rule->flags & IORESOURCE_IRQ_OPTIONAL) { + res->start = -1; + res->end = -1; + res->flags |= IORESOURCE_DISABLED; + dev_dbg(&dev->dev, " irq %d disabled (optional)\n", idx); + goto __add; + } + dev_dbg(&dev->dev, " couldn't assign irq %d\n", idx); return -EBUSY; diff --git a/drivers/pnp/quirks.c b/drivers/pnp/quirks.c index 48e60171b3ba..e8515ce0d296 100644 --- a/drivers/pnp/quirks.c +++ b/drivers/pnp/quirks.c @@ -121,34 +121,46 @@ static struct pnp_option *quirk_isapnp_mpu_options(struct pnp_dev *dev) struct pnp_option *res; /* - * Build a functional IRQ-less variant of each MPU option. + * Build a functional IRQ-optional variant of each MPU option. */ for (res = dev->dependent; res; res = res->next) { struct pnp_option *curr; struct pnp_port *port; - struct pnp_port *copy; + struct pnp_port *copy_port; + struct pnp_irq *irq; + struct pnp_irq *copy_irq; port = res->port; - if (!port || !res->irq) + irq = res->irq; + if (!port || !irq) continue; - copy = pnp_alloc(sizeof *copy); - if (!copy) + copy_port = pnp_alloc(sizeof *copy_port); + if (!copy_port) + break; + + copy_irq = pnp_alloc(sizeof *copy_irq); + if (!copy_irq) { + kfree(copy_port); break; + } + + *copy_port = *port; + copy_port->next = NULL; - copy->min = port->min; - copy->max = port->max; - copy->align = port->align; - copy->size = port->size; - copy->flags = port->flags; + *copy_irq = *irq; + copy_irq->flags |= IORESOURCE_IRQ_OPTIONAL; + copy_irq->next = NULL; curr = pnp_build_option(PNP_RES_PRIORITY_FUNCTIONAL); if (!curr) { - kfree(copy); + kfree(copy_port); + kfree(copy_irq); break; } - curr->port = copy; + curr->port = copy_port; + curr->irq = copy_irq; if (prev) prev->next = curr; @@ -157,7 +169,7 @@ static struct pnp_option *quirk_isapnp_mpu_options(struct pnp_dev *dev) prev = curr; } if (head) - dev_info(&dev->dev, "adding IRQ-less MPU options\n"); + dev_info(&dev->dev, "adding IRQ-optional MPU options\n"); return head; } @@ -167,10 +179,6 @@ static void quirk_ad1815_mpu_resources(struct pnp_dev *dev) struct pnp_option *res; struct pnp_irq *irq; - /* - * Distribute the independent IRQ over the dependent options - */ - res = dev->independent; if (!res) return; @@ -179,33 +187,8 @@ static void quirk_ad1815_mpu_resources(struct pnp_dev *dev) if (!irq || irq->next) return; - res = dev->dependent; - if (!res) - return; - - while (1) { - struct pnp_irq *copy; - - copy = pnp_alloc(sizeof *copy); - if (!copy) - break; - - bitmap_copy(copy->map.bits, irq->map.bits, PNP_IRQ_NR); - copy->flags = irq->flags; - - copy->next = res->irq; /* Yes, this is NULL */ - res->irq = copy; - - if (!res->next) - break; - res = res->next; - } - kfree(irq); - - res->next = quirk_isapnp_mpu_options(dev); - - res = dev->independent; - res->irq = NULL; + irq->flags |= IORESOURCE_IRQ_OPTIONAL; + dev_info(&dev->dev, "made independent IRQ optional\n"); } static void quirk_isapnp_mpu_resources(struct pnp_dev *dev) diff --git a/include/linux/ioport.h b/include/linux/ioport.h index 39db059ffb8b..2cd07cc29687 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -59,6 +59,7 @@ struct resource_list { #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) #define IORESOURCE_IRQ_LOWLEVEL (1<<3) #define IORESOURCE_IRQ_SHAREABLE (1<<4) +#define IORESOURCE_IRQ_OPTIONAL (1<<5) /* PnP DMA specific bits (IORESOURCE_BITS) */ #define IORESOURCE_DMA_TYPE_MASK (3<<0) -- cgit v1.2.3 From 1f32ca31e7409d37c1b25e5f81840fb184380cdf Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 27 Jun 2008 16:57:17 -0600 Subject: PNP: convert resource options to single linked list ISAPNP, PNPBIOS, and ACPI describe the "possible resource settings" of a device, i.e., the possibilities an OS bus driver has when it assigns I/O port, MMIO, and other resources to the device. PNP used to maintain this "possible resource setting" information in one independent option structure and a list of dependent option structures for each device. Each of these option structures had lists of I/O, memory, IRQ, and DMA resources, for example: dev independent options ind-io0 -> ind-io1 ... ind-mem0 -> ind-mem1 ... ... dependent option set 0 dep0-io0 -> dep0-io1 ... dep0-mem0 -> dep0-mem1 ... ... dependent option set 1 dep1-io0 -> dep1-io1 ... dep1-mem0 -> dep1-mem1 ... ... ... This data structure was designed for ISAPNP, where the OS configures device resource settings by writing directly to configuration registers. The OS can write the registers in arbitrary order much like it writes PCI BARs. However, for PNPBIOS and ACPI devices, the OS uses firmware interfaces that perform device configuration, and it is important to pass the desired settings to those interfaces in the correct order. The OS learns the correct order by using firmware interfaces that return the "current resource settings" and "possible resource settings," but the option structures above doesn't store the ordering information. This patch replaces the independent and dependent lists with a single list of options. For example, a device might have possible resource settings like this: dev options ind-io0 -> dep0-io0 -> dep1->io0 -> ind-io1 ... All the possible settings are in the same list, in the order they come from the firmware "possible resource settings" list. Each entry is tagged with an independent/dependent flag. Dependent entries also have a "set number" and an optional priority value. All dependent entries must be assigned from the same set. For example, the OS can use all the entries from dependent set 0, or all the entries from dependent set 1, but it cannot mix entries from set 0 with entries from set 1. Prior to this patch PNP didn't keep track of the order of this list, and it assigned all independent options first, then all dependent ones. Using the example above, that resulted in a "desired configuration" list like this: ind->io0 -> ind->io1 -> depN-io0 ... instead of the list the firmware expects, which looks like this: ind->io0 -> depN-io0 -> ind-io1 ... Signed-off-by: Bjorn Helgaas Signed-off-by: Andi Kleen Acked-by: Rene Herman Signed-off-by: Len Brown --- drivers/pnp/base.h | 93 +++++++++---- drivers/pnp/core.c | 4 +- drivers/pnp/interface.c | 75 +++++------ drivers/pnp/isapnp/core.c | 72 +++++----- drivers/pnp/manager.c | 145 +++++++-------------- drivers/pnp/pnpacpi/rsparser.c | 93 ++++++------- drivers/pnp/pnpbios/rsparser.c | 67 +++++----- drivers/pnp/quirks.c | 290 ++++++++++++++++++++++------------------- drivers/pnp/resource.c | 268 +++++++++---------------------------- drivers/pnp/support.c | 92 +++++++++++++ include/linux/pnp.h | 6 +- 11 files changed, 571 insertions(+), 634 deletions(-) (limited to 'include') diff --git a/drivers/pnp/base.h b/drivers/pnp/base.h index 360c6385686c..e3fa9a2d9a3d 100644 --- a/drivers/pnp/base.h +++ b/drivers/pnp/base.h @@ -1,3 +1,8 @@ +/* + * Copyright (C) 2008 Hewlett-Packard Development Company, L.P. + * Bjorn Helgaas + */ + extern spinlock_t pnp_lock; void *pnp_alloc(long size); @@ -25,8 +30,6 @@ struct pnp_port { resource_size_t align; /* align boundary */ resource_size_t size; /* size of range */ unsigned char flags; /* port flags */ - unsigned char pad; /* pad */ - struct pnp_port *next; /* next port */ }; #define PNP_IRQ_NR 256 @@ -35,14 +38,11 @@ typedef struct { DECLARE_BITMAP(bits, PNP_IRQ_NR); } pnp_irq_mask_t; struct pnp_irq { pnp_irq_mask_t map; /* bitmap for IRQ lines */ unsigned char flags; /* IRQ flags */ - unsigned char pad; /* pad */ - struct pnp_irq *next; /* next IRQ */ }; struct pnp_dma { unsigned char map; /* bitmask for DMA channels */ unsigned char flags; /* DMA flags */ - struct pnp_dma *next; /* next port */ }; struct pnp_mem { @@ -51,44 +51,91 @@ struct pnp_mem { resource_size_t align; /* align boundary */ resource_size_t size; /* size of range */ unsigned char flags; /* memory flags */ - unsigned char pad; /* pad */ - struct pnp_mem *next; /* next memory resource */ }; +#define PNP_OPTION_DEPENDENT 0x80000000 +#define PNP_OPTION_SET_MASK 0xffff +#define PNP_OPTION_SET_SHIFT 12 +#define PNP_OPTION_PRIORITY_MASK 0xfff +#define PNP_OPTION_PRIORITY_SHIFT 0 + #define PNP_RES_PRIORITY_PREFERRED 0 #define PNP_RES_PRIORITY_ACCEPTABLE 1 #define PNP_RES_PRIORITY_FUNCTIONAL 2 -#define PNP_RES_PRIORITY_INVALID 65535 +#define PNP_RES_PRIORITY_INVALID PNP_OPTION_PRIORITY_MASK struct pnp_option { - unsigned short priority; /* priority */ - struct pnp_port *port; /* first port */ - struct pnp_irq *irq; /* first IRQ */ - struct pnp_dma *dma; /* first DMA */ - struct pnp_mem *mem; /* first memory resource */ - struct pnp_option *next; /* used to chain dependent resources */ + struct list_head list; + unsigned int flags; /* independent/dependent, set, priority */ + + unsigned long type; /* IORESOURCE_{IO,MEM,IRQ,DMA} */ + union { + struct pnp_port port; + struct pnp_irq irq; + struct pnp_dma dma; + struct pnp_mem mem; + } u; }; -struct pnp_option *pnp_build_option(int priority); -struct pnp_option *pnp_register_independent_option(struct pnp_dev *dev); -struct pnp_option *pnp_register_dependent_option(struct pnp_dev *dev, - int priority); -int pnp_register_irq_resource(struct pnp_dev *dev, struct pnp_option *option, +int pnp_register_irq_resource(struct pnp_dev *dev, unsigned int option_flags, pnp_irq_mask_t *map, unsigned char flags); -int pnp_register_dma_resource(struct pnp_dev *dev, struct pnp_option *option, +int pnp_register_dma_resource(struct pnp_dev *dev, unsigned int option_flags, unsigned char map, unsigned char flags); -int pnp_register_port_resource(struct pnp_dev *dev, struct pnp_option *option, +int pnp_register_port_resource(struct pnp_dev *dev, unsigned int option_flags, resource_size_t min, resource_size_t max, resource_size_t align, resource_size_t size, unsigned char flags); -int pnp_register_mem_resource(struct pnp_dev *dev, struct pnp_option *option, +int pnp_register_mem_resource(struct pnp_dev *dev, unsigned int option_flags, resource_size_t min, resource_size_t max, resource_size_t align, resource_size_t size, unsigned char flags); + +static inline int pnp_option_is_dependent(struct pnp_option *option) +{ + return option->flags & PNP_OPTION_DEPENDENT ? 1 : 0; +} + +static inline unsigned int pnp_option_set(struct pnp_option *option) +{ + return (option->flags >> PNP_OPTION_SET_SHIFT) & PNP_OPTION_SET_MASK; +} + +static inline unsigned int pnp_option_priority(struct pnp_option *option) +{ + return (option->flags >> PNP_OPTION_PRIORITY_SHIFT) & + PNP_OPTION_PRIORITY_MASK; +} + +static inline unsigned int pnp_new_dependent_set(struct pnp_dev *dev, + int priority) +{ + unsigned int flags; + + if (priority > PNP_RES_PRIORITY_FUNCTIONAL) { + dev_warn(&dev->dev, "invalid dependent option priority %d " + "clipped to %d", priority, + PNP_RES_PRIORITY_INVALID); + priority = PNP_RES_PRIORITY_INVALID; + } + + flags = PNP_OPTION_DEPENDENT | + ((dev->num_dependent_sets & PNP_OPTION_SET_MASK) << + PNP_OPTION_SET_SHIFT) | + ((priority & PNP_OPTION_PRIORITY_MASK) << + PNP_OPTION_PRIORITY_SHIFT); + + dev->num_dependent_sets++; + + return flags; +} + +char *pnp_option_priority_name(struct pnp_option *option); +void dbg_pnp_show_option(struct pnp_dev *dev, struct pnp_option *option); + void pnp_init_resources(struct pnp_dev *dev); void pnp_fixup_device(struct pnp_dev *dev); -void pnp_free_option(struct pnp_option *option); +void pnp_free_options(struct pnp_dev *dev); int __pnp_add_device(struct pnp_dev *dev); void __pnp_remove_device(struct pnp_dev *dev); diff --git a/drivers/pnp/core.c b/drivers/pnp/core.c index 7182da92aec3..a411582bcd72 100644 --- a/drivers/pnp/core.c +++ b/drivers/pnp/core.c @@ -118,10 +118,9 @@ static void pnp_release_device(struct device *dmdev) { struct pnp_dev *dev = to_pnp_dev(dmdev); - pnp_free_option(dev->independent); - pnp_free_option(dev->dependent); pnp_free_ids(dev); pnp_free_resources(dev); + pnp_free_options(dev); kfree(dev); } @@ -135,6 +134,7 @@ struct pnp_dev *pnp_alloc_dev(struct pnp_protocol *protocol, int id, char *pnpid return NULL; INIT_LIST_HEAD(&dev->resources); + INIT_LIST_HEAD(&dev->options); dev->protocol = protocol; dev->number = id; dev->dma_mask = DMA_24BIT_MASK; diff --git a/drivers/pnp/interface.c b/drivers/pnp/interface.c index 7a9fb5544b80..a876ecf7028c 100644 --- a/drivers/pnp/interface.c +++ b/drivers/pnp/interface.c @@ -3,6 +3,8 @@ * * Some code, especially possible resource dumping is based on isapnp_proc.c (c) Jaroslav Kysela * Copyright 2002 Adam Belay + * Copyright (C) 2008 Hewlett-Packard Development Company, L.P. + * Bjorn Helgaas */ #include @@ -184,39 +186,22 @@ static void pnp_print_mem(pnp_info_buffer_t * buffer, char *space, } static void pnp_print_option(pnp_info_buffer_t * buffer, char *space, - struct pnp_option *option, int dep) + struct pnp_option *option) { - char *s; - struct pnp_port *port; - struct pnp_irq *irq; - struct pnp_dma *dma; - struct pnp_mem *mem; - - if (dep) { - switch (option->priority) { - case PNP_RES_PRIORITY_PREFERRED: - s = "preferred"; - break; - case PNP_RES_PRIORITY_ACCEPTABLE: - s = "acceptable"; - break; - case PNP_RES_PRIORITY_FUNCTIONAL: - s = "functional"; - break; - default: - s = "invalid"; - } - pnp_printf(buffer, "Dependent: %02i - Priority %s\n", dep, s); + switch (option->type) { + case IORESOURCE_IO: + pnp_print_port(buffer, space, &option->u.port); + break; + case IORESOURCE_MEM: + pnp_print_mem(buffer, space, &option->u.mem); + break; + case IORESOURCE_IRQ: + pnp_print_irq(buffer, space, &option->u.irq); + break; + case IORESOURCE_DMA: + pnp_print_dma(buffer, space, &option->u.dma); + break; } - - for (port = option->port; port; port = port->next) - pnp_print_port(buffer, space, port); - for (irq = option->irq; irq; irq = irq->next) - pnp_print_irq(buffer, space, irq); - for (dma = option->dma; dma; dma = dma->next) - pnp_print_dma(buffer, space, dma); - for (mem = option->mem; mem; mem = mem->next) - pnp_print_mem(buffer, space, mem); } static ssize_t pnp_show_options(struct device *dmdev, @@ -224,9 +209,9 @@ static ssize_t pnp_show_options(struct device *dmdev, { struct pnp_dev *dev = to_pnp_dev(dmdev); pnp_info_buffer_t *buffer; - struct pnp_option *independent = dev->independent; - struct pnp_option *dependent = dev->dependent; - int ret, dep = 1; + struct pnp_option *option; + int ret, dep = 0, set = 0; + char *indent; buffer = pnp_alloc(sizeof(pnp_info_buffer_t)); if (!buffer) @@ -235,14 +220,24 @@ static ssize_t pnp_show_options(struct device *dmdev, buffer->len = PAGE_SIZE; buffer->buffer = buf; buffer->curr = buffer->buffer; - if (independent) - pnp_print_option(buffer, "", independent, 0); - while (dependent) { - pnp_print_option(buffer, " ", dependent, dep); - dependent = dependent->next; - dep++; + list_for_each_entry(option, &dev->options, list) { + if (pnp_option_is_dependent(option)) { + indent = " "; + if (!dep || pnp_option_set(option) != set) { + set = pnp_option_set(option); + dep = 1; + pnp_printf(buffer, "Dependent: %02i - " + "Priority %s\n", set, + pnp_option_priority_name(option)); + } + } else { + dep = 0; + indent = ""; + } + pnp_print_option(buffer, indent, option); } + ret = (buffer->curr - buf); kfree(buffer); return ret; diff --git a/drivers/pnp/isapnp/core.c b/drivers/pnp/isapnp/core.c index 53cc4d6133e6..101a835e8759 100644 --- a/drivers/pnp/isapnp/core.c +++ b/drivers/pnp/isapnp/core.c @@ -429,7 +429,7 @@ static struct pnp_dev *__init isapnp_parse_device(struct pnp_card *card, * Add IRQ resource to resources list. */ static void __init isapnp_parse_irq_resource(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, int size) { unsigned char tmp[3]; @@ -446,27 +446,27 @@ static void __init isapnp_parse_irq_resource(struct pnp_dev *dev, if (size > 2) flags = tmp[2]; - pnp_register_irq_resource(dev, option, &map, flags); + pnp_register_irq_resource(dev, option_flags, &map, flags); } /* * Add DMA resource to resources list. */ static void __init isapnp_parse_dma_resource(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, int size) { unsigned char tmp[2]; isapnp_peek(tmp, size); - pnp_register_dma_resource(dev, option, tmp[0], tmp[1]); + pnp_register_dma_resource(dev, option_flags, tmp[0], tmp[1]); } /* * Add port resource to resources list. */ static void __init isapnp_parse_port_resource(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, int size) { unsigned char tmp[7]; @@ -479,14 +479,15 @@ static void __init isapnp_parse_port_resource(struct pnp_dev *dev, align = tmp[5]; len = tmp[6]; flags = tmp[0] ? IORESOURCE_IO_16BIT_ADDR : 0; - pnp_register_port_resource(dev, option, min, max, align, len, flags); + pnp_register_port_resource(dev, option_flags, + min, max, align, len, flags); } /* * Add fixed port resource to resources list. */ static void __init isapnp_parse_fixed_port_resource(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, int size) { unsigned char tmp[3]; @@ -495,7 +496,7 @@ static void __init isapnp_parse_fixed_port_resource(struct pnp_dev *dev, isapnp_peek(tmp, size); base = (tmp[1] << 8) | tmp[0]; len = tmp[2]; - pnp_register_port_resource(dev, option, base, base, 0, len, + pnp_register_port_resource(dev, option_flags, base, base, 0, len, IORESOURCE_IO_FIXED); } @@ -503,7 +504,7 @@ static void __init isapnp_parse_fixed_port_resource(struct pnp_dev *dev, * Add memory resource to resources list. */ static void __init isapnp_parse_mem_resource(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, int size) { unsigned char tmp[9]; @@ -516,14 +517,15 @@ static void __init isapnp_parse_mem_resource(struct pnp_dev *dev, align = (tmp[6] << 8) | tmp[5]; len = ((tmp[8] << 8) | tmp[7]) << 8; flags = tmp[0]; - pnp_register_mem_resource(dev, option, min, max, align, len, flags); + pnp_register_mem_resource(dev, option_flags, + min, max, align, len, flags); } /* * Add 32-bit memory resource to resources list. */ static void __init isapnp_parse_mem32_resource(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, int size) { unsigned char tmp[17]; @@ -536,14 +538,15 @@ static void __init isapnp_parse_mem32_resource(struct pnp_dev *dev, align = (tmp[12] << 24) | (tmp[11] << 16) | (tmp[10] << 8) | tmp[9]; len = (tmp[16] << 24) | (tmp[15] << 16) | (tmp[14] << 8) | tmp[13]; flags = tmp[0]; - pnp_register_mem_resource(dev, option, min, max, align, len, flags); + pnp_register_mem_resource(dev, option_flags, + min, max, align, len, flags); } /* * Add 32-bit fixed memory resource to resources list. */ static void __init isapnp_parse_fixed_mem32_resource(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, int size) { unsigned char tmp[9]; @@ -554,7 +557,7 @@ static void __init isapnp_parse_fixed_mem32_resource(struct pnp_dev *dev, base = (tmp[4] << 24) | (tmp[3] << 16) | (tmp[2] << 8) | tmp[1]; len = (tmp[8] << 24) | (tmp[7] << 16) | (tmp[6] << 8) | tmp[5]; flags = tmp[0]; - pnp_register_mem_resource(dev, option, base, base, 0, len, flags); + pnp_register_mem_resource(dev, option_flags, base, base, 0, len, flags); } /* @@ -584,18 +587,14 @@ static int __init isapnp_create_device(struct pnp_card *card, { int number = 0, skip = 0, priority, compat = 0; unsigned char type, tmp[17]; - struct pnp_option *option, *option_independent; + unsigned int option_flags; struct pnp_dev *dev; u32 eisa_id; char id[8]; if ((dev = isapnp_parse_device(card, size, number++)) == NULL) return 1; - option_independent = option = pnp_register_independent_option(dev); - if (!option) { - kfree(dev); - return 1; - } + option_flags = 0; pnp_add_card_device(card, dev); while (1) { @@ -612,12 +611,7 @@ static int __init isapnp_create_device(struct pnp_card *card, return 1; size = 0; skip = 0; - option = pnp_register_independent_option(dev); - option_independent = option; - if (!option) { - kfree(dev); - return 1; - } + option_flags = 0; pnp_add_card_device(card, dev); } else { skip = 1; @@ -638,13 +632,13 @@ static int __init isapnp_create_device(struct pnp_card *card, case _STAG_IRQ: if (size < 2 || size > 3) goto __skip; - isapnp_parse_irq_resource(dev, option, size); + isapnp_parse_irq_resource(dev, option_flags, size); size = 0; break; case _STAG_DMA: if (size != 2) goto __skip; - isapnp_parse_dma_resource(dev, option, size); + isapnp_parse_dma_resource(dev, option_flags, size); size = 0; break; case _STAG_STARTDEP: @@ -656,29 +650,24 @@ static int __init isapnp_create_device(struct pnp_card *card, priority = tmp[0]; size = 0; } - option = pnp_register_dependent_option(dev, priority); - if (!option) - return 1; + option_flags = pnp_new_dependent_set(dev, priority); break; case _STAG_ENDDEP: if (size != 0) goto __skip; - if (option_independent == option) - dev_warn(&dev->dev, "missing " - "_STAG_STARTDEP tag\n"); - option = option_independent; - dev_dbg(&dev->dev, "end dependent options\n"); + option_flags = 0; break; case _STAG_IOPORT: if (size != 7) goto __skip; - isapnp_parse_port_resource(dev, option, size); + isapnp_parse_port_resource(dev, option_flags, size); size = 0; break; case _STAG_FIXEDIO: if (size != 3) goto __skip; - isapnp_parse_fixed_port_resource(dev, option, size); + isapnp_parse_fixed_port_resource(dev, option_flags, + size); size = 0; break; case _STAG_VENDOR: @@ -686,7 +675,7 @@ static int __init isapnp_create_device(struct pnp_card *card, case _LTAG_MEMRANGE: if (size != 9) goto __skip; - isapnp_parse_mem_resource(dev, option, size); + isapnp_parse_mem_resource(dev, option_flags, size); size = 0; break; case _LTAG_ANSISTR: @@ -701,13 +690,14 @@ static int __init isapnp_create_device(struct pnp_card *card, case _LTAG_MEM32RANGE: if (size != 17) goto __skip; - isapnp_parse_mem32_resource(dev, option, size); + isapnp_parse_mem32_resource(dev, option_flags, size); size = 0; break; case _LTAG_FIXEDMEM32RANGE: if (size != 9) goto __skip; - isapnp_parse_fixed_mem32_resource(dev, option, size); + isapnp_parse_fixed_mem32_resource(dev, option_flags, + size); size = 0; break; case _STAG_END: diff --git a/drivers/pnp/manager.c b/drivers/pnp/manager.c index a20accb5ef8f..b526eaad3f6c 100644 --- a/drivers/pnp/manager.c +++ b/drivers/pnp/manager.c @@ -3,6 +3,8 @@ * * based on isapnp.c resource management (c) Jaroslav Kysela * Copyright 2003 Adam Belay + * Copyright (C) 2008 Hewlett-Packard Development Company, L.P. + * Bjorn Helgaas */ #include @@ -228,102 +230,51 @@ static void pnp_clean_resource_table(struct pnp_dev *dev) /** * pnp_assign_resources - assigns resources to the device based on the specified dependent number * @dev: pointer to the desired device - * @depnum: the dependent function number - * - * Only set depnum to 0 if the device does not have dependent options. + * @set: the dependent function number */ -static int pnp_assign_resources(struct pnp_dev *dev, int depnum) +static int pnp_assign_resources(struct pnp_dev *dev, int set) { - struct pnp_port *port; - struct pnp_mem *mem; - struct pnp_irq *irq; - struct pnp_dma *dma; + struct pnp_option *option; int nport = 0, nmem = 0, nirq = 0, ndma = 0; + int ret = 0; - dbg_pnp_show_resources(dev, "before pnp_assign_resources"); + dev_dbg(&dev->dev, "pnp_assign_resources, try dependent set %d\n", set); mutex_lock(&pnp_res_mutex); pnp_clean_resource_table(dev); - if (dev->independent) { - dev_dbg(&dev->dev, "assigning independent options\n"); - port = dev->independent->port; - mem = dev->independent->mem; - irq = dev->independent->irq; - dma = dev->independent->dma; - while (port) { - if (pnp_assign_port(dev, port, nport) < 0) - goto fail; - nport++; - port = port->next; - } - while (mem) { - if (pnp_assign_mem(dev, mem, nmem) < 0) - goto fail; - nmem++; - mem = mem->next; - } - while (irq) { - if (pnp_assign_irq(dev, irq, nirq) < 0) - goto fail; - nirq++; - irq = irq->next; - } - while (dma) { - if (pnp_assign_dma(dev, dma, ndma) < 0) - goto fail; - ndma++; - dma = dma->next; - } - } - if (depnum) { - struct pnp_option *dep; - int i; - - dev_dbg(&dev->dev, "assigning dependent option %d\n", depnum); - for (i = 1, dep = dev->dependent; i < depnum; - i++, dep = dep->next) - if (!dep) - goto fail; - port = dep->port; - mem = dep->mem; - irq = dep->irq; - dma = dep->dma; - while (port) { - if (pnp_assign_port(dev, port, nport) < 0) - goto fail; - nport++; - port = port->next; - } - while (mem) { - if (pnp_assign_mem(dev, mem, nmem) < 0) - goto fail; - nmem++; - mem = mem->next; - } - while (irq) { - if (pnp_assign_irq(dev, irq, nirq) < 0) - goto fail; - nirq++; - irq = irq->next; - } - while (dma) { - if (pnp_assign_dma(dev, dma, ndma) < 0) - goto fail; - ndma++; - dma = dma->next; + list_for_each_entry(option, &dev->options, list) { + if (pnp_option_is_dependent(option) && + pnp_option_set(option) != set) + continue; + + switch (option->type) { + case IORESOURCE_IO: + ret = pnp_assign_port(dev, &option->u.port, nport++); + break; + case IORESOURCE_MEM: + ret = pnp_assign_mem(dev, &option->u.mem, nmem++); + break; + case IORESOURCE_IRQ: + ret = pnp_assign_irq(dev, &option->u.irq, nirq++); + break; + case IORESOURCE_DMA: + ret = pnp_assign_dma(dev, &option->u.dma, ndma++); + break; + default: + ret = -EINVAL; + break; } - } else if (dev->dependent) - goto fail; - - mutex_unlock(&pnp_res_mutex); - dbg_pnp_show_resources(dev, "after pnp_assign_resources"); - return 1; + if (ret < 0) + break; + } -fail: - pnp_clean_resource_table(dev); mutex_unlock(&pnp_res_mutex); - dbg_pnp_show_resources(dev, "after pnp_assign_resources (failed)"); - return 0; + if (ret < 0) { + dev_dbg(&dev->dev, "pnp_assign_resources failed (%d)\n", ret); + pnp_clean_resource_table(dev); + } else + dbg_pnp_show_resources(dev, "pnp_assign_resources succeeded"); + return ret; } /** @@ -332,29 +283,25 @@ fail: */ int pnp_auto_config_dev(struct pnp_dev *dev) { - struct pnp_option *dep; - int i = 1; + int i, ret; if (!pnp_can_configure(dev)) { dev_dbg(&dev->dev, "configuration not supported\n"); return -ENODEV; } - if (!dev->dependent) { - if (pnp_assign_resources(dev, 0)) + ret = pnp_assign_resources(dev, 0); + if (ret == 0) + return 0; + + for (i = 1; i < dev->num_dependent_sets; i++) { + ret = pnp_assign_resources(dev, i); + if (ret == 0) return 0; - } else { - dep = dev->dependent; - do { - if (pnp_assign_resources(dev, i)) - return 0; - dep = dep->next; - i++; - } while (dep); } dev_err(&dev->dev, "unable to assign resources\n"); - return -EBUSY; + return ret; } /** diff --git a/drivers/pnp/pnpacpi/rsparser.c b/drivers/pnp/pnpacpi/rsparser.c index e114b3d2b933..c2f59f4d20bc 100644 --- a/drivers/pnp/pnpacpi/rsparser.c +++ b/drivers/pnp/pnpacpi/rsparser.c @@ -407,7 +407,7 @@ int pnpacpi_parse_allocated_resource(struct pnp_dev *dev) } static __init void pnpacpi_parse_dma_option(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, struct acpi_resource_dma *p) { int i; @@ -420,11 +420,11 @@ static __init void pnpacpi_parse_dma_option(struct pnp_dev *dev, map |= 1 << p->channels[i]; flags = dma_flags(p->type, p->bus_master, p->transfer); - pnp_register_dma_resource(dev, option, map, flags); + pnp_register_dma_resource(dev, option_flags, map, flags); } static __init void pnpacpi_parse_irq_option(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, struct acpi_resource_irq *p) { int i; @@ -440,11 +440,11 @@ static __init void pnpacpi_parse_irq_option(struct pnp_dev *dev, __set_bit(p->interrupts[i], map.bits); flags = irq_flags(p->triggering, p->polarity, p->sharable); - pnp_register_irq_resource(dev, option, &map, flags); + pnp_register_irq_resource(dev, option_flags, &map, flags); } static __init void pnpacpi_parse_ext_irq_option(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, struct acpi_resource_extended_irq *p) { int i; @@ -467,11 +467,11 @@ static __init void pnpacpi_parse_ext_irq_option(struct pnp_dev *dev, } flags = irq_flags(p->triggering, p->polarity, p->sharable); - pnp_register_irq_resource(dev, option, &map, flags); + pnp_register_irq_resource(dev, option_flags, &map, flags); } static __init void pnpacpi_parse_port_option(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, struct acpi_resource_io *io) { unsigned char flags = 0; @@ -481,23 +481,23 @@ static __init void pnpacpi_parse_port_option(struct pnp_dev *dev, if (io->io_decode == ACPI_DECODE_16) flags = IORESOURCE_IO_16BIT_ADDR; - pnp_register_port_resource(dev, option, io->minimum, io->maximum, + pnp_register_port_resource(dev, option_flags, io->minimum, io->maximum, io->alignment, io->address_length, flags); } static __init void pnpacpi_parse_fixed_port_option(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, struct acpi_resource_fixed_io *io) { if (io->address_length == 0) return; - pnp_register_port_resource(dev, option, io->address, io->address, 0, - io->address_length, IORESOURCE_IO_FIXED); + pnp_register_port_resource(dev, option_flags, io->address, io->address, + 0, io->address_length, IORESOURCE_IO_FIXED); } static __init void pnpacpi_parse_mem24_option(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, struct acpi_resource_memory24 *p) { unsigned char flags = 0; @@ -507,12 +507,12 @@ static __init void pnpacpi_parse_mem24_option(struct pnp_dev *dev, if (p->write_protect == ACPI_READ_WRITE_MEMORY) flags = IORESOURCE_MEM_WRITEABLE; - pnp_register_mem_resource(dev, option, p->minimum, p->maximum, + pnp_register_mem_resource(dev, option_flags, p->minimum, p->maximum, p->alignment, p->address_length, flags); } static __init void pnpacpi_parse_mem32_option(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, struct acpi_resource_memory32 *p) { unsigned char flags = 0; @@ -522,12 +522,12 @@ static __init void pnpacpi_parse_mem32_option(struct pnp_dev *dev, if (p->write_protect == ACPI_READ_WRITE_MEMORY) flags = IORESOURCE_MEM_WRITEABLE; - pnp_register_mem_resource(dev, option, p->minimum, p->maximum, + pnp_register_mem_resource(dev, option_flags, p->minimum, p->maximum, p->alignment, p->address_length, flags); } static __init void pnpacpi_parse_fixed_mem32_option(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, struct acpi_resource_fixed_memory32 *p) { unsigned char flags = 0; @@ -537,12 +537,12 @@ static __init void pnpacpi_parse_fixed_mem32_option(struct pnp_dev *dev, if (p->write_protect == ACPI_READ_WRITE_MEMORY) flags = IORESOURCE_MEM_WRITEABLE; - pnp_register_mem_resource(dev, option, p->address, p->address, + pnp_register_mem_resource(dev, option_flags, p->address, p->address, 0, p->address_length, flags); } static __init void pnpacpi_parse_address_option(struct pnp_dev *dev, - struct pnp_option *option, + unsigned int option_flags, struct acpi_resource *r) { struct acpi_resource_address64 addr, *p = &addr; @@ -562,18 +562,18 @@ static __init void pnpacpi_parse_address_option(struct pnp_dev *dev, if (p->resource_type == ACPI_MEMORY_RANGE) { if (p->info.mem.write_protect == ACPI_READ_WRITE_MEMORY) flags = IORESOURCE_MEM_WRITEABLE; - pnp_register_mem_resource(dev, option, p->minimum, p->minimum, - 0, p->address_length, flags); + pnp_register_mem_resource(dev, option_flags, p->minimum, + p->minimum, 0, p->address_length, + flags); } else if (p->resource_type == ACPI_IO_RANGE) - pnp_register_port_resource(dev, option, p->minimum, p->minimum, - 0, p->address_length, + pnp_register_port_resource(dev, option_flags, p->minimum, + p->minimum, 0, p->address_length, IORESOURCE_IO_FIXED); } struct acpipnp_parse_option_s { - struct pnp_option *option; - struct pnp_option *option_independent; struct pnp_dev *dev; + unsigned int option_flags; }; static __init acpi_status pnpacpi_option_resource(struct acpi_resource *res, @@ -582,15 +582,15 @@ static __init acpi_status pnpacpi_option_resource(struct acpi_resource *res, int priority; struct acpipnp_parse_option_s *parse_data = data; struct pnp_dev *dev = parse_data->dev; - struct pnp_option *option = parse_data->option; + unsigned int option_flags = parse_data->option_flags; switch (res->type) { case ACPI_RESOURCE_TYPE_IRQ: - pnpacpi_parse_irq_option(dev, option, &res->data.irq); + pnpacpi_parse_irq_option(dev, option_flags, &res->data.irq); break; case ACPI_RESOURCE_TYPE_DMA: - pnpacpi_parse_dma_option(dev, option, &res->data.dma); + pnpacpi_parse_dma_option(dev, option_flags, &res->data.dma); break; case ACPI_RESOURCE_TYPE_START_DEPENDENT: @@ -610,31 +610,19 @@ static __init acpi_status pnpacpi_option_resource(struct acpi_resource *res, priority = PNP_RES_PRIORITY_INVALID; break; } - /* TBD: Consider performance/robustness bits */ - option = pnp_register_dependent_option(dev, priority); - if (!option) - return AE_ERROR; - parse_data->option = option; + parse_data->option_flags = pnp_new_dependent_set(dev, priority); break; case ACPI_RESOURCE_TYPE_END_DEPENDENT: - /*only one EndDependentFn is allowed */ - if (!parse_data->option_independent) { - dev_warn(&dev->dev, "more than one EndDependentFn " - "in _PRS\n"); - return AE_ERROR; - } - parse_data->option = parse_data->option_independent; - parse_data->option_independent = NULL; - dev_dbg(&dev->dev, "end dependent options\n"); + parse_data->option_flags = 0; break; case ACPI_RESOURCE_TYPE_IO: - pnpacpi_parse_port_option(dev, option, &res->data.io); + pnpacpi_parse_port_option(dev, option_flags, &res->data.io); break; case ACPI_RESOURCE_TYPE_FIXED_IO: - pnpacpi_parse_fixed_port_option(dev, option, + pnpacpi_parse_fixed_port_option(dev, option_flags, &res->data.fixed_io); break; @@ -643,29 +631,31 @@ static __init acpi_status pnpacpi_option_resource(struct acpi_resource *res, break; case ACPI_RESOURCE_TYPE_MEMORY24: - pnpacpi_parse_mem24_option(dev, option, &res->data.memory24); + pnpacpi_parse_mem24_option(dev, option_flags, + &res->data.memory24); break; case ACPI_RESOURCE_TYPE_MEMORY32: - pnpacpi_parse_mem32_option(dev, option, &res->data.memory32); + pnpacpi_parse_mem32_option(dev, option_flags, + &res->data.memory32); break; case ACPI_RESOURCE_TYPE_FIXED_MEMORY32: - pnpacpi_parse_fixed_mem32_option(dev, option, + pnpacpi_parse_fixed_mem32_option(dev, option_flags, &res->data.fixed_memory32); break; case ACPI_RESOURCE_TYPE_ADDRESS16: case ACPI_RESOURCE_TYPE_ADDRESS32: case ACPI_RESOURCE_TYPE_ADDRESS64: - pnpacpi_parse_address_option(dev, option, res); + pnpacpi_parse_address_option(dev, option_flags, res); break; case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: break; case ACPI_RESOURCE_TYPE_EXTENDED_IRQ: - pnpacpi_parse_ext_irq_option(dev, option, + pnpacpi_parse_ext_irq_option(dev, option_flags, &res->data.extended_irq); break; @@ -689,12 +679,9 @@ int __init pnpacpi_parse_resource_option_data(struct pnp_dev *dev) dev_dbg(&dev->dev, "parse resource options\n"); - parse_data.option = pnp_register_independent_option(dev); - if (!parse_data.option) - return -ENOMEM; - - parse_data.option_independent = parse_data.option; parse_data.dev = dev; + parse_data.option_flags = 0; + status = acpi_walk_resources(handle, METHOD_NAME__PRS, pnpacpi_option_resource, &parse_data); diff --git a/drivers/pnp/pnpbios/rsparser.c b/drivers/pnp/pnpbios/rsparser.c index db23ba78d39c..ca567671379e 100644 --- a/drivers/pnp/pnpbios/rsparser.c +++ b/drivers/pnp/pnpbios/rsparser.c @@ -216,7 +216,7 @@ len_err: static __init void pnpbios_parse_mem_option(struct pnp_dev *dev, unsigned char *p, int size, - struct pnp_option *option) + unsigned int option_flags) { resource_size_t min, max, align, len; unsigned char flags; @@ -226,12 +226,13 @@ static __init void pnpbios_parse_mem_option(struct pnp_dev *dev, align = (p[9] << 8) | p[8]; len = ((p[11] << 8) | p[10]) << 8; flags = p[3]; - pnp_register_mem_resource(dev, option, min, max, align, len, flags); + pnp_register_mem_resource(dev, option_flags, min, max, align, len, + flags); } static __init void pnpbios_parse_mem32_option(struct pnp_dev *dev, unsigned char *p, int size, - struct pnp_option *option) + unsigned int option_flags) { resource_size_t min, max, align, len; unsigned char flags; @@ -241,12 +242,13 @@ static __init void pnpbios_parse_mem32_option(struct pnp_dev *dev, align = (p[15] << 24) | (p[14] << 16) | (p[13] << 8) | p[12]; len = (p[19] << 24) | (p[18] << 16) | (p[17] << 8) | p[16]; flags = p[3]; - pnp_register_mem_resource(dev, option, min, max, align, len, flags); + pnp_register_mem_resource(dev, option_flags, min, max, align, len, + flags); } static __init void pnpbios_parse_fixed_mem32_option(struct pnp_dev *dev, unsigned char *p, int size, - struct pnp_option *option) + unsigned int option_flags) { resource_size_t base, len; unsigned char flags; @@ -254,12 +256,12 @@ static __init void pnpbios_parse_fixed_mem32_option(struct pnp_dev *dev, base = (p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4]; len = (p[11] << 24) | (p[10] << 16) | (p[9] << 8) | p[8]; flags = p[3]; - pnp_register_mem_resource(dev, option, base, base, 0, len, flags); + pnp_register_mem_resource(dev, option_flags, base, base, 0, len, flags); } static __init void pnpbios_parse_irq_option(struct pnp_dev *dev, unsigned char *p, int size, - struct pnp_option *option) + unsigned int option_flags) { unsigned long bits; pnp_irq_mask_t map; @@ -273,19 +275,19 @@ static __init void pnpbios_parse_irq_option(struct pnp_dev *dev, if (size > 2) flags = p[3]; - pnp_register_irq_resource(dev, option, &map, flags); + pnp_register_irq_resource(dev, option_flags, &map, flags); } static __init void pnpbios_parse_dma_option(struct pnp_dev *dev, unsigned char *p, int size, - struct pnp_option *option) + unsigned int option_flags) { - pnp_register_dma_resource(dev, option, p[1], p[2]); + pnp_register_dma_resource(dev, option_flags, p[1], p[2]); } static __init void pnpbios_parse_port_option(struct pnp_dev *dev, unsigned char *p, int size, - struct pnp_option *option) + unsigned int option_flags) { resource_size_t min, max, align, len; unsigned char flags; @@ -295,38 +297,35 @@ static __init void pnpbios_parse_port_option(struct pnp_dev *dev, align = p[6]; len = p[7]; flags = p[1] ? IORESOURCE_IO_16BIT_ADDR : 0; - pnp_register_port_resource(dev, option, min, max, align, len, flags); + pnp_register_port_resource(dev, option_flags, min, max, align, len, + flags); } static __init void pnpbios_parse_fixed_port_option(struct pnp_dev *dev, unsigned char *p, int size, - struct pnp_option *option) + unsigned int option_flags) { resource_size_t base, len; base = (p[2] << 8) | p[1]; len = p[3]; - pnp_register_port_resource(dev, option, base, base, 0, len, + pnp_register_port_resource(dev, option_flags, base, base, 0, len, IORESOURCE_IO_FIXED); } static __init unsigned char * pnpbios_parse_resource_option_data(unsigned char *p, unsigned char *end, - struct pnp_dev *dev) + struct pnp_dev *dev) { unsigned int len, tag; int priority; - struct pnp_option *option, *option_independent; + unsigned int option_flags; if (!p) return NULL; dev_dbg(&dev->dev, "parse resource options\n"); - - option_independent = option = pnp_register_independent_option(dev); - if (!option) - return NULL; - + option_flags = 0; while ((char *)p < (char *)end) { /* determine the type of tag */ @@ -343,37 +342,38 @@ pnpbios_parse_resource_option_data(unsigned char *p, unsigned char *end, case LARGE_TAG_MEM: if (len != 9) goto len_err; - pnpbios_parse_mem_option(dev, p, len, option); + pnpbios_parse_mem_option(dev, p, len, option_flags); break; case LARGE_TAG_MEM32: if (len != 17) goto len_err; - pnpbios_parse_mem32_option(dev, p, len, option); + pnpbios_parse_mem32_option(dev, p, len, option_flags); break; case LARGE_TAG_FIXEDMEM32: if (len != 9) goto len_err; - pnpbios_parse_fixed_mem32_option(dev, p, len, option); + pnpbios_parse_fixed_mem32_option(dev, p, len, + option_flags); break; case SMALL_TAG_IRQ: if (len < 2 || len > 3) goto len_err; - pnpbios_parse_irq_option(dev, p, len, option); + pnpbios_parse_irq_option(dev, p, len, option_flags); break; case SMALL_TAG_DMA: if (len != 2) goto len_err; - pnpbios_parse_dma_option(dev, p, len, option); + pnpbios_parse_dma_option(dev, p, len, option_flags); break; case SMALL_TAG_PORT: if (len != 7) goto len_err; - pnpbios_parse_port_option(dev, p, len, option); + pnpbios_parse_port_option(dev, p, len, option_flags); break; case SMALL_TAG_VENDOR: @@ -383,7 +383,8 @@ pnpbios_parse_resource_option_data(unsigned char *p, unsigned char *end, case SMALL_TAG_FIXEDPORT: if (len != 3) goto len_err; - pnpbios_parse_fixed_port_option(dev, p, len, option); + pnpbios_parse_fixed_port_option(dev, p, len, + option_flags); break; case SMALL_TAG_STARTDEP: @@ -392,19 +393,13 @@ pnpbios_parse_resource_option_data(unsigned char *p, unsigned char *end, priority = PNP_RES_PRIORITY_ACCEPTABLE; if (len > 0) priority = p[1]; - option = pnp_register_dependent_option(dev, priority); - if (!option) - return NULL; + option_flags = pnp_new_dependent_set(dev, priority); break; case SMALL_TAG_ENDDEP: if (len != 0) goto len_err; - if (option_independent == option) - dev_warn(&dev->dev, "missing " - "SMALL_TAG_STARTDEP tag\n"); - option = option_independent; - dev_dbg(&dev->dev, "end dependent options\n"); + option_flags = 0; break; case SMALL_TAG_END: diff --git a/drivers/pnp/quirks.c b/drivers/pnp/quirks.c index e8515ce0d296..55f55ed72dc7 100644 --- a/drivers/pnp/quirks.c +++ b/drivers/pnp/quirks.c @@ -5,6 +5,8 @@ * when building up the resource structure for the first time. * * Copyright (c) 2000 Peter Denison + * Copyright (C) 2008 Hewlett-Packard Development Company, L.P. + * Bjorn Helgaas * * Heavily based on PCI quirks handling which is * @@ -20,189 +22,207 @@ #include #include "base.h" +static void quirk_awe32_add_ports(struct pnp_dev *dev, + struct pnp_option *option, + unsigned int offset) +{ + struct pnp_option *new_option; + + new_option = kmalloc(sizeof(struct pnp_option), GFP_KERNEL); + if (!new_option) { + dev_err(&dev->dev, "couldn't add ioport region to option set " + "%d\n", pnp_option_set(option)); + return; + } + + *new_option = *option; + new_option->u.port.min += offset; + new_option->u.port.max += offset; + list_add(&new_option->list, &option->list); + + dev_info(&dev->dev, "added ioport region %#llx-%#llx to set %d\n", + (unsigned long long) new_option->u.port.min, + (unsigned long long) new_option->u.port.max, + pnp_option_set(option)); +} + static void quirk_awe32_resources(struct pnp_dev *dev) { - struct pnp_port *port, *port2, *port3; - struct pnp_option *res = dev->dependent; + struct pnp_option *option; + unsigned int set = ~0; /* - * Unfortunately the isapnp_add_port_resource is too tightly bound - * into the PnP discovery sequence, and cannot be used. Link in the - * two extra ports (at offset 0x400 and 0x800 from the one given) by - * hand. + * Add two extra ioport regions (at offset 0x400 and 0x800 from the + * one given) to every dependent option set. */ - for (; res; res = res->next) { - port2 = pnp_alloc(sizeof(struct pnp_port)); - if (!port2) - return; - port3 = pnp_alloc(sizeof(struct pnp_port)); - if (!port3) { - kfree(port2); - return; + list_for_each_entry(option, &dev->options, list) { + if (pnp_option_is_dependent(option) && + pnp_option_set(option) != set) { + set = pnp_option_set(option); + quirk_awe32_add_ports(dev, option, 0x800); + quirk_awe32_add_ports(dev, option, 0x400); } - port = res->port; - memcpy(port2, port, sizeof(struct pnp_port)); - memcpy(port3, port, sizeof(struct pnp_port)); - port->next = port2; - port2->next = port3; - port2->min += 0x400; - port2->max += 0x400; - port3->min += 0x800; - port3->max += 0x800; - dev_info(&dev->dev, - "AWE32 quirk - added ioports 0x%lx and 0x%lx\n", - (unsigned long)port2->min, - (unsigned long)port3->min); } } static void quirk_cmi8330_resources(struct pnp_dev *dev) { - struct pnp_option *res = dev->dependent; - unsigned long tmp; - - for (; res; res = res->next) { - - struct pnp_irq *irq; - struct pnp_dma *dma; + struct pnp_option *option; + struct pnp_irq *irq; + struct pnp_dma *dma; - for (irq = res->irq; irq; irq = irq->next) { - /* Valid irqs are 5, 7, 10 */ - tmp = 0x04A0; - bitmap_copy(irq->map.bits, &tmp, 16); - } + list_for_each_entry(option, &dev->options, list) { + if (!pnp_option_is_dependent(option)) + continue; - for (dma = res->dma; dma; dma = dma->next) { - /* Valid 8bit dma channels are 1,3 */ + if (option->type == IORESOURCE_IRQ) { + irq = &option->u.irq; + bitmap_zero(irq->map.bits, PNP_IRQ_NR); + __set_bit(5, irq->map.bits); + __set_bit(7, irq->map.bits); + __set_bit(10, irq->map.bits); + dev_info(&dev->dev, "set possible IRQs in " + "option set %d to 5, 7, 10\n", + pnp_option_set(option)); + } else if (option->type == IORESOURCE_DMA) { + dma = &option->u.dma; if ((dma->flags & IORESOURCE_DMA_TYPE_MASK) == - IORESOURCE_DMA_8BIT) - dma->map = 0x000A; + IORESOURCE_DMA_8BIT && + dma->map != 0x0A) { + dev_info(&dev->dev, "changing possible " + "DMA channel mask in option set %d " + "from %#02x to 0x0A (1, 3)\n", + pnp_option_set(option), dma->map); + dma->map = 0x0A; + } } } - dev_info(&dev->dev, "CMI8330 quirk - forced possible IRQs to 5, 7, 10 " - "and DMA channels to 1, 3\n"); } static void quirk_sb16audio_resources(struct pnp_dev *dev) { + struct pnp_option *option; + unsigned int prev_option_flags = ~0, n = 0; struct pnp_port *port; - struct pnp_option *res = dev->dependent; - int changed = 0; /* - * The default range on the mpu port for these devices is 0x388-0x388. + * The default range on the OPL port for these devices is 0x388-0x388. * Here we increase that range so that two such cards can be * auto-configured. */ + list_for_each_entry(option, &dev->options, list) { + if (prev_option_flags != option->flags) { + prev_option_flags = option->flags; + n = 0; + } - for (; res; res = res->next) { - port = res->port; - if (!port) - continue; - port = port->next; - if (!port) - continue; - port = port->next; - if (!port) - continue; - if (port->min != port->max) - continue; - port->max += 0x70; - changed = 1; + if (pnp_option_is_dependent(option) && + option->type == IORESOURCE_IO) { + n++; + port = &option->u.port; + if (n == 3 && port->min == port->max) { + port->max += 0x70; + dev_info(&dev->dev, "increased option port " + "range from %#llx-%#llx to " + "%#llx-%#llx\n", + (unsigned long long) port->min, + (unsigned long long) port->min, + (unsigned long long) port->min, + (unsigned long long) port->max); + } + } } - if (changed) - dev_info(&dev->dev, "SB audio device quirk - increased port range\n"); } -static struct pnp_option *quirk_isapnp_mpu_options(struct pnp_dev *dev) +static struct pnp_option *pnp_clone_dependent_set(struct pnp_dev *dev, + unsigned int set) { - struct pnp_option *head = NULL; - struct pnp_option *prev = NULL; - struct pnp_option *res; - - /* - * Build a functional IRQ-optional variant of each MPU option. - */ - - for (res = dev->dependent; res; res = res->next) { - struct pnp_option *curr; - struct pnp_port *port; - struct pnp_port *copy_port; - struct pnp_irq *irq; - struct pnp_irq *copy_irq; - - port = res->port; - irq = res->irq; - if (!port || !irq) - continue; + struct pnp_option *tail = NULL, *first_new_option = NULL; + struct pnp_option *option, *new_option; + unsigned int flags; - copy_port = pnp_alloc(sizeof *copy_port); - if (!copy_port) - break; - - copy_irq = pnp_alloc(sizeof *copy_irq); - if (!copy_irq) { - kfree(copy_port); - break; - } + list_for_each_entry(option, &dev->options, list) { + if (pnp_option_is_dependent(option)) + tail = option; + } + if (!tail) { + dev_err(&dev->dev, "no dependent option sets\n"); + return NULL; + } - *copy_port = *port; - copy_port->next = NULL; + flags = pnp_new_dependent_set(dev, PNP_RES_PRIORITY_FUNCTIONAL); + list_for_each_entry(option, &dev->options, list) { + if (pnp_option_is_dependent(option) && + pnp_option_set(option) == set) { + new_option = kmalloc(sizeof(struct pnp_option), + GFP_KERNEL); + if (!new_option) { + dev_err(&dev->dev, "couldn't clone dependent " + "set %d\n", set); + return NULL; + } - *copy_irq = *irq; - copy_irq->flags |= IORESOURCE_IRQ_OPTIONAL; - copy_irq->next = NULL; + *new_option = *option; + new_option->flags = flags; + if (!first_new_option) + first_new_option = new_option; - curr = pnp_build_option(PNP_RES_PRIORITY_FUNCTIONAL); - if (!curr) { - kfree(copy_port); - kfree(copy_irq); - break; + list_add(&new_option->list, &tail->list); + tail = new_option; } - curr->port = copy_port; - curr->irq = copy_irq; - - if (prev) - prev->next = curr; - else - head = curr; - prev = curr; } - if (head) - dev_info(&dev->dev, "adding IRQ-optional MPU options\n"); - return head; + return first_new_option; } -static void quirk_ad1815_mpu_resources(struct pnp_dev *dev) + +static void quirk_add_irq_optional_dependent_sets(struct pnp_dev *dev) { - struct pnp_option *res; + struct pnp_option *new_option; + unsigned int num_sets, i, set; struct pnp_irq *irq; - res = dev->independent; - if (!res) - return; + num_sets = dev->num_dependent_sets; + for (i = 0; i < num_sets; i++) { + new_option = pnp_clone_dependent_set(dev, i); + if (!new_option) + return; - irq = res->irq; - if (!irq || irq->next) - return; + set = pnp_option_set(new_option); + while (new_option && pnp_option_set(new_option) == set) { + if (new_option->type == IORESOURCE_IRQ) { + irq = &new_option->u.irq; + irq->flags |= IORESOURCE_IRQ_OPTIONAL; + } + dbg_pnp_show_option(dev, new_option); + new_option = list_entry(new_option->list.next, + struct pnp_option, list); + } - irq->flags |= IORESOURCE_IRQ_OPTIONAL; - dev_info(&dev->dev, "made independent IRQ optional\n"); + dev_info(&dev->dev, "added dependent option set %d (same as " + "set %d except IRQ optional)\n", set, i); + } } -static void quirk_isapnp_mpu_resources(struct pnp_dev *dev) +static void quirk_ad1815_mpu_resources(struct pnp_dev *dev) { - struct pnp_option *res; + struct pnp_option *option; + struct pnp_irq *irq = NULL; + unsigned int independent_irqs = 0; + + list_for_each_entry(option, &dev->options, list) { + if (option->type == IORESOURCE_IRQ && + !pnp_option_is_dependent(option)) { + independent_irqs++; + irq = &option->u.irq; + } + } - res = dev->dependent; - if (!res) + if (independent_irqs != 1) return; - while (res->next) - res = res->next; - - res->next = quirk_isapnp_mpu_options(dev); + irq->flags |= IORESOURCE_IRQ_OPTIONAL; + dev_info(&dev->dev, "made independent IRQ optional\n"); } #include @@ -297,10 +317,10 @@ static struct pnp_fixup pnp_fixups[] = { {"CTL0043", quirk_sb16audio_resources}, {"CTL0044", quirk_sb16audio_resources}, {"CTL0045", quirk_sb16audio_resources}, - /* Add IRQ-less MPU options */ + /* Add IRQ-optional MPU options */ {"ADS7151", quirk_ad1815_mpu_resources}, - {"ADS7181", quirk_isapnp_mpu_resources}, - {"AZT0002", quirk_isapnp_mpu_resources}, + {"ADS7181", quirk_add_irq_optional_dependent_sets}, + {"AZT0002", quirk_add_irq_optional_dependent_sets}, /* PnP resources that might overlap PCI BARs */ {"PNP0c01", quirk_system_pci_resources}, {"PNP0c02", quirk_system_pci_resources}, diff --git a/drivers/pnp/resource.c b/drivers/pnp/resource.c index a795864dc695..d6388970a1a4 100644 --- a/drivers/pnp/resource.c +++ b/drivers/pnp/resource.c @@ -3,6 +3,8 @@ * * based on isapnp.c resource management (c) Jaroslav Kysela * Copyright 2003 Adam Belay + * Copyright (C) 2008 Hewlett-Packard Development Company, L.P. + * Bjorn Helgaas */ #include @@ -28,78 +30,36 @@ static int pnp_reserve_mem[16] = {[0 ... 15] = -1 }; /* reserve (don't use) some * option registration */ -struct pnp_option *pnp_build_option(int priority) +struct pnp_option *pnp_build_option(struct pnp_dev *dev, unsigned long type, + unsigned int option_flags) { - struct pnp_option *option = pnp_alloc(sizeof(struct pnp_option)); + struct pnp_option *option; + option = kzalloc(sizeof(struct pnp_option), GFP_KERNEL); if (!option) return NULL; - option->priority = priority & 0xff; - /* make sure the priority is valid */ - if (option->priority > PNP_RES_PRIORITY_FUNCTIONAL) - option->priority = PNP_RES_PRIORITY_INVALID; - - return option; -} - -struct pnp_option *pnp_register_independent_option(struct pnp_dev *dev) -{ - struct pnp_option *option; - - option = pnp_build_option(PNP_RES_PRIORITY_PREFERRED); - - /* this should never happen but if it does we'll try to continue */ - if (dev->independent) - dev_err(&dev->dev, "independent resource already registered\n"); - dev->independent = option; - - dev_dbg(&dev->dev, "new independent option\n"); - return option; -} - -struct pnp_option *pnp_register_dependent_option(struct pnp_dev *dev, - int priority) -{ - struct pnp_option *option; + option->flags = option_flags; + option->type = type; - option = pnp_build_option(priority); - - if (dev->dependent) { - struct pnp_option *parent = dev->dependent; - while (parent->next) - parent = parent->next; - parent->next = option; - } else - dev->dependent = option; - - dev_dbg(&dev->dev, "new dependent option (priority %#x)\n", priority); + list_add_tail(&option->list, &dev->options); return option; } -int pnp_register_irq_resource(struct pnp_dev *dev, struct pnp_option *option, +int pnp_register_irq_resource(struct pnp_dev *dev, unsigned int option_flags, pnp_irq_mask_t *map, unsigned char flags) { - struct pnp_irq *irq, *ptr; -#ifdef DEBUG - char buf[PNP_IRQ_NR]; /* hex-encoded, so this is overkill but safe */ -#endif + struct pnp_option *option; + struct pnp_irq *irq; - irq = kzalloc(sizeof(struct pnp_irq), GFP_KERNEL); - if (!irq) + option = pnp_build_option(dev, IORESOURCE_IRQ, option_flags); + if (!option) return -ENOMEM; + irq = &option->u.irq; irq->map = *map; irq->flags = flags; - ptr = option->irq; - while (ptr && ptr->next) - ptr = ptr->next; - if (ptr) - ptr->next = irq; - else - option->irq = irq; - #ifdef CONFIG_PCI { int i; @@ -110,163 +70,81 @@ int pnp_register_irq_resource(struct pnp_dev *dev, struct pnp_option *option, } #endif -#ifdef DEBUG - bitmap_scnprintf(buf, sizeof(buf), irq->map.bits, PNP_IRQ_NR); - dev_dbg(&dev->dev, " irq bitmask %s flags %#x\n", buf, - irq->flags); -#endif + dbg_pnp_show_option(dev, option); return 0; } -int pnp_register_dma_resource(struct pnp_dev *dev, struct pnp_option *option, +int pnp_register_dma_resource(struct pnp_dev *dev, unsigned int option_flags, unsigned char map, unsigned char flags) { - struct pnp_dma *dma, *ptr; + struct pnp_option *option; + struct pnp_dma *dma; - dma = kzalloc(sizeof(struct pnp_dma), GFP_KERNEL); - if (!dma) + option = pnp_build_option(dev, IORESOURCE_DMA, option_flags); + if (!option) return -ENOMEM; + dma = &option->u.dma; dma->map = map; dma->flags = flags; - ptr = option->dma; - while (ptr && ptr->next) - ptr = ptr->next; - if (ptr) - ptr->next = dma; - else - option->dma = dma; - - dev_dbg(&dev->dev, " dma bitmask %#x flags %#x\n", dma->map, - dma->flags); + dbg_pnp_show_option(dev, option); return 0; } -int pnp_register_port_resource(struct pnp_dev *dev, struct pnp_option *option, +int pnp_register_port_resource(struct pnp_dev *dev, unsigned int option_flags, resource_size_t min, resource_size_t max, resource_size_t align, resource_size_t size, unsigned char flags) { - struct pnp_port *port, *ptr; + struct pnp_option *option; + struct pnp_port *port; - port = kzalloc(sizeof(struct pnp_port), GFP_KERNEL); - if (!port) + option = pnp_build_option(dev, IORESOURCE_IO, option_flags); + if (!option) return -ENOMEM; + port = &option->u.port; port->min = min; port->max = max; port->align = align; port->size = size; port->flags = flags; - ptr = option->port; - while (ptr && ptr->next) - ptr = ptr->next; - if (ptr) - ptr->next = port; - else - option->port = port; - - dev_dbg(&dev->dev, " io " - "min %#llx max %#llx align %lld size %lld flags %#x\n", - (unsigned long long) port->min, - (unsigned long long) port->max, - (unsigned long long) port->align, - (unsigned long long) port->size, port->flags); + dbg_pnp_show_option(dev, option); return 0; } -int pnp_register_mem_resource(struct pnp_dev *dev, struct pnp_option *option, +int pnp_register_mem_resource(struct pnp_dev *dev, unsigned int option_flags, resource_size_t min, resource_size_t max, resource_size_t align, resource_size_t size, unsigned char flags) { - struct pnp_mem *mem, *ptr; + struct pnp_option *option; + struct pnp_mem *mem; - mem = kzalloc(sizeof(struct pnp_mem), GFP_KERNEL); - if (!mem) + option = pnp_build_option(dev, IORESOURCE_MEM, option_flags); + if (!option) return -ENOMEM; + mem = &option->u.mem; mem->min = min; mem->max = max; mem->align = align; mem->size = size; mem->flags = flags; - ptr = option->mem; - while (ptr && ptr->next) - ptr = ptr->next; - if (ptr) - ptr->next = mem; - else - option->mem = mem; - - dev_dbg(&dev->dev, " mem " - "min %#llx max %#llx align %lld size %lld flags %#x\n", - (unsigned long long) mem->min, - (unsigned long long) mem->max, - (unsigned long long) mem->align, - (unsigned long long) mem->size, mem->flags); + dbg_pnp_show_option(dev, option); return 0; } -static void pnp_free_port(struct pnp_port *port) -{ - struct pnp_port *next; - - while (port) { - next = port->next; - kfree(port); - port = next; - } -} - -static void pnp_free_irq(struct pnp_irq *irq) -{ - struct pnp_irq *next; - - while (irq) { - next = irq->next; - kfree(irq); - irq = next; - } -} - -static void pnp_free_dma(struct pnp_dma *dma) -{ - struct pnp_dma *next; - - while (dma) { - next = dma->next; - kfree(dma); - dma = next; - } -} - -static void pnp_free_mem(struct pnp_mem *mem) +void pnp_free_options(struct pnp_dev *dev) { - struct pnp_mem *next; - - while (mem) { - next = mem->next; - kfree(mem); - mem = next; - } -} + struct pnp_option *option, *tmp; -void pnp_free_option(struct pnp_option *option) -{ - struct pnp_option *next; - - while (option) { - next = option->next; - pnp_free_port(option->port); - pnp_free_irq(option->irq); - pnp_free_dma(option->dma); - pnp_free_mem(option->mem); + list_for_each_entry_safe(option, tmp, &dev->options, list) { + list_del(&option->list); kfree(option); - option = next; } } @@ -668,66 +546,50 @@ struct pnp_resource *pnp_add_mem_resource(struct pnp_dev *dev, return pnp_res; } -static int pnp_possible_option(struct pnp_option *option, int type, - resource_size_t start, resource_size_t size) +/* + * Determine whether the specified resource is a possible configuration + * for this device. + */ +int pnp_possible_config(struct pnp_dev *dev, int type, resource_size_t start, + resource_size_t size) { - struct pnp_option *tmp; + struct pnp_option *option; struct pnp_port *port; struct pnp_mem *mem; struct pnp_irq *irq; struct pnp_dma *dma; - if (!option) - return 0; + list_for_each_entry(option, &dev->options, list) { + if (option->type != type) + continue; - for (tmp = option; tmp; tmp = tmp->next) { - switch (type) { + switch (option->type) { case IORESOURCE_IO: - for (port = tmp->port; port; port = port->next) { - if (port->min == start && port->size == size) - return 1; - } + port = &option->u.port; + if (port->min == start && port->size == size) + return 1; break; case IORESOURCE_MEM: - for (mem = tmp->mem; mem; mem = mem->next) { - if (mem->min == start && mem->size == size) - return 1; - } + mem = &option->u.mem; + if (mem->min == start && mem->size == size) + return 1; break; case IORESOURCE_IRQ: - for (irq = tmp->irq; irq; irq = irq->next) { - if (start < PNP_IRQ_NR && - test_bit(start, irq->map.bits)) - return 1; - } + irq = &option->u.irq; + if (start < PNP_IRQ_NR && + test_bit(start, irq->map.bits)) + return 1; break; case IORESOURCE_DMA: - for (dma = tmp->dma; dma; dma = dma->next) { - if (dma->map & (1 << start)) - return 1; - } + dma = &option->u.dma; + if (dma->map & (1 << start)) + return 1; break; } } return 0; } - -/* - * Determine whether the specified resource is a possible configuration - * for this device. - */ -int pnp_possible_config(struct pnp_dev *dev, int type, resource_size_t start, - resource_size_t size) -{ - if (pnp_possible_option(dev->independent, type, start, size)) - return 1; - - if (pnp_possible_option(dev->dependent, type, start, size)) - return 1; - - return 0; -} EXPORT_SYMBOL(pnp_possible_config); /* format is: pnp_reserve_irq=irq1[,irq2] .... */ diff --git a/drivers/pnp/support.c b/drivers/pnp/support.c index 0ad42db94884..bbf78ef4ba02 100644 --- a/drivers/pnp/support.c +++ b/drivers/pnp/support.c @@ -2,6 +2,8 @@ * support.c - standard functions for the use of pnp protocol drivers * * Copyright 2003 Adam Belay + * Copyright (C) 2008 Hewlett-Packard Development Company, L.P. + * Bjorn Helgaas */ #include @@ -117,3 +119,93 @@ void dbg_pnp_show_resources(struct pnp_dev *dev, char *desc) } #endif } + +char *pnp_option_priority_name(struct pnp_option *option) +{ + switch (pnp_option_priority(option)) { + case PNP_RES_PRIORITY_PREFERRED: + return "preferred"; + case PNP_RES_PRIORITY_ACCEPTABLE: + return "acceptable"; + case PNP_RES_PRIORITY_FUNCTIONAL: + return "functional"; + } + return "invalid"; +} + +void dbg_pnp_show_option(struct pnp_dev *dev, struct pnp_option *option) +{ +#ifdef DEBUG + char buf[128]; + int len = 0, i; + struct pnp_port *port; + struct pnp_mem *mem; + struct pnp_irq *irq; + struct pnp_dma *dma; + + if (pnp_option_is_dependent(option)) + len += snprintf(buf + len, sizeof(buf) - len, + " dependent set %d (%s) ", + pnp_option_set(option), + pnp_option_priority_name(option)); + else + len += snprintf(buf + len, sizeof(buf) - len, " independent "); + + switch (option->type) { + case IORESOURCE_IO: + port = &option->u.port; + len += snprintf(buf + len, sizeof(buf) - len, "io min %#llx " + "max %#llx align %lld size %lld flags %#x", + (unsigned long long) port->min, + (unsigned long long) port->max, + (unsigned long long) port->align, + (unsigned long long) port->size, port->flags); + break; + case IORESOURCE_MEM: + mem = &option->u.mem; + len += snprintf(buf + len, sizeof(buf) - len, "mem min %#llx " + "max %#llx align %lld size %lld flags %#x", + (unsigned long long) mem->min, + (unsigned long long) mem->max, + (unsigned long long) mem->align, + (unsigned long long) mem->size, mem->flags); + break; + case IORESOURCE_IRQ: + irq = &option->u.irq; + len += snprintf(buf + len, sizeof(buf) - len, "irq"); + if (bitmap_empty(irq->map.bits, PNP_IRQ_NR)) + len += snprintf(buf + len, sizeof(buf) - len, + " "); + else { + for (i = 0; i < PNP_IRQ_NR; i++) + if (test_bit(i, irq->map.bits)) + len += snprintf(buf + len, + sizeof(buf) - len, + " %d", i); + } + len += snprintf(buf + len, sizeof(buf) - len, " flags %#x", + irq->flags); + if (irq->flags & IORESOURCE_IRQ_OPTIONAL) + len += snprintf(buf + len, sizeof(buf) - len, + " (optional)"); + break; + case IORESOURCE_DMA: + dma = &option->u.dma; + len += snprintf(buf + len, sizeof(buf) - len, "dma"); + if (!dma->map) + len += snprintf(buf + len, sizeof(buf) - len, + " "); + else { + for (i = 0; i < 8; i++) + if (dma->map & (1 << i)) + len += snprintf(buf + len, + sizeof(buf) - len, + " %d", i); + } + len += snprintf(buf + len, sizeof(buf) - len, " (bitmask %#x) " + "flags %#x", dma->map, dma->flags); + break; + } + dev_dbg(&dev->dev, "%s\n", buf); +#endif +} diff --git a/include/linux/pnp.h b/include/linux/pnp.h index 785126ffcc11..1ce54b63085d 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -1,6 +1,8 @@ /* * Linux Plug and Play Support * Copyright by Adam Belay + * Copyright (C) 2008 Hewlett-Packard Development Company, L.P. + * Bjorn Helgaas */ #ifndef _LINUX_PNP_H @@ -249,9 +251,9 @@ struct pnp_dev { int active; int capabilities; - struct pnp_option *independent; - struct pnp_option *dependent; + unsigned int num_dependent_sets; struct list_head resources; + struct list_head options; char name[PNP_NAME_LEN]; /* contains a human-readable name */ int flags; /* used by protocols */ -- cgit v1.2.3 From 4d3870431d17346c4fdd80e087b7d76f1b5941d5 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 16 Jul 2008 23:27:08 +0200 Subject: Add the ability to reset the machine using the RESET_REG in ACPI's FADT table. Signed-off-by: Aaron Durbin Signed-off-by: Andi Kleen Cc: Len Brown Cc: Andi Kleen Signed-off-by: Andrew Morton --- drivers/acpi/Makefile | 2 +- drivers/acpi/reboot.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/acpi/reboot.h | 14 ++++++++------ 3 files changed, 59 insertions(+), 7 deletions(-) create mode 100644 drivers/acpi/reboot.c (limited to 'include') diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 40b0fcae4c78..4efbe598c817 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -21,7 +21,7 @@ obj-$(CONFIG_X86) += blacklist.o # # ACPI Core Subsystem (Interpreter) # -obj-y += osl.o utils.o \ +obj-y += osl.o utils.o reboot.o\ dispatcher/ events/ executer/ hardware/ \ namespace/ parser/ resources/ tables/ \ utilities/ diff --git a/drivers/acpi/reboot.c b/drivers/acpi/reboot.c new file mode 100644 index 000000000000..a6b662c00b67 --- /dev/null +++ b/drivers/acpi/reboot.c @@ -0,0 +1,50 @@ + +#include +#include +#include + +void acpi_reboot(void) +{ + struct acpi_generic_address *rr; + struct pci_bus *bus0; + u8 reset_value; + unsigned int devfn; + + if (acpi_disabled) + return; + + rr = &acpi_gbl_FADT.reset_register; + + /* Is the reset register supported? */ + if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER) || + rr->bit_width != 8 || rr->bit_offset != 0) + return; + + reset_value = acpi_gbl_FADT.reset_value; + + /* The reset register can only exist in I/O, Memory or PCI config space + * on a device on bus 0. */ + switch (rr->space_id) { + case ACPI_ADR_SPACE_PCI_CONFIG: + /* The reset register can only live on bus 0. */ + bus0 = pci_find_bus(0, 0); + if (!bus0) + return; + /* Form PCI device/function pair. */ + devfn = PCI_DEVFN((rr->address >> 32) & 0xffff, + (rr->address >> 16) & 0xffff); + printk(KERN_DEBUG "Resetting with ACPI PCI RESET_REG."); + /* Write the value that resets us. */ + pci_bus_write_config_byte(bus0, devfn, + (rr->address & 0xffff), reset_value); + break; + + case ACPI_ADR_SPACE_SYSTEM_MEMORY: + case ACPI_ADR_SPACE_SYSTEM_IO: + printk(KERN_DEBUG "ACPI MEMORY or I/O RESET_REG.\n"); + acpi_hw_low_level_write(8, reset_value, rr); + break; + } + /* Wait ten seconds */ + acpi_os_stall(10000000); +} diff --git a/include/acpi/reboot.h b/include/acpi/reboot.h index 8857f57e0b78..0419184ce886 100644 --- a/include/acpi/reboot.h +++ b/include/acpi/reboot.h @@ -1,9 +1,11 @@ +#ifndef __ACPI_REBOOT_H +#define __ACPI_REBOOT_H + +#ifdef CONFIG_ACPI +extern void acpi_reboot(void); +#else +static inline void acpi_reboot(void) { } +#endif -/* - * Dummy placeholder to make the EFI patches apply to the x86 tree. - * Andrew/Len, please just kill this file if you encounter it. - */ -#ifndef acpi_reboot -# define acpi_reboot() do { } while (0) #endif -- cgit v1.2.3 From d442cc44c0db56e84ef6aa244a88427d2efe06cd Mon Sep 17 00:00:00 2001 From: "Martin K. Petersen" Date: Wed, 16 Jul 2008 16:09:06 -0400 Subject: block: Trivial fix for blk_integrity_rq() Fail integrity check gracefully when request does not have a bio attached (BLOCK_PC). Signed-off-by: Martin K. Petersen Signed-off-by: Linus Torvalds --- include/linux/blkdev.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 32a441b05fd5..88d68081a0f1 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -985,6 +985,9 @@ static inline int bdev_integrity_enabled(struct block_device *bdev, int rw) static inline int blk_integrity_rq(struct request *rq) { + if (rq->bio == NULL) + return 0; + return bio_integrity(rq->bio); } -- cgit v1.2.3 From f470021adb9190819c03d6d8c5c860a17480aa6d Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Mon, 24 Mar 2008 18:36:23 -0700 Subject: ptrace children revamp ptrace no longer fiddles with the children/sibling links, and the old ptrace_children list is gone. Now ptrace, whether of one's own children or another's via PTRACE_ATTACH, just uses the new ptraced list instead. There should be no user-visible difference that matters. The only change is the order in which do_wait() sees multiple stopped children and stopped ptrace attachees. Since wait_task_stopped() was changed earlier so it no longer reorders the children list, we already know this won't cause any new problems. Signed-off-by: Roland McGrath --- include/linux/init_task.h | 4 +- include/linux/sched.h | 26 +++--- kernel/exit.c | 226 ++++++++++++++++++++++++---------------------- kernel/fork.c | 6 +- kernel/ptrace.c | 37 +++++--- 5 files changed, 160 insertions(+), 139 deletions(-) (limited to 'include') diff --git a/include/linux/init_task.h b/include/linux/init_task.h index 9927a88674a3..93c45acf249a 100644 --- a/include/linux/init_task.h +++ b/include/linux/init_task.h @@ -140,8 +140,8 @@ extern struct group_info init_groups; .nr_cpus_allowed = NR_CPUS, \ }, \ .tasks = LIST_HEAD_INIT(tsk.tasks), \ - .ptrace_children= LIST_HEAD_INIT(tsk.ptrace_children), \ - .ptrace_list = LIST_HEAD_INIT(tsk.ptrace_list), \ + .ptraced = LIST_HEAD_INIT(tsk.ptraced), \ + .ptrace_entry = LIST_HEAD_INIT(tsk.ptrace_entry), \ .real_parent = &tsk, \ .parent = &tsk, \ .children = LIST_HEAD_INIT(tsk.children), \ diff --git a/include/linux/sched.h b/include/linux/sched.h index ba2f859c6e4f..1941d8b5cf11 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1062,12 +1062,6 @@ struct task_struct { #endif struct list_head tasks; - /* - * ptrace_list/ptrace_children forms the list of my children - * that were stolen by a ptracer. - */ - struct list_head ptrace_children; - struct list_head ptrace_list; struct mm_struct *mm, *active_mm; @@ -1089,18 +1083,25 @@ struct task_struct { /* * pointers to (original) parent process, youngest child, younger sibling, * older sibling, respectively. (p->father can be replaced with - * p->parent->pid) + * p->real_parent->pid) */ - struct task_struct *real_parent; /* real parent process (when being debugged) */ - struct task_struct *parent; /* parent process */ + struct task_struct *real_parent; /* real parent process */ + struct task_struct *parent; /* recipient of SIGCHLD, wait4() reports */ /* - * children/sibling forms the list of my children plus the - * tasks I'm ptracing. + * children/sibling forms the list of my natural children */ struct list_head children; /* list of my children */ struct list_head sibling; /* linkage in my parent's children list */ struct task_struct *group_leader; /* threadgroup leader */ + /* + * ptraced is the list of tasks this task is using ptrace on. + * This includes both natural children and PTRACE_ATTACH targets. + * p->ptrace_entry is p's link on the p->parent->ptraced list. + */ + struct list_head ptraced; + struct list_head ptrace_entry; + /* PID/PID hash table linkage. */ struct pid_link pids[PIDTYPE_MAX]; struct list_head thread_group; @@ -1876,9 +1877,6 @@ extern void wait_task_inactive(struct task_struct * p); #define wait_task_inactive(p) do { } while (0) #endif -#define remove_parent(p) list_del_init(&(p)->sibling) -#define add_parent(p) list_add_tail(&(p)->sibling,&(p)->parent->children) - #define next_task(p) list_entry(rcu_dereference((p)->tasks.next), struct task_struct, tasks) #define for_each_process(p) \ diff --git a/kernel/exit.c b/kernel/exit.c index 7453356a961f..1e909826a804 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -71,7 +71,7 @@ static void __unhash_process(struct task_struct *p) __get_cpu_var(process_counts)--; } list_del_rcu(&p->thread_group); - remove_parent(p); + list_del_init(&p->sibling); } /* @@ -152,6 +152,18 @@ static void delayed_put_task_struct(struct rcu_head *rhp) put_task_struct(container_of(rhp, struct task_struct, rcu)); } +/* + * Do final ptrace-related cleanup of a zombie being reaped. + * + * Called with write_lock(&tasklist_lock) held. + */ +static void ptrace_release_task(struct task_struct *p) +{ + BUG_ON(!list_empty(&p->ptraced)); + ptrace_unlink(p); + BUG_ON(!list_empty(&p->ptrace_entry)); +} + void release_task(struct task_struct * p) { struct task_struct *leader; @@ -160,8 +172,7 @@ repeat: atomic_dec(&p->user->processes); proc_flush_task(p); write_lock_irq(&tasklist_lock); - ptrace_unlink(p); - BUG_ON(!list_empty(&p->ptrace_list) || !list_empty(&p->ptrace_children)); + ptrace_release_task(p); __exit_signal(p); /* @@ -315,9 +326,8 @@ static void reparent_to_kthreadd(void) ptrace_unlink(current); /* Reparent to init */ - remove_parent(current); current->real_parent = current->parent = kthreadd_task; - add_parent(current); + list_move_tail(¤t->sibling, ¤t->real_parent->children); /* Set the exit signal to SIGCHLD so we signal init on exit */ current->exit_signal = SIGCHLD; @@ -692,37 +702,71 @@ static void exit_mm(struct task_struct * tsk) mmput(mm); } -static void -reparent_thread(struct task_struct *p, struct task_struct *father, int traced) +/* + * Detach all tasks we were using ptrace on. + * Any that need to be release_task'd are put on the @dead list. + * + * Called with write_lock(&tasklist_lock) held. + */ +static void ptrace_exit(struct task_struct *parent, struct list_head *dead) { - if (p->pdeath_signal) - /* We already hold the tasklist_lock here. */ - group_send_sig_info(p->pdeath_signal, SEND_SIG_NOINFO, p); + struct task_struct *p, *n; - /* Move the child from its dying parent to the new one. */ - if (unlikely(traced)) { - /* Preserve ptrace links if someone else is tracing this child. */ - list_del_init(&p->ptrace_list); - if (ptrace_reparented(p)) - list_add(&p->ptrace_list, &p->real_parent->ptrace_children); - } else { - /* If this child is being traced, then we're the one tracing it - * anyway, so let go of it. + list_for_each_entry_safe(p, n, &parent->ptraced, ptrace_entry) { + __ptrace_unlink(p); + + if (p->exit_state != EXIT_ZOMBIE) + continue; + + /* + * If it's a zombie, our attachedness prevented normal + * parent notification or self-reaping. Do notification + * now if it would have happened earlier. If it should + * reap itself, add it to the @dead list. We can't call + * release_task() here because we already hold tasklist_lock. + * + * If it's our own child, there is no notification to do. */ - p->ptrace = 0; - remove_parent(p); - p->parent = p->real_parent; - add_parent(p); + if (!task_detached(p) && thread_group_empty(p)) { + if (!same_thread_group(p->real_parent, parent)) + do_notify_parent(p, p->exit_signal); + } - if (task_is_traced(p)) { + if (task_detached(p)) { /* - * If it was at a trace stop, turn it into - * a normal stop since it's no longer being - * traced. + * Mark it as in the process of being reaped. */ - ptrace_untrace(p); + p->exit_state = EXIT_DEAD; + list_add(&p->ptrace_entry, dead); } } +} + +/* + * Finish up exit-time ptrace cleanup. + * + * Called without locks. + */ +static void ptrace_exit_finish(struct task_struct *parent, + struct list_head *dead) +{ + struct task_struct *p, *n; + + BUG_ON(!list_empty(&parent->ptraced)); + + list_for_each_entry_safe(p, n, dead, ptrace_entry) { + list_del_init(&p->ptrace_entry); + release_task(p); + } +} + +static void reparent_thread(struct task_struct *p, struct task_struct *father) +{ + if (p->pdeath_signal) + /* We already hold the tasklist_lock here. */ + group_send_sig_info(p->pdeath_signal, SEND_SIG_NOINFO, p); + + list_move_tail(&p->sibling, &p->real_parent->children); /* If this is a threaded reparent there is no need to * notify anyone anything has happened. @@ -737,7 +781,8 @@ reparent_thread(struct task_struct *p, struct task_struct *father, int traced) /* If we'd notified the old parent about this child's death, * also notify the new parent. */ - if (!traced && p->exit_state == EXIT_ZOMBIE && + if (!ptrace_reparented(p) && + p->exit_state == EXIT_ZOMBIE && !task_detached(p) && thread_group_empty(p)) do_notify_parent(p, p->exit_signal); @@ -754,12 +799,15 @@ reparent_thread(struct task_struct *p, struct task_struct *father, int traced) static void forget_original_parent(struct task_struct *father) { struct task_struct *p, *n, *reaper = father; - struct list_head ptrace_dead; - - INIT_LIST_HEAD(&ptrace_dead); + LIST_HEAD(ptrace_dead); write_lock_irq(&tasklist_lock); + /* + * First clean up ptrace if we were using it. + */ + ptrace_exit(father, &ptrace_dead); + do { reaper = next_thread(reaper); if (reaper == father) { @@ -768,58 +816,19 @@ static void forget_original_parent(struct task_struct *father) } } while (reaper->flags & PF_EXITING); - /* - * There are only two places where our children can be: - * - * - in our child list - * - in our ptraced child list - * - * Search them and reparent children. - */ list_for_each_entry_safe(p, n, &father->children, sibling) { - int ptrace; - - ptrace = p->ptrace; - - /* if father isn't the real parent, then ptrace must be enabled */ - BUG_ON(father != p->real_parent && !ptrace); - - if (father == p->real_parent) { - /* reparent with a reaper, real father it's us */ - p->real_parent = reaper; - reparent_thread(p, father, 0); - } else { - /* reparent ptraced task to its real parent */ - __ptrace_unlink (p); - if (p->exit_state == EXIT_ZOMBIE && !task_detached(p) && - thread_group_empty(p)) - do_notify_parent(p, p->exit_signal); - } - - /* - * if the ptraced child is a detached zombie we must collect - * it before we exit, or it will remain zombie forever since - * we prevented it from self-reap itself while it was being - * traced by us, to be able to see it in wait4. - */ - if (unlikely(ptrace && p->exit_state == EXIT_ZOMBIE && task_detached(p))) - list_add(&p->ptrace_list, &ptrace_dead); - } - - list_for_each_entry_safe(p, n, &father->ptrace_children, ptrace_list) { p->real_parent = reaper; - reparent_thread(p, father, 1); + if (p->parent == father) { + BUG_ON(p->ptrace); + p->parent = p->real_parent; + } + reparent_thread(p, father); } write_unlock_irq(&tasklist_lock); BUG_ON(!list_empty(&father->children)); - BUG_ON(!list_empty(&father->ptrace_children)); - - list_for_each_entry_safe(p, n, &ptrace_dead, ptrace_list) { - list_del_init(&p->ptrace_list); - release_task(p); - } + ptrace_exit_finish(father, &ptrace_dead); } /* @@ -1180,13 +1189,6 @@ static int eligible_child(enum pid_type type, struct pid *pid, int options, return 0; } - /* - * Do not consider detached threads that are - * not ptraced: - */ - if (task_detached(p) && !p->ptrace) - return 0; - /* Wait for all children (clone and not) if __WALL is set; * otherwise, wait for clone children *only* if __WCLONE is * set; otherwise, wait for non-clone children *only*. (Note: @@ -1399,7 +1401,7 @@ static int wait_task_zombie(struct task_struct *p, int options, * the lock and this task is uninteresting. If we return nonzero, we have * released the lock and the system call should return. */ -static int wait_task_stopped(struct task_struct *p, +static int wait_task_stopped(int ptrace, struct task_struct *p, int options, struct siginfo __user *infop, int __user *stat_addr, struct rusage __user *ru) { @@ -1407,7 +1409,7 @@ static int wait_task_stopped(struct task_struct *p, uid_t uid = 0; /* unneeded, required by compiler */ pid_t pid; - if (!(p->ptrace & PT_PTRACED) && !(options & WUNTRACED)) + if (!(options & WUNTRACED)) return 0; exit_code = 0; @@ -1416,7 +1418,7 @@ static int wait_task_stopped(struct task_struct *p, if (unlikely(!task_is_stopped_or_traced(p))) goto unlock_sig; - if (!(p->ptrace & PT_PTRACED) && p->signal->group_stop_count > 0) + if (!ptrace && p->signal->group_stop_count > 0) /* * A group stop is in progress and this is the group leader. * We won't report until all threads have stopped. @@ -1445,7 +1447,7 @@ unlock_sig: */ get_task_struct(p); pid = task_pid_vnr(p); - why = (p->ptrace & PT_PTRACED) ? CLD_TRAPPED : CLD_STOPPED; + why = ptrace ? CLD_TRAPPED : CLD_STOPPED; read_unlock(&tasklist_lock); if (unlikely(options & WNOWAIT)) @@ -1536,7 +1538,7 @@ static int wait_task_continued(struct task_struct *p, int options, * Returns zero if the search for a child should continue; * then *@notask_error is 0 if @p is an eligible child, or still -ECHILD. */ -static int wait_consider_task(struct task_struct *parent, +static int wait_consider_task(struct task_struct *parent, int ptrace, struct task_struct *p, int *notask_error, enum pid_type type, struct pid *pid, int options, struct siginfo __user *infop, @@ -1546,6 +1548,15 @@ static int wait_consider_task(struct task_struct *parent, if (ret <= 0) return ret; + if (likely(!ptrace) && unlikely(p->ptrace)) { + /* + * This child is hidden by ptrace. + * We aren't allowed to see it now, but eventually we will. + */ + *notask_error = 0; + return 0; + } + if (p->exit_state == EXIT_DEAD) return 0; @@ -1562,7 +1573,8 @@ static int wait_consider_task(struct task_struct *parent, *notask_error = 0; if (task_is_stopped_or_traced(p)) - return wait_task_stopped(p, options, infop, stat_addr, ru); + return wait_task_stopped(ptrace, p, options, + infop, stat_addr, ru); return wait_task_continued(p, options, infop, stat_addr, ru); } @@ -1583,11 +1595,16 @@ static int do_wait_thread(struct task_struct *tsk, int *notask_error, struct task_struct *p; list_for_each_entry(p, &tsk->children, sibling) { - int ret = wait_consider_task(tsk, p, notask_error, - type, pid, options, - infop, stat_addr, ru); - if (ret) - return ret; + /* + * Do not consider detached threads. + */ + if (!task_detached(p)) { + int ret = wait_consider_task(tsk, 0, p, notask_error, + type, pid, options, + infop, stat_addr, ru); + if (ret) + return ret; + } } return 0; @@ -1601,21 +1618,16 @@ static int ptrace_do_wait(struct task_struct *tsk, int *notask_error, struct task_struct *p; /* - * If we never saw an eligile child, check for children stolen by - * ptrace. We don't leave -ECHILD in *@notask_error if there are any, - * because we will eventually be allowed to wait for them again. + * Traditionally we see ptrace'd stopped tasks regardless of options. */ - if (!*notask_error) - return 0; + options |= WUNTRACED; - list_for_each_entry(p, &tsk->ptrace_children, ptrace_list) { - int ret = eligible_child(type, pid, options, p); - if (unlikely(ret < 0)) + list_for_each_entry(p, &tsk->ptraced, ptrace_entry) { + int ret = wait_consider_task(tsk, 1, p, notask_error, + type, pid, options, + infop, stat_addr, ru); + if (ret) return ret; - if (ret) { - *notask_error = 0; - return 0; - } } return 0; diff --git a/kernel/fork.c b/kernel/fork.c index 4bd2f516401f..adefc1131f27 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -1125,8 +1125,8 @@ static struct task_struct *copy_process(unsigned long clone_flags, */ p->group_leader = p; INIT_LIST_HEAD(&p->thread_group); - INIT_LIST_HEAD(&p->ptrace_children); - INIT_LIST_HEAD(&p->ptrace_list); + INIT_LIST_HEAD(&p->ptrace_entry); + INIT_LIST_HEAD(&p->ptraced); /* Now that the task is set up, run cgroup callbacks if * necessary. We need to run them before the task is visible @@ -1198,7 +1198,7 @@ static struct task_struct *copy_process(unsigned long clone_flags, } if (likely(p->pid)) { - add_parent(p); + list_add_tail(&p->sibling, &p->real_parent->children); if (unlikely(p->ptrace & PT_PTRACED)) __ptrace_link(p, current->parent); diff --git a/kernel/ptrace.c b/kernel/ptrace.c index e337390fce01..8392a9da6450 100644 --- a/kernel/ptrace.c +++ b/kernel/ptrace.c @@ -33,13 +33,9 @@ */ void __ptrace_link(struct task_struct *child, struct task_struct *new_parent) { - BUG_ON(!list_empty(&child->ptrace_list)); - if (child->parent == new_parent) - return; - list_add(&child->ptrace_list, &child->parent->ptrace_children); - remove_parent(child); + BUG_ON(!list_empty(&child->ptrace_entry)); + list_add(&child->ptrace_entry, &new_parent->ptraced); child->parent = new_parent; - add_parent(child); } /* @@ -73,12 +69,8 @@ void __ptrace_unlink(struct task_struct *child) BUG_ON(!child->ptrace); child->ptrace = 0; - if (ptrace_reparented(child)) { - list_del_init(&child->ptrace_list); - remove_parent(child); - child->parent = child->real_parent; - add_parent(child); - } + child->parent = child->real_parent; + list_del_init(&child->ptrace_entry); if (task_is_traced(child)) ptrace_untrace(child); @@ -492,15 +484,34 @@ int ptrace_traceme(void) /* * Are we already being traced? */ +repeat: task_lock(current); if (!(current->ptrace & PT_PTRACED)) { + /* + * See ptrace_attach() comments about the locking here. + */ + unsigned long flags; + if (!write_trylock_irqsave(&tasklist_lock, flags)) { + task_unlock(current); + do { + cpu_relax(); + } while (!write_can_lock(&tasklist_lock)); + goto repeat; + } + ret = security_ptrace(current->parent, current, PTRACE_MODE_ATTACH); + /* * Set the ptrace bit in the process ptrace flags. + * Then link us on our parent's ptraced list. */ - if (!ret) + if (!ret) { current->ptrace |= PT_PTRACED; + __ptrace_link(current, current->real_parent); + } + + write_unlock_irqrestore(&tasklist_lock, flags); } task_unlock(current); return ret; -- cgit v1.2.3 From 626f311737770f0fb5c09a6da2ea795a559aa42a Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Thu, 17 Jul 2008 17:16:42 +0200 Subject: [S390] chsc headers userspace cleanup Kernel headers shouldn't expose functions to userspace. Cc: Cornelia Huck Signed-off-by: Adrian Bunk Signed-off-by: Heiko Carstens Cc: Martin Schwidefsky --- include/asm-s390/Kbuild | 2 +- include/asm-s390/chpid.h | 6 +++--- include/asm-s390/schid.h | 3 +++ 3 files changed, 7 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-s390/Kbuild b/include/asm-s390/Kbuild index 09f312501eb5..bb5e9edb9825 100644 --- a/include/asm-s390/Kbuild +++ b/include/asm-s390/Kbuild @@ -8,9 +8,9 @@ header-y += ucontext.h header-y += vtoc.h header-y += zcrypt.h header-y += kvm.h -header-y += schid.h header-y += chsc.h unifdef-y += cmb.h unifdef-y += debug.h unifdef-y += chpid.h +unifdef-y += schid.h diff --git a/include/asm-s390/chpid.h b/include/asm-s390/chpid.h index 606844d0a5c3..dfe3c7f3439a 100644 --- a/include/asm-s390/chpid.h +++ b/include/asm-s390/chpid.h @@ -20,6 +20,9 @@ struct chp_id { u8 id; } __attribute__((packed)); +#ifdef __KERNEL__ +#include + static inline void chp_id_init(struct chp_id *chpid) { memset(chpid, 0, sizeof(struct chp_id)); @@ -40,9 +43,6 @@ static inline void chp_id_next(struct chp_id *chpid) } } -#ifdef __KERNEL__ -#include - static inline int chp_id_is_valid(struct chp_id *chpid) { return (chpid->cssid <= __MAX_CSSID); diff --git a/include/asm-s390/schid.h b/include/asm-s390/schid.h index 5017ffa78e04..7bdc0fe15691 100644 --- a/include/asm-s390/schid.h +++ b/include/asm-s390/schid.h @@ -10,6 +10,7 @@ struct subchannel_id { __u32 sch_no : 16; } __attribute__ ((packed, aligned(4))); +#ifdef __KERNEL__ /* Helper function for sane state of pre-allocated subchannel_id. */ static inline void @@ -25,4 +26,6 @@ schid_equal(struct subchannel_id *schid1, struct subchannel_id *schid2) return !memcmp(schid1, schid2, sizeof(struct subchannel_id)); } +#endif /* __KERNEL__ */ + #endif /* ASM_SCHID_H */ -- cgit v1.2.3 From 779e6e1c724d30e0fd1baca78b852e41e3a23c1d Mon Sep 17 00:00:00 2001 From: Jan Glauber Date: Thu, 17 Jul 2008 17:16:48 +0200 Subject: [S390] qdio: new qdio driver. List of major changes: - split qdio driver into several files - seperation of thin interrupt code - improved handling for multiple thin interrupt devices - inbound and outbound processing now always runs in tasklet context - significant less tasklet schedules per interrupt needed - merged qebsm with non-qebsm handling - cleanup qdio interface and added kerneldoc - coding style Reviewed-by: Cornelia Huck Reviewed-by: Utz Bacher Reviewed-by: Ursula Braun Signed-off-by: Jan Glauber Signed-off-by: Martin Schwidefsky Signed-off-by: Heiko Carstens --- drivers/s390/cio/Makefile | 2 + drivers/s390/cio/qdio.c | 3929 ------------------------------------- drivers/s390/cio/qdio.h | 835 +++----- drivers/s390/cio/qdio_debug.c | 240 +++ drivers/s390/cio/qdio_debug.h | 91 + drivers/s390/cio/qdio_main.c | 1755 +++++++++++++++++ drivers/s390/cio/qdio_perf.c | 151 ++ drivers/s390/cio/qdio_perf.h | 54 + drivers/s390/cio/qdio_setup.c | 521 +++++ drivers/s390/cio/qdio_thinint.c | 380 ++++ drivers/s390/net/qeth_core.h | 12 +- drivers/s390/net/qeth_core_main.c | 87 +- drivers/s390/net/qeth_l2_main.c | 26 +- drivers/s390/net/qeth_l3_main.c | 25 +- drivers/s390/scsi/zfcp_dbf.c | 12 +- drivers/s390/scsi/zfcp_dbf.h | 2 - drivers/s390/scsi/zfcp_ext.h | 5 +- drivers/s390/scsi/zfcp_qdio.c | 42 +- include/asm-s390/qdio.h | 646 +++--- include/asm-s390/setup.h | 2 +- 20 files changed, 3874 insertions(+), 4943 deletions(-) delete mode 100644 drivers/s390/cio/qdio.c create mode 100644 drivers/s390/cio/qdio_debug.c create mode 100644 drivers/s390/cio/qdio_debug.h create mode 100644 drivers/s390/cio/qdio_main.c create mode 100644 drivers/s390/cio/qdio_perf.c create mode 100644 drivers/s390/cio/qdio_perf.h create mode 100644 drivers/s390/cio/qdio_setup.c create mode 100644 drivers/s390/cio/qdio_thinint.c (limited to 'include') diff --git a/drivers/s390/cio/Makefile b/drivers/s390/cio/Makefile index 91e9e3f3073a..bd79bd165396 100644 --- a/drivers/s390/cio/Makefile +++ b/drivers/s390/cio/Makefile @@ -9,4 +9,6 @@ ccw_device-objs += device_id.o device_pgid.o device_status.o obj-y += ccw_device.o cmf.o obj-$(CONFIG_CHSC_SCH) += chsc_sch.o obj-$(CONFIG_CCWGROUP) += ccwgroup.o + +qdio-objs := qdio_main.o qdio_thinint.o qdio_debug.o qdio_perf.o qdio_setup.o obj-$(CONFIG_QDIO) += qdio.o diff --git a/drivers/s390/cio/qdio.c b/drivers/s390/cio/qdio.c deleted file mode 100644 index 2bf36e14b102..000000000000 --- a/drivers/s390/cio/qdio.c +++ /dev/null @@ -1,3929 +0,0 @@ -/* - * - * linux/drivers/s390/cio/qdio.c - * - * Linux for S/390 QDIO base support, Hipersocket base support - * version 2 - * - * Copyright 2000,2002 IBM Corporation - * Author(s): Utz Bacher - * 2.6 cio integration by Cornelia Huck - * - * Restriction: only 63 iqdio subchannels would have its own indicator, - * after that, subsequent subchannels share one indicator - * - * - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "cio.h" -#include "css.h" -#include "device.h" -#include "qdio.h" -#include "ioasm.h" -#include "chsc.h" - -/****************** MODULE PARAMETER VARIABLES ********************/ -MODULE_AUTHOR("Utz Bacher "); -MODULE_DESCRIPTION("QDIO base support version 2, " \ - "Copyright 2000 IBM Corporation"); -MODULE_LICENSE("GPL"); - -/******************** HERE WE GO ***********************************/ - -static const char version[] = "QDIO base support version 2"; - -static int qdio_performance_stats = 0; -static int proc_perf_file_registration; -static struct qdio_perf_stats perf_stats; - -static int hydra_thinints; -static int is_passthrough = 0; -static int omit_svs; - -static int indicator_used[INDICATORS_PER_CACHELINE]; -static __u32 * volatile indicators; -static __u32 volatile spare_indicator; -static atomic_t spare_indicator_usecount; -#define QDIO_MEMPOOL_SCSSC_ELEMENTS 2 -static mempool_t *qdio_mempool_scssc; -static struct kmem_cache *qdio_q_cache; - -static debug_info_t *qdio_dbf_setup; -static debug_info_t *qdio_dbf_sbal; -static debug_info_t *qdio_dbf_trace; -static debug_info_t *qdio_dbf_sense; -#ifdef CONFIG_QDIO_DEBUG -static debug_info_t *qdio_dbf_slsb_out; -static debug_info_t *qdio_dbf_slsb_in; -#endif /* CONFIG_QDIO_DEBUG */ - -/* iQDIO stuff: */ -static volatile struct qdio_q *tiq_list=NULL; /* volatile as it could change - during a while loop */ -static DEFINE_SPINLOCK(ttiq_list_lock); -static void *tiqdio_ind; -static void tiqdio_tl(unsigned long); -static DECLARE_TASKLET(tiqdio_tasklet,tiqdio_tl,0); - -/* not a macro, as one of the arguments is atomic_read */ -static inline int -qdio_min(int a,int b) -{ - if (a> 12); /* time>>12 is microseconds */ -} - -/* - * unfortunately, we can't just xchg the values; in do_QDIO we want to reserve - * the q in any case, so that we'll not be interrupted when we are in - * qdio_mark_tiq... shouldn't have a really bad impact, as reserving almost - * ever works (last famous words) - */ -static inline int -qdio_reserve_q(struct qdio_q *q) -{ - return atomic_add_return(1,&q->use_count) - 1; -} - -static inline void -qdio_release_q(struct qdio_q *q) -{ - atomic_dec(&q->use_count); -} - -/*check ccq */ -static int -qdio_check_ccq(struct qdio_q *q, unsigned int ccq) -{ - char dbf_text[15]; - - if (ccq == 0 || ccq == 32) - return 0; - if (ccq == 96 || ccq == 97) - return 1; - /*notify devices immediately*/ - sprintf(dbf_text,"%d", ccq); - QDIO_DBF_TEXT2(1,trace,dbf_text); - return -EIO; -} -/* EQBS: extract buffer states */ -static int -qdio_do_eqbs(struct qdio_q *q, unsigned char *state, - unsigned int *start, unsigned int *cnt) -{ - struct qdio_irq *irq; - unsigned int tmp_cnt, q_no, ccq; - int rc ; - char dbf_text[15]; - - ccq = 0; - tmp_cnt = *cnt; - irq = (struct qdio_irq*)q->irq_ptr; - q_no = q->q_no; - if(!q->is_input_q) - q_no += irq->no_input_qs; -again: - ccq = do_eqbs(irq->sch_token, state, q_no, start, cnt); - rc = qdio_check_ccq(q, ccq); - if ((ccq == 96) && (tmp_cnt != *cnt)) - rc = 0; - if (rc == 1) { - QDIO_DBF_TEXT5(1,trace,"eqAGAIN"); - goto again; - } - if (rc < 0) { - QDIO_DBF_TEXT2(1,trace,"eqberr"); - sprintf(dbf_text,"%2x,%2x,%d,%d",tmp_cnt, *cnt, ccq, q_no); - QDIO_DBF_TEXT2(1,trace,dbf_text); - q->handler(q->cdev,QDIO_STATUS_ACTIVATE_CHECK_CONDITION| - QDIO_STATUS_LOOK_FOR_ERROR, - 0, 0, 0, -1, -1, q->int_parm); - return 0; - } - return (tmp_cnt - *cnt); -} - -/* SQBS: set buffer states */ -static int -qdio_do_sqbs(struct qdio_q *q, unsigned char state, - unsigned int *start, unsigned int *cnt) -{ - struct qdio_irq *irq; - unsigned int tmp_cnt, q_no, ccq; - int rc; - char dbf_text[15]; - - ccq = 0; - tmp_cnt = *cnt; - irq = (struct qdio_irq*)q->irq_ptr; - q_no = q->q_no; - if(!q->is_input_q) - q_no += irq->no_input_qs; -again: - ccq = do_sqbs(irq->sch_token, state, q_no, start, cnt); - rc = qdio_check_ccq(q, ccq); - if (rc == 1) { - QDIO_DBF_TEXT5(1,trace,"sqAGAIN"); - goto again; - } - if (rc < 0) { - QDIO_DBF_TEXT3(1,trace,"sqberr"); - sprintf(dbf_text,"%2x,%2x",tmp_cnt,*cnt); - QDIO_DBF_TEXT3(1,trace,dbf_text); - sprintf(dbf_text,"%d,%d",ccq,q_no); - QDIO_DBF_TEXT3(1,trace,dbf_text); - q->handler(q->cdev,QDIO_STATUS_ACTIVATE_CHECK_CONDITION| - QDIO_STATUS_LOOK_FOR_ERROR, - 0, 0, 0, -1, -1, q->int_parm); - return 0; - } - return (tmp_cnt - *cnt); -} - -static inline int -qdio_set_slsb(struct qdio_q *q, unsigned int *bufno, - unsigned char state, unsigned int *count) -{ - volatile char *slsb; - struct qdio_irq *irq; - - irq = (struct qdio_irq*)q->irq_ptr; - if (!irq->is_qebsm) { - slsb = (char *)&q->slsb.acc.val[(*bufno)]; - xchg(slsb, state); - return 1; - } - return qdio_do_sqbs(q, state, bufno, count); -} - -#ifdef CONFIG_QDIO_DEBUG -static inline void -qdio_trace_slsb(struct qdio_q *q) -{ - if (q->queue_type==QDIO_TRACE_QTYPE) { - if (q->is_input_q) - QDIO_DBF_HEX2(0,slsb_in,&q->slsb, - QDIO_MAX_BUFFERS_PER_Q); - else - QDIO_DBF_HEX2(0,slsb_out,&q->slsb, - QDIO_MAX_BUFFERS_PER_Q); - } -} -#endif - -static inline int -set_slsb(struct qdio_q *q, unsigned int *bufno, - unsigned char state, unsigned int *count) -{ - int rc; -#ifdef CONFIG_QDIO_DEBUG - qdio_trace_slsb(q); -#endif - rc = qdio_set_slsb(q, bufno, state, count); -#ifdef CONFIG_QDIO_DEBUG - qdio_trace_slsb(q); -#endif - return rc; -} -static inline int -qdio_siga_sync(struct qdio_q *q, unsigned int gpr2, - unsigned int gpr3) -{ - int cc; - - QDIO_DBF_TEXT4(0,trace,"sigasync"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - qdio_perf_stat_inc(&perf_stats.siga_syncs); - - cc = do_siga_sync(q->schid, gpr2, gpr3); - if (cc) - QDIO_DBF_HEX3(0,trace,&cc,sizeof(int*)); - - return cc; -} - -static inline int -qdio_siga_sync_q(struct qdio_q *q) -{ - if (q->is_input_q) - return qdio_siga_sync(q, 0, q->mask); - return qdio_siga_sync(q, q->mask, 0); -} - -static int -__do_siga_output(struct qdio_q *q, unsigned int *busy_bit) -{ - struct qdio_irq *irq; - unsigned int fc = 0; - unsigned long schid; - - irq = (struct qdio_irq *) q->irq_ptr; - if (!irq->is_qebsm) - schid = *((u32 *)&q->schid); - else { - schid = irq->sch_token; - fc |= 0x80; - } - return do_siga_output(schid, q->mask, busy_bit, fc); -} - -/* - * returns QDIO_SIGA_ERROR_ACCESS_EXCEPTION as cc, when SIGA returns - * an access exception - */ -static int -qdio_siga_output(struct qdio_q *q) -{ - int cc; - __u32 busy_bit; - __u64 start_time=0; - - qdio_perf_stat_inc(&perf_stats.siga_outs); - - QDIO_DBF_TEXT4(0,trace,"sigaout"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - for (;;) { - cc = __do_siga_output(q, &busy_bit); -//QDIO_PRINT_ERR("cc=%x, busy=%x\n",cc,busy_bit); - if ((cc==2) && (busy_bit) && (q->is_iqdio_q)) { - if (!start_time) - start_time=NOW; - if ((NOW-start_time)>QDIO_BUSY_BIT_PATIENCE) - break; - } else - break; - } - - if ((cc==2) && (busy_bit)) - cc |= QDIO_SIGA_ERROR_B_BIT_SET; - - if (cc) - QDIO_DBF_HEX3(0,trace,&cc,sizeof(int*)); - - return cc; -} - -static int -qdio_siga_input(struct qdio_q *q) -{ - int cc; - - QDIO_DBF_TEXT4(0,trace,"sigain"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - qdio_perf_stat_inc(&perf_stats.siga_ins); - - cc = do_siga_input(q->schid, q->mask); - - if (cc) - QDIO_DBF_HEX3(0,trace,&cc,sizeof(int*)); - - return cc; -} - -/* locked by the locks in qdio_activate and qdio_cleanup */ -static __u32 * -qdio_get_indicator(void) -{ - int i; - - for (i = 0; i < INDICATORS_PER_CACHELINE; i++) - if (!indicator_used[i]) { - indicator_used[i]=1; - return indicators+i; - } - atomic_inc(&spare_indicator_usecount); - return (__u32 * volatile) &spare_indicator; -} - -/* locked by the locks in qdio_activate and qdio_cleanup */ -static void -qdio_put_indicator(__u32 *addr) -{ - int i; - - if ( (addr) && (addr!=&spare_indicator) ) { - i=addr-indicators; - indicator_used[i]=0; - } - if (addr == &spare_indicator) - atomic_dec(&spare_indicator_usecount); -} - -static inline void -tiqdio_clear_summary_bit(__u32 *location) -{ - QDIO_DBF_TEXT5(0,trace,"clrsummb"); - QDIO_DBF_HEX5(0,trace,&location,sizeof(void*)); - - xchg(location,0); -} - -static inline void -tiqdio_set_summary_bit(__u32 *location) -{ - QDIO_DBF_TEXT5(0,trace,"setsummb"); - QDIO_DBF_HEX5(0,trace,&location,sizeof(void*)); - - xchg(location,-1); -} - -static inline void -tiqdio_sched_tl(void) -{ - tasklet_hi_schedule(&tiqdio_tasklet); -} - -static void -qdio_mark_tiq(struct qdio_q *q) -{ - unsigned long flags; - - QDIO_DBF_TEXT4(0,trace,"mark iq"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - spin_lock_irqsave(&ttiq_list_lock,flags); - if (unlikely(atomic_read(&q->is_in_shutdown))) - goto out_unlock; - - if (!q->is_input_q) - goto out_unlock; - - if ((q->list_prev) || (q->list_next)) - goto out_unlock; - - if (!tiq_list) { - tiq_list=q; - q->list_prev=q; - q->list_next=q; - } else { - q->list_next=tiq_list; - q->list_prev=tiq_list->list_prev; - tiq_list->list_prev->list_next=q; - tiq_list->list_prev=q; - } - spin_unlock_irqrestore(&ttiq_list_lock,flags); - - tiqdio_set_summary_bit((__u32*)q->dev_st_chg_ind); - tiqdio_sched_tl(); - return; -out_unlock: - spin_unlock_irqrestore(&ttiq_list_lock,flags); - return; -} - -static inline void -qdio_mark_q(struct qdio_q *q) -{ - QDIO_DBF_TEXT4(0,trace,"mark q"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - if (unlikely(atomic_read(&q->is_in_shutdown))) - return; - - tasklet_schedule(&q->tasklet); -} - -static int -qdio_stop_polling(struct qdio_q *q) -{ -#ifdef QDIO_USE_PROCESSING_STATE - unsigned int tmp, gsf, count = 1; - unsigned char state = 0; - struct qdio_irq *irq = (struct qdio_irq *) q->irq_ptr; - - if (!atomic_xchg(&q->polling,0)) - return 1; - - QDIO_DBF_TEXT4(0,trace,"stoppoll"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - /* show the card that we are not polling anymore */ - if (!q->is_input_q) - return 1; - - tmp = gsf = GET_SAVED_FRONTIER(q); - tmp = ((tmp + QDIO_MAX_BUFFERS_PER_Q-1) & (QDIO_MAX_BUFFERS_PER_Q-1) ); - set_slsb(q, &tmp, SLSB_P_INPUT_NOT_INIT, &count); - - /* - * we don't issue this SYNC_MEMORY, as we trust Rick T and - * moreover will not use the PROCESSING state under VM, so - * q->polling was 0 anyway - */ - /*SYNC_MEMORY;*/ - if (irq->is_qebsm) { - count = 1; - qdio_do_eqbs(q, &state, &gsf, &count); - } else - state = q->slsb.acc.val[gsf]; - if (state != SLSB_P_INPUT_PRIMED) - return 1; - /* - * set our summary bit again, as otherwise there is a - * small window we can miss between resetting it and - * checking for PRIMED state - */ - if (q->is_thinint_q) - tiqdio_set_summary_bit((__u32*)q->dev_st_chg_ind); - return 0; - -#else /* QDIO_USE_PROCESSING_STATE */ - return 1; -#endif /* QDIO_USE_PROCESSING_STATE */ -} - -/* - * see the comment in do_QDIO and before qdio_reserve_q about the - * sophisticated locking outside of unmark_q, so that we don't need to - * disable the interrupts :-) -*/ -static void -qdio_unmark_q(struct qdio_q *q) -{ - unsigned long flags; - - QDIO_DBF_TEXT4(0,trace,"unmark q"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - if ((!q->list_prev)||(!q->list_next)) - return; - - if ((q->is_thinint_q)&&(q->is_input_q)) { - /* iQDIO */ - spin_lock_irqsave(&ttiq_list_lock,flags); - /* in case cleanup has done this already and simultanously - * qdio_unmark_q is called from the interrupt handler, we've - * got to check this in this specific case again */ - if ((!q->list_prev)||(!q->list_next)) - goto out; - if (q->list_next==q) { - /* q was the only interesting q */ - tiq_list=NULL; - q->list_next=NULL; - q->list_prev=NULL; - } else { - q->list_next->list_prev=q->list_prev; - q->list_prev->list_next=q->list_next; - tiq_list=q->list_next; - q->list_next=NULL; - q->list_prev=NULL; - } -out: - spin_unlock_irqrestore(&ttiq_list_lock,flags); - } -} - -static inline unsigned long -tiqdio_clear_global_summary(void) -{ - unsigned long time; - - QDIO_DBF_TEXT5(0,trace,"clrglobl"); - - time = do_clear_global_summary(); - - QDIO_DBF_HEX5(0,trace,&time,sizeof(unsigned long)); - - return time; -} - - -/************************* OUTBOUND ROUTINES *******************************/ -static int -qdio_qebsm_get_outbound_buffer_frontier(struct qdio_q *q) -{ - struct qdio_irq *irq; - unsigned char state; - unsigned int cnt, count, ftc; - - irq = (struct qdio_irq *) q->irq_ptr; - if ((!q->is_iqdio_q) && (!q->hydra_gives_outbound_pcis)) - SYNC_MEMORY; - - ftc = q->first_to_check; - count = qdio_min(atomic_read(&q->number_of_buffers_used), - (QDIO_MAX_BUFFERS_PER_Q-1)); - if (count == 0) - return q->first_to_check; - cnt = qdio_do_eqbs(q, &state, &ftc, &count); - if (cnt == 0) - return q->first_to_check; - switch (state) { - case SLSB_P_OUTPUT_ERROR: - QDIO_DBF_TEXT3(0,trace,"outperr"); - atomic_sub(cnt , &q->number_of_buffers_used); - if (q->qdio_error) - q->error_status_flags |= - QDIO_STATUS_MORE_THAN_ONE_QDIO_ERROR; - q->qdio_error = SLSB_P_OUTPUT_ERROR; - q->error_status_flags |= QDIO_STATUS_LOOK_FOR_ERROR; - q->first_to_check = ftc; - break; - case SLSB_P_OUTPUT_EMPTY: - QDIO_DBF_TEXT5(0,trace,"outpempt"); - atomic_sub(cnt, &q->number_of_buffers_used); - q->first_to_check = ftc; - break; - case SLSB_CU_OUTPUT_PRIMED: - /* all buffers primed */ - QDIO_DBF_TEXT5(0,trace,"outpprim"); - break; - default: - break; - } - QDIO_DBF_HEX4(0,trace,&q->first_to_check,sizeof(int)); - return q->first_to_check; -} - -static int -qdio_qebsm_get_inbound_buffer_frontier(struct qdio_q *q) -{ - struct qdio_irq *irq; - unsigned char state; - int tmp, ftc, count, cnt; - char dbf_text[15]; - - - irq = (struct qdio_irq *) q->irq_ptr; - ftc = q->first_to_check; - count = qdio_min(atomic_read(&q->number_of_buffers_used), - (QDIO_MAX_BUFFERS_PER_Q-1)); - if (count == 0) - return q->first_to_check; - cnt = qdio_do_eqbs(q, &state, &ftc, &count); - if (cnt == 0) - return q->first_to_check; - switch (state) { - case SLSB_P_INPUT_ERROR : -#ifdef CONFIG_QDIO_DEBUG - QDIO_DBF_TEXT3(1,trace,"inperr"); - sprintf(dbf_text,"%2x,%2x",ftc,count); - QDIO_DBF_TEXT3(1,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - if (q->qdio_error) - q->error_status_flags |= - QDIO_STATUS_MORE_THAN_ONE_QDIO_ERROR; - q->qdio_error = SLSB_P_INPUT_ERROR; - q->error_status_flags |= QDIO_STATUS_LOOK_FOR_ERROR; - atomic_sub(cnt, &q->number_of_buffers_used); - q->first_to_check = ftc; - break; - case SLSB_P_INPUT_PRIMED : - QDIO_DBF_TEXT3(0,trace,"inptprim"); - sprintf(dbf_text,"%2x,%2x",ftc,count); - QDIO_DBF_TEXT3(1,trace,dbf_text); - tmp = 0; - ftc = q->first_to_check; -#ifdef QDIO_USE_PROCESSING_STATE - if (cnt > 1) { - cnt -= 1; - tmp = set_slsb(q, &ftc, SLSB_P_INPUT_NOT_INIT, &cnt); - if (!tmp) - break; - } - cnt = 1; - tmp += set_slsb(q, &ftc, - SLSB_P_INPUT_PROCESSING, &cnt); - atomic_set(&q->polling, 1); -#else - tmp = set_slsb(q, &ftc, SLSB_P_INPUT_NOT_INIT, &cnt); -#endif - atomic_sub(tmp, &q->number_of_buffers_used); - q->first_to_check = ftc; - break; - case SLSB_CU_INPUT_EMPTY: - case SLSB_P_INPUT_NOT_INIT: - case SLSB_P_INPUT_PROCESSING: - QDIO_DBF_TEXT5(0,trace,"inpnipro"); - break; - default: - break; - } - QDIO_DBF_HEX4(0,trace,&q->first_to_check,sizeof(int)); - return q->first_to_check; -} - -static int -qdio_get_outbound_buffer_frontier(struct qdio_q *q) -{ - struct qdio_irq *irq; - volatile char *slsb; - unsigned int count = 1; - int first_not_to_check, f, f_mod_no; - char dbf_text[15]; - - QDIO_DBF_TEXT4(0,trace,"getobfro"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - irq = (struct qdio_irq *) q->irq_ptr; - if (irq->is_qebsm) - return qdio_qebsm_get_outbound_buffer_frontier(q); - - slsb=&q->slsb.acc.val[0]; - f_mod_no=f=q->first_to_check; - /* - * f points to already processed elements, so f+no_used is correct... - * ... but: we don't check 128 buffers, as otherwise - * qdio_has_outbound_q_moved would return 0 - */ - first_not_to_check=f+qdio_min(atomic_read(&q->number_of_buffers_used), - (QDIO_MAX_BUFFERS_PER_Q-1)); - - if (((!q->is_iqdio_q) && (!q->hydra_gives_outbound_pcis)) || - (q->queue_type == QDIO_IQDIO_QFMT_ASYNCH)) - SYNC_MEMORY; - -check_next: - if (f==first_not_to_check) - goto out; - - switch(slsb[f_mod_no]) { - - /* the adapter has not fetched the output yet */ - case SLSB_CU_OUTPUT_PRIMED: - QDIO_DBF_TEXT5(0,trace,"outpprim"); - break; - - /* the adapter got it */ - case SLSB_P_OUTPUT_EMPTY: - atomic_dec(&q->number_of_buffers_used); - f++; - f_mod_no=f&(QDIO_MAX_BUFFERS_PER_Q-1); - QDIO_DBF_TEXT5(0,trace,"outpempt"); - goto check_next; - - case SLSB_P_OUTPUT_ERROR: - QDIO_DBF_TEXT3(0,trace,"outperr"); - sprintf(dbf_text,"%x-%x-%x",f_mod_no, - q->sbal[f_mod_no]->element[14].sbalf.value, - q->sbal[f_mod_no]->element[15].sbalf.value); - QDIO_DBF_TEXT3(1,trace,dbf_text); - QDIO_DBF_HEX2(1,sbal,q->sbal[f_mod_no],256); - - /* kind of process the buffer */ - set_slsb(q, &f_mod_no, SLSB_P_OUTPUT_NOT_INIT, &count); - - /* - * we increment the frontier, as this buffer - * was processed obviously - */ - atomic_dec(&q->number_of_buffers_used); - f_mod_no=(f_mod_no+1)&(QDIO_MAX_BUFFERS_PER_Q-1); - - if (q->qdio_error) - q->error_status_flags|= - QDIO_STATUS_MORE_THAN_ONE_QDIO_ERROR; - q->qdio_error=SLSB_P_OUTPUT_ERROR; - q->error_status_flags|=QDIO_STATUS_LOOK_FOR_ERROR; - - break; - - /* no new buffers */ - default: - QDIO_DBF_TEXT5(0,trace,"outpni"); - } -out: - return (q->first_to_check=f_mod_no); -} - -/* all buffers are processed */ -static int -qdio_is_outbound_q_done(struct qdio_q *q) -{ - int no_used; -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[15]; -#endif - - no_used=atomic_read(&q->number_of_buffers_used); - -#ifdef CONFIG_QDIO_DEBUG - if (no_used) { - sprintf(dbf_text,"oqisnt%02x",no_used); - QDIO_DBF_TEXT4(0,trace,dbf_text); - } else { - QDIO_DBF_TEXT4(0,trace,"oqisdone"); - } - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); -#endif /* CONFIG_QDIO_DEBUG */ - return (no_used==0); -} - -static int -qdio_has_outbound_q_moved(struct qdio_q *q) -{ - int i; - - i=qdio_get_outbound_buffer_frontier(q); - - if ( (i!=GET_SAVED_FRONTIER(q)) || - (q->error_status_flags&QDIO_STATUS_LOOK_FOR_ERROR) ) { - SAVE_FRONTIER(q,i); - QDIO_DBF_TEXT4(0,trace,"oqhasmvd"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - return 1; - } else { - QDIO_DBF_TEXT4(0,trace,"oqhsntmv"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - return 0; - } -} - -static void -qdio_kick_outbound_q(struct qdio_q *q) -{ - int result; -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[15]; - - QDIO_DBF_TEXT4(0,trace,"kickoutq"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); -#endif /* CONFIG_QDIO_DEBUG */ - - if (!q->siga_out) - return; - - /* here's the story with cc=2 and busy bit set (thanks, Rick): - * VM's CP could present us cc=2 and busy bit set on SIGA-write - * during reconfiguration of their Guest LAN (only in HIPERS mode, - * QDIO mode is asynchronous -- cc=2 and busy bit there will take - * the queues down immediately; and not being under VM we have a - * problem on cc=2 and busy bit set right away). - * - * Therefore qdio_siga_output will try for a short time constantly, - * if such a condition occurs. If it doesn't change, it will - * increase the busy_siga_counter and save the timestamp, and - * schedule the queue for later processing (via mark_q, using the - * queue tasklet). __qdio_outbound_processing will check out the - * counter. If non-zero, it will call qdio_kick_outbound_q as often - * as the value of the counter. This will attempt further SIGA - * instructions. For each successful SIGA, the counter is - * decreased, for failing SIGAs the counter remains the same, after - * all. - * After some time of no movement, qdio_kick_outbound_q will - * finally fail and reflect corresponding error codes to call - * the upper layer module and have it take the queues down. - * - * Note that this is a change from the original HiperSockets design - * (saying cc=2 and busy bit means take the queues down), but in - * these days Guest LAN didn't exist... excessive cc=2 with busy bit - * conditions will still take the queues down, but the threshold is - * higher due to the Guest LAN environment. - */ - - - result=qdio_siga_output(q); - - switch (result) { - case 0: - /* went smooth this time, reset timestamp */ -#ifdef CONFIG_QDIO_DEBUG - QDIO_DBF_TEXT3(0,trace,"cc2reslv"); - sprintf(dbf_text,"%4x%2x%2x",q->schid.sch_no,q->q_no, - atomic_read(&q->busy_siga_counter)); - QDIO_DBF_TEXT3(0,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - q->timing.busy_start=0; - break; - case (2|QDIO_SIGA_ERROR_B_BIT_SET): - /* cc=2 and busy bit: */ - atomic_inc(&q->busy_siga_counter); - - /* if the last siga was successful, save - * timestamp here */ - if (!q->timing.busy_start) - q->timing.busy_start=NOW; - - /* if we're in time, don't touch error_status_flags - * and siga_error */ - if (NOW-q->timing.busy_startschid.sch_no,q->q_no, - atomic_read(&q->busy_siga_counter)); - QDIO_DBF_TEXT3(0,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - /* else fallthrough and report error */ - default: - /* for plain cc=1, 2 or 3: */ - if (q->siga_error) - q->error_status_flags|= - QDIO_STATUS_MORE_THAN_ONE_SIGA_ERROR; - q->error_status_flags|= - QDIO_STATUS_LOOK_FOR_ERROR; - q->siga_error=result; - } -} - -static void -qdio_kick_outbound_handler(struct qdio_q *q) -{ - int start, end, real_end, count; -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[15]; -#endif - - start = q->first_element_to_kick; - /* last_move_ftc was just updated */ - real_end = GET_SAVED_FRONTIER(q); - end = (real_end+QDIO_MAX_BUFFERS_PER_Q-1)& - (QDIO_MAX_BUFFERS_PER_Q-1); - count = (end+QDIO_MAX_BUFFERS_PER_Q+1-start)& - (QDIO_MAX_BUFFERS_PER_Q-1); - -#ifdef CONFIG_QDIO_DEBUG - QDIO_DBF_TEXT4(0,trace,"kickouth"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - sprintf(dbf_text,"s=%2xc=%2x",start,count); - QDIO_DBF_TEXT4(0,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - - if (q->state==QDIO_IRQ_STATE_ACTIVE) - q->handler(q->cdev,QDIO_STATUS_OUTBOUND_INT| - q->error_status_flags, - q->qdio_error,q->siga_error,q->q_no,start,count, - q->int_parm); - - /* for the next time: */ - q->first_element_to_kick=real_end; - q->qdio_error=0; - q->siga_error=0; - q->error_status_flags=0; -} - -static void -__qdio_outbound_processing(struct qdio_q *q) -{ - int siga_attempts; - - QDIO_DBF_TEXT4(0,trace,"qoutproc"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - if (unlikely(qdio_reserve_q(q))) { - qdio_release_q(q); - qdio_perf_stat_inc(&perf_stats.outbound_tl_runs_resched); - /* as we're sissies, we'll check next time */ - if (likely(!atomic_read(&q->is_in_shutdown))) { - qdio_mark_q(q); - QDIO_DBF_TEXT4(0,trace,"busy,agn"); - } - return; - } - qdio_perf_stat_inc(&perf_stats.outbound_tl_runs); - qdio_perf_stat_inc(&perf_stats.tl_runs); - - /* see comment in qdio_kick_outbound_q */ - siga_attempts=atomic_read(&q->busy_siga_counter); - while (siga_attempts) { - atomic_dec(&q->busy_siga_counter); - qdio_kick_outbound_q(q); - siga_attempts--; - } - - if (qdio_has_outbound_q_moved(q)) - qdio_kick_outbound_handler(q); - - if (q->queue_type == QDIO_ZFCP_QFMT) { - if ((!q->hydra_gives_outbound_pcis) && - (!qdio_is_outbound_q_done(q))) - qdio_mark_q(q); - } - else if (((!q->is_iqdio_q) && (!q->is_pci_out)) || - (q->queue_type == QDIO_IQDIO_QFMT_ASYNCH)) { - /* - * make sure buffer switch from PRIMED to EMPTY is noticed - * and outbound_handler is called - */ - if (qdio_is_outbound_q_done(q)) { - del_timer(&q->timer); - } else { - if (!timer_pending(&q->timer)) - mod_timer(&q->timer, jiffies + - QDIO_FORCE_CHECK_TIMEOUT); - } - } - - qdio_release_q(q); -} - -static void -qdio_outbound_processing(unsigned long q) -{ - __qdio_outbound_processing((struct qdio_q *) q); -} - -/************************* INBOUND ROUTINES *******************************/ - - -static int -qdio_get_inbound_buffer_frontier(struct qdio_q *q) -{ - struct qdio_irq *irq; - int f,f_mod_no; - volatile char *slsb; - unsigned int count = 1; - int first_not_to_check; -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[15]; -#endif /* CONFIG_QDIO_DEBUG */ -#ifdef QDIO_USE_PROCESSING_STATE - int last_position=-1; -#endif /* QDIO_USE_PROCESSING_STATE */ - - QDIO_DBF_TEXT4(0,trace,"getibfro"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - irq = (struct qdio_irq *) q->irq_ptr; - if (irq->is_qebsm) - return qdio_qebsm_get_inbound_buffer_frontier(q); - - slsb=&q->slsb.acc.val[0]; - f_mod_no=f=q->first_to_check; - /* - * we don't check 128 buffers, as otherwise qdio_has_inbound_q_moved - * would return 0 - */ - first_not_to_check=f+qdio_min(atomic_read(&q->number_of_buffers_used), - (QDIO_MAX_BUFFERS_PER_Q-1)); - - /* - * we don't use this one, as a PCI or we after a thin interrupt - * will sync the queues - */ - /* SYNC_MEMORY;*/ - -check_next: - f_mod_no=f&(QDIO_MAX_BUFFERS_PER_Q-1); - if (f==first_not_to_check) - goto out; - switch (slsb[f_mod_no]) { - - /* CU_EMPTY means frontier is reached */ - case SLSB_CU_INPUT_EMPTY: - QDIO_DBF_TEXT5(0,trace,"inptempt"); - break; - - /* P_PRIMED means set slsb to P_PROCESSING and move on */ - case SLSB_P_INPUT_PRIMED: - QDIO_DBF_TEXT5(0,trace,"inptprim"); - -#ifdef QDIO_USE_PROCESSING_STATE - /* - * as soon as running under VM, polling the input queues will - * kill VM in terms of CP overhead - */ - if (q->siga_sync) { - set_slsb(q, &f_mod_no, SLSB_P_INPUT_NOT_INIT, &count); - } else { - /* set the previous buffer to NOT_INIT. The current - * buffer will be set to PROCESSING at the end of - * this function to avoid further interrupts. */ - if (last_position>=0) - set_slsb(q, &last_position, - SLSB_P_INPUT_NOT_INIT, &count); - atomic_set(&q->polling,1); - last_position=f_mod_no; - } -#else /* QDIO_USE_PROCESSING_STATE */ - set_slsb(q, &f_mod_no, SLSB_P_INPUT_NOT_INIT, &count); -#endif /* QDIO_USE_PROCESSING_STATE */ - /* - * not needed, as the inbound queue will be synced on the next - * siga-r, resp. tiqdio_is_inbound_q_done will do the siga-s - */ - /*SYNC_MEMORY;*/ - f++; - atomic_dec(&q->number_of_buffers_used); - goto check_next; - - case SLSB_P_INPUT_NOT_INIT: - case SLSB_P_INPUT_PROCESSING: - QDIO_DBF_TEXT5(0,trace,"inpnipro"); - break; - - /* P_ERROR means frontier is reached, break and report error */ - case SLSB_P_INPUT_ERROR: -#ifdef CONFIG_QDIO_DEBUG - sprintf(dbf_text,"inperr%2x",f_mod_no); - QDIO_DBF_TEXT3(1,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - QDIO_DBF_HEX2(1,sbal,q->sbal[f_mod_no],256); - - /* kind of process the buffer */ - set_slsb(q, &f_mod_no, SLSB_P_INPUT_NOT_INIT, &count); - - if (q->qdio_error) - q->error_status_flags|= - QDIO_STATUS_MORE_THAN_ONE_QDIO_ERROR; - q->qdio_error=SLSB_P_INPUT_ERROR; - q->error_status_flags|=QDIO_STATUS_LOOK_FOR_ERROR; - - /* we increment the frontier, as this buffer - * was processed obviously */ - f_mod_no=(f_mod_no+1)&(QDIO_MAX_BUFFERS_PER_Q-1); - atomic_dec(&q->number_of_buffers_used); - -#ifdef QDIO_USE_PROCESSING_STATE - last_position=-1; -#endif /* QDIO_USE_PROCESSING_STATE */ - - break; - - /* everything else means frontier not changed (HALTED or so) */ - default: - break; - } -out: - q->first_to_check=f_mod_no; - -#ifdef QDIO_USE_PROCESSING_STATE - if (last_position>=0) - set_slsb(q, &last_position, SLSB_P_INPUT_PROCESSING, &count); -#endif /* QDIO_USE_PROCESSING_STATE */ - - QDIO_DBF_HEX4(0,trace,&q->first_to_check,sizeof(int)); - - return q->first_to_check; -} - -static int -qdio_has_inbound_q_moved(struct qdio_q *q) -{ - int i; - - i=qdio_get_inbound_buffer_frontier(q); - if ( (i!=GET_SAVED_FRONTIER(q)) || - (q->error_status_flags&QDIO_STATUS_LOOK_FOR_ERROR) ) { - SAVE_FRONTIER(q,i); - if ((!q->siga_sync)&&(!q->hydra_gives_outbound_pcis)) - SAVE_TIMESTAMP(q); - - QDIO_DBF_TEXT4(0,trace,"inhasmvd"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - return 1; - } else { - QDIO_DBF_TEXT4(0,trace,"inhsntmv"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - return 0; - } -} - -/* means, no more buffers to be filled */ -static int -tiqdio_is_inbound_q_done(struct qdio_q *q) -{ - int no_used; - unsigned int start_buf, count; - unsigned char state = 0; - struct qdio_irq *irq = (struct qdio_irq *) q->irq_ptr; - -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[15]; -#endif - - no_used=atomic_read(&q->number_of_buffers_used); - - /* propagate the change from 82 to 80 through VM */ - SYNC_MEMORY; - -#ifdef CONFIG_QDIO_DEBUG - if (no_used) { - sprintf(dbf_text,"iqisnt%02x",no_used); - QDIO_DBF_TEXT4(0,trace,dbf_text); - } else { - QDIO_DBF_TEXT4(0,trace,"iniqisdo"); - } - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); -#endif /* CONFIG_QDIO_DEBUG */ - - if (!no_used) - return 1; - if (irq->is_qebsm) { - count = 1; - start_buf = q->first_to_check; - qdio_do_eqbs(q, &state, &start_buf, &count); - } else - state = q->slsb.acc.val[q->first_to_check]; - if (state != SLSB_P_INPUT_PRIMED) - /* - * nothing more to do, if next buffer is not PRIMED. - * note that we did a SYNC_MEMORY before, that there - * has been a sychnronization. - * we will return 0 below, as there is nothing to do - * (stop_polling not necessary, as we have not been - * using the PROCESSING state - */ - return 0; - - /* - * ok, the next input buffer is primed. that means, that device state - * change indicator and adapter local summary are set, so we will find - * it next time. - * we will return 0 below, as there is nothing to do, except scheduling - * ourselves for the next time. - */ - tiqdio_set_summary_bit((__u32*)q->dev_st_chg_ind); - tiqdio_sched_tl(); - return 0; -} - -static int -qdio_is_inbound_q_done(struct qdio_q *q) -{ - int no_used; - unsigned int start_buf, count; - unsigned char state = 0; - struct qdio_irq *irq = (struct qdio_irq *) q->irq_ptr; - -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[15]; -#endif - - no_used=atomic_read(&q->number_of_buffers_used); - - /* - * we need that one for synchronization with the adapter, as it - * does a kind of PCI avoidance - */ - SYNC_MEMORY; - - if (!no_used) { - QDIO_DBF_TEXT4(0,trace,"inqisdnA"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - return 1; - } - if (irq->is_qebsm) { - count = 1; - start_buf = q->first_to_check; - qdio_do_eqbs(q, &state, &start_buf, &count); - } else - state = q->slsb.acc.val[q->first_to_check]; - if (state == SLSB_P_INPUT_PRIMED) { - /* we got something to do */ - QDIO_DBF_TEXT4(0,trace,"inqisntA"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - return 0; - } - - /* on VM, we don't poll, so the q is always done here */ - if (q->siga_sync) - return 1; - if (q->hydra_gives_outbound_pcis) - return 1; - - /* - * at this point we know, that inbound first_to_check - * has (probably) not moved (see qdio_inbound_processing) - */ - if (NOW>GET_SAVED_TIMESTAMP(q)+q->timing.threshold) { -#ifdef CONFIG_QDIO_DEBUG - QDIO_DBF_TEXT4(0,trace,"inqisdon"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - sprintf(dbf_text,"pf%02xcn%02x",q->first_to_check,no_used); - QDIO_DBF_TEXT4(0,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - return 1; - } else { -#ifdef CONFIG_QDIO_DEBUG - QDIO_DBF_TEXT4(0,trace,"inqisntd"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - sprintf(dbf_text,"pf%02xcn%02x",q->first_to_check,no_used); - QDIO_DBF_TEXT4(0,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - return 0; - } -} - -static void -qdio_kick_inbound_handler(struct qdio_q *q) -{ - int count, start, end, real_end, i; -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[15]; -#endif - - QDIO_DBF_TEXT4(0,trace,"kickinh"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - start=q->first_element_to_kick; - real_end=q->first_to_check; - end=(real_end+QDIO_MAX_BUFFERS_PER_Q-1)&(QDIO_MAX_BUFFERS_PER_Q-1); - - i=start; - count=0; - while (1) { - count++; - if (i==end) - break; - i=(i+1)&(QDIO_MAX_BUFFERS_PER_Q-1); - } - -#ifdef CONFIG_QDIO_DEBUG - sprintf(dbf_text,"s=%2xc=%2x",start,count); - QDIO_DBF_TEXT4(0,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - - if (likely(q->state==QDIO_IRQ_STATE_ACTIVE)) - q->handler(q->cdev, - QDIO_STATUS_INBOUND_INT|q->error_status_flags, - q->qdio_error,q->siga_error,q->q_no,start,count, - q->int_parm); - - /* for the next time: */ - q->first_element_to_kick=real_end; - q->qdio_error=0; - q->siga_error=0; - q->error_status_flags=0; - - qdio_perf_stat_inc(&perf_stats.inbound_cnt); -} - -static void -__tiqdio_inbound_processing(struct qdio_q *q, int spare_ind_was_set) -{ - struct qdio_irq *irq_ptr; - struct qdio_q *oq; - int i; - - QDIO_DBF_TEXT4(0,trace,"iqinproc"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - /* - * we first want to reserve the q, so that we know, that we don't - * interrupt ourselves and call qdio_unmark_q, as is_in_shutdown might - * be set - */ - if (unlikely(qdio_reserve_q(q))) { - qdio_release_q(q); - qdio_perf_stat_inc(&perf_stats.inbound_thin_tl_runs_resched); - /* - * as we might just be about to stop polling, we make - * sure that we check again at least once more - */ - tiqdio_sched_tl(); - return; - } - qdio_perf_stat_inc(&perf_stats.inbound_thin_tl_runs); - if (unlikely(atomic_read(&q->is_in_shutdown))) { - qdio_unmark_q(q); - goto out; - } - - /* - * we reset spare_ind_was_set, when the queue does not use the - * spare indicator - */ - if (spare_ind_was_set) - spare_ind_was_set = (q->dev_st_chg_ind == &spare_indicator); - - if (!(*(q->dev_st_chg_ind)) && !spare_ind_was_set) - goto out; - /* - * q->dev_st_chg_ind is the indicator, be it shared or not. - * only clear it, if indicator is non-shared - */ - if (q->dev_st_chg_ind != &spare_indicator) - tiqdio_clear_summary_bit((__u32*)q->dev_st_chg_ind); - - if (q->hydra_gives_outbound_pcis) { - if (!q->siga_sync_done_on_thinints) { - SYNC_MEMORY_ALL; - } else if (!q->siga_sync_done_on_outb_tis) { - SYNC_MEMORY_ALL_OUTB; - } - } else { - SYNC_MEMORY; - } - /* - * maybe we have to do work on our outbound queues... at least - * we have to check the outbound-int-capable thinint-capable - * queues - */ - if (q->hydra_gives_outbound_pcis) { - irq_ptr = (struct qdio_irq*)q->irq_ptr; - for (i=0;ino_output_qs;i++) { - oq = irq_ptr->output_qs[i]; - if (!qdio_is_outbound_q_done(oq)) { - qdio_perf_stat_dec(&perf_stats.tl_runs); - __qdio_outbound_processing(oq); - } - } - } - - if (!qdio_has_inbound_q_moved(q)) - goto out; - - qdio_kick_inbound_handler(q); - if (tiqdio_is_inbound_q_done(q)) - if (!qdio_stop_polling(q)) { - /* - * we set the flags to get into the stuff next time, - * see also comment in qdio_stop_polling - */ - tiqdio_set_summary_bit((__u32*)q->dev_st_chg_ind); - tiqdio_sched_tl(); - } -out: - qdio_release_q(q); -} - -static void -tiqdio_inbound_processing(unsigned long q) -{ - __tiqdio_inbound_processing((struct qdio_q *) q, - atomic_read(&spare_indicator_usecount)); -} - -static void -__qdio_inbound_processing(struct qdio_q *q) -{ - int q_laps=0; - - QDIO_DBF_TEXT4(0,trace,"qinproc"); - QDIO_DBF_HEX4(0,trace,&q,sizeof(void*)); - - if (unlikely(qdio_reserve_q(q))) { - qdio_release_q(q); - qdio_perf_stat_inc(&perf_stats.inbound_tl_runs_resched); - /* as we're sissies, we'll check next time */ - if (likely(!atomic_read(&q->is_in_shutdown))) { - qdio_mark_q(q); - QDIO_DBF_TEXT4(0,trace,"busy,agn"); - } - return; - } - qdio_perf_stat_inc(&perf_stats.inbound_tl_runs); - qdio_perf_stat_inc(&perf_stats.tl_runs); - -again: - if (qdio_has_inbound_q_moved(q)) { - qdio_kick_inbound_handler(q); - if (!qdio_stop_polling(q)) { - q_laps++; - if (q_lapssiga_sync) - return 2; - - if (unlikely(qdio_reserve_q(q))) { - qdio_release_q(q); - qdio_perf_stat_inc(&perf_stats.inbound_thin_tl_runs_resched); - /* - * as we might just be about to stop polling, we make - * sure that we check again at least once more - */ - - /* - * sanity -- we'd get here without setting the - * dev st chg ind - */ - tiqdio_set_summary_bit((__u32*)q->dev_st_chg_ind); - tiqdio_sched_tl(); - return 0; - } - if (qdio_stop_polling(q)) { - qdio_release_q(q); - return 2; - } - if (q_lapsdev_st_chg_ind); - tiqdio_sched_tl(); - qdio_release_q(q); - return 1; - -} -#endif /* QDIO_USE_PROCESSING_STATE */ - -static void -tiqdio_inbound_checks(void) -{ - struct qdio_q *q; - int spare_ind_was_set=0; -#ifdef QDIO_USE_PROCESSING_STATE - int q_laps=0; -#endif /* QDIO_USE_PROCESSING_STATE */ - - QDIO_DBF_TEXT4(0,trace,"iqdinbck"); - QDIO_DBF_TEXT5(0,trace,"iqlocsum"); - -#ifdef QDIO_USE_PROCESSING_STATE -again: -#endif /* QDIO_USE_PROCESSING_STATE */ - - /* when the spare indicator is used and set, save that and clear it */ - if ((atomic_read(&spare_indicator_usecount)) && spare_indicator) { - spare_ind_was_set = 1; - tiqdio_clear_summary_bit((__u32*)&spare_indicator); - } - - q=(struct qdio_q*)tiq_list; - do { - if (!q) - break; - __tiqdio_inbound_processing(q, spare_ind_was_set); - q=(struct qdio_q*)q->list_next; - } while (q!=(struct qdio_q*)tiq_list); - -#ifdef QDIO_USE_PROCESSING_STATE - q=(struct qdio_q*)tiq_list; - do { - int ret; - - ret = tiqdio_reset_processing_state(q, q_laps); - switch (ret) { - case 0: - return; - case 1: - q_laps++; - case 2: - q = (struct qdio_q*)q->list_next; - break; - default: - q_laps++; - goto again; - } - } while (q!=(struct qdio_q*)tiq_list); -#endif /* QDIO_USE_PROCESSING_STATE */ -} - -static void -tiqdio_tl(unsigned long data) -{ - QDIO_DBF_TEXT4(0,trace,"iqdio_tl"); - - qdio_perf_stat_inc(&perf_stats.tl_runs); - - tiqdio_inbound_checks(); -} - -/********************* GENERAL HELPER_ROUTINES ***********************/ - -static void -qdio_release_irq_memory(struct qdio_irq *irq_ptr) -{ - int i; - struct qdio_q *q; - - for (i = 0; i < QDIO_MAX_QUEUES_PER_IRQ; i++) { - q = irq_ptr->input_qs[i]; - if (q) { - free_page((unsigned long) q->slib); - kmem_cache_free(qdio_q_cache, q); - } - q = irq_ptr->output_qs[i]; - if (q) { - free_page((unsigned long) q->slib); - kmem_cache_free(qdio_q_cache, q); - } - } - free_page((unsigned long) irq_ptr->qdr); - free_page((unsigned long) irq_ptr); -} - -static void -qdio_set_impl_params(struct qdio_irq *irq_ptr, - unsigned int qib_param_field_format, - /* pointer to 128 bytes or NULL, if no param field */ - unsigned char *qib_param_field, - /* pointer to no_queues*128 words of data or NULL */ - unsigned int no_input_qs, - unsigned int no_output_qs, - unsigned long *input_slib_elements, - unsigned long *output_slib_elements) -{ - int i,j; - - if (!irq_ptr) - return; - - irq_ptr->qib.pfmt=qib_param_field_format; - if (qib_param_field) - memcpy(irq_ptr->qib.parm,qib_param_field, - QDIO_MAX_BUFFERS_PER_Q); - - if (input_slib_elements) - for (i=0;iinput_qs[i]->slib->slibe[j].parms= - input_slib_elements[ - i*QDIO_MAX_BUFFERS_PER_Q+j]; - } - if (output_slib_elements) - for (i=0;ioutput_qs[i]->slib->slibe[j].parms= - output_slib_elements[ - i*QDIO_MAX_BUFFERS_PER_Q+j]; - } -} - -static int -qdio_alloc_qs(struct qdio_irq *irq_ptr, - int no_input_qs, int no_output_qs) -{ - int i; - struct qdio_q *q; - - for (i = 0; i < no_input_qs; i++) { - q = kmem_cache_alloc(qdio_q_cache, GFP_KERNEL); - if (!q) - return -ENOMEM; - memset(q, 0, sizeof(*q)); - - q->slib = (struct slib *) __get_free_page(GFP_KERNEL); - if (!q->slib) { - kmem_cache_free(qdio_q_cache, q); - return -ENOMEM; - } - irq_ptr->input_qs[i]=q; - } - - for (i = 0; i < no_output_qs; i++) { - q = kmem_cache_alloc(qdio_q_cache, GFP_KERNEL); - if (!q) - return -ENOMEM; - memset(q, 0, sizeof(*q)); - - q->slib = (struct slib *) __get_free_page(GFP_KERNEL); - if (!q->slib) { - kmem_cache_free(qdio_q_cache, q); - return -ENOMEM; - } - irq_ptr->output_qs[i]=q; - } - return 0; -} - -static void -qdio_fill_qs(struct qdio_irq *irq_ptr, struct ccw_device *cdev, - int no_input_qs, int no_output_qs, - qdio_handler_t *input_handler, - qdio_handler_t *output_handler, - unsigned long int_parm,int q_format, - unsigned long flags, - void **inbound_sbals_array, - void **outbound_sbals_array) -{ - struct qdio_q *q; - int i,j; - char dbf_text[20]; /* see qdio_initialize */ - void *ptr; - int available; - - sprintf(dbf_text,"qfqs%4x",cdev->private->schid.sch_no); - QDIO_DBF_TEXT0(0,setup,dbf_text); - for (i=0;iinput_qs[i]; - - memset(q,0,((char*)&q->slib)-((char*)q)); - sprintf(dbf_text,"in-q%4x",i); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_DBF_HEX0(0,setup,&q,sizeof(void*)); - - memset(q->slib,0,PAGE_SIZE); - q->sl=(struct sl*)(((char*)q->slib)+PAGE_SIZE/2); - - available=0; - - for (j=0;jsbal[j]=*(inbound_sbals_array++); - - q->queue_type=q_format; - q->int_parm=int_parm; - q->schid = irq_ptr->schid; - q->irq_ptr = irq_ptr; - q->cdev = cdev; - q->mask=1<<(31-i); - q->q_no=i; - q->is_input_q=1; - q->first_to_check=0; - q->last_move_ftc=0; - q->handler=input_handler; - q->dev_st_chg_ind=irq_ptr->dev_st_chg_ind; - - /* q->is_thinint_q isn't valid at this time, but - * irq_ptr->is_thinint_irq is - */ - if (irq_ptr->is_thinint_irq) - tasklet_init(&q->tasklet, tiqdio_inbound_processing, - (unsigned long) q); - else - tasklet_init(&q->tasklet, qdio_inbound_processing, - (unsigned long) q); - - /* actually this is not used for inbound queues. yet. */ - atomic_set(&q->busy_siga_counter,0); - q->timing.busy_start=0; - -/* for (j=0;jtiming.last_transfer_times[j]=(qdio_get_micros()/ - QDIO_STATS_NUMBER)*j; - q->timing.last_transfer_index=QDIO_STATS_NUMBER-1; -*/ - - /* fill in slib */ - if (i>0) irq_ptr->input_qs[i-1]->slib->nsliba= - (unsigned long)(q->slib); - q->slib->sla=(unsigned long)(q->sl); - q->slib->slsba=(unsigned long)(&q->slsb.acc.val[0]); - - /* fill in sl */ - for (j=0;jsl->element[j].sbal=(unsigned long)(q->sbal[j]); - - QDIO_DBF_TEXT2(0,setup,"sl-sb-b0"); - ptr=(void*)q->sl; - QDIO_DBF_HEX2(0,setup,&ptr,sizeof(void*)); - ptr=(void*)&q->slsb; - QDIO_DBF_HEX2(0,setup,&ptr,sizeof(void*)); - ptr=(void*)q->sbal[0]; - QDIO_DBF_HEX2(0,setup,&ptr,sizeof(void*)); - - /* fill in slsb */ - if (!irq_ptr->is_qebsm) { - unsigned int count = 1; - for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++) - set_slsb(q, &j, SLSB_P_INPUT_NOT_INIT, &count); - } - } - - for (i=0;ioutput_qs[i]; - memset(q,0,((char*)&q->slib)-((char*)q)); - - sprintf(dbf_text,"outq%4x",i); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_DBF_HEX0(0,setup,&q,sizeof(void*)); - - memset(q->slib,0,PAGE_SIZE); - q->sl=(struct sl*)(((char*)q->slib)+PAGE_SIZE/2); - - available=0; - - for (j=0;jsbal[j]=*(outbound_sbals_array++); - - q->queue_type=q_format; - if ((q->queue_type == QDIO_IQDIO_QFMT) && - (no_output_qs > 1) && - (i == no_output_qs-1)) - q->queue_type = QDIO_IQDIO_QFMT_ASYNCH; - q->int_parm=int_parm; - q->is_input_q=0; - q->is_pci_out = 0; - q->schid = irq_ptr->schid; - q->cdev = cdev; - q->irq_ptr = irq_ptr; - q->mask=1<<(31-i); - q->q_no=i; - q->first_to_check=0; - q->last_move_ftc=0; - q->handler=output_handler; - - tasklet_init(&q->tasklet, qdio_outbound_processing, - (unsigned long) q); - setup_timer(&q->timer, qdio_outbound_processing, - (unsigned long) q); - - atomic_set(&q->busy_siga_counter,0); - q->timing.busy_start=0; - - /* fill in slib */ - if (i>0) irq_ptr->output_qs[i-1]->slib->nsliba= - (unsigned long)(q->slib); - q->slib->sla=(unsigned long)(q->sl); - q->slib->slsba=(unsigned long)(&q->slsb.acc.val[0]); - - /* fill in sl */ - for (j=0;jsl->element[j].sbal=(unsigned long)(q->sbal[j]); - - QDIO_DBF_TEXT2(0,setup,"sl-sb-b0"); - ptr=(void*)q->sl; - QDIO_DBF_HEX2(0,setup,&ptr,sizeof(void*)); - ptr=(void*)&q->slsb; - QDIO_DBF_HEX2(0,setup,&ptr,sizeof(void*)); - ptr=(void*)q->sbal[0]; - QDIO_DBF_HEX2(0,setup,&ptr,sizeof(void*)); - - /* fill in slsb */ - if (!irq_ptr->is_qebsm) { - unsigned int count = 1; - for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++) - set_slsb(q, &j, SLSB_P_OUTPUT_NOT_INIT, &count); - } - } -} - -static void -qdio_fill_thresholds(struct qdio_irq *irq_ptr, - unsigned int no_input_qs, - unsigned int no_output_qs, - unsigned int min_input_threshold, - unsigned int max_input_threshold, - unsigned int min_output_threshold, - unsigned int max_output_threshold) -{ - int i; - struct qdio_q *q; - - for (i=0;iinput_qs[i]; - q->timing.threshold=max_input_threshold; -/* for (j=0;jthreshold_classes[j].threshold= - min_input_threshold+ - (max_input_threshold-min_input_threshold)/ - QDIO_STATS_CLASSES; - } - qdio_use_thresholds(q,QDIO_STATS_CLASSES/2);*/ - } - for (i=0;ioutput_qs[i]; - q->timing.threshold=max_output_threshold; -/* for (j=0;jthreshold_classes[j].threshold= - min_output_threshold+ - (max_output_threshold-min_output_threshold)/ - QDIO_STATS_CLASSES; - } - qdio_use_thresholds(q,QDIO_STATS_CLASSES/2);*/ - } -} - -static void tiqdio_thinint_handler(void *ind, void *drv_data) -{ - QDIO_DBF_TEXT4(0,trace,"thin_int"); - - qdio_perf_stat_inc(&perf_stats.thinints); - - /* SVS only when needed: - * issue SVS to benefit from iqdio interrupt avoidance - * (SVS clears AISOI)*/ - if (!omit_svs) - tiqdio_clear_global_summary(); - - tiqdio_inbound_checks(); -} - -static void -qdio_set_state(struct qdio_irq *irq_ptr, enum qdio_irq_states state) -{ - int i; -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[15]; - - QDIO_DBF_TEXT5(0,trace,"newstate"); - sprintf(dbf_text,"%4x%4x",irq_ptr->schid.sch_no,state); - QDIO_DBF_TEXT5(0,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - - irq_ptr->state=state; - for (i=0;ino_input_qs;i++) - irq_ptr->input_qs[i]->state=state; - for (i=0;ino_output_qs;i++) - irq_ptr->output_qs[i]->state=state; - mb(); -} - -static void -qdio_irq_check_sense(struct subchannel_id schid, struct irb *irb) -{ - char dbf_text[15]; - - if (irb->esw.esw0.erw.cons) { - sprintf(dbf_text,"sens%4x",schid.sch_no); - QDIO_DBF_TEXT2(1,trace,dbf_text); - QDIO_DBF_HEX0(0,sense,irb,QDIO_DBF_SENSE_LEN); - - QDIO_PRINT_WARN("sense data available on qdio channel.\n"); - QDIO_HEXDUMP16(WARN,"irb: ",irb); - QDIO_HEXDUMP16(WARN,"sense data: ",irb->ecw); - } - -} - -static void -qdio_handle_pci(struct qdio_irq *irq_ptr) -{ - int i; - struct qdio_q *q; - - qdio_perf_stat_inc(&perf_stats.pcis); - for (i=0;ino_input_qs;i++) { - q=irq_ptr->input_qs[i]; - if (q->is_input_q&QDIO_FLAG_NO_INPUT_INTERRUPT_CONTEXT) - qdio_mark_q(q); - else { - qdio_perf_stat_dec(&perf_stats.tl_runs); - __qdio_inbound_processing(q); - } - } - if (!irq_ptr->hydra_gives_outbound_pcis) - return; - for (i=0;ino_output_qs;i++) { - q=irq_ptr->output_qs[i]; - if (qdio_is_outbound_q_done(q)) - continue; - qdio_perf_stat_dec(&perf_stats.tl_runs); - if (!irq_ptr->sync_done_on_outb_pcis) - SYNC_MEMORY; - __qdio_outbound_processing(q); - } -} - -static void qdio_establish_handle_irq(struct ccw_device*, int, int); - -static void -qdio_handle_activate_check(struct ccw_device *cdev, unsigned long intparm, - int cstat, int dstat) -{ - struct qdio_irq *irq_ptr; - struct qdio_q *q; - char dbf_text[15]; - - irq_ptr = cdev->private->qdio_data; - - QDIO_DBF_TEXT2(1, trace, "ick2"); - sprintf(dbf_text,"%s", cdev->dev.bus_id); - QDIO_DBF_TEXT2(1,trace,dbf_text); - QDIO_DBF_HEX2(0,trace,&intparm,sizeof(int)); - QDIO_DBF_HEX2(0,trace,&dstat,sizeof(int)); - QDIO_DBF_HEX2(0,trace,&cstat,sizeof(int)); - QDIO_PRINT_ERR("received check condition on activate " \ - "queues on device %s (cs=x%x, ds=x%x).\n", - cdev->dev.bus_id, cstat, dstat); - if (irq_ptr->no_input_qs) { - q=irq_ptr->input_qs[0]; - } else if (irq_ptr->no_output_qs) { - q=irq_ptr->output_qs[0]; - } else { - QDIO_PRINT_ERR("oops... no queue registered for device %s!?\n", - cdev->dev.bus_id); - goto omit_handler_call; - } - q->handler(q->cdev,QDIO_STATUS_ACTIVATE_CHECK_CONDITION| - QDIO_STATUS_LOOK_FOR_ERROR, - 0,0,0,-1,-1,q->int_parm); -omit_handler_call: - qdio_set_state(irq_ptr,QDIO_IRQ_STATE_STOPPED); - -} - -static void -qdio_call_shutdown(struct work_struct *work) -{ - struct ccw_device_private *priv; - struct ccw_device *cdev; - - priv = container_of(work, struct ccw_device_private, kick_work); - cdev = priv->cdev; - qdio_shutdown(cdev, QDIO_FLAG_CLEANUP_USING_CLEAR); - put_device(&cdev->dev); -} - -static void -qdio_timeout_handler(struct ccw_device *cdev) -{ - struct qdio_irq *irq_ptr; - char dbf_text[15]; - - QDIO_DBF_TEXT2(0, trace, "qtoh"); - sprintf(dbf_text, "%s", cdev->dev.bus_id); - QDIO_DBF_TEXT2(0, trace, dbf_text); - - irq_ptr = cdev->private->qdio_data; - sprintf(dbf_text, "state:%d", irq_ptr->state); - QDIO_DBF_TEXT2(0, trace, dbf_text); - - switch (irq_ptr->state) { - case QDIO_IRQ_STATE_INACTIVE: - QDIO_PRINT_ERR("establish queues on irq 0.%x.%04x: timed out\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no); - QDIO_DBF_TEXT2(1,setup,"eq:timeo"); - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ERR); - break; - case QDIO_IRQ_STATE_CLEANUP: - QDIO_PRINT_INFO("Did not get interrupt on cleanup, " - "irq=0.%x.%x.\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no); - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ERR); - break; - case QDIO_IRQ_STATE_ESTABLISHED: - case QDIO_IRQ_STATE_ACTIVE: - /* I/O has been terminated by common I/O layer. */ - QDIO_PRINT_INFO("Queues on irq 0.%x.%04x killed by cio.\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no); - QDIO_DBF_TEXT2(1, trace, "cio:term"); - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_STOPPED); - if (get_device(&cdev->dev)) { - /* Can't call shutdown from interrupt context. */ - PREPARE_WORK(&cdev->private->kick_work, - qdio_call_shutdown); - queue_work(ccw_device_work, &cdev->private->kick_work); - } - break; - default: - BUG(); - } - wake_up(&cdev->private->wait_q); -} - -static void -qdio_handler(struct ccw_device *cdev, unsigned long intparm, struct irb *irb) -{ - struct qdio_irq *irq_ptr; - int cstat,dstat; - char dbf_text[15]; - -#ifdef CONFIG_QDIO_DEBUG - QDIO_DBF_TEXT4(0, trace, "qint"); - sprintf(dbf_text, "%s", cdev->dev.bus_id); - QDIO_DBF_TEXT4(0, trace, dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - - if (!intparm) { - QDIO_PRINT_ERR("got unsolicited interrupt in qdio " \ - "handler, device %s\n", cdev->dev.bus_id); - return; - } - - irq_ptr = cdev->private->qdio_data; - if (!irq_ptr) { - QDIO_DBF_TEXT2(1, trace, "uint"); - sprintf(dbf_text,"%s", cdev->dev.bus_id); - QDIO_DBF_TEXT2(1,trace,dbf_text); - QDIO_PRINT_ERR("received interrupt on unused device %s!\n", - cdev->dev.bus_id); - return; - } - - if (IS_ERR(irb)) { - /* Currently running i/o is in error. */ - switch (PTR_ERR(irb)) { - case -EIO: - QDIO_PRINT_ERR("i/o error on device %s\n", - cdev->dev.bus_id); - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ERR); - wake_up(&cdev->private->wait_q); - return; - case -ETIMEDOUT: - qdio_timeout_handler(cdev); - return; - default: - QDIO_PRINT_ERR("unknown error state %ld on device %s\n", - PTR_ERR(irb), cdev->dev.bus_id); - return; - } - } - - qdio_irq_check_sense(irq_ptr->schid, irb); - -#ifdef CONFIG_QDIO_DEBUG - sprintf(dbf_text, "state:%d", irq_ptr->state); - QDIO_DBF_TEXT4(0, trace, dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - - cstat = irb->scsw.cmd.cstat; - dstat = irb->scsw.cmd.dstat; - - switch (irq_ptr->state) { - case QDIO_IRQ_STATE_INACTIVE: - qdio_establish_handle_irq(cdev, cstat, dstat); - break; - - case QDIO_IRQ_STATE_CLEANUP: - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_INACTIVE); - break; - - case QDIO_IRQ_STATE_ESTABLISHED: - case QDIO_IRQ_STATE_ACTIVE: - if (cstat & SCHN_STAT_PCI) { - qdio_handle_pci(irq_ptr); - break; - } - - if ((cstat&~SCHN_STAT_PCI)||dstat) { - qdio_handle_activate_check(cdev, intparm, cstat, dstat); - break; - } - default: - QDIO_PRINT_ERR("got interrupt for queues in state %d on " \ - "device %s?!\n", - irq_ptr->state, cdev->dev.bus_id); - } - wake_up(&cdev->private->wait_q); - -} - -int -qdio_synchronize(struct ccw_device *cdev, unsigned int flags, - unsigned int queue_number) -{ - int cc = 0; - struct qdio_q *q; - struct qdio_irq *irq_ptr; - void *ptr; -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[15]="SyncXXXX"; -#endif - - irq_ptr = cdev->private->qdio_data; - if (!irq_ptr) - return -ENODEV; - -#ifdef CONFIG_QDIO_DEBUG - *((int*)(&dbf_text[4])) = irq_ptr->schid.sch_no; - QDIO_DBF_HEX4(0,trace,dbf_text,QDIO_DBF_TRACE_LEN); - *((int*)(&dbf_text[0]))=flags; - *((int*)(&dbf_text[4]))=queue_number; - QDIO_DBF_HEX4(0,trace,dbf_text,QDIO_DBF_TRACE_LEN); -#endif /* CONFIG_QDIO_DEBUG */ - - if (flags&QDIO_FLAG_SYNC_INPUT) { - q=irq_ptr->input_qs[queue_number]; - if (!q) - return -EINVAL; - if (!(irq_ptr->is_qebsm)) - cc = do_siga_sync(q->schid, 0, q->mask); - } else if (flags&QDIO_FLAG_SYNC_OUTPUT) { - q=irq_ptr->output_qs[queue_number]; - if (!q) - return -EINVAL; - if (!(irq_ptr->is_qebsm)) - cc = do_siga_sync(q->schid, q->mask, 0); - } else - return -EINVAL; - - ptr=&cc; - if (cc) - QDIO_DBF_HEX3(0,trace,&ptr,sizeof(int)); - - return cc; -} - -static int -qdio_get_ssqd_information(struct subchannel_id *schid, - struct qdio_chsc_ssqd **ssqd_area) -{ - int result; - - QDIO_DBF_TEXT0(0, setup, "getssqd"); - *ssqd_area = mempool_alloc(qdio_mempool_scssc, GFP_ATOMIC); - if (!ssqd_area) { - QDIO_PRINT_WARN("Could not get memory for chsc on sch x%x.\n", - schid->sch_no); - return -ENOMEM; - } - - (*ssqd_area)->request = (struct chsc_header) { - .length = 0x0010, - .code = 0x0024, - }; - (*ssqd_area)->first_sch = schid->sch_no; - (*ssqd_area)->last_sch = schid->sch_no; - (*ssqd_area)->ssid = schid->ssid; - result = chsc(*ssqd_area); - - if (result) { - QDIO_PRINT_WARN("CHSC returned cc %i on sch 0.%x.%x.\n", - result, schid->ssid, schid->sch_no); - goto out; - } - - if ((*ssqd_area)->response.code != QDIO_CHSC_RESPONSE_CODE_OK) { - QDIO_PRINT_WARN("CHSC response is 0x%x on sch 0.%x.%x.\n", - (*ssqd_area)->response.code, - schid->ssid, schid->sch_no); - goto out; - } - if (!((*ssqd_area)->flags & CHSC_FLAG_QDIO_CAPABILITY) || - !((*ssqd_area)->flags & CHSC_FLAG_VALIDITY) || - ((*ssqd_area)->sch != schid->sch_no)) { - QDIO_PRINT_WARN("huh? problems checking out sch 0.%x.%x... " \ - "using all SIGAs.\n", - schid->ssid, schid->sch_no); - goto out; - } - return 0; -out: - return -EINVAL; -} - -int -qdio_get_ssqd_pct(struct ccw_device *cdev) -{ - struct qdio_chsc_ssqd *ssqd_area; - struct subchannel_id schid; - char dbf_text[15]; - int rc; - int pct = 0; - - QDIO_DBF_TEXT0(0, setup, "getpct"); - schid = ccw_device_get_subchannel_id(cdev); - rc = qdio_get_ssqd_information(&schid, &ssqd_area); - if (!rc) - pct = (int)ssqd_area->pct; - if (rc != -ENOMEM) - mempool_free(ssqd_area, qdio_mempool_scssc); - sprintf(dbf_text, "pct: %d", pct); - QDIO_DBF_TEXT2(0, setup, dbf_text); - return pct; -} -EXPORT_SYMBOL(qdio_get_ssqd_pct); - -static void -qdio_check_subchannel_qebsm(struct qdio_irq *irq_ptr, unsigned long token) -{ - struct qdio_q *q; - int i; - unsigned int count, start_buf; - char dbf_text[15]; - - /*check if QEBSM is disabled */ - if (!(irq_ptr->is_qebsm) || !(irq_ptr->qdioac & 0x01)) { - irq_ptr->is_qebsm = 0; - irq_ptr->sch_token = 0; - irq_ptr->qib.rflags &= ~QIB_RFLAGS_ENABLE_QEBSM; - QDIO_DBF_TEXT0(0,setup,"noV=V"); - return; - } - irq_ptr->sch_token = token; - /*input queue*/ - for (i = 0; i < irq_ptr->no_input_qs;i++) { - q = irq_ptr->input_qs[i]; - count = QDIO_MAX_BUFFERS_PER_Q; - start_buf = 0; - set_slsb(q, &start_buf, SLSB_P_INPUT_NOT_INIT, &count); - } - sprintf(dbf_text,"V=V:%2x",irq_ptr->is_qebsm); - QDIO_DBF_TEXT0(0,setup,dbf_text); - sprintf(dbf_text,"%8lx",irq_ptr->sch_token); - QDIO_DBF_TEXT0(0,setup,dbf_text); - /*output queue*/ - for (i = 0; i < irq_ptr->no_output_qs; i++) { - q = irq_ptr->output_qs[i]; - count = QDIO_MAX_BUFFERS_PER_Q; - start_buf = 0; - set_slsb(q, &start_buf, SLSB_P_OUTPUT_NOT_INIT, &count); - } -} - -static void -qdio_get_ssqd_siga(struct qdio_irq *irq_ptr) -{ - int rc; - struct qdio_chsc_ssqd *ssqd_area; - - QDIO_DBF_TEXT0(0,setup,"getssqd"); - irq_ptr->qdioac = 0; - rc = qdio_get_ssqd_information(&irq_ptr->schid, &ssqd_area); - if (rc) { - QDIO_PRINT_WARN("using all SIGAs for sch x%x.n", - irq_ptr->schid.sch_no); - irq_ptr->qdioac = CHSC_FLAG_SIGA_INPUT_NECESSARY | - CHSC_FLAG_SIGA_OUTPUT_NECESSARY | - CHSC_FLAG_SIGA_SYNC_NECESSARY; /* all flags set */ - irq_ptr->is_qebsm = 0; - } else - irq_ptr->qdioac = ssqd_area->qdioac1; - - qdio_check_subchannel_qebsm(irq_ptr, ssqd_area->sch_token); - if (rc != -ENOMEM) - mempool_free(ssqd_area, qdio_mempool_scssc); -} - -static unsigned int -tiqdio_check_chsc_availability(void) -{ - char dbf_text[15]; - - /* Check for bit 41. */ - if (!css_general_characteristics.aif) { - QDIO_PRINT_WARN("Adapter interruption facility not " \ - "installed.\n"); - return -ENOENT; - } - - /* Check for bits 107 and 108. */ - if (!css_chsc_characteristics.scssc || - !css_chsc_characteristics.scsscf) { - QDIO_PRINT_WARN("Set Chan Subsys. Char. & Fast-CHSCs " \ - "not available.\n"); - return -ENOENT; - } - - /* Check for OSA/FCP thin interrupts (bit 67). */ - hydra_thinints = css_general_characteristics.aif_osa; - sprintf(dbf_text,"hydrati%1x", hydra_thinints); - QDIO_DBF_TEXT0(0,setup,dbf_text); - -#ifdef CONFIG_64BIT - /* Check for QEBSM support in general (bit 58). */ - is_passthrough = css_general_characteristics.qebsm; -#endif - sprintf(dbf_text,"cssQBS:%1x", is_passthrough); - QDIO_DBF_TEXT0(0,setup,dbf_text); - - /* Check for aif time delay disablement fac (bit 56). If installed, - * omit svs even under lpar (good point by rick again) */ - omit_svs = css_general_characteristics.aif_tdd; - sprintf(dbf_text,"omitsvs%1x", omit_svs); - QDIO_DBF_TEXT0(0,setup,dbf_text); - return 0; -} - - -static unsigned int -tiqdio_set_subchannel_ind(struct qdio_irq *irq_ptr, int reset_to_zero) -{ - unsigned long real_addr_local_summary_bit; - unsigned long real_addr_dev_st_chg_ind; - void *ptr; - char dbf_text[15]; - - unsigned int resp_code; - int result; - - struct { - struct chsc_header request; - u16 operation_code; - u16 reserved1; - u32 reserved2; - u32 reserved3; - u64 summary_indicator_addr; - u64 subchannel_indicator_addr; - u32 ks:4; - u32 kc:4; - u32 reserved4:21; - u32 isc:3; - u32 word_with_d_bit; - /* set to 0x10000000 to enable - * time delay disablement facility */ - u32 reserved5; - struct subchannel_id schid; - u32 reserved6[1004]; - struct chsc_header response; - u32 reserved7; - } *scssc_area; - - if (!irq_ptr->is_thinint_irq) - return -ENODEV; - - if (reset_to_zero) { - real_addr_local_summary_bit=0; - real_addr_dev_st_chg_ind=0; - } else { - real_addr_local_summary_bit= - virt_to_phys((volatile void *)tiqdio_ind); - real_addr_dev_st_chg_ind= - virt_to_phys((volatile void *)irq_ptr->dev_st_chg_ind); - } - - scssc_area = mempool_alloc(qdio_mempool_scssc, GFP_ATOMIC); - if (!scssc_area) { - QDIO_PRINT_WARN("No memory for setting indicators on " \ - "subchannel 0.%x.%x.\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no); - return -ENOMEM; - } - scssc_area->request = (struct chsc_header) { - .length = 0x0fe0, - .code = 0x0021, - }; - scssc_area->operation_code = 0; - - scssc_area->summary_indicator_addr = real_addr_local_summary_bit; - scssc_area->subchannel_indicator_addr = real_addr_dev_st_chg_ind; - scssc_area->ks = QDIO_STORAGE_KEY; - scssc_area->kc = QDIO_STORAGE_KEY; - scssc_area->isc = TIQDIO_THININT_ISC; - scssc_area->schid = irq_ptr->schid; - /* enables the time delay disablement facility. Don't care - * whether it is really there (i.e. we haven't checked for - * it) */ - if (css_general_characteristics.aif_tdd) - scssc_area->word_with_d_bit = 0x10000000; - else - QDIO_PRINT_WARN("Time delay disablement facility " \ - "not available\n"); - - result = chsc(scssc_area); - if (result) { - QDIO_PRINT_WARN("could not set indicators on irq 0.%x.%x, " \ - "cc=%i.\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no,result); - result = -EIO; - goto out; - } - - resp_code = scssc_area->response.code; - if (resp_code!=QDIO_CHSC_RESPONSE_CODE_OK) { - QDIO_PRINT_WARN("response upon setting indicators " \ - "is 0x%x.\n",resp_code); - sprintf(dbf_text,"sidR%4x",resp_code); - QDIO_DBF_TEXT1(0,trace,dbf_text); - QDIO_DBF_TEXT1(0,setup,dbf_text); - ptr=&scssc_area->response; - QDIO_DBF_HEX2(1,setup,&ptr,QDIO_DBF_SETUP_LEN); - result = -EIO; - goto out; - } - - QDIO_DBF_TEXT2(0,setup,"setscind"); - QDIO_DBF_HEX2(0,setup,&real_addr_local_summary_bit, - sizeof(unsigned long)); - QDIO_DBF_HEX2(0,setup,&real_addr_dev_st_chg_ind,sizeof(unsigned long)); - result = 0; -out: - mempool_free(scssc_area, qdio_mempool_scssc); - return result; - -} - -static unsigned int -tiqdio_set_delay_target(struct qdio_irq *irq_ptr, unsigned long delay_target) -{ - unsigned int resp_code; - int result; - void *ptr; - char dbf_text[15]; - - struct { - struct chsc_header request; - u16 operation_code; - u16 reserved1; - u32 reserved2; - u32 reserved3; - u32 reserved4[2]; - u32 delay_target; - u32 reserved5[1009]; - struct chsc_header response; - u32 reserved6; - } *scsscf_area; - - if (!irq_ptr->is_thinint_irq) - return -ENODEV; - - scsscf_area = mempool_alloc(qdio_mempool_scssc, GFP_ATOMIC); - if (!scsscf_area) { - QDIO_PRINT_WARN("No memory for setting delay target on " \ - "subchannel 0.%x.%x.\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no); - return -ENOMEM; - } - scsscf_area->request = (struct chsc_header) { - .length = 0x0fe0, - .code = 0x1027, - }; - - scsscf_area->delay_target = delay_target<<16; - - result=chsc(scsscf_area); - if (result) { - QDIO_PRINT_WARN("could not set delay target on irq 0.%x.%x, " \ - "cc=%i. Continuing.\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no, - result); - result = -EIO; - goto out; - } - - resp_code = scsscf_area->response.code; - if (resp_code!=QDIO_CHSC_RESPONSE_CODE_OK) { - QDIO_PRINT_WARN("response upon setting delay target " \ - "is 0x%x. Continuing.\n",resp_code); - sprintf(dbf_text,"sdtR%4x",resp_code); - QDIO_DBF_TEXT1(0,trace,dbf_text); - QDIO_DBF_TEXT1(0,setup,dbf_text); - ptr=&scsscf_area->response; - QDIO_DBF_HEX2(1,trace,&ptr,QDIO_DBF_TRACE_LEN); - } - QDIO_DBF_TEXT2(0,trace,"delytrgt"); - QDIO_DBF_HEX2(0,trace,&delay_target,sizeof(unsigned long)); - result = 0; /* not critical */ -out: - mempool_free(scsscf_area, qdio_mempool_scssc); - return result; -} - -int -qdio_cleanup(struct ccw_device *cdev, int how) -{ - struct qdio_irq *irq_ptr; - char dbf_text[15]; - int rc; - - irq_ptr = cdev->private->qdio_data; - if (!irq_ptr) - return -ENODEV; - - sprintf(dbf_text,"qcln%4x",irq_ptr->schid.sch_no); - QDIO_DBF_TEXT1(0,trace,dbf_text); - QDIO_DBF_TEXT0(0,setup,dbf_text); - - rc = qdio_shutdown(cdev, how); - if ((rc == 0) || (rc == -EINPROGRESS)) - rc = qdio_free(cdev); - return rc; -} - -int -qdio_shutdown(struct ccw_device *cdev, int how) -{ - struct qdio_irq *irq_ptr; - int i; - int result = 0; - int rc; - unsigned long flags; - int timeout; - char dbf_text[15]; - - irq_ptr = cdev->private->qdio_data; - if (!irq_ptr) - return -ENODEV; - - down(&irq_ptr->setting_up_sema); - - sprintf(dbf_text,"qsqs%4x",irq_ptr->schid.sch_no); - QDIO_DBF_TEXT1(0,trace,dbf_text); - QDIO_DBF_TEXT0(0,setup,dbf_text); - - /* mark all qs as uninteresting */ - for (i=0;ino_input_qs;i++) - atomic_set(&irq_ptr->input_qs[i]->is_in_shutdown,1); - - for (i=0;ino_output_qs;i++) - atomic_set(&irq_ptr->output_qs[i]->is_in_shutdown,1); - - tasklet_kill(&tiqdio_tasklet); - - for (i=0;ino_input_qs;i++) { - qdio_unmark_q(irq_ptr->input_qs[i]); - tasklet_kill(&irq_ptr->input_qs[i]->tasklet); - wait_event_interruptible_timeout(cdev->private->wait_q, - !atomic_read(&irq_ptr-> - input_qs[i]-> - use_count), - QDIO_NO_USE_COUNT_TIMEOUT); - if (atomic_read(&irq_ptr->input_qs[i]->use_count)) - result=-EINPROGRESS; - } - - for (i=0;ino_output_qs;i++) { - tasklet_kill(&irq_ptr->output_qs[i]->tasklet); - del_timer(&irq_ptr->output_qs[i]->timer); - wait_event_interruptible_timeout(cdev->private->wait_q, - !atomic_read(&irq_ptr-> - output_qs[i]-> - use_count), - QDIO_NO_USE_COUNT_TIMEOUT); - if (atomic_read(&irq_ptr->output_qs[i]->use_count)) - result=-EINPROGRESS; - } - - /* cleanup subchannel */ - spin_lock_irqsave(get_ccwdev_lock(cdev),flags); - if (how&QDIO_FLAG_CLEANUP_USING_CLEAR) { - rc = ccw_device_clear(cdev, QDIO_DOING_CLEANUP); - timeout=QDIO_CLEANUP_CLEAR_TIMEOUT; - } else if (how&QDIO_FLAG_CLEANUP_USING_HALT) { - rc = ccw_device_halt(cdev, QDIO_DOING_CLEANUP); - timeout=QDIO_CLEANUP_HALT_TIMEOUT; - } else { /* default behaviour */ - rc = ccw_device_halt(cdev, QDIO_DOING_CLEANUP); - timeout=QDIO_CLEANUP_HALT_TIMEOUT; - } - if (rc == -ENODEV) { - /* No need to wait for device no longer present. */ - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_INACTIVE); - spin_unlock_irqrestore(get_ccwdev_lock(cdev), flags); - } else if (((void *)cdev->handler != (void *)qdio_handler) && rc == 0) { - /* - * Whoever put another handler there, has to cope with the - * interrupt theirself. Might happen if qdio_shutdown was - * called on already shutdown queues, but this shouldn't have - * bad side effects. - */ - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_INACTIVE); - spin_unlock_irqrestore(get_ccwdev_lock(cdev), flags); - } else if (rc == 0) { - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_CLEANUP); - spin_unlock_irqrestore(get_ccwdev_lock(cdev),flags); - - wait_event_interruptible_timeout(cdev->private->wait_q, - irq_ptr->state == QDIO_IRQ_STATE_INACTIVE || - irq_ptr->state == QDIO_IRQ_STATE_ERR, - timeout); - } else { - QDIO_PRINT_INFO("ccw_device_{halt,clear} returned %d for " - "device %s\n", result, cdev->dev.bus_id); - spin_unlock_irqrestore(get_ccwdev_lock(cdev), flags); - result = rc; - goto out; - } - if (irq_ptr->is_thinint_irq) { - qdio_put_indicator((__u32*)irq_ptr->dev_st_chg_ind); - tiqdio_set_subchannel_ind(irq_ptr,1); - /* reset adapter interrupt indicators */ - } - - /* exchange int handlers, if necessary */ - if ((void*)cdev->handler == (void*)qdio_handler) - cdev->handler=irq_ptr->original_int_handler; - - /* Ignore errors. */ - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_INACTIVE); -out: - up(&irq_ptr->setting_up_sema); - return result; -} - -int -qdio_free(struct ccw_device *cdev) -{ - struct qdio_irq *irq_ptr; - char dbf_text[15]; - - irq_ptr = cdev->private->qdio_data; - if (!irq_ptr) - return -ENODEV; - - down(&irq_ptr->setting_up_sema); - - sprintf(dbf_text,"qfqs%4x",irq_ptr->schid.sch_no); - QDIO_DBF_TEXT1(0,trace,dbf_text); - QDIO_DBF_TEXT0(0,setup,dbf_text); - - cdev->private->qdio_data = NULL; - - up(&irq_ptr->setting_up_sema); - - qdio_release_irq_memory(irq_ptr); - module_put(THIS_MODULE); - return 0; -} - -static void -qdio_allocate_do_dbf(struct qdio_initialize *init_data) -{ - char dbf_text[20]; /* if a printf printed out more than 8 chars */ - - sprintf(dbf_text,"qfmt:%x",init_data->q_format); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_DBF_HEX0(0,setup,init_data->adapter_name,8); - sprintf(dbf_text,"qpff%4x",init_data->qib_param_field_format); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_DBF_HEX0(0,setup,&init_data->qib_param_field,sizeof(char*)); - QDIO_DBF_HEX0(0,setup,&init_data->input_slib_elements,sizeof(long*)); - QDIO_DBF_HEX0(0,setup,&init_data->output_slib_elements,sizeof(long*)); - sprintf(dbf_text,"miit%4x",init_data->min_input_threshold); - QDIO_DBF_TEXT0(0,setup,dbf_text); - sprintf(dbf_text,"mait%4x",init_data->max_input_threshold); - QDIO_DBF_TEXT0(0,setup,dbf_text); - sprintf(dbf_text,"miot%4x",init_data->min_output_threshold); - QDIO_DBF_TEXT0(0,setup,dbf_text); - sprintf(dbf_text,"maot%4x",init_data->max_output_threshold); - QDIO_DBF_TEXT0(0,setup,dbf_text); - sprintf(dbf_text,"niq:%4x",init_data->no_input_qs); - QDIO_DBF_TEXT0(0,setup,dbf_text); - sprintf(dbf_text,"noq:%4x",init_data->no_output_qs); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_DBF_HEX0(0,setup,&init_data->input_handler,sizeof(void*)); - QDIO_DBF_HEX0(0,setup,&init_data->output_handler,sizeof(void*)); - QDIO_DBF_HEX0(0,setup,&init_data->int_parm,sizeof(long)); - QDIO_DBF_HEX0(0,setup,&init_data->flags,sizeof(long)); - QDIO_DBF_HEX0(0,setup,&init_data->input_sbal_addr_array,sizeof(void*)); - QDIO_DBF_HEX0(0,setup,&init_data->output_sbal_addr_array,sizeof(void*)); -} - -static void -qdio_allocate_fill_input_desc(struct qdio_irq *irq_ptr, int i, int iqfmt) -{ - irq_ptr->input_qs[i]->is_iqdio_q = iqfmt; - irq_ptr->input_qs[i]->is_thinint_q = irq_ptr->is_thinint_irq; - - irq_ptr->qdr->qdf0[i].sliba=(unsigned long)(irq_ptr->input_qs[i]->slib); - - irq_ptr->qdr->qdf0[i].sla=(unsigned long)(irq_ptr->input_qs[i]->sl); - - irq_ptr->qdr->qdf0[i].slsba= - (unsigned long)(&irq_ptr->input_qs[i]->slsb.acc.val[0]); - - irq_ptr->qdr->qdf0[i].akey=QDIO_STORAGE_KEY; - irq_ptr->qdr->qdf0[i].bkey=QDIO_STORAGE_KEY; - irq_ptr->qdr->qdf0[i].ckey=QDIO_STORAGE_KEY; - irq_ptr->qdr->qdf0[i].dkey=QDIO_STORAGE_KEY; -} - -static void -qdio_allocate_fill_output_desc(struct qdio_irq *irq_ptr, int i, - int j, int iqfmt) -{ - irq_ptr->output_qs[i]->is_iqdio_q = iqfmt; - irq_ptr->output_qs[i]->is_thinint_q = irq_ptr->is_thinint_irq; - - irq_ptr->qdr->qdf0[i+j].sliba=(unsigned long)(irq_ptr->output_qs[i]->slib); - - irq_ptr->qdr->qdf0[i+j].sla=(unsigned long)(irq_ptr->output_qs[i]->sl); - - irq_ptr->qdr->qdf0[i+j].slsba= - (unsigned long)(&irq_ptr->output_qs[i]->slsb.acc.val[0]); - - irq_ptr->qdr->qdf0[i+j].akey=QDIO_STORAGE_KEY; - irq_ptr->qdr->qdf0[i+j].bkey=QDIO_STORAGE_KEY; - irq_ptr->qdr->qdf0[i+j].ckey=QDIO_STORAGE_KEY; - irq_ptr->qdr->qdf0[i+j].dkey=QDIO_STORAGE_KEY; -} - - -static void -qdio_initialize_set_siga_flags_input(struct qdio_irq *irq_ptr) -{ - int i; - - for (i=0;ino_input_qs;i++) { - irq_ptr->input_qs[i]->siga_sync= - irq_ptr->qdioac&CHSC_FLAG_SIGA_SYNC_NECESSARY; - irq_ptr->input_qs[i]->siga_in= - irq_ptr->qdioac&CHSC_FLAG_SIGA_INPUT_NECESSARY; - irq_ptr->input_qs[i]->siga_out= - irq_ptr->qdioac&CHSC_FLAG_SIGA_OUTPUT_NECESSARY; - irq_ptr->input_qs[i]->siga_sync_done_on_thinints= - irq_ptr->qdioac&CHSC_FLAG_SIGA_SYNC_DONE_ON_THININTS; - irq_ptr->input_qs[i]->hydra_gives_outbound_pcis= - irq_ptr->hydra_gives_outbound_pcis; - irq_ptr->input_qs[i]->siga_sync_done_on_outb_tis= - ((irq_ptr->qdioac& - (CHSC_FLAG_SIGA_SYNC_DONE_ON_OUTB_PCIS| - CHSC_FLAG_SIGA_SYNC_DONE_ON_THININTS))== - (CHSC_FLAG_SIGA_SYNC_DONE_ON_OUTB_PCIS| - CHSC_FLAG_SIGA_SYNC_DONE_ON_THININTS)); - - } -} - -static void -qdio_initialize_set_siga_flags_output(struct qdio_irq *irq_ptr) -{ - int i; - - for (i=0;ino_output_qs;i++) { - irq_ptr->output_qs[i]->siga_sync= - irq_ptr->qdioac&CHSC_FLAG_SIGA_SYNC_NECESSARY; - irq_ptr->output_qs[i]->siga_in= - irq_ptr->qdioac&CHSC_FLAG_SIGA_INPUT_NECESSARY; - irq_ptr->output_qs[i]->siga_out= - irq_ptr->qdioac&CHSC_FLAG_SIGA_OUTPUT_NECESSARY; - irq_ptr->output_qs[i]->siga_sync_done_on_thinints= - irq_ptr->qdioac&CHSC_FLAG_SIGA_SYNC_DONE_ON_THININTS; - irq_ptr->output_qs[i]->hydra_gives_outbound_pcis= - irq_ptr->hydra_gives_outbound_pcis; - irq_ptr->output_qs[i]->siga_sync_done_on_outb_tis= - ((irq_ptr->qdioac& - (CHSC_FLAG_SIGA_SYNC_DONE_ON_OUTB_PCIS| - CHSC_FLAG_SIGA_SYNC_DONE_ON_THININTS))== - (CHSC_FLAG_SIGA_SYNC_DONE_ON_OUTB_PCIS| - CHSC_FLAG_SIGA_SYNC_DONE_ON_THININTS)); - - } -} - -static int -qdio_establish_irq_check_for_errors(struct ccw_device *cdev, int cstat, - int dstat) -{ - char dbf_text[15]; - struct qdio_irq *irq_ptr; - - irq_ptr = cdev->private->qdio_data; - - if (cstat || (dstat & ~(DEV_STAT_CHN_END|DEV_STAT_DEV_END))) { - sprintf(dbf_text,"ick1%4x",irq_ptr->schid.sch_no); - QDIO_DBF_TEXT2(1,trace,dbf_text); - QDIO_DBF_HEX2(0,trace,&dstat,sizeof(int)); - QDIO_DBF_HEX2(0,trace,&cstat,sizeof(int)); - QDIO_PRINT_ERR("received check condition on establish " \ - "queues on irq 0.%x.%x (cs=x%x, ds=x%x).\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no, - cstat,dstat); - qdio_set_state(irq_ptr,QDIO_IRQ_STATE_ERR); - } - - if (!(dstat & DEV_STAT_DEV_END)) { - QDIO_DBF_TEXT2(1,setup,"eq:no de"); - QDIO_DBF_HEX2(0,setup,&dstat, sizeof(dstat)); - QDIO_DBF_HEX2(0,setup,&cstat, sizeof(cstat)); - QDIO_PRINT_ERR("establish queues on irq 0.%x.%04x: didn't get " - "device end: dstat=%02x, cstat=%02x\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no, - dstat, cstat); - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ERR); - return 1; - } - - if (dstat & ~(DEV_STAT_CHN_END|DEV_STAT_DEV_END)) { - QDIO_DBF_TEXT2(1,setup,"eq:badio"); - QDIO_DBF_HEX2(0,setup,&dstat, sizeof(dstat)); - QDIO_DBF_HEX2(0,setup,&cstat, sizeof(cstat)); - QDIO_PRINT_ERR("establish queues on irq 0.%x.%04x: got " - "the following devstat: dstat=%02x, " - "cstat=%02x\n", irq_ptr->schid.ssid, - irq_ptr->schid.sch_no, dstat, cstat); - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ERR); - return 1; - } - return 0; -} - -static void -qdio_establish_handle_irq(struct ccw_device *cdev, int cstat, int dstat) -{ - struct qdio_irq *irq_ptr; - char dbf_text[15]; - - irq_ptr = cdev->private->qdio_data; - - sprintf(dbf_text,"qehi%4x",cdev->private->schid.sch_no); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_DBF_TEXT0(0,trace,dbf_text); - - if (qdio_establish_irq_check_for_errors(cdev, cstat, dstat)) - return; - - qdio_set_state(irq_ptr,QDIO_IRQ_STATE_ESTABLISHED); -} - -int -qdio_initialize(struct qdio_initialize *init_data) -{ - int rc; - char dbf_text[15]; - - sprintf(dbf_text,"qini%4x",init_data->cdev->private->schid.sch_no); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_DBF_TEXT0(0,trace,dbf_text); - - rc = qdio_allocate(init_data); - if (rc == 0) { - rc = qdio_establish(init_data); - if (rc != 0) - qdio_free(init_data->cdev); - } - - return rc; -} - - -int -qdio_allocate(struct qdio_initialize *init_data) -{ - struct qdio_irq *irq_ptr; - char dbf_text[15]; - - sprintf(dbf_text,"qalc%4x",init_data->cdev->private->schid.sch_no); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_DBF_TEXT0(0,trace,dbf_text); - if ( (init_data->no_input_qs>QDIO_MAX_QUEUES_PER_IRQ) || - (init_data->no_output_qs>QDIO_MAX_QUEUES_PER_IRQ) || - ((init_data->no_input_qs) && (!init_data->input_handler)) || - ((init_data->no_output_qs) && (!init_data->output_handler)) ) - return -EINVAL; - - if (!init_data->input_sbal_addr_array) - return -EINVAL; - - if (!init_data->output_sbal_addr_array) - return -EINVAL; - - qdio_allocate_do_dbf(init_data); - - /* create irq */ - irq_ptr = (void *) get_zeroed_page(GFP_KERNEL | GFP_DMA); - - QDIO_DBF_TEXT0(0,setup,"irq_ptr:"); - QDIO_DBF_HEX0(0,setup,&irq_ptr,sizeof(void*)); - - if (!irq_ptr) { - QDIO_PRINT_ERR("allocation of irq_ptr failed!\n"); - return -ENOMEM; - } - - init_MUTEX(&irq_ptr->setting_up_sema); - - /* QDR must be in DMA area since CCW data address is only 32 bit */ - irq_ptr->qdr = (struct qdr *) __get_free_page(GFP_KERNEL | GFP_DMA); - if (!(irq_ptr->qdr)) { - free_page((unsigned long) irq_ptr); - QDIO_PRINT_ERR("allocation of irq_ptr->qdr failed!\n"); - return -ENOMEM; - } - QDIO_DBF_TEXT0(0,setup,"qdr:"); - QDIO_DBF_HEX0(0,setup,&irq_ptr->qdr,sizeof(void*)); - - if (qdio_alloc_qs(irq_ptr, - init_data->no_input_qs, - init_data->no_output_qs)) { - QDIO_PRINT_ERR("queue allocation failed!\n"); - qdio_release_irq_memory(irq_ptr); - return -ENOMEM; - } - - init_data->cdev->private->qdio_data = irq_ptr; - - qdio_set_state(irq_ptr,QDIO_IRQ_STATE_INACTIVE); - - return 0; -} - -static int qdio_fill_irq(struct qdio_initialize *init_data) -{ - int i; - char dbf_text[15]; - struct ciw *ciw; - int is_iqdio; - struct qdio_irq *irq_ptr; - - irq_ptr = init_data->cdev->private->qdio_data; - - memset(irq_ptr,0,((char*)&irq_ptr->qdr)-((char*)irq_ptr)); - - /* wipes qib.ac, required by ar7063 */ - memset(irq_ptr->qdr,0,sizeof(struct qdr)); - - irq_ptr->int_parm=init_data->int_parm; - - irq_ptr->schid = ccw_device_get_subchannel_id(init_data->cdev); - irq_ptr->no_input_qs=init_data->no_input_qs; - irq_ptr->no_output_qs=init_data->no_output_qs; - - if (init_data->q_format==QDIO_IQDIO_QFMT) { - irq_ptr->is_iqdio_irq=1; - irq_ptr->is_thinint_irq=1; - } else { - irq_ptr->is_iqdio_irq=0; - irq_ptr->is_thinint_irq=hydra_thinints; - } - sprintf(dbf_text,"is_i_t%1x%1x", - irq_ptr->is_iqdio_irq,irq_ptr->is_thinint_irq); - QDIO_DBF_TEXT2(0,setup,dbf_text); - - if (irq_ptr->is_thinint_irq) { - irq_ptr->dev_st_chg_ind = qdio_get_indicator(); - QDIO_DBF_HEX1(0,setup,&irq_ptr->dev_st_chg_ind,sizeof(void*)); - if (!irq_ptr->dev_st_chg_ind) { - QDIO_PRINT_WARN("no indicator location available " \ - "for irq 0.%x.%x\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no); - qdio_release_irq_memory(irq_ptr); - return -ENOBUFS; - } - } - - /* defaults */ - irq_ptr->equeue.cmd=DEFAULT_ESTABLISH_QS_CMD; - irq_ptr->equeue.count=DEFAULT_ESTABLISH_QS_COUNT; - irq_ptr->aqueue.cmd=DEFAULT_ACTIVATE_QS_CMD; - irq_ptr->aqueue.count=DEFAULT_ACTIVATE_QS_COUNT; - - qdio_fill_qs(irq_ptr, init_data->cdev, - init_data->no_input_qs, - init_data->no_output_qs, - init_data->input_handler, - init_data->output_handler,init_data->int_parm, - init_data->q_format,init_data->flags, - init_data->input_sbal_addr_array, - init_data->output_sbal_addr_array); - - if (!try_module_get(THIS_MODULE)) { - QDIO_PRINT_CRIT("try_module_get() failed!\n"); - qdio_release_irq_memory(irq_ptr); - return -EINVAL; - } - - qdio_fill_thresholds(irq_ptr,init_data->no_input_qs, - init_data->no_output_qs, - init_data->min_input_threshold, - init_data->max_input_threshold, - init_data->min_output_threshold, - init_data->max_output_threshold); - - /* fill in qdr */ - irq_ptr->qdr->qfmt=init_data->q_format; - irq_ptr->qdr->iqdcnt=init_data->no_input_qs; - irq_ptr->qdr->oqdcnt=init_data->no_output_qs; - irq_ptr->qdr->iqdsz=sizeof(struct qdesfmt0)/4; /* size in words */ - irq_ptr->qdr->oqdsz=sizeof(struct qdesfmt0)/4; - - irq_ptr->qdr->qiba=(unsigned long)&irq_ptr->qib; - irq_ptr->qdr->qkey=QDIO_STORAGE_KEY; - - /* fill in qib */ - irq_ptr->is_qebsm = is_passthrough; - if (irq_ptr->is_qebsm) - irq_ptr->qib.rflags |= QIB_RFLAGS_ENABLE_QEBSM; - - irq_ptr->qib.qfmt=init_data->q_format; - if (init_data->no_input_qs) - irq_ptr->qib.isliba=(unsigned long)(irq_ptr->input_qs[0]->slib); - if (init_data->no_output_qs) - irq_ptr->qib.osliba=(unsigned long)(irq_ptr->output_qs[0]->slib); - memcpy(irq_ptr->qib.ebcnam,init_data->adapter_name,8); - - qdio_set_impl_params(irq_ptr,init_data->qib_param_field_format, - init_data->qib_param_field, - init_data->no_input_qs, - init_data->no_output_qs, - init_data->input_slib_elements, - init_data->output_slib_elements); - - /* first input descriptors, then output descriptors */ - is_iqdio = (init_data->q_format == QDIO_IQDIO_QFMT) ? 1 : 0; - for (i=0;ino_input_qs;i++) - qdio_allocate_fill_input_desc(irq_ptr, i, is_iqdio); - - for (i=0;ino_output_qs;i++) - qdio_allocate_fill_output_desc(irq_ptr, i, - init_data->no_input_qs, - is_iqdio); - - /* qdr, qib, sls, slsbs, slibs, sbales filled. */ - - /* get qdio commands */ - ciw = ccw_device_get_ciw(init_data->cdev, CIW_TYPE_EQUEUE); - if (!ciw) { - QDIO_DBF_TEXT2(1,setup,"no eq"); - QDIO_PRINT_INFO("No equeue CIW found for QDIO commands. " - "Trying to use default.\n"); - } else - irq_ptr->equeue = *ciw; - ciw = ccw_device_get_ciw(init_data->cdev, CIW_TYPE_AQUEUE); - if (!ciw) { - QDIO_DBF_TEXT2(1,setup,"no aq"); - QDIO_PRINT_INFO("No aqueue CIW found for QDIO commands. " - "Trying to use default.\n"); - } else - irq_ptr->aqueue = *ciw; - - /* Set new interrupt handler. */ - irq_ptr->original_int_handler = init_data->cdev->handler; - init_data->cdev->handler = qdio_handler; - - return 0; -} - -int -qdio_establish(struct qdio_initialize *init_data) -{ - struct qdio_irq *irq_ptr; - unsigned long saveflags; - int result, result2; - struct ccw_device *cdev; - char dbf_text[20]; - - cdev=init_data->cdev; - irq_ptr = cdev->private->qdio_data; - if (!irq_ptr) - return -EINVAL; - - if (cdev->private->state != DEV_STATE_ONLINE) - return -EINVAL; - - down(&irq_ptr->setting_up_sema); - - qdio_fill_irq(init_data); - - /* the thinint CHSC stuff */ - if (irq_ptr->is_thinint_irq) { - - result = tiqdio_set_subchannel_ind(irq_ptr,0); - if (result) { - up(&irq_ptr->setting_up_sema); - qdio_shutdown(cdev, QDIO_FLAG_CLEANUP_USING_CLEAR); - return result; - } - tiqdio_set_delay_target(irq_ptr,TIQDIO_DELAY_TARGET); - } - - sprintf(dbf_text,"qest%4x",cdev->private->schid.sch_no); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_DBF_TEXT0(0,trace,dbf_text); - - /* establish q */ - irq_ptr->ccw.cmd_code=irq_ptr->equeue.cmd; - irq_ptr->ccw.flags=CCW_FLAG_SLI; - irq_ptr->ccw.count=irq_ptr->equeue.count; - irq_ptr->ccw.cda=QDIO_GET_ADDR(irq_ptr->qdr); - - spin_lock_irqsave(get_ccwdev_lock(cdev),saveflags); - - ccw_device_set_options_mask(cdev, 0); - result = ccw_device_start(cdev, &irq_ptr->ccw, - QDIO_DOING_ESTABLISH, 0, 0); - if (result) { - result2 = ccw_device_start(cdev, &irq_ptr->ccw, - QDIO_DOING_ESTABLISH, 0, 0); - sprintf(dbf_text,"eq:io%4x",result); - QDIO_DBF_TEXT2(1,setup,dbf_text); - if (result2) { - sprintf(dbf_text,"eq:io%4x",result); - QDIO_DBF_TEXT2(1,setup,dbf_text); - } - QDIO_PRINT_WARN("establish queues on irq 0.%x.%04x: do_IO " \ - "returned %i, next try returned %i\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no, - result, result2); - result=result2; - } - - spin_unlock_irqrestore(get_ccwdev_lock(cdev),saveflags); - - if (result) { - up(&irq_ptr->setting_up_sema); - qdio_shutdown(cdev,QDIO_FLAG_CLEANUP_USING_CLEAR); - return result; - } - - wait_event_interruptible_timeout(cdev->private->wait_q, - irq_ptr->state == QDIO_IRQ_STATE_ESTABLISHED || - irq_ptr->state == QDIO_IRQ_STATE_ERR, - QDIO_ESTABLISH_TIMEOUT); - - if (irq_ptr->state == QDIO_IRQ_STATE_ESTABLISHED) - result = 0; - else { - up(&irq_ptr->setting_up_sema); - qdio_shutdown(cdev, QDIO_FLAG_CLEANUP_USING_CLEAR); - return -EIO; - } - - qdio_get_ssqd_siga(irq_ptr); - /* if this gets set once, we're running under VM and can omit SVSes */ - if (irq_ptr->qdioac&CHSC_FLAG_SIGA_SYNC_NECESSARY) - omit_svs=1; - - sprintf(dbf_text,"qdioac%2x",irq_ptr->qdioac); - QDIO_DBF_TEXT2(0,setup,dbf_text); - - sprintf(dbf_text,"qib ac%2x",irq_ptr->qib.ac); - QDIO_DBF_TEXT2(0,setup,dbf_text); - - irq_ptr->hydra_gives_outbound_pcis= - irq_ptr->qib.ac&QIB_AC_OUTBOUND_PCI_SUPPORTED; - irq_ptr->sync_done_on_outb_pcis= - irq_ptr->qdioac&CHSC_FLAG_SIGA_SYNC_DONE_ON_OUTB_PCIS; - - qdio_initialize_set_siga_flags_input(irq_ptr); - qdio_initialize_set_siga_flags_output(irq_ptr); - - up(&irq_ptr->setting_up_sema); - - return result; - -} - -int -qdio_activate(struct ccw_device *cdev, int flags) -{ - struct qdio_irq *irq_ptr; - int i,result=0,result2; - unsigned long saveflags; - char dbf_text[20]; /* see qdio_initialize */ - - irq_ptr = cdev->private->qdio_data; - if (!irq_ptr) - return -ENODEV; - - if (cdev->private->state != DEV_STATE_ONLINE) - return -EINVAL; - - down(&irq_ptr->setting_up_sema); - if (irq_ptr->state==QDIO_IRQ_STATE_INACTIVE) { - result=-EBUSY; - goto out; - } - - sprintf(dbf_text,"qact%4x", irq_ptr->schid.sch_no); - QDIO_DBF_TEXT2(0,setup,dbf_text); - QDIO_DBF_TEXT2(0,trace,dbf_text); - - /* activate q */ - irq_ptr->ccw.cmd_code=irq_ptr->aqueue.cmd; - irq_ptr->ccw.flags=CCW_FLAG_SLI; - irq_ptr->ccw.count=irq_ptr->aqueue.count; - irq_ptr->ccw.cda=QDIO_GET_ADDR(0); - - spin_lock_irqsave(get_ccwdev_lock(cdev),saveflags); - - ccw_device_set_options(cdev, CCWDEV_REPORT_ALL); - result=ccw_device_start(cdev,&irq_ptr->ccw,QDIO_DOING_ACTIVATE, - 0, DOIO_DENY_PREFETCH); - if (result) { - result2=ccw_device_start(cdev,&irq_ptr->ccw, - QDIO_DOING_ACTIVATE,0,0); - sprintf(dbf_text,"aq:io%4x",result); - QDIO_DBF_TEXT2(1,setup,dbf_text); - if (result2) { - sprintf(dbf_text,"aq:io%4x",result); - QDIO_DBF_TEXT2(1,setup,dbf_text); - } - QDIO_PRINT_WARN("activate queues on irq 0.%x.%04x: do_IO " \ - "returned %i, next try returned %i\n", - irq_ptr->schid.ssid, irq_ptr->schid.sch_no, - result, result2); - result=result2; - } - - spin_unlock_irqrestore(get_ccwdev_lock(cdev),saveflags); - if (result) - goto out; - - for (i=0;ino_input_qs;i++) { - if (irq_ptr->is_thinint_irq) { - /* - * that way we know, that, if we will get interrupted - * by tiqdio_inbound_processing, qdio_unmark_q will - * not be called - */ - qdio_reserve_q(irq_ptr->input_qs[i]); - qdio_mark_tiq(irq_ptr->input_qs[i]); - qdio_release_q(irq_ptr->input_qs[i]); - } - } - - if (flags&QDIO_FLAG_NO_INPUT_INTERRUPT_CONTEXT) { - for (i=0;ino_input_qs;i++) { - irq_ptr->input_qs[i]->is_input_q|= - QDIO_FLAG_NO_INPUT_INTERRUPT_CONTEXT; - } - } - - msleep(QDIO_ACTIVATE_TIMEOUT); - switch (irq_ptr->state) { - case QDIO_IRQ_STATE_STOPPED: - case QDIO_IRQ_STATE_ERR: - up(&irq_ptr->setting_up_sema); - qdio_shutdown(cdev, QDIO_FLAG_CLEANUP_USING_CLEAR); - down(&irq_ptr->setting_up_sema); - result = -EIO; - break; - default: - qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ACTIVE); - result = 0; - } - out: - up(&irq_ptr->setting_up_sema); - - return result; -} - -/* buffers filled forwards again to make Rick happy */ -static void -qdio_do_qdio_fill_input(struct qdio_q *q, unsigned int qidx, - unsigned int count, struct qdio_buffer *buffers) -{ - struct qdio_irq *irq = (struct qdio_irq *) q->irq_ptr; - int tmp = 0; - - qidx &= (QDIO_MAX_BUFFERS_PER_Q - 1); - if (irq->is_qebsm) { - while (count) { - tmp = set_slsb(q, &qidx, SLSB_CU_INPUT_EMPTY, &count); - if (!tmp) - return; - } - return; - } - for (;;) { - set_slsb(q, &qidx, SLSB_CU_INPUT_EMPTY, &count); - count--; - if (!count) break; - qidx = (qidx + 1) & (QDIO_MAX_BUFFERS_PER_Q - 1); - } -} - -static void -qdio_do_qdio_fill_output(struct qdio_q *q, unsigned int qidx, - unsigned int count, struct qdio_buffer *buffers) -{ - struct qdio_irq *irq = (struct qdio_irq *) q->irq_ptr; - int tmp = 0; - - qidx &= (QDIO_MAX_BUFFERS_PER_Q - 1); - if (irq->is_qebsm) { - while (count) { - tmp = set_slsb(q, &qidx, SLSB_CU_OUTPUT_PRIMED, &count); - if (!tmp) - return; - } - return; - } - - for (;;) { - set_slsb(q, &qidx, SLSB_CU_OUTPUT_PRIMED, &count); - count--; - if (!count) break; - qidx = (qidx + 1) & (QDIO_MAX_BUFFERS_PER_Q - 1); - } -} - -static void -do_qdio_handle_inbound(struct qdio_q *q, unsigned int callflags, - unsigned int qidx, unsigned int count, - struct qdio_buffer *buffers) -{ - int used_elements; - - /* This is the inbound handling of queues */ - used_elements=atomic_add_return(count, &q->number_of_buffers_used) - count; - - qdio_do_qdio_fill_input(q,qidx,count,buffers); - - if ((used_elements+count==QDIO_MAX_BUFFERS_PER_Q)&& - (callflags&QDIO_FLAG_UNDER_INTERRUPT)) - atomic_xchg(&q->polling,0); - - if (used_elements) - return; - if (callflags&QDIO_FLAG_DONT_SIGA) - return; - if (q->siga_in) { - int result; - - result=qdio_siga_input(q); - if (result) { - if (q->siga_error) - q->error_status_flags|= - QDIO_STATUS_MORE_THAN_ONE_SIGA_ERROR; - q->error_status_flags|=QDIO_STATUS_LOOK_FOR_ERROR; - q->siga_error=result; - } - } - - qdio_mark_q(q); -} - -static void -do_qdio_handle_outbound(struct qdio_q *q, unsigned int callflags, - unsigned int qidx, unsigned int count, - struct qdio_buffer *buffers) -{ - int used_elements; - unsigned int cnt, start_buf; - unsigned char state = 0; - struct qdio_irq *irq = (struct qdio_irq *) q->irq_ptr; - - /* This is the outbound handling of queues */ - qdio_do_qdio_fill_output(q,qidx,count,buffers); - - used_elements=atomic_add_return(count, &q->number_of_buffers_used) - count; - - if (callflags&QDIO_FLAG_DONT_SIGA) { - qdio_perf_stat_inc(&perf_stats.outbound_cnt); - return; - } - if (callflags & QDIO_FLAG_PCI_OUT) - q->is_pci_out = 1; - else - q->is_pci_out = 0; - if (q->is_iqdio_q) { - /* one siga for every sbal */ - while (count--) - qdio_kick_outbound_q(q); - - __qdio_outbound_processing(q); - } else { - /* under VM, we do a SIGA sync unconditionally */ - SYNC_MEMORY; - else { - /* - * w/o shadow queues (else branch of - * SYNC_MEMORY :-/ ), we try to - * fast-requeue buffers - */ - if (irq->is_qebsm) { - cnt = 1; - start_buf = ((qidx+QDIO_MAX_BUFFERS_PER_Q-1) & - (QDIO_MAX_BUFFERS_PER_Q-1)); - qdio_do_eqbs(q, &state, &start_buf, &cnt); - } else - state = q->slsb.acc.val[(qidx+QDIO_MAX_BUFFERS_PER_Q-1) - &(QDIO_MAX_BUFFERS_PER_Q-1) ]; - if (state != SLSB_CU_OUTPUT_PRIMED) { - qdio_kick_outbound_q(q); - } else { - QDIO_DBF_TEXT3(0,trace, "fast-req"); - qdio_perf_stat_inc(&perf_stats.fast_reqs); - } - } - /* - * only marking the q could take too long, - * the upper layer module could do a lot of - * traffic in that time - */ - __qdio_outbound_processing(q); - } - - qdio_perf_stat_inc(&perf_stats.outbound_cnt); -} - -/* count must be 1 in iqdio */ -int -do_QDIO(struct ccw_device *cdev,unsigned int callflags, - unsigned int queue_number, unsigned int qidx, - unsigned int count,struct qdio_buffer *buffers) -{ - struct qdio_irq *irq_ptr; -#ifdef CONFIG_QDIO_DEBUG - char dbf_text[20]; - - sprintf(dbf_text,"doQD%04x",cdev->private->schid.sch_no); - QDIO_DBF_TEXT3(0,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - - if ( (qidx>QDIO_MAX_BUFFERS_PER_Q) || - (count>QDIO_MAX_BUFFERS_PER_Q) || - (queue_number>QDIO_MAX_QUEUES_PER_IRQ) ) - return -EINVAL; - - if (count==0) - return 0; - - irq_ptr = cdev->private->qdio_data; - if (!irq_ptr) - return -ENODEV; - -#ifdef CONFIG_QDIO_DEBUG - if (callflags&QDIO_FLAG_SYNC_INPUT) - QDIO_DBF_HEX3(0,trace,&irq_ptr->input_qs[queue_number], - sizeof(void*)); - else - QDIO_DBF_HEX3(0,trace,&irq_ptr->output_qs[queue_number], - sizeof(void*)); - sprintf(dbf_text,"flag%04x",callflags); - QDIO_DBF_TEXT3(0,trace,dbf_text); - sprintf(dbf_text,"qi%02xct%02x",qidx,count); - QDIO_DBF_TEXT3(0,trace,dbf_text); -#endif /* CONFIG_QDIO_DEBUG */ - - if (irq_ptr->state!=QDIO_IRQ_STATE_ACTIVE) - return -EBUSY; - - if (callflags&QDIO_FLAG_SYNC_INPUT) - do_qdio_handle_inbound(irq_ptr->input_qs[queue_number], - callflags, qidx, count, buffers); - else if (callflags&QDIO_FLAG_SYNC_OUTPUT) - do_qdio_handle_outbound(irq_ptr->output_qs[queue_number], - callflags, qidx, count, buffers); - else { - QDIO_DBF_TEXT3(1,trace,"doQD:inv"); - return -EINVAL; - } - return 0; -} - -static int -qdio_perf_procfile_read(char *buffer, char **buffer_location, off_t offset, - int buffer_length, int *eof, void *data) -{ - int c=0; - - /* we are always called with buffer_length=4k, so we all - deliver on the first read */ - if (offset>0) - return 0; - -#define _OUTP_IT(x...) c+=sprintf(buffer+c,x) -#ifdef CONFIG_64BIT - _OUTP_IT("Number of tasklet runs (total) : %li\n", - (long)atomic64_read(&perf_stats.tl_runs)); - _OUTP_IT("Inbound tasklet runs tried/retried : %li/%li\n", - (long)atomic64_read(&perf_stats.inbound_tl_runs), - (long)atomic64_read(&perf_stats.inbound_tl_runs_resched)); - _OUTP_IT("Inbound-thin tasklet runs tried/retried : %li/%li\n", - (long)atomic64_read(&perf_stats.inbound_thin_tl_runs), - (long)atomic64_read(&perf_stats.inbound_thin_tl_runs_resched)); - _OUTP_IT("Outbound tasklet runs tried/retried : %li/%li\n", - (long)atomic64_read(&perf_stats.outbound_tl_runs), - (long)atomic64_read(&perf_stats.outbound_tl_runs_resched)); - _OUTP_IT("\n"); - _OUTP_IT("Number of SIGA sync's issued : %li\n", - (long)atomic64_read(&perf_stats.siga_syncs)); - _OUTP_IT("Number of SIGA in's issued : %li\n", - (long)atomic64_read(&perf_stats.siga_ins)); - _OUTP_IT("Number of SIGA out's issued : %li\n", - (long)atomic64_read(&perf_stats.siga_outs)); - _OUTP_IT("Number of PCIs caught : %li\n", - (long)atomic64_read(&perf_stats.pcis)); - _OUTP_IT("Number of adapter interrupts caught : %li\n", - (long)atomic64_read(&perf_stats.thinints)); - _OUTP_IT("Number of fast requeues (outg. SBALs w/o SIGA) : %li\n", - (long)atomic64_read(&perf_stats.fast_reqs)); - _OUTP_IT("\n"); - _OUTP_IT("Number of inbound transfers : %li\n", - (long)atomic64_read(&perf_stats.inbound_cnt)); - _OUTP_IT("Number of do_QDIOs outbound : %li\n", - (long)atomic64_read(&perf_stats.outbound_cnt)); -#else /* CONFIG_64BIT */ - _OUTP_IT("Number of tasklet runs (total) : %i\n", - atomic_read(&perf_stats.tl_runs)); - _OUTP_IT("Inbound tasklet runs tried/retried : %i/%i\n", - atomic_read(&perf_stats.inbound_tl_runs), - atomic_read(&perf_stats.inbound_tl_runs_resched)); - _OUTP_IT("Inbound-thin tasklet runs tried/retried : %i/%i\n", - atomic_read(&perf_stats.inbound_thin_tl_runs), - atomic_read(&perf_stats.inbound_thin_tl_runs_resched)); - _OUTP_IT("Outbound tasklet runs tried/retried : %i/%i\n", - atomic_read(&perf_stats.outbound_tl_runs), - atomic_read(&perf_stats.outbound_tl_runs_resched)); - _OUTP_IT("\n"); - _OUTP_IT("Number of SIGA sync's issued : %i\n", - atomic_read(&perf_stats.siga_syncs)); - _OUTP_IT("Number of SIGA in's issued : %i\n", - atomic_read(&perf_stats.siga_ins)); - _OUTP_IT("Number of SIGA out's issued : %i\n", - atomic_read(&perf_stats.siga_outs)); - _OUTP_IT("Number of PCIs caught : %i\n", - atomic_read(&perf_stats.pcis)); - _OUTP_IT("Number of adapter interrupts caught : %i\n", - atomic_read(&perf_stats.thinints)); - _OUTP_IT("Number of fast requeues (outg. SBALs w/o SIGA) : %i\n", - atomic_read(&perf_stats.fast_reqs)); - _OUTP_IT("\n"); - _OUTP_IT("Number of inbound transfers : %i\n", - atomic_read(&perf_stats.inbound_cnt)); - _OUTP_IT("Number of do_QDIOs outbound : %i\n", - atomic_read(&perf_stats.outbound_cnt)); -#endif /* CONFIG_64BIT */ - _OUTP_IT("\n"); - - return c; -} - -static struct proc_dir_entry *qdio_perf_proc_file; - -static void -qdio_add_procfs_entry(void) -{ - proc_perf_file_registration=0; - qdio_perf_proc_file=create_proc_entry(QDIO_PERF, - S_IFREG|0444,NULL); - if (qdio_perf_proc_file) { - qdio_perf_proc_file->read_proc=&qdio_perf_procfile_read; - } else proc_perf_file_registration=-1; - - if (proc_perf_file_registration) - QDIO_PRINT_WARN("was not able to register perf. " \ - "proc-file (%i).\n", - proc_perf_file_registration); -} - -static void -qdio_remove_procfs_entry(void) -{ - if (!proc_perf_file_registration) /* means if it went ok earlier */ - remove_proc_entry(QDIO_PERF,NULL); -} - -/** - * attributes in sysfs - *****************************************************************************/ - -static ssize_t -qdio_performance_stats_show(struct bus_type *bus, char *buf) -{ - return sprintf(buf, "%i\n", qdio_performance_stats ? 1 : 0); -} - -static ssize_t -qdio_performance_stats_store(struct bus_type *bus, const char *buf, size_t count) -{ - unsigned long i; - int ret; - - ret = strict_strtoul(buf, 16, &i); - if (!ret && ((i == 0) || (i == 1))) { - if (i == qdio_performance_stats) - return count; - qdio_performance_stats = i; - if (i==0) { - /* reset perf. stat. info */ -#ifdef CONFIG_64BIT - atomic64_set(&perf_stats.tl_runs, 0); - atomic64_set(&perf_stats.outbound_tl_runs, 0); - atomic64_set(&perf_stats.inbound_tl_runs, 0); - atomic64_set(&perf_stats.inbound_tl_runs_resched, 0); - atomic64_set(&perf_stats.inbound_thin_tl_runs, 0); - atomic64_set(&perf_stats.inbound_thin_tl_runs_resched, - 0); - atomic64_set(&perf_stats.siga_outs, 0); - atomic64_set(&perf_stats.siga_ins, 0); - atomic64_set(&perf_stats.siga_syncs, 0); - atomic64_set(&perf_stats.pcis, 0); - atomic64_set(&perf_stats.thinints, 0); - atomic64_set(&perf_stats.fast_reqs, 0); - atomic64_set(&perf_stats.outbound_cnt, 0); - atomic64_set(&perf_stats.inbound_cnt, 0); -#else /* CONFIG_64BIT */ - atomic_set(&perf_stats.tl_runs, 0); - atomic_set(&perf_stats.outbound_tl_runs, 0); - atomic_set(&perf_stats.inbound_tl_runs, 0); - atomic_set(&perf_stats.inbound_tl_runs_resched, 0); - atomic_set(&perf_stats.inbound_thin_tl_runs, 0); - atomic_set(&perf_stats.inbound_thin_tl_runs_resched, 0); - atomic_set(&perf_stats.siga_outs, 0); - atomic_set(&perf_stats.siga_ins, 0); - atomic_set(&perf_stats.siga_syncs, 0); - atomic_set(&perf_stats.pcis, 0); - atomic_set(&perf_stats.thinints, 0); - atomic_set(&perf_stats.fast_reqs, 0); - atomic_set(&perf_stats.outbound_cnt, 0); - atomic_set(&perf_stats.inbound_cnt, 0); -#endif /* CONFIG_64BIT */ - } - } else { - QDIO_PRINT_ERR("QDIO performance_stats: write 0 or 1 to this file!\n"); - return -EINVAL; - } - return count; -} - -static BUS_ATTR(qdio_performance_stats, 0644, qdio_performance_stats_show, - qdio_performance_stats_store); - -static void -tiqdio_register_thinints(void) -{ - char dbf_text[20]; - - tiqdio_ind = - s390_register_adapter_interrupt(&tiqdio_thinint_handler, NULL, - TIQDIO_THININT_ISC); - if (IS_ERR(tiqdio_ind)) { - sprintf(dbf_text, "regthn%lx", PTR_ERR(tiqdio_ind)); - QDIO_DBF_TEXT0(0,setup,dbf_text); - QDIO_PRINT_ERR("failed to register adapter handler " \ - "(rc=%li).\nAdapter interrupts might " \ - "not work. Continuing.\n", - PTR_ERR(tiqdio_ind)); - tiqdio_ind = NULL; - } -} - -static void -tiqdio_unregister_thinints(void) -{ - if (tiqdio_ind) - s390_unregister_adapter_interrupt(tiqdio_ind, - TIQDIO_THININT_ISC); -} - -static int -qdio_get_qdio_memory(void) -{ - int i; - indicator_used[0]=1; - - for (i=1;i + * Jan Glauber + */ #ifndef _CIO_QDIO_H #define _CIO_QDIO_H #include -#include #include +#include "chsc.h" -#ifdef CONFIG_QDIO_DEBUG -#define QDIO_VERBOSE_LEVEL 9 -#else /* CONFIG_QDIO_DEBUG */ -#define QDIO_VERBOSE_LEVEL 5 -#endif /* CONFIG_QDIO_DEBUG */ -#define QDIO_USE_PROCESSING_STATE - -#define QDIO_MINIMAL_BH_RELIEF_TIME 16 -#define QDIO_TIMER_POLL_VALUE 1 -#define IQDIO_TIMER_POLL_VALUE 1 - -/* - * unfortunately this can't be (QDIO_MAX_BUFFERS_PER_Q*4/3) or so -- as - * we never know, whether we'll get initiative again, e.g. to give the - * transmit skb's back to the stack, however the stack may be waiting for - * them... therefore we define 4 as threshold to start polling (which - * will stop as soon as the asynchronous queue catches up) - * btw, this only applies to the asynchronous HiperSockets queue - */ -#define IQDIO_FILL_LEVEL_TO_POLL 4 - -#define TIQDIO_THININT_ISC QDIO_AIRQ_ISC -#define TIQDIO_DELAY_TARGET 0 -#define QDIO_BUSY_BIT_PATIENCE 100 /* in microsecs */ -#define QDIO_BUSY_BIT_GIVE_UP 10000000 /* 10 seconds */ -#define IQDIO_GLOBAL_LAPS 2 /* GLOBAL_LAPS are not used as we */ -#define IQDIO_GLOBAL_LAPS_INT 1 /* don't global summary */ -#define IQDIO_LOCAL_LAPS 4 -#define IQDIO_LOCAL_LAPS_INT 1 -#define IQDIO_GLOBAL_SUMMARY_CC_MASK 2 -/*#define IQDIO_IQDC_INT_PARM 0x1234*/ - -#define QDIO_Q_LAPS 5 - -#define QDIO_STORAGE_KEY PAGE_DEFAULT_KEY - -#define L2_CACHELINE_SIZE 256 -#define INDICATORS_PER_CACHELINE (L2_CACHELINE_SIZE/sizeof(__u32)) - -#define QDIO_PERF "qdio_perf" - -/* must be a power of 2 */ -/*#define QDIO_STATS_NUMBER 4 - -#define QDIO_STATS_CLASSES 2 -#define QDIO_STATS_COUNT_NEEDED 2*/ - -#define QDIO_NO_USE_COUNT_TIMEOUT (1*HZ) /* wait for 1 sec on each q before - exiting without having use_count - of the queue to 0 */ - -#define QDIO_ESTABLISH_TIMEOUT (1*HZ) -#define QDIO_CLEANUP_CLEAR_TIMEOUT (20*HZ) -#define QDIO_CLEANUP_HALT_TIMEOUT (10*HZ) -#define QDIO_FORCE_CHECK_TIMEOUT (10*HZ) -#define QDIO_ACTIVATE_TIMEOUT (5) /* 5 ms */ +#define QDIO_BUSY_BIT_PATIENCE 100 /* 100 microseconds */ +#define QDIO_BUSY_BIT_GIVE_UP 2000000 /* 2 seconds = eternity */ +#define QDIO_INPUT_THRESHOLD 500 /* 500 microseconds */ enum qdio_irq_states { QDIO_IRQ_STATE_INACTIVE, @@ -72,565 +26,352 @@ enum qdio_irq_states { NR_QDIO_IRQ_STATES, }; -/* used as intparm in do_IO: */ -#define QDIO_DOING_SENSEID 0 -#define QDIO_DOING_ESTABLISH 1 -#define QDIO_DOING_ACTIVATE 2 -#define QDIO_DOING_CLEANUP 3 - -/************************* DEBUG FACILITY STUFF *********************/ - -#define QDIO_DBF_HEX(ex,name,level,addr,len) \ - do { \ - if (ex) \ - debug_exception(qdio_dbf_##name,level,(void*)(addr),len); \ - else \ - debug_event(qdio_dbf_##name,level,(void*)(addr),len); \ - } while (0) -#define QDIO_DBF_TEXT(ex,name,level,text) \ - do { \ - if (ex) \ - debug_text_exception(qdio_dbf_##name,level,text); \ - else \ - debug_text_event(qdio_dbf_##name,level,text); \ - } while (0) - - -#define QDIO_DBF_HEX0(ex,name,addr,len) QDIO_DBF_HEX(ex,name,0,addr,len) -#define QDIO_DBF_HEX1(ex,name,addr,len) QDIO_DBF_HEX(ex,name,1,addr,len) -#define QDIO_DBF_HEX2(ex,name,addr,len) QDIO_DBF_HEX(ex,name,2,addr,len) -#ifdef CONFIG_QDIO_DEBUG -#define QDIO_DBF_HEX3(ex,name,addr,len) QDIO_DBF_HEX(ex,name,3,addr,len) -#define QDIO_DBF_HEX4(ex,name,addr,len) QDIO_DBF_HEX(ex,name,4,addr,len) -#define QDIO_DBF_HEX5(ex,name,addr,len) QDIO_DBF_HEX(ex,name,5,addr,len) -#define QDIO_DBF_HEX6(ex,name,addr,len) QDIO_DBF_HEX(ex,name,6,addr,len) -#else /* CONFIG_QDIO_DEBUG */ -#define QDIO_DBF_HEX3(ex,name,addr,len) do {} while (0) -#define QDIO_DBF_HEX4(ex,name,addr,len) do {} while (0) -#define QDIO_DBF_HEX5(ex,name,addr,len) do {} while (0) -#define QDIO_DBF_HEX6(ex,name,addr,len) do {} while (0) -#endif /* CONFIG_QDIO_DEBUG */ - -#define QDIO_DBF_TEXT0(ex,name,text) QDIO_DBF_TEXT(ex,name,0,text) -#define QDIO_DBF_TEXT1(ex,name,text) QDIO_DBF_TEXT(ex,name,1,text) -#define QDIO_DBF_TEXT2(ex,name,text) QDIO_DBF_TEXT(ex,name,2,text) -#ifdef CONFIG_QDIO_DEBUG -#define QDIO_DBF_TEXT3(ex,name,text) QDIO_DBF_TEXT(ex,name,3,text) -#define QDIO_DBF_TEXT4(ex,name,text) QDIO_DBF_TEXT(ex,name,4,text) -#define QDIO_DBF_TEXT5(ex,name,text) QDIO_DBF_TEXT(ex,name,5,text) -#define QDIO_DBF_TEXT6(ex,name,text) QDIO_DBF_TEXT(ex,name,6,text) -#else /* CONFIG_QDIO_DEBUG */ -#define QDIO_DBF_TEXT3(ex,name,text) do {} while (0) -#define QDIO_DBF_TEXT4(ex,name,text) do {} while (0) -#define QDIO_DBF_TEXT5(ex,name,text) do {} while (0) -#define QDIO_DBF_TEXT6(ex,name,text) do {} while (0) -#endif /* CONFIG_QDIO_DEBUG */ - -#define QDIO_DBF_SETUP_NAME "qdio_setup" -#define QDIO_DBF_SETUP_LEN 8 -#define QDIO_DBF_SETUP_PAGES 4 -#define QDIO_DBF_SETUP_NR_AREAS 1 -#ifdef CONFIG_QDIO_DEBUG -#define QDIO_DBF_SETUP_LEVEL 6 -#else /* CONFIG_QDIO_DEBUG */ -#define QDIO_DBF_SETUP_LEVEL 2 -#endif /* CONFIG_QDIO_DEBUG */ - -#define QDIO_DBF_SBAL_NAME "qdio_labs" /* sbal */ -#define QDIO_DBF_SBAL_LEN 256 -#define QDIO_DBF_SBAL_PAGES 4 -#define QDIO_DBF_SBAL_NR_AREAS 2 -#ifdef CONFIG_QDIO_DEBUG -#define QDIO_DBF_SBAL_LEVEL 6 -#else /* CONFIG_QDIO_DEBUG */ -#define QDIO_DBF_SBAL_LEVEL 2 -#endif /* CONFIG_QDIO_DEBUG */ - -#define QDIO_DBF_TRACE_NAME "qdio_trace" -#define QDIO_DBF_TRACE_LEN 8 -#define QDIO_DBF_TRACE_NR_AREAS 2 -#ifdef CONFIG_QDIO_DEBUG -#define QDIO_DBF_TRACE_PAGES 16 -#define QDIO_DBF_TRACE_LEVEL 4 /* -------- could be even more verbose here */ -#else /* CONFIG_QDIO_DEBUG */ -#define QDIO_DBF_TRACE_PAGES 4 -#define QDIO_DBF_TRACE_LEVEL 2 -#endif /* CONFIG_QDIO_DEBUG */ - -#define QDIO_DBF_SENSE_NAME "qdio_sense" -#define QDIO_DBF_SENSE_LEN 64 -#define QDIO_DBF_SENSE_PAGES 2 -#define QDIO_DBF_SENSE_NR_AREAS 1 -#ifdef CONFIG_QDIO_DEBUG -#define QDIO_DBF_SENSE_LEVEL 6 -#else /* CONFIG_QDIO_DEBUG */ -#define QDIO_DBF_SENSE_LEVEL 2 -#endif /* CONFIG_QDIO_DEBUG */ - -#ifdef CONFIG_QDIO_DEBUG -#define QDIO_TRACE_QTYPE QDIO_ZFCP_QFMT - -#define QDIO_DBF_SLSB_OUT_NAME "qdio_slsb_out" -#define QDIO_DBF_SLSB_OUT_LEN QDIO_MAX_BUFFERS_PER_Q -#define QDIO_DBF_SLSB_OUT_PAGES 256 -#define QDIO_DBF_SLSB_OUT_NR_AREAS 1 -#define QDIO_DBF_SLSB_OUT_LEVEL 6 - -#define QDIO_DBF_SLSB_IN_NAME "qdio_slsb_in" -#define QDIO_DBF_SLSB_IN_LEN QDIO_MAX_BUFFERS_PER_Q -#define QDIO_DBF_SLSB_IN_PAGES 256 -#define QDIO_DBF_SLSB_IN_NR_AREAS 1 -#define QDIO_DBF_SLSB_IN_LEVEL 6 -#endif /* CONFIG_QDIO_DEBUG */ - -#define QDIO_PRINTK_HEADER QDIO_NAME ": " - -#if QDIO_VERBOSE_LEVEL>8 -#define QDIO_PRINT_STUPID(x...) printk( KERN_DEBUG QDIO_PRINTK_HEADER x) -#else -#define QDIO_PRINT_STUPID(x...) do { } while (0) -#endif +/* used as intparm in do_IO */ +#define QDIO_DOING_ESTABLISH 1 +#define QDIO_DOING_ACTIVATE 2 +#define QDIO_DOING_CLEANUP 3 + +#define SLSB_STATE_NOT_INIT 0x0 +#define SLSB_STATE_EMPTY 0x1 +#define SLSB_STATE_PRIMED 0x2 +#define SLSB_STATE_HALTED 0xe +#define SLSB_STATE_ERROR 0xf +#define SLSB_TYPE_INPUT 0x0 +#define SLSB_TYPE_OUTPUT 0x20 +#define SLSB_OWNER_PROG 0x80 +#define SLSB_OWNER_CU 0x40 + +#define SLSB_P_INPUT_NOT_INIT \ + (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT) /* 0x80 */ +#define SLSB_P_INPUT_ACK \ + (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x81 */ +#define SLSB_CU_INPUT_EMPTY \ + (SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x41 */ +#define SLSB_P_INPUT_PRIMED \ + (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED) /* 0x82 */ +#define SLSB_P_INPUT_HALTED \ + (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED) /* 0x8e */ +#define SLSB_P_INPUT_ERROR \ + (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR) /* 0x8f */ +#define SLSB_P_OUTPUT_NOT_INIT \ + (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */ +#define SLSB_P_OUTPUT_EMPTY \ + (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY) /* 0xa1 */ +#define SLSB_CU_OUTPUT_PRIMED \ + (SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED) /* 0x62 */ +#define SLSB_P_OUTPUT_HALTED \ + (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED) /* 0xae */ +#define SLSB_P_OUTPUT_ERROR \ + (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR) /* 0xaf */ + +#define SLSB_ERROR_DURING_LOOKUP 0xff + +/* additional CIWs returned by extended Sense-ID */ +#define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */ +#define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */ -#if QDIO_VERBOSE_LEVEL>7 -#define QDIO_PRINT_ALL(x...) printk( QDIO_PRINTK_HEADER x) -#else -#define QDIO_PRINT_ALL(x...) do { } while (0) -#endif - -#if QDIO_VERBOSE_LEVEL>6 -#define QDIO_PRINT_INFO(x...) printk( QDIO_PRINTK_HEADER x) -#else -#define QDIO_PRINT_INFO(x...) do { } while (0) -#endif - -#if QDIO_VERBOSE_LEVEL>5 -#define QDIO_PRINT_WARN(x...) printk( QDIO_PRINTK_HEADER x) -#else -#define QDIO_PRINT_WARN(x...) do { } while (0) -#endif - -#if QDIO_VERBOSE_LEVEL>4 -#define QDIO_PRINT_ERR(x...) printk( QDIO_PRINTK_HEADER x) -#else -#define QDIO_PRINT_ERR(x...) do { } while (0) -#endif - -#if QDIO_VERBOSE_LEVEL>3 -#define QDIO_PRINT_CRIT(x...) printk( QDIO_PRINTK_HEADER x) -#else -#define QDIO_PRINT_CRIT(x...) do { } while (0) -#endif - -#if QDIO_VERBOSE_LEVEL>2 -#define QDIO_PRINT_ALERT(x...) printk( QDIO_PRINTK_HEADER x) -#else -#define QDIO_PRINT_ALERT(x...) do { } while (0) -#endif +/* flags for st qdio sch data */ +#define CHSC_FLAG_QDIO_CAPABILITY 0x80 +#define CHSC_FLAG_VALIDITY 0x40 + +/* qdio adapter-characteristics-1 flag */ +#define AC1_SIGA_INPUT_NEEDED 0x40 /* process input queues */ +#define AC1_SIGA_OUTPUT_NEEDED 0x20 /* process output queues */ +#define AC1_SIGA_SYNC_NEEDED 0x10 /* ask hypervisor to sync */ +#define AC1_AUTOMATIC_SYNC_ON_THININT 0x08 /* set by hypervisor */ +#define AC1_AUTOMATIC_SYNC_ON_OUT_PCI 0x04 /* set by hypervisor */ +#define AC1_SC_QEBSM_AVAILABLE 0x02 /* available for subchannel */ +#define AC1_SC_QEBSM_ENABLED 0x01 /* enabled for subchannel */ -#if QDIO_VERBOSE_LEVEL>1 -#define QDIO_PRINT_EMERG(x...) printk( QDIO_PRINTK_HEADER x) -#else -#define QDIO_PRINT_EMERG(x...) do { } while (0) -#endif - -#define QDIO_HEXDUMP16(importance,header,ptr) \ -QDIO_PRINT_##importance(header "%02x %02x %02x %02x " \ - "%02x %02x %02x %02x %02x %02x %02x %02x " \ - "%02x %02x %02x %02x\n",*(((char*)ptr)), \ - *(((char*)ptr)+1),*(((char*)ptr)+2), \ - *(((char*)ptr)+3),*(((char*)ptr)+4), \ - *(((char*)ptr)+5),*(((char*)ptr)+6), \ - *(((char*)ptr)+7),*(((char*)ptr)+8), \ - *(((char*)ptr)+9),*(((char*)ptr)+10), \ - *(((char*)ptr)+11),*(((char*)ptr)+12), \ - *(((char*)ptr)+13),*(((char*)ptr)+14), \ - *(((char*)ptr)+15)); \ -QDIO_PRINT_##importance(header "%02x %02x %02x %02x %02x %02x %02x %02x " \ - "%02x %02x %02x %02x %02x %02x %02x %02x\n", \ - *(((char*)ptr)+16),*(((char*)ptr)+17), \ - *(((char*)ptr)+18),*(((char*)ptr)+19), \ - *(((char*)ptr)+20),*(((char*)ptr)+21), \ - *(((char*)ptr)+22),*(((char*)ptr)+23), \ - *(((char*)ptr)+24),*(((char*)ptr)+25), \ - *(((char*)ptr)+26),*(((char*)ptr)+27), \ - *(((char*)ptr)+28),*(((char*)ptr)+29), \ - *(((char*)ptr)+30),*(((char*)ptr)+31)); - -/****************** END OF DEBUG FACILITY STUFF *********************/ +#ifdef CONFIG_64BIT +static inline int do_sqbs(u64 token, unsigned char state, int queue, + int *start, int *count) +{ + register unsigned long _ccq asm ("0") = *count; + register unsigned long _token asm ("1") = token; + unsigned long _queuestart = ((unsigned long)queue << 32) | *start; -/* - * Some instructions as assembly - */ + asm volatile( + " .insn rsy,0xeb000000008A,%1,0,0(%2)" + : "+d" (_ccq), "+d" (_queuestart) + : "d" ((unsigned long)state), "d" (_token) + : "memory", "cc"); + *count = _ccq & 0xff; + *start = _queuestart & 0xff; -static inline int -do_sqbs(unsigned long sch, unsigned char state, int queue, - unsigned int *start, unsigned int *count) -{ -#ifdef CONFIG_64BIT - register unsigned long _ccq asm ("0") = *count; - register unsigned long _sch asm ("1") = sch; - unsigned long _queuestart = ((unsigned long)queue << 32) | *start; - - asm volatile( - " .insn rsy,0xeb000000008A,%1,0,0(%2)" - : "+d" (_ccq), "+d" (_queuestart) - : "d" ((unsigned long)state), "d" (_sch) - : "memory", "cc"); - *count = _ccq & 0xff; - *start = _queuestart & 0xff; - - return (_ccq >> 32) & 0xff; -#else - return 0; -#endif + return (_ccq >> 32) & 0xff; } -static inline int -do_eqbs(unsigned long sch, unsigned char *state, int queue, - unsigned int *start, unsigned int *count) +static inline int do_eqbs(u64 token, unsigned char *state, int queue, + int *start, int *count) { -#ifdef CONFIG_64BIT register unsigned long _ccq asm ("0") = *count; - register unsigned long _sch asm ("1") = sch; + register unsigned long _token asm ("1") = token; unsigned long _queuestart = ((unsigned long)queue << 32) | *start; unsigned long _state = 0; asm volatile( " .insn rrf,0xB99c0000,%1,%2,0,0" : "+d" (_ccq), "+d" (_queuestart), "+d" (_state) - : "d" (_sch) - : "memory", "cc" ); + : "d" (_token) + : "memory", "cc"); *count = _ccq & 0xff; *start = _queuestart & 0xff; *state = _state & 0xff; return (_ccq >> 32) & 0xff; -#else - return 0; -#endif -} - - -static inline int -do_siga_sync(struct subchannel_id schid, unsigned int mask1, unsigned int mask2) -{ - register unsigned long reg0 asm ("0") = 2; - register struct subchannel_id reg1 asm ("1") = schid; - register unsigned long reg2 asm ("2") = mask1; - register unsigned long reg3 asm ("3") = mask2; - int cc; - - asm volatile( - " siga 0\n" - " ipm %0\n" - " srl %0,28\n" - : "=d" (cc) - : "d" (reg0), "d" (reg1), "d" (reg2), "d" (reg3) : "cc"); - return cc; -} - -static inline int -do_siga_input(struct subchannel_id schid, unsigned int mask) -{ - register unsigned long reg0 asm ("0") = 1; - register struct subchannel_id reg1 asm ("1") = schid; - register unsigned long reg2 asm ("2") = mask; - int cc; - - asm volatile( - " siga 0\n" - " ipm %0\n" - " srl %0,28\n" - : "=d" (cc) - : "d" (reg0), "d" (reg1), "d" (reg2) : "cc", "memory"); - return cc; -} - -static inline int -do_siga_output(unsigned long schid, unsigned long mask, __u32 *bb, - unsigned int fc) -{ - register unsigned long __fc asm("0") = fc; - register unsigned long __schid asm("1") = schid; - register unsigned long __mask asm("2") = mask; - int cc; - - asm volatile( - " siga 0\n" - "0: ipm %0\n" - " srl %0,28\n" - "1:\n" - EX_TABLE(0b,1b) - : "=d" (cc), "+d" (__fc), "+d" (__schid), "+d" (__mask) - : "0" (QDIO_SIGA_ERROR_ACCESS_EXCEPTION) - : "cc", "memory"); - (*bb) = ((unsigned int) __fc) >> 31; - return cc; -} - -static inline unsigned long -do_clear_global_summary(void) -{ - register unsigned long __fn asm("1") = 3; - register unsigned long __tmp asm("2"); - register unsigned long __time asm("3"); - - asm volatile( - " .insn rre,0xb2650000,2,0" - : "+d" (__fn), "=d" (__tmp), "=d" (__time)); - return __time; } - -/* - * QDIO device commands returned by extended Sense-ID - */ -#define DEFAULT_ESTABLISH_QS_CMD 0x1b -#define DEFAULT_ESTABLISH_QS_COUNT 0x1000 -#define DEFAULT_ACTIVATE_QS_CMD 0x1f -#define DEFAULT_ACTIVATE_QS_COUNT 0 - -/* - * additional CIWs returned by extended Sense-ID - */ -#define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */ -#define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */ +#else +static inline int do_sqbs(u64 token, unsigned char state, int queue, + int *start, int *count) { return 0; } +static inline int do_eqbs(u64 token, unsigned char *state, int queue, + int *start, int *count) { return 0; } +#endif /* CONFIG_64BIT */ -#define QDIO_CHSC_RESPONSE_CODE_OK 1 -/* flags for st qdio sch data */ -#define CHSC_FLAG_QDIO_CAPABILITY 0x80 -#define CHSC_FLAG_VALIDITY 0x40 +struct qdio_irq; -#define CHSC_FLAG_SIGA_INPUT_NECESSARY 0x40 -#define CHSC_FLAG_SIGA_OUTPUT_NECESSARY 0x20 -#define CHSC_FLAG_SIGA_SYNC_NECESSARY 0x10 -#define CHSC_FLAG_SIGA_SYNC_DONE_ON_THININTS 0x08 -#define CHSC_FLAG_SIGA_SYNC_DONE_ON_OUTB_PCIS 0x04 +struct siga_flag { + u8 input:1; + u8 output:1; + u8 sync:1; + u8 no_sync_ti:1; + u8 no_sync_out_ti:1; + u8 no_sync_out_pci:1; + u8:2; +} __attribute__ ((packed)); -struct qdio_chsc_ssqd { +struct chsc_ssqd_area { struct chsc_header request; - u16 reserved1:10; - u16 ssid:2; - u16 fmt:4; + u16:10; + u8 ssid:2; + u8 fmt:4; u16 first_sch; - u16 reserved2; + u16:16; u16 last_sch; - u32 reserved3; + u32:32; struct chsc_header response; - u32 reserved4; - u8 flags; - u8 reserved5; - u16 sch; - u8 qfmt; - u8 parm; - u8 qdioac1; - u8 sch_class; - u8 pct; - u8 icnt; - u8 reserved7; - u8 ocnt; - u8 reserved8; - u8 mbccnt; - u16 qdioac2; - u64 sch_token; -}; + u32:32; + struct qdio_ssqd_desc qdio_ssqd; +} __attribute__ ((packed)); -struct qdio_perf_stats { -#ifdef CONFIG_64BIT - atomic64_t tl_runs; - atomic64_t outbound_tl_runs; - atomic64_t outbound_tl_runs_resched; - atomic64_t inbound_tl_runs; - atomic64_t inbound_tl_runs_resched; - atomic64_t inbound_thin_tl_runs; - atomic64_t inbound_thin_tl_runs_resched; - - atomic64_t siga_outs; - atomic64_t siga_ins; - atomic64_t siga_syncs; - atomic64_t pcis; - atomic64_t thinints; - atomic64_t fast_reqs; - - atomic64_t outbound_cnt; - atomic64_t inbound_cnt; -#else /* CONFIG_64BIT */ - atomic_t tl_runs; - atomic_t outbound_tl_runs; - atomic_t outbound_tl_runs_resched; - atomic_t inbound_tl_runs; - atomic_t inbound_tl_runs_resched; - atomic_t inbound_thin_tl_runs; - atomic_t inbound_thin_tl_runs_resched; - - atomic_t siga_outs; - atomic_t siga_ins; - atomic_t siga_syncs; - atomic_t pcis; - atomic_t thinints; - atomic_t fast_reqs; - - atomic_t outbound_cnt; - atomic_t inbound_cnt; -#endif /* CONFIG_64BIT */ +struct scssc_area { + struct chsc_header request; + u16 operation_code; + u16:16; + u32:32; + u32:32; + u64 summary_indicator_addr; + u64 subchannel_indicator_addr; + u32 ks:4; + u32 kc:4; + u32:21; + u32 isc:3; + u32 word_with_d_bit; + u32:32; + struct subchannel_id schid; + u32 reserved[1004]; + struct chsc_header response; + u32:32; +} __attribute__ ((packed)); + +struct qdio_input_q { + /* input buffer acknowledgement flag */ + int polling; + + /* last time of noticing incoming data */ + u64 timestamp; + + /* lock for clearing the acknowledgement */ + spinlock_t lock; }; -/* unlikely as the later the better */ -#define SYNC_MEMORY if (unlikely(q->siga_sync)) qdio_siga_sync_q(q) -#define SYNC_MEMORY_ALL if (unlikely(q->siga_sync)) \ - qdio_siga_sync(q,~0U,~0U) -#define SYNC_MEMORY_ALL_OUTB if (unlikely(q->siga_sync)) \ - qdio_siga_sync(q,~0U,0) +struct qdio_output_q { + /* failed siga-w attempts*/ + atomic_t busy_siga_counter; -#define NOW qdio_get_micros() -#define SAVE_TIMESTAMP(q) q->timing.last_transfer_time=NOW -#define GET_SAVED_TIMESTAMP(q) (q->timing.last_transfer_time) -#define SAVE_FRONTIER(q,val) q->last_move_ftc=val -#define GET_SAVED_FRONTIER(q) (q->last_move_ftc) + /* start time of busy condition */ + u64 timestamp; -#define MY_MODULE_STRING(x) #x + /* PCIs are enabled for the queue */ + int pci_out_enabled; -#ifdef CONFIG_64BIT -#define QDIO_GET_ADDR(x) ((__u32)(unsigned long)x) -#else /* CONFIG_64BIT */ -#define QDIO_GET_ADDR(x) ((__u32)(long)x) -#endif /* CONFIG_64BIT */ + /* timer to check for more outbound work */ + struct timer_list timer; +}; struct qdio_q { - volatile struct slsb slsb; + struct slsb slsb; + union { + struct qdio_input_q in; + struct qdio_output_q out; + } u; - char unused[QDIO_MAX_BUFFERS_PER_Q]; + /* queue number */ + int nr; - __u32 * dev_st_chg_ind; + /* bitmask of queue number */ + int mask; + /* input or output queue */ int is_input_q; - struct subchannel_id schid; - struct ccw_device *cdev; - - unsigned int is_iqdio_q; - unsigned int is_thinint_q; - /* bit 0 means queue 0, bit 1 means queue 1, ... */ - unsigned int mask; - unsigned int q_no; + /* list of thinint input queues */ + struct list_head entry; + /* upper-layer program handler */ qdio_handler_t (*handler); - /* points to the next buffer to be checked for having - * been processed by the card (outbound) - * or to the next buffer the program should check for (inbound) */ - volatile int first_to_check; - /* and the last time it was: */ - volatile int last_move_ftc; + /* + * inbound: next buffer the program should check for + * outbound: next buffer to check for having been processed + * by the card + */ + int first_to_check; - atomic_t number_of_buffers_used; - atomic_t polling; + /* first_to_check of the last time */ + int last_move_ftc; - unsigned int siga_in; - unsigned int siga_out; - unsigned int siga_sync; - unsigned int siga_sync_done_on_thinints; - unsigned int siga_sync_done_on_outb_tis; - unsigned int hydra_gives_outbound_pcis; + /* beginning position for calling the program */ + int first_to_kick; - /* used to save beginning position when calling dd_handlers */ - int first_element_to_kick; + /* number of buffers in use by the adapter */ + atomic_t nr_buf_used; - atomic_t use_count; - atomic_t is_in_shutdown; - - void *irq_ptr; - - struct timer_list timer; -#ifdef QDIO_USE_TIMERS_FOR_POLLING - atomic_t timer_already_set; - spinlock_t timer_lock; -#else /* QDIO_USE_TIMERS_FOR_POLLING */ + struct qdio_irq *irq_ptr; struct tasklet_struct tasklet; -#endif /* QDIO_USE_TIMERS_FOR_POLLING */ - - enum qdio_irq_states state; - - /* used to store the error condition during a data transfer */ + /* error condition during a data transfer */ unsigned int qdio_error; - unsigned int siga_error; - unsigned int error_status_flags; - - /* list of interesting queues */ - volatile struct qdio_q *list_next; - volatile struct qdio_q *list_prev; struct sl *sl; - volatile struct sbal *sbal[QDIO_MAX_BUFFERS_PER_Q]; - - struct qdio_buffer *qdio_buffers[QDIO_MAX_BUFFERS_PER_Q]; - - unsigned long int_parm; - - /*struct { - int in_bh_check_limit; - int threshold; - } threshold_classes[QDIO_STATS_CLASSES];*/ - - struct { - /* inbound: the time to stop polling - outbound: the time to kick peer */ - int threshold; /* the real value */ - - /* outbound: last time of do_QDIO - inbound: last time of noticing incoming data */ - /*__u64 last_transfer_times[QDIO_STATS_NUMBER]; - int last_transfer_index; */ - - __u64 last_transfer_time; - __u64 busy_start; - } timing; - atomic_t busy_siga_counter; - unsigned int queue_type; - unsigned int is_pci_out; - - /* leave this member at the end. won't be cleared in qdio_fill_qs */ - struct slib *slib; /* a page is allocated under this pointer, - sl points into this page, offset PAGE_SIZE/2 - (after slib) */ + struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q]; + + /* + * Warning: Leave this member at the end so it won't be cleared in + * qdio_fill_qs. A page is allocated under this pointer and used for + * slib and sl. slib is 2048 bytes big and sl points to offset + * PAGE_SIZE / 2. + */ + struct slib *slib; } __attribute__ ((aligned(256))); struct qdio_irq { - __u32 * volatile dev_st_chg_ind; + struct qib qib; + u32 *dsci; /* address of device state change indicator */ + struct ccw_device *cdev; unsigned long int_parm; struct subchannel_id schid; - - unsigned int is_iqdio_irq; - unsigned int is_thinint_irq; - unsigned int hydra_gives_outbound_pcis; - unsigned int sync_done_on_outb_pcis; - - /* QEBSM facility */ - unsigned int is_qebsm; - unsigned long sch_token; + unsigned long sch_token; /* QEBSM facility */ enum qdio_irq_states state; - unsigned int no_input_qs; - unsigned int no_output_qs; + struct siga_flag siga_flag; /* siga sync information from qdioac */ - unsigned char qdioac; + int nr_input_qs; + int nr_output_qs; struct ccw1 ccw; - struct ciw equeue; struct ciw aqueue; - struct qib qib; - - void (*original_int_handler) (struct ccw_device *, - unsigned long, struct irb *); + struct qdio_ssqd_desc ssqd_desc; + + void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *); - /* leave these four members together at the end. won't be cleared in qdio_fill_irq */ + /* + * Warning: Leave these members together at the end so they won't be + * cleared in qdio_setup_irq. + */ struct qdr *qdr; + unsigned long chsc_page; + struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ]; struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ]; - struct semaphore setting_up_sema; + + struct mutex setup_mutex; }; -#endif + +/* helper functions */ +#define queue_type(q) q->irq_ptr->qib.qfmt + +#define is_thinint_irq(irq) \ + (irq->qib.qfmt == QDIO_IQDIO_QFMT || \ + css_general_characteristics.aif_osa) + +/* the highest iqdio queue is used for multicast */ +static inline int multicast_outbound(struct qdio_q *q) +{ + return (q->irq_ptr->nr_output_qs > 1) && + (q->nr == q->irq_ptr->nr_output_qs - 1); +} + +static inline unsigned long long get_usecs(void) +{ + return monotonic_clock() >> 12; +} + +#define pci_out_supported(q) \ + (q->irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED) +#define is_qebsm(q) (q->irq_ptr->sch_token != 0) + +#define need_siga_sync_thinint(q) (!q->irq_ptr->siga_flag.no_sync_ti) +#define need_siga_sync_out_thinint(q) (!q->irq_ptr->siga_flag.no_sync_out_ti) +#define need_siga_in(q) (q->irq_ptr->siga_flag.input) +#define need_siga_out(q) (q->irq_ptr->siga_flag.output) +#define need_siga_sync(q) (q->irq_ptr->siga_flag.sync) +#define siga_syncs_out_pci(q) (q->irq_ptr->siga_flag.no_sync_out_pci) + +#define for_each_input_queue(irq_ptr, q, i) \ + for (i = 0, q = irq_ptr->input_qs[0]; \ + i < irq_ptr->nr_input_qs; \ + q = irq_ptr->input_qs[++i]) +#define for_each_output_queue(irq_ptr, q, i) \ + for (i = 0, q = irq_ptr->output_qs[0]; \ + i < irq_ptr->nr_output_qs; \ + q = irq_ptr->output_qs[++i]) + +#define prev_buf(bufnr) \ + ((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK) +#define next_buf(bufnr) \ + ((bufnr + 1) & QDIO_MAX_BUFFERS_MASK) +#define add_buf(bufnr, inc) \ + ((bufnr + inc) & QDIO_MAX_BUFFERS_MASK) + +/* prototypes for thin interrupt */ +void qdio_sync_after_thinint(struct qdio_q *q); +int get_buf_state(struct qdio_q *q, unsigned int bufnr, unsigned char *state); +void qdio_check_outbound_after_thinint(struct qdio_q *q); +int qdio_inbound_q_moved(struct qdio_q *q); +void qdio_kick_inbound_handler(struct qdio_q *q); +void qdio_stop_polling(struct qdio_q *q); +int qdio_siga_sync_q(struct qdio_q *q); + +void qdio_setup_thinint(struct qdio_irq *irq_ptr); +int qdio_establish_thinint(struct qdio_irq *irq_ptr); +void qdio_shutdown_thinint(struct qdio_irq *irq_ptr); +void tiqdio_add_input_queues(struct qdio_irq *irq_ptr); +void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr); +void tiqdio_inbound_processing(unsigned long q); +int tiqdio_allocate_memory(void); +void tiqdio_free_memory(void); +int tiqdio_register_thinints(void); +void tiqdio_unregister_thinints(void); + +/* prototypes for setup */ +void qdio_inbound_processing(unsigned long data); +void qdio_outbound_processing(unsigned long data); +void qdio_outbound_timer(unsigned long data); +void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm, + struct irb *irb); +int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs, + int nr_output_qs); +void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr); +int qdio_setup_irq(struct qdio_initialize *init_data); +void qdio_print_subchannel_info(struct qdio_irq *irq_ptr, + struct ccw_device *cdev); +void qdio_release_memory(struct qdio_irq *irq_ptr); +int qdio_setup_init(void); +void qdio_setup_exit(void); + +#endif /* _CIO_QDIO_H */ diff --git a/drivers/s390/cio/qdio_debug.c b/drivers/s390/cio/qdio_debug.c new file mode 100644 index 000000000000..337aa3087a78 --- /dev/null +++ b/drivers/s390/cio/qdio_debug.c @@ -0,0 +1,240 @@ +/* + * drivers/s390/cio/qdio_debug.c + * + * Copyright IBM Corp. 2008 + * + * Author: Jan Glauber (jang@linux.vnet.ibm.com) + */ +#include +#include +#include +#include +#include +#include "qdio_debug.h" +#include "qdio.h" + +debug_info_t *qdio_dbf_setup; +debug_info_t *qdio_dbf_trace; + +static struct dentry *debugfs_root; +#define MAX_DEBUGFS_QUEUES 32 +static struct dentry *debugfs_queues[MAX_DEBUGFS_QUEUES] = { NULL }; +static DEFINE_MUTEX(debugfs_mutex); + +void qdio_allocate_do_dbf(struct qdio_initialize *init_data) +{ + char dbf_text[20]; + + sprintf(dbf_text, "qfmt:%x", init_data->q_format); + QDIO_DBF_TEXT0(0, setup, dbf_text); + QDIO_DBF_HEX0(0, setup, init_data->adapter_name, 8); + sprintf(dbf_text, "qpff%4x", init_data->qib_param_field_format); + QDIO_DBF_TEXT0(0, setup, dbf_text); + QDIO_DBF_HEX0(0, setup, &init_data->qib_param_field, sizeof(void *)); + QDIO_DBF_HEX0(0, setup, &init_data->input_slib_elements, sizeof(void *)); + QDIO_DBF_HEX0(0, setup, &init_data->output_slib_elements, sizeof(void *)); + sprintf(dbf_text, "niq:%4x", init_data->no_input_qs); + QDIO_DBF_TEXT0(0, setup, dbf_text); + sprintf(dbf_text, "noq:%4x", init_data->no_output_qs); + QDIO_DBF_TEXT0(0, setup, dbf_text); + QDIO_DBF_HEX0(0, setup, &init_data->input_handler, sizeof(void *)); + QDIO_DBF_HEX0(0, setup, &init_data->output_handler, sizeof(void *)); + QDIO_DBF_HEX0(0, setup, &init_data->int_parm, sizeof(long)); + QDIO_DBF_HEX0(0, setup, &init_data->flags, sizeof(long)); + QDIO_DBF_HEX0(0, setup, &init_data->input_sbal_addr_array, sizeof(void *)); + QDIO_DBF_HEX0(0, setup, &init_data->output_sbal_addr_array, sizeof(void *)); +} + +static void qdio_unregister_dbf_views(void) +{ + if (qdio_dbf_setup) + debug_unregister(qdio_dbf_setup); + if (qdio_dbf_trace) + debug_unregister(qdio_dbf_trace); +} + +static int qdio_register_dbf_views(void) +{ + qdio_dbf_setup = debug_register("qdio_setup", QDIO_DBF_SETUP_PAGES, + QDIO_DBF_SETUP_NR_AREAS, + QDIO_DBF_SETUP_LEN); + if (!qdio_dbf_setup) + goto oom; + debug_register_view(qdio_dbf_setup, &debug_hex_ascii_view); + debug_set_level(qdio_dbf_setup, QDIO_DBF_SETUP_LEVEL); + + qdio_dbf_trace = debug_register("qdio_trace", QDIO_DBF_TRACE_PAGES, + QDIO_DBF_TRACE_NR_AREAS, + QDIO_DBF_TRACE_LEN); + if (!qdio_dbf_trace) + goto oom; + debug_register_view(qdio_dbf_trace, &debug_hex_ascii_view); + debug_set_level(qdio_dbf_trace, QDIO_DBF_TRACE_LEVEL); + return 0; +oom: + qdio_unregister_dbf_views(); + return -ENOMEM; +} + +static int qstat_show(struct seq_file *m, void *v) +{ + unsigned char state; + struct qdio_q *q = m->private; + int i; + + if (!q) + return 0; + + seq_printf(m, "device state indicator: %d\n", *q->irq_ptr->dsci); + seq_printf(m, "nr_used: %d\n", atomic_read(&q->nr_buf_used)); + seq_printf(m, "ftc: %d\n", q->first_to_check); + seq_printf(m, "last_move_ftc: %d\n", q->last_move_ftc); + seq_printf(m, "polling: %d\n", q->u.in.polling); + seq_printf(m, "slsb buffer states:\n"); + + qdio_siga_sync_q(q); + for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; i++) { + get_buf_state(q, i, &state); + switch (state) { + case SLSB_P_INPUT_NOT_INIT: + case SLSB_P_OUTPUT_NOT_INIT: + seq_printf(m, "N"); + break; + case SLSB_P_INPUT_PRIMED: + case SLSB_CU_OUTPUT_PRIMED: + seq_printf(m, "+"); + break; + case SLSB_P_INPUT_ACK: + seq_printf(m, "A"); + break; + case SLSB_P_INPUT_ERROR: + case SLSB_P_OUTPUT_ERROR: + seq_printf(m, "x"); + break; + case SLSB_CU_INPUT_EMPTY: + case SLSB_P_OUTPUT_EMPTY: + seq_printf(m, "-"); + break; + case SLSB_P_INPUT_HALTED: + case SLSB_P_OUTPUT_HALTED: + seq_printf(m, "."); + break; + default: + seq_printf(m, "?"); + } + if (i == 63) + seq_printf(m, "\n"); + } + seq_printf(m, "\n"); + return 0; +} + +static ssize_t qstat_seq_write(struct file *file, const char __user *buf, + size_t count, loff_t *off) +{ + struct seq_file *seq = file->private_data; + struct qdio_q *q = seq->private; + + if (!q) + return 0; + + if (q->is_input_q) + xchg(q->irq_ptr->dsci, 1); + local_bh_disable(); + tasklet_schedule(&q->tasklet); + local_bh_enable(); + return count; +} + +static int qstat_seq_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, qstat_show, + filp->f_path.dentry->d_inode->i_private); +} + +static void get_queue_name(struct qdio_q *q, struct ccw_device *cdev, char *name) +{ + memset(name, 0, sizeof(name)); + sprintf(name, "%s", cdev->dev.bus_id); + if (q->is_input_q) + sprintf(name + strlen(name), "_input"); + else + sprintf(name + strlen(name), "_output"); + sprintf(name + strlen(name), "_%d", q->nr); +} + +static void remove_debugfs_entry(struct qdio_q *q) +{ + int i; + + for (i = 0; i < MAX_DEBUGFS_QUEUES; i++) { + if (!debugfs_queues[i]) + continue; + if (debugfs_queues[i]->d_inode->i_private == q) { + debugfs_remove(debugfs_queues[i]); + debugfs_queues[i] = NULL; + } + } +} + +static struct file_operations debugfs_fops = { + .owner = THIS_MODULE, + .open = qstat_seq_open, + .read = seq_read, + .write = qstat_seq_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static void setup_debugfs_entry(struct qdio_q *q, struct ccw_device *cdev) +{ + int i = 0; + char name[40]; + + while (debugfs_queues[i] != NULL) { + i++; + if (i >= MAX_DEBUGFS_QUEUES) + return; + } + get_queue_name(q, cdev, name); + debugfs_queues[i] = debugfs_create_file(name, S_IFREG | S_IRUGO | S_IWUSR, + debugfs_root, q, &debugfs_fops); +} + +void qdio_setup_debug_entries(struct qdio_irq *irq_ptr, struct ccw_device *cdev) +{ + struct qdio_q *q; + int i; + + mutex_lock(&debugfs_mutex); + for_each_input_queue(irq_ptr, q, i) + setup_debugfs_entry(q, cdev); + for_each_output_queue(irq_ptr, q, i) + setup_debugfs_entry(q, cdev); + mutex_unlock(&debugfs_mutex); +} + +void qdio_shutdown_debug_entries(struct qdio_irq *irq_ptr, struct ccw_device *cdev) +{ + struct qdio_q *q; + int i; + + mutex_lock(&debugfs_mutex); + for_each_input_queue(irq_ptr, q, i) + remove_debugfs_entry(q); + for_each_output_queue(irq_ptr, q, i) + remove_debugfs_entry(q); + mutex_unlock(&debugfs_mutex); +} + +int __init qdio_debug_init(void) +{ + debugfs_root = debugfs_create_dir("qdio_queues", NULL); + return qdio_register_dbf_views(); +} + +void qdio_debug_exit(void) +{ + debugfs_remove(debugfs_root); + qdio_unregister_dbf_views(); +} diff --git a/drivers/s390/cio/qdio_debug.h b/drivers/s390/cio/qdio_debug.h new file mode 100644 index 000000000000..8484b83698e1 --- /dev/null +++ b/drivers/s390/cio/qdio_debug.h @@ -0,0 +1,91 @@ +/* + * drivers/s390/cio/qdio_debug.h + * + * Copyright IBM Corp. 2008 + * + * Author: Jan Glauber (jang@linux.vnet.ibm.com) + */ +#ifndef QDIO_DEBUG_H +#define QDIO_DEBUG_H + +#include +#include +#include "qdio.h" + +#define QDIO_DBF_HEX(ex, name, level, addr, len) \ + do { \ + if (ex) \ + debug_exception(qdio_dbf_##name, level, (void *)(addr), len); \ + else \ + debug_event(qdio_dbf_##name, level, (void *)(addr), len); \ + } while (0) +#define QDIO_DBF_TEXT(ex, name, level, text) \ + do { \ + if (ex) \ + debug_text_exception(qdio_dbf_##name, level, text); \ + else \ + debug_text_event(qdio_dbf_##name, level, text); \ + } while (0) + +#define QDIO_DBF_HEX0(ex, name, addr, len) QDIO_DBF_HEX(ex, name, 0, addr, len) +#define QDIO_DBF_HEX1(ex, name, addr, len) QDIO_DBF_HEX(ex, name, 1, addr, len) +#define QDIO_DBF_HEX2(ex, name, addr, len) QDIO_DBF_HEX(ex, name, 2, addr, len) + +#ifdef CONFIG_QDIO_DEBUG +#define QDIO_DBF_HEX3(ex, name, addr, len) QDIO_DBF_HEX(ex, name, 3, addr, len) +#define QDIO_DBF_HEX4(ex, name, addr, len) QDIO_DBF_HEX(ex, name, 4, addr, len) +#define QDIO_DBF_HEX5(ex, name, addr, len) QDIO_DBF_HEX(ex, name, 5, addr, len) +#define QDIO_DBF_HEX6(ex, name, addr, len) QDIO_DBF_HEX(ex, name, 6, addr, len) +#else +#define QDIO_DBF_HEX3(ex, name, addr, len) do {} while (0) +#define QDIO_DBF_HEX4(ex, name, addr, len) do {} while (0) +#define QDIO_DBF_HEX5(ex, name, addr, len) do {} while (0) +#define QDIO_DBF_HEX6(ex, name, addr, len) do {} while (0) +#endif /* CONFIG_QDIO_DEBUG */ + +#define QDIO_DBF_TEXT0(ex, name, text) QDIO_DBF_TEXT(ex, name, 0, text) +#define QDIO_DBF_TEXT1(ex, name, text) QDIO_DBF_TEXT(ex, name, 1, text) +#define QDIO_DBF_TEXT2(ex, name, text) QDIO_DBF_TEXT(ex, name, 2, text) + +#ifdef CONFIG_QDIO_DEBUG +#define QDIO_DBF_TEXT3(ex, name, text) QDIO_DBF_TEXT(ex, name, 3, text) +#define QDIO_DBF_TEXT4(ex, name, text) QDIO_DBF_TEXT(ex, name, 4, text) +#define QDIO_DBF_TEXT5(ex, name, text) QDIO_DBF_TEXT(ex, name, 5, text) +#define QDIO_DBF_TEXT6(ex, name, text) QDIO_DBF_TEXT(ex, name, 6, text) +#else +#define QDIO_DBF_TEXT3(ex, name, text) do {} while (0) +#define QDIO_DBF_TEXT4(ex, name, text) do {} while (0) +#define QDIO_DBF_TEXT5(ex, name, text) do {} while (0) +#define QDIO_DBF_TEXT6(ex, name, text) do {} while (0) +#endif /* CONFIG_QDIO_DEBUG */ + +/* s390dbf views */ +#define QDIO_DBF_SETUP_LEN 8 +#define QDIO_DBF_SETUP_PAGES 4 +#define QDIO_DBF_SETUP_NR_AREAS 1 + +#define QDIO_DBF_TRACE_LEN 8 +#define QDIO_DBF_TRACE_NR_AREAS 2 + +#ifdef CONFIG_QDIO_DEBUG +#define QDIO_DBF_TRACE_PAGES 16 +#define QDIO_DBF_SETUP_LEVEL 6 +#define QDIO_DBF_TRACE_LEVEL 4 +#else /* !CONFIG_QDIO_DEBUG */ +#define QDIO_DBF_TRACE_PAGES 4 +#define QDIO_DBF_SETUP_LEVEL 2 +#define QDIO_DBF_TRACE_LEVEL 2 +#endif /* CONFIG_QDIO_DEBUG */ + +extern debug_info_t *qdio_dbf_setup; +extern debug_info_t *qdio_dbf_trace; + +void qdio_allocate_do_dbf(struct qdio_initialize *init_data); +void debug_print_bstat(struct qdio_q *q); +void qdio_setup_debug_entries(struct qdio_irq *irq_ptr, + struct ccw_device *cdev); +void qdio_shutdown_debug_entries(struct qdio_irq *irq_ptr, + struct ccw_device *cdev); +int qdio_debug_init(void); +void qdio_debug_exit(void); +#endif diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c new file mode 100644 index 000000000000..d10c73cc1688 --- /dev/null +++ b/drivers/s390/cio/qdio_main.c @@ -0,0 +1,1755 @@ +/* + * linux/drivers/s390/cio/qdio_main.c + * + * Linux for s390 qdio support, buffer handling, qdio API and module support. + * + * Copyright 2000,2008 IBM Corp. + * Author(s): Utz Bacher + * Jan Glauber + * 2.6 cio integration by Cornelia Huck + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cio.h" +#include "css.h" +#include "device.h" +#include "qdio.h" +#include "qdio_debug.h" +#include "qdio_perf.h" + +MODULE_AUTHOR("Utz Bacher ,"\ + "Jan Glauber "); +MODULE_DESCRIPTION("QDIO base support"); +MODULE_LICENSE("GPL"); + +static inline int do_siga_sync(struct subchannel_id schid, + unsigned int out_mask, unsigned int in_mask) +{ + register unsigned long __fc asm ("0") = 2; + register struct subchannel_id __schid asm ("1") = schid; + register unsigned long out asm ("2") = out_mask; + register unsigned long in asm ("3") = in_mask; + int cc; + + asm volatile( + " siga 0\n" + " ipm %0\n" + " srl %0,28\n" + : "=d" (cc) + : "d" (__fc), "d" (__schid), "d" (out), "d" (in) : "cc"); + return cc; +} + +static inline int do_siga_input(struct subchannel_id schid, unsigned int mask) +{ + register unsigned long __fc asm ("0") = 1; + register struct subchannel_id __schid asm ("1") = schid; + register unsigned long __mask asm ("2") = mask; + int cc; + + asm volatile( + " siga 0\n" + " ipm %0\n" + " srl %0,28\n" + : "=d" (cc) + : "d" (__fc), "d" (__schid), "d" (__mask) : "cc", "memory"); + return cc; +} + +/** + * do_siga_output - perform SIGA-w/wt function + * @schid: subchannel id or in case of QEBSM the subchannel token + * @mask: which output queues to process + * @bb: busy bit indicator, set only if SIGA-w/wt could not access a buffer + * @fc: function code to perform + * + * Returns cc or QDIO_ERROR_SIGA_ACCESS_EXCEPTION. + * Note: For IQDC unicast queues only the highest priority queue is processed. + */ +static inline int do_siga_output(unsigned long schid, unsigned long mask, + u32 *bb, unsigned int fc) +{ + register unsigned long __fc asm("0") = fc; + register unsigned long __schid asm("1") = schid; + register unsigned long __mask asm("2") = mask; + int cc = QDIO_ERROR_SIGA_ACCESS_EXCEPTION; + + asm volatile( + " siga 0\n" + "0: ipm %0\n" + " srl %0,28\n" + "1:\n" + EX_TABLE(0b, 1b) + : "+d" (cc), "+d" (__fc), "+d" (__schid), "+d" (__mask) + : : "cc", "memory"); + *bb = ((unsigned int) __fc) >> 31; + return cc; +} + +static inline int qdio_check_ccq(struct qdio_q *q, unsigned int ccq) +{ + char dbf_text[15]; + + /* all done or next buffer state different */ + if (ccq == 0 || ccq == 32) + return 0; + /* not all buffers processed */ + if (ccq == 96 || ccq == 97) + return 1; + /* notify devices immediately */ + sprintf(dbf_text, "%d", ccq); + QDIO_DBF_TEXT2(1, trace, dbf_text); + return -EIO; +} + +/** + * qdio_do_eqbs - extract buffer states for QEBSM + * @q: queue to manipulate + * @state: state of the extracted buffers + * @start: buffer number to start at + * @count: count of buffers to examine + * + * Returns the number of successfull extracted equal buffer states. + * Stops processing if a state is different from the last buffers state. + */ +static int qdio_do_eqbs(struct qdio_q *q, unsigned char *state, + int start, int count) +{ + unsigned int ccq = 0; + int tmp_count = count, tmp_start = start; + int nr = q->nr; + int rc; + char dbf_text[15]; + + BUG_ON(!q->irq_ptr->sch_token); + + if (!q->is_input_q) + nr += q->irq_ptr->nr_input_qs; +again: + ccq = do_eqbs(q->irq_ptr->sch_token, state, nr, &tmp_start, &tmp_count); + rc = qdio_check_ccq(q, ccq); + + /* At least one buffer was processed, return and extract the remaining + * buffers later. + */ + if ((ccq == 96) && (count != tmp_count)) + return (count - tmp_count); + if (rc == 1) { + QDIO_DBF_TEXT5(1, trace, "eqAGAIN"); + goto again; + } + + if (rc < 0) { + QDIO_DBF_TEXT2(1, trace, "eqberr"); + sprintf(dbf_text, "%2x,%2x,%d,%d", count, tmp_count, ccq, nr); + QDIO_DBF_TEXT2(1, trace, dbf_text); + q->handler(q->irq_ptr->cdev, + QDIO_ERROR_ACTIVATE_CHECK_CONDITION, + 0, -1, -1, q->irq_ptr->int_parm); + return 0; + } + return count - tmp_count; +} + +/** + * qdio_do_sqbs - set buffer states for QEBSM + * @q: queue to manipulate + * @state: new state of the buffers + * @start: first buffer number to change + * @count: how many buffers to change + * + * Returns the number of successfully changed buffers. + * Does retrying until the specified count of buffer states is set or an + * error occurs. + */ +static int qdio_do_sqbs(struct qdio_q *q, unsigned char state, int start, + int count) +{ + unsigned int ccq = 0; + int tmp_count = count, tmp_start = start; + int nr = q->nr; + int rc; + char dbf_text[15]; + + BUG_ON(!q->irq_ptr->sch_token); + + if (!q->is_input_q) + nr += q->irq_ptr->nr_input_qs; +again: + ccq = do_sqbs(q->irq_ptr->sch_token, state, nr, &tmp_start, &tmp_count); + rc = qdio_check_ccq(q, ccq); + if (rc == 1) { + QDIO_DBF_TEXT5(1, trace, "sqAGAIN"); + goto again; + } + if (rc < 0) { + QDIO_DBF_TEXT3(1, trace, "sqberr"); + sprintf(dbf_text, "%2x,%2x", count, tmp_count); + QDIO_DBF_TEXT3(1, trace, dbf_text); + sprintf(dbf_text, "%d,%d", ccq, nr); + QDIO_DBF_TEXT3(1, trace, dbf_text); + + q->handler(q->irq_ptr->cdev, + QDIO_ERROR_ACTIVATE_CHECK_CONDITION, + 0, -1, -1, q->irq_ptr->int_parm); + return 0; + } + WARN_ON(tmp_count); + return count - tmp_count; +} + +/* returns number of examined buffers and their common state in *state */ +static inline int get_buf_states(struct qdio_q *q, unsigned int bufnr, + unsigned char *state, unsigned int count) +{ + unsigned char __state = 0; + int i; + + BUG_ON(bufnr > QDIO_MAX_BUFFERS_MASK); + BUG_ON(count > QDIO_MAX_BUFFERS_PER_Q); + + if (is_qebsm(q)) + return qdio_do_eqbs(q, state, bufnr, count); + + for (i = 0; i < count; i++) { + if (!__state) + __state = q->slsb.val[bufnr]; + else if (q->slsb.val[bufnr] != __state) + break; + bufnr = next_buf(bufnr); + } + *state = __state; + return i; +} + +inline int get_buf_state(struct qdio_q *q, unsigned int bufnr, + unsigned char *state) +{ + return get_buf_states(q, bufnr, state, 1); +} + +/* wrap-around safe setting of slsb states, returns number of changed buffers */ +static inline int set_buf_states(struct qdio_q *q, int bufnr, + unsigned char state, int count) +{ + int i; + + BUG_ON(bufnr > QDIO_MAX_BUFFERS_MASK); + BUG_ON(count > QDIO_MAX_BUFFERS_PER_Q); + + if (is_qebsm(q)) + return qdio_do_sqbs(q, state, bufnr, count); + + for (i = 0; i < count; i++) { + xchg(&q->slsb.val[bufnr], state); + bufnr = next_buf(bufnr); + } + return count; +} + +static inline int set_buf_state(struct qdio_q *q, int bufnr, + unsigned char state) +{ + return set_buf_states(q, bufnr, state, 1); +} + +/* set slsb states to initial state */ +void qdio_init_buf_states(struct qdio_irq *irq_ptr) +{ + struct qdio_q *q; + int i; + + for_each_input_queue(irq_ptr, q, i) + set_buf_states(q, 0, SLSB_P_INPUT_NOT_INIT, + QDIO_MAX_BUFFERS_PER_Q); + for_each_output_queue(irq_ptr, q, i) + set_buf_states(q, 0, SLSB_P_OUTPUT_NOT_INIT, + QDIO_MAX_BUFFERS_PER_Q); +} + +static int qdio_siga_sync(struct qdio_q *q, unsigned int output, + unsigned int input) +{ + int cc; + + if (!need_siga_sync(q)) + return 0; + + qdio_perf_stat_inc(&perf_stats.siga_sync); + + cc = do_siga_sync(q->irq_ptr->schid, output, input); + if (cc) { + QDIO_DBF_TEXT4(0, trace, "sigasync"); + QDIO_DBF_HEX4(0, trace, &q, sizeof(void *)); + QDIO_DBF_HEX3(0, trace, &cc, sizeof(int *)); + } + return cc; +} + +inline int qdio_siga_sync_q(struct qdio_q *q) +{ + if (q->is_input_q) + return qdio_siga_sync(q, 0, q->mask); + else + return qdio_siga_sync(q, q->mask, 0); +} + +static inline int qdio_siga_sync_out(struct qdio_q *q) +{ + return qdio_siga_sync(q, ~0U, 0); +} + +static inline int qdio_siga_sync_all(struct qdio_q *q) +{ + return qdio_siga_sync(q, ~0U, ~0U); +} + +static inline int qdio_do_siga_output(struct qdio_q *q, unsigned int *busy_bit) +{ + unsigned int fc = 0; + unsigned long schid; + + if (!is_qebsm(q)) + schid = *((u32 *)&q->irq_ptr->schid); + else { + schid = q->irq_ptr->sch_token; + fc |= 0x80; + } + return do_siga_output(schid, q->mask, busy_bit, fc); +} + +static int qdio_siga_output(struct qdio_q *q) +{ + int cc; + u32 busy_bit; + u64 start_time = 0; + + QDIO_DBF_TEXT5(0, trace, "sigaout"); + QDIO_DBF_HEX5(0, trace, &q, sizeof(void *)); + + qdio_perf_stat_inc(&perf_stats.siga_out); +again: + cc = qdio_do_siga_output(q, &busy_bit); + if (queue_type(q) == QDIO_IQDIO_QFMT && cc == 2 && busy_bit) { + if (!start_time) + start_time = get_usecs(); + else if ((get_usecs() - start_time) < QDIO_BUSY_BIT_PATIENCE) + goto again; + } + + if (cc == 2 && busy_bit) + cc |= QDIO_ERROR_SIGA_BUSY; + if (cc) + QDIO_DBF_HEX3(0, trace, &cc, sizeof(int *)); + return cc; +} + +static inline int qdio_siga_input(struct qdio_q *q) +{ + int cc; + + QDIO_DBF_TEXT4(0, trace, "sigain"); + QDIO_DBF_HEX4(0, trace, &q, sizeof(void *)); + + qdio_perf_stat_inc(&perf_stats.siga_in); + + cc = do_siga_input(q->irq_ptr->schid, q->mask); + if (cc) + QDIO_DBF_HEX3(0, trace, &cc, sizeof(int *)); + return cc; +} + +/* called from thinint inbound handler */ +void qdio_sync_after_thinint(struct qdio_q *q) +{ + if (pci_out_supported(q)) { + if (need_siga_sync_thinint(q)) + qdio_siga_sync_all(q); + else if (need_siga_sync_out_thinint(q)) + qdio_siga_sync_out(q); + } else + qdio_siga_sync_q(q); +} + +inline void qdio_stop_polling(struct qdio_q *q) +{ + spin_lock_bh(&q->u.in.lock); + if (!q->u.in.polling) { + spin_unlock_bh(&q->u.in.lock); + return; + } + q->u.in.polling = 0; + qdio_perf_stat_inc(&perf_stats.debug_stop_polling); + + /* show the card that we are not polling anymore */ + set_buf_state(q, q->last_move_ftc, SLSB_P_INPUT_NOT_INIT); + spin_unlock_bh(&q->u.in.lock); +} + +static void announce_buffer_error(struct qdio_q *q) +{ + char dbf_text[15]; + + if (q->is_input_q) + QDIO_DBF_TEXT3(1, trace, "inperr"); + else + QDIO_DBF_TEXT3(0, trace, "outperr"); + + sprintf(dbf_text, "%x-%x-%x", q->first_to_check, + q->sbal[q->first_to_check]->element[14].flags, + q->sbal[q->first_to_check]->element[15].flags); + QDIO_DBF_TEXT3(1, trace, dbf_text); + QDIO_DBF_HEX2(1, trace, q->sbal[q->first_to_check], 256); + + q->qdio_error = QDIO_ERROR_SLSB_STATE; +} + +static int get_inbound_buffer_frontier(struct qdio_q *q) +{ + int count, stop; + unsigned char state; + + /* + * If we still poll don't update last_move_ftc, keep the + * previously ACK buffer there. + */ + if (!q->u.in.polling) + q->last_move_ftc = q->first_to_check; + + /* + * Don't check 128 buffers, as otherwise qdio_inbound_q_moved + * would return 0. + */ + count = min(atomic_read(&q->nr_buf_used), QDIO_MAX_BUFFERS_MASK); + stop = add_buf(q->first_to_check, count); + + /* + * No siga sync here, as a PCI or we after a thin interrupt + * will sync the queues. + */ + + /* need to set count to 1 for non-qebsm */ + if (!is_qebsm(q)) + count = 1; + +check_next: + if (q->first_to_check == stop) + goto out; + + count = get_buf_states(q, q->first_to_check, &state, count); + if (!count) + goto out; + + switch (state) { + case SLSB_P_INPUT_PRIMED: + QDIO_DBF_TEXT5(0, trace, "inptprim"); + + /* + * Only ACK the first buffer. The ACK will be removed in + * qdio_stop_polling. + */ + if (q->u.in.polling) + state = SLSB_P_INPUT_NOT_INIT; + else { + q->u.in.polling = 1; + state = SLSB_P_INPUT_ACK; + } + set_buf_state(q, q->first_to_check, state); + + /* + * Need to change all PRIMED buffers to NOT_INIT, otherwise + * we're loosing initiative in the thinint code. + */ + if (count > 1) + set_buf_states(q, next_buf(q->first_to_check), + SLSB_P_INPUT_NOT_INIT, count - 1); + + /* + * No siga-sync needed for non-qebsm here, as the inbound queue + * will be synced on the next siga-r, resp. + * tiqdio_is_inbound_q_done will do the siga-sync. + */ + q->first_to_check = add_buf(q->first_to_check, count); + atomic_sub(count, &q->nr_buf_used); + goto check_next; + case SLSB_P_INPUT_ERROR: + announce_buffer_error(q); + /* process the buffer, the upper layer will take care of it */ + q->first_to_check = add_buf(q->first_to_check, count); + atomic_sub(count, &q->nr_buf_used); + break; + case SLSB_CU_INPUT_EMPTY: + case SLSB_P_INPUT_NOT_INIT: + case SLSB_P_INPUT_ACK: + QDIO_DBF_TEXT5(0, trace, "inpnipro"); + break; + default: + BUG(); + } +out: + QDIO_DBF_HEX4(0, trace, &q->first_to_check, sizeof(int)); + return q->first_to_check; +} + +int qdio_inbound_q_moved(struct qdio_q *q) +{ + int bufnr; + + bufnr = get_inbound_buffer_frontier(q); + + if ((bufnr != q->last_move_ftc) || q->qdio_error) { + if (!need_siga_sync(q) && !pci_out_supported(q)) + q->u.in.timestamp = get_usecs(); + + QDIO_DBF_TEXT4(0, trace, "inhasmvd"); + QDIO_DBF_HEX4(0, trace, &q, sizeof(void *)); + return 1; + } else + return 0; +} + +static int qdio_inbound_q_done(struct qdio_q *q) +{ + unsigned char state; +#ifdef CONFIG_QDIO_DEBUG + char dbf_text[15]; +#endif + + if (!atomic_read(&q->nr_buf_used)) + return 1; + + /* + * We need that one for synchronization with the adapter, as it + * does a kind of PCI avoidance. + */ + qdio_siga_sync_q(q); + + get_buf_state(q, q->first_to_check, &state); + if (state == SLSB_P_INPUT_PRIMED) + /* we got something to do */ + return 0; + + /* on VM, we don't poll, so the q is always done here */ + if (need_siga_sync(q) || pci_out_supported(q)) + return 1; + + /* + * At this point we know, that inbound first_to_check + * has (probably) not moved (see qdio_inbound_processing). + */ + if (get_usecs() > q->u.in.timestamp + QDIO_INPUT_THRESHOLD) { +#ifdef CONFIG_QDIO_DEBUG + QDIO_DBF_TEXT4(0, trace, "inqisdon"); + QDIO_DBF_HEX4(0, trace, &q, sizeof(void *)); + sprintf(dbf_text, "pf%02x", q->first_to_check); + QDIO_DBF_TEXT4(0, trace, dbf_text); +#endif /* CONFIG_QDIO_DEBUG */ + return 1; + } else { +#ifdef CONFIG_QDIO_DEBUG + QDIO_DBF_TEXT4(0, trace, "inqisntd"); + QDIO_DBF_HEX4(0, trace, &q, sizeof(void *)); + sprintf(dbf_text, "pf%02x", q->first_to_check); + QDIO_DBF_TEXT4(0, trace, dbf_text); +#endif /* CONFIG_QDIO_DEBUG */ + return 0; + } +} + +void qdio_kick_inbound_handler(struct qdio_q *q) +{ + int count, start, end; +#ifdef CONFIG_QDIO_DEBUG + char dbf_text[15]; +#endif + + qdio_perf_stat_inc(&perf_stats.inbound_handler); + + start = q->first_to_kick; + end = q->first_to_check; + if (end >= start) + count = end - start; + else + count = end + QDIO_MAX_BUFFERS_PER_Q - start; + +#ifdef CONFIG_QDIO_DEBUG + sprintf(dbf_text, "s=%2xc=%2x", start, count); + QDIO_DBF_TEXT4(0, trace, dbf_text); +#endif /* CONFIG_QDIO_DEBUG */ + + if (unlikely(q->irq_ptr->state != QDIO_IRQ_STATE_ACTIVE)) + return; + + q->handler(q->irq_ptr->cdev, q->qdio_error, q->nr, + start, count, q->irq_ptr->int_parm); + + /* for the next time */ + q->first_to_kick = q->first_to_check; + q->qdio_error = 0; +} + +static void __qdio_inbound_processing(struct qdio_q *q) +{ + qdio_perf_stat_inc(&perf_stats.tasklet_inbound); +again: + if (!qdio_inbound_q_moved(q)) + return; + + qdio_kick_inbound_handler(q); + + if (!qdio_inbound_q_done(q)) + /* means poll time is not yet over */ + goto again; + + qdio_stop_polling(q); + /* + * We need to check again to not lose initiative after + * resetting the ACK state. + */ + if (!qdio_inbound_q_done(q)) + goto again; +} + +/* inbound tasklet */ +void qdio_inbound_processing(unsigned long data) +{ + struct qdio_q *q = (struct qdio_q *)data; + __qdio_inbound_processing(q); +} + +static int get_outbound_buffer_frontier(struct qdio_q *q) +{ + int count, stop; + unsigned char state; + + if (((queue_type(q) != QDIO_IQDIO_QFMT) && !pci_out_supported(q)) || + (queue_type(q) == QDIO_IQDIO_QFMT && multicast_outbound(q))) + qdio_siga_sync_q(q); + + /* + * Don't check 128 buffers, as otherwise qdio_inbound_q_moved + * would return 0. + */ + count = min(atomic_read(&q->nr_buf_used), QDIO_MAX_BUFFERS_MASK); + stop = add_buf(q->first_to_check, count); + + /* need to set count to 1 for non-qebsm */ + if (!is_qebsm(q)) + count = 1; + +check_next: + if (q->first_to_check == stop) + return q->first_to_check; + + count = get_buf_states(q, q->first_to_check, &state, count); + if (!count) + return q->first_to_check; + + switch (state) { + case SLSB_P_OUTPUT_EMPTY: + /* the adapter got it */ + QDIO_DBF_TEXT5(0, trace, "outpempt"); + + atomic_sub(count, &q->nr_buf_used); + q->first_to_check = add_buf(q->first_to_check, count); + /* + * We fetch all buffer states at once. get_buf_states may + * return count < stop. For QEBSM we do not loop. + */ + if (is_qebsm(q)) + break; + goto check_next; + case SLSB_P_OUTPUT_ERROR: + announce_buffer_error(q); + /* process the buffer, the upper layer will take care of it */ + q->first_to_check = add_buf(q->first_to_check, count); + atomic_sub(count, &q->nr_buf_used); + break; + case SLSB_CU_OUTPUT_PRIMED: + /* the adapter has not fetched the output yet */ + QDIO_DBF_TEXT5(0, trace, "outpprim"); + break; + case SLSB_P_OUTPUT_NOT_INIT: + case SLSB_P_OUTPUT_HALTED: + break; + default: + BUG(); + } + return q->first_to_check; +} + +/* all buffers processed? */ +static inline int qdio_outbound_q_done(struct qdio_q *q) +{ + return atomic_read(&q->nr_buf_used) == 0; +} + +static inline int qdio_outbound_q_moved(struct qdio_q *q) +{ + int bufnr; + + bufnr = get_outbound_buffer_frontier(q); + + if ((bufnr != q->last_move_ftc) || q->qdio_error) { + q->last_move_ftc = bufnr; + QDIO_DBF_TEXT4(0, trace, "oqhasmvd"); + QDIO_DBF_HEX4(0, trace, &q, sizeof(void *)); + return 1; + } else + return 0; +} + +/* + * VM could present us cc=2 and busy bit set on SIGA-write + * during reconfiguration of their Guest LAN (only in iqdio mode, + * otherwise qdio is asynchronous and cc=2 and busy bit there will take + * the queues down immediately). + * + * Therefore qdio_siga_output will try for a short time constantly, + * if such a condition occurs. If it doesn't change, it will + * increase the busy_siga_counter and save the timestamp, and + * schedule the queue for later processing. qdio_outbound_processing + * will check out the counter. If non-zero, it will call qdio_kick_outbound_q + * as often as the value of the counter. This will attempt further SIGA + * instructions. For each successful SIGA, the counter is + * decreased, for failing SIGAs the counter remains the same, after + * all. After some time of no movement, qdio_kick_outbound_q will + * finally fail and reflect corresponding error codes to call + * the upper layer module and have it take the queues down. + * + * Note that this is a change from the original HiperSockets design + * (saying cc=2 and busy bit means take the queues down), but in + * these days Guest LAN didn't exist... excessive cc=2 with busy bit + * conditions will still take the queues down, but the threshold is + * higher due to the Guest LAN environment. + * + * Called from outbound tasklet and do_QDIO handler. + */ +static void qdio_kick_outbound_q(struct qdio_q *q) +{ + int rc; +#ifdef CONFIG_QDIO_DEBUG + char dbf_text[15]; + + QDIO_DBF_TEXT5(0, trace, "kickoutq"); + QDIO_DBF_HEX5(0, trace, &q, sizeof(void *)); +#endif /* CONFIG_QDIO_DEBUG */ + + if (!need_siga_out(q)) + return; + + rc = qdio_siga_output(q); + switch (rc) { + case 0: + /* went smooth this time, reset timestamp */ + q->u.out.timestamp = 0; + + /* TODO: improve error handling for CC=0 case */ +#ifdef CONFIG_QDIO_DEBUG + QDIO_DBF_TEXT3(0, trace, "cc2reslv"); + sprintf(dbf_text, "%4x%2x%2x", q->irq_ptr->schid.sch_no, q->nr, + atomic_read(&q->u.out.busy_siga_counter)); + QDIO_DBF_TEXT3(0, trace, dbf_text); +#endif /* CONFIG_QDIO_DEBUG */ + break; + /* cc=2 and busy bit */ + case (2 | QDIO_ERROR_SIGA_BUSY): + atomic_inc(&q->u.out.busy_siga_counter); + + /* if the last siga was successful, save timestamp here */ + if (!q->u.out.timestamp) + q->u.out.timestamp = get_usecs(); + + /* if we're in time, don't touch qdio_error */ + if (get_usecs() - q->u.out.timestamp < QDIO_BUSY_BIT_GIVE_UP) { + tasklet_schedule(&q->tasklet); + break; + } + QDIO_DBF_TEXT2(0, trace, "cc2REPRT"); +#ifdef CONFIG_QDIO_DEBUG + sprintf(dbf_text, "%4x%2x%2x", q->irq_ptr->schid.sch_no, q->nr, + atomic_read(&q->u.out.busy_siga_counter)); + QDIO_DBF_TEXT3(0, trace, dbf_text); +#endif /* CONFIG_QDIO_DEBUG */ + default: + /* for plain cc=1, 2 or 3 */ + q->qdio_error = rc; + } +} + +static void qdio_kick_outbound_handler(struct qdio_q *q) +{ + int start, end, count; +#ifdef CONFIG_QDIO_DEBUG + char dbf_text[15]; +#endif + + start = q->first_to_kick; + end = q->last_move_ftc; + if (end >= start) + count = end - start; + else + count = end + QDIO_MAX_BUFFERS_PER_Q - start; + +#ifdef CONFIG_QDIO_DEBUG + QDIO_DBF_TEXT4(0, trace, "kickouth"); + QDIO_DBF_HEX4(0, trace, &q, sizeof(void *)); + + sprintf(dbf_text, "s=%2xc=%2x", start, count); + QDIO_DBF_TEXT4(0, trace, dbf_text); +#endif /* CONFIG_QDIO_DEBUG */ + + if (unlikely(q->irq_ptr->state != QDIO_IRQ_STATE_ACTIVE)) + return; + + q->handler(q->irq_ptr->cdev, q->qdio_error, q->nr, start, count, + q->irq_ptr->int_parm); + + /* for the next time: */ + q->first_to_kick = q->last_move_ftc; + q->qdio_error = 0; +} + +static void __qdio_outbound_processing(struct qdio_q *q) +{ + int siga_attempts; + + qdio_perf_stat_inc(&perf_stats.tasklet_outbound); + + /* see comment in qdio_kick_outbound_q */ + siga_attempts = atomic_read(&q->u.out.busy_siga_counter); + while (siga_attempts--) { + atomic_dec(&q->u.out.busy_siga_counter); + qdio_kick_outbound_q(q); + } + + BUG_ON(atomic_read(&q->nr_buf_used) < 0); + + if (qdio_outbound_q_moved(q)) + qdio_kick_outbound_handler(q); + + if (queue_type(q) == QDIO_ZFCP_QFMT) { + if (!pci_out_supported(q) && !qdio_outbound_q_done(q)) + tasklet_schedule(&q->tasklet); + return; + } + + /* bail out for HiperSockets unicast queues */ + if (queue_type(q) == QDIO_IQDIO_QFMT && !multicast_outbound(q)) + return; + + if (q->u.out.pci_out_enabled) + return; + + /* + * Now we know that queue type is either qeth without pci enabled + * or HiperSockets multicast. Make sure buffer switch from PRIMED to + * EMPTY is noticed and outbound_handler is called after some time. + */ + if (qdio_outbound_q_done(q)) + del_timer(&q->u.out.timer); + else { + if (!timer_pending(&q->u.out.timer)) { + mod_timer(&q->u.out.timer, jiffies + 10 * HZ); + qdio_perf_stat_inc(&perf_stats.debug_tl_out_timer); + } + } +} + +/* outbound tasklet */ +void qdio_outbound_processing(unsigned long data) +{ + struct qdio_q *q = (struct qdio_q *)data; + __qdio_outbound_processing(q); +} + +void qdio_outbound_timer(unsigned long data) +{ + struct qdio_q *q = (struct qdio_q *)data; + tasklet_schedule(&q->tasklet); +} + +/* called from thinint inbound tasklet */ +void qdio_check_outbound_after_thinint(struct qdio_q *q) +{ + struct qdio_q *out; + int i; + + if (!pci_out_supported(q)) + return; + + for_each_output_queue(q->irq_ptr, out, i) + if (!qdio_outbound_q_done(out)) + tasklet_schedule(&out->tasklet); +} + +static inline void qdio_set_state(struct qdio_irq *irq_ptr, + enum qdio_irq_states state) +{ +#ifdef CONFIG_QDIO_DEBUG + char dbf_text[15]; + + QDIO_DBF_TEXT5(0, trace, "newstate"); + sprintf(dbf_text, "%4x%4x", irq_ptr->schid.sch_no, state); + QDIO_DBF_TEXT5(0, trace, dbf_text); +#endif /* CONFIG_QDIO_DEBUG */ + + irq_ptr->state = state; + mb(); +} + +static void qdio_irq_check_sense(struct subchannel_id schid, struct irb *irb) +{ + char dbf_text[15]; + + if (irb->esw.esw0.erw.cons) { + sprintf(dbf_text, "sens%4x", schid.sch_no); + QDIO_DBF_TEXT2(1, trace, dbf_text); + QDIO_DBF_HEX0(0, trace, irb, 64); + QDIO_DBF_HEX0(0, trace, irb->ecw, 64); + } +} + +/* PCI interrupt handler */ +static void qdio_int_handler_pci(struct qdio_irq *irq_ptr) +{ + int i; + struct qdio_q *q; + + qdio_perf_stat_inc(&perf_stats.pci_int); + + for_each_input_queue(irq_ptr, q, i) + tasklet_schedule(&q->tasklet); + + if (!(irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)) + return; + + for_each_output_queue(irq_ptr, q, i) { + if (qdio_outbound_q_done(q)) + continue; + + if (!siga_syncs_out_pci(q)) + qdio_siga_sync_q(q); + + tasklet_schedule(&q->tasklet); + } +} + +static void qdio_handle_activate_check(struct ccw_device *cdev, + unsigned long intparm, int cstat, int dstat) +{ + struct qdio_irq *irq_ptr = cdev->private->qdio_data; + struct qdio_q *q; + char dbf_text[15]; + + QDIO_DBF_TEXT2(1, trace, "ick2"); + sprintf(dbf_text, "%s", cdev->dev.bus_id); + QDIO_DBF_TEXT2(1, trace, dbf_text); + QDIO_DBF_HEX2(0, trace, &intparm, sizeof(int)); + QDIO_DBF_HEX2(0, trace, &dstat, sizeof(int)); + QDIO_DBF_HEX2(0, trace, &cstat, sizeof(int)); + + if (irq_ptr->nr_input_qs) { + q = irq_ptr->input_qs[0]; + } else if (irq_ptr->nr_output_qs) { + q = irq_ptr->output_qs[0]; + } else { + dump_stack(); + goto no_handler; + } + q->handler(q->irq_ptr->cdev, QDIO_ERROR_ACTIVATE_CHECK_CONDITION, + 0, -1, -1, irq_ptr->int_parm); +no_handler: + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_STOPPED); +} + +static void qdio_call_shutdown(struct work_struct *work) +{ + struct ccw_device_private *priv; + struct ccw_device *cdev; + + priv = container_of(work, struct ccw_device_private, kick_work); + cdev = priv->cdev; + qdio_shutdown(cdev, QDIO_FLAG_CLEANUP_USING_CLEAR); + put_device(&cdev->dev); +} + +static void qdio_int_error(struct ccw_device *cdev) +{ + struct qdio_irq *irq_ptr = cdev->private->qdio_data; + + switch (irq_ptr->state) { + case QDIO_IRQ_STATE_INACTIVE: + case QDIO_IRQ_STATE_CLEANUP: + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ERR); + break; + case QDIO_IRQ_STATE_ESTABLISHED: + case QDIO_IRQ_STATE_ACTIVE: + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_STOPPED); + if (get_device(&cdev->dev)) { + /* Can't call shutdown from interrupt context. */ + PREPARE_WORK(&cdev->private->kick_work, + qdio_call_shutdown); + queue_work(ccw_device_work, &cdev->private->kick_work); + } + break; + default: + WARN_ON(1); + } + wake_up(&cdev->private->wait_q); +} + +static int qdio_establish_check_errors(struct ccw_device *cdev, int cstat, + int dstat) +{ + struct qdio_irq *irq_ptr = cdev->private->qdio_data; + + if (cstat || (dstat & ~(DEV_STAT_CHN_END | DEV_STAT_DEV_END))) { + QDIO_DBF_TEXT2(1, setup, "eq:ckcon"); + goto error; + } + + if (!(dstat & DEV_STAT_DEV_END)) { + QDIO_DBF_TEXT2(1, setup, "eq:no de"); + goto error; + } + + if (dstat & ~(DEV_STAT_CHN_END | DEV_STAT_DEV_END)) { + QDIO_DBF_TEXT2(1, setup, "eq:badio"); + goto error; + } + return 0; +error: + QDIO_DBF_HEX2(0, trace, &cstat, sizeof(int)); + QDIO_DBF_HEX2(0, trace, &dstat, sizeof(int)); + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ERR); + return 1; +} + +static void qdio_establish_handle_irq(struct ccw_device *cdev, int cstat, + int dstat) +{ + struct qdio_irq *irq_ptr = cdev->private->qdio_data; + char dbf_text[15]; + + sprintf(dbf_text, "qehi%4x", cdev->private->schid.sch_no); + QDIO_DBF_TEXT0(0, setup, dbf_text); + QDIO_DBF_TEXT0(0, trace, dbf_text); + + if (!qdio_establish_check_errors(cdev, cstat, dstat)) + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ESTABLISHED); +} + +/* qdio interrupt handler */ +void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm, + struct irb *irb) +{ + struct qdio_irq *irq_ptr = cdev->private->qdio_data; + int cstat, dstat; + char dbf_text[15]; + + qdio_perf_stat_inc(&perf_stats.qdio_int); + + if (!intparm || !irq_ptr) { + sprintf(dbf_text, "qihd%4x", cdev->private->schid.sch_no); + QDIO_DBF_TEXT2(1, setup, dbf_text); + return; + } + + if (IS_ERR(irb)) { + switch (PTR_ERR(irb)) { + case -EIO: + sprintf(dbf_text, "ierr%4x", + cdev->private->schid.sch_no); + QDIO_DBF_TEXT2(1, setup, dbf_text); + qdio_int_error(cdev); + return; + case -ETIMEDOUT: + sprintf(dbf_text, "qtoh%4x", + cdev->private->schid.sch_no); + QDIO_DBF_TEXT2(1, setup, dbf_text); + qdio_int_error(cdev); + return; + default: + WARN_ON(1); + return; + } + } + qdio_irq_check_sense(irq_ptr->schid, irb); + + cstat = irb->scsw.cmd.cstat; + dstat = irb->scsw.cmd.dstat; + + switch (irq_ptr->state) { + case QDIO_IRQ_STATE_INACTIVE: + qdio_establish_handle_irq(cdev, cstat, dstat); + break; + + case QDIO_IRQ_STATE_CLEANUP: + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_INACTIVE); + break; + + case QDIO_IRQ_STATE_ESTABLISHED: + case QDIO_IRQ_STATE_ACTIVE: + if (cstat & SCHN_STAT_PCI) { + qdio_int_handler_pci(irq_ptr); + /* no state change so no need to wake up wait_q */ + return; + } + if ((cstat & ~SCHN_STAT_PCI) || dstat) { + qdio_handle_activate_check(cdev, intparm, cstat, + dstat); + break; + } + default: + WARN_ON(1); + } + wake_up(&cdev->private->wait_q); +} + +/** + * qdio_get_ssqd_desc - get qdio subchannel description + * @cdev: ccw device to get description for + * + * Returns a pointer to the saved qdio subchannel description, + * or NULL for not setup qdio devices. + */ +struct qdio_ssqd_desc *qdio_get_ssqd_desc(struct ccw_device *cdev) +{ + struct qdio_irq *irq_ptr; + + QDIO_DBF_TEXT0(0, setup, "getssqd"); + + irq_ptr = cdev->private->qdio_data; + if (!irq_ptr) + return NULL; + + return &irq_ptr->ssqd_desc; +} +EXPORT_SYMBOL_GPL(qdio_get_ssqd_desc); + +/** + * qdio_cleanup - shutdown queues and free data structures + * @cdev: associated ccw device + * @how: use halt or clear to shutdown + * + * This function calls qdio_shutdown() for @cdev with method @how + * and on success qdio_free() for @cdev. + */ +int qdio_cleanup(struct ccw_device *cdev, int how) +{ + struct qdio_irq *irq_ptr; + char dbf_text[15]; + int rc; + + irq_ptr = cdev->private->qdio_data; + if (!irq_ptr) + return -ENODEV; + + sprintf(dbf_text, "qcln%4x", irq_ptr->schid.sch_no); + QDIO_DBF_TEXT1(0, trace, dbf_text); + QDIO_DBF_TEXT0(0, setup, dbf_text); + + rc = qdio_shutdown(cdev, how); + if (rc == 0) + rc = qdio_free(cdev); + return rc; +} +EXPORT_SYMBOL_GPL(qdio_cleanup); + +static void qdio_shutdown_queues(struct ccw_device *cdev) +{ + struct qdio_irq *irq_ptr = cdev->private->qdio_data; + struct qdio_q *q; + int i; + + for_each_input_queue(irq_ptr, q, i) + tasklet_disable(&q->tasklet); + + for_each_output_queue(irq_ptr, q, i) { + tasklet_disable(&q->tasklet); + del_timer(&q->u.out.timer); + } +} + +/** + * qdio_shutdown - shut down a qdio subchannel + * @cdev: associated ccw device + * @how: use halt or clear to shutdown + */ +int qdio_shutdown(struct ccw_device *cdev, int how) +{ + struct qdio_irq *irq_ptr; + int rc; + unsigned long flags; + char dbf_text[15]; + + irq_ptr = cdev->private->qdio_data; + if (!irq_ptr) + return -ENODEV; + + mutex_lock(&irq_ptr->setup_mutex); + /* + * Subchannel was already shot down. We cannot prevent being called + * twice since cio may trigger a shutdown asynchronously. + */ + if (irq_ptr->state == QDIO_IRQ_STATE_INACTIVE) { + mutex_unlock(&irq_ptr->setup_mutex); + return 0; + } + + sprintf(dbf_text, "qsqs%4x", irq_ptr->schid.sch_no); + QDIO_DBF_TEXT1(0, trace, dbf_text); + QDIO_DBF_TEXT0(0, setup, dbf_text); + + tiqdio_remove_input_queues(irq_ptr); + qdio_shutdown_queues(cdev); + qdio_shutdown_debug_entries(irq_ptr, cdev); + + /* cleanup subchannel */ + spin_lock_irqsave(get_ccwdev_lock(cdev), flags); + + if (how & QDIO_FLAG_CLEANUP_USING_CLEAR) + rc = ccw_device_clear(cdev, QDIO_DOING_CLEANUP); + else + /* default behaviour is halt */ + rc = ccw_device_halt(cdev, QDIO_DOING_CLEANUP); + if (rc) { + sprintf(dbf_text, "sher%4x", irq_ptr->schid.sch_no); + QDIO_DBF_TEXT0(0, setup, dbf_text); + sprintf(dbf_text, "rc=%d", rc); + QDIO_DBF_TEXT0(0, setup, dbf_text); + goto no_cleanup; + } + + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_CLEANUP); + spin_unlock_irqrestore(get_ccwdev_lock(cdev), flags); + wait_event_interruptible_timeout(cdev->private->wait_q, + irq_ptr->state == QDIO_IRQ_STATE_INACTIVE || + irq_ptr->state == QDIO_IRQ_STATE_ERR, + 10 * HZ); + spin_lock_irqsave(get_ccwdev_lock(cdev), flags); + +no_cleanup: + qdio_shutdown_thinint(irq_ptr); + + /* restore interrupt handler */ + if ((void *)cdev->handler == (void *)qdio_int_handler) + cdev->handler = irq_ptr->orig_handler; + spin_unlock_irqrestore(get_ccwdev_lock(cdev), flags); + + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_INACTIVE); + mutex_unlock(&irq_ptr->setup_mutex); + module_put(THIS_MODULE); + if (rc) + return rc; + return 0; +} +EXPORT_SYMBOL_GPL(qdio_shutdown); + +/** + * qdio_free - free data structures for a qdio subchannel + * @cdev: associated ccw device + */ +int qdio_free(struct ccw_device *cdev) +{ + struct qdio_irq *irq_ptr; + char dbf_text[15]; + + irq_ptr = cdev->private->qdio_data; + if (!irq_ptr) + return -ENODEV; + + mutex_lock(&irq_ptr->setup_mutex); + + sprintf(dbf_text, "qfqs%4x", irq_ptr->schid.sch_no); + QDIO_DBF_TEXT1(0, trace, dbf_text); + QDIO_DBF_TEXT0(0, setup, dbf_text); + + cdev->private->qdio_data = NULL; + mutex_unlock(&irq_ptr->setup_mutex); + + qdio_release_memory(irq_ptr); + return 0; +} +EXPORT_SYMBOL_GPL(qdio_free); + +/** + * qdio_initialize - allocate and establish queues for a qdio subchannel + * @init_data: initialization data + * + * This function first allocates queues via qdio_allocate() and on success + * establishes them via qdio_establish(). + */ +int qdio_initialize(struct qdio_initialize *init_data) +{ + int rc; + char dbf_text[15]; + + sprintf(dbf_text, "qini%4x", init_data->cdev->private->schid.sch_no); + QDIO_DBF_TEXT0(0, setup, dbf_text); + QDIO_DBF_TEXT0(0, trace, dbf_text); + + rc = qdio_allocate(init_data); + if (rc) + return rc; + + rc = qdio_establish(init_data); + if (rc) + qdio_free(init_data->cdev); + return rc; +} +EXPORT_SYMBOL_GPL(qdio_initialize); + +/** + * qdio_allocate - allocate qdio queues and associated data + * @init_data: initialization data + */ +int qdio_allocate(struct qdio_initialize *init_data) +{ + struct qdio_irq *irq_ptr; + char dbf_text[15]; + + sprintf(dbf_text, "qalc%4x", init_data->cdev->private->schid.sch_no); + QDIO_DBF_TEXT0(0, setup, dbf_text); + QDIO_DBF_TEXT0(0, trace, dbf_text); + + if ((init_data->no_input_qs && !init_data->input_handler) || + (init_data->no_output_qs && !init_data->output_handler)) + return -EINVAL; + + if ((init_data->no_input_qs > QDIO_MAX_QUEUES_PER_IRQ) || + (init_data->no_output_qs > QDIO_MAX_QUEUES_PER_IRQ)) + return -EINVAL; + + if ((!init_data->input_sbal_addr_array) || + (!init_data->output_sbal_addr_array)) + return -EINVAL; + + qdio_allocate_do_dbf(init_data); + + /* irq_ptr must be in GFP_DMA since it contains ccw1.cda */ + irq_ptr = (void *) get_zeroed_page(GFP_KERNEL | GFP_DMA); + if (!irq_ptr) + goto out_err; + QDIO_DBF_TEXT0(0, setup, "irq_ptr:"); + QDIO_DBF_HEX0(0, setup, &irq_ptr, sizeof(void *)); + + mutex_init(&irq_ptr->setup_mutex); + + /* + * Allocate a page for the chsc calls in qdio_establish. + * Must be pre-allocated since a zfcp recovery will call + * qdio_establish. In case of low memory and swap on a zfcp disk + * we may not be able to allocate memory otherwise. + */ + irq_ptr->chsc_page = get_zeroed_page(GFP_KERNEL); + if (!irq_ptr->chsc_page) + goto out_rel; + + /* qdr is used in ccw1.cda which is u32 */ + irq_ptr->qdr = kzalloc(sizeof(struct qdr), GFP_KERNEL | GFP_DMA); + if (!irq_ptr->qdr) + goto out_rel; + WARN_ON((unsigned long)irq_ptr->qdr & 0xfff); + + QDIO_DBF_TEXT0(0, setup, "qdr:"); + QDIO_DBF_HEX0(0, setup, &irq_ptr->qdr, sizeof(void *)); + + if (qdio_allocate_qs(irq_ptr, init_data->no_input_qs, + init_data->no_output_qs)) + goto out_rel; + + init_data->cdev->private->qdio_data = irq_ptr; + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_INACTIVE); + return 0; +out_rel: + qdio_release_memory(irq_ptr); +out_err: + return -ENOMEM; +} +EXPORT_SYMBOL_GPL(qdio_allocate); + +/** + * qdio_establish - establish queues on a qdio subchannel + * @init_data: initialization data + */ +int qdio_establish(struct qdio_initialize *init_data) +{ + char dbf_text[20]; + struct qdio_irq *irq_ptr; + struct ccw_device *cdev = init_data->cdev; + unsigned long saveflags; + int rc; + + irq_ptr = cdev->private->qdio_data; + if (!irq_ptr) + return -ENODEV; + + if (cdev->private->state != DEV_STATE_ONLINE) + return -EINVAL; + + if (!try_module_get(THIS_MODULE)) + return -EINVAL; + + sprintf(dbf_text, "qest%4x", cdev->private->schid.sch_no); + QDIO_DBF_TEXT0(0, setup, dbf_text); + QDIO_DBF_TEXT0(0, trace, dbf_text); + + mutex_lock(&irq_ptr->setup_mutex); + qdio_setup_irq(init_data); + + rc = qdio_establish_thinint(irq_ptr); + if (rc) { + mutex_unlock(&irq_ptr->setup_mutex); + qdio_shutdown(cdev, QDIO_FLAG_CLEANUP_USING_CLEAR); + return rc; + } + + /* establish q */ + irq_ptr->ccw.cmd_code = irq_ptr->equeue.cmd; + irq_ptr->ccw.flags = CCW_FLAG_SLI; + irq_ptr->ccw.count = irq_ptr->equeue.count; + irq_ptr->ccw.cda = (u32)((addr_t)irq_ptr->qdr); + + spin_lock_irqsave(get_ccwdev_lock(cdev), saveflags); + ccw_device_set_options_mask(cdev, 0); + + rc = ccw_device_start(cdev, &irq_ptr->ccw, QDIO_DOING_ESTABLISH, 0, 0); + if (rc) { + sprintf(dbf_text, "eq:io%4x", irq_ptr->schid.sch_no); + QDIO_DBF_TEXT2(1, setup, dbf_text); + sprintf(dbf_text, "eq:rc%4x", rc); + QDIO_DBF_TEXT2(1, setup, dbf_text); + } + spin_unlock_irqrestore(get_ccwdev_lock(cdev), saveflags); + + if (rc) { + mutex_unlock(&irq_ptr->setup_mutex); + qdio_shutdown(cdev, QDIO_FLAG_CLEANUP_USING_CLEAR); + return rc; + } + + wait_event_interruptible_timeout(cdev->private->wait_q, + irq_ptr->state == QDIO_IRQ_STATE_ESTABLISHED || + irq_ptr->state == QDIO_IRQ_STATE_ERR, HZ); + + if (irq_ptr->state != QDIO_IRQ_STATE_ESTABLISHED) { + mutex_unlock(&irq_ptr->setup_mutex); + qdio_shutdown(cdev, QDIO_FLAG_CLEANUP_USING_CLEAR); + return -EIO; + } + + qdio_setup_ssqd_info(irq_ptr); + sprintf(dbf_text, "qib ac%2x", irq_ptr->qib.ac); + QDIO_DBF_TEXT2(0, setup, dbf_text); + + /* qebsm is now setup if available, initialize buffer states */ + qdio_init_buf_states(irq_ptr); + + mutex_unlock(&irq_ptr->setup_mutex); + qdio_print_subchannel_info(irq_ptr, cdev); + qdio_setup_debug_entries(irq_ptr, cdev); + return 0; +} +EXPORT_SYMBOL_GPL(qdio_establish); + +/** + * qdio_activate - activate queues on a qdio subchannel + * @cdev: associated cdev + */ +int qdio_activate(struct ccw_device *cdev) +{ + struct qdio_irq *irq_ptr; + int rc; + unsigned long saveflags; + char dbf_text[20]; + + irq_ptr = cdev->private->qdio_data; + if (!irq_ptr) + return -ENODEV; + + if (cdev->private->state != DEV_STATE_ONLINE) + return -EINVAL; + + mutex_lock(&irq_ptr->setup_mutex); + if (irq_ptr->state == QDIO_IRQ_STATE_INACTIVE) { + rc = -EBUSY; + goto out; + } + + sprintf(dbf_text, "qact%4x", irq_ptr->schid.sch_no); + QDIO_DBF_TEXT2(0, setup, dbf_text); + QDIO_DBF_TEXT2(0, trace, dbf_text); + + irq_ptr->ccw.cmd_code = irq_ptr->aqueue.cmd; + irq_ptr->ccw.flags = CCW_FLAG_SLI; + irq_ptr->ccw.count = irq_ptr->aqueue.count; + irq_ptr->ccw.cda = 0; + + spin_lock_irqsave(get_ccwdev_lock(cdev), saveflags); + ccw_device_set_options(cdev, CCWDEV_REPORT_ALL); + + rc = ccw_device_start(cdev, &irq_ptr->ccw, QDIO_DOING_ACTIVATE, + 0, DOIO_DENY_PREFETCH); + if (rc) { + sprintf(dbf_text, "aq:io%4x", irq_ptr->schid.sch_no); + QDIO_DBF_TEXT2(1, setup, dbf_text); + sprintf(dbf_text, "aq:rc%4x", rc); + QDIO_DBF_TEXT2(1, setup, dbf_text); + } + spin_unlock_irqrestore(get_ccwdev_lock(cdev), saveflags); + + if (rc) + goto out; + + if (is_thinint_irq(irq_ptr)) + tiqdio_add_input_queues(irq_ptr); + + /* wait for subchannel to become active */ + msleep(5); + + switch (irq_ptr->state) { + case QDIO_IRQ_STATE_STOPPED: + case QDIO_IRQ_STATE_ERR: + mutex_unlock(&irq_ptr->setup_mutex); + qdio_shutdown(cdev, QDIO_FLAG_CLEANUP_USING_CLEAR); + return -EIO; + default: + qdio_set_state(irq_ptr, QDIO_IRQ_STATE_ACTIVE); + rc = 0; + } +out: + mutex_unlock(&irq_ptr->setup_mutex); + return rc; +} +EXPORT_SYMBOL_GPL(qdio_activate); + +static inline int buf_in_between(int bufnr, int start, int count) +{ + int end = add_buf(start, count); + + if (end > start) { + if (bufnr >= start && bufnr < end) + return 1; + else + return 0; + } + + /* wrap-around case */ + if ((bufnr >= start && bufnr <= QDIO_MAX_BUFFERS_PER_Q) || + (bufnr < end)) + return 1; + else + return 0; +} + +/** + * handle_inbound - reset processed input buffers + * @q: queue containing the buffers + * @callflags: flags + * @bufnr: first buffer to process + * @count: how many buffers are emptied + */ +static void handle_inbound(struct qdio_q *q, unsigned int callflags, + int bufnr, int count) +{ + unsigned long flags; + int used, rc; + + /* + * do_QDIO could run in parallel with the queue tasklet so the + * upper-layer programm could empty the ACK'ed buffer here. + * If that happens we must clear the polling flag, otherwise + * qdio_stop_polling() could set the buffer to NOT_INIT after + * it was set to EMPTY which would kill us. + */ + spin_lock_irqsave(&q->u.in.lock, flags); + if (q->u.in.polling) + if (buf_in_between(q->last_move_ftc, bufnr, count)) + q->u.in.polling = 0; + + count = set_buf_states(q, bufnr, SLSB_CU_INPUT_EMPTY, count); + spin_unlock_irqrestore(&q->u.in.lock, flags); + + used = atomic_add_return(count, &q->nr_buf_used) - count; + BUG_ON(used + count > QDIO_MAX_BUFFERS_PER_Q); + + /* no need to signal as long as the adapter had free buffers */ + if (used) + return; + + if (need_siga_in(q)) { + rc = qdio_siga_input(q); + if (rc) + q->qdio_error = rc; + } +} + +/** + * handle_outbound - process filled outbound buffers + * @q: queue containing the buffers + * @callflags: flags + * @bufnr: first buffer to process + * @count: how many buffers are filled + */ +static void handle_outbound(struct qdio_q *q, unsigned int callflags, + int bufnr, int count) +{ + unsigned char state; + int used; + + qdio_perf_stat_inc(&perf_stats.outbound_handler); + + count = set_buf_states(q, bufnr, SLSB_CU_OUTPUT_PRIMED, count); + used = atomic_add_return(count, &q->nr_buf_used); + BUG_ON(used > QDIO_MAX_BUFFERS_PER_Q); + + if (callflags & QDIO_FLAG_PCI_OUT) + q->u.out.pci_out_enabled = 1; + else + q->u.out.pci_out_enabled = 0; + + if (queue_type(q) == QDIO_IQDIO_QFMT) { + if (multicast_outbound(q)) + qdio_kick_outbound_q(q); + else + /* + * One siga-w per buffer required for unicast + * HiperSockets. + */ + while (count--) + qdio_kick_outbound_q(q); + goto out; + } + + if (need_siga_sync(q)) { + qdio_siga_sync_q(q); + goto out; + } + + /* try to fast requeue buffers */ + get_buf_state(q, prev_buf(bufnr), &state); + if (state != SLSB_CU_OUTPUT_PRIMED) + qdio_kick_outbound_q(q); + else { + QDIO_DBF_TEXT5(0, trace, "fast-req"); + qdio_perf_stat_inc(&perf_stats.fast_requeue); + } +out: + /* Fixme: could wait forever if called from process context */ + tasklet_schedule(&q->tasklet); +} + +/** + * do_QDIO - process input or output buffers + * @cdev: associated ccw_device for the qdio subchannel + * @callflags: input or output and special flags from the program + * @q_nr: queue number + * @bufnr: buffer number + * @count: how many buffers to process + */ +int do_QDIO(struct ccw_device *cdev, unsigned int callflags, + int q_nr, int bufnr, int count) +{ + struct qdio_irq *irq_ptr; +#ifdef CONFIG_QDIO_DEBUG + char dbf_text[20]; + + sprintf(dbf_text, "doQD%04x", cdev->private->schid.sch_no); + QDIO_DBF_TEXT3(0, trace, dbf_text); +#endif /* CONFIG_QDIO_DEBUG */ + + if ((bufnr > QDIO_MAX_BUFFERS_PER_Q) || + (count > QDIO_MAX_BUFFERS_PER_Q) || + (q_nr > QDIO_MAX_QUEUES_PER_IRQ)) + return -EINVAL; + + if (!count) + return 0; + + irq_ptr = cdev->private->qdio_data; + if (!irq_ptr) + return -ENODEV; + +#ifdef CONFIG_QDIO_DEBUG + if (callflags & QDIO_FLAG_SYNC_INPUT) + QDIO_DBF_HEX3(0, trace, &irq_ptr->input_qs[q_nr], + sizeof(void *)); + else + QDIO_DBF_HEX3(0, trace, &irq_ptr->output_qs[q_nr], + sizeof(void *)); + + sprintf(dbf_text, "flag%04x", callflags); + QDIO_DBF_TEXT3(0, trace, dbf_text); + sprintf(dbf_text, "qi%02xct%02x", bufnr, count); + QDIO_DBF_TEXT3(0, trace, dbf_text); +#endif /* CONFIG_QDIO_DEBUG */ + + if (irq_ptr->state != QDIO_IRQ_STATE_ACTIVE) + return -EBUSY; + + if (callflags & QDIO_FLAG_SYNC_INPUT) + handle_inbound(irq_ptr->input_qs[q_nr], + callflags, bufnr, count); + else if (callflags & QDIO_FLAG_SYNC_OUTPUT) + handle_outbound(irq_ptr->output_qs[q_nr], + callflags, bufnr, count); + else { + QDIO_DBF_TEXT3(1, trace, "doQD:inv"); + return -EINVAL; + } + return 0; +} +EXPORT_SYMBOL_GPL(do_QDIO); + +static int __init init_QDIO(void) +{ + int rc; + + rc = qdio_setup_init(); + if (rc) + return rc; + rc = tiqdio_allocate_memory(); + if (rc) + goto out_cache; + rc = qdio_debug_init(); + if (rc) + goto out_ti; + rc = qdio_setup_perf_stats(); + if (rc) + goto out_debug; + rc = tiqdio_register_thinints(); + if (rc) + goto out_perf; + return 0; + +out_perf: + qdio_remove_perf_stats(); +out_debug: + qdio_debug_exit(); +out_ti: + tiqdio_free_memory(); +out_cache: + qdio_setup_exit(); + return rc; +} + +static void __exit exit_QDIO(void) +{ + tiqdio_unregister_thinints(); + tiqdio_free_memory(); + qdio_remove_perf_stats(); + qdio_debug_exit(); + qdio_setup_exit(); +} + +module_init(init_QDIO); +module_exit(exit_QDIO); diff --git a/drivers/s390/cio/qdio_perf.c b/drivers/s390/cio/qdio_perf.c new file mode 100644 index 000000000000..ea01b85b1cc9 --- /dev/null +++ b/drivers/s390/cio/qdio_perf.c @@ -0,0 +1,151 @@ +/* + * drivers/s390/cio/qdio_perf.c + * + * Copyright IBM Corp. 2008 + * + * Author: Jan Glauber (jang@linux.vnet.ibm.com) + */ +#include +#include +#include +#include + +#include "cio.h" +#include "css.h" +#include "device.h" +#include "ioasm.h" +#include "chsc.h" +#include "qdio_debug.h" +#include "qdio_perf.h" + +int qdio_performance_stats; +struct qdio_perf_stats perf_stats; + +#ifdef CONFIG_PROC_FS +static struct proc_dir_entry *qdio_perf_pde; +#endif + +inline void qdio_perf_stat_inc(atomic_long_t *count) +{ + if (qdio_performance_stats) + atomic_long_inc(count); +} + +inline void qdio_perf_stat_dec(atomic_long_t *count) +{ + if (qdio_performance_stats) + atomic_long_dec(count); +} + +/* + * procfs functions + */ +static int qdio_perf_proc_show(struct seq_file *m, void *v) +{ + seq_printf(m, "Number of qdio interrupts\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.qdio_int)); + seq_printf(m, "Number of PCI interrupts\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.pci_int)); + seq_printf(m, "Number of adapter interrupts\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.thin_int)); + seq_printf(m, "\n"); + seq_printf(m, "Inbound tasklet runs\t\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.tasklet_inbound)); + seq_printf(m, "Outbound tasklet runs\t\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.tasklet_outbound)); + seq_printf(m, "Adapter interrupt tasklet runs/loops\t\t: %li/%li\n", + (long)atomic_long_read(&perf_stats.tasklet_thinint), + (long)atomic_long_read(&perf_stats.tasklet_thinint_loop)); + seq_printf(m, "Adapter interrupt inbound tasklet runs/loops\t: %li/%li\n", + (long)atomic_long_read(&perf_stats.thinint_inbound), + (long)atomic_long_read(&perf_stats.thinint_inbound_loop)); + seq_printf(m, "\n"); + seq_printf(m, "Number of SIGA In issued\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.siga_in)); + seq_printf(m, "Number of SIGA Out issued\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.siga_out)); + seq_printf(m, "Number of SIGA Sync issued\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.siga_sync)); + seq_printf(m, "\n"); + seq_printf(m, "Number of inbound transfers\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.inbound_handler)); + seq_printf(m, "Number of outbound transfers\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.outbound_handler)); + seq_printf(m, "\n"); + seq_printf(m, "Number of fast requeues (outg. SBAL w/o SIGA)\t: %li\n", + (long)atomic_long_read(&perf_stats.fast_requeue)); + seq_printf(m, "Number of outbound tasklet mod_timer calls\t: %li\n", + (long)atomic_long_read(&perf_stats.debug_tl_out_timer)); + seq_printf(m, "Number of stop polling calls\t\t\t: %li\n", + (long)atomic_long_read(&perf_stats.debug_stop_polling)); + seq_printf(m, "AI inbound tasklet loops after stop polling\t: %li\n", + (long)atomic_long_read(&perf_stats.thinint_inbound_loop2)); + seq_printf(m, "\n"); + return 0; +} +static int qdio_perf_seq_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, qdio_perf_proc_show, NULL); +} + +static struct file_operations qdio_perf_proc_fops = { + .owner = THIS_MODULE, + .open = qdio_perf_seq_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +/* + * sysfs functions + */ +static ssize_t qdio_perf_stats_show(struct bus_type *bus, char *buf) +{ + return sprintf(buf, "%i\n", qdio_performance_stats ? 1 : 0); +} + +static ssize_t qdio_perf_stats_store(struct bus_type *bus, + const char *buf, size_t count) +{ + unsigned long i; + + if (strict_strtoul(buf, 16, &i) != 0) + return -EINVAL; + if ((i != 0) && (i != 1)) + return -EINVAL; + if (i == qdio_performance_stats) + return count; + + qdio_performance_stats = i; + /* reset performance statistics */ + if (i == 0) + memset(&perf_stats, 0, sizeof(struct qdio_perf_stats)); + return count; +} + +static BUS_ATTR(qdio_performance_stats, 0644, qdio_perf_stats_show, + qdio_perf_stats_store); + +int __init qdio_setup_perf_stats(void) +{ + int rc; + + rc = bus_create_file(&ccw_bus_type, &bus_attr_qdio_performance_stats); + if (rc) + return rc; + +#ifdef CONFIG_PROC_FS + memset(&perf_stats, 0, sizeof(struct qdio_perf_stats)); + qdio_perf_pde = proc_create("qdio_perf", S_IFREG | S_IRUGO, + NULL, &qdio_perf_proc_fops); +#endif + return 0; +} + +void __exit qdio_remove_perf_stats(void) +{ +#ifdef CONFIG_PROC_FS + remove_proc_entry("qdio_perf", NULL); +#endif + bus_remove_file(&ccw_bus_type, &bus_attr_qdio_performance_stats); +} diff --git a/drivers/s390/cio/qdio_perf.h b/drivers/s390/cio/qdio_perf.h new file mode 100644 index 000000000000..5c406a8b7387 --- /dev/null +++ b/drivers/s390/cio/qdio_perf.h @@ -0,0 +1,54 @@ +/* + * drivers/s390/cio/qdio_perf.h + * + * Copyright IBM Corp. 2008 + * + * Author: Jan Glauber (jang@linux.vnet.ibm.com) + */ +#ifndef QDIO_PERF_H +#define QDIO_PERF_H + +#include +#include +#include + +struct qdio_perf_stats { + /* interrupt handler calls */ + atomic_long_t qdio_int; + atomic_long_t pci_int; + atomic_long_t thin_int; + + /* tasklet runs */ + atomic_long_t tasklet_inbound; + atomic_long_t tasklet_outbound; + atomic_long_t tasklet_thinint; + atomic_long_t tasklet_thinint_loop; + atomic_long_t thinint_inbound; + atomic_long_t thinint_inbound_loop; + atomic_long_t thinint_inbound_loop2; + + /* signal adapter calls */ + atomic_long_t siga_out; + atomic_long_t siga_in; + atomic_long_t siga_sync; + + /* misc */ + atomic_long_t inbound_handler; + atomic_long_t outbound_handler; + atomic_long_t fast_requeue; + + /* for debugging */ + atomic_long_t debug_tl_out_timer; + atomic_long_t debug_stop_polling; +}; + +extern struct qdio_perf_stats perf_stats; +extern int qdio_performance_stats; + +int qdio_setup_perf_stats(void); +void qdio_remove_perf_stats(void); + +extern void qdio_perf_stat_inc(atomic_long_t *count); +extern void qdio_perf_stat_dec(atomic_long_t *count); + +#endif diff --git a/drivers/s390/cio/qdio_setup.c b/drivers/s390/cio/qdio_setup.c new file mode 100644 index 000000000000..f0923a8aceda --- /dev/null +++ b/drivers/s390/cio/qdio_setup.c @@ -0,0 +1,521 @@ +/* + * driver/s390/cio/qdio_setup.c + * + * qdio queue initialization + * + * Copyright (C) IBM Corp. 2008 + * Author(s): Jan Glauber + */ +#include +#include +#include + +#include "cio.h" +#include "css.h" +#include "device.h" +#include "ioasm.h" +#include "chsc.h" +#include "qdio.h" +#include "qdio_debug.h" + +static struct kmem_cache *qdio_q_cache; + +/* + * qebsm is only available under 64bit but the adapter sets the feature + * flag anyway, so we manually override it. + */ +static inline int qebsm_possible(void) +{ +#ifdef CONFIG_64BIT + return css_general_characteristics.qebsm; +#endif + return 0; +} + +/* + * qib_param_field: pointer to 128 bytes or NULL, if no param field + * nr_input_qs: pointer to nr_queues*128 words of data or NULL + */ +static void set_impl_params(struct qdio_irq *irq_ptr, + unsigned int qib_param_field_format, + unsigned char *qib_param_field, + unsigned long *input_slib_elements, + unsigned long *output_slib_elements) +{ + struct qdio_q *q; + int i, j; + + if (!irq_ptr) + return; + + WARN_ON((unsigned long)&irq_ptr->qib & 0xff); + irq_ptr->qib.pfmt = qib_param_field_format; + if (qib_param_field) + memcpy(irq_ptr->qib.parm, qib_param_field, + QDIO_MAX_BUFFERS_PER_Q); + + if (!input_slib_elements) + goto output; + + for_each_input_queue(irq_ptr, q, i) { + for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++) + q->slib->slibe[j].parms = + input_slib_elements[i * QDIO_MAX_BUFFERS_PER_Q + j]; + } +output: + if (!output_slib_elements) + return; + + for_each_output_queue(irq_ptr, q, i) { + for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++) + q->slib->slibe[j].parms = + output_slib_elements[i * QDIO_MAX_BUFFERS_PER_Q + j]; + } +} + +static int __qdio_allocate_qs(struct qdio_q **irq_ptr_qs, int nr_queues) +{ + struct qdio_q *q; + int i; + + for (i = 0; i < nr_queues; i++) { + q = kmem_cache_alloc(qdio_q_cache, GFP_KERNEL); + if (!q) + return -ENOMEM; + WARN_ON((unsigned long)q & 0xff); + + q->slib = (struct slib *) __get_free_page(GFP_KERNEL); + if (!q->slib) { + kmem_cache_free(qdio_q_cache, q); + return -ENOMEM; + } + WARN_ON((unsigned long)q->slib & 0x7ff); + irq_ptr_qs[i] = q; + } + return 0; +} + +int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs, int nr_output_qs) +{ + int rc; + + rc = __qdio_allocate_qs(irq_ptr->input_qs, nr_input_qs); + if (rc) + return rc; + rc = __qdio_allocate_qs(irq_ptr->output_qs, nr_output_qs); + return rc; +} + +static void setup_queues_misc(struct qdio_q *q, struct qdio_irq *irq_ptr, + qdio_handler_t *handler, int i) +{ + /* must be cleared by every qdio_establish */ + memset(q, 0, ((char *)&q->slib) - ((char *)q)); + memset(q->slib, 0, PAGE_SIZE); + + q->irq_ptr = irq_ptr; + q->mask = 1 << (31 - i); + q->nr = i; + q->handler = handler; +} + +static void setup_storage_lists(struct qdio_q *q, struct qdio_irq *irq_ptr, + void **sbals_array, char *dbf_text, int i) +{ + struct qdio_q *prev; + int j; + + QDIO_DBF_TEXT0(0, setup, dbf_text); + QDIO_DBF_HEX0(0, setup, &q, sizeof(void *)); + + q->sl = (struct sl *)((char *)q->slib + PAGE_SIZE / 2); + + /* fill in sbal */ + for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++) { + q->sbal[j] = *sbals_array++; + WARN_ON((unsigned long)q->sbal[j] & 0xff); + } + + /* fill in slib */ + if (i > 0) { + prev = (q->is_input_q) ? irq_ptr->input_qs[i - 1] + : irq_ptr->output_qs[i - 1]; + prev->slib->nsliba = (unsigned long)q->slib; + } + + q->slib->sla = (unsigned long)q->sl; + q->slib->slsba = (unsigned long)&q->slsb.val[0]; + + /* fill in sl */ + for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++) + q->sl->element[j].sbal = (unsigned long)q->sbal[j]; + + QDIO_DBF_TEXT2(0, setup, "sl-sb-b0"); + QDIO_DBF_HEX2(0, setup, q->sl, sizeof(void *)); + QDIO_DBF_HEX2(0, setup, &q->slsb, sizeof(void *)); + QDIO_DBF_HEX2(0, setup, q->sbal, sizeof(void *)); +} + +static void setup_queues(struct qdio_irq *irq_ptr, + struct qdio_initialize *qdio_init) +{ + char dbf_text[20]; + struct qdio_q *q; + void **input_sbal_array = qdio_init->input_sbal_addr_array; + void **output_sbal_array = qdio_init->output_sbal_addr_array; + int i; + + sprintf(dbf_text, "qfqs%4x", qdio_init->cdev->private->schid.sch_no); + QDIO_DBF_TEXT0(0, setup, dbf_text); + + for_each_input_queue(irq_ptr, q, i) { + sprintf(dbf_text, "in-q%4x", i); + setup_queues_misc(q, irq_ptr, qdio_init->input_handler, i); + + q->is_input_q = 1; + spin_lock_init(&q->u.in.lock); + setup_storage_lists(q, irq_ptr, input_sbal_array, dbf_text, i); + input_sbal_array += QDIO_MAX_BUFFERS_PER_Q; + + if (is_thinint_irq(irq_ptr)) + tasklet_init(&q->tasklet, tiqdio_inbound_processing, + (unsigned long) q); + else + tasklet_init(&q->tasklet, qdio_inbound_processing, + (unsigned long) q); + } + + for_each_output_queue(irq_ptr, q, i) { + sprintf(dbf_text, "outq%4x", i); + setup_queues_misc(q, irq_ptr, qdio_init->output_handler, i); + + q->is_input_q = 0; + setup_storage_lists(q, irq_ptr, output_sbal_array, + dbf_text, i); + output_sbal_array += QDIO_MAX_BUFFERS_PER_Q; + + tasklet_init(&q->tasklet, qdio_outbound_processing, + (unsigned long) q); + setup_timer(&q->u.out.timer, (void(*)(unsigned long)) + &qdio_outbound_timer, (unsigned long)q); + } +} + +static void process_ac_flags(struct qdio_irq *irq_ptr, unsigned char qdioac) +{ + if (qdioac & AC1_SIGA_INPUT_NEEDED) + irq_ptr->siga_flag.input = 1; + if (qdioac & AC1_SIGA_OUTPUT_NEEDED) + irq_ptr->siga_flag.output = 1; + if (qdioac & AC1_SIGA_SYNC_NEEDED) + irq_ptr->siga_flag.sync = 1; + if (qdioac & AC1_AUTOMATIC_SYNC_ON_THININT) + irq_ptr->siga_flag.no_sync_ti = 1; + if (qdioac & AC1_AUTOMATIC_SYNC_ON_OUT_PCI) + irq_ptr->siga_flag.no_sync_out_pci = 1; + + if (irq_ptr->siga_flag.no_sync_out_pci && + irq_ptr->siga_flag.no_sync_ti) + irq_ptr->siga_flag.no_sync_out_ti = 1; +} + +static void check_and_setup_qebsm(struct qdio_irq *irq_ptr, + unsigned char qdioac, unsigned long token) +{ + char dbf_text[15]; + + if (!(irq_ptr->qib.rflags & QIB_RFLAGS_ENABLE_QEBSM)) + goto no_qebsm; + if (!(qdioac & AC1_SC_QEBSM_AVAILABLE) || + (!(qdioac & AC1_SC_QEBSM_ENABLED))) + goto no_qebsm; + + irq_ptr->sch_token = token; + + QDIO_DBF_TEXT0(0, setup, "V=V:1"); + sprintf(dbf_text, "%8lx", irq_ptr->sch_token); + QDIO_DBF_TEXT0(0, setup, dbf_text); + return; + +no_qebsm: + irq_ptr->sch_token = 0; + irq_ptr->qib.rflags &= ~QIB_RFLAGS_ENABLE_QEBSM; + QDIO_DBF_TEXT0(0, setup, "noV=V"); +} + +static int __get_ssqd_info(struct qdio_irq *irq_ptr) +{ + struct chsc_ssqd_area *ssqd; + int rc; + + QDIO_DBF_TEXT0(0, setup, "getssqd"); + ssqd = (struct chsc_ssqd_area *)irq_ptr->chsc_page; + memset(ssqd, 0, PAGE_SIZE); + + ssqd->request = (struct chsc_header) { + .length = 0x0010, + .code = 0x0024, + }; + ssqd->first_sch = irq_ptr->schid.sch_no; + ssqd->last_sch = irq_ptr->schid.sch_no; + ssqd->ssid = irq_ptr->schid.ssid; + + if (chsc(ssqd)) + return -EIO; + rc = chsc_error_from_response(ssqd->response.code); + if (rc) + return rc; + + if (!(ssqd->qdio_ssqd.flags & CHSC_FLAG_QDIO_CAPABILITY) || + !(ssqd->qdio_ssqd.flags & CHSC_FLAG_VALIDITY) || + (ssqd->qdio_ssqd.sch != irq_ptr->schid.sch_no)) + return -EINVAL; + + memcpy(&irq_ptr->ssqd_desc, &ssqd->qdio_ssqd, + sizeof(struct qdio_ssqd_desc)); + return 0; +} + +void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr) +{ + unsigned char qdioac; + char dbf_text[15]; + int rc; + + rc = __get_ssqd_info(irq_ptr); + if (rc) { + QDIO_DBF_TEXT2(0, setup, "ssqdasig"); + sprintf(dbf_text, "schno%x", irq_ptr->schid.sch_no); + QDIO_DBF_TEXT2(0, setup, dbf_text); + sprintf(dbf_text, "rc:%d", rc); + QDIO_DBF_TEXT2(0, setup, dbf_text); + /* all flags set, worst case */ + qdioac = AC1_SIGA_INPUT_NEEDED | AC1_SIGA_OUTPUT_NEEDED | + AC1_SIGA_SYNC_NEEDED; + } else + qdioac = irq_ptr->ssqd_desc.qdioac1; + + check_and_setup_qebsm(irq_ptr, qdioac, irq_ptr->ssqd_desc.sch_token); + process_ac_flags(irq_ptr, qdioac); + + sprintf(dbf_text, "qdioac%2x", qdioac); + QDIO_DBF_TEXT2(0, setup, dbf_text); +} + +void qdio_release_memory(struct qdio_irq *irq_ptr) +{ + struct qdio_q *q; + int i; + + /* + * Must check queue array manually since irq_ptr->nr_input_queues / + * irq_ptr->nr_input_queues may not yet be set. + */ + for (i = 0; i < QDIO_MAX_QUEUES_PER_IRQ; i++) { + q = irq_ptr->input_qs[i]; + if (q) { + free_page((unsigned long) q->slib); + kmem_cache_free(qdio_q_cache, q); + } + } + for (i = 0; i < QDIO_MAX_QUEUES_PER_IRQ; i++) { + q = irq_ptr->output_qs[i]; + if (q) { + free_page((unsigned long) q->slib); + kmem_cache_free(qdio_q_cache, q); + } + } + kfree(irq_ptr->qdr); + free_page(irq_ptr->chsc_page); + free_page((unsigned long) irq_ptr); +} + +static void __qdio_allocate_fill_qdr(struct qdio_irq *irq_ptr, + struct qdio_q **irq_ptr_qs, + int i, int nr) +{ + irq_ptr->qdr->qdf0[i + nr].sliba = + (unsigned long)irq_ptr_qs[i]->slib; + + irq_ptr->qdr->qdf0[i + nr].sla = + (unsigned long)irq_ptr_qs[i]->sl; + + irq_ptr->qdr->qdf0[i + nr].slsba = + (unsigned long)&irq_ptr_qs[i]->slsb.val[0]; + + irq_ptr->qdr->qdf0[i + nr].akey = PAGE_DEFAULT_KEY; + irq_ptr->qdr->qdf0[i + nr].bkey = PAGE_DEFAULT_KEY; + irq_ptr->qdr->qdf0[i + nr].ckey = PAGE_DEFAULT_KEY; + irq_ptr->qdr->qdf0[i + nr].dkey = PAGE_DEFAULT_KEY; +} + +static void setup_qdr(struct qdio_irq *irq_ptr, + struct qdio_initialize *qdio_init) +{ + int i; + + irq_ptr->qdr->qfmt = qdio_init->q_format; + irq_ptr->qdr->iqdcnt = qdio_init->no_input_qs; + irq_ptr->qdr->oqdcnt = qdio_init->no_output_qs; + irq_ptr->qdr->iqdsz = sizeof(struct qdesfmt0) / 4; /* size in words */ + irq_ptr->qdr->oqdsz = sizeof(struct qdesfmt0) / 4; + irq_ptr->qdr->qiba = (unsigned long)&irq_ptr->qib; + irq_ptr->qdr->qkey = PAGE_DEFAULT_KEY; + + for (i = 0; i < qdio_init->no_input_qs; i++) + __qdio_allocate_fill_qdr(irq_ptr, irq_ptr->input_qs, i, 0); + + for (i = 0; i < qdio_init->no_output_qs; i++) + __qdio_allocate_fill_qdr(irq_ptr, irq_ptr->output_qs, i, + qdio_init->no_input_qs); +} + +static void setup_qib(struct qdio_irq *irq_ptr, + struct qdio_initialize *init_data) +{ + if (qebsm_possible()) + irq_ptr->qib.rflags |= QIB_RFLAGS_ENABLE_QEBSM; + + irq_ptr->qib.qfmt = init_data->q_format; + if (init_data->no_input_qs) + irq_ptr->qib.isliba = + (unsigned long)(irq_ptr->input_qs[0]->slib); + if (init_data->no_output_qs) + irq_ptr->qib.osliba = + (unsigned long)(irq_ptr->output_qs[0]->slib); + memcpy(irq_ptr->qib.ebcnam, init_data->adapter_name, 8); +} + +int qdio_setup_irq(struct qdio_initialize *init_data) +{ + struct ciw *ciw; + struct qdio_irq *irq_ptr = init_data->cdev->private->qdio_data; + int rc; + + memset(irq_ptr, 0, ((char *)&irq_ptr->qdr) - ((char *)irq_ptr)); + /* wipes qib.ac, required by ar7063 */ + memset(irq_ptr->qdr, 0, sizeof(struct qdr)); + + irq_ptr->int_parm = init_data->int_parm; + irq_ptr->nr_input_qs = init_data->no_input_qs; + irq_ptr->nr_output_qs = init_data->no_output_qs; + + irq_ptr->schid = ccw_device_get_subchannel_id(init_data->cdev); + irq_ptr->cdev = init_data->cdev; + setup_queues(irq_ptr, init_data); + + setup_qib(irq_ptr, init_data); + qdio_setup_thinint(irq_ptr); + set_impl_params(irq_ptr, init_data->qib_param_field_format, + init_data->qib_param_field, + init_data->input_slib_elements, + init_data->output_slib_elements); + + /* fill input and output descriptors */ + setup_qdr(irq_ptr, init_data); + + /* qdr, qib, sls, slsbs, slibs, sbales are filled now */ + + /* get qdio commands */ + ciw = ccw_device_get_ciw(init_data->cdev, CIW_TYPE_EQUEUE); + if (!ciw) { + QDIO_DBF_TEXT2(1, setup, "no eq"); + rc = -EINVAL; + goto out_err; + } + irq_ptr->equeue = *ciw; + + ciw = ccw_device_get_ciw(init_data->cdev, CIW_TYPE_AQUEUE); + if (!ciw) { + QDIO_DBF_TEXT2(1, setup, "no aq"); + rc = -EINVAL; + goto out_err; + } + irq_ptr->aqueue = *ciw; + + /* set new interrupt handler */ + irq_ptr->orig_handler = init_data->cdev->handler; + init_data->cdev->handler = qdio_int_handler; + return 0; +out_err: + qdio_release_memory(irq_ptr); + return rc; +} + +void qdio_print_subchannel_info(struct qdio_irq *irq_ptr, + struct ccw_device *cdev) +{ + char s[80]; + + sprintf(s, "%s ", cdev->dev.bus_id); + + switch (irq_ptr->qib.qfmt) { + case QDIO_QETH_QFMT: + sprintf(s + strlen(s), "OSADE "); + break; + case QDIO_ZFCP_QFMT: + sprintf(s + strlen(s), "ZFCP "); + break; + case QDIO_IQDIO_QFMT: + sprintf(s + strlen(s), "HiperSockets "); + break; + } + sprintf(s + strlen(s), "using: "); + + if (!is_thinint_irq(irq_ptr)) + sprintf(s + strlen(s), "no"); + sprintf(s + strlen(s), "AdapterInterrupts "); + if (!(irq_ptr->sch_token != 0)) + sprintf(s + strlen(s), "no"); + sprintf(s + strlen(s), "QEBSM "); + if (!(irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)) + sprintf(s + strlen(s), "no"); + sprintf(s + strlen(s), "OutboundPCI "); + if (!css_general_characteristics.aif_tdd) + sprintf(s + strlen(s), "no"); + sprintf(s + strlen(s), "TDD\n"); + printk(KERN_INFO "qdio: %s", s); + + memset(s, 0, sizeof(s)); + sprintf(s, "%s SIGA required: ", cdev->dev.bus_id); + if (irq_ptr->siga_flag.input) + sprintf(s + strlen(s), "Read "); + if (irq_ptr->siga_flag.output) + sprintf(s + strlen(s), "Write "); + if (irq_ptr->siga_flag.sync) + sprintf(s + strlen(s), "Sync "); + if (!irq_ptr->siga_flag.no_sync_ti) + sprintf(s + strlen(s), "SyncAI "); + if (!irq_ptr->siga_flag.no_sync_out_ti) + sprintf(s + strlen(s), "SyncOutAI "); + if (!irq_ptr->siga_flag.no_sync_out_pci) + sprintf(s + strlen(s), "SyncOutPCI"); + sprintf(s + strlen(s), "\n"); + printk(KERN_INFO "qdio: %s", s); +} + +int __init qdio_setup_init(void) +{ + char dbf_text[15]; + + qdio_q_cache = kmem_cache_create("qdio_q", sizeof(struct qdio_q), + 256, 0, NULL); + if (!qdio_q_cache) + return -ENOMEM; + + /* Check for OSA/FCP thin interrupts (bit 67). */ + sprintf(dbf_text, "thini%1x", + (css_general_characteristics.aif_osa) ? 1 : 0); + QDIO_DBF_TEXT0(0, setup, dbf_text); + + /* Check for QEBSM support in general (bit 58). */ + sprintf(dbf_text, "cssQBS:%1x", + (qebsm_possible()) ? 1 : 0); + QDIO_DBF_TEXT0(0, setup, dbf_text); + return 0; +} + +void __exit qdio_setup_exit(void) +{ + kmem_cache_destroy(qdio_q_cache); +} diff --git a/drivers/s390/cio/qdio_thinint.c b/drivers/s390/cio/qdio_thinint.c new file mode 100644 index 000000000000..9291a771d812 --- /dev/null +++ b/drivers/s390/cio/qdio_thinint.c @@ -0,0 +1,380 @@ +/* + * linux/drivers/s390/cio/thinint_qdio.c + * + * thin interrupt support for qdio + * + * Copyright 2000-2008 IBM Corp. + * Author(s): Utz Bacher + * Cornelia Huck + * Jan Glauber + */ +#include +#include +#include +#include +#include +#include + +#include "cio.h" +#include "ioasm.h" +#include "qdio.h" +#include "qdio_debug.h" +#include "qdio_perf.h" + +/* + * Restriction: only 63 iqdio subchannels would have its own indicator, + * after that, subsequent subchannels share one indicator + */ +#define TIQDIO_NR_NONSHARED_IND 63 +#define TIQDIO_NR_INDICATORS (TIQDIO_NR_NONSHARED_IND + 1) +#define TIQDIO_SHARED_IND 63 + +/* list of thin interrupt input queues */ +static LIST_HEAD(tiq_list); + +/* adapter local summary indicator */ +static unsigned char *tiqdio_alsi; + +/* device state change indicators */ +struct indicator_t { + u32 ind; /* u32 because of compare-and-swap performance */ + atomic_t count; /* use count, 0 or 1 for non-shared indicators */ +}; +static struct indicator_t *q_indicators; + +static void tiqdio_tasklet_fn(unsigned long data); +static DECLARE_TASKLET(tiqdio_tasklet, tiqdio_tasklet_fn, 0); + +static int css_qdio_omit_svs; + +static inline unsigned long do_clear_global_summary(void) +{ + register unsigned long __fn asm("1") = 3; + register unsigned long __tmp asm("2"); + register unsigned long __time asm("3"); + + asm volatile( + " .insn rre,0xb2650000,2,0" + : "+d" (__fn), "=d" (__tmp), "=d" (__time)); + return __time; +} + +/* returns addr for the device state change indicator */ +static u32 *get_indicator(void) +{ + int i; + + for (i = 0; i < TIQDIO_NR_NONSHARED_IND; i++) + if (!atomic_read(&q_indicators[i].count)) { + atomic_set(&q_indicators[i].count, 1); + return &q_indicators[i].ind; + } + + /* use the shared indicator */ + atomic_inc(&q_indicators[TIQDIO_SHARED_IND].count); + return &q_indicators[TIQDIO_SHARED_IND].ind; +} + +static void put_indicator(u32 *addr) +{ + int i; + + if (!addr) + return; + i = ((unsigned long)addr - (unsigned long)q_indicators) / + sizeof(struct indicator_t); + atomic_dec(&q_indicators[i].count); +} + +void tiqdio_add_input_queues(struct qdio_irq *irq_ptr) +{ + struct qdio_q *q; + int i; + + /* No TDD facility? If we must use SIGA-s we can also omit SVS. */ + if (!css_qdio_omit_svs && irq_ptr->siga_flag.sync) + css_qdio_omit_svs = 1; + + for_each_input_queue(irq_ptr, q, i) { + list_add_rcu(&q->entry, &tiq_list); + synchronize_rcu(); + } + xchg(irq_ptr->dsci, 1); + tasklet_schedule(&tiqdio_tasklet); +} + +/* + * we cannot stop the tiqdio tasklet here since it is for all + * thinint qdio devices and it must run as long as there is a + * thinint device left + */ +void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr) +{ + struct qdio_q *q; + int i; + + for_each_input_queue(irq_ptr, q, i) { + list_del_rcu(&q->entry); + synchronize_rcu(); + } +} + +static inline int tiqdio_inbound_q_done(struct qdio_q *q) +{ + unsigned char state; + + if (!atomic_read(&q->nr_buf_used)) + return 1; + + qdio_siga_sync_q(q); + get_buf_state(q, q->first_to_check, &state); + + if (state == SLSB_P_INPUT_PRIMED) + /* more work coming */ + return 0; + return 1; +} + +static inline int shared_ind(struct qdio_irq *irq_ptr) +{ + return irq_ptr->dsci == &q_indicators[TIQDIO_SHARED_IND].ind; +} + +static void __tiqdio_inbound_processing(struct qdio_q *q) +{ + qdio_perf_stat_inc(&perf_stats.thinint_inbound); + qdio_sync_after_thinint(q); + + /* + * Maybe we have work on our outbound queues... at least + * we have to check the PCI capable queues. + */ + qdio_check_outbound_after_thinint(q); + +again: + if (!qdio_inbound_q_moved(q)) + return; + + qdio_kick_inbound_handler(q); + + if (!tiqdio_inbound_q_done(q)) { + qdio_perf_stat_inc(&perf_stats.thinint_inbound_loop); + goto again; + } + + qdio_stop_polling(q); + /* + * We need to check again to not lose initiative after + * resetting the ACK state. + */ + if (!tiqdio_inbound_q_done(q)) { + qdio_perf_stat_inc(&perf_stats.thinint_inbound_loop2); + goto again; + } +} + +void tiqdio_inbound_processing(unsigned long data) +{ + struct qdio_q *q = (struct qdio_q *)data; + + __tiqdio_inbound_processing(q); +} + +/* check for work on all inbound thinint queues */ +static void tiqdio_tasklet_fn(unsigned long data) +{ + struct qdio_q *q; + + qdio_perf_stat_inc(&perf_stats.tasklet_thinint); +again: + + /* protect tiq_list entries, only changed in activate or shutdown */ + rcu_read_lock(); + + list_for_each_entry_rcu(q, &tiq_list, entry) + /* only process queues from changed sets */ + if (*q->irq_ptr->dsci) { + + /* only clear it if the indicator is non-shared */ + if (!shared_ind(q->irq_ptr)) + xchg(q->irq_ptr->dsci, 0); + /* + * don't call inbound processing directly since + * that could starve other thinint queues + */ + tasklet_schedule(&q->tasklet); + } + + rcu_read_unlock(); + + /* + * if we used the shared indicator clear it now after all queues + * were processed + */ + if (atomic_read(&q_indicators[TIQDIO_SHARED_IND].count)) { + xchg(&q_indicators[TIQDIO_SHARED_IND].ind, 0); + + /* prevent racing */ + if (*tiqdio_alsi) + xchg(&q_indicators[TIQDIO_SHARED_IND].ind, 1); + } + + /* check for more work */ + if (*tiqdio_alsi) { + xchg(tiqdio_alsi, 0); + qdio_perf_stat_inc(&perf_stats.tasklet_thinint_loop); + goto again; + } +} + +/** + * tiqdio_thinint_handler - thin interrupt handler for qdio + * @ind: pointer to adapter local summary indicator + * @drv_data: NULL + */ +static void tiqdio_thinint_handler(void *ind, void *drv_data) +{ + qdio_perf_stat_inc(&perf_stats.thin_int); + + /* + * SVS only when needed: issue SVS to benefit from iqdio interrupt + * avoidance (SVS clears adapter interrupt suppression overwrite) + */ + if (!css_qdio_omit_svs) + do_clear_global_summary(); + + /* + * reset local summary indicator (tiqdio_alsi) to stop adapter + * interrupts for now, the tasklet will clean all dsci's + */ + xchg((u8 *)ind, 0); + tasklet_hi_schedule(&tiqdio_tasklet); +} + +static int set_subchannel_ind(struct qdio_irq *irq_ptr, int reset) +{ + struct scssc_area *scssc_area; + char dbf_text[15]; + void *ptr; + int rc; + + scssc_area = (struct scssc_area *)irq_ptr->chsc_page; + memset(scssc_area, 0, PAGE_SIZE); + + if (reset) { + scssc_area->summary_indicator_addr = 0; + scssc_area->subchannel_indicator_addr = 0; + } else { + scssc_area->summary_indicator_addr = virt_to_phys(tiqdio_alsi); + scssc_area->subchannel_indicator_addr = + virt_to_phys(irq_ptr->dsci); + } + + scssc_area->request = (struct chsc_header) { + .length = 0x0fe0, + .code = 0x0021, + }; + scssc_area->operation_code = 0; + scssc_area->ks = PAGE_DEFAULT_KEY; + scssc_area->kc = PAGE_DEFAULT_KEY; + scssc_area->isc = QDIO_AIRQ_ISC; + scssc_area->schid = irq_ptr->schid; + + /* enable the time delay disablement facility */ + if (css_general_characteristics.aif_tdd) + scssc_area->word_with_d_bit = 0x10000000; + + rc = chsc(scssc_area); + if (rc) + return -EIO; + + rc = chsc_error_from_response(scssc_area->response.code); + if (rc) { + sprintf(dbf_text, "sidR%4x", scssc_area->response.code); + QDIO_DBF_TEXT1(0, trace, dbf_text); + QDIO_DBF_TEXT1(0, setup, dbf_text); + ptr = &scssc_area->response; + QDIO_DBF_HEX2(1, setup, &ptr, QDIO_DBF_SETUP_LEN); + return rc; + } + + QDIO_DBF_TEXT2(0, setup, "setscind"); + QDIO_DBF_HEX2(0, setup, &scssc_area->summary_indicator_addr, + sizeof(unsigned long)); + QDIO_DBF_HEX2(0, setup, &scssc_area->subchannel_indicator_addr, + sizeof(unsigned long)); + return 0; +} + +/* allocate non-shared indicators and shared indicator */ +int __init tiqdio_allocate_memory(void) +{ + q_indicators = kzalloc(sizeof(struct indicator_t) * TIQDIO_NR_INDICATORS, + GFP_KERNEL); + if (!q_indicators) + return -ENOMEM; + return 0; +} + +void tiqdio_free_memory(void) +{ + kfree(q_indicators); +} + +int __init tiqdio_register_thinints(void) +{ + char dbf_text[20]; + + isc_register(QDIO_AIRQ_ISC); + tiqdio_alsi = s390_register_adapter_interrupt(&tiqdio_thinint_handler, + NULL, QDIO_AIRQ_ISC); + if (IS_ERR(tiqdio_alsi)) { + sprintf(dbf_text, "regthn%lx", PTR_ERR(tiqdio_alsi)); + QDIO_DBF_TEXT0(0, setup, dbf_text); + tiqdio_alsi = NULL; + isc_unregister(QDIO_AIRQ_ISC); + return -ENOMEM; + } + return 0; +} + +int qdio_establish_thinint(struct qdio_irq *irq_ptr) +{ + if (!is_thinint_irq(irq_ptr)) + return 0; + + /* Check for aif time delay disablement. If installed, + * omit SVS even under LPAR + */ + if (css_general_characteristics.aif_tdd) + css_qdio_omit_svs = 1; + return set_subchannel_ind(irq_ptr, 0); +} + +void qdio_setup_thinint(struct qdio_irq *irq_ptr) +{ + if (!is_thinint_irq(irq_ptr)) + return; + irq_ptr->dsci = get_indicator(); + QDIO_DBF_HEX1(0, setup, &irq_ptr->dsci, sizeof(void *)); +} + +void qdio_shutdown_thinint(struct qdio_irq *irq_ptr) +{ + if (!is_thinint_irq(irq_ptr)) + return; + + /* reset adapter interrupt indicators */ + put_indicator(irq_ptr->dsci); + set_subchannel_ind(irq_ptr, 1); +} + +void __exit tiqdio_unregister_thinints(void) +{ + tasklet_disable(&tiqdio_tasklet); + + if (tiqdio_alsi) { + s390_unregister_adapter_interrupt(tiqdio_alsi, QDIO_AIRQ_ISC); + isc_unregister(QDIO_AIRQ_ISC); + } +} diff --git a/drivers/s390/net/qeth_core.h b/drivers/s390/net/qeth_core.h index 699ac11debd8..1895dbb553cd 100644 --- a/drivers/s390/net/qeth_core.h +++ b/drivers/s390/net/qeth_core.h @@ -239,11 +239,6 @@ static inline int qeth_is_ipa_enabled(struct qeth_ipa_info *ipa, /*not used unless the microcode gets patched*/ #define QETH_PCI_TIMER_VALUE(card) 3 -#define QETH_MIN_INPUT_THRESHOLD 1 -#define QETH_MAX_INPUT_THRESHOLD 500 -#define QETH_MIN_OUTPUT_THRESHOLD 1 -#define QETH_MAX_OUTPUT_THRESHOLD 300 - /* priority queing */ #define QETH_PRIOQ_DEFAULT QETH_NO_PRIO_QUEUEING #define QETH_DEFAULT_QUEUE 2 @@ -811,17 +806,14 @@ int qeth_send_ipa_cmd(struct qeth_card *, struct qeth_cmd_buffer *, struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *, enum qeth_ipa_cmds, enum qeth_prot_versions); int qeth_query_setadapterparms(struct qeth_card *); -int qeth_check_qdio_errors(struct qdio_buffer *, unsigned int, - unsigned int, const char *); +int qeth_check_qdio_errors(struct qdio_buffer *, unsigned int, const char *); void qeth_queue_input_buffer(struct qeth_card *, int); struct sk_buff *qeth_core_get_next_skb(struct qeth_card *, struct qdio_buffer *, struct qdio_buffer_element **, int *, struct qeth_hdr **); void qeth_schedule_recovery(struct qeth_card *); void qeth_qdio_output_handler(struct ccw_device *, unsigned int, - unsigned int, unsigned int, - unsigned int, int, int, - unsigned long); + int, int, int, unsigned long); void qeth_clear_ipacmd_list(struct qeth_card *); int qeth_qdio_clear_card(struct qeth_card *, int); void qeth_clear_working_pool_list(struct qeth_card *); diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 0ac54dc638c2..c3ad89e302bd 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -2073,7 +2073,7 @@ static void qeth_create_qib_param_field_blkt(struct qeth_card *card, static int qeth_qdio_activate(struct qeth_card *card) { QETH_DBF_TEXT(SETUP, 3, "qdioact"); - return qdio_activate(CARD_DDEV(card), 0); + return qdio_activate(CARD_DDEV(card)); } static int qeth_dm_act(struct qeth_card *card) @@ -2349,16 +2349,11 @@ int qeth_init_qdio_queues(struct qeth_card *card) card->qdio.in_q->next_buf_to_init = card->qdio.in_buf_pool.buf_count - 1; rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0, - card->qdio.in_buf_pool.buf_count - 1, NULL); + card->qdio.in_buf_pool.buf_count - 1); if (rc) { QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc); return rc; } - rc = qdio_synchronize(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0); - if (rc) { - QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc); - return rc; - } /* outbound queue */ for (i = 0; i < card->qdio.no_out_queues; ++i) { memset(card->qdio.out_qs[i]->qdio_bufs, 0, @@ -2559,9 +2554,9 @@ int qeth_query_setadapterparms(struct qeth_card *card) EXPORT_SYMBOL_GPL(qeth_query_setadapterparms); int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error, - unsigned int siga_error, const char *dbftext) + const char *dbftext) { - if (qdio_error || siga_error) { + if (qdio_error) { QETH_DBF_TEXT(TRACE, 2, dbftext); QETH_DBF_TEXT(QERR, 2, dbftext); QETH_DBF_TEXT_(QERR, 2, " F15=%02X", @@ -2569,7 +2564,6 @@ int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error, QETH_DBF_TEXT_(QERR, 2, " F14=%02X", buf->element[14].flags & 0xff); QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error); - QETH_DBF_TEXT_(QERR, 2, " serr=%X", siga_error); return 1; } return 0; @@ -2622,9 +2616,8 @@ void qeth_queue_input_buffer(struct qeth_card *card, int index) card->perf_stats.inbound_do_qdio_start_time = qeth_get_micros(); } - rc = do_QDIO(CARD_DDEV(card), - QDIO_FLAG_SYNC_INPUT | QDIO_FLAG_UNDER_INTERRUPT, - 0, queue->next_buf_to_init, count, NULL); + rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, + queue->next_buf_to_init, count); if (card->options.performance_stats) card->perf_stats.inbound_do_qdio_time += qeth_get_micros() - @@ -2643,14 +2636,13 @@ void qeth_queue_input_buffer(struct qeth_card *card, int index) EXPORT_SYMBOL_GPL(qeth_queue_input_buffer); static int qeth_handle_send_error(struct qeth_card *card, - struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err, - unsigned int siga_err) + struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err) { int sbalf15 = buffer->buffer->element[15].flags & 0xff; - int cc = siga_err & 3; + int cc = qdio_err & 3; QETH_DBF_TEXT(TRACE, 6, "hdsnderr"); - qeth_check_qdio_errors(buffer->buffer, qdio_err, siga_err, "qouterr"); + qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr"); switch (cc) { case 0: if (qdio_err) { @@ -2662,7 +2654,7 @@ static int qeth_handle_send_error(struct qeth_card *card, } return QETH_SEND_ERROR_NONE; case 2: - if (siga_err & QDIO_SIGA_ERROR_B_BIT_SET) { + if (qdio_err & QDIO_ERROR_SIGA_BUSY) { QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B"); QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card)); return QETH_SEND_ERROR_KICK_IT; @@ -2758,8 +2750,8 @@ static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue) return 0; } -static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int under_int, - int index, int count) +static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index, + int count) { struct qeth_qdio_out_buffer *buf; int rc; @@ -2807,12 +2799,10 @@ static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int under_int, qeth_get_micros(); } qdio_flags = QDIO_FLAG_SYNC_OUTPUT; - if (under_int) - qdio_flags |= QDIO_FLAG_UNDER_INTERRUPT; if (atomic_read(&queue->set_pci_flags_count)) qdio_flags |= QDIO_FLAG_PCI_OUT; rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags, - queue->queue_no, index, count, NULL); + queue->queue_no, index, count); if (queue->card->options.performance_stats) queue->card->perf_stats.outbound_do_qdio_time += qeth_get_micros() - @@ -2866,16 +2856,15 @@ static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue) queue->card->perf_stats.bufs_sent_pack += flush_cnt; if (flush_cnt) - qeth_flush_buffers(queue, 1, index, flush_cnt); + qeth_flush_buffers(queue, index, flush_cnt); atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED); } } } -void qeth_qdio_output_handler(struct ccw_device *ccwdev, unsigned int status, - unsigned int qdio_error, unsigned int siga_error, - unsigned int __queue, int first_element, int count, - unsigned long card_ptr) +void qeth_qdio_output_handler(struct ccw_device *ccwdev, + unsigned int qdio_error, int __queue, int first_element, + int count, unsigned long card_ptr) { struct qeth_card *card = (struct qeth_card *) card_ptr; struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue]; @@ -2883,15 +2872,12 @@ void qeth_qdio_output_handler(struct ccw_device *ccwdev, unsigned int status, int i; QETH_DBF_TEXT(TRACE, 6, "qdouhdl"); - if (status & QDIO_STATUS_LOOK_FOR_ERROR) { - if (status & QDIO_STATUS_ACTIVATE_CHECK_CONDITION) { - QETH_DBF_TEXT(TRACE, 2, "achkcond"); - QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card)); - QETH_DBF_TEXT_(TRACE, 2, "%08x", status); - netif_stop_queue(card->dev); - qeth_schedule_recovery(card); - return; - } + if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) { + QETH_DBF_TEXT(TRACE, 2, "achkcond"); + QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card)); + netif_stop_queue(card->dev); + qeth_schedule_recovery(card); + return; } if (card->options.performance_stats) { card->perf_stats.outbound_handler_cnt++; @@ -2901,8 +2887,7 @@ void qeth_qdio_output_handler(struct ccw_device *ccwdev, unsigned int status, for (i = first_element; i < (first_element + count); ++i) { buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q]; /*we only handle the KICK_IT error by doing a recovery */ - if (qeth_handle_send_error(card, buffer, - qdio_error, siga_error) + if (qeth_handle_send_error(card, buffer, qdio_error) == QETH_SEND_ERROR_KICK_IT){ netif_stop_queue(card->dev); qeth_schedule_recovery(card); @@ -3164,11 +3149,11 @@ int qeth_do_send_packet_fast(struct qeth_card *card, atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED); if (ctx == NULL) { qeth_fill_buffer(queue, buffer, skb); - qeth_flush_buffers(queue, 0, index, 1); + qeth_flush_buffers(queue, index, 1); } else { flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index); WARN_ON(buffers_needed != flush_cnt); - qeth_flush_buffers(queue, 0, index, flush_cnt); + qeth_flush_buffers(queue, index, flush_cnt); } return 0; out: @@ -3221,8 +3206,8 @@ int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue, * again */ if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY){ - qeth_flush_buffers(queue, 0, - start_index, flush_count); + qeth_flush_buffers(queue, start_index, + flush_count); atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED); return -EBUSY; @@ -3253,7 +3238,7 @@ int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue, flush_count += tmp; out: if (flush_count) - qeth_flush_buffers(queue, 0, start_index, flush_count); + qeth_flush_buffers(queue, start_index, flush_count); else if (!atomic_read(&queue->set_pci_flags_count)) atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH); /* @@ -3274,7 +3259,7 @@ out: if (!flush_count && !atomic_read(&queue->set_pci_flags_count)) flush_count += qeth_flush_buffers_on_no_pci(queue); if (flush_count) - qeth_flush_buffers(queue, 0, start_index, flush_count); + qeth_flush_buffers(queue, start_index, flush_count); } /* at this point the queue is UNLOCKED again */ if (queue->card->options.performance_stats && do_pack) @@ -3686,10 +3671,6 @@ static int qeth_qdio_establish(struct qeth_card *card) init_data.q_format = qeth_get_qdio_q_format(card); init_data.qib_param_field_format = 0; init_data.qib_param_field = qib_param_field; - init_data.min_input_threshold = QETH_MIN_INPUT_THRESHOLD; - init_data.max_input_threshold = QETH_MAX_INPUT_THRESHOLD; - init_data.min_output_threshold = QETH_MIN_OUTPUT_THRESHOLD; - init_data.max_output_threshold = QETH_MAX_OUTPUT_THRESHOLD; init_data.no_input_qs = 1; init_data.no_output_qs = card->qdio.no_out_queues; init_data.input_handler = card->discipline.input_handler; @@ -3751,8 +3732,9 @@ static int qeth_core_driver_group(const char *buf, struct device *root_dev, int qeth_core_hardsetup_card(struct qeth_card *card) { + struct qdio_ssqd_desc *qdio_ssqd; int retries = 3; - int mpno; + int mpno = 0; int rc; QETH_DBF_TEXT(SETUP, 2, "hrdsetup"); @@ -3784,7 +3766,10 @@ retry: QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc); return rc; } - mpno = qdio_get_ssqd_pct(CARD_DDEV(card)); + + qdio_ssqd = qdio_get_ssqd_desc(CARD_DDEV(card)); + if (qdio_ssqd) + mpno = qdio_ssqd->pcnt; if (mpno) mpno = min(mpno - 1, QETH_MAX_PORTNO); if (card->info.portno > mpno) { diff --git a/drivers/s390/net/qeth_l2_main.c b/drivers/s390/net/qeth_l2_main.c index f682f7b14480..3fbc3bdec0c5 100644 --- a/drivers/s390/net/qeth_l2_main.c +++ b/drivers/s390/net/qeth_l2_main.c @@ -726,8 +726,7 @@ tx_drop: } static void qeth_l2_qdio_input_handler(struct ccw_device *ccwdev, - unsigned int status, unsigned int qdio_err, - unsigned int siga_err, unsigned int queue, + unsigned int qdio_err, unsigned int queue, int first_element, int count, unsigned long card_ptr) { struct net_device *net_dev; @@ -742,23 +741,20 @@ static void qeth_l2_qdio_input_handler(struct ccw_device *ccwdev, card->perf_stats.inbound_cnt++; card->perf_stats.inbound_start_time = qeth_get_micros(); } - if (status & QDIO_STATUS_LOOK_FOR_ERROR) { - if (status & QDIO_STATUS_ACTIVATE_CHECK_CONDITION) { - QETH_DBF_TEXT(TRACE, 1, "qdinchk"); - QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card)); - QETH_DBF_TEXT_(TRACE, 1, "%04X%04X", first_element, - count); - QETH_DBF_TEXT_(TRACE, 1, "%04X%04X", queue, status); - qeth_schedule_recovery(card); - return; - } + if (qdio_err & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) { + QETH_DBF_TEXT(TRACE, 1, "qdinchk"); + QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card)); + QETH_DBF_TEXT_(TRACE, 1, "%04X%04X", first_element, + count); + QETH_DBF_TEXT_(TRACE, 1, "%04X", queue); + qeth_schedule_recovery(card); + return; } for (i = first_element; i < (first_element + count); ++i) { index = i % QDIO_MAX_BUFFERS_PER_Q; buffer = &card->qdio.in_q->bufs[index]; - if (!((status & QDIO_STATUS_LOOK_FOR_ERROR) && - qeth_check_qdio_errors(buffer->buffer, - qdio_err, siga_err, "qinerr"))) + if (!(qdio_err && + qeth_check_qdio_errors(buffer->buffer, qdio_err, "qinerr"))) qeth_l2_process_inbound_buffer(card, buffer, index); /* clear buffer and give back to hardware */ qeth_put_buffer_pool_entry(card, buffer->pool_entry); diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index 06deaee50f6d..22f64aa6dd1f 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -2939,8 +2939,7 @@ static int qeth_l3_setup_netdev(struct qeth_card *card) } static void qeth_l3_qdio_input_handler(struct ccw_device *ccwdev, - unsigned int status, unsigned int qdio_err, - unsigned int siga_err, unsigned int queue, int first_element, + unsigned int qdio_err, unsigned int queue, int first_element, int count, unsigned long card_ptr) { struct net_device *net_dev; @@ -2955,23 +2954,21 @@ static void qeth_l3_qdio_input_handler(struct ccw_device *ccwdev, card->perf_stats.inbound_cnt++; card->perf_stats.inbound_start_time = qeth_get_micros(); } - if (status & QDIO_STATUS_LOOK_FOR_ERROR) { - if (status & QDIO_STATUS_ACTIVATE_CHECK_CONDITION) { - QETH_DBF_TEXT(TRACE, 1, "qdinchk"); - QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card)); - QETH_DBF_TEXT_(TRACE, 1, "%04X%04X", - first_element, count); - QETH_DBF_TEXT_(TRACE, 1, "%04X%04X", queue, status); - qeth_schedule_recovery(card); - return; - } + if (qdio_err & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) { + QETH_DBF_TEXT(TRACE, 1, "qdinchk"); + QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card)); + QETH_DBF_TEXT_(TRACE, 1, "%04X%04X", + first_element, count); + QETH_DBF_TEXT_(TRACE, 1, "%04X", queue); + qeth_schedule_recovery(card); + return; } for (i = first_element; i < (first_element + count); ++i) { index = i % QDIO_MAX_BUFFERS_PER_Q; buffer = &card->qdio.in_q->bufs[index]; - if (!((status & QDIO_STATUS_LOOK_FOR_ERROR) && + if (!(qdio_err && qeth_check_qdio_errors(buffer->buffer, - qdio_err, siga_err, "qinerr"))) + qdio_err, "qinerr"))) qeth_l3_process_inbound_buffer(card, buffer, index); /* clear buffer and give back to hardware */ qeth_put_buffer_pool_entry(card, buffer->pool_entry); diff --git a/drivers/s390/scsi/zfcp_dbf.c b/drivers/s390/scsi/zfcp_dbf.c index 36169c6944fd..fca48b88fc53 100644 --- a/drivers/s390/scsi/zfcp_dbf.c +++ b/drivers/s390/scsi/zfcp_dbf.c @@ -297,15 +297,13 @@ void zfcp_hba_dbf_event_fsf_unsol(const char *tag, struct zfcp_adapter *adapter, /** * zfcp_hba_dbf_event_qdio - trace event for QDIO related failure * @adapter: adapter affected by this QDIO related event - * @status: as passed by qdio module * @qdio_error: as passed by qdio module - * @siga_error: as passed by qdio module * @sbal_index: first buffer with error condition, as passed by qdio module * @sbal_count: number of buffers affected, as passed by qdio module */ -void zfcp_hba_dbf_event_qdio(struct zfcp_adapter *adapter, unsigned int status, - unsigned int qdio_error, unsigned int siga_error, - int sbal_index, int sbal_count) +void zfcp_hba_dbf_event_qdio(struct zfcp_adapter *adapter, + unsigned int qdio_error, int sbal_index, + int sbal_count) { struct zfcp_hba_dbf_record *r = &adapter->hba_dbf_buf; unsigned long flags; @@ -313,9 +311,7 @@ void zfcp_hba_dbf_event_qdio(struct zfcp_adapter *adapter, unsigned int status, spin_lock_irqsave(&adapter->hba_dbf_lock, flags); memset(r, 0, sizeof(*r)); strncpy(r->tag, "qdio", ZFCP_DBF_TAG_SIZE); - r->u.qdio.status = status; r->u.qdio.qdio_error = qdio_error; - r->u.qdio.siga_error = siga_error; r->u.qdio.sbal_index = sbal_index; r->u.qdio.sbal_count = sbal_count; debug_event(adapter->hba_dbf, 0, r, sizeof(*r)); @@ -398,9 +394,7 @@ static void zfcp_hba_dbf_view_status(char **p, static void zfcp_hba_dbf_view_qdio(char **p, struct zfcp_hba_dbf_record_qdio *r) { - zfcp_dbf_out(p, "status", "0x%08x", r->status); zfcp_dbf_out(p, "qdio_error", "0x%08x", r->qdio_error); - zfcp_dbf_out(p, "siga_error", "0x%08x", r->siga_error); zfcp_dbf_out(p, "sbal_index", "0x%02x", r->sbal_index); zfcp_dbf_out(p, "sbal_count", "0x%02x", r->sbal_count); } diff --git a/drivers/s390/scsi/zfcp_dbf.h b/drivers/s390/scsi/zfcp_dbf.h index d04aea604974..0ddb18449d11 100644 --- a/drivers/s390/scsi/zfcp_dbf.h +++ b/drivers/s390/scsi/zfcp_dbf.h @@ -139,9 +139,7 @@ struct zfcp_hba_dbf_record_status { } __attribute__ ((packed)); struct zfcp_hba_dbf_record_qdio { - u32 status; u32 qdio_error; - u32 siga_error; u8 sbal_index; u8 sbal_count; } __attribute__ ((packed)); diff --git a/drivers/s390/scsi/zfcp_ext.h b/drivers/s390/scsi/zfcp_ext.h index 8065b2b224b7..edfdb21591f3 100644 --- a/drivers/s390/scsi/zfcp_ext.h +++ b/drivers/s390/scsi/zfcp_ext.h @@ -48,9 +48,8 @@ extern void zfcp_rec_dbf_event_action(u8, struct zfcp_erp_action *); extern void zfcp_hba_dbf_event_fsf_response(struct zfcp_fsf_req *); extern void zfcp_hba_dbf_event_fsf_unsol(const char *, struct zfcp_adapter *, struct fsf_status_read_buffer *); -extern void zfcp_hba_dbf_event_qdio(struct zfcp_adapter *, - unsigned int, unsigned int, unsigned int, - int, int); +extern void zfcp_hba_dbf_event_qdio(struct zfcp_adapter *, unsigned int, int, + int); extern void zfcp_san_dbf_event_ct_request(struct zfcp_fsf_req *); extern void zfcp_san_dbf_event_ct_response(struct zfcp_fsf_req *); extern void zfcp_san_dbf_event_els_request(struct zfcp_fsf_req *); diff --git a/drivers/s390/scsi/zfcp_qdio.c b/drivers/s390/scsi/zfcp_qdio.c index 72e3094796d4..d6dbd653fde9 100644 --- a/drivers/s390/scsi/zfcp_qdio.c +++ b/drivers/s390/scsi/zfcp_qdio.c @@ -74,17 +74,15 @@ static void zfcp_qdio_zero_sbals(struct qdio_buffer *sbal[], int first, int cnt) } } -static void zfcp_qdio_int_req(struct ccw_device *cdev, unsigned int status, - unsigned int qdio_err, unsigned int siga_err, - unsigned int queue_no, int first, int count, +static void zfcp_qdio_int_req(struct ccw_device *cdev, unsigned int qdio_err, + int queue_no, int first, int count, unsigned long parm) { struct zfcp_adapter *adapter = (struct zfcp_adapter *) parm; struct zfcp_qdio_queue *queue = &adapter->req_q; - if (unlikely(status & QDIO_STATUS_LOOK_FOR_ERROR)) { - zfcp_hba_dbf_event_qdio(adapter, status, qdio_err, siga_err, - first, count); + if (unlikely(qdio_err)) { + zfcp_hba_dbf_event_qdio(adapter, qdio_err, first, count); zfcp_qdio_handler_error(adapter, 140); return; } @@ -129,8 +127,7 @@ static void zfcp_qdio_resp_put_back(struct zfcp_adapter *adapter, int processed) count = atomic_read(&queue->count) + processed; - retval = do_QDIO(cdev, QDIO_FLAG_SYNC_INPUT | QDIO_FLAG_UNDER_INTERRUPT, - 0, start, count, NULL); + retval = do_QDIO(cdev, QDIO_FLAG_SYNC_INPUT, 0, start, count); if (unlikely(retval)) { atomic_set(&queue->count, count); @@ -142,9 +139,8 @@ static void zfcp_qdio_resp_put_back(struct zfcp_adapter *adapter, int processed) } } -static void zfcp_qdio_int_resp(struct ccw_device *cdev, unsigned int status, - unsigned int qdio_err, unsigned int siga_err, - unsigned int queue_no, int first, int count, +static void zfcp_qdio_int_resp(struct ccw_device *cdev, unsigned int qdio_err, + int queue_no, int first, int count, unsigned long parm) { struct zfcp_adapter *adapter = (struct zfcp_adapter *) parm; @@ -152,9 +148,8 @@ static void zfcp_qdio_int_resp(struct ccw_device *cdev, unsigned int status, volatile struct qdio_buffer_element *sbale; int sbal_idx, sbale_idx, sbal_no; - if (unlikely(status & QDIO_STATUS_LOOK_FOR_ERROR)) { - zfcp_hba_dbf_event_qdio(adapter, status, qdio_err, siga_err, - first, count); + if (unlikely(qdio_err)) { + zfcp_hba_dbf_event_qdio(adapter, qdio_err, first, count); zfcp_qdio_handler_error(adapter, 147); return; } @@ -362,7 +357,7 @@ int zfcp_qdio_send(struct zfcp_fsf_req *fsf_req) } retval = do_QDIO(adapter->ccw_device, QDIO_FLAG_SYNC_OUTPUT, 0, first, - count, NULL); + count); if (unlikely(retval)) { zfcp_qdio_zero_sbals(req_q->sbal, first, count); return retval; @@ -400,10 +395,6 @@ int zfcp_qdio_allocate(struct zfcp_adapter *adapter) init_data->qib_param_field = NULL; init_data->input_slib_elements = NULL; init_data->output_slib_elements = NULL; - init_data->min_input_threshold = 1; - init_data->max_input_threshold = 5000; - init_data->min_output_threshold = 1; - init_data->max_output_threshold = 1000; init_data->no_input_qs = 1; init_data->no_output_qs = 1; init_data->input_handler = zfcp_qdio_int_resp; @@ -436,9 +427,7 @@ void zfcp_qdio_close(struct zfcp_adapter *adapter) atomic_clear_mask(ZFCP_STATUS_ADAPTER_QDIOUP, &adapter->status); spin_unlock(&req_q->lock); - while (qdio_shutdown(adapter->ccw_device, QDIO_FLAG_CLEANUP_USING_CLEAR) - == -EINPROGRESS) - ssleep(1); + qdio_shutdown(adapter->ccw_device, QDIO_FLAG_CLEANUP_USING_CLEAR); /* cleanup used outbound sbals */ count = atomic_read(&req_q->count); @@ -473,7 +462,7 @@ int zfcp_qdio_open(struct zfcp_adapter *adapter) return -EIO; } - if (qdio_activate(adapter->ccw_device, 0)) { + if (qdio_activate(adapter->ccw_device)) { dev_err(&adapter->ccw_device->dev, "Activate of QDIO queues failed.\n"); goto failed_qdio; @@ -487,7 +476,7 @@ int zfcp_qdio_open(struct zfcp_adapter *adapter) } if (do_QDIO(adapter->ccw_device, QDIO_FLAG_SYNC_INPUT, 0, 0, - QDIO_MAX_BUFFERS_PER_Q, NULL)) { + QDIO_MAX_BUFFERS_PER_Q)) { dev_err(&adapter->ccw_device->dev, "Init of QDIO response queue failed.\n"); goto failed_qdio; @@ -501,9 +490,6 @@ int zfcp_qdio_open(struct zfcp_adapter *adapter) return 0; failed_qdio: - while (qdio_shutdown(adapter->ccw_device, QDIO_FLAG_CLEANUP_USING_CLEAR) - == -EINPROGRESS) - ssleep(1); - + qdio_shutdown(adapter->ccw_device, QDIO_FLAG_CLEANUP_USING_CLEAR); return -EIO; } diff --git a/include/asm-s390/qdio.h b/include/asm-s390/qdio.h index 11240342a0f4..6813772171f2 100644 --- a/include/asm-s390/qdio.h +++ b/include/asm-s390/qdio.h @@ -1,404 +1,382 @@ /* * linux/include/asm-s390/qdio.h * - * Linux for S/390 QDIO base support, Hipersocket base support - * version 2 - * - * Copyright 2000,2002 IBM Corporation + * Copyright 2000,2008 IBM Corp. * Author(s): Utz Bacher + * Jan Glauber * */ #ifndef __QDIO_H__ #define __QDIO_H__ -/* note, that most of the typedef's are from ingo. */ - #include #include #include -#define QDIO_NAME "qdio " - -#ifndef __s390x__ -#define QDIO_32_BIT -#endif /* __s390x__ */ - -/**** CONSTANTS, that are relied on without using these symbols *****/ -#define QDIO_MAX_QUEUES_PER_IRQ 32 /* used in width of unsigned int */ -/************************ END of CONSTANTS **************************/ -#define QDIO_MAX_BUFFERS_PER_Q 128 /* must be a power of 2 (%x=&(x-1)*/ -#define QDIO_BUF_ORDER 7 /* 2**this == number of pages used for sbals in 1 q */ -#define QDIO_MAX_ELEMENTS_PER_BUFFER 16 -#define SBAL_SIZE 256 - -#define QDIO_QETH_QFMT 0 -#define QDIO_ZFCP_QFMT 1 -#define QDIO_IQDIO_QFMT 2 -#define QDIO_IQDIO_QFMT_ASYNCH 3 - -struct qdio_buffer_element{ - unsigned int flags; - unsigned int length; -#ifdef QDIO_32_BIT - void *reserved; -#endif /* QDIO_32_BIT */ - void *addr; -} __attribute__ ((packed,aligned(16))); - -struct qdio_buffer{ - volatile struct qdio_buffer_element element[16]; -} __attribute__ ((packed,aligned(256))); - - -/* params are: ccw_device, status, qdio_error, siga_error, - queue_number, first element processed, number of elements processed, - int_parm */ -typedef void qdio_handler_t(struct ccw_device *,unsigned int,unsigned int, - unsigned int,unsigned int,int,int,unsigned long); - - -#define QDIO_STATUS_INBOUND_INT 0x01 -#define QDIO_STATUS_OUTBOUND_INT 0x02 -#define QDIO_STATUS_LOOK_FOR_ERROR 0x04 -#define QDIO_STATUS_MORE_THAN_ONE_QDIO_ERROR 0x08 -#define QDIO_STATUS_MORE_THAN_ONE_SIGA_ERROR 0x10 -#define QDIO_STATUS_ACTIVATE_CHECK_CONDITION 0x20 - -#define QDIO_SIGA_ERROR_ACCESS_EXCEPTION 0x10 -#define QDIO_SIGA_ERROR_B_BIT_SET 0x20 - -/* for qdio_initialize */ -#define QDIO_INBOUND_0COPY_SBALS 0x01 -#define QDIO_OUTBOUND_0COPY_SBALS 0x02 -#define QDIO_USE_OUTBOUND_PCIS 0x04 - -/* for qdio_cleanup */ -#define QDIO_FLAG_CLEANUP_USING_CLEAR 0x01 -#define QDIO_FLAG_CLEANUP_USING_HALT 0x02 - -struct qdio_initialize { - struct ccw_device *cdev; - unsigned char q_format; - unsigned char adapter_name[8]; - unsigned int qib_param_field_format; /*adapter dependent*/ - /* pointer to 128 bytes or NULL, if no param field */ - unsigned char *qib_param_field; /* adapter dependent */ - /* pointer to no_queues*128 words of data or NULL */ - unsigned long *input_slib_elements; - unsigned long *output_slib_elements; - unsigned int min_input_threshold; - unsigned int max_input_threshold; - unsigned int min_output_threshold; - unsigned int max_output_threshold; - unsigned int no_input_qs; - unsigned int no_output_qs; - qdio_handler_t *input_handler; - qdio_handler_t *output_handler; - unsigned long int_parm; - unsigned long flags; - void **input_sbal_addr_array; /* addr of n*128 void ptrs */ - void **output_sbal_addr_array; /* addr of n*128 void ptrs */ -}; - -extern int qdio_initialize(struct qdio_initialize *init_data); -extern int qdio_allocate(struct qdio_initialize *init_data); -extern int qdio_establish(struct qdio_initialize *init_data); - -extern int qdio_activate(struct ccw_device *,int flags); - -#define QDIO_STATE_MUST_USE_OUTB_PCI 0x00000001 -#define QDIO_STATE_INACTIVE 0x00000002 /* after qdio_cleanup */ -#define QDIO_STATE_ESTABLISHED 0x00000004 /* after qdio_initialize */ -#define QDIO_STATE_ACTIVE 0x00000008 /* after qdio_activate */ -#define QDIO_STATE_STOPPED 0x00000010 /* after queues went down */ -extern unsigned long qdio_get_status(int irq); - - -#define QDIO_FLAG_SYNC_INPUT 0x01 -#define QDIO_FLAG_SYNC_OUTPUT 0x02 -#define QDIO_FLAG_UNDER_INTERRUPT 0x04 -#define QDIO_FLAG_NO_INPUT_INTERRUPT_CONTEXT 0x08 /* no effect on - adapter interrupts */ -#define QDIO_FLAG_DONT_SIGA 0x10 -#define QDIO_FLAG_PCI_OUT 0x20 - -extern int do_QDIO(struct ccw_device*, unsigned int flags, - unsigned int queue_number, - unsigned int qidx,unsigned int count, - struct qdio_buffer *buffers); - -extern int qdio_get_ssqd_pct(struct ccw_device*); -extern int qdio_synchronize(struct ccw_device*, unsigned int flags, - unsigned int queue_number); - -extern int qdio_cleanup(struct ccw_device*, int how); -extern int qdio_shutdown(struct ccw_device*, int how); -extern int qdio_free(struct ccw_device*); - -unsigned char qdio_get_slsb_state(struct ccw_device*, unsigned int flag, - unsigned int queue_number, - unsigned int qidx); - -extern void qdio_init_scrubber(void); - +#define QDIO_MAX_QUEUES_PER_IRQ 32 +#define QDIO_MAX_BUFFERS_PER_Q 128 +#define QDIO_MAX_BUFFERS_MASK (QDIO_MAX_BUFFERS_PER_Q - 1) +#define QDIO_MAX_ELEMENTS_PER_BUFFER 16 +#define QDIO_SBAL_SIZE 256 + +#define QDIO_QETH_QFMT 0 +#define QDIO_ZFCP_QFMT 1 +#define QDIO_IQDIO_QFMT 2 + +/** + * struct qdesfmt0 - queue descriptor, format 0 + * @sliba: storage list information block address + * @sla: storage list address + * @slsba: storage list state block address + * @akey: access key for DLIB + * @bkey: access key for SL + * @ckey: access key for SBALs + * @dkey: access key for SLSB + */ struct qdesfmt0 { -#ifdef QDIO_32_BIT - unsigned long res1; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long sliba; /* storage-list-information-block - address */ -#ifdef QDIO_32_BIT - unsigned long res2; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long sla; /* storage-list address */ -#ifdef QDIO_32_BIT - unsigned long res3; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long slsba; /* storage-list-state-block address */ - unsigned int res4; /* reserved */ - unsigned int akey : 4; /* access key for DLIB */ - unsigned int bkey : 4; /* access key for SL */ - unsigned int ckey : 4; /* access key for SBALs */ - unsigned int dkey : 4; /* access key for SLSB */ - unsigned int res5 : 16; /* reserved */ + u64 sliba; + u64 sla; + u64 slsba; + u32 : 32; + u32 akey : 4; + u32 bkey : 4; + u32 ckey : 4; + u32 dkey : 4; + u32 : 16; } __attribute__ ((packed)); -/* - * Queue-Description record (QDR) +/** + * struct qdr - queue description record (QDR) + * @qfmt: queue format + * @pfmt: implementation dependent parameter format + * @ac: adapter characteristics + * @iqdcnt: input queue descriptor count + * @oqdcnt: output queue descriptor count + * @iqdsz: inpout queue descriptor size + * @oqdsz: output queue descriptor size + * @qiba: queue information block address + * @qkey: queue information block key + * @qdf0: queue descriptions */ struct qdr { - unsigned int qfmt : 8; /* queue format */ - unsigned int pfmt : 8; /* impl. dep. parameter format */ - unsigned int res1 : 8; /* reserved */ - unsigned int ac : 8; /* adapter characteristics */ - unsigned int res2 : 8; /* reserved */ - unsigned int iqdcnt : 8; /* input-queue-descriptor count */ - unsigned int res3 : 8; /* reserved */ - unsigned int oqdcnt : 8; /* output-queue-descriptor count */ - unsigned int res4 : 8; /* reserved */ - unsigned int iqdsz : 8; /* input-queue-descriptor size */ - unsigned int res5 : 8; /* reserved */ - unsigned int oqdsz : 8; /* output-queue-descriptor size */ - unsigned int res6[9]; /* reserved */ -#ifdef QDIO_32_BIT - unsigned long res7; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long qiba; /* queue-information-block address */ - unsigned int res8; /* reserved */ - unsigned int qkey : 4; /* queue-information-block key */ - unsigned int res9 : 28; /* reserved */ -/* union _qd {*/ /* why this? */ - struct qdesfmt0 qdf0[126]; -/* } qd;*/ -} __attribute__ ((packed,aligned(4096))); - - -/* - * queue information block (QIB) - */ -#define QIB_AC_INBOUND_PCI_SUPPORTED 0x80 -#define QIB_AC_OUTBOUND_PCI_SUPPORTED 0x40 + u32 qfmt : 8; + u32 pfmt : 8; + u32 : 8; + u32 ac : 8; + u32 : 8; + u32 iqdcnt : 8; + u32 : 8; + u32 oqdcnt : 8; + u32 : 8; + u32 iqdsz : 8; + u32 : 8; + u32 oqdsz : 8; + /* private: */ + u32 res[9]; + /* public: */ + u64 qiba; + u32 : 32; + u32 qkey : 4; + u32 : 28; + struct qdesfmt0 qdf0[126]; +} __attribute__ ((packed, aligned(4096))); + +#define QIB_AC_OUTBOUND_PCI_SUPPORTED 0x40 #define QIB_RFLAGS_ENABLE_QEBSM 0x80 +/** + * struct qib - queue information block (QIB) + * @qfmt: queue format + * @pfmt: implementation dependent parameter format + * @rflags: QEBSM + * @ac: adapter characteristics + * @isliba: absolute address of first input SLIB + * @osliba: absolute address of first output SLIB + * @ebcnam: adapter identifier in EBCDIC + * @parm: implementation dependent parameters + */ struct qib { - unsigned int qfmt : 8; /* queue format */ - unsigned int pfmt : 8; /* impl. dep. parameter format */ - unsigned int rflags : 8; /* QEBSM */ - unsigned int ac : 8; /* adapter characteristics */ - unsigned int res2; /* reserved */ -#ifdef QDIO_32_BIT - unsigned long res3; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long isliba; /* absolute address of 1st - input SLIB */ -#ifdef QDIO_32_BIT - unsigned long res4; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long osliba; /* absolute address of 1st - output SLIB */ - unsigned int res5; /* reserved */ - unsigned int res6; /* reserved */ - unsigned char ebcnam[8]; /* adapter identifier in EBCDIC */ - unsigned char res7[88]; /* reserved */ - unsigned char parm[QDIO_MAX_BUFFERS_PER_Q]; - /* implementation dependent - parameters */ -} __attribute__ ((packed,aligned(256))); - - -/* - * storage-list-information block element (SLIBE) + u32 qfmt : 8; + u32 pfmt : 8; + u32 rflags : 8; + u32 ac : 8; + u32 : 32; + u64 isliba; + u64 osliba; + u32 : 32; + u32 : 32; + u8 ebcnam[8]; + /* private: */ + u8 res[88]; + /* public: */ + u8 parm[QDIO_MAX_BUFFERS_PER_Q]; +} __attribute__ ((packed, aligned(256))); + +/** + * struct slibe - storage list information block element (SLIBE) + * @parms: implementation dependent parameters */ struct slibe { -#ifdef QDIO_32_BIT - unsigned long res; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long parms; /* implementation dependent - parameters */ + u64 parms; }; -/* - * storage-list-information block (SLIB) +/** + * struct slib - storage list information block (SLIB) + * @nsliba: next SLIB address (if any) + * @sla: SL address + * @slsba: SLSB address + * @slibe: SLIB elements */ struct slib { -#ifdef QDIO_32_BIT - unsigned long res1; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long nsliba; /* next SLIB address (if any) */ -#ifdef QDIO_32_BIT - unsigned long res2; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long sla; /* SL address */ -#ifdef QDIO_32_BIT - unsigned long res3; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long slsba; /* SLSB address */ - unsigned char res4[1000]; /* reserved */ - struct slibe slibe[QDIO_MAX_BUFFERS_PER_Q]; /* SLIB elements */ -} __attribute__ ((packed,aligned(2048))); - + u64 nsliba; + u64 sla; + u64 slsba; + /* private: */ + u8 res[1000]; + /* public: */ + struct slibe slibe[QDIO_MAX_BUFFERS_PER_Q]; +} __attribute__ ((packed, aligned(2048))); + +/** + * struct sbal_flags - storage block address list flags + * @last: last entry + * @cont: contiguous storage + * @frag: fragmentation + */ struct sbal_flags { - unsigned char res1 : 1; /* reserved */ - unsigned char last : 1; /* last entry */ - unsigned char cont : 1; /* contiguous storage */ - unsigned char res2 : 1; /* reserved */ - unsigned char frag : 2; /* fragmentation (s.below) */ - unsigned char res3 : 2; /* reserved */ + u8 : 1; + u8 last : 1; + u8 cont : 1; + u8 : 1; + u8 frag : 2; + u8 : 2; } __attribute__ ((packed)); -#define SBAL_FLAGS_FIRST_FRAG 0x04000000UL -#define SBAL_FLAGS_MIDDLE_FRAG 0x08000000UL -#define SBAL_FLAGS_LAST_FRAG 0x0c000000UL -#define SBAL_FLAGS_LAST_ENTRY 0x40000000UL -#define SBAL_FLAGS_CONTIGUOUS 0x20000000UL +#define SBAL_FLAGS_FIRST_FRAG 0x04000000UL +#define SBAL_FLAGS_MIDDLE_FRAG 0x08000000UL +#define SBAL_FLAGS_LAST_FRAG 0x0c000000UL +#define SBAL_FLAGS_LAST_ENTRY 0x40000000UL +#define SBAL_FLAGS_CONTIGUOUS 0x20000000UL -#define SBAL_FLAGS0_DATA_CONTINUATION 0x20UL +#define SBAL_FLAGS0_DATA_CONTINUATION 0x20UL /* Awesome OpenFCP extensions */ -#define SBAL_FLAGS0_TYPE_STATUS 0x00UL -#define SBAL_FLAGS0_TYPE_WRITE 0x08UL -#define SBAL_FLAGS0_TYPE_READ 0x10UL -#define SBAL_FLAGS0_TYPE_WRITE_READ 0x18UL -#define SBAL_FLAGS0_MORE_SBALS 0x04UL -#define SBAL_FLAGS0_COMMAND 0x02UL -#define SBAL_FLAGS0_LAST_SBAL 0x00UL -#define SBAL_FLAGS0_ONLY_SBAL SBAL_FLAGS0_COMMAND -#define SBAL_FLAGS0_MIDDLE_SBAL SBAL_FLAGS0_MORE_SBALS -#define SBAL_FLAGS0_FIRST_SBAL SBAL_FLAGS0_MORE_SBALS | SBAL_FLAGS0_COMMAND -/* Naught of interest beyond this point */ - -#define SBAL_FLAGS0_PCI 0x40 +#define SBAL_FLAGS0_TYPE_STATUS 0x00UL +#define SBAL_FLAGS0_TYPE_WRITE 0x08UL +#define SBAL_FLAGS0_TYPE_READ 0x10UL +#define SBAL_FLAGS0_TYPE_WRITE_READ 0x18UL +#define SBAL_FLAGS0_MORE_SBALS 0x04UL +#define SBAL_FLAGS0_COMMAND 0x02UL +#define SBAL_FLAGS0_LAST_SBAL 0x00UL +#define SBAL_FLAGS0_ONLY_SBAL SBAL_FLAGS0_COMMAND +#define SBAL_FLAGS0_MIDDLE_SBAL SBAL_FLAGS0_MORE_SBALS +#define SBAL_FLAGS0_FIRST_SBAL SBAL_FLAGS0_MORE_SBALS | SBAL_FLAGS0_COMMAND +#define SBAL_FLAGS0_PCI 0x40 + +/** + * struct sbal_sbalf_0 - sbal flags for sbale 0 + * @pci: PCI indicator + * @cont: data continuation + * @sbtype: storage-block type (FCP) + */ struct sbal_sbalf_0 { - unsigned char res1 : 1; /* reserved */ - unsigned char pci : 1; /* PCI indicator */ - unsigned char cont : 1; /* data continuation */ - unsigned char sbtype: 2; /* storage-block type (OpenFCP) */ - unsigned char res2 : 3; /* reserved */ + u8 : 1; + u8 pci : 1; + u8 cont : 1; + u8 sbtype : 2; + u8 : 3; } __attribute__ ((packed)); +/** + * struct sbal_sbalf_1 - sbal flags for sbale 1 + * @key: storage key + */ struct sbal_sbalf_1 { - unsigned char res1 : 4; /* reserved */ - unsigned char key : 4; /* storage key */ + u8 : 4; + u8 key : 4; } __attribute__ ((packed)); +/** + * struct sbal_sbalf_14 - sbal flags for sbale 14 + * @erridx: error index + */ struct sbal_sbalf_14 { - unsigned char res1 : 4; /* reserved */ - unsigned char erridx : 4; /* error index */ + u8 : 4; + u8 erridx : 4; } __attribute__ ((packed)); +/** + * struct sbal_sbalf_15 - sbal flags for sbale 15 + * @reason: reason for error state + */ struct sbal_sbalf_15 { - unsigned char reason; /* reserved */ + u8 reason; } __attribute__ ((packed)); +/** + * union sbal_sbalf - storage block address list flags + * @i0: sbalf0 + * @i1: sbalf1 + * @i14: sbalf14 + * @i15: sblaf15 + * @value: raw value + */ union sbal_sbalf { struct sbal_sbalf_0 i0; struct sbal_sbalf_1 i1; struct sbal_sbalf_14 i14; struct sbal_sbalf_15 i15; - unsigned char value; + u8 value; }; -struct sbal_element { - union { - struct sbal_flags bits; /* flags */ - unsigned char value; - } flags; - unsigned int res1 : 16; /* reserved */ - union sbal_sbalf sbalf; /* SBAL flags */ - unsigned int res2 : 16; /* reserved */ - unsigned int count : 16; /* data count */ -#ifdef QDIO_32_BIT - unsigned long res3; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long addr; /* absolute data address */ -} __attribute__ ((packed,aligned(16))); +/** + * struct qdio_buffer_element - SBAL entry + * @flags: flags + * @length: length + * @addr: address +*/ +struct qdio_buffer_element { + u32 flags; + u32 length; +#ifdef CONFIG_32BIT + /* private: */ + void *reserved; + /* public: */ +#endif + void *addr; +} __attribute__ ((packed, aligned(16))); -/* - * strorage-block access-list (SBAL) +/** + * struct qdio_buffer - storage block address list (SBAL) + * @element: SBAL entries */ -struct sbal { - struct sbal_element element[QDIO_MAX_ELEMENTS_PER_BUFFER]; -} __attribute__ ((packed,aligned(256))); +struct qdio_buffer { + struct qdio_buffer_element element[QDIO_MAX_ELEMENTS_PER_BUFFER]; +} __attribute__ ((packed, aligned(256))); -/* - * storage-list (SL) +/** + * struct sl_element - storage list entry + * @sbal: absolute SBAL address */ struct sl_element { -#ifdef QDIO_32_BIT - unsigned long res; /* reserved */ -#endif /* QDIO_32_BIT */ - unsigned long sbal; /* absolute SBAL address */ +#ifdef CONFIG_32BIT + /* private: */ + unsigned long reserved; + /* public: */ +#endif + unsigned long sbal; } __attribute__ ((packed)); +/** + * struct sl - storage list (SL) + * @element: SL entries + */ struct sl { struct sl_element element[QDIO_MAX_BUFFERS_PER_Q]; -} __attribute__ ((packed,aligned(1024))); +} __attribute__ ((packed, aligned(1024))); -/* - * storage-list-state block (SLSB) +/** + * struct slsb - storage list state block (SLSB) + * @val: state per buffer */ -struct slsb_flags { - unsigned char owner : 2; /* SBAL owner */ - unsigned char type : 1; /* buffer type */ - unsigned char state : 5; /* processing state */ +struct slsb { + u8 val[QDIO_MAX_BUFFERS_PER_Q]; +} __attribute__ ((packed, aligned(256))); + +struct qdio_ssqd_desc { + u8 flags; + u8:8; + u16 sch; + u8 qfmt; + u8 parm; + u8 qdioac1; + u8 sch_class; + u8 pcnt; + u8 icnt; + u8:8; + u8 ocnt; + u8:8; + u8 mbccnt; + u16 qdioac2; + u64 sch_token; + u64:64; } __attribute__ ((packed)); +/* params are: ccw_device, qdio_error, queue_number, + first element processed, number of elements processed, int_parm */ +typedef void qdio_handler_t(struct ccw_device *, unsigned int, int, + int, int, unsigned long); -struct slsb { - union { - unsigned char val[QDIO_MAX_BUFFERS_PER_Q]; - struct slsb_flags flags[QDIO_MAX_BUFFERS_PER_Q]; - } acc; -} __attribute__ ((packed,aligned(256))); +/* qdio errors reported to the upper-layer program */ +#define QDIO_ERROR_SIGA_ACCESS_EXCEPTION 0x10 +#define QDIO_ERROR_SIGA_BUSY 0x20 +#define QDIO_ERROR_ACTIVATE_CHECK_CONDITION 0x40 +#define QDIO_ERROR_SLSB_STATE 0x80 -/* - * SLSB values +/* for qdio_initialize */ +#define QDIO_INBOUND_0COPY_SBALS 0x01 +#define QDIO_OUTBOUND_0COPY_SBALS 0x02 +#define QDIO_USE_OUTBOUND_PCIS 0x04 + +/* for qdio_cleanup */ +#define QDIO_FLAG_CLEANUP_USING_CLEAR 0x01 +#define QDIO_FLAG_CLEANUP_USING_HALT 0x02 + +/** + * struct qdio_initialize - qdio initalization data + * @cdev: associated ccw device + * @q_format: queue format + * @adapter_name: name for the adapter + * @qib_param_field_format: format for qib_parm_field + * @qib_param_field: pointer to 128 bytes or NULL, if no param field + * @input_slib_elements: pointer to no_input_qs * 128 words of data or NULL + * @output_slib_elements: pointer to no_output_qs * 128 words of data or NULL + * @no_input_qs: number of input queues + * @no_output_qs: number of output queues + * @input_handler: handler to be called for input queues + * @output_handler: handler to be called for output queues + * @int_parm: interruption parameter + * @flags: initialization flags + * @input_sbal_addr_array: address of no_input_qs * 128 pointers + * @output_sbal_addr_array: address of no_output_qs * 128 pointers */ -#define SLSB_OWNER_PROG 1 -#define SLSB_OWNER_CU 2 - -#define SLSB_TYPE_INPUT 0 -#define SLSB_TYPE_OUTPUT 1 - -#define SLSB_STATE_NOT_INIT 0 -#define SLSB_STATE_EMPTY 1 -#define SLSB_STATE_PRIMED 2 -#define SLSB_STATE_HALTED 0xe -#define SLSB_STATE_ERROR 0xf - -#define SLSB_P_INPUT_NOT_INIT 0x80 -#define SLSB_P_INPUT_PROCESSING 0x81 -#define SLSB_CU_INPUT_EMPTY 0x41 -#define SLSB_P_INPUT_PRIMED 0x82 -#define SLSB_P_INPUT_HALTED 0x8E -#define SLSB_P_INPUT_ERROR 0x8F - -#define SLSB_P_OUTPUT_NOT_INIT 0xA0 -#define SLSB_P_OUTPUT_EMPTY 0xA1 -#define SLSB_CU_OUTPUT_PRIMED 0x62 -#define SLSB_P_OUTPUT_HALTED 0xAE -#define SLSB_P_OUTPUT_ERROR 0xAF - -#define SLSB_ERROR_DURING_LOOKUP 0xFF +struct qdio_initialize { + struct ccw_device *cdev; + unsigned char q_format; + unsigned char adapter_name[8]; + unsigned int qib_param_field_format; + unsigned char *qib_param_field; + unsigned long *input_slib_elements; + unsigned long *output_slib_elements; + unsigned int no_input_qs; + unsigned int no_output_qs; + qdio_handler_t *input_handler; + qdio_handler_t *output_handler; + unsigned long int_parm; + unsigned long flags; + void **input_sbal_addr_array; + void **output_sbal_addr_array; +}; + +#define QDIO_STATE_INACTIVE 0x00000002 /* after qdio_cleanup */ +#define QDIO_STATE_ESTABLISHED 0x00000004 /* after qdio_establish */ +#define QDIO_STATE_ACTIVE 0x00000008 /* after qdio_activate */ +#define QDIO_STATE_STOPPED 0x00000010 /* after queues went down */ + +#define QDIO_FLAG_SYNC_INPUT 0x01 +#define QDIO_FLAG_SYNC_OUTPUT 0x02 +#define QDIO_FLAG_PCI_OUT 0x10 + +extern int qdio_initialize(struct qdio_initialize *init_data); +extern int qdio_allocate(struct qdio_initialize *init_data); +extern int qdio_establish(struct qdio_initialize *init_data); +extern int qdio_activate(struct ccw_device *); + +extern int do_QDIO(struct ccw_device*, unsigned int flags, + int q_nr, int qidx, int count); +extern int qdio_cleanup(struct ccw_device*, int how); +extern int qdio_shutdown(struct ccw_device*, int how); +extern int qdio_free(struct ccw_device *); +extern struct qdio_ssqd_desc *qdio_get_ssqd_desc(struct ccw_device *cdev); #endif /* __QDIO_H__ */ diff --git a/include/asm-s390/setup.h b/include/asm-s390/setup.h index f09ee3f72977..4ba14e463e83 100644 --- a/include/asm-s390/setup.h +++ b/include/asm-s390/setup.h @@ -65,6 +65,7 @@ extern unsigned long machine_flags; #define MACHINE_FLAG_VM (1UL << 0) #define MACHINE_FLAG_IEEE (1UL << 1) +#define MACHINE_FLAG_P390 (1UL << 2) #define MACHINE_FLAG_CSP (1UL << 3) #define MACHINE_FLAG_MVPG (1UL << 4) #define MACHINE_FLAG_DIAG44 (1UL << 5) @@ -77,7 +78,6 @@ extern unsigned long machine_flags; #define MACHINE_IS_VM (machine_flags & MACHINE_FLAG_VM) #define MACHINE_IS_KVM (machine_flags & MACHINE_FLAG_KVM) -#define MACHINE_IS_P390 (machine_flags & MACHINE_FLAG_P390) #define MACHINE_HAS_DIAG9C (machine_flags & MACHINE_FLAG_DIAG9C) #ifndef __s390x__ -- cgit v1.2.3 From 2567d71cc7acd99f0a0dd02e17fe17fd7df7b30c Mon Sep 17 00:00:00 2001 From: Rusty Russell Date: Tue, 15 Jul 2008 15:02:27 +1000 Subject: x86: fix asm/e820.h for userspace inclusion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit asm-x86/e820.h is included from userspace. 'x86: make e820.c to have common functions' (b79cd8f1268bab57ff85b19d131f7f23deab2dee) broke it: make -C Documentation/lguest cc -Wall -Wmissing-declarations -Wmissing-prototypes -O3 -I../../include lguest.c -lz -o lguest In file included from ../../include/asm-x86/bootparam.h:8, from lguest.c:45: ../../include/asm/e820.h:66: error: expected ‘)’ before ‘start’ ../../include/asm/e820.h:67: error: expected ‘)’ before ‘start’ ../../include/asm/e820.h:68: error: expected ‘)’ before ‘start’ ../../include/asm/e820.h:72: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’ before ‘e820_update_range’ ... Signed-off-by: Rusty Russell Cc: Yinghai Lu Signed-off-by: Ingo Molnar --- include/asm-x86/e820.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-x86/e820.h b/include/asm-x86/e820.h index 33e793e991d0..06633b01dd5b 100644 --- a/include/asm-x86/e820.h +++ b/include/asm-x86/e820.h @@ -59,6 +59,7 @@ struct e820map { struct e820entry map[E820_X_MAX]; }; +#ifdef __KERNEL__ /* see comment in arch/x86/kernel/e820.c */ extern struct e820map e820; extern struct e820map e820_saved; @@ -115,7 +116,7 @@ extern void setup_memory_map(void); extern char *default_machine_specific_memory_setup(void); extern char *machine_specific_memory_setup(void); extern char *memory_setup(void); - +#endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ #define ISA_START_ADDRESS 0xa0000 -- cgit v1.2.3