From 1b2e2b73b4c84c918686c04a00724197036c0847 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 21 Aug 2006 17:06:38 +0100 Subject: [ARM] Cleanup arch/arm/mm a little Move top_pmd into arch/arm/mm/mm.h - nothing outside arch/arm/mm references it. Move the repeated definition of TOP_PTE into mm/mm.h, as well as a few function prototypes. Signed-off-by: Russell King --- include/asm-arm/page.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h index b721270b9986..af9c3fe7588c 100644 --- a/include/asm-arm/page.h +++ b/include/asm-arm/page.h @@ -174,9 +174,6 @@ typedef unsigned long pgprot_t; #endif /* STRICT_MM_TYPECHECKS */ -/* the upper-most page table pointer */ -extern pmd_t *top_pmd; - #endif /* CONFIG_MMU */ #include -- cgit v1.2.3 From 7ad1bcb25c5623f1f87c50fdf2272f58ff91db5a Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 27 Aug 2006 12:07:02 +0100 Subject: [ARM] Add ARM irqtrace support This adds support for irqtrace for lockdep on ARM. Signed-off-by: Russell King --- arch/arm/Kconfig | 4 ++ arch/arm/kernel/entry-armv.S | 13 +++++ include/asm-arm/irqflags.h | 132 +++++++++++++++++++++++++++++++++++++++++++ include/asm-arm/system.h | 125 +--------------------------------------- 4 files changed, 150 insertions(+), 124 deletions(-) create mode 100644 include/asm-arm/irqflags.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f81a62380add..d9376f048ed7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -51,6 +51,10 @@ config GENERIC_HARDIRQS bool default y +config TRACE_IRQFLAGS_SUPPORT + bool + default y + config HARDIRQS_SW_RESEND bool default y diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index de4e33137901..bd623b73445f 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -191,6 +191,9 @@ __dabt_svc: __irq_svc: svc_entry +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif #ifdef CONFIG_PREEMPT get_thread_info tsk ldr r8, [tsk, #TI_PREEMPT] @ get preempt count @@ -211,6 +214,10 @@ preempt_return: #endif ldr r0, [sp, #S_PSR] @ irqs are already disabled msr spsr_cxsf, r0 +#ifdef CONFIG_TRACE_IRQFLAGS + tst r0, #PSR_I_BIT + bleq trace_hardirqs_on +#endif ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr .ltorg @@ -398,6 +405,9 @@ __dabt_usr: __irq_usr: usr_entry +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif get_thread_info tsk #ifdef CONFIG_PREEMPT ldr r8, [tsk, #TI_PREEMPT] @ get preempt count @@ -412,6 +422,9 @@ __irq_usr: teq r0, r7 strne r0, [r0, -r0] #endif +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_on +#endif mov why, #0 b ret_to_user diff --git a/include/asm-arm/irqflags.h b/include/asm-arm/irqflags.h new file mode 100644 index 000000000000..6d09974e6646 --- /dev/null +++ b/include/asm-arm/irqflags.h @@ -0,0 +1,132 @@ +#ifndef __ASM_ARM_IRQFLAGS_H +#define __ASM_ARM_IRQFLAGS_H + +#ifdef __KERNEL__ + +#include + +/* + * CPU interrupt mask handling. + */ +#if __LINUX_ARM_ARCH__ >= 6 + +#define raw_local_irq_save(x) \ + ({ \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_save\n" \ + "cpsid i" \ + : "=r" (x) : : "memory", "cc"); \ + }) + +#define raw_local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc") +#define raw_local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc") +#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc") +#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc") + +#else + +/* + * Save the current interrupt enable state & disable IRQs + */ +#define raw_local_irq_save(x) \ + ({ \ + unsigned long temp; \ + (void) (&temp == &x); \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_save\n" \ +" orr %1, %0, #128\n" \ +" msr cpsr_c, %1" \ + : "=r" (x), "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +/* + * Enable IRQs + */ +#define raw_local_irq_enable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_enable\n" \ +" bic %0, %0, #128\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +/* + * Disable IRQs + */ +#define raw_local_irq_disable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_disable\n" \ +" orr %0, %0, #128\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +/* + * Enable FIQs + */ +#define local_fiq_enable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ stf\n" \ +" bic %0, %0, #64\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +/* + * Disable FIQs + */ +#define local_fiq_disable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ clf\n" \ +" orr %0, %0, #64\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +#endif + +/* + * Save the current interrupt enable state. + */ +#define raw_local_save_flags(x) \ + ({ \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_save_flags" \ + : "=r" (x) : : "memory", "cc"); \ + }) + +/* + * restore saved IRQ & FIQ state + */ +#define raw_local_irq_restore(x) \ + __asm__ __volatile__( \ + "msr cpsr_c, %0 @ local_irq_restore\n" \ + : \ + : "r" (x) \ + : "memory", "cc") + +#define raw_irqs_disabled_flags(flags) \ +({ \ + (int)((flags) & PSR_I_BIT); \ +}) + +#endif +#endif diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 0947cbf9b69a..174ff52661b0 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -207,130 +207,7 @@ static inline void sched_cacheflush(void) { } -/* - * CPU interrupt mask handling. - */ -#if __LINUX_ARM_ARCH__ >= 6 - -#define local_irq_save(x) \ - ({ \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_save\n" \ - "cpsid i" \ - : "=r" (x) : : "memory", "cc"); \ - }) - -#define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc") -#define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc") -#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc") -#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc") - -#else - -/* - * Save the current interrupt enable state & disable IRQs - */ -#define local_irq_save(x) \ - ({ \ - unsigned long temp; \ - (void) (&temp == &x); \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_save\n" \ -" orr %1, %0, #128\n" \ -" msr cpsr_c, %1" \ - : "=r" (x), "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -/* - * Enable IRQs - */ -#define local_irq_enable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_enable\n" \ -" bic %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -/* - * Disable IRQs - */ -#define local_irq_disable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_disable\n" \ -" orr %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -/* - * Enable FIQs - */ -#define local_fiq_enable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ stf\n" \ -" bic %0, %0, #64\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -/* - * Disable FIQs - */ -#define local_fiq_disable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ clf\n" \ -" orr %0, %0, #64\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -#endif - -/* - * Save the current interrupt enable state. - */ -#define local_save_flags(x) \ - ({ \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_save_flags" \ - : "=r" (x) : : "memory", "cc"); \ - }) - -/* - * restore saved IRQ & FIQ state - */ -#define local_irq_restore(x) \ - __asm__ __volatile__( \ - "msr cpsr_c, %0 @ local_irq_restore\n" \ - : \ - : "r" (x) \ - : "memory", "cc") - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - (int)(flags & PSR_I_BIT); \ -}) +#include #ifdef CONFIG_SMP -- cgit v1.2.3 From 6a39dd6222dda5ee2414a1b42e8e62118742a49e Mon Sep 17 00:00:00 2001 From: Daniel Jacobowitz Date: Wed, 30 Aug 2006 15:02:08 +0100 Subject: [ARM] 3759/2: Remove uses of %? Patch from Daniel Jacobowitz The ARM kernel has several uses of asm("foo%?"). %? is a GCC internal modifier used to output conditional execution predicates. However, no version of GCC supports conditionalizing asm statements. GCC 4.2 will correctly expand %? to the empty string in user asms. Earlier versions may reuse the condition from the previous instruction. In 'if (foo) asm ("bar%?");' this is somewhat likely to be right... but not reliable. So, the only safe thing to do is to remove the uses of %?. I believe the tlbflush.h occurances were supposed to be removed before, based on the comment about %? not working at the top of that file. Old versions of GCC could omit branches around user asms if the asm didn't mark the condition codes as clobbered. This problem hasn't been seen on any recent (3.x or 4.x) GCC, but it could theoretically happen. So, where %? was removed a cc clobber was added. Signed-off-by: Daniel Jacobowitz Signed-off-by: Russell King --- arch/arm/kernel/traps.c | 2 +- arch/arm/mach-footbridge/dc21285.c | 27 ++++++++------ arch/arm/vfp/vfpinstr.h | 8 ++-- include/asm-arm/arch-l7200/io.h | 8 ++-- include/asm-arm/tlbflush.h | 76 +++++++++++++++++++------------------- 5 files changed, 62 insertions(+), 59 deletions(-) (limited to 'include') diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index aeeed806f991..bede380c07a9 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -191,7 +191,7 @@ void show_stack(struct task_struct *tsk, unsigned long *sp) if (tsk != current) fp = thread_saved_fp(tsk); else - asm("mov%? %0, fp" : "=r" (fp)); + asm("mov %0, fp" : "=r" (fp) : : "cc"); c_backtrace(fp, 0x10); barrier(); diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index 823e25d4547e..a1ae49df5c3b 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -69,16 +69,16 @@ dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where, if (addr) switch (size) { case 1: - asm("ldr%?b %0, [%1, %2]" - : "=r" (v) : "r" (addr), "r" (where)); + asm("ldrb %0, [%1, %2]" + : "=r" (v) : "r" (addr), "r" (where) : "cc"); break; case 2: - asm("ldr%?h %0, [%1, %2]" - : "=r" (v) : "r" (addr), "r" (where)); + asm("ldrh %0, [%1, %2]" + : "=r" (v) : "r" (addr), "r" (where) : "cc"); break; case 4: - asm("ldr%? %0, [%1, %2]" - : "=r" (v) : "r" (addr), "r" (where)); + asm("ldr %0, [%1, %2]" + : "=r" (v) : "r" (addr), "r" (where) : "cc"); break; } @@ -103,16 +103,19 @@ dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where, if (addr) switch (size) { case 1: - asm("str%?b %0, [%1, %2]" - : : "r" (value), "r" (addr), "r" (where)); + asm("strb %0, [%1, %2]" + : : "r" (value), "r" (addr), "r" (where) + : "cc"); break; case 2: - asm("str%?h %0, [%1, %2]" - : : "r" (value), "r" (addr), "r" (where)); + asm("strh %0, [%1, %2]" + : : "r" (value), "r" (addr), "r" (where) + : "cc"); break; case 4: - asm("str%? %0, [%1, %2]" - : : "r" (value), "r" (addr), "r" (where)); + asm("str %0, [%1, %2]" + : : "r" (value), "r" (addr), "r" (where) + : "cc"); break; } diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h index 6c819aeae006..7f343a4beca0 100644 --- a/arch/arm/vfp/vfpinstr.h +++ b/arch/arm/vfp/vfpinstr.h @@ -73,14 +73,14 @@ #define fmrx(_vfp_) ({ \ u32 __v; \ - asm("mrc%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \ - : "=r" (__v)); \ + asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \ + : "=r" (__v) : : "cc"); \ __v; \ }) #define fmxr(_vfp_,_var_) \ - asm("mcr%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \ - : : "r" (_var_)) + asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \ + : : "r" (_var_) : "cc") u32 vfp_single_cpdo(u32 inst, u32 fpscr); u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs); diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h index cd080d8384d9..d744d97c18a5 100644 --- a/include/asm-arm/arch-l7200/io.h +++ b/include/asm-arm/arch-l7200/io.h @@ -31,9 +31,9 @@ static inline unsigned int __arch_getw(unsigned long a) { unsigned int value; - __asm__ __volatile__("ldr%?h %0, [%1, #0] @ getw" + __asm__ __volatile__("ldrh %0, [%1, #0] @ getw" : "=&r" (value) - : "r" (a)); + : "r" (a) : "cc"); return value; } @@ -42,8 +42,8 @@ static inline unsigned int __arch_getw(unsigned long a) static inline void __arch_putw(unsigned int value, unsigned long a) { - __asm__ __volatile__("str%?h %0, [%1, #0] @ putw" - : : "r" (value), "r" (a)); + __asm__ __volatile__("strh %0, [%1, #0] @ putw" + : : "r" (value), "r" (a) : "cc"); } /* diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index d97fc76189a5..cd10a0b5f8ae 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -247,16 +247,16 @@ static inline void local_flush_tlb_all(void) const unsigned int __tlb_flag = __cpu_tlb_flags; if (tlb_flag(TLB_WB)) - asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); + asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V3_FULL)) - asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL)) - asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL)) - asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) - asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); } static inline void local_flush_tlb_mm(struct mm_struct *mm) @@ -266,25 +266,25 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) const unsigned int __tlb_flag = __cpu_tlb_flags; if (tlb_flag(TLB_WB)) - asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); + asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) { if (tlb_flag(TLB_V3_FULL)) - asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_U_FULL)) - asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_D_FULL)) - asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_I_FULL)) - asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); } if (tlb_flag(TLB_V6_U_ASID)) - asm("mcr%? p15, 0, %0, c8, c7, 2" : : "r" (asid)); + asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc"); if (tlb_flag(TLB_V6_D_ASID)) - asm("mcr%? p15, 0, %0, c8, c6, 2" : : "r" (asid)); + asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); if (tlb_flag(TLB_V6_I_ASID)) - asm("mcr%? p15, 0, %0, c8, c5, 2" : : "r" (asid)); + asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); } static inline void @@ -296,27 +296,27 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); if (tlb_flag(TLB_WB)) - asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); + asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero)); if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { if (tlb_flag(TLB_V3_PAGE)) - asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (uaddr)); + asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V4_U_PAGE)) - asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr)); + asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V4_D_PAGE)) - asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr)); + asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V4_I_PAGE)) - asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr)); + asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) - asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); } if (tlb_flag(TLB_V6_U_PAGE)) - asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr)); + asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V6_D_PAGE)) - asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr)); + asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V6_I_PAGE)) - asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr)); + asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); } static inline void local_flush_tlb_kernel_page(unsigned long kaddr) @@ -327,31 +327,31 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) kaddr &= PAGE_MASK; if (tlb_flag(TLB_WB)) - asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); + asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V3_PAGE)) - asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (kaddr)); + asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc"); if (tlb_flag(TLB_V4_U_PAGE)) - asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr)); + asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc"); if (tlb_flag(TLB_V4_D_PAGE)) - asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr)); + asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); if (tlb_flag(TLB_V4_I_PAGE)) - asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr)); + asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) - asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); + asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V6_U_PAGE)) - asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr)); + asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc"); if (tlb_flag(TLB_V6_D_PAGE)) - asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr)); + asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc"); if (tlb_flag(TLB_V6_I_PAGE)) - asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr)); + asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); /* The ARM ARM states that the completion of a TLB maintenance * operation is only guaranteed by a DSB instruction */ if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE)) - asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); + asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); } /* @@ -373,11 +373,11 @@ static inline void flush_pmd_entry(pmd_t *pmd) const unsigned int __tlb_flag = __cpu_tlb_flags; if (tlb_flag(TLB_DCLEAN)) - asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd" - : : "r" (pmd)); + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" + : : "r" (pmd) : "cc"); if (tlb_flag(TLB_WB)) - asm("mcr%? p15, 0, %0, c7, c10, 4 @ flush_pmd" - : : "r" (zero)); + asm("mcr p15, 0, %0, c7, c10, 4 @ flush_pmd" + : : "r" (zero) : "cc"); } static inline void clean_pmd_entry(pmd_t *pmd) @@ -385,8 +385,8 @@ static inline void clean_pmd_entry(pmd_t *pmd) const unsigned int __tlb_flag = __cpu_tlb_flags; if (tlb_flag(TLB_DCLEAN)) - asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd" - : : "r" (pmd)); + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" + : : "r" (pmd) : "cc"); } #undef tlb_flag -- cgit v1.2.3 From acc46c0144b6d1cf0d77bb8b4d1b7dcd5dc28d71 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Thu, 14 Sep 2006 00:28:26 +1000 Subject: [ARM] nommu: create flat.h to support uClinux flat binaries Create header with uClinux flat format binary support macros for ARM platforms. Derived from the m68knommu flat.h. Signed-off-by: Greg Ungerer Signed-off-by: Russell King --- include/asm-arm/flat.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/asm-arm/flat.h (limited to 'include') diff --git a/include/asm-arm/flat.h b/include/asm-arm/flat.h new file mode 100644 index 000000000000..966946478589 --- /dev/null +++ b/include/asm-arm/flat.h @@ -0,0 +1,16 @@ +/* + * include/asm-arm/flat.h -- uClinux flat-format executables + */ + +#ifndef __ARM_FLAT_H__ +#define __ARM_FLAT_H__ + +#define flat_stack_align(sp) /* nothing needed */ +#define flat_argvp_envp_on_stack() 1 +#define flat_old_ram_flag(flags) (flags) +#define flat_reloc_valid(reloc, size) ((reloc) <= (size)) +#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp) +#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) +#define flat_get_relocate_addr(rel) (rel) + +#endif /* __ARM_FLAT_H__ */ -- cgit v1.2.3 From fd88edd20fb0e8e2729aa8ce565316242189ceea Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 15 Sep 2006 23:34:34 +0100 Subject: [ARM] 3795/1: S3C24XX: add base AC97 registers Add base definitions for the AC97 register definitions. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/map.h | 5 +++++ include/asm-arm/arch-s3c2410/regs-ac97.h | 23 +++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/asm-arm/arch-s3c2410/regs-ac97.h (limited to 'include') diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h index 27ba0ac3fdd5..7895042d176b 100644 --- a/include/asm-arm/arch-s3c2410/map.h +++ b/include/asm-arm/arch-s3c2410/map.h @@ -160,6 +160,11 @@ #define S3C2440_PA_CAMIF (0x4F000000) #define S3C2440_SZ_CAMIF SZ_1M +/* AC97 */ + +#define S3C2440_PA_AC97 (0x5B000000) +#define S3C2440_SZ_AC97 SZ_1M + /* ISA style IO, for each machine to sort out mappings for, if it * implements it. We reserve two 16M regions for ISA. */ diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/arch-s3c2410/regs-ac97.h new file mode 100644 index 000000000000..bdd6a4f93d7f --- /dev/null +++ b/include/asm-arm/arch-s3c2410/regs-ac97.h @@ -0,0 +1,23 @@ +/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h + * + * Copyright (c) 2006 Simtec Electronics + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2440 AC97 Controller +*/ + +#ifndef __ASM_ARCH_REGS_AC97_H +#define __ASM_ARCH_REGS_AC97_H __FILE__ + +#define S3C_AC97_GLBCTRL (0x00) +#define S3C_AC97_GLBSTAT (0x04) +#define S3C_AC97_CODEC_CMD (0x08) +#define S3C_AC97_PCM_ADDR (0x10) +#define S3C_AC97_PCM_DATA (0x18) +#define S3C_AC97_MIC_DATA (0x1C) + +#endif /* __ASM_ARCH_REGS_AC97_H */ -- cgit v1.2.3 From 505788cccbb96cd496b646594c8a5fcdc26bc2d9 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 15 Sep 2006 23:42:24 +0100 Subject: [ARM] 3796/1: S3C24XX: Add per-cpu DMA channel mapper Allow each CPU type in the S3C24XX range to select the DMA channel mapping it supports. We change the DMA registration to use an virtual channel number that the DMA system will allocate to a hardware channel at request time. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/Makefile | 6 + arch/arm/mach-s3c2410/dma.c | 241 ++++++++++++++++++++++++++----------- arch/arm/mach-s3c2410/dma.h | 45 +++++++ include/asm-arm/arch-s3c2410/dma.h | 34 ++++++ 4 files changed, 257 insertions(+), 69 deletions(-) create mode 100644 arch/arm/mach-s3c2410/dma.h (limited to 'include') diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 0eadec916214..e4c32f6ffb71 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -9,6 +9,8 @@ obj-y := cpu.o irq.o time.o gpio.o clock.o devs.o obj-m := obj-n := obj- := +obj-dma-y := +obj-dma-n := # DMA obj-$(CONFIG_S3C2410_DMA) += dma.o @@ -57,6 +59,10 @@ obj-$(CONFIG_CPU_S3C2442) += s3c2442-clock.o obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o +# merge in dma objects + +obj-y += $(obj-dma-y) + # machine specific support obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index cc92a7b2db88..d264bbbd8bef 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -1,35 +1,16 @@ -/* linux/arch/arm/mach-bast/dma.c +/* linux/arch/arm/mach-s3c2410/dma.c * - * (c) 2003-2005 Simtec Electronics + * (c) 2003-2005,2006 Simtec Electronics * Ben Dooks * * S3C2410 DMA core * - * http://www.simtec.co.uk/products/EB2410ITX/ + * http://armlinux.simtec.co.uk/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * Changelog: - * 27-Feb-2005 BJD Added kmem cache for dma descriptors - * 18-Nov-2004 BJD Removed error for loading onto stopped channel - * 10-Nov-2004 BJD Ensure all external symbols exported for modules - * 10-Nov-2004 BJD Use sys_device and sysdev_class for power management - * 08-Aug-2004 BJD Apply rmk's suggestions - * 21-Jul-2004 BJD Ported to linux 2.6 - * 12-Jul-2004 BJD Finished re-write and change of API - * 06-Jul-2004 BJD Rewrote dma code to try and cope with various problems - * 23-May-2003 BJD Created file - * 19-Aug-2003 BJD Cleanup, header fix, added URL - * - * This file is based on the Sangwook Lee/Samsung patches, re-written due - * to various ommisions from the code (such as flexible dma configuration) - * for use with the BAST system board. - * - * The re-write is pretty much complete, and should be good enough for any - * possible DMA function - */ +*/ #ifdef CONFIG_S3C2410_DMA_DEBUG @@ -55,10 +36,14 @@ #include #include +#include "dma.h" + /* io map for dma */ static void __iomem *dma_base; static kmem_cache_t *dma_kmem; +struct s3c24xx_dma_selection dma_sel; + /* dma channel state information */ struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; @@ -79,7 +64,6 @@ dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val) pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); writel(val, dma_regaddr(chan, reg)); } - #endif #define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) @@ -151,12 +135,20 @@ dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan) #define dbg_showchan(chan) do { } while(0) #endif /* CONFIG_S3C2410_DMA_DEBUG */ -#define check_channel(chan) \ - do { if ((chan) >= S3C2410_DMA_CHANNELS) { \ - printk(KERN_ERR "%s: invalid channel %d\n", __FUNCTION__, (chan)); \ - return -EINVAL; \ - } } while(0) +static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX]; +/* lookup_dma_channel + * + * change the dma channel number given into a real dma channel id +*/ + +static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel) +{ + if (channel & DMACH_LOW_LEVEL) + return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL]; + else + return dma_chan_map[channel]; +} /* s3c2410_dma_stats_timeout * @@ -321,8 +313,10 @@ static inline void s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf, enum s3c2410_dma_buffresult result) { +#if 0 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n", chan->callback_fn, buf, buf->id, buf->size, result); +#endif if (chan->callback_fn != NULL) { (chan->callback_fn)(chan, buf->id, buf->size, result); @@ -439,7 +433,6 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan) return 0; } - /* s3c2410_dma_enqueue * * queue an given buffer for dma transfer. @@ -460,11 +453,12 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan) int s3c2410_dma_enqueue(unsigned int channel, void *id, dma_addr_t data, int size) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); struct s3c2410_dma_buf *buf; unsigned long flags; - check_channel(channel); + if (chan == NULL) + return -EINVAL; pr_debug("%s: id=%p, data=%08x, size=%d\n", __FUNCTION__, id, (unsigned int)data, size); @@ -562,8 +556,10 @@ s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf) static inline void s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) { +#if 0 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n", chan->number, chan->load_state); +#endif switch (chan->load_state) { case S3C2410_DMALOAD_NONE: @@ -718,7 +714,8 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) if (chan->load_state == S3C2410_DMALOAD_NONE) { pr_debug("dma%d: end of transfer, stopping channel (%ld)\n", chan->number, jiffies); - s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP); + s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL, + S3C2410_DMAOP_STOP); } } @@ -726,37 +723,34 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) return IRQ_HANDLED; } +static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel); + /* s3c2410_request_dma * * get control of an dma channel */ -int s3c2410_dma_request(unsigned int channel, struct s3c2410_dma_client *client, +int s3c2410_dma_request(unsigned int channel, + struct s3c2410_dma_client *client, void *dev) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan; unsigned long flags; int err; pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", channel, client->name, dev); - check_channel(channel); - local_irq_save(flags); - dbg_showchan(chan); - - if (chan->in_use) { - if (client != chan->client) { - printk(KERN_ERR "dma%d: already in use\n", channel); - local_irq_restore(flags); - return -EBUSY; - } else { - printk(KERN_ERR "dma%d: client already has channel\n", channel); - } + chan = s3c2410_dma_map_channel(channel); + if (chan == NULL) { + local_irq_restore(flags); + return -EBUSY; } + dbg_showchan(chan); + chan->client = client; chan->in_use = 1; @@ -809,14 +803,14 @@ EXPORT_SYMBOL(s3c2410_dma_request); int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); unsigned long flags; - check_channel(channel); + if (chan == NULL) + return -EINVAL; local_irq_save(flags); - if (chan->client != client) { printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", channel, chan->client, client); @@ -837,8 +831,12 @@ int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) if (chan->irq_claimed) free_irq(chan->irq, (void *)chan); + chan->irq_claimed = 0; + if (!(channel & DMACH_LOW_LEVEL)) + dma_chan_map[channel] = NULL; + local_irq_restore(flags); return 0; @@ -848,8 +846,8 @@ EXPORT_SYMBOL(s3c2410_dma_free); static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan) { - unsigned long tmp; unsigned long flags; + unsigned long tmp; pr_debug("%s:\n", __FUNCTION__); @@ -997,9 +995,10 @@ s3c2410_dma_started(struct s3c2410_dma_chan *chan) int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - check_channel(channel); + if (chan == NULL) + return -EINVAL; switch (op) { case S3C2410_DMAOP_START: @@ -1046,12 +1045,19 @@ int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", __FUNCTION__, channel, xferunit, dcon); - check_channel(channel); + if (chan == NULL) + return -EINVAL; + + printk("Initial dcon is %08x\n", dcon); + + dcon |= chan->dcon & dma_sel.dcon_mask; + + printk("New dcon is %08x\n", dcon); switch (xferunit) { case 1: @@ -1086,9 +1092,10 @@ EXPORT_SYMBOL(s3c2410_dma_config); int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - check_channel(channel); + if (chan == NULL) + return -EINVAL; pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags); @@ -1106,9 +1113,10 @@ EXPORT_SYMBOL(s3c2410_dma_setflags); int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - check_channel(channel); + if (chan == NULL) + return -EINVAL; pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn); @@ -1121,9 +1129,10 @@ EXPORT_SYMBOL(s3c2410_dma_set_opfn); int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - check_channel(channel); + if (chan == NULL) + return -EINVAL; pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn); @@ -1153,9 +1162,10 @@ int s3c2410_dma_devconfig(int channel, int hwcfg, unsigned long devaddr) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - check_channel(channel); + if (chan == NULL) + return -EINVAL; pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", __FUNCTION__, (int)source, hwcfg, devaddr); @@ -1200,9 +1210,10 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig); int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) { - struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - check_channel(channel); + if (chan == NULL) + return -EINVAL; if (src != NULL) *src = dma_rdreg(chan, S3C2410_DMA_DCSRC); @@ -1252,7 +1263,7 @@ static int s3c2410_dma_resume(struct sys_device *dev) #define s3c2410_dma_resume NULL #endif /* CONFIG_PM */ -static struct sysdev_class dma_sysclass = { +struct sysdev_class dma_sysclass = { set_kset_name("s3c24xx-dma"), .suspend = s3c2410_dma_suspend, .resume = s3c2410_dma_resume, @@ -1265,7 +1276,6 @@ static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f) memset(p, 0, sizeof(struct s3c2410_dma_buf)); } - /* initialisation code */ static int __init s3c2410_init_dma(void) @@ -1274,7 +1284,7 @@ static int __init s3c2410_init_dma(void) int channel; int ret; - printk("S3C2410 DMA Driver, (c) 2003-2004 Simtec Electronics\n"); + printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n"); dma_base = ioremap(S3C24XX_PA_DMA, 0x200); if (dma_base == NULL) { @@ -1282,6 +1292,8 @@ static int __init s3c2410_init_dma(void) return -ENOMEM; } + printk("Registering sysclass\n"); + ret = sysdev_class_register(&dma_sysclass); if (ret != 0) { printk(KERN_ERR "dma sysclass registration failed\n"); @@ -1335,4 +1347,95 @@ static int __init s3c2410_init_dma(void) return ret; } -__initcall(s3c2410_init_dma); +core_initcall(s3c2410_init_dma); + +static inline int is_channel_valid(unsigned int channel) +{ + return (channel & DMA_CH_VALID); +} + +/* s3c2410_dma_map_channel() + * + * turn the virtual channel number into a real, and un-used hardware + * channel. + * + * currently this code uses first-free channel from the specified harware + * map, not taking into account anything that the board setup code may + * have to say about the likely peripheral set to be in use. +*/ + +struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel) +{ + struct s3c24xx_dma_map *ch_map; + struct s3c2410_dma_chan *dmach; + int ch; + + if (dma_sel.map == NULL || channel > dma_sel.map_size) + return NULL; + + ch_map = dma_sel.map + channel; + + for (ch = 0; ch < S3C2410_DMA_CHANNELS; ch++) { + if (!is_channel_valid(ch_map->channels[ch])) + continue; + + if (s3c2410_chans[ch].in_use == 0) { + printk("mapped channel %d to %d\n", channel, ch); + break; + } + } + + if (ch >= S3C2410_DMA_CHANNELS) + return NULL; + + /* update our channel mapping */ + + dmach = &s3c2410_chans[ch]; + dma_chan_map[channel] = dmach; + + /* select the channel */ + + (dma_sel.select)(dmach, ch_map); + + return dmach; +} + +static void s3c24xx_dma_show_ch(struct s3c24xx_dma_map *map, int ch) +{ + /* show the channel configuration */ + + printk("%2d: %20s, channels %c%c%c%c\n", ch, map->name, + (is_channel_valid(map->channels[0]) ? '0' : '-'), + (is_channel_valid(map->channels[1]) ? '1' : '-'), + (is_channel_valid(map->channels[2]) ? '2' : '-'), + (is_channel_valid(map->channels[3]) ? '3' : '-')); +} + +static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch) +{ + if (1) + s3c24xx_dma_show_ch(map, ch); + + return 0; +} + +int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel) +{ + struct s3c24xx_dma_map *nmap; + size_t map_sz = sizeof(*nmap) * sel->map_size; + int ptr; + + nmap = kmalloc(map_sz, GFP_KERNEL); + if (nmap == NULL) + return -ENOMEM; + + memcpy(nmap, sel->map, map_sz); + memcpy(&dma_sel, sel, sizeof(*sel)); + + dma_sel.map = nmap; + + for (ptr = 0; ptr < sel->map_size; ptr++) + s3c24xx_dma_check_entry(nmap+ptr, ptr); + + return 0; +} diff --git a/arch/arm/mach-s3c2410/dma.h b/arch/arm/mach-s3c2410/dma.h new file mode 100644 index 000000000000..0ebfe0aab80b --- /dev/null +++ b/arch/arm/mach-s3c2410/dma.h @@ -0,0 +1,45 @@ +/* arch/arm/mach-s3c2410/dma.h + * + * Copyright (C) 2006 Simtec Electronics + * Ben Dooks + * + * Samsung S3C24XX DMA support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern struct sysdev_class dma_sysclass; +extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; + +#define DMA_CH_VALID (1<<31) + +struct s3c24xx_dma_addr { + unsigned long from; + unsigned long to; +}; + +/* struct s3c24xx_dma_map + * + * this holds the mapping information for the channel selected + * to be connected to the specified device +*/ + +struct s3c24xx_dma_map { + const char *name; + struct s3c24xx_dma_addr hw_addr; + + unsigned long channels[S3C2410_DMA_CHANNELS]; +}; + +struct s3c24xx_dma_selection { + struct s3c24xx_dma_map *map; + unsigned long map_size; + unsigned long dcon_mask; + + void (*select)(struct s3c2410_dma_chan *chan, + struct s3c24xx_dma_map *map); +}; + +extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel); diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h index 3661e465b0a5..166fc89d62d7 100644 --- a/include/asm-arm/arch-s3c2410/dma.h +++ b/include/asm-arm/arch-s3c2410/dma.h @@ -23,6 +23,36 @@ #define MAX_DMA_ADDRESS 0x40000000 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ +/* We use `virtual` dma channels to hide the fact we have only a limited + * number of DMA channels, and not of all of them (dependant on the device) + * can be attached to any DMA source. We therefore let the DMA core handle + * the allocation of hardware channels to clients. +*/ + +enum dma_ch { + DMACH_XD0, + DMACH_XD1, + DMACH_SDI, + DMACH_SPI0, + DMACH_SPI1, + DMACH_UART0, + DMACH_UART1, + DMACH_UART2, + DMACH_TIMER, + DMACH_I2S_IN, + DMACH_I2S_OUT, + DMACH_PCM_IN, + DMACH_PCM_OUT, + DMACH_MIC_IN, + DMACH_USB_EP1, + DMACH_USB_EP2, + DMACH_USB_EP3, + DMACH_USB_EP4, + DMACH_MAX, /* the end entry */ +}; + +#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ + /* we have 4 dma channels */ #define S3C2410_DMA_CHANNELS (4) @@ -149,6 +179,8 @@ struct s3c2410_dma_stats { unsigned long timeout_failed; }; +struct s3c2410_dma_map; + /* struct s3c2410_dma_chan * * full state information for each DMA channel @@ -174,6 +206,8 @@ struct s3c2410_dma_chan { unsigned long load_timeout; unsigned int flags; /* channel flags */ + struct s3c24xx_dma_map *map; /* channel hw maps */ + /* channel's hardware position and configuration */ void __iomem *regs; /* channels registers */ void __iomem *addr_reg; /* data address register */ -- cgit v1.2.3 From 3e9fc8e5de0fb00226325cf34eb08411eb72ec6d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 16 Sep 2006 00:11:32 +0100 Subject: [ARM] 3804/1: S3C2442: LCD register update Add LCD register definitions for the S3C2442. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/regs-lcd.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h index b306d6e3135d..d8f1adfd17f0 100644 --- a/include/asm-arm/arch-s3c2410/regs-lcd.h +++ b/include/asm-arm/arch-s3c2410/regs-lcd.h @@ -113,6 +113,13 @@ #define S3C2410_LCDINT_FRSYNC (1<<1) #define S3C2410_LCDINT_FICNT (1<<0) +/* s3c2442 extra stn registers */ + +#define S3C2442_REDLUT S3C2410_LCDREG(0x20) +#define S3C2442_GREENLUT S3C2410_LCDREG(0x24) +#define S3C2442_BLUELUT S3C2410_LCDREG(0x28) +#define S3C2442_DITHMODE S3C2410_LCDREG(0x20) + #define S3C2410_LPCSEL S3C2410_LCDREG(0x60) #define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) -- cgit v1.2.3 From 34148c6990d2f0107b53fe4ddf29b1ba30e613d3 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 16 Sep 2006 00:12:53 +0100 Subject: [ARM] 3805/1: S3C2412: LCD register update Add LCD register definitions for the S3C2412. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/regs-lcd.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h index d8f1adfd17f0..6d7881c8cfc8 100644 --- a/include/asm-arm/arch-s3c2410/regs-lcd.h +++ b/include/asm-arm/arch-s3c2410/regs-lcd.h @@ -63,6 +63,8 @@ #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) +/* LDCCON4 changes for STN mode on the S3C2412 */ + #define S3C2410_LCDCON4_MVAL(x) ((x) << 8) #define S3C2410_LCDCON4_HSPW(x) ((x) << 0) #define S3C2410_LCDCON4_WLH(x) ((x) << 0) @@ -124,6 +126,27 @@ #define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) +/* S3C2412 registers */ + +#define S3C2412_TPAL S3C2410_LCDREG(0x20) + +#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24) +#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28) +#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C) + +#define S3C2412_TCONSEL S3C2410_LCDREG(0x30) + +#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34) +#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38) +#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C) +#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40) + +#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4)) +#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4)) +#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4)) + +#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4)) + #endif /* ___ASM_ARCH_REGS_LCD_H */ -- cgit v1.2.3 From 8dd5c845bbc26c3517398abc3e5477b4b42e7176 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sat, 16 Sep 2006 10:47:18 +0100 Subject: [ARM] 3810/1: switch atomic helpers over to raw_local_irq_{save,restore} Now that we have raw_* variants of local_irq_$FOO(), switch the atomic helpers over to use those raw_* variants. This is necessary when using lockdep on pre-ARMv6 hardware, as lockdep uses atomic_t counters in the trace_hardirqs_off() path. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/atomic.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h index 4b0ce3e7de9a..ea88aa6bfc78 100644 --- a/include/asm-arm/atomic.h +++ b/include/asm-arm/atomic.h @@ -128,10 +128,10 @@ static inline int atomic_add_return(int i, atomic_t *v) unsigned long flags; int val; - local_irq_save(flags); + raw_local_irq_save(flags); val = v->counter; v->counter = val += i; - local_irq_restore(flags); + raw_local_irq_restore(flags); return val; } @@ -141,10 +141,10 @@ static inline int atomic_sub_return(int i, atomic_t *v) unsigned long flags; int val; - local_irq_save(flags); + raw_local_irq_save(flags); val = v->counter; v->counter = val -= i; - local_irq_restore(flags); + raw_local_irq_restore(flags); return val; } @@ -154,11 +154,11 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) int ret; unsigned long flags; - local_irq_save(flags); + raw_local_irq_save(flags); ret = v->counter; if (likely(ret == old)) v->counter = new; - local_irq_restore(flags); + raw_local_irq_restore(flags); return ret; } @@ -167,9 +167,9 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) { unsigned long flags; - local_irq_save(flags); + raw_local_irq_save(flags); *addr &= ~mask; - local_irq_restore(flags); + raw_local_irq_restore(flags); } #endif /* __LINUX_ARM_ARCH__ */ -- cgit v1.2.3 From 51635ad282ead58b9d164f07e1fb62a9456b427c Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sat, 16 Sep 2006 10:50:22 +0100 Subject: [ARM] 3813/1: prevent >= 4G /dev/mem mmap() Prevent userland from mapping in physical address regions >= 4G by checking for that in valid_mmap_phys_addr_range(). Unfortunately, we cannot override valid_mmap_phys_addr_range() without also overriding valid_phys_addr_range(), so copy drivers/char/mem.c's version of valid_phys_addr_range() over to arch/arm/mm/mmap.c as well. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mm/mmap.c | 22 ++++++++++++++++++++++ include/asm-arm/io.h | 4 ++++ 2 files changed, 26 insertions(+) (limited to 'include') diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index 29e54807c5bc..b0b5f4694070 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -114,3 +114,25 @@ full_search: } } + +/* + * You really shouldn't be using read() or write() on /dev/mem. This + * might go away in the future. + */ +int valid_phys_addr_range(unsigned long addr, size_t size) +{ + if (addr + size > __pa(high_memory)) + return 0; + + return 1; +} + +/* + * We don't use supersection mappings for mmap() on /dev/mem, which + * means that we can't map the memory area above the 4G barrier into + * userspace. + */ +int valid_mmap_phys_addr_range(unsigned long pfn, size_t size) +{ + return !(pfn + (size >> PAGE_SHIFT) > 0x00100000); +} diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index bf7b9dea30f1..8076a85c3675 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -280,6 +280,10 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); #define BIOVEC_MERGEABLE(vec1, vec2) \ ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) +#define ARCH_HAS_VALID_PHYS_ADDR_RANGE +extern int valid_phys_addr_range(unsigned long addr, size_t size); +extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); + /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem * access -- cgit v1.2.3 From 34348012d6b43eca5e241fe97381420d5758866c Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 18 Sep 2006 23:52:03 +0100 Subject: [ARM] 3800/2: S3C2412: DMA channel mappings DMA channel mappings for the S3C2312 Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/Makefile | 1 + arch/arm/mach-s3c2410/s3c2412-dma.c | 160 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-s3c2410/dma.h | 32 ++++++++ 3 files changed, 193 insertions(+) create mode 100644 arch/arm/mach-s3c2410/s3c2412-dma.c (limited to 'include') diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 23f0909915db..0d87a9de0034 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o obj-$(CONFIG_CPU_S3C2412) += s3c2412.o obj-$(CONFIG_CPU_S3C2412) += s3c2412-irq.o obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o +obj-dma-$(CONFIG_CPU_S3C2412) += s3c2412-dma.o # # S3C244X support diff --git a/arch/arm/mach-s3c2410/s3c2412-dma.c b/arch/arm/mach-s3c2410/s3c2412-dma.c new file mode 100644 index 000000000000..171f3706d36d --- /dev/null +++ b/arch/arm/mach-s3c2410/s3c2412-dma.c @@ -0,0 +1,160 @@ +/* linux/arch/arm/mach-s3c2410/s3c2412-dma.c + * + * (c) 2006 Simtec Electronics + * Ben Dooks + * + * S3C2412 DMA selection + * + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include + +#include +#include +#include + +#include "dma.h" +#include "cpu.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID } + +static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { + [DMACH_XD0] = { + .name = "xdreq0", + .channels = MAP(S3C2412_DMAREQSEL_XDREQ0), + }, + [DMACH_XD1] = { + .name = "xdreq1", + .channels = MAP(S3C2412_DMAREQSEL_XDREQ1), + }, + [DMACH_SDI] = { + .name = "sdi", + .channels = MAP(S3C2412_DMAREQSEL_SDI), + .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, + .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_SPI0] = { + .name = "spi0", + .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), + .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, + }, + [DMACH_SPI1] = { + .name = "spi1", + .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), + .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, + }, + [DMACH_UART0] = { + .name = "uart0", + .channels = MAP(S3C2412_DMAREQSEL_UART0_0), + .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, + }, + [DMACH_UART1] = { + .name = "uart1", + .channels = MAP(S3C2412_DMAREQSEL_UART1_0), + .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, + }, + [DMACH_UART2] = { + .name = "uart2", + .channels = MAP(S3C2412_DMAREQSEL_UART2_0), + .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, + }, + [DMACH_UART0_SRC2] = { + .name = "uart0", + .channels = MAP(S3C2412_DMAREQSEL_UART0_1), + .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, + }, + [DMACH_UART1_SRC2] = { + .name = "uart1", + .channels = MAP(S3C2412_DMAREQSEL_UART1_1), + .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, + }, + [DMACH_UART2_SRC2] = { + .name = "uart2", + .channels = MAP(S3C2412_DMAREQSEL_UART2_1), + .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, + }, + [DMACH_TIMER] = { + .name = "timer", + .channels = MAP(S3C2412_DMAREQSEL_TIMER), + }, + [DMACH_I2S_IN] = { + .name = "i2s-sdi", + .channels = MAP(S3C2412_DMAREQSEL_I2SRX), + .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_I2S_OUT] = { + .name = "i2s-sdo", + .channels = MAP(S3C2412_DMAREQSEL_I2STX), + .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_USB_EP1] = { + .name = "usb-ep1", + .channels = MAP(S3C2412_DMAREQSEL_USBEP1), + }, + [DMACH_USB_EP2] = { + .name = "usb-ep2", + .channels = MAP(S3C2412_DMAREQSEL_USBEP2), + }, + [DMACH_USB_EP3] = { + .name = "usb-ep3", + .channels = MAP(S3C2412_DMAREQSEL_USBEP3), + }, + [DMACH_USB_EP4] = { + .name = "usb-ep4", + .channels = MAP(S3C2412_DMAREQSEL_USBEP4), + }, +}; + +static void s3c2412_dma_select(struct s3c2410_dma_chan *chan, + struct s3c24xx_dma_map *map) +{ + writel(chan->regs + S3C2412_DMA_DMAREQSEL, + map->channels[0] | S3C2412_DMAREQSEL_HW); +} + +static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { + .select = s3c2412_dma_select, + .dcon_mask = 0, + .map = s3c2412_dma_mappings, + .map_size = ARRAY_SIZE(s3c2412_dma_mappings), +}; + +static int s3c2412_dma_add(struct sys_device *sysdev) +{ + return s3c24xx_dma_init_map(&s3c2412_dma_sel); +} + +static struct sysdev_driver s3c2412_dma_driver = { + .add = s3c2412_dma_add, +}; + +static int __init s3c2412_dma_init(void) +{ + return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver); +} + +arch_initcall(s3c2412_dma_init); diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h index 166fc89d62d7..7ac224836971 100644 --- a/include/asm-arm/arch-s3c2410/dma.h +++ b/include/asm-arm/arch-s3c2410/dma.h @@ -48,6 +48,9 @@ enum dma_ch { DMACH_USB_EP2, DMACH_USB_EP3, DMACH_USB_EP4, + DMACH_UART0_SRC2, /* s3c2412 second uart sources */ + DMACH_UART1_SRC2, + DMACH_UART2_SRC2, DMACH_MAX, /* the end entry */ }; @@ -317,6 +320,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); #define S3C2410_DMA_DCSRC (0x18) #define S3C2410_DMA_DCDST (0x1C) #define S3C2410_DMA_DMASKTRIG (0x20) +#define S3C2412_DMA_DMAREQSEL (0x24) #define S3C2410_DISRCC_INC (1<<0) #define S3C2410_DISRCC_APB (1<<1) @@ -383,4 +387,32 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); #define S3C2440_DCON_CH3_PCMOUT (6<<24) #endif +#ifdef CONFIG_CPU_S3C2412 + +#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) + +#define S3C2412_DMAREQSEL_HW (1) + +#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0) +#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1) +#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2) +#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3) +#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4) +#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5) +#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9) +#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10) +#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13) +#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14) +#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15) +#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16) +#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17) +#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18) +#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19) +#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20) +#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21) +#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) +#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) +#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) + +#endif #endif /* __ASM_ARCH_DMA_H */ -- cgit v1.2.3 From 98954df6917cb8f7e65f4f0f79ed641112fcf6b6 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:02:25 +0100 Subject: [ARM] 3816/1: iop3xx: rename config symbols Rename CONFIG_ARCH_IOP321 to CONFIG_ARCH_IOP32X and CONFIG_ARCH_IOP331 to CONFIG_ARCH_IOP33X. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/boot/compressed/head.S | 2 +- arch/arm/configs/ep80219_defconfig | 4 ++-- arch/arm/configs/iq31244_defconfig | 4 ++-- arch/arm/configs/iq80321_defconfig | 4 ++-- arch/arm/configs/iq80331_defconfig | 2 +- arch/arm/configs/iq80332_defconfig | 2 +- arch/arm/mach-iop3xx/Kconfig | 16 ++++++++-------- arch/arm/mach-iop3xx/Makefile | 4 ++-- arch/arm/mach-iop3xx/Makefile.boot | 2 +- arch/arm/mach-iop3xx/iop331-setup.c | 2 +- arch/arm/oprofile/op_model_xscale.c | 4 ++-- drivers/i2c/busses/i2c-iop3xx.c | 4 ++-- include/asm-arm/arch-iop3xx/debug-macro.S | 2 +- include/asm-arm/arch-iop3xx/entry-macro.S | 4 ++-- include/asm-arm/arch-iop3xx/iop321.h | 2 +- include/asm-arm/arch-iop3xx/iop331.h | 4 ++-- include/asm-arm/arch-iop3xx/irqs.h | 4 ++-- include/asm-arm/arch-iop3xx/memory.h | 6 +++--- include/asm-arm/arch-iop3xx/system.h | 4 ++-- include/asm-arm/arch-iop3xx/uncompress.h | 4 ++-- 20 files changed, 40 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 14a9ff9c68df..d7ecc7ece82d 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -42,7 +42,7 @@ add \rb, \rb, #0x00010000 @ Ser1 #endif .endm -#elif defined(CONFIG_ARCH_IOP331) +#elif defined(CONFIG_ARCH_IOP33X) .macro loadsp, rb mov \rb, #0xff000000 orr \rb, \rb, #0x00ff0000 diff --git a/arch/arm/configs/ep80219_defconfig b/arch/arm/configs/ep80219_defconfig index 3c73b707c2f3..199f1567345d 100644 --- a/arch/arm/configs/ep80219_defconfig +++ b/arch/arm/configs/ep80219_defconfig @@ -93,8 +93,8 @@ CONFIG_ARCH_IQ31244=y # CONFIG_ARCH_IQ80331 is not set # CONFIG_MACH_IQ80332 is not set CONFIG_ARCH_EP80219=y -CONFIG_ARCH_IOP321=y -# CONFIG_ARCH_IOP331 is not set +CONFIG_ARCH_IOP32X=y +# CONFIG_ARCH_IOP33X is not set # # IOP3xx Chipset Features diff --git a/arch/arm/configs/iq31244_defconfig b/arch/arm/configs/iq31244_defconfig index 32467160a6df..27f884417b90 100644 --- a/arch/arm/configs/iq31244_defconfig +++ b/arch/arm/configs/iq31244_defconfig @@ -94,8 +94,8 @@ CONFIG_ARCH_IQ31244=y # CONFIG_ARCH_IQ80331 is not set # CONFIG_MACH_IQ80332 is not set # CONFIG_ARCH_EP80219 is not set -CONFIG_ARCH_IOP321=y -# CONFIG_ARCH_IOP331 is not set +CONFIG_ARCH_IOP32X=y +# CONFIG_ARCH_IOP33X is not set # # IOP3xx Chipset Features diff --git a/arch/arm/configs/iq80321_defconfig b/arch/arm/configs/iq80321_defconfig index b000da753c41..33f21a24cf4e 100644 --- a/arch/arm/configs/iq80321_defconfig +++ b/arch/arm/configs/iq80321_defconfig @@ -93,8 +93,8 @@ CONFIG_ARCH_IQ80321=y # CONFIG_ARCH_IQ80331 is not set # CONFIG_MACH_IQ80332 is not set # CONFIG_ARCH_EP80219 is not set -CONFIG_ARCH_IOP321=y -# CONFIG_ARCH_IOP331 is not set +CONFIG_ARCH_IOP32X=y +# CONFIG_ARCH_IOP33X is not set # # IOP3xx Chipset Features diff --git a/arch/arm/configs/iq80331_defconfig b/arch/arm/configs/iq80331_defconfig index 46c79e1efe07..67a8bd7dba29 100644 --- a/arch/arm/configs/iq80331_defconfig +++ b/arch/arm/configs/iq80331_defconfig @@ -93,7 +93,7 @@ CONFIG_ARCH_IOP3XX=y CONFIG_ARCH_IQ80331=y # CONFIG_MACH_IQ80332 is not set # CONFIG_ARCH_EP80219 is not set -CONFIG_ARCH_IOP331=y +CONFIG_ARCH_IOP33X=y # # IOP3xx Chipset Features diff --git a/arch/arm/configs/iq80332_defconfig b/arch/arm/configs/iq80332_defconfig index 11959b705d82..c8dea45cb017 100644 --- a/arch/arm/configs/iq80332_defconfig +++ b/arch/arm/configs/iq80332_defconfig @@ -93,7 +93,7 @@ CONFIG_ARCH_IOP3XX=y # CONFIG_ARCH_IQ80331 is not set CONFIG_MACH_IQ80332=y # CONFIG_ARCH_EP80219 is not set -CONFIG_ARCH_IOP331=y +CONFIG_ARCH_IOP33X=y # # IOP3xx Chipset Features diff --git a/arch/arm/mach-iop3xx/Kconfig b/arch/arm/mach-iop3xx/Kconfig index 4422f2388607..887c3753727f 100644 --- a/arch/arm/mach-iop3xx/Kconfig +++ b/arch/arm/mach-iop3xx/Kconfig @@ -6,48 +6,48 @@ comment "IOP3xx Platform Types" config ARCH_IQ80321 bool "Enable support for IQ80321" - select ARCH_IOP321 + select ARCH_IOP32X help Say Y here if you want to run your kernel on the Intel IQ80321 evaluation kit for the IOP321 chipset. config ARCH_IQ31244 bool "Enable support for IQ31244" - select ARCH_IOP321 + select ARCH_IOP32X help Say Y here if you want to run your kernel on the Intel IQ31244 evaluation kit for the IOP321 chipset. config ARCH_IQ80331 bool "Enable support for IQ80331" - select ARCH_IOP331 + select ARCH_IOP33X help Say Y here if you want to run your kernel on the Intel IQ80331 evaluation kit for the IOP331 chipset. config MACH_IQ80332 bool "Enable support for IQ80332" - select ARCH_IOP331 + select ARCH_IOP33X help Say Y here if you want to run your kernel on the Intel IQ80332 evaluation kit for the IOP332 chipset. config ARCH_EP80219 bool "Enable support for EP80219" - select ARCH_IOP321 + select ARCH_IOP32X select ARCH_IQ31244 help Say Y here if you want to run your kernel on the Intel EP80219 evaluation kit for the Intel 80219 chipset (a IOP321 variant). # Which IOP variant are we running? -config ARCH_IOP321 +config ARCH_IOP32X bool help The IQ80321 uses the IOP321 variant. The IQ31244 and EP80219 uses the IOP321 variant. -config ARCH_IOP331 +config ARCH_IOP33X bool default ARCH_IQ80331 help @@ -57,7 +57,7 @@ comment "IOP3xx Chipset Features" config IOP331_STEPD bool "Chip stepping D of the IOP80331 processor or IOP80333" - depends on (ARCH_IOP331) + depends on ARCH_IOP33X help Say Y here if you have StepD of the IOP80331 or IOP8033 based platforms. diff --git a/arch/arm/mach-iop3xx/Makefile b/arch/arm/mach-iop3xx/Makefile index b17eb1f46102..ad3051524480 100644 --- a/arch/arm/mach-iop3xx/Makefile +++ b/arch/arm/mach-iop3xx/Makefile @@ -10,9 +10,9 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_ARCH_IOP321) += iop321-setup.o iop321-irq.o iop321-pci.o iop321-time.o +obj-$(CONFIG_ARCH_IOP32X) += iop321-setup.o iop321-irq.o iop321-pci.o iop321-time.o -obj-$(CONFIG_ARCH_IOP331) += iop331-setup.o iop331-irq.o iop331-pci.o iop331-time.o +obj-$(CONFIG_ARCH_IOP33X) += iop331-setup.o iop331-irq.o iop331-pci.o iop331-time.o obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o diff --git a/arch/arm/mach-iop3xx/Makefile.boot b/arch/arm/mach-iop3xx/Makefile.boot index 6387aa20461b..e120c233b706 100644 --- a/arch/arm/mach-iop3xx/Makefile.boot +++ b/arch/arm/mach-iop3xx/Makefile.boot @@ -1,7 +1,7 @@ zreladdr-y := 0xa0008000 params_phys-y := 0xa0000100 initrd_phys-y := 0xa0800000 -ifeq ($(CONFIG_ARCH_IOP331),y) +ifeq ($(CONFIG_ARCH_IOP33X),y) zreladdr-y := 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-iop3xx/iop331-setup.c b/arch/arm/mach-iop3xx/iop331-setup.c index 3cc98d892ad4..b2f24931d143 100644 --- a/arch/arm/mach-iop3xx/iop331-setup.c +++ b/arch/arm/mach-iop3xx/iop331-setup.c @@ -177,7 +177,7 @@ void __init iop331_map_io(void) iotable_init(iop331_std_desc, ARRAY_SIZE(iop331_std_desc)); } -#ifdef CONFIG_ARCH_IOP331 +#ifdef CONFIG_ARCH_IOP33X extern void iop331_init_irq(void); extern struct sys_timer iop331_timer; #endif diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c index 34fdc733743b..7e0cc5b15b15 100644 --- a/arch/arm/oprofile/op_model_xscale.c +++ b/arch/arm/oprofile/op_model_xscale.c @@ -36,10 +36,10 @@ #ifdef CONFIG_ARCH_IOP310 #define XSCALE_PMU_IRQ IRQ_XS80200_PMU #endif -#ifdef CONFIG_ARCH_IOP321 +#ifdef CONFIG_ARCH_IOP32X #define XSCALE_PMU_IRQ IRQ_IOP321_CORE_PMU #endif -#ifdef CONFIG_ARCH_IOP331 +#ifdef CONFIG_ARCH_IOP33X #define XSCALE_PMU_IRQ IRQ_IOP331_CORE_PMU #endif #ifdef CONFIG_ARCH_PXA diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c index 48c56939c861..035417f5a003 100644 --- a/drivers/i2c/busses/i2c-iop3xx.c +++ b/drivers/i2c/busses/i2c-iop3xx.c @@ -82,9 +82,9 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) /* * Every time unit enable is asserted, GPOD needs to be cleared - * on IOP321 to avoid data corruption on the bus. + * on IOP32X to avoid data corruption on the bus. */ -#ifdef CONFIG_ARCH_IOP321 +#ifdef CONFIG_ARCH_IOP32X #define IOP321_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */ #define IOP321_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */ diff --git a/include/asm-arm/arch-iop3xx/debug-macro.S b/include/asm-arm/arch-iop3xx/debug-macro.S index ce007e531994..dcc6856d14ff 100644 --- a/include/asm-arm/arch-iop3xx/debug-macro.S +++ b/include/asm-arm/arch-iop3xx/debug-macro.S @@ -15,7 +15,7 @@ mov \rx, #0xfe000000 @ physical #if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244) orr \rx, \rx, #0x00800000 @ location of the UART -#elif defined(CONFIG_ARCH_IOP331) +#elif defined(CONFIG_ARCH_IOP33X) mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x000fe000 @ Physical Base diff --git a/include/asm-arm/arch-iop3xx/entry-macro.S b/include/asm-arm/arch-iop3xx/entry-macro.S index 926668c098a5..f3db54637ad3 100644 --- a/include/asm-arm/arch-iop3xx/entry-macro.S +++ b/include/asm-arm/arch-iop3xx/entry-macro.S @@ -9,7 +9,7 @@ */ #include -#if defined(CONFIG_ARCH_IOP321) +#if defined(CONFIG_ARCH_IOP32X) .macro disable_fiq .endm @@ -28,7 +28,7 @@ 1001: .endm -#elif defined(CONFIG_ARCH_IOP331) +#elif defined(CONFIG_ARCH_IOP33X) .macro disable_fiq .endm diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h index f8df778a356f..d198d72a50a4 100644 --- a/include/asm-arm/arch-iop3xx/iop321.h +++ b/include/asm-arm/arch-iop3xx/iop321.h @@ -21,7 +21,7 @@ * IOP3xx variants but behave slightly differently on each. */ #ifndef __ASSEMBLY__ -#ifdef CONFIG_ARCH_IOP321 +#ifdef CONFIG_ARCH_IOP32X #define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420)) #else #define iop_is_321() 0 diff --git a/include/asm-arm/arch-iop3xx/iop331.h b/include/asm-arm/arch-iop3xx/iop331.h index fbf0cc11bdd9..4d7bcc62cb3e 100644 --- a/include/asm-arm/arch-iop3xx/iop331.h +++ b/include/asm-arm/arch-iop3xx/iop331.h @@ -20,7 +20,7 @@ * IOP3xx variants but behave slightly differently on each. */ #ifndef __ASSEMBLY__ -#ifdef CONFIG_ARCH_IOP331 +#ifdef CONFIG_ARCH_IOP33X /*#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090) */ #define iop_is_331() ((processor_id & 0xffffff30) == 0x69054010) #else @@ -257,7 +257,7 @@ #define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8) #define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC) -#if defined(CONFIG_ARCH_IOP331) +#if defined(CONFIG_ARCH_IOP33X) #define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */ #endif diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h index b2c03f4c269c..4f7c7aa87b4a 100644 --- a/include/asm-arm/arch-iop3xx/irqs.h +++ b/include/asm-arm/arch-iop3xx/irqs.h @@ -12,10 +12,10 @@ /* * Chipset-specific bits */ -#ifdef CONFIG_ARCH_IOP321 +#ifdef CONFIG_ARCH_IOP32X #include "iop321-irqs.h" #endif -#ifdef CONFIG_ARCH_IOP331 +#ifdef CONFIG_ARCH_IOP33X #include "iop331-irqs.h" #endif diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h index e43ebd984745..25666184e8fc 100644 --- a/include/asm-arm/arch-iop3xx/memory.h +++ b/include/asm-arm/arch-iop3xx/memory.h @@ -10,7 +10,7 @@ /* * Physical DRAM offset. */ -#ifndef CONFIG_ARCH_IOP331 +#ifndef CONFIG_ARCH_IOP33X #define PHYS_OFFSET UL(0xa0000000) #else #define PHYS_OFFSET UL(0x00000000) @@ -23,12 +23,12 @@ * bus_to_virt: Used to convert an address for DMA operations * to an address that the kernel can use. */ -#if defined(CONFIG_ARCH_IOP321) +#if defined(CONFIG_ARCH_IOP32X) #define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0)) #define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2))) -#elif defined(CONFIG_ARCH_IOP331) +#elif defined(CONFIG_ARCH_IOP33X) #define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0)) #define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2))) diff --git a/include/asm-arm/arch-iop3xx/system.h b/include/asm-arm/arch-iop3xx/system.h index af6ae8cd36c9..a16cbb77a7f6 100644 --- a/include/asm-arm/arch-iop3xx/system.h +++ b/include/asm-arm/arch-iop3xx/system.h @@ -16,11 +16,11 @@ static inline void arch_idle(void) static inline void arch_reset(char mode) { -#ifdef CONFIG_ARCH_IOP321 +#ifdef CONFIG_ARCH_IOP32X *IOP321_PCSR = 0x30; #endif -#ifdef CONFIG_ARCH_IOP331 +#ifdef CONFIG_ARCH_IOP33X *IOP331_PCSR = 0x30; #endif diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h index fbdd5af644fe..066c16bc1250 100644 --- a/include/asm-arm/arch-iop3xx/uncompress.h +++ b/include/asm-arm/arch-iop3xx/uncompress.h @@ -6,9 +6,9 @@ #include #include -#ifdef CONFIG_ARCH_IOP321 +#ifdef CONFIG_ARCH_IOP32X #define UTYPE unsigned char * -#elif defined(CONFIG_ARCH_IOP331) +#elif defined(CONFIG_ARCH_IOP33X) #define UTYPE u32 * #else #error "Missing IOP3xx arch type def" -- cgit v1.2.3 From 3f7e5815f4b774270e6506962de37af85aa9c830 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:10:26 +0100 Subject: [ARM] 3817/1: iop3xx: split the iop3xx mach into iop32x and iop33x Split the iop3xx mach type into iop32x and iop33x -- split the config symbols, and move the code in the mach-iop3xx directory to the mach-iop32x and mach-iop33x directories. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/Kconfig | 20 +- arch/arm/Makefile | 3 +- arch/arm/configs/ep80219_defconfig | 5 +- arch/arm/configs/iq31244_defconfig | 5 +- arch/arm/configs/iq80321_defconfig | 5 +- arch/arm/configs/iq80331_defconfig | 4 +- arch/arm/configs/iq80332_defconfig | 4 +- arch/arm/mach-iop32x/Kconfig | 28 +++ arch/arm/mach-iop32x/Makefile | 11 + arch/arm/mach-iop32x/Makefile.boot | 3 + arch/arm/mach-iop32x/common.c | 72 ++++++ arch/arm/mach-iop32x/iq31244-mm.c | 45 ++++ arch/arm/mach-iop32x/iq31244-pci.c | 129 +++++++++++ arch/arm/mach-iop32x/iq80321-mm.c | 45 ++++ arch/arm/mach-iop32x/iq80321-pci.c | 123 ++++++++++ arch/arm/mach-iop32x/irq.c | 97 ++++++++ arch/arm/mach-iop32x/pci.c | 220 ++++++++++++++++++ arch/arm/mach-iop32x/setup.c | 173 ++++++++++++++ arch/arm/mach-iop32x/time.c | 108 +++++++++ arch/arm/mach-iop33x/Kconfig | 27 +++ arch/arm/mach-iop33x/Makefile | 11 + arch/arm/mach-iop33x/Makefile.boot | 3 + arch/arm/mach-iop33x/common.c | 22 ++ arch/arm/mach-iop33x/iq80331-mm.c | 35 +++ arch/arm/mach-iop33x/iq80331-pci.c | 119 ++++++++++ arch/arm/mach-iop33x/iq80332-mm.c | 35 +++ arch/arm/mach-iop33x/iq80332-pci.c | 125 ++++++++++ arch/arm/mach-iop33x/irq.c | 129 +++++++++++ arch/arm/mach-iop33x/pci.c | 222 ++++++++++++++++++ arch/arm/mach-iop33x/setup.c | 221 ++++++++++++++++++ arch/arm/mach-iop33x/time.c | 106 +++++++++ arch/arm/mach-iop3xx/Kconfig | 66 ------ arch/arm/mach-iop3xx/Makefile | 23 -- arch/arm/mach-iop3xx/Makefile.boot | 9 - arch/arm/mach-iop3xx/common.c | 72 ------ arch/arm/mach-iop3xx/iop321-irq.c | 97 -------- arch/arm/mach-iop3xx/iop321-pci.c | 220 ------------------ arch/arm/mach-iop3xx/iop321-setup.c | 173 -------------- arch/arm/mach-iop3xx/iop321-time.c | 108 --------- arch/arm/mach-iop3xx/iop331-irq.c | 129 ----------- arch/arm/mach-iop3xx/iop331-pci.c | 222 ------------------ arch/arm/mach-iop3xx/iop331-setup.c | 221 ------------------ arch/arm/mach-iop3xx/iop331-time.c | 106 --------- arch/arm/mach-iop3xx/iq31244-mm.c | 45 ---- arch/arm/mach-iop3xx/iq31244-pci.c | 129 ----------- arch/arm/mach-iop3xx/iq80321-mm.c | 45 ---- arch/arm/mach-iop3xx/iq80321-pci.c | 123 ---------- arch/arm/mach-iop3xx/iq80331-mm.c | 35 --- arch/arm/mach-iop3xx/iq80331-pci.c | 119 ---------- arch/arm/mach-iop3xx/iq80332-mm.c | 35 --- arch/arm/mach-iop3xx/iq80332-pci.c | 125 ---------- arch/arm/mm/Kconfig | 2 +- drivers/i2c/busses/Kconfig | 2 +- include/asm-arm/arch-iop32x/debug-macro.S | 20 ++ include/asm-arm/arch-iop32x/dma.h | 9 + include/asm-arm/arch-iop32x/entry-macro.S | 28 +++ include/asm-arm/arch-iop32x/hardware.h | 54 +++++ include/asm-arm/arch-iop32x/io.h | 21 ++ include/asm-arm/arch-iop32x/iop321.h | 341 ++++++++++++++++++++++++++++ include/asm-arm/arch-iop32x/iq31244.h | 24 ++ include/asm-arm/arch-iop32x/iq80321.h | 24 ++ include/asm-arm/arch-iop32x/irqs.h | 98 ++++++++ include/asm-arm/arch-iop32x/memory.h | 27 +++ include/asm-arm/arch-iop32x/system.h | 29 +++ include/asm-arm/arch-iop32x/timex.h | 8 + include/asm-arm/arch-iop32x/uncompress.h | 38 ++++ include/asm-arm/arch-iop32x/vmalloc.h | 16 ++ include/asm-arm/arch-iop33x/debug-macro.S | 24 ++ include/asm-arm/arch-iop33x/dma.h | 9 + include/asm-arm/arch-iop33x/entry-macro.S | 34 +++ include/asm-arm/arch-iop33x/hardware.h | 54 +++++ include/asm-arm/arch-iop33x/io.h | 21 ++ include/asm-arm/arch-iop33x/iop331.h | 358 +++++++++++++++++++++++++++++ include/asm-arm/arch-iop33x/iq80331.h | 23 ++ include/asm-arm/arch-iop33x/iq80332.h | 23 ++ include/asm-arm/arch-iop33x/irqs.h | 130 +++++++++++ include/asm-arm/arch-iop33x/memory.h | 26 +++ include/asm-arm/arch-iop33x/system.h | 29 +++ include/asm-arm/arch-iop33x/timex.h | 8 + include/asm-arm/arch-iop33x/uncompress.h | 36 +++ include/asm-arm/arch-iop33x/vmalloc.h | 16 ++ include/asm-arm/arch-iop3xx/debug-macro.S | 35 --- include/asm-arm/arch-iop3xx/dma.h | 9 - include/asm-arm/arch-iop3xx/entry-macro.S | 57 ----- include/asm-arm/arch-iop3xx/hardware.h | 57 ----- include/asm-arm/arch-iop3xx/io.h | 21 -- include/asm-arm/arch-iop3xx/iop321-irqs.h | 100 -------- include/asm-arm/arch-iop3xx/iop321.h | 345 ---------------------------- include/asm-arm/arch-iop3xx/iop331-irqs.h | 132 ----------- include/asm-arm/arch-iop3xx/iop331.h | 363 ------------------------------ include/asm-arm/arch-iop3xx/iq31244.h | 24 -- include/asm-arm/arch-iop3xx/iq80321.h | 24 -- include/asm-arm/arch-iop3xx/iq80331.h | 23 -- include/asm-arm/arch-iop3xx/iq80332.h | 23 -- include/asm-arm/arch-iop3xx/irqs.h | 21 -- include/asm-arm/arch-iop3xx/memory.h | 38 ---- include/asm-arm/arch-iop3xx/system.h | 35 --- include/asm-arm/arch-iop3xx/timex.h | 20 -- include/asm-arm/arch-iop3xx/uncompress.h | 48 ---- include/asm-arm/arch-iop3xx/vmalloc.h | 16 -- 100 files changed, 3666 insertions(+), 3514 deletions(-) create mode 100644 arch/arm/mach-iop32x/Kconfig create mode 100644 arch/arm/mach-iop32x/Makefile create mode 100644 arch/arm/mach-iop32x/Makefile.boot create mode 100644 arch/arm/mach-iop32x/common.c create mode 100644 arch/arm/mach-iop32x/iq31244-mm.c create mode 100644 arch/arm/mach-iop32x/iq31244-pci.c create mode 100644 arch/arm/mach-iop32x/iq80321-mm.c create mode 100644 arch/arm/mach-iop32x/iq80321-pci.c create mode 100644 arch/arm/mach-iop32x/irq.c create mode 100644 arch/arm/mach-iop32x/pci.c create mode 100644 arch/arm/mach-iop32x/setup.c create mode 100644 arch/arm/mach-iop32x/time.c create mode 100644 arch/arm/mach-iop33x/Kconfig create mode 100644 arch/arm/mach-iop33x/Makefile create mode 100644 arch/arm/mach-iop33x/Makefile.boot create mode 100644 arch/arm/mach-iop33x/common.c create mode 100644 arch/arm/mach-iop33x/iq80331-mm.c create mode 100644 arch/arm/mach-iop33x/iq80331-pci.c create mode 100644 arch/arm/mach-iop33x/iq80332-mm.c create mode 100644 arch/arm/mach-iop33x/iq80332-pci.c create mode 100644 arch/arm/mach-iop33x/irq.c create mode 100644 arch/arm/mach-iop33x/pci.c create mode 100644 arch/arm/mach-iop33x/setup.c create mode 100644 arch/arm/mach-iop33x/time.c delete mode 100644 arch/arm/mach-iop3xx/Kconfig delete mode 100644 arch/arm/mach-iop3xx/Makefile delete mode 100644 arch/arm/mach-iop3xx/Makefile.boot delete mode 100644 arch/arm/mach-iop3xx/common.c delete mode 100644 arch/arm/mach-iop3xx/iop321-irq.c delete mode 100644 arch/arm/mach-iop3xx/iop321-pci.c delete mode 100644 arch/arm/mach-iop3xx/iop321-setup.c delete mode 100644 arch/arm/mach-iop3xx/iop321-time.c delete mode 100644 arch/arm/mach-iop3xx/iop331-irq.c delete mode 100644 arch/arm/mach-iop3xx/iop331-pci.c delete mode 100644 arch/arm/mach-iop3xx/iop331-setup.c delete mode 100644 arch/arm/mach-iop3xx/iop331-time.c delete mode 100644 arch/arm/mach-iop3xx/iq31244-mm.c delete mode 100644 arch/arm/mach-iop3xx/iq31244-pci.c delete mode 100644 arch/arm/mach-iop3xx/iq80321-mm.c delete mode 100644 arch/arm/mach-iop3xx/iq80321-pci.c delete mode 100644 arch/arm/mach-iop3xx/iq80331-mm.c delete mode 100644 arch/arm/mach-iop3xx/iq80331-pci.c delete mode 100644 arch/arm/mach-iop3xx/iq80332-mm.c delete mode 100644 arch/arm/mach-iop3xx/iq80332-pci.c create mode 100644 include/asm-arm/arch-iop32x/debug-macro.S create mode 100644 include/asm-arm/arch-iop32x/dma.h create mode 100644 include/asm-arm/arch-iop32x/entry-macro.S create mode 100644 include/asm-arm/arch-iop32x/hardware.h create mode 100644 include/asm-arm/arch-iop32x/io.h create mode 100644 include/asm-arm/arch-iop32x/iop321.h create mode 100644 include/asm-arm/arch-iop32x/iq31244.h create mode 100644 include/asm-arm/arch-iop32x/iq80321.h create mode 100644 include/asm-arm/arch-iop32x/irqs.h create mode 100644 include/asm-arm/arch-iop32x/memory.h create mode 100644 include/asm-arm/arch-iop32x/system.h create mode 100644 include/asm-arm/arch-iop32x/timex.h create mode 100644 include/asm-arm/arch-iop32x/uncompress.h create mode 100644 include/asm-arm/arch-iop32x/vmalloc.h create mode 100644 include/asm-arm/arch-iop33x/debug-macro.S create mode 100644 include/asm-arm/arch-iop33x/dma.h create mode 100644 include/asm-arm/arch-iop33x/entry-macro.S create mode 100644 include/asm-arm/arch-iop33x/hardware.h create mode 100644 include/asm-arm/arch-iop33x/io.h create mode 100644 include/asm-arm/arch-iop33x/iop331.h create mode 100644 include/asm-arm/arch-iop33x/iq80331.h create mode 100644 include/asm-arm/arch-iop33x/iq80332.h create mode 100644 include/asm-arm/arch-iop33x/irqs.h create mode 100644 include/asm-arm/arch-iop33x/memory.h create mode 100644 include/asm-arm/arch-iop33x/system.h create mode 100644 include/asm-arm/arch-iop33x/timex.h create mode 100644 include/asm-arm/arch-iop33x/uncompress.h create mode 100644 include/asm-arm/arch-iop33x/vmalloc.h delete mode 100644 include/asm-arm/arch-iop3xx/debug-macro.S delete mode 100644 include/asm-arm/arch-iop3xx/dma.h delete mode 100644 include/asm-arm/arch-iop3xx/entry-macro.S delete mode 100644 include/asm-arm/arch-iop3xx/hardware.h delete mode 100644 include/asm-arm/arch-iop3xx/io.h delete mode 100644 include/asm-arm/arch-iop3xx/iop321-irqs.h delete mode 100644 include/asm-arm/arch-iop3xx/iop321.h delete mode 100644 include/asm-arm/arch-iop3xx/iop331-irqs.h delete mode 100644 include/asm-arm/arch-iop3xx/iop331.h delete mode 100644 include/asm-arm/arch-iop3xx/iq31244.h delete mode 100644 include/asm-arm/arch-iop3xx/iq80321.h delete mode 100644 include/asm-arm/arch-iop3xx/iq80331.h delete mode 100644 include/asm-arm/arch-iop3xx/iq80332.h delete mode 100644 include/asm-arm/arch-iop3xx/irqs.h delete mode 100644 include/asm-arm/arch-iop3xx/memory.h delete mode 100644 include/asm-arm/arch-iop3xx/system.h delete mode 100644 include/asm-arm/arch-iop3xx/timex.h delete mode 100644 include/asm-arm/arch-iop3xx/uncompress.h delete mode 100644 include/asm-arm/arch-iop3xx/vmalloc.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d9376f048ed7..0fb17bbb86bc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -202,12 +202,20 @@ config ARCH_IMX help Support for Motorola's i.MX family of processors (MX1, MXL). -config ARCH_IOP3XX - bool "IOP3xx-based" +config ARCH_IOP32X + bool "IOP32x-based" depends on MMU select PCI help - Support for Intel's IOP3XX (XScale) family of processors. + Support for Intel's 80219 and IOP32X (XScale) family of + processors. + +config ARCH_IOP33X + bool "IOP33x-based" + depends on MMU + select PCI + help + Support for Intel's IOP33X (XScale) family of processors. config ARCH_IXP4XX bool "IXP4xx-based" @@ -312,7 +320,9 @@ source "arch/arm/mach-footbridge/Kconfig" source "arch/arm/mach-integrator/Kconfig" -source "arch/arm/mach-iop3xx/Kconfig" +source "arch/arm/mach-iop32x/Kconfig" + +source "arch/arm/mach-iop33x/Kconfig" source "arch/arm/mach-ixp4xx/Kconfig" @@ -848,7 +858,7 @@ source "drivers/block/Kconfig" source "drivers/acorn/block/Kconfig" -if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \ +if PCMCIA || ARCH_CLPS7500 || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX \ || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \ || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \ || ARCH_IXP23XX diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 92873cdee31f..ac786bf0f546 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -101,7 +101,8 @@ endif machine-$(CONFIG_ARCH_INTEGRATOR) := integrator textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 machine-$(CONFIG_ARCH_CLPS711X) := clps711x - machine-$(CONFIG_ARCH_IOP3XX) := iop3xx + machine-$(CONFIG_ARCH_IOP32X) := iop32x + machine-$(CONFIG_ARCH_IOP33X) := iop33x machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx machine-$(CONFIG_ARCH_IXP2000) := ixp2000 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx diff --git a/arch/arm/configs/ep80219_defconfig b/arch/arm/configs/ep80219_defconfig index 199f1567345d..f91cf8ff359d 100644 --- a/arch/arm/configs/ep80219_defconfig +++ b/arch/arm/configs/ep80219_defconfig @@ -66,7 +66,8 @@ CONFIG_KMOD=y # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set -CONFIG_ARCH_IOP3XX=y +CONFIG_ARCH_IOP32X=y +# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_L7200 is not set @@ -93,8 +94,6 @@ CONFIG_ARCH_IQ31244=y # CONFIG_ARCH_IQ80331 is not set # CONFIG_MACH_IQ80332 is not set CONFIG_ARCH_EP80219=y -CONFIG_ARCH_IOP32X=y -# CONFIG_ARCH_IOP33X is not set # # IOP3xx Chipset Features diff --git a/arch/arm/configs/iq31244_defconfig b/arch/arm/configs/iq31244_defconfig index 27f884417b90..ce1b1f20b763 100644 --- a/arch/arm/configs/iq31244_defconfig +++ b/arch/arm/configs/iq31244_defconfig @@ -67,7 +67,8 @@ CONFIG_KMOD=y # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set -CONFIG_ARCH_IOP3XX=y +CONFIG_ARCH_IOP32X=y +# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_L7200 is not set @@ -94,8 +95,6 @@ CONFIG_ARCH_IQ31244=y # CONFIG_ARCH_IQ80331 is not set # CONFIG_MACH_IQ80332 is not set # CONFIG_ARCH_EP80219 is not set -CONFIG_ARCH_IOP32X=y -# CONFIG_ARCH_IOP33X is not set # # IOP3xx Chipset Features diff --git a/arch/arm/configs/iq80321_defconfig b/arch/arm/configs/iq80321_defconfig index 33f21a24cf4e..f00b0d2159dd 100644 --- a/arch/arm/configs/iq80321_defconfig +++ b/arch/arm/configs/iq80321_defconfig @@ -66,7 +66,8 @@ CONFIG_KMOD=y # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set -CONFIG_ARCH_IOP3XX=y +CONFIG_ARCH_IOP32X=y +# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_L7200 is not set @@ -93,8 +94,6 @@ CONFIG_ARCH_IQ80321=y # CONFIG_ARCH_IQ80331 is not set # CONFIG_MACH_IQ80332 is not set # CONFIG_ARCH_EP80219 is not set -CONFIG_ARCH_IOP32X=y -# CONFIG_ARCH_IOP33X is not set # # IOP3xx Chipset Features diff --git a/arch/arm/configs/iq80331_defconfig b/arch/arm/configs/iq80331_defconfig index 67a8bd7dba29..af3a87e469d5 100644 --- a/arch/arm/configs/iq80331_defconfig +++ b/arch/arm/configs/iq80331_defconfig @@ -66,7 +66,8 @@ CONFIG_KMOD=y # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set -CONFIG_ARCH_IOP3XX=y +# CONFIG_ARCH_IOP32X is not set +CONFIG_ARCH_IOP33X=y # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_L7200 is not set @@ -93,7 +94,6 @@ CONFIG_ARCH_IOP3XX=y CONFIG_ARCH_IQ80331=y # CONFIG_MACH_IQ80332 is not set # CONFIG_ARCH_EP80219 is not set -CONFIG_ARCH_IOP33X=y # # IOP3xx Chipset Features diff --git a/arch/arm/configs/iq80332_defconfig b/arch/arm/configs/iq80332_defconfig index c8dea45cb017..931c78755a30 100644 --- a/arch/arm/configs/iq80332_defconfig +++ b/arch/arm/configs/iq80332_defconfig @@ -66,7 +66,8 @@ CONFIG_KMOD=y # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set -CONFIG_ARCH_IOP3XX=y +# CONFIG_ARCH_IOP32X is not set +CONFIG_ARCH_IOP33X=y # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_L7200 is not set @@ -93,7 +94,6 @@ CONFIG_ARCH_IOP3XX=y # CONFIG_ARCH_IQ80331 is not set CONFIG_MACH_IQ80332=y # CONFIG_ARCH_EP80219 is not set -CONFIG_ARCH_IOP33X=y # # IOP3xx Chipset Features diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig new file mode 100644 index 000000000000..21e3e8c8c2ad --- /dev/null +++ b/arch/arm/mach-iop32x/Kconfig @@ -0,0 +1,28 @@ +if ARCH_IOP32X + +menu "IOP32x Implementation Options" + +comment "IOP32x Platform Types" + +config ARCH_IQ80321 + bool "Enable support for IQ80321" + help + Say Y here if you want to run your kernel on the Intel IQ80321 + evaluation kit for the IOP321 chipset. + +config ARCH_IQ31244 + bool "Enable support for IQ31244" + help + Say Y here if you want to run your kernel on the Intel IQ31244 + evaluation kit for the IOP321 chipset. + +config ARCH_EP80219 + bool "Enable support for EP80219" + select ARCH_IQ31244 + help + Say Y here if you want to run your kernel on the Intel EP80219 + evaluation kit for the Intel 80219 chipset (a IOP321 variant). + +endmenu + +endif diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile new file mode 100644 index 000000000000..94144f7efa6c --- /dev/null +++ b/arch/arm/mach-iop32x/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for the linux kernel. +# + +obj-y := common.o setup.o irq.o pci.o time.o +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o +obj-$(CONFIG_ARCH_IQ31244) += iq31244-mm.o iq31244-pci.o diff --git a/arch/arm/mach-iop32x/Makefile.boot b/arch/arm/mach-iop32x/Makefile.boot new file mode 100644 index 000000000000..47000dccd61f --- /dev/null +++ b/arch/arm/mach-iop32x/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0xa0008000 +params_phys-y := 0xa0000100 +initrd_phys-y := 0xa0800000 diff --git a/arch/arm/mach-iop32x/common.c b/arch/arm/mach-iop32x/common.c new file mode 100644 index 000000000000..8044af6a54e1 --- /dev/null +++ b/arch/arm/mach-iop32x/common.c @@ -0,0 +1,72 @@ +/* + * arch/arm/mach-iop32x/common.c + * + * Common routines shared across all IOP3xx implementations + * + * Author: Deepak Saxena + * + * Copyright 2003 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + +/* + * Shared variables + */ +unsigned long iop3xx_pcibios_min_io = 0; +unsigned long iop3xx_pcibios_min_mem = 0; + +#ifdef CONFIG_ARCH_EP80219 +#include +/* + * Default power-off for EP80219 + */ + +static inline void ep80219_send_to_pic(__u8 c) { +} + +void ep80219_power_off(void) +{ + /* + * This function will send a SHUTDOWN_COMPLETE message to the PIC controller + * over I2C. We are not using the i2c subsystem since we are going to power + * off and it may be removed + */ + + /* Send the Address byte w/ the start condition */ + *IOP321_IDBR1 = 0x60; + *IOP321_ICR1 = 0xE9; + mdelay(1); + + /* Send the START_MSG byte w/ no start or stop condition */ + *IOP321_IDBR1 = 0x0F; + *IOP321_ICR1 = 0xE8; + mdelay(1); + + /* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or stop condition */ + *IOP321_IDBR1 = 0x03; + *IOP321_ICR1 = 0xE8; + mdelay(1); + + /* Send an ignored byte w/ stop condition */ + *IOP321_IDBR1 = 0x00; + *IOP321_ICR1 = 0xEA; + + while (1) ; +} + +#include +#include + +static int __init ep80219_init(void) +{ + pm_power_off = ep80219_power_off; + return 0; +} +arch_initcall(ep80219_init); +#endif diff --git a/arch/arm/mach-iop32x/iq31244-mm.c b/arch/arm/mach-iop32x/iq31244-mm.c new file mode 100644 index 000000000000..ffc6692c95ad --- /dev/null +++ b/arch/arm/mach-iop32x/iq31244-mm.c @@ -0,0 +1,45 @@ +/* + * linux/arch/arm/mach-iop32x/iq31244-mm.c + * + * Low level memory initialization for iq80321 platform + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include + +#include +#include +#include + +#include + + +/* + * IQ80321 specific IO mappings + * + * We use RedBoot's setup for the onboard devices. + */ +static struct map_desc iq31244_io_desc[] __initdata = { + { /* on-board devices */ + .virtual = IQ31244_UART, + .pfn = __phys_to_pfn(IQ31244_UART), + .length = 0x00100000, + .type = MT_DEVICE + } +}; + +void __init iq31244_map_io(void) +{ + iop321_map_io(); + + iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc)); +} diff --git a/arch/arm/mach-iop32x/iq31244-pci.c b/arch/arm/mach-iop32x/iq31244-pci.c new file mode 100644 index 000000000000..e447c8103ecd --- /dev/null +++ b/arch/arm/mach-iop32x/iq31244-pci.c @@ -0,0 +1,129 @@ +/* + * arch/arm/mach-iop32x/iq31244-pci.c + * + * PCI support for the Intel IQ31244 reference board + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* + * The following macro is used to lookup irqs in a standard table + * format for those systems that do not already have PCI + * interrupts properly routed. We assume 1 <= pin <= 4 + */ +#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ +({ int _ctl_ = -1; \ + unsigned int _idsel = idsel - minid; \ + if (_idsel <= maxid) \ + _ctl_ = pci_irq_table[_idsel][pin-1]; \ + _ctl_; }) + +#define INTA IRQ_IQ31244_INTA +#define INTB IRQ_IQ31244_INTB +#define INTC IRQ_IQ31244_INTC +#define INTD IRQ_IQ31244_INTD + +#define INTE IRQ_IQ31244_I82546 + +static inline int __init +iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +{ + static int pci_irq_table[][4] = { + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ +#ifdef CONFIG_ARCH_EP80219 + {INTB, INTB, INTB, INTB}, /* CFlash */ + {INTE, INTE, INTE, INTE}, /* 82551 Pro 100 */ + {INTD, INTD, INTD, INTD}, /* PCI-X Slot */ + {INTC, INTC, INTC, INTC}, /* SATA */ +#else + {INTB, INTB, INTB, INTB}, /* CFlash */ + {INTC, INTC, INTC, INTC}, /* SATA */ + {INTD, INTD, INTD, INTD}, /* PCI-X Slot */ + {INTE, INTE, INTE, INTE}, /* 82546 GigE */ +#endif // CONFIG_ARCH_EP80219 + }; + + BUG_ON(pin < 1 || pin > 4); + + return PCI_IRQ_TABLE_LOOKUP(0, 7); +} + +static int iq31244_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + if(nr != 0) + return 0; + + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + res[0].start = IOP321_PCI_LOWER_IO_VA; + res[0].end = IOP321_PCI_UPPER_IO_VA; + res[0].name = "IQ31244 PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + + res[1].start = IOP321_PCI_LOWER_MEM_PA; + res[1].end = IOP321_PCI_UPPER_MEM_PA; + res[1].name = "IQ31244 PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); + + sys->mem_offset = IOP321_PCI_MEM_OFFSET; + sys->io_offset = IOP321_PCI_IO_OFFSET; + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + + return 1; +} + +static void iq31244_preinit(void) +{ + iop321_init(); +} + +static struct hw_pci iq31244_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iq31244_setup, + .scan = iop321_scan_bus, + .preinit = iq31244_preinit, + .map_irq = iq31244_map_irq +}; + +static int __init iq31244_pci_init(void) +{ + if (machine_is_iq31244()) + pci_common_init(&iq31244_pci); + return 0; +} + +subsys_initcall(iq31244_pci_init); + + + + diff --git a/arch/arm/mach-iop32x/iq80321-mm.c b/arch/arm/mach-iop32x/iq80321-mm.c new file mode 100644 index 000000000000..5f702a7ff622 --- /dev/null +++ b/arch/arm/mach-iop32x/iq80321-mm.c @@ -0,0 +1,45 @@ +/* + * linux/arch/arm/mach-iop32x/iq80321-mm.c + * + * Low level memory initialization for iq80321 platform + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include + +#include +#include +#include + +#include + + +/* + * IQ80321 specific IO mappings + * + * We use RedBoot's setup for the onboard devices. + */ +static struct map_desc iq80321_io_desc[] __initdata = { + { /* on-board devices */ + .virtual = IQ80321_UART, + .pfn = __phys_to_pfn(IQ80321_UART), + .length = 0x00100000, + .type = MT_DEVICE + } +}; + +void __init iq80321_map_io(void) +{ + iop321_map_io(); + + iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc)); +} diff --git a/arch/arm/mach-iop32x/iq80321-pci.c b/arch/arm/mach-iop32x/iq80321-pci.c new file mode 100644 index 000000000000..8767950e131f --- /dev/null +++ b/arch/arm/mach-iop32x/iq80321-pci.c @@ -0,0 +1,123 @@ +/* + * arch/arm/mach-iop32x/iq80321-pci.c + * + * PCI support for the Intel IQ80321 reference board + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* + * The following macro is used to lookup irqs in a standard table + * format for those systems that do not already have PCI + * interrupts properly routed. We assume 1 <= pin <= 4 + */ +#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ +({ int _ctl_ = -1; \ + unsigned int _idsel = idsel - minid; \ + if (_idsel <= maxid) \ + _ctl_ = pci_irq_table[_idsel][pin-1]; \ + _ctl_; }) + +#define INTA IRQ_IQ80321_INTA +#define INTB IRQ_IQ80321_INTB +#define INTC IRQ_IQ80321_INTC +#define INTD IRQ_IQ80321_INTD + +#define INTE IRQ_IQ80321_I82544 + +static inline int __init +iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +{ + static int pci_irq_table[][4] = { + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + {INTE, INTE, INTE, INTE}, /* Gig-E */ + {-1, -1, -1, -1}, /* Unused */ + {INTC, INTD, INTA, INTB}, /* PCI-X Slot */ + {-1, -1, -1, -1}, + }; + + BUG_ON(pin < 1 || pin > 4); + +// return PCI_IRQ_TABLE_LOOKUP(4, 7); + return pci_irq_table[idsel%4][pin-1]; +} + +static int iq80321_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + if(nr != 0) + return 0; + + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + res[0].start = IOP321_PCI_LOWER_IO_VA; + res[0].end = IOP321_PCI_UPPER_IO_VA; + res[0].name = "IQ80321 PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + + res[1].start = IOP321_PCI_LOWER_MEM_PA; + res[1].end = IOP321_PCI_UPPER_MEM_PA; + res[1].name = "IQ80321 PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); + + sys->mem_offset = IOP321_PCI_MEM_OFFSET; + sys->io_offset = IOP321_PCI_IO_OFFSET; + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + + return 1; +} + +static void iq80321_preinit(void) +{ + iop321_init(); +} + +static struct hw_pci iq80321_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iq80321_setup, + .scan = iop321_scan_bus, + .preinit = iq80321_preinit, + .map_irq = iq80321_map_irq +}; + +static int __init iq80321_pci_init(void) +{ + if (machine_is_iq80321()) + pci_common_init(&iq80321_pci); + return 0; +} + +subsys_initcall(iq80321_pci_init); + + + + diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c new file mode 100644 index 000000000000..c5f633d2d632 --- /dev/null +++ b/arch/arm/mach-iop32x/irq.c @@ -0,0 +1,97 @@ +/* + * linux/arch/arm/mach-iop32x/irq.c + * + * Generic IOP32X IRQ handling functionality + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Added IOP3XX chipset and IQ80321 board masking code. + * + */ +#include +#include +#include + +#include +#include +#include + +#include + +static u32 iop321_mask /* = 0 */; + +static inline void intctl_write(u32 val) +{ + asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); +} + +static inline void intstr_write(u32 val) +{ + asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); +} + +static void +iop321_irq_mask (unsigned int irq) +{ + + iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS)); + + intctl_write(iop321_mask); +} + +static void +iop321_irq_unmask (unsigned int irq) +{ + iop321_mask |= (1 << (irq - IOP321_IRQ_OFS)); + + intctl_write(iop321_mask); +} + +struct irq_chip ext_chip = { + .name = "IOP", + .ack = iop321_irq_mask, + .mask = iop321_irq_mask, + .unmask = iop321_irq_unmask, +}; + +void __init iop321_init_irq(void) +{ + unsigned int i, tmp; + + /* Enable access to coprocessor 6 for dealing with IRQs. + * From RMK: + * Basically, the Intel documentation here is poor. It appears that + * you need to set the bit to be able to access the coprocessor from + * SVC mode. Whether that allows access from user space or not is + * unclear. + */ + asm volatile ( + "mrc p15, 0, %0, c15, c1, 0\n\t" + "orr %0, %0, %1\n\t" + "mcr p15, 0, %0, c15, c1, 0\n\t" + /* The action is delayed, so we have to do this: */ + "mrc p15, 0, %0, c15, c1, 0\n\t" + "mov %0, %0\n\t" + "sub pc, pc, #4" + : "=r" (tmp) : "i" (1 << 6) ); + + intctl_write(0); // disable all interrupts + intstr_write(0); // treat all as IRQ + if(machine_is_iq80321() || + machine_is_iq31244()) // all interrupts are inputs to chip + *IOP321_PCIIRSR = 0x0f; + + for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++) + { + set_irq_chip(i, &ext_chip); + set_irq_handler(i, do_level_IRQ); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + + } +} + diff --git a/arch/arm/mach-iop32x/pci.c b/arch/arm/mach-iop32x/pci.c new file mode 100644 index 000000000000..1a7c683673f2 --- /dev/null +++ b/arch/arm/mach-iop32x/pci.c @@ -0,0 +1,220 @@ +/* + * arch/arm/mach-iop32x/pci.c + * + * PCI support for the Intel IOP321 chipset + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +// #define DEBUG + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) do { } while (0) +#endif + +/* + * This routine builds either a type0 or type1 configuration command. If the + * bus is on the 80321 then a type0 made, else a type1 is created. + */ +static u32 iop321_cfg_address(struct pci_bus *bus, int devfn, int where) +{ + struct pci_sys_data *sys = bus->sysdata; + u32 addr; + + if (sys->busnr == bus->number) + addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); + else + addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; + + addr |= PCI_FUNC(devfn) << 8 | (where & ~3); + + return addr; +} + +/* + * This routine checks the status of the last configuration cycle. If an error + * was detected it returns a 1, else it returns a 0. The errors being checked + * are parity, master abort, target abort (master and target). These types of + * errors occure during a config cycle where there is no device, like during + * the discovery stage. + */ +static int iop321_pci_status(void) +{ + unsigned int status; + int ret = 0; + + /* + * Check the status registers. + */ + status = *IOP321_ATUSR; + if (status & 0xf900) + { + DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); + *IOP321_ATUSR = status & 0xf900; + ret = 1; + } + status = *IOP321_ATUISR; + if (status & 0x679f) + { + DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); + *IOP321_ATUISR = status & 0x679f; + ret = 1; + } + return ret; +} + +/* + * Simply write the address register and read the configuration + * data. Note that the 4 nop's ensure that we are able to handle + * a delayed abort (in theory.) + */ +static inline u32 iop321_read(unsigned long addr) +{ + u32 val; + + __asm__ __volatile__( + "str %1, [%2]\n\t" + "ldr %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : "=r" (val) + : "r" (addr), "r" (IOP321_OCCAR), "r" (IOP321_OCCDR)); + + return val; +} + +/* + * The read routines must check the error status of the last configuration + * cycle. If there was an error, the routine returns all hex f's. + */ +static int +iop321_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + unsigned long addr = iop321_cfg_address(bus, devfn, where); + u32 val = iop321_read(addr) >> ((where & 3) * 8); + + if( iop321_pci_status() ) + val = 0xffffffff; + + *value = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + unsigned long addr = iop321_cfg_address(bus, devfn, where); + u32 val; + + if (size != 4) { + val = iop321_read(addr); + if (!iop321_pci_status() == 0) + return PCIBIOS_SUCCESSFUL; + + where = (where & 3) * 8; + + if (size == 1) + val &= ~(0xff << where); + else + val &= ~(0xffff << where); + + *IOP321_OCCDR = val | value << where; + } else { + asm volatile( + "str %1, [%2]\n\t" + "str %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : + : "r" (value), "r" (addr), + "r" (IOP321_OCCAR), "r" (IOP321_OCCDR)); + } + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops iop321_ops = { + .read = iop321_read_config, + .write = iop321_write_config, +}; + +/* + * When a PCI device does not exist during config cycles, the 80200 gets a + * bus error instead of returning 0xffffffff. This handler simply returns. + */ +int +iop321_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", + addr, fsr, regs->ARM_pc, regs->ARM_lr); + + /* + * If it was an imprecise abort, then we need to correct the + * return address to be _after_ the instruction. + */ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; + + return 0; +} + +/* + * Scan an IOP321 PCI bus. sys->bus defines which bus we scan. + */ +struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &iop321_ops, sys); +} + +void iop321_init(void) +{ + DBG("PCI: Intel 80321 PCI init code.\n"); + DBG("ATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD); + DBG("ATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n", + *IOP321_OMWTVR0, + *IOP321_OIOWTVR); + DBG("ATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR); + DBG("ATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n", + *IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0); + DBG("ATU: IOP321_OMWTVR0=0x%08x\n", *IOP321_OMWTVR0); + DBG("ATU: IOP321_IABAR1=0x%08x IOP321_IALR1=0x%08x\n", + *IOP321_IABAR1, *IOP321_IALR1); + DBG("ATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n", + *IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR); + DBG("ATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n", + *IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2); + DBG("ATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n", + *IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3); + + hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort"); +} + diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c new file mode 100644 index 000000000000..729678799271 --- /dev/null +++ b/arch/arm/mach-iop32x/setup.c @@ -0,0 +1,173 @@ +/* + * linux/arch/arm/mach-iop32x/setup.c + * + * Author: Nicolas Pitre + * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2004 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IOP321_UART_XTAL 1843200 + +/* + * Standard IO mapping for all IOP321 based systems + */ +static struct map_desc iop321_std_desc[] __initdata = { + { /* mem mapped registers */ + .virtual = IOP321_VIRT_MEM_BASE, + .pfn = __phys_to_pfn(IOP321_PHYS_MEM_BASE), + .length = 0x00002000, + .type = MT_DEVICE + }, { /* PCI IO space */ + .virtual = IOP321_PCI_LOWER_IO_VA, + .pfn = __phys_to_pfn(IOP321_PCI_LOWER_IO_PA), + .length = IOP321_PCI_IO_WINDOW_SIZE, + .type = MT_DEVICE + } +}; + +#ifdef CONFIG_ARCH_IQ80321 +#define UARTBASE IQ80321_UART +#define IRQ_UART IRQ_IQ80321_UART +#endif + +#ifdef CONFIG_ARCH_IQ31244 +#define UARTBASE IQ31244_UART +#define IRQ_UART IRQ_IQ31244_UART +#endif + +static struct uart_port iop321_serial_ports[] = { + { + .membase = (char*)(UARTBASE), + .mapbase = (UARTBASE), + .irq = IRQ_UART, + .flags = UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 0, + .uartclk = IOP321_UART_XTAL, + .line = 0, + .type = PORT_16550A, + .fifosize = 16 + } +}; + +static struct resource iop32x_i2c_0_resources[] = { + [0] = { + .start = 0xfffff680, + .end = 0xfffff698, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP321_I2C_0, + .end = IRQ_IOP321_I2C_0, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource iop32x_i2c_1_resources[] = { + [0] = { + .start = 0xfffff6a0, + .end = 0xfffff6b8, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP321_I2C_1, + .end = IRQ_IOP321_I2C_1, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device iop32x_i2c_0_controller = { + .name = "IOP3xx-I2C", + .id = 0, + .num_resources = 2, + .resource = iop32x_i2c_0_resources +}; + +static struct platform_device iop32x_i2c_1_controller = { + .name = "IOP3xx-I2C", + .id = 1, + .num_resources = 2, + .resource = iop32x_i2c_1_resources +}; + +static struct platform_device *iop32x_devices[] __initdata = { + &iop32x_i2c_0_controller, + &iop32x_i2c_1_controller +}; + +void __init iop32x_init(void) +{ + if(iop_is_321()) + { + platform_add_devices(iop32x_devices, + ARRAY_SIZE(iop32x_devices)); + } +} + +void __init iop321_map_io(void) +{ + iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc)); + early_serial_setup(&iop321_serial_ports[0]); +} + +#ifdef CONFIG_ARCH_IQ80321 +extern void iq80321_map_io(void); +extern struct sys_timer iop321_timer; +extern void iop321_init_time(void); +#endif + +#ifdef CONFIG_ARCH_IQ31244 +extern void iq31244_map_io(void); +extern struct sys_timer iop321_timer; +extern void iop321_init_time(void); +#endif + +#if defined(CONFIG_ARCH_IQ80321) +MACHINE_START(IQ80321, "Intel IQ80321") + /* Maintainer: Intel Corporation */ + .phys_io = IQ80321_UART, + .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, + .map_io = iq80321_map_io, + .init_irq = iop321_init_irq, + .timer = &iop321_timer, + .boot_params = 0xa0000100, + .init_machine = iop32x_init, +MACHINE_END +#elif defined(CONFIG_ARCH_IQ31244) +MACHINE_START(IQ31244, "Intel IQ31244") + /* Maintainer: Intel Corp. */ + .phys_io = IQ31244_UART, + .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, + .map_io = iq31244_map_io, + .init_irq = iop321_init_irq, + .timer = &iop321_timer, + .boot_params = 0xa0000100, + .init_machine = iop32x_init, +MACHINE_END +#else +#error No machine descriptor defined for this IOP3XX implementation +#endif diff --git a/arch/arm/mach-iop32x/time.c b/arch/arm/mach-iop32x/time.c new file mode 100644 index 000000000000..3cabbbca0a02 --- /dev/null +++ b/arch/arm/mach-iop32x/time.c @@ -0,0 +1,108 @@ +/* + * arch/arm/mach-iop32x/time.c + * + * Timer code for IOP321 based systems + * + * Author: Deepak Saxena + * + * Copyright 2002-2003 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define IOP321_TIME_SYNC 0 + +static inline unsigned long get_elapsed(void) +{ + return LATCH - *IOP321_TU_TCR0; +} + +static unsigned long iop321_gettimeoffset(void) +{ + unsigned long elapsed, usec; + u32 tisr1, tisr2; + + /* + * If an interrupt was pending before we read the timer, + * we've already wrapped. Factor this into the time. + * If an interrupt was pending after we read the timer, + * it may have wrapped between checking the interrupt + * status and reading the timer. Re-read the timer to + * be sure its value is after the wrap. + */ + + asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr1)); + elapsed = get_elapsed(); + asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr2)); + + if(tisr1 & 1) + elapsed += LATCH; + else if (tisr2 & 1) + elapsed = LATCH + get_elapsed(); + + /* + * Now convert them to usec. + */ + usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000)); + + return usec; +} + +static irqreturn_t +iop321_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + u32 tisr; + + write_seqlock(&xtime_lock); + + asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr)); + tisr |= 1; + asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr)); + + timer_tick(regs); + + write_sequnlock(&xtime_lock); + + return IRQ_HANDLED; +} + +static struct irqaction iop321_timer_irq = { + .name = "IOP321 Timer Tick", + .handler = iop321_timer_interrupt, + .flags = IRQF_DISABLED | IRQF_TIMER, +}; + +static void __init iop321_timer_init(void) +{ + u32 timer_ctl; + + setup_irq(IRQ_IOP321_TIMER0, &iop321_timer_irq); + + timer_ctl = IOP321_TMR_EN | IOP321_TMR_PRIVILEGED | IOP321_TMR_RELOAD | + IOP321_TMR_RATIO_1_1; + + asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (LATCH)); + + asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); +} + +struct sys_timer iop321_timer = { + .init = &iop321_timer_init, + .offset = iop321_gettimeoffset, +}; diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig new file mode 100644 index 000000000000..410df546e954 --- /dev/null +++ b/arch/arm/mach-iop33x/Kconfig @@ -0,0 +1,27 @@ +if ARCH_IOP33X + +menu "IOP33x Implementation Options" + +comment "IOP33x Platform Types" + +config ARCH_IQ80331 + bool "Enable support for IQ80331" + help + Say Y here if you want to run your kernel on the Intel IQ80331 + evaluation kit for the IOP331 chipset. + +config MACH_IQ80332 + bool "Enable support for IQ80332" + help + Say Y here if you want to run your kernel on the Intel IQ80332 + evaluation kit for the IOP332 chipset. + +config IOP331_STEPD + bool "Chip stepping D of the IOP80331 processor or IOP80333" + help + Say Y here if you have StepD of the IOP80331 or IOP8033 + based platforms. + +endmenu + +endif diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile new file mode 100644 index 000000000000..0f1a8fffe187 --- /dev/null +++ b/arch/arm/mach-iop33x/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for the linux kernel. +# + +obj-y := common.o setup.o irq.o pci.o time.o +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_ARCH_IQ80331) += iq80331-mm.o iq80331-pci.o +obj-$(CONFIG_MACH_IQ80332) += iq80332-mm.o iq80332-pci.o diff --git a/arch/arm/mach-iop33x/Makefile.boot b/arch/arm/mach-iop33x/Makefile.boot new file mode 100644 index 000000000000..67039c3e0c48 --- /dev/null +++ b/arch/arm/mach-iop33x/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-iop33x/common.c b/arch/arm/mach-iop33x/common.c new file mode 100644 index 000000000000..dd75f2b8e74f --- /dev/null +++ b/arch/arm/mach-iop33x/common.c @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-iop33x/common.c + * + * Common routines shared across all IOP3xx implementations + * + * Author: Deepak Saxena + * + * Copyright 2003 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + +/* + * Shared variables + */ +unsigned long iop3xx_pcibios_min_io = 0; +unsigned long iop3xx_pcibios_min_mem = 0; diff --git a/arch/arm/mach-iop33x/iq80331-mm.c b/arch/arm/mach-iop33x/iq80331-mm.c new file mode 100644 index 000000000000..eb59445a0fca --- /dev/null +++ b/arch/arm/mach-iop33x/iq80331-mm.c @@ -0,0 +1,35 @@ +/* + * linux/arch/arm/mach-iop33x/iq80331-mm.c + * + * Low level memory initialization for iq80331 platform + * + * Author: Dave Jiang + * Copyright (C) 2003 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include + +#include +#include +#include + +#include + + +/* + * IQ80331 specific IO mappings + * + * We use RedBoot's setup for the onboard devices. + */ + +void __init iq80331_map_io(void) +{ + iop331_map_io(); +} diff --git a/arch/arm/mach-iop33x/iq80331-pci.c b/arch/arm/mach-iop33x/iq80331-pci.c new file mode 100644 index 000000000000..71adb12a9421 --- /dev/null +++ b/arch/arm/mach-iop33x/iq80331-pci.c @@ -0,0 +1,119 @@ +/* + * arch/arm/mach-iop33x/iq80331-pci.c + * + * PCI support for the Intel IQ80331 reference board + * + * Author: Dave Jiang + * Copyright (C) 2003, 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* + * The following macro is used to lookup irqs in a standard table + * format for those systems that do not already have PCI + * interrupts properly routed. We assume 1 <= pin <= 4 + */ +#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ +({ int _ctl_ = -1; \ + unsigned int _idsel = idsel - minid; \ + if (_idsel <= maxid) \ + _ctl_ = pci_irq_table[_idsel][pin-1]; \ + _ctl_; }) + +#define INTA IRQ_IQ80331_INTA +#define INTB IRQ_IQ80331_INTB +#define INTC IRQ_IQ80331_INTC +#define INTD IRQ_IQ80331_INTD + +//#define INTE IRQ_IQ80331_I82544 + +static inline int __init +iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +{ + static int pci_irq_table[][4] = { + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + {INTB, INTC, INTD, INTA}, /* PCI-X Slot */ + {INTC, INTC, INTC, INTC}, /* GigE */ + }; + + BUG_ON(pin < 1 || pin > 4); + + return PCI_IRQ_TABLE_LOOKUP(1, 7); +} + +static int iq80331_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + if(nr != 0) + return 0; + + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + res[0].start = IOP331_PCI_LOWER_IO_VA; + res[0].end = IOP331_PCI_UPPER_IO_VA; + res[0].name = "IQ80331 PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + + res[1].start = IOP331_PCI_LOWER_MEM_PA; + res[1].end = IOP331_PCI_UPPER_MEM_PA; + res[1].name = "IQ80331 PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); + + sys->mem_offset = IOP331_PCI_MEM_OFFSET; + sys->io_offset = IOP331_PCI_IO_OFFSET; + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + + return 1; +} + +static void iq80331_preinit(void) +{ + iop331_init(); +} + +static struct hw_pci iq80331_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iq80331_setup, + .scan = iop331_scan_bus, + .preinit = iq80331_preinit, + .map_irq = iq80331_map_irq +}; + +static int __init iq80331_pci_init(void) +{ + if (machine_is_iq80331()) + pci_common_init(&iq80331_pci); + return 0; +} + +subsys_initcall(iq80331_pci_init); + + + + diff --git a/arch/arm/mach-iop33x/iq80332-mm.c b/arch/arm/mach-iop33x/iq80332-mm.c new file mode 100644 index 000000000000..f7bc73113ea8 --- /dev/null +++ b/arch/arm/mach-iop33x/iq80332-mm.c @@ -0,0 +1,35 @@ +/* + * linux/arch/arm/mach-iop33x/iq80332-mm.c + * + * Low level memory initialization for iq80332 platform + * + * Author: Dave Jiang + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include + +#include +#include +#include + +#include + + +/* + * IQ80332 specific IO mappings + * + * We use RedBoot's setup for the onboard devices. + */ + +void __init iq80332_map_io(void) +{ + iop331_map_io(); +} diff --git a/arch/arm/mach-iop33x/iq80332-pci.c b/arch/arm/mach-iop33x/iq80332-pci.c new file mode 100644 index 000000000000..f3010f85b1a2 --- /dev/null +++ b/arch/arm/mach-iop33x/iq80332-pci.c @@ -0,0 +1,125 @@ +/* + * arch/arm/mach-iop33x/iq80332-pci.c + * + * PCI support for the Intel IQ80332 reference board + * + * Author: Dave Jiang + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* + * The following macro is used to lookup irqs in a standard table + * format for those systems that do not already have PCI + * interrupts properly routed. We assume 1 <= pin <= 4 + */ +#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ +({ int _ctl_ = -1; \ + unsigned int _idsel = idsel - minid; \ + if (_idsel <= maxid) \ + _ctl_ = pci_irq_table[_idsel][pin-1]; \ + _ctl_; }) + +#define INTA IRQ_IQ80332_INTA +#define INTB IRQ_IQ80332_INTB +#define INTC IRQ_IQ80332_INTC +#define INTD IRQ_IQ80332_INTD + +//#define INTE IRQ_IQ80332_I82544 + +static inline int __init +iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +{ + static int pci_irq_table[][8] = { + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + {-1, -1, -1, -1}, + {-1, -1, -1, -1}, + {-1, -1, -1, -1}, + {INTA, INTB, INTC, INTD}, /* PCI-X Slot */ + {-1, -1, -1, -1}, + {INTC, INTC, INTC, INTC}, /* GigE */ + {-1, -1, -1, -1}, + {-1, -1, -1, -1}, + }; + + BUG_ON(pin < 1 || pin > 4); + + return PCI_IRQ_TABLE_LOOKUP(1, 7); +} + +static int iq80332_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + if(nr != 0) + return 0; + + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + res[0].start = IOP331_PCI_LOWER_IO_VA; + res[0].end = IOP331_PCI_UPPER_IO_VA; + res[0].name = "IQ80332 PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + + res[1].start = IOP331_PCI_LOWER_MEM_PA; + res[1].end = IOP331_PCI_UPPER_MEM_PA; + res[1].name = "IQ80332 PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); + + sys->mem_offset = IOP331_PCI_MEM_OFFSET; + sys->io_offset = IOP331_PCI_IO_OFFSET; + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + + return 1; +} + +static void iq80332_preinit(void) +{ + iop331_init(); +} + +static struct hw_pci iq80332_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iq80332_setup, + .scan = iop331_scan_bus, + .preinit = iq80332_preinit, + .map_irq = iq80332_map_irq +}; + +static int __init iq80332_pci_init(void) +{ + if (machine_is_iq80332()) + pci_common_init(&iq80332_pci); + return 0; +} + +subsys_initcall(iq80332_pci_init); + + + + diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c new file mode 100644 index 000000000000..029fa78876a5 --- /dev/null +++ b/arch/arm/mach-iop33x/irq.c @@ -0,0 +1,129 @@ +/* + * linux/arch/arm/mach-iop33x/irq.c + * + * Generic IOP331 IRQ handling functionality + * + * Author: Dave Jiang + * Copyright (C) 2003 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * + */ +#include +#include +#include + +#include +#include +#include + +#include + +static u32 iop331_mask0 = 0; +static u32 iop331_mask1 = 0; + +static inline void intctl_write0(u32 val) +{ + // INTCTL0 + asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); +} + +static inline void intctl_write1(u32 val) +{ + // INTCTL1 + asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val)); +} + +static inline void intstr_write0(u32 val) +{ + // INTSTR0 + asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val)); +} + +static inline void intstr_write1(u32 val) +{ + // INTSTR1 + asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val)); +} + +static void +iop331_irq_mask1 (unsigned int irq) +{ + iop331_mask0 &= ~(1 << (irq - IOP331_IRQ_OFS)); + intctl_write0(iop331_mask0); +} + +static void +iop331_irq_mask2 (unsigned int irq) +{ + iop331_mask1 &= ~(1 << (irq - IOP331_IRQ_OFS - 32)); + intctl_write1(iop331_mask1); +} + +static void +iop331_irq_unmask1(unsigned int irq) +{ + iop331_mask0 |= (1 << (irq - IOP331_IRQ_OFS)); + intctl_write0(iop331_mask0); +} + +static void +iop331_irq_unmask2(unsigned int irq) +{ + iop331_mask1 |= (1 << (irq - IOP331_IRQ_OFS - 32)); + intctl_write1(iop331_mask1); +} + +struct irq_chip iop331_irqchip1 = { + .name = "IOP-1", + .ack = iop331_irq_mask1, + .mask = iop331_irq_mask1, + .unmask = iop331_irq_unmask1, +}; + +struct irq_chip iop331_irqchip2 = { + .name = "IOP-2", + .ack = iop331_irq_mask2, + .mask = iop331_irq_mask2, + .unmask = iop331_irq_unmask2, +}; + +void __init iop331_init_irq(void) +{ + unsigned int i, tmp; + + /* Enable access to coprocessor 6 for dealing with IRQs. + * From RMK: + * Basically, the Intel documentation here is poor. It appears that + * you need to set the bit to be able to access the coprocessor from + * SVC mode. Whether that allows access from user space or not is + * unclear. + */ + asm volatile ( + "mrc p15, 0, %0, c15, c1, 0\n\t" + "orr %0, %0, %1\n\t" + "mcr p15, 0, %0, c15, c1, 0\n\t" + /* The action is delayed, so we have to do this: */ + "mrc p15, 0, %0, c15, c1, 0\n\t" + "mov %0, %0\n\t" + "sub pc, pc, #4" + : "=r" (tmp) : "i" (1 << 6) ); + + intctl_write0(0); // disable all interrupts + intctl_write1(0); + intstr_write0(0); // treat all as IRQ + intstr_write1(0); + if(machine_is_iq80331()) // all interrupts are inputs to chip + *IOP331_PCIIRSR = 0x0f; + + for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++) + { + set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2); + set_irq_handler(i, do_level_IRQ); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } +} + diff --git a/arch/arm/mach-iop33x/pci.c b/arch/arm/mach-iop33x/pci.c new file mode 100644 index 000000000000..bf6aba91b47d --- /dev/null +++ b/arch/arm/mach-iop33x/pci.c @@ -0,0 +1,222 @@ +/* + * arch/arm/mach-iop33x/pci.c + * + * PCI support for the Intel IOP331 chipset + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright (C) 2003, 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#undef DEBUG +#undef DEBUG1 + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) do { } while (0) +#endif + +#ifdef DEBUG1 +#define DBG1(x...) printk(x) +#else +#define DBG1(x...) do { } while (0) +#endif + +/* + * This routine builds either a type0 or type1 configuration command. If the + * bus is on the 80331 then a type0 made, else a type1 is created. + */ +static u32 iop331_cfg_address(struct pci_bus *bus, int devfn, int where) +{ + struct pci_sys_data *sys = bus->sysdata; + u32 addr; + + if (sys->busnr == bus->number) + addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); + else + addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; + + addr |= PCI_FUNC(devfn) << 8 | (where & ~3); + + return addr; +} + +/* + * This routine checks the status of the last configuration cycle. If an error + * was detected it returns a 1, else it returns a 0. The errors being checked + * are parity, master abort, target abort (master and target). These types of + * errors occure during a config cycle where there is no device, like during + * the discovery stage. + */ +static int iop331_pci_status(void) +{ + unsigned int status; + int ret = 0; + + /* + * Check the status registers. + */ + status = *IOP331_ATUSR; + if (status & 0xf900) + { + DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); + *IOP331_ATUSR = status & 0xf900; + ret = 1; + } + status = *IOP331_ATUISR; + if (status & 0x679f) + { + DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); + *IOP331_ATUISR = status & 0x679f; + ret = 1; + } + return ret; +} + +/* + * Simply write the address register and read the configuration + * data. Note that the 4 nop's ensure that we are able to handle + * a delayed abort (in theory.) + */ +static inline u32 iop331_read(unsigned long addr) +{ + u32 val; + + __asm__ __volatile__( + "str %1, [%2]\n\t" + "ldr %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : "=r" (val) + : "r" (addr), "r" (IOP331_OCCAR), "r" (IOP331_OCCDR)); + + return val; +} + +/* + * The read routines must check the error status of the last configuration + * cycle. If there was an error, the routine returns all hex f's. + */ +static int +iop331_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + unsigned long addr = iop331_cfg_address(bus, devfn, where); + u32 val = iop331_read(addr) >> ((where & 3) * 8); + + if( iop331_pci_status() ) + val = 0xffffffff; + + *value = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop331_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + unsigned long addr = iop331_cfg_address(bus, devfn, where); + u32 val; + + if (size != 4) { + val = iop331_read(addr); + if (!iop331_pci_status() == 0) + return PCIBIOS_SUCCESSFUL; + + where = (where & 3) * 8; + + if (size == 1) + val &= ~(0xff << where); + else + val &= ~(0xffff << where); + + *IOP331_OCCDR = val | value << where; + } else { + asm volatile( + "str %1, [%2]\n\t" + "str %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : + : "r" (value), "r" (addr), + "r" (IOP331_OCCAR), "r" (IOP331_OCCDR)); + } + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops iop331_ops = { + .read = iop331_read_config, + .write = iop331_write_config, +}; + +/* + * When a PCI device does not exist during config cycles, the XScale gets a + * bus error instead of returning 0xffffffff. This handler simply returns. + */ +int +iop331_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", + addr, fsr, regs->ARM_pc, regs->ARM_lr); + + /* + * If it was an imprecise abort, then we need to correct the + * return address to be _after_ the instruction. + */ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; + + return 0; +} + +/* + * Scan an IOP331 PCI bus. sys->bus defines which bus we scan. + */ +struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &iop331_ops, sys); +} + +void iop331_init(void) +{ + DBG1("PCI: Intel 80331 PCI init code.\n"); + DBG1("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD); + DBG1("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n", + *IOP331_OMWTVR0, + *IOP331_OIOWTVR); + DBG1("\tATU: IOP331_OMWTVR1=0x%04x\n", *IOP331_OMWTVR1); + DBG1("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR); + DBG1("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0); + DBG1("\tATU: IOP31_IABAR1=0x%08x IOP331_IALR1=0x%08x\n", *IOP331_IABAR1, *IOP331_IALR1); + DBG1("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR); + DBG1("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2); + DBG1("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3); + + hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort"); +} + diff --git a/arch/arm/mach-iop33x/setup.c b/arch/arm/mach-iop33x/setup.c new file mode 100644 index 000000000000..c14c7da5ec4c --- /dev/null +++ b/arch/arm/mach-iop33x/setup.c @@ -0,0 +1,221 @@ +/* + * linux/arch/arm/mach-iop33x/setup.c + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright (C) 2004 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IOP331_UART_XTAL 33334000 + +/* + * Standard IO mapping for all IOP331 based systems + */ +static struct map_desc iop331_std_desc[] __initdata = { + { /* mem mapped registers */ + .virtual = IOP331_VIRT_MEM_BASE, + .pfn = __phys_to_pfn(IOP331_PHYS_MEM_BASE), + .length = 0x00002000, + .type = MT_DEVICE + }, { /* PCI IO space */ + .virtual = IOP331_PCI_LOWER_IO_VA, + .pfn = __phys_to_pfn(IOP331_PCI_LOWER_IO_PA), + .length = IOP331_PCI_IO_WINDOW_SIZE, + .type = MT_DEVICE + } +}; + +static struct resource iop33x_uart0_resources[] = { + [0] = { + .start = IOP331_UART0_PHYS, + .end = IOP331_UART0_PHYS + 0x3f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP331_UART0, + .end = IRQ_IOP331_UART0, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource iop33x_uart1_resources[] = { + [0] = { + .start = IOP331_UART1_PHYS, + .end = IOP331_UART1_PHYS + 0x3f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP331_UART1, + .end = IRQ_IOP331_UART1, + .flags = IORESOURCE_IRQ + } +}; + +static struct plat_serial8250_port iop33x_uart0_data[] = { + { + .membase = (char*)(IOP331_UART0_VIRT), + .mapbase = (IOP331_UART0_PHYS), + .irq = IRQ_IOP331_UART0, + .uartclk = IOP331_UART_XTAL, + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_SKIP_TEST, + }, + { }, +}; + +static struct plat_serial8250_port iop33x_uart1_data[] = { + { + .membase = (char*)(IOP331_UART1_VIRT), + .mapbase = (IOP331_UART1_PHYS), + .irq = IRQ_IOP331_UART1, + .uartclk = IOP331_UART_XTAL, + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_SKIP_TEST, + }, + { }, +}; + +static struct platform_device iop33x_uart0 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev.platform_data = iop33x_uart0_data, + .num_resources = 2, + .resource = iop33x_uart0_resources, +}; + +static struct platform_device iop33x_uart1 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev.platform_data = iop33x_uart1_data, + .num_resources = 2, + .resource = iop33x_uart1_resources, +}; + +static struct resource iop33x_i2c_0_resources[] = { + [0] = { + .start = 0xfffff680, + .end = 0xfffff698, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP331_I2C_0, + .end = IRQ_IOP331_I2C_0, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource iop33x_i2c_1_resources[] = { + [0] = { + .start = 0xfffff6a0, + .end = 0xfffff6b8, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP331_I2C_1, + .end = IRQ_IOP331_I2C_1, + .flags = IORESOURCE_IRQ + } +}; + +static struct platform_device iop33x_i2c_0_controller = { + .name = "IOP3xx-I2C", + .id = 0, + .num_resources = 2, + .resource = iop33x_i2c_0_resources +}; + +static struct platform_device iop33x_i2c_1_controller = { + .name = "IOP3xx-I2C", + .id = 1, + .num_resources = 2, + .resource = iop33x_i2c_1_resources +}; + +static struct platform_device *iop33x_devices[] __initdata = { + &iop33x_uart0, + &iop33x_uart1, + &iop33x_i2c_0_controller, + &iop33x_i2c_1_controller +}; + +void __init iop33x_init(void) +{ + if(iop_is_331()) + { + platform_add_devices(iop33x_devices, + ARRAY_SIZE(iop33x_devices)); + } +} + +void __init iop331_map_io(void) +{ + iotable_init(iop331_std_desc, ARRAY_SIZE(iop331_std_desc)); +} + +#ifdef CONFIG_ARCH_IOP33X +extern void iop331_init_irq(void); +extern struct sys_timer iop331_timer; +#endif + +#ifdef CONFIG_ARCH_IQ80331 +extern void iq80331_map_io(void); +#endif + +#ifdef CONFIG_MACH_IQ80332 +extern void iq80332_map_io(void); +#endif + +#if defined(CONFIG_ARCH_IQ80331) +MACHINE_START(IQ80331, "Intel IQ80331") + /* Maintainer: Intel Corp. */ + .phys_io = 0xfefff000, + .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical + .map_io = iq80331_map_io, + .init_irq = iop331_init_irq, + .timer = &iop331_timer, + .boot_params = 0x0100, + .init_machine = iop33x_init, +MACHINE_END + +#elif defined(CONFIG_MACH_IQ80332) +MACHINE_START(IQ80332, "Intel IQ80332") + /* Maintainer: Intel Corp. */ + .phys_io = 0xfefff000, + .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical + .map_io = iq80332_map_io, + .init_irq = iop331_init_irq, + .timer = &iop331_timer, + .boot_params = 0x0100, + .init_machine = iop33x_init, +MACHINE_END + +#else +#error No machine descriptor defined for this IOP3XX implementation +#endif + + diff --git a/arch/arm/mach-iop33x/time.c b/arch/arm/mach-iop33x/time.c new file mode 100644 index 000000000000..d839cd0d926e --- /dev/null +++ b/arch/arm/mach-iop33x/time.c @@ -0,0 +1,106 @@ +/* + * arch/arm/mach-iop33x/time.c + * + * Timer code for IOP331 based systems + * + * Author: Dave Jiang + * + * Copyright 2003 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +static inline unsigned long get_elapsed(void) +{ + return LATCH - *IOP331_TU_TCR0; +} + +static unsigned long iop331_gettimeoffset(void) +{ + unsigned long elapsed, usec; + u32 tisr1, tisr2; + + /* + * If an interrupt was pending before we read the timer, + * we've already wrapped. Factor this into the time. + * If an interrupt was pending after we read the timer, + * it may have wrapped between checking the interrupt + * status and reading the timer. Re-read the timer to + * be sure its value is after the wrap. + */ + + asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr1)); + elapsed = get_elapsed(); + asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr2)); + + if(tisr1 & 1) + elapsed += LATCH; + else if (tisr2 & 1) + elapsed = LATCH + get_elapsed(); + + /* + * Now convert them to usec. + */ + usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000)); + + return usec; +} + +static irqreturn_t +iop331_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + u32 tisr; + + write_seqlock(&xtime_lock); + + asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr)); + tisr |= 1; + asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr)); + + timer_tick(regs); + + write_sequnlock(&xtime_lock); + return IRQ_HANDLED; +} + +static struct irqaction iop331_timer_irq = { + .name = "IOP331 Timer Tick", + .handler = iop331_timer_interrupt, + .flags = IRQF_DISABLED | IRQF_TIMER, +}; + +static void __init iop331_timer_init(void) +{ + u32 timer_ctl; + + setup_irq(IRQ_IOP331_TIMER0, &iop331_timer_irq); + + timer_ctl = IOP331_TMR_EN | IOP331_TMR_PRIVILEGED | IOP331_TMR_RELOAD | + IOP331_TMR_RATIO_1_1; + + asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (LATCH)); + + asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); + +} + +struct sys_timer iop331_timer = { + .init = iop331_timer_init, + .offset = iop331_gettimeoffset, +}; diff --git a/arch/arm/mach-iop3xx/Kconfig b/arch/arm/mach-iop3xx/Kconfig deleted file mode 100644 index 887c3753727f..000000000000 --- a/arch/arm/mach-iop3xx/Kconfig +++ /dev/null @@ -1,66 +0,0 @@ -if ARCH_IOP3XX - -menu "IOP3xx Implementation Options" - -comment "IOP3xx Platform Types" - -config ARCH_IQ80321 - bool "Enable support for IQ80321" - select ARCH_IOP32X - help - Say Y here if you want to run your kernel on the Intel IQ80321 - evaluation kit for the IOP321 chipset. - -config ARCH_IQ31244 - bool "Enable support for IQ31244" - select ARCH_IOP32X - help - Say Y here if you want to run your kernel on the Intel IQ31244 - evaluation kit for the IOP321 chipset. - -config ARCH_IQ80331 - bool "Enable support for IQ80331" - select ARCH_IOP33X - help - Say Y here if you want to run your kernel on the Intel IQ80331 - evaluation kit for the IOP331 chipset. - -config MACH_IQ80332 - bool "Enable support for IQ80332" - select ARCH_IOP33X - help - Say Y here if you want to run your kernel on the Intel IQ80332 - evaluation kit for the IOP332 chipset. - -config ARCH_EP80219 - bool "Enable support for EP80219" - select ARCH_IOP32X - select ARCH_IQ31244 - help - Say Y here if you want to run your kernel on the Intel EP80219 - evaluation kit for the Intel 80219 chipset (a IOP321 variant). - -# Which IOP variant are we running? -config ARCH_IOP32X - bool - help - The IQ80321 uses the IOP321 variant. - The IQ31244 and EP80219 uses the IOP321 variant. - -config ARCH_IOP33X - bool - default ARCH_IQ80331 - help - The IQ80331, IQ80332, and IQ80333 uses the IOP331 variant. - -comment "IOP3xx Chipset Features" - -config IOP331_STEPD - bool "Chip stepping D of the IOP80331 processor or IOP80333" - depends on ARCH_IOP33X - help - Say Y here if you have StepD of the IOP80331 or IOP8033 - based platforms. - -endmenu -endif diff --git a/arch/arm/mach-iop3xx/Makefile b/arch/arm/mach-iop3xx/Makefile deleted file mode 100644 index ad3051524480..000000000000 --- a/arch/arm/mach-iop3xx/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := common.o - -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_ARCH_IOP32X) += iop321-setup.o iop321-irq.o iop321-pci.o iop321-time.o - -obj-$(CONFIG_ARCH_IOP33X) += iop331-setup.o iop331-irq.o iop331-pci.o iop331-time.o - -obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o - -obj-$(CONFIG_ARCH_IQ31244) += iq31244-mm.o iq31244-pci.o - -obj-$(CONFIG_ARCH_IQ80331) += iq80331-mm.o iq80331-pci.o - -obj-$(CONFIG_MACH_IQ80332) += iq80332-mm.o iq80332-pci.o diff --git a/arch/arm/mach-iop3xx/Makefile.boot b/arch/arm/mach-iop3xx/Makefile.boot deleted file mode 100644 index e120c233b706..000000000000 --- a/arch/arm/mach-iop3xx/Makefile.boot +++ /dev/null @@ -1,9 +0,0 @@ - zreladdr-y := 0xa0008000 -params_phys-y := 0xa0000100 -initrd_phys-y := 0xa0800000 -ifeq ($(CONFIG_ARCH_IOP33X),y) - zreladdr-y := 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 -endif - diff --git a/arch/arm/mach-iop3xx/common.c b/arch/arm/mach-iop3xx/common.c deleted file mode 100644 index d7f50e57e753..000000000000 --- a/arch/arm/mach-iop3xx/common.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * arch/arm/mach-iop3xx/common.c - * - * Common routines shared across all IOP3xx implementations - * - * Author: Deepak Saxena - * - * Copyright 2003 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include - -/* - * Shared variables - */ -unsigned long iop3xx_pcibios_min_io = 0; -unsigned long iop3xx_pcibios_min_mem = 0; - -#ifdef CONFIG_ARCH_EP80219 -#include -/* - * Default power-off for EP80219 - */ - -static inline void ep80219_send_to_pic(__u8 c) { -} - -void ep80219_power_off(void) -{ - /* - * This function will send a SHUTDOWN_COMPLETE message to the PIC controller - * over I2C. We are not using the i2c subsystem since we are going to power - * off and it may be removed - */ - - /* Send the Address byte w/ the start condition */ - *IOP321_IDBR1 = 0x60; - *IOP321_ICR1 = 0xE9; - mdelay(1); - - /* Send the START_MSG byte w/ no start or stop condition */ - *IOP321_IDBR1 = 0x0F; - *IOP321_ICR1 = 0xE8; - mdelay(1); - - /* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or stop condition */ - *IOP321_IDBR1 = 0x03; - *IOP321_ICR1 = 0xE8; - mdelay(1); - - /* Send an ignored byte w/ stop condition */ - *IOP321_IDBR1 = 0x00; - *IOP321_ICR1 = 0xEA; - - while (1) ; -} - -#include -#include - -static int __init ep80219_init(void) -{ - pm_power_off = ep80219_power_off; - return 0; -} -arch_initcall(ep80219_init); -#endif diff --git a/arch/arm/mach-iop3xx/iop321-irq.c b/arch/arm/mach-iop3xx/iop321-irq.c deleted file mode 100644 index 88ac333472c8..000000000000 --- a/arch/arm/mach-iop3xx/iop321-irq.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * linux/arch/arm/mach-iop3xx/iop321-irq.c - * - * Generic IOP321 IRQ handling functionality - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Added IOP3XX chipset and IQ80321 board masking code. - * - */ -#include -#include -#include - -#include -#include -#include - -#include - -static u32 iop321_mask /* = 0 */; - -static inline void intctl_write(u32 val) -{ - asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); -} - -static inline void intstr_write(u32 val) -{ - asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); -} - -static void -iop321_irq_mask (unsigned int irq) -{ - - iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS)); - - intctl_write(iop321_mask); -} - -static void -iop321_irq_unmask (unsigned int irq) -{ - iop321_mask |= (1 << (irq - IOP321_IRQ_OFS)); - - intctl_write(iop321_mask); -} - -struct irq_chip ext_chip = { - .name = "IOP", - .ack = iop321_irq_mask, - .mask = iop321_irq_mask, - .unmask = iop321_irq_unmask, -}; - -void __init iop321_init_irq(void) -{ - unsigned int i, tmp; - - /* Enable access to coprocessor 6 for dealing with IRQs. - * From RMK: - * Basically, the Intel documentation here is poor. It appears that - * you need to set the bit to be able to access the coprocessor from - * SVC mode. Whether that allows access from user space or not is - * unclear. - */ - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, %1\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - /* The action is delayed, so we have to do this: */ - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4" - : "=r" (tmp) : "i" (1 << 6) ); - - intctl_write(0); // disable all interrupts - intstr_write(0); // treat all as IRQ - if(machine_is_iq80321() || - machine_is_iq31244()) // all interrupts are inputs to chip - *IOP321_PCIIRSR = 0x0f; - - for(i = IOP321_IRQ_OFS; i < NR_IOP321_IRQS; i++) - { - set_irq_chip(i, &ext_chip); - set_irq_handler(i, do_level_IRQ); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - - } -} - diff --git a/arch/arm/mach-iop3xx/iop321-pci.c b/arch/arm/mach-iop3xx/iop321-pci.c deleted file mode 100644 index 8ba6a0e23134..000000000000 --- a/arch/arm/mach-iop3xx/iop321-pci.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * arch/arm/mach-iop3xx/iop321-pci.c - * - * PCI support for the Intel IOP321 chipset - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -// #define DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) do { } while (0) -#endif - -/* - * This routine builds either a type0 or type1 configuration command. If the - * bus is on the 80321 then a type0 made, else a type1 is created. - */ -static u32 iop321_cfg_address(struct pci_bus *bus, int devfn, int where) -{ - struct pci_sys_data *sys = bus->sysdata; - u32 addr; - - if (sys->busnr == bus->number) - addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); - else - addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; - - addr |= PCI_FUNC(devfn) << 8 | (where & ~3); - - return addr; -} - -/* - * This routine checks the status of the last configuration cycle. If an error - * was detected it returns a 1, else it returns a 0. The errors being checked - * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during - * the discovery stage. - */ -static int iop321_pci_status(void) -{ - unsigned int status; - int ret = 0; - - /* - * Check the status registers. - */ - status = *IOP321_ATUSR; - if (status & 0xf900) - { - DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); - *IOP321_ATUSR = status & 0xf900; - ret = 1; - } - status = *IOP321_ATUISR; - if (status & 0x679f) - { - DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); - *IOP321_ATUISR = status & 0x679f; - ret = 1; - } - return ret; -} - -/* - * Simply write the address register and read the configuration - * data. Note that the 4 nop's ensure that we are able to handle - * a delayed abort (in theory.) - */ -static inline u32 iop321_read(unsigned long addr) -{ - u32 val; - - __asm__ __volatile__( - "str %1, [%2]\n\t" - "ldr %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : "=r" (val) - : "r" (addr), "r" (IOP321_OCCAR), "r" (IOP321_OCCDR)); - - return val; -} - -/* - * The read routines must check the error status of the last configuration - * cycle. If there was an error, the routine returns all hex f's. - */ -static int -iop321_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - unsigned long addr = iop321_cfg_address(bus, devfn, where); - u32 val = iop321_read(addr) >> ((where & 3) * 8); - - if( iop321_pci_status() ) - val = 0xffffffff; - - *value = val; - - return PCIBIOS_SUCCESSFUL; -} - -static int -iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - unsigned long addr = iop321_cfg_address(bus, devfn, where); - u32 val; - - if (size != 4) { - val = iop321_read(addr); - if (!iop321_pci_status() == 0) - return PCIBIOS_SUCCESSFUL; - - where = (where & 3) * 8; - - if (size == 1) - val &= ~(0xff << where); - else - val &= ~(0xffff << where); - - *IOP321_OCCDR = val | value << where; - } else { - asm volatile( - "str %1, [%2]\n\t" - "str %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : - : "r" (value), "r" (addr), - "r" (IOP321_OCCAR), "r" (IOP321_OCCDR)); - } - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops iop321_ops = { - .read = iop321_read_config, - .write = iop321_write_config, -}; - -/* - * When a PCI device does not exist during config cycles, the 80200 gets a - * bus error instead of returning 0xffffffff. This handler simply returns. - */ -int -iop321_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", - addr, fsr, regs->ARM_pc, regs->ARM_lr); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -/* - * Scan an IOP321 PCI bus. sys->bus defines which bus we scan. - */ -struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_bus(sys->busnr, &iop321_ops, sys); -} - -void iop321_init(void) -{ - DBG("PCI: Intel 80321 PCI init code.\n"); - DBG("ATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD); - DBG("ATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n", - *IOP321_OMWTVR0, - *IOP321_OIOWTVR); - DBG("ATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR); - DBG("ATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n", - *IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0); - DBG("ATU: IOP321_OMWTVR0=0x%08x\n", *IOP321_OMWTVR0); - DBG("ATU: IOP321_IABAR1=0x%08x IOP321_IALR1=0x%08x\n", - *IOP321_IABAR1, *IOP321_IALR1); - DBG("ATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n", - *IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR); - DBG("ATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n", - *IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2); - DBG("ATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n", - *IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3); - - hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort"); -} - diff --git a/arch/arm/mach-iop3xx/iop321-setup.c b/arch/arm/mach-iop3xx/iop321-setup.c deleted file mode 100644 index b6d096903c4a..000000000000 --- a/arch/arm/mach-iop3xx/iop321-setup.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * linux/arch/arm/mach-iop3xx/iop321-setup.c - * - * Author: Nicolas Pitre - * Copyright (C) 2001 MontaVista Software, Inc. - * Copyright (C) 2004 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IOP321_UART_XTAL 1843200 - -/* - * Standard IO mapping for all IOP321 based systems - */ -static struct map_desc iop321_std_desc[] __initdata = { - { /* mem mapped registers */ - .virtual = IOP321_VIRT_MEM_BASE, - .pfn = __phys_to_pfn(IOP321_PHYS_MEM_BASE), - .length = 0x00002000, - .type = MT_DEVICE - }, { /* PCI IO space */ - .virtual = IOP321_PCI_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP321_PCI_LOWER_IO_PA), - .length = IOP321_PCI_IO_WINDOW_SIZE, - .type = MT_DEVICE - } -}; - -#ifdef CONFIG_ARCH_IQ80321 -#define UARTBASE IQ80321_UART -#define IRQ_UART IRQ_IQ80321_UART -#endif - -#ifdef CONFIG_ARCH_IQ31244 -#define UARTBASE IQ31244_UART -#define IRQ_UART IRQ_IQ31244_UART -#endif - -static struct uart_port iop321_serial_ports[] = { - { - .membase = (char*)(UARTBASE), - .mapbase = (UARTBASE), - .irq = IRQ_UART, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = IOP321_UART_XTAL, - .line = 0, - .type = PORT_16550A, - .fifosize = 16 - } -}; - -static struct resource iop32x_i2c_0_resources[] = { - [0] = { - .start = 0xfffff680, - .end = 0xfffff698, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP321_I2C_0, - .end = IRQ_IOP321_I2C_0, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop32x_i2c_1_resources[] = { - [0] = { - .start = 0xfffff6a0, - .end = 0xfffff6b8, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP321_I2C_1, - .end = IRQ_IOP321_I2C_1, - .flags = IORESOURCE_IRQ - } -}; - -static struct platform_device iop32x_i2c_0_controller = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = iop32x_i2c_0_resources -}; - -static struct platform_device iop32x_i2c_1_controller = { - .name = "IOP3xx-I2C", - .id = 1, - .num_resources = 2, - .resource = iop32x_i2c_1_resources -}; - -static struct platform_device *iop32x_devices[] __initdata = { - &iop32x_i2c_0_controller, - &iop32x_i2c_1_controller -}; - -void __init iop32x_init(void) -{ - if(iop_is_321()) - { - platform_add_devices(iop32x_devices, - ARRAY_SIZE(iop32x_devices)); - } -} - -void __init iop321_map_io(void) -{ - iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc)); - early_serial_setup(&iop321_serial_ports[0]); -} - -#ifdef CONFIG_ARCH_IQ80321 -extern void iq80321_map_io(void); -extern struct sys_timer iop321_timer; -extern void iop321_init_time(void); -#endif - -#ifdef CONFIG_ARCH_IQ31244 -extern void iq31244_map_io(void); -extern struct sys_timer iop321_timer; -extern void iop321_init_time(void); -#endif - -#if defined(CONFIG_ARCH_IQ80321) -MACHINE_START(IQ80321, "Intel IQ80321") - /* Maintainer: Intel Corporation */ - .phys_io = IQ80321_UART, - .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, - .map_io = iq80321_map_io, - .init_irq = iop321_init_irq, - .timer = &iop321_timer, - .boot_params = 0xa0000100, - .init_machine = iop32x_init, -MACHINE_END -#elif defined(CONFIG_ARCH_IQ31244) -MACHINE_START(IQ31244, "Intel IQ31244") - /* Maintainer: Intel Corp. */ - .phys_io = IQ31244_UART, - .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, - .map_io = iq31244_map_io, - .init_irq = iop321_init_irq, - .timer = &iop321_timer, - .boot_params = 0xa0000100, - .init_machine = iop32x_init, -MACHINE_END -#else -#error No machine descriptor defined for this IOP3XX implementation -#endif diff --git a/arch/arm/mach-iop3xx/iop321-time.c b/arch/arm/mach-iop3xx/iop321-time.c deleted file mode 100644 index 04b1a6f7ebae..000000000000 --- a/arch/arm/mach-iop3xx/iop321-time.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * arch/arm/mach-iop3xx/iop321-time.c - * - * Timer code for IOP321 based systems - * - * Author: Deepak Saxena - * - * Copyright 2002-2003 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define IOP321_TIME_SYNC 0 - -static inline unsigned long get_elapsed(void) -{ - return LATCH - *IOP321_TU_TCR0; -} - -static unsigned long iop321_gettimeoffset(void) -{ - unsigned long elapsed, usec; - u32 tisr1, tisr2; - - /* - * If an interrupt was pending before we read the timer, - * we've already wrapped. Factor this into the time. - * If an interrupt was pending after we read the timer, - * it may have wrapped between checking the interrupt - * status and reading the timer. Re-read the timer to - * be sure its value is after the wrap. - */ - - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr1)); - elapsed = get_elapsed(); - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr2)); - - if(tisr1 & 1) - elapsed += LATCH; - else if (tisr2 & 1) - elapsed = LATCH + get_elapsed(); - - /* - * Now convert them to usec. - */ - usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000)); - - return usec; -} - -static irqreturn_t -iop321_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - u32 tisr; - - write_seqlock(&xtime_lock); - - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr)); - tisr |= 1; - asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr)); - - timer_tick(regs); - - write_sequnlock(&xtime_lock); - - return IRQ_HANDLED; -} - -static struct irqaction iop321_timer_irq = { - .name = "IOP321 Timer Tick", - .handler = iop321_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER, -}; - -static void __init iop321_timer_init(void) -{ - u32 timer_ctl; - - setup_irq(IRQ_IOP321_TIMER0, &iop321_timer_irq); - - timer_ctl = IOP321_TMR_EN | IOP321_TMR_PRIVILEGED | IOP321_TMR_RELOAD | - IOP321_TMR_RATIO_1_1; - - asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (LATCH)); - - asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); -} - -struct sys_timer iop321_timer = { - .init = &iop321_timer_init, - .offset = iop321_gettimeoffset, -}; diff --git a/arch/arm/mach-iop3xx/iop331-irq.c b/arch/arm/mach-iop3xx/iop331-irq.c deleted file mode 100644 index cab11722ced2..000000000000 --- a/arch/arm/mach-iop3xx/iop331-irq.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * linux/arch/arm/mach-iop3xx/iop331-irq.c - * - * Generic IOP331 IRQ handling functionality - * - * Author: Dave Jiang - * Copyright (C) 2003 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * - */ -#include -#include -#include - -#include -#include -#include - -#include - -static u32 iop331_mask0 = 0; -static u32 iop331_mask1 = 0; - -static inline void intctl_write0(u32 val) -{ - // INTCTL0 - asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); -} - -static inline void intctl_write1(u32 val) -{ - // INTCTL1 - asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val)); -} - -static inline void intstr_write0(u32 val) -{ - // INTSTR0 - asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val)); -} - -static inline void intstr_write1(u32 val) -{ - // INTSTR1 - asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val)); -} - -static void -iop331_irq_mask1 (unsigned int irq) -{ - iop331_mask0 &= ~(1 << (irq - IOP331_IRQ_OFS)); - intctl_write0(iop331_mask0); -} - -static void -iop331_irq_mask2 (unsigned int irq) -{ - iop331_mask1 &= ~(1 << (irq - IOP331_IRQ_OFS - 32)); - intctl_write1(iop331_mask1); -} - -static void -iop331_irq_unmask1(unsigned int irq) -{ - iop331_mask0 |= (1 << (irq - IOP331_IRQ_OFS)); - intctl_write0(iop331_mask0); -} - -static void -iop331_irq_unmask2(unsigned int irq) -{ - iop331_mask1 |= (1 << (irq - IOP331_IRQ_OFS - 32)); - intctl_write1(iop331_mask1); -} - -struct irq_chip iop331_irqchip1 = { - .name = "IOP-1", - .ack = iop331_irq_mask1, - .mask = iop331_irq_mask1, - .unmask = iop331_irq_unmask1, -}; - -struct irq_chip iop331_irqchip2 = { - .name = "IOP-2", - .ack = iop331_irq_mask2, - .mask = iop331_irq_mask2, - .unmask = iop331_irq_unmask2, -}; - -void __init iop331_init_irq(void) -{ - unsigned int i, tmp; - - /* Enable access to coprocessor 6 for dealing with IRQs. - * From RMK: - * Basically, the Intel documentation here is poor. It appears that - * you need to set the bit to be able to access the coprocessor from - * SVC mode. Whether that allows access from user space or not is - * unclear. - */ - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, %1\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - /* The action is delayed, so we have to do this: */ - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4" - : "=r" (tmp) : "i" (1 << 6) ); - - intctl_write0(0); // disable all interrupts - intctl_write1(0); - intstr_write0(0); // treat all as IRQ - intstr_write1(0); - if(machine_is_iq80331()) // all interrupts are inputs to chip - *IOP331_PCIIRSR = 0x0f; - - for(i = IOP331_IRQ_OFS; i < NR_IOP331_IRQS; i++) - { - set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2); - set_irq_handler(i, do_level_IRQ); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } -} - diff --git a/arch/arm/mach-iop3xx/iop331-pci.c b/arch/arm/mach-iop3xx/iop331-pci.c deleted file mode 100644 index 44dd213b48a3..000000000000 --- a/arch/arm/mach-iop3xx/iop331-pci.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * arch/arm/mach-iop3xx/iop331-pci.c - * - * PCI support for the Intel IOP331 chipset - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright (C) 2003, 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#undef DEBUG -#undef DEBUG1 - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) do { } while (0) -#endif - -#ifdef DEBUG1 -#define DBG1(x...) printk(x) -#else -#define DBG1(x...) do { } while (0) -#endif - -/* - * This routine builds either a type0 or type1 configuration command. If the - * bus is on the 80331 then a type0 made, else a type1 is created. - */ -static u32 iop331_cfg_address(struct pci_bus *bus, int devfn, int where) -{ - struct pci_sys_data *sys = bus->sysdata; - u32 addr; - - if (sys->busnr == bus->number) - addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); - else - addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; - - addr |= PCI_FUNC(devfn) << 8 | (where & ~3); - - return addr; -} - -/* - * This routine checks the status of the last configuration cycle. If an error - * was detected it returns a 1, else it returns a 0. The errors being checked - * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during - * the discovery stage. - */ -static int iop331_pci_status(void) -{ - unsigned int status; - int ret = 0; - - /* - * Check the status registers. - */ - status = *IOP331_ATUSR; - if (status & 0xf900) - { - DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); - *IOP331_ATUSR = status & 0xf900; - ret = 1; - } - status = *IOP331_ATUISR; - if (status & 0x679f) - { - DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); - *IOP331_ATUISR = status & 0x679f; - ret = 1; - } - return ret; -} - -/* - * Simply write the address register and read the configuration - * data. Note that the 4 nop's ensure that we are able to handle - * a delayed abort (in theory.) - */ -static inline u32 iop331_read(unsigned long addr) -{ - u32 val; - - __asm__ __volatile__( - "str %1, [%2]\n\t" - "ldr %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : "=r" (val) - : "r" (addr), "r" (IOP331_OCCAR), "r" (IOP331_OCCDR)); - - return val; -} - -/* - * The read routines must check the error status of the last configuration - * cycle. If there was an error, the routine returns all hex f's. - */ -static int -iop331_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - unsigned long addr = iop331_cfg_address(bus, devfn, where); - u32 val = iop331_read(addr) >> ((where & 3) * 8); - - if( iop331_pci_status() ) - val = 0xffffffff; - - *value = val; - - return PCIBIOS_SUCCESSFUL; -} - -static int -iop331_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - unsigned long addr = iop331_cfg_address(bus, devfn, where); - u32 val; - - if (size != 4) { - val = iop331_read(addr); - if (!iop331_pci_status() == 0) - return PCIBIOS_SUCCESSFUL; - - where = (where & 3) * 8; - - if (size == 1) - val &= ~(0xff << where); - else - val &= ~(0xffff << where); - - *IOP331_OCCDR = val | value << where; - } else { - asm volatile( - "str %1, [%2]\n\t" - "str %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : - : "r" (value), "r" (addr), - "r" (IOP331_OCCAR), "r" (IOP331_OCCDR)); - } - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops iop331_ops = { - .read = iop331_read_config, - .write = iop331_write_config, -}; - -/* - * When a PCI device does not exist during config cycles, the XScale gets a - * bus error instead of returning 0xffffffff. This handler simply returns. - */ -int -iop331_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", - addr, fsr, regs->ARM_pc, regs->ARM_lr); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -/* - * Scan an IOP331 PCI bus. sys->bus defines which bus we scan. - */ -struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_bus(sys->busnr, &iop331_ops, sys); -} - -void iop331_init(void) -{ - DBG1("PCI: Intel 80331 PCI init code.\n"); - DBG1("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD); - DBG1("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n", - *IOP331_OMWTVR0, - *IOP331_OIOWTVR); - DBG1("\tATU: IOP331_OMWTVR1=0x%04x\n", *IOP331_OMWTVR1); - DBG1("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR); - DBG1("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0); - DBG1("\tATU: IOP31_IABAR1=0x%08x IOP331_IALR1=0x%08x\n", *IOP331_IABAR1, *IOP331_IALR1); - DBG1("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR); - DBG1("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2); - DBG1("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3); - - hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort"); -} - diff --git a/arch/arm/mach-iop3xx/iop331-setup.c b/arch/arm/mach-iop3xx/iop331-setup.c deleted file mode 100644 index b2f24931d143..000000000000 --- a/arch/arm/mach-iop3xx/iop331-setup.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * linux/arch/arm/mach-iop3xx/iop331-setup.c - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright (C) 2004 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IOP331_UART_XTAL 33334000 - -/* - * Standard IO mapping for all IOP331 based systems - */ -static struct map_desc iop331_std_desc[] __initdata = { - { /* mem mapped registers */ - .virtual = IOP331_VIRT_MEM_BASE, - .pfn = __phys_to_pfn(IOP331_PHYS_MEM_BASE), - .length = 0x00002000, - .type = MT_DEVICE - }, { /* PCI IO space */ - .virtual = IOP331_PCI_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP331_PCI_LOWER_IO_PA), - .length = IOP331_PCI_IO_WINDOW_SIZE, - .type = MT_DEVICE - } -}; - -static struct resource iop33x_uart0_resources[] = { - [0] = { - .start = IOP331_UART0_PHYS, - .end = IOP331_UART0_PHYS + 0x3f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP331_UART0, - .end = IRQ_IOP331_UART0, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop33x_uart1_resources[] = { - [0] = { - .start = IOP331_UART1_PHYS, - .end = IOP331_UART1_PHYS + 0x3f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP331_UART1, - .end = IRQ_IOP331_UART1, - .flags = IORESOURCE_IRQ - } -}; - -static struct plat_serial8250_port iop33x_uart0_data[] = { - { - .membase = (char*)(IOP331_UART0_VIRT), - .mapbase = (IOP331_UART0_PHYS), - .irq = IRQ_IOP331_UART0, - .uartclk = IOP331_UART_XTAL, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_SKIP_TEST, - }, - { }, -}; - -static struct plat_serial8250_port iop33x_uart1_data[] = { - { - .membase = (char*)(IOP331_UART1_VIRT), - .mapbase = (IOP331_UART1_PHYS), - .irq = IRQ_IOP331_UART1, - .uartclk = IOP331_UART_XTAL, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_SKIP_TEST, - }, - { }, -}; - -static struct platform_device iop33x_uart0 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = iop33x_uart0_data, - .num_resources = 2, - .resource = iop33x_uart0_resources, -}; - -static struct platform_device iop33x_uart1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev.platform_data = iop33x_uart1_data, - .num_resources = 2, - .resource = iop33x_uart1_resources, -}; - -static struct resource iop33x_i2c_0_resources[] = { - [0] = { - .start = 0xfffff680, - .end = 0xfffff698, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP331_I2C_0, - .end = IRQ_IOP331_I2C_0, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop33x_i2c_1_resources[] = { - [0] = { - .start = 0xfffff6a0, - .end = 0xfffff6b8, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP331_I2C_1, - .end = IRQ_IOP331_I2C_1, - .flags = IORESOURCE_IRQ - } -}; - -static struct platform_device iop33x_i2c_0_controller = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = iop33x_i2c_0_resources -}; - -static struct platform_device iop33x_i2c_1_controller = { - .name = "IOP3xx-I2C", - .id = 1, - .num_resources = 2, - .resource = iop33x_i2c_1_resources -}; - -static struct platform_device *iop33x_devices[] __initdata = { - &iop33x_uart0, - &iop33x_uart1, - &iop33x_i2c_0_controller, - &iop33x_i2c_1_controller -}; - -void __init iop33x_init(void) -{ - if(iop_is_331()) - { - platform_add_devices(iop33x_devices, - ARRAY_SIZE(iop33x_devices)); - } -} - -void __init iop331_map_io(void) -{ - iotable_init(iop331_std_desc, ARRAY_SIZE(iop331_std_desc)); -} - -#ifdef CONFIG_ARCH_IOP33X -extern void iop331_init_irq(void); -extern struct sys_timer iop331_timer; -#endif - -#ifdef CONFIG_ARCH_IQ80331 -extern void iq80331_map_io(void); -#endif - -#ifdef CONFIG_MACH_IQ80332 -extern void iq80332_map_io(void); -#endif - -#if defined(CONFIG_ARCH_IQ80331) -MACHINE_START(IQ80331, "Intel IQ80331") - /* Maintainer: Intel Corp. */ - .phys_io = 0xfefff000, - .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical - .map_io = iq80331_map_io, - .init_irq = iop331_init_irq, - .timer = &iop331_timer, - .boot_params = 0x0100, - .init_machine = iop33x_init, -MACHINE_END - -#elif defined(CONFIG_MACH_IQ80332) -MACHINE_START(IQ80332, "Intel IQ80332") - /* Maintainer: Intel Corp. */ - .phys_io = 0xfefff000, - .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical - .map_io = iq80332_map_io, - .init_irq = iop331_init_irq, - .timer = &iop331_timer, - .boot_params = 0x0100, - .init_machine = iop33x_init, -MACHINE_END - -#else -#error No machine descriptor defined for this IOP3XX implementation -#endif - - diff --git a/arch/arm/mach-iop3xx/iop331-time.c b/arch/arm/mach-iop3xx/iop331-time.c deleted file mode 100644 index 0c09e74c5740..000000000000 --- a/arch/arm/mach-iop3xx/iop331-time.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * arch/arm/mach-iop3xx/iop331-time.c - * - * Timer code for IOP331 based systems - * - * Author: Dave Jiang - * - * Copyright 2003 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -static inline unsigned long get_elapsed(void) -{ - return LATCH - *IOP331_TU_TCR0; -} - -static unsigned long iop331_gettimeoffset(void) -{ - unsigned long elapsed, usec; - u32 tisr1, tisr2; - - /* - * If an interrupt was pending before we read the timer, - * we've already wrapped. Factor this into the time. - * If an interrupt was pending after we read the timer, - * it may have wrapped between checking the interrupt - * status and reading the timer. Re-read the timer to - * be sure its value is after the wrap. - */ - - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr1)); - elapsed = get_elapsed(); - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr2)); - - if(tisr1 & 1) - elapsed += LATCH; - else if (tisr2 & 1) - elapsed = LATCH + get_elapsed(); - - /* - * Now convert them to usec. - */ - usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000)); - - return usec; -} - -static irqreturn_t -iop331_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - u32 tisr; - - write_seqlock(&xtime_lock); - - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr)); - tisr |= 1; - asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr)); - - timer_tick(regs); - - write_sequnlock(&xtime_lock); - return IRQ_HANDLED; -} - -static struct irqaction iop331_timer_irq = { - .name = "IOP331 Timer Tick", - .handler = iop331_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER, -}; - -static void __init iop331_timer_init(void) -{ - u32 timer_ctl; - - setup_irq(IRQ_IOP331_TIMER0, &iop331_timer_irq); - - timer_ctl = IOP331_TMR_EN | IOP331_TMR_PRIVILEGED | IOP331_TMR_RELOAD | - IOP331_TMR_RATIO_1_1; - - asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (LATCH)); - - asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); - -} - -struct sys_timer iop331_timer = { - .init = iop331_timer_init, - .offset = iop331_gettimeoffset, -}; diff --git a/arch/arm/mach-iop3xx/iq31244-mm.c b/arch/arm/mach-iop3xx/iq31244-mm.c deleted file mode 100644 index e874b54eefe3..000000000000 --- a/arch/arm/mach-iop3xx/iq31244-mm.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * linux/arch/arm/mach-iop3xx/mm.c - * - * Low level memory initialization for iq80321 platform - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include - -#include -#include -#include - -#include - - -/* - * IQ80321 specific IO mappings - * - * We use RedBoot's setup for the onboard devices. - */ -static struct map_desc iq31244_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ31244_UART, - .pfn = __phys_to_pfn(IQ31244_UART), - .length = 0x00100000, - .type = MT_DEVICE - } -}; - -void __init iq31244_map_io(void) -{ - iop321_map_io(); - - iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc)); -} diff --git a/arch/arm/mach-iop3xx/iq31244-pci.c b/arch/arm/mach-iop3xx/iq31244-pci.c deleted file mode 100644 index f3c6413fa5bd..000000000000 --- a/arch/arm/mach-iop3xx/iq31244-pci.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * arch/arm/mach-iop3xx/iq80321-pci.c - * - * PCI support for the Intel IQ80321 reference board - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * The following macro is used to lookup irqs in a standard table - * format for those systems that do not already have PCI - * interrupts properly routed. We assume 1 <= pin <= 4 - */ -#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ -({ int _ctl_ = -1; \ - unsigned int _idsel = idsel - minid; \ - if (_idsel <= maxid) \ - _ctl_ = pci_irq_table[_idsel][pin-1]; \ - _ctl_; }) - -#define INTA IRQ_IQ31244_INTA -#define INTB IRQ_IQ31244_INTB -#define INTC IRQ_IQ31244_INTC -#define INTD IRQ_IQ31244_INTD - -#define INTE IRQ_IQ31244_I82546 - -static inline int __init -iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ -#ifdef CONFIG_ARCH_EP80219 - {INTB, INTB, INTB, INTB}, /* CFlash */ - {INTE, INTE, INTE, INTE}, /* 82551 Pro 100 */ - {INTD, INTD, INTD, INTD}, /* PCI-X Slot */ - {INTC, INTC, INTC, INTC}, /* SATA */ -#else - {INTB, INTB, INTB, INTB}, /* CFlash */ - {INTC, INTC, INTC, INTC}, /* SATA */ - {INTD, INTD, INTD, INTD}, /* PCI-X Slot */ - {INTE, INTE, INTE, INTE}, /* 82546 GigE */ -#endif // CONFIG_ARCH_EP80219 - }; - - BUG_ON(pin < 1 || pin > 4); - - return PCI_IRQ_TABLE_LOOKUP(0, 7); -} - -static int iq31244_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - - if(nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res[0].start = IOP321_PCI_LOWER_IO_VA; - res[0].end = IOP321_PCI_UPPER_IO_VA; - res[0].name = "IQ31244 PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - - res[1].start = IOP321_PCI_LOWER_MEM_PA; - res[1].end = IOP321_PCI_UPPER_MEM_PA; - res[1].name = "IQ31244 PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); - - sys->mem_offset = IOP321_PCI_MEM_OFFSET; - sys->io_offset = IOP321_PCI_IO_OFFSET; - - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; - - return 1; -} - -static void iq31244_preinit(void) -{ - iop321_init(); -} - -static struct hw_pci iq31244_pci __initdata = { - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = iq31244_setup, - .scan = iop321_scan_bus, - .preinit = iq31244_preinit, - .map_irq = iq31244_map_irq -}; - -static int __init iq31244_pci_init(void) -{ - if (machine_is_iq31244()) - pci_common_init(&iq31244_pci); - return 0; -} - -subsys_initcall(iq31244_pci_init); - - - - diff --git a/arch/arm/mach-iop3xx/iq80321-mm.c b/arch/arm/mach-iop3xx/iq80321-mm.c deleted file mode 100644 index d9cac5e1fc3d..000000000000 --- a/arch/arm/mach-iop3xx/iq80321-mm.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * linux/arch/arm/mach-iop3xx/mm.c - * - * Low level memory initialization for iq80321 platform - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include - -#include -#include -#include - -#include - - -/* - * IQ80321 specific IO mappings - * - * We use RedBoot's setup for the onboard devices. - */ -static struct map_desc iq80321_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ80321_UART, - .pfn = __phys_to_pfn(IQ80321_UART), - .length = 0x00100000, - .type = MT_DEVICE - } -}; - -void __init iq80321_map_io(void) -{ - iop321_map_io(); - - iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc)); -} diff --git a/arch/arm/mach-iop3xx/iq80321-pci.c b/arch/arm/mach-iop3xx/iq80321-pci.c deleted file mode 100644 index d9758d3f6e7f..000000000000 --- a/arch/arm/mach-iop3xx/iq80321-pci.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * arch/arm/mach-iop3xx/iq80321-pci.c - * - * PCI support for the Intel IQ80321 reference board - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * The following macro is used to lookup irqs in a standard table - * format for those systems that do not already have PCI - * interrupts properly routed. We assume 1 <= pin <= 4 - */ -#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ -({ int _ctl_ = -1; \ - unsigned int _idsel = idsel - minid; \ - if (_idsel <= maxid) \ - _ctl_ = pci_irq_table[_idsel][pin-1]; \ - _ctl_; }) - -#define INTA IRQ_IQ80321_INTA -#define INTB IRQ_IQ80321_INTB -#define INTC IRQ_IQ80321_INTC -#define INTD IRQ_IQ80321_INTD - -#define INTE IRQ_IQ80321_I82544 - -static inline int __init -iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {INTE, INTE, INTE, INTE}, /* Gig-E */ - {-1, -1, -1, -1}, /* Unused */ - {INTC, INTD, INTA, INTB}, /* PCI-X Slot */ - {-1, -1, -1, -1}, - }; - - BUG_ON(pin < 1 || pin > 4); - -// return PCI_IRQ_TABLE_LOOKUP(4, 7); - return pci_irq_table[idsel%4][pin-1]; -} - -static int iq80321_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - - if(nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res[0].start = IOP321_PCI_LOWER_IO_VA; - res[0].end = IOP321_PCI_UPPER_IO_VA; - res[0].name = "IQ80321 PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - - res[1].start = IOP321_PCI_LOWER_MEM_PA; - res[1].end = IOP321_PCI_UPPER_MEM_PA; - res[1].name = "IQ80321 PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); - - sys->mem_offset = IOP321_PCI_MEM_OFFSET; - sys->io_offset = IOP321_PCI_IO_OFFSET; - - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; - - return 1; -} - -static void iq80321_preinit(void) -{ - iop321_init(); -} - -static struct hw_pci iq80321_pci __initdata = { - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = iq80321_setup, - .scan = iop321_scan_bus, - .preinit = iq80321_preinit, - .map_irq = iq80321_map_irq -}; - -static int __init iq80321_pci_init(void) -{ - if (machine_is_iq80321()) - pci_common_init(&iq80321_pci); - return 0; -} - -subsys_initcall(iq80321_pci_init); - - - - diff --git a/arch/arm/mach-iop3xx/iq80331-mm.c b/arch/arm/mach-iop3xx/iq80331-mm.c deleted file mode 100644 index 129eb49b0670..000000000000 --- a/arch/arm/mach-iop3xx/iq80331-mm.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * linux/arch/arm/mach-iop3xx/mm.c - * - * Low level memory initialization for iq80331 platform - * - * Author: Dave Jiang - * Copyright (C) 2003 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include - -#include -#include -#include - -#include - - -/* - * IQ80331 specific IO mappings - * - * We use RedBoot's setup for the onboard devices. - */ - -void __init iq80331_map_io(void) -{ - iop331_map_io(); -} diff --git a/arch/arm/mach-iop3xx/iq80331-pci.c b/arch/arm/mach-iop3xx/iq80331-pci.c deleted file mode 100644 index 40d861002492..000000000000 --- a/arch/arm/mach-iop3xx/iq80331-pci.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * arch/arm/mach-iop3xx/iq80331-pci.c - * - * PCI support for the Intel IQ80331 reference board - * - * Author: Dave Jiang - * Copyright (C) 2003, 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * The following macro is used to lookup irqs in a standard table - * format for those systems that do not already have PCI - * interrupts properly routed. We assume 1 <= pin <= 4 - */ -#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ -({ int _ctl_ = -1; \ - unsigned int _idsel = idsel - minid; \ - if (_idsel <= maxid) \ - _ctl_ = pci_irq_table[_idsel][pin-1]; \ - _ctl_; }) - -#define INTA IRQ_IQ80331_INTA -#define INTB IRQ_IQ80331_INTB -#define INTC IRQ_IQ80331_INTC -#define INTD IRQ_IQ80331_INTD - -//#define INTE IRQ_IQ80331_I82544 - -static inline int __init -iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {INTB, INTC, INTD, INTA}, /* PCI-X Slot */ - {INTC, INTC, INTC, INTC}, /* GigE */ - }; - - BUG_ON(pin < 1 || pin > 4); - - return PCI_IRQ_TABLE_LOOKUP(1, 7); -} - -static int iq80331_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - - if(nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res[0].start = IOP331_PCI_LOWER_IO_VA; - res[0].end = IOP331_PCI_UPPER_IO_VA; - res[0].name = "IQ80331 PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - - res[1].start = IOP331_PCI_LOWER_MEM_PA; - res[1].end = IOP331_PCI_UPPER_MEM_PA; - res[1].name = "IQ80331 PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); - - sys->mem_offset = IOP331_PCI_MEM_OFFSET; - sys->io_offset = IOP331_PCI_IO_OFFSET; - - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; - - return 1; -} - -static void iq80331_preinit(void) -{ - iop331_init(); -} - -static struct hw_pci iq80331_pci __initdata = { - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = iq80331_setup, - .scan = iop331_scan_bus, - .preinit = iq80331_preinit, - .map_irq = iq80331_map_irq -}; - -static int __init iq80331_pci_init(void) -{ - if (machine_is_iq80331()) - pci_common_init(&iq80331_pci); - return 0; -} - -subsys_initcall(iq80331_pci_init); - - - - diff --git a/arch/arm/mach-iop3xx/iq80332-mm.c b/arch/arm/mach-iop3xx/iq80332-mm.c deleted file mode 100644 index 2feaf7591f53..000000000000 --- a/arch/arm/mach-iop3xx/iq80332-mm.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * linux/arch/arm/mach-iop3xx/mm.c - * - * Low level memory initialization for iq80332 platform - * - * Author: Dave Jiang - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include - -#include -#include -#include - -#include - - -/* - * IQ80332 specific IO mappings - * - * We use RedBoot's setup for the onboard devices. - */ - -void __init iq80332_map_io(void) -{ - iop331_map_io(); -} diff --git a/arch/arm/mach-iop3xx/iq80332-pci.c b/arch/arm/mach-iop3xx/iq80332-pci.c deleted file mode 100644 index afc0676318e4..000000000000 --- a/arch/arm/mach-iop3xx/iq80332-pci.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * arch/arm/mach-iop3xx/iq80332-pci.c - * - * PCI support for the Intel IQ80332 reference board - * - * Author: Dave Jiang - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * The following macro is used to lookup irqs in a standard table - * format for those systems that do not already have PCI - * interrupts properly routed. We assume 1 <= pin <= 4 - */ -#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ -({ int _ctl_ = -1; \ - unsigned int _idsel = idsel - minid; \ - if (_idsel <= maxid) \ - _ctl_ = pci_irq_table[_idsel][pin-1]; \ - _ctl_; }) - -#define INTA IRQ_IQ80332_INTA -#define INTB IRQ_IQ80332_INTB -#define INTC IRQ_IQ80332_INTC -#define INTD IRQ_IQ80332_INTD - -//#define INTE IRQ_IQ80332_I82544 - -static inline int __init -iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) -{ - static int pci_irq_table[][8] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - {INTA, INTB, INTC, INTD}, /* PCI-X Slot */ - {-1, -1, -1, -1}, - {INTC, INTC, INTC, INTC}, /* GigE */ - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - }; - - BUG_ON(pin < 1 || pin > 4); - - return PCI_IRQ_TABLE_LOOKUP(1, 7); -} - -static int iq80332_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - - if(nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res[0].start = IOP331_PCI_LOWER_IO_VA; - res[0].end = IOP331_PCI_UPPER_IO_VA; - res[0].name = "IQ80332 PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - - res[1].start = IOP331_PCI_LOWER_MEM_PA; - res[1].end = IOP331_PCI_UPPER_MEM_PA; - res[1].name = "IQ80332 PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); - - sys->mem_offset = IOP331_PCI_MEM_OFFSET; - sys->io_offset = IOP331_PCI_IO_OFFSET; - - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; - - return 1; -} - -static void iq80332_preinit(void) -{ - iop331_init(); -} - -static struct hw_pci iq80332_pci __initdata = { - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = iq80332_setup, - .scan = iop331_scan_bus, - .preinit = iq80332_preinit, - .map_irq = iq80332_map_irq -}; - -static int __init iq80332_pci_init(void) -{ - if (machine_is_iq80332()) - pci_common_init(&iq80332_pci); - return 0; -} - -subsys_initcall(iq80332_pci_init); - - - - diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index b4f220dd5eb8..b59c74100a84 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -232,7 +232,7 @@ config CPU_SA1100 # XScale config CPU_XSCALE bool - depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 + depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 default y select CPU_32v5 select CPU_ABRT_EV5T diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 884320e70403..a843d6b10a0c 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -196,7 +196,7 @@ config I2C_IBM_IIC config I2C_IOP3XX tristate "Intel IOP3xx and IXP4xx on-chip I2C interface" - depends on (ARCH_IOP3XX || ARCH_IXP4XX) && I2C + depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX) && I2C help Say Y here if you want to use the IIC bus controller on the Intel IOP3xx I/O Processors or IXP4xx Network Processors. diff --git a/include/asm-arm/arch-iop32x/debug-macro.S b/include/asm-arm/arch-iop32x/debug-macro.S new file mode 100644 index 000000000000..75ab2e0d8c67 --- /dev/null +++ b/include/asm-arm/arch-iop32x/debug-macro.S @@ -0,0 +1,20 @@ +/* linux/include/asm-arm/arch-iop32x/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart,rx + mov \rx, #0xfe000000 @ physical + orr \rx, \rx, #0x00800000 @ location of the UART + .endm + +#define UART_SHIFT 0 +#include diff --git a/include/asm-arm/arch-iop32x/dma.h b/include/asm-arm/arch-iop32x/dma.h new file mode 100644 index 000000000000..5be36676e58f --- /dev/null +++ b/include/asm-arm/arch-iop32x/dma.h @@ -0,0 +1,9 @@ +/* + * linux/include/asm-arm/arch-iop32x/dma.h + * + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S new file mode 100644 index 000000000000..52d9435c6a34 --- /dev/null +++ b/include/asm-arm/arch-iop32x/entry-macro.S @@ -0,0 +1,28 @@ +/* + * include/asm-arm/arch-iop32x/entry-macro.S + * + * Low-level IRQ helper macros for IOP32x-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include + + .macro disable_fiq + .endm + + /* + * Note: only deal with normal interrupts, not FIQ + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov \irqnr, #0 + mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC + cmp \irqstat, #0 + beq 1001f + clz \irqnr, \irqstat + mov \base, #31 + subs \irqnr,\base,\irqnr + add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT +1001: + .endm diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h new file mode 100644 index 000000000000..8fb10134a107 --- /dev/null +++ b/include/asm-arm/arch-iop32x/hardware.h @@ -0,0 +1,54 @@ +/* + * linux/include/asm-arm/arch-iop32x/hardware.h + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +/* + * Note about PCI IO space mappings + * + * To make IO space accesses efficient, we store virtual addresses in + * the IO resources. + * + * The PCI IO space is located at virtual 0xfe000000 from physical + * 0x90000000. The PCI BARs must be programmed with physical addresses, + * but when we read them, we convert them to virtual addresses. See + * arch/arm/mach-iop3xx/iop3xx-pci.c + */ + +#define pcibios_assign_all_busses() 1 + + +/* + * The min PCI I/O and MEM space are dependent on what specific + * chipset/platform we are running on, so instead of hardcoding with + * #ifdefs, we just fill these in the platform level PCI init code. + */ +#ifndef __ASSEMBLY__ +extern unsigned long iop3xx_pcibios_min_io; +extern unsigned long iop3xx_pcibios_min_mem; + +extern unsigned int processor_id; +#endif + +/* + * We just set these to zero since they are really bogus anyways + */ +#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io) +#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem) + +/* + * Generic chipset bits + * + */ +#include "iop321.h" + +/* + * Board specific bits + */ +#include "iq80321.h" +#include "iq31244.h" + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h new file mode 100644 index 000000000000..36d05ada12c4 --- /dev/null +++ b/include/asm-arm/arch-iop32x/io.h @@ -0,0 +1,21 @@ +/* + * linux/include/asm-arm/arch-iop32x/io.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#include + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(p) ((void __iomem *)(p)) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h new file mode 100644 index 000000000000..7ba93faf8da4 --- /dev/null +++ b/include/asm-arm/arch-iop32x/iop321.h @@ -0,0 +1,341 @@ +/* + * linux/include/asm/arch-iop32x/iop321.h + * + * Intel IOP321 Chip definitions + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IOP321_HW_H_ +#define _IOP321_HW_H_ + + +/* + * This is needed for mixed drivers that need to work on all + * IOP3xx variants but behave slightly differently on each. + */ +#ifndef __ASSEMBLY__ +#define iop_is_321() 1 +#endif + +/* + * IOP321 I/O and Mem space regions for PCI autoconfiguration + */ +#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000 +#define IOP321_PCI_LOWER_IO_PA 0x90000000 +#define IOP321_PCI_LOWER_IO_VA 0xfe000000 +#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR) +#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1) +#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1) +#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1) +#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA) + +/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */ +#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ +#define IOP321_PCI_LOWER_MEM_PA 0x80000000 +#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0) +#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1) +#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1) +#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA) + + +/* + * IOP321 chipset registers + */ +#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ +#define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */ +#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg)) + +/* Reserved 0x00000000 through 0x000000FF */ + +/* Address Translation Unit 0x00000100 through 0x000001FF */ +#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100) +#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102) +#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104) +#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106) +#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108) +#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109) +#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C) +#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D) +#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E) +#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F) +#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110) +#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114) +#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118) +#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C) +#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120) +#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124) +#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C) +#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E) +#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130) +/* Reserved 0x00000134 through 0x0000013B */ +#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C) +#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D) +#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E) +#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F) +#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140) +#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144) +#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148) +#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C) +#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150) +#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154) +#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158) +#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C) +#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160) +#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164) +#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168) +#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C) +/* Reserved 0x00000170 through 0x00000177*/ +#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178) +/* Reserved 0x0000017C through 0x0000017F*/ +#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180) +#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184) +#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188) +#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C) +#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190) +#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194) +#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198) +#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C) +/* Reserved 0x000001A0 through 0x000001A3*/ +#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4) +/* Reserved 0x000001A8 through 0x000001AB*/ +#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC) +/* Reserved 0x000001B0 through 0x000001BB*/ +#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC) +#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0) +#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1) +#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2) +#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4) +/* Reserved 0x000001C6 through 0x000001DF */ +#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0) +#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1) +#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2) +#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4) +#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC) + +/* Messaging Unit 0x00000300 through 0x000003FF */ + +/* Reserved 0x00000300 through 0x0000030c */ +#define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310) +#define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314) +#define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318) +#define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C) +#define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320) +#define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324) +#define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328) +#define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C) +#define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330) +#define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334) +/* Reserved 0x00000338 through 0x0000034F */ +#define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350) +#define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354) +/* Reserved 0x00000358 through 0x0000035C */ +#define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360) +#define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364) +#define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368) +#define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C) +#define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370) +#define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374) +#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378) +#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C) +#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380) + +#define IOP321_IIxR_MASK 0x7f /* masks all */ +#define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */ +#define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */ +#define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */ +#define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */ +#define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */ +#define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */ +#define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */ + +/* Reserved 0x00000384 through 0x000003FF */ + +/* DMA Controller 0x00000400 through 0x000004FF */ +#define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400) +#define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404) +#define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C) +#define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410) +#define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414) +#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418) +#define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C) +#define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420) +#define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424) +/* Reserved 0x00000428 through 0x0000043C */ +#define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440) +#define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444) +#define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C) +#define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450) +#define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454) +#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458) +#define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C) +#define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460) +#define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464) +/* Reserved 0x00000468 through 0x000004FF */ + +/* Memory controller 0x00000500 through 0x0005FF */ + +/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ +#define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680) +#define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684) +#define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688) +#define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C) +#define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690) +#define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694) +#define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698) +#define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C) +#define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0) +#define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4) +#define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8) +#define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC) +#define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0) +#define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4) +#define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8) +/* Reserved 0x000006BC */ +#define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0) +/* Reserved 0x000006C4 through 0x000006DC */ +#define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0) +#define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4) + +#define IOP321_PBCR_EN 0x1 + +#define IOP321_PBISR_BOOR_ERR 0x1 + +/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ +#define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700) +#define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704) +#define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708) +/* reserved 0x00000070c */ +#define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710) +/* PERC0 DOESN'T EXIST - index from 1! */ +#define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710) + +#define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */ + +/* Internal arbitration unit 0x00000780 through 0x0007BF */ +#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780) +#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784) +#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788) + +/* General Purpose I/O Registers */ +#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4) +#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8) +#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC) + +/* Interrupt Controller */ +#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0) +#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4) +#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8) +#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) + +/* Timers */ + +#define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0) +#define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4) + +#ifdef CONFIG_ARCH_IQ80321 +#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */ +#elif defined(CONFIG_ARCH_IQ31244) +#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */ +#endif + +#ifdef CONFIG_ARCH_EP80219 +#undef IOP321_TICK_RATE +#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */ +#endif + +#define IOP321_TMR_TC 0x01 +#define IOP321_TMR_EN 0x02 +#define IOP321_TMR_RELOAD 0x04 +#define IOP321_TMR_PRIVILEGED 0x09 + +#define IOP321_TMR_RATIO_1_1 0x00 +#define IOP321_TMR_RATIO_4_1 0x10 +#define IOP321_TMR_RATIO_8_1 0x20 +#define IOP321_TMR_RATIO_16_1 0x30 + +#define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8) +#define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC) +#define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0) +#define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4) +#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8) +#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC) + +/* Application accelerator unit 0x00000800 - 0x000008FF */ +#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800) +#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804) +#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808) +#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C) +#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810) +#define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814) +#define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818) +#define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C) +#define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C) +#define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830) +#define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834) +#define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838) +#define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840) +#define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844) +#define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848) +#define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C) +#define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850) +#define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854) +#define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858) +#define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C) +#define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864) +#define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868) +#define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C) +#define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870) +#define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874) +#define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878) +#define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C) +#define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880) +#define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888) +#define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C) +#define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890) +#define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894) +#define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898) +#define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C) +#define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0) +#define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4) +#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820) +#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824) +#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828) +#define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c) +#define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860) +#define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884) + + +/* SSP serial port unit 0x00001600 - 0x0000167F */ +/* I2C bus interface unit 0x00001680 - 0x000016FF */ +#define IOP321_ICR0 (volatile u32 *)IOP321_REG_ADDR(0x00001680) +#define IOP321_ISR0 (volatile u32 *)IOP321_REG_ADDR(0x00001684) +#define IOP321_ISAR0 (volatile u32 *)IOP321_REG_ADDR(0x00001688) +#define IOP321_IDBR0 (volatile u32 *)IOP321_REG_ADDR(0x0000168C) +/* Reserved 0x00001690 */ +#define IOP321_IBMR0 (volatile u32 *)IOP321_REG_ADDR(0x00001694) +/* Reserved 0x00001698 */ +/* Reserved 0x0000169C */ +#define IOP321_ICR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A0) +#define IOP321_ISR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A4) +#define IOP321_ISAR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A8) +#define IOP321_IDBR1 (volatile u32 *)IOP321_REG_ADDR(0x000016AC) +#define IOP321_IBMR1 (volatile u32 *)IOP321_REG_ADDR(0x000016B4) +/* Reserved 0x000016B8 through 0x000016FC */ + +/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ + + +#ifndef __ASSEMBLY__ +extern void iop321_map_io(void); +extern void iop321_init_irq(void); +extern void iop321_time_init(void); +#endif + +#endif // _IOP321_HW_H_ diff --git a/include/asm-arm/arch-iop32x/iq31244.h b/include/asm-arm/arch-iop32x/iq31244.h new file mode 100644 index 000000000000..f490063d2156 --- /dev/null +++ b/include/asm-arm/arch-iop32x/iq31244.h @@ -0,0 +1,24 @@ +/* + * linux/include/asm/arch-iop32x/iq31244.h + * + * Intel IQ31244 evaluation board registers + */ + +#ifndef _IQ31244_H_ +#define _IQ31244_H_ + +#define IQ31244_FLASHBASE 0xf0000000 /* Flash */ +#define IQ31244_FLASHSIZE 0x00800000 +#define IQ31244_FLASHWIDTH 2 + +#define IQ31244_UART 0xfe800000 /* UART #1 */ +#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ +#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ +#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ +#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ + +#ifndef __ASSEMBLY__ +extern void iq31244_map_io(void); +#endif + +#endif // _IQ31244_H_ diff --git a/include/asm-arm/arch-iop32x/iq80321.h b/include/asm-arm/arch-iop32x/iq80321.h new file mode 100644 index 000000000000..7015a605ab64 --- /dev/null +++ b/include/asm-arm/arch-iop32x/iq80321.h @@ -0,0 +1,24 @@ +/* + * linux/include/asm/arch-iop32x/iq80321.h + * + * Intel IQ80321 evaluation board registers + */ + +#ifndef _IQ80321_H_ +#define _IQ80321_H_ + +#define IQ80321_FLASHBASE 0xf0000000 /* Flash */ +#define IQ80321_FLASHSIZE 0x00800000 +#define IQ80321_FLASHWIDTH 1 + +#define IQ80321_UART 0xfe800000 /* UART #1 */ +#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ +#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ +#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ +#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ + +#ifndef __ASSEMBLY__ +extern void iq80321_map_io(void); +#endif + +#endif // _IQ80321_H_ diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h new file mode 100644 index 000000000000..4b0c82711f96 --- /dev/null +++ b/include/asm-arm/arch-iop32x/irqs.h @@ -0,0 +1,98 @@ +/* + * linux/include/asm-arm/arch-iop32x/irqs.h + * + * Author: Rory Bolt + * Copyright: (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _IRQS_H_ +#define _IRQS_H_ + +/* + * IOP80321 chipset interrupts + */ +#define IOP321_IRQ_OFS 0 +#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x)) + +/* + * On IRQ or FIQ register + */ +#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0) +#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1) +#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2) +#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3) +#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4) +#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5) +#define IRQ_IOP321_AA_EOT IOP321_IRQ(6) +#define IRQ_IOP321_AA_EOC IOP321_IRQ(7) +#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8) +#define IRQ_IOP321_TIMER0 IOP321_IRQ(9) +#define IRQ_IOP321_TIMER1 IOP321_IRQ(10) +#define IRQ_IOP321_I2C_0 IOP321_IRQ(11) +#define IRQ_IOP321_I2C_1 IOP321_IRQ(12) +#define IRQ_IOP321_MESSAGING IOP321_IRQ(13) +#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14) +#define IRQ_IOP321_PERFMON IOP321_IRQ(15) +#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16) +#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17) +#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18) +#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19) +#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20) +#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21) +#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22) +#define IRQ_IOP321_AA_ERR IOP321_IRQ(23) +#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24) +#define IRQ_IOP321_SSP IOP321_IRQ(25) +#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26) +#define IRQ_IOP321_XINT0 IOP321_IRQ(27) +#define IRQ_IOP321_XINT1 IOP321_IRQ(28) +#define IRQ_IOP321_XINT2 IOP321_IRQ(29) +#define IRQ_IOP321_XINT3 IOP321_IRQ(30) +#define IRQ_IOP321_HPI IOP321_IRQ(31) + +#define NR_IRQS (IOP321_IRQ(31) + 1) + + +/* + * Interrupts available on the IQ80321 board + */ + +/* + * On board devices + */ +#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0 +#define IRQ_IQ80321_UART IRQ_IOP321_XINT1 + +/* + * PCI interrupts + */ +#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0 +#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1 +#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2 +#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3 + +/* + * Interrupts on the IQ31244 board + */ + +/* + * On board devices + */ +#define IRQ_IQ31244_UART IRQ_IOP321_XINT1 +#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0 +#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2 +#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3 + +/* + * PCI interrupts + */ +#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0 +#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1 +#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2 +#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3 + +#endif // _IRQ_H_ diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h new file mode 100644 index 000000000000..b4073f15b405 --- /dev/null +++ b/include/asm-arm/arch-iop32x/memory.h @@ -0,0 +1,27 @@ +/* + * linux/include/asm-arm/arch-iop32x/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0xa0000000) + +/* + * Virtual view <-> PCI DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ + +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2))) + + +#endif diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h new file mode 100644 index 000000000000..d4c8d691e1b0 --- /dev/null +++ b/include/asm-arm/arch-iop32x/system.h @@ -0,0 +1,29 @@ +/* + * linux/include/asm-arm/arch-iop32x/system.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + + +static inline void arch_reset(char mode) +{ + *IOP321_PCSR = 0x30; + + if ( 1 && mode == 's') { + /* Jump into ROM at address 0 */ + cpu_reset(0); + } else { + /* No on-chip reset capability */ + cpu_reset(0); + } +} + diff --git a/include/asm-arm/arch-iop32x/timex.h b/include/asm-arm/arch-iop32x/timex.h new file mode 100644 index 000000000000..08badde2e820 --- /dev/null +++ b/include/asm-arm/arch-iop32x/timex.h @@ -0,0 +1,8 @@ +/* + * linux/include/asm-arm/arch-iop32x/timex.h + * + * IOP3xx architecture timex specifications + */ +#include + +#define CLOCK_TICK_RATE IOP321_TICK_RATE diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h new file mode 100644 index 000000000000..4a85f20c796f --- /dev/null +++ b/include/asm-arm/arch-iop32x/uncompress.h @@ -0,0 +1,38 @@ +/* + * linux/include/asm-arm/arch-iop32x/uncompress.h + */ +#include +#include +#include +#include + +static volatile u8 *uart_base; + +#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) + +static inline void putc(char c) +{ + while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) + barrier(); + *uart_base = c; +} + +static inline void flush(void) +{ +} + +static __inline__ void __arch_decomp_setup(unsigned long arch_id) +{ + if (machine_is_iq80321()) + uart_base = (volatile u8 *)IQ80321_UART; + else if (machine_is_iq31244()) + uart_base = (volatile u8 *)IQ31244_UART; + else + uart_base = (volatile u8 *)0xfe800000; +} + +/* + * nothing to do + */ +#define arch_decomp_setup() __arch_decomp_setup(arch_id) +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-iop32x/vmalloc.h b/include/asm-arm/arch-iop32x/vmalloc.h new file mode 100644 index 000000000000..8492e1708a63 --- /dev/null +++ b/include/asm-arm/arch-iop32x/vmalloc.h @@ -0,0 +1,16 @@ +/* + * linux/include/asm-arm/arch-iop32x/vmalloc.h + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +//#define VMALLOC_END (0xe8000000) +/* increase usable physical RAM to ~992M per RMK */ +#define VMALLOC_END (0xfe000000) + diff --git a/include/asm-arm/arch-iop33x/debug-macro.S b/include/asm-arm/arch-iop33x/debug-macro.S new file mode 100644 index 000000000000..b647edff475d --- /dev/null +++ b/include/asm-arm/arch-iop33x/debug-macro.S @@ -0,0 +1,24 @@ +/* linux/include/asm-arm/arch-iop33x/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ mmu enabled? + moveq \rx, #0xff000000 @ physical + movne \rx, #0xfe000000 @ virtual + orr \rx, \rx, #0x00ff0000 + orr \rx, \rx, #0x0000f700 + .endm + +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-iop33x/dma.h b/include/asm-arm/arch-iop33x/dma.h new file mode 100644 index 000000000000..d577ca59f4b0 --- /dev/null +++ b/include/asm-arm/arch-iop33x/dma.h @@ -0,0 +1,9 @@ +/* + * linux/include/asm-arm/arch-iop33x/dma.h + * + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S new file mode 100644 index 000000000000..980ec9b1ac83 --- /dev/null +++ b/include/asm-arm/arch-iop33x/entry-macro.S @@ -0,0 +1,34 @@ +/* + * include/asm-arm/arch-iop33x/entry-macro.S + * + * Low-level IRQ helper macros for IOP33x-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include + + .macro disable_fiq + .endm + + /* + * Note: only deal with normal interrupts, not FIQ + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov \irqnr, #0 + mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0 + cmp \irqstat, #0 + bne 1002f + mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1 + cmp \irqstat, #0 + beq 1001f + clz \irqnr, \irqstat + rsbs \irqnr,\irqnr,#31 @ recommend by RMK + add \irqnr,\irqnr,#IRQ_IOP331_XINT8 + b 1001f +1002: clz \irqnr, \irqstat + rsbs \irqnr,\irqnr,#31 @ recommend by RMK + add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT +1001: + .endm diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h new file mode 100644 index 000000000000..4a457084c5c6 --- /dev/null +++ b/include/asm-arm/arch-iop33x/hardware.h @@ -0,0 +1,54 @@ +/* + * linux/include/asm-arm/arch-iop33x/hardware.h + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +/* + * Note about PCI IO space mappings + * + * To make IO space accesses efficient, we store virtual addresses in + * the IO resources. + * + * The PCI IO space is located at virtual 0xfe000000 from physical + * 0x90000000. The PCI BARs must be programmed with physical addresses, + * but when we read them, we convert them to virtual addresses. See + * arch/arm/mach-iop33x/pci.c + */ + +#define pcibios_assign_all_busses() 1 + + +/* + * The min PCI I/O and MEM space are dependent on what specific + * chipset/platform we are running on, so instead of hardcoding with + * #ifdefs, we just fill these in the platform level PCI init code. + */ +#ifndef __ASSEMBLY__ +extern unsigned long iop3xx_pcibios_min_io; +extern unsigned long iop3xx_pcibios_min_mem; + +extern unsigned int processor_id; +#endif + +/* + * We just set these to zero since they are really bogus anyways + */ +#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io) +#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem) + +/* + * Generic chipset bits + * + */ +#include "iop331.h" + +/* + * Board specific bits + */ +#include "iq80331.h" +#include "iq80332.h" + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h new file mode 100644 index 000000000000..a9949d5d4953 --- /dev/null +++ b/include/asm-arm/arch-iop33x/io.h @@ -0,0 +1,21 @@ +/* + * linux/include/asm-arm/arch-iop33x/io.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#include + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(p) ((void __iomem *)(p)) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h new file mode 100644 index 000000000000..780b707edb1e --- /dev/null +++ b/include/asm-arm/arch-iop33x/iop331.h @@ -0,0 +1,358 @@ +/* + * linux/include/asm/arch-iop33x/iop331.h + * + * Intel IOP331 Chip definitions + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright (C) 2003, 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IOP331_HW_H_ +#define _IOP331_HW_H_ + + +/* + * This is needed for mixed drivers that need to work on all + * IOP3xx variants but behave slightly differently on each. + */ +#ifndef __ASSEMBLY__ +#define iop_is_331() 1 +#endif + +/* + * IOP331 I/O and Mem space regions for PCI autoconfiguration + */ +#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000 +#define IOP331_PCI_LOWER_IO_PA 0x90000000 +#define IOP331_PCI_LOWER_IO_VA 0xfe000000 +#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR) +#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1) +#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1) +#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1) +#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA) + +/* this can be 128M if OMWTVR1 is set */ +#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ +/* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */ +#define IOP331_PCI_LOWER_MEM_PA 0x80000000 +#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0) +#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1) +#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1) +#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA) + +/* + * IOP331 chipset registers + */ +#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ +#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */ +#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg)) + +/* Reserved 0x00000000 through 0x000000FF */ + +/* Address Translation Unit 0x00000100 through 0x000001FF */ +#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100) +#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102) +#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104) +#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106) +#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108) +#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109) +#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C) +#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D) +#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E) +#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F) +#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110) +#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114) +#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118) +#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C) +#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120) +#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124) +#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C) +#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E) +#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130) +#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134) +/* Reserved 0x00000138 through 0x0000013B */ +#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C) +#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D) +#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E) +#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F) +#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140) +#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144) +#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148) +#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C) +#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150) +#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154) +#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158) +#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C) +#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160) +#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164) +#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168) +#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C) +/* Reserved 0x00000170 through 0x00000177*/ +#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178) +/* Reserved 0x0000017C through 0x0000017F*/ +#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180) +#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184) +#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188) +#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C) +#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190) +#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194) +#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198) +#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C) +/* Reserved 0x000001A0 through 0x000001A3*/ +#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4) +/* Reserved 0x000001A8 through 0x000001AB*/ +#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC) +/* Reserved 0x000001B0 through 0x000001BB*/ +#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8) +#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9) +#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA) +#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC) +#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0) +#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1) +#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2) +#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4) +/* Reserved 0x000001C6 through 0x000001CF */ +#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0) +#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1) +#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2) +#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4) +#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8) +#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC) +#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0) +#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1) +#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2) +#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4) +#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC) + +/* Messaging Unit 0x00000300 through 0x000003FF */ + +/* Reserved 0x00000300 through 0x0000030c */ +#define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310) +#define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314) +#define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318) +#define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C) +#define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320) +#define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324) +#define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328) +#define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C) +#define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330) +#define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334) +/* Reserved 0x00000338 through 0x0000034F */ +#define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350) +#define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354) +/* Reserved 0x00000358 through 0x0000035C */ +#define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360) +#define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364) +#define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368) +#define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C) +#define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370) +#define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374) +#define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378) +#define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C) +#define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380) +/* Reserved 0x00000384 through 0x000003FF */ + +/* DMA Controller 0x00000400 through 0x000004FF */ +#define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400) +#define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404) +#define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C) +#define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410) +#define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414) +#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418) +#define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C) +#define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420) +#define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424) +/* Reserved 0x00000428 through 0x0000043C */ +#define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440) +#define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444) +#define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C) +#define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450) +#define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454) +#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458) +#define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C) +#define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460) +#define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464) +/* Reserved 0x00000468 through 0x000004FF */ + +/* Memory controller 0x00000500 through 0x0005FF */ + +/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ +#define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680) +#define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684) +#define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688) +#define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C) +#define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690) +#define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694) +#define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698) +#define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C) +#define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0) +#define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4) +#define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8) +#define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC) +#define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0) +#define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4) +#define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8) +/* Reserved 0x000006BC */ +#define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0) +/* Reserved 0x000006C4 through 0x000006DC */ +#define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0) +#define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4) + +#define IOP331_PBCR_EN 0x1 + +#define IOP331_PBISR_BOOR_ERR 0x1 + + + +/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ +/* Internal arbitration unit 0x00000780 through 0x0007BF */ + +/* Interrupt Controller */ +#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790) +#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794) +#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798) +#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C) +#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0) +#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4) +#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8) +#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC) +#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0) +#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4) +#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8) +#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC) +#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0) +#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4) +#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8) +#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC) + + +/* Timers */ + +#define IOP331_TU_TMR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D0) +#define IOP331_TU_TMR1 (volatile u32 *)IOP331_REG_ADDR(0x000007D4) + +#define IOP331_TMR_TC 0x01 +#define IOP331_TMR_EN 0x02 +#define IOP331_TMR_RELOAD 0x04 +#define IOP331_TMR_PRIVILEGED 0x09 + +#define IOP331_TMR_RATIO_1_1 0x00 +#define IOP331_TMR_RATIO_4_1 0x10 +#define IOP331_TMR_RATIO_8_1 0x20 +#define IOP331_TMR_RATIO_16_1 0x30 + +#define IOP331_TU_TCR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D8) +#define IOP331_TU_TCR1 (volatile u32 *)IOP331_REG_ADDR(0x000007DC) +#define IOP331_TU_TRR0 (volatile u32 *)IOP331_REG_ADDR(0x000007E0) +#define IOP331_TU_TRR1 (volatile u32 *)IOP331_REG_ADDR(0x000007E4) +#define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8) +#define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC) + +#if defined(CONFIG_ARCH_IOP33X) +#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */ +#endif + +#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333) +#undef IOP331_TICK_RATE +#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */ +#endif + +/* Application accelerator unit 0x00000800 - 0x000008FF */ +#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800) +#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804) +#define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808) +#define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C) +#define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810) +#define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814) +#define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818) +#define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C) +#define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C) +#define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830) +#define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834) +#define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838) +#define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840) +#define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844) +#define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848) +#define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C) +#define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850) +#define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854) +#define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858) +#define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C) +#define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864) +#define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868) +#define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C) +#define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870) +#define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874) +#define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878) +#define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C) +#define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880) +#define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888) +#define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C) +#define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890) +#define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894) +#define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898) +#define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C) +#define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0) +#define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4) +#define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820) +#define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824) +#define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828) +#define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c) +#define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860) +#define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884) + + +#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0) +#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8) +/* SSP serial port unit 0x00001600 - 0x0000167F */ + +/* I2C bus interface unit 0x00001680 - 0x000016FF */ +/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ + +#define IOP331_ICR0 (volatile u32 *)IOP331_REG_ADDR(0x00001680) +#define IOP331_ISR0 (volatile u32 *)IOP331_REG_ADDR(0x00001684) +#define IOP331_ISAR0 (volatile u32 *)IOP331_REG_ADDR(0x00001688) +#define IOP331_IDBR0 (volatile u32 *)IOP331_REG_ADDR(0x0000168C) +/* Reserved 0x00001690 */ +#define IOP331_IBMR0 (volatile u32 *)IOP331_REG_ADDR(0x00001694) +/* Reserved 0x00001698 */ +/* Reserved 0x0000169C */ +#define IOP331_ICR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A0) +#define IOP331_ISR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A4) +#define IOP331_ISAR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A8) +#define IOP331_IDBR1 (volatile u32 *)IOP331_REG_ADDR(0x000016AC) +#define IOP331_IBMR1 (volatile u32 *)IOP331_REG_ADDR(0x000016B4) +/* Reserved 0x000016B8 through 0x000016FF */ + +/* 0x00001700 through 0x0000172C UART 0 */ + +/* Reserved 0x00001730 through 0x0000173F */ + +/* 0x00001740 through 0x0000176C UART 1 */ + +#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */ +#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */ +#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */ +#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */ + +/* Reserved 0x00001770 through 0x0000177F */ + +/* General Purpose I/O Registers */ +#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780) +#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784) +#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788) + +/* Reserved 0x0000178c through 0x000019ff */ + + +#ifndef __ASSEMBLY__ +extern void iop331_map_io(void); +extern void iop331_init_irq(void); +extern void iop331_time_init(void); +#endif + +#endif // _IOP331_HW_H_ diff --git a/include/asm-arm/arch-iop33x/iq80331.h b/include/asm-arm/arch-iop33x/iq80331.h new file mode 100644 index 000000000000..bda7ab6d55cf --- /dev/null +++ b/include/asm-arm/arch-iop33x/iq80331.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm/arch-iop33x/iq80331.h + * + * Intel IQ80331 evaluation board registers + */ + +#ifndef _IQ80331_H_ +#define _IQ80331_H_ + +#define IQ80331_FLASHBASE 0xc0000000 /* Flash */ +#define IQ80331_FLASHSIZE 0x00800000 +#define IQ80331_FLASHWIDTH 1 + +#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ +#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ +#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ +#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ + +#ifndef __ASSEMBLY__ +extern void iq80331_map_io(void); +#endif + +#endif // _IQ80331_H_ diff --git a/include/asm-arm/arch-iop33x/iq80332.h b/include/asm-arm/arch-iop33x/iq80332.h new file mode 100644 index 000000000000..f728e04378ab --- /dev/null +++ b/include/asm-arm/arch-iop33x/iq80332.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm/arch-iop33x/iq80332.h + * + * Intel IQ80332 evaluation board registers + */ + +#ifndef _IQ80332_H_ +#define _IQ80332_H_ + +#define IQ80332_FLASHBASE 0xc0000000 /* Flash */ +#define IQ80332_FLASHSIZE 0x00800000 +#define IQ80332_FLASHWIDTH 1 + +#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ +#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ +#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ +#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ + +#ifndef __ASSEMBLY__ +extern void iq80332_map_io(void); +#endif + +#endif // _IQ80332_H_ diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h new file mode 100644 index 000000000000..45856a12815a --- /dev/null +++ b/include/asm-arm/arch-iop33x/irqs.h @@ -0,0 +1,130 @@ +/* + * linux/include/asm-arm/arch-iop33x/irqs.h + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright: (C) 2003 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _IRQS_H_ +#define _IRQS_H_ + +/* + * IOP80331 chipset interrupts + */ +#define IOP331_IRQ_OFS 0 +#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x)) + +/* + * On IRQ or FIQ register + */ +#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0) +#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1) +#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2) +#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3) +#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4) +#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5) +#define IRQ_IOP331_AA_EOT IOP331_IRQ(6) +#define IRQ_IOP331_AA_EOC IOP331_IRQ(7) +#define IRQ_IOP331_TIMER0 IOP331_IRQ(8) +#define IRQ_IOP331_TIMER1 IOP331_IRQ(9) +#define IRQ_IOP331_I2C_0 IOP331_IRQ(10) +#define IRQ_IOP331_I2C_1 IOP331_IRQ(11) +#define IRQ_IOP331_MSG IOP331_IRQ(12) +#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13) +#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14) +#define IRQ_IOP331_PERFMON IOP331_IRQ(15) +#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16) +#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17) +#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18) +#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19) +#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20) +#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21) +#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22) +#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23) +#define IRQ_IOP331_XINT0 IOP331_IRQ(24) +#define IRQ_IOP331_XINT1 IOP331_IRQ(25) +#define IRQ_IOP331_XINT2 IOP331_IRQ(26) +#define IRQ_IOP331_XINT3 IOP331_IRQ(27) +#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28) +#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29) +#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30) +#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31) +#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0 +#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1 +#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2 +#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3 +#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4 +#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5 +#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6 +#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7 +#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8 +#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9 +#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10 +#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11 +#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12 +#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13 +#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14 +#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15 +#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16 +#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17 +#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18 +#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19 +#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20 +#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21 +#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22 +#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23 +#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24 +#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25 +#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26 +#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27 +#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28 +#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29 +#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30 +#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31 + +#define NR_IRQS (IOP331_IRQ(63) + 1) + + +/* + * Interrupts available on the IQ80331 board + */ + +/* + * On board devices + */ +#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0 +#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0 +#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1 + +/* + * PCI interrupts + */ +#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0 +#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1 +#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2 +#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3 + +/* + * Interrupts available on the IQ80332 board + */ + +/* + * On board devices + */ +#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0 +#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0 +#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1 + +/* + * PCI interrupts + */ +#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0 +#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1 +#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2 +#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3 + +#endif // _IRQ_H_ diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h new file mode 100644 index 000000000000..5e47164934ce --- /dev/null +++ b/include/asm-arm/arch-iop33x/memory.h @@ -0,0 +1,26 @@ +/* + * linux/include/asm-arm/arch-iop33x/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x00000000) + +/* + * Virtual view <-> PCI DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2))) + + +#endif diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h new file mode 100644 index 000000000000..43cc787ea629 --- /dev/null +++ b/include/asm-arm/arch-iop33x/system.h @@ -0,0 +1,29 @@ +/* + * linux/include/asm-arm/arch-iop33x/system.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + + +static inline void arch_reset(char mode) +{ + *IOP331_PCSR = 0x30; + + if ( 1 && mode == 's') { + /* Jump into ROM at address 0 */ + cpu_reset(0); + } else { + /* No on-chip reset capability */ + cpu_reset(0); + } +} + diff --git a/include/asm-arm/arch-iop33x/timex.h b/include/asm-arm/arch-iop33x/timex.h new file mode 100644 index 000000000000..cc8085fa2a1e --- /dev/null +++ b/include/asm-arm/arch-iop33x/timex.h @@ -0,0 +1,8 @@ +/* + * linux/include/asm-arm/arch-iop33x/timex.h + * + * IOP3xx architecture timex specifications + */ +#include + +#define CLOCK_TICK_RATE IOP331_TICK_RATE diff --git a/include/asm-arm/arch-iop33x/uncompress.h b/include/asm-arm/arch-iop33x/uncompress.h new file mode 100644 index 000000000000..62904ae3b038 --- /dev/null +++ b/include/asm-arm/arch-iop33x/uncompress.h @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/arch-iop33x/uncompress.h + */ +#include +#include +#include +#include + +static volatile u32 *uart_base; + +#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) + +static inline void putc(char c) +{ + while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) + barrier(); + *uart_base = c; +} + +static inline void flush(void) +{ +} + +static __inline__ void __arch_decomp_setup(unsigned long arch_id) +{ + if (machine_is_iq80331() || machine_is_iq80332()) + uart_base = (volatile u32 *)IOP331_UART0_PHYS; + else + uart_base = (volatile u32 *)0xfe800000; +} + +/* + * nothing to do + */ +#define arch_decomp_setup() __arch_decomp_setup(arch_id) +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-iop33x/vmalloc.h b/include/asm-arm/arch-iop33x/vmalloc.h new file mode 100644 index 000000000000..b5092027449e --- /dev/null +++ b/include/asm-arm/arch-iop33x/vmalloc.h @@ -0,0 +1,16 @@ +/* + * linux/include/asm-arm/arch-iop33x/vmalloc.h + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +//#define VMALLOC_END (0xe8000000) +/* increase usable physical RAM to ~992M per RMK */ +#define VMALLOC_END (0xfe000000) + diff --git a/include/asm-arm/arch-iop3xx/debug-macro.S b/include/asm-arm/arch-iop3xx/debug-macro.S deleted file mode 100644 index dcc6856d14ff..000000000000 --- a/include/asm-arm/arch-iop3xx/debug-macro.S +++ /dev/null @@ -1,35 +0,0 @@ -/* linux/include/asm-arm/arch-iop3xx/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart,rx - mov \rx, #0xfe000000 @ physical -#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244) - orr \rx, \rx, #0x00800000 @ location of the UART -#elif defined(CONFIG_ARCH_IOP33X) - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - moveq \rx, #0x000fe000 @ Physical Base - movne \rx, #0 - orr \rx, \rx, #0xfe000000 - orr \rx, \rx, #0x00f00000 @ Virtual Base - orr \rx, \rx, #0x00001700 @ location of the UART -#else -#error Unknown IOP3XX implementation -#endif - .endm - -#if !defined(CONFIG_ARCH_IQ80321) || !defined(CONFIG_ARCH_IQ31244) || !defined(CONFIG_ARCH_IQ80331) -#define FLOW_CONTROL -#endif -#define UART_SHIFT 0 -#include diff --git a/include/asm-arm/arch-iop3xx/dma.h b/include/asm-arm/arch-iop3xx/dma.h deleted file mode 100644 index 1e808db8af2a..000000000000 --- a/include/asm-arm/arch-iop3xx/dma.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/dma.h - * - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ diff --git a/include/asm-arm/arch-iop3xx/entry-macro.S b/include/asm-arm/arch-iop3xx/entry-macro.S deleted file mode 100644 index f3db54637ad3..000000000000 --- a/include/asm-arm/arch-iop3xx/entry-macro.S +++ /dev/null @@ -1,57 +0,0 @@ -/* - * include/asm-arm/arch-iop3xx/entry-macro.S - * - * Low-level IRQ helper macros for IOP3xx-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include - -#if defined(CONFIG_ARCH_IOP32X) - .macro disable_fiq - .endm - - /* - * Note: only deal with normal interrupts, not FIQ - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov \irqnr, #0 - mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC - cmp \irqstat, #0 - beq 1001f - clz \irqnr, \irqstat - mov \base, #31 - subs \irqnr,\base,\irqnr - add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT -1001: - .endm - -#elif defined(CONFIG_ARCH_IOP33X) - .macro disable_fiq - .endm - - /* - * Note: only deal with normal interrupts, not FIQ - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov \irqnr, #0 - mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0 - cmp \irqstat, #0 - bne 1002f - mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1 - cmp \irqstat, #0 - beq 1001f - clz \irqnr, \irqstat - rsbs \irqnr,\irqnr,#31 @ recommend by RMK - add \irqnr,\irqnr,#IRQ_IOP331_XINT8 - b 1001f -1002: clz \irqnr, \irqstat - rsbs \irqnr,\irqnr,#31 @ recommend by RMK - add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT -1001: - .endm - -#endif - diff --git a/include/asm-arm/arch-iop3xx/hardware.h b/include/asm-arm/arch-iop3xx/hardware.h deleted file mode 100644 index 3b138171d086..000000000000 --- a/include/asm-arm/arch-iop3xx/hardware.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/hardware.h - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include - -/* - * Note about PCI IO space mappings - * - * To make IO space accesses efficient, we store virtual addresses in - * the IO resources. - * - * The PCI IO space is located at virtual 0xfe000000 from physical - * 0x90000000. The PCI BARs must be programmed with physical addresses, - * but when we read them, we convert them to virtual addresses. See - * arch/arm/mach-iop3xx/iop3xx-pci.c - */ - -#define pcibios_assign_all_busses() 1 - - -/* - * The min PCI I/O and MEM space are dependent on what specific - * chipset/platform we are running on, so instead of hardcoding with - * #ifdefs, we just fill these in the platform level PCI init code. - */ -#ifndef __ASSEMBLY__ -extern unsigned long iop3xx_pcibios_min_io; -extern unsigned long iop3xx_pcibios_min_mem; - -extern unsigned int processor_id; -#endif - -/* - * We just set these to zero since they are really bogus anyways - */ -#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io) -#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem) - -/* - * Generic chipset bits - * - */ -#include "iop321.h" -#include "iop331.h" - -/* - * Board specific bits - */ -#include "iq80321.h" -#include "iq31244.h" -#include "iq80331.h" -#include "iq80332.h" - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop3xx/io.h deleted file mode 100644 index 36adbdf5055a..000000000000 --- a/include/asm-arm/arch-iop3xx/io.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/io.h - * - * Copyright (C) 2001 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(p) ((void __iomem *)(p)) -#define __mem_pci(a) (a) - -#endif diff --git a/include/asm-arm/arch-iop3xx/iop321-irqs.h b/include/asm-arm/arch-iop3xx/iop321-irqs.h deleted file mode 100644 index 2fcc1654cb9d..000000000000 --- a/include/asm-arm/arch-iop3xx/iop321-irqs.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/irqs.h - * - * Author: Rory Bolt - * Copyright: (C) 2002 Rory Bolt - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef _IOP321_IRQS_H_ -#define _IOP321_IRQS_H_ - -/* - * IOP80321 chipset interrupts - */ -#define IOP321_IRQ_OFS 0 -#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x)) - -/* - * On IRQ or FIQ register - */ -#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0) -#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1) -#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2) -#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3) -#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4) -#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5) -#define IRQ_IOP321_AA_EOT IOP321_IRQ(6) -#define IRQ_IOP321_AA_EOC IOP321_IRQ(7) -#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8) -#define IRQ_IOP321_TIMER0 IOP321_IRQ(9) -#define IRQ_IOP321_TIMER1 IOP321_IRQ(10) -#define IRQ_IOP321_I2C_0 IOP321_IRQ(11) -#define IRQ_IOP321_I2C_1 IOP321_IRQ(12) -#define IRQ_IOP321_MESSAGING IOP321_IRQ(13) -#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14) -#define IRQ_IOP321_PERFMON IOP321_IRQ(15) -#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16) -#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17) -#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18) -#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19) -#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20) -#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21) -#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22) -#define IRQ_IOP321_AA_ERR IOP321_IRQ(23) -#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24) -#define IRQ_IOP321_SSP IOP321_IRQ(25) -#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26) -#define IRQ_IOP321_XINT0 IOP321_IRQ(27) -#define IRQ_IOP321_XINT1 IOP321_IRQ(28) -#define IRQ_IOP321_XINT2 IOP321_IRQ(29) -#define IRQ_IOP321_XINT3 IOP321_IRQ(30) -#define IRQ_IOP321_HPI IOP321_IRQ(31) - -#define NR_IOP321_IRQS (IOP321_IRQ(31) + 1) - -#define NR_IRQS NR_IOP321_IRQS - - -/* - * Interrupts available on the IQ80321 board - */ - -/* - * On board devices - */ -#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0 -#define IRQ_IQ80321_UART IRQ_IOP321_XINT1 - -/* - * PCI interrupts - */ -#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0 -#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1 -#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2 -#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3 - -/* - * Interrupts on the IQ31244 board - */ - -/* - * On board devices - */ -#define IRQ_IQ31244_UART IRQ_IOP321_XINT1 -#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0 -#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2 -#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3 - -/* - * PCI interrupts - */ -#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0 -#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1 -#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2 -#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3 - -#endif // _IOP321_IRQ_H_ diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h deleted file mode 100644 index d198d72a50a4..000000000000 --- a/include/asm-arm/arch-iop3xx/iop321.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * linux/include/asm/arch-iop3xx/iop321.h - * - * Intel IOP321 Chip definitions - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IOP321_HW_H_ -#define _IOP321_HW_H_ - - -/* - * This is needed for mixed drivers that need to work on all - * IOP3xx variants but behave slightly differently on each. - */ -#ifndef __ASSEMBLY__ -#ifdef CONFIG_ARCH_IOP32X -#define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420)) -#else -#define iop_is_321() 0 -#endif -#endif - -/* - * IOP321 I/O and Mem space regions for PCI autoconfiguration - */ -#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000 -#define IOP321_PCI_LOWER_IO_PA 0x90000000 -#define IOP321_PCI_LOWER_IO_VA 0xfe000000 -#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR) -#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1) -#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1) -#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1) -#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA) - -/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */ -#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ -#define IOP321_PCI_LOWER_MEM_PA 0x80000000 -#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0) -#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1) -#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1) -#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA) - - -/* - * IOP321 chipset registers - */ -#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ -#define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */ -#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg)) - -/* Reserved 0x00000000 through 0x000000FF */ - -/* Address Translation Unit 0x00000100 through 0x000001FF */ -#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100) -#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102) -#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104) -#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106) -#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108) -#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109) -#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C) -#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D) -#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E) -#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F) -#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110) -#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114) -#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118) -#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C) -#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120) -#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124) -#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C) -#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E) -#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130) -/* Reserved 0x00000134 through 0x0000013B */ -#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C) -#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D) -#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E) -#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F) -#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140) -#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144) -#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148) -#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C) -#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150) -#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154) -#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158) -#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C) -#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160) -#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164) -#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168) -#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C) -/* Reserved 0x00000170 through 0x00000177*/ -#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178) -/* Reserved 0x0000017C through 0x0000017F*/ -#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180) -#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184) -#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188) -#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C) -#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190) -#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194) -#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198) -#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C) -/* Reserved 0x000001A0 through 0x000001A3*/ -#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4) -/* Reserved 0x000001A8 through 0x000001AB*/ -#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC) -/* Reserved 0x000001B0 through 0x000001BB*/ -#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC) -#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0) -#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1) -#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2) -#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4) -/* Reserved 0x000001C6 through 0x000001DF */ -#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0) -#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1) -#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2) -#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4) -#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC) - -/* Messaging Unit 0x00000300 through 0x000003FF */ - -/* Reserved 0x00000300 through 0x0000030c */ -#define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310) -#define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314) -#define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318) -#define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C) -#define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320) -#define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324) -#define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328) -#define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C) -#define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330) -#define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334) -/* Reserved 0x00000338 through 0x0000034F */ -#define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350) -#define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354) -/* Reserved 0x00000358 through 0x0000035C */ -#define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360) -#define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364) -#define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368) -#define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C) -#define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370) -#define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374) -#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378) -#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C) -#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380) - -#define IOP321_IIxR_MASK 0x7f /* masks all */ -#define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */ -#define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */ -#define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */ -#define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */ -#define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */ -#define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */ -#define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */ - -/* Reserved 0x00000384 through 0x000003FF */ - -/* DMA Controller 0x00000400 through 0x000004FF */ -#define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400) -#define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404) -#define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C) -#define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410) -#define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414) -#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418) -#define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C) -#define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420) -#define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424) -/* Reserved 0x00000428 through 0x0000043C */ -#define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440) -#define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444) -#define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C) -#define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450) -#define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454) -#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458) -#define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C) -#define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460) -#define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464) -/* Reserved 0x00000468 through 0x000004FF */ - -/* Memory controller 0x00000500 through 0x0005FF */ - -/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ -#define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680) -#define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684) -#define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688) -#define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C) -#define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690) -#define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694) -#define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698) -#define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C) -#define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0) -#define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4) -#define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8) -#define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC) -#define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0) -#define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4) -#define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8) -/* Reserved 0x000006BC */ -#define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0) -/* Reserved 0x000006C4 through 0x000006DC */ -#define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0) -#define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4) - -#define IOP321_PBCR_EN 0x1 - -#define IOP321_PBISR_BOOR_ERR 0x1 - -/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ -#define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700) -#define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704) -#define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708) -/* reserved 0x00000070c */ -#define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710) -/* PERC0 DOESN'T EXIST - index from 1! */ -#define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710) - -#define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */ - -/* Internal arbitration unit 0x00000780 through 0x0007BF */ -#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780) -#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784) -#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788) - -/* General Purpose I/O Registers */ -#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4) -#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8) -#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC) - -/* Interrupt Controller */ -#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0) -#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4) -#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8) -#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) - -/* Timers */ - -#define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0) -#define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4) - -#ifdef CONFIG_ARCH_IQ80321 -#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */ -#elif defined(CONFIG_ARCH_IQ31244) -#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */ -#endif - -#ifdef CONFIG_ARCH_EP80219 -#undef IOP321_TICK_RATE -#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */ -#endif - -#define IOP321_TMR_TC 0x01 -#define IOP321_TMR_EN 0x02 -#define IOP321_TMR_RELOAD 0x04 -#define IOP321_TMR_PRIVILEGED 0x09 - -#define IOP321_TMR_RATIO_1_1 0x00 -#define IOP321_TMR_RATIO_4_1 0x10 -#define IOP321_TMR_RATIO_8_1 0x20 -#define IOP321_TMR_RATIO_16_1 0x30 - -#define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8) -#define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC) -#define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0) -#define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4) -#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8) -#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC) - -/* Application accelerator unit 0x00000800 - 0x000008FF */ -#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800) -#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804) -#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808) -#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C) -#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810) -#define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814) -#define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818) -#define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C) -#define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C) -#define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830) -#define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834) -#define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838) -#define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840) -#define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844) -#define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848) -#define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C) -#define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850) -#define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854) -#define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858) -#define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C) -#define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864) -#define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868) -#define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C) -#define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870) -#define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874) -#define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878) -#define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C) -#define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880) -#define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888) -#define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C) -#define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890) -#define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894) -#define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898) -#define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C) -#define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0) -#define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4) -#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820) -#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824) -#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828) -#define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c) -#define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860) -#define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884) - - -/* SSP serial port unit 0x00001600 - 0x0000167F */ -/* I2C bus interface unit 0x00001680 - 0x000016FF */ -#define IOP321_ICR0 (volatile u32 *)IOP321_REG_ADDR(0x00001680) -#define IOP321_ISR0 (volatile u32 *)IOP321_REG_ADDR(0x00001684) -#define IOP321_ISAR0 (volatile u32 *)IOP321_REG_ADDR(0x00001688) -#define IOP321_IDBR0 (volatile u32 *)IOP321_REG_ADDR(0x0000168C) -/* Reserved 0x00001690 */ -#define IOP321_IBMR0 (volatile u32 *)IOP321_REG_ADDR(0x00001694) -/* Reserved 0x00001698 */ -/* Reserved 0x0000169C */ -#define IOP321_ICR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A0) -#define IOP321_ISR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A4) -#define IOP321_ISAR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A8) -#define IOP321_IDBR1 (volatile u32 *)IOP321_REG_ADDR(0x000016AC) -#define IOP321_IBMR1 (volatile u32 *)IOP321_REG_ADDR(0x000016B4) -/* Reserved 0x000016B8 through 0x000016FC */ - -/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ - - -#ifndef __ASSEMBLY__ -extern void iop321_map_io(void); -extern void iop321_init_irq(void); -extern void iop321_time_init(void); -#endif - -#endif // _IOP321_HW_H_ diff --git a/include/asm-arm/arch-iop3xx/iop331-irqs.h b/include/asm-arm/arch-iop3xx/iop331-irqs.h deleted file mode 100644 index 7135ad7e335e..000000000000 --- a/include/asm-arm/arch-iop3xx/iop331-irqs.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/irqs.h - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright: (C) 2003 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef _IOP331_IRQS_H_ -#define _IOP331_IRQS_H_ - -/* - * IOP80331 chipset interrupts - */ -#define IOP331_IRQ_OFS 0 -#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x)) - -/* - * On IRQ or FIQ register - */ -#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0) -#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1) -#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2) -#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3) -#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4) -#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5) -#define IRQ_IOP331_AA_EOT IOP331_IRQ(6) -#define IRQ_IOP331_AA_EOC IOP331_IRQ(7) -#define IRQ_IOP331_TIMER0 IOP331_IRQ(8) -#define IRQ_IOP331_TIMER1 IOP331_IRQ(9) -#define IRQ_IOP331_I2C_0 IOP331_IRQ(10) -#define IRQ_IOP331_I2C_1 IOP331_IRQ(11) -#define IRQ_IOP331_MSG IOP331_IRQ(12) -#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13) -#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14) -#define IRQ_IOP331_PERFMON IOP331_IRQ(15) -#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16) -#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17) -#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18) -#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19) -#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20) -#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21) -#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22) -#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23) -#define IRQ_IOP331_XINT0 IOP331_IRQ(24) -#define IRQ_IOP331_XINT1 IOP331_IRQ(25) -#define IRQ_IOP331_XINT2 IOP331_IRQ(26) -#define IRQ_IOP331_XINT3 IOP331_IRQ(27) -#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28) -#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29) -#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30) -#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31) -#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0 -#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1 -#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2 -#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3 -#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4 -#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5 -#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6 -#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7 -#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8 -#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9 -#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10 -#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11 -#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12 -#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13 -#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14 -#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15 -#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16 -#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17 -#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18 -#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19 -#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20 -#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21 -#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22 -#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23 -#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24 -#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25 -#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26 -#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27 -#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28 -#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29 -#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30 -#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31 - -#define NR_IOP331_IRQS (IOP331_IRQ(63) + 1) - -#define NR_IRQS NR_IOP331_IRQS - - -/* - * Interrupts available on the IQ80331 board - */ - -/* - * On board devices - */ -#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0 -#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0 -#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1 - -/* - * PCI interrupts - */ -#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0 -#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1 -#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2 -#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3 - -/* - * Interrupts available on the IQ80332 board - */ - -/* - * On board devices - */ -#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0 -#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0 -#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1 - -/* - * PCI interrupts - */ -#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0 -#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1 -#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2 -#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3 - -#endif // _IOP331_IRQ_H_ diff --git a/include/asm-arm/arch-iop3xx/iop331.h b/include/asm-arm/arch-iop3xx/iop331.h deleted file mode 100644 index 4d7bcc62cb3e..000000000000 --- a/include/asm-arm/arch-iop3xx/iop331.h +++ /dev/null @@ -1,363 +0,0 @@ -/* - * linux/include/asm/arch-iop3xx/iop331.h - * - * Intel IOP331 Chip definitions - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright (C) 2003, 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IOP331_HW_H_ -#define _IOP331_HW_H_ - - -/* - * This is needed for mixed drivers that need to work on all - * IOP3xx variants but behave slightly differently on each. - */ -#ifndef __ASSEMBLY__ -#ifdef CONFIG_ARCH_IOP33X -/*#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090) */ -#define iop_is_331() ((processor_id & 0xffffff30) == 0x69054010) -#else -#define iop_is_331() 0 -#endif -#endif - -/* - * IOP331 I/O and Mem space regions for PCI autoconfiguration - */ -#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000 -#define IOP331_PCI_LOWER_IO_PA 0x90000000 -#define IOP331_PCI_LOWER_IO_VA 0xfe000000 -#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR) -#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1) -#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1) -#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1) -#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA) - -/* this can be 128M if OMWTVR1 is set */ -#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ -/* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */ -#define IOP331_PCI_LOWER_MEM_PA 0x80000000 -#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0) -#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1) -#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1) -#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA) - -/* - * IOP331 chipset registers - */ -#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ -#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */ -#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg)) - -/* Reserved 0x00000000 through 0x000000FF */ - -/* Address Translation Unit 0x00000100 through 0x000001FF */ -#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100) -#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102) -#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104) -#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106) -#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108) -#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109) -#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C) -#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D) -#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E) -#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F) -#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110) -#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114) -#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118) -#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C) -#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120) -#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124) -#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C) -#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E) -#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130) -#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134) -/* Reserved 0x00000138 through 0x0000013B */ -#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C) -#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D) -#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E) -#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F) -#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140) -#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144) -#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148) -#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C) -#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150) -#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154) -#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158) -#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C) -#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160) -#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164) -#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168) -#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C) -/* Reserved 0x00000170 through 0x00000177*/ -#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178) -/* Reserved 0x0000017C through 0x0000017F*/ -#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180) -#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184) -#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188) -#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C) -#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190) -#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194) -#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198) -#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C) -/* Reserved 0x000001A0 through 0x000001A3*/ -#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4) -/* Reserved 0x000001A8 through 0x000001AB*/ -#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC) -/* Reserved 0x000001B0 through 0x000001BB*/ -#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8) -#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9) -#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA) -#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC) -#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0) -#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1) -#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2) -#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4) -/* Reserved 0x000001C6 through 0x000001CF */ -#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0) -#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1) -#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2) -#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4) -#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8) -#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC) -#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0) -#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1) -#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2) -#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4) -#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC) - -/* Messaging Unit 0x00000300 through 0x000003FF */ - -/* Reserved 0x00000300 through 0x0000030c */ -#define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310) -#define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314) -#define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318) -#define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C) -#define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320) -#define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324) -#define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328) -#define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C) -#define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330) -#define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334) -/* Reserved 0x00000338 through 0x0000034F */ -#define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350) -#define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354) -/* Reserved 0x00000358 through 0x0000035C */ -#define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360) -#define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364) -#define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368) -#define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C) -#define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370) -#define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374) -#define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378) -#define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C) -#define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380) -/* Reserved 0x00000384 through 0x000003FF */ - -/* DMA Controller 0x00000400 through 0x000004FF */ -#define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400) -#define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404) -#define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C) -#define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410) -#define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414) -#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418) -#define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C) -#define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420) -#define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424) -/* Reserved 0x00000428 through 0x0000043C */ -#define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440) -#define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444) -#define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C) -#define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450) -#define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454) -#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458) -#define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C) -#define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460) -#define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464) -/* Reserved 0x00000468 through 0x000004FF */ - -/* Memory controller 0x00000500 through 0x0005FF */ - -/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ -#define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680) -#define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684) -#define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688) -#define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C) -#define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690) -#define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694) -#define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698) -#define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C) -#define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0) -#define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4) -#define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8) -#define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC) -#define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0) -#define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4) -#define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8) -/* Reserved 0x000006BC */ -#define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0) -/* Reserved 0x000006C4 through 0x000006DC */ -#define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0) -#define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4) - -#define IOP331_PBCR_EN 0x1 - -#define IOP331_PBISR_BOOR_ERR 0x1 - - - -/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ -/* Internal arbitration unit 0x00000780 through 0x0007BF */ - -/* Interrupt Controller */ -#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790) -#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794) -#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798) -#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C) -#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0) -#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4) -#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8) -#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC) -#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0) -#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4) -#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8) -#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC) -#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0) -#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4) -#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8) -#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC) - - -/* Timers */ - -#define IOP331_TU_TMR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D0) -#define IOP331_TU_TMR1 (volatile u32 *)IOP331_REG_ADDR(0x000007D4) - -#define IOP331_TMR_TC 0x01 -#define IOP331_TMR_EN 0x02 -#define IOP331_TMR_RELOAD 0x04 -#define IOP331_TMR_PRIVILEGED 0x09 - -#define IOP331_TMR_RATIO_1_1 0x00 -#define IOP331_TMR_RATIO_4_1 0x10 -#define IOP331_TMR_RATIO_8_1 0x20 -#define IOP331_TMR_RATIO_16_1 0x30 - -#define IOP331_TU_TCR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D8) -#define IOP331_TU_TCR1 (volatile u32 *)IOP331_REG_ADDR(0x000007DC) -#define IOP331_TU_TRR0 (volatile u32 *)IOP331_REG_ADDR(0x000007E0) -#define IOP331_TU_TRR1 (volatile u32 *)IOP331_REG_ADDR(0x000007E4) -#define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8) -#define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC) - -#if defined(CONFIG_ARCH_IOP33X) -#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */ -#endif - -#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333) -#undef IOP331_TICK_RATE -#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */ -#endif - -/* Application accelerator unit 0x00000800 - 0x000008FF */ -#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800) -#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804) -#define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808) -#define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C) -#define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810) -#define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814) -#define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818) -#define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C) -#define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C) -#define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830) -#define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834) -#define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838) -#define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840) -#define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844) -#define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848) -#define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C) -#define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850) -#define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854) -#define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858) -#define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C) -#define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864) -#define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868) -#define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C) -#define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870) -#define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874) -#define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878) -#define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C) -#define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880) -#define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888) -#define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C) -#define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890) -#define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894) -#define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898) -#define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C) -#define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0) -#define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4) -#define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820) -#define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824) -#define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828) -#define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c) -#define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860) -#define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884) - - -#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0) -#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8) -/* SSP serial port unit 0x00001600 - 0x0000167F */ - -/* I2C bus interface unit 0x00001680 - 0x000016FF */ -/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ - -#define IOP331_ICR0 (volatile u32 *)IOP331_REG_ADDR(0x00001680) -#define IOP331_ISR0 (volatile u32 *)IOP331_REG_ADDR(0x00001684) -#define IOP331_ISAR0 (volatile u32 *)IOP331_REG_ADDR(0x00001688) -#define IOP331_IDBR0 (volatile u32 *)IOP331_REG_ADDR(0x0000168C) -/* Reserved 0x00001690 */ -#define IOP331_IBMR0 (volatile u32 *)IOP331_REG_ADDR(0x00001694) -/* Reserved 0x00001698 */ -/* Reserved 0x0000169C */ -#define IOP331_ICR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A0) -#define IOP331_ISR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A4) -#define IOP331_ISAR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A8) -#define IOP331_IDBR1 (volatile u32 *)IOP331_REG_ADDR(0x000016AC) -#define IOP331_IBMR1 (volatile u32 *)IOP331_REG_ADDR(0x000016B4) -/* Reserved 0x000016B8 through 0x000016FF */ - -/* 0x00001700 through 0x0000172C UART 0 */ - -/* Reserved 0x00001730 through 0x0000173F */ - -/* 0x00001740 through 0x0000176C UART 1 */ - -#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */ -#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */ -#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */ -#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */ - -/* Reserved 0x00001770 through 0x0000177F */ - -/* General Purpose I/O Registers */ -#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780) -#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784) -#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788) - -/* Reserved 0x0000178c through 0x000019ff */ - - -#ifndef __ASSEMBLY__ -extern void iop331_map_io(void); -extern void iop331_init_irq(void); -extern void iop331_time_init(void); -#endif - -#endif // _IOP331_HW_H_ diff --git a/include/asm-arm/arch-iop3xx/iq31244.h b/include/asm-arm/arch-iop3xx/iq31244.h deleted file mode 100644 index 4177cfa8100f..000000000000 --- a/include/asm-arm/arch-iop3xx/iq31244.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * linux/include/asm/arch-iop3xx/iq31244.h - * - * Intel IQ31244 evaluation board registers - */ - -#ifndef _IQ31244_H_ -#define _IQ31244_H_ - -#define IQ31244_FLASHBASE 0xf0000000 /* Flash */ -#define IQ31244_FLASHSIZE 0x00800000 -#define IQ31244_FLASHWIDTH 2 - -#define IQ31244_UART 0xfe800000 /* UART #1 */ -#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ -#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ -#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ -#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ - -#ifndef __ASSEMBLY__ -extern void iq31244_map_io(void); -#endif - -#endif // _IQ31244_H_ diff --git a/include/asm-arm/arch-iop3xx/iq80321.h b/include/asm-arm/arch-iop3xx/iq80321.h deleted file mode 100644 index cb8725979ffa..000000000000 --- a/include/asm-arm/arch-iop3xx/iq80321.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * linux/include/asm/arch-iop3xx/iq80321.h - * - * Intel IQ80321 evaluation board registers - */ - -#ifndef _IQ80321_H_ -#define _IQ80321_H_ - -#define IQ80321_FLASHBASE 0xf0000000 /* Flash */ -#define IQ80321_FLASHSIZE 0x00800000 -#define IQ80321_FLASHWIDTH 1 - -#define IQ80321_UART 0xfe800000 /* UART #1 */ -#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ -#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ -#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ -#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ - -#ifndef __ASSEMBLY__ -extern void iq80321_map_io(void); -#endif - -#endif // _IQ80321_H_ diff --git a/include/asm-arm/arch-iop3xx/iq80331.h b/include/asm-arm/arch-iop3xx/iq80331.h deleted file mode 100644 index 0668e78d483e..000000000000 --- a/include/asm-arm/arch-iop3xx/iq80331.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/include/asm/arch-iop3xx/iq80331.h - * - * Intel IQ80331 evaluation board registers - */ - -#ifndef _IQ80331_H_ -#define _IQ80331_H_ - -#define IQ80331_FLASHBASE 0xc0000000 /* Flash */ -#define IQ80331_FLASHSIZE 0x00800000 -#define IQ80331_FLASHWIDTH 1 - -#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ -#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ -#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ -#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ - -#ifndef __ASSEMBLY__ -extern void iq80331_map_io(void); -#endif - -#endif // _IQ80331_H_ diff --git a/include/asm-arm/arch-iop3xx/iq80332.h b/include/asm-arm/arch-iop3xx/iq80332.h deleted file mode 100644 index e5fff1775d1a..000000000000 --- a/include/asm-arm/arch-iop3xx/iq80332.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/include/asm/arch-iop3xx/iq80332.h - * - * Intel IQ80332 evaluation board registers - */ - -#ifndef _IQ80332_H_ -#define _IQ80332_H_ - -#define IQ80332_FLASHBASE 0xc0000000 /* Flash */ -#define IQ80332_FLASHSIZE 0x00800000 -#define IQ80332_FLASHWIDTH 1 - -#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ -#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ -#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ -#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ - -#ifndef __ASSEMBLY__ -extern void iq80332_map_io(void); -#endif - -#endif // _IQ80332_H_ diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h deleted file mode 100644 index 4f7c7aa87b4a..000000000000 --- a/include/asm-arm/arch-iop3xx/irqs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/irqs.h - * - * Copyright: (C) 2001-2003 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -/* - * Chipset-specific bits - */ -#ifdef CONFIG_ARCH_IOP32X -#include "iop321-irqs.h" -#endif - -#ifdef CONFIG_ARCH_IOP33X -#include "iop331-irqs.h" -#endif diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h deleted file mode 100644 index 25666184e8fc..000000000000 --- a/include/asm-arm/arch-iop3xx/memory.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/memory.h - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include - -/* - * Physical DRAM offset. - */ -#ifndef CONFIG_ARCH_IOP33X -#define PHYS_OFFSET UL(0xa0000000) -#else -#define PHYS_OFFSET UL(0x00000000) -#endif - -/* - * Virtual view <-> PCI DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#if defined(CONFIG_ARCH_IOP32X) - -#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0)) -#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2))) - -#elif defined(CONFIG_ARCH_IOP33X) - -#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0)) -#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2))) - -#endif - -#endif diff --git a/include/asm-arm/arch-iop3xx/system.h b/include/asm-arm/arch-iop3xx/system.h deleted file mode 100644 index a16cbb77a7f6..000000000000 --- a/include/asm-arm/arch-iop3xx/system.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/system.h - * - * Copyright (C) 2001 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - - -static inline void arch_reset(char mode) -{ -#ifdef CONFIG_ARCH_IOP32X - *IOP321_PCSR = 0x30; -#endif - -#ifdef CONFIG_ARCH_IOP33X - *IOP331_PCSR = 0x30; -#endif - - if ( 1 && mode == 's') { - /* Jump into ROM at address 0 */ - cpu_reset(0); - } else { - /* No on-chip reset capability */ - cpu_reset(0); - } -} - diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h deleted file mode 100644 index 14ca8d0f7b29..000000000000 --- a/include/asm-arm/arch-iop3xx/timex.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/timex.h - * - * IOP3xx architecture timex specifications - */ -#include - -#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244) - -#define CLOCK_TICK_RATE IOP321_TICK_RATE - -#elif defined(CONFIG_ARCH_IQ80331) || defined(CONFIG_MACH_IQ80332) - -#define CLOCK_TICK_RATE IOP331_TICK_RATE - -#else - -#error "No IOP3xx timex information for this architecture" - -#endif diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h deleted file mode 100644 index 066c16bc1250..000000000000 --- a/include/asm-arm/arch-iop3xx/uncompress.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/uncompress.h - */ -#include -#include -#include -#include - -#ifdef CONFIG_ARCH_IOP32X -#define UTYPE unsigned char * -#elif defined(CONFIG_ARCH_IOP33X) -#define UTYPE u32 * -#else -#error "Missing IOP3xx arch type def" -#endif - -static volatile UTYPE uart_base; - -#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) - -static inline void putc(char c) -{ - while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) - barrier(); - *uart_base = c; -} - -static inline void flush(void) -{ -} - -static __inline__ void __arch_decomp_setup(unsigned long arch_id) -{ - if(machine_is_iq80321()) - uart_base = (volatile UTYPE)IQ80321_UART; - else if(machine_is_iq31244()) - uart_base = (volatile UTYPE)IQ31244_UART; - else if(machine_is_iq80331() || machine_is_iq80332()) - uart_base = (volatile UTYPE)IOP331_UART0_PHYS; - else - uart_base = (volatile UTYPE)0xfe800000; -} - -/* - * nothing to do - */ -#define arch_decomp_setup() __arch_decomp_setup(arch_id) -#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-iop3xx/vmalloc.h b/include/asm-arm/arch-iop3xx/vmalloc.h deleted file mode 100644 index 0f2f6847f93c..000000000000 --- a/include/asm-arm/arch-iop3xx/vmalloc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop3xx/vmalloc.h - */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -//#define VMALLOC_END (0xe8000000) -/* increase usable physical RAM to ~992M per RMK */ -#define VMALLOC_END (0xfe000000) - -- cgit v1.2.3 From 7ae1f7ec525c32db441836ab0ab010b85cb819a2 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:12:53 +0100 Subject: [ARM] 3818/1: iop3xx: introduce arch/arm/plat-iop for shared iop32x/iop33x code Introduce the arch/arm/plat-iop directory, for code shared between the iop32x and iop33x, and move the common memory map setup bits there. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/Kconfig | 5 +++++ arch/arm/Makefile | 1 + arch/arm/mach-iop32x/iq31244-mm.c | 3 ++- arch/arm/mach-iop32x/iq80321-mm.c | 3 ++- arch/arm/mach-iop32x/setup.c | 22 ------------------ arch/arm/mach-iop33x/Makefile | 4 ++-- arch/arm/mach-iop33x/iq80331-mm.c | 35 ----------------------------- arch/arm/mach-iop33x/iq80332-mm.c | 35 ----------------------------- arch/arm/mach-iop33x/setup.c | 35 +++-------------------------- arch/arm/plat-iop/Makefile | 8 +++++++ arch/arm/plat-iop/setup.c | 38 +++++++++++++++++++++++++++++++ include/asm-arm/arch-iop32x/iop321.h | 1 - include/asm-arm/arch-iop33x/iop331.h | 1 - include/asm-arm/hardware/iop3xx.h | 43 ++++++++++++++++++++++++++++++++++++ 14 files changed, 104 insertions(+), 130 deletions(-) delete mode 100644 arch/arm/mach-iop33x/iq80331-mm.c delete mode 100644 arch/arm/mach-iop33x/iq80332-mm.c create mode 100644 arch/arm/plat-iop/Makefile create mode 100644 arch/arm/plat-iop/setup.c create mode 100644 include/asm-arm/hardware/iop3xx.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0fb17bbb86bc..665ce173e664 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -205,6 +205,7 @@ config ARCH_IMX config ARCH_IOP32X bool "IOP32x-based" depends on MMU + select PLAT_IOP select PCI help Support for Intel's 80219 and IOP32X (XScale) family of @@ -213,6 +214,7 @@ config ARCH_IOP32X config ARCH_IOP33X bool "IOP33x-based" depends on MMU + select PLAT_IOP select PCI help Support for Intel's IOP33X (XScale) family of processors. @@ -362,6 +364,9 @@ source "arch/arm/mach-netx/Kconfig" config ARCH_ACORN bool +config PLAT_IOP + bool + source arch/arm/mm/Kconfig # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ac786bf0f546..80cee786500c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -158,6 +158,7 @@ core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ) core-$(CONFIG_VFP) += arch/arm/vfp/ # If we have a common platform directory, then include it in the build. +core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ diff --git a/arch/arm/mach-iop32x/iq31244-mm.c b/arch/arm/mach-iop32x/iq31244-mm.c index ffc6692c95ad..fba22d5d908f 100644 --- a/arch/arm/mach-iop32x/iq31244-mm.c +++ b/arch/arm/mach-iop32x/iq31244-mm.c @@ -21,6 +21,7 @@ #include #include +#include /* @@ -39,7 +40,7 @@ static struct map_desc iq31244_io_desc[] __initdata = { void __init iq31244_map_io(void) { - iop321_map_io(); + iop3xx_map_io(); iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc)); } diff --git a/arch/arm/mach-iop32x/iq80321-mm.c b/arch/arm/mach-iop32x/iq80321-mm.c index 5f702a7ff622..b6a3079ad29e 100644 --- a/arch/arm/mach-iop32x/iq80321-mm.c +++ b/arch/arm/mach-iop32x/iq80321-mm.c @@ -21,6 +21,7 @@ #include #include +#include /* @@ -39,7 +40,7 @@ static struct map_desc iq80321_io_desc[] __initdata = { void __init iq80321_map_io(void) { - iop321_map_io(); + iop3xx_map_io(); iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc)); } diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c index 729678799271..48d806474f40 100644 --- a/arch/arm/mach-iop32x/setup.c +++ b/arch/arm/mach-iop32x/setup.c @@ -32,23 +32,6 @@ #define IOP321_UART_XTAL 1843200 -/* - * Standard IO mapping for all IOP321 based systems - */ -static struct map_desc iop321_std_desc[] __initdata = { - { /* mem mapped registers */ - .virtual = IOP321_VIRT_MEM_BASE, - .pfn = __phys_to_pfn(IOP321_PHYS_MEM_BASE), - .length = 0x00002000, - .type = MT_DEVICE - }, { /* PCI IO space */ - .virtual = IOP321_PCI_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP321_PCI_LOWER_IO_PA), - .length = IOP321_PCI_IO_WINDOW_SIZE, - .type = MT_DEVICE - } -}; - #ifdef CONFIG_ARCH_IQ80321 #define UARTBASE IQ80321_UART #define IRQ_UART IRQ_IQ80321_UART @@ -126,11 +109,6 @@ void __init iop32x_init(void) platform_add_devices(iop32x_devices, ARRAY_SIZE(iop32x_devices)); } -} - -void __init iop321_map_io(void) -{ - iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc)); early_serial_setup(&iop321_serial_ports[0]); } diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile index 0f1a8fffe187..7865923b0a60 100644 --- a/arch/arm/mach-iop33x/Makefile +++ b/arch/arm/mach-iop33x/Makefile @@ -7,5 +7,5 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_ARCH_IQ80331) += iq80331-mm.o iq80331-pci.o -obj-$(CONFIG_MACH_IQ80332) += iq80332-mm.o iq80332-pci.o +obj-$(CONFIG_ARCH_IQ80331) += iq80331-pci.o +obj-$(CONFIG_MACH_IQ80332) += iq80332-pci.o diff --git a/arch/arm/mach-iop33x/iq80331-mm.c b/arch/arm/mach-iop33x/iq80331-mm.c deleted file mode 100644 index eb59445a0fca..000000000000 --- a/arch/arm/mach-iop33x/iq80331-mm.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * linux/arch/arm/mach-iop33x/iq80331-mm.c - * - * Low level memory initialization for iq80331 platform - * - * Author: Dave Jiang - * Copyright (C) 2003 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include - -#include -#include -#include - -#include - - -/* - * IQ80331 specific IO mappings - * - * We use RedBoot's setup for the onboard devices. - */ - -void __init iq80331_map_io(void) -{ - iop331_map_io(); -} diff --git a/arch/arm/mach-iop33x/iq80332-mm.c b/arch/arm/mach-iop33x/iq80332-mm.c deleted file mode 100644 index f7bc73113ea8..000000000000 --- a/arch/arm/mach-iop33x/iq80332-mm.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * linux/arch/arm/mach-iop33x/iq80332-mm.c - * - * Low level memory initialization for iq80332 platform - * - * Author: Dave Jiang - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include - -#include -#include -#include - -#include - - -/* - * IQ80332 specific IO mappings - * - * We use RedBoot's setup for the onboard devices. - */ - -void __init iq80332_map_io(void) -{ - iop331_map_io(); -} diff --git a/arch/arm/mach-iop33x/setup.c b/arch/arm/mach-iop33x/setup.c index c14c7da5ec4c..67cb21cb0ad9 100644 --- a/arch/arm/mach-iop33x/setup.c +++ b/arch/arm/mach-iop33x/setup.c @@ -28,26 +28,10 @@ #include #include #include +#include #define IOP331_UART_XTAL 33334000 -/* - * Standard IO mapping for all IOP331 based systems - */ -static struct map_desc iop331_std_desc[] __initdata = { - { /* mem mapped registers */ - .virtual = IOP331_VIRT_MEM_BASE, - .pfn = __phys_to_pfn(IOP331_PHYS_MEM_BASE), - .length = 0x00002000, - .type = MT_DEVICE - }, { /* PCI IO space */ - .virtual = IOP331_PCI_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP331_PCI_LOWER_IO_PA), - .length = IOP331_PCI_IO_WINDOW_SIZE, - .type = MT_DEVICE - } -}; - static struct resource iop33x_uart0_resources[] = { [0] = { .start = IOP331_UART0_PHYS, @@ -172,30 +156,17 @@ void __init iop33x_init(void) } } -void __init iop331_map_io(void) -{ - iotable_init(iop331_std_desc, ARRAY_SIZE(iop331_std_desc)); -} - #ifdef CONFIG_ARCH_IOP33X extern void iop331_init_irq(void); extern struct sys_timer iop331_timer; #endif -#ifdef CONFIG_ARCH_IQ80331 -extern void iq80331_map_io(void); -#endif - -#ifdef CONFIG_MACH_IQ80332 -extern void iq80332_map_io(void); -#endif - #if defined(CONFIG_ARCH_IQ80331) MACHINE_START(IQ80331, "Intel IQ80331") /* Maintainer: Intel Corp. */ .phys_io = 0xfefff000, .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical - .map_io = iq80331_map_io, + .map_io = iop3xx_map_io, .init_irq = iop331_init_irq, .timer = &iop331_timer, .boot_params = 0x0100, @@ -207,7 +178,7 @@ MACHINE_START(IQ80332, "Intel IQ80332") /* Maintainer: Intel Corp. */ .phys_io = 0xfefff000, .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical - .map_io = iq80332_map_io, + .map_io = iop3xx_map_io, .init_irq = iop331_init_irq, .timer = &iop331_timer, .boot_params = 0x0100, diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile new file mode 100644 index 000000000000..b299103537c5 --- /dev/null +++ b/arch/arm/plat-iop/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +obj-y := setup.o +obj-m := +obj-n := +obj- := diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c new file mode 100644 index 000000000000..4689db638e95 --- /dev/null +++ b/arch/arm/plat-iop/setup.c @@ -0,0 +1,38 @@ +/* + * arch/arm/plat-iop/setup.c + * + * Author: Nicolas Pitre + * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2004 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +/* + * Standard IO mapping for all IOP3xx based systems + */ +static struct map_desc iop3xx_std_desc[] __initdata = { + { /* mem mapped registers */ + .virtual = IOP3XX_PERIPHERAL_VIRT_BASE, + .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), + .length = IOP3XX_PERIPHERAL_SIZE, + .type = MT_DEVICE, + }, { /* PCI IO space */ + .virtual = IOP3XX_PCI_LOWER_IO_VA, + .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA), + .length = IOP3XX_PCI_IO_WINDOW_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init iop3xx_map_io(void) +{ + iotable_init(iop3xx_std_desc, ARRAY_SIZE(iop3xx_std_desc)); +} diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h index 7ba93faf8da4..307272b07809 100644 --- a/include/asm-arm/arch-iop32x/iop321.h +++ b/include/asm-arm/arch-iop32x/iop321.h @@ -333,7 +333,6 @@ #ifndef __ASSEMBLY__ -extern void iop321_map_io(void); extern void iop321_init_irq(void); extern void iop321_time_init(void); #endif diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h index 780b707edb1e..21430f877ea7 100644 --- a/include/asm-arm/arch-iop33x/iop331.h +++ b/include/asm-arm/arch-iop33x/iop331.h @@ -350,7 +350,6 @@ #ifndef __ASSEMBLY__ -extern void iop331_map_io(void); extern void iop331_init_irq(void); extern void iop331_time_init(void); #endif diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h new file mode 100644 index 000000000000..c17cc19cdfab --- /dev/null +++ b/include/asm-arm/hardware/iop3xx.h @@ -0,0 +1,43 @@ +/* + * include/asm-arm/hardware/iop3xx.h + * + * Intel IOP32X and IOP33X register definitions + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IOP3XX_H +#define __IOP3XX_H + +/* + * IOP3XX processor registers + */ +#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000 +#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000 +#define IOP3XX_PERIPHERAL_SIZE 0x00002000 +#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) + + +/* + * IOP3XX I/O and Mem space regions for PCI autoconfiguration + */ +#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000 +#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 + +#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 +#define IOP3XX_PCI_LOWER_IO_PA 0x90000000 +#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 + + +#ifndef __ASSEMBLY__ +void iop3xx_map_io(void); +#endif + + +#endif -- cgit v1.2.3 From e25d64f1242e8586f6e20c26fd876a4d956a6c45 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:15:21 +0100 Subject: [ARM] 3819/1: iop3xx: factor out shared i2c code Move the i2c bits shared between iop32x and iop33x to plat-iop/i2c.c and include/asm-arm/hardware/iop3xx.h. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/common.c | 17 ++++---- arch/arm/mach-iop32x/setup.c | 53 ++--------------------- arch/arm/mach-iop33x/setup.c | 44 +------------------- arch/arm/plat-iop/Makefile | 2 +- arch/arm/plat-iop/i2c.c | 81 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-iop32x/iop321.h | 14 ------- include/asm-arm/arch-iop33x/iop331.h | 16 ------- include/asm-arm/hardware/iop3xx.h | 15 +++++++ 8 files changed, 111 insertions(+), 131 deletions(-) create mode 100644 arch/arm/plat-iop/i2c.c (limited to 'include') diff --git a/arch/arm/mach-iop32x/common.c b/arch/arm/mach-iop32x/common.c index 8044af6a54e1..17e7d650fecb 100644 --- a/arch/arm/mach-iop32x/common.c +++ b/arch/arm/mach-iop32x/common.c @@ -14,6 +14,7 @@ #include #include +#include /* * Shared variables @@ -39,23 +40,23 @@ void ep80219_power_off(void) */ /* Send the Address byte w/ the start condition */ - *IOP321_IDBR1 = 0x60; - *IOP321_ICR1 = 0xE9; + *IOP3XX_IDBR1 = 0x60; + *IOP3XX_ICR1 = 0xE9; mdelay(1); /* Send the START_MSG byte w/ no start or stop condition */ - *IOP321_IDBR1 = 0x0F; - *IOP321_ICR1 = 0xE8; + *IOP3XX_IDBR1 = 0x0F; + *IOP3XX_ICR1 = 0xE8; mdelay(1); /* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or stop condition */ - *IOP321_IDBR1 = 0x03; - *IOP321_ICR1 = 0xE8; + *IOP3XX_IDBR1 = 0x03; + *IOP3XX_ICR1 = 0xE8; mdelay(1); /* Send an ignored byte w/ stop condition */ - *IOP321_IDBR1 = 0x00; - *IOP321_ICR1 = 0xEA; + *IOP3XX_IDBR1 = 0x00; + *IOP3XX_ICR1 = 0xEA; while (1) ; } diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c index 48d806474f40..1a03b0b41baa 100644 --- a/arch/arm/mach-iop32x/setup.c +++ b/arch/arm/mach-iop32x/setup.c @@ -29,6 +29,7 @@ #include #include #include +#include #define IOP321_UART_XTAL 1843200 @@ -57,58 +58,10 @@ static struct uart_port iop321_serial_ports[] = { } }; -static struct resource iop32x_i2c_0_resources[] = { - [0] = { - .start = 0xfffff680, - .end = 0xfffff698, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP321_I2C_0, - .end = IRQ_IOP321_I2C_0, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop32x_i2c_1_resources[] = { - [0] = { - .start = 0xfffff6a0, - .end = 0xfffff6b8, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP321_I2C_1, - .end = IRQ_IOP321_I2C_1, - .flags = IORESOURCE_IRQ - } -}; - -static struct platform_device iop32x_i2c_0_controller = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = iop32x_i2c_0_resources -}; - -static struct platform_device iop32x_i2c_1_controller = { - .name = "IOP3xx-I2C", - .id = 1, - .num_resources = 2, - .resource = iop32x_i2c_1_resources -}; - -static struct platform_device *iop32x_devices[] __initdata = { - &iop32x_i2c_0_controller, - &iop32x_i2c_1_controller -}; - void __init iop32x_init(void) { - if(iop_is_321()) - { - platform_add_devices(iop32x_devices, - ARRAY_SIZE(iop32x_devices)); - } + platform_device_register(&iop3xx_i2c0_device); + platform_device_register(&iop3xx_i2c1_device); early_serial_setup(&iop321_serial_ports[0]); } diff --git a/arch/arm/mach-iop33x/setup.c b/arch/arm/mach-iop33x/setup.c index 67cb21cb0ad9..ad737d6582b5 100644 --- a/arch/arm/mach-iop33x/setup.c +++ b/arch/arm/mach-iop33x/setup.c @@ -100,51 +100,9 @@ static struct platform_device iop33x_uart1 = { .resource = iop33x_uart1_resources, }; -static struct resource iop33x_i2c_0_resources[] = { - [0] = { - .start = 0xfffff680, - .end = 0xfffff698, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP331_I2C_0, - .end = IRQ_IOP331_I2C_0, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop33x_i2c_1_resources[] = { - [0] = { - .start = 0xfffff6a0, - .end = 0xfffff6b8, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP331_I2C_1, - .end = IRQ_IOP331_I2C_1, - .flags = IORESOURCE_IRQ - } -}; - -static struct platform_device iop33x_i2c_0_controller = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = iop33x_i2c_0_resources -}; - -static struct platform_device iop33x_i2c_1_controller = { - .name = "IOP3xx-I2C", - .id = 1, - .num_resources = 2, - .resource = iop33x_i2c_1_resources -}; - static struct platform_device *iop33x_devices[] __initdata = { &iop33x_uart0, &iop33x_uart1, - &iop33x_i2c_0_controller, - &iop33x_i2c_1_controller }; void __init iop33x_init(void) @@ -154,6 +112,8 @@ void __init iop33x_init(void) platform_add_devices(iop33x_devices, ARRAY_SIZE(iop33x_devices)); } + platform_device_register(&iop3xx_i2c0_device); + platform_device_register(&iop3xx_i2c1_device); } #ifdef CONFIG_ARCH_IOP33X diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile index b299103537c5..be6ab7c71ca3 100644 --- a/arch/arm/plat-iop/Makefile +++ b/arch/arm/plat-iop/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := setup.o +obj-y := i2c.o setup.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c new file mode 100644 index 000000000000..7ae149c2e982 --- /dev/null +++ b/arch/arm/plat-iop/i2c.c @@ -0,0 +1,81 @@ +/* + * arch/arm/plat-iop/i2c.c + * + * Author: Nicolas Pitre + * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2004 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ARCH_IOP32X +#define IRQ_IOP3XX_I2C_0 IRQ_IOP321_I2C_0 +#define IRQ_IOP3XX_I2C_1 IRQ_IOP321_I2C_1 +#endif +#ifdef CONFIG_ARCH_IOP33X +#define IRQ_IOP3XX_I2C_0 IRQ_IOP331_I2C_0 +#define IRQ_IOP3XX_I2C_1 IRQ_IOP331_I2C_1 +#endif + +static struct resource iop3xx_i2c0_resources[] = { + [0] = { + .start = 0xfffff680, + .end = 0xfffff697, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP3XX_I2C_0, + .end = IRQ_IOP3XX_I2C_0, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device iop3xx_i2c0_device = { + .name = "IOP3xx-I2C", + .id = 0, + .num_resources = 2, + .resource = iop3xx_i2c0_resources, +}; + + +static struct resource iop3xx_i2c1_resources[] = { + [0] = { + .start = 0xfffff6a0, + .end = 0xfffff6b7, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP3XX_I2C_1, + .end = IRQ_IOP3XX_I2C_1, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device iop3xx_i2c1_device = { + .name = "IOP3xx-I2C", + .id = 1, + .num_resources = 2, + .resource = iop3xx_i2c1_resources, +}; diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h index 307272b07809..1a82dd96bf50 100644 --- a/include/asm-arm/arch-iop32x/iop321.h +++ b/include/asm-arm/arch-iop32x/iop321.h @@ -314,20 +314,6 @@ /* SSP serial port unit 0x00001600 - 0x0000167F */ /* I2C bus interface unit 0x00001680 - 0x000016FF */ -#define IOP321_ICR0 (volatile u32 *)IOP321_REG_ADDR(0x00001680) -#define IOP321_ISR0 (volatile u32 *)IOP321_REG_ADDR(0x00001684) -#define IOP321_ISAR0 (volatile u32 *)IOP321_REG_ADDR(0x00001688) -#define IOP321_IDBR0 (volatile u32 *)IOP321_REG_ADDR(0x0000168C) -/* Reserved 0x00001690 */ -#define IOP321_IBMR0 (volatile u32 *)IOP321_REG_ADDR(0x00001694) -/* Reserved 0x00001698 */ -/* Reserved 0x0000169C */ -#define IOP321_ICR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A0) -#define IOP321_ISR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A4) -#define IOP321_ISAR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A8) -#define IOP321_IDBR1 (volatile u32 *)IOP321_REG_ADDR(0x000016AC) -#define IOP321_IBMR1 (volatile u32 *)IOP321_REG_ADDR(0x000016B4) -/* Reserved 0x000016B8 through 0x000016FC */ /* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h index 21430f877ea7..a7f47122c5e1 100644 --- a/include/asm-arm/arch-iop33x/iop331.h +++ b/include/asm-arm/arch-iop33x/iop331.h @@ -311,22 +311,6 @@ /* SSP serial port unit 0x00001600 - 0x0000167F */ /* I2C bus interface unit 0x00001680 - 0x000016FF */ -/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ - -#define IOP331_ICR0 (volatile u32 *)IOP331_REG_ADDR(0x00001680) -#define IOP331_ISR0 (volatile u32 *)IOP331_REG_ADDR(0x00001684) -#define IOP331_ISAR0 (volatile u32 *)IOP331_REG_ADDR(0x00001688) -#define IOP331_IDBR0 (volatile u32 *)IOP331_REG_ADDR(0x0000168C) -/* Reserved 0x00001690 */ -#define IOP331_IBMR0 (volatile u32 *)IOP331_REG_ADDR(0x00001694) -/* Reserved 0x00001698 */ -/* Reserved 0x0000169C */ -#define IOP331_ICR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A0) -#define IOP331_ISR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A4) -#define IOP331_ISAR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A8) -#define IOP331_IDBR1 (volatile u32 *)IOP331_REG_ADDR(0x000016AC) -#define IOP331_IBMR1 (volatile u32 *)IOP331_REG_ADDR(0x000016B4) -/* Reserved 0x000016B8 through 0x000016FF */ /* 0x00001700 through 0x0000172C UART 0 */ diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index c17cc19cdfab..ea7d05970001 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -23,6 +23,18 @@ #define IOP3XX_PERIPHERAL_SIZE 0x00002000 #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) +/* I2C bus interface unit */ +#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) +#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) +#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688) +#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c) +#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694) +#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0) +#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4) +#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8) +#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac) +#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4) + /* * IOP3XX I/O and Mem space regions for PCI autoconfiguration @@ -37,6 +49,9 @@ #ifndef __ASSEMBLY__ void iop3xx_map_io(void); + +extern struct platform_device iop3xx_i2c0_device; +extern struct platform_device iop3xx_i2c1_device; #endif -- cgit v1.2.3 From 0cb015f9dea8a40d82d170be1a4f39ff909890bf Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:16:23 +0100 Subject: [ARM] 3820/1: iop3xx: factor out shared pci code Merge the iop32x PCI code and iop33x PCI code into plat-iop/pci.c. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/plat-iop/Makefile | 2 +- arch/arm/plat-iop/pci.c | 247 ++++++++++++++++++++++++++++++++++++++ include/asm-arm/hardware/iop3xx.h | 60 +++++++++ include/asm-arm/mach/pci.h | 4 + 4 files changed, 312 insertions(+), 1 deletion(-) create mode 100644 arch/arm/plat-iop/pci.c (limited to 'include') diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile index be6ab7c71ca3..efde7a513fb7 100644 --- a/arch/arm/plat-iop/Makefile +++ b/arch/arm/plat-iop/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := i2c.o setup.o +obj-y := i2c.o pci.o setup.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c new file mode 100644 index 000000000000..e647812654f2 --- /dev/null +++ b/arch/arm/plat-iop/pci.c @@ -0,0 +1,247 @@ +/* + * arch/arm/plat-iop/pci.c + * + * PCI support for the Intel IOP32X and IOP33X processors + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// #define DEBUG + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) do { } while (0) +#endif + +/* + * This routine builds either a type0 or type1 configuration command. If the + * bus is on the 803xx then a type0 made, else a type1 is created. + */ +static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where) +{ + struct pci_sys_data *sys = bus->sysdata; + u32 addr; + + if (sys->busnr == bus->number) + addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); + else + addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; + + addr |= PCI_FUNC(devfn) << 8 | (where & ~3); + + return addr; +} + +/* + * This routine checks the status of the last configuration cycle. If an error + * was detected it returns a 1, else it returns a 0. The errors being checked + * are parity, master abort, target abort (master and target). These types of + * errors occure during a config cycle where there is no device, like during + * the discovery stage. + */ +static int iop3xx_pci_status(void) +{ + unsigned int status; + int ret = 0; + + /* + * Check the status registers. + */ + status = *IOP3XX_ATUSR; + if (status & 0xf900) { + DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); + *IOP3XX_ATUSR = status & 0xf900; + ret = 1; + } + + status = *IOP3XX_ATUISR; + if (status & 0x679f) { + DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); + *IOP3XX_ATUISR = status & 0x679f; + ret = 1; + } + + return ret; +} + +/* + * Simply write the address register and read the configuration + * data. Note that the 4 nop's ensure that we are able to handle + * a delayed abort (in theory.) + */ +static inline u32 iop3xx_read(unsigned long addr) +{ + u32 val; + + __asm__ __volatile__( + "str %1, [%2]\n\t" + "ldr %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : "=r" (val) + : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); + + return val; +} + +/* + * The read routines must check the error status of the last configuration + * cycle. If there was an error, the routine returns all hex f's. + */ +static int +iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + unsigned long addr = iop3xx_cfg_address(bus, devfn, where); + u32 val = iop3xx_read(addr) >> ((where & 3) * 8); + + if (iop3xx_pci_status()) + val = 0xffffffff; + + *value = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + unsigned long addr = iop3xx_cfg_address(bus, devfn, where); + u32 val; + + if (size != 4) { + val = iop3xx_read(addr); + if (iop3xx_pci_status()) + return PCIBIOS_SUCCESSFUL; + + where = (where & 3) * 8; + + if (size == 1) + val &= ~(0xff << where); + else + val &= ~(0xffff << where); + + *IOP3XX_OCCDR = val | value << where; + } else { + asm volatile( + "str %1, [%2]\n\t" + "str %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : + : "r" (value), "r" (addr), + "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); + } + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops iop3xx_ops = { + .read = iop3xx_read_config, + .write = iop3xx_write_config, +}; + +/* + * When a PCI device does not exist during config cycles, the 80200 gets a + * bus error instead of returning 0xffffffff. This handler simply returns. + */ +static int +iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", + addr, fsr, regs->ARM_pc, regs->ARM_lr); + + /* + * If it was an imprecise abort, then we need to correct the + * return address to be _after_ the instruction. + */ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; + + return 0; +} + +int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + if (nr != 0) + return 0; + + res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + res[0].start = IOP3XX_PCI_LOWER_IO_VA; + res[0].end = IOP3XX_PCI_LOWER_IO_VA + IOP3XX_PCI_IO_WINDOW_SIZE - 1; + res[0].name = "IOP3XX PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + request_resource(&ioport_resource, &res[0]); + + res[1].start = IOP3XX_PCI_LOWER_MEM_PA; + res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; + res[1].name = "IOP3XX PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + request_resource(&iomem_resource, &res[1]); + + sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA; + sys->io_offset = IOP3XX_PCI_LOWER_IO_VA - IOP3XX_PCI_LOWER_IO_BA; + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + + return 1; +} + +struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &iop3xx_ops, sys); +} + +void iop3xx_pci_preinit(void) +{ + DBG("PCI: Intel 803xx PCI init code.\n"); + DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); + DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n", + *IOP3XX_OMWTVR0, + *IOP3XX_OIOWTVR); + DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); + DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n", + *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); + DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0); + DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n", + *IOP3XX_IABAR1, *IOP3XX_IALR1); + DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n", + *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); + DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n", + *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); + DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n", + *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); + + hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); +} diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index ea7d05970001..d488ced2e12d 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -23,6 +23,64 @@ #define IOP3XX_PERIPHERAL_SIZE 0x00002000 #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) +/* Address Translation Unit */ +#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100) +#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102) +#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104) +#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106) +#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108) +#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109) +#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c) +#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d) +#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e) +#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f) +#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110) +#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114) +#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118) +#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c) +#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120) +#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124) +#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c) +#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e) +#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130) +#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c) +#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d) +#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e) +#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f) +#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140) +#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144) +#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148) +#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c) +#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150) +#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154) +#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158) +#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c) +#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160) +#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164) +#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168) +#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c) +#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178) +#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180) +#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184) +#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188) +#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c) +#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190) +#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194) +#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198) +#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c) +#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4) +#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac) +#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc) +#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0) +#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1) +#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2) +#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4) +#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0) +#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1) +#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2) +#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) +#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) + /* I2C bus interface unit */ #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) @@ -41,10 +99,12 @@ */ #define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000 #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 +#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0) #define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 #define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 +#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR) #ifndef __ASSEMBLY__ diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h index 923e0ca66200..cb41defad4a1 100644 --- a/include/asm-arm/mach/pci.h +++ b/include/asm-arm/mach/pci.h @@ -52,6 +52,10 @@ void pci_common_init(struct hw_pci *); /* * PCI controllers */ +extern int iop3xx_pci_setup(int nr, struct pci_sys_data *); +extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); +extern void iop3xx_pci_preinit(void); + extern int iop321_setup(int nr, struct pci_sys_data *); extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *); extern void iop321_init(void); -- cgit v1.2.3 From 7e9740b11529a0a69789fbe92d324f293e6266f6 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:17:36 +0100 Subject: [ARM] 3821/1: iop3xx: switch iop32x/iop33x over to shared pci code Switch the iop32x and iop33x code over to the common PCI implementation, and remove the (nearly identical) iop32x and iop33x PCI implementations. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/Makefile | 2 +- arch/arm/mach-iop32x/common.c | 6 - arch/arm/mach-iop32x/iq31244-pci.c | 45 +------ arch/arm/mach-iop32x/iq80321-pci.c | 45 +------ arch/arm/mach-iop32x/irq.c | 2 +- arch/arm/mach-iop32x/pci.c | 220 -------------------------------- arch/arm/mach-iop33x/Makefile | 2 +- arch/arm/mach-iop33x/common.c | 22 ---- arch/arm/mach-iop33x/iq80331-pci.c | 45 +------ arch/arm/mach-iop33x/iq80332-pci.c | 45 +------ arch/arm/mach-iop33x/irq.c | 2 +- arch/arm/mach-iop33x/pci.c | 222 --------------------------------- include/asm-arm/arch-iop32x/hardware.h | 20 +-- include/asm-arm/arch-iop32x/iop321.h | 86 +------------ include/asm-arm/arch-iop32x/memory.h | 4 +- include/asm-arm/arch-iop32x/system.h | 2 +- include/asm-arm/arch-iop33x/hardware.h | 20 +-- include/asm-arm/arch-iop33x/iop331.h | 96 +------------- include/asm-arm/arch-iop33x/memory.h | 4 +- include/asm-arm/arch-iop33x/system.h | 2 +- include/asm-arm/mach/pci.h | 8 -- 21 files changed, 30 insertions(+), 870 deletions(-) delete mode 100644 arch/arm/mach-iop32x/pci.c delete mode 100644 arch/arm/mach-iop33x/common.c delete mode 100644 arch/arm/mach-iop33x/pci.c (limited to 'include') diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile index 94144f7efa6c..7266224ab6d7 100644 --- a/arch/arm/mach-iop32x/Makefile +++ b/arch/arm/mach-iop32x/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := common.o setup.o irq.o pci.o time.o +obj-y := common.o setup.o irq.o time.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-iop32x/common.c b/arch/arm/mach-iop32x/common.c index 17e7d650fecb..9a17a081327d 100644 --- a/arch/arm/mach-iop32x/common.c +++ b/arch/arm/mach-iop32x/common.c @@ -16,12 +16,6 @@ #include #include -/* - * Shared variables - */ -unsigned long iop3xx_pcibios_min_io = 0; -unsigned long iop3xx_pcibios_min_mem = 0; - #ifdef CONFIG_ARCH_EP80219 #include /* diff --git a/arch/arm/mach-iop32x/iq31244-pci.c b/arch/arm/mach-iop32x/iq31244-pci.c index e447c8103ecd..605b79553747 100644 --- a/arch/arm/mach-iop32x/iq31244-pci.c +++ b/arch/arm/mach-iop32x/iq31244-pci.c @@ -67,51 +67,12 @@ iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) return PCI_IRQ_TABLE_LOOKUP(0, 7); } -static int iq31244_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - - if(nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res[0].start = IOP321_PCI_LOWER_IO_VA; - res[0].end = IOP321_PCI_UPPER_IO_VA; - res[0].name = "IQ31244 PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - - res[1].start = IOP321_PCI_LOWER_MEM_PA; - res[1].end = IOP321_PCI_UPPER_MEM_PA; - res[1].name = "IQ31244 PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); - - sys->mem_offset = IOP321_PCI_MEM_OFFSET; - sys->io_offset = IOP321_PCI_IO_OFFSET; - - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; - - return 1; -} - -static void iq31244_preinit(void) -{ - iop321_init(); -} - static struct hw_pci iq31244_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, - .setup = iq31244_setup, - .scan = iop321_scan_bus, - .preinit = iq31244_preinit, + .setup = iop3xx_pci_setup, + .scan = iop3xx_pci_scan_bus, + .preinit = iop3xx_pci_preinit, .map_irq = iq31244_map_irq }; diff --git a/arch/arm/mach-iop32x/iq80321-pci.c b/arch/arm/mach-iop32x/iq80321-pci.c index 8767950e131f..cedc37b968b7 100644 --- a/arch/arm/mach-iop32x/iq80321-pci.c +++ b/arch/arm/mach-iop32x/iq80321-pci.c @@ -61,51 +61,12 @@ iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) return pci_irq_table[idsel%4][pin-1]; } -static int iq80321_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - - if(nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res[0].start = IOP321_PCI_LOWER_IO_VA; - res[0].end = IOP321_PCI_UPPER_IO_VA; - res[0].name = "IQ80321 PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - - res[1].start = IOP321_PCI_LOWER_MEM_PA; - res[1].end = IOP321_PCI_UPPER_MEM_PA; - res[1].name = "IQ80321 PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); - - sys->mem_offset = IOP321_PCI_MEM_OFFSET; - sys->io_offset = IOP321_PCI_IO_OFFSET; - - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; - - return 1; -} - -static void iq80321_preinit(void) -{ - iop321_init(); -} - static struct hw_pci iq80321_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, - .setup = iq80321_setup, - .scan = iop321_scan_bus, - .preinit = iq80321_preinit, + .setup = iop3xx_pci_setup, + .scan = iop3xx_pci_scan_bus, + .preinit = iop3xx_pci_preinit, .map_irq = iq80321_map_irq }; diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index c5f633d2d632..76f2d561dbc1 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -84,7 +84,7 @@ void __init iop321_init_irq(void) intstr_write(0); // treat all as IRQ if(machine_is_iq80321() || machine_is_iq31244()) // all interrupts are inputs to chip - *IOP321_PCIIRSR = 0x0f; + *IOP3XX_PCIIRSR = 0x0f; for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++) { diff --git a/arch/arm/mach-iop32x/pci.c b/arch/arm/mach-iop32x/pci.c deleted file mode 100644 index 1a7c683673f2..000000000000 --- a/arch/arm/mach-iop32x/pci.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * arch/arm/mach-iop32x/pci.c - * - * PCI support for the Intel IOP321 chipset - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -// #define DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) do { } while (0) -#endif - -/* - * This routine builds either a type0 or type1 configuration command. If the - * bus is on the 80321 then a type0 made, else a type1 is created. - */ -static u32 iop321_cfg_address(struct pci_bus *bus, int devfn, int where) -{ - struct pci_sys_data *sys = bus->sysdata; - u32 addr; - - if (sys->busnr == bus->number) - addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); - else - addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; - - addr |= PCI_FUNC(devfn) << 8 | (where & ~3); - - return addr; -} - -/* - * This routine checks the status of the last configuration cycle. If an error - * was detected it returns a 1, else it returns a 0. The errors being checked - * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during - * the discovery stage. - */ -static int iop321_pci_status(void) -{ - unsigned int status; - int ret = 0; - - /* - * Check the status registers. - */ - status = *IOP321_ATUSR; - if (status & 0xf900) - { - DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); - *IOP321_ATUSR = status & 0xf900; - ret = 1; - } - status = *IOP321_ATUISR; - if (status & 0x679f) - { - DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); - *IOP321_ATUISR = status & 0x679f; - ret = 1; - } - return ret; -} - -/* - * Simply write the address register and read the configuration - * data. Note that the 4 nop's ensure that we are able to handle - * a delayed abort (in theory.) - */ -static inline u32 iop321_read(unsigned long addr) -{ - u32 val; - - __asm__ __volatile__( - "str %1, [%2]\n\t" - "ldr %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : "=r" (val) - : "r" (addr), "r" (IOP321_OCCAR), "r" (IOP321_OCCDR)); - - return val; -} - -/* - * The read routines must check the error status of the last configuration - * cycle. If there was an error, the routine returns all hex f's. - */ -static int -iop321_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - unsigned long addr = iop321_cfg_address(bus, devfn, where); - u32 val = iop321_read(addr) >> ((where & 3) * 8); - - if( iop321_pci_status() ) - val = 0xffffffff; - - *value = val; - - return PCIBIOS_SUCCESSFUL; -} - -static int -iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - unsigned long addr = iop321_cfg_address(bus, devfn, where); - u32 val; - - if (size != 4) { - val = iop321_read(addr); - if (!iop321_pci_status() == 0) - return PCIBIOS_SUCCESSFUL; - - where = (where & 3) * 8; - - if (size == 1) - val &= ~(0xff << where); - else - val &= ~(0xffff << where); - - *IOP321_OCCDR = val | value << where; - } else { - asm volatile( - "str %1, [%2]\n\t" - "str %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : - : "r" (value), "r" (addr), - "r" (IOP321_OCCAR), "r" (IOP321_OCCDR)); - } - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops iop321_ops = { - .read = iop321_read_config, - .write = iop321_write_config, -}; - -/* - * When a PCI device does not exist during config cycles, the 80200 gets a - * bus error instead of returning 0xffffffff. This handler simply returns. - */ -int -iop321_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", - addr, fsr, regs->ARM_pc, regs->ARM_lr); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -/* - * Scan an IOP321 PCI bus. sys->bus defines which bus we scan. - */ -struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_bus(sys->busnr, &iop321_ops, sys); -} - -void iop321_init(void) -{ - DBG("PCI: Intel 80321 PCI init code.\n"); - DBG("ATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD); - DBG("ATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n", - *IOP321_OMWTVR0, - *IOP321_OIOWTVR); - DBG("ATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR); - DBG("ATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n", - *IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0); - DBG("ATU: IOP321_OMWTVR0=0x%08x\n", *IOP321_OMWTVR0); - DBG("ATU: IOP321_IABAR1=0x%08x IOP321_IALR1=0x%08x\n", - *IOP321_IABAR1, *IOP321_IALR1); - DBG("ATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n", - *IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR); - DBG("ATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n", - *IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2); - DBG("ATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n", - *IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3); - - hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort"); -} - diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile index 7865923b0a60..6c74f13b1139 100644 --- a/arch/arm/mach-iop33x/Makefile +++ b/arch/arm/mach-iop33x/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := common.o setup.o irq.o pci.o time.o +obj-y := setup.o irq.o time.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-iop33x/common.c b/arch/arm/mach-iop33x/common.c deleted file mode 100644 index dd75f2b8e74f..000000000000 --- a/arch/arm/mach-iop33x/common.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-iop33x/common.c - * - * Common routines shared across all IOP3xx implementations - * - * Author: Deepak Saxena - * - * Copyright 2003 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include - -/* - * Shared variables - */ -unsigned long iop3xx_pcibios_min_io = 0; -unsigned long iop3xx_pcibios_min_mem = 0; diff --git a/arch/arm/mach-iop33x/iq80331-pci.c b/arch/arm/mach-iop33x/iq80331-pci.c index 71adb12a9421..8b0bed5e2f91 100644 --- a/arch/arm/mach-iop33x/iq80331-pci.c +++ b/arch/arm/mach-iop33x/iq80331-pci.c @@ -57,51 +57,12 @@ iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) return PCI_IRQ_TABLE_LOOKUP(1, 7); } -static int iq80331_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - - if(nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res[0].start = IOP331_PCI_LOWER_IO_VA; - res[0].end = IOP331_PCI_UPPER_IO_VA; - res[0].name = "IQ80331 PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - - res[1].start = IOP331_PCI_LOWER_MEM_PA; - res[1].end = IOP331_PCI_UPPER_MEM_PA; - res[1].name = "IQ80331 PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); - - sys->mem_offset = IOP331_PCI_MEM_OFFSET; - sys->io_offset = IOP331_PCI_IO_OFFSET; - - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; - - return 1; -} - -static void iq80331_preinit(void) -{ - iop331_init(); -} - static struct hw_pci iq80331_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, - .setup = iq80331_setup, - .scan = iop331_scan_bus, - .preinit = iq80331_preinit, + .setup = iop3xx_pci_setup, + .scan = iop3xx_pci_scan_bus, + .preinit = iop3xx_pci_preinit, .map_irq = iq80331_map_irq }; diff --git a/arch/arm/mach-iop33x/iq80332-pci.c b/arch/arm/mach-iop33x/iq80332-pci.c index f3010f85b1a2..0de8aa748dd8 100644 --- a/arch/arm/mach-iop33x/iq80332-pci.c +++ b/arch/arm/mach-iop33x/iq80332-pci.c @@ -63,51 +63,12 @@ iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) return PCI_IRQ_TABLE_LOOKUP(1, 7); } -static int iq80332_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - - if(nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res[0].start = IOP331_PCI_LOWER_IO_VA; - res[0].end = IOP331_PCI_UPPER_IO_VA; - res[0].name = "IQ80332 PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - - res[1].start = IOP331_PCI_LOWER_MEM_PA; - res[1].end = IOP331_PCI_UPPER_MEM_PA; - res[1].name = "IQ80332 PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); - - sys->mem_offset = IOP331_PCI_MEM_OFFSET; - sys->io_offset = IOP331_PCI_IO_OFFSET; - - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; - - return 1; -} - -static void iq80332_preinit(void) -{ - iop331_init(); -} - static struct hw_pci iq80332_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, - .setup = iq80332_setup, - .scan = iop331_scan_bus, - .preinit = iq80332_preinit, + .setup = iop3xx_pci_setup, + .scan = iop3xx_pci_scan_bus, + .preinit = iop3xx_pci_preinit, .map_irq = iq80332_map_irq }; diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index 029fa78876a5..bcffc33a5be8 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -117,7 +117,7 @@ void __init iop331_init_irq(void) intstr_write0(0); // treat all as IRQ intstr_write1(0); if(machine_is_iq80331()) // all interrupts are inputs to chip - *IOP331_PCIIRSR = 0x0f; + *IOP3XX_PCIIRSR = 0x0f; for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++) { diff --git a/arch/arm/mach-iop33x/pci.c b/arch/arm/mach-iop33x/pci.c deleted file mode 100644 index bf6aba91b47d..000000000000 --- a/arch/arm/mach-iop33x/pci.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * arch/arm/mach-iop33x/pci.c - * - * PCI support for the Intel IOP331 chipset - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright (C) 2003, 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#undef DEBUG -#undef DEBUG1 - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) do { } while (0) -#endif - -#ifdef DEBUG1 -#define DBG1(x...) printk(x) -#else -#define DBG1(x...) do { } while (0) -#endif - -/* - * This routine builds either a type0 or type1 configuration command. If the - * bus is on the 80331 then a type0 made, else a type1 is created. - */ -static u32 iop331_cfg_address(struct pci_bus *bus, int devfn, int where) -{ - struct pci_sys_data *sys = bus->sysdata; - u32 addr; - - if (sys->busnr == bus->number) - addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); - else - addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; - - addr |= PCI_FUNC(devfn) << 8 | (where & ~3); - - return addr; -} - -/* - * This routine checks the status of the last configuration cycle. If an error - * was detected it returns a 1, else it returns a 0. The errors being checked - * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during - * the discovery stage. - */ -static int iop331_pci_status(void) -{ - unsigned int status; - int ret = 0; - - /* - * Check the status registers. - */ - status = *IOP331_ATUSR; - if (status & 0xf900) - { - DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); - *IOP331_ATUSR = status & 0xf900; - ret = 1; - } - status = *IOP331_ATUISR; - if (status & 0x679f) - { - DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); - *IOP331_ATUISR = status & 0x679f; - ret = 1; - } - return ret; -} - -/* - * Simply write the address register and read the configuration - * data. Note that the 4 nop's ensure that we are able to handle - * a delayed abort (in theory.) - */ -static inline u32 iop331_read(unsigned long addr) -{ - u32 val; - - __asm__ __volatile__( - "str %1, [%2]\n\t" - "ldr %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : "=r" (val) - : "r" (addr), "r" (IOP331_OCCAR), "r" (IOP331_OCCDR)); - - return val; -} - -/* - * The read routines must check the error status of the last configuration - * cycle. If there was an error, the routine returns all hex f's. - */ -static int -iop331_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - unsigned long addr = iop331_cfg_address(bus, devfn, where); - u32 val = iop331_read(addr) >> ((where & 3) * 8); - - if( iop331_pci_status() ) - val = 0xffffffff; - - *value = val; - - return PCIBIOS_SUCCESSFUL; -} - -static int -iop331_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - unsigned long addr = iop331_cfg_address(bus, devfn, where); - u32 val; - - if (size != 4) { - val = iop331_read(addr); - if (!iop331_pci_status() == 0) - return PCIBIOS_SUCCESSFUL; - - where = (where & 3) * 8; - - if (size == 1) - val &= ~(0xff << where); - else - val &= ~(0xffff << where); - - *IOP331_OCCDR = val | value << where; - } else { - asm volatile( - "str %1, [%2]\n\t" - "str %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : - : "r" (value), "r" (addr), - "r" (IOP331_OCCAR), "r" (IOP331_OCCDR)); - } - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops iop331_ops = { - .read = iop331_read_config, - .write = iop331_write_config, -}; - -/* - * When a PCI device does not exist during config cycles, the XScale gets a - * bus error instead of returning 0xffffffff. This handler simply returns. - */ -int -iop331_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", - addr, fsr, regs->ARM_pc, regs->ARM_lr); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -/* - * Scan an IOP331 PCI bus. sys->bus defines which bus we scan. - */ -struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_bus(sys->busnr, &iop331_ops, sys); -} - -void iop331_init(void) -{ - DBG1("PCI: Intel 80331 PCI init code.\n"); - DBG1("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD); - DBG1("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n", - *IOP331_OMWTVR0, - *IOP331_OIOWTVR); - DBG1("\tATU: IOP331_OMWTVR1=0x%04x\n", *IOP331_OMWTVR1); - DBG1("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR); - DBG1("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0); - DBG1("\tATU: IOP31_IABAR1=0x%08x IOP331_IALR1=0x%08x\n", *IOP331_IABAR1, *IOP331_IALR1); - DBG1("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR); - DBG1("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2); - DBG1("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3); - - hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort"); -} - diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h index 8fb10134a107..16d0630ab252 100644 --- a/include/asm-arm/arch-iop32x/hardware.h +++ b/include/asm-arm/arch-iop32x/hardware.h @@ -19,26 +19,10 @@ */ #define pcibios_assign_all_busses() 1 +#define PCIBIOS_MIN_IO 0x00000000 +#define PCIBIOS_MIN_MEM 0x00000000 -/* - * The min PCI I/O and MEM space are dependent on what specific - * chipset/platform we are running on, so instead of hardcoding with - * #ifdefs, we just fill these in the platform level PCI init code. - */ -#ifndef __ASSEMBLY__ -extern unsigned long iop3xx_pcibios_min_io; -extern unsigned long iop3xx_pcibios_min_mem; - -extern unsigned int processor_id; -#endif - -/* - * We just set these to zero since they are really bogus anyways - */ -#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io) -#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem) - /* * Generic chipset bits * diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h index 1a82dd96bf50..e3c85a05e73a 100644 --- a/include/asm-arm/arch-iop32x/iop321.h +++ b/include/asm-arm/arch-iop32x/iop321.h @@ -24,27 +24,6 @@ #define iop_is_321() 1 #endif -/* - * IOP321 I/O and Mem space regions for PCI autoconfiguration - */ -#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000 -#define IOP321_PCI_LOWER_IO_PA 0x90000000 -#define IOP321_PCI_LOWER_IO_VA 0xfe000000 -#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR) -#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1) -#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1) -#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1) -#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA) - -/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */ -#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ -#define IOP321_PCI_LOWER_MEM_PA 0x80000000 -#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0) -#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1) -#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1) -#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA) - - /* * IOP321 chipset registers */ @@ -55,69 +34,6 @@ /* Reserved 0x00000000 through 0x000000FF */ /* Address Translation Unit 0x00000100 through 0x000001FF */ -#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100) -#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102) -#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104) -#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106) -#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108) -#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109) -#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C) -#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D) -#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E) -#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F) -#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110) -#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114) -#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118) -#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C) -#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120) -#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124) -#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C) -#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E) -#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130) -/* Reserved 0x00000134 through 0x0000013B */ -#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C) -#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D) -#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E) -#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F) -#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140) -#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144) -#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148) -#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C) -#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150) -#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154) -#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158) -#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C) -#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160) -#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164) -#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168) -#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C) -/* Reserved 0x00000170 through 0x00000177*/ -#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178) -/* Reserved 0x0000017C through 0x0000017F*/ -#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180) -#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184) -#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188) -#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C) -#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190) -#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194) -#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198) -#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C) -/* Reserved 0x000001A0 through 0x000001A3*/ -#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4) -/* Reserved 0x000001A8 through 0x000001AB*/ -#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC) -/* Reserved 0x000001B0 through 0x000001BB*/ -#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC) -#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0) -#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1) -#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2) -#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4) -/* Reserved 0x000001C6 through 0x000001DF */ -#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0) -#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1) -#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2) -#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4) -#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC) /* Messaging Unit 0x00000300 through 0x000003FF */ @@ -317,6 +233,8 @@ /* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ +#include + #ifndef __ASSEMBLY__ extern void iop321_init_irq(void); diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h index b4073f15b405..4c64d9e7229b 100644 --- a/include/asm-arm/arch-iop32x/memory.h +++ b/include/asm-arm/arch-iop32x/memory.h @@ -20,8 +20,8 @@ * to an address that the kernel can use. */ -#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0)) -#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2))) +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2))) #endif diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h index d4c8d691e1b0..1ac207a0d52e 100644 --- a/include/asm-arm/arch-iop32x/system.h +++ b/include/asm-arm/arch-iop32x/system.h @@ -16,7 +16,7 @@ static inline void arch_idle(void) static inline void arch_reset(char mode) { - *IOP321_PCSR = 0x30; + *IOP3XX_PCSR = 0x30; if ( 1 && mode == 's') { /* Jump into ROM at address 0 */ diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h index 4a457084c5c6..5e3cb32af020 100644 --- a/include/asm-arm/arch-iop33x/hardware.h +++ b/include/asm-arm/arch-iop33x/hardware.h @@ -19,26 +19,10 @@ */ #define pcibios_assign_all_busses() 1 +#define PCIBIOS_MIN_IO 0x00000000 +#define PCIBIOS_MIN_MEM 0x00000000 -/* - * The min PCI I/O and MEM space are dependent on what specific - * chipset/platform we are running on, so instead of hardcoding with - * #ifdefs, we just fill these in the platform level PCI init code. - */ -#ifndef __ASSEMBLY__ -extern unsigned long iop3xx_pcibios_min_io; -extern unsigned long iop3xx_pcibios_min_mem; - -extern unsigned int processor_id; -#endif - -/* - * We just set these to zero since they are really bogus anyways - */ -#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io) -#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem) - /* * Generic chipset bits * diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h index a7f47122c5e1..e85e1a2e1a86 100644 --- a/include/asm-arm/arch-iop33x/iop331.h +++ b/include/asm-arm/arch-iop33x/iop331.h @@ -23,27 +23,6 @@ #define iop_is_331() 1 #endif -/* - * IOP331 I/O and Mem space regions for PCI autoconfiguration - */ -#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000 -#define IOP331_PCI_LOWER_IO_PA 0x90000000 -#define IOP331_PCI_LOWER_IO_VA 0xfe000000 -#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR) -#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1) -#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1) -#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1) -#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA) - -/* this can be 128M if OMWTVR1 is set */ -#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ -/* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */ -#define IOP331_PCI_LOWER_MEM_PA 0x80000000 -#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0) -#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1) -#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1) -#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA) - /* * IOP331 chipset registers */ @@ -54,79 +33,6 @@ /* Reserved 0x00000000 through 0x000000FF */ /* Address Translation Unit 0x00000100 through 0x000001FF */ -#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100) -#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102) -#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104) -#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106) -#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108) -#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109) -#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C) -#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D) -#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E) -#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F) -#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110) -#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114) -#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118) -#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C) -#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120) -#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124) -#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C) -#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E) -#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130) -#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134) -/* Reserved 0x00000138 through 0x0000013B */ -#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C) -#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D) -#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E) -#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F) -#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140) -#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144) -#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148) -#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C) -#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150) -#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154) -#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158) -#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C) -#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160) -#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164) -#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168) -#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C) -/* Reserved 0x00000170 through 0x00000177*/ -#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178) -/* Reserved 0x0000017C through 0x0000017F*/ -#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180) -#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184) -#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188) -#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C) -#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190) -#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194) -#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198) -#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C) -/* Reserved 0x000001A0 through 0x000001A3*/ -#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4) -/* Reserved 0x000001A8 through 0x000001AB*/ -#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC) -/* Reserved 0x000001B0 through 0x000001BB*/ -#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8) -#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9) -#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA) -#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC) -#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0) -#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1) -#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2) -#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4) -/* Reserved 0x000001C6 through 0x000001CF */ -#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0) -#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1) -#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2) -#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4) -#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8) -#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC) -#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0) -#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1) -#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2) -#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4) -#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC) /* Messaging Unit 0x00000300 through 0x000003FF */ @@ -332,6 +238,8 @@ /* Reserved 0x0000178c through 0x000019ff */ +#include + #ifndef __ASSEMBLY__ extern void iop331_init_irq(void); diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h index 5e47164934ce..de208d2cca4e 100644 --- a/include/asm-arm/arch-iop33x/memory.h +++ b/include/asm-arm/arch-iop33x/memory.h @@ -19,8 +19,8 @@ * bus_to_virt: Used to convert an address for DMA operations * to an address that the kernel can use. */ -#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0)) -#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2))) +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2))) #endif diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h index 43cc787ea629..8270ad9f86c8 100644 --- a/include/asm-arm/arch-iop33x/system.h +++ b/include/asm-arm/arch-iop33x/system.h @@ -16,7 +16,7 @@ static inline void arch_idle(void) static inline void arch_reset(char mode) { - *IOP331_PCSR = 0x30; + *IOP3XX_PCSR = 0x30; if ( 1 && mode == 's') { /* Jump into ROM at address 0 */ diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h index cb41defad4a1..24621c49a0c7 100644 --- a/include/asm-arm/mach/pci.h +++ b/include/asm-arm/mach/pci.h @@ -56,14 +56,6 @@ extern int iop3xx_pci_setup(int nr, struct pci_sys_data *); extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); extern void iop3xx_pci_preinit(void); -extern int iop321_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *); -extern void iop321_init(void); - -extern int iop331_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *); -extern void iop331_init(void); - extern int dc21285_setup(int nr, struct pci_sys_data *); extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); extern void dc21285_preinit(void); -- cgit v1.2.3 From 48388b2a56ae5e0f1c422e84d536f31729469b17 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:18:16 +0100 Subject: [ARM] 3822/1: iop3xx: rewrite time handling Merge and rewrite the iop32x/iop33x time code to do lost jiffy tracking properly, and put the result in plat-iop/time.c. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/plat-iop/Makefile | 2 +- arch/arm/plat-iop/time.c | 94 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-iop32x/iop321.h | 6 +++ include/asm-arm/arch-iop33x/iop331.h | 6 +++ include/asm-arm/hardware/iop3xx.h | 20 ++++++++ 5 files changed, 127 insertions(+), 1 deletion(-) create mode 100644 arch/arm/plat-iop/time.c (limited to 'include') diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile index efde7a513fb7..d20cdec3a944 100644 --- a/arch/arm/plat-iop/Makefile +++ b/arch/arm/plat-iop/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := i2c.o pci.o setup.o +obj-y := i2c.o pci.o setup.o time.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c new file mode 100644 index 000000000000..5730a0d7ed67 --- /dev/null +++ b/arch/arm/plat-iop/time.c @@ -0,0 +1,94 @@ +/* + * arch/arm/plat-iop/time.c + * + * Timer code for IOP32x and IOP33x based systems + * + * Author: Deepak Saxena + * + * Copyright 2002-2003 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ARCH_IOP32X +#define IRQ_IOP3XX_TIMER0 IRQ_IOP321_TIMER0 +#else +#ifdef CONFIG_ARCH_IOP33X +#define IRQ_IOP3XX_TIMER0 IRQ_IOP331_TIMER0 +#endif +#endif + +static unsigned long ticks_per_jiffy; +static unsigned long ticks_per_usec; +static unsigned long next_jiffy_time; + +unsigned long iop3xx_gettimeoffset(void) +{ + unsigned long offset; + + offset = next_jiffy_time - *IOP3XX_TU_TCR1; + + return offset / ticks_per_usec; +} + +static irqreturn_t +iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + write_seqlock(&xtime_lock); + + asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1)); + + while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) + >= ticks_per_jiffy) { + timer_tick(regs); + next_jiffy_time -= ticks_per_jiffy; + } + + write_sequnlock(&xtime_lock); + + return IRQ_HANDLED; +} + +static struct irqaction iop3xx_timer_irq = { + .name = "IOP3XX Timer Tick", + .handler = iop3xx_timer_interrupt, + .flags = IRQF_DISABLED | IRQF_TIMER, +}; + +void __init iop3xx_init_time(unsigned long tick_rate) +{ + u32 timer_ctl; + + ticks_per_jiffy = (tick_rate + HZ/2) / HZ; + ticks_per_usec = tick_rate / 1000000; + next_jiffy_time = 0xffffffff; + + timer_ctl = IOP3XX_TMR_EN | IOP3XX_TMR_PRIVILEGED | + IOP3XX_TMR_RELOAD | IOP3XX_TMR_RATIO_1_1; + + /* + * We use timer 0 for our timer interrupt, and timer 1 as + * monotonic counter for tracking missed jiffies. + */ + asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); + asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); + asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); + asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); + + setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq); +} diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h index e3c85a05e73a..bd96b8d55a76 100644 --- a/include/asm-arm/arch-iop32x/iop321.h +++ b/include/asm-arm/arch-iop32x/iop321.h @@ -233,6 +233,12 @@ /* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ +/* + * Peripherals that are shared between the iop32x and iop33x but + * located at different addresses. + */ +#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) + #include diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h index e85e1a2e1a86..b301ef8f7f32 100644 --- a/include/asm-arm/arch-iop33x/iop331.h +++ b/include/asm-arm/arch-iop33x/iop331.h @@ -238,6 +238,12 @@ /* Reserved 0x0000178c through 0x000019ff */ +/* + * Peripherals that are shared between the iop32x and iop33x but + * located at different addresses. + */ +#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg)) + #include diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index d488ced2e12d..b21ea41b149e 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -81,6 +81,24 @@ #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) +/* Timers */ +#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000) +#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004) +#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008) +#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c) +#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010) +#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) +#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) +#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) +#define IOP3XX_TMR_TC 0x01 +#define IOP3XX_TMR_EN 0x02 +#define IOP3XX_TMR_RELOAD 0x04 +#define IOP3XX_TMR_PRIVILEGED 0x09 +#define IOP3XX_TMR_RATIO_1_1 0x00 +#define IOP3XX_TMR_RATIO_4_1 0x10 +#define IOP3XX_TMR_RATIO_8_1 0x20 +#define IOP3XX_TMR_RATIO_16_1 0x30 + /* I2C bus interface unit */ #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) @@ -109,6 +127,8 @@ #ifndef __ASSEMBLY__ void iop3xx_map_io(void); +void iop3xx_init_time(unsigned long); +unsigned long iop3xx_gettimeoffset(void); extern struct platform_device iop3xx_i2c0_device; extern struct platform_device iop3xx_i2c1_device; -- cgit v1.2.3 From 863753a81e4f863015be34900dc2ba3637622f34 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:19:02 +0100 Subject: [ARM] 3823/1: iop3xx: switch iop32x/iop33x over to shared time code Switch the iop32x and iop33x code over to the common time implementation, and remove the (nearly identical) iop32x and iop33x time implementations. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/Makefile | 2 +- arch/arm/mach-iop32x/setup.c | 15 +++-- arch/arm/mach-iop32x/time.c | 108 ----------------------------------- arch/arm/mach-iop33x/Makefile | 2 +- arch/arm/mach-iop33x/setup.c | 12 +++- arch/arm/mach-iop33x/time.c | 106 ---------------------------------- include/asm-arm/arch-iop32x/iop321.h | 21 ------- include/asm-arm/arch-iop32x/timex.h | 2 +- include/asm-arm/arch-iop33x/iop331.h | 21 ------- include/asm-arm/arch-iop33x/timex.h | 2 +- 10 files changed, 26 insertions(+), 265 deletions(-) delete mode 100644 arch/arm/mach-iop32x/time.c delete mode 100644 arch/arm/mach-iop33x/time.c (limited to 'include') diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile index 7266224ab6d7..ef561db20c9b 100644 --- a/arch/arm/mach-iop32x/Makefile +++ b/arch/arm/mach-iop32x/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := common.o setup.o irq.o time.o +obj-y := common.o setup.o irq.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c index 1a03b0b41baa..68de247a4cca 100644 --- a/arch/arm/mach-iop32x/setup.c +++ b/arch/arm/mach-iop32x/setup.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #define IOP321_UART_XTAL 1843200 @@ -67,16 +68,22 @@ void __init iop32x_init(void) #ifdef CONFIG_ARCH_IQ80321 extern void iq80321_map_io(void); -extern struct sys_timer iop321_timer; -extern void iop321_init_time(void); #endif #ifdef CONFIG_ARCH_IQ31244 extern void iq31244_map_io(void); -extern struct sys_timer iop321_timer; -extern void iop321_init_time(void); #endif +static void __init iop3xx_timer_init(void) +{ + iop3xx_init_time(IOP321_TICK_RATE); +} + +struct sys_timer iop321_timer = { + .init = iop3xx_timer_init, + .offset = iop3xx_gettimeoffset, +}; + #if defined(CONFIG_ARCH_IQ80321) MACHINE_START(IQ80321, "Intel IQ80321") /* Maintainer: Intel Corporation */ diff --git a/arch/arm/mach-iop32x/time.c b/arch/arm/mach-iop32x/time.c deleted file mode 100644 index 3cabbbca0a02..000000000000 --- a/arch/arm/mach-iop32x/time.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * arch/arm/mach-iop32x/time.c - * - * Timer code for IOP321 based systems - * - * Author: Deepak Saxena - * - * Copyright 2002-2003 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define IOP321_TIME_SYNC 0 - -static inline unsigned long get_elapsed(void) -{ - return LATCH - *IOP321_TU_TCR0; -} - -static unsigned long iop321_gettimeoffset(void) -{ - unsigned long elapsed, usec; - u32 tisr1, tisr2; - - /* - * If an interrupt was pending before we read the timer, - * we've already wrapped. Factor this into the time. - * If an interrupt was pending after we read the timer, - * it may have wrapped between checking the interrupt - * status and reading the timer. Re-read the timer to - * be sure its value is after the wrap. - */ - - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr1)); - elapsed = get_elapsed(); - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr2)); - - if(tisr1 & 1) - elapsed += LATCH; - else if (tisr2 & 1) - elapsed = LATCH + get_elapsed(); - - /* - * Now convert them to usec. - */ - usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000)); - - return usec; -} - -static irqreturn_t -iop321_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - u32 tisr; - - write_seqlock(&xtime_lock); - - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr)); - tisr |= 1; - asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr)); - - timer_tick(regs); - - write_sequnlock(&xtime_lock); - - return IRQ_HANDLED; -} - -static struct irqaction iop321_timer_irq = { - .name = "IOP321 Timer Tick", - .handler = iop321_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER, -}; - -static void __init iop321_timer_init(void) -{ - u32 timer_ctl; - - setup_irq(IRQ_IOP321_TIMER0, &iop321_timer_irq); - - timer_ctl = IOP321_TMR_EN | IOP321_TMR_PRIVILEGED | IOP321_TMR_RELOAD | - IOP321_TMR_RATIO_1_1; - - asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (LATCH)); - - asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); -} - -struct sys_timer iop321_timer = { - .init = &iop321_timer_init, - .offset = iop321_gettimeoffset, -}; diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile index 6c74f13b1139..f825cee57d9f 100644 --- a/arch/arm/mach-iop33x/Makefile +++ b/arch/arm/mach-iop33x/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := setup.o irq.o time.o +obj-y := setup.o irq.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-iop33x/setup.c b/arch/arm/mach-iop33x/setup.c index ad737d6582b5..7cf5015436f3 100644 --- a/arch/arm/mach-iop33x/setup.c +++ b/arch/arm/mach-iop33x/setup.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #define IOP331_UART_XTAL 33334000 @@ -118,9 +119,18 @@ void __init iop33x_init(void) #ifdef CONFIG_ARCH_IOP33X extern void iop331_init_irq(void); -extern struct sys_timer iop331_timer; #endif +static void __init iop3xx_timer_init(void) +{ + iop3xx_init_time(IOP331_TICK_RATE); +} + +struct sys_timer iop331_timer = { + .init = iop3xx_timer_init, + .offset = iop3xx_gettimeoffset, +}; + #if defined(CONFIG_ARCH_IQ80331) MACHINE_START(IQ80331, "Intel IQ80331") /* Maintainer: Intel Corp. */ diff --git a/arch/arm/mach-iop33x/time.c b/arch/arm/mach-iop33x/time.c deleted file mode 100644 index d839cd0d926e..000000000000 --- a/arch/arm/mach-iop33x/time.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * arch/arm/mach-iop33x/time.c - * - * Timer code for IOP331 based systems - * - * Author: Dave Jiang - * - * Copyright 2003 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -static inline unsigned long get_elapsed(void) -{ - return LATCH - *IOP331_TU_TCR0; -} - -static unsigned long iop331_gettimeoffset(void) -{ - unsigned long elapsed, usec; - u32 tisr1, tisr2; - - /* - * If an interrupt was pending before we read the timer, - * we've already wrapped. Factor this into the time. - * If an interrupt was pending after we read the timer, - * it may have wrapped between checking the interrupt - * status and reading the timer. Re-read the timer to - * be sure its value is after the wrap. - */ - - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr1)); - elapsed = get_elapsed(); - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr2)); - - if(tisr1 & 1) - elapsed += LATCH; - else if (tisr2 & 1) - elapsed = LATCH + get_elapsed(); - - /* - * Now convert them to usec. - */ - usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000)); - - return usec; -} - -static irqreturn_t -iop331_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - u32 tisr; - - write_seqlock(&xtime_lock); - - asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr)); - tisr |= 1; - asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr)); - - timer_tick(regs); - - write_sequnlock(&xtime_lock); - return IRQ_HANDLED; -} - -static struct irqaction iop331_timer_irq = { - .name = "IOP331 Timer Tick", - .handler = iop331_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER, -}; - -static void __init iop331_timer_init(void) -{ - u32 timer_ctl; - - setup_irq(IRQ_IOP331_TIMER0, &iop331_timer_irq); - - timer_ctl = IOP331_TMR_EN | IOP331_TMR_PRIVILEGED | IOP331_TMR_RELOAD | - IOP331_TMR_RATIO_1_1; - - asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (LATCH)); - - asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); - -} - -struct sys_timer iop331_timer = { - .init = iop331_timer_init, - .offset = iop331_gettimeoffset, -}; diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h index bd96b8d55a76..34fe07f0a44e 100644 --- a/include/asm-arm/arch-iop32x/iop321.h +++ b/include/asm-arm/arch-iop32x/iop321.h @@ -151,10 +151,6 @@ #define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) /* Timers */ - -#define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0) -#define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4) - #ifdef CONFIG_ARCH_IQ80321 #define IOP321_TICK_RATE 200000000 /* 200 MHz clock */ #elif defined(CONFIG_ARCH_IQ31244) @@ -166,23 +162,6 @@ #define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */ #endif -#define IOP321_TMR_TC 0x01 -#define IOP321_TMR_EN 0x02 -#define IOP321_TMR_RELOAD 0x04 -#define IOP321_TMR_PRIVILEGED 0x09 - -#define IOP321_TMR_RATIO_1_1 0x00 -#define IOP321_TMR_RATIO_4_1 0x10 -#define IOP321_TMR_RATIO_8_1 0x20 -#define IOP321_TMR_RATIO_16_1 0x30 - -#define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8) -#define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC) -#define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0) -#define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4) -#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8) -#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC) - /* Application accelerator unit 0x00000800 - 0x000008FF */ #define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800) #define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804) diff --git a/include/asm-arm/arch-iop32x/timex.h b/include/asm-arm/arch-iop32x/timex.h index 08badde2e820..328f37282c3e 100644 --- a/include/asm-arm/arch-iop32x/timex.h +++ b/include/asm-arm/arch-iop32x/timex.h @@ -5,4 +5,4 @@ */ #include -#define CLOCK_TICK_RATE IOP321_TICK_RATE +#define CLOCK_TICK_RATE (100 * HZ) diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h index b301ef8f7f32..4ebcd7197c86 100644 --- a/include/asm-arm/arch-iop33x/iop331.h +++ b/include/asm-arm/arch-iop33x/iop331.h @@ -137,27 +137,6 @@ /* Timers */ - -#define IOP331_TU_TMR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D0) -#define IOP331_TU_TMR1 (volatile u32 *)IOP331_REG_ADDR(0x000007D4) - -#define IOP331_TMR_TC 0x01 -#define IOP331_TMR_EN 0x02 -#define IOP331_TMR_RELOAD 0x04 -#define IOP331_TMR_PRIVILEGED 0x09 - -#define IOP331_TMR_RATIO_1_1 0x00 -#define IOP331_TMR_RATIO_4_1 0x10 -#define IOP331_TMR_RATIO_8_1 0x20 -#define IOP331_TMR_RATIO_16_1 0x30 - -#define IOP331_TU_TCR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D8) -#define IOP331_TU_TCR1 (volatile u32 *)IOP331_REG_ADDR(0x000007DC) -#define IOP331_TU_TRR0 (volatile u32 *)IOP331_REG_ADDR(0x000007E0) -#define IOP331_TU_TRR1 (volatile u32 *)IOP331_REG_ADDR(0x000007E4) -#define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8) -#define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC) - #if defined(CONFIG_ARCH_IOP33X) #define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */ #endif diff --git a/include/asm-arm/arch-iop33x/timex.h b/include/asm-arm/arch-iop33x/timex.h index cc8085fa2a1e..8994322a09f4 100644 --- a/include/asm-arm/arch-iop33x/timex.h +++ b/include/asm-arm/arch-iop33x/timex.h @@ -5,4 +5,4 @@ */ #include -#define CLOCK_TICK_RATE IOP331_TICK_RATE +#define CLOCK_TICK_RATE (100 * HZ) -- cgit v1.2.3 From 0b29de4a6ac0936f56b974a3c19bd9c24ac5b5d7 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:20:55 +0100 Subject: [ARM] 3824/1: iop3xx: add cp6 enable/disable macros Add macros to enable and disable access to CP6. On the iop3xx, enabling CP6 access unfortunately also enables access to that coprocessor from unprivileged code, so we need these macros to enable and disable access to the coprocessor whenever we need to access it. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/hardware/iop3xx.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'include') diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index b21ea41b149e..98b7cbc405e6 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -132,6 +132,34 @@ unsigned long iop3xx_gettimeoffset(void); extern struct platform_device iop3xx_i2c0_device; extern struct platform_device iop3xx_i2c1_device; + +extern inline void iop3xx_cp6_enable(void) +{ + u32 temp; + + asm volatile ( + "mrc p15, 0, %0, c15, c1, 0\n\t" + "orr %0, %0, #(1 << 6)\n\t" + "mcr p15, 0, %0, c15, c1, 0\n\t" + "mrc p15, 0, %0, c15, c1, 0\n\t" + "mov %0, %0\n\t" + "sub pc, pc, #4\n\t" + : "=r" (temp) ); +} + +extern inline void iop3xx_cp6_disable(void) +{ + u32 temp; + + asm volatile ( + "mrc p15, 0, %0, c15, c1, 0\n\t" + "bic %0, %0, #(1 << 6)\n\t" + "mcr p15, 0, %0, c15, c1, 0\n\t" + "mrc p15, 0, %0, c15, c1, 0\n\t" + "mov %0, %0\n\t" + "sub pc, pc, #4\n\t" + : "=r" (temp) ); +} #endif -- cgit v1.2.3 From 38ce73ebd74a9a1738b73619557f2397c59ba628 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:21:38 +0100 Subject: [ARM] 3825/1: iop3xx: use cp6 enable/disable macros Add CP6 enable/disable sequences to the timekeeping code and the IRQ code. As a result, we can't depend on CP6 access being enabled when we enter get_irqnr_and_base anymore, so switch the latter over to using memory-mapped accesses for now. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/irq.c | 23 +++++------------------ arch/arm/mach-iop33x/irq.c | 27 +++++++++------------------ arch/arm/plat-iop/time.c | 4 ++++ include/asm-arm/arch-iop32x/entry-macro.S | 3 ++- include/asm-arm/arch-iop33x/entry-macro.S | 5 +++-- 5 files changed, 23 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 76f2d561dbc1..cdd6943ce768 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -27,12 +27,16 @@ static u32 iop321_mask /* = 0 */; static inline void intctl_write(u32 val) { + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static inline void intstr_write(u32 val) { + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static void @@ -61,24 +65,7 @@ struct irq_chip ext_chip = { void __init iop321_init_irq(void) { - unsigned int i, tmp; - - /* Enable access to coprocessor 6 for dealing with IRQs. - * From RMK: - * Basically, the Intel documentation here is poor. It appears that - * you need to set the bit to be able to access the coprocessor from - * SVC mode. Whether that allows access from user space or not is - * unclear. - */ - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, %1\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - /* The action is delayed, so we have to do this: */ - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4" - : "=r" (tmp) : "i" (1 << 6) ); + unsigned int i; intctl_write(0); // disable all interrupts intstr_write(0); // treat all as IRQ diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index bcffc33a5be8..d667439c8573 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -28,25 +28,33 @@ static u32 iop331_mask1 = 0; static inline void intctl_write0(u32 val) { // INTCTL0 + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static inline void intctl_write1(u32 val) { // INTCTL1 + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static inline void intstr_write0(u32 val) { // INTSTR0 + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static inline void intstr_write1(u32 val) { // INTSTR1 + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static void @@ -93,24 +101,7 @@ struct irq_chip iop331_irqchip2 = { void __init iop331_init_irq(void) { - unsigned int i, tmp; - - /* Enable access to coprocessor 6 for dealing with IRQs. - * From RMK: - * Basically, the Intel documentation here is poor. It appears that - * you need to set the bit to be able to access the coprocessor from - * SVC mode. Whether that allows access from user space or not is - * unclear. - */ - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, %1\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - /* The action is delayed, so we have to do this: */ - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4" - : "=r" (tmp) : "i" (1 << 6) ); + unsigned int i; intctl_write0(0); // disable all interrupts intctl_write1(0); diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 5730a0d7ed67..bed20f3669f4 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -51,7 +51,9 @@ iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { write_seqlock(&xtime_lock); + iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1)); + iop3xx_cp6_disable(); while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) >= ticks_per_jiffy) { @@ -85,10 +87,12 @@ void __init iop3xx_init_time(unsigned long tick_rate) * We use timer 0 for our timer interrupt, and timer 1 as * monotonic counter for tracking missed jiffies. */ + iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); + iop3xx_cp6_disable(); setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq); } diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S index 52d9435c6a34..00038c17317a 100644 --- a/include/asm-arm/arch-iop32x/entry-macro.S +++ b/include/asm-arm/arch-iop32x/entry-macro.S @@ -17,7 +17,8 @@ */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov \irqnr, #0 - mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC + ldr \base, =IOP3XX_REG_ADDR(0x07D8) + ldr \irqstat, [\base] @ Read IINTSRC cmp \irqstat, #0 beq 1001f clz \irqnr, \irqstat diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S index 980ec9b1ac83..57f6ea0069e4 100644 --- a/include/asm-arm/arch-iop33x/entry-macro.S +++ b/include/asm-arm/arch-iop33x/entry-macro.S @@ -17,10 +17,11 @@ */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov \irqnr, #0 - mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0 + ldr \base, =IOP3XX_REG_ADDR(0x7A0) + ldr \irqstat, [\base] @ Read IINTSRC0 cmp \irqstat, #0 bne 1002f - mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1 + ldr \irqstat, [\base, #4] @ Read IINTSRC1 cmp \irqstat, #0 beq 1001f clz \irqnr, \irqstat -- cgit v1.2.3 From 610300e8f4f833904096ca1233ffd9dbd73fb11f Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:22:24 +0100 Subject: [ARM] 3826/1: iop3xx: remove IOP3??_IRQ_OFS irq offset Get rid of the unused IOP3??_IRQ_OFS irq offset define, start IRQ numbering from zero. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/irq.c | 6 +- arch/arm/mach-iop33x/irq.c | 10 +-- include/asm-arm/arch-iop32x/entry-macro.S | 1 - include/asm-arm/arch-iop32x/irqs.h | 68 ++++++++---------- include/asm-arm/arch-iop33x/entry-macro.S | 1 - include/asm-arm/arch-iop33x/irqs.h | 110 +++++++++++------------------- 6 files changed, 76 insertions(+), 120 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index cdd6943ce768..ff049e02f5f7 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -43,7 +43,7 @@ static void iop321_irq_mask (unsigned int irq) { - iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS)); + iop321_mask &= ~(1 << irq); intctl_write(iop321_mask); } @@ -51,7 +51,7 @@ iop321_irq_mask (unsigned int irq) static void iop321_irq_unmask (unsigned int irq) { - iop321_mask |= (1 << (irq - IOP321_IRQ_OFS)); + iop321_mask |= (1 << irq); intctl_write(iop321_mask); } @@ -73,7 +73,7 @@ void __init iop321_init_irq(void) machine_is_iq31244()) // all interrupts are inputs to chip *IOP3XX_PCIIRSR = 0x0f; - for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++) + for(i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &ext_chip); set_irq_handler(i, do_level_IRQ); diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index d667439c8573..675ed3989973 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -60,28 +60,28 @@ static inline void intstr_write1(u32 val) static void iop331_irq_mask1 (unsigned int irq) { - iop331_mask0 &= ~(1 << (irq - IOP331_IRQ_OFS)); + iop331_mask0 &= ~(1 << irq); intctl_write0(iop331_mask0); } static void iop331_irq_mask2 (unsigned int irq) { - iop331_mask1 &= ~(1 << (irq - IOP331_IRQ_OFS - 32)); + iop331_mask1 &= ~(1 << (irq - 32)); intctl_write1(iop331_mask1); } static void iop331_irq_unmask1(unsigned int irq) { - iop331_mask0 |= (1 << (irq - IOP331_IRQ_OFS)); + iop331_mask0 |= (1 << irq); intctl_write0(iop331_mask0); } static void iop331_irq_unmask2(unsigned int irq) { - iop331_mask1 |= (1 << (irq - IOP331_IRQ_OFS - 32)); + iop331_mask1 |= (1 << (irq - 32)); intctl_write1(iop331_mask1); } @@ -110,7 +110,7 @@ void __init iop331_init_irq(void) if(machine_is_iq80331()) // all interrupts are inputs to chip *IOP3XX_PCIIRSR = 0x0f; - for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++) + for(i = 0; i < NR_IRQS; i++) { set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2); set_irq_handler(i, do_level_IRQ); diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S index 00038c17317a..c5ec1e23cbea 100644 --- a/include/asm-arm/arch-iop32x/entry-macro.S +++ b/include/asm-arm/arch-iop32x/entry-macro.S @@ -24,6 +24,5 @@ clz \irqnr, \irqstat mov \base, #31 subs \irqnr,\base,\irqnr - add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT 1001: .endm diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h index 4b0c82711f96..9fefcf3372b1 100644 --- a/include/asm-arm/arch-iop32x/irqs.h +++ b/include/asm-arm/arch-iop32x/irqs.h @@ -15,46 +15,36 @@ /* * IOP80321 chipset interrupts */ -#define IOP321_IRQ_OFS 0 -#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x)) +#define IRQ_IOP321_DMA0_EOT 0 +#define IRQ_IOP321_DMA0_EOC 1 +#define IRQ_IOP321_DMA1_EOT 2 +#define IRQ_IOP321_DMA1_EOC 3 +#define IRQ_IOP321_AA_EOT 6 +#define IRQ_IOP321_AA_EOC 7 +#define IRQ_IOP321_CORE_PMON 8 +#define IRQ_IOP321_TIMER0 9 +#define IRQ_IOP321_TIMER1 10 +#define IRQ_IOP321_I2C_0 11 +#define IRQ_IOP321_I2C_1 12 +#define IRQ_IOP321_MESSAGING 13 +#define IRQ_IOP321_ATU_BIST 14 +#define IRQ_IOP321_PERFMON 15 +#define IRQ_IOP321_CORE_PMU 16 +#define IRQ_IOP321_BIU_ERR 17 +#define IRQ_IOP321_ATU_ERR 18 +#define IRQ_IOP321_MCU_ERR 19 +#define IRQ_IOP321_DMA0_ERR 20 +#define IRQ_IOP321_DMA1_ERR 21 +#define IRQ_IOP321_AA_ERR 23 +#define IRQ_IOP321_MSG_ERR 24 +#define IRQ_IOP321_SSP 25 +#define IRQ_IOP321_XINT0 27 +#define IRQ_IOP321_XINT1 28 +#define IRQ_IOP321_XINT2 29 +#define IRQ_IOP321_XINT3 30 +#define IRQ_IOP321_HPI 31 -/* - * On IRQ or FIQ register - */ -#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0) -#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1) -#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2) -#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3) -#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4) -#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5) -#define IRQ_IOP321_AA_EOT IOP321_IRQ(6) -#define IRQ_IOP321_AA_EOC IOP321_IRQ(7) -#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8) -#define IRQ_IOP321_TIMER0 IOP321_IRQ(9) -#define IRQ_IOP321_TIMER1 IOP321_IRQ(10) -#define IRQ_IOP321_I2C_0 IOP321_IRQ(11) -#define IRQ_IOP321_I2C_1 IOP321_IRQ(12) -#define IRQ_IOP321_MESSAGING IOP321_IRQ(13) -#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14) -#define IRQ_IOP321_PERFMON IOP321_IRQ(15) -#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16) -#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17) -#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18) -#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19) -#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20) -#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21) -#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22) -#define IRQ_IOP321_AA_ERR IOP321_IRQ(23) -#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24) -#define IRQ_IOP321_SSP IOP321_IRQ(25) -#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26) -#define IRQ_IOP321_XINT0 IOP321_IRQ(27) -#define IRQ_IOP321_XINT1 IOP321_IRQ(28) -#define IRQ_IOP321_XINT2 IOP321_IRQ(29) -#define IRQ_IOP321_XINT3 IOP321_IRQ(30) -#define IRQ_IOP321_HPI IOP321_IRQ(31) - -#define NR_IRQS (IOP321_IRQ(31) + 1) +#define NR_IRQS 32 /* diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S index 57f6ea0069e4..425aa7aafa0e 100644 --- a/include/asm-arm/arch-iop33x/entry-macro.S +++ b/include/asm-arm/arch-iop33x/entry-macro.S @@ -30,6 +30,5 @@ b 1001f 1002: clz \irqnr, \irqstat rsbs \irqnr,\irqnr,#31 @ recommend by RMK - add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT 1001: .endm diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h index 45856a12815a..2e3ade3b5ff9 100644 --- a/include/asm-arm/arch-iop33x/irqs.h +++ b/include/asm-arm/arch-iop33x/irqs.h @@ -15,78 +15,46 @@ /* * IOP80331 chipset interrupts */ -#define IOP331_IRQ_OFS 0 -#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x)) +#define IRQ_IOP331_DMA0_EOT 0 +#define IRQ_IOP331_DMA0_EOC 1 +#define IRQ_IOP331_DMA1_EOT 2 +#define IRQ_IOP331_DMA1_EOC 3 +#define IRQ_IOP331_AA_EOT 6 +#define IRQ_IOP331_AA_EOC 7 +#define IRQ_IOP331_TIMER0 8 +#define IRQ_IOP331_TIMER1 9 +#define IRQ_IOP331_I2C_0 10 +#define IRQ_IOP331_I2C_1 11 +#define IRQ_IOP331_MSG 12 +#define IRQ_IOP331_MSGIBQ 13 +#define IRQ_IOP331_ATU_BIST 14 +#define IRQ_IOP331_PERFMON 15 +#define IRQ_IOP331_CORE_PMU 16 +#define IRQ_IOP331_XINT0 24 +#define IRQ_IOP331_XINT1 25 +#define IRQ_IOP331_XINT2 26 +#define IRQ_IOP331_XINT3 27 +#define IRQ_IOP331_XINT8 32 +#define IRQ_IOP331_XINT9 33 +#define IRQ_IOP331_XINT10 34 +#define IRQ_IOP331_XINT11 35 +#define IRQ_IOP331_XINT12 36 +#define IRQ_IOP331_XINT13 37 +#define IRQ_IOP331_XINT14 38 +#define IRQ_IOP331_XINT15 39 +#define IRQ_IOP331_UART0 51 +#define IRQ_IOP331_UART1 52 +#define IRQ_IOP331_PBIE 53 +#define IRQ_IOP331_ATU_CRW 54 +#define IRQ_IOP331_ATU_ERR 55 +#define IRQ_IOP331_MCU_ERR 56 +#define IRQ_IOP331_DMA0_ERR 57 +#define IRQ_IOP331_DMA1_ERR 58 +#define IRQ_IOP331_AA_ERR 60 +#define IRQ_IOP331_MSG_ERR 62 +#define IRQ_IOP331_HPI 63 -/* - * On IRQ or FIQ register - */ -#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0) -#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1) -#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2) -#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3) -#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4) -#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5) -#define IRQ_IOP331_AA_EOT IOP331_IRQ(6) -#define IRQ_IOP331_AA_EOC IOP331_IRQ(7) -#define IRQ_IOP331_TIMER0 IOP331_IRQ(8) -#define IRQ_IOP331_TIMER1 IOP331_IRQ(9) -#define IRQ_IOP331_I2C_0 IOP331_IRQ(10) -#define IRQ_IOP331_I2C_1 IOP331_IRQ(11) -#define IRQ_IOP331_MSG IOP331_IRQ(12) -#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13) -#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14) -#define IRQ_IOP331_PERFMON IOP331_IRQ(15) -#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16) -#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17) -#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18) -#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19) -#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20) -#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21) -#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22) -#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23) -#define IRQ_IOP331_XINT0 IOP331_IRQ(24) -#define IRQ_IOP331_XINT1 IOP331_IRQ(25) -#define IRQ_IOP331_XINT2 IOP331_IRQ(26) -#define IRQ_IOP331_XINT3 IOP331_IRQ(27) -#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28) -#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29) -#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30) -#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31) -#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0 -#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1 -#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2 -#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3 -#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4 -#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5 -#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6 -#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7 -#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8 -#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9 -#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10 -#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11 -#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12 -#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13 -#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14 -#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15 -#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16 -#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17 -#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18 -#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19 -#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20 -#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21 -#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22 -#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23 -#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24 -#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25 -#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26 -#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27 -#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28 -#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29 -#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30 -#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31 - -#define NR_IRQS (IOP331_IRQ(63) + 1) +#define NR_IRQS 64 /* -- cgit v1.2.3 From 72edd84a6b2db1a21d1ed07929cae560e276a0a6 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:23:07 +0100 Subject: [ARM] 3827/1: iop3xx: add common gpio module Implement the gpio_line_{config,get,set} API for iop3xx. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/plat-iop/Makefile | 2 +- arch/arm/plat-iop/gpio.c | 48 ++++++++++++++++++++++++++++++++++++ drivers/i2c/busses/i2c-iop3xx.c | 16 ++++++------ include/asm-arm/arch-iop32x/iop321.h | 1 + include/asm-arm/arch-iop33x/iop331.h | 1 + include/asm-arm/hardware/iop3xx.h | 21 ++++++++++++++++ 6 files changed, 81 insertions(+), 8 deletions(-) create mode 100644 arch/arm/plat-iop/gpio.c (limited to 'include') diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile index d20cdec3a944..23da00b11517 100644 --- a/arch/arm/plat-iop/Makefile +++ b/arch/arm/plat-iop/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := i2c.o pci.o setup.o time.o +obj-y := gpio.o i2c.o pci.o setup.o time.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c new file mode 100644 index 000000000000..eda436083417 --- /dev/null +++ b/arch/arm/plat-iop/gpio.c @@ -0,0 +1,48 @@ +/* + * arch/arm/plat-iop/gpio.c + * GPIO handling for Intel IOP3xx processors. + * + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include + +void gpio_line_config(int line, int direction) +{ + unsigned long flags; + + local_irq_save(flags); + if (direction == GPIO_IN) { + *IOP3XX_GPOE |= 1 << line; + } else if (direction == GPIO_OUT) { + *IOP3XX_GPOE &= ~(1 << line); + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_line_config); + +int gpio_line_get(int line) +{ + return !!(*IOP3XX_GPID & (1 << line)); +} +EXPORT_SYMBOL(gpio_line_get); + +void gpio_line_set(int line, int value) +{ + unsigned long flags; + + local_irq_save(flags); + if (value == GPIO_LOW) { + *IOP3XX_GPOD &= ~(1 << line); + } else if (value == GPIO_HIGH) { + *IOP3XX_GPOD |= 1 << line; + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_line_set); diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c index 035417f5a003..a2d0cc3a7785 100644 --- a/drivers/i2c/busses/i2c-iop3xx.c +++ b/drivers/i2c/busses/i2c-iop3xx.c @@ -82,14 +82,16 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) /* * Every time unit enable is asserted, GPOD needs to be cleared - * on IOP32X to avoid data corruption on the bus. + * on IOP3XX to avoid data corruption on the bus. */ -#ifdef CONFIG_ARCH_IOP32X -#define IOP321_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */ -#define IOP321_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */ - - *IOP321_GPOD &= (iop3xx_adap->id == 0) ? ~IOP321_GPOD_I2C0 : - ~IOP321_GPOD_I2C1; +#ifdef CONFIG_PLAT_IOP + if (iop3xx_adap->id == 0) { + gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW); + gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW); + } else { + gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW); + gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW); + } #endif /* NB SR bits not same position as CR IE bits :-( */ iop3xx_adap->SR_enabled = diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h index 34fe07f0a44e..1e57e0094767 100644 --- a/include/asm-arm/arch-iop32x/iop321.h +++ b/include/asm-arm/arch-iop32x/iop321.h @@ -216,6 +216,7 @@ * Peripherals that are shared between the iop32x and iop33x but * located at different addresses. */ +#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg)) #define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) #include diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h index 4ebcd7197c86..d12a95aa967a 100644 --- a/include/asm-arm/arch-iop33x/iop331.h +++ b/include/asm-arm/arch-iop33x/iop331.h @@ -221,6 +221,7 @@ * Peripherals that are shared between the iop32x and iop33x but * located at different addresses. */ +#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg)) #define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg)) #include diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index 98b7cbc405e6..f3c61d041fca 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -15,6 +15,22 @@ #ifndef __IOP3XX_H #define __IOP3XX_H +/* + * IOP3XX GPIO handling + */ +#define GPIO_IN 0 +#define GPIO_OUT 1 +#define GPIO_LOW 0 +#define GPIO_HIGH 1 +#define IOP3XX_GPIO_LINE(x) (x) + +#ifndef __ASSEMBLY__ +extern void gpio_line_config(int line, int direction); +extern int gpio_line_get(int line); +extern void gpio_line_set(int line, int value); +#endif + + /* * IOP3XX processor registers */ @@ -81,6 +97,11 @@ #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) +/* General Purpose I/O */ +#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0004) +#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0008) +#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x000c) + /* Timers */ #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000) #define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004) -- cgit v1.2.3 From 7412b10f7967ef4210ed6f793004d23642dc5140 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:24:10 +0100 Subject: [ARM] 3829/1: iop3xx: optimise irq entry macros Squeeze three instructions out of the iop32x irq demuxer, and nine out of the iop33x irq demuxer by using the hardware vector generator. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop33x/irq.c | 16 ++++++++++++++++ include/asm-arm/arch-iop32x/entry-macro.S | 10 +++------- include/asm-arm/arch-iop33x/entry-macro.S | 22 +++++----------------- 3 files changed, 24 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index 675ed3989973..3c720551ac12 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -57,6 +57,20 @@ static inline void intstr_write1(u32 val) iop3xx_cp6_disable(); } +static inline void intbase_write(u32 val) +{ + iop3xx_cp6_enable(); + asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); + iop3xx_cp6_disable(); +} + +static inline void intsize_write(u32 val) +{ + iop3xx_cp6_enable(); + asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); + iop3xx_cp6_disable(); +} + static void iop331_irq_mask1 (unsigned int irq) { @@ -107,6 +121,8 @@ void __init iop331_init_irq(void) intctl_write1(0); intstr_write0(0); // treat all as IRQ intstr_write1(0); + intbase_write(0); + intsize_write(1); if(machine_is_iq80331()) // all interrupts are inputs to chip *IOP3XX_PCIIRSR = 0x0f; diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S index c5ec1e23cbea..3497fef0b890 100644 --- a/include/asm-arm/arch-iop32x/entry-macro.S +++ b/include/asm-arm/arch-iop32x/entry-macro.S @@ -16,13 +16,9 @@ * Note: only deal with normal interrupts, not FIQ */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov \irqnr, #0 ldr \base, =IOP3XX_REG_ADDR(0x07D8) ldr \irqstat, [\base] @ Read IINTSRC - cmp \irqstat, #0 - beq 1001f - clz \irqnr, \irqstat - mov \base, #31 - subs \irqnr,\base,\irqnr -1001: + cmp \irqstat, #0 + clzne \irqnr, \irqstat + rsbne \irqnr, \irqnr, #31 .endm diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S index 425aa7aafa0e..4750e98e9b4a 100644 --- a/include/asm-arm/arch-iop33x/entry-macro.S +++ b/include/asm-arm/arch-iop33x/entry-macro.S @@ -12,23 +12,11 @@ .macro disable_fiq .endm - /* - * Note: only deal with normal interrupts, not FIQ - */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov \irqnr, #0 - ldr \base, =IOP3XX_REG_ADDR(0x7A0) - ldr \irqstat, [\base] @ Read IINTSRC0 - cmp \irqstat, #0 - bne 1002f - ldr \irqstat, [\base, #4] @ Read IINTSRC1 + ldr \base, =IOP3XX_REG_ADDR(0x07C8) + ldr \irqstat, [\base] @ Read IINTVEC cmp \irqstat, #0 - beq 1001f - clz \irqnr, \irqstat - rsbs \irqnr,\irqnr,#31 @ recommend by RMK - add \irqnr,\irqnr,#IRQ_IOP331_XINT8 - b 1001f -1002: clz \irqnr, \irqstat - rsbs \irqnr,\irqnr,#31 @ recommend by RMK -1001: + ldreq \irqstat, [\base] @ erratum 63 workaround + adds \irqnr, \irqstat, #1 + movne \irqnr, \irqstat, lsr #2 .endm -- cgit v1.2.3 From c680b77efe4542830bb170e1cc40db1c47c569bc Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:24:52 +0100 Subject: [ARM] 3830/1: iop3xx: board support file cleanup Revamp the iop3xx board support: move the support code for each iop board type into its own file, start using platform serial and platform physmap flash devices, switch to a per-board time tick rate, and get rid of the ARCH_EP80219 and STEPD config options by doing the relevant checks at run time. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/configs/ep80219_defconfig | 7 +- arch/arm/configs/iq31244_defconfig | 7 +- arch/arm/configs/iq80321_defconfig | 5 +- arch/arm/configs/iq80331_defconfig | 10 +- arch/arm/configs/iq80332_defconfig | 10 +- arch/arm/mach-iop32x/Kconfig | 7 - arch/arm/mach-iop32x/Makefile | 6 +- arch/arm/mach-iop32x/common.c | 67 -------- arch/arm/mach-iop32x/iq31244-mm.c | 46 ------ arch/arm/mach-iop32x/iq31244-pci.c | 90 ---------- arch/arm/mach-iop32x/iq31244.c | 293 +++++++++++++++++++++++++++++++++ arch/arm/mach-iop32x/iq80321-mm.c | 46 ------ arch/arm/mach-iop32x/iq80321-pci.c | 84 ---------- arch/arm/mach-iop32x/iq80321.c | 193 ++++++++++++++++++++++ arch/arm/mach-iop32x/setup.c | 111 ------------- arch/arm/mach-iop33x/Kconfig | 6 - arch/arm/mach-iop33x/Makefile | 6 +- arch/arm/mach-iop33x/iq80331-pci.c | 80 --------- arch/arm/mach-iop33x/iq80331.c | 148 +++++++++++++++++ arch/arm/mach-iop33x/iq80332-pci.c | 86 ---------- arch/arm/mach-iop33x/iq80332.c | 148 +++++++++++++++++ arch/arm/mach-iop33x/setup.c | 162 ------------------ arch/arm/mach-iop33x/uart.c | 106 ++++++++++++ include/asm-arm/arch-iop32x/iop321.h | 12 -- include/asm-arm/arch-iop32x/iq31244.h | 7 - include/asm-arm/arch-iop32x/iq80321.h | 7 - include/asm-arm/arch-iop32x/irqs.h | 38 ----- include/asm-arm/arch-iop33x/hardware.h | 5 + include/asm-arm/arch-iop33x/iop331.h | 10 -- include/asm-arm/arch-iop33x/iq80331.h | 7 - include/asm-arm/arch-iop33x/iq80332.h | 7 - include/asm-arm/arch-iop33x/irqs.h | 38 ----- 32 files changed, 911 insertions(+), 944 deletions(-) delete mode 100644 arch/arm/mach-iop32x/common.c delete mode 100644 arch/arm/mach-iop32x/iq31244-mm.c delete mode 100644 arch/arm/mach-iop32x/iq31244-pci.c create mode 100644 arch/arm/mach-iop32x/iq31244.c delete mode 100644 arch/arm/mach-iop32x/iq80321-mm.c delete mode 100644 arch/arm/mach-iop32x/iq80321-pci.c create mode 100644 arch/arm/mach-iop32x/iq80321.c delete mode 100644 arch/arm/mach-iop32x/setup.c delete mode 100644 arch/arm/mach-iop33x/iq80331-pci.c create mode 100644 arch/arm/mach-iop33x/iq80331.c delete mode 100644 arch/arm/mach-iop33x/iq80332-pci.c create mode 100644 arch/arm/mach-iop33x/iq80332.c delete mode 100644 arch/arm/mach-iop33x/setup.c create mode 100644 arch/arm/mach-iop33x/uart.c (limited to 'include') diff --git a/arch/arm/configs/ep80219_defconfig b/arch/arm/configs/ep80219_defconfig index f91cf8ff359d..c10f3a8afb59 100644 --- a/arch/arm/configs/ep80219_defconfig +++ b/arch/arm/configs/ep80219_defconfig @@ -93,7 +93,6 @@ CONFIG_ARCH_IOP32X=y CONFIG_ARCH_IQ31244=y # CONFIG_ARCH_IQ80331 is not set # CONFIG_MACH_IQ80332 is not set -CONFIG_ARCH_EP80219=y # # IOP3xx Chipset Features @@ -231,9 +230,9 @@ CONFIG_MTD_CFI_UTIL=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0xf0000000 -CONFIG_MTD_PHYSMAP_LEN=0x00800000 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_EDB7312 is not set diff --git a/arch/arm/configs/iq31244_defconfig b/arch/arm/configs/iq31244_defconfig index ce1b1f20b763..0955577243de 100644 --- a/arch/arm/configs/iq31244_defconfig +++ b/arch/arm/configs/iq31244_defconfig @@ -94,7 +94,6 @@ CONFIG_ARCH_IOP32X=y CONFIG_ARCH_IQ31244=y # CONFIG_ARCH_IQ80331 is not set # CONFIG_MACH_IQ80332 is not set -# CONFIG_ARCH_EP80219 is not set # # IOP3xx Chipset Features @@ -232,9 +231,9 @@ CONFIG_MTD_CFI_UTIL=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0xf0000000 -CONFIG_MTD_PHYSMAP_LEN=0x00800000 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_EDB7312 is not set diff --git a/arch/arm/configs/iq80321_defconfig b/arch/arm/configs/iq80321_defconfig index f00b0d2159dd..96be4c058546 100644 --- a/arch/arm/configs/iq80321_defconfig +++ b/arch/arm/configs/iq80321_defconfig @@ -93,7 +93,6 @@ CONFIG_ARCH_IQ80321=y # CONFIG_ARCH_IQ31244 is not set # CONFIG_ARCH_IQ80331 is not set # CONFIG_MACH_IQ80332 is not set -# CONFIG_ARCH_EP80219 is not set # # IOP3xx Chipset Features @@ -231,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0xf0000000 -CONFIG_MTD_PHYSMAP_LEN=0x00800000 +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_EDB7312 is not set diff --git a/arch/arm/configs/iq80331_defconfig b/arch/arm/configs/iq80331_defconfig index af3a87e469d5..874872ab6bdd 100644 --- a/arch/arm/configs/iq80331_defconfig +++ b/arch/arm/configs/iq80331_defconfig @@ -93,12 +93,6 @@ CONFIG_ARCH_IOP33X=y # CONFIG_ARCH_IQ31244 is not set CONFIG_ARCH_IQ80331=y # CONFIG_MACH_IQ80332 is not set -# CONFIG_ARCH_EP80219 is not set - -# -# IOP3xx Chipset Features -# -CONFIG_IOP331_STEPD=y # # Processor Type @@ -236,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0xc0000000 -CONFIG_MTD_PHYSMAP_LEN=0x00800000 +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_EDB7312 is not set diff --git a/arch/arm/configs/iq80332_defconfig b/arch/arm/configs/iq80332_defconfig index 931c78755a30..a79895316535 100644 --- a/arch/arm/configs/iq80332_defconfig +++ b/arch/arm/configs/iq80332_defconfig @@ -93,12 +93,6 @@ CONFIG_ARCH_IOP33X=y # CONFIG_ARCH_IQ31244 is not set # CONFIG_ARCH_IQ80331 is not set CONFIG_MACH_IQ80332=y -# CONFIG_ARCH_EP80219 is not set - -# -# IOP3xx Chipset Features -# -# CONFIG_IOP331_STEPD is not set # # Processor Type @@ -236,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0xc0000000 -CONFIG_MTD_PHYSMAP_LEN=0x00800000 +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_EDB7312 is not set diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index 21e3e8c8c2ad..ff8a77a8866e 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig @@ -16,13 +16,6 @@ config ARCH_IQ31244 Say Y here if you want to run your kernel on the Intel IQ31244 evaluation kit for the IOP321 chipset. -config ARCH_EP80219 - bool "Enable support for EP80219" - select ARCH_IQ31244 - help - Say Y here if you want to run your kernel on the Intel EP80219 - evaluation kit for the Intel 80219 chipset (a IOP321 variant). - endmenu endif diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile index ef561db20c9b..af1747ae392d 100644 --- a/arch/arm/mach-iop32x/Makefile +++ b/arch/arm/mach-iop32x/Makefile @@ -2,10 +2,10 @@ # Makefile for the linux kernel. # -obj-y := common.o setup.o irq.o +obj-y := irq.o obj-m := obj-n := obj- := -obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o -obj-$(CONFIG_ARCH_IQ31244) += iq31244-mm.o iq31244-pci.o +obj-$(CONFIG_ARCH_IQ80321) += iq80321.o +obj-$(CONFIG_ARCH_IQ31244) += iq31244.o diff --git a/arch/arm/mach-iop32x/common.c b/arch/arm/mach-iop32x/common.c deleted file mode 100644 index 9a17a081327d..000000000000 --- a/arch/arm/mach-iop32x/common.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * arch/arm/mach-iop32x/common.c - * - * Common routines shared across all IOP3xx implementations - * - * Author: Deepak Saxena - * - * Copyright 2003 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include - -#ifdef CONFIG_ARCH_EP80219 -#include -/* - * Default power-off for EP80219 - */ - -static inline void ep80219_send_to_pic(__u8 c) { -} - -void ep80219_power_off(void) -{ - /* - * This function will send a SHUTDOWN_COMPLETE message to the PIC controller - * over I2C. We are not using the i2c subsystem since we are going to power - * off and it may be removed - */ - - /* Send the Address byte w/ the start condition */ - *IOP3XX_IDBR1 = 0x60; - *IOP3XX_ICR1 = 0xE9; - mdelay(1); - - /* Send the START_MSG byte w/ no start or stop condition */ - *IOP3XX_IDBR1 = 0x0F; - *IOP3XX_ICR1 = 0xE8; - mdelay(1); - - /* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or stop condition */ - *IOP3XX_IDBR1 = 0x03; - *IOP3XX_ICR1 = 0xE8; - mdelay(1); - - /* Send an ignored byte w/ stop condition */ - *IOP3XX_IDBR1 = 0x00; - *IOP3XX_ICR1 = 0xEA; - - while (1) ; -} - -#include -#include - -static int __init ep80219_init(void) -{ - pm_power_off = ep80219_power_off; - return 0; -} -arch_initcall(ep80219_init); -#endif diff --git a/arch/arm/mach-iop32x/iq31244-mm.c b/arch/arm/mach-iop32x/iq31244-mm.c deleted file mode 100644 index fba22d5d908f..000000000000 --- a/arch/arm/mach-iop32x/iq31244-mm.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * linux/arch/arm/mach-iop32x/iq31244-mm.c - * - * Low level memory initialization for iq80321 platform - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include - -#include -#include -#include - -#include -#include - - -/* - * IQ80321 specific IO mappings - * - * We use RedBoot's setup for the onboard devices. - */ -static struct map_desc iq31244_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ31244_UART, - .pfn = __phys_to_pfn(IQ31244_UART), - .length = 0x00100000, - .type = MT_DEVICE - } -}; - -void __init iq31244_map_io(void) -{ - iop3xx_map_io(); - - iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc)); -} diff --git a/arch/arm/mach-iop32x/iq31244-pci.c b/arch/arm/mach-iop32x/iq31244-pci.c deleted file mode 100644 index 605b79553747..000000000000 --- a/arch/arm/mach-iop32x/iq31244-pci.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * arch/arm/mach-iop32x/iq31244-pci.c - * - * PCI support for the Intel IQ31244 reference board - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * The following macro is used to lookup irqs in a standard table - * format for those systems that do not already have PCI - * interrupts properly routed. We assume 1 <= pin <= 4 - */ -#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ -({ int _ctl_ = -1; \ - unsigned int _idsel = idsel - minid; \ - if (_idsel <= maxid) \ - _ctl_ = pci_irq_table[_idsel][pin-1]; \ - _ctl_; }) - -#define INTA IRQ_IQ31244_INTA -#define INTB IRQ_IQ31244_INTB -#define INTC IRQ_IQ31244_INTC -#define INTD IRQ_IQ31244_INTD - -#define INTE IRQ_IQ31244_I82546 - -static inline int __init -iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ -#ifdef CONFIG_ARCH_EP80219 - {INTB, INTB, INTB, INTB}, /* CFlash */ - {INTE, INTE, INTE, INTE}, /* 82551 Pro 100 */ - {INTD, INTD, INTD, INTD}, /* PCI-X Slot */ - {INTC, INTC, INTC, INTC}, /* SATA */ -#else - {INTB, INTB, INTB, INTB}, /* CFlash */ - {INTC, INTC, INTC, INTC}, /* SATA */ - {INTD, INTD, INTD, INTD}, /* PCI-X Slot */ - {INTE, INTE, INTE, INTE}, /* 82546 GigE */ -#endif // CONFIG_ARCH_EP80219 - }; - - BUG_ON(pin < 1 || pin > 4); - - return PCI_IRQ_TABLE_LOOKUP(0, 7); -} - -static struct hw_pci iq31244_pci __initdata = { - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = iop3xx_pci_setup, - .scan = iop3xx_pci_scan_bus, - .preinit = iop3xx_pci_preinit, - .map_irq = iq31244_map_irq -}; - -static int __init iq31244_pci_init(void) -{ - if (machine_is_iq31244()) - pci_common_init(&iq31244_pci); - return 0; -} - -subsys_initcall(iq31244_pci_init); - - - - diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c new file mode 100644 index 000000000000..88b77d32b0ac --- /dev/null +++ b/arch/arm/mach-iop32x/iq31244.c @@ -0,0 +1,293 @@ +/* + * arch/arm/mach-iop32x/iq31244.c + * + * Board support code for the Intel EP80219 and IQ31244 platforms. + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * Copyright 2003 (c) MontaVista, Software, Inc. + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* + * The EP80219 and IQ31244 use the same machine ID. To find out + * which of the two we're running on, we look at the processor ID. + */ +static int is_80219(void) +{ + extern int processor_id; + return !!((processor_id & 0xffffffe0) == 0x69052e20); +} + + +/* + * EP80219/IQ31244 timer tick configuration. + */ +static void __init iq31244_timer_init(void) +{ + if (is_80219()) { + /* 33.333 MHz crystal. */ + iop3xx_init_time(200000000); + } else { + /* 33.000 MHz crystal. */ + iop3xx_init_time(198000000); + } +} + +static struct sys_timer iq31244_timer = { + .init = iq31244_timer_init, + .offset = iop3xx_gettimeoffset, +}; + + +/* + * IQ31244 I/O. + */ +static struct map_desc iq31244_io_desc[] __initdata = { + { /* on-board devices */ + .virtual = IQ31244_UART, + .pfn = __phys_to_pfn(IQ31244_UART), + .length = 0x00100000, + .type = MT_DEVICE, + }, +}; + +void __init iq31244_map_io(void) +{ + iop3xx_map_io(); + iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc)); +} + + +/* + * EP80219/IQ31244 PCI. + */ +static inline int __init +ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + if (slot == 0) { + /* CFlash */ + irq = IRQ_IOP321_XINT1; + } else if (slot == 1) { + /* 82551 Pro 100 */ + irq = IRQ_IOP321_XINT0; + } else if (slot == 2) { + /* PCI-X Slot */ + irq = IRQ_IOP321_XINT3; + } else if (slot == 3) { + /* SATA */ + irq = IRQ_IOP321_XINT2; + } else { + printk(KERN_ERR "ep80219_pci_map_irq() called for unknown " + "device PCI:%d:%d:%d\n", dev->bus->number, + PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + irq = -1; + } + + return irq; +} + +static struct hw_pci ep80219_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iop3xx_pci_setup, + .preinit = iop3xx_pci_preinit, + .scan = iop3xx_pci_scan_bus, + .map_irq = ep80219_pci_map_irq, +}; + +static inline int __init +iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + if (slot == 0) { + /* CFlash */ + irq = IRQ_IOP321_XINT1; + } else if (slot == 1) { + /* SATA */ + irq = IRQ_IOP321_XINT2; + } else if (slot == 2) { + /* PCI-X Slot */ + irq = IRQ_IOP321_XINT3; + } else if (slot == 3) { + /* 82546 GigE */ + irq = IRQ_IOP321_XINT0; + } else { + printk(KERN_ERR "iq31244_pci_map_irq() called for unknown " + "device PCI:%d:%d:%d\n", dev->bus->number, + PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + irq = -1; + } + + return irq; +} + +static struct hw_pci iq31244_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iop3xx_pci_setup, + .preinit = iop3xx_pci_preinit, + .scan = iop3xx_pci_scan_bus, + .map_irq = iq31244_pci_map_irq, +}; + +static int __init iq31244_pci_init(void) +{ + if (machine_is_iq31244()) { + if (is_80219()) { + pci_common_init(&ep80219_pci); + } else { + pci_common_init(&iq31244_pci); + } + } + + return 0; +} + +subsys_initcall(iq31244_pci_init); + + +/* + * IQ31244 machine initialisation. + */ +static struct physmap_flash_data iq31244_flash_data = { + .width = 2, +}; + +static struct resource iq31244_flash_resource = { + .start = 0xf0000000, + .end = 0xf07fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device iq31244_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &iq31244_flash_data, + }, + .num_resources = 1, + .resource = &iq31244_flash_resource, +}; + +static struct plat_serial8250_port iq31244_serial_port[] = { + { + .mapbase = IQ31244_UART, + .membase = (char *)IQ31244_UART, + .irq = IRQ_IOP321_XINT1, + .flags = UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 0, + .uartclk = 1843200, + }, + { }, +}; + +static struct resource iq31244_uart_resource = { + .start = IQ31244_UART, + .end = IQ31244_UART + 7, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device iq31244_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = iq31244_serial_port, + }, + .num_resources = 1, + .resource = &iq31244_uart_resource, +}; + +/* + * This function will send a SHUTDOWN_COMPLETE message to the PIC + * controller over I2C. We are not using the i2c subsystem since + * we are going to power off and it may be removed + */ +void ep80219_power_off(void) +{ + /* + * Send the Address byte w/ the start condition + */ + *IOP3XX_IDBR1 = 0x60; + *IOP3XX_ICR1 = 0xE9; + mdelay(1); + + /* + * Send the START_MSG byte w/ no start or stop condition + */ + *IOP3XX_IDBR1 = 0x0F; + *IOP3XX_ICR1 = 0xE8; + mdelay(1); + + /* + * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or + * stop condition + */ + *IOP3XX_IDBR1 = 0x03; + *IOP3XX_ICR1 = 0xE8; + mdelay(1); + + /* + * Send an ignored byte w/ stop condition + */ + *IOP3XX_IDBR1 = 0x00; + *IOP3XX_ICR1 = 0xEA; + + while (1) + ; +} + +static void __init iq31244_init_machine(void) +{ + platform_device_register(&iop3xx_i2c0_device); + platform_device_register(&iop3xx_i2c1_device); + platform_device_register(&iq31244_flash_device); + platform_device_register(&iq31244_serial_device); + + if (is_80219()) + pm_power_off = ep80219_power_off; +} + +MACHINE_START(IQ31244, "Intel IQ31244") + /* Maintainer: Intel Corp. */ + .phys_io = IQ31244_UART, + .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = iq31244_map_io, + .init_irq = iop321_init_irq, + .timer = &iq31244_timer, + .init_machine = iq31244_init_machine, +MACHINE_END diff --git a/arch/arm/mach-iop32x/iq80321-mm.c b/arch/arm/mach-iop32x/iq80321-mm.c deleted file mode 100644 index b6a3079ad29e..000000000000 --- a/arch/arm/mach-iop32x/iq80321-mm.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * linux/arch/arm/mach-iop32x/iq80321-mm.c - * - * Low level memory initialization for iq80321 platform - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include - -#include -#include -#include - -#include -#include - - -/* - * IQ80321 specific IO mappings - * - * We use RedBoot's setup for the onboard devices. - */ -static struct map_desc iq80321_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ80321_UART, - .pfn = __phys_to_pfn(IQ80321_UART), - .length = 0x00100000, - .type = MT_DEVICE - } -}; - -void __init iq80321_map_io(void) -{ - iop3xx_map_io(); - - iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc)); -} diff --git a/arch/arm/mach-iop32x/iq80321-pci.c b/arch/arm/mach-iop32x/iq80321-pci.c deleted file mode 100644 index cedc37b968b7..000000000000 --- a/arch/arm/mach-iop32x/iq80321-pci.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * arch/arm/mach-iop32x/iq80321-pci.c - * - * PCI support for the Intel IQ80321 reference board - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * The following macro is used to lookup irqs in a standard table - * format for those systems that do not already have PCI - * interrupts properly routed. We assume 1 <= pin <= 4 - */ -#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ -({ int _ctl_ = -1; \ - unsigned int _idsel = idsel - minid; \ - if (_idsel <= maxid) \ - _ctl_ = pci_irq_table[_idsel][pin-1]; \ - _ctl_; }) - -#define INTA IRQ_IQ80321_INTA -#define INTB IRQ_IQ80321_INTB -#define INTC IRQ_IQ80321_INTC -#define INTD IRQ_IQ80321_INTD - -#define INTE IRQ_IQ80321_I82544 - -static inline int __init -iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {INTE, INTE, INTE, INTE}, /* Gig-E */ - {-1, -1, -1, -1}, /* Unused */ - {INTC, INTD, INTA, INTB}, /* PCI-X Slot */ - {-1, -1, -1, -1}, - }; - - BUG_ON(pin < 1 || pin > 4); - -// return PCI_IRQ_TABLE_LOOKUP(4, 7); - return pci_irq_table[idsel%4][pin-1]; -} - -static struct hw_pci iq80321_pci __initdata = { - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = iop3xx_pci_setup, - .scan = iop3xx_pci_scan_bus, - .preinit = iop3xx_pci_preinit, - .map_irq = iq80321_map_irq -}; - -static int __init iq80321_pci_init(void) -{ - if (machine_is_iq80321()) - pci_common_init(&iq80321_pci); - return 0; -} - -subsys_initcall(iq80321_pci_init); - - - - diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c new file mode 100644 index 000000000000..3c9b86271759 --- /dev/null +++ b/arch/arm/mach-iop32x/iq80321.c @@ -0,0 +1,193 @@ +/* + * arch/arm/mach-iop32x/iq80321.c + * + * Board support code for the Intel IQ80321 platform. + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * IQ80321 timer tick configuration. + */ +static void __init iq80321_timer_init(void) +{ + /* 33.333 MHz crystal. */ + iop3xx_init_time(200000000); +} + +static struct sys_timer iq80321_timer = { + .init = iq80321_timer_init, + .offset = iop3xx_gettimeoffset, +}; + + +/* + * IQ80321 I/O. + */ +static struct map_desc iq80321_io_desc[] __initdata = { + { /* on-board devices */ + .virtual = IQ80321_UART, + .pfn = __phys_to_pfn(IQ80321_UART), + .length = 0x00100000, + .type = MT_DEVICE, + }, +}; + +void __init iq80321_map_io(void) +{ + iop3xx_map_io(); + iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc)); +} + + +/* + * IQ80321 PCI. + */ +static inline int __init +iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + if ((slot == 2 || slot == 6) && pin == 1) { + /* PCI-X Slot INTA */ + irq = IRQ_IOP321_XINT2; + } else if ((slot == 2 || slot == 6) && pin == 2) { + /* PCI-X Slot INTA */ + irq = IRQ_IOP321_XINT3; + } else if ((slot == 2 || slot == 6) && pin == 3) { + /* PCI-X Slot INTA */ + irq = IRQ_IOP321_XINT0; + } else if ((slot == 2 || slot == 6) && pin == 4) { + /* PCI-X Slot INTA */ + irq = IRQ_IOP321_XINT1; + } else if (slot == 4 || slot == 8) { + /* Gig-E */ + irq = IRQ_IOP321_XINT0; + } else { + printk(KERN_ERR "iq80321_pci_map_irq() called for unknown " + "device PCI:%d:%d:%d\n", dev->bus->number, + PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + irq = -1; + } + + return irq; +} + +static struct hw_pci iq80321_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iop3xx_pci_setup, + .preinit = iop3xx_pci_preinit, + .scan = iop3xx_pci_scan_bus, + .map_irq = iq80321_pci_map_irq, +}; + +static int __init iq80321_pci_init(void) +{ + if (machine_is_iq80321()) + pci_common_init(&iq80321_pci); + + return 0; +} + +subsys_initcall(iq80321_pci_init); + + +/* + * IQ80321 machine initialisation. + */ +static struct physmap_flash_data iq80321_flash_data = { + .width = 1, +}; + +static struct resource iq80321_flash_resource = { + .start = 0xf0000000, + .end = 0xf07fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device iq80321_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &iq80321_flash_data, + }, + .num_resources = 1, + .resource = &iq80321_flash_resource, +}; + +static struct plat_serial8250_port iq80321_serial_port[] = { + { + .mapbase = IQ80321_UART, + .membase = (char *)IQ80321_UART, + .irq = IRQ_IOP321_XINT1, + .flags = UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 0, + .uartclk = 1843200, + }, + { }, +}; + +static struct resource iq80321_uart_resource = { + .start = IQ80321_UART, + .end = IQ80321_UART + 7, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device iq80321_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = iq80321_serial_port, + }, + .num_resources = 1, + .resource = &iq80321_uart_resource, +}; + +static void __init iq80321_init_machine(void) +{ + platform_device_register(&iop3xx_i2c0_device); + platform_device_register(&iop3xx_i2c1_device); + platform_device_register(&iq80321_flash_device); + platform_device_register(&iq80321_serial_device); +} + +MACHINE_START(IQ80321, "Intel IQ80321") + /* Maintainer: Intel Corp. */ + .phys_io = IQ80321_UART, + .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = iq80321_map_io, + .init_irq = iop321_init_irq, + .timer = &iq80321_timer, + .init_machine = iq80321_init_machine, +MACHINE_END diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c deleted file mode 100644 index 68de247a4cca..000000000000 --- a/arch/arm/mach-iop32x/setup.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * linux/arch/arm/mach-iop32x/setup.c - * - * Author: Nicolas Pitre - * Copyright (C) 2001 MontaVista Software, Inc. - * Copyright (C) 2004 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IOP321_UART_XTAL 1843200 - -#ifdef CONFIG_ARCH_IQ80321 -#define UARTBASE IQ80321_UART -#define IRQ_UART IRQ_IQ80321_UART -#endif - -#ifdef CONFIG_ARCH_IQ31244 -#define UARTBASE IQ31244_UART -#define IRQ_UART IRQ_IQ31244_UART -#endif - -static struct uart_port iop321_serial_ports[] = { - { - .membase = (char*)(UARTBASE), - .mapbase = (UARTBASE), - .irq = IRQ_UART, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = IOP321_UART_XTAL, - .line = 0, - .type = PORT_16550A, - .fifosize = 16 - } -}; - -void __init iop32x_init(void) -{ - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - early_serial_setup(&iop321_serial_ports[0]); -} - -#ifdef CONFIG_ARCH_IQ80321 -extern void iq80321_map_io(void); -#endif - -#ifdef CONFIG_ARCH_IQ31244 -extern void iq31244_map_io(void); -#endif - -static void __init iop3xx_timer_init(void) -{ - iop3xx_init_time(IOP321_TICK_RATE); -} - -struct sys_timer iop321_timer = { - .init = iop3xx_timer_init, - .offset = iop3xx_gettimeoffset, -}; - -#if defined(CONFIG_ARCH_IQ80321) -MACHINE_START(IQ80321, "Intel IQ80321") - /* Maintainer: Intel Corporation */ - .phys_io = IQ80321_UART, - .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, - .map_io = iq80321_map_io, - .init_irq = iop321_init_irq, - .timer = &iop321_timer, - .boot_params = 0xa0000100, - .init_machine = iop32x_init, -MACHINE_END -#elif defined(CONFIG_ARCH_IQ31244) -MACHINE_START(IQ31244, "Intel IQ31244") - /* Maintainer: Intel Corp. */ - .phys_io = IQ31244_UART, - .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, - .map_io = iq31244_map_io, - .init_irq = iop321_init_irq, - .timer = &iop321_timer, - .boot_params = 0xa0000100, - .init_machine = iop32x_init, -MACHINE_END -#else -#error No machine descriptor defined for this IOP3XX implementation -#endif diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig index 410df546e954..9aa016bb18f9 100644 --- a/arch/arm/mach-iop33x/Kconfig +++ b/arch/arm/mach-iop33x/Kconfig @@ -16,12 +16,6 @@ config MACH_IQ80332 Say Y here if you want to run your kernel on the Intel IQ80332 evaluation kit for the IOP332 chipset. -config IOP331_STEPD - bool "Chip stepping D of the IOP80331 processor or IOP80333" - help - Say Y here if you have StepD of the IOP80331 or IOP8033 - based platforms. - endmenu endif diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile index f825cee57d9f..90081d8c9d16 100644 --- a/arch/arm/mach-iop33x/Makefile +++ b/arch/arm/mach-iop33x/Makefile @@ -2,10 +2,10 @@ # Makefile for the linux kernel. # -obj-y := setup.o irq.o +obj-y := irq.o uart.o obj-m := obj-n := obj- := -obj-$(CONFIG_ARCH_IQ80331) += iq80331-pci.o -obj-$(CONFIG_MACH_IQ80332) += iq80332-pci.o +obj-$(CONFIG_ARCH_IQ80331) += iq80331.o +obj-$(CONFIG_MACH_IQ80332) += iq80332.o diff --git a/arch/arm/mach-iop33x/iq80331-pci.c b/arch/arm/mach-iop33x/iq80331-pci.c deleted file mode 100644 index 8b0bed5e2f91..000000000000 --- a/arch/arm/mach-iop33x/iq80331-pci.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * arch/arm/mach-iop33x/iq80331-pci.c - * - * PCI support for the Intel IQ80331 reference board - * - * Author: Dave Jiang - * Copyright (C) 2003, 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * The following macro is used to lookup irqs in a standard table - * format for those systems that do not already have PCI - * interrupts properly routed. We assume 1 <= pin <= 4 - */ -#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ -({ int _ctl_ = -1; \ - unsigned int _idsel = idsel - minid; \ - if (_idsel <= maxid) \ - _ctl_ = pci_irq_table[_idsel][pin-1]; \ - _ctl_; }) - -#define INTA IRQ_IQ80331_INTA -#define INTB IRQ_IQ80331_INTB -#define INTC IRQ_IQ80331_INTC -#define INTD IRQ_IQ80331_INTD - -//#define INTE IRQ_IQ80331_I82544 - -static inline int __init -iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {INTB, INTC, INTD, INTA}, /* PCI-X Slot */ - {INTC, INTC, INTC, INTC}, /* GigE */ - }; - - BUG_ON(pin < 1 || pin > 4); - - return PCI_IRQ_TABLE_LOOKUP(1, 7); -} - -static struct hw_pci iq80331_pci __initdata = { - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = iop3xx_pci_setup, - .scan = iop3xx_pci_scan_bus, - .preinit = iop3xx_pci_preinit, - .map_irq = iq80331_map_irq -}; - -static int __init iq80331_pci_init(void) -{ - if (machine_is_iq80331()) - pci_common_init(&iq80331_pci); - return 0; -} - -subsys_initcall(iq80331_pci_init); - - - - diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c new file mode 100644 index 000000000000..6b8475da3df6 --- /dev/null +++ b/arch/arm/mach-iop33x/iq80331.c @@ -0,0 +1,148 @@ +/* + * arch/arm/mach-iop33x/iq80331.c + * + * Board support code for the Intel IQ80331 platform. + * + * Author: Dave Jiang + * Copyright (C) 2003 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * IQ80331 timer tick configuration. + */ +static void __init iq80331_timer_init(void) +{ + /* D-Step parts run at a higher internal bus frequency */ + if (*IOP3XX_ATURID >= 0xa) + iop3xx_init_time(333000000); + else + iop3xx_init_time(266000000); +} + +static struct sys_timer iq80331_timer = { + .init = iq80331_timer_init, + .offset = iop3xx_gettimeoffset, +}; + + +/* + * IQ80331 PCI. + */ +static inline int __init +iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + if (slot == 1 && pin == 1) { + /* PCI-X Slot INTA */ + irq = IRQ_IOP331_XINT1; + } else if (slot == 1 && pin == 2) { + /* PCI-X Slot INTB */ + irq = IRQ_IOP331_XINT2; + } else if (slot == 1 && pin == 3) { + /* PCI-X Slot INTC */ + irq = IRQ_IOP331_XINT3; + } else if (slot == 1 && pin == 4) { + /* PCI-X Slot INTD */ + irq = IRQ_IOP331_XINT0; + } else if (slot == 2) { + /* GigE */ + irq = IRQ_IOP331_XINT2; + } else { + printk(KERN_ERR "iq80331_pci_map_irq() called for unknown " + "device PCI:%d:%d:%d\n", dev->bus->number, + PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + irq = -1; + } + + return irq; +} + +static struct hw_pci iq80331_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iop3xx_pci_setup, + .preinit = iop3xx_pci_preinit, + .scan = iop3xx_pci_scan_bus, + .map_irq = iq80331_pci_map_irq, +}; + +static int __init iq80331_pci_init(void) +{ + if (machine_is_iq80331()) + pci_common_init(&iq80331_pci); + + return 0; +} + +subsys_initcall(iq80331_pci_init); + + +/* + * IQ80331 machine initialisation. + */ +static struct physmap_flash_data iq80331_flash_data = { + .width = 1, +}; + +static struct resource iq80331_flash_resource = { + .start = 0xc0000000, + .end = 0xc07fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device iq80331_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &iq80331_flash_data, + }, + .num_resources = 1, + .resource = &iq80331_flash_resource, +}; + +static void __init iq80331_init_machine(void) +{ + platform_device_register(&iop3xx_i2c0_device); + platform_device_register(&iop3xx_i2c1_device); + platform_device_register(&iop33x_uart0_device); + platform_device_register(&iop33x_uart1_device); + platform_device_register(&iq80331_flash_device); +} + +MACHINE_START(IQ80331, "Intel IQ80331") + /* Maintainer: Intel Corp. */ + .phys_io = 0xfefff000, + .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = iop3xx_map_io, + .init_irq = iop331_init_irq, + .timer = &iq80331_timer, + .init_machine = iq80331_init_machine, +MACHINE_END diff --git a/arch/arm/mach-iop33x/iq80332-pci.c b/arch/arm/mach-iop33x/iq80332-pci.c deleted file mode 100644 index 0de8aa748dd8..000000000000 --- a/arch/arm/mach-iop33x/iq80332-pci.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * arch/arm/mach-iop33x/iq80332-pci.c - * - * PCI support for the Intel IQ80332 reference board - * - * Author: Dave Jiang - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * The following macro is used to lookup irqs in a standard table - * format for those systems that do not already have PCI - * interrupts properly routed. We assume 1 <= pin <= 4 - */ -#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ -({ int _ctl_ = -1; \ - unsigned int _idsel = idsel - minid; \ - if (_idsel <= maxid) \ - _ctl_ = pci_irq_table[_idsel][pin-1]; \ - _ctl_; }) - -#define INTA IRQ_IQ80332_INTA -#define INTB IRQ_IQ80332_INTB -#define INTC IRQ_IQ80332_INTC -#define INTD IRQ_IQ80332_INTD - -//#define INTE IRQ_IQ80332_I82544 - -static inline int __init -iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) -{ - static int pci_irq_table[][8] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - {INTA, INTB, INTC, INTD}, /* PCI-X Slot */ - {-1, -1, -1, -1}, - {INTC, INTC, INTC, INTC}, /* GigE */ - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - }; - - BUG_ON(pin < 1 || pin > 4); - - return PCI_IRQ_TABLE_LOOKUP(1, 7); -} - -static struct hw_pci iq80332_pci __initdata = { - .swizzle = pci_std_swizzle, - .nr_controllers = 1, - .setup = iop3xx_pci_setup, - .scan = iop3xx_pci_scan_bus, - .preinit = iop3xx_pci_preinit, - .map_irq = iq80332_map_irq -}; - -static int __init iq80332_pci_init(void) -{ - if (machine_is_iq80332()) - pci_common_init(&iq80332_pci); - return 0; -} - -subsys_initcall(iq80332_pci_init); - - - - diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c new file mode 100644 index 000000000000..150f3fd5de0b --- /dev/null +++ b/arch/arm/mach-iop33x/iq80332.c @@ -0,0 +1,148 @@ +/* + * arch/arm/mach-iop33x/iq80332.c + * + * Board support code for the Intel IQ80332 platform. + * + * Author: Dave Jiang + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * IQ80332 timer tick configuration. + */ +static void __init iq80332_timer_init(void) +{ + /* D-Step parts and the iop333 run at a higher internal bus frequency */ + if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374) + iop3xx_init_time(333000000); + else + iop3xx_init_time(266000000); +} + +static struct sys_timer iq80332_timer = { + .init = iq80332_timer_init, + .offset = iop3xx_gettimeoffset, +}; + + +/* + * IQ80332 PCI. + */ +static inline int __init +iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + if (slot == 4 && pin == 1) { + /* PCI-X Slot INTA */ + irq = IRQ_IOP331_XINT0; + } else if (slot == 4 && pin == 2) { + /* PCI-X Slot INTB */ + irq = IRQ_IOP331_XINT1; + } else if (slot == 4 && pin == 3) { + /* PCI-X Slot INTC */ + irq = IRQ_IOP331_XINT2; + } else if (slot == 4 && pin == 4) { + /* PCI-X Slot INTD */ + irq = IRQ_IOP331_XINT3; + } else if (slot == 6) { + /* GigE */ + irq = IRQ_IOP331_XINT2; + } else { + printk(KERN_ERR "iq80332_pci_map_irq() called for unknown " + "device PCI:%d:%d:%d\n", dev->bus->number, + PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + irq = -1; + } + + return irq; +} + +static struct hw_pci iq80332_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iop3xx_pci_setup, + .preinit = iop3xx_pci_preinit, + .scan = iop3xx_pci_scan_bus, + .map_irq = iq80332_pci_map_irq, +}; + +static int __init iq80332_pci_init(void) +{ + if (machine_is_iq80332()) + pci_common_init(&iq80332_pci); + + return 0; +} + +subsys_initcall(iq80332_pci_init); + + +/* + * IQ80332 machine initialisation. + */ +static struct physmap_flash_data iq80332_flash_data = { + .width = 1, +}; + +static struct resource iq80332_flash_resource = { + .start = 0xc0000000, + .end = 0xc07fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device iq80332_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &iq80332_flash_data, + }, + .num_resources = 1, + .resource = &iq80332_flash_resource, +}; + +static void __init iq80332_init_machine(void) +{ + platform_device_register(&iop3xx_i2c0_device); + platform_device_register(&iop3xx_i2c1_device); + platform_device_register(&iop33x_uart0_device); + platform_device_register(&iop33x_uart1_device); + platform_device_register(&iq80332_flash_device); +} + +MACHINE_START(IQ80332, "Intel IQ80332") + /* Maintainer: Intel Corp. */ + .phys_io = 0xfefff000, + .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = iop3xx_map_io, + .init_irq = iop331_init_irq, + .timer = &iq80332_timer, + .init_machine = iq80332_init_machine, +MACHINE_END diff --git a/arch/arm/mach-iop33x/setup.c b/arch/arm/mach-iop33x/setup.c deleted file mode 100644 index 7cf5015436f3..000000000000 --- a/arch/arm/mach-iop33x/setup.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * linux/arch/arm/mach-iop33x/setup.c - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright (C) 2004 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IOP331_UART_XTAL 33334000 - -static struct resource iop33x_uart0_resources[] = { - [0] = { - .start = IOP331_UART0_PHYS, - .end = IOP331_UART0_PHYS + 0x3f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP331_UART0, - .end = IRQ_IOP331_UART0, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop33x_uart1_resources[] = { - [0] = { - .start = IOP331_UART1_PHYS, - .end = IOP331_UART1_PHYS + 0x3f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP331_UART1, - .end = IRQ_IOP331_UART1, - .flags = IORESOURCE_IRQ - } -}; - -static struct plat_serial8250_port iop33x_uart0_data[] = { - { - .membase = (char*)(IOP331_UART0_VIRT), - .mapbase = (IOP331_UART0_PHYS), - .irq = IRQ_IOP331_UART0, - .uartclk = IOP331_UART_XTAL, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_SKIP_TEST, - }, - { }, -}; - -static struct plat_serial8250_port iop33x_uart1_data[] = { - { - .membase = (char*)(IOP331_UART1_VIRT), - .mapbase = (IOP331_UART1_PHYS), - .irq = IRQ_IOP331_UART1, - .uartclk = IOP331_UART_XTAL, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_SKIP_TEST, - }, - { }, -}; - -static struct platform_device iop33x_uart0 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = iop33x_uart0_data, - .num_resources = 2, - .resource = iop33x_uart0_resources, -}; - -static struct platform_device iop33x_uart1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev.platform_data = iop33x_uart1_data, - .num_resources = 2, - .resource = iop33x_uart1_resources, -}; - -static struct platform_device *iop33x_devices[] __initdata = { - &iop33x_uart0, - &iop33x_uart1, -}; - -void __init iop33x_init(void) -{ - if(iop_is_331()) - { - platform_add_devices(iop33x_devices, - ARRAY_SIZE(iop33x_devices)); - } - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); -} - -#ifdef CONFIG_ARCH_IOP33X -extern void iop331_init_irq(void); -#endif - -static void __init iop3xx_timer_init(void) -{ - iop3xx_init_time(IOP331_TICK_RATE); -} - -struct sys_timer iop331_timer = { - .init = iop3xx_timer_init, - .offset = iop3xx_gettimeoffset, -}; - -#if defined(CONFIG_ARCH_IQ80331) -MACHINE_START(IQ80331, "Intel IQ80331") - /* Maintainer: Intel Corp. */ - .phys_io = 0xfefff000, - .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical - .map_io = iop3xx_map_io, - .init_irq = iop331_init_irq, - .timer = &iop331_timer, - .boot_params = 0x0100, - .init_machine = iop33x_init, -MACHINE_END - -#elif defined(CONFIG_MACH_IQ80332) -MACHINE_START(IQ80332, "Intel IQ80332") - /* Maintainer: Intel Corp. */ - .phys_io = 0xfefff000, - .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical - .map_io = iop3xx_map_io, - .init_irq = iop331_init_irq, - .timer = &iop331_timer, - .boot_params = 0x0100, - .init_machine = iop33x_init, -MACHINE_END - -#else -#error No machine descriptor defined for this IOP3XX implementation -#endif - - diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c new file mode 100644 index 000000000000..d221d4abaa87 --- /dev/null +++ b/arch/arm/mach-iop33x/uart.c @@ -0,0 +1,106 @@ +/* + * linux/arch/arm/mach-iop33x/uart.c + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright (C) 2004 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IOP331_UART_XTAL 33334000 + +static struct plat_serial8250_port iop33x_uart0_data[] = { + { + .membase = (char *)IOP331_UART0_VIRT, + .mapbase = IOP331_UART0_PHYS, + .irq = IRQ_IOP331_UART0, + .uartclk = IOP331_UART_XTAL, + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_SKIP_TEST, + }, + { }, +}; + +static struct resource iop33x_uart0_resources[] = { + [0] = { + .start = IOP331_UART0_PHYS, + .end = IOP331_UART0_PHYS + 0x3f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP331_UART0, + .end = IRQ_IOP331_UART0, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device iop33x_uart0_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = iop33x_uart0_data, + }, + .num_resources = 2, + .resource = iop33x_uart0_resources, +}; + + +static struct resource iop33x_uart1_resources[] = { + [0] = { + .start = IOP331_UART1_PHYS, + .end = IOP331_UART1_PHYS + 0x3f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP331_UART1, + .end = IRQ_IOP331_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct plat_serial8250_port iop33x_uart1_data[] = { + { + .membase = (char *)IOP331_UART1_VIRT, + .mapbase = IOP331_UART1_PHYS, + .irq = IRQ_IOP331_UART1, + .uartclk = IOP331_UART_XTAL, + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_SKIP_TEST, + }, + { }, +}; + +struct platform_device iop33x_uart1_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = iop33x_uart1_data, + }, + .num_resources = 2, + .resource = iop33x_uart1_resources, +}; diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h index 1e57e0094767..8042946327ed 100644 --- a/include/asm-arm/arch-iop32x/iop321.h +++ b/include/asm-arm/arch-iop32x/iop321.h @@ -150,18 +150,6 @@ #define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8) #define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) -/* Timers */ -#ifdef CONFIG_ARCH_IQ80321 -#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */ -#elif defined(CONFIG_ARCH_IQ31244) -#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */ -#endif - -#ifdef CONFIG_ARCH_EP80219 -#undef IOP321_TICK_RATE -#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */ -#endif - /* Application accelerator unit 0x00000800 - 0x000008FF */ #define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800) #define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804) diff --git a/include/asm-arm/arch-iop32x/iq31244.h b/include/asm-arm/arch-iop32x/iq31244.h index f490063d2156..cf2d2343398d 100644 --- a/include/asm-arm/arch-iop32x/iq31244.h +++ b/include/asm-arm/arch-iop32x/iq31244.h @@ -7,18 +7,11 @@ #ifndef _IQ31244_H_ #define _IQ31244_H_ -#define IQ31244_FLASHBASE 0xf0000000 /* Flash */ -#define IQ31244_FLASHSIZE 0x00800000 -#define IQ31244_FLASHWIDTH 2 - #define IQ31244_UART 0xfe800000 /* UART #1 */ #define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ #define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ #define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ #define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ -#ifndef __ASSEMBLY__ -extern void iq31244_map_io(void); -#endif #endif // _IQ31244_H_ diff --git a/include/asm-arm/arch-iop32x/iq80321.h b/include/asm-arm/arch-iop32x/iq80321.h index 7015a605ab64..55d70f49b7fd 100644 --- a/include/asm-arm/arch-iop32x/iq80321.h +++ b/include/asm-arm/arch-iop32x/iq80321.h @@ -7,18 +7,11 @@ #ifndef _IQ80321_H_ #define _IQ80321_H_ -#define IQ80321_FLASHBASE 0xf0000000 /* Flash */ -#define IQ80321_FLASHSIZE 0x00800000 -#define IQ80321_FLASHWIDTH 1 - #define IQ80321_UART 0xfe800000 /* UART #1 */ #define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ #define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ #define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ #define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ -#ifndef __ASSEMBLY__ -extern void iq80321_map_io(void); -#endif #endif // _IQ80321_H_ diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h index 9fefcf3372b1..a48327ced92e 100644 --- a/include/asm-arm/arch-iop32x/irqs.h +++ b/include/asm-arm/arch-iop32x/irqs.h @@ -47,42 +47,4 @@ #define NR_IRQS 32 -/* - * Interrupts available on the IQ80321 board - */ - -/* - * On board devices - */ -#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0 -#define IRQ_IQ80321_UART IRQ_IOP321_XINT1 - -/* - * PCI interrupts - */ -#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0 -#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1 -#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2 -#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3 - -/* - * Interrupts on the IQ31244 board - */ - -/* - * On board devices - */ -#define IRQ_IQ31244_UART IRQ_IOP321_XINT1 -#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0 -#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2 -#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3 - -/* - * PCI interrupts - */ -#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0 -#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1 -#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2 -#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3 - #endif // _IRQ_H_ diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h index 5e3cb32af020..3ebfdc6fea99 100644 --- a/include/asm-arm/arch-iop33x/hardware.h +++ b/include/asm-arm/arch-iop33x/hardware.h @@ -22,6 +22,11 @@ #define PCIBIOS_MIN_IO 0x00000000 #define PCIBIOS_MIN_MEM 0x00000000 +#ifndef __ASSEMBLY__ +extern struct platform_device iop33x_uart0_device; +extern struct platform_device iop33x_uart1_device; +#endif + /* * Generic chipset bits diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h index d12a95aa967a..a21872abd877 100644 --- a/include/asm-arm/arch-iop33x/iop331.h +++ b/include/asm-arm/arch-iop33x/iop331.h @@ -136,16 +136,6 @@ #define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC) -/* Timers */ -#if defined(CONFIG_ARCH_IOP33X) -#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */ -#endif - -#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333) -#undef IOP331_TICK_RATE -#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */ -#endif - /* Application accelerator unit 0x00000800 - 0x000008FF */ #define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800) #define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804) diff --git a/include/asm-arm/arch-iop33x/iq80331.h b/include/asm-arm/arch-iop33x/iq80331.h index bda7ab6d55cf..186762bf8944 100644 --- a/include/asm-arm/arch-iop33x/iq80331.h +++ b/include/asm-arm/arch-iop33x/iq80331.h @@ -7,17 +7,10 @@ #ifndef _IQ80331_H_ #define _IQ80331_H_ -#define IQ80331_FLASHBASE 0xc0000000 /* Flash */ -#define IQ80331_FLASHSIZE 0x00800000 -#define IQ80331_FLASHWIDTH 1 - #define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ #define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ #define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ #define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ -#ifndef __ASSEMBLY__ -extern void iq80331_map_io(void); -#endif #endif // _IQ80331_H_ diff --git a/include/asm-arm/arch-iop33x/iq80332.h b/include/asm-arm/arch-iop33x/iq80332.h index f728e04378ab..2a5d4ee01df9 100644 --- a/include/asm-arm/arch-iop33x/iq80332.h +++ b/include/asm-arm/arch-iop33x/iq80332.h @@ -7,17 +7,10 @@ #ifndef _IQ80332_H_ #define _IQ80332_H_ -#define IQ80332_FLASHBASE 0xc0000000 /* Flash */ -#define IQ80332_FLASHSIZE 0x00800000 -#define IQ80332_FLASHWIDTH 1 - #define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ #define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ #define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ #define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ -#ifndef __ASSEMBLY__ -extern void iq80332_map_io(void); -#endif #endif // _IQ80332_H_ diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h index 2e3ade3b5ff9..a875404a07fc 100644 --- a/include/asm-arm/arch-iop33x/irqs.h +++ b/include/asm-arm/arch-iop33x/irqs.h @@ -57,42 +57,4 @@ #define NR_IRQS 64 -/* - * Interrupts available on the IQ80331 board - */ - -/* - * On board devices - */ -#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0 -#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0 -#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1 - -/* - * PCI interrupts - */ -#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0 -#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1 -#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2 -#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3 - -/* - * Interrupts available on the IQ80332 board - */ - -/* - * On board devices - */ -#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0 -#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0 -#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1 - -/* - * PCI interrupts - */ -#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0 -#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1 -#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2 -#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3 - #endif // _IRQ_H_ -- cgit v1.2.3 From 475549faa161f4e002225f2ef75fdd2a6d83d151 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:25:33 +0100 Subject: [ARM] 3831/1: iop3xx: factor out common register defines Factor out the register defines for a number of other peripherals common to the iop32x and iop33x. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/arch-iop32x/iop321.h | 132 ----------------------------------- include/asm-arm/arch-iop33x/iop331.h | 115 ------------------------------ include/asm-arm/hardware/iop3xx.h | 114 ++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+), 247 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h index 8042946327ed..1757222a4cad 100644 --- a/include/asm-arm/arch-iop32x/iop321.h +++ b/include/asm-arm/arch-iop32x/iop321.h @@ -37,102 +37,13 @@ /* Messaging Unit 0x00000300 through 0x000003FF */ -/* Reserved 0x00000300 through 0x0000030c */ -#define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310) -#define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314) -#define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318) -#define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C) -#define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320) -#define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324) -#define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328) -#define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C) -#define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330) -#define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334) -/* Reserved 0x00000338 through 0x0000034F */ -#define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350) -#define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354) -/* Reserved 0x00000358 through 0x0000035C */ -#define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360) -#define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364) -#define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368) -#define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C) -#define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370) -#define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374) -#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378) -#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C) -#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380) - -#define IOP321_IIxR_MASK 0x7f /* masks all */ -#define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */ -#define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */ -#define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */ -#define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */ -#define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */ -#define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */ -#define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */ - -/* Reserved 0x00000384 through 0x000003FF */ - /* DMA Controller 0x00000400 through 0x000004FF */ -#define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400) -#define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404) -#define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C) -#define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410) -#define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414) -#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418) -#define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C) -#define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420) -#define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424) -/* Reserved 0x00000428 through 0x0000043C */ -#define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440) -#define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444) -#define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C) -#define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450) -#define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454) -#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458) -#define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C) -#define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460) -#define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464) -/* Reserved 0x00000468 through 0x000004FF */ /* Memory controller 0x00000500 through 0x0005FF */ /* Peripheral bus interface unit 0x00000680 through 0x0006FF */ -#define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680) -#define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684) -#define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688) -#define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C) -#define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690) -#define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694) -#define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698) -#define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C) -#define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0) -#define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4) -#define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8) -#define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC) -#define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0) -#define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4) -#define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8) -/* Reserved 0x000006BC */ -#define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0) -/* Reserved 0x000006C4 through 0x000006DC */ -#define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0) -#define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4) - -#define IOP321_PBCR_EN 0x1 - -#define IOP321_PBISR_BOOR_ERR 0x1 /* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ -#define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700) -#define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704) -#define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708) -/* reserved 0x00000070c */ -#define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710) -/* PERC0 DOESN'T EXIST - index from 1! */ -#define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710) - -#define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */ /* Internal arbitration unit 0x00000780 through 0x0007BF */ #define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780) @@ -151,49 +62,6 @@ #define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) /* Application accelerator unit 0x00000800 - 0x000008FF */ -#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800) -#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804) -#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808) -#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C) -#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810) -#define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814) -#define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818) -#define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C) -#define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C) -#define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830) -#define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834) -#define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838) -#define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840) -#define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844) -#define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848) -#define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C) -#define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850) -#define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854) -#define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858) -#define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C) -#define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864) -#define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868) -#define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C) -#define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870) -#define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874) -#define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878) -#define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C) -#define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880) -#define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888) -#define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C) -#define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890) -#define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894) -#define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898) -#define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C) -#define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0) -#define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4) -#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820) -#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824) -#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828) -#define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c) -#define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860) -#define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884) - /* SSP serial port unit 0x00001600 - 0x0000167F */ /* I2C bus interface unit 0x00001680 - 0x000016FF */ diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h index a21872abd877..8c7ec583615f 100644 --- a/include/asm-arm/arch-iop33x/iop331.h +++ b/include/asm-arm/arch-iop33x/iop331.h @@ -36,83 +36,11 @@ /* Messaging Unit 0x00000300 through 0x000003FF */ -/* Reserved 0x00000300 through 0x0000030c */ -#define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310) -#define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314) -#define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318) -#define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C) -#define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320) -#define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324) -#define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328) -#define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C) -#define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330) -#define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334) -/* Reserved 0x00000338 through 0x0000034F */ -#define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350) -#define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354) -/* Reserved 0x00000358 through 0x0000035C */ -#define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360) -#define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364) -#define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368) -#define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C) -#define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370) -#define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374) -#define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378) -#define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C) -#define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380) -/* Reserved 0x00000384 through 0x000003FF */ - /* DMA Controller 0x00000400 through 0x000004FF */ -#define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400) -#define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404) -#define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C) -#define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410) -#define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414) -#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418) -#define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C) -#define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420) -#define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424) -/* Reserved 0x00000428 through 0x0000043C */ -#define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440) -#define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444) -#define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C) -#define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450) -#define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454) -#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458) -#define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C) -#define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460) -#define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464) -/* Reserved 0x00000468 through 0x000004FF */ /* Memory controller 0x00000500 through 0x0005FF */ /* Peripheral bus interface unit 0x00000680 through 0x0006FF */ -#define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680) -#define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684) -#define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688) -#define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C) -#define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690) -#define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694) -#define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698) -#define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C) -#define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0) -#define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4) -#define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8) -#define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC) -#define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0) -#define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4) -#define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8) -/* Reserved 0x000006BC */ -#define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0) -/* Reserved 0x000006C4 through 0x000006DC */ -#define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0) -#define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4) - -#define IOP331_PBCR_EN 0x1 - -#define IOP331_PBISR_BOOR_ERR 0x1 - - /* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ /* Internal arbitration unit 0x00000780 through 0x0007BF */ @@ -137,49 +65,6 @@ /* Application accelerator unit 0x00000800 - 0x000008FF */ -#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800) -#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804) -#define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808) -#define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C) -#define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810) -#define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814) -#define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818) -#define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C) -#define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C) -#define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830) -#define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834) -#define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838) -#define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840) -#define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844) -#define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848) -#define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C) -#define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850) -#define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854) -#define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858) -#define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C) -#define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864) -#define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868) -#define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C) -#define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870) -#define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874) -#define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878) -#define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C) -#define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880) -#define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888) -#define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C) -#define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890) -#define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894) -#define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898) -#define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C) -#define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0) -#define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4) -#define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820) -#define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824) -#define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828) -#define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c) -#define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860) -#define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884) - #define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0) #define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8) diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index f3c61d041fca..1018a7486ab7 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -97,6 +97,76 @@ extern void gpio_line_set(int line, int value); #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) +/* Messaging Unit */ +#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) +#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) +#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318) +#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c) +#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320) +#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324) +#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328) +#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c) +#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330) +#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334) +#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350) +#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354) +#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360) +#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364) +#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368) +#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c) +#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370) +#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374) +#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378) +#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c) +#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380) + +/* DMA Controller */ +#define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400) +#define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404) +#define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c) +#define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410) +#define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414) +#define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418) +#define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c) +#define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420) +#define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424) +#define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440) +#define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444) +#define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c) +#define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450) +#define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454) +#define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458) +#define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c) +#define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460) +#define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464) + +/* Peripheral bus interface */ +#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680) +#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684) +#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688) +#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c) +#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690) +#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694) +#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698) +#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c) +#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0) +#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4) +#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8) +#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac) +#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0) +#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4) +#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0) +#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0) +#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4) + +/* Peripheral performance monitoring unit */ +#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700) +#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704) +#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708) +#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710) +/* PERCR0 DOESN'T EXIST - index from 1! */ +#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710) + /* General Purpose I/O */ #define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0004) #define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0008) @@ -120,6 +190,50 @@ extern void gpio_line_set(int line, int value); #define IOP3XX_TMR_RATIO_8_1 0x20 #define IOP3XX_TMR_RATIO_16_1 0x30 +/* Application accelerator unit */ +#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) +#define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804) +#define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808) +#define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c) +#define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810) +#define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814) +#define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818) +#define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c) +#define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820) +#define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824) +#define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828) +#define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c) +#define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830) +#define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834) +#define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838) +#define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c) +#define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840) +#define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844) +#define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848) +#define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c) +#define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850) +#define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854) +#define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858) +#define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c) +#define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860) +#define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864) +#define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868) +#define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c) +#define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870) +#define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874) +#define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878) +#define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c) +#define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880) +#define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884) +#define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888) +#define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c) +#define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890) +#define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894) +#define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898) +#define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c) +#define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0) +#define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4) + /* I2C bus interface unit */ #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) -- cgit v1.2.3 From c852ac80440db9b0a47f48578e9c6303078abbc1 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:26:25 +0100 Subject: [ARM] 3832/1: iop3xx: coding style cleanup Since the iop32x code isn't iop321-specific, and the iop33x code isn't iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up the code to conform to the coding style guidelines somewhat better. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/Kconfig | 9 +-- arch/arm/mach-iop32x/iq31244.c | 22 +++--- arch/arm/mach-iop32x/iq80321.c | 14 ++-- arch/arm/mach-iop32x/irq.c | 54 ++++++--------- arch/arm/mach-iop33x/iq80331.c | 12 ++-- arch/arm/mach-iop33x/iq80332.c | 12 ++-- arch/arm/mach-iop33x/irq.c | 95 ++++++++++++-------------- arch/arm/mach-iop33x/uart.c | 37 +++++----- arch/arm/oprofile/op_model_xscale.c | 6 +- arch/arm/plat-iop/i2c.c | 8 +-- arch/arm/plat-iop/time.c | 4 +- include/asm-arm/arch-iop32x/debug-macro.S | 14 ++-- include/asm-arm/arch-iop32x/dma.h | 4 +- include/asm-arm/arch-iop32x/entry-macro.S | 11 ++- include/asm-arm/arch-iop32x/hardware.h | 24 ++++--- include/asm-arm/arch-iop32x/io.h | 11 +-- include/asm-arm/arch-iop32x/iop321.h | 86 ----------------------- include/asm-arm/arch-iop32x/iop32x.h | 28 ++++++++ include/asm-arm/arch-iop32x/iq31244.h | 8 +-- include/asm-arm/arch-iop32x/iq80321.h | 8 +-- include/asm-arm/arch-iop32x/irqs.h | 66 +++++++++--------- include/asm-arm/arch-iop32x/memory.h | 7 +- include/asm-arm/arch-iop32x/system.h | 17 ++--- include/asm-arm/arch-iop32x/timex.h | 5 +- include/asm-arm/arch-iop32x/uncompress.h | 7 +- include/asm-arm/arch-iop32x/vmalloc.h | 15 +--- include/asm-arm/arch-iop33x/debug-macro.S | 12 ++-- include/asm-arm/arch-iop33x/dma.h | 4 +- include/asm-arm/arch-iop33x/entry-macro.S | 8 +-- include/asm-arm/arch-iop33x/hardware.h | 19 +++--- include/asm-arm/arch-iop33x/io.h | 12 ++-- include/asm-arm/arch-iop33x/iop331.h | 110 ------------------------------ include/asm-arm/arch-iop33x/iop33x.h | 33 +++++++++ include/asm-arm/arch-iop33x/iq80331.h | 8 +-- include/asm-arm/arch-iop33x/iq80332.h | 8 +-- include/asm-arm/arch-iop33x/irqs.h | 86 +++++++++++------------ include/asm-arm/arch-iop33x/memory.h | 6 +- include/asm-arm/arch-iop33x/system.h | 17 ++--- include/asm-arm/arch-iop33x/timex.h | 3 +- include/asm-arm/arch-iop33x/uncompress.h | 9 +-- include/asm-arm/arch-iop33x/vmalloc.h | 15 +--- 41 files changed, 376 insertions(+), 558 deletions(-) delete mode 100644 include/asm-arm/arch-iop32x/iop321.h create mode 100644 include/asm-arm/arch-iop32x/iop32x.h delete mode 100644 include/asm-arm/arch-iop33x/iop331.h create mode 100644 include/asm-arm/arch-iop33x/iop33x.h (limited to 'include') diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index ff8a77a8866e..d7abfaa525c3 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig @@ -8,13 +8,14 @@ config ARCH_IQ80321 bool "Enable support for IQ80321" help Say Y here if you want to run your kernel on the Intel IQ80321 - evaluation kit for the IOP321 chipset. + evaluation kit for the IOP321 processor. config ARCH_IQ31244 - bool "Enable support for IQ31244" + bool "Enable support for EP80219/IQ31244" help - Say Y here if you want to run your kernel on the Intel IQ31244 - evaluation kit for the IOP321 chipset. + Say Y here if you want to run your kernel on the Intel EP80219 + evaluation kit for the Intel 80219 processor (a IOP321 variant) + or the IQ31244 evaluation kit for the IOP321 processor. endmenu diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 88b77d32b0ac..be4aedfa0de6 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -98,16 +98,16 @@ ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (slot == 0) { /* CFlash */ - irq = IRQ_IOP321_XINT1; + irq = IRQ_IOP32X_XINT1; } else if (slot == 1) { /* 82551 Pro 100 */ - irq = IRQ_IOP321_XINT0; + irq = IRQ_IOP32X_XINT0; } else if (slot == 2) { /* PCI-X Slot */ - irq = IRQ_IOP321_XINT3; + irq = IRQ_IOP32X_XINT3; } else if (slot == 3) { /* SATA */ - irq = IRQ_IOP321_XINT2; + irq = IRQ_IOP32X_XINT2; } else { printk(KERN_ERR "ep80219_pci_map_irq() called for unknown " "device PCI:%d:%d:%d\n", dev->bus->number, @@ -134,18 +134,18 @@ iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (slot == 0) { /* CFlash */ - irq = IRQ_IOP321_XINT1; + irq = IRQ_IOP32X_XINT1; } else if (slot == 1) { /* SATA */ - irq = IRQ_IOP321_XINT2; + irq = IRQ_IOP32X_XINT2; } else if (slot == 2) { /* PCI-X Slot */ - irq = IRQ_IOP321_XINT3; + irq = IRQ_IOP32X_XINT3; } else if (slot == 3) { /* 82546 GigE */ - irq = IRQ_IOP321_XINT0; + irq = IRQ_IOP32X_XINT0; } else { - printk(KERN_ERR "iq31244_pci_map_irq() called for unknown " + printk(KERN_ERR "iq31244_pci_map_irq called for unknown " "device PCI:%d:%d:%d\n", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); irq = -1; @@ -206,7 +206,7 @@ static struct plat_serial8250_port iq31244_serial_port[] = { { .mapbase = IQ31244_UART, .membase = (char *)IQ31244_UART, - .irq = IRQ_IOP321_XINT1, + .irq = IRQ_IOP32X_XINT1, .flags = UPF_SKIP_TEST, .iotype = UPIO_MEM, .regshift = 0, @@ -287,7 +287,7 @@ MACHINE_START(IQ31244, "Intel IQ31244") .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = iq31244_map_io, - .init_irq = iop321_init_irq, + .init_irq = iop32x_init_irq, .timer = &iq31244_timer, .init_machine = iq31244_init_machine, MACHINE_END diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 3c9b86271759..1f37b5501888 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -78,19 +78,19 @@ iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if ((slot == 2 || slot == 6) && pin == 1) { /* PCI-X Slot INTA */ - irq = IRQ_IOP321_XINT2; + irq = IRQ_IOP32X_XINT2; } else if ((slot == 2 || slot == 6) && pin == 2) { /* PCI-X Slot INTA */ - irq = IRQ_IOP321_XINT3; + irq = IRQ_IOP32X_XINT3; } else if ((slot == 2 || slot == 6) && pin == 3) { /* PCI-X Slot INTA */ - irq = IRQ_IOP321_XINT0; + irq = IRQ_IOP32X_XINT0; } else if ((slot == 2 || slot == 6) && pin == 4) { /* PCI-X Slot INTA */ - irq = IRQ_IOP321_XINT1; + irq = IRQ_IOP32X_XINT1; } else if (slot == 4 || slot == 8) { /* Gig-E */ - irq = IRQ_IOP321_XINT0; + irq = IRQ_IOP32X_XINT0; } else { printk(KERN_ERR "iq80321_pci_map_irq() called for unknown " "device PCI:%d:%d:%d\n", dev->bus->number, @@ -148,7 +148,7 @@ static struct plat_serial8250_port iq80321_serial_port[] = { { .mapbase = IQ80321_UART, .membase = (char *)IQ80321_UART, - .irq = IRQ_IOP321_XINT1, + .irq = IRQ_IOP32X_XINT1, .flags = UPF_SKIP_TEST, .iotype = UPIO_MEM, .regshift = 0, @@ -187,7 +187,7 @@ MACHINE_START(IQ80321, "Intel IQ80321") .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = iq80321_map_io, - .init_irq = iop321_init_irq, + .init_irq = iop32x_init_irq, .timer = &iq80321_timer, .init_machine = iq80321_init_machine, MACHINE_END diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index ff049e02f5f7..21294be5a369 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-iop32x/irq.c + * arch/arm/mach-iop32x/irq.c * * Generic IOP32X IRQ handling functionality * @@ -9,76 +9,66 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * Added IOP3XX chipset and IQ80321 board masking code. - * */ + #include #include #include - #include #include #include - #include -static u32 iop321_mask /* = 0 */; +static u32 iop32x_mask; static inline void intctl_write(u32 val) { iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } static inline void intstr_write(u32 val) { iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } static void -iop321_irq_mask (unsigned int irq) +iop32x_irq_mask(unsigned int irq) { - - iop321_mask &= ~(1 << irq); - - intctl_write(iop321_mask); + iop32x_mask &= ~(1 << irq); + intctl_write(iop32x_mask); } static void -iop321_irq_unmask (unsigned int irq) +iop32x_irq_unmask(unsigned int irq) { - iop321_mask |= (1 << irq); - - intctl_write(iop321_mask); + iop32x_mask |= 1 << irq; + intctl_write(iop32x_mask); } struct irq_chip ext_chip = { - .name = "IOP", - .ack = iop321_irq_mask, - .mask = iop321_irq_mask, - .unmask = iop321_irq_unmask, + .name = "IOP32x", + .ack = iop32x_irq_mask, + .mask = iop32x_irq_mask, + .unmask = iop32x_irq_unmask, }; -void __init iop321_init_irq(void) +void __init iop32x_init_irq(void) { - unsigned int i; + int i; - intctl_write(0); // disable all interrupts - intstr_write(0); // treat all as IRQ - if(machine_is_iq80321() || - machine_is_iq31244()) // all interrupts are inputs to chip + intctl_write(0); + intstr_write(0); + if (machine_is_iq80321() || + machine_is_iq31244()) *IOP3XX_PCIIRSR = 0x0f; - for(i = 0; i < NR_IRQS; i++) - { + for (i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &ext_chip); set_irq_handler(i, do_level_IRQ); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } } - diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index 6b8475da3df6..97a7b7488264 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -61,19 +61,19 @@ iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (slot == 1 && pin == 1) { /* PCI-X Slot INTA */ - irq = IRQ_IOP331_XINT1; + irq = IRQ_IOP33X_XINT1; } else if (slot == 1 && pin == 2) { /* PCI-X Slot INTB */ - irq = IRQ_IOP331_XINT2; + irq = IRQ_IOP33X_XINT2; } else if (slot == 1 && pin == 3) { /* PCI-X Slot INTC */ - irq = IRQ_IOP331_XINT3; + irq = IRQ_IOP33X_XINT3; } else if (slot == 1 && pin == 4) { /* PCI-X Slot INTD */ - irq = IRQ_IOP331_XINT0; + irq = IRQ_IOP33X_XINT0; } else if (slot == 2) { /* GigE */ - irq = IRQ_IOP331_XINT2; + irq = IRQ_IOP33X_XINT2; } else { printk(KERN_ERR "iq80331_pci_map_irq() called for unknown " "device PCI:%d:%d:%d\n", dev->bus->number, @@ -142,7 +142,7 @@ MACHINE_START(IQ80331, "Intel IQ80331") .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, .boot_params = 0x00000100, .map_io = iop3xx_map_io, - .init_irq = iop331_init_irq, + .init_irq = iop33x_init_irq, .timer = &iq80331_timer, .init_machine = iq80331_init_machine, MACHINE_END diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 150f3fd5de0b..9887bfc1c078 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -61,19 +61,19 @@ iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (slot == 4 && pin == 1) { /* PCI-X Slot INTA */ - irq = IRQ_IOP331_XINT0; + irq = IRQ_IOP33X_XINT0; } else if (slot == 4 && pin == 2) { /* PCI-X Slot INTB */ - irq = IRQ_IOP331_XINT1; + irq = IRQ_IOP33X_XINT1; } else if (slot == 4 && pin == 3) { /* PCI-X Slot INTC */ - irq = IRQ_IOP331_XINT2; + irq = IRQ_IOP33X_XINT2; } else if (slot == 4 && pin == 4) { /* PCI-X Slot INTD */ - irq = IRQ_IOP331_XINT3; + irq = IRQ_IOP33X_XINT3; } else if (slot == 6) { /* GigE */ - irq = IRQ_IOP331_XINT2; + irq = IRQ_IOP33X_XINT2; } else { printk(KERN_ERR "iq80332_pci_map_irq() called for unknown " "device PCI:%d:%d:%d\n", dev->bus->number, @@ -142,7 +142,7 @@ MACHINE_START(IQ80332, "Intel IQ80332") .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, .boot_params = 0x00000100, .map_io = iop3xx_map_io, - .init_irq = iop331_init_irq, + .init_irq = iop33x_init_irq, .timer = &iq80332_timer, .init_machine = iq80332_init_machine, MACHINE_END diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index 3c720551ac12..63304b3d0d76 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-iop33x/irq.c + * arch/arm/mach-iop33x/irq.c * * Generic IOP331 IRQ handling functionality * @@ -9,51 +9,44 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * */ + #include #include #include - #include #include #include - #include -static u32 iop331_mask0 = 0; -static u32 iop331_mask1 = 0; +static u32 iop33x_mask0; +static u32 iop33x_mask1; -static inline void intctl_write0(u32 val) +static inline void intctl0_write(u32 val) { - // INTCTL0 iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } -static inline void intctl_write1(u32 val) +static inline void intctl1_write(u32 val) { - // INTCTL1 iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } -static inline void intstr_write0(u32 val) +static inline void intstr0_write(u32 val) { - // INTSTR0 iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } -static inline void intstr_write1(u32 val) +static inline void intstr1_write(u32 val) { - // INTSTR1 iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } @@ -72,65 +65,63 @@ static inline void intsize_write(u32 val) } static void -iop331_irq_mask1 (unsigned int irq) +iop33x_irq_mask1 (unsigned int irq) { - iop331_mask0 &= ~(1 << irq); - intctl_write0(iop331_mask0); + iop33x_mask0 &= ~(1 << irq); + intctl0_write(iop33x_mask0); } static void -iop331_irq_mask2 (unsigned int irq) +iop33x_irq_mask2 (unsigned int irq) { - iop331_mask1 &= ~(1 << (irq - 32)); - intctl_write1(iop331_mask1); + iop33x_mask1 &= ~(1 << (irq - 32)); + intctl1_write(iop33x_mask1); } static void -iop331_irq_unmask1(unsigned int irq) +iop33x_irq_unmask1(unsigned int irq) { - iop331_mask0 |= (1 << irq); - intctl_write0(iop331_mask0); + iop33x_mask0 |= 1 << irq; + intctl0_write(iop33x_mask0); } static void -iop331_irq_unmask2(unsigned int irq) +iop33x_irq_unmask2(unsigned int irq) { - iop331_mask1 |= (1 << (irq - 32)); - intctl_write1(iop331_mask1); + iop33x_mask1 |= (1 << (irq - 32)); + intctl1_write(iop33x_mask1); } -struct irq_chip iop331_irqchip1 = { - .name = "IOP-1", - .ack = iop331_irq_mask1, - .mask = iop331_irq_mask1, - .unmask = iop331_irq_unmask1, +struct irq_chip iop33x_irqchip1 = { + .name = "IOP33x-1", + .ack = iop33x_irq_mask1, + .mask = iop33x_irq_mask1, + .unmask = iop33x_irq_unmask1, }; -struct irq_chip iop331_irqchip2 = { - .name = "IOP-2", - .ack = iop331_irq_mask2, - .mask = iop331_irq_mask2, - .unmask = iop331_irq_unmask2, +struct irq_chip iop33x_irqchip2 = { + .name = "IOP33x-2", + .ack = iop33x_irq_mask2, + .mask = iop33x_irq_mask2, + .unmask = iop33x_irq_unmask2, }; -void __init iop331_init_irq(void) +void __init iop33x_init_irq(void) { - unsigned int i; + int i; - intctl_write0(0); // disable all interrupts - intctl_write1(0); - intstr_write0(0); // treat all as IRQ - intstr_write1(0); + intctl0_write(0); + intctl1_write(0); + intstr0_write(0); + intstr1_write(0); intbase_write(0); intsize_write(1); - if(machine_is_iq80331()) // all interrupts are inputs to chip + if (machine_is_iq80331()) *IOP3XX_PCIIRSR = 0x0f; - for(i = 0; i < NR_IRQS; i++) - { - set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2); + for (i = 0; i < NR_IRQS; i++) { + set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); set_irq_handler(i, do_level_IRQ); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } - diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c index d221d4abaa87..ac297cd0276c 100644 --- a/arch/arm/mach-iop33x/uart.c +++ b/arch/arm/mach-iop33x/uart.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-iop33x/uart.c + * arch/arm/mach-iop33x/uart.c * * Author: Dave Jiang (dave.jiang@intel.com) * Copyright (C) 2004 Intel Corporation. @@ -17,7 +17,6 @@ #include #include #include - #include #include #include @@ -30,14 +29,14 @@ #include #include -#define IOP331_UART_XTAL 33334000 +#define IOP33X_UART_XTAL 33334000 static struct plat_serial8250_port iop33x_uart0_data[] = { { - .membase = (char *)IOP331_UART0_VIRT, - .mapbase = IOP331_UART0_PHYS, - .irq = IRQ_IOP331_UART0, - .uartclk = IOP331_UART_XTAL, + .membase = (char *)IOP33X_UART0_VIRT, + .mapbase = IOP33X_UART0_PHYS, + .irq = IRQ_IOP33X_UART0, + .uartclk = IOP33X_UART_XTAL, .regshift = 2, .iotype = UPIO_MEM, .flags = UPF_SKIP_TEST, @@ -47,13 +46,13 @@ static struct plat_serial8250_port iop33x_uart0_data[] = { static struct resource iop33x_uart0_resources[] = { [0] = { - .start = IOP331_UART0_PHYS, - .end = IOP331_UART0_PHYS + 0x3f, + .start = IOP33X_UART0_PHYS, + .end = IOP33X_UART0_PHYS + 0x3f, .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_IOP331_UART0, - .end = IRQ_IOP331_UART0, + .start = IRQ_IOP33X_UART0, + .end = IRQ_IOP33X_UART0, .flags = IORESOURCE_IRQ, }, }; @@ -71,23 +70,23 @@ struct platform_device iop33x_uart0_device = { static struct resource iop33x_uart1_resources[] = { [0] = { - .start = IOP331_UART1_PHYS, - .end = IOP331_UART1_PHYS + 0x3f, + .start = IOP33X_UART1_PHYS, + .end = IOP33X_UART1_PHYS + 0x3f, .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_IOP331_UART1, - .end = IRQ_IOP331_UART1, + .start = IRQ_IOP33X_UART1, + .end = IRQ_IOP33X_UART1, .flags = IORESOURCE_IRQ, }, }; static struct plat_serial8250_port iop33x_uart1_data[] = { { - .membase = (char *)IOP331_UART1_VIRT, - .mapbase = IOP331_UART1_PHYS, - .irq = IRQ_IOP331_UART1, - .uartclk = IOP331_UART_XTAL, + .membase = (char *)IOP33X_UART1_VIRT, + .mapbase = IOP33X_UART1_PHYS, + .irq = IRQ_IOP33X_UART1, + .uartclk = IOP33X_UART_XTAL, .regshift = 2, .iotype = UPIO_MEM, .flags = UPF_SKIP_TEST, diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c index 7e0cc5b15b15..6576143f2559 100644 --- a/arch/arm/oprofile/op_model_xscale.c +++ b/arch/arm/oprofile/op_model_xscale.c @@ -37,10 +37,10 @@ #define XSCALE_PMU_IRQ IRQ_XS80200_PMU #endif #ifdef CONFIG_ARCH_IOP32X -#define XSCALE_PMU_IRQ IRQ_IOP321_CORE_PMU +#define XSCALE_PMU_IRQ IRQ_IOP32X_CORE_PMU #endif #ifdef CONFIG_ARCH_IOP33X -#define XSCALE_PMU_IRQ IRQ_IOP331_CORE_PMU +#define XSCALE_PMU_IRQ IRQ_IOP33X_CORE_PMU #endif #ifdef CONFIG_ARCH_PXA #define XSCALE_PMU_IRQ IRQ_PMU @@ -88,7 +88,7 @@ static struct pmu_counter results[MAX_COUNTERS]; /* * There are two versions of the PMU in current XScale processors * with differing register layouts and number of performance counters. - * e.g. IOP321 is xsc1 whilst IOP331 is xsc2. + * e.g. IOP32x is xsc1 whilst IOP33x is xsc2. * We detect which register layout to use in xscale_detect_pmu() */ enum { PMU_XSC1, PMU_XSC2 }; diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c index 7ae149c2e982..e99909bdba71 100644 --- a/arch/arm/plat-iop/i2c.c +++ b/arch/arm/plat-iop/i2c.c @@ -31,12 +31,12 @@ #include #ifdef CONFIG_ARCH_IOP32X -#define IRQ_IOP3XX_I2C_0 IRQ_IOP321_I2C_0 -#define IRQ_IOP3XX_I2C_1 IRQ_IOP321_I2C_1 +#define IRQ_IOP3XX_I2C_0 IRQ_IOP32X_I2C_0 +#define IRQ_IOP3XX_I2C_1 IRQ_IOP32X_I2C_1 #endif #ifdef CONFIG_ARCH_IOP33X -#define IRQ_IOP3XX_I2C_0 IRQ_IOP331_I2C_0 -#define IRQ_IOP3XX_I2C_1 IRQ_IOP331_I2C_1 +#define IRQ_IOP3XX_I2C_0 IRQ_IOP33X_I2C_0 +#define IRQ_IOP3XX_I2C_1 IRQ_IOP33X_I2C_1 #endif static struct resource iop3xx_i2c0_resources[] = { diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index bed20f3669f4..06282dffbdc6 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -26,10 +26,10 @@ #include #ifdef CONFIG_ARCH_IOP32X -#define IRQ_IOP3XX_TIMER0 IRQ_IOP321_TIMER0 +#define IRQ_IOP3XX_TIMER0 IRQ_IOP32X_TIMER0 #else #ifdef CONFIG_ARCH_IOP33X -#define IRQ_IOP3XX_TIMER0 IRQ_IOP331_TIMER0 +#define IRQ_IOP3XX_TIMER0 IRQ_IOP33X_TIMER0 #endif #endif diff --git a/include/asm-arm/arch-iop32x/debug-macro.S b/include/asm-arm/arch-iop32x/debug-macro.S index 75ab2e0d8c67..9022b6849e23 100644 --- a/include/asm-arm/arch-iop32x/debug-macro.S +++ b/include/asm-arm/arch-iop32x/debug-macro.S @@ -1,18 +1,18 @@ -/* linux/include/asm-arm/arch-iop32x/debug-macro.S +/* + * include/asm-arm/arch-iop32x/debug-macro.S * * Debugging macro include header * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * -*/ + */ - .macro addruart,rx - mov \rx, #0xfe000000 @ physical + .macro addruart, rx + mov \rx, #0xfe000000 @ physical as well as virtual orr \rx, \rx, #0x00800000 @ location of the UART .endm diff --git a/include/asm-arm/arch-iop32x/dma.h b/include/asm-arm/arch-iop32x/dma.h index 5be36676e58f..e977a9ef3160 100644 --- a/include/asm-arm/arch-iop32x/dma.h +++ b/include/asm-arm/arch-iop32x/dma.h @@ -1,7 +1,7 @@ /* - * linux/include/asm-arm/arch-iop32x/dma.h + * include/asm-arm/arch-iop32x/dma.h * - * Copyright (C) 2004 Intel Corp. + * Copyright (C) 2004 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S index 3497fef0b890..1500cbbd2295 100644 --- a/include/asm-arm/arch-iop32x/entry-macro.S +++ b/include/asm-arm/arch-iop32x/entry-macro.S @@ -3,19 +3,16 @@ * * Low-level IRQ helper macros for IOP32x-based platforms * - * This file is licensed under the terms of the GNU General Public + * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include +#include - .macro disable_fiq + .macro disable_fiq .endm - /* - * Note: only deal with normal interrupts, not FIQ - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \base, =IOP3XX_REG_ADDR(0x07D8) ldr \irqstat, [\base] @ Read IINTSRC cmp \irqstat, #0 diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h index 16d0630ab252..6a3001f2f7e0 100644 --- a/include/asm-arm/arch-iop32x/hardware.h +++ b/include/asm-arm/arch-iop32x/hardware.h @@ -1,8 +1,9 @@ /* - * linux/include/asm-arm/arch-iop32x/hardware.h + * include/asm-arm/arch-iop32x/hardware.h */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H + +#ifndef __HARDWARE_H +#define __HARDWARE_H #include @@ -13,21 +14,23 @@ * the IO resources. * * The PCI IO space is located at virtual 0xfe000000 from physical - * 0x90000000. The PCI BARs must be programmed with physical addresses, - * but when we read them, we convert them to virtual addresses. See - * arch/arm/mach-iop3xx/iop3xx-pci.c + * 0x90000000. The PCI BARs must be programmed with physical addresses, + * but when we read them, we convert them to virtual addresses. See + * arch/arm/plat-iop/pci.c. */ - #define pcibios_assign_all_busses() 1 #define PCIBIOS_MIN_IO 0x00000000 #define PCIBIOS_MIN_MEM 0x00000000 +#ifndef __ASSEMBLY__ +void iop32x_init_irq(void); +#endif + /* * Generic chipset bits - * */ -#include "iop321.h" +#include "iop32x.h" /* * Board specific bits @@ -35,4 +38,5 @@ #include "iq80321.h" #include "iq31244.h" -#endif /* _ASM_ARCH_HARDWARE_H */ + +#endif diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h index 36d05ada12c4..12d9ee02cde3 100644 --- a/include/asm-arm/arch-iop32x/io.h +++ b/include/asm-arm/arch-iop32x/io.h @@ -1,21 +1,22 @@ /* - * linux/include/asm-arm/arch-iop32x/io.h + * include/asm-arm/arch-iop32x/io.h * - * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2001 MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H +#ifndef __IO_H +#define __IO_H #include -#define IO_SPACE_LIMIT 0xffffffff +#define IO_SPACE_LIMIT 0xffffffff #define __io(p) ((void __iomem *)(p)) #define __mem_pci(a) (a) + #endif diff --git a/include/asm-arm/arch-iop32x/iop321.h b/include/asm-arm/arch-iop32x/iop321.h deleted file mode 100644 index 1757222a4cad..000000000000 --- a/include/asm-arm/arch-iop32x/iop321.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * linux/include/asm/arch-iop32x/iop321.h - * - * Intel IOP321 Chip definitions - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IOP321_HW_H_ -#define _IOP321_HW_H_ - - -/* - * This is needed for mixed drivers that need to work on all - * IOP3xx variants but behave slightly differently on each. - */ -#ifndef __ASSEMBLY__ -#define iop_is_321() 1 -#endif - -/* - * IOP321 chipset registers - */ -#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ -#define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */ -#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg)) - -/* Reserved 0x00000000 through 0x000000FF */ - -/* Address Translation Unit 0x00000100 through 0x000001FF */ - -/* Messaging Unit 0x00000300 through 0x000003FF */ - -/* DMA Controller 0x00000400 through 0x000004FF */ - -/* Memory controller 0x00000500 through 0x0005FF */ - -/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ - -/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ - -/* Internal arbitration unit 0x00000780 through 0x0007BF */ -#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780) -#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784) -#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788) - -/* General Purpose I/O Registers */ -#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4) -#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8) -#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC) - -/* Interrupt Controller */ -#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0) -#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4) -#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8) -#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) - -/* Application accelerator unit 0x00000800 - 0x000008FF */ - -/* SSP serial port unit 0x00001600 - 0x0000167F */ -/* I2C bus interface unit 0x00001680 - 0x000016FF */ - -/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */ - -/* - * Peripherals that are shared between the iop32x and iop33x but - * located at different addresses. - */ -#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg)) -#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) - -#include - - -#ifndef __ASSEMBLY__ -extern void iop321_init_irq(void); -extern void iop321_time_init(void); -#endif - -#endif // _IOP321_HW_H_ diff --git a/include/asm-arm/arch-iop32x/iop32x.h b/include/asm-arm/arch-iop32x/iop32x.h new file mode 100644 index 000000000000..4bbd85f3ed2a --- /dev/null +++ b/include/asm-arm/arch-iop32x/iop32x.h @@ -0,0 +1,28 @@ +/* + * include/asm-arm/arch-iop32x/iop32x.h + * + * Intel IOP32X Chip definitions + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IOP32X_H +#define __IOP32X_H + +/* + * Peripherals that are shared between the iop32x and iop33x but + * located at different addresses. + */ +#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg)) +#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) + +#include + + +#endif diff --git a/include/asm-arm/arch-iop32x/iq31244.h b/include/asm-arm/arch-iop32x/iq31244.h index cf2d2343398d..fff4eafa1f6b 100644 --- a/include/asm-arm/arch-iop32x/iq31244.h +++ b/include/asm-arm/arch-iop32x/iq31244.h @@ -1,11 +1,11 @@ /* - * linux/include/asm/arch-iop32x/iq31244.h + * include/asm-arm/arch-iop32x/iq31244.h * * Intel IQ31244 evaluation board registers */ -#ifndef _IQ31244_H_ -#define _IQ31244_H_ +#ifndef __IQ31244_H +#define __IQ31244_H #define IQ31244_UART 0xfe800000 /* UART #1 */ #define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ @@ -14,4 +14,4 @@ #define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ -#endif // _IQ31244_H_ +#endif diff --git a/include/asm-arm/arch-iop32x/iq80321.h b/include/asm-arm/arch-iop32x/iq80321.h index 55d70f49b7fd..eb69db9b9a06 100644 --- a/include/asm-arm/arch-iop32x/iq80321.h +++ b/include/asm-arm/arch-iop32x/iq80321.h @@ -1,11 +1,11 @@ /* - * linux/include/asm/arch-iop32x/iq80321.h + * include/asm-arm/arch-iop32x/iq80321.h * * Intel IQ80321 evaluation board registers */ -#ifndef _IQ80321_H_ -#define _IQ80321_H_ +#ifndef __IQ80321_H +#define __IQ80321_H #define IQ80321_UART 0xfe800000 /* UART #1 */ #define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ @@ -14,4 +14,4 @@ #define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ -#endif // _IQ80321_H_ +#endif diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h index a48327ced92e..bbaef873afce 100644 --- a/include/asm-arm/arch-iop32x/irqs.h +++ b/include/asm-arm/arch-iop32x/irqs.h @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/arch-iop32x/irqs.h + * include/asm-arm/arch-iop32x/irqs.h * * Author: Rory Bolt * Copyright: (C) 2002 Rory Bolt @@ -7,44 +7,44 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * */ -#ifndef _IRQS_H_ -#define _IRQS_H_ + +#ifndef __IRQS_H +#define __IRQS_H /* * IOP80321 chipset interrupts */ -#define IRQ_IOP321_DMA0_EOT 0 -#define IRQ_IOP321_DMA0_EOC 1 -#define IRQ_IOP321_DMA1_EOT 2 -#define IRQ_IOP321_DMA1_EOC 3 -#define IRQ_IOP321_AA_EOT 6 -#define IRQ_IOP321_AA_EOC 7 -#define IRQ_IOP321_CORE_PMON 8 -#define IRQ_IOP321_TIMER0 9 -#define IRQ_IOP321_TIMER1 10 -#define IRQ_IOP321_I2C_0 11 -#define IRQ_IOP321_I2C_1 12 -#define IRQ_IOP321_MESSAGING 13 -#define IRQ_IOP321_ATU_BIST 14 -#define IRQ_IOP321_PERFMON 15 -#define IRQ_IOP321_CORE_PMU 16 -#define IRQ_IOP321_BIU_ERR 17 -#define IRQ_IOP321_ATU_ERR 18 -#define IRQ_IOP321_MCU_ERR 19 -#define IRQ_IOP321_DMA0_ERR 20 -#define IRQ_IOP321_DMA1_ERR 21 -#define IRQ_IOP321_AA_ERR 23 -#define IRQ_IOP321_MSG_ERR 24 -#define IRQ_IOP321_SSP 25 -#define IRQ_IOP321_XINT0 27 -#define IRQ_IOP321_XINT1 28 -#define IRQ_IOP321_XINT2 29 -#define IRQ_IOP321_XINT3 30 -#define IRQ_IOP321_HPI 31 +#define IRQ_IOP32X_DMA0_EOT 0 +#define IRQ_IOP32X_DMA0_EOC 1 +#define IRQ_IOP32X_DMA1_EOT 2 +#define IRQ_IOP32X_DMA1_EOC 3 +#define IRQ_IOP32X_AA_EOT 6 +#define IRQ_IOP32X_AA_EOC 7 +#define IRQ_IOP32X_CORE_PMON 8 +#define IRQ_IOP32X_TIMER0 9 +#define IRQ_IOP32X_TIMER1 10 +#define IRQ_IOP32X_I2C_0 11 +#define IRQ_IOP32X_I2C_1 12 +#define IRQ_IOP32X_MESSAGING 13 +#define IRQ_IOP32X_ATU_BIST 14 +#define IRQ_IOP32X_PERFMON 15 +#define IRQ_IOP32X_CORE_PMU 16 +#define IRQ_IOP32X_BIU_ERR 17 +#define IRQ_IOP32X_ATU_ERR 18 +#define IRQ_IOP32X_MCU_ERR 19 +#define IRQ_IOP32X_DMA0_ERR 20 +#define IRQ_IOP32X_DMA1_ERR 21 +#define IRQ_IOP32X_AA_ERR 23 +#define IRQ_IOP32X_MSG_ERR 24 +#define IRQ_IOP32X_SSP 25 +#define IRQ_IOP32X_XINT0 27 +#define IRQ_IOP32X_XINT1 28 +#define IRQ_IOP32X_XINT2 29 +#define IRQ_IOP32X_XINT3 30 +#define IRQ_IOP32X_HPI 31 #define NR_IRQS 32 -#endif // _IRQ_H_ +#endif diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h index 4c64d9e7229b..764cd3f0d416 100644 --- a/include/asm-arm/arch-iop32x/memory.h +++ b/include/asm-arm/arch-iop32x/memory.h @@ -1,9 +1,9 @@ /* - * linux/include/asm-arm/arch-iop32x/memory.h + * include/asm-arm/arch-iop32x/memory.h */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H +#ifndef __MEMORY_H +#define __MEMORY_H #include @@ -19,7 +19,6 @@ * bus_to_virt: Used to convert an address for DMA operations * to an address that the kernel can use. */ - #define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0)) #define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2))) diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h index 1ac207a0d52e..c65ede3e627a 100644 --- a/include/asm-arm/arch-iop32x/system.h +++ b/include/asm-arm/arch-iop32x/system.h @@ -1,7 +1,7 @@ /* - * linux/include/asm-arm/arch-iop32x/system.h + * include/asm-arm/arch-iop32x/system.h * - * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2001 MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -13,17 +13,10 @@ static inline void arch_idle(void) cpu_do_idle(); } - static inline void arch_reset(char mode) { - *IOP3XX_PCSR = 0x30; + *IOP3XX_PCSR = 0x30; - if ( 1 && mode == 's') { - /* Jump into ROM at address 0 */ - cpu_reset(0); - } else { - /* No on-chip reset capability */ - cpu_reset(0); - } + /* Jump into ROM at address 0 */ + cpu_reset(0); } - diff --git a/include/asm-arm/arch-iop32x/timex.h b/include/asm-arm/arch-iop32x/timex.h index 328f37282c3e..9934b087311b 100644 --- a/include/asm-arm/arch-iop32x/timex.h +++ b/include/asm-arm/arch-iop32x/timex.h @@ -1,8 +1,9 @@ /* - * linux/include/asm-arm/arch-iop32x/timex.h + * include/asm-arm/arch-iop32x/timex.h * - * IOP3xx architecture timex specifications + * IOP32x architecture timex specifications */ + #include #define CLOCK_TICK_RATE (100 * HZ) diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h index 4a85f20c796f..e64f52bf2bce 100644 --- a/include/asm-arm/arch-iop32x/uncompress.h +++ b/include/asm-arm/arch-iop32x/uncompress.h @@ -1,6 +1,7 @@ /* - * linux/include/asm-arm/arch-iop32x/uncompress.h + * include/asm-arm/arch-iop32x/uncompress.h */ + #include #include #include @@ -8,13 +9,13 @@ static volatile u8 *uart_base; -#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) +#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) static inline void putc(char c) { while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) barrier(); - *uart_base = c; + uart_base[UART_TX] = c; } static inline void flush(void) diff --git a/include/asm-arm/arch-iop32x/vmalloc.h b/include/asm-arm/arch-iop32x/vmalloc.h index 8492e1708a63..0a70baa19517 100644 --- a/include/asm-arm/arch-iop32x/vmalloc.h +++ b/include/asm-arm/arch-iop32x/vmalloc.h @@ -1,16 +1,5 @@ /* - * linux/include/asm-arm/arch-iop32x/vmalloc.h + * include/asm-arm/arch-iop32x/vmalloc.h */ -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -//#define VMALLOC_END (0xe8000000) -/* increase usable physical RAM to ~992M per RMK */ -#define VMALLOC_END (0xfe000000) - +#define VMALLOC_END 0xfe000000 diff --git a/include/asm-arm/arch-iop33x/debug-macro.S b/include/asm-arm/arch-iop33x/debug-macro.S index b647edff475d..9e7132ebe6a7 100644 --- a/include/asm-arm/arch-iop33x/debug-macro.S +++ b/include/asm-arm/arch-iop33x/debug-macro.S @@ -1,17 +1,17 @@ -/* linux/include/asm-arm/arch-iop33x/debug-macro.S +/* + * include/asm-arm/arch-iop33x/debug-macro.S * * Debugging macro include header * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * -*/ + */ - .macro addruart,rx + .macro addruart, rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ mmu enabled? moveq \rx, #0xff000000 @ physical diff --git a/include/asm-arm/arch-iop33x/dma.h b/include/asm-arm/arch-iop33x/dma.h index d577ca59f4b0..b7775fdc5ad3 100644 --- a/include/asm-arm/arch-iop33x/dma.h +++ b/include/asm-arm/arch-iop33x/dma.h @@ -1,7 +1,7 @@ /* - * linux/include/asm-arm/arch-iop33x/dma.h + * include/asm-arm/arch-iop33x/dma.h * - * Copyright (C) 2004 Intel Corp. + * Copyright (C) 2004 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S index 4750e98e9b4a..92b791702e34 100644 --- a/include/asm-arm/arch-iop33x/entry-macro.S +++ b/include/asm-arm/arch-iop33x/entry-macro.S @@ -3,16 +3,16 @@ * * Low-level IRQ helper macros for IOP33x-based platforms * - * This file is licensed under the terms of the GNU General Public + * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include +#include - .macro disable_fiq + .macro disable_fiq .endm - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \base, =IOP3XX_REG_ADDR(0x07C8) ldr \irqstat, [\base] @ Read IINTVEC cmp \irqstat, #0 diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h index 3ebfdc6fea99..0659cf94d040 100644 --- a/include/asm-arm/arch-iop33x/hardware.h +++ b/include/asm-arm/arch-iop33x/hardware.h @@ -1,8 +1,9 @@ /* - * linux/include/asm-arm/arch-iop33x/hardware.h + * include/asm-arm/arch-iop33x/hardware.h */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H + +#ifndef __HARDWARE_H +#define __HARDWARE_H #include @@ -15,14 +16,15 @@ * The PCI IO space is located at virtual 0xfe000000 from physical * 0x90000000. The PCI BARs must be programmed with physical addresses, * but when we read them, we convert them to virtual addresses. See - * arch/arm/mach-iop33x/pci.c + * arch/arm/mach-iop3xx/iop3xx-pci.c */ - -#define pcibios_assign_all_busses() 1 +#define pcibios_assign_all_busses() 1 #define PCIBIOS_MIN_IO 0x00000000 #define PCIBIOS_MIN_MEM 0x00000000 #ifndef __ASSEMBLY__ +void iop33x_init_irq(void); + extern struct platform_device iop33x_uart0_device; extern struct platform_device iop33x_uart1_device; #endif @@ -32,7 +34,7 @@ extern struct platform_device iop33x_uart1_device; * Generic chipset bits * */ -#include "iop331.h" +#include "iop33x.h" /* * Board specific bits @@ -40,4 +42,5 @@ extern struct platform_device iop33x_uart1_device; #include "iq80331.h" #include "iq80332.h" -#endif /* _ASM_ARCH_HARDWARE_H */ + +#endif diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h index a9949d5d4953..c017402bab96 100644 --- a/include/asm-arm/arch-iop33x/io.h +++ b/include/asm-arm/arch-iop33x/io.h @@ -1,21 +1,21 @@ /* - * linux/include/asm-arm/arch-iop33x/io.h + * include/asm-arm/arch-iop33x/io.h * - * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2001 MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H +#ifndef __IO_H +#define __IO_H #include -#define IO_SPACE_LIMIT 0xffffffff - +#define IO_SPACE_LIMIT 0xffffffff #define __io(p) ((void __iomem *)(p)) #define __mem_pci(a) (a) + #endif diff --git a/include/asm-arm/arch-iop33x/iop331.h b/include/asm-arm/arch-iop33x/iop331.h deleted file mode 100644 index 8c7ec583615f..000000000000 --- a/include/asm-arm/arch-iop33x/iop331.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * linux/include/asm/arch-iop33x/iop331.h - * - * Intel IOP331 Chip definitions - * - * Author: Dave Jiang (dave.jiang@intel.com) - * Copyright (C) 2003, 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IOP331_HW_H_ -#define _IOP331_HW_H_ - - -/* - * This is needed for mixed drivers that need to work on all - * IOP3xx variants but behave slightly differently on each. - */ -#ifndef __ASSEMBLY__ -#define iop_is_331() 1 -#endif - -/* - * IOP331 chipset registers - */ -#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/ -#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */ -#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg)) - -/* Reserved 0x00000000 through 0x000000FF */ - -/* Address Translation Unit 0x00000100 through 0x000001FF */ - -/* Messaging Unit 0x00000300 through 0x000003FF */ - -/* DMA Controller 0x00000400 through 0x000004FF */ - -/* Memory controller 0x00000500 through 0x0005FF */ - -/* Peripheral bus interface unit 0x00000680 through 0x0006FF */ - -/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */ -/* Internal arbitration unit 0x00000780 through 0x0007BF */ - -/* Interrupt Controller */ -#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790) -#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794) -#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798) -#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C) -#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0) -#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4) -#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8) -#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC) -#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0) -#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4) -#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8) -#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC) -#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0) -#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4) -#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8) -#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC) - - -/* Application accelerator unit 0x00000800 - 0x000008FF */ - -#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0) -#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8) -/* SSP serial port unit 0x00001600 - 0x0000167F */ - -/* I2C bus interface unit 0x00001680 - 0x000016FF */ - -/* 0x00001700 through 0x0000172C UART 0 */ - -/* Reserved 0x00001730 through 0x0000173F */ - -/* 0x00001740 through 0x0000176C UART 1 */ - -#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */ -#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */ -#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */ -#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */ - -/* Reserved 0x00001770 through 0x0000177F */ - -/* General Purpose I/O Registers */ -#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780) -#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784) -#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788) - -/* Reserved 0x0000178c through 0x000019ff */ - -/* - * Peripherals that are shared between the iop32x and iop33x but - * located at different addresses. - */ -#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg)) -#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg)) - -#include - - -#ifndef __ASSEMBLY__ -extern void iop331_init_irq(void); -extern void iop331_time_init(void); -#endif - -#endif // _IOP331_HW_H_ diff --git a/include/asm-arm/arch-iop33x/iop33x.h b/include/asm-arm/arch-iop33x/iop33x.h new file mode 100644 index 000000000000..7ac6e93db5ff --- /dev/null +++ b/include/asm-arm/arch-iop33x/iop33x.h @@ -0,0 +1,33 @@ +/* + * include/asm-arm/arch-iop33x/iop33x.h + * + * Intel IOP33X Chip definitions + * + * Author: Dave Jiang (dave.jiang@intel.com) + * Copyright (C) 2003, 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IOP33X_H +#define __IOP33X_H + +/* + * Peripherals that are shared between the iop32x and iop33x but + * located at different addresses. + */ +#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg)) +#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg)) + +#include + +/* UARTs */ +#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700) +#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700) +#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740) +#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740) + + +#endif diff --git a/include/asm-arm/arch-iop33x/iq80331.h b/include/asm-arm/arch-iop33x/iq80331.h index 186762bf8944..79b9302017ea 100644 --- a/include/asm-arm/arch-iop33x/iq80331.h +++ b/include/asm-arm/arch-iop33x/iq80331.h @@ -1,11 +1,11 @@ /* - * linux/include/asm/arch-iop33x/iq80331.h + * include/asm-arm/arch-iop33x/iq80331.h * * Intel IQ80331 evaluation board registers */ -#ifndef _IQ80331_H_ -#define _IQ80331_H_ +#ifndef __IQ80331_H +#define __IQ80331_H #define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ #define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ @@ -13,4 +13,4 @@ #define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ -#endif // _IQ80331_H_ +#endif diff --git a/include/asm-arm/arch-iop33x/iq80332.h b/include/asm-arm/arch-iop33x/iq80332.h index 2a5d4ee01df9..053165629492 100644 --- a/include/asm-arm/arch-iop33x/iq80332.h +++ b/include/asm-arm/arch-iop33x/iq80332.h @@ -1,11 +1,11 @@ /* - * linux/include/asm/arch-iop33x/iq80332.h + * include/asm-arm/arch-iop33x/iq80332.h * * Intel IQ80332 evaluation board registers */ -#ifndef _IQ80332_H_ -#define _IQ80332_H_ +#ifndef __IQ80332_H +#define __IQ80332_H #define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ #define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ @@ -13,4 +13,4 @@ #define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ -#endif // _IQ80332_H_ +#endif diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h index a875404a07fc..d045f8403396 100644 --- a/include/asm-arm/arch-iop33x/irqs.h +++ b/include/asm-arm/arch-iop33x/irqs.h @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/arch-iop33x/irqs.h + * include/asm-arm/arch-iop33x/irqs.h * * Author: Dave Jiang (dave.jiang@intel.com) * Copyright: (C) 2003 Intel Corp. @@ -7,54 +7,54 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * */ -#ifndef _IRQS_H_ -#define _IRQS_H_ + +#ifndef __IRQS_H +#define __IRQS_H /* * IOP80331 chipset interrupts */ -#define IRQ_IOP331_DMA0_EOT 0 -#define IRQ_IOP331_DMA0_EOC 1 -#define IRQ_IOP331_DMA1_EOT 2 -#define IRQ_IOP331_DMA1_EOC 3 -#define IRQ_IOP331_AA_EOT 6 -#define IRQ_IOP331_AA_EOC 7 -#define IRQ_IOP331_TIMER0 8 -#define IRQ_IOP331_TIMER1 9 -#define IRQ_IOP331_I2C_0 10 -#define IRQ_IOP331_I2C_1 11 -#define IRQ_IOP331_MSG 12 -#define IRQ_IOP331_MSGIBQ 13 -#define IRQ_IOP331_ATU_BIST 14 -#define IRQ_IOP331_PERFMON 15 -#define IRQ_IOP331_CORE_PMU 16 -#define IRQ_IOP331_XINT0 24 -#define IRQ_IOP331_XINT1 25 -#define IRQ_IOP331_XINT2 26 -#define IRQ_IOP331_XINT3 27 -#define IRQ_IOP331_XINT8 32 -#define IRQ_IOP331_XINT9 33 -#define IRQ_IOP331_XINT10 34 -#define IRQ_IOP331_XINT11 35 -#define IRQ_IOP331_XINT12 36 -#define IRQ_IOP331_XINT13 37 -#define IRQ_IOP331_XINT14 38 -#define IRQ_IOP331_XINT15 39 -#define IRQ_IOP331_UART0 51 -#define IRQ_IOP331_UART1 52 -#define IRQ_IOP331_PBIE 53 -#define IRQ_IOP331_ATU_CRW 54 -#define IRQ_IOP331_ATU_ERR 55 -#define IRQ_IOP331_MCU_ERR 56 -#define IRQ_IOP331_DMA0_ERR 57 -#define IRQ_IOP331_DMA1_ERR 58 -#define IRQ_IOP331_AA_ERR 60 -#define IRQ_IOP331_MSG_ERR 62 -#define IRQ_IOP331_HPI 63 +#define IRQ_IOP33X_DMA0_EOT 0 +#define IRQ_IOP33X_DMA0_EOC 1 +#define IRQ_IOP33X_DMA1_EOT 2 +#define IRQ_IOP33X_DMA1_EOC 3 +#define IRQ_IOP33X_AA_EOT 6 +#define IRQ_IOP33X_AA_EOC 7 +#define IRQ_IOP33X_TIMER0 8 +#define IRQ_IOP33X_TIMER1 9 +#define IRQ_IOP33X_I2C_0 10 +#define IRQ_IOP33X_I2C_1 11 +#define IRQ_IOP33X_MSG 12 +#define IRQ_IOP33X_MSGIBQ 13 +#define IRQ_IOP33X_ATU_BIST 14 +#define IRQ_IOP33X_PERFMON 15 +#define IRQ_IOP33X_CORE_PMU 16 +#define IRQ_IOP33X_XINT0 24 +#define IRQ_IOP33X_XINT1 25 +#define IRQ_IOP33X_XINT2 26 +#define IRQ_IOP33X_XINT3 27 +#define IRQ_IOP33X_XINT8 32 +#define IRQ_IOP33X_XINT9 33 +#define IRQ_IOP33X_XINT10 34 +#define IRQ_IOP33X_XINT11 35 +#define IRQ_IOP33X_XINT12 36 +#define IRQ_IOP33X_XINT13 37 +#define IRQ_IOP33X_XINT14 38 +#define IRQ_IOP33X_XINT15 39 +#define IRQ_IOP33X_UART0 51 +#define IRQ_IOP33X_UART1 52 +#define IRQ_IOP33X_PBIE 53 +#define IRQ_IOP33X_ATU_CRW 54 +#define IRQ_IOP33X_ATU_ERR 55 +#define IRQ_IOP33X_MCU_ERR 56 +#define IRQ_IOP33X_DMA0_ERR 57 +#define IRQ_IOP33X_DMA1_ERR 58 +#define IRQ_IOP33X_AA_ERR 60 +#define IRQ_IOP33X_MSG_ERR 62 +#define IRQ_IOP33X_HPI 63 #define NR_IRQS 64 -#endif // _IRQ_H_ +#endif diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h index de208d2cca4e..0d39139b241e 100644 --- a/include/asm-arm/arch-iop33x/memory.h +++ b/include/asm-arm/arch-iop33x/memory.h @@ -1,9 +1,9 @@ /* - * linux/include/asm-arm/arch-iop33x/memory.h + * include/asm-arm/arch-iop33x/memory.h */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H +#ifndef __MEMORY_H +#define __MEMORY_H #include diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h index 8270ad9f86c8..00dd07ece262 100644 --- a/include/asm-arm/arch-iop33x/system.h +++ b/include/asm-arm/arch-iop33x/system.h @@ -1,7 +1,7 @@ /* - * linux/include/asm-arm/arch-iop33x/system.h + * include/asm-arm/arch-iop33x/system.h * - * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2001 MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -13,17 +13,10 @@ static inline void arch_idle(void) cpu_do_idle(); } - static inline void arch_reset(char mode) { - *IOP3XX_PCSR = 0x30; + *IOP3XX_PCSR = 0x30; - if ( 1 && mode == 's') { - /* Jump into ROM at address 0 */ - cpu_reset(0); - } else { - /* No on-chip reset capability */ - cpu_reset(0); - } + /* Jump into ROM at address 0 */ + cpu_reset(0); } - diff --git a/include/asm-arm/arch-iop33x/timex.h b/include/asm-arm/arch-iop33x/timex.h index 8994322a09f4..fe3e1e369ff9 100644 --- a/include/asm-arm/arch-iop33x/timex.h +++ b/include/asm-arm/arch-iop33x/timex.h @@ -1,8 +1,9 @@ /* - * linux/include/asm-arm/arch-iop33x/timex.h + * include/asm-arm/arch-iop33x/timex.h * * IOP3xx architecture timex specifications */ + #include #define CLOCK_TICK_RATE (100 * HZ) diff --git a/include/asm-arm/arch-iop33x/uncompress.h b/include/asm-arm/arch-iop33x/uncompress.h index 62904ae3b038..e17fbc05877b 100644 --- a/include/asm-arm/arch-iop33x/uncompress.h +++ b/include/asm-arm/arch-iop33x/uncompress.h @@ -1,6 +1,7 @@ /* - * linux/include/asm-arm/arch-iop33x/uncompress.h + * include/asm-arm/arch-iop33x/uncompress.h */ + #include #include #include @@ -8,13 +9,13 @@ static volatile u32 *uart_base; -#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) +#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) static inline void putc(char c) { while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) barrier(); - *uart_base = c; + uart_base[UART_TX] = c; } static inline void flush(void) @@ -24,7 +25,7 @@ static inline void flush(void) static __inline__ void __arch_decomp_setup(unsigned long arch_id) { if (machine_is_iq80331() || machine_is_iq80332()) - uart_base = (volatile u32 *)IOP331_UART0_PHYS; + uart_base = (volatile u32 *)IOP33X_UART0_PHYS; else uart_base = (volatile u32 *)0xfe800000; } diff --git a/include/asm-arm/arch-iop33x/vmalloc.h b/include/asm-arm/arch-iop33x/vmalloc.h index b5092027449e..66f545a7f4fc 100644 --- a/include/asm-arm/arch-iop33x/vmalloc.h +++ b/include/asm-arm/arch-iop33x/vmalloc.h @@ -1,16 +1,5 @@ /* - * linux/include/asm-arm/arch-iop33x/vmalloc.h + * include/asm-arm/arch-iop33x/vmalloc.h */ -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -//#define VMALLOC_END (0xe8000000) -/* increase usable physical RAM to ~992M per RMK */ -#define VMALLOC_END (0xfe000000) - +#define VMALLOC_END 0xfe000000 -- cgit v1.2.3 From 3b7a86c2f01dafa797908fdcf386f51eb0d01f29 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 20 Sep 2006 21:57:06 +0100 Subject: [ARM] 3846/1: S3C24XX: Fix osiris memory map The memory mapping for the Osiris machine are all off by one bit, and the base address has been fixed for writing (bit25 is being checked by the write, but not on read) Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/osiris-map.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h index e2d406218ae5..a14164dfa525 100644 --- a/include/asm-arm/arch-s3c2410/osiris-map.h +++ b/include/asm-arm/arch-s3c2410/osiris-map.h @@ -18,22 +18,22 @@ /* start peripherals off after the S3C2410 */ -#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x05000000)) +#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000)) -#define OSIRIS_PA_CPLD (S3C2410_CS1 | (3<<25)) +#define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26)) /* we put the CPLD registers next, to get them out of the way */ -#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000) /* 0x01300000 */ +#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000) #define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD) -#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000) /* 0x01400000 */ -#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<24)) +#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000) +#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<23)) -#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000) /* 0x01500000 */ -#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<24)) +#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000) +#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) -#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000) /* 0x01600000 */ -#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<24)) +#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000) +#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<23)) #endif /* __ASM_ARCH_OSIRISMAP_H */ -- cgit v1.2.3 From 17b602b1c1a38f3f0a4461bb1f571346e751b36b Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 21 Sep 2006 02:24:38 +0100 Subject: [ARM] 3849/1: fix get_unaligned() for gcc >= 4.1 gcc 4.1's __typeof__ propagates 'const', which breaks get_unaligned(). Rewrite get_unaligned() not to use __typeof__. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/unaligned.h | 62 ++++++++++++++++++--------------------------- 1 file changed, 25 insertions(+), 37 deletions(-) (limited to 'include') diff --git a/include/asm-arm/unaligned.h b/include/asm-arm/unaligned.h index 1b39c2f322c9..795b9e5b9e6a 100644 --- a/include/asm-arm/unaligned.h +++ b/include/asm-arm/unaligned.h @@ -3,7 +3,7 @@ #include -extern int __bug_unaligned_x(void *ptr); +extern int __bug_unaligned_x(const void *ptr); /* * What is the most efficient way of loading/storing an unaligned value? @@ -51,44 +51,32 @@ extern int __bug_unaligned_x(void *ptr); #define __get_unaligned_4_be(__p) \ (__p[0] << 24 | __p[1] << 16 | __p[2] << 8 | __p[3]) -#define __get_unaligned_le(ptr) \ - ({ \ - __typeof__(*(ptr)) __v; \ - __u8 *__p = (__u8 *)(ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: __v = *(ptr); break; \ - case 2: __v = __get_unaligned_2_le(__p); break; \ - case 4: __v = __get_unaligned_4_le(__p); break; \ - case 8: { \ - unsigned int __v1, __v2; \ - __v2 = __get_unaligned_4_le((__p+4)); \ - __v1 = __get_unaligned_4_le(__p); \ - __v = ((unsigned long long)__v2 << 32 | __v1); \ - } \ - break; \ - default: __v = __bug_unaligned_x(__p); break; \ - } \ - __v; \ +#define __get_unaligned_8_le(__p) \ + ((unsigned long long)__get_unaligned_4_le((__p+4)) << 32 | \ + __get_unaligned_4_le(__p)) + +#define __get_unaligned_8_be(__p) \ + ((unsigned long long)__get_unaligned_4_be(__p) << 32 | \ + __get_unaligned_4_be((__p+4))) + +#define __get_unaligned_le(ptr) \ + ({ \ + const __u8 *__p = (const __u8 *)(ptr); \ + __builtin_choose_expr(sizeof(*(ptr)) == 1, *__p, \ + __builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_le(__p), \ + __builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_le(__p), \ + __builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_le(__p), \ + (void)__bug_unaligned_x(__p))))); \ }) -#define __get_unaligned_be(ptr) \ - ({ \ - __typeof__(*(ptr)) __v; \ - __u8 *__p = (__u8 *)(ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: __v = *(ptr); break; \ - case 2: __v = __get_unaligned_2_be(__p); break; \ - case 4: __v = __get_unaligned_4_be(__p); break; \ - case 8: { \ - unsigned int __v1, __v2; \ - __v2 = __get_unaligned_4_be(__p); \ - __v1 = __get_unaligned_4_be((__p+4)); \ - __v = ((unsigned long long)__v2 << 32 | __v1); \ - } \ - break; \ - default: __v = __bug_unaligned_x(__p); break; \ - } \ - __v; \ +#define __get_unaligned_be(ptr) \ + ({ \ + const __u8 *__p = (const __u8 *)(ptr); \ + __builtin_choose_expr(sizeof(*(ptr)) == 1, *__p, \ + __builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_be(__p), \ + __builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_be(__p), \ + __builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_be(__p), \ + (void)__bug_unaligned_x(__p))))); \ }) -- cgit v1.2.3 From e60d07b6cd38a7afb85f2cf51aebcb3359b63819 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 21 Sep 2006 02:42:12 +0100 Subject: [ARM] 3850/1: iop3xx: add thecus n2100 support Add support for the Thecus n2100 (80219-based.) Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/configs/iop32x_defconfig | 119 +++++++++++++++- arch/arm/mach-iop32x/Kconfig | 6 + arch/arm/mach-iop32x/Makefile | 1 + arch/arm/mach-iop32x/irq.c | 3 +- arch/arm/mach-iop32x/n2100.c | 251 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-iop32x/hardware.h | 1 + include/asm-arm/arch-iop32x/n2100.h | 19 +++ include/asm-arm/arch-iop32x/system.h | 11 ++ 8 files changed, 408 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-iop32x/n2100.c create mode 100644 include/asm-arm/arch-iop32x/n2100.h (limited to 'include') diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig index af7ead33c6dd..af3b40c0508a 100644 --- a/arch/arm/configs/iop32x_defconfig +++ b/arch/arm/configs/iop32x_defconfig @@ -128,6 +128,7 @@ CONFIG_ARCH_IOP32X=y # CONFIG_ARCH_IQ80321=y CONFIG_ARCH_IQ31244=y +CONFIG_MACH_N2100=y CONFIG_PLAT_IOP=y # @@ -601,7 +602,8 @@ CONFIG_E1000_NAPI=y # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set +CONFIG_R8169=y +# CONFIG_R8169_NAPI is not set # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set @@ -897,12 +899,125 @@ CONFIG_DUMMY_CONSOLE=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_TOUCHSCREEN is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_ATI_REMOTE2 is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGETKIT is not set +# CONFIG_USB_PHIDGETSERVO is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set + +# +# USB DSL modem support +# + # # USB Gadget Support # diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index d7abfaa525c3..0a397a4a6ac9 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig @@ -17,6 +17,12 @@ config ARCH_IQ31244 evaluation kit for the Intel 80219 processor (a IOP321 variant) or the IQ31244 evaluation kit for the IOP321 processor. +config MACH_N2100 + bool "Enable support for the Thecus n2100" + help + Say Y here if you want to run your kernel on the Thecus n2100 + NAS appliance. + endmenu endif diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile index af1747ae392d..9c62470cd4f5 100644 --- a/arch/arm/mach-iop32x/Makefile +++ b/arch/arm/mach-iop32x/Makefile @@ -9,3 +9,4 @@ obj- := obj-$(CONFIG_ARCH_IQ80321) += iq80321.o obj-$(CONFIG_ARCH_IQ31244) += iq31244.o +obj-$(CONFIG_MACH_N2100) += n2100.o diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 21294be5a369..17fb94e6e29f 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -63,7 +63,8 @@ void __init iop32x_init_irq(void) intctl_write(0); intstr_write(0); if (machine_is_iq80321() || - machine_is_iq31244()) + machine_is_iq31244() || + machine_is_n2100()) *IOP3XX_PCIIRSR = 0x0f; for (i = 0; i < NR_IRQS; i++) { diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c new file mode 100644 index 000000000000..a2c94a47b2b2 --- /dev/null +++ b/arch/arm/mach-iop32x/n2100.c @@ -0,0 +1,251 @@ +/* + * arch/arm/mach-iop32x/n2100.c + * + * Board support code for the Thecus N2100 platform. + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * Copyright 2003 (c) MontaVista, Software, Inc. + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * N2100 timer tick configuration. + */ +static void __init n2100_timer_init(void) +{ + /* 33.000 MHz crystal. */ + iop3xx_init_time(198000000); +} + +static struct sys_timer n2100_timer = { + .init = n2100_timer_init, + .offset = iop3xx_gettimeoffset, +}; + + +/* + * N2100 I/O. + */ +static struct map_desc n2100_io_desc[] __initdata = { + { /* on-board devices */ + .virtual = N2100_UART, + .pfn = __phys_to_pfn(N2100_UART), + .length = 0x00100000, + .type = MT_DEVICE + }, +}; + +void __init n2100_map_io(void) +{ + iop3xx_map_io(); + iotable_init(n2100_io_desc, ARRAY_SIZE(n2100_io_desc)); +} + + +/* + * N2100 PCI. + */ +static inline int __init +n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + if (PCI_SLOT(dev->devfn) == 1) { + /* RTL8110SB #1 */ + irq = IRQ_IOP32X_XINT0; + } else if (PCI_SLOT(dev->devfn) == 2) { + /* RTL8110SB #2 */ + irq = IRQ_IOP32X_XINT1; + } else if (PCI_SLOT(dev->devfn) == 3) { + /* Sil3512 */ + irq = IRQ_IOP32X_XINT2; + } else if (PCI_SLOT(dev->devfn) == 4 && pin == 1) { + /* VT6212 INTA */ + irq = IRQ_IOP32X_XINT1; + } else if (PCI_SLOT(dev->devfn) == 4 && pin == 2) { + /* VT6212 INTB */ + irq = IRQ_IOP32X_XINT0; + } else if (PCI_SLOT(dev->devfn) == 4 && pin == 3) { + /* VT6212 INTC */ + irq = IRQ_IOP32X_XINT2; + } else if (PCI_SLOT(dev->devfn) == 5) { + /* Mini-PCI slot */ + irq = IRQ_IOP32X_XINT3; + } else { + printk(KERN_ERR "n2100_pci_map_irq() called for unknown " + "device PCI:%d:%d:%d\n", dev->bus->number, + PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + irq = -1; + } + + return irq; +} + +static struct hw_pci n2100_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iop3xx_pci_setup, + .preinit = iop3xx_pci_preinit, + .scan = iop3xx_pci_scan_bus, + .map_irq = n2100_pci_map_irq, +}; + +static int __init n2100_pci_init(void) +{ + if (machine_is_n2100()) + pci_common_init(&n2100_pci); + + return 0; +} + +subsys_initcall(n2100_pci_init); + + +/* + * N2100 machine initialisation. + */ +static struct physmap_flash_data n2100_flash_data = { + .width = 2, +}; + +static struct resource n2100_flash_resource = { + .start = 0xf0000000, + .end = 0xf0ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device n2100_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &n2100_flash_data, + }, + .num_resources = 1, + .resource = &n2100_flash_resource, +}; + + +static struct plat_serial8250_port n2100_serial_port[] = { + { + .mapbase = N2100_UART, + .membase = (char *)N2100_UART, + .irq = 0, + .flags = UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 0, + .uartclk = 1843200, + }, + { }, +}; + +static struct resource n2100_uart_resource = { + .start = N2100_UART, + .end = N2100_UART + 7, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device n2100_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = n2100_serial_port, + }, + .num_resources = 1, + .resource = &n2100_uart_resource, +}; + + +/* + * Pull PCA9532 GPIO #8 low to power off the machine. + */ +static void n2100_power_off(void) +{ + local_irq_disable(); + + /* Start condition, I2C address of PCA9532, write transaction. */ + *IOP3XX_IDBR0 = 0xc0; + *IOP3XX_ICR0 = 0xe9; + mdelay(1); + + /* Write address 0x08. */ + *IOP3XX_IDBR0 = 0x08; + *IOP3XX_ICR0 = 0xe8; + mdelay(1); + + /* Write data 0x01, stop condition. */ + *IOP3XX_IDBR0 = 0x01; + *IOP3XX_ICR0 = 0xea; + + while (1) + ; +} + + +static struct timer_list power_button_poll_timer; + +static void power_button_poll(unsigned long dummy) +{ + if (gpio_line_get(N2100_POWER_BUTTON) == 0) { + ctrl_alt_del(); + return; + } + + power_button_poll_timer.expires = jiffies + (HZ / 10); + add_timer(&power_button_poll_timer); +} + + +static void __init n2100_init_machine(void) +{ + platform_device_register(&iop3xx_i2c0_device); + platform_device_register(&n2100_flash_device); + platform_device_register(&n2100_serial_device); + + pm_power_off = n2100_power_off; + + init_timer(&power_button_poll_timer); + power_button_poll_timer.function = power_button_poll; + power_button_poll_timer.expires = jiffies + (HZ / 10); + add_timer(&power_button_poll_timer); +} + +MACHINE_START(N2100, "Thecus N2100") + /* Maintainer: Lennert Buytenhek */ + .phys_io = N2100_UART, + .io_pg_offst = ((N2100_UART) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = n2100_map_io, + .init_irq = iop32x_init_irq, + .timer = &n2100_timer, + .init_machine = n2100_init_machine, +MACHINE_END diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h index 6a3001f2f7e0..c6f58b91ddbc 100644 --- a/include/asm-arm/arch-iop32x/hardware.h +++ b/include/asm-arm/arch-iop32x/hardware.h @@ -37,6 +37,7 @@ void iop32x_init_irq(void); */ #include "iq80321.h" #include "iq31244.h" +#include "n2100.h" #endif diff --git a/include/asm-arm/arch-iop32x/n2100.h b/include/asm-arm/arch-iop32x/n2100.h new file mode 100644 index 000000000000..fed31a648425 --- /dev/null +++ b/include/asm-arm/arch-iop32x/n2100.h @@ -0,0 +1,19 @@ +/* + * include/asm/arch-iop32x/n2100.h + * + * Thecus N2100 board registers + */ + +#ifndef __N2100_H +#define __N2100_H + +#define N2100_UART 0xfe800000 /* UART */ + +#define N2100_COPY_BUTTON IOP3XX_GPIO_LINE(0) +#define N2100_PCA9532_RESET IOP3XX_GPIO_LINE(2) +#define N2100_RESET_BUTTON IOP3XX_GPIO_LINE(3) +#define N2100_HARDWARE_RESET IOP3XX_GPIO_LINE(4) +#define N2100_POWER_BUTTON IOP3XX_GPIO_LINE(5) + + +#endif diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h index c65ede3e627a..17b7eb7e9c0d 100644 --- a/include/asm-arm/arch-iop32x/system.h +++ b/include/asm-arm/arch-iop32x/system.h @@ -8,6 +8,8 @@ * published by the Free Software Foundation. */ +#include + static inline void arch_idle(void) { cpu_do_idle(); @@ -15,6 +17,15 @@ static inline void arch_idle(void) static inline void arch_reset(char mode) { + local_irq_disable(); + + if (machine_is_n2100()) { + gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW); + gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT); + while (1) + ; + } + *IOP3XX_PCSR = 0x30; /* Jump into ROM at address 0 */ -- cgit v1.2.3 From 0c92e830bd39f3e6cf7b151dffecafbdc623496c Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 21 Sep 2006 02:46:03 +0100 Subject: [ARM] 3851/1: iop3xx: add io-data glantank support Add support for the IO-Data GLAN Tank, from Martin Michlmayr. Signed-off-by: Martin Michlmayr Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/configs/iop32x_defconfig | 1 + arch/arm/mach-iop32x/Kconfig | 7 ++ arch/arm/mach-iop32x/Makefile | 1 + arch/arm/mach-iop32x/glantank.c | 195 +++++++++++++++++++++++++++++++++ arch/arm/mach-iop32x/irq.c | 3 +- include/asm-arm/arch-iop32x/glantank.h | 13 +++ include/asm-arm/arch-iop32x/hardware.h | 1 + 7 files changed, 220 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-iop32x/glantank.c create mode 100644 include/asm-arm/arch-iop32x/glantank.h (limited to 'include') diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig index af3b40c0508a..0d67f66e78c2 100644 --- a/arch/arm/configs/iop32x_defconfig +++ b/arch/arm/configs/iop32x_defconfig @@ -126,6 +126,7 @@ CONFIG_ARCH_IOP32X=y # # IOP32x Platform Types # +CONFIG_MACH_GLANTANK=y CONFIG_ARCH_IQ80321=y CONFIG_ARCH_IQ31244=y CONFIG_MACH_N2100=y diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index 0a397a4a6ac9..c072d94070da 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig @@ -4,6 +4,13 @@ menu "IOP32x Implementation Options" comment "IOP32x Platform Types" +config MACH_GLANTANK + bool "Enable support for the IO-Data GLAN Tank" + help + Say Y here if you want to run your kernel on the GLAN Tank + NAS appliance or machines from IO-Data's HDL-Gxxx, HDL-GWxxx + and HDL-GZxxx series. + config ARCH_IQ80321 bool "Enable support for IQ80321" help diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile index 9c62470cd4f5..7b05b37e1f94 100644 --- a/arch/arm/mach-iop32x/Makefile +++ b/arch/arm/mach-iop32x/Makefile @@ -7,6 +7,7 @@ obj-m := obj-n := obj- := +obj-$(CONFIG_MACH_GLANTANK) += glantank.o obj-$(CONFIG_ARCH_IQ80321) += iq80321.o obj-$(CONFIG_ARCH_IQ31244) += iq31244.o obj-$(CONFIG_MACH_N2100) += n2100.o diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c new file mode 100644 index 000000000000..b9b765057dbe --- /dev/null +++ b/arch/arm/mach-iop32x/glantank.c @@ -0,0 +1,195 @@ +/* + * arch/arm/mach-iop32x/glantank.c + * + * Board support code for the GLAN Tank. + * + * Copyright (C) 2006 Martin Michlmayr + * Copyright (C) 2006 Lennert Buytenhek + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * GLAN Tank timer tick configuration. + */ +static void __init glantank_timer_init(void) +{ + /* 33.333 MHz crystal. */ + iop3xx_init_time(200000000); +} + +static struct sys_timer glantank_timer = { + .init = glantank_timer_init, + .offset = iop3xx_gettimeoffset, +}; + + +/* + * GLAN Tank I/O. + */ +static struct map_desc glantank_io_desc[] __initdata = { + { /* on-board devices */ + .virtual = GLANTANK_UART, + .pfn = __phys_to_pfn(GLANTANK_UART), + .length = 0x00100000, + .type = MT_DEVICE + }, +}; + +void __init glantank_map_io(void) +{ + iop3xx_map_io(); + iotable_init(glantank_io_desc, ARRAY_SIZE(glantank_io_desc)); +} + + +/* + * GLAN Tank PCI. + */ +#define INTA IRQ_IOP32X_XINT0 +#define INTB IRQ_IOP32X_XINT1 +#define INTC IRQ_IOP32X_XINT2 +#define INTD IRQ_IOP32X_XINT3 + +static inline int __init +glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + static int pci_irq_table[][4] = { + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + {INTD, INTD, INTD, INTD}, /* UART (8250) */ + {INTA, INTA, INTA, INTA}, /* Ethernet (E1000) */ + {INTB, INTB, INTB, INTB}, /* IDE (AEC6280R) */ + {INTC, INTC, INTC, INTC}, /* USB (NEC) */ + }; + + BUG_ON(pin < 1 || pin > 4); + + return pci_irq_table[slot % 4][pin - 1]; +} + +static struct hw_pci glantank_pci __initdata = { + .swizzle = pci_std_swizzle, + .nr_controllers = 1, + .setup = iop3xx_pci_setup, + .preinit = iop3xx_pci_preinit, + .scan = iop3xx_pci_scan_bus, + .map_irq = glantank_pci_map_irq, +}; + +static int __init glantank_pci_init(void) +{ + if (machine_is_glantank()) + pci_common_init(&glantank_pci); + + return 0; +} + +subsys_initcall(glantank_pci_init); + + +/* + * GLAN Tank machine initialization. + */ +static struct physmap_flash_data glantank_flash_data = { + .width = 1, +}; + +static struct resource glantank_flash_resource = { + .start = 0xf0000000, + .end = 0xf007ffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device glantank_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &glantank_flash_data, + }, + .num_resources = 1, + .resource = &glantank_flash_resource, +}; + +static struct plat_serial8250_port glantank_serial_port[] = { + { + .mapbase = GLANTANK_UART, + .membase = (char *)GLANTANK_UART, + .irq = IRQ_IOP32X_XINT3, + .flags = UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 0, + .uartclk = 1843200, + }, + { }, +}; + +static struct resource glantank_uart_resource = { + .start = GLANTANK_UART, + .end = GLANTANK_UART + 7, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device glantank_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = glantank_serial_port, + }, + .num_resources = 1, + .resource = &glantank_uart_resource, +}; + +static void glantank_power_off(void) +{ + __raw_writeb(0x01, 0xfe8d0004); + + while (1) + ; +} + +static void __init glantank_init_machine(void) +{ + platform_device_register(&iop3xx_i2c0_device); + platform_device_register(&iop3xx_i2c1_device); + platform_device_register(&glantank_flash_device); + platform_device_register(&glantank_serial_device); + + pm_power_off = glantank_power_off; +} + +MACHINE_START(GLANTANK, "GLAN Tank") + /* Maintainer: Lennert Buytenhek */ + .phys_io = GLANTANK_UART, + .io_pg_offst = ((GLANTANK_UART) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = glantank_map_io, + .init_irq = iop32x_init_irq, + .timer = &glantank_timer, + .init_machine = glantank_init_machine, +MACHINE_END diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 17fb94e6e29f..69d6302f40cf 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -62,7 +62,8 @@ void __init iop32x_init_irq(void) intctl_write(0); intstr_write(0); - if (machine_is_iq80321() || + if (machine_is_glantank() || + machine_is_iq80321() || machine_is_iq31244() || machine_is_n2100()) *IOP3XX_PCIIRSR = 0x0f; diff --git a/include/asm-arm/arch-iop32x/glantank.h b/include/asm-arm/arch-iop32x/glantank.h new file mode 100644 index 000000000000..3b065618dd00 --- /dev/null +++ b/include/asm-arm/arch-iop32x/glantank.h @@ -0,0 +1,13 @@ +/* + * include/asm/arch-iop32x/glantank.h + * + * IO-Data GLAN Tank board registers + */ + +#ifndef __GLANTANK_H +#define __GLANTANK_H + +#define GLANTANK_UART 0xfe800000 /* UART */ + + +#endif diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h index c6f58b91ddbc..6556ed5eee31 100644 --- a/include/asm-arm/arch-iop32x/hardware.h +++ b/include/asm-arm/arch-iop32x/hardware.h @@ -35,6 +35,7 @@ void iop32x_init_irq(void); /* * Board specific bits */ +#include "glantank.h" #include "iq80321.h" #include "iq31244.h" #include "n2100.h" -- cgit v1.2.3 From e7cc2c59cc83558fc26f17eee3c8f901119f0a7c Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 21 Sep 2006 03:35:20 +0100 Subject: [ARM] 3852/1: convert atomic bitops and __xchg over to raw_local_irq_{save,restore} Thomas Gleixner noticed that bitops.h should also use the raw_* irq disable/enable variants, and __xchg needs them as well. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/bitops.h | 24 ++++++++++++------------ include/asm-arm/system.h | 8 ++++---- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 0ac54b1a8bad..b41831b6432f 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -37,9 +37,9 @@ static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long * p += bit >> 5; - local_irq_save(flags); + raw_local_irq_save(flags); *p |= mask; - local_irq_restore(flags); + raw_local_irq_restore(flags); } static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p) @@ -49,9 +49,9 @@ static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long p += bit >> 5; - local_irq_save(flags); + raw_local_irq_save(flags); *p &= ~mask; - local_irq_restore(flags); + raw_local_irq_restore(flags); } static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p) @@ -61,9 +61,9 @@ static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned lon p += bit >> 5; - local_irq_save(flags); + raw_local_irq_save(flags); *p ^= mask; - local_irq_restore(flags); + raw_local_irq_restore(flags); } static inline int @@ -75,10 +75,10 @@ ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p) p += bit >> 5; - local_irq_save(flags); + raw_local_irq_save(flags); res = *p; *p = res | mask; - local_irq_restore(flags); + raw_local_irq_restore(flags); return res & mask; } @@ -92,10 +92,10 @@ ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p) p += bit >> 5; - local_irq_save(flags); + raw_local_irq_save(flags); res = *p; *p = res & ~mask; - local_irq_restore(flags); + raw_local_irq_restore(flags); return res & mask; } @@ -109,10 +109,10 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) p += bit >> 5; - local_irq_save(flags); + raw_local_irq_save(flags); res = *p; *p = res ^ mask; - local_irq_restore(flags); + raw_local_irq_restore(flags); return res & mask; } diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 174ff52661b0..c19c5b009f71 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -282,17 +282,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size #error SMP is not supported on this platform #endif case 1: - local_irq_save(flags); + raw_local_irq_save(flags); ret = *(volatile unsigned char *)ptr; *(volatile unsigned char *)ptr = x; - local_irq_restore(flags); + raw_local_irq_restore(flags); break; case 4: - local_irq_save(flags); + raw_local_irq_save(flags); ret = *(volatile unsigned long *)ptr; *(volatile unsigned long *)ptr = x; - local_irq_restore(flags); + raw_local_irq_restore(flags); break; #else case 1: -- cgit v1.2.3 From 93bda4c0214441b0bb03b61c2bf1d6727896a750 Mon Sep 17 00:00:00 2001 From: Samuel Ortiz Date: Mon, 25 Sep 2006 12:41:22 +0300 Subject: ARM: OMAP: Added OMAP24xx camera IRQ definition Signed-off-by: Samuel Ortiz Signed-off-by: Juha Yrjola Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/irqs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 2542495d8a43..636f21cae3ee 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h @@ -237,6 +237,7 @@ #define INT_24XX_SDMA_IRQ1 13 #define INT_24XX_SDMA_IRQ2 14 #define INT_24XX_SDMA_IRQ3 15 +#define INT_24XX_CAM_IRQ 24 #define INT_24XX_DSS_IRQ 25 #define INT_24XX_GPIO_BANK1 29 #define INT_24XX_GPIO_BANK2 30 -- cgit v1.2.3 From abc45e1d69542281fb2b40968e5d112f51976623 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Mon, 25 Sep 2006 12:41:25 +0300 Subject: ARM: OMAP: Apollon MMC support Apollon board MMC supports on OMAP2 TODO: We have to check MMC on H4 Signed-off-by: Kyungmin Park Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-apollon.c | 7 +++++-- arch/arm/mach-omap2/mux.c | 14 ++++++++++++++ arch/arm/plat-omap/devices.c | 20 +++++++++++++++++--- include/asm-arm/arch-omap/irqs.h | 1 + include/asm-arm/arch-omap/mux.h | 14 ++++++++++++++ 5 files changed, 51 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 7993b7bae2bd..2db6b732b084 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -166,8 +166,8 @@ static struct omap_uart_config apollon_uart_config __initdata = { static struct omap_mmc_config apollon_mmc_config __initdata = { .mmc [0] = { - .enabled = 0, - .wire4 = 0, + .enabled = 1, + .wire4 = 1, .wp_pin = -1, .power_pin = -1, .switch_pin = -1, @@ -257,6 +257,9 @@ static void __init omap_apollon_init(void) /* REVISIT: where's the correct place */ omap_cfg_reg(W19_24XX_SYS_NIRQ); + /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ + CONTROL_DEVCONF |= (1 << 24); + /* * Make sure the serial ports are muxed on at this point. * You have to mux them off in device drivers later on diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 60ef084faffd..f538d0fdb13c 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -104,6 +104,20 @@ MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1) MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) +/* MMC/SDIO */ +MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1) +MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1) +MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1) +MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1) +MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1) +MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1) +MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1) +MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1) +MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1) +MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1) +MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1) +MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1) + /* Keypad GPIO*/ MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1) MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1) diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 1812f237d12f..dbc3f44e07a6 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -148,7 +148,7 @@ static inline void omap_init_kp(void) {} #ifdef CONFIG_ARCH_OMAP24XX #define OMAP_MMC1_BASE 0x4809c000 -#define OMAP_MMC1_INT 83 +#define OMAP_MMC1_INT INT_24XX_MMC_IRQ #else #define OMAP_MMC1_BASE 0xfffb7800 #define OMAP_MMC1_INT INT_MMC @@ -225,7 +225,14 @@ static void __init omap_init_mmc(void) /* block 1 is always available and has just one pinout option */ mmc = &mmc_conf->mmc[0]; if (mmc->enabled) { - if (!cpu_is_omap24xx()) { + if (cpu_is_omap24xx()) { + omap_cfg_reg(H18_24XX_MMC_CMD); + omap_cfg_reg(H15_24XX_MMC_CLKI); + omap_cfg_reg(G19_24XX_MMC_CLKO); + omap_cfg_reg(F20_24XX_MMC_DAT0); + omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); + omap_cfg_reg(G18_24XX_MMC_CMD_DIR); + } else { omap_cfg_reg(MMC_CMD); omap_cfg_reg(MMC_CLK); omap_cfg_reg(MMC_DAT0); @@ -236,7 +243,14 @@ static void __init omap_init_mmc(void) } } if (mmc->wire4) { - if (!cpu_is_omap24xx()) { + if (cpu_is_omap24xx()) { + omap_cfg_reg(H14_24XX_MMC_DAT1); + omap_cfg_reg(E19_24XX_MMC_DAT2); + omap_cfg_reg(D19_24XX_MMC_DAT3); + omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); + omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); + omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); + } else { omap_cfg_reg(MMC_DAT1); /* NOTE: DAT2 can be on W10 (here) or M15 */ if (!mmc->nomux) diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 636f21cae3ee..c5bb05a69b81 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h @@ -262,6 +262,7 @@ #define INT_24XX_UART1_IRQ 72 #define INT_24XX_UART2_IRQ 73 #define INT_24XX_UART3_IRQ 74 +#define INT_24XX_MMC_IRQ 83 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and * 16 MPUIO lines */ diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 679869c5e68f..a6df97c11839 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -461,6 +461,20 @@ enum omap24xx_index { K15_24XX_UART3_TX, K14_24XX_UART3_RX, + /* MMC/SDIO */ + G19_24XX_MMC_CLKO, + H18_24XX_MMC_CMD, + F20_24XX_MMC_DAT0, + H14_24XX_MMC_DAT1, + E19_24XX_MMC_DAT2, + D19_24XX_MMC_DAT3, + F19_24XX_MMC_DAT_DIR0, + E20_24XX_MMC_DAT_DIR1, + F18_24XX_MMC_DAT_DIR2, + E18_24XX_MMC_DAT_DIR3, + G18_24XX_MMC_CMD_DIR, + H15_24XX_MMC_CLKI, + /* Keypad GPIO*/ T19_24XX_KBR0, R19_24XX_KBR1, -- cgit v1.2.3 From 75a1d10e2f110380adaa9b993fd417537e2f85ba Mon Sep 17 00:00:00 2001 From: Mark Howell Date: Mon, 25 Sep 2006 12:41:29 +0300 Subject: ARM: OMAP: mux: add config for 16xx SPI pins This patch adds pin mux info for the SPI master/slave interface on OMAP16xx. Data from OMAP 1611/1612 TRM and errata. Works for me on my 1611/H2 with current git kernel. Signed-off-by: Mark Howell Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/mux.c | 11 +++++++++++ include/asm-arm/arch-omap/mux.h | 11 +++++++++++ 2 files changed, 22 insertions(+) (limited to 'include') diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index fa74ef7af15f..5432335bc493 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -199,6 +199,17 @@ MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1) MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1) MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1) +/* OMAP-1610 SPI */ +MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1) +MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1) +MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1) +MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1) +MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1) +MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1) +MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1) +MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1) +MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1) + /* OMAP-1610 Flash */ MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1) MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1) diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index a6df97c11839..828cc5c114e1 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -320,6 +320,17 @@ enum omap1xxx_index { P15_1610_UWIRE_CS3, N15_1610_UWIRE_CS1, + /* OMAP-1610 SPI */ + U19_1610_SPIF_SCK, + U18_1610_SPIF_DIN, + P20_1610_SPIF_DIN, + W21_1610_SPIF_DOUT, + R18_1610_SPIF_DOUT, + N14_1610_SPIF_CS0, + N15_1610_SPIF_CS1, + T19_1610_SPIF_CS2, + P15_1610_SPIF_CS3, + /* OMAP-1610 Flash */ L3_1610_FLASH_CS2B_OE, M8_1610_FLASH_CS2B_WE, -- cgit v1.2.3 From 2eaff915744b6c8db7770fa9e841fd1c0105fb0b Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Mon, 25 Sep 2006 12:41:31 +0300 Subject: ARM: OMAP: Add some extra #defines for Amstrad Delta This patch adds some further #defines regarding GPIOs and latch bits for the Amstrad Delta; the drivers that use them will be submitted at a later date but there's no reason not to have the information already there and available for use. Signed-off-by: Jonathan McDowell Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/board-ams-delta.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-omap/board-ams-delta.h b/include/asm-arm/arch-omap/board-ams-delta.h index 0070f6d3b75c..9aee15d97145 100644 --- a/include/asm-arm/arch-omap/board-ams-delta.h +++ b/include/asm-arm/arch-omap/board-ams-delta.h @@ -50,9 +50,20 @@ #define AMS_DELTA_LATCH2_NAND_NWE 0x0020 #define AMS_DELTA_LATCH2_NAND_ALE 0x0040 #define AMS_DELTA_LATCH2_NAND_CLE 0x0080 +#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100 +#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200 +#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400 +#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800 #define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000 #define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000 +#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0 +#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1 +#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2 +#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4 +#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6 +#define AMS_DELTA_GPIO_PIN_SCARD_IO 7 +#define AMS_DELTA_GPIO_PIN_CONFIG 11 #define AMS_DELTA_GPIO_PIN_NAND_RB 12 #ifndef __ASSEMBLY__ -- cgit v1.2.3 From f37e4580c409e290f6e482007c3573cdb4470bf9 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 25 Sep 2006 12:41:33 +0300 Subject: ARM: OMAP2: Dynamic allocator for GPMC memory space Add support for assigning memory regions dynamically to peripherals attached to GPMC interface. Platform specific code should now call gpmc_cs_request to get a free GPMC memory region instead of using a fixed address. Make the H4 and Apollon platform initialization use the new API. Signed-off-by: Imre Deak Signed-off-by: Juha Yrjola Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 180 ++++++++++++++++++++++++++++++++++++++- include/asm-arm/arch-omap/gpmc.h | 4 +- 2 files changed, 180 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index c7a48f921fef..f4f04d87df32 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include @@ -41,6 +43,19 @@ #define GPMC_CS0 0x60 #define GPMC_CS_SIZE 0x30 +#define GPMC_CS_NUM 8 +#define GPMC_MEM_START 0x00000000 +#define GPMC_MEM_END 0x3FFFFFFF +#define BOOT_ROM_SPACE 0x100000 /* 1MB */ + +#define GPMC_CHUNK_SHIFT 24 /* 16 MB */ +#define GPMC_SECTION_SHIFT 28 /* 128 MB */ + +static struct resource gpmc_mem_root; +static struct resource gpmc_cs_mem[GPMC_CS_NUM]; +static spinlock_t gpmc_mem_lock = SPIN_LOCK_UNLOCKED; +static unsigned gpmc_cs_map; + static void __iomem *gpmc_base = (void __iomem *) IO_ADDRESS(GPMC_BASE); static void __iomem *gpmc_cs_base = @@ -187,9 +202,168 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) return 0; } -unsigned long gpmc_cs_get_base_addr(int cs) +static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) +{ + u32 l; + u32 mask; + + mask = (1 << GPMC_SECTION_SHIFT) - size; + l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + l &= ~0x3f; + l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; + l &= ~(0x0f << 8); + l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; + l |= 1 << 6; /* CSVALID */ + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); +} + +static void gpmc_cs_disable_mem(int cs) +{ + u32 l; + + l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + l &= ~(1 << 6); /* CSVALID */ + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); +} + +static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) +{ + u32 l; + u32 mask; + + l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; + mask = (l >> 8) & 0x0f; + *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); +} + +static int gpmc_cs_mem_enabled(int cs) +{ + u32 l; + + l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + return l & (1 << 6); +} + +static void gpmc_cs_set_reserved(int cs, int reserved) { - return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24; + gpmc_cs_map &= ~(1 << cs); + gpmc_cs_map |= (reserved ? 1 : 0) << cs; +} + +static int gpmc_cs_reserved(int cs) +{ + return gpmc_cs_map & (1 << cs); +} + +static unsigned long gpmc_mem_align(unsigned long size) +{ + int order; + + size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); + order = GPMC_CHUNK_SHIFT - 1; + do { + size >>= 1; + order++; + } while (size); + size = 1 << order; + return size; +} + +static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) +{ + struct resource *res = &gpmc_cs_mem[cs]; + int r; + + size = gpmc_mem_align(size); + spin_lock(&gpmc_mem_lock); + res->start = base; + res->end = base + size - 1; + r = request_resource(&gpmc_mem_root, res); + spin_unlock(&gpmc_mem_lock); + + return r; +} + +int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) +{ + struct resource *res = &gpmc_cs_mem[cs]; + int r = -1; + + if (cs > GPMC_CS_NUM) + return -ENODEV; + + size = gpmc_mem_align(size); + if (size > (1 << GPMC_SECTION_SHIFT)) + return -ENOMEM; + + spin_lock(&gpmc_mem_lock); + if (gpmc_cs_reserved(cs)) { + r = -EBUSY; + goto out; + } + if (gpmc_cs_mem_enabled(cs)) + r = adjust_resource(res, res->start & ~(size - 1), size); + if (r < 0) + r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, + size, NULL, NULL); + if (r < 0) + goto out; + + gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1); + *base = res->start; + gpmc_cs_set_reserved(cs, 1); +out: + spin_unlock(&gpmc_mem_lock); + return r; +} + +void gpmc_cs_free(int cs) +{ + spin_lock(&gpmc_mem_lock); + if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) { + printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); + BUG(); + spin_unlock(&gpmc_mem_lock); + return; + } + gpmc_cs_disable_mem(cs); + release_resource(&gpmc_cs_mem[cs]); + gpmc_cs_set_reserved(cs, 0); + spin_unlock(&gpmc_mem_lock); +} + +void __init gpmc_mem_init(void) +{ + int cs; + unsigned long boot_rom_space = 0; + + if (cpu_is_omap242x()) { + u32 l; + l = omap_readl(OMAP242X_CONTROL_STATUS); + /* In case of internal boot the 1st MB is redirected to the + * boot ROM memory space. + */ + if (l & (1 << 3)) + boot_rom_space = BOOT_ROM_SPACE; + } else + /* We assume internal boot if the mode can't be + * determined. + */ + boot_rom_space = BOOT_ROM_SPACE; + gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; + gpmc_mem_root.end = GPMC_MEM_END; + + /* Reserve all regions that has been set up by bootloader */ + for (cs = 0; cs < GPMC_CS_NUM; cs++) { + u32 base, size; + + if (!gpmc_cs_mem_enabled(cs)) + continue; + gpmc_cs_get_memconf(cs, &base, &size); + if (gpmc_cs_insert_mem(cs, base, size) < 0) + BUG(); + } } void __init gpmc_init(void) @@ -206,4 +380,6 @@ void __init gpmc_init(void) l &= 0x03 << 3; l |= (0x02 << 3) | (1 << 0); gpmc_write_reg(GPMC_SYSCONFIG, l); + + gpmc_mem_init(); } diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h index 1a0a5207822d..7c03ef6c14c4 100644 --- a/include/asm-arm/arch-omap/gpmc.h +++ b/include/asm-arm/arch-omap/gpmc.h @@ -85,7 +85,7 @@ extern void gpmc_cs_write_reg(int cs, int idx, u32 val); extern u32 gpmc_cs_read_reg(int cs, int idx); extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); -extern unsigned long gpmc_cs_get_base_addr(int cs); - +extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); +extern void gpmc_cs_free(int cs); #endif -- cgit v1.2.3 From 123e9a5573098dbb10194c18d6d575620d0e94f3 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 25 Sep 2006 12:41:34 +0300 Subject: ARM: OMAP: DMA source and destination addresses are unsigned Also export some omap24xx specific DMA functions. Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dma.c | 2 ++ include/asm-arm/arch-omap/dma.h | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 9948d7a26339..0889769cb225 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1422,11 +1422,13 @@ EXPORT_SYMBOL(omap_request_dma); EXPORT_SYMBOL(omap_free_dma); EXPORT_SYMBOL(omap_start_dma); EXPORT_SYMBOL(omap_stop_dma); +EXPORT_SYMBOL(omap_set_dma_callback); EXPORT_SYMBOL(omap_enable_dma_irq); EXPORT_SYMBOL(omap_disable_dma_irq); EXPORT_SYMBOL(omap_set_dma_transfer_params); EXPORT_SYMBOL(omap_set_dma_color_mode); +EXPORT_SYMBOL(omap_set_dma_write_mode); EXPORT_SYMBOL(omap_set_dma_src_params); EXPORT_SYMBOL(omap_set_dma_src_index); diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index 1b1b02307e77..33cd48d9a853 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -338,13 +338,13 @@ struct omap_dma_channel_params { int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ int src_amode; /* constant , post increment, indexed , double indexed */ - int src_start; /* source address : physical */ + unsigned long src_start; /* source address : physical */ int src_ei; /* source element index */ int src_fi; /* source frame index */ int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ int dst_amode; /* constant , post increment, indexed , double indexed */ - int dst_start; /* source address : physical */ + unsigned long dst_start; /* source address : physical */ int dst_ei; /* source element index */ int dst_fi; /* source frame index */ -- cgit v1.2.3 From 12583a70ac6b6641905e37fdd61a7f711fb4ce2b Mon Sep 17 00:00:00 2001 From: Timo Teras Date: Mon, 25 Sep 2006 12:41:42 +0300 Subject: ARM: OMAP: Add enable/disable functions for dmtimer Add enable/disable functions which effectively control the GPT iclk and fclk. Signed-off-by: Timo Teras Signed-off-by: Juha Yrjola Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dmtimer.c | 73 ++++++++++++++++--------------------- include/asm-arm/arch-omap/dmtimer.h | 2 + 2 files changed, 33 insertions(+), 42 deletions(-) (limited to 'include') diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index fb2a23e7c172..8d6197497a74 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -75,6 +75,7 @@ struct omap_dm_timer { #endif void __iomem *io_base; unsigned reserved:1; + unsigned enabled:1; }; #ifdef CONFIG_ARCH_OMAP1 @@ -164,7 +165,7 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer) omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); omap_dm_timer_wait_for_reset(timer); } - omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK); + omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); /* Set to smart-idle mode */ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG); @@ -174,15 +175,8 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer) static void omap_dm_timer_prepare(struct omap_dm_timer *timer) { - omap_dm_clk_enable(timer->fclk); - omap_dm_clk_enable(timer->iclk); - + omap_dm_timer_enable(timer); omap_dm_timer_reset(timer); - - /* Leave iclk enabled for GPT1 as it is needed for the - * system timer to work properly. */ - if (timer != &dm_timers[0]) - omap_dm_clk_disable(timer->iclk); } struct omap_dm_timer *omap_dm_timer_request(void) @@ -233,18 +227,36 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) void omap_dm_timer_free(struct omap_dm_timer *timer) { - omap_dm_clk_enable(timer->iclk); + omap_dm_timer_enable(timer); omap_dm_timer_reset(timer); - omap_dm_clk_disable(timer->iclk); - - if (timer == &dm_timers[0]) - omap_dm_clk_disable(timer->iclk); - omap_dm_clk_disable(timer->fclk); + omap_dm_timer_disable(timer); WARN_ON(!timer->reserved); timer->reserved = 0; } +void omap_dm_timer_enable(struct omap_dm_timer *timer) +{ + if (timer->enabled) + return; + + omap_dm_clk_enable(timer->fclk); + omap_dm_clk_enable(timer->iclk); + + timer->enabled = 1; +} + +void omap_dm_timer_disable(struct omap_dm_timer *timer) +{ + if (!timer->enabled) + return; + + omap_dm_clk_disable(timer->iclk); + omap_dm_clk_disable(timer->fclk); + + timer->enabled = 0; +} + int omap_dm_timer_get_irq(struct omap_dm_timer *timer) { return timer->irq; @@ -301,35 +313,29 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) void omap_dm_timer_trigger(struct omap_dm_timer *timer) { - omap_dm_clk_enable(timer->iclk); omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); - omap_dm_clk_disable(timer->iclk); } void omap_dm_timer_start(struct omap_dm_timer *timer) { u32 l; - omap_dm_clk_enable(timer->iclk); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (!(l & OMAP_TIMER_CTRL_ST)) { l |= OMAP_TIMER_CTRL_ST; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); } - omap_dm_clk_disable(timer->iclk); } void omap_dm_timer_stop(struct omap_dm_timer *timer) { u32 l; - omap_dm_clk_enable(timer->iclk); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (l & OMAP_TIMER_CTRL_ST) { l &= ~0x1; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); } - omap_dm_clk_disable(timer->iclk); } #ifdef CONFIG_ARCH_OMAP1 @@ -367,7 +373,6 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, { u32 l; - omap_dm_clk_enable(timer->iclk); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (autoreload) l |= OMAP_TIMER_CTRL_AR; @@ -376,7 +381,6 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); - omap_dm_clk_disable(timer->iclk); } void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, @@ -384,7 +388,6 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, { u32 l; - omap_dm_clk_enable(timer->iclk); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (enable) l |= OMAP_TIMER_CTRL_CE; @@ -392,7 +395,6 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, l &= ~OMAP_TIMER_CTRL_CE; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); - omap_dm_clk_disable(timer->iclk); } @@ -401,7 +403,6 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, { u32 l; - omap_dm_clk_enable(timer->iclk); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | OMAP_TIMER_CTRL_PT | (0x03 << 10)); @@ -411,14 +412,12 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, l |= OMAP_TIMER_CTRL_PT; l |= trigger << 10; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); - omap_dm_clk_disable(timer->iclk); } void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) { u32 l; - omap_dm_clk_enable(timer->iclk); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); if (prescaler >= 0x00 && prescaler <= 0x07) { @@ -426,51 +425,40 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) l |= prescaler << 2; } omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); - omap_dm_clk_disable(timer->iclk); } void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value) { - omap_dm_clk_enable(timer->iclk); omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); - omap_dm_clk_disable(timer->iclk); } unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) { unsigned int l; - omap_dm_clk_enable(timer->iclk); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); - omap_dm_clk_disable(timer->iclk); return l; } void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) { - omap_dm_clk_enable(timer->iclk); omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); - omap_dm_clk_disable(timer->iclk); } unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) { unsigned int l; - omap_dm_clk_enable(timer->iclk); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG); - omap_dm_clk_disable(timer->iclk); return l; } void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) { - omap_dm_clk_enable(timer->iclk); omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); - omap_dm_clk_disable(timer->iclk); } int omap_dm_timers_active(void) @@ -481,13 +469,14 @@ int omap_dm_timers_active(void) struct omap_dm_timer *timer; timer = &dm_timers[i]; - omap_dm_clk_enable(timer->iclk); + + if (!timer->enabled) + continue; + if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & OMAP_TIMER_CTRL_ST) { - omap_dm_clk_disable(timer->iclk); return 1; } - omap_dm_clk_disable(timer->iclk); } return 0; } diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h index 7a289ff07404..b5f3a71b899d 100644 --- a/include/asm-arm/arch-omap/dmtimer.h +++ b/include/asm-arm/arch-omap/dmtimer.h @@ -52,6 +52,8 @@ int omap_dm_timer_init(void); struct omap_dm_timer *omap_dm_timer_request(void); struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); void omap_dm_timer_free(struct omap_dm_timer *timer); +void omap_dm_timer_enable(struct omap_dm_timer *timer); +void omap_dm_timer_disable(struct omap_dm_timer *timer); int omap_dm_timer_get_irq(struct omap_dm_timer *timer); -- cgit v1.2.3 From 709eb3e5ccb304dca011c41456da5ffd246d7271 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 25 Sep 2006 12:45:45 +0300 Subject: ARM: OMAP: Sync DMA with linux-omap tree This patch syncs OMAP DMA code with linux-omap tree. Mostly allow changing DMA callback function and set OMAP2 specific transfer mode. Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dma.c | 85 +++++++++++++++++++++++++++++++---------- include/asm-arm/arch-omap/dma.h | 12 +++++- 2 files changed, 75 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 0889769cb225..1bbb431843ce 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -119,32 +119,41 @@ static void clear_lch_regs(int lch) omap_writew(0, lch_base + i); } -void omap_set_dma_priority(int dst_port, int priority) +void omap_set_dma_priority(int lch, int dst_port, int priority) { unsigned long reg; u32 l; - switch (dst_port) { - case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ - reg = OMAP_TC_OCPT1_PRIOR; - break; - case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ - reg = OMAP_TC_OCPT2_PRIOR; - break; - case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ - reg = OMAP_TC_EMIFF_PRIOR; - break; - case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ - reg = OMAP_TC_EMIFS_PRIOR; - break; - default: - BUG(); - return; + if (cpu_class_is_omap1()) { + switch (dst_port) { + case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ + reg = OMAP_TC_OCPT1_PRIOR; + break; + case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ + reg = OMAP_TC_OCPT2_PRIOR; + break; + case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ + reg = OMAP_TC_EMIFF_PRIOR; + break; + case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ + reg = OMAP_TC_EMIFS_PRIOR; + break; + default: + BUG(); + return; + } + l = omap_readl(reg); + l &= ~(0xf << 8); + l |= (priority & 0xf) << 8; + omap_writel(l, reg); + } + + if (cpu_is_omap24xx()) { + if (priority) + OMAP_DMA_CCR_REG(lch) |= (1 << 6); + else + OMAP_DMA_CCR_REG(lch) &= ~(1 << 6); } - l = omap_readl(reg); - l &= ~(0xf << 8); - l |= (priority & 0xf) << 8; - omap_writel(l, reg); } void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, @@ -234,6 +243,14 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) OMAP1_DMA_LCH_CTRL_REG(lch) = w; } +void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) +{ + if (cpu_is_omap24xx()) { + OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16); + OMAP_DMA_CSDP_REG(lch) |= (mode << 16); + } +} + /* Note that src_port is only for omap1 */ void omap_set_dma_src_params(int lch, int src_port, int src_amode, unsigned long src_start, @@ -697,6 +714,32 @@ void omap_stop_dma(int lch) dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; } +/* + * Allows changing the DMA callback function or data. This may be needed if + * the driver shares a single DMA channel for multiple dma triggers. + */ +int omap_set_dma_callback(int lch, + void (* callback)(int lch, u16 ch_status, void *data), + void *data) +{ + unsigned long flags; + + if (lch < 0) + return -ENODEV; + + spin_lock_irqsave(&dma_chan_lock, flags); + if (dma_chan[lch].dev_id == -1) { + printk(KERN_ERR "DMA callback for not set for free channel\n"); + spin_unlock_irqrestore(&dma_chan_lock, flags); + return -EINVAL; + } + dma_chan[lch].callback = callback; + dma_chan[lch].data = data; + spin_unlock_irqrestore(&dma_chan_lock, flags); + + return 0; +} + /* * Returns current physical source address for the given DMA channel. * If the channel is running the caller must disable interrupts prior calling diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index 33cd48d9a853..d591d0585bba 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -331,6 +331,12 @@ enum omap_dma_color_mode { OMAP_DMA_TRANSPARENT_COPY }; +enum omap_dma_write_mode { + OMAP_DMA_WRITE_NON_POSTED = 0, + OMAP_DMA_WRITE_POSTED, + OMAP_DMA_WRITE_LAST_NON_POSTED +}; + struct omap_dma_channel_params { int data_type; /* data type 8,16,32 */ int elem_count; /* number of elements in a frame */ @@ -356,7 +362,7 @@ struct omap_dma_channel_params { }; -extern void omap_set_dma_priority(int dst_port, int priority); +extern void omap_set_dma_priority(int lch, int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, void (* callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch); @@ -371,6 +377,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type, int dma_trigger, int src_or_dst_synch); extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color); +extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, unsigned long src_start, @@ -394,6 +401,9 @@ extern void omap_set_dma_params(int lch, extern void omap_dma_link_lch (int lch_head, int lch_queue); extern void omap_dma_unlink_lch (int lch_head, int lch_queue); +extern int omap_set_dma_callback(int lch, + void (* callback)(int lch, u16 ch_status, void *data), + void *data); extern dma_addr_t omap_get_dma_src_pos(int lch); extern dma_addr_t omap_get_dma_dst_pos(int lch); extern int omap_get_dma_src_addr_counter(int lch); -- cgit v1.2.3 From 90afd5cb2ac0977c38e83b6b21493da911b242b3 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 25 Sep 2006 13:27:20 +0300 Subject: ARM: OMAP: Sync clocks with linux-omap tree Mostly clean up CONFIG_OMAP_RESET_CLOCKS. Also includes a patch from Imre Deak to make McSPI clocks use id. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/clock.c | 107 +++++++++++++++++--------------------- arch/arm/mach-omap1/clock.h | 14 +++++ arch/arm/mach-omap2/clock.c | 39 ++++++-------- arch/arm/mach-omap2/clock.h | 18 ++++--- arch/arm/plat-omap/clock.c | 25 +++++++++ include/asm-arm/arch-omap/clock.h | 1 + 6 files changed, 117 insertions(+), 87 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index f1958e882e86..638490e62d5f 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -20,6 +20,7 @@ #include #include +#include #include #include @@ -586,77 +587,53 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) *-------------------------------------------------------------------------*/ #ifdef CONFIG_OMAP_RESET_CLOCKS -/* - * Resets some clocks that may be left on from bootloader, - * but leaves serial clocks on. See also omap_late_clk_reset(). - */ -static inline void omap1_early_clk_reset(void) -{ - //omap_writel(0x3 << 29, MOD_CONF_CTRL_0); -} -static int __init omap1_late_clk_reset(void) +static void __init omap1_clk_disable_unused(struct clk *clk) { - /* Turn off all unused clocks */ - struct clk *p; __u32 regval32; - /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ - regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4); - omap_writew(regval32, SOFT_REQ_REG); - omap_writew(0, SOFT_REQ_REG2); - - list_for_each_entry(p, &clocks, node) { - if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) || - p->enable_reg == 0) - continue; - - /* Clocks in the DSP domain need api_ck. Just assume bootloader - * has not enabled any DSP clocks */ - if ((u32)p->enable_reg == DSP_IDLECT2) { - printk(KERN_INFO "Skipping reset check for DSP domain " - "clock \"%s\"\n", p->name); - continue; - } + /* Clocks in the DSP domain need api_ck. Just assume bootloader + * has not enabled any DSP clocks */ + if ((u32)clk->enable_reg == DSP_IDLECT2) { + printk(KERN_INFO "Skipping reset check for DSP domain " + "clock \"%s\"\n", clk->name); + return; + } - /* Is the clock already disabled? */ - if (p->flags & ENABLE_REG_32BIT) { - if (p->flags & VIRTUAL_IO_ADDRESS) - regval32 = __raw_readl(p->enable_reg); - else - regval32 = omap_readl(p->enable_reg); - } else { - if (p->flags & VIRTUAL_IO_ADDRESS) - regval32 = __raw_readw(p->enable_reg); + /* Is the clock already disabled? */ + if (clk->flags & ENABLE_REG_32BIT) { + if (clk->flags & VIRTUAL_IO_ADDRESS) + regval32 = __raw_readl(clk->enable_reg); else - regval32 = omap_readw(p->enable_reg); - } - - if ((regval32 & (1 << p->enable_bit)) == 0) - continue; + regval32 = omap_readl(clk->enable_reg); + } else { + if (clk->flags & VIRTUAL_IO_ADDRESS) + regval32 = __raw_readw(clk->enable_reg); + else + regval32 = omap_readw(clk->enable_reg); + } - /* FIXME: This clock seems to be necessary but no-one - * has asked for its activation. */ - if (p == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera - || p == &ck_dpll1out.clk // FIX: SoSSI, SSR - || p == &arm_gpio_ck // FIX: GPIO code for 1510 - ) { - printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", - p->name); - continue; - } + if ((regval32 & (1 << clk->enable_bit)) == 0) + return; - printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name); - p->disable(p); - printk(" done\n"); + /* FIXME: This clock seems to be necessary but no-one + * has asked for its activation. */ + if (clk == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera + || clk == &ck_dpll1out.clk // FIX: SoSSI, SSR + || clk == &arm_gpio_ck // FIX: GPIO code for 1510 + ) { + printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", + clk->name); + return; } - return 0; + printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); + clk->disable(clk); + printk(" done\n"); } -late_initcall(omap1_late_clk_reset); #else -#define omap1_early_clk_reset() {} +#define omap1_clk_disable_unused NULL #endif static struct clk_functions omap1_clk_functions = { @@ -664,6 +641,7 @@ static struct clk_functions omap1_clk_functions = { .clk_disable = omap1_clk_disable, .clk_round_rate = omap1_clk_round_rate, .clk_set_rate = omap1_clk_set_rate, + .clk_disable_unused = omap1_clk_disable_unused, }; int __init omap1_clk_init(void) @@ -671,8 +649,13 @@ int __init omap1_clk_init(void) struct clk ** clkp; const struct omap_clock_config *info; int crystal_type = 0; /* Default 12 MHz */ + u32 reg; + + /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ + reg = omap_readw(SOFT_REQ_REG) & (1 << 4); + omap_writew(reg, SOFT_REQ_REG); + omap_writew(0, SOFT_REQ_REG2); - omap1_early_clk_reset(); clk_init(&omap1_clk_functions); /* By default all idlect1 clocks are allowed to idle */ @@ -772,6 +755,12 @@ int __init omap1_clk_init(void) omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); #endif + /* Amstrad Delta wants BCLK high when inactive */ + if (machine_is_ams_delta()) + omap_writel(omap_readl(ULPD_CLOCK_CTRL) | + (1 << SDW_MCLK_INV_BIT), + ULPD_CLOCK_CTRL); + /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ /* (on 730, bit 13 must not be cleared) */ if (cpu_is_omap730()) diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index b7c68819c4e7..f7df00205c4a 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -89,6 +89,7 @@ struct arm_idlect1_clk { #define EN_DSPTIMCK 5 /* Various register defines for clock controls scattered around OMAP chip */ +#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ @@ -741,6 +742,18 @@ static struct clk i2c_fck = { .disable = &omap1_clk_disable_generic, }; +static struct clk i2c_ick = { + .name = "i2c_ick", + .id = 1, + .flags = CLOCK_IN_OMAP16XX | + VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | + ALWAYS_ENABLED, + .parent = &armper_ck.clk, + .recalc = &followparent_recalc, + .enable = &omap1_clk_enable_generic, + .disable = &omap1_clk_disable_generic, +}; + static struct clk * onchip_clks[] = { /* non-ULPD clocks */ &ck_ref, @@ -790,6 +803,7 @@ static struct clk * onchip_clks[] = { /* Virtual clocks */ &virtual_ck_mpu, &i2c_fck, + &i2c_ick, }; #endif diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 26ac49ecb78d..0de201c3d50b 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -1025,12 +1025,29 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate) * Omap2 clock reset and init functions *-------------------------------------------------------------------------*/ +#ifdef CONFIG_OMAP_RESET_CLOCKS +static void __init omap2_clk_disable_unused(struct clk *clk) +{ + u32 regval32; + + regval32 = __raw_readl(clk->enable_reg); + if ((regval32 & (1 << clk->enable_bit)) == 0) + return; + + printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); + _omap2_clk_disable(clk); +} +#else +#define omap2_clk_disable_unused NULL +#endif + static struct clk_functions omap2_clk_functions = { .clk_enable = omap2_clk_enable, .clk_disable = omap2_clk_disable, .clk_round_rate = omap2_clk_round_rate, .clk_set_rate = omap2_clk_set_rate, .clk_set_parent = omap2_clk_set_parent, + .clk_disable_unused = omap2_clk_disable_unused, }; static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys) @@ -1070,28 +1087,6 @@ void omap2_clk_prepare_for_reboot(void) clk_set_rate(vclk, rate); } -#ifdef CONFIG_OMAP_RESET_CLOCKS -static void __init omap2_disable_unused_clocks(void) -{ - struct clk *ck; - u32 regval32; - - list_for_each_entry(ck, &clocks, node) { - if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) || - ck->enable_reg == 0) - continue; - - regval32 = __raw_readl(ck->enable_reg); - if ((regval32 & (1 << ck->enable_bit)) == 0) - continue; - - printk(KERN_INFO "Disabling unused clock \"%s\"\n", ck->name); - _omap2_clk_disable(ck); - } -} -late_initcall(omap2_disable_unused_clocks); -#endif - /* * Switch the MPU rate if specified on cmdline. * We cannot do this early until cmdline is parsed. diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 223152d9663f..8816f5a33a28 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -1368,7 +1368,8 @@ static struct clk mcbsp5_fck = { }; static struct clk mcspi1_ick = { - .name = "mcspi1_ick", + .name = "mcspi_ick", + .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, @@ -1377,7 +1378,8 @@ static struct clk mcspi1_ick = { }; static struct clk mcspi1_fck = { - .name = "mcspi1_fck", + .name = "mcspi_fck", + .id = 1, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, @@ -1386,7 +1388,8 @@ static struct clk mcspi1_fck = { }; static struct clk mcspi2_ick = { - .name = "mcspi2_ick", + .name = "mcspi_ick", + .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, @@ -1395,7 +1398,8 @@ static struct clk mcspi2_ick = { }; static struct clk mcspi2_fck = { - .name = "mcspi2_fck", + .name = "mcspi_fck", + .id = 2, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, @@ -1404,7 +1408,8 @@ static struct clk mcspi2_fck = { }; static struct clk mcspi3_ick = { - .name = "mcspi3_ick", + .name = "mcspi_ick", + .id = 3, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, @@ -1413,7 +1418,8 @@ static struct clk mcspi3_ick = { }; static struct clk mcspi3_fck = { - .name = "mcspi3_fck", + .name = "mcspi_fck", + .id = 3, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP243X, .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 4abf2714f2d9..f1179ad4be1b 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -323,6 +323,31 @@ EXPORT_SYMBOL(clk_allow_idle); /*-------------------------------------------------------------------------*/ +#ifdef CONFIG_OMAP_RESET_CLOCKS +/* + * Disable any unused clocks left on by the bootloader + */ +static int __init clk_disable_unused(void) +{ + struct clk *ck; + unsigned long flags; + + list_for_each_entry(ck, &clocks, node) { + if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) || + ck->enable_reg == 0) + continue; + + spin_lock_irqsave(&clockfw_lock, flags); + if (arch_clock->clk_disable_unused) + arch_clock->clk_disable_unused(ck); + spin_unlock_irqrestore(&clockfw_lock, flags); + } + + return 0; +} +late_initcall(clk_disable_unused); +#endif + int __init clk_init(struct clk_functions * custom_clocks) { if (!custom_clocks) { diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index f83003f5287b..fa6881049903 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -45,6 +45,7 @@ struct clk_functions { struct clk * (*clk_get_parent)(struct clk *clk); void (*clk_allow_idle)(struct clk *clk); void (*clk_deny_idle)(struct clk *clk); + void (*clk_disable_unused)(struct clk *clk); }; extern unsigned int mpurate; -- cgit v1.2.3 From 4052ebb7a2729bd7c28260cdf8e470c0d81b9c56 Mon Sep 17 00:00:00 2001 From: "George G. Davis" Date: Fri, 22 Sep 2006 18:36:38 +0100 Subject: [ARM] 3859/1: Fix devicemaps_init() XIP_KERNEL odd 1MiB XIP_PHYS_ADDR translation error The ARM XIP_KERNEL map created in devicemaps_init() is wrong. The map.pfn is rounded down to an even 1MiB section boundary which results in va/pa translations errors when XIP_PHYS_ADDR starts on an odd 1MiB boundary and this causes the kernel to hang. This patch fixes ARM XIP_KERNEL translation errors for the odd 1MiB XIP_PHYS_ADDR boundary case. Signed-off-by: George G. Davis Signed-off-by: Russell King --- arch/arm/mm/init.c | 4 ++-- include/asm-arm/pgtable.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 1099af6d470a..64262bda8e54 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -434,9 +434,9 @@ static void __init devicemaps_init(struct machine_desc *mdesc) * It is always first in the modulearea. */ #ifdef CONFIG_XIP_KERNEL - map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & PGDIR_MASK); + map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); map.virtual = MODULE_START; - map.length = ((unsigned long)&_etext - map.virtual + ~PGDIR_MASK) & PGDIR_MASK; + map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; map.type = MT_ROM; create_mapping(&map); #endif diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 8d3919c6458c..38b2b55688e2 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -135,6 +135,13 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define FIRST_USER_PGD_NR 1 #define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR) +/* + * section address mask and size definitions. + */ +#define SECTION_SHIFT 20 +#define SECTION_SIZE (1UL << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) + /* * ARMv6 supersection address mask and size definitions. */ -- cgit v1.2.3 From 456335e2072fb35bf290b45e61d51916c322c145 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 27 Sep 2006 10:00:54 +0100 Subject: [ARM] Separate page table manipulation code from bootmem initialisation nommu does not require the page table manipulation code in the bootmem initialisation paths. Move this into separate inline functions. Signed-off-by: Russell King --- arch/arm/mm/init.c | 73 +++++++++++++++++++++++++++++-------------------- include/asm-arm/setup.h | 12 ++++---- 2 files changed, 51 insertions(+), 34 deletions(-) (limited to 'include') diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 64262bda8e54..83145d1d3389 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -226,6 +226,44 @@ static __init void reserve_node_zero(pg_data_t *pgdat) reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size); } +static inline void prepare_page_table(struct meminfo *mi) +{ + unsigned long addr; + + /* + * Clear out all the mappings below the kernel image. + */ + for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE) + pmd_clear(pmd_off_k(addr)); + +#ifdef CONFIG_XIP_KERNEL + /* The XIP kernel is mapped in the module area -- skip over it */ + addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK; +#endif + for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) + pmd_clear(pmd_off_k(addr)); + + /* + * Clear out all the kernel space mappings, except for the first + * memory bank, up to the end of the vmalloc region. + */ + for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size); + addr < VMALLOC_END; addr += PGDIR_SIZE) + pmd_clear(pmd_off_k(addr)); +} + +static inline void map_memory_bank(struct membank *bank) +{ + struct map_desc map; + + map.pfn = __phys_to_pfn(bank->start); + map.virtual = __phys_to_virt(bank->start); + map.length = bank->size; + map.type = MT_MEMORY; + + create_mapping(&map); +} + static unsigned long __init bootmem_init_node(int node, int initrd_node, struct meminfo *mi) { @@ -242,23 +280,18 @@ bootmem_init_node(int node, int initrd_node, struct meminfo *mi) * Calculate the pfn range, and map the memory banks for this node. */ for_each_nodebank(i, mi, node) { + struct membank *bank = &mi->bank[i]; unsigned long start, end; - struct map_desc map; - start = mi->bank[i].start >> PAGE_SHIFT; - end = (mi->bank[i].start + mi->bank[i].size) >> PAGE_SHIFT; + start = bank->start >> PAGE_SHIFT; + end = (bank->start + bank->size) >> PAGE_SHIFT; if (start_pfn > start) start_pfn = start; if (end_pfn < end) end_pfn = end; - map.pfn = __phys_to_pfn(mi->bank[i].start); - map.virtual = __phys_to_virt(mi->bank[i].start); - map.length = mi->bank[i].size; - map.type = MT_MEMORY; - - create_mapping(&map); + map_memory_bank(bank); } /* @@ -342,7 +375,7 @@ bootmem_init_node(int node, int initrd_node, struct meminfo *mi) static void __init bootmem_init(struct meminfo *mi) { - unsigned long addr, memend_pfn = 0; + unsigned long memend_pfn = 0; int node, initrd_node, i; /* @@ -354,25 +387,7 @@ static void __init bootmem_init(struct meminfo *mi) memcpy(&meminfo, mi, sizeof(meminfo)); - /* - * Clear out all the mappings below the kernel image. - */ - for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE) - pmd_clear(pmd_off_k(addr)); -#ifdef CONFIG_XIP_KERNEL - /* The XIP kernel is mapped in the module area -- skip over it */ - addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK; -#endif - for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) - pmd_clear(pmd_off_k(addr)); - - /* - * Clear out all the kernel space mappings, except for the first - * memory bank, up to the end of the vmalloc region. - */ - for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size); - addr < VMALLOC_END; addr += PGDIR_SIZE) - pmd_clear(pmd_off_k(addr)); + prepare_page_table(mi); /* * Locate which node contains the ramdisk image, if any. diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h index ea3ed2465233..aa4b5782f0c9 100644 --- a/include/asm-arm/setup.h +++ b/include/asm-arm/setup.h @@ -194,13 +194,15 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn } # define NR_BANKS 8 #endif +struct membank { + unsigned long start; + unsigned long size; + int node; +}; + struct meminfo { int nr_banks; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; + struct membank bank[NR_BANKS]; }; /* -- cgit v1.2.3 From f12d0d7c7786af39435ef6ae9defe47fb58f6091 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Tue, 26 Sep 2006 17:36:37 +0900 Subject: [ARM] nommu: manage the CP15 things All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/Kconfig | 3 ++- arch/arm/Kconfig-nommu | 8 ++++++++ arch/arm/boot/compressed/Makefile | 4 ++++ arch/arm/boot/compressed/head.S | 6 ++++++ arch/arm/kernel/head-nommu.S | 7 ++++++- arch/arm/kernel/process.c | 22 ++++++++++++++++------ arch/arm/mm/Kconfig | 8 ++++---- arch/arm/mm/cache-v4.S | 10 ++++++++++ include/asm-arm/system.h | 4 ++++ 9 files changed, 60 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0810d27c039e..2673fee3281c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -621,6 +621,7 @@ config LEDS_CPU config ALIGNMENT_TRAP bool + depends on CPU_CP15_MMU default y if !ARCH_EBSA110 help ARM processors can not fetch/store information which is not @@ -852,7 +853,7 @@ source "drivers/base/Kconfig" source "drivers/connector/Kconfig" -if ALIGNMENT_TRAP +if ALIGNMENT_TRAP || !CPU_CP15_MMU source "drivers/mtd/Kconfig" endif diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu index e1574be2ded6..f087376748d1 100644 --- a/arch/arm/Kconfig-nommu +++ b/arch/arm/Kconfig-nommu @@ -25,6 +25,14 @@ config FLASH_SIZE hex 'FLASH Size' if SET_MEM_PARAM default 0x00400000 +config PROCESSOR_ID + hex + default 0x00007700 + depends on !CPU_CP15 + help + If processor has no CP15 register, this processor ID is + used instead of the auto-probing which utilizes the register. + config REMAP_VECTORS_TO_RAM bool 'Install vectors to the begining of RAM' if DRAM_BASE depends on DRAM_BASE diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 2adc1527e0eb..adddc7131685 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -51,7 +51,11 @@ OBJS += head-at91rm9200.o endif ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) +ifeq ($(CONFIG_CPU_CP15),y) OBJS += big-endian.o +else +# The endian should be set by h/w design. +endif endif # diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 75df1f764a10..e5ab51b9cceb 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -82,9 +82,11 @@ kphex r6, 8 /* processor id */ kputc #':' kphex r7, 8 /* architecture id */ +#ifdef CONFIG_CPU_CP15 kputc #':' mrc p15, 0, r0, c1, c0 kphex r0, 8 /* control reg */ +#endif kputc #'\n' kphex r5, 8 /* decompressed kernel start */ kputc #'-' @@ -507,7 +509,11 @@ call_kernel: bl cache_clean_flush */ call_cache_fn: adr r12, proc_types +#ifdef CONFIG_CPU_CP15 mrc p15, 0, r6, c0, c0 @ get processor ID +#else + ldr r6, =CONFIG_PROCESSOR_ID +#endif 1: ldr r1, [r12, #0] @ get value ldr r2, [r12, #4] @ get mask eor r1, r1, r6 @ (real ^ match) diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index ac9eb3d30518..698a537915dd 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -9,7 +9,6 @@ * published by the Free Software Foundation. * * Common kernel startup code (non-paged MM) - * for 32-bit CPUs which has a process ID register(CP15). * */ #include @@ -40,7 +39,11 @@ ENTRY(stext) msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode @ and irqs disabled +#ifndef CONFIG_CPU_CP15 + ldr r9, =CONFIG_PROCESSOR_ID +#else mrc p15, 0, r9, c0, c0 @ get processor id +#endif bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? beq __error_p @ yes, error 'p' @@ -58,6 +61,7 @@ ENTRY(stext) */ .type __after_proc_init, %function __after_proc_init: +#ifdef CONFIG_CPU_CP15 mrc p15, 0, r0, c1, c0, 0 @ read control reg #ifdef CONFIG_ALIGNMENT_TRAP orr r0, r0, #CR_A @@ -74,6 +78,7 @@ __after_proc_init: bic r0, r0, #CR_I #endif mcr p15, 0, r0, c1, c0, 0 @ write control reg +#endif /* CONFIG_CPU_CP15 */ mov pc, r13 @ clear the BSS and jump @ to start_kernel diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 3079535afccd..bf35c178a877 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -221,16 +221,26 @@ void __show_regs(struct pt_regs *regs) processor_modes[processor_mode(regs)], thumb_mode(regs) ? " (T)" : "", get_fs() == get_ds() ? "kernel" : "user"); +#if CONFIG_CPU_CP15 { - unsigned int ctrl, transbase, dac; + unsigned int ctrl; __asm__ ( " mrc p15, 0, %0, c1, c0\n" - " mrc p15, 0, %1, c2, c0\n" - " mrc p15, 0, %2, c3, c0\n" - : "=r" (ctrl), "=r" (transbase), "=r" (dac)); - printk("Control: %04X Table: %08X DAC: %08X\n", - ctrl, transbase, dac); + : "=r" (ctrl)); + printk("Control: %04X\n", ctrl); } +#ifdef CONFIG_CPU_CP15_MMU + { + unsigned int transbase, dac; + __asm__ ( + " mrc p15, 0, %0, c2, c0\n" + " mrc p15, 0, %1, c3, c0\n" + : "=r" (transbase), "=r" (dac)); + printk("Table: %08X DAC: %08X\n", + transbase, dac); + } +#endif +#endif } void show_regs(struct pt_regs * regs) diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index c7fb835c148c..0ac11ea84508 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -445,15 +445,15 @@ config CPU_BIG_ENDIAN of your chipset/board/processor. config CPU_ICACHE_DISABLE - bool "Disable I-Cache" - depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 + bool "Disable I-Cache (I-bit)" + depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) help Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N. config CPU_DCACHE_DISABLE - bool "Disable D-Cache" - depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 + bool "Disable D-Cache (C-bit)" + depends on CPU_CP15 help Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N. diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index b8ad5d58ebe2..b2908063ed6a 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S @@ -29,9 +29,13 @@ ENTRY(v4_flush_user_cache_all) * Clean and invalidate the entire cache. */ ENTRY(v4_flush_kern_cache_all) +#ifdef CPU_CP15 mov r0, #0 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache mov pc, lr +#else + /* FALLTHROUGH */ +#endif /* * flush_user_cache_range(start, end, flags) @@ -44,9 +48,13 @@ ENTRY(v4_flush_kern_cache_all) * - flags - vma_area_struct flags describing address space */ ENTRY(v4_flush_user_cache_range) +#ifdef CPU_CP15 mov ip, #0 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache mov pc, lr +#else + /* FALLTHROUGH */ +#endif /* * coherent_kern_range(start, end) @@ -108,8 +116,10 @@ ENTRY(v4_dma_inv_range) * - end - virtual end address */ ENTRY(v4_dma_flush_range) +#ifdef CPU_CP15 mov r0, #0 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache +#endif /* FALLTHROUGH */ /* diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index c19c5b009f71..f05fbe31576c 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -46,6 +46,7 @@ #define CPUID_TCM 2 #define CPUID_TLBTYPE 3 +#ifdef CONFIG_CPU_CP15 #define read_cpuid(reg) \ ({ \ unsigned int __val; \ @@ -55,6 +56,9 @@ : "cc"); \ __val; \ }) +#else +#define read_cpuid(reg) (processor_id) +#endif /* * This is used to ensure the compiler did actually allocate the register we -- cgit v1.2.3 From 07e0da78abdc679714a12e7a60137d950c346681 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Tue, 26 Sep 2006 17:37:36 +0900 Subject: [ARM] nommu: add ARM7TDMI core support This patch adds ARM7TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/Makefile | 1 + arch/arm/mm/Kconfig | 13 +++ arch/arm/mm/Makefile | 1 + arch/arm/mm/proc-arm7tdmi.S | 249 +++++++++++++++++++++++++++++++++++++++++++ include/asm-arm/cacheflush.h | 2 +- include/asm-arm/proc-fns.h | 8 ++ 6 files changed, 273 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mm/proc-arm7tdmi.S (limited to 'include') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 80cee786500c..282333fe0a74 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -55,6 +55,7 @@ arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3 # This selects how we optimise for the processor. tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610 tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710 +tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 0ac11ea84508..9f860aa9c908 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -25,6 +25,19 @@ config CPU_ARM610 Say Y if you want support for the ARM610 processor. Otherwise, say N. +# ARM7TDMI +config CPU_ARM7TDMI + bool "Support ARM7TDMI processor" + select CPU_32v4T + select CPU_ABRT_LV4T + select CPU_CACHE_V4 + help + A 32-bit RISC microprocessor based on the ARM7 processor core + which has no memory control unit and cache. + + Say Y if you want support for the ARM7TDMI processor. + Otherwise, say N. + # ARM710 config CPU_ARM710 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 2d0ab19db496..908f6d437174 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o +obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o obj-$(CONFIG_CPU_ARM920T) += proc-arm920.o obj-$(CONFIG_CPU_ARM922T) += proc-arm922.o diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S new file mode 100644 index 000000000000..22d7e3100ea6 --- /dev/null +++ b/arch/arm/mm/proc-arm7tdmi.S @@ -0,0 +1,249 @@ +/* + * linux/arch/arm/mm/proc-arm7tdmi.S: utility functions for ARM7TDMI + * + * Copyright (C) 2003-2006 Hyok S. Choi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + + .text +/* + * cpu_arm7tdmi_proc_init() + * cpu_arm7tdmi_do_idle() + * cpu_arm7tdmi_dcache_clean_area() + * cpu_arm7tdmi_switch_mm() + * + * These are not required. + */ +ENTRY(cpu_arm7tdmi_proc_init) +ENTRY(cpu_arm7tdmi_do_idle) +ENTRY(cpu_arm7tdmi_dcache_clean_area) +ENTRY(cpu_arm7tdmi_switch_mm) + mov pc, lr + +/* + * cpu_arm7tdmi_proc_fin() + */ +ENTRY(cpu_arm7tdmi_proc_fin) + mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE + msr cpsr_c, r0 + mov pc, lr + +/* + * Function: cpu_arm7tdmi_reset(loc) + * Params : loc(r0) address to jump to + * Purpose : Sets up everything for a reset and jump to the location for soft reset. + */ +ENTRY(cpu_arm7tdmi_reset) + mov pc, r0 + + __INIT + + .type __arm7tdmi_setup, #function +__arm7tdmi_setup: + mov pc, lr + .size __arm7tdmi_setup, . - __arm7tdmi_setup + + __INITDATA + +/* + * Purpose : Function pointers used to access above functions - all calls + * come through these + */ + .type arm7tdmi_processor_functions, #object +ENTRY(arm7tdmi_processor_functions) + .word v4t_late_abort + .word cpu_arm7tdmi_proc_init + .word cpu_arm7tdmi_proc_fin + .word cpu_arm7tdmi_reset + .word cpu_arm7tdmi_do_idle + .word cpu_arm7tdmi_dcache_clean_area + .word cpu_arm7tdmi_switch_mm + .word 0 @ cpu_*_set_pte + .size arm7tdmi_processor_functions, . - arm7tdmi_processor_functions + + .section ".rodata" + + .type cpu_arch_name, #object +cpu_arch_name: + .asciz "armv4t" + .size cpu_arch_name, . - cpu_arch_name + + .type cpu_elf_name, #object +cpu_elf_name: + .asciz "v4" + .size cpu_elf_name, . - cpu_elf_name + + .type cpu_arm7tdmi_name, #object +cpu_arm7tdmi_name: + .asciz "ARM7TDMI" + .size cpu_arm7tdmi_name, . - cpu_arm7tdmi_name + + .type cpu_triscenda7_name, #object +cpu_triscenda7_name: + .asciz "Triscend-A7x" + .size cpu_triscenda7_name, . - cpu_triscenda7_name + + .type cpu_at91_name, #object +cpu_at91_name: + .asciz "Atmel-AT91M40xxx" + .size cpu_at91_name, . - cpu_at91_name + + .type cpu_s3c3410_name, #object +cpu_s3c3410_name: + .asciz "Samsung-S3C3410" + .size cpu_s3c3410_name, . - cpu_s3c3410_name + + .type cpu_s3c44b0x_name, #object +cpu_s3c44b0x_name: + .asciz "Samsung-S3C44B0x" + .size cpu_s3c44b0x_name, . - cpu_s3c44b0x_name + + .type cpu_s3c4510b, #object +cpu_s3c4510b_name: + .asciz "Samsung-S3C4510B" + .size cpu_s3c4510b_name, . - cpu_s3c4510b_name + + .type cpu_s3c4530_name, #object +cpu_s3c4530_name: + .asciz "Samsung-S3C4530" + .size cpu_s3c4530_name, . - cpu_s3c4530_name + + .type cpu_netarm_name, #object +cpu_netarm_name: + .asciz "NETARM" + .size cpu_netarm_name, . - cpu_netarm_name + + .align + + .section ".proc.info.init", #alloc, #execinstr + + .type __arm7tdmi_proc_info, #object +__arm7tdmi_proc_info: + .long 0x41007700 + .long 0xfff8ff00 + .long 0 + .long 0 + b __arm7tdmi_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_26BIT + .long cpu_arm7tdmi_name + .long arm7tdmi_processor_functions + .long 0 + .long 0 + .long v4_cache_fns + .size __arm7tdmi_proc_info, . - __arm7dmi_proc_info + + .type __triscenda7_proc_info, #object +__triscenda7_proc_info: + .long 0x0001d2ff + .long 0x0001ffff + .long 0 + .long 0 + b __arm7tdmi_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT + .long cpu_triscenda7_name + .long arm7tdmi_processor_functions + .long 0 + .long 0 + .long v4_cache_fns + .size __triscenda7_proc_info, . - __triscenda7_proc_info + + .type __at91_proc_info, #object +__at91_proc_info: + .long 0x14000040 + .long 0xfff000e0 + .long 0 + .long 0 + b __arm7tdmi_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT + .long cpu_at91_name + .long arm7tdmi_processor_functions + .long 0 + .long 0 + .long v4_cache_fns + .size __at91_proc_info, . - __at91_proc_info + + .type __s3c4510b_proc_info, #object +__s3c4510b_proc_info: + .long 0x36365000 + .long 0xfffff000 + .long 0 + .long 0 + b __arm7tdmi_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT + .long cpu_s3c4510b_name + .long arm7tdmi_processor_functions + .long 0 + .long 0 + .long v4_cache_fns + .size __s3c4510b_proc_info, . - __s3c4510b_proc_info + + .type __s3c4530_proc_info, #object +__s3c4530_proc_info: + .long 0x4c000000 + .long 0xfff000e0 + .long 0 + .long 0 + b __arm7tdmi_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT + .long cpu_s3c4530_name + .long arm7tdmi_processor_functions + .long 0 + .long 0 + .long v4_cache_fns + .size __s3c4530_proc_info, . - __s3c4530_proc_info + + .type __s3c3410_proc_info, #object +__s3c3410_proc_info: + .long 0x34100000 + .long 0xffff0000 + .long 0 + .long 0 + b __arm7tdmi_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT + .long cpu_s3c3410_name + .long arm7tdmi_processor_functions + .long 0 + .long 0 + .long v4_cache_fns + .size __s3c3410_proc_info, . - __s3c3410_proc_info + + .type __s3c44b0x_proc_info, #object +__s3c44b0x_proc_info: + .long 0x44b00000 + .long 0xffff0000 + .long 0 + .long 0 + b __arm7tdmi_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT + .long cpu_s3c44b0x_name + .long arm7tdmi_processor_functions + .long 0 + .long 0 + .long v4_cache_fns + .size __s3c44b0x_proc_info, . - __s3c44b0x_proc_info diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index e4a2569c636c..e7bfff298e46 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -33,7 +33,7 @@ # endif #endif -#if defined(CONFIG_CPU_ARM720T) +#if defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM7TDMI) # ifdef _CACHE # define MULTI_CACHE 1 # else diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h index 1bde92cdaebd..3e8c057e66b5 100644 --- a/include/asm-arm/proc-fns.h +++ b/include/asm-arm/proc-fns.h @@ -33,6 +33,14 @@ # define CPU_NAME cpu_arm6 # endif # endif +# ifdef CONFIG_CPU_ARM7TDMI +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm7tdmi +# endif +# endif # ifdef CONFIG_CPU_ARM710 # ifdef CPU_NAME # undef MULTI_CPU -- cgit v1.2.3 From b731c3118d87f26c8bf3f358ffbbc24450af50a6 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Tue, 26 Sep 2006 17:37:50 +0900 Subject: [ARM] nommu: add ARM740T core support This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache. Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/Makefile | 1 + arch/arm/mm/Kconfig | 19 ++++- arch/arm/mm/Makefile | 1 + arch/arm/mm/proc-arm740.S | 174 +++++++++++++++++++++++++++++++++++++++++++ include/asm-arm/cacheflush.h | 3 +- include/asm-arm/proc-fns.h | 8 ++ 6 files changed, 203 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mm/proc-arm740.S (limited to 'include') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 282333fe0a74..8ec4b46d2cbb 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -57,6 +57,7 @@ tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610 tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710 tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi +tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 9f860aa9c908..87f9fece9606 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -75,6 +75,21 @@ config CPU_ARM720T Say Y if you want support for the ARM720T processor. Otherwise, say N. +# ARM740T +config CPU_ARM740T + bool "Support ARM740T processor" if ARCH_INTEGRATOR + select CPU_32v4T + select CPU_ABRT_LV4T + select CPU_CACHE_V3 # although the core is v4t + select CPU_CP15_MPU + help + A 32-bit RISC processor with 8KB cache or 4KB variants, + write buffer and MPU(Protection Unit) built around + an ARM7TDMI core. + + Say Y if you want support for the ARM740T processor. + Otherwise, say N. + # ARM920T config CPU_ARM920T bool "Support ARM920T processor" @@ -436,7 +451,7 @@ comment "Processor Features" config ARM_THUMB bool "Support Thumb user binaries" - depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 + depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 default y help Say Y if you want to include kernel support for running user space @@ -473,7 +488,7 @@ config CPU_DCACHE_DISABLE config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE + depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 908f6d437174..d10db822d3b8 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o +obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o obj-$(CONFIG_CPU_ARM920T) += proc-arm920.o obj-$(CONFIG_CPU_ARM922T) += proc-arm922.o obj-$(CONFIG_CPU_ARM925T) += proc-arm925.o diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S new file mode 100644 index 000000000000..40713818a87b --- /dev/null +++ b/arch/arm/mm/proc-arm740.S @@ -0,0 +1,174 @@ +/* + * linux/arch/arm/mm/arm740.S: utility functions for ARM740 + * + * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + + .text +/* + * cpu_arm740_proc_init() + * cpu_arm740_do_idle() + * cpu_arm740_dcache_clean_area() + * cpu_arm740_switch_mm() + * + * These are not required. + */ +ENTRY(cpu_arm740_proc_init) +ENTRY(cpu_arm740_do_idle) +ENTRY(cpu_arm740_dcache_clean_area) +ENTRY(cpu_arm740_switch_mm) + mov pc, lr + +/* + * cpu_arm740_proc_fin() + */ +ENTRY(cpu_arm740_proc_fin) + stmfd sp!, {lr} + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE + msr cpsr_c, ip + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x3f000000 @ bank/f/lock/s + bic r0, r0, #0x0000000c @ w-buffer/cache + mcr p15, 0, r0, c1, c0, 0 @ disable caches + mcr p15, 0, r0, c7, c0, 0 @ invalidate cache + ldmfd sp!, {pc} + +/* + * cpu_arm740_reset(loc) + * Params : r0 = address to jump to + * Notes : This sets up everything for a reset + */ +ENTRY(cpu_arm740_reset) + mov ip, #0 + mcr p15, 0, ip, c7, c0, 0 @ invalidate cache + mrc p15, 0, ip, c1, c0, 0 @ get ctrl register + bic ip, ip, #0x0000000c @ ............wc.. + mcr p15, 0, ip, c1, c0, 0 @ ctrl register + mov pc, r0 + + __INIT + + .type __arm740_setup, #function +__arm740_setup: + mov r0, #0 + mcr p15, 0, r0, c7, c0, 0 @ invalidate caches + + mcr p15, 0, r0, c6, c3 @ disable area 3~7 + mcr p15, 0, r0, c6, c4 + mcr p15, 0, r0, c6, c5 + mcr p15, 0, r0, c6, c6 + mcr p15, 0, r0, c6, c7 + + mov r0, #0x0000003F @ base = 0, size = 4GB + mcr p15, 0, r0, c6, c0 @ set area 0, default + + ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM + ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) + mov r2, #10 @ 11 is the minimum (4KB) +1: add r2, r2, #1 @ area size *= 2 + mov r1, r1, lsr #1 + bne 1b @ count not zero r-shift + orr r0, r0, r2, lsl #1 @ the area register value + orr r0, r0, #1 @ set enable bit + mcr p15, 0, r0, c6, c1 @ set area 1, RAM + + ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH + ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB) + mov r2, #10 @ 11 is the minimum (4KB) +1: add r2, r2, #1 @ area size *= 2 + mov r1, r1, lsr #1 + bne 1b @ count not zero r-shift + orr r0, r0, r2, lsl #1 @ the area register value + orr r0, r0, #1 @ set enable bit + mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH + + mov r0, #0x06 + mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mov r0, #0x00 @ disable whole write buffer +#else + mov r0, #0x02 @ Region 1 write bufferred +#endif + mcr p15, 0, r0, c3, c0 + + mov r0, #0x10000 + sub r0, r0, #1 @ r0 = 0xffff + mcr p15, 0, r0, c5, c0 @ all read/write access + + mrc p15, 0, r0, c1, c0 @ get control register + bic r0, r0, #0x3F000000 @ set to standard caching mode + @ need some benchmark + orr r0, r0, #0x0000000d @ MPU/Cache/WB + + mov pc, lr + + .size __arm740_setup, . - __arm740_setup + + __INITDATA + +/* + * Purpose : Function pointers used to access above functions - all calls + * come through these + */ + .type arm740_processor_functions, #object +ENTRY(arm740_processor_functions) + .word v4t_late_abort + .word cpu_arm740_proc_init + .word cpu_arm740_proc_fin + .word cpu_arm740_reset + .word cpu_arm740_do_idle + .word cpu_arm740_dcache_clean_area + .word cpu_arm740_switch_mm + .word 0 @ cpu_*_set_pte + .size arm740_processor_functions, . - arm740_processor_functions + + .section ".rodata" + + .type cpu_arch_name, #object +cpu_arch_name: + .asciz "armv4" + .size cpu_arch_name, . - cpu_arch_name + + .type cpu_elf_name, #object +cpu_elf_name: + .asciz "v4" + .size cpu_elf_name, . - cpu_elf_name + + .type cpu_arm740_name, #object +cpu_arm740_name: + .ascii "ARM740T" + .size cpu_arm740_name, . - cpu_arm740_name + + .align + + .section ".proc.info.init", #alloc, #execinstr + .type __arm740_proc_info,#object +__arm740_proc_info: + .long 0x41807400 + .long 0xfffffff0 + .long 0 + b __arm740_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT + .long cpu_arm740_name + .long arm740_processor_functions + .long 0 + .long 0 + .long v3_cache_fns @ cache model + .size __arm740_proc_info, . - __arm740_proc_info + + diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index e7bfff298e46..24924e64f883 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -25,7 +25,8 @@ #undef _CACHE #undef MULTI_CACHE -#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) +#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) || \ + defined(CONFIG_CPU_ARM740T) # ifdef _CACHE # define MULTI_CACHE 1 # else diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h index 3e8c057e66b5..17dfc0de9658 100644 --- a/include/asm-arm/proc-fns.h +++ b/include/asm-arm/proc-fns.h @@ -57,6 +57,14 @@ # define CPU_NAME cpu_arm720 # endif # endif +# ifdef CONFIG_CPU_ARM740T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm740 +# endif +# endif # ifdef CONFIG_CPU_ARM920T # ifdef CPU_NAME # undef MULTI_CPU -- cgit v1.2.3 From 43f5f0146ef5c3a3421ea53a0708fd37edcb8905 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Tue, 26 Sep 2006 17:38:05 +0900 Subject: [ARM] nommu: add ARM9TDMI core support This patch adds ARM9TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/Makefile | 1 + arch/arm/mm/Kconfig | 13 +++++ arch/arm/mm/Makefile | 1 + arch/arm/mm/proc-arm9tdmi.S | 134 +++++++++++++++++++++++++++++++++++++++++++ include/asm-arm/cacheflush.h | 3 +- include/asm-arm/proc-fns.h | 8 +++ 6 files changed, 159 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mm/proc-arm9tdmi.S (limited to 'include') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 8ec4b46d2cbb..a29e64175f8f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -58,6 +58,7 @@ tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710 tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi +tune-$(CONFIG_CPU_ARM9TDMI) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 87f9fece9606..ed9d32c2469e 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -90,6 +90,19 @@ config CPU_ARM740T Say Y if you want support for the ARM740T processor. Otherwise, say N. +# ARM9TDMI +config CPU_ARM9TDMI + bool "Support ARM9TDMI processor" + select CPU_32v4T + select CPU_ABRT_EV4T + select CPU_CACHE_V4 + help + A 32-bit RISC microprocessor based on the ARM9 processor core + which has no memory control unit and cache. + + Say Y if you want support for the ARM9TDMI processor. + Otherwise, say N. + # ARM920T config CPU_ARM920T bool "Support ARM920T processor" diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index d10db822d3b8..053957eebe24 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o +obj-$(CONFIG_CPU_ARM9TDMI) += proc-arm9tdmi.o obj-$(CONFIG_CPU_ARM920T) += proc-arm920.o obj-$(CONFIG_CPU_ARM922T) += proc-arm922.o obj-$(CONFIG_CPU_ARM925T) += proc-arm925.o diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S new file mode 100644 index 000000000000..95c90f13caa8 --- /dev/null +++ b/arch/arm/mm/proc-arm9tdmi.S @@ -0,0 +1,134 @@ +/* + * linux/arch/arm/mm/proc-arm9tdmi.S: utility functions for ARM9TDMI + * + * Copyright (C) 2003-2006 Hyok S. Choi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + + .text +/* + * cpu_arm9tdmi_proc_init() + * cpu_arm9tdmi_do_idle() + * cpu_arm9tdmi_dcache_clean_area() + * cpu_arm9tdmi_switch_mm() + * + * These are not required. + */ +ENTRY(cpu_arm9tdmi_proc_init) +ENTRY(cpu_arm9tdmi_do_idle) +ENTRY(cpu_arm9tdmi_dcache_clean_area) +ENTRY(cpu_arm9tdmi_switch_mm) + mov pc, lr + +/* + * cpu_arm9tdmi_proc_fin() + */ +ENTRY(cpu_arm9tdmi_proc_fin) + mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE + msr cpsr_c, r0 + mov pc, lr + +/* + * Function: cpu_arm9tdmi_reset(loc) + * Params : loc(r0) address to jump to + * Purpose : Sets up everything for a reset and jump to the location for soft reset. + */ +ENTRY(cpu_arm9tdmi_reset) + mov pc, r0 + + __INIT + + .type __arm9tdmi_setup, #function +__arm9tdmi_setup: + mov pc, lr + .size __arm9tdmi_setup, . - __arm9tdmi_setup + + __INITDATA + +/* + * Purpose : Function pointers used to access above functions - all calls + * come through these + */ + .type arm9tdmi_processor_functions, #object +ENTRY(arm9tdmi_processor_functions) + .word v4t_early_abort + .word cpu_arm9tdmi_proc_init + .word cpu_arm9tdmi_proc_fin + .word cpu_arm9tdmi_reset + .word cpu_arm9tdmi_do_idle + .word cpu_arm9tdmi_dcache_clean_area + .word cpu_arm9tdmi_switch_mm + .word 0 @ cpu_*_set_pte + .size arm9tdmi_processor_functions, . - arm9tdmi_processor_functions + + .section ".rodata" + + .type cpu_arch_name, #object +cpu_arch_name: + .asciz "armv4t" + .size cpu_arch_name, . - cpu_arch_name + + .type cpu_elf_name, #object +cpu_elf_name: + .asciz "v4" + .size cpu_elf_name, . - cpu_elf_name + + .type cpu_arm9tdmi_name, #object +cpu_arm9tdmi_name: + .asciz "ARM9TDMI" + .size cpu_arm9tdmi_name, . - cpu_arm9tdmi_name + + .type cpu_p2001_name, #object +cpu_p2001_name: + .asciz "P2001" + .size cpu_p2001_name, . - cpu_p2001_name + + .align + + .section ".proc.info.init", #alloc, #execinstr + + .type __arm9tdmi_proc_info, #object +__arm9tdmi_proc_info: + .long 0x41009900 + .long 0xfff8ff00 + .long 0 + .long 0 + b __arm9tdmi_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT + .long cpu_arm9tdmi_name + .long arm9tdmi_processor_functions + .long 0 + .long 0 + .long v4_cache_fns + .size __arm9tdmi_proc_info, . - __arm9dmi_proc_info + + .type __p2001_proc_info, #object +__p2001_proc_info: + .long 0x41029000 + .long 0xffffffff + .long 0 + .long 0 + b __arm9tdmi_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT + .long cpu_p2001_name + .long arm9tdmi_processor_functions + .long 0 + .long 0 + .long v4_cache_fns + .size __p2001_proc_info, . - __p2001_proc_info diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 24924e64f883..77ff6fe86dbd 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -34,7 +34,8 @@ # endif #endif -#if defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM7TDMI) +#if defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM7TDMI) || \ + defined(CONFIG_CPU_ARM9TDMI) # ifdef _CACHE # define MULTI_CACHE 1 # else diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h index 17dfc0de9658..7bb9dab310f5 100644 --- a/include/asm-arm/proc-fns.h +++ b/include/asm-arm/proc-fns.h @@ -65,6 +65,14 @@ # define CPU_NAME cpu_arm740 # endif # endif +# ifdef CONFIG_CPU_ARM9TDMI +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm9tdmi +# endif +# endif # ifdef CONFIG_CPU_ARM920T # ifdef CPU_NAME # undef MULTI_CPU -- cgit v1.2.3 From d60674eb5d961b2421db16cc373dc163f38cc105 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Tue, 26 Sep 2006 17:38:18 +0900 Subject: [ARM] nommu: add ARM940T core support This patch adds ARM940T core support which has 4KB D-cache, 4KB I-cache and a MPU. Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/Makefile | 1 + arch/arm/mm/Kconfig | 20 ++- arch/arm/mm/Makefile | 1 + arch/arm/mm/proc-arm940.S | 369 +++++++++++++++++++++++++++++++++++++++++++ include/asm-arm/cacheflush.h | 8 + include/asm-arm/proc-fns.h | 8 + 6 files changed, 405 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mm/proc-arm940.S (limited to 'include') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a29e64175f8f..4c424c95dd3a 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -59,6 +59,7 @@ tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM9TDMI) :=-mtune=arm9tdmi +tune-$(CONFIG_CPU_ARM940T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index ed9d32c2469e..34d00738293f 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -184,6 +184,22 @@ config CPU_ARM926T Say Y if you want support for the ARM926T processor. Otherwise, say N. +# ARM940T +config CPU_ARM940T + bool "Support ARM940T processor" if ARCH_INTEGRATOR + select CPU_32v4T + select CPU_ABRT_EV4T + select CPU_CACHE_VIVT + select CPU_CP15_MPU + help + ARM940T is a member of the ARM9TDMI family of general- + purpose microprocessors with MPU and seperate 4KB + instruction and 4KB data cases, each with a 4-word line + length. + + Say Y if you want support for the ARM940T processor. + Otherwise, say N. + # ARM1020 - needs validating config CPU_ARM1020 bool "Support ARM1020T (rev 0) processor" @@ -464,7 +480,7 @@ comment "Processor Features" config ARM_THUMB bool "Support Thumb user binaries" - depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 + depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 default y help Say Y if you want to include kernel support for running user space @@ -501,7 +517,7 @@ config CPU_DCACHE_DISABLE config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE + depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 053957eebe24..f89fe1b2a4ad 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_CPU_ARM920T) += proc-arm920.o obj-$(CONFIG_CPU_ARM922T) += proc-arm922.o obj-$(CONFIG_CPU_ARM925T) += proc-arm925.o obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o +obj-$(CONFIG_CPU_ARM940T) += proc-arm940.o obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S new file mode 100644 index 000000000000..14846ac2d0e6 --- /dev/null +++ b/arch/arm/mm/proc-arm940.S @@ -0,0 +1,369 @@ +/* + * linux/arch/arm/mm/arm940.S: utility functions for ARM940T + * + * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */ +#define CACHE_DLINESIZE 16 +#define CACHE_DSEGMENTS 4 +#define CACHE_DENTRIES 64 + + .text +/* + * cpu_arm940_proc_init() + * cpu_arm940_switch_mm() + * + * These are not required. + */ +ENTRY(cpu_arm940_proc_init) +ENTRY(cpu_arm940_switch_mm) + mov pc, lr + +/* + * cpu_arm940_proc_fin() + */ +ENTRY(cpu_arm940_proc_fin) + stmfd sp!, {lr} + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE + msr cpsr_c, ip + bl arm940_flush_kern_cache_all + mrc p15, 0, r0, c1, c0, 0 @ ctrl register + bic r0, r0, #0x00001000 @ i-cache + bic r0, r0, #0x00000004 @ d-cache + mcr p15, 0, r0, c1, c0, 0 @ disable caches + ldmfd sp!, {pc} + +/* + * cpu_arm940_reset(loc) + * Params : r0 = address to jump to + * Notes : This sets up everything for a reset + */ +ENTRY(cpu_arm940_reset) + mov ip, #0 + mcr p15, 0, ip, c7, c5, 0 @ flush I cache + mcr p15, 0, ip, c7, c6, 0 @ flush D cache + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mrc p15, 0, ip, c1, c0, 0 @ ctrl register + bic ip, ip, #0x00000005 @ .............c.p + bic ip, ip, #0x00001000 @ i-cache + mcr p15, 0, ip, c1, c0, 0 @ ctrl register + mov pc, r0 + +/* + * cpu_arm940_do_idle() + */ + .align 5 +ENTRY(cpu_arm940_do_idle) + mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt + mov pc, lr + +/* + * flush_user_cache_all() + */ +ENTRY(arm940_flush_user_cache_all) + /* FALLTHROUGH */ + +/* + * flush_kern_cache_all() + * + * Clean and invalidate the entire cache. + */ +ENTRY(arm940_flush_kern_cache_all) + mov r2, #VM_EXEC + /* FALLTHROUGH */ + +/* + * flush_user_cache_range(start, end, flags) + * + * There is no efficient way to flush a range of cache entries + * in the specified address range. Thus, flushes all. + * + * - start - start address (inclusive) + * - end - end address (exclusive) + * - flags - vm_flags describing address space + */ +ENTRY(arm940_flush_user_cache_range) + mov ip, #0 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, ip, c7, c6, 0 @ flush D cache +#else + mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments +1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries +2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index + subs r3, r3, #1 << 26 + bcs 2b @ entries 63 to 0 + subs r1, r1, #1 << 4 + bcs 1b @ segments 3 to 0 +#endif + tst r2, #VM_EXEC + mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache + mcrne p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * coherent_kern_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(arm940_coherent_kern_range) + /* FALLTHROUGH */ + +/* + * coherent_user_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(arm940_coherent_user_range) + /* FALLTHROUGH */ + +/* + * flush_kern_dcache_page(void *page) + * + * Ensure no D cache aliasing occurs, either with itself or + * the I cache + * + * - addr - page aligned address + */ +ENTRY(arm940_flush_kern_dcache_page) + mov ip, #0 + mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments +1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries +2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index + subs r3, r3, #1 << 26 + bcs 2b @ entries 63 to 0 + subs r1, r1, #1 << 4 + bcs 1b @ segments 7 to 0 + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * dma_inv_range(start, end) + * + * There is no efficient way to invalidate a specifid virtual + * address range. Thus, invalidates all. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(arm940_dma_inv_range) + mov ip, #0 + mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments +1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries +2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry + subs r3, r3, #1 << 26 + bcs 2b @ entries 63 to 0 + subs r1, r1, #1 << 4 + bcs 1b @ segments 7 to 0 + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * dma_clean_range(start, end) + * + * There is no efficient way to clean a specifid virtual + * address range. Thus, cleans all. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(arm940_dma_clean_range) +ENTRY(cpu_arm940_dcache_clean_area) + mov ip, #0 +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH + mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments +1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries +2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry + subs r3, r3, #1 << 26 + bcs 2b @ entries 63 to 0 + subs r1, r1, #1 << 4 + bcs 1b @ segments 7 to 0 +#endif + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * dma_flush_range(start, end) + * + * There is no efficient way to clean and invalidate a specifid + * virtual address range. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(arm940_dma_flush_range) + mov ip, #0 + mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments +1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries +2: +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry +#else + mcr p15, 0, r3, c7, c10, 2 @ clean D entry +#endif + subs r3, r3, #1 << 26 + bcs 2b @ entries 63 to 0 + subs r1, r1, #1 << 4 + bcs 1b @ segments 7 to 0 + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +ENTRY(arm940_cache_fns) + .long arm940_flush_kern_cache_all + .long arm940_flush_user_cache_all + .long arm940_flush_user_cache_range + .long arm940_coherent_kern_range + .long arm940_coherent_user_range + .long arm940_flush_kern_dcache_page + .long arm940_dma_inv_range + .long arm940_dma_clean_range + .long arm940_dma_flush_range + + __INIT + + .type __arm940_setup, #function +__arm940_setup: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB + + mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7 + mcr p15, 0, r0, c6, c4, 0 + mcr p15, 0, r0, c6, c5, 0 + mcr p15, 0, r0, c6, c6, 0 + mcr p15, 0, r0, c6, c7, 0 + + mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7 + mcr p15, 0, r0, c6, c4, 1 + mcr p15, 0, r0, c6, c5, 1 + mcr p15, 0, r0, c6, c6, 1 + mcr p15, 0, r0, c6, c7, 1 + + mov r0, #0x0000003F @ base = 0, size = 4GB + mcr p15, 0, r0, c6, c0, 0 @ set area 0, default + mcr p15, 0, r0, c6, c0, 1 + + ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM + ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) + mov r2, #10 @ 11 is the minimum (4KB) +1: add r2, r2, #1 @ area size *= 2 + mov r1, r1, lsr #1 + bne 1b @ count not zero r-shift + orr r0, r0, r2, lsl #1 @ the area register value + orr r0, r0, #1 @ set enable bit + mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM + mcr p15, 0, r0, c6, c1, 1 + + ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH + ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB) + mov r2, #10 @ 11 is the minimum (4KB) +1: add r2, r2, #1 @ area size *= 2 + mov r1, r1, lsr #1 + bne 1b @ count not zero r-shift + orr r0, r0, r2, lsl #1 @ the area register value + orr r0, r0, #1 @ set enable bit + mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH + mcr p15, 0, r0, c6, c2, 1 + + mov r0, #0x06 + mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable + mcr p15, 0, r0, c2, c0, 1 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mov r0, #0x00 @ disable whole write buffer +#else + mov r0, #0x02 @ Region 1 write bufferred +#endif + mcr p15, 0, r0, c3, c0, 0 + + mov r0, #0x10000 + sub r0, r0, #1 @ r0 = 0xffff + mcr p15, 0, r0, c5, c0, 0 @ all read/write access + mcr p15, 0, r0, c5, c0, 1 + + mrc p15, 0, r0, c1, c0 @ get control register + orr r0, r0, #0x00001000 @ I-cache + orr r0, r0, #0x00000005 @ MPU/D-cache + + mov pc, lr + + .size __arm940_setup, . - __arm940_setup + + __INITDATA + +/* + * Purpose : Function pointers used to access above functions - all calls + * come through these + */ + .type arm940_processor_functions, #object +ENTRY(arm940_processor_functions) + .word v4t_early_abort + .word cpu_arm940_proc_init + .word cpu_arm940_proc_fin + .word cpu_arm940_reset + .word cpu_arm940_do_idle + .word cpu_arm940_dcache_clean_area + .word cpu_arm940_switch_mm + .word 0 @ cpu_*_set_pte + .size arm940_processor_functions, . - arm940_processor_functions + + .section ".rodata" + +.type cpu_arch_name, #object +cpu_arch_name: + .asciz "armv4t" + .size cpu_arch_name, . - cpu_arch_name + + .type cpu_elf_name, #object +cpu_elf_name: + .asciz "v4" + .size cpu_elf_name, . - cpu_elf_name + + .type cpu_arm940_name, #object +cpu_arm940_name: + .ascii "ARM940T" + .size cpu_arm940_name, . - cpu_arm940_name + + .align + + .section ".proc.info.init", #alloc, #execinstr + + .type __arm940_proc_info,#object +__arm940_proc_info: + .long 0x41009400 + .long 0xff00fff0 + .long 0 + b __arm940_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB + .long cpu_arm940_name + .long arm940_processor_functions + .long 0 + .long 0 + .long arm940_cache_fns + .size __arm940_proc_info, . - __arm940_proc_info + diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 77ff6fe86dbd..b0a8603400be 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -56,6 +56,14 @@ # endif #endif +#if defined(CONFIG_CPU_ARM940T) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE arm940 +# endif +#endif + #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100) # ifdef _CACHE # define MULTI_CACHE 1 diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h index 7bb9dab310f5..87f3ea97f48c 100644 --- a/include/asm-arm/proc-fns.h +++ b/include/asm-arm/proc-fns.h @@ -105,6 +105,14 @@ # define CPU_NAME cpu_arm926 # endif # endif +# ifdef CONFIG_CPU_ARM940T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm940 +# endif +# endif # ifdef CONFIG_CPU_SA110 # ifdef CPU_NAME # undef MULTI_CPU -- cgit v1.2.3 From f37f46eb1c0bd0b11c34ef06c7365658be989d80 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Tue, 26 Sep 2006 17:38:32 +0900 Subject: [ARM] nommu: add ARM946E-S core support This patch adds ARM946E-S core support which has typically 8KB I&D cache. It has a MPU and supports ARMv5TE instruction set. Because the ARM946E-S core can be synthesizable with various cache size, CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations. Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/Makefile | 1 + arch/arm/mm/Kconfig | 34 +++- arch/arm/mm/Makefile | 1 + arch/arm/mm/proc-arm946.S | 424 +++++++++++++++++++++++++++++++++++++++++++ include/asm-arm/cacheflush.h | 8 + include/asm-arm/proc-fns.h | 8 + 6 files changed, 473 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mm/proc-arm946.S (limited to 'include') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4c424c95dd3a..2a0b2c8a1fe0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -60,6 +60,7 @@ tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM9TDMI) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM940T) :=-mtune=arm9tdmi +tune-$(CONFIG_CPU_ARM946T) :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi) tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 34d00738293f..893d3fc8078f 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -200,6 +200,21 @@ config CPU_ARM940T Say Y if you want support for the ARM940T processor. Otherwise, say N. +# ARM946E-S +config CPU_ARM946E + bool "Support ARM946E-S processor" if ARCH_INTEGRATOR + select CPU_32v5 + select CPU_ABRT_EV5T + select CPU_CACHE_VIVT + select CPU_CP15_MPU + help + ARM946E-S is a member of the ARM9E-S family of high- + performance, 32-bit system-on-chip processor solutions. + The TCM and ARMv5TE 32-bit instruction set is supported. + + Say Y if you want support for the ARM946E-S processor. + Otherwise, say N. + # ARM1020 - needs validating config CPU_ARM1020 bool "Support ARM1020T (rev 0) processor" @@ -480,7 +495,7 @@ comment "Processor Features" config ARM_THUMB bool "Support Thumb user binaries" - depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 + depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 default y help Say Y if you want to include kernel support for running user space @@ -515,9 +530,22 @@ config CPU_DCACHE_DISABLE Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N. +config CPU_DCACHE_SIZE + hex + depends on CPU_ARM740T || CPU_ARM946E + default 0x00001000 if CPU_ARM740T + default 0x00002000 # default size for ARM946E-S + help + Some cores are synthesizable to have various sized cache. For + ARM946E-S case, it can vary from 0KB to 1MB. + To support such cache operations, it is efficient to know the size + before compile time. + If your SoC is configured to have a different size, define the value + here with proper conditions. + config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE + depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you @@ -525,7 +553,7 @@ config CPU_DCACHE_WRITETHROUGH config CPU_CACHE_ROUND_ROBIN bool "Round robin I and D cache replacement algorithm" - depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) + depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) help Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N. diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index f89fe1b2a4ad..ed81b9ef10cb 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_CPU_ARM922T) += proc-arm922.o obj-$(CONFIG_CPU_ARM925T) += proc-arm925.o obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o obj-$(CONFIG_CPU_ARM940T) += proc-arm940.o +obj-$(CONFIG_CPU_ARM946E) += proc-arm946.o obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S new file mode 100644 index 000000000000..6dc7942c4cfe --- /dev/null +++ b/arch/arm/mm/proc-arm946.S @@ -0,0 +1,424 @@ +/* + * linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S + * + * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com) + * + * (Many of cache codes are from proc-arm926.S) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* + * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache, + * comprising 256 lines of 32 bytes (8 words). + */ +#define CACHE_DSIZE (CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */ +#define CACHE_DLINESIZE 32 /* fixed */ +#define CACHE_DSEGMENTS 4 /* fixed */ +#define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE) +#define CACHE_DLIMIT (CACHE_DSIZE * 4) /* benchmark needed */ + + .text +/* + * cpu_arm946_proc_init() + * cpu_arm946_switch_mm() + * + * These are not required. + */ +ENTRY(cpu_arm946_proc_init) +ENTRY(cpu_arm946_switch_mm) + mov pc, lr + +/* + * cpu_arm946_proc_fin() + */ +ENTRY(cpu_arm946_proc_fin) + stmfd sp!, {lr} + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE + msr cpsr_c, ip + bl arm946_flush_kern_cache_all + mrc p15, 0, r0, c1, c0, 0 @ ctrl register + bic r0, r0, #0x00001000 @ i-cache + bic r0, r0, #0x00000004 @ d-cache + mcr p15, 0, r0, c1, c0, 0 @ disable caches + ldmfd sp!, {pc} + +/* + * cpu_arm946_reset(loc) + * Params : r0 = address to jump to + * Notes : This sets up everything for a reset + */ +ENTRY(cpu_arm946_reset) + mov ip, #0 + mcr p15, 0, ip, c7, c5, 0 @ flush I cache + mcr p15, 0, ip, c7, c6, 0 @ flush D cache + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mrc p15, 0, ip, c1, c0, 0 @ ctrl register + bic ip, ip, #0x00000005 @ .............c.p + bic ip, ip, #0x00001000 @ i-cache + mcr p15, 0, ip, c1, c0, 0 @ ctrl register + mov pc, r0 + +/* + * cpu_arm946_do_idle() + */ + .align 5 +ENTRY(cpu_arm946_do_idle) + mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt + mov pc, lr + +/* + * flush_user_cache_all() + */ +ENTRY(arm946_flush_user_cache_all) + /* FALLTHROUGH */ + +/* + * flush_kern_cache_all() + * + * Clean and invalidate the entire cache. + */ +ENTRY(arm946_flush_kern_cache_all) + mov r2, #VM_EXEC + mov ip, #0 +__flush_whole_cache: +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, ip, c7, c6, 0 @ flush D cache +#else + mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments +1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries +2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index + subs r3, r3, #1 << 4 + bcs 2b @ entries n to 0 + subs r1, r1, #1 << 29 + bcs 1b @ segments 3 to 0 +#endif + tst r2, #VM_EXEC + mcrne p15, 0, ip, c7, c5, 0 @ flush I cache + mcrne p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * flush_user_cache_range(start, end, flags) + * + * Clean and invalidate a range of cache entries in the + * specified address range. + * + * - start - start address (inclusive) + * - end - end address (exclusive) + * - flags - vm_flags describing address space + * (same as arm926) + */ +ENTRY(arm946_flush_user_cache_range) + mov ip, #0 + sub r3, r1, r0 @ calculate total size + cmp r3, #CACHE_DLIMIT + bhs __flush_whole_cache + +1: tst r2, #VM_EXEC +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE +#else + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE +#endif + cmp r0, r1 + blo 1b + tst r2, #VM_EXEC + mcrne p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * coherent_kern_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(arm946_coherent_kern_range) + /* FALLTHROUGH */ + +/* + * coherent_user_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * + * - start - virtual start address + * - end - virtual end address + * (same as arm926) + */ +ENTRY(arm946_coherent_user_range) + bic r0, r0, #CACHE_DLINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * flush_kern_dcache_page(void *page) + * + * Ensure no D cache aliasing occurs, either with itself or + * the I cache + * + * - addr - page aligned address + * (same as arm926) + */ +ENTRY(arm946_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ +1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * dma_inv_range(start, end) + * + * Invalidate (discard) the specified virtual address range. + * May not write back any entries. If 'start' or 'end' + * are not cache line aligned, those lines must be written + * back. + * + * - start - virtual start address + * - end - virtual end address + * (same as arm926) + */ +ENTRY(arm946_dma_inv_range) +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH + tst r0, #CACHE_DLINESIZE - 1 + mcrne p15, 0, r0, c7, c10, 1 @ clean D entry + tst r1, #CACHE_DLINESIZE - 1 + mcrne p15, 0, r1, c7, c10, 1 @ clean D entry +#endif + bic r0, r0, #CACHE_DLINESIZE - 1 +1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * dma_clean_range(start, end) + * + * Clean the specified virtual address range. + * + * - start - virtual start address + * - end - virtual end address + * + * (same as arm926) + */ +ENTRY(arm946_dma_clean_range) +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH + bic r0, r0, #CACHE_DLINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b +#endif + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * dma_flush_range(start, end) + * + * Clean and invalidate the specified virtual address range. + * + * - start - virtual start address + * - end - virtual end address + * + * (same as arm926) + */ +ENTRY(arm946_dma_flush_range) + bic r0, r0, #CACHE_DLINESIZE - 1 +1: +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry +#else + mcr p15, 0, r0, c7, c10, 1 @ clean D entry +#endif + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +ENTRY(arm946_cache_fns) + .long arm946_flush_kern_cache_all + .long arm946_flush_user_cache_all + .long arm946_flush_user_cache_range + .long arm946_coherent_kern_range + .long arm946_coherent_user_range + .long arm946_flush_kern_dcache_page + .long arm946_dma_inv_range + .long arm946_dma_clean_range + .long arm946_dma_flush_range + + +ENTRY(cpu_arm946_dcache_clean_area) +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHE_DLINESIZE + subs r1, r1, #CACHE_DLINESIZE + bhi 1b +#endif + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + + __INIT + + .type __arm946_setup, #function +__arm946_setup: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB + + mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7 + mcr p15, 0, r0, c6, c4, 0 + mcr p15, 0, r0, c6, c5, 0 + mcr p15, 0, r0, c6, c6, 0 + mcr p15, 0, r0, c6, c7, 0 + + mov r0, #0x0000003F @ base = 0, size = 4GB + mcr p15, 0, r0, c6, c0, 0 @ set region 0, default + + ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM + ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) + mov r2, #10 @ 11 is the minimum (4KB) +1: add r2, r2, #1 @ area size *= 2 + mov r1, r1, lsr #1 + bne 1b @ count not zero r-shift + orr r0, r0, r2, lsl #1 @ the region register value + orr r0, r0, #1 @ set enable bit + mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM + + ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH + ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB) + mov r2, #10 @ 11 is the minimum (4KB) +1: add r2, r2, #1 @ area size *= 2 + mov r1, r1, lsr #1 + bne 1b @ count not zero r-shift + orr r0, r0, r2, lsl #1 @ the region register value + orr r0, r0, #1 @ set enable bit + mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH + + mov r0, #0x06 + mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable + mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mov r0, #0x00 @ disable whole write buffer +#else + mov r0, #0x02 @ region 1 write bufferred +#endif + mcr p15, 0, r0, c3, c0, 0 + +/* + * Access Permission Settings for future permission control by PU. + * + * priv. user + * region 0 (whole) rw -- : b0001 + * region 1 (RAM) rw rw : b0011 + * region 2 (FLASH) rw r- : b0010 + * region 3~7 (none) -- -- : b0000 + */ + mov r0, #0x00000031 + orr r0, r0, #0x00000200 + mcr p15, 0, r0, c5, c0, 2 @ set data access permission + mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission + + mrc p15, 0, r0, c1, c0 @ get control register + orr r0, r0, #0x00001000 @ I-cache + orr r0, r0, #0x00000005 @ MPU/D-cache +#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN + orr r0, r0, #0x00004000 @ .1.. .... .... .... +#endif + mov pc, lr + + .size __arm946_setup, . - __arm946_setup + + __INITDATA + +/* + * Purpose : Function pointers used to access above functions - all calls + * come through these + */ + .type arm946_processor_functions, #object +ENTRY(arm946_processor_functions) + .word v5t_early_abort + .word cpu_arm946_proc_init + .word cpu_arm946_proc_fin + .word cpu_arm946_reset + .word cpu_arm946_do_idle + + .word cpu_arm946_dcache_clean_area + .word cpu_arm946_switch_mm + .word 0 @ cpu_*_set_pte + .size arm946_processor_functions, . - arm946_processor_functions + + .section ".rodata" + + .type cpu_arch_name, #object +cpu_arch_name: + .asciz "armv5te" + .size cpu_arch_name, . - cpu_arch_name + + .type cpu_elf_name, #object +cpu_elf_name: + .asciz "v5t" + .size cpu_elf_name, . - cpu_elf_name + + .type cpu_arm946_name, #object +cpu_arm946_name: + .ascii "ARM946E-S" + .size cpu_arm946_name, . - cpu_arm946_name + + .align + + .section ".proc.info.init", #alloc, #execinstr + .type __arm946_proc_info,#object +__arm946_proc_info: + .long 0x41009460 + .long 0xff00fff0 + .long 0 + b __arm946_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB + .long cpu_arm946_name + .long arm946_processor_functions + .long 0 + .long 0 + .long arm940_cache_fns + .size __arm946_proc_info, . - __arm946_proc_info + diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index b0a8603400be..b611a8ea0bb2 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -64,6 +64,14 @@ # endif #endif +#if defined(CONFIG_CPU_ARM946E) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE arm946 +# endif +#endif + #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100) # ifdef _CACHE # define MULTI_CACHE 1 diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h index 87f3ea97f48c..ea7e54c319be 100644 --- a/include/asm-arm/proc-fns.h +++ b/include/asm-arm/proc-fns.h @@ -113,6 +113,14 @@ # define CPU_NAME cpu_arm940 # endif # endif +# ifdef CONFIG_CPU_ARM946E +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm946 +# endif +# endif # ifdef CONFIG_CPU_SA110 # ifdef CPU_NAME # undef MULTI_CPU -- cgit v1.2.3 From 6cc7cbef948ea2660cc40d7aab090a479f7db6a2 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 27 Sep 2006 18:00:35 +0100 Subject: [ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h Three of the generic cache method options were using explicit CPU types, whereas they could use the CPU_CACHE_* definitions instead. Switch them over to use the CPU_CACHE_* definitions. Signed-off-by: Russell King --- include/asm-arm/cacheflush.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index b611a8ea0bb2..f0845646aacb 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -25,8 +25,7 @@ #undef _CACHE #undef MULTI_CACHE -#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) || \ - defined(CONFIG_CPU_ARM740T) +#if defined(CONFIG_CPU_CACHE_V3) # ifdef _CACHE # define MULTI_CACHE 1 # else @@ -34,8 +33,7 @@ # endif #endif -#if defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM7TDMI) || \ - defined(CONFIG_CPU_ARM9TDMI) +#if defined(CONFIG_CPU_CACHE_V4) # ifdef _CACHE # define MULTI_CACHE 1 # else @@ -72,7 +70,7 @@ # endif #endif -#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100) +#if defined(CONFIG_CPU_CACHE_V4WB) # ifdef _CACHE # define MULTI_CACHE 1 # else -- cgit v1.2.3 From 8d48427ecb0639593ccf14e807479b7873254ccb Mon Sep 17 00:00:00 2001 From: Richard Purdie Date: Mon, 25 Sep 2006 20:11:48 +0100 Subject: [ARM] 3847/2: Convert LOMOMO to use struct device for GPIOs Convert LOMOMO to use struct device * for GPIOs instead of struct locomo_dev. This enables access to the GPIOs from code which is not a locomo device itself (such as audio). Access for gpio 31 is removed for error handling (no such hardware exists). Signed-off-by: Richard Purdie Signed-off-by: Russell King --- arch/arm/common/locomo.c | 32 ++++++++++++++++++++++---------- arch/arm/mach-sa1100/collie.c | 23 ++++++++++------------- drivers/video/backlight/locomolcd.c | 30 +++++++++++++++--------------- include/asm-arm/hardware/locomo.h | 9 +++++---- 4 files changed, 52 insertions(+), 42 deletions(-) (limited to 'include') diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index 4e0dcaef6eb2..c46dc65ec79a 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -814,12 +814,15 @@ static inline struct locomo *locomo_chip_driver(struct locomo_dev *ldev) return (struct locomo *)dev_get_drvdata(ldev->dev.parent); } -void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned int dir) +void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir) { - struct locomo *lchip = locomo_chip_driver(ldev); + struct locomo *lchip = dev_get_drvdata(dev); unsigned long flags; unsigned int r; + if (!lchip) + return; + spin_lock_irqsave(&lchip->lock, flags); r = locomo_readl(lchip->base + LOCOMO_GPD); @@ -836,12 +839,15 @@ void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned in spin_unlock_irqrestore(&lchip->lock, flags); } -unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits) +int locomo_gpio_read_level(struct device *dev, unsigned int bits) { - struct locomo *lchip = locomo_chip_driver(ldev); + struct locomo *lchip = dev_get_drvdata(dev); unsigned long flags; unsigned int ret; + if (!lchip) + return -ENODEV; + spin_lock_irqsave(&lchip->lock, flags); ret = locomo_readl(lchip->base + LOCOMO_GPL); spin_unlock_irqrestore(&lchip->lock, flags); @@ -850,12 +856,15 @@ unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits) return ret; } -unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits) +int locomo_gpio_read_output(struct device *dev, unsigned int bits) { - struct locomo *lchip = locomo_chip_driver(ldev); + struct locomo *lchip = dev_get_drvdata(dev); unsigned long flags; unsigned int ret; + if (!lchip) + return -ENODEV; + spin_lock_irqsave(&lchip->lock, flags); ret = locomo_readl(lchip->base + LOCOMO_GPO); spin_unlock_irqrestore(&lchip->lock, flags); @@ -864,12 +873,15 @@ unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits) return ret; } -void locomo_gpio_write(struct locomo_dev *ldev, unsigned int bits, unsigned int set) +void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set) { - struct locomo *lchip = locomo_chip_driver(ldev); + struct locomo *lchip = dev_get_drvdata(dev); unsigned long flags; unsigned int r; + if (!lchip) + return; + spin_lock_irqsave(&lchip->lock, flags); r = locomo_readl(lchip->base + LOCOMO_GPO); @@ -1058,9 +1070,9 @@ void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf) struct locomo *lchip = locomo_chip_driver(dev); if (vr) - locomo_gpio_write(dev, LOCOMO_GPIO_FL_VR, 1); + locomo_gpio_write(dev->dev.parent, LOCOMO_GPIO_FL_VR, 1); else - locomo_gpio_write(dev, LOCOMO_GPIO_FL_VR, 0); + locomo_gpio_write(dev->dev.parent, LOCOMO_GPIO_FL_VR, 0); spin_lock_irqsave(&lchip->lock, flags); locomo_writel(bpwf, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index a0dfa390e34b..6496eb645cee 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -91,30 +91,29 @@ static struct mcp_plat_data collie_mcp_data = { /* * low-level UART features. */ -static struct locomo_dev *uart_dev = NULL; +struct platform_device collie_locomo_device; static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl) { - if (!uart_dev) return; - if (mctrl & TIOCM_RTS) - locomo_gpio_write(uart_dev, LOCOMO_GPIO_RTS, 0); + locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 0); else - locomo_gpio_write(uart_dev, LOCOMO_GPIO_RTS, 1); + locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 1); if (mctrl & TIOCM_DTR) - locomo_gpio_write(uart_dev, LOCOMO_GPIO_DTR, 0); + locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 0); else - locomo_gpio_write(uart_dev, LOCOMO_GPIO_DTR, 1); + locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 1); } static u_int collie_uart_get_mctrl(struct uart_port *port) { int ret = TIOCM_CD; unsigned int r; - if (!uart_dev) return ret; - r = locomo_gpio_read_output(uart_dev, LOCOMO_GPIO_CTS & LOCOMO_GPIO_DSR); + r = locomo_gpio_read_output(&collie_locomo_device.dev, LOCOMO_GPIO_CTS & LOCOMO_GPIO_DSR); + if (r == -ENODEV) + return ret; if (r & LOCOMO_GPIO_CTS) ret |= TIOCM_CTS; if (r & LOCOMO_GPIO_DSR) @@ -130,13 +129,11 @@ static struct sa1100_port_fns collie_port_fns __initdata = { static int collie_uart_probe(struct locomo_dev *dev) { - uart_dev = dev; return 0; } static int collie_uart_remove(struct locomo_dev *dev) { - uart_dev = NULL; return 0; } @@ -170,7 +167,7 @@ static struct resource locomo_resources[] = { }, }; -static struct platform_device locomo_device = { +struct platform_device collie_locomo_device = { .name = "locomo", .id = 0, .num_resources = ARRAY_SIZE(locomo_resources), @@ -178,7 +175,7 @@ static struct platform_device locomo_device = { }; static struct platform_device *devices[] __initdata = { - &locomo_device, + &collie_locomo_device, &colliescoop_device, }; diff --git a/drivers/video/backlight/locomolcd.c b/drivers/video/backlight/locomolcd.c index caf1eca199b0..628571c63bac 100644 --- a/drivers/video/backlight/locomolcd.c +++ b/drivers/video/backlight/locomolcd.c @@ -33,19 +33,19 @@ static unsigned long locomolcd_flags; static void locomolcd_on(int comadj) { - locomo_gpio_set_dir(locomolcd_dev, LOCOMO_GPIO_LCD_VSHA_ON, 0); - locomo_gpio_write(locomolcd_dev, LOCOMO_GPIO_LCD_VSHA_ON, 1); + locomo_gpio_set_dir(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_VSHA_ON, 0); + locomo_gpio_write(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_VSHA_ON, 1); mdelay(2); - locomo_gpio_set_dir(locomolcd_dev, LOCOMO_GPIO_LCD_VSHD_ON, 0); - locomo_gpio_write(locomolcd_dev, LOCOMO_GPIO_LCD_VSHD_ON, 1); + locomo_gpio_set_dir(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_VSHD_ON, 0); + locomo_gpio_write(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_VSHD_ON, 1); mdelay(2); locomo_m62332_senddata(locomolcd_dev, comadj, 0); mdelay(5); - locomo_gpio_set_dir(locomolcd_dev, LOCOMO_GPIO_LCD_VEE_ON, 0); - locomo_gpio_write(locomolcd_dev, LOCOMO_GPIO_LCD_VEE_ON, 1); + locomo_gpio_set_dir(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_VEE_ON, 0); + locomo_gpio_write(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_VEE_ON, 1); mdelay(10); /* TFTCRST | CPSOUT=0 | CPSEN */ @@ -58,8 +58,8 @@ static void locomolcd_on(int comadj) locomo_writel((0x04 | 0x01), locomolcd_dev->mapbase + LOCOMO_TC); mdelay(10); - locomo_gpio_set_dir(locomolcd_dev, LOCOMO_GPIO_LCD_MOD, 0); - locomo_gpio_write(locomolcd_dev, LOCOMO_GPIO_LCD_MOD, 1); + locomo_gpio_set_dir(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_MOD, 0); + locomo_gpio_write(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_MOD, 1); } static void locomolcd_off(int comadj) @@ -68,16 +68,16 @@ static void locomolcd_off(int comadj) locomo_writel(0x06, locomolcd_dev->mapbase + LOCOMO_TC); mdelay(1); - locomo_gpio_write(locomolcd_dev, LOCOMO_GPIO_LCD_VSHA_ON, 0); + locomo_gpio_write(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_VSHA_ON, 0); mdelay(110); - locomo_gpio_write(locomolcd_dev, LOCOMO_GPIO_LCD_VEE_ON, 0); + locomo_gpio_write(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_VEE_ON, 0); mdelay(700); /* TFTCRST=0 | CPSOUT=0 | CPSEN = 0 */ locomo_writel(0, locomolcd_dev->mapbase + LOCOMO_TC); - locomo_gpio_write(locomolcd_dev, LOCOMO_GPIO_LCD_MOD, 0); - locomo_gpio_write(locomolcd_dev, LOCOMO_GPIO_LCD_VSHD_ON, 0); + locomo_gpio_write(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_MOD, 0); + locomo_gpio_write(locomolcd_dev->dev.parent, LOCOMO_GPIO_LCD_VSHD_ON, 0); } void locomolcd_power(int on) @@ -167,14 +167,14 @@ static int locomolcd_resume(struct locomo_dev *dev) #define locomolcd_resume NULL #endif -static int locomolcd_probe(struct locomo_dev *dev) +static int locomolcd_probe(struct locomo_dev *ldev) { unsigned long flags; local_irq_save(flags); - locomolcd_dev = dev; + locomolcd_dev = ldev; - locomo_gpio_set_dir(dev, LOCOMO_GPIO_FL_VR, 0); + locomo_gpio_set_dir(ldev->dev.parent, LOCOMO_GPIO_FL_VR, 0); /* the poodle_lcd_power function is called for the first time * from fs_initcall, which is before locomo is activated. diff --git a/include/asm-arm/hardware/locomo.h b/include/asm-arm/hardware/locomo.h index 22dfb1737768..2599a6bc70e4 100644 --- a/include/asm-arm/hardware/locomo.h +++ b/include/asm-arm/hardware/locomo.h @@ -197,10 +197,11 @@ int locomo_driver_register(struct locomo_driver *); void locomo_driver_unregister(struct locomo_driver *); /* GPIO control functions */ -void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned int dir); -unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits); -unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits); -void locomo_gpio_write(struct locomo_dev *ldev, unsigned int bits, unsigned int set); +void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir); +int locomo_gpio_read_level(struct device *dev, unsigned int bits); +int locomo_gpio_read_output(struct device *dev, unsigned int bits); +void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set); + /* M62332 control function */ void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel); -- cgit v1.2.3 From a2025e7f73ae5eab0a25dad88c60aba67e3ae690 Mon Sep 17 00:00:00 2001 From: Dirk Opfer Date: Mon, 25 Sep 2006 22:41:47 +0100 Subject: [ARM] 3863/1: Add Locomo SPI Device The Locomo chip has a SPI interface which is used for SD/MMC cards (only collie). This patch adds the definition for the SPI device inside the Locomo chip. Signed-off-by: Dirk Opfer Signed-off-by: Russell King --- arch/arm/common/locomo.c | 29 ++++++++++++++++++----------- include/asm-arm/hardware/locomo.h | 24 +++++++++++++----------- 2 files changed, 31 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index c46dc65ec79a..181ef1ead5b8 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -121,6 +121,13 @@ static struct locomo_dev_info locomo_devices[] = { .offset = 0, .length = 0, }, + { + .devid = LOCOMO_DEVID_SPI, + .irq = {}, + .name = "locomo-spi", + .offset = LOCOMO_SPI, + .length = 0x30, + }, }; @@ -374,7 +381,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc, struct irqdesc *d; void __iomem *mapbase = get_irq_chipdata(irq); - req = locomo_readl(mapbase + LOCOMO_SPIIR) & 0x000F; + req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F; if (req) { irq = LOCOMO_IRQ_SPI_START; d = irq_desc + irq; @@ -391,35 +398,35 @@ static void locomo_spi_ack_irq(unsigned int irq) { void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; - r = locomo_readl(mapbase + LOCOMO_SPIWE); + r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE); r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPIWE); + locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIWE); - r = locomo_readl(mapbase + LOCOMO_SPIIS); + r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIS); r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPIIS); + locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIIS); - r = locomo_readl(mapbase + LOCOMO_SPIWE); + r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE); r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPIWE); + locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIWE); } static void locomo_spi_mask_irq(unsigned int irq) { void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; - r = locomo_readl(mapbase + LOCOMO_SPIIE); + r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPIIE); + locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIIE); } static void locomo_spi_unmask_irq(unsigned int irq) { void __iomem *mapbase = get_irq_chipdata(irq); unsigned int r; - r = locomo_readl(mapbase + LOCOMO_SPIIE); + r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPIIE); + locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIIE); } static struct irq_chip locomo_spi_chip = { diff --git a/include/asm-arm/hardware/locomo.h b/include/asm-arm/hardware/locomo.h index 2599a6bc70e4..adab77780ed3 100644 --- a/include/asm-arm/hardware/locomo.h +++ b/include/asm-arm/hardware/locomo.h @@ -54,17 +54,18 @@ #define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */ /* SPI interface */ -#define LOCOMO_SPIMD 0x60 /* SPI mode setting */ -#define LOCOMO_SPICT 0x64 /* SPI mode control */ -#define LOCOMO_SPIST 0x68 /* SPI status */ -#define LOCOMO_SPIIS 0x70 /* SPI interrupt status */ -#define LOCOMO_SPIWE 0x74 /* SPI interrupt status write enable */ -#define LOCOMO_SPIIE 0x78 /* SPI interrupt enable */ -#define LOCOMO_SPIIR 0x7c /* SPI interrupt request */ -#define LOCOMO_SPITD 0x80 /* SPI transfer data write */ -#define LOCOMO_SPIRD 0x84 /* SPI receive data read */ -#define LOCOMO_SPITS 0x88 /* SPI transfer data shift */ -#define LOCOMO_SPIRS 0x8C /* SPI receive data shift */ +#define LOCOMO_SPI 0x60 +#define LOCOMO_SPIMD 0x00 /* SPI mode setting */ +#define LOCOMO_SPICT 0x04 /* SPI mode control */ +#define LOCOMO_SPIST 0x08 /* SPI status */ +#define LOCOMO_SPIIS 0x10 /* SPI interrupt status */ +#define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */ +#define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */ +#define LOCOMO_SPIIR 0x1c /* SPI interrupt request */ +#define LOCOMO_SPITD 0x20 /* SPI transfer data write */ +#define LOCOMO_SPIRD 0x24 /* SPI receive data read */ +#define LOCOMO_SPITS 0x28 /* SPI transfer data shift */ +#define LOCOMO_SPIRS 0x2C /* SPI receive data shift */ #define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */ #define LOCOMO_SPI_OVRN (1 << 2) /* Over Run bit */ #define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */ @@ -161,6 +162,7 @@ extern struct bus_type locomo_bus_type; #define LOCOMO_DEVID_AUDIO 3 #define LOCOMO_DEVID_LED 4 #define LOCOMO_DEVID_UART 5 +#define LOCOMO_DEVID_SPI 6 struct locomo_dev { struct device dev; -- cgit v1.2.3 From 576b3ef2495c732a56509febd5de5144f3ebccf6 Mon Sep 17 00:00:00 2001 From: Dirk Opfer Date: Mon, 25 Sep 2006 22:51:02 +0100 Subject: [ARM] 3864/1: Refactore sharpsl_pm This patch adds another hook into sharpsl_pm to notify the machine specific driver immediately after resume. This is needed to support the Sharp SL-6000 (Tosa). Signed-off-by: Dirk Opfer Signed-off-by: Russell King --- arch/arm/common/sharpsl_pm.c | 4 ++++ include/asm-arm/hardware/sharpsl_pm.h | 1 + 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index 59b5ddec480f..f412dedda684 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c @@ -40,6 +40,7 @@ #define SHARPSL_CHARGE_FINISH_TIME (msecs_to_jiffies(10*60*1000)) /* 10 min */ #define SHARPSL_BATCHK_TIME (msecs_to_jiffies(15*1000)) /* 15 sec */ #define SHARPSL_BATCHK_TIME_SUSPEND (60*10) /* 10 min */ + #define SHARPSL_WAIT_CO_TIME 15 /* 15 sec */ #define SHARPSL_WAIT_DISCHARGE_ON 100 /* 100 msec */ #define SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP 10 /* 10 msec */ @@ -575,6 +576,9 @@ static int corgi_pxa_pm_enter(suspend_state_t state) while (corgi_enter_suspend(alarm_time,alarm_status,state)) {} + if (sharpsl_pm.machinfo->earlyresume) + sharpsl_pm.machinfo->earlyresume(); + dev_dbg(sharpsl_pm.dev, "SharpSL resuming...\n"); return 0; diff --git a/include/asm-arm/hardware/sharpsl_pm.h b/include/asm-arm/hardware/sharpsl_pm.h index ecf15b83956f..a836e76a14f7 100644 --- a/include/asm-arm/hardware/sharpsl_pm.h +++ b/include/asm-arm/hardware/sharpsl_pm.h @@ -25,6 +25,7 @@ struct sharpsl_charger_machinfo { void (*measure_temp)(int); void (*presuspend)(void); void (*postsuspend)(void); + void (*earlyresume)(void); unsigned long (*read_devdata)(int); #define SHARPSL_BATT_VOLT 1 #define SHARPSL_BATT_TEMP 2 -- cgit v1.2.3 From 72729910c38ca5b4736032c15dc3f9d48fe4f68a Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Wed, 27 Sep 2006 09:44:11 +0100 Subject: [ARM] 3865/1: AT91RM9200 header updates This is more preparation for adding support for the new Atmel AT91SAM9 processors. Changes include: - Replace AT91_BASE_* with AT91RM9200_BASE_* - Replace AT91_ID_* with AT91RM9200_ID_* - ROM, SRAM and UHP address definitions moved to at91rm9200.h. - The raw AT91_P[ABCD]_* definitions are now depreciated in favour of the GPIO API. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91rm9200/at91rm9200.c | 32 ++++---- arch/arm/mach-at91rm9200/clock.c | 28 +++---- arch/arm/mach-at91rm9200/devices.c | 72 ++++++++-------- arch/arm/mach-at91rm9200/gpio.c | 16 ++-- arch/arm/mach-at91rm9200/irq.c | 4 +- arch/arm/mach-at91rm9200/pm.c | 14 ++-- drivers/mmc/at91_mci.c | 4 +- drivers/net/arm/at91_ether.c | 2 +- drivers/serial/at91_serial.c | 2 +- drivers/usb/gadget/at91_udc.c | 6 +- include/asm-arm/arch-at91rm9200/at91rm9200.h | 118 +++++++++++++++------------ include/asm-arm/arch-at91rm9200/gpio.h | 2 +- include/asm-arm/arch-at91rm9200/hardware.h | 37 ++++----- include/asm-arm/arch-at91rm9200/irqs.h | 2 +- 14 files changed, 173 insertions(+), 166 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c index 0985b1c42c7c..e21cb845d112 100644 --- a/arch/arm/mach-at91rm9200/at91rm9200.c +++ b/arch/arm/mach-at91rm9200/at91rm9200.c @@ -26,78 +26,78 @@ static struct map_desc at91rm9200_io_desc[] __initdata = { .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_SPI, - .pfn = __phys_to_pfn(AT91_BASE_SPI), + .pfn = __phys_to_pfn(AT91RM9200_BASE_SPI), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_SSC2, - .pfn = __phys_to_pfn(AT91_BASE_SSC2), + .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC2), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_SSC1, - .pfn = __phys_to_pfn(AT91_BASE_SSC1), + .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC1), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_SSC0, - .pfn = __phys_to_pfn(AT91_BASE_SSC0), + .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC0), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_US3, - .pfn = __phys_to_pfn(AT91_BASE_US3), + .pfn = __phys_to_pfn(AT91RM9200_BASE_US3), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_US2, - .pfn = __phys_to_pfn(AT91_BASE_US2), + .pfn = __phys_to_pfn(AT91RM9200_BASE_US2), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_US1, - .pfn = __phys_to_pfn(AT91_BASE_US1), + .pfn = __phys_to_pfn(AT91RM9200_BASE_US1), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_US0, - .pfn = __phys_to_pfn(AT91_BASE_US0), + .pfn = __phys_to_pfn(AT91RM9200_BASE_US0), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_EMAC, - .pfn = __phys_to_pfn(AT91_BASE_EMAC), + .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_TWI, - .pfn = __phys_to_pfn(AT91_BASE_TWI), + .pfn = __phys_to_pfn(AT91RM9200_BASE_TWI), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_MCI, - .pfn = __phys_to_pfn(AT91_BASE_MCI), + .pfn = __phys_to_pfn(AT91RM9200_BASE_MCI), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_UDP, - .pfn = __phys_to_pfn(AT91_BASE_UDP), + .pfn = __phys_to_pfn(AT91RM9200_BASE_UDP), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_TCB1, - .pfn = __phys_to_pfn(AT91_BASE_TCB1), + .pfn = __phys_to_pfn(AT91RM9200_BASE_TCB1), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_TCB0, - .pfn = __phys_to_pfn(AT91_BASE_TCB0), + .pfn = __phys_to_pfn(AT91RM9200_BASE_TCB0), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_SRAM_VIRT_BASE, - .pfn = __phys_to_pfn(AT91_SRAM_BASE), - .length = AT91_SRAM_SIZE, + .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE), + .length = AT91RM9200_SRAM_SIZE, .type = MT_DEVICE, }, }; diff --git a/arch/arm/mach-at91rm9200/clock.c b/arch/arm/mach-at91rm9200/clock.c index edc2cc837ae6..5b7892277bee 100644 --- a/arch/arm/mach-at91rm9200/clock.c +++ b/arch/arm/mach-at91rm9200/clock.c @@ -190,85 +190,85 @@ static void pmc_periph_mode(struct clk *clk, int is_on) static struct clk udc_clk = { .name = "udc_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_UDP, + .pmc_mask = 1 << AT91RM9200_ID_UDP, .mode = pmc_periph_mode, }; static struct clk ohci_clk = { .name = "ohci_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_UHP, + .pmc_mask = 1 << AT91RM9200_ID_UHP, .mode = pmc_periph_mode, }; static struct clk ether_clk = { .name = "ether_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_EMAC, + .pmc_mask = 1 << AT91RM9200_ID_EMAC, .mode = pmc_periph_mode, }; static struct clk mmc_clk = { .name = "mci_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_MCI, + .pmc_mask = 1 << AT91RM9200_ID_MCI, .mode = pmc_periph_mode, }; static struct clk twi_clk = { .name = "twi_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_TWI, + .pmc_mask = 1 << AT91RM9200_ID_TWI, .mode = pmc_periph_mode, }; static struct clk usart0_clk = { .name = "usart0_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_US0, + .pmc_mask = 1 << AT91RM9200_ID_US0, .mode = pmc_periph_mode, }; static struct clk usart1_clk = { .name = "usart1_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_US1, + .pmc_mask = 1 << AT91RM9200_ID_US1, .mode = pmc_periph_mode, }; static struct clk usart2_clk = { .name = "usart2_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_US2, + .pmc_mask = 1 << AT91RM9200_ID_US2, .mode = pmc_periph_mode, }; static struct clk usart3_clk = { .name = "usart3_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_US3, + .pmc_mask = 1 << AT91RM9200_ID_US3, .mode = pmc_periph_mode, }; static struct clk spi_clk = { .name = "spi0_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_SPI, + .pmc_mask = 1 << AT91RM9200_ID_SPI, .mode = pmc_periph_mode, }; static struct clk pioA_clk = { .name = "pioA_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_PIOA, + .pmc_mask = 1 << AT91RM9200_ID_PIOA, .mode = pmc_periph_mode, }; static struct clk pioB_clk = { .name = "pioB_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_PIOB, + .pmc_mask = 1 << AT91RM9200_ID_PIOB, .mode = pmc_periph_mode, }; static struct clk pioC_clk = { .name = "pioC_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_PIOC, + .pmc_mask = 1 << AT91RM9200_ID_PIOC, .mode = pmc_periph_mode, }; static struct clk pioD_clk = { .name = "pioD_clk", .parent = &mck, - .pmc_mask = 1 << AT91_ID_PIOD, + .pmc_mask = 1 << AT91RM9200_ID_PIOD, .mode = pmc_periph_mode, }; diff --git a/arch/arm/mach-at91rm9200/devices.c b/arch/arm/mach-at91rm9200/devices.c index 4352acb88178..db7c684cdb63 100644 --- a/arch/arm/mach-at91rm9200/devices.c +++ b/arch/arm/mach-at91rm9200/devices.c @@ -35,13 +35,13 @@ static struct at91_usbh_data usbh_data; static struct resource at91_usbh_resources[] = { [0] = { - .start = AT91_UHP_BASE, - .end = AT91_UHP_BASE + SZ_1M - 1, + .start = AT91RM9200_UHP_BASE, + .end = AT91RM9200_UHP_BASE + SZ_1M - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_ID_UHP, - .end = AT91_ID_UHP, + .start = AT91RM9200_ID_UHP, + .end = AT91RM9200_ID_UHP, .flags = IORESOURCE_IRQ, }, }; @@ -80,13 +80,13 @@ static struct at91_udc_data udc_data; static struct resource at91_udc_resources[] = { [0] = { - .start = AT91_BASE_UDP, - .end = AT91_BASE_UDP + SZ_16K - 1, + .start = AT91RM9200_BASE_UDP, + .end = AT91RM9200_BASE_UDP + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_ID_UDP, - .end = AT91_ID_UDP, + .start = AT91RM9200_ID_UDP, + .end = AT91RM9200_ID_UDP, .flags = IORESOURCE_IRQ, }, }; @@ -131,13 +131,13 @@ static struct at91_eth_data eth_data; static struct resource at91_eth_resources[] = { [0] = { - .start = AT91_BASE_EMAC, - .end = AT91_BASE_EMAC + SZ_16K - 1, + .start = AT91RM9200_BASE_EMAC, + .end = AT91RM9200_BASE_EMAC + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_ID_EMAC, - .end = AT91_ID_EMAC, + .start = AT91RM9200_ID_EMAC, + .end = AT91RM9200_ID_EMAC, .flags = IORESOURCE_IRQ, }, }; @@ -263,13 +263,13 @@ static struct at91_mmc_data mmc_data; static struct resource at91_mmc_resources[] = { [0] = { - .start = AT91_BASE_MCI, - .end = AT91_BASE_MCI + SZ_16K - 1, + .start = AT91RM9200_BASE_MCI, + .end = AT91RM9200_BASE_MCI + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_ID_MCI, - .end = AT91_ID_MCI, + .start = AT91RM9200_ID_MCI, + .end = AT91RM9200_ID_MCI, .flags = IORESOURCE_IRQ, }, }; @@ -423,13 +423,13 @@ static u64 spi_dmamask = 0xffffffffUL; static struct resource at91_spi_resources[] = { [0] = { - .start = AT91_BASE_SPI, - .end = AT91_BASE_SPI + SZ_16K - 1, + .start = AT91RM9200_BASE_SPI, + .end = AT91RM9200_BASE_SPI + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_ID_SPI, - .end = AT91_ID_SPI, + .start = AT91RM9200_ID_SPI, + .end = AT91RM9200_ID_SPI, .flags = IORESOURCE_IRQ, }, }; @@ -582,13 +582,13 @@ static inline void configure_dbgu_pins(void) static struct resource uart0_resources[] = { [0] = { - .start = AT91_BASE_US0, - .end = AT91_BASE_US0 + SZ_16K - 1, + .start = AT91RM9200_BASE_US0, + .end = AT91RM9200_BASE_US0 + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_ID_US0, - .end = AT91_ID_US0, + .start = AT91RM9200_ID_US0, + .end = AT91RM9200_ID_US0, .flags = IORESOURCE_IRQ, }, }; @@ -624,13 +624,13 @@ static inline void configure_usart0_pins(void) static struct resource uart1_resources[] = { [0] = { - .start = AT91_BASE_US1, - .end = AT91_BASE_US1 + SZ_16K - 1, + .start = AT91RM9200_BASE_US1, + .end = AT91RM9200_BASE_US1 + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_ID_US1, - .end = AT91_ID_US1, + .start = AT91RM9200_ID_US1, + .end = AT91RM9200_ID_US1, .flags = IORESOURCE_IRQ, }, }; @@ -665,13 +665,13 @@ static inline void configure_usart1_pins(void) static struct resource uart2_resources[] = { [0] = { - .start = AT91_BASE_US2, - .end = AT91_BASE_US2 + SZ_16K - 1, + .start = AT91RM9200_BASE_US2, + .end = AT91RM9200_BASE_US2 + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_ID_US2, - .end = AT91_ID_US2, + .start = AT91RM9200_ID_US2, + .end = AT91RM9200_ID_US2, .flags = IORESOURCE_IRQ, }, }; @@ -700,13 +700,13 @@ static inline void configure_usart2_pins(void) static struct resource uart3_resources[] = { [0] = { - .start = AT91_BASE_US3, - .end = AT91_BASE_US3 + SZ_16K - 1, + .start = AT91RM9200_BASE_US3, + .end = AT91RM9200_BASE_US3 + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_ID_US3, - .end = AT91_ID_US3, + .start = AT91RM9200_ID_US3, + .end = AT91RM9200_ID_US3, .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c index cec199fd6721..8476cb8856c9 100644 --- a/arch/arm/mach-at91rm9200/gpio.c +++ b/arch/arm/mach-at91rm9200/gpio.c @@ -261,10 +261,10 @@ void at91_gpio_suspend(void) at91_sys_write(pio_controller_offset[i] + PIO_IER, wakeups[i]); if (!wakeups[i]) { - disable_irq_wake(AT91_ID_PIOA + i); - at91_sys_write(AT91_PMC_PCDR, 1 << (AT91_ID_PIOA + i)); + disable_irq_wake(AT91RM9200_ID_PIOA + i); + at91_sys_write(AT91_PMC_PCDR, 1 << (AT91RM9200_ID_PIOA + i)); } else { - enable_irq_wake(AT91_ID_PIOA + i); + enable_irq_wake(AT91RM9200_ID_PIOA + i); #ifdef CONFIG_PM_DEBUG printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]); #endif @@ -282,10 +282,10 @@ void at91_gpio_resume(void) } at91_sys_write(AT91_PMC_PCER, - (1 << AT91_ID_PIOA) - | (1 << AT91_ID_PIOB) - | (1 << AT91_ID_PIOC) - | (1 << AT91_ID_PIOD)); + (1 << AT91RM9200_ID_PIOA) + | (1 << AT91RM9200_ID_PIOB) + | (1 << AT91RM9200_ID_PIOC) + | (1 << AT91RM9200_ID_PIOD)); } #else @@ -384,7 +384,7 @@ void __init at91_gpio_irq_setup(unsigned banks) if (banks > 4) banks = 4; - for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA; + for (pioc = 0, pin = PIN_BASE, id = AT91RM9200_ID_PIOA; pioc < banks; pioc++, id++) { void __iomem *controller; diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c index c3a5e777f9f8..8cd60a99c5b8 100644 --- a/arch/arm/mach-at91rm9200/irq.c +++ b/arch/arm/mach-at91rm9200/irq.c @@ -61,12 +61,12 @@ static int at91_aic_set_type(unsigned irq, unsigned type) srctype = AT91_AIC_SRCTYPE_RISING; break; case IRQT_LOW: - if ((irq > AT91_ID_FIQ) && (irq < AT91_ID_IRQ0)) /* only supported on external interrupts */ + if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */ return -EINVAL; srctype = AT91_AIC_SRCTYPE_LOW; break; case IRQT_FALLING: - if ((irq > AT91_ID_FIQ) && (irq < AT91_ID_IRQ0)) /* only supported on external interrupts */ + if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */ return -EINVAL; srctype = AT91_AIC_SRCTYPE_FALLING; break; diff --git a/arch/arm/mach-at91rm9200/pm.c b/arch/arm/mach-at91rm9200/pm.c index 47e5480feb7e..32c95d8eaacf 100644 --- a/arch/arm/mach-at91rm9200/pm.c +++ b/arch/arm/mach-at91rm9200/pm.c @@ -123,13 +123,13 @@ static int at91_pm_enter(suspend_state_t state) (at91_sys_read(AT91_PMC_PCSR) | (1 << AT91_ID_FIQ) | (1 << AT91_ID_SYS) - | (1 << AT91_ID_IRQ0) - | (1 << AT91_ID_IRQ1) - | (1 << AT91_ID_IRQ2) - | (1 << AT91_ID_IRQ3) - | (1 << AT91_ID_IRQ4) - | (1 << AT91_ID_IRQ5) - | (1 << AT91_ID_IRQ6)) + | (1 << AT91RM9200_ID_IRQ0) + | (1 << AT91RM9200_ID_IRQ1) + | (1 << AT91RM9200_ID_IRQ2) + | (1 << AT91RM9200_ID_IRQ3) + | (1 << AT91RM9200_ID_IRQ4) + | (1 << AT91RM9200_ID_IRQ5) + | (1 << AT91RM9200_ID_IRQ6)) & at91_sys_read(AT91_AIC_IMR), state); diff --git a/drivers/mmc/at91_mci.c b/drivers/mmc/at91_mci.c index 6b7638b84290..4b3d4d637030 100644 --- a/drivers/mmc/at91_mci.c +++ b/drivers/mmc/at91_mci.c @@ -850,7 +850,7 @@ static int at91_mci_probe(struct platform_device *pdev) /* * Allocate the MCI interrupt */ - ret = request_irq(AT91_ID_MCI, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host); + ret = request_irq(AT91RM9200_ID_MCI, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host); if (ret) { printk(KERN_ERR "Failed to request MCI interrupt\n"); clk_disable(mci_clk); @@ -906,7 +906,7 @@ static int at91_mci_remove(struct platform_device *pdev) mmc_remove_host(mmc); at91_mci_disable(); - free_irq(AT91_ID_MCI, host); + free_irq(AT91RM9200_ID_MCI, host); mmc_free_host(mmc); clk_disable(mci_clk); /* Disable the peripheral clock */ diff --git a/drivers/net/arm/at91_ether.c b/drivers/net/arm/at91_ether.c index 95b28aa01f4f..3ecf2cc53a7c 100644 --- a/drivers/net/arm/at91_ether.c +++ b/drivers/net/arm/at91_ether.c @@ -947,7 +947,7 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add return -ENOMEM; dev->base_addr = AT91_VA_BASE_EMAC; - dev->irq = AT91_ID_EMAC; + dev->irq = AT91RM9200_ID_EMAC; SET_MODULE_OWNER(dev); /* Install the interrupt handler */ diff --git a/drivers/serial/at91_serial.c b/drivers/serial/at91_serial.c index 54c6b2adf7b7..bf4bf103e5a0 100644 --- a/drivers/serial/at91_serial.c +++ b/drivers/serial/at91_serial.c @@ -139,7 +139,7 @@ static void at91_set_mctrl(struct uart_port *port, u_int mctrl) * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21. * We need to drive the pin manually. */ - if (port->mapbase == AT91_BASE_US0) { + if (port->mapbase == AT91RM9200_BASE_US0) { if (mctrl & TIOCM_RTS) at91_set_gpio_value(AT91_PIN_PA21, 0); else diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index cfebca05ead5..043744f1ab72 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -1658,7 +1658,7 @@ static int __devinit at91udc_probe(struct platform_device *pdev) return -ENODEV; } - if (!request_mem_region(AT91_BASE_UDP, SZ_16K, driver_name)) { + if (!request_mem_region(AT91RM9200_BASE_UDP, SZ_16K, driver_name)) { DBG("someone's using UDC memory\n"); return -EBUSY; } @@ -1720,7 +1720,7 @@ static int __devinit at91udc_probe(struct platform_device *pdev) fail1: device_unregister(&udc->gadget.dev); fail0: - release_mem_region(AT91_BASE_UDP, SZ_16K); + release_mem_region(AT91RM9200_BASE_UDP, SZ_16K); DBG("%s probe failed, %d\n", driver_name, retval); return retval; } @@ -1742,7 +1742,7 @@ static int __devexit at91udc_remove(struct platform_device *pdev) free_irq(udc->board.vbus_pin, udc); free_irq(udc->udp_irq, udc); device_unregister(&udc->gadget.dev); - release_mem_region(AT91_BASE_UDP, SZ_16K); + release_mem_region(AT91RM9200_BASE_UDP, SZ_16K); clk_put(udc->iclk); clk_put(udc->fclk); diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h index 58f40931a5c1..a5a86b1ff886 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200.h +++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h @@ -19,66 +19,79 @@ /* * Peripheral identifiers/interrupts. */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripheral */ -#define AT91_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91_ID_US0 6 /* USART 0 */ -#define AT91_ID_US1 7 /* USART 1 */ -#define AT91_ID_US2 8 /* USART 2 */ -#define AT91_ID_US3 9 /* USART 3 */ -#define AT91_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91_ID_UDP 11 /* USB Device Port */ -#define AT91_ID_TWI 12 /* Two-Wire Interface */ -#define AT91_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91_ID_TC0 17 /* Timer Counter 0 */ -#define AT91_ID_TC1 18 /* Timer Counter 1 */ -#define AT91_ID_TC2 19 /* Timer Counter 2 */ -#define AT91_ID_TC3 20 /* Timer Counter 3 */ -#define AT91_ID_TC4 21 /* Timer Counter 4 */ -#define AT91_ID_TC5 22 /* Timer Counter 5 */ -#define AT91_ID_UHP 23 /* USB Host port */ -#define AT91_ID_EMAC 24 /* Ethernet MAC */ -#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ -#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ -#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ -#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ -#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripheral */ +#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ +#define AT91RM9200_ID_US0 6 /* USART 0 */ +#define AT91RM9200_ID_US1 7 /* USART 1 */ +#define AT91RM9200_ID_US2 8 /* USART 2 */ +#define AT91RM9200_ID_US3 9 /* USART 3 */ +#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ +#define AT91RM9200_ID_UDP 11 /* USB Device Port */ +#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ +#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ +#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ +#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ +#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ +#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ +#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ +#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ +#define AT91RM9200_ID_UHP 23 /* USB Host port */ +#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ +#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ +#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ +#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ +#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ +#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ /* * Peripheral physical base addresses. */ -#define AT91_BASE_TCB0 0xfffa0000 -#define AT91_BASE_TC0 0xfffa0000 -#define AT91_BASE_TC1 0xfffa0040 -#define AT91_BASE_TC2 0xfffa0080 -#define AT91_BASE_TCB1 0xfffa4000 -#define AT91_BASE_TC3 0xfffa4000 -#define AT91_BASE_TC4 0xfffa4040 -#define AT91_BASE_TC5 0xfffa4080 -#define AT91_BASE_UDP 0xfffb0000 -#define AT91_BASE_MCI 0xfffb4000 -#define AT91_BASE_TWI 0xfffb8000 -#define AT91_BASE_EMAC 0xfffbc000 -#define AT91_BASE_US0 0xfffc0000 -#define AT91_BASE_US1 0xfffc4000 -#define AT91_BASE_US2 0xfffc8000 -#define AT91_BASE_US3 0xfffcc000 -#define AT91_BASE_SSC0 0xfffd0000 -#define AT91_BASE_SSC1 0xfffd4000 -#define AT91_BASE_SSC2 0xfffd8000 -#define AT91_BASE_SPI 0xfffe0000 +#define AT91RM9200_BASE_TCB0 0xfffa0000 +#define AT91RM9200_BASE_TC0 0xfffa0000 +#define AT91RM9200_BASE_TC1 0xfffa0040 +#define AT91RM9200_BASE_TC2 0xfffa0080 +#define AT91RM9200_BASE_TCB1 0xfffa4000 +#define AT91RM9200_BASE_TC3 0xfffa4000 +#define AT91RM9200_BASE_TC4 0xfffa4040 +#define AT91RM9200_BASE_TC5 0xfffa4080 +#define AT91RM9200_BASE_UDP 0xfffb0000 +#define AT91RM9200_BASE_MCI 0xfffb4000 +#define AT91RM9200_BASE_TWI 0xfffb8000 +#define AT91RM9200_BASE_EMAC 0xfffbc000 +#define AT91RM9200_BASE_US0 0xfffc0000 +#define AT91RM9200_BASE_US1 0xfffc4000 +#define AT91RM9200_BASE_US2 0xfffc8000 +#define AT91RM9200_BASE_US3 0xfffcc000 +#define AT91RM9200_BASE_SSC0 0xfffd0000 +#define AT91RM9200_BASE_SSC1 0xfffd4000 +#define AT91RM9200_BASE_SSC2 0xfffd8000 +#define AT91RM9200_BASE_SPI 0xfffe0000 #define AT91_BASE_SYS 0xfffff000 +/* + * Internal Memory. + */ +#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ +#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ + +#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ +#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ + +#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ + + +#if 0 /* * PIO pin definitions (peripheral A/B multiplexing). */ @@ -257,5 +270,6 @@ #define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */ #define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */ #define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */ +#endif #endif diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h index dbde1baaf251..6243f28a0b81 100644 --- a/include/asm-arm/arch-at91rm9200/gpio.h +++ b/include/asm-arm/arch-at91rm9200/gpio.h @@ -20,7 +20,7 @@ #define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */ #define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */ -/* these pin numbers double as IRQ numbers, like AT91_ID_* values */ +/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ #define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) #define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h index 235d39d91107..878e65f369bf 100644 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ b/include/asm-arm/arch-at91rm9200/hardware.h @@ -34,27 +34,23 @@ * Virtual to Physical Address mapping for IO devices. */ #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) -#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91_BASE_SPI) -#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91_BASE_SSC2) -#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91_BASE_SSC1) -#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91_BASE_SSC0) -#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91_BASE_US3) -#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91_BASE_US2) -#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91_BASE_US1) -#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91_BASE_US0) -#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91_BASE_EMAC) -#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91_BASE_TWI) -#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91_BASE_MCI) -#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91_BASE_UDP) -#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91_BASE_TCB1) -#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91_BASE_TCB0) - -/* Internal SRAM */ -#define AT91_SRAM_BASE 0x00200000 /* Internal SRAM base address */ -#define AT91_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */ +#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI) +#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91RM9200_BASE_SSC2) +#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91RM9200_BASE_SSC1) +#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91RM9200_BASE_SSC0) +#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91RM9200_BASE_US3) +#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91RM9200_BASE_US2) +#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91RM9200_BASE_US1) +#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91RM9200_BASE_US0) +#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) +#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI) +#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI) +#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP) +#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91RM9200_BASE_TCB1) +#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91RM9200_BASE_TCB0) /* Internal SRAM is mapped below the IO devices */ -#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE) +#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE) /* Serial ports */ #define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */ @@ -71,9 +67,6 @@ /* Compact Flash */ #define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */ -/* Multi-Master Memory controller */ -#define AT91_UHP_BASE 0x00300000 /* USB Host controller */ - /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h index f63842c2c093..763cb96c418b 100644 --- a/include/asm-arm/arch-at91rm9200/irqs.h +++ b/include/asm-arm/arch-at91rm9200/irqs.h @@ -32,7 +32,7 @@ /* - * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h + * IRQ interrupt symbols are the AT91xxx_ID_* symbols * for IRQs handled directly through the AIC, or else the AT91_PIN_* * symbols in gpio.h for ones handled indirectly as GPIOs. * We make provision for 4 banks of GPIO. -- cgit v1.2.3 From f21738341ca330ec83ef978ee63ffa5ecf13f082 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Wed, 27 Sep 2006 13:23:00 +0100 Subject: [ARM] 3867/1: AT91 GPIO update This patch makes the AT91 gpio.c support processor-generic (AT91RM9200 and AT91SAM9xxx). The GPIO controllers supported by a particular AT91 processor are defined in the processor-specific file and are registered with gpio.c at startup. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91rm9200/at91rm9200.c | 39 +++++++++++++- arch/arm/mach-at91rm9200/board-1arm.c | 15 +++--- arch/arm/mach-at91rm9200/board-carmeva.c | 16 +++--- arch/arm/mach-at91rm9200/board-csb337.c | 15 +++--- arch/arm/mach-at91rm9200/board-csb637.c | 15 +++--- arch/arm/mach-at91rm9200/board-dk.c | 15 +++--- arch/arm/mach-at91rm9200/board-eb9200.c | 15 +++--- arch/arm/mach-at91rm9200/board-ek.c | 15 +++--- arch/arm/mach-at91rm9200/board-kafa.c | 15 +++--- arch/arm/mach-at91rm9200/board-kb9202.c | 15 +++--- arch/arm/mach-at91rm9200/generic.h | 16 ++++-- arch/arm/mach-at91rm9200/gpio.c | 89 ++++++++++++++++++-------------- arch/arm/mach-at91rm9200/irq.c | 2 - include/asm-arm/arch-at91rm9200/gpio.h | 16 +++--- 14 files changed, 164 insertions(+), 134 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c index ae04cbdf0bff..c32d0c996f90 100644 --- a/arch/arm/mach-at91rm9200/at91rm9200.c +++ b/arch/arm/mach-at91rm9200/at91rm9200.c @@ -243,11 +243,34 @@ static void __init at91rm9200_register_clocks(void) clk_register(&pck3); } +/* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ + +static struct at91_gpio_bank at91rm9200_gpio[] = { + { + .id = AT91RM9200_ID_PIOA, + .offset = AT91_PIOA, + .clock = &pioA_clk, + }, { + .id = AT91RM9200_ID_PIOB, + .offset = AT91_PIOB, + .clock = &pioB_clk, + }, { + .id = AT91RM9200_ID_PIOC, + .offset = AT91_PIOC, + .clock = &pioC_clk, + }, { + .id = AT91RM9200_ID_PIOD, + .offset = AT91_PIOD, + .clock = &pioD_clk, + } +}; /* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */ -void __init at91rm9200_initialize(unsigned long main_clock) +void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks) { /* Map peripherals */ iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); @@ -257,8 +280,16 @@ void __init at91rm9200_initialize(unsigned long main_clock) /* Register the processor-specific clocks */ at91rm9200_register_clocks(); + + /* Initialize GPIO subsystem */ + at91_gpio_init(at91rm9200_gpio, banks); } + +/* -------------------------------------------------------------------- + * Interrupt initialization + * -------------------------------------------------------------------- */ + /* * The default interrupt priority levels (0 = lowest, 7 = highest). */ @@ -297,10 +328,14 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { 0 /* Advanced Interrupt Controller (IRQ6) */ }; -void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS]) +void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS]) { if (!priority) priority = at91rm9200_default_irq_priority; + /* Initialize the AIC interrupt controller */ at91_aic_init(priority); + + /* Enable GPIO interrupts */ + at91_gpio_irq_setup(); } diff --git a/arch/arm/mach-at91rm9200/board-1arm.c b/arch/arm/mach-at91rm9200/board-1arm.c index d2aa9c4a8b24..36eecd7161f5 100644 --- a/arch/arm/mach-at91rm9200/board-1arm.c +++ b/arch/arm/mach-at91rm9200/board-1arm.c @@ -39,14 +39,6 @@ #include "generic.h" -static void __init onearm_init_irq(void) -{ - /* Initialize AIC controller */ - at91rm9200_init_irq(NULL); - - /* Set up the GPIO interrupts */ - at91_gpio_irq_setup(PQFP_GPIO_BANKS); -} /* * Serial port configuration. @@ -62,12 +54,17 @@ static struct at91_uart_config __initdata onearm_uart_config = { static void __init onearm_map_io(void) { /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91rm9200_initialize(18432000, AT91RM9200_PQFP); /* Setup the serial ports and console */ at91_init_serial(&onearm_uart_config); } +static void __init onearm_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + static struct at91_eth_data __initdata onearm_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, diff --git a/arch/arm/mach-at91rm9200/board-carmeva.c b/arch/arm/mach-at91rm9200/board-carmeva.c index 6af252bcb083..50e513681ae6 100644 --- a/arch/arm/mach-at91rm9200/board-carmeva.c +++ b/arch/arm/mach-at91rm9200/board-carmeva.c @@ -40,14 +40,6 @@ #include "generic.h" -static void __init carmeva_init_irq(void) -{ - /* Initialize AIC controller */ - at91rm9200_init_irq(NULL); - - /* Set up the GPIO interrupts */ - at91_gpio_irq_setup(BGA_GPIO_BANKS); -} /* * Serial port configuration. @@ -63,12 +55,18 @@ static struct at91_uart_config __initdata carmeva_uart_config = { static void __init carmeva_map_io(void) { /* Initialize processor: 20.000 MHz crystal */ - at91rm9200_initialize(20000000); + at91rm9200_initialize(20000000, AT91RM9200_BGA); /* Setup the serial ports and console */ at91_init_serial(&carmeva_uart_config); } +static void __init carmeva_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + + static struct at91_eth_data __initdata carmeva_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, diff --git a/arch/arm/mach-at91rm9200/board-csb337.c b/arch/arm/mach-at91rm9200/board-csb337.c index f74b483329c0..8eeae491ce71 100644 --- a/arch/arm/mach-at91rm9200/board-csb337.c +++ b/arch/arm/mach-at91rm9200/board-csb337.c @@ -39,14 +39,6 @@ #include "generic.h" -static void __init csb337_init_irq(void) -{ - /* Initialize AIC controller */ - at91rm9200_init_irq(NULL); - - /* Set up the GPIO interrupts */ - at91_gpio_irq_setup(BGA_GPIO_BANKS); -} /* * Serial port configuration. @@ -62,7 +54,7 @@ static struct at91_uart_config __initdata csb337_uart_config = { static void __init csb337_map_io(void) { /* Initialize processor: 3.6864 MHz crystal */ - at91rm9200_initialize(3686400); + at91rm9200_initialize(3686400, AT91RM9200_BGA); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); @@ -71,6 +63,11 @@ static void __init csb337_map_io(void) at91_init_serial(&csb337_uart_config); } +static void __init csb337_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + static struct at91_eth_data __initdata csb337_eth_data = { .phy_irq_pin = AT91_PIN_PC2, .is_rmii = 0, diff --git a/arch/arm/mach-at91rm9200/board-csb637.c b/arch/arm/mach-at91rm9200/board-csb637.c index 880350997a3b..a29fa0e822ce 100644 --- a/arch/arm/mach-at91rm9200/board-csb637.c +++ b/arch/arm/mach-at91rm9200/board-csb637.c @@ -38,14 +38,6 @@ #include "generic.h" -static void __init csb637_init_irq(void) -{ - /* Initialize AIC controller */ - at91rm9200_init_irq(NULL); - - /* Set up the GPIO interrupts */ - at91_gpio_irq_setup(BGA_GPIO_BANKS); -} /* * Serial port configuration. @@ -61,7 +53,7 @@ static struct at91_uart_config __initdata csb637_uart_config = { static void __init csb637_map_io(void) { /* Initialize processor: 3.6864 MHz crystal */ - at91rm9200_initialize(3686400); + at91rm9200_initialize(3686400, AT91RM9200_BGA); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); @@ -70,6 +62,11 @@ static void __init csb637_map_io(void) at91_init_serial(&csb637_uart_config); } +static void __init csb637_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + static struct at91_eth_data __initdata csb637_eth_data = { .phy_irq_pin = AT91_PIN_PC0, .is_rmii = 0, diff --git a/arch/arm/mach-at91rm9200/board-dk.c b/arch/arm/mach-at91rm9200/board-dk.c index 23ea9d63b986..54c32d00b610 100644 --- a/arch/arm/mach-at91rm9200/board-dk.c +++ b/arch/arm/mach-at91rm9200/board-dk.c @@ -42,14 +42,6 @@ #include "generic.h" -static void __init dk_init_irq(void) -{ - /* Initialize AIC controller */ - at91rm9200_init_irq(NULL); - - /* Set up the GPIO interrupts */ - at91_gpio_irq_setup(BGA_GPIO_BANKS); -} /* * Serial port configuration. @@ -65,7 +57,7 @@ static struct at91_uart_config __initdata dk_uart_config = { static void __init dk_map_io(void) { /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91rm9200_initialize(18432000, AT91RM9200_BGA); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); @@ -74,6 +66,11 @@ static void __init dk_map_io(void) at91_init_serial(&dk_uart_config); } +static void __init dk_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + static struct at91_eth_data __initdata dk_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, diff --git a/arch/arm/mach-at91rm9200/board-eb9200.c b/arch/arm/mach-at91rm9200/board-eb9200.c index 2ceb267585ad..c6e0d51fbea0 100644 --- a/arch/arm/mach-at91rm9200/board-eb9200.c +++ b/arch/arm/mach-at91rm9200/board-eb9200.c @@ -40,14 +40,6 @@ #include "generic.h" -static void __init eb9200_init_irq(void) -{ - /* Initialize AIC controller */ - at91rm9200_init_irq(NULL); - - /* Set up the GPIO interrupts */ - at91_gpio_irq_setup(BGA_GPIO_BANKS); -} /* * Serial port configuration. @@ -63,12 +55,17 @@ static struct at91_uart_config __initdata eb9200_uart_config = { static void __init eb9200_map_io(void) { /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91rm9200_initialize(18432000, AT91RM9200_BGA); /* Setup the serial ports and console */ at91_init_serial(&eb9200_uart_config); } +static void __init eb9200_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + static struct at91_eth_data __initdata eb9200_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, diff --git a/arch/arm/mach-at91rm9200/board-ek.c b/arch/arm/mach-at91rm9200/board-ek.c index 8cd83364cd80..830eb7932178 100644 --- a/arch/arm/mach-at91rm9200/board-ek.c +++ b/arch/arm/mach-at91rm9200/board-ek.c @@ -42,14 +42,6 @@ #include "generic.h" -static void __init ek_init_irq(void) -{ - /* Initialize AIC controller */ - at91rm9200_init_irq(NULL); - - /* Set up the GPIO interrupts */ - at91_gpio_irq_setup(BGA_GPIO_BANKS); -} /* * Serial port configuration. @@ -65,7 +57,7 @@ static struct at91_uart_config __initdata ek_uart_config = { static void __init ek_map_io(void) { /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91rm9200_initialize(18432000, AT91RM9200_BGA); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); @@ -74,6 +66,11 @@ static void __init ek_map_io(void) at91_init_serial(&ek_uart_config); } +static void __init ek_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + static struct at91_eth_data __initdata ek_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, diff --git a/arch/arm/mach-at91rm9200/board-kafa.c b/arch/arm/mach-at91rm9200/board-kafa.c index d9a6b7e7d63a..91e301924f2c 100644 --- a/arch/arm/mach-at91rm9200/board-kafa.c +++ b/arch/arm/mach-at91rm9200/board-kafa.c @@ -39,14 +39,6 @@ #include "generic.h" -static void __init kafa_init_irq(void) -{ - /* Initialize AIC controller */ - at91rm9200_init_irq(NULL); - - /* Set up the GPIO interrupts */ - at91_gpio_irq_setup(PQFP_GPIO_BANKS); -} /* * Serial port configuration. @@ -62,7 +54,7 @@ static struct at91_uart_config __initdata kafa_uart_config = { static void __init kafa_map_io(void) { /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91rm9200_initialize(18432000, AT91RM9200_PQFP); /* Set up the LEDs */ at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); @@ -71,6 +63,11 @@ static void __init kafa_map_io(void) at91_init_serial(&kafa_uart_config); } +static void __init kafa_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + static struct at91_eth_data __initdata kafa_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 0, diff --git a/arch/arm/mach-at91rm9200/board-kb9202.c b/arch/arm/mach-at91rm9200/board-kb9202.c index 935238ffa330..55b08f9b9537 100644 --- a/arch/arm/mach-at91rm9200/board-kb9202.c +++ b/arch/arm/mach-at91rm9200/board-kb9202.c @@ -40,14 +40,6 @@ #include "generic.h" -static void __init kb9202_init_irq(void) -{ - /* Initialize AIC controller */ - at91rm9200_init_irq(NULL); - - /* Set up the GPIO interrupts */ - at91_gpio_irq_setup(PQFP_GPIO_BANKS); -} /* * Serial port configuration. @@ -63,7 +55,7 @@ static struct at91_uart_config __initdata kb9202_uart_config = { static void __init kb9202_map_io(void) { /* Initialize processor: 10 MHz crystal */ - at91rm9200_initialize(10000000); + at91rm9200_initialize(10000000, AT91RM9200_PQFP); /* Set up the LEDs */ at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); @@ -72,6 +64,11 @@ static void __init kb9202_map_io(void) at91_init_serial(&kb9202_uart_config); } +static void __init kb9202_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + static struct at91_eth_data __initdata kb9202_eth_data = { .phy_irq_pin = AT91_PIN_PB29, .is_rmii = 0, diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h index c44e0e074682..694e411e285f 100644 --- a/arch/arm/mach-at91rm9200/generic.h +++ b/arch/arm/mach-at91rm9200/generic.h @@ -9,12 +9,11 @@ */ /* Processors */ -extern void __init at91rm9200_initialize(unsigned long main_clock); +extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks); /* Interrupts */ -extern void __init at91rm9200_init_irq(unsigned int priority[]); +extern void __init at91rm9200_init_interrupts(unsigned int priority[]); extern void __init at91_aic_init(unsigned int priority[]); -extern void __init at91_gpio_irq_setup(unsigned banks); /* Timer */ struct sys_timer; @@ -29,3 +28,14 @@ extern void __init at91_clock_associate(const char *id, struct device *dev, cons extern void at91_irq_suspend(void); extern void at91_irq_resume(void); + /* GPIO */ +#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ +#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ + +struct at91_gpio_bank { + unsigned short id; /* peripheral ID */ + unsigned long offset; /* offset from system peripheral base */ + struct clk *clock; /* associated clock */ +}; +extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks); +extern void __init at91_gpio_irq_setup(void); diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c index 8476cb8856c9..58c9bf5e9520 100644 --- a/arch/arm/mach-at91rm9200/gpio.c +++ b/arch/arm/mach-at91rm9200/gpio.c @@ -9,6 +9,7 @@ * (at your option) any later version. */ +#include #include #include #include @@ -20,12 +21,12 @@ #include #include -static const u32 pio_controller_offset[4] = { - AT91_PIOA, - AT91_PIOB, - AT91_PIOC, - AT91_PIOD, -}; +#include "generic.h" + + +static struct at91_gpio_bank *gpio; +static int gpio_banks; + static inline void __iomem *pin_to_controller(unsigned pin) { @@ -33,8 +34,8 @@ static inline void __iomem *pin_to_controller(unsigned pin) pin -= PIN_BASE; pin /= 32; - if (likely(pin < BGA_GPIO_BANKS)) - return sys_base + pio_controller_offset[pin]; + if (likely(pin < gpio_banks)) + return sys_base + gpio[pin].offset; return NULL; } @@ -179,7 +180,6 @@ EXPORT_SYMBOL(at91_set_multi_drive); /*--------------------------------------------------------------------------*/ - /* * assuming the pin is muxed as a gpio output, set its value. */ @@ -216,8 +216,8 @@ EXPORT_SYMBOL(at91_get_gpio_value); #ifdef CONFIG_PM -static u32 wakeups[BGA_GPIO_BANKS]; -static u32 backups[BGA_GPIO_BANKS]; +static u32 wakeups[MAX_GPIO_BANKS]; +static u32 backups[MAX_GPIO_BANKS]; static int gpio_irq_set_wake(unsigned pin, unsigned state) { @@ -226,7 +226,7 @@ static int gpio_irq_set_wake(unsigned pin, unsigned state) pin -= PIN_BASE; pin /= 32; - if (unlikely(pin >= BGA_GPIO_BANKS)) + if (unlikely(pin >= MAX_GPIO_BANKS)) return -EINVAL; if (state) @@ -241,8 +241,8 @@ void at91_gpio_suspend(void) { int i; - for (i = 0; i < BGA_GPIO_BANKS; i++) { - u32 pio = pio_controller_offset[i]; + for (i = 0; i < gpio_banks; i++) { + u32 pio = gpio[i].offset; /* * Note: drivers should have disabled GPIO interrupts that @@ -257,14 +257,14 @@ void at91_gpio_suspend(void) * first place! */ backups[i] = at91_sys_read(pio + PIO_IMR); - at91_sys_write(pio_controller_offset[i] + PIO_IDR, backups[i]); - at91_sys_write(pio_controller_offset[i] + PIO_IER, wakeups[i]); + at91_sys_write(pio + PIO_IDR, backups[i]); + at91_sys_write(pio + PIO_IER, wakeups[i]); if (!wakeups[i]) { - disable_irq_wake(AT91RM9200_ID_PIOA + i); - at91_sys_write(AT91_PMC_PCDR, 1 << (AT91RM9200_ID_PIOA + i)); + disable_irq_wake(gpio[i].id); + at91_sys_write(AT91_PMC_PCDR, 1 << gpio[i].id); } else { - enable_irq_wake(AT91RM9200_ID_PIOA + i); + enable_irq_wake(gpio[i].id); #ifdef CONFIG_PM_DEBUG printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]); #endif @@ -276,16 +276,13 @@ void at91_gpio_resume(void) { int i; - for (i = 0; i < BGA_GPIO_BANKS; i++) { - at91_sys_write(pio_controller_offset[i] + PIO_IDR, wakeups[i]); - at91_sys_write(pio_controller_offset[i] + PIO_IER, backups[i]); - } + for (i = 0; i < gpio_banks; i++) { + u32 pio = gpio[i].offset; - at91_sys_write(AT91_PMC_PCER, - (1 << AT91RM9200_ID_PIOA) - | (1 << AT91RM9200_ID_PIOB) - | (1 << AT91RM9200_ID_PIOC) - | (1 << AT91RM9200_ID_PIOD)); + at91_sys_write(pio + PIO_IDR, wakeups[i]); + at91_sys_write(pio + PIO_IER, backups[i]); + at91_sys_write(AT91_PMC_PCER, 1 << gpio[i].id); + } } #else @@ -377,20 +374,25 @@ static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs /* now it may re-trigger */ } -/* call this from board-specific init_irq */ -void __init at91_gpio_irq_setup(unsigned banks) +/*--------------------------------------------------------------------------*/ + +/* + * Called from the processor-specific init to enable GPIO interrupt support. + */ +void __init at91_gpio_irq_setup(void) { - unsigned pioc, pin, id; + unsigned pioc, pin; - if (banks > 4) - banks = 4; - for (pioc = 0, pin = PIN_BASE, id = AT91RM9200_ID_PIOA; - pioc < banks; - pioc++, id++) { + for (pioc = 0, pin = PIN_BASE; + pioc < gpio_banks; + pioc++) { void __iomem *controller; + unsigned id = gpio[pioc].id; unsigned i; - controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc]; + clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */ + + controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset; __raw_writel(~0, controller + PIO_IDR); set_irq_data(id, (void *) pin); @@ -408,5 +410,16 @@ void __init at91_gpio_irq_setup(unsigned banks) set_irq_chained_handler(id, gpio_irq_handler); } - pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks); + pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); +} + +/* + * Called from the processor-specific init to enable GPIO pin support. + */ +void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) +{ + BUG_ON(nr_banks > MAX_GPIO_BANKS); + + gpio = data; + gpio_banks = nr_banks; } diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c index 8cd60a99c5b8..3e488117ca91 100644 --- a/arch/arm/mach-at91rm9200/irq.c +++ b/arch/arm/mach-at91rm9200/irq.c @@ -34,8 +34,6 @@ #include #include -#include "generic.h" - static void at91_aic_mask_irq(unsigned int irq) { diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h index 6243f28a0b81..a011d27876a2 100644 --- a/include/asm-arm/arch-at91rm9200/gpio.h +++ b/include/asm-arm/arch-at91rm9200/gpio.h @@ -17,8 +17,7 @@ #define PIN_BASE NR_AIC_IRQS -#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */ -#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */ +#define MAX_GPIO_BANKS 4 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ @@ -180,17 +179,18 @@ #ifndef __ASSEMBLY__ /* setup setup routines, called from board init or driver probe() */ -extern int at91_set_A_periph(unsigned pin, int use_pullup); -extern int at91_set_B_periph(unsigned pin, int use_pullup); -extern int at91_set_gpio_input(unsigned pin, int use_pullup); -extern int at91_set_gpio_output(unsigned pin, int value); -extern int at91_set_deglitch(unsigned pin, int is_on); -extern int at91_set_multi_drive(unsigned pin, int is_on); +extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); +extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); +extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); /* callable at any time */ extern int at91_set_gpio_value(unsigned pin, int value); extern int at91_get_gpio_value(unsigned pin); +/* callable only from core power-management code */ extern void at91_gpio_suspend(void); extern void at91_gpio_resume(void); #endif -- cgit v1.2.3 From 97f0fb68f142b477773c05140da27c1dbd31a2ab Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Wed, 27 Sep 2006 16:18:18 +0100 Subject: [ARM] 3868/1: AT91 hardware header update This patch adds the hardware register definitions for the TWI (I2C) controller found on the AT91RM9200 and AT91SAM9xx processors. It also defines the AIC Fast-Forcing registers added to the AT91SAM9's. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91rm9200/at91rm9200_sys.h | 3 ++ include/asm-arm/arch-at91rm9200/at91rm9200_twi.h | 57 ++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 include/asm-arm/arch-at91rm9200/at91rm9200_twi.h (limited to 'include') diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h index 0f4c12d5f0cd..73693fea76a2 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h @@ -80,6 +80,9 @@ #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ +#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ +#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ +#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ /* * PIO Controllers. diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h new file mode 100644 index 000000000000..93547d7482bd --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h @@ -0,0 +1,57 @@ +/* + * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Two-wire Interface (TWI) registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91RM9200_TWI_H +#define AT91RM9200_TWI_H + +#define AT91_TWI_CR 0x00 /* Control Register */ +#define AT91_TWI_START (1 << 0) /* Send a Start Condition */ +#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ +#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ +#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ +#define AT91_TWI_SWRST (1 << 7) /* Software Reset */ + +#define AT91_TWI_MMR 0x04 /* Master Mode Register */ +#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */ +#define AT91_TWI_IADRSZ_NO (0 << 8) +#define AT91_TWI_IADRSZ_1 (1 << 8) +#define AT91_TWI_IADRSZ_2 (2 << 8) +#define AT91_TWI_IADRSZ_3 (3 << 8) +#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ +#define AT91_TWI_DADR (0x7f << 16) /* Device Address */ + +#define AT91_TWI_IADR 0x0c /* Internal Address Register */ + +#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ +#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */ +#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */ +#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */ + +#define AT91_TWI_SR 0x20 /* Status Register */ +#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ +#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ +#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ +#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */ +#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */ +#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ + +#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ +#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ +#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */ +#define AT91_TWI_RHR 0x30 /* Receive Holding Register */ +#define AT91_TWI_THR 0x34 /* Transmit Holding Register */ + +#endif + -- cgit v1.2.3 From 1f51c10c5e85050506663bce1d69513eb901db87 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Thu, 28 Sep 2006 16:26:47 +0100 Subject: [ARM] 3870/1: AT91: Start removing static memory mappings This patch removes the static memory mapping for the currently-unused peripherals [Synchronous Serial, Timer/Counter unit], and for those drivers that already ioremap() their registers [UART]. Also, the Ethernet driver now uses the platform_device resources but doesn't yet use ioremap() so we need to pass it the virtual address instead of the physical address. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91rm9200/at91rm9200.c | 45 ------------------------------ arch/arm/mach-at91rm9200/devices.c | 4 +-- include/asm-arm/arch-at91rm9200/hardware.h | 9 ------ 3 files changed, 2 insertions(+), 56 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c index c32d0c996f90..dcf6136fedf9 100644 --- a/arch/arm/mach-at91rm9200/at91rm9200.c +++ b/arch/arm/mach-at91rm9200/at91rm9200.c @@ -30,41 +30,6 @@ static struct map_desc at91rm9200_io_desc[] __initdata = { .pfn = __phys_to_pfn(AT91RM9200_BASE_SPI), .length = SZ_16K, .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_SSC2, - .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC2), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_SSC1, - .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC1), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_SSC0, - .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC0), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_US3, - .pfn = __phys_to_pfn(AT91RM9200_BASE_US3), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_US2, - .pfn = __phys_to_pfn(AT91RM9200_BASE_US2), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_US1, - .pfn = __phys_to_pfn(AT91RM9200_BASE_US1), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_US0, - .pfn = __phys_to_pfn(AT91RM9200_BASE_US0), - .length = SZ_16K, - .type = MT_DEVICE, }, { .virtual = AT91_VA_BASE_EMAC, .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), @@ -85,16 +50,6 @@ static struct map_desc at91rm9200_io_desc[] __initdata = { .pfn = __phys_to_pfn(AT91RM9200_BASE_UDP), .length = SZ_16K, .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_TCB1, - .pfn = __phys_to_pfn(AT91RM9200_BASE_TCB1), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_VA_BASE_TCB0, - .pfn = __phys_to_pfn(AT91RM9200_BASE_TCB0), - .length = SZ_16K, - .type = MT_DEVICE, }, { .virtual = AT91_SRAM_VIRT_BASE, .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE), diff --git a/arch/arm/mach-at91rm9200/devices.c b/arch/arm/mach-at91rm9200/devices.c index db7c684cdb63..01525530c287 100644 --- a/arch/arm/mach-at91rm9200/devices.c +++ b/arch/arm/mach-at91rm9200/devices.c @@ -131,8 +131,8 @@ static struct at91_eth_data eth_data; static struct resource at91_eth_resources[] = { [0] = { - .start = AT91RM9200_BASE_EMAC, - .end = AT91RM9200_BASE_EMAC + SZ_16K - 1, + .start = AT91_VA_BASE_EMAC, + .end = AT91_VA_BASE_EMAC + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h index 878e65f369bf..6551b4d1ff7b 100644 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ b/include/asm-arm/arch-at91rm9200/hardware.h @@ -35,19 +35,10 @@ */ #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) #define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI) -#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91RM9200_BASE_SSC2) -#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91RM9200_BASE_SSC1) -#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91RM9200_BASE_SSC0) -#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91RM9200_BASE_US3) -#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91RM9200_BASE_US2) -#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91RM9200_BASE_US1) -#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91RM9200_BASE_US0) #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) #define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI) #define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI) #define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP) -#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91RM9200_BASE_TCB1) -#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91RM9200_BASE_TCB0) /* Internal SRAM is mapped below the IO devices */ #define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE) -- cgit v1.2.3 From 746140c71d537560bbd22c1b148fb21031c30e71 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 22 Sep 2006 00:16:30 +0100 Subject: [ARM] 3855/1: Add generic time support This patch adds Generic time-of-day support for the ARM architecture. The support is currently added using #ifdef's so that it can support sub-arches that do not (yet) have a clocksource added. As sub-arches add clocksource support, they should 'select GENERIC_TIME' Signed-off-by: Deepak Saxena Signed-off-by: Daniel Walker Signed-off-by: Kevin Hilman Acked-by: John Stultz Signed-off-by: Russell King --- arch/arm/Kconfig | 4 ++++ arch/arm/kernel/time.c | 6 ++++++ include/asm-arm/mach/time.h | 2 ++ include/asm-arm/timeofday.h | 4 ++++ 4 files changed, 16 insertions(+) create mode 100644 include/asm-arm/timeofday.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0810d27c039e..314ac6ba0ec4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -17,6 +17,10 @@ config ARM Europe. There is an ARM Linux project with a web page at . +config GENERIC_TIME + bool + default n + config MMU bool default y diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 09a67d771857..d4dceb5f06e9 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -69,10 +69,12 @@ EXPORT_SYMBOL(profile_pc); */ int (*set_rtc)(void); +#ifndef CONFIG_GENERIC_TIME static unsigned long dummy_gettimeoffset(void) { return 0; } +#endif /* * Scheduler clock - returns current time in nanosec units. @@ -230,6 +232,7 @@ static inline void do_leds(void) #define do_leds() #endif +#ifndef CONFIG_GENERIC_TIME void do_gettimeofday(struct timeval *tv) { unsigned long flags; @@ -291,6 +294,7 @@ int do_settimeofday(struct timespec *tv) } EXPORT_SYMBOL(do_settimeofday); +#endif /* !CONFIG_GENERIC_TIME */ /** * save_time_delta - Save the offset between system time and RTC time @@ -500,8 +504,10 @@ device_initcall(timer_init_sysfs); void __init time_init(void) { +#ifndef CONFIG_GENERIC_TIME if (system_timer->offset == NULL) system_timer->offset = dummy_gettimeoffset; +#endif system_timer->init(); #ifdef CONFIG_NO_IDLE_HZ diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h index dee0bc336fe8..1eb93f5c0d6c 100644 --- a/include/asm-arm/mach/time.h +++ b/include/asm-arm/mach/time.h @@ -38,7 +38,9 @@ struct sys_timer { void (*init)(void); void (*suspend)(void); void (*resume)(void); +#ifndef CONFIG_GENERIC_TIME unsigned long (*offset)(void); +#endif #ifdef CONFIG_NO_IDLE_HZ struct dyn_tick_timer *dyn_tick; diff --git a/include/asm-arm/timeofday.h b/include/asm-arm/timeofday.h new file mode 100644 index 000000000000..27254bd5b94f --- /dev/null +++ b/include/asm-arm/timeofday.h @@ -0,0 +1,4 @@ +#ifndef _ASM_ARM_TIMEOFDAY_H +#define _ASM_ARM_TIMEOFDAY_H +#include +#endif -- cgit v1.2.3 From 84904d0ead0a8c419abd45c7b2ac8d76d50a0d48 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 22 Sep 2006 00:58:57 +0100 Subject: [ARM] 3856/1: Add clocksource for Intel IXP4xx platforms Enables the ixp4xx platforms to use Generic time-of-day. Signed-off-by: Kevin Hilman Acked-by: John Stultz Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- arch/arm/Kconfig | 1 + arch/arm/mach-ixp4xx/common.c | 38 ++++++++++++++++++++++++---------- arch/arm/mach-ixp4xx/nslu2-setup.c | 2 ++ include/asm-arm/arch-ixp4xx/platform.h | 5 +++++ 4 files changed, 35 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 314ac6ba0ec4..147abe0383d8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -226,6 +226,7 @@ config ARCH_IOP33X config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU + select GENERIC_TIME help Support for Intel's IXP4XX (XScale) family of processors. diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 7c25dbd5a181..35dd8b3824b0 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -255,16 +256,6 @@ static unsigned volatile last_jiffy_time; #define CLOCK_TICKS_PER_USEC ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC) -/* IRQs are disabled before entering here from do_gettimeofday() */ -static unsigned long ixp4xx_gettimeoffset(void) -{ - u32 elapsed; - - elapsed = *IXP4XX_OSTS - last_jiffy_time; - - return elapsed / CLOCK_TICKS_PER_USEC; -} - static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { write_seqlock(&xtime_lock); @@ -309,7 +300,6 @@ static void __init ixp4xx_timer_init(void) struct sys_timer ixp4xx_timer = { .init = ixp4xx_timer_init, - .offset = ixp4xx_gettimeoffset, }; static struct resource ixp46x_i2c_resources[] = { @@ -365,3 +355,29 @@ void __init ixp4xx_sys_init(void) ixp4xx_exp_bus_size >> 20); } +cycle_t ixp4xx_get_cycles(void) +{ + return *IXP4XX_OSTS; +} + +static struct clocksource clocksource_ixp4xx = { + .name = "OSTS", + .rating = 200, + .read = ixp4xx_get_cycles, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .is_continuous = 1, +}; + +unsigned long ixp4xx_timer_freq = FREQ; +static int __init ixp4xx_clocksource_init(void) +{ + clocksource_ixp4xx.mult = + clocksource_hz2mult(ixp4xx_timer_freq, + clocksource_ixp4xx.shift); + clocksource_register(&clocksource_ixp4xx); + + return 0; +} + +device_initcall(ixp4xx_clocksource_init); diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index 749a337494d3..162c266e5f8f 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -159,6 +159,8 @@ static void nslu2_power_off(void) static void __init nslu2_init(void) { + ixp4xx_timer_freq = NSLU2_FREQ; + ixp4xx_sys_init(); nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h index 13aee17b0475..8d10a9187693 100644 --- a/include/asm-arm/arch-ixp4xx/platform.h +++ b/include/asm-arm/arch-ixp4xx/platform.h @@ -89,6 +89,11 @@ struct ixp4xx_i2c_pins { struct sys_timer; +/* + * Frequency of clock used for primary clocksource + */ +extern unsigned long ixp4xx_timer_freq; + /* * Functions used by platform-level setup code */ -- cgit v1.2.3