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author | Amit Nischal <anischal@codeaurora.org> | 2017-02-15 14:32:01 +0530 |
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committer | Amit Nischal <anischal@codeaurora.org> | 2017-02-17 09:16:24 +0530 |
commit | 6d3288e6d51848e7cb03ef910a74eb6ae82be7a6 (patch) | |
tree | e66d8255a758161f1ccee456c060cc9e8c233175 /drivers/clk/qcom | |
parent | 3ba1a36ad812171629b91f5a49e486b2529c22a2 (diff) |
clk: qcom: Add support to list registers for slew PLL
For slew PLL, register content is required to be displayed
for debug purpose. Add support for the same by adding
list_register clock ops to clk_alpha_pll_slew_ops.
Change-Id: I806edd4d62ff00a4b36d17942afd746b03616534
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom')
-rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 375f1420f3bb..0a8d73049b81 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -858,5 +858,6 @@ const struct clk_ops clk_alpha_pll_slew_ops = { .recalc_rate = clk_alpha_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .set_rate = clk_alpha_pll_slew_set_rate, + .list_registers = clk_alpha_pll_list_registers, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_slew_ops); |